1364 files changed, 17841 insertions, 122804 deletions

diff --git a/include/acpi/acmacros.h b/include/acpi/acmacros.h
index 57ab9e9d7593..74a9617776a8 100644
--- a/include/acpi/acmacros.h
+++ b/include/acpi/acmacros.h
@@ -467,7 +467,7 @@ struct acpi_integer_overlay {
 /*
  * If ACPI_GET_FUNCTION_NAME was not defined in the compiler-dependent header,
  * define it now. This is the case where there the compiler does not support
- * a __FUNCTION__ macro or equivalent.
+ * a __func__ macro or equivalent.
  */
 #ifndef ACPI_GET_FUNCTION_NAME
 #define ACPI_GET_FUNCTION_NAME          _acpi_function_name
@@ -475,12 +475,12 @@ struct acpi_integer_overlay {
  * The Name parameter should be the procedure name as a quoted string.
  * The function name is also used by the function exit macros below.
  * Note: (const char) is used to be compatible with the debug interfaces
- * and macros such as __FUNCTION__.
+ * and macros such as __func__.
  */
 #define ACPI_FUNCTION_NAME(name)        static const char _acpi_function_name[] = #name;
 
 #else
-/* Compiler supports __FUNCTION__ (or equivalent) -- Ignore this macro */
+/* Compiler supports __func__ (or equivalent) -- Ignore this macro */
 
 #define ACPI_FUNCTION_NAME(name)
 #endif
diff --git a/include/acpi/platform/acgcc.h b/include/acpi/platform/acgcc.h
index 8996dba90cd9..8e2cdc57b197 100644
--- a/include/acpi/platform/acgcc.h
+++ b/include/acpi/platform/acgcc.h
@@ -46,7 +46,7 @@
 
 /* Function name is used for debug output. Non-ANSI, compiler-dependent */
 
-#define ACPI_GET_FUNCTION_NAME          __FUNCTION__
+#define ACPI_GET_FUNCTION_NAME          __func__
 
 /*
  * This macro is used to tag functions as "printf-like" because
diff --git a/include/asm-arm/plat-s3c/debug-macro.S b/include/asm-arm/plat-s3c/debug-macro.S
deleted file mode 100644
index 84c40b847da8..000000000000
--- a/include/asm-arm/plat-s3c/debug-macro.S
+++ /dev/null
@@ -1,75 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/debug-macro.S
- *
- * Copyright 2005, 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#include <asm/plat-s3c/regs-serial.h>
-
-/* The S3C2440 implementations are used by default as they are the
- * most widely re-used */
-
-        .macro fifo_level_s3c2440 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
-                and     \rd, \rd, #S3C2440_UFSTAT_TXMASK
-        .endm
-
-#ifndef fifo_level
-#define fifo_level fifo_level_s3c2410
-#endif
-
-        .macro  fifo_full_s3c2440 rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFSTAT ]
-                tst     \rd, #S3C2440_UFSTAT_TXFULL
-        .endm
-
-#ifndef fifo_full
-#define fifo_full fifo_full_s3c2440
-#endif
-
-        .macro  senduart,rd,rx
-                strb    \rd, [\rx, # S3C2410_UTXH ]
-        .endm
-
-        .macro  busyuart, rd, rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
-                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
-                beq     1001f                           @
-                @ FIFO enabled...
-1003:
-                fifo_full \rd, \rx
-                bne     1003b
-                b       1002f
-
-1001:
-                @ busy waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
-                tst     \rd, #S3C2410_UTRSTAT_TXFE
-                beq     1001b
-
-1002:           @ exit busyuart
-        .endm
-
-        .macro  waituart,rd,rx
-                ldr     \rd, [ \rx, # S3C2410_UFCON ]
-                tst     \rd, #S3C2410_UFCON_FIFOMODE    @ fifo enabled?
-                beq     1001f                           @
-                @ FIFO enabled...
-1003:
-                fifo_level \rd, \rx
-                teq     \rd, #0
-                bne     1003b
-                b       1002f
-1001:
-                @ idle waiting for non fifo
-                ldr     \rd, [ \rx, # S3C2410_UTRSTAT ]
-                tst     \rd, #S3C2410_UTRSTAT_TXFE
-                beq     1001b
-
-1002:           @ exit busyuart
-        .endm
diff --git a/include/asm-arm/plat-s3c/map.h b/include/asm-arm/plat-s3c/map.h
deleted file mode 100644
index b84289d32a54..000000000000
--- a/include/asm-arm/plat-s3c/map.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/map.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - Memory map definitions (virtual addresses)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_MAP_H
-#define __ASM_PLAT_MAP_H __FILE__
-
-/* Fit all our registers in at 0xF4000000 upwards, trying to use as
- * little of the VA space as possible so vmalloc and friends have a
- * better chance of getting memory.
- *
- * we try to ensure stuff like the IRQ registers are available for
- * an single MOVS instruction (ie, only 8 bits of set data)
- */
-
-#define S3C_ADDR_BASE   (0xF4000000)
-
-#ifndef __ASSEMBLY__
-#define S3C_ADDR(x)     ((void __iomem __force *)S3C_ADDR_BASE + (x))
-#else
-#define S3C_ADDR(x)     (S3C_ADDR_BASE + (x))
-#endif
-
-#define S3C_VA_IRQ      S3C_ADDR(0x00000000)    /* irq controller(s) */
-#define S3C_VA_SYS      S3C_ADDR(0x00100000)    /* system control */
-#define S3C_VA_MEM      S3C_ADDR(0x00200000)    /* system control */
-#define S3C_VA_TIMER    S3C_ADDR(0x00300000)    /* timer block */
-#define S3C_VA_WATCHDOG S3C_ADDR(0x00400000)    /* watchdog */
-#define S3C_VA_UART     S3C_ADDR(0x01000000)    /* UART */
-
-#endif /* __ASM_PLAT_MAP_H */
diff --git a/include/asm-arm/plat-s3c/regs-adc.h b/include/asm-arm/plat-s3c/regs-adc.h
deleted file mode 100644
index 4323cccc86cd..000000000000
--- a/include/asm-arm/plat-s3c/regs-adc.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-adc.h
- *
- * Copyright (c) 2004 Shannon Holland <holland@loser.net>
- *
- * This program is free software; yosu can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 ADC registers
-*/
-
-#ifndef __ASM_ARCH_REGS_ADC_H
-#define __ASM_ARCH_REGS_ADC_H "regs-adc.h"
-
-#define S3C2410_ADCREG(x) (x)
-
-#define S3C2410_ADCCON     S3C2410_ADCREG(0x00)
-#define S3C2410_ADCTSC     S3C2410_ADCREG(0x04)
-#define S3C2410_ADCDLY     S3C2410_ADCREG(0x08)
-#define S3C2410_ADCDAT0    S3C2410_ADCREG(0x0C)
-#define S3C2410_ADCDAT1    S3C2410_ADCREG(0x10)
-
-
-/* ADCCON Register Bits */
-#define S3C2410_ADCCON_ECFLG            (1<<15)
-#define S3C2410_ADCCON_PRSCEN           (1<<14)
-#define S3C2410_ADCCON_PRSCVL(x)        (((x)&0xFF)<<6)
-#define S3C2410_ADCCON_PRSCVLMASK       (0xFF<<6)
-#define S3C2410_ADCCON_SELMUX(x)        (((x)&0x7)<<3)
-#define S3C2410_ADCCON_MUXMASK          (0x7<<3)
-#define S3C2410_ADCCON_STDBM            (1<<2)
-#define S3C2410_ADCCON_READ_START       (1<<1)
-#define S3C2410_ADCCON_ENABLE_START     (1<<0)
-#define S3C2410_ADCCON_STARTMASK        (0x3<<0)
-
-
-/* ADCTSC Register Bits */
-#define S3C2410_ADCTSC_YM_SEN           (1<<7)
-#define S3C2410_ADCTSC_YP_SEN           (1<<6)
-#define S3C2410_ADCTSC_XM_SEN           (1<<5)
-#define S3C2410_ADCTSC_XP_SEN           (1<<4)
-#define S3C2410_ADCTSC_PULL_UP_DISABLE  (1<<3)
-#define S3C2410_ADCTSC_AUTO_PST         (1<<2)
-#define S3C2410_ADCTSC_XY_PST(x)        (((x)&0x3)<<0)
-
-/* ADCDAT0 Bits */
-#define S3C2410_ADCDAT0_UPDOWN          (1<<15)
-#define S3C2410_ADCDAT0_AUTO_PST        (1<<14)
-#define S3C2410_ADCDAT0_XY_PST          (0x3<<12)
-#define S3C2410_ADCDAT0_XPDATA_MASK     (0x03FF)
-
-/* ADCDAT1 Bits */
-#define S3C2410_ADCDAT1_UPDOWN          (1<<15)
-#define S3C2410_ADCDAT1_AUTO_PST        (1<<14)
-#define S3C2410_ADCDAT1_XY_PST          (0x3<<12)
-#define S3C2410_ADCDAT1_YPDATA_MASK     (0x03FF)
-
-#endif /* __ASM_ARCH_REGS_ADC_H */
-
-
diff --git a/include/asm-arm/plat-s3c/regs-serial.h b/include/asm-arm/plat-s3c/regs-serial.h
deleted file mode 100644
index a0daa647b92c..000000000000
--- a/include/asm-arm/plat-s3c/regs-serial.h
+++ /dev/null
@@ -1,232 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-serial.h
- *
- *  From linux/include/asm-arm/hardware/serial_s3c2410.h
- *
- *  Internal header file for Samsung S3C2410 serial ports (UART0-2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- *  Additional defines, (c) 2003 Simtec Electronics (linux@simtec.co.uk)
- *
- *  Adapted from:
- *
- *  Internal header file for MX1ADS serial ports (UART1 & 2)
- *
- *  Copyright (C) 2002 Shane Nay (shane@minirl.com)
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
-*/
-
-#ifndef __ASM_ARM_REGS_SERIAL_H
-#define __ASM_ARM_REGS_SERIAL_H
-
-#define S3C24XX_VA_UART0      (S3C_VA_UART)
-#define S3C24XX_VA_UART1      (S3C_VA_UART + 0x4000 )
-#define S3C24XX_VA_UART2      (S3C_VA_UART + 0x8000 )
-#define S3C24XX_VA_UART3      (S3C_VA_UART + 0xC000 )
-
-#define S3C2410_PA_UART0      (S3C24XX_PA_UART)
-#define S3C2410_PA_UART1      (S3C24XX_PA_UART + 0x4000 )
-#define S3C2410_PA_UART2      (S3C24XX_PA_UART + 0x8000 )
-#define S3C2443_PA_UART3      (S3C24XX_PA_UART + 0xC000 )
-
-#define S3C2410_URXH      (0x24)
-#define S3C2410_UTXH      (0x20)
-#define S3C2410_ULCON     (0x00)
-#define S3C2410_UCON      (0x04)
-#define S3C2410_UFCON     (0x08)
-#define S3C2410_UMCON     (0x0C)
-#define S3C2410_UBRDIV    (0x28)
-#define S3C2410_UTRSTAT   (0x10)
-#define S3C2410_UERSTAT   (0x14)
-#define S3C2410_UFSTAT    (0x18)
-#define S3C2410_UMSTAT    (0x1C)
-
-#define S3C2410_LCON_CFGMASK      ((0xF<<3)|(0x3))
-
-#define S3C2410_LCON_CS5          (0x0)
-#define S3C2410_LCON_CS6          (0x1)
-#define S3C2410_LCON_CS7          (0x2)
-#define S3C2410_LCON_CS8          (0x3)
-#define S3C2410_LCON_CSMASK       (0x3)
-
-#define S3C2410_LCON_PNONE        (0x0)
-#define S3C2410_LCON_PEVEN        (0x5 << 3)
-#define S3C2410_LCON_PODD         (0x4 << 3)
-#define S3C2410_LCON_PMASK        (0x7 << 3)
-
-#define S3C2410_LCON_STOPB        (1<<2)
-#define S3C2410_LCON_IRM          (1<<6)
-
-#define S3C2440_UCON_CLKMASK      (3<<10)
-#define S3C2440_UCON_PCLK         (0<<10)
-#define S3C2440_UCON_UCLK         (1<<10)
-#define S3C2440_UCON_PCLK2        (2<<10)
-#define S3C2440_UCON_FCLK         (3<<10)
-#define S3C2443_UCON_EPLL         (3<<10)
-
-#define S3C2440_UCON2_FCLK_EN     (1<<15)
-#define S3C2440_UCON0_DIVMASK     (15 << 12)
-#define S3C2440_UCON1_DIVMASK     (15 << 12)
-#define S3C2440_UCON2_DIVMASK     (7 << 12)
-#define S3C2440_UCON_DIVSHIFT     (12)
-
-#define S3C2412_UCON_CLKMASK    (3<<10)
-#define S3C2412_UCON_UCLK       (1<<10)
-#define S3C2412_UCON_USYSCLK    (3<<10)
-#define S3C2412_UCON_PCLK       (0<<10)
-#define S3C2412_UCON_PCLK2      (2<<10)
-
-#define S3C2410_UCON_UCLK         (1<<10)
-#define S3C2410_UCON_SBREAK       (1<<4)
-
-#define S3C2410_UCON_TXILEVEL     (1<<9)
-#define S3C2410_UCON_RXILEVEL     (1<<8)
-#define S3C2410_UCON_TXIRQMODE    (1<<2)
-#define S3C2410_UCON_RXIRQMODE    (1<<0)
-#define S3C2410_UCON_RXFIFO_TOI   (1<<7)
-#define S3C2443_UCON_RXERR_IRQEN  (1<<6)
-#define S3C2443_UCON_LOOPBACK     (1<<5)
-
-#define S3C2410_UCON_DEFAULT      (S3C2410_UCON_TXILEVEL  | \
-                                   S3C2410_UCON_RXILEVEL  | \
-                                   S3C2410_UCON_TXIRQMODE | \
-                                   S3C2410_UCON_RXIRQMODE | \
-                                   S3C2410_UCON_RXFIFO_TOI)
-
-#define S3C2410_UFCON_FIFOMODE    (1<<0)
-#define S3C2410_UFCON_TXTRIG0     (0<<6)
-#define S3C2410_UFCON_RXTRIG8     (1<<4)
-#define S3C2410_UFCON_RXTRIG12    (2<<4)
-
-/* S3C2440 FIFO trigger levels */
-#define S3C2440_UFCON_RXTRIG1     (0<<4)
-#define S3C2440_UFCON_RXTRIG8     (1<<4)
-#define S3C2440_UFCON_RXTRIG16    (2<<4)
-#define S3C2440_UFCON_RXTRIG32    (3<<4)
-
-#define S3C2440_UFCON_TXTRIG0     (0<<6)
-#define S3C2440_UFCON_TXTRIG16    (1<<6)
-#define S3C2440_UFCON_TXTRIG32    (2<<6)
-#define S3C2440_UFCON_TXTRIG48    (3<<6)
-
-#define S3C2410_UFCON_RESETBOTH   (3<<1)
-#define S3C2410_UFCON_RESETTX     (1<<2)
-#define S3C2410_UFCON_RESETRX     (1<<1)
-
-#define S3C2410_UFCON_DEFAULT     (S3C2410_UFCON_FIFOMODE | \
-                                   S3C2410_UFCON_TXTRIG0  | \
-                                   S3C2410_UFCON_RXTRIG8 )
-
-#define S3C2410_UMCOM_AFC         (1<<4)
-#define S3C2410_UMCOM_RTS_LOW     (1<<0)
-
-#define S3C2412_UMCON_AFC_63    (0<<5)          /* same as s3c2443 */
-#define S3C2412_UMCON_AFC_56    (1<<5)
-#define S3C2412_UMCON_AFC_48    (2<<5)
-#define S3C2412_UMCON_AFC_40    (3<<5)
-#define S3C2412_UMCON_AFC_32    (4<<5)
-#define S3C2412_UMCON_AFC_24    (5<<5)
-#define S3C2412_UMCON_AFC_16    (6<<5)
-#define S3C2412_UMCON_AFC_8     (7<<5)
-
-#define S3C2410_UFSTAT_TXFULL     (1<<9)
-#define S3C2410_UFSTAT_RXFULL     (1<<8)
-#define S3C2410_UFSTAT_TXMASK     (15<<4)
-#define S3C2410_UFSTAT_TXSHIFT    (4)
-#define S3C2410_UFSTAT_RXMASK     (15<<0)
-#define S3C2410_UFSTAT_RXSHIFT    (0)
-
-/* UFSTAT S3C2443 same as S3C2440 */
-#define S3C2440_UFSTAT_TXFULL     (1<<14)
-#define S3C2440_UFSTAT_RXFULL     (1<<6)
-#define S3C2440_UFSTAT_TXSHIFT    (8)
-#define S3C2440_UFSTAT_RXSHIFT    (0)
-#define S3C2440_UFSTAT_TXMASK     (63<<8)
-#define S3C2440_UFSTAT_RXMASK     (63)
-
-#define S3C2410_UTRSTAT_TXE       (1<<2)
-#define S3C2410_UTRSTAT_TXFE      (1<<1)
-#define S3C2410_UTRSTAT_RXDR      (1<<0)
-
-#define S3C2410_UERSTAT_OVERRUN   (1<<0)
-#define S3C2410_UERSTAT_FRAME     (1<<2)
-#define S3C2410_UERSTAT_BREAK     (1<<3)
-#define S3C2443_UERSTAT_PARITY    (1<<1)
-
-#define S3C2410_UERSTAT_ANY       (S3C2410_UERSTAT_OVERRUN | \
-                                   S3C2410_UERSTAT_FRAME | \
-                                   S3C2410_UERSTAT_BREAK)
-
-#define S3C2410_UMSTAT_CTS        (1<<0)
-#define S3C2410_UMSTAT_DeltaCTS   (1<<2)
-
-#define S3C2443_DIVSLOT           (0x2C)
-
-#ifndef __ASSEMBLY__
-
-/* struct s3c24xx_uart_clksrc
- *
- * this structure defines a named clock source that can be used for the
- * uart, so that the best clock can be selected for the requested baud
- * rate.
- *
- * min_baud and max_baud define the range of baud-rates this clock is
- * acceptable for, if they are both zero, it is assumed any baud rate that
- * can be generated from this clock will be used.
- *
- * divisor gives the divisor from the clock to the one seen by the uart
-*/
-
-struct s3c24xx_uart_clksrc {
-        const char      *name;
-        unsigned int     divisor;
-        unsigned int     min_baud;
-        unsigned int     max_baud;
-};
-
-/* configuration structure for per-machine configurations for the
- * serial port
- *
- * the pointer is setup by the machine specific initialisation from the
- * arch/arm/mach-s3c2410/ directory.
-*/
-
-struct s3c2410_uartcfg {
-        unsigned char      hwport;       /* hardware port number */
-        unsigned char      unused;
-        unsigned short     flags;
-        upf_t              uart_flags;   /* default uart flags */
-
-        unsigned long      ucon;         /* value of ucon for port */
-        unsigned long      ulcon;        /* value of ulcon for port */
-        unsigned long      ufcon;        /* value of ufcon for port */
-
-        struct s3c24xx_uart_clksrc *clocks;
-        unsigned int                clocks_size;
-};
-
-/* s3c24xx_uart_devs
- *
- * this is exported from the core as we cannot use driver_register(),
- * or platform_add_device() before the console_initcall()
-*/
-
-extern struct platform_device *s3c24xx_uart_devs[3];
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ASM_ARM_REGS_SERIAL_H */
-
diff --git a/include/asm-arm/plat-s3c/regs-timer.h b/include/asm-arm/plat-s3c/regs-timer.h
deleted file mode 100644
index cc0eedd53e38..000000000000
--- a/include/asm-arm/plat-s3c/regs-timer.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/* arch/arm/mach-s3c2410/include/mach/regs-timer.h
- *
- * Copyright (c) 2003 Simtec Electronics <linux@simtec.co.uk>
- *                    http://www.simtec.co.uk/products/SWLINUX/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * S3C2410 Timer configuration
-*/
-
-
-#ifndef __ASM_ARCH_REGS_TIMER_H
-#define __ASM_ARCH_REGS_TIMER_H
-
-#define S3C_TIMERREG(x) (S3C_VA_TIMER + (x))
-#define S3C_TIMERREG2(tmr,reg) S3C_TIMERREG((reg)+0x0c+((tmr)*0x0c))
-
-#define S3C2410_TCFG0         S3C_TIMERREG(0x00)
-#define S3C2410_TCFG1         S3C_TIMERREG(0x04)
-#define S3C2410_TCON          S3C_TIMERREG(0x08)
-
-#define S3C2410_TCFG_PRESCALER0_MASK (255<<0)
-#define S3C2410_TCFG_PRESCALER1_MASK (255<<8)
-#define S3C2410_TCFG_PRESCALER1_SHIFT (8)
-#define S3C2410_TCFG_DEADZONE_MASK   (255<<16)
-#define S3C2410_TCFG_DEADZONE_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX4_DIV2   (0<<16)
-#define S3C2410_TCFG1_MUX4_DIV4   (1<<16)
-#define S3C2410_TCFG1_MUX4_DIV8   (2<<16)
-#define S3C2410_TCFG1_MUX4_DIV16  (3<<16)
-#define S3C2410_TCFG1_MUX4_TCLK1  (4<<16)
-#define S3C2410_TCFG1_MUX4_MASK   (15<<16)
-#define S3C2410_TCFG1_MUX4_SHIFT  (16)
-
-#define S3C2410_TCFG1_MUX3_DIV2   (0<<12)
-#define S3C2410_TCFG1_MUX3_DIV4   (1<<12)
-#define S3C2410_TCFG1_MUX3_DIV8   (2<<12)
-#define S3C2410_TCFG1_MUX3_DIV16  (3<<12)
-#define S3C2410_TCFG1_MUX3_TCLK1  (4<<12)
-#define S3C2410_TCFG1_MUX3_MASK   (15<<12)
-
-
-#define S3C2410_TCFG1_MUX2_DIV2   (0<<8)
-#define S3C2410_TCFG1_MUX2_DIV4   (1<<8)
-#define S3C2410_TCFG1_MUX2_DIV8   (2<<8)
-#define S3C2410_TCFG1_MUX2_DIV16  (3<<8)
-#define S3C2410_TCFG1_MUX2_TCLK1  (4<<8)
-#define S3C2410_TCFG1_MUX2_MASK   (15<<8)
-
-
-#define S3C2410_TCFG1_MUX1_DIV2   (0<<4)
-#define S3C2410_TCFG1_MUX1_DIV4   (1<<4)
-#define S3C2410_TCFG1_MUX1_DIV8   (2<<4)
-#define S3C2410_TCFG1_MUX1_DIV16  (3<<4)
-#define S3C2410_TCFG1_MUX1_TCLK0  (4<<4)
-#define S3C2410_TCFG1_MUX1_MASK   (15<<4)
-
-#define S3C2410_TCFG1_MUX0_DIV2   (0<<0)
-#define S3C2410_TCFG1_MUX0_DIV4   (1<<0)
-#define S3C2410_TCFG1_MUX0_DIV8   (2<<0)
-#define S3C2410_TCFG1_MUX0_DIV16  (3<<0)
-#define S3C2410_TCFG1_MUX0_TCLK0  (4<<0)
-#define S3C2410_TCFG1_MUX0_MASK   (15<<0)
-
-#define S3C2410_TCFG1_MUX_DIV2    (0<<0)
-#define S3C2410_TCFG1_MUX_DIV4    (1<<0)
-#define S3C2410_TCFG1_MUX_DIV8    (2<<0)
-#define S3C2410_TCFG1_MUX_DIV16   (3<<0)
-#define S3C2410_TCFG1_MUX_TCLK    (4<<0)
-#define S3C2410_TCFG1_MUX_MASK    (15<<0)
-
-#define S3C2410_TCFG1_SHIFT(x)    ((x) * 4)
-
-/* for each timer, we have an count buffer, an compare buffer and
- * an observation buffer
-*/
-
-/* WARNING - timer 4 has no buffer reg, and it's observation is at +4 */
-
-#define S3C2410_TCNTB(tmr)    S3C_TIMERREG2(tmr, 0x00)
-#define S3C2410_TCMPB(tmr)    S3C_TIMERREG2(tmr, 0x04)
-#define S3C2410_TCNTO(tmr)    S3C_TIMERREG2(tmr, (((tmr) == 4) ? 0x04 : 0x08))
-
-#define S3C2410_TCON_T4RELOAD     (1<<22)
-#define S3C2410_TCON_T4MANUALUPD  (1<<21)
-#define S3C2410_TCON_T4START      (1<<20)
-
-#define S3C2410_TCON_T3RELOAD     (1<<19)
-#define S3C2410_TCON_T3INVERT     (1<<18)
-#define S3C2410_TCON_T3MANUALUPD  (1<<17)
-#define S3C2410_TCON_T3START      (1<<16)
-
-#define S3C2410_TCON_T2RELOAD     (1<<15)
-#define S3C2410_TCON_T2INVERT     (1<<14)
-#define S3C2410_TCON_T2MANUALUPD  (1<<13)
-#define S3C2410_TCON_T2START      (1<<12)
-
-#define S3C2410_TCON_T1RELOAD     (1<<11)
-#define S3C2410_TCON_T1INVERT     (1<<10)
-#define S3C2410_TCON_T1MANUALUPD  (1<<9)
-#define S3C2410_TCON_T1START      (1<<8)
-
-#define S3C2410_TCON_T0DEADZONE   (1<<4)
-#define S3C2410_TCON_T0RELOAD     (1<<3)
-#define S3C2410_TCON_T0INVERT     (1<<2)
-#define S3C2410_TCON_T0MANUALUPD  (1<<1)
-#define S3C2410_TCON_T0START      (1<<0)
-
-#endif /*  __ASM_ARCH_REGS_TIMER_H */
-
-
-
diff --git a/include/asm-arm/plat-s3c/uncompress.h b/include/asm-arm/plat-s3c/uncompress.h
deleted file mode 100644
index 19b9eda39485..000000000000
--- a/include/asm-arm/plat-s3c/uncompress.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/* linux/include/asm-arm/plat-s3c/uncompress.h
- *
- * Copyright 2003, 2007 Simtec Electronics
- *      http://armlinux.simtec.co.uk/
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * S3C - uncompress code
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifndef __ASM_PLAT_UNCOMPRESS_H
-#define __ASM_PLAT_UNCOMPRESS_H
-
-typedef unsigned int upf_t;     /* cannot include linux/serial_core.h */
-
-/* uart setup */
-
-static unsigned int fifo_mask;
-static unsigned int fifo_max;
-
-/* forward declerations */
-
-static void arch_detect_cpu(void);
-
-/* defines for UART registers */
-
-#include <asm/plat-s3c/regs-serial.h>
-#include <asm/plat-s3c/regs-watchdog.h>
-
-/* working in physical space... */
-#undef S3C2410_WDOGREG
-#define S3C2410_WDOGREG(x) ((S3C24XX_PA_WATCHDOG + (x)))
-
-/* how many bytes we allow into the FIFO at a time in FIFO mode */
-#define FIFO_MAX         (14)
-
-#define uart_base S3C24XX_PA_UART + (0x4000*CONFIG_S3C_LOWLEVEL_UART_PORT)
-
-static __inline__ void
-uart_wr(unsigned int reg, unsigned int val)
-{
-        volatile unsigned int *ptr;
-
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        *ptr = val;
-}
-
-static __inline__ unsigned int
-uart_rd(unsigned int reg)
-{
-        volatile unsigned int *ptr;
-
-        ptr = (volatile unsigned int *)(reg + uart_base);
-        return *ptr;
-}
-
-/* we can deal with the case the UARTs are being run
- * in FIFO mode, so that we don't hold up our execution
- * waiting for tx to happen...
-*/
-
-static void putc(int ch)
-{
-        if (uart_rd(S3C2410_UFCON) & S3C2410_UFCON_FIFOMODE) {
-                int level;
-
-                while (1) {
-                        level = uart_rd(S3C2410_UFSTAT);
-                        level &= fifo_mask;
-
-                        if (level < fifo_max)
-                                break;
-                }
-
-        } else {
-                /* not using fifos */
-
-                while ((uart_rd(S3C2410_UTRSTAT) & S3C2410_UTRSTAT_TXE) != S3C2410_UTRSTAT_TXE)
-                        barrier();
-        }
-
-        /* write byte to transmission register */
-        uart_wr(S3C2410_UTXH, ch);
-}
-
-static inline void flush(void)
-{
-}
-
-#define __raw_writel(d,ad) do { *((volatile unsigned int *)(ad)) = (d); } while(0)
-
-/* CONFIG_S3C_BOOT_WATCHDOG
- *
- * Simple boot-time watchdog setup, to reboot the system if there is
- * any problem with the boot process
-*/
-
-#ifdef CONFIG_S3C_BOOT_WATCHDOG
-
-#define WDOG_COUNT (0xff00)
-
-static inline void arch_decomp_wdog(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-}
-
-static void arch_decomp_wdog_start(void)
-{
-        __raw_writel(WDOG_COUNT, S3C2410_WTDAT);
-        __raw_writel(WDOG_COUNT, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x80), S3C2410_WTCON);
-}
-
-#else
-#define arch_decomp_wdog_start()
-#define arch_decomp_wdog()
-#endif
-
-#ifdef CONFIG_S3C_BOOT_ERROR_RESET
-
-static void arch_decomp_error(const char *x)
-{
-        putstr("\n\n");
-        putstr(x);
-        putstr("\n\n -- System resetting\n");
-
-        __raw_writel(0x4000, S3C2410_WTDAT);
-        __raw_writel(0x4000, S3C2410_WTCNT);
-        __raw_writel(S3C2410_WTCON_ENABLE | S3C2410_WTCON_DIV128 | S3C2410_WTCON_RSTEN | S3C2410_WTCON_PRESCALE(0x40), S3C2410_WTCON);
-
-        while(1);
-}
-
-#define arch_error arch_decomp_error
-#endif
-
-static void error(char *err);
-
-static void
-arch_decomp_setup(void)
-{
-        /* we may need to setup the uart(s) here if we are not running
-         * on an BAST... the BAST will have left the uarts configured
-         * after calling linux.
-         */
-
-        arch_detect_cpu();
-        arch_decomp_wdog_start();
-}
-
-
-#endif /* __ASM_PLAT_UNCOMPRESS_H */
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
deleted file mode 100644
index 235b753cd877..000000000000
--- a/include/asm-arm/plat-s3c24xx/clock.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/clock.h
- * linux/arch/arm/mach-s3c2410/clock.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      http://www.simtec.co.uk/products/SWLINUX/
- *      Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-struct clk {
-        struct list_head      list;
-        struct module        *owner;
-        struct clk           *parent;
-        const char           *name;
-        int                   id;
-        int                   usage;
-        unsigned long         rate;
-        unsigned long         ctrlbit;
-
-        int                 (*enable)(struct clk *, int enable);
-        int                 (*set_rate)(struct clk *c, unsigned long rate);
-        unsigned long       (*get_rate)(struct clk *c);
-        unsigned long       (*round_rate)(struct clk *c, unsigned long rate);
-        int                 (*set_parent)(struct clk *c, struct clk *parent);
-};
-
-/* other clocks which may be registered by board support */
-
-extern struct clk s3c24xx_dclk0;
-extern struct clk s3c24xx_dclk1;
-extern struct clk s3c24xx_clkout0;
-extern struct clk s3c24xx_clkout1;
-extern struct clk s3c24xx_uclk;
-
-extern struct clk clk_usb_bus;
-
-/* core clock support */
-
-extern struct clk clk_f;
-extern struct clk clk_h;
-extern struct clk clk_p;
-extern struct clk clk_mpll;
-extern struct clk clk_upll;
-extern struct clk clk_xtal;
-
-/* exports for arch/arm/mach-s3c2410
- *
- * Please DO NOT use these outside of arch/arm/mach-s3c2410
-*/
-
-extern struct mutex clocks_mutex;
-
-extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
-
-extern int s3c24xx_register_clock(struct clk *clk);
-extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
-
-extern int s3c24xx_setup_clocks(unsigned long xtal,
-                                unsigned long fclk,
-                                unsigned long hclk,
-                                unsigned long pclk);
diff --git a/include/asm-arm/plat-s3c24xx/common-smdk.h b/include/asm-arm/plat-s3c24xx/common-smdk.h
deleted file mode 100644
index 58d9094c935c..000000000000
--- a/include/asm-arm/plat-s3c24xx/common-smdk.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/common-smdk.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Common code for SMDK2410 and SMDK2440 boards
- *
- * http://www.fluff.org/ben/smdk2440/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern void smdk_machine_init(void);
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
deleted file mode 100644
index 23e420e8bd5b..000000000000
--- a/include/asm-arm/plat-s3c24xx/cpu.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/cpu.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* todo - fix when rmk changes iodescs to use `void __iomem *` */
-
-#define IODESC_ENT(x) { (unsigned long)S3C24XX_VA_##x, __phys_to_pfn(S3C24XX_PA_##x), S3C24XX_SZ_##x, MT_DEVICE }
-
-#ifndef MHZ
-#define MHZ (1000*1000)
-#endif
-
-#define print_mhz(m) ((m) / MHZ), ((m / 1000) % 1000)
-
-/* forward declaration */
-struct s3c24xx_uart_resources;
-struct platform_device;
-struct s3c2410_uartcfg;
-struct map_desc;
-
-/* core initialisation functions */
-
-extern void s3c24xx_init_irq(void);
-
-extern void s3c24xx_init_io(struct map_desc *mach_desc, int size);
-
-extern void s3c24xx_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c24xx_init_clocks(int xtal);
-
-extern void s3c24xx_init_uartdevs(char *name,
-                                  struct s3c24xx_uart_resources *res,
-                                  struct s3c2410_uartcfg *cfg, int no);
-
-/* timer for 2410/2440 */
-
-struct sys_timer;
-extern struct sys_timer s3c24xx_timer;
-
-/* system device classes */
-
-extern struct sysdev_class s3c2410_sysclass;
-extern struct sysdev_class s3c2412_sysclass;
-extern struct sysdev_class s3c2440_sysclass;
-extern struct sysdev_class s3c2442_sysclass;
-extern struct sysdev_class s3c2443_sysclass;
diff --git a/include/asm-arm/plat-s3c24xx/devs.h b/include/asm-arm/plat-s3c24xx/devs.h
deleted file mode 100644
index badaac9d64a8..000000000000
--- a/include/asm-arm/plat-s3c24xx/devs.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/devs.h
- *
- * Copyright (c) 2004 Simtec Electronics
- * Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 standard platform devices
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-#include <linux/platform_device.h>
-
-struct s3c24xx_uart_resources {
-        struct resource         *resources;
-        unsigned long            nr_resources;
-};
-
-extern struct s3c24xx_uart_resources s3c2410_uart_resources[];
-
-extern struct platform_device *s3c24xx_uart_devs[];
-extern struct platform_device *s3c24xx_uart_src[];
-
-extern struct platform_device s3c_device_timer[];
-
-extern struct platform_device s3c_device_usb;
-extern struct platform_device s3c_device_lcd;
-extern struct platform_device s3c_device_wdt;
-extern struct platform_device s3c_device_i2c;
-extern struct platform_device s3c_device_iis;
-extern struct platform_device s3c_device_rtc;
-extern struct platform_device s3c_device_adc;
-extern struct platform_device s3c_device_sdi;
-extern struct platform_device s3c_device_hsmmc;
-
-extern struct platform_device s3c_device_spi0;
-extern struct platform_device s3c_device_spi1;
-
-extern struct platform_device s3c_device_nand;
-
-extern struct platform_device s3c_device_usbgadget;
-
-/* s3c2440 specific devices */
-
-#ifdef CONFIG_CPU_S3C2440
-
-extern struct platform_device s3c_device_camif;
-
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/dma.h b/include/asm-arm/plat-s3c24xx/dma.h
deleted file mode 100644
index c78efe316fc8..000000000000
--- a/include/asm-arm/plat-s3c24xx/dma.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/dma.h
- *
- * Copyright (C) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Samsung S3C24XX DMA support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-extern struct sysdev_class dma_sysclass;
-extern struct s3c2410_dma_chan s3c2410_chans[S3C2410_DMA_CHANNELS];
-
-#define DMA_CH_VALID            (1<<31)
-#define DMA_CH_NEVER            (1<<30)
-
-struct s3c24xx_dma_addr {
-        unsigned long           from;
-        unsigned long           to;
-};
-
-/* struct s3c24xx_dma_map
- *
- * this holds the mapping information for the channel selected
- * to be connected to the specified device
-*/
-
-struct s3c24xx_dma_map {
-        const char              *name;
-        struct s3c24xx_dma_addr  hw_addr;
-
-        unsigned long            channels[S3C2410_DMA_CHANNELS];
-        unsigned long            channels_rx[S3C2410_DMA_CHANNELS];
-};
-
-struct s3c24xx_dma_selection {
-        struct s3c24xx_dma_map  *map;
-        unsigned long            map_size;
-        unsigned long            dcon_mask;
-
-        void    (*select)(struct s3c2410_dma_chan *chan,
-                          struct s3c24xx_dma_map *map);
-
-        void    (*direction)(struct s3c2410_dma_chan *chan,
-                             struct s3c24xx_dma_map *map,
-                             enum s3c2410_dmasrc dir);
-};
-
-extern int s3c24xx_dma_init_map(struct s3c24xx_dma_selection *sel);
-
-/* struct s3c24xx_dma_order_ch
- *
- * channel map for one of the `enum dma_ch` dma channels. the list
- * entry contains a set of low-level channel numbers, orred with
- * DMA_CH_VALID, which are checked in the order in the array.
-*/
-
-struct s3c24xx_dma_order_ch {
-        unsigned int    list[S3C2410_DMA_CHANNELS];     /* list of channels */
-        unsigned int    flags;                          /* flags */
-};
-
-/* struct s3c24xx_dma_order
- *
- * information provided by either the core or the board to give the
- * dma system a hint on how to allocate channels
-*/
-
-struct s3c24xx_dma_order {
-        struct s3c24xx_dma_order_ch     channels[DMACH_MAX];
-};
-
-extern int s3c24xx_dma_order_set(struct s3c24xx_dma_order *map);
-
-/* DMA init code, called from the cpu support code */
-
-extern int s3c2410_dma_init(void);
-
-extern int s3c24xx_dma_init(unsigned int channels, unsigned int irq,
-                            unsigned int stride);
diff --git a/include/asm-arm/plat-s3c24xx/irq.h b/include/asm-arm/plat-s3c24xx/irq.h
deleted file mode 100644
index 45746a995343..000000000000
--- a/include/asm-arm/plat-s3c24xx/irq.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/irq.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C24XX CPU IRQ support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#define irqdbf(x...)
-#define irqdbf2(x...)
-
-#define EXTINT_OFF (IRQ_EINT4 - 4)
-
-/* these are exported for arch/arm/mach-* usage */
-extern struct irq_chip s3c_irq_level_chip;
-extern struct irq_chip s3c_irq_chip;
-
-static inline void
-s3c_irqsub_mask(unsigned int irqno, unsigned int parentbit,
-                int subcheck)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
-
-        /* check to see if we need to mask the parent IRQ */
-
-        if ((submask  & subcheck) == subcheck) {
-                __raw_writel(mask | parentbit, S3C2410_INTMSK);
-        }
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-
-}
-
-static inline void
-s3c_irqsub_unmask(unsigned int irqno, unsigned int parentbit)
-{
-        unsigned long mask;
-        unsigned long submask;
-
-        submask = __raw_readl(S3C2410_INTSUBMSK);
-        mask = __raw_readl(S3C2410_INTMSK);
-
-        submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
-        mask &= ~parentbit;
-
-        /* write back masks */
-        __raw_writel(submask, S3C2410_INTSUBMSK);
-        __raw_writel(mask, S3C2410_INTMSK);
-}
-
-
-static inline void
-s3c_irqsub_maskack(unsigned int irqno, unsigned int parentmask, unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        s3c_irqsub_mask(irqno, parentmask, group);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-static inline void
-s3c_irqsub_ack(unsigned int irqno, unsigned int parentmask, unsigned int group)
-{
-        unsigned int bit = 1UL << (irqno - IRQ_S3CUART_RX0);
-
-        __raw_writel(bit, S3C2410_SUBSRCPND);
-
-        /* only ack parent if we've got all the irqs (seems we must
-         * ack, all and hope that the irq system retriggers ok when
-         * the interrupt goes off again)
-         */
-
-        if (1) {
-                __raw_writel(parentmask, S3C2410_SRCPND);
-                __raw_writel(parentmask, S3C2410_INTPND);
-        }
-}
-
-/* exported for use in arch/arm/mach-s3c2410 */
-
-#ifdef CONFIG_PM
-extern int s3c_irq_wake(unsigned int irqno, unsigned int state);
-#else
-#define s3c_irq_wake NULL
-#endif
-
-extern int s3c_irqext_type(unsigned int irq, unsigned int type);
diff --git a/include/asm-arm/plat-s3c24xx/pm.h b/include/asm-arm/plat-s3c24xx/pm.h
deleted file mode 100644
index cc623667e48a..000000000000
--- a/include/asm-arm/plat-s3c24xx/pm.h
+++ /dev/null
@@ -1,73 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/pm.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Written by Ben Dooks, <ben@simtec.co.uk>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-/* s3c2410_pm_init
- *
- * called from board at initialisation time to setup the power
- * management
-*/
-
-#ifdef CONFIG_PM
-
-extern __init int s3c2410_pm_init(void);
-
-#else
-
-static inline int s3c2410_pm_init(void)
-{
-        return 0;
-}
-#endif
-
-/* configuration for the IRQ mask over sleep */
-extern unsigned long s3c_irqwake_intmask;
-extern unsigned long s3c_irqwake_eintmask;
-
-/* IRQ masks for IRQs allowed to go to sleep (see irq.c) */
-extern unsigned long s3c_irqwake_intallow;
-extern unsigned long s3c_irqwake_eintallow;
-
-/* per-cpu sleep functions */
-
-extern void (*pm_cpu_prep)(void);
-extern void (*pm_cpu_sleep)(void);
-
-/* Flags for PM Control */
-
-extern unsigned long s3c_pm_flags;
-
-/* from sleep.S */
-
-extern int  s3c2410_cpu_save(unsigned long *saveblk);
-extern void s3c2410_cpu_suspend(void);
-extern void s3c2410_cpu_resume(void);
-
-extern unsigned long s3c2410_sleep_save_phys;
-
-/* sleep save info */
-
-struct sleep_save {
-        void __iomem    *reg;
-        unsigned long   val;
-};
-
-#define SAVE_ITEM(x) \
-        { .reg = (x) }
-
-extern void s3c2410_pm_do_save(struct sleep_save *ptr, int count);
-extern void s3c2410_pm_do_restore(struct sleep_save *ptr, int count);
-
-#ifdef CONFIG_PM
-extern int s3c24xx_irq_suspend(struct sys_device *dev, pm_message_t state);
-extern int s3c24xx_irq_resume(struct sys_device *dev);
-#else
-#define s3c24xx_irq_suspend NULL
-#define s3c24xx_irq_resume  NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2400.h b/include/asm-arm/plat-s3c24xx/s3c2400.h
deleted file mode 100644
index 3a5a16821af8..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2400.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2400.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for S3C2400 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
- * Modifications:
- *     09-Fev-2006 LCVR  First version, based on s3c2410.h
-*/
-
-#ifdef CONFIG_CPU_S3C2400
-
-extern  int s3c2400_init(void);
-
-extern void s3c2400_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2400_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2400_init_clocks(int xtal);
-
-#else
-#define s3c2400_init_clocks NULL
-#define s3c2400_init_uarts NULL
-#define s3c2400_map_io NULL
-#define s3c2400_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2410.h b/include/asm-arm/plat-s3c24xx/s3c2410.h
deleted file mode 100644
index 3cd1ec677b3f..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2410.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2410.h
- *
- * Copyright (c) 2004 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2410 machine directory
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- *
-*/
-
-#ifdef CONFIG_CPU_S3C2410
-
-extern  int s3c2410_init(void);
-
-extern void s3c2410_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2410_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2410_init_clocks(int xtal);
-
-#else
-#define s3c2410_init_clocks NULL
-#define s3c2410_init_uarts NULL
-#define s3c2410_map_io NULL
-#define s3c2410_init NULL
-#endif
-
-extern int s3c2410_baseclk_add(void);
diff --git a/include/asm-arm/plat-s3c24xx/s3c2412.h b/include/asm-arm/plat-s3c24xx/s3c2412.h
deleted file mode 100644
index 3ec97685e781..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2412.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2412.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2412 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2412
-
-extern  int s3c2412_init(void);
-
-extern void s3c2412_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2412_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2412_init_clocks(int xtal);
-
-extern  int s3c2412_baseclk_add(void);
-#else
-#define s3c2412_init_clocks NULL
-#define s3c2412_init_uarts NULL
-#define s3c2412_map_io NULL
-#define s3c2412_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2440.h b/include/asm-arm/plat-s3c24xx/s3c2440.h
deleted file mode 100644
index 107853bf9481..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2440.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2440.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2440 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2440
-extern  int s3c2440_init(void);
-#else
-#define s3c2440_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2442.h b/include/asm-arm/plat-s3c24xx/s3c2442.h
deleted file mode 100644
index 451a23a2092a..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2442.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2442.h
- *
- * Copyright (c) 2006 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2442 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2442
-extern  int s3c2442_init(void);
-#else
-#define s3c2442_init NULL
-#endif
diff --git a/include/asm-arm/plat-s3c24xx/s3c2443.h b/include/asm-arm/plat-s3c24xx/s3c2443.h
deleted file mode 100644
index 11d83b5c84e6..000000000000
--- a/include/asm-arm/plat-s3c24xx/s3c2443.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/* linux/include/asm-arm/plat-s3c24xx/s3c2443.h
- *
- * Copyright (c) 2004-2005 Simtec Electronics
- *      Ben Dooks <ben@simtec.co.uk>
- *
- * Header file for s3c2443 cpu support
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
-*/
-
-#ifdef CONFIG_CPU_S3C2443
-
-struct s3c2410_uartcfg;
-
-extern  int s3c2443_init(void);
-
-extern void s3c2443_map_io(struct map_desc *mach_desc, int size);
-
-extern void s3c2443_init_uarts(struct s3c2410_uartcfg *cfg, int no);
-
-extern void s3c2443_init_clocks(int xtal);
-
-extern  int s3c2443_baseclk_add(void);
-
-#else
-#define s3c2443_init_clocks NULL
-#define s3c2443_init_uarts NULL
-#define s3c2443_map_io NULL
-#define s3c2443_init NULL
-#endif
diff --git a/include/asm-blackfin/.gitignore b/include/asm-blackfin/.gitignore
deleted file mode 100644
index 7858564a4466..000000000000
--- a/include/asm-blackfin/.gitignore
+++ /dev/null
@@ -1 +0,0 @@
-+mach
diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild
deleted file mode 100644
index 606ecfdcc962..000000000000
--- a/include/asm-blackfin/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-unifdef-y += fixed_code.h
diff --git a/include/asm-blackfin/a.out.h b/include/asm-blackfin/a.out.h
deleted file mode 100644
index 6c3d652ebd33..000000000000
--- a/include/asm-blackfin/a.out.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __BFIN_A_OUT_H__
-#define __BFIN_A_OUT_H__
-
-struct exec {
-        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
-        unsigned a_text;        /* length of text, in bytes */
-        unsigned a_data;        /* length of data, in bytes */
-        unsigned a_bss;         /* length of uninitialized data area for file, in bytes */
-        unsigned a_syms;        /* length of symbol table data in file, in bytes */
-        unsigned a_entry;       /* start address */
-        unsigned a_trsize;      /* length of relocation info for text, in bytes */
-        unsigned a_drsize;      /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif                          /* __BFIN_A_OUT_H__ */
diff --git a/include/asm-blackfin/atomic.h b/include/asm-blackfin/atomic.h
deleted file mode 100644
index 7cf508718605..000000000000
--- a/include/asm-blackfin/atomic.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef __ARCH_BLACKFIN_ATOMIC__
-#define __ARCH_BLACKFIN_ATOMIC__
-
-#include <asm/system.h> /* local_irq_XXX() */
-
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- *
- * Generally we do not concern about SMP BFIN systems, so we don't have
- * to deal with that.
- *
- * Tony Kou (tonyko@lineo.ca)   Lineo Inc.   2001
- */
-
-typedef struct {
-        int counter;
-} atomic_t;
-#define ATOMIC_INIT(i)  { (i) }
-
-#define atomic_read(v)          ((v)->counter)
-#define atomic_set(v, i)        (((v)->counter) = i)
-
-static __inline__ void atomic_add(int i, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter += i;
-        local_irq_restore(flags);
-}
-
-static __inline__ void atomic_sub(int i, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter -= i;
-        local_irq_restore(flags);
-
-}
-
-static inline int atomic_add_return(int i, atomic_t * v)
-{
-        int __temp = 0;
-        long flags;
-
-        local_irq_save(flags);
-        v->counter += i;
-        __temp = v->counter;
-        local_irq_restore(flags);
-
-
-        return __temp;
-}
-
-#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
-static inline int atomic_sub_return(int i, atomic_t * v)
-{
-        int __temp = 0;
-        long flags;
-
-        local_irq_save(flags);
-        v->counter -= i;
-        __temp = v->counter;
-        local_irq_restore(flags);
-
-        return __temp;
-}
-
-static __inline__ void atomic_inc(volatile atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter++;
-        local_irq_restore(flags);
-}
-
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
-
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-static __inline__ void atomic_dec(volatile atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter--;
-        local_irq_restore(flags);
-}
-
-static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter &= ~mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
-{
-        long flags;
-
-        local_irq_save(flags);
-        v->counter |= mask;
-        local_irq_restore(flags);
-}
-
-/* Atomic operations are already serializing */
-#define smp_mb__before_atomic_dec()    barrier()
-#define smp_mb__after_atomic_dec() barrier()
-#define smp_mb__before_atomic_inc()    barrier()
-#define smp_mb__after_atomic_inc() barrier()
-
-#define atomic_dec_return(v) atomic_sub_return(1,(v))
-#define atomic_inc_return(v) atomic_add_return(1,(v))
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
-#include <asm-generic/atomic.h>
-
-#endif                          /* __ARCH_BLACKFIN_ATOMIC __ */
diff --git a/include/asm-blackfin/auxvec.h b/include/asm-blackfin/auxvec.h
deleted file mode 100644
index 215506cd87b7..000000000000
--- a/include/asm-blackfin/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASMBFIN_AUXVEC_H
-#define __ASMBFIN_AUXVEC_H
-
-#endif
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
deleted file mode 100644
index 7ba70de66f2b..000000000000
--- a/include/asm-blackfin/bfin-global.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * File:         include/asm-blackfin/bfin-global.h
- * Based on:
- * Author: *
- * Created:
- * Description:  Global extern defines for blackfin
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _BFIN_GLOBAL_H_
-#define _BFIN_GLOBAL_H_
-
-#ifndef __ASSEMBLY__
-
-#include <asm-generic/sections.h>
-#include <asm/ptrace.h>
-#include <asm/user.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-
-#if defined(CONFIG_DMA_UNCACHED_4M)
-# define DMA_UNCACHED_REGION (4 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_2M)
-# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
-#elif defined(CONFIG_DMA_UNCACHED_1M)
-# define DMA_UNCACHED_REGION (1024 * 1024)
-#else
-# define DMA_UNCACHED_REGION (0)
-#endif
-
-extern unsigned long get_cclk(void);
-extern unsigned long get_sclk(void);
-extern unsigned long sclk_to_usecs(unsigned long sclk);
-extern unsigned long usecs_to_sclk(unsigned long usecs);
-
-extern void dump_bfin_process(struct pt_regs *regs);
-extern void dump_bfin_mem(struct pt_regs *regs);
-extern void dump_bfin_trace_buffer(void);
-
-/* init functions only */
-extern int init_arch_irq(void);
-extern void bfin_icache_init(void);
-extern void bfin_dcache_init(void);
-extern void init_exception_vectors(void);
-extern void program_IAR(void);
-
-extern void bfin_reset(void);
-extern asmlinkage void lower_to_irq14(void);
-extern asmlinkage void bfin_return_from_exception(void);
-extern asmlinkage void evt14_softirq(void);
-extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
-extern int bfin_internal_set_wake(unsigned int irq, unsigned int state);
-
-extern void *l1_data_A_sram_alloc(size_t);
-extern void *l1_data_B_sram_alloc(size_t);
-extern void *l1_inst_sram_alloc(size_t);
-extern void *l1_data_sram_alloc(size_t);
-extern void *l1_data_sram_zalloc(size_t);
-extern void *l2_sram_alloc(size_t);
-extern void *l2_sram_zalloc(size_t);
-extern int l1_data_A_sram_free(const void*);
-extern int l1_data_B_sram_free(const void*);
-extern int l1_inst_sram_free(const void*);
-extern int l1_data_sram_free(const void*);
-extern int l2_sram_free(const void *);
-extern int sram_free(const void*);
-
-#define L1_INST_SRAM            0x00000001
-#define L1_DATA_A_SRAM          0x00000002
-#define L1_DATA_B_SRAM          0x00000004
-#define L1_DATA_SRAM            0x00000006
-#define L2_SRAM                 0x00000008
-extern void *sram_alloc_with_lsl(size_t, unsigned long);
-extern int sram_free_with_lsl(const void*);
-
-extern const char bfin_board_name[];
-
-extern unsigned long bfin_sic_iwr[];
-extern unsigned vr_wakeup;
-extern u16 _bfin_swrst; /* shadow for Software Reset Register (SWRST) */
-extern unsigned long _ramstart, _ramend, _rambase;
-extern unsigned long memory_start, memory_end, physical_mem_end;
-extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
-        _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[],
-        _stext_l2[], _etext_l2[], _sdata_l2[], _edata_l2[], _sbss_l2[],
-        _ebss_l2[], _l2_lma_start[];
-
-/* only used when CONFIG_MTD_UCLINUX */
-extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
-
-#ifdef CONFIG_BFIN_ICACHE_LOCK
-extern void cache_grab_lock(int way);
-extern void cache_lock(int way);
-#endif
-
-#endif
-
-#endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
deleted file mode 100644
index 9fa19158e38d..000000000000
--- a/include/asm-blackfin/bfin5xx_spi.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/************************************************************
-
-* Copyright (C) 2006-2008, Analog Devices. All Rights Reserved
-*
-* FILE bfin5xx_spi.h
-* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
-*
-*
-* DATE OF CREATION: March. 10th 2006
-*
-* SYNOPSIS:
-*
-* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
-**************************************************************
-
-* MODIFICATION HISTORY:
-* March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
-
-************************************************************/
-
-#ifndef _SPI_CHANNEL_H_
-#define _SPI_CHANNEL_H_
-
-#define SPI_READ              0
-#define SPI_WRITE             1
-
-#define SPI_CTRL_OFF            0x0
-#define SPI_FLAG_OFF            0x4
-#define SPI_STAT_OFF            0x8
-#define SPI_TXBUFF_OFF          0xc
-#define SPI_RXBUFF_OFF          0x10
-#define SPI_BAUD_OFF            0x14
-#define SPI_SHAW_OFF            0x18
-
-
-#define BIT_CTL_ENABLE      0x4000
-#define BIT_CTL_OPENDRAIN   0x2000
-#define BIT_CTL_MASTER      0x1000
-#define BIT_CTL_POLAR       0x0800
-#define BIT_CTL_PHASE       0x0400
-#define BIT_CTL_BITORDER    0x0200
-#define BIT_CTL_WORDSIZE    0x0100
-#define BIT_CTL_MISOENABLE  0x0020
-#define BIT_CTL_RXMOD       0x0000
-#define BIT_CTL_TXMOD       0x0001
-#define BIT_CTL_TIMOD_DMA_TX 0x0003
-#define BIT_CTL_TIMOD_DMA_RX 0x0002
-#define BIT_CTL_SENDOPT     0x0004
-#define BIT_CTL_TIMOD       0x0003
-
-#define BIT_STAT_SPIF       0x0001
-#define BIT_STAT_MODF       0x0002
-#define BIT_STAT_TXE        0x0004
-#define BIT_STAT_TXS        0x0008
-#define BIT_STAT_RBSY       0x0010
-#define BIT_STAT_RXS        0x0020
-#define BIT_STAT_TXCOL      0x0040
-#define BIT_STAT_CLR        0xFFFF
-
-#define BIT_STU_SENDOVER    0x0001
-#define BIT_STU_RECVFULL    0x0020
-
-#define CFG_SPI_ENABLE      1
-#define CFG_SPI_DISABLE     0
-
-#define CFG_SPI_OUTENABLE   1
-#define CFG_SPI_OUTDISABLE  0
-
-#define CFG_SPI_ACTLOW      1
-#define CFG_SPI_ACTHIGH     0
-
-#define CFG_SPI_PHASESTART  1
-#define CFG_SPI_PHASEMID    0
-
-#define CFG_SPI_MASTER      1
-#define CFG_SPI_SLAVE       0
-
-#define CFG_SPI_SENELAST    0
-#define CFG_SPI_SENDZERO    1
-
-#define CFG_SPI_RCVFLUSH    1
-#define CFG_SPI_RCVDISCARD  0
-
-#define CFG_SPI_LSBFIRST    1
-#define CFG_SPI_MSBFIRST    0
-
-#define CFG_SPI_WORDSIZE16  1
-#define CFG_SPI_WORDSIZE8   0
-
-#define CFG_SPI_MISOENABLE   1
-#define CFG_SPI_MISODISABLE  0
-
-#define CFG_SPI_READ      0x00
-#define CFG_SPI_WRITE     0x01
-#define CFG_SPI_DMAREAD   0x02
-#define CFG_SPI_DMAWRITE  0x03
-
-#define CFG_SPI_CSCLEARALL  0
-#define CFG_SPI_CHIPSEL1    1
-#define CFG_SPI_CHIPSEL2    2
-#define CFG_SPI_CHIPSEL3    3
-#define CFG_SPI_CHIPSEL4    4
-#define CFG_SPI_CHIPSEL5    5
-#define CFG_SPI_CHIPSEL6    6
-#define CFG_SPI_CHIPSEL7    7
-
-#define CFG_SPI_CS1VALUE    1
-#define CFG_SPI_CS2VALUE    2
-#define CFG_SPI_CS3VALUE    3
-#define CFG_SPI_CS4VALUE    4
-#define CFG_SPI_CS5VALUE    5
-#define CFG_SPI_CS6VALUE    6
-#define CFG_SPI_CS7VALUE    7
-
-#define CMD_SPI_SET_BAUDRATE  2
-#define CMD_SPI_GET_SYSTEMCLOCK   25
-#define CMD_SPI_SET_WRITECONTINUOUS     26
-
-/* device.platform_data for SSP controller devices */
-struct bfin5xx_spi_master {
-        u16 num_chipselect;
-        u8 enable_dma;
-        u16 pin_req[4];
-};
-
-/* spi_board_info.controller_data for SPI slave devices,
- * copied to spi_device.platform_data ... mostly for dma tuning
- */
-struct bfin5xx_spi_chip {
-        u16 ctl_reg;
-        u8 enable_dma;
-        u8 bits_per_word;
-        u8 cs_change_per_word;
-        u16 cs_chg_udelay; /* Some devices require 16-bit delays */
-};
-
-#endif /* _SPI_CHANNEL_H_ */
diff --git a/include/asm-blackfin/bfin_simple_timer.h b/include/asm-blackfin/bfin_simple_timer.h
deleted file mode 100644
index fccbb595464a..000000000000
--- a/include/asm-blackfin/bfin_simple_timer.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _bfin_simple_timer_h_
-#define _bfin_simple_timer_h_
-
-#include <linux/ioctl.h>
-
-#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
-
-#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  2)
-#define BFIN_SIMPLE_TIMER_START      _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
-#define BFIN_SIMPLE_TIMER_STOP       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
-#define BFIN_SIMPLE_TIMER_READ       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
-
-#endif
diff --git a/include/asm-blackfin/bfin_sport.h b/include/asm-blackfin/bfin_sport.h
deleted file mode 100644
index c76ed8def302..000000000000
--- a/include/asm-blackfin/bfin_sport.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * File:         include/asm-blackfin/bfin_sport.h
- * Based on:
- * Author:       Roy Huang (roy.huang@analog.com)
- *
- * Created:      Thu Aug. 24 2006
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __BFIN_SPORT_H__
-#define __BFIN_SPORT_H__
-
-#define SPORT_MAJOR     237
-#define SPORT_NR_DEVS   2
-
-/* Sport mode: it can be set to TDM, i2s or others */
-#define NORM_MODE       0x0
-#define TDM_MODE        0x1
-#define I2S_MODE        0x2
-
-/* Data format, normal, a-law or u-law */
-#define NORM_FORMAT     0x0
-#define ALAW_FORMAT     0x2
-#define ULAW_FORMAT     0x3
-struct sport_register;
-
-/* Function driver which use sport must initialize the structure */
-struct sport_config {
-        /*TDM (multichannels), I2S or other mode */
-        unsigned int mode:3;
-
-        /* if TDM mode is selected, channels must be set */
-        int channels;           /* Must be in 8 units */
-        unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
-
-        /* I2S mode */
-        unsigned int right_first:1;     /* Right stereo channel first */
-
-        /* In mormal mode, the following item need to be set */
-        unsigned int lsb_first:1;       /* order of transmit or receive data */
-        unsigned int fsync:1;   /* Frame sync required */
-        unsigned int data_indep:1;      /* data independent frame sync generated */
-        unsigned int act_low:1; /* Active low TFS */
-        unsigned int late_fsync:1;      /* Late frame sync */
-        unsigned int tckfe:1;
-        unsigned int sec_en:1;  /* Secondary side enabled */
-
-        /* Choose clock source */
-        unsigned int int_clk:1; /* Internal or external clock */
-
-        /* If external clock is used, the following fields are ignored */
-        int serial_clk;
-        int fsync_clk;
-
-        unsigned int data_format:2;     /*Normal, u-law or a-law */
-
-        int word_len;           /* How length of the word in bits, 3-32 bits */
-        int dma_enabled;
-};
-
-struct sport_register {
-        unsigned short tcr1;
-        unsigned short reserved0;
-        unsigned short tcr2;
-        unsigned short reserved1;
-        unsigned short tclkdiv;
-        unsigned short reserved2;
-        unsigned short tfsdiv;
-        unsigned short reserved3;
-        unsigned long tx;
-        unsigned long reserved_l0;
-        unsigned long rx;
-        unsigned long reserved_l1;
-        unsigned short rcr1;
-        unsigned short reserved4;
-        unsigned short rcr2;
-        unsigned short reserved5;
-        unsigned short rclkdiv;
-        unsigned short reserved6;
-        unsigned short rfsdiv;
-        unsigned short reserved7;
-        unsigned short stat;
-        unsigned short reserved8;
-        unsigned short chnl;
-        unsigned short reserved9;
-        unsigned short mcmc1;
-        unsigned short reserved10;
-        unsigned short mcmc2;
-        unsigned short reserved11;
-        unsigned long mtcs0;
-        unsigned long mtcs1;
-        unsigned long mtcs2;
-        unsigned long mtcs3;
-        unsigned long mrcs0;
-        unsigned long mrcs1;
-        unsigned long mrcs2;
-        unsigned long mrcs3;
-};
-
-#define SPORT_IOC_MAGIC         'P'
-#define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
-
-/* Test purpose */
-#define ENABLE_AD73311          _IOWR('P', 0x02, int)
-
-struct sport_dev {
-        struct cdev cdev;       /* Char device structure */
-
-        int sport_num;
-
-        int dma_rx_chan;
-        int dma_tx_chan;
-
-        int rx_irq;
-        unsigned char *rx_buf;  /* Buffer store the received data */
-        int rx_len;             /* How many bytes will be received */
-        int rx_received;        /* How many bytes has been received */
-
-        int tx_irq;
-        const unsigned char *tx_buf;
-        int tx_len;
-        int tx_sent;
-
-        int sport_err_irq;
-
-        struct mutex mutex;     /* mutual exclusion semaphore */
-        struct task_struct *task;
-
-        wait_queue_head_t waitq;
-        int     wait_con;
-        struct sport_register *regs;
-        struct sport_config config;
-};
-
-#define SPORT_TCR1      0
-#define SPORT_TCR2      1
-#define SPORT_TCLKDIV   2
-#define SPORT_TFSDIV    3
-#define SPORT_RCR1      8
-#define SPORT_RCR2      9
-#define SPORT_RCLKDIV   10
-#define SPORT_RFSDIV    11
-#define SPORT_CHANNEL   13
-#define SPORT_MCMC1     14
-#define SPORT_MCMC2     15
-#define SPORT_MTCS0     16
-#define SPORT_MTCS1     17
-#define SPORT_MTCS2     18
-#define SPORT_MTCS3     19
-#define SPORT_MRCS0     20
-#define SPORT_MRCS1     21
-#define SPORT_MRCS2     22
-#define SPORT_MRCS3     23
-
-#endif                          /*__BFIN_SPORT_H__*/
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
deleted file mode 100644
index b39a175c79c1..000000000000
--- a/include/asm-blackfin/bitops.h
+++ /dev/null
@@ -1,218 +0,0 @@
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#include <linux/compiler.h>
-#include <asm/byteorder.h>      /* swab32 */
-#include <asm/system.h>         /* save_flags */
-
-#ifdef __KERNEL__
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/ffz.h>
-
-static __inline__ void set_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        *a |= mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        *a |= mask;
-}
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      barrier()
-#define smp_mb__after_clear_bit()       barrier()
-
-static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-        unsigned long flags;
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        *a &= ~mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        *a &= ~mask;
-}
-
-static __inline__ void change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, flags;
-        unsigned long *ADDR = (unsigned long *)addr;
-
-        ADDR += nr >> 5;
-        mask = 1 << (nr & 31);
-        local_irq_save(flags);
-        *ADDR ^= mask;
-        local_irq_restore(flags);
-}
-
-static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask;
-        unsigned long *ADDR = (unsigned long *)addr;
-
-        ADDR += nr >> 5;
-        mask = 1 << (nr & 31);
-        *ADDR ^= mask;
-}
-
-static __inline__ int test_and_set_bit(int nr, void *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        retval = (mask & *a) != 0;
-        *a |= mask;
-        local_irq_restore(flags);
-
-        return retval;
-}
-
-static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        retval = (mask & *a) != 0;
-        *a |= mask;
-        return retval;
-}
-
-static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        retval = (mask & *a) != 0;
-        *a &= ~mask;
-        local_irq_restore(flags);
-
-        return retval;
-}
-
-static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        retval = (mask & *a) != 0;
-        *a &= ~mask;
-        return retval;
-}
-
-static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-        unsigned long flags;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        local_irq_save(flags);
-        retval = (mask & *a) != 0;
-        *a ^= mask;
-        local_irq_restore(flags);
-        return retval;
-}
-
-static __inline__ int __test_and_change_bit(int nr,
-                                            volatile unsigned long *addr)
-{
-        int mask, retval;
-        volatile unsigned int *a = (volatile unsigned int *)addr;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        retval = (mask & *a) != 0;
-        *a ^= mask;
-        return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const void *addr)
-{
-        return ((1UL << (nr & 31)) &
-                (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, const void *addr)
-{
-        int *a = (int *)addr;
-        int mask;
-
-        a += nr >> 5;
-        mask = 1 << (nr & 0x1f);
-        return ((mask & *a) != 0);
-}
-
-#define test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#include <asm-generic/bitops/find.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/lock.h>
-
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
-
-#include <asm-generic/bitops/minix.h>
-
-#endif                          /* __KERNEL__ */
-
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif                          /* _BLACKFIN_BITOPS_H */
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
deleted file mode 100644
index 984b74f0a2ec..000000000000
--- a/include/asm-blackfin/blackfin.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _BLACKFIN_H_
-#define _BLACKFIN_H_
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-#include <asm/mach/anomaly.h>
-
-#ifndef __ASSEMBLY__
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
-        int _tmp;
-        if (ANOMALY_05000312)
-                __asm__ __volatile__(
-                        "cli %0;"
-                        "nop;"
-                        "nop;"
-                        "ssync;"
-                        "sti %0;"
-                        : "=d" (_tmp)
-                );
-        else if (ANOMALY_05000244)
-                __asm__ __volatile__(
-                        "nop;"
-                        "nop;"
-                        "nop;"
-                        "ssync;"
-                );
-        else
-                __asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
-        int _tmp;
-        if (ANOMALY_05000312)
-                __asm__ __volatile__(
-                        "cli %0;"
-                        "nop;"
-                        "nop;"
-                        "csync;"
-                        "sti %0;"
-                        : "=d" (_tmp)
-                );
-        else if (ANOMALY_05000244)
-                __asm__ __volatile__(
-                        "nop;"
-                        "nop;"
-                        "nop;"
-                        "csync;"
-                );
-        else
-                __asm__ __volatile__("csync;");
-}
-
-#else  /* __ASSEMBLY__ */
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-
-#elif ANOMALY_05000244
-#define SSYNC(scratch) nop; nop; nop; SSYNC;
-#define CSYNC(scratch) nop; nop; nop; CSYNC;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#include <asm/mach/blackfin.h>
-#include <asm/bfin-global.h>
-
-#endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h
deleted file mode 100644
index 6d3e11b1fc57..000000000000
--- a/include/asm-blackfin/bug.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _BLACKFIN_BUG_H
-#define _BLACKFIN_BUG_H
-
-#ifdef CONFIG_BUG
-#define HAVE_ARCH_BUG
-
-#define BUG() do { \
-        dump_bfin_trace_buffer(); \
-        printk(KERN_EMERG "BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
-        panic("BUG!"); \
-} while (0)
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif
diff --git a/include/asm-blackfin/bugs.h b/include/asm-blackfin/bugs.h
deleted file mode 100644
index 9093c9c1fb81..000000000000
--- a/include/asm-blackfin/bugs.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- *  include/asm-blackfin/bugs.h
- *
- *  Copyright (C) 1994  Linus Torvalds
- */
-
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Needs:
- *      void check_bugs(void);
- */
-
-static void check_bugs(void)
-{
-}
diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
deleted file mode 100644
index 6a673d42da18..000000000000
--- a/include/asm-blackfin/byteorder.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef _BLACKFIN_BYTEORDER_H
-#define _BLACKFIN_BYTEORDER_H
-
-#include <asm/types.h>
-#include <linux/compiler.h>
-
-#ifdef __GNUC__
-
-static __inline__ __attribute_const__ __u32 ___arch__swahb32(__u32 xx)
-{
-        __u32 tmp;
-        __asm__("%1 = %0 >> 8 (V);\n\t"
-                "%0 = %0 << 8 (V);\n\t"
-                "%0 = %0 | %1;\n\t"
-                : "+d"(xx), "=&d"(tmp));
-        return xx;
-}
-
-static __inline__ __attribute_const__ __u32 ___arch__swahw32(__u32 xx)
-{
-        __u32 rv;
-        __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
-        return rv;
-}
-
-#define __arch__swahb32(x) ___arch__swahb32(x)
-#define __arch__swahw32(x) ___arch__swahw32(x)
-#define __arch__swab32(x) ___arch__swahb32(___arch__swahw32(x))
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 xx)
-{
-        __u32 xw = xx;
-        __asm__("%0 <<= 8;\n    %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
-        return (__u16)xw;
-}
-
-#define __arch__swab16(x) ___arch__swab16(x)
-
-#endif
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/little_endian.h>
-
-#endif                          /* _BLACKFIN_BYTEORDER_H */
diff --git a/include/asm-blackfin/cache.h b/include/asm-blackfin/cache.h
deleted file mode 100644
index 023d72133b5a..000000000000
--- a/include/asm-blackfin/cache.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * include/asm-blackfin/cache.h
- */
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT  5
-#define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES L1_CACHE_BYTES
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned                             \
-          __attribute__((__aligned__(L1_CACHE_BYTES),   \
-                __section__(".data_l1.cacheline_aligned")))
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX      5
-
-#endif
diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h
deleted file mode 100644
index d81a77545a04..000000000000
--- a/include/asm-blackfin/cacheflush.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * File:         include/asm-blackfin/cacheflush.h
- * Based on:     include/asm-m68knommu/cacheflush.h
- * Author:       LG Soft India
- *               Copyright (C) 2004 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  Blackfin low-level cache routines adapted from the i386
- *               and PPC versions by Greg Ungerer (gerg@snapgear.com)
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BLACKFIN_CACHEFLUSH_H
-#define _BLACKFIN_CACHEFLUSH_H
-
-#include <asm/cplb.h>
-
-extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
-extern void blackfin_icache_flush_range(unsigned int, unsigned int);
-extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
-extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
-extern void blackfin_dflush_page(void *);
-
-#define flush_dcache_mmap_lock(mapping)         do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
-#define flush_cache_mm(mm)                      do { } while (0)
-#define flush_cache_range(vma, start, end)      do { } while (0)
-#define flush_cache_page(vma, vmaddr)           do { } while (0)
-#define flush_cache_vmap(start, end)            do { } while (0)
-#define flush_cache_vunmap(start, end)          do { } while (0)
-
-static inline void flush_icache_range(unsigned start, unsigned end)
-{
-#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_ICACHE)
-
-# if defined(CONFIG_BFIN_WT)
-        blackfin_icache_flush_range((start), (end));
-# else
-        blackfin_icache_dcache_flush_range((start), (end));
-# endif
-
-#else
-
-# if defined(CONFIG_BFIN_ICACHE)
-        blackfin_icache_flush_range((start), (end));
-# endif
-# if defined(CONFIG_BFIN_DCACHE)
-        blackfin_dcache_flush_range((start), (end));
-# endif
-
-#endif
-}
-
-#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
-do { memcpy(dst, src, len); \
-     flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
-} while (0)
-#define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
-
-#if defined(CONFIG_BFIN_DCACHE)
-# define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
-#else
-# define invalidate_dcache_range(start,end)     do { } while (0)
-#endif
-#if defined(CONFIG_BFIN_DCACHE) && defined(CONFIG_BFIN_WB)
-# define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
-# define flush_dcache_page(page)                        blackfin_dflush_page(page_address(page))
-#else
-# define flush_dcache_range(start,end)          do { } while (0)
-# define flush_dcache_page(page)                        do { } while (0)
-#endif
-
-#endif                          /* _BLACKFIN_ICACHEFLUSH_H */
diff --git a/include/asm-blackfin/checksum.h b/include/asm-blackfin/checksum.h
deleted file mode 100644
index 6f6af2b8e9e0..000000000000
--- a/include/asm-blackfin/checksum.h
+++ /dev/null
@@ -1,100 +0,0 @@
-#ifndef _BFIN_CHECKSUM_H
-#define _BFIN_CHECKSUM_H
-
-/*
- * MODIFIED FOR BFIN April 30, 2001 akbar.hussain@lineo.com
- *
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-/*
- * the same as csum_partial, but copies from src while it
- * checksums
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-__wsum csum_partial_copy(const void *src, void *dst,
-                               int len, __wsum sum);
-
-/*
- * the same as csum_partial_copy, but copies from user space.
- *
- * here even more important to align src and dst on a 32-bit (or even
- * better 64-bit) boundary
- */
-
-extern __wsum csum_partial_copy_from_user(const void __user *src, void *dst,
-                                          int len, __wsum sum, int *csum_err);
-
-#define csum_partial_copy_nocheck(src, dst, len, sum)   \
-        csum_partial_copy((src), (dst), (len), (sum))
-
-__sum16 ip_fast_csum(unsigned char *iph, unsigned int ihl);
-
-/*
- *      Fold a partial checksum
- */
-
-static inline __sum16 csum_fold(__wsum sum)
-{
-        while (sum >> 16)
-                sum = (sum & 0xffff) + (sum >> 16);
-        return ((~(sum << 16)) >> 16);
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-
-static inline __wsum
-csum_tcpudp_nofold(__be32 saddr, __be32 daddr, unsigned short len,
-                   unsigned short proto, __wsum sum)
-{
-
-        __asm__ ("%0 = %0 + %1;\n\t"
-                 "CC = AC0;\n\t"
-                 "if !CC jump 4;\n\t"
-                 "%0 = %0 + %4;\n\t"
-                 "%0 = %0 + %2;\n\t"
-                 "CC = AC0;\n\t"
-                 "if !CC jump 4;\n\t"
-                 "%0 = %0 + %4;\n\t"
-                 "%0 = %0 + %3;\n\t"
-                 "CC = AC0;\n\t"
-                 "if !CC jump 4;\n\t"
-                 "%0 = %0 + %4;\n\t"
-                 "NOP;\n\t"
-                 : "=d" (sum)
-                 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
-
-        return (sum);
-}
-
-static inline __sum16
-csum_tcpudp_magic(__be32 saddr, __be32 daddr, unsigned short len,
-                  unsigned short proto, __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-
-extern __sum16 ip_compute_csum(const void *buff, int len);
-
-#endif                          /* _BFIN_CHECKSUM_H */
diff --git a/include/asm-blackfin/cplb-mpu.h b/include/asm-blackfin/cplb-mpu.h
deleted file mode 100644
index 75c67b99d607..000000000000
--- a/include/asm-blackfin/cplb-mpu.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplbinit.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#ifndef __ASM_BFIN_CPLB_MPU_H
-#define __ASM_BFIN_CPLB_MPU_H
-
-struct cplb_entry {
-        unsigned long data, addr;
-};
-
-struct mem_region {
-        unsigned long start, end;
-        unsigned long dcplb_data;
-        unsigned long icplb_data;
-};
-
-extern struct cplb_entry dcplb_tbl[MAX_CPLBS];
-extern struct cplb_entry icplb_tbl[MAX_CPLBS];
-extern int first_switched_icplb;
-extern int first_mask_dcplb;
-extern int first_switched_dcplb;
-
-extern int nr_dcplb_miss, nr_icplb_miss, nr_icplb_supv_miss, nr_dcplb_prot;
-extern int nr_cplb_flush;
-
-extern int page_mask_order;
-extern int page_mask_nelts;
-
-extern unsigned long *current_rwx_mask;
-
-extern void flush_switched_cplbs(void);
-extern void set_mask_dcplbs(unsigned long *);
-
-extern void __noreturn panic_cplb_error(int seqstat, struct pt_regs *);
-
-#endif /* __ASM_BFIN_CPLB_MPU_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
deleted file mode 100644
index 5b0da9a69b67..000000000000
--- a/include/asm-blackfin/cplb.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplb.h
- * Based on:     include/asm-blackfin/mach-bf537/bf537.h
- * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
- *
- * Created:      2000
- * Description:  Common CPLB definitions for CPLB init
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _CPLB_H
-#define _CPLB_H
-
-#include <asm/blackfin.h>
-#include <asm/mach/anomaly.h>
-
-#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
-#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
-#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
-
-/*Use the menuconfig cache policy here - CONFIG_BFIN_WT/CONFIG_BFIN_WB*/
-
-#if ANOMALY_05000158
-#define ANOMALY_05000158_WORKAROUND             0x200
-#else
-#define ANOMALY_05000158_WORKAROUND             0x0
-#endif
-
-#define CPLB_COMMON     (CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#ifdef CONFIG_BFIN_WB         /*Write Back Policy */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_COMMON)
-#else                           /*Write Through */
-#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_COMMON)
-#endif
-
-#define L1_DMEMORY       (CPLB_LOCK | CPLB_COMMON)
-#define L2_MEMORY        (CPLB_COMMON)
-#define SDRAM_DNON_CHBL  (CPLB_COMMON)
-#define SDRAM_EBIU       (CPLB_COMMON)
-#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
-
-#define SIZE_1K 0x00000400      /* 1K */
-#define SIZE_4K 0x00001000      /* 4K */
-#define SIZE_1M 0x00100000      /* 1M */
-#define SIZE_4M 0x00400000      /* 4M */
-
-#ifdef CONFIG_MPU
-#define MAX_CPLBS 16
-#else
-#define MAX_CPLBS (16 * 2)
-#endif
-
-#define ASYNC_MEMORY_CPLB_COVERAGE      ((ASYNC_BANK0_SIZE + ASYNC_BANK1_SIZE + \
-                                 ASYNC_BANK2_SIZE + ASYNC_BANK3_SIZE) / SIZE_4M)
-
-#define CPLB_ENABLE_ICACHE_P    0
-#define CPLB_ENABLE_DCACHE_P    1
-#define CPLB_ENABLE_DCACHE2_P   2
-#define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P    4
-#define CPLB_ENABLE_DCPLBS_P    5
-
-#define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
-                                CPLB_ENABLE_ICPLBS | \
-                                CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED           0x0000
-#define CPLB_NO_UNLOCKED        0x0001
-#define CPLB_NO_ADDR_MATCH      0x0002
-#define CPLB_PROT_VIOL          0x0003
-#define CPLB_UNKNOWN_ERR        0x0004
-
-#define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
-
-#endif                          /* _CPLB_H */
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
deleted file mode 100644
index 0eb1c1b685a7..000000000000
--- a/include/asm-blackfin/cplbinit.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * File:         include/asm-blackfin/cplbinit.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __ASM_CPLBINIT_H__
-#define __ASM_CPLBINIT_H__
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-
-#ifdef CONFIG_MPU
-
-#include <asm/cplb-mpu.h>
-
-#else
-
-#define INITIAL_T 0x1
-#define SWITCH_T  0x2
-#define I_CPLB    0x4
-#define D_CPLB    0x8
-
-#define IN_KERNEL 1
-
-enum
-{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
-
-struct cplb_desc {
-        u32 start; /* start address */
-        u32 end; /* end address */
-        u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
-        u16 attr;/* attributes */
-        u16 i_conf;/* I-CPLB DATA */
-        u16 d_conf;/* D-CPLB DATA */
-        u16 valid;/* valid */
-        const s8 name[30];/* name */
-};
-
-struct cplb_tab {
-  u_long *tab;
-        u16 pos;
-        u16 size;
-};
-
-extern u_long icplb_table[];
-extern u_long dcplb_table[];
-
-/* Till here we are discussing about the static memory management model.
- * However, the operating envoronments commonly define more CPLB
- * descriptors to cover the entire addressable memory than will fit into
- * the available on-chip 16 CPLB MMRs. When this happens, the below table
- * will be used which will hold all the potentially required CPLB descriptors
- *
- * This is how Page descriptor Table is implemented in uClinux/Blackfin.
- */
-
-extern u_long ipdt_table[];
-extern u_long dpdt_table[];
-#ifdef CONFIG_CPLB_INFO
-extern u_long ipdt_swapcount_table[];
-extern u_long dpdt_swapcount_table[];
-#endif
-
-#endif /* CONFIG_MPU */
-
-extern unsigned long reserved_mem_dcache_on;
-extern unsigned long reserved_mem_icache_on;
-
-extern void generate_cpl_tables(void);
-
-#endif
diff --git a/include/asm-blackfin/cpumask.h b/include/asm-blackfin/cpumask.h
deleted file mode 100644
index b20a8e9012cb..000000000000
--- a/include/asm-blackfin/cpumask.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_BLACKFIN_CPUMASK_H
-#define _ASM_BLACKFIN_CPUMASK_H
-
-#include <asm-generic/cpumask.h>
-
-#endif                          /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/include/asm-blackfin/cputime.h b/include/asm-blackfin/cputime.h
deleted file mode 100644
index 2b19705f9885..000000000000
--- a/include/asm-blackfin/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BLACKFIN_CPUTIME_H
-#define __BLACKFIN_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif                          /* __BLACKFIN_CPUTIME_H */
diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
deleted file mode 100644
index 31918d29122c..000000000000
--- a/include/asm-blackfin/current.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef _BLACKFIN_CURRENT_H
-#define _BLACKFIN_CURRENT_H
-/*
- *      current.h
- *      (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
- *
- *      rather than dedicate a register (as the m68k source does), we
- *      just keep a global,  we should probably just change it all to be
- *      current and lose _current_task.
- */
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct *get_current(void) __attribute__ ((__const__));
-static inline struct task_struct *get_current(void)
-{
-        return (current_thread_info()->task);
-}
-
-#define current (get_current())
-
-#endif                          /* _BLACKFIN_CURRENT_H */
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
deleted file mode 100644
index 473a8113277f..000000000000
--- a/include/asm-blackfin/delay.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * delay.h - delay functions
- *
- * Copyright (c) 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_DELAY_H__
-#define __ASM_DELAY_H__
-
-#include <asm/mach/anomaly.h>
-
-static inline void __delay(unsigned long loops)
-{
-        if (ANOMALY_05000312) {
-                /* Interrupted loads to loop registers -> bad */
-                unsigned long tmp;
-                __asm__ __volatile__(
-                        "[--SP] = LC0;"
-                        "[--SP] = LT0;"
-                        "[--SP] = LB0;"
-                        "LSETUP (1f,1f) LC0 = %1;"
-                        "1: NOP;"
-                        /* We take advantage of the fact that LC0 is 0 at
-                         * the end of the loop.  Otherwise we'd need some
-                         * NOPs after the CLI here.
-                         */
-                        "CLI %0;"
-                        "LB0 = [SP++];"
-                        "LT0 = [SP++];"
-                        "LC0 = [SP++];"
-                        "STI %0;"
-                        : "=d" (tmp)
-                        : "a" (loops)
-                );
-        } else
-                __asm__ __volatile__ (
-                        "LSETUP(1f, 1f) LC0 = %0;"
-                        "1: NOP;"
-                        :
-                        : "a" (loops)
-                        : "LT0", "LB0", "LC0"
-                );
-}
-
-#include <linux/param.h>        /* needed for HZ */
-
-/*
- * Use only for very small delays ( < 1 msec).  Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays.  This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-static inline void udelay(unsigned long usecs)
-{
-        extern unsigned long loops_per_jiffy;
-        __delay(usecs * loops_per_jiffy / (1000000 / HZ));
-}
-
-#endif
diff --git a/include/asm-blackfin/device.h b/include/asm-blackfin/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-blackfin/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-blackfin/div64.h b/include/asm-blackfin/div64.h
deleted file mode 100644
index 6cd978cefb28..000000000000
--- a/include/asm-blackfin/div64.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/div64.h>
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
deleted file mode 100644
index 1a13c2fc3667..000000000000
--- a/include/asm-blackfin/dma-mapping.h
+++ /dev/null
@@ -1,83 +0,0 @@
-#ifndef _BLACKFIN_DMA_MAPPING_H
-#define _BLACKFIN_DMA_MAPPING_H
-
-#include <asm/scatterlist.h>
-
-void dma_alloc_init(unsigned long start, unsigned long end);
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                         dma_addr_t *dma_handle, gfp_t gfp);
-void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
-                       dma_addr_t dma_handle);
-
-/*
- * Now for the API extensions over the pci_ one
- */
-#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
-#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-#define dma_mapping_error
-
-/*
- * Map a single buffer of the indicated size for DMA in streaming mode.
- * The 32-bit bus address to use is returned.
- *
- * Once the device is given the dma address, the device owns this memory
- * until either pci_unmap_single or pci_dma_sync_single is performed.
- */
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-                                 enum dma_data_direction direction);
-
-static inline dma_addr_t
-dma_map_page(struct device *dev, struct page *page,
-             unsigned long offset, size_t size,
-             enum dma_data_direction dir)
-{
-        return dma_map_single(dev, page_address(page) + offset, size, dir);
-}
-
-/*
- * Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
-                          enum dma_data_direction direction);
-
-static inline void
-dma_unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
-               enum dma_data_direction dir)
-{
-        dma_unmap_single(dev, dma_addr, size, dir);
-}
-
-/*
- * Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-                      enum dma_data_direction direction);
-
-/*
- * Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-                      int nhwentries, enum dma_data_direction direction);
-
-#endif                          /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
deleted file mode 100644
index 3cd4b522aa3f..000000000000
--- a/include/asm-blackfin/dma.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * File:         include/asm-blackfin/simple_bf533_dma.h
- * Based on:     none - original work
- * Author:       LG Soft India
- *               Copyright (C) 2004-2005 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  This file contains the major Data structures and constants
- *               used for DMA Implementation in BF533
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <asm/io.h>
-#include <linux/slab.h>
-#include <asm/irq.h>
-#include <asm/signal.h>
-
-#include <linux/kernel.h>
-#include <asm/mach/dma.h>
-#include <linux/mm.h>
-#include <linux/interrupt.h>
-#include <asm/blackfin.h>
-
-#define MAX_DMA_ADDRESS PAGE_OFFSET
-
-/*****************************************************************************
-*        Generic DMA  Declarations
-*
-****************************************************************************/
-enum dma_chan_status {
-        DMA_CHANNEL_FREE,
-        DMA_CHANNEL_REQUESTED,
-        DMA_CHANNEL_ENABLED,
-};
-
-/*-------------------------
- * config reg bits value
- *-------------------------*/
-#define DATA_SIZE_8             0
-#define DATA_SIZE_16            1
-#define DATA_SIZE_32            2
-
-#define DMA_FLOW_STOP           0
-#define DMA_FLOW_AUTO           1
-#define DMA_FLOW_ARRAY          4
-#define DMA_FLOW_SMALL          6
-#define DMA_FLOW_LARGE          7
-
-#define DIMENSION_LINEAR    0
-#define DIMENSION_2D           1
-
-#define DIR_READ     0
-#define DIR_WRITE    1
-
-#define INTR_DISABLE   0
-#define INTR_ON_BUF    2
-#define INTR_ON_ROW    3
-
-#define DMA_NOSYNC_KEEP_DMA_BUF 0
-#define DMA_SYNC_RESTART        1
-
-struct dmasg {
-        unsigned long next_desc_addr;
-        unsigned long start_addr;
-        unsigned short cfg;
-        unsigned short x_count;
-        short x_modify;
-        unsigned short y_count;
-        short y_modify;
-} __attribute__((packed));
-
-struct dma_register {
-        unsigned long next_desc_ptr;    /* DMA Next Descriptor Pointer register */
-        unsigned long start_addr;       /* DMA Start address  register */
-
-        unsigned short cfg;     /* DMA Configuration register */
-        unsigned short dummy1;  /* DMA Configuration register */
-
-        unsigned long reserved;
-
-        unsigned short x_count; /* DMA x_count register */
-        unsigned short dummy2;
-
-        short x_modify; /* DMA x_modify register */
-        unsigned short dummy3;
-
-        unsigned short y_count; /* DMA y_count register */
-        unsigned short dummy4;
-
-        short y_modify; /* DMA y_modify register */
-        unsigned short dummy5;
-
-        unsigned long curr_desc_ptr;    /* DMA Current Descriptor Pointer
-                                           register */
-        unsigned long curr_addr_ptr;    /* DMA Current Address Pointer
-                                                   register */
-        unsigned short irq_status;      /* DMA irq status register */
-        unsigned short dummy6;
-
-        unsigned short peripheral_map;  /* DMA peripheral map register */
-        unsigned short dummy7;
-
-        unsigned short curr_x_count;    /* DMA Current x-count register */
-        unsigned short dummy8;
-
-        unsigned long reserved2;
-
-        unsigned short curr_y_count;    /* DMA Current y-count register */
-        unsigned short dummy9;
-
-        unsigned long reserved3;
-
-};
-
-typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
-
-struct dma_channel {
-        struct mutex dmalock;
-        char *device_id;
-        enum dma_chan_status chan_status;
-        struct dma_register *regs;
-        struct dmasg *sg;               /* large mode descriptor */
-        unsigned int ctrl_num;  /* controller number */
-        dma_interrupt_t irq_callback;
-        void *data;
-        unsigned int dma_enable_flag;
-        unsigned int loopback_flag;
-#ifdef CONFIG_PM
-        unsigned short saved_peripheral_map;
-#endif
-};
-
-#ifdef CONFIG_PM
-int blackfin_dma_suspend(void);
-void blackfin_dma_resume(void);
-#endif
-
-/*******************************************************************************
-*       DMA API's
-*******************************************************************************/
-/* functions to set register mode */
-void set_dma_start_addr(unsigned int channel, unsigned long addr);
-void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
-void set_dma_curr_desc_addr(unsigned int channel, unsigned long addr);
-void set_dma_x_count(unsigned int channel, unsigned short x_count);
-void set_dma_x_modify(unsigned int channel, short x_modify);
-void set_dma_y_count(unsigned int channel, unsigned short y_count);
-void set_dma_y_modify(unsigned int channel, short y_modify);
-void set_dma_config(unsigned int channel, unsigned short config);
-unsigned short set_bfin_dma_config(char direction, char flow_mode,
-                                   char intr_mode, char dma_mode, char width,
-                                   char syncmode);
-void set_dma_curr_addr(unsigned int channel, unsigned long addr);
-
-/* get curr status for polling */
-unsigned short get_dma_curr_irqstat(unsigned int channel);
-unsigned short get_dma_curr_xcount(unsigned int channel);
-unsigned short get_dma_curr_ycount(unsigned int channel);
-unsigned long get_dma_next_desc_ptr(unsigned int channel);
-unsigned long get_dma_curr_desc_ptr(unsigned int channel);
-unsigned long get_dma_curr_addr(unsigned int channel);
-
-/* set large DMA mode descriptor */
-void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
-
-/* check if current channel is in use */
-int dma_channel_active(unsigned int channel);
-
-/* common functions must be called in any mode */
-void free_dma(unsigned int channel);
-int dma_channel_active(unsigned int channel); /* check if a channel is in use */
-void disable_dma(unsigned int channel);
-void enable_dma(unsigned int channel);
-int request_dma(unsigned int channel, char *device_id);
-int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
-                     void *data);
-void dma_disable_irq(unsigned int channel);
-void dma_enable_irq(unsigned int channel);
-void clear_dma_irqstat(unsigned int channel);
-void *dma_memcpy(void *dest, const void *src, size_t count);
-void *safe_dma_memcpy(void *dest, const void *src, size_t count);
-
-extern int channel2irq(unsigned int channel);
-extern struct dma_register *dma_io_base_addr[MAX_BLACKFIN_DMA_CHANNEL];
-
-#endif
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
deleted file mode 100644
index 96e8208f929a..000000000000
--- a/include/asm-blackfin/dpmc.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * include/asm-blackfin/dpmc.h -  Miscellaneous IOCTL commands for Dynamic Power
- *                              Management Controller Driver.
- * Copyright (C) 2004-2008 Analog Device Inc.
- *
- */
-#ifndef _BLACKFIN_DPMC_H_
-#define _BLACKFIN_DPMC_H_
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-
-void sleep_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void hibernate_mode(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void sleep_deeper(u32 sic_iwr0, u32 sic_iwr1, u32 sic_iwr2);
-void do_hibernate(int wakeup);
-void set_dram_srfs(void);
-void unset_dram_srfs(void);
-
-#define VRPAIR(vlev, freq) (((vlev) << 16) | ((freq) >> 16))
-
-struct bfin_dpmc_platform_data {
-        const unsigned int *tuple_tab;
-        unsigned short tabsize;
-        unsigned short vr_settling_time; /* in us */
-};
-
-#else
-
-#define PM_PUSH(x) \
-        R0 = [P0 + (x - SRAM_BASE_ADDRESS)];\
-        [--SP] =  R0;\
-
-#define PM_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - SRAM_BASE_ADDRESS)] = R0;\
-
-#define PM_SYS_PUSH(x) \
-        R0 = [P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-
-#define PM_SYS_POP(x) \
-        R0 = [SP++];\
-        [P0 + (x - PLL_CTL)] = R0;\
-
-#define PM_SYS_PUSH16(x) \
-        R0 = w[P0 + (x - PLL_CTL)];\
-        [--SP] =  R0;\
-
-#define PM_SYS_POP16(x) \
-        R0 = [SP++];\
-        w[P0 + (x - PLL_CTL)] = R0;\
-
-#endif
-#endif  /* __KERNEL__ */
-
-#endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/early_printk.h b/include/asm-blackfin/early_printk.h
deleted file mode 100644
index 110f1c1f845c..000000000000
--- a/include/asm-blackfin/early_printk.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * File:         include/asm-blackfin/early_printk.h
- * Author:       Robin Getz <rgetz@blackfin.uclinux.org
- *
- * Created:      14Aug2007
- * Description:  function prototpyes for early printk
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifdef CONFIG_EARLY_PRINTK
-extern int setup_early_printk(char *);
-#else
-#define setup_early_printk(fmt) do { } while (0)
-#endif /* CONFIG_EARLY_PRINTK */
diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h
deleted file mode 100644
index 67a03a8a353e..000000000000
--- a/include/asm-blackfin/elf.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/* Changes made by  LG Soft Oct 2004*/
-
-#ifndef __ASMBFIN_ELF_H
-#define __ASMBFIN_ELF_H
-
-/*
- * ELF register definitions..
- */
-
-#include <asm/ptrace.h>
-#include <asm/user.h>
-
-/* Processor specific flags for the ELF header e_flags field.  */
-#define EF_BFIN_PIC             0x00000001      /* -fpic */
-#define EF_BFIN_FDPIC           0x00000002      /* -mfdpic */
-#define EF_BFIN_CODE_IN_L1      0x00000010      /* --code-in-l1 */
-#define EF_BFIN_DATA_IN_L1      0x00000020      /* --data-in-l1 */
-#define EF_BFIN_CODE_IN_L2      0x00000040      /* --code-in-l2 */
-#define EF_BFIN_DATA_IN_L2      0x00000080      /* --data-in-l2 */
-
-typedef unsigned long elf_greg_t;
-
-#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef struct user_bfinfp_struct elf_fpregset_t;
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
-
-#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
-#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
-
-/* EM_BLACKFIN defined in linux/elf.h   */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-#define ELF_DATA        ELFDATA2LSB
-#define ELF_ARCH        EM_BLACKFIN
-
-#define ELF_PLAT_INIT(_r)       _r->p1 = 0
-
-#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr)     \
-do {                                                                                    \
-        _regs->r7       = 0;                                            \
-        _regs->p0       = _exec_map_addr;                               \
-        _regs->p1       = _interp_map_addr;                             \
-        _regs->p2       = _dynamic_addr;                                \
-} while(0)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_FDPIC_CORE_EFLAGS   EF_BFIN_FDPIC
-#define ELF_EXEC_PAGESIZE       4096
-
-#define R_unused0       0       /* relocation type 0 is not defined */
-#define R_pcrel5m2      1       /*LSETUP part a */
-#define R_unused1       2       /* relocation type 2 is not defined */
-#define R_pcrel10       3       /* type 3, if cc jump <target>  */
-#define R_pcrel12_jump  4       /* type 4, jump <target> */
-#define R_rimm16        5       /* type 0x5, rN = <target> */
-#define R_luimm16       6       /* # 0x6, preg.l=<target> Load imm 16 to lower half */
-#define R_huimm16       7       /* # 0x7, preg.h=<target> Load imm 16 to upper half */
-#define R_pcrel12_jump_s 8      /* # 0x8 jump.s <target> */
-#define R_pcrel24_jump_x 9      /* # 0x9 jump.x <target> */
-#define R_pcrel24       10      /* # 0xa call <target> , not expandable */
-#define R_unusedb       11      /* # 0xb not generated */
-#define R_unusedc       12      /* # 0xc  not used */
-#define R_pcrel24_jump_l 13     /*0xd jump.l <target> */
-#define R_pcrel24_call_x 14     /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
-#define R_var_eq_symb    15     /* 0xf, linker should treat it same as 0x12 */
-#define R_byte_data      16     /* 0x10, .byte var = symbol */
-#define R_byte2_data     17     /* 0x11, .byte2 var = symbol */
-#define R_byte4_data     18     /* 0x12, .byte4 var = symbol and .var var=symbol */
-#define R_pcrel11        19     /* 0x13, lsetup part b */
-#define R_unused14      20      /* 0x14, undefined */
-#define R_unused15       21     /* not generated by VDSP 3.5 */
-
-/* arithmetic relocations */
-#define R_push           0xE0
-#define R_const          0xE1
-#define R_add            0xE2
-#define R_sub            0xE3
-#define R_mult           0xE4
-#define R_div            0xE5
-#define R_mod            0xE6
-#define R_lshift         0xE7
-#define R_rshift         0xE8
-#define R_and            0xE9
-#define R_or             0xEA
-#define R_xor            0xEB
-#define R_land           0xEC
-#define R_lor            0xED
-#define R_len            0xEE
-#define R_neg            0xEF
-#define R_comp           0xF0
-#define R_page           0xF1
-#define R_hwpage         0xF2
-#define R_addr           0xF3
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#define ELF_ET_DYN_BASE         0xD0000000UL
-
-#define ELF_CORE_COPY_REGS(pr_reg, regs)        \
-        memcpy((char *) &pr_reg, (char *)regs,  \
-               sizeof(struct pt_regs));
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  */
-
-#define ELF_HWCAP       (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.  */
-
-#define ELF_PLATFORM  (NULL)
-
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
-
-#endif
diff --git a/include/asm-blackfin/emergency-restart.h b/include/asm-blackfin/emergency-restart.h
deleted file mode 100644
index 27f6c785d103..000000000000
--- a/include/asm-blackfin/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif                          /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
deleted file mode 100644
index c4f721e0d00d..000000000000
--- a/include/asm-blackfin/entry.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __BFIN_ENTRY_H
-#define __BFIN_ENTRY_H
-
-#include <asm/setup.h>
-#include <asm/page.h>
-
-#ifdef __ASSEMBLY__
-
-#define LFLUSH_I_AND_D  0x00000808
-#define LSIGTRAP        5
-
-/* process bits for task_struct.flags */
-#define PF_TRACESYS_OFF 3
-#define PF_TRACESYS_BIT 5
-#define PF_PTRACED_OFF  3
-#define PF_PTRACED_BIT  4
-#define PF_DTRACE_OFF   1
-#define PF_DTRACE_BIT   5
-
-/*
- * NOTE!  The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/* This one is used for exceptions, emulation, and NMI.  It doesn't push
-   RETI and doesn't do cli.  */
-#define SAVE_ALL_SYS            save_context_no_interrupts
-/* This is used for all normal interrupts.  It saves a minimum of registers
-   to the stack, loads the IRQ number, and jumps to common code.  */
-#define INTERRUPT_ENTRY(N)                                              \
-    [--sp] = SYSCFG;                                                    \
-                                                                        \
-    [--sp] = P0;        /*orig_p0*/                                     \
-    [--sp] = R0;        /*orig_r0*/                                     \
-    [--sp] = (R7:0,P5:0);                                               \
-    R0 = (N);                                                           \
-    jump __common_int_entry;
-
-/* For timer interrupts, we need to save IPEND, since the user_mode
-           macro accesses it to determine where to account time.  */
-#define TIMER_INTERRUPT_ENTRY(N)                                        \
-    [--sp] = SYSCFG;                                                    \
-                                                                        \
-    [--sp] = P0;        /*orig_p0*/                                     \
-    [--sp] = R0;        /*orig_r0*/                                     \
-    [--sp] = (R7:0,P5:0);                                               \
-    p0.l = lo(IPEND);                                                   \
-    p0.h = hi(IPEND);                                                   \
-    r1 = [p0];                                                          \
-    R0 = (N);                                                           \
-    jump __common_int_entry;
-
-/* This one pushes RETI without using CLI.  Interrupts are enabled.  */
-#define SAVE_CONTEXT_SYSCALL    save_context_syscall
-#define SAVE_CONTEXT            save_context_with_interrupts
-
-#define RESTORE_ALL_SYS         restore_context_no_interrupts
-#define RESTORE_CONTEXT         restore_context_with_interrupts
-
-#endif                          /* __ASSEMBLY__ */
-#endif                          /* __BFIN_ENTRY_H */
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
deleted file mode 100644
index 164e4f39bb57..000000000000
--- a/include/asm-blackfin/errno.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_ERRNO_H
-#define _BFIN_ERRNO_H
-
-#include<asm-generic/errno.h>
-
-#endif                          /* _BFIN_ERRNO_H */
diff --git a/include/asm-blackfin/fb.h b/include/asm-blackfin/fb.h
deleted file mode 100644
index c7df38030992..000000000000
--- a/include/asm-blackfin/fb.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-#include <linux/fb.h>
-
-#define fb_pgprotect(...) do {} while (0)
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-        return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-blackfin/fcntl.h b/include/asm-blackfin/fcntl.h
deleted file mode 100644
index 9c4037127857..000000000000
--- a/include/asm-blackfin/fcntl.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _BFIN_FCNTL_H
-#define _BFIN_FCNTL_H
-
-/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
-   located on an ext2 file system */
-#define O_DIRECTORY      040000 /* must be a directory */
-#define O_NOFOLLOW      0100000 /* don't follow links */
-#define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
-#define O_LARGEFILE     0400000
-
-#include <asm-generic/fcntl.h>
-
-#endif
diff --git a/include/asm-blackfin/fixed_code.h b/include/asm-blackfin/fixed_code.h
deleted file mode 100644
index 32c4d495d847..000000000000
--- a/include/asm-blackfin/fixed_code.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/* This file defines the fixed addresses where userspace programs can find
-   atomic code sequences.  */
-
-#ifndef __BFIN_ASM_FIXED_CODE_H__
-#define __BFIN_ASM_FIXED_CODE_H__
-
-#ifdef __KERNEL__
-#ifndef __ASSEMBLY__
-#include <linux/linkage.h>
-#include <linux/ptrace.h>
-extern asmlinkage void finish_atomic_sections(struct pt_regs *regs);
-extern char fixed_code_start;
-extern char fixed_code_end;
-extern int atomic_xchg32(void);
-extern int atomic_cas32(void);
-extern int atomic_add32(void);
-extern int atomic_sub32(void);
-extern int atomic_ior32(void);
-extern int atomic_and32(void);
-extern int atomic_xor32(void);
-extern void safe_user_instruction(void);
-extern void sigreturn_stub(void);
-#endif
-#endif
-
-#define FIXED_CODE_START        0x400
-
-#define SIGRETURN_STUB          0x400
-
-#define ATOMIC_SEQS_START       0x410
-
-#define ATOMIC_XCHG32           0x410
-#define ATOMIC_CAS32            0x420
-#define ATOMIC_ADD32            0x430
-#define ATOMIC_SUB32            0x440
-#define ATOMIC_IOR32            0x450
-#define ATOMIC_AND32            0x460
-#define ATOMIC_XOR32            0x470
-
-#define ATOMIC_SEQS_END         0x480
-
-#define SAFE_USER_INSTRUCTION   0x480
-
-#define FIXED_CODE_END          0x490
-
-#endif
diff --git a/include/asm-blackfin/flat.h b/include/asm-blackfin/flat.h
deleted file mode 100644
index e70074e05f4e..000000000000
--- a/include/asm-blackfin/flat.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * include/asm-blackfin/flat.h -- uClinux flat-format executables
- *
- * Copyright (C) 2003,
- *
- */
-
-#ifndef __BLACKFIN_FLAT_H__
-#define __BLACKFIN_FLAT_H__
-
-#include <asm/unaligned.h>
-
-#define flat_stack_align(sp)    /* nothing needed */
-#define flat_argvp_envp_on_stack()              0
-#define flat_old_ram_flag(flags)                (flags)
-
-extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr,
-                                        unsigned long relval,
-                                        unsigned long flags,
-                                        unsigned long *persistent);
-
-extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
-                                unsigned long relval);
-
-/* The amount by which a relocation can exceed the program image limits
-   without being regarded as an error.  */
-
-#define flat_reloc_valid(reloc, size)   ((reloc) <= (size))
-
-#define flat_get_addr_from_rp(rp, relval, flags, persistent)    \
-        bfin_get_addr_from_rp(rp, relval, flags, persistent)
-#define flat_put_addr_at_rp(rp, val, relval)    \
-        bfin_put_addr_at_rp(rp, val, relval)
-
-/* Convert a relocation entry into an address.  */
-static inline unsigned long
-flat_get_relocate_addr (unsigned long relval)
-{
-        return relval & 0x03ffffff; /* Mask out top 6 bits */
-}
-
-static inline int flat_set_persistent(unsigned long relval,
-                                      unsigned long *persistent)
-{
-        int type = (relval >> 26) & 7;
-        if (type == 3) {
-                *persistent = relval << 16;
-                return 1;
-        }
-        return 0;
-}
-
-static inline int flat_addr_absolute(unsigned long relval)
-{
-        return (relval & (1 << 29)) != 0;
-}
-
-#endif                          /* __BLACKFIN_FLAT_H__ */
diff --git a/include/asm-blackfin/futex.h b/include/asm-blackfin/futex.h
deleted file mode 100644
index 6a332a9f099c..000000000000
--- a/include/asm-blackfin/futex.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#include <asm-generic/futex.h>
-
-#endif
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
deleted file mode 100644
index 168f1251eb4d..000000000000
--- a/include/asm-blackfin/gpio.h
+++ /dev/null
@@ -1,456 +0,0 @@
-/*
- * File:         arch/blackfin/kernel/bfin_gpio.h
- * Based on:
- * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2008 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-/*
-*  Number     BF537/6/4    BF561    BF533/2/1
-*             BF527/5/2
-*
-*  GPIO_0       PF0         PF0        PF0
-*  GPIO_1       PF1         PF1        PF1
-*  GPIO_2       PF2         PF2        PF2
-*  GPIO_3       PF3         PF3        PF3
-*  GPIO_4       PF4         PF4        PF4
-*  GPIO_5       PF5         PF5        PF5
-*  GPIO_6       PF6         PF6        PF6
-*  GPIO_7       PF7         PF7        PF7
-*  GPIO_8       PF8         PF8        PF8
-*  GPIO_9       PF9         PF9        PF9
-*  GPIO_10      PF10        PF10       PF10
-*  GPIO_11      PF11        PF11       PF11
-*  GPIO_12      PF12        PF12       PF12
-*  GPIO_13      PF13        PF13       PF13
-*  GPIO_14      PF14        PF14       PF14
-*  GPIO_15      PF15        PF15       PF15
-*  GPIO_16      PG0         PF16
-*  GPIO_17      PG1         PF17
-*  GPIO_18      PG2         PF18
-*  GPIO_19      PG3         PF19
-*  GPIO_20      PG4         PF20
-*  GPIO_21      PG5         PF21
-*  GPIO_22      PG6         PF22
-*  GPIO_23      PG7         PF23
-*  GPIO_24      PG8         PF24
-*  GPIO_25      PG9         PF25
-*  GPIO_26      PG10        PF26
-*  GPIO_27      PG11        PF27
-*  GPIO_28      PG12        PF28
-*  GPIO_29      PG13        PF29
-*  GPIO_30      PG14        PF30
-*  GPIO_31      PG15        PF31
-*  GPIO_32      PH0         PF32
-*  GPIO_33      PH1         PF33
-*  GPIO_34      PH2         PF34
-*  GPIO_35      PH3         PF35
-*  GPIO_36      PH4         PF36
-*  GPIO_37      PH5         PF37
-*  GPIO_38      PH6         PF38
-*  GPIO_39      PH7         PF39
-*  GPIO_40      PH8         PF40
-*  GPIO_41      PH9         PF41
-*  GPIO_42      PH10        PF42
-*  GPIO_43      PH11        PF43
-*  GPIO_44      PH12        PF44
-*  GPIO_45      PH13        PF45
-*  GPIO_46      PH14        PF46
-*  GPIO_47      PH15        PF47
-*/
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#define gpio_bank(x) ((x) >> 4)
-#define gpio_bit(x)  (1<<((x) & 0xF))
-#define gpio_sub_n(x) ((x) & 0xF)
-
-#define GPIO_BANKSIZE 16
-
-#define GPIO_0  0
-#define GPIO_1  1
-#define GPIO_2  2
-#define GPIO_3  3
-#define GPIO_4  4
-#define GPIO_5  5
-#define GPIO_6  6
-#define GPIO_7  7
-#define GPIO_8  8
-#define GPIO_9  9
-#define GPIO_10 10
-#define GPIO_11 11
-#define GPIO_12 12
-#define GPIO_13 13
-#define GPIO_14 14
-#define GPIO_15 15
-#define GPIO_16 16
-#define GPIO_17 17
-#define GPIO_18 18
-#define GPIO_19 19
-#define GPIO_20 20
-#define GPIO_21 21
-#define GPIO_22 22
-#define GPIO_23 23
-#define GPIO_24 24
-#define GPIO_25 25
-#define GPIO_26 26
-#define GPIO_27 27
-#define GPIO_28 28
-#define GPIO_29 29
-#define GPIO_30 30
-#define GPIO_31 31
-#define GPIO_32 32
-#define GPIO_33 33
-#define GPIO_34 34
-#define GPIO_35 35
-#define GPIO_36 36
-#define GPIO_37 37
-#define GPIO_38 38
-#define GPIO_39 39
-#define GPIO_40 40
-#define GPIO_41 41
-#define GPIO_42 42
-#define GPIO_43 43
-#define GPIO_44 44
-#define GPIO_45 45
-#define GPIO_46 46
-#define GPIO_47 47
-
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-
-#ifdef BF533_FAMILY
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-
-#endif
-
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PG0        16
-#define GPIO_PG1        17
-#define GPIO_PG2        18
-#define GPIO_PG3        19
-#define GPIO_PG4        20
-#define GPIO_PG5        21
-#define GPIO_PG6        22
-#define GPIO_PG7        23
-#define GPIO_PG8        24
-#define GPIO_PG9        25
-#define GPIO_PG10       26
-#define GPIO_PG11       27
-#define GPIO_PG12       28
-#define GPIO_PG13       29
-#define GPIO_PG14       30
-#define GPIO_PG15       31
-#define GPIO_PH0        32
-#define GPIO_PH1        33
-#define GPIO_PH2        34
-#define GPIO_PH3        35
-#define GPIO_PH4        36
-#define GPIO_PH5        37
-#define GPIO_PH6        38
-#define GPIO_PH7        39
-#define GPIO_PH8        40
-#define GPIO_PH9        41
-#define GPIO_PH10       42
-#define GPIO_PH11       43
-#define GPIO_PH12       44
-#define GPIO_PH13       45
-#define GPIO_PH14       46
-#define GPIO_PH15       47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif
-
-#ifdef BF548_FAMILY
-#include <asm-blackfin/mach-bf548/gpio.h>
-#endif
-
-#ifdef BF561_FAMILY
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0        0
-#define GPIO_PF1        1
-#define GPIO_PF2        2
-#define GPIO_PF3        3
-#define GPIO_PF4        4
-#define GPIO_PF5        5
-#define GPIO_PF6        6
-#define GPIO_PF7        7
-#define GPIO_PF8        8
-#define GPIO_PF9        9
-#define GPIO_PF10       10
-#define GPIO_PF11       11
-#define GPIO_PF12       12
-#define GPIO_PF13       13
-#define GPIO_PF14       14
-#define GPIO_PF15       15
-#define GPIO_PF16       16
-#define GPIO_PF17       17
-#define GPIO_PF18       18
-#define GPIO_PF19       19
-#define GPIO_PF20       20
-#define GPIO_PF21       21
-#define GPIO_PF22       22
-#define GPIO_PF23       23
-#define GPIO_PF24       24
-#define GPIO_PF25       25
-#define GPIO_PF26       26
-#define GPIO_PF27       27
-#define GPIO_PF28       28
-#define GPIO_PF29       29
-#define GPIO_PF30       30
-#define GPIO_PF31       31
-#define GPIO_PF32       32
-#define GPIO_PF33       33
-#define GPIO_PF34       34
-#define GPIO_PF35       35
-#define GPIO_PF36       36
-#define GPIO_PF37       37
-#define GPIO_PF38       38
-#define GPIO_PF39       39
-#define GPIO_PF40       40
-#define GPIO_PF41       41
-#define GPIO_PF42       42
-#define GPIO_PF43       43
-#define GPIO_PF44       44
-#define GPIO_PF45       45
-#define GPIO_PF46       46
-#define GPIO_PF47       47
-
-#define PORT_FIO0 GPIO_0
-#define PORT_FIO1 GPIO_16
-#define PORT_FIO2 GPIO_32
-#endif
-
-#ifndef __ASSEMBLY__
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-*              to Blackfin processor General Purpose
-*              Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-#ifndef BF548_FAMILY
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
-        unsigned short data;
-        unsigned short dummy1;
-        unsigned short data_clear;
-        unsigned short dummy2;
-        unsigned short data_set;
-        unsigned short dummy3;
-        unsigned short toggle;
-        unsigned short dummy4;
-        unsigned short maska;
-        unsigned short dummy5;
-        unsigned short maska_clear;
-        unsigned short dummy6;
-        unsigned short maska_set;
-        unsigned short dummy7;
-        unsigned short maska_toggle;
-        unsigned short dummy8;
-        unsigned short maskb;
-        unsigned short dummy9;
-        unsigned short maskb_clear;
-        unsigned short dummy10;
-        unsigned short maskb_set;
-        unsigned short dummy11;
-        unsigned short maskb_toggle;
-        unsigned short dummy12;
-        unsigned short dir;
-        unsigned short dummy13;
-        unsigned short polar;
-        unsigned short dummy14;
-        unsigned short edge;
-        unsigned short dummy15;
-        unsigned short both;
-        unsigned short dummy16;
-        unsigned short inen;
-};
-#endif
-
-#ifdef CONFIG_PM
-
-unsigned int bfin_pm_standby_setup(void);
-void bfin_pm_standby_restore(void);
-
-void bfin_gpio_pm_hibernate_restore(void);
-void bfin_gpio_pm_hibernate_suspend(void);
-
-#ifndef CONFIG_BF54x
-#define PM_WAKE_RISING  0x1
-#define PM_WAKE_FALLING 0x2
-#define PM_WAKE_HIGH    0x4
-#define PM_WAKE_LOW     0x8
-#define PM_WAKE_BOTH_EDGES      (PM_WAKE_RISING | PM_WAKE_FALLING)
-#define PM_WAKE_IGNORE  0xF0
-
-int gpio_pm_wakeup_request(unsigned gpio, unsigned char type);
-void gpio_pm_wakeup_free(unsigned gpio);
-
-struct gpio_port_s {
-        unsigned short data;
-        unsigned short maska;
-        unsigned short maskb;
-        unsigned short dir;
-        unsigned short polar;
-        unsigned short edge;
-        unsigned short both;
-        unsigned short inen;
-
-        unsigned short fer;
-        unsigned short reserved;
-        unsigned short mux;
-};
-#endif /*CONFIG_BF54x*/
-#endif /*CONFIG_PM*/
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int gpio_request(unsigned, const char *);
-void gpio_free(unsigned);
-
-void gpio_set_value(unsigned gpio, int arg);
-int gpio_get_value(unsigned gpio);
-
-#ifndef BF548_FAMILY
-#define gpio_set_value(gpio, value)     set_gpio_data(gpio, value)
-#endif
-
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-#include <asm/irq.h>
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return (gpio + GPIO_IRQ_BASE);
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return (irq - GPIO_IRQ_BASE);
-}
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/include/asm-blackfin/gptimers.h b/include/asm-blackfin/gptimers.h
deleted file mode 100644
index 0520d2aac8f3..000000000000
--- a/include/asm-blackfin/gptimers.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * gptimers.h - Blackfin General Purpose Timer structs/defines/prototypes
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- * Copyright (C) 2005 John DeHority
- * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
- *
- * Licensed under the GPL-2.
- */
-
-#ifndef _BLACKFIN_TIMERS_H_
-#define _BLACKFIN_TIMERS_H_
-
-#include <linux/types.h>
-#include <asm/blackfin.h>
-
-/*
- * BF537/BF527: 8 timers:
- */
-#if defined(BF527_FAMILY) || defined(BF537_FAMILY)
-# define MAX_BLACKFIN_GPTIMERS 8
-# define TIMER0_GROUP_REG      TIMER_ENABLE
-#endif
-/*
- * BF54x: 11 timers (BF542: 8 timers):
- */
-#if defined(BF548_FAMILY)
-# ifdef CONFIG_BF542
-#  define MAX_BLACKFIN_GPTIMERS 8
-# else
-#  define MAX_BLACKFIN_GPTIMERS 11
-#  define TIMER8_GROUP_REG      TIMER_ENABLE1
-# endif
-# define TIMER0_GROUP_REG       TIMER_ENABLE0
-#endif
-/*
- * BF561: 12 timers:
- */
-#if defined(CONFIG_BF561)
-# define MAX_BLACKFIN_GPTIMERS 12
-# define TIMER0_GROUP_REG      TMRS8_ENABLE
-# define TIMER8_GROUP_REG      TMRS4_ENABLE
-#endif
-/*
- * All others: 3 timers:
- */
-#if !defined(MAX_BLACKFIN_GPTIMERS)
-# define MAX_BLACKFIN_GPTIMERS 3
-# define TIMER0_GROUP_REG      TIMER_ENABLE
-#endif
-
-#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
-#define BFIN_TIMER_OCTET(x) ((x) >> 3)
-
-/* used in masks for timer_enable() and timer_disable() */
-#define TIMER0bit  0x0001  /*  0001b */
-#define TIMER1bit  0x0002  /*  0010b */
-#define TIMER2bit  0x0004  /*  0100b */
-#define TIMER3bit  0x0008
-#define TIMER4bit  0x0010
-#define TIMER5bit  0x0020
-#define TIMER6bit  0x0040
-#define TIMER7bit  0x0080
-#define TIMER8bit  0x0100
-#define TIMER9bit  0x0200
-#define TIMER10bit 0x0400
-#define TIMER11bit 0x0800
-
-#define TIMER0_id   0
-#define TIMER1_id   1
-#define TIMER2_id   2
-#define TIMER3_id   3
-#define TIMER4_id   4
-#define TIMER5_id   5
-#define TIMER6_id   6
-#define TIMER7_id   7
-#define TIMER8_id   8
-#define TIMER9_id   9
-#define TIMER10_id 10
-#define TIMER11_id 11
-
-/* associated timers for ppi framesync: */
-
-#if defined(CONFIG_BF561)
-# define FS0_1_TIMER_ID   TIMER8_id
-# define FS0_2_TIMER_ID   TIMER9_id
-# define FS1_1_TIMER_ID   TIMER10_id
-# define FS1_2_TIMER_ID   TIMER11_id
-# define FS0_1_TIMER_BIT  TIMER8bit
-# define FS0_2_TIMER_BIT  TIMER9bit
-# define FS1_1_TIMER_BIT  TIMER10bit
-# define FS1_2_TIMER_BIT  TIMER11bit
-# undef FS1_TIMER_ID
-# undef FS2_TIMER_ID
-# undef FS1_TIMER_BIT
-# undef FS2_TIMER_BIT
-#else
-# define FS1_TIMER_ID  TIMER0_id
-# define FS2_TIMER_ID  TIMER1_id
-# define FS1_TIMER_BIT TIMER0bit
-# define FS2_TIMER_BIT TIMER1bit
-#endif
-
-/*
- * Timer Configuration Register Bits
- */
-#define TIMER_ERR           0xC000
-#define TIMER_ERR_OVFL      0x4000
-#define TIMER_ERR_PROG_PER  0x8000
-#define TIMER_ERR_PROG_PW   0xC000
-#define TIMER_EMU_RUN       0x0200
-#define TIMER_TOGGLE_HI     0x0100
-#define TIMER_CLK_SEL       0x0080
-#define TIMER_OUT_DIS       0x0040
-#define TIMER_TIN_SEL       0x0020
-#define TIMER_IRQ_ENA       0x0010
-#define TIMER_PERIOD_CNT    0x0008
-#define TIMER_PULSE_HI      0x0004
-#define TIMER_MODE          0x0003
-#define TIMER_MODE_PWM      0x0001
-#define TIMER_MODE_WDTH     0x0002
-#define TIMER_MODE_EXT_CLK  0x0003
-
-/*
- * Timer Status Register Bits
- */
-#define TIMER_STATUS_TIMIL0  0x0001
-#define TIMER_STATUS_TIMIL1  0x0002
-#define TIMER_STATUS_TIMIL2  0x0004
-#define TIMER_STATUS_TIMIL3  0x00000008
-#define TIMER_STATUS_TIMIL4  0x00010000
-#define TIMER_STATUS_TIMIL5  0x00020000
-#define TIMER_STATUS_TIMIL6  0x00040000
-#define TIMER_STATUS_TIMIL7  0x00080000
-#define TIMER_STATUS_TIMIL8  0x0001
-#define TIMER_STATUS_TIMIL9  0x0002
-#define TIMER_STATUS_TIMIL10 0x0004
-#define TIMER_STATUS_TIMIL11 0x0008
-
-#define TIMER_STATUS_TOVF0   0x0010     /* timer 0 overflow error */
-#define TIMER_STATUS_TOVF1   0x0020
-#define TIMER_STATUS_TOVF2   0x0040
-#define TIMER_STATUS_TOVF3   0x00000080
-#define TIMER_STATUS_TOVF4   0x00100000
-#define TIMER_STATUS_TOVF5   0x00200000
-#define TIMER_STATUS_TOVF6   0x00400000
-#define TIMER_STATUS_TOVF7   0x00800000
-#define TIMER_STATUS_TOVF8   0x0010
-#define TIMER_STATUS_TOVF9   0x0020
-#define TIMER_STATUS_TOVF10  0x0040
-#define TIMER_STATUS_TOVF11  0x0080
-
-/*
- * Timer Slave Enable Status : write 1 to clear
- */
-#define TIMER_STATUS_TRUN0  0x1000
-#define TIMER_STATUS_TRUN1  0x2000
-#define TIMER_STATUS_TRUN2  0x4000
-#define TIMER_STATUS_TRUN3  0x00008000
-#define TIMER_STATUS_TRUN4  0x10000000
-#define TIMER_STATUS_TRUN5  0x20000000
-#define TIMER_STATUS_TRUN6  0x40000000
-#define TIMER_STATUS_TRUN7  0x80000000
-#define TIMER_STATUS_TRUN   0xF000F000
-#define TIMER_STATUS_TRUN8  0x1000
-#define TIMER_STATUS_TRUN9  0x2000
-#define TIMER_STATUS_TRUN10 0x4000
-#define TIMER_STATUS_TRUN11 0x8000
-
-/* The actual gptimer API */
-
-void     set_gptimer_pwidth    (int timer_id, uint32_t width);
-uint32_t get_gptimer_pwidth    (int timer_id);
-void     set_gptimer_period    (int timer_id, uint32_t period);
-uint32_t get_gptimer_period    (int timer_id);
-uint32_t get_gptimer_count     (int timer_id);
-uint16_t get_gptimer_intr      (int timer_id);
-void     clear_gptimer_intr    (int timer_id);
-uint16_t get_gptimer_over      (int timer_id);
-void     clear_gptimer_over    (int timer_id);
-void     set_gptimer_config    (int timer_id, uint16_t config);
-uint16_t get_gptimer_config    (int timer_id);
-void     set_gptimer_pulse_hi  (int timer_id);
-void     clear_gptimer_pulse_hi(int timer_id);
-void     enable_gptimers       (uint16_t mask);
-void     disable_gptimers      (uint16_t mask);
-uint16_t get_enabled_gptimers  (void);
-uint32_t get_gptimer_status    (int group);
-void     set_gptimer_status    (int group, uint32_t value);
-
-#endif
diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h
deleted file mode 100644
index b6b19f1b9dab..000000000000
--- a/include/asm-blackfin/hardirq.h
+++ /dev/null
@@ -1,45 +0,0 @@
-#ifndef __BFIN_HARDIRQ_H
-#define __BFIN_HARDIRQ_H
-
-#include <linux/cache.h>
-#include <linux/threads.h>
-#include <asm/irq.h>
-
-typedef struct {
-        unsigned int __softirq_pending;
-        unsigned int __syscall_count;
-        struct task_struct *__ksoftirqd_task;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-/*
- * We put the hardirq and softirq counter into the preemption
- * counter. The bitmask has the following meaning:
- *
- * - bits 0-7 are the preemption count (max preemption depth: 256)
- * - bits 8-15 are the softirq count (max # of softirqs: 256)
- * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
- *
- * - ( bit 26 is the PREEMPT_ACTIVE flag. )
- *
- * PREEMPT_MASK: 0x000000ff
- * HARDIRQ_MASK: 0x0000ff00
- * SOFTIRQ_MASK: 0x00ff0000
- */
-
-#if NR_IRQS > 256
-#define HARDIRQ_BITS    9
-#else
-#define HARDIRQ_BITS    8
-#endif
-
-#ifdef NR_IRQS
-# if (1 << HARDIRQ_BITS) < NR_IRQS
-# error HARDIRQ_BITS is too low!
-# endif
-#endif
-
-#define __ARCH_IRQ_EXIT_IRQS_DISABLED   1
-
-#endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
deleted file mode 100644
index 5b51eaec012c..000000000000
--- a/include/asm-blackfin/hw_irq.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_BFIN_HW_IRQ_H
-#define __ASM_BFIN_HW_IRQ_H
-
-/* Dummy include. */
-
-#endif
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
deleted file mode 100644
index cbbf7ffdbbff..000000000000
--- a/include/asm-blackfin/io.h
+++ /dev/null
@@ -1,212 +0,0 @@
-#ifndef _BFIN_IO_H
-#define _BFIN_IO_H
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-#include <linux/compiler.h>
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = b [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
-
-        return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = w [%2] (z);\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
-
-        return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-        unsigned int val;
-        int tmp;
-
-        __asm__ __volatile__ ("cli %1;\n\t"
-                        "NOP; NOP; SSYNC;\n\t"
-                        "%0 = [%2];\n\t"
-                        "sti %1;\n\t"
-                        : "=d"(val), "=d"(tmp): "a"(addr)
-                        );
-        return val;
-}
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
-#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
-#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
-
-#define inb(addr)    readb(addr)
-#define inw(addr)    readw(addr)
-#define inl(addr)    readl(addr)
-#define outb(x,addr) ((void) writeb(x,addr))
-#define outw(x,addr) ((void) writew(x,addr))
-#define outl(x,addr) ((void) writel(x,addr))
-
-#define inb_p(addr)    inb(addr)
-#define inw_p(addr)    inw(addr)
-#define inl_p(addr)    inl(addr)
-#define outb_p(x,addr) outb(x,addr)
-#define outw_p(x,addr) outw(x,addr)
-#define outl_p(x,addr) outl(x,addr)
-
-#define ioread8_rep(a,d,c)      insb(a,d,c)
-#define ioread16_rep(a,d,c)     insw(a,d,c)
-#define ioread32_rep(a,d,c)     insl(a,d,c)
-#define iowrite8_rep(a,s,c)     outsb(a,s,c)
-#define iowrite16_rep(a,s,c)    outsw(a,s,c)
-#define iowrite32_rep(a,s,c)    outsl(a,s,c)
-
-#define ioread8(X)                      readb(X)
-#define ioread16(X)                     readw(X)
-#define ioread32(X)                     readl(X)
-#define iowrite8(val,X)                 writeb(val,X)
-#define iowrite16(val,X)                writew(val,X)
-#define iowrite32(val,X)                writel(val,X)
-
-#define IO_SPACE_LIMIT 0xffffffff
-
-/* Values for nocacheflag and cmode */
-#define IOMAP_NOCACHE_SER               1
-
-#ifndef __ASSEMBLY__
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-
-extern void dma_outsb(unsigned long port, const void *addr, unsigned short count);
-extern void dma_outsw(unsigned long port, const void *addr, unsigned short count);
-extern void dma_outsl(unsigned long port, const void *addr, unsigned short count);
-
-extern void dma_insb(unsigned long port, void *addr, unsigned short count);
-extern void dma_insw(unsigned long port, void *addr, unsigned short count);
-extern void dma_insl(unsigned long port, void *addr, unsigned short count);
-
-/*
- * Map some physical address range into the kernel address space.
- */
-static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
-                                int cacheflag)
-{
-        return (void __iomem *)physaddr;
-}
-
-/*
- * Unmap a ioremap()ed region again
- */
-static inline void iounmap(void *addr)
-{
-}
-
-/*
- * __iounmap unmaps nearly everything, so be careful
- * it doesn't free currently pointer/page tables anymore but it
- * wans't used anyway and might be added later.
- */
-static inline void __iounmap(void *addr, unsigned long size)
-{
-}
-
-/*
- * Set new cache mode for some kernel address space.
- * The caller must push data for that range itself, if such data may already
- * be in the cache.
- */
-static inline void kernel_set_cachemode(void *addr, unsigned long size,
-                                        int cmode)
-{
-}
-
-static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-static inline void __iomem *ioremap_nocache(unsigned long physaddr,
-                                            unsigned long size)
-{
-        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
-}
-
-extern void blkfin_inv_cache_all(void);
-
-#endif
-
-#define ioport_map(port, nr)            ((void __iomem*)(port))
-#define ioport_unmap(addr)
-
-/* Pages to physical address... */
-#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
-#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
-
-#define phys_to_virt(vaddr)     ((void *) (vaddr))
-#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
-
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BFIN_IO_H */
diff --git a/include/asm-blackfin/ioctl.h b/include/asm-blackfin/ioctl.h
deleted file mode 100644
index b279fe06dfe5..000000000000
--- a/include/asm-blackfin/ioctl.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/ioctl.h>
diff --git a/include/asm-blackfin/ioctls.h b/include/asm-blackfin/ioctls.h
deleted file mode 100644
index 895e3173165d..000000000000
--- a/include/asm-blackfin/ioctls.h
+++ /dev/null
@@ -1,87 +0,0 @@
-#ifndef __ARCH_BFIN_IOCTLS_H__
-#define __ARCH_BFIN_IOCTLS_H__
-
-#include <asm/ioctl.h>
-
-/* 0x54 is just a magic number to make these relatively unique ('T') */
-
-#define TCGETS          0x5401
-#define TCSETS          0x5402
-#define TCSETSW         0x5403
-#define TCSETSF         0x5404
-#define TCGETA          0x5405
-#define TCSETA          0x5406
-#define TCSETAW         0x5407
-#define TCSETAF         0x5408
-#define TCSBRK          0x5409
-#define TCXONC          0x540A
-#define TCFLSH          0x540B
-#define TIOCEXCL        0x540C
-#define TIOCNXCL        0x540D
-#define TIOCSCTTY       0x540E
-#define TIOCGPGRP       0x540F
-#define TIOCSPGRP       0x5410
-#define TIOCOUTQ        0x5411
-#define TIOCSTI         0x5412
-#define TIOCGWINSZ      0x5413
-#define TIOCSWINSZ      0x5414
-#define TIOCMGET        0x5415
-#define TIOCMBIS        0x5416
-#define TIOCMBIC        0x5417
-#define TIOCMSET        0x5418
-#define TIOCGSOFTCAR    0x5419
-#define TIOCSSOFTCAR    0x541A
-#define FIONREAD        0x541B
-#define TIOCINQ         FIONREAD
-#define TIOCLINUX       0x541C
-#define TIOCCONS        0x541D
-#define TIOCGSERIAL     0x541E
-#define TIOCSSERIAL     0x541F
-#define TIOCPKT         0x5420
-#define FIONBIO         0x5421
-#define TIOCNOTTY       0x5422
-#define TIOCSETD        0x5423
-#define TIOCGETD        0x5424
-#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
-#define TIOCTTYGSTRUCT  0x5426  /* For debugging only */
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x5429  /* Return the session ID of FD */
-#define TCGETS2         _IOR('T', 0x2A, struct termios2)
-#define TCSETS2         _IOW('T', 0x2B, struct termios2)
-#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
-#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
-/* Get Pty Number (of pty-mux device) */
-#define TIOCGPTN        _IOR('T', 0x30, unsigned int)
-#define TIOCSPTLCK      _IOW('T', 0x31, int)    /* Lock/unlock Pty */
-
-#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
-#define FIOCLEX         0x5451
-#define FIOASYNC        0x5452
-#define TIOCSERCONFIG   0x5453
-#define TIOCSERGWILD    0x5454
-#define TIOCSERSWILD    0x5455
-#define TIOCGLCKTRMIOS  0x5456
-#define TIOCSLCKTRMIOS  0x5457
-#define TIOCSERGSTRUCT  0x5458  /* For debugging only */
-#define TIOCSERGETLSR   0x5459  /* Get line status register */
-#define TIOCSERGETMULTI 0x545A  /* Get multiport config  */
-#define TIOCSERSETMULTI 0x545B  /* Set multiport config */
-
-#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
-
-#define FIOQSIZE        0x545E
-
-/* Used for packet mode */
-#define TIOCPKT_DATA             0
-#define TIOCPKT_FLUSHREAD        1
-#define TIOCPKT_FLUSHWRITE       2
-#define TIOCPKT_STOP             4
-#define TIOCPKT_START            8
-#define TIOCPKT_NOSTOP          16
-#define TIOCPKT_DOSTOP          32
-
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
-
-#endif                          /* __ARCH_BFIN_IOCTLS_H__ */
diff --git a/include/asm-blackfin/ipcbuf.h b/include/asm-blackfin/ipcbuf.h
deleted file mode 100644
index 8f0899cdf4d2..000000000000
--- a/include/asm-blackfin/ipcbuf.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/* Changes origined from m68k version.    Lineo Inc.  May 2001   */
-
-#ifndef __BFIN_IPCBUF_H__
-#define __BFIN_IPCBUF_H__
-
-/*
- * The user_ipc_perm structure for m68k architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit mode_t and seq
- * - 2 miscellaneous 32-bit values
- */
-
-struct ipc64_perm {
-        __kernel_key_t key;
-        __kernel_uid32_t uid;
-        __kernel_gid32_t gid;
-        __kernel_uid32_t cuid;
-        __kernel_gid32_t cgid;
-        __kernel_mode_t mode;
-        unsigned short __pad1;
-        unsigned short seq;
-        unsigned short __pad2;
-        unsigned long __unused1;
-        unsigned long __unused2;
-};
-
-#endif                          /* __BFIN_IPCBUF_H__ */
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
deleted file mode 100644
index 86b67834354d..000000000000
--- a/include/asm-blackfin/irq.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- *
- * Changed by HuTao Apr18, 2003
- *
- * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
- * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
- * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
- *
- * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
- * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
- * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
- */
-
-#ifndef _BFIN_IRQ_H_
-#define _BFIN_IRQ_H_
-
-#include <asm/mach/irq.h>
-#include <asm/ptrace.h>
-
-/*******************************************************************************
- *****   INTRODUCTION ***********
- *   On the Blackfin, the interrupt structure allows remmapping of the hardware
- *   levels.
- * - I'm going to assume that the H/W level is going to stay at the default
- *   settings. If someone wants to go through and abstart this out, feel free
- *   to mod the interrupt numbering scheme.
- * - I'm abstracting the interrupts so that uClinux does not know anything
- *   about the H/W levels. If you want to change the H/W AND keep the abstracted
- *   levels that uClinux sees, you should be able to do most of it here.
- * - I've left the "abstract" numbering sparce in case someone wants to pull the
- *   interrupts apart (just the TX/RX for the various devices)
- *******************************************************************************/
-
-/* SYS_IRQS and NR_IRQS are defined in <asm/mach-bf5xx/irq.h>*/
-
-/*
- * Machine specific interrupt sources.
- *
- * Adding an interrupt service routine for a source with this bit
- * set indicates a special machine specific interrupt source.
- * The machine specific files define these sources.
- *
- * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
- * introduce unnecessary overhead.
- *
- * All interrupt handling is actually machine specific so it is better
- * to use function pointers, as used by the Sparc port, and select the
- * interrupt handling functions when initializing the kernel. This way
- * we save some unnecessary overhead at run-time.
- *                                                      01/11/97 - Jes
- */
-
-extern void ack_bad_irq(unsigned int irq);
-
-static __inline__ int irq_canonicalize(int irq)
-{
-        return irq;
-}
-
-/* count of spurious interrupts */
-/* extern volatile unsigned int num_spurious; */
-
-#ifndef NO_IRQ
-#define NO_IRQ ((unsigned int)(-1))
-#endif
-
-#define SIC_SYSIRQ(irq) (irq - (IRQ_CORETMR + 1))
-
-#endif                          /* _BFIN_IRQ_H_ */
diff --git a/include/asm-blackfin/irq_handler.h b/include/asm-blackfin/irq_handler.h
deleted file mode 100644
index 139b5208f9d8..000000000000
--- a/include/asm-blackfin/irq_handler.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef _IRQ_HANDLER_H
-#define _IRQ_HANDLER_H
-
-#include <linux/types.h>
-#include <linux/linkage.h>
-
-/* BASE LEVEL interrupt handler routines */
-asmlinkage void evt_exception(void);
-asmlinkage void trap(void);
-asmlinkage void evt_ivhw(void);
-asmlinkage void evt_timer(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_evt7(void);
-asmlinkage void evt_evt8(void);
-asmlinkage void evt_evt9(void);
-asmlinkage void evt_evt10(void);
-asmlinkage void evt_evt11(void);
-asmlinkage void evt_evt12(void);
-asmlinkage void evt_evt13(void);
-asmlinkage void evt_soft_int1(void);
-asmlinkage void evt_system_call(void);
-asmlinkage void init_exception_buff(void);
-asmlinkage void trap_c(struct pt_regs *fp);
-asmlinkage void ex_replaceable(void);
-asmlinkage void early_trap(void);
-
-extern void *ex_table[];
-extern void return_from_exception(void);
-
-extern int bfin_request_exception(unsigned int exception, void (*handler)(void));
-extern int bfin_free_exception(unsigned int exception, void (*handler)(void));
-
-#endif
diff --git a/include/asm-blackfin/irq_regs.h b/include/asm-blackfin/irq_regs.h
deleted file mode 100644
index 3dd9c0b70270..000000000000
--- a/include/asm-blackfin/irq_regs.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/irq_regs.h>
diff --git a/include/asm-blackfin/kdebug.h b/include/asm-blackfin/kdebug.h
deleted file mode 100644
index 6ece1b037665..000000000000
--- a/include/asm-blackfin/kdebug.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/kdebug.h>
diff --git a/include/asm-blackfin/kgdb.h b/include/asm-blackfin/kgdb.h
deleted file mode 100644
index 0f73847fd6bc..000000000000
--- a/include/asm-blackfin/kgdb.h
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * File:         include/asm-blackfin/kgdb.h
- * Based on:
- * Author:       Sonic Zhang
- *
- * Created:
- * Description:
- *
- * Rev:          $Id: kgdb_bfin_linux-2.6.x.patch 4934 2007-02-13 09:32:11Z sonicz $
- *
- * Modified:
- *               Copyright 2005-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __ASM_BLACKFIN_KGDB_H__
-#define __ASM_BLACKFIN_KGDB_H__
-
-#include <linux/ptrace.h>
-
-/* gdb locks */
-#define KGDB_MAX_NO_CPUS 8
-
-/************************************************************************/
-/* BUFMAX defines the maximum number of characters in inbound/outbound buffers*/
-/* at least NUMREGBYTES*2 are needed for register packets */
-/* Longer buffer is needed to list all threads */
-#define BUFMAX 2048
-
-/*
- *  Note that this register image is different from
- *  the register image that Linux produces at interrupt time.
- *  
- *  Linux's register image is defined by struct pt_regs in ptrace.h.
- */
-enum regnames {
-  /* Core Registers */
-  BFIN_R0 = 0,
-  BFIN_R1,
-  BFIN_R2,
-  BFIN_R3,
-  BFIN_R4,
-  BFIN_R5,
-  BFIN_R6,
-  BFIN_R7,
-  BFIN_P0,
-  BFIN_P1,
-  BFIN_P2,
-  BFIN_P3,
-  BFIN_P4,
-  BFIN_P5,
-  BFIN_SP,
-  BFIN_FP,
-  BFIN_I0,
-  BFIN_I1,
-  BFIN_I2,
-  BFIN_I3,
-  BFIN_M0,
-  BFIN_M1,
-  BFIN_M2,
-  BFIN_M3,
-  BFIN_B0,
-  BFIN_B1,
-  BFIN_B2,
-  BFIN_B3,
-  BFIN_L0,
-  BFIN_L1,
-  BFIN_L2,
-  BFIN_L3,
-  BFIN_A0_DOT_X,
-  BFIN_A0_DOT_W,
-  BFIN_A1_DOT_X,
-  BFIN_A1_DOT_W,
-  BFIN_ASTAT,
-  BFIN_RETS,
-  BFIN_LC0,
-  BFIN_LT0,
-  BFIN_LB0,
-  BFIN_LC1,
-  BFIN_LT1,
-  BFIN_LB1,
-  BFIN_CYCLES,
-  BFIN_CYCLES2,
-  BFIN_USP,
-  BFIN_SEQSTAT,
-  BFIN_SYSCFG,
-  BFIN_RETI,
-  BFIN_RETX,
-  BFIN_RETN,
-  BFIN_RETE,
-  
-  /* Pseudo Registers */
-  BFIN_PC,
-  BFIN_CC,
-  BFIN_EXTRA1,          /* Address of .text section.  */
-  BFIN_EXTRA2,          /* Address of .data section.  */
-  BFIN_EXTRA3,          /* Address of .bss section.  */
-  BFIN_FDPIC_EXEC, 
-  BFIN_FDPIC_INTERP,
-
-  /* MMRs */
-  BFIN_IPEND,
-
-  /* LAST ENTRY SHOULD NOT BE CHANGED.  */
-  BFIN_NUM_REGS         /* The number of all registers.  */
-};
-
-/* Number of bytes of registers.  */
-#define NUMREGBYTES BFIN_NUM_REGS*4
-
-#define BREAKPOINT() asm("   EXCPT 2;");
-#define BREAK_INSTR_SIZE       2
-#define HW_BREAKPOINT_NUM               6
-
-/* Instruction watchpoint address control register bits mask */
-#define WPPWR           0x1
-#define WPIREN01        0x2
-#define WPIRINV01       0x4
-#define WPIAEN0         0x8
-#define WPIAEN1         0x10
-#define WPICNTEN0       0x20
-#define WPICNTEN1       0x40
-#define EMUSW0          0x80
-#define EMUSW1          0x100
-#define WPIREN23        0x200
-#define WPIRINV23       0x400
-#define WPIAEN2         0x800
-#define WPIAEN3         0x1000
-#define WPICNTEN2       0x2000
-#define WPICNTEN3       0x4000
-#define EMUSW2          0x8000
-#define EMUSW3          0x10000
-#define WPIREN45        0x20000
-#define WPIRINV45       0x40000
-#define WPIAEN4         0x80000
-#define WPIAEN5         0x100000
-#define WPICNTEN4       0x200000
-#define WPICNTEN5       0x400000
-#define EMUSW4          0x800000
-#define EMUSW5          0x1000000
-#define WPAND           0x2000000
-
-/* Data watchpoint address control register bits mask */
-#define WPDREN01        0x1
-#define WPDRINV01       0x2
-#define WPDAEN0         0x4
-#define WPDAEN1         0x8
-#define WPDCNTEN0       0x10
-#define WPDCNTEN1       0x20
-#define WPDSRC0         0xc0
-#define WPDACC0         0x300
-#define WPDSRC1         0xc00
-#define WPDACC1         0x3000
-
-/* Watchpoint status register bits mask */
-#define STATIA0         0x1
-#define STATIA1         0x2
-#define STATIA2         0x4
-#define STATIA3         0x8
-#define STATIA4         0x10
-#define STATIA5         0x20
-#define STATDA0         0x40
-#define STATDA1         0x80
-
-extern void kgdb_print(const char *fmt, ...);
-extern void init_kgdb_uart(void);
-
-#endif
diff --git a/include/asm-blackfin/kmap_types.h b/include/asm-blackfin/kmap_types.h
deleted file mode 100644
index e215f7104974..000000000000
--- a/include/asm-blackfin/kmap_types.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-enum km_type {
-        KM_BOUNCE_READ,
-        KM_SKB_SUNRPC_DATA,
-        KM_SKB_DATA_SOFTIRQ,
-        KM_USER0,
-        KM_USER1,
-        KM_BIO_SRC_IRQ,
-        KM_BIO_DST_IRQ,
-        KM_PTE0,
-        KM_PTE1,
-        KM_IRQ0,
-        KM_IRQ1,
-        KM_SOFTIRQ0,
-        KM_SOFTIRQ1,
-        KM_TYPE_NR
-};
-
-#endif
diff --git a/include/asm-blackfin/l1layout.h b/include/asm-blackfin/l1layout.h
deleted file mode 100644
index c13ded777828..000000000000
--- a/include/asm-blackfin/l1layout.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * l1layout.h
- * Defines a layout of L1 scratchpad memory that userspace can rely on.
- */
-
-#ifndef _L1LAYOUT_H_
-#define _L1LAYOUT_H_
-
-#include <asm/blackfin.h>
-
-#ifndef __ASSEMBLY__
-
-/* Data that is "mapped" into the process VM at the start of the L1 scratch
-   memory, so that each process can access it at a fixed address.  Used for
-   stack checking.  */
-struct l1_scratch_task_info
-{
-        /* Points to the start of the stack.  */
-        void *stack_start;
-        /* Not updated by the kernel; a user process can modify this to
-           keep track of the lowest address of the stack pointer during its
-           runtime.  */
-        void *lowest_sp;
-};
-
-/* A pointer to the structure in memory.  */
-#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
-
-#endif
-
-#endif
diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
deleted file mode 100644
index 5a822bb790f7..000000000000
--- a/include/asm-blackfin/linkage.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#define __ALIGN .align 4
-#define __ALIGN_STR ".align 4"
-
-#endif
diff --git a/include/asm-blackfin/local.h b/include/asm-blackfin/local.h
deleted file mode 100644
index 75afffbc6421..000000000000
--- a/include/asm-blackfin/local.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BLACKFIN_LOCAL_H
-#define __BLACKFIN_LOCAL_H
-
-#include <asm-generic/local.h>
-
-#endif                          /* __BLACKFIN_LOCAL_H */
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h
deleted file mode 100644
index b7b166f4f064..000000000000
--- a/include/asm-blackfin/mach-bf527/anomaly.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf527/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision C, 01/25/2008; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* New Feature: EMAC TX DMA Word Alignment */
-#define ANOMALY_05000285 (1)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (1)
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (1)
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (1)
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (1)
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (__SILICON_REVISION__ < 1)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (__SILICON_REVISION__ > 0)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* New Feature: Higher Default CCLK Rate */
-#define ANOMALY_05000368 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (__SILICON_REVISION__ > 0)
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (1)
-/* USB Full-speed Mode not Fully Tested */
-#define ANOMALY_05000381 (1)
-/* New Feature: Boot from OTP Memory */
-#define ANOMALY_05000385 (1)
-/* New Feature: bfrom_SysControl() Routine */
-#define ANOMALY_05000386 (1)
-/* New Feature: Programmable Preboot Settings */
-#define ANOMALY_05000387 (1)
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (1)
-/* New Feature: pTempCurrent Added to ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (1)
-/* New Feature: dTempByteCount Value Increased in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (1)
-/* New Feature: Log Buffer Functionality */
-#define ANOMALY_05000394 (1)
-/* New Feature: Hook Routine Functionality */
-#define ANOMALY_05000395 (1)
-/* New Feature: Header Indirect Bit */
-#define ANOMALY_05000396 (1)
-/* New Feature: BK_ONES, BK_ZEROS, and BK_DATECODE Constants */
-#define ANOMALY_05000397 (1)
-/* New Feature: SWRESET, DFRESET and WDRESET Bits Added to SYSCR Register */
-#define ANOMALY_05000398 (1)
-/* New Feature: BCODE_NOBOOT Added to BCODE Field of SYSCR Register */
-#define ANOMALY_05000399 (1)
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf527/bf527.h b/include/asm-blackfin/mach-bf527/bf527.h
deleted file mode 100644
index 056eb4b9cd25..000000000000
--- a/include/asm-blackfin/mach-bf527/bf527.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/bf527.h
- * Based on:    include/asm-blackfin/mach-bf537/bf537.h
- * Author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF527
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF527_H__
-#define __MACH_BF527_H__
-
-#define SUPPORTED_REVID 2
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR    0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF527
-#define CPU "BF527"
-#endif
-#ifdef CONFIG_BF525
-#define CPU "BF525"
-#endif
-#ifdef CONFIG_BF522
-#define CPU "BF522"
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF527_H__  */
diff --git a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
deleted file mode 100644
index 2526b6ed6faa..000000000000
--- a/include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_THR), v)
-#define UART_PUT_DLL(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLL), v)
-#define UART_PUT_IER(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_IER), v)
-#define UART_SET_IER(uart, v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart, v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_DLH), v)
-#define UART_PUT_LCR(uart, v)    bfin_write16(((uart)->port.membase + OFFSET_LCR), v)
-#define UART_PUT_GCTL(uart, v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL), v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port port;
-        unsigned int old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int tx_done;
-        int tx_count;
-        struct circ_buf rx_dma_buf;
-        struct timer_list rx_dma_timer;
-        int rx_dma_nrows;
-        unsigned int tx_dma_channel;
-        unsigned int rx_dma_channel;
-        struct work_struct tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list cts_timer;
-        int cts_pin;
-        int rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long uart_base_addr;
-        int uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int uart_tx_dma_channel;
-        unsigned int uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int uart_cts_pin;
-        int uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-         0xFFC00400,
-         IRQ_UART0_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART0_TX,
-         CH_UART0_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-         CONFIG_UART0_CTS_PIN,
-         CONFIG_UART0_RTS_PIN,
-#endif
-         },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-         0xFFC02000,
-         IRQ_UART1_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-         CH_UART1_TX,
-         CH_UART1_RX,
-#endif
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-         CONFIG_UART1_CTS_PIN,
-         CONFIG_UART1_RTS_PIN,
-#endif
-         },
-#endif
-};
-
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
-#define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf527/bfin_sir.h b/include/asm-blackfin/mach-bf527/bfin_sir.h
deleted file mode 100644
index cfd8ad4f1f2c..000000000000
--- a/include/asm-blackfin/mach-bf527/bfin_sir.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf527/blackfin.h b/include/asm-blackfin/mach-bf527/blackfin.h
deleted file mode 100644
index 297821e2d79a..000000000000
--- a/include/asm-blackfin/mach-bf527/blackfin.h
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF527_FAMILY
-
-#include "bf527.h"
-#include "mem_map.h"
-#include "defBF522.h"
-#include "anomaly.h"
-
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "defBF527.h"
-#endif
-
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "defBF525.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF522.h"
-
-#if defined(CONFIG_BF527) || defined(CONFIG_BF526)
-#include "cdefBF527.h"
-#endif
-
-#if defined(CONFIG_BF525) || defined(CONFIG_BF524)
-#include "cdefBF525.h"
-#endif
-#endif
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-/* DPMC*/
-#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
-#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
-#define STOPCK_OFF STOPCK
-
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf527/cdefBF522.h b/include/asm-blackfin/mach-bf527/cdefBF522.h
deleted file mode 100644
index 52c06494b886..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF522.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefbf522.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF522_H
-#define _CDEF_BF522_H
-
-/* include all Core registers and bit definitions */
-#include "defBF522.h"
-
-/* include core specific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-#endif /* _CDEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF525.h b/include/asm-blackfin/mach-bf527/cdefBF525.h
deleted file mode 100644
index 2cc67e4b4d86..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF525.h
+++ /dev/null
@@ -1,461 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefbf525.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF525_H
-#define _CDEF_BF525_H
-
-/* include all Core registers and bit definitions */
-#include "defBF525.h"
-
-/* include core specific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF527.h b/include/asm-blackfin/mach-bf527/cdefBF527.h
deleted file mode 100644
index 5bd1a8601743..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF527.h
+++ /dev/null
@@ -1,626 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefbf527.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF527_H
-#define _CDEF_BF527_H
-
-/* include all Core registers and bit definitions */
-#include "defBF527.h"
-
-/* include core specific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* include cdefBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "cdefBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
-
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
-
-#define bfin_read_EMAC_OPMODE()                 bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)             bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()                 bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)             bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()                 bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)             bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()                 bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)             bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()                 bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)             bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()                 bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)             bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()                 bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)             bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()                    bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)                bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()                  bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)              bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()                  bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)              bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()               bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)           bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()            bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val)        bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()            bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val)        bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()            bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val)        bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()            bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val)        bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()             bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val)         bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()             bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val)         bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()            bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val)        bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()            bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val)        bfin_write32(EMAC_WKUP_FFCRC1, val)
-
-#define bfin_read_EMAC_SYSCTL()                 bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)             bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()                 bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)             bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()                bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)            bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()                bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)            bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()                bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)            bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()                bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)            bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()                bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)            bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()                bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)            bfin_write32(EMAC_TX_IRQE, val)
-
-#define bfin_read_EMAC_MMC_CTL()                bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)            bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()              bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val)          bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()              bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val)          bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()              bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val)          bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()              bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val)          bfin_write32(EMAC_MMC_TIRQE, val)
-
-#define bfin_read_EMAC_RXC_OK()                 bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)             bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()                bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)            bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()              bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val)          bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()              bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val)          bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()             bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val)         bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()             bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val)         bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()              bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val)          bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()              bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val)          bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()             bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val)         bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()             bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val)         bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()               bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)           bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()             bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val)         bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()             bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val)         bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()              bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val)          bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()             bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val)         bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()             bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val)         bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()              bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val)          bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()              bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val)          bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()               bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)           bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()              bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val)          bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()              bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val)          bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()              bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val)          bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()             bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val)         bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()             bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val)         bfin_write32(EMAC_RXC_GE1024, val)
-
-#define bfin_read_EMAC_TXC_OK()                 bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)             bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()               bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)           bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()             bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val)         bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()              bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val)          bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()              bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val)          bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()             bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val)         bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()             bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val)         bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()             bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val)         bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()             bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val)         bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()             bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val)         bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()              bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val)          bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()              bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val)          bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()             bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val)         bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()             bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val)         bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()             bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val)         bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()             bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val)         bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()               bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)           bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()              bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val)          bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()              bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val)          bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()              bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val)          bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()             bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val)         bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()             bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val)         bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()              bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val)          bfin_write32(EMAC_TXC_ABORT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()                   bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)               bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()                   bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)               bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()                  bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)              bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()                  bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)              bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()                 bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)             bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()                 bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)             bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()                 bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)             bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()                bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)            bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()                   bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)               bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()                   bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)               bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()                bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)            bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()                bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)            bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()              bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endpoint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endpoint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-
-/* USB Endpoint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-
-/* USB Endpoint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-
-/* USB Endpoint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-
-/* USB Endpoint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-
-/* USB Endpoint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-
-/* USB Endpoint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-
-/* USB Endpoint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-#endif /* _CDEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h b/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
deleted file mode 100644
index 9dbdbec8ea1b..000000000000
--- a/include/asm-blackfin/mach-bf527/cdefBF52x_base.h
+++ /dev/null
@@ -1,1204 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/cdefBF52x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF52X_H
-#define _CDEF_BF52X_H
-
-#include <asm/system.h>
-#include <asm/blackfin.h>
-
-#include "defBF52x_base.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* ==== begin from cdefBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                     bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()                     bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)                 bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()                      bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                    bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)                bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()                 bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)             bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()                      bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)                  bfin_write32(CHIPID, val)
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                       bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                   bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()                       bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                   bfin_write16(SYSCR, val)
-
-#define bfin_read_SIC_RVECT()                   bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)               bfin_write32(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()                  bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)              bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK(x)                  bfin_read32(SIC_IMASK0 + (x << 6))
-#define bfin_write_SIC_IMASK(x, val)            bfin_write32((SIC_IMASK0 + (x << 6)), val)
-
-#define bfin_read_SIC_IAR0()                    bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)                bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()                    bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)                bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()                    bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)                bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()                    bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)                bfin_write32(SIC_IAR3, val)
-
-#define bfin_read_SIC_ISR0()                    bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)                bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR(x)                    bfin_read32(SIC_ISR0 + (x << 6))
-#define bfin_write_SIC_ISR(x, val)              bfin_write32((SIC_ISR0 + (x << 6)), val)
-
-#define bfin_read_SIC_IWR0()                    bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)                bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR(x)                    bfin_read32(SIC_IWR0 + (x << 6))
-#define bfin_write_SIC_IWR(x, val)              bfin_write32((SIC_IWR0 + (x << 6)), val)
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-
-#define bfin_read_SIC_IMASK1()                  bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)              bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()                    bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)                bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()                    bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)                bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()                    bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)                bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()                    bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)                bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()                    bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)                bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()                    bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)                bfin_write32(SIC_IWR1, val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                    bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)                bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()                    bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)                bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()                   bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)               bfin_write32(WDOG_STAT, val)
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                    bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)                bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()                    bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)                bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()                   bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)               bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()                   bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)               bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()                   bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)               bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_FAST()                    bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)                bfin_write16(RTC_FAST, val)
-#define bfin_read_RTC_PREN()                    bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)                bfin_write16(RTC_PREN, val)
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                   bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)               bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()                   bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)               bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()                   bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)               bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()                   bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)               bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()                   bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)               bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()                   bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)               bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()                   bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)               bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()                   bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)               bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()                   bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)               bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()                   bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)               bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()                   bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)               bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()                  bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)              bfin_write16(UART0_GCTL, val)
-
-
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                     bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)                 bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()                     bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)                 bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()                    bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)                bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()                    bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)                bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()                    bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)                bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()                    bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)                bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()                  bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)              bfin_write16(SPI_SHADOW, val)
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-#define bfin_read_TIMER_ENABLE()                bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)            bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()               bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)           bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()                bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)            bfin_write32(TIMER_STATUS, val)
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                     bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)                 bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()               bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)           bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()                 bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)             bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()              bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)          bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()               bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)           bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()         bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)     bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()           bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)       bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()        bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val)    bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()               bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)           bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()         bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)     bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()           bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)       bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()        bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val)    bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()                 bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)             bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()               bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)           bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()                bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)            bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()                bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)            bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()                bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)            bfin_write16(PORTFIO_INEN, val)
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_TX32()                 bfin_read32(SPORT0_TX32)
-#define bfin_write_SPORT0_TX32(val)             bfin_write32(SPORT0_TX32, val)
-#define bfin_read_SPORT0_RX32()                 bfin_read32(SPORT0_RX32)
-#define bfin_write_SPORT0_RX32(val)             bfin_write32(SPORT0_RX32, val)
-#define bfin_read_SPORT0_TX16()                 bfin_read16(SPORT0_TX16)
-#define bfin_write_SPORT0_TX16(val)             bfin_write16(SPORT0_TX16, val)
-#define bfin_read_SPORT0_RX16()                 bfin_read16(SPORT0_RX16)
-#define bfin_write_SPORT0_RX16(val)             bfin_write16(SPORT0_RX16, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()                 bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)             bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()                 bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)             bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()              bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)          bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()               bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)           bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()                   bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)               bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()                   bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)               bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_TX32()                 bfin_read32(SPORT1_TX32)
-#define bfin_write_SPORT1_TX32(val)             bfin_write32(SPORT1_TX32, val)
-#define bfin_read_SPORT1_RX32()                 bfin_read32(SPORT1_RX32)
-#define bfin_write_SPORT1_RX32(val)             bfin_write32(SPORT1_RX32, val)
-#define bfin_read_SPORT1_TX16()                 bfin_read16(SPORT1_TX16)
-#define bfin_write_SPORT1_TX16(val)             bfin_write16(SPORT1_TX16, val)
-#define bfin_read_SPORT1_RX16()                 bfin_read16(SPORT1_RX16)
-#define bfin_write_SPORT1_RX16(val)             bfin_write16(SPORT1_RX16, val)
-#define bfin_read_SPORT1_RCR1()                 bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)             bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()                 bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)             bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()              bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)          bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()               bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)           bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()                 bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)             bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()                 bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)             bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()                bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)            bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()                bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)            bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()                bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)            bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()                bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)            bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()                bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)            bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()                bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)            bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()                bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)            bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()                bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)            bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()                bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)            bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()                bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)            bfin_write32(SPORT1_MRCS3, val)
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()                 bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)             bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()                bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)            bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()                bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)            bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()                 bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)             bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()                 bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)             bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()                  bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)              bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()                 bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)             bfin_write16(EBIU_SDSTAT, val)
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                  bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)              bfin_write16(DMA_TC_PER, val)
-#define bfin_read_DMA_TC_CNT()                  bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)              bfin_write16(DMA_TC_CNT, val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                   bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)               bfin_write16(DMA_TCPER, val)
-#define bfin_read_DMA_TCCNT()                   bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)               bfin_write16(DMA_TCCNT, val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()                 bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)             bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()                  bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)              bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY()                   bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)               bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()                   bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)               bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()                   bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)               bfin_write16(PPI_FRAME, val)
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                     bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)                 bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()               bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)           bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()                 bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)             bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()              bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)          bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()               bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)           bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()         bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)     bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()           bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)       bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()        bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val)    bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()               bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)           bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()         bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)     bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()           bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)       bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()        bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val)    bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()                 bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)             bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()               bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)           bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()                bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)            bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()                bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)            bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()                bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)            bfin_write16(PORTGIO_INEN, val)
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                     bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)                 bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()               bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)           bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()                 bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)             bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()              bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)          bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()               bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)           bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()         bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)     bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()           bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)       bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()        bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val)    bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()               bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)           bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()         bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)     bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()           bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)       bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()        bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val)    bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()                 bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)             bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()               bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)           bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()                bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)            bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()                bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)            bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()                bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)            bfin_write16(PORTHIO_INEN, val)
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()                   bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)               bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()                   bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)               bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-
-/* Omit CAN register sets from the cdefBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                   bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)               bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()                   bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)               bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()                   bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)               bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()                    bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)                bfin_write16(PORT_MUX, val)
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-/* ==== end from cdefBF534.h ==== */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-
-#define bfin_read_PORTF_MUX()                   bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)               bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()                   bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)               bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()                   bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)               bfin_write16(PORTH_MUX, val)
-
-#define bfin_read_PORTF_DRIVE()                 bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)             bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()                 bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)             bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()                 bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)             bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()                  bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)              bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()                  bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)              bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()                  bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)              bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERISIS()            bfin_read16(PORTF_HYSTERISIS)
-#define bfin_write_PORTF_HYSTERISIS(val)        bfin_write16(PORTF_HYSTERISIS, val)
-#define bfin_read_PORTG_HYSTERISIS()            bfin_read16(PORTG_HYSTERISIS)
-#define bfin_write_PORTG_HYSTERISIS(val)        bfin_write16(PORTG_HYSTERISIS, val)
-#define bfin_read_PORTH_HYSTERISIS()            bfin_read16(PORTH_HYSTERISIS)
-#define bfin_write_PORTH_HYSTERISIS(val)        bfin_write16(PORTH_HYSTERISIS, val)
-#define bfin_read_MISCPORT_DRIVE()              bfin_read16(MISCPORT_DRIVE)
-#define bfin_write_MISCPORT_DRIVE(val)          bfin_write16(MISCPORT_DRIVE, val)
-#define bfin_read_MISCPORT_SLEW()               bfin_read16(MISCPORT_SLEW)
-#define bfin_write_MISCPORT_SLEW(val)           bfin_write16(MISCPORT_SLEW, val)
-#define bfin_read_MISCPORT_HYSTERISIS()         bfin_read16(MISCPORT_HYSTERISIS)
-#define bfin_write_MISCPORT_HYSTERISIS(val)     bfin_write16(MISCPORT_HYSTERISIS, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()                 bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()                  bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)              bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()                   bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)               bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()                  bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)              bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()                 bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)             bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()                bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)            bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()                 bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)             bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()                     bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)                 bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()                     bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)                 bfin_write32(CNT_MIN, val)
-
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()                 bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)             bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()                     bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)                 bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()                  bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)              bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()                  bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)              bfin_write32(OTP_TIMING, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()               bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)           bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()              bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)          bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()               bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)           bfin_write16(SECURE_STATUS, val)
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()                   bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)               bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()                   bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)               bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()                   bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)               bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()                   bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)               bfin_write32(OTP_DATA3, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()                     bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)                 bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()                    bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)                bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()                 bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)             bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()                 bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)             bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()                    bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)                bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()                    bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)                bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()                    bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)                bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()                    bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)                bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()                   bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)               bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()                     bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)                 bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()                   bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)               bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()                    bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)                bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()                    bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)                bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()                     bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)                 bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()                 bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)             bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()                 bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)             bfin_write16(NFC_DATA_RD, val)
-
-#endif /* _CDEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF522.h b/include/asm-blackfin/mach-bf527/defBF522.h
deleted file mode 100644
index 9671d8f2c5ef..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF522.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF522.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF522_H
-#define _DEF_BF522_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF522 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-#endif /* _DEF_BF522_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF525.h b/include/asm-blackfin/mach-bf527/defBF525.h
deleted file mode 100644
index 6a375a084acc..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF525.h
+++ /dev/null
@@ -1,713 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF525.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF525_H
-#define _DEF_BF525_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF525 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF525 that are not in the common header */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF525_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF527.h b/include/asm-blackfin/mach-bf527/defBF527.h
deleted file mode 100644
index f1a70db70cb8..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF527.h
+++ /dev/null
@@ -1,1090 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF527.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF527_H
-#define _DEF_BF527_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF527 */
-
-/* Include defBF52x_base.h for the set of #defines that are common to all ADSP-BF52x processors */
-#include "defBF52x_base.h"
-
-/* The following are the #defines needed by ADSP-BF527 that are not in the common header */
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF) */
-
-#define EMAC_OPMODE             0xFFC03000       /* Operating Mode Register                              */
-#define EMAC_ADDRLO             0xFFC03004       /* Address Low (32 LSBs) Register                       */
-#define EMAC_ADDRHI             0xFFC03008       /* Address High (16 MSBs) Register                      */
-#define EMAC_HASHLO             0xFFC0300C       /* Multicast Hash Table Low (Bins 31-0) Register        */
-#define EMAC_HASHHI             0xFFC03010       /* Multicast Hash Table High (Bins 63-32) Register      */
-#define EMAC_STAADD             0xFFC03014       /* Station Management Address Register                  */
-#define EMAC_STADAT             0xFFC03018       /* Station Management Data Register                     */
-#define EMAC_FLC                0xFFC0301C       /* Flow Control Register                                */
-#define EMAC_VLAN1              0xFFC03020       /* VLAN1 Tag Register                                   */
-#define EMAC_VLAN2              0xFFC03024       /* VLAN2 Tag Register                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C       /* Wake-Up Control/Status Register                      */
-#define EMAC_WKUP_FFMSK0        0xFFC03030       /* Wake-Up Frame Filter 0 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK1        0xFFC03034       /* Wake-Up Frame Filter 1 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK2        0xFFC03038       /* Wake-Up Frame Filter 2 Byte Mask Register            */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C       /* Wake-Up Frame Filter 3 Byte Mask Register            */
-#define EMAC_WKUP_FFCMD         0xFFC03040       /* Wake-Up Frame Filter Commands Register               */
-#define EMAC_WKUP_FFOFF         0xFFC03044       /* Wake-Up Frame Filter Offsets Register                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048       /* Wake-Up Frame Filter 0,1 CRC-16 Register             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C       /* Wake-Up Frame Filter 2,3 CRC-16 Register             */
-
-#define EMAC_SYSCTL             0xFFC03060       /* EMAC System Control Register                         */
-#define EMAC_SYSTAT             0xFFC03064       /* EMAC System Status Register                          */
-#define EMAC_RX_STAT            0xFFC03068       /* RX Current Frame Status Register                     */
-#define EMAC_RX_STKY            0xFFC0306C       /* RX Sticky Frame Status Register                      */
-#define EMAC_RX_IRQE            0xFFC03070       /* RX Frame Status Interrupt Enables Register           */
-#define EMAC_TX_STAT            0xFFC03074       /* TX Current Frame Status Register                     */
-#define EMAC_TX_STKY            0xFFC03078       /* TX Sticky Frame Status Register                      */
-#define EMAC_TX_IRQE            0xFFC0307C       /* TX Frame Status Interrupt Enables Register           */
-
-#define EMAC_MMC_CTL            0xFFC03080       /* MMC Counter Control Register                         */
-#define EMAC_MMC_RIRQS          0xFFC03084       /* MMC RX Interrupt Status Register                     */
-#define EMAC_MMC_RIRQE          0xFFC03088       /* MMC RX Interrupt Enables Register                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C       /* MMC TX Interrupt Status Register                     */
-#define EMAC_MMC_TIRQE          0xFFC03090       /* MMC TX Interrupt Enables Register                    */
-
-#define EMAC_RXC_OK             0xFFC03100       /* RX Frame Successful Count                            */
-#define EMAC_RXC_FCS            0xFFC03104       /* RX Frame FCS Failure Count                           */
-#define EMAC_RXC_ALIGN          0xFFC03108       /* RX Alignment Error Count                             */
-#define EMAC_RXC_OCTET          0xFFC0310C       /* RX Octets Successfully Received Count                */
-#define EMAC_RXC_DMAOVF         0xFFC03110       /* Internal MAC Sublayer Error RX Frame Count           */
-#define EMAC_RXC_UNICST         0xFFC03114       /* Unicast RX Frame Count                               */
-#define EMAC_RXC_MULTI          0xFFC03118       /* Multicast RX Frame Count                             */
-#define EMAC_RXC_BROAD          0xFFC0311C       /* Broadcast RX Frame Count                             */
-#define EMAC_RXC_LNERRI         0xFFC03120       /* RX Frame In Range Error Count                        */
-#define EMAC_RXC_LNERRO         0xFFC03124       /* RX Frame Out Of Range Error Count                    */
-#define EMAC_RXC_LONG           0xFFC03128       /* RX Frame Too Long Count                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C       /* MAC Control RX Frame Count                           */
-#define EMAC_RXC_OPCODE         0xFFC03130       /* Unsupported Op-Code RX Frame Count                   */
-#define EMAC_RXC_PAUSE          0xFFC03134       /* MAC Control Pause RX Frame Count                     */
-#define EMAC_RXC_ALLFRM         0xFFC03138       /* Overall RX Frame Count                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C       /* Overall RX Octet Count                               */
-#define EMAC_RXC_TYPED          0xFFC03140       /* Type/Length Consistent RX Frame Count                */
-#define EMAC_RXC_SHORT          0xFFC03144       /* RX Frame Fragment Count - Byte Count x < 64          */
-#define EMAC_RXC_EQ64           0xFFC03148       /* Good RX Frame Count - Byte Count x = 64              */
-#define EMAC_RXC_LT128          0xFFC0314C       /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define EMAC_RXC_LT256          0xFFC03150       /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define EMAC_RXC_LT512          0xFFC03154       /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define EMAC_RXC_LT1024         0xFFC03158       /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define EMAC_RXC_GE1024         0xFFC0315C       /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define EMAC_TXC_OK             0xFFC03180       /* TX Frame Successful Count                             */
-#define EMAC_TXC_1COL           0xFFC03184       /* TX Frames Successful After Single Collision Count     */
-#define EMAC_TXC_GT1COL         0xFFC03188       /* TX Frames Successful After Multiple Collisions Count  */
-#define EMAC_TXC_OCTET          0xFFC0318C       /* TX Octets Successfully Received Count                 */
-#define EMAC_TXC_DEFER          0xFFC03190       /* TX Frame Delayed Due To Busy Count                    */
-#define EMAC_TXC_LATECL         0xFFC03194       /* Late TX Collisions Count                              */
-#define EMAC_TXC_XS_COL         0xFFC03198       /* TX Frame Failed Due To Excessive Collisions Count     */
-#define EMAC_TXC_DMAUND         0xFFC0319C       /* Internal MAC Sublayer Error TX Frame Count            */
-#define EMAC_TXC_CRSERR         0xFFC031A0       /* Carrier Sense Deasserted During TX Frame Count        */
-#define EMAC_TXC_UNICST         0xFFC031A4       /* Unicast TX Frame Count                                */
-#define EMAC_TXC_MULTI          0xFFC031A8       /* Multicast TX Frame Count                              */
-#define EMAC_TXC_BROAD          0xFFC031AC       /* Broadcast TX Frame Count                              */
-#define EMAC_TXC_XS_DFR         0xFFC031B0       /* TX Frames With Excessive Deferral Count               */
-#define EMAC_TXC_MACCTL         0xFFC031B4       /* MAC Control TX Frame Count                            */
-#define EMAC_TXC_ALLFRM         0xFFC031B8       /* Overall TX Frame Count                                */
-#define EMAC_TXC_ALLOCT         0xFFC031BC       /* Overall TX Octet Count                                */
-#define EMAC_TXC_EQ64           0xFFC031C0       /* Good TX Frame Count - Byte Count x = 64               */
-#define EMAC_TXC_LT128          0xFFC031C4       /* Good TX Frame Count - Byte Count  64 < x < 128        */
-#define EMAC_TXC_LT256          0xFFC031C8       /* Good TX Frame Count - Byte Count 128 <= x < 256       */
-#define EMAC_TXC_LT512          0xFFC031CC       /* Good TX Frame Count - Byte Count 256 <= x < 512       */
-#define EMAC_TXC_LT1024         0xFFC031D0       /* Good TX Frame Count - Byte Count 512 <= x < 1024      */
-#define EMAC_TXC_GE1024         0xFFC031D4       /* Good TX Frame Count - Byte Count x >= 1024            */
-#define EMAC_TXC_ABORT          0xFFC031D8       /* Total TX Frames Aborted Count                         */
-
-/* Listing for IEEE-Supported Count Registers */
-
-#define FramesReceivedOK                EMAC_RXC_OK        /* RX Frame Successful Count                            */
-#define FrameCheckSequenceErrors        EMAC_RXC_FCS       /* RX Frame FCS Failure Count                           */
-#define AlignmentErrors                 EMAC_RXC_ALIGN     /* RX Alignment Error Count                             */
-#define OctetsReceivedOK                EMAC_RXC_OCTET     /* RX Octets Successfully Received Count                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF    /* Internal MAC Sublayer Error RX Frame Count           */
-#define UnicastFramesReceivedOK         EMAC_RXC_UNICST    /* Unicast RX Frame Count                               */
-#define MulticastFramesReceivedOK       EMAC_RXC_MULTI     /* Multicast RX Frame Count                             */
-#define BroadcastFramesReceivedOK       EMAC_RXC_BROAD     /* Broadcast RX Frame Count                             */
-#define InRangeLengthErrors             EMAC_RXC_LNERRI    /* RX Frame In Range Error Count                        */
-#define OutOfRangeLengthField           EMAC_RXC_LNERRO    /* RX Frame Out Of Range Error Count                    */
-#define FrameTooLongErrors              EMAC_RXC_LONG      /* RX Frame Too Long Count                              */
-#define MACControlFramesReceived        EMAC_RXC_MACCTL    /* MAC Control RX Frame Count                           */
-#define UnsupportedOpcodesReceived      EMAC_RXC_OPCODE    /* Unsupported Op-Code RX Frame Count                   */
-#define PAUSEMACCtrlFramesReceived      EMAC_RXC_PAUSE     /* MAC Control Pause RX Frame Count                     */
-#define FramesReceivedAll               EMAC_RXC_ALLFRM    /* Overall RX Frame Count                               */
-#define OctetsReceivedAll               EMAC_RXC_ALLOCT    /* Overall RX Octet Count                               */
-#define TypedFramesReceived             EMAC_RXC_TYPED     /* Type/Length Consistent RX Frame Count                */
-#define FramesLenLt64Received           EMAC_RXC_SHORT     /* RX Frame Fragment Count - Byte Count x < 64          */
-#define FramesLenEq64Received           EMAC_RXC_EQ64      /* Good RX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Received         EMAC_RXC_LT128     /* Good RX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Received        EMAC_RXC_LT256     /* Good RX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Received        EMAC_RXC_LT512     /* Good RX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Received       EMAC_RXC_LT1024    /* Good RX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxReceived       EMAC_RXC_GE1024    /* Good RX Frame Count - Byte Count x >= 1024           */
-
-#define FramesTransmittedOK             EMAC_TXC_OK        /* TX Frame Successful Count                            */
-#define SingleCollisionFrames           EMAC_TXC_1COL      /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames         EMAC_TXC_GT1COL    /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK             EMAC_TXC_OCTET     /* TX Octets Successfully Received Count                */
-#define FramesWithDeferredXmissions     EMAC_TXC_DEFER     /* TX Frame Delayed Due To Busy Count                   */
-#define LateCollisions                  EMAC_TXC_LATECL    /* Late TX Collisions Count                             */
-#define FramesAbortedDueToXSColls       EMAC_TXC_XS_COL    /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND    /* Internal MAC Sublayer Error TX Frame Count           */
-#define CarrierSenseErrors              EMAC_TXC_CRSERR    /* Carrier Sense Deasserted During TX Frame Count       */
-#define UnicastFramesXmittedOK          EMAC_TXC_UNICST    /* Unicast TX Frame Count                               */
-#define MulticastFramesXmittedOK        EMAC_TXC_MULTI     /* Multicast TX Frame Count                             */
-#define BroadcastFramesXmittedOK        EMAC_TXC_BROAD     /* Broadcast TX Frame Count                             */
-#define FramesWithExcessiveDeferral     EMAC_TXC_XS_DFR    /* TX Frames With Excessive Deferral Count              */
-#define MACControlFramesTransmitted     EMAC_TXC_MACCTL    /* MAC Control TX Frame Count                           */
-#define FramesTransmittedAll            EMAC_TXC_ALLFRM    /* Overall TX Frame Count                               */
-#define OctetsTransmittedAll            EMAC_TXC_ALLOCT    /* Overall TX Octet Count                               */
-#define FramesLenEq64Transmitted        EMAC_TXC_EQ64      /* Good TX Frame Count - Byte Count x = 64              */
-#define FramesLen65_127Transmitted      EMAC_TXC_LT128     /* Good TX Frame Count - Byte Count  64 < x < 128       */
-#define FramesLen128_255Transmitted     EMAC_TXC_LT256     /* Good TX Frame Count - Byte Count 128 <= x < 256      */
-#define FramesLen256_511Transmitted     EMAC_TXC_LT512     /* Good TX Frame Count - Byte Count 256 <= x < 512      */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024    /* Good TX Frame Count - Byte Count 512 <= x < 1024     */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024    /* Good TX Frame Count - Byte Count x >= 1024           */
-#define TxAbortedFrames                 EMAC_TXC_ABORT     /* Total TX Frames Aborted Count                        */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-
-/* EMAC_OPMODE Masks */
-
-#define RE                 0x00000001     /* Receiver Enable                                    */
-#define ASTP               0x00000002     /* Enable Automatic Pad Stripping On RX Frames        */
-#define HU                 0x00000010     /* Hash Filter Unicast Address                        */
-#define HM                 0x00000020     /* Hash Filter Multicast Address                      */
-#define PAM                0x00000040     /* Pass-All-Multicast Mode Enable                     */
-#define PR                 0x00000080     /* Promiscuous Mode Enable                            */
-#define IFE                0x00000100     /* Inverse Filtering Enable                           */
-#define DBF                0x00000200     /* Disable Broadcast Frame Reception                  */
-#define PBF                0x00000400     /* Pass Bad Frames Enable                             */
-#define PSF                0x00000800     /* Pass Short Frames Enable                           */
-#define RAF                0x00001000     /* Receive-All Mode                                   */
-#define TE                 0x00010000     /* Transmitter Enable                                 */
-#define DTXPAD             0x00020000     /* Disable Automatic TX Padding                       */
-#define DTXCRC             0x00040000     /* Disable Automatic TX CRC Generation                */
-#define DC                 0x00080000     /* Deferral Check                                     */
-#define BOLMT              0x00300000     /* Back-Off Limit                                     */
-#define BOLMT_10           0x00000000     /*            10-bit range                            */
-#define BOLMT_8            0x00100000     /*            8-bit range                             */
-#define BOLMT_4            0x00200000     /*            4-bit range                             */
-#define BOLMT_1            0x00300000     /*            1-bit range                             */
-#define DRTY               0x00400000     /* Disable TX Retry On Collision                      */
-#define LCTRE              0x00800000     /* Enable TX Retry On Late Collision                  */
-#define RMII               0x01000000     /* RMII/MII* Mode                                     */
-#define RMII_10            0x02000000     /* Speed Select for RMII Port (10MBit/100MBit*)       */
-#define FDMODE             0x04000000     /* Duplex Mode Enable (Full/Half*)                    */
-#define LB                 0x08000000     /* Internal Loopback Enable                           */
-#define DRO                0x10000000     /* Disable Receive Own Frames (Half-Duplex Mode)      */
-
-/* EMAC_STAADD Masks */
-
-#define STABUSY            0x00000001     /* Initiate Station Mgt Reg Access / STA Busy Stat    */
-#define STAOP              0x00000002     /* Station Management Operation Code (Write/Read*)    */
-#define STADISPRE          0x00000004     /* Disable Preamble Generation                        */
-#define STAIE              0x00000008     /* Station Mgt. Transfer Done Interrupt Enable        */
-#define REGAD              0x000007C0     /* STA Register Address                               */
-#define PHYAD              0x0000F800     /* PHY Device Address                                 */
-
-#define SET_REGAD(x) (((x)&0x1F)<<  6 )   /* Set STA Register Address                           */
-#define SET_PHYAD(x) (((x)&0x1F)<< 11 )   /* Set PHY Device Address                             */
-
-/* EMAC_STADAT Mask */
-
-#define STADATA            0x0000FFFF     /* Station Management Data                            */
-
-/* EMAC_FLC Masks */
-
-#define FLCBUSY            0x00000001     /* Send Flow Ctrl Frame / Flow Ctrl Busy Status       */
-#define FLCE               0x00000002     /* Flow Control Enable                                */
-#define PCF                0x00000004     /* Pass Control Frames                                */
-#define BKPRSEN            0x00000008     /* Enable Backpressure                                */
-#define FLCPAUSE           0xFFFF0000     /* Pause Time                                         */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16) /* Set Pause Time                                   */
-
-/* EMAC_WKUP_CTL Masks */
-
-#define CAPWKFRM           0x00000001    /* Capture Wake-Up Frames                              */
-#define MPKE               0x00000002    /* Magic Packet Enable                                 */
-#define RWKE               0x00000004    /* Remote Wake-Up Frame Enable                         */
-#define GUWKE              0x00000008    /* Global Unicast Wake Enable                          */
-#define MPKS               0x00000020    /* Magic Packet Received Status                        */
-#define RWKS               0x00000F00    /* Wake-Up Frame Received Status, Filters 3:0          */
-
-/* EMAC_WKUP_FFCMD Masks */
-
-#define WF0_E              0x00000001    /* Enable Wake-Up Filter 0                              */
-#define WF0_T              0x00000008    /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define WF1_E              0x00000100    /* Enable Wake-Up Filter 1                              */
-#define WF1_T              0x00000800    /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define WF2_E              0x00010000    /* Enable Wake-Up Filter 2                              */
-#define WF2_T              0x00080000    /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define WF3_E              0x01000000    /* Enable Wake-Up Filter 3                              */
-#define WF3_T              0x08000000    /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks */
-
-#define WF0_OFF            0x000000FF    /* Wake-Up Filter 0 Pattern Offset                      */
-#define WF1_OFF            0x0000FF00    /* Wake-Up Filter 1 Pattern Offset                      */
-#define WF2_OFF            0x00FF0000    /* Wake-Up Filter 2 Pattern Offset                      */
-#define WF3_OFF            0xFF000000    /* Wake-Up Filter 3 Pattern Offset                      */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 ) /* Set Wake-Up Filter 0 Byte Offset                    */
-#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 ) /* Set Wake-Up Filter 1 Byte Offset                    */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 ) /* Set Wake-Up Filter 2 Byte Offset                    */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 ) /* Set Wake-Up Filter 3 Byte Offset                    */
-/* Set ALL Offsets */
-#define SET_WF_OFFS(x0,x1,x2,x3) (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks */
-
-#define WF0_CRC           0x0000FFFF    /* Wake-Up Filter 0 Pattern CRC                           */
-#define WF1_CRC           0xFFFF0000    /* Wake-Up Filter 1 Pattern CRC                           */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 0 Target CRC                   */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 1 Target CRC                   */
-
-/* EMAC_WKUP_FFCRC1 Masks */
-
-#define WF2_CRC           0x0000FFFF    /* Wake-Up Filter 2 Pattern CRC                           */
-#define WF3_CRC           0xFFFF0000    /* Wake-Up Filter 3 Pattern CRC                           */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 ) /* Set Wake-Up Filter 2 Target CRC                   */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 ) /* Set Wake-Up Filter 3 Target CRC                   */
-
-/* EMAC_SYSCTL Masks */
-
-#define PHYIE             0x00000001    /* PHY_INT Interrupt Enable                               */
-#define RXDWA             0x00000002    /* Receive Frame DMA Word Alignment (Odd/Even*)           */
-#define RXCKS             0x00000004    /* Enable RX Frame TCP/UDP Checksum Computation           */
-#define TXDWA             0x00000010    /* Transmit Frame DMA Word Alignment (Odd/Even*)          */
-#define MDCDIV            0x00003F00    /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]            */
-
-#define SET_MDCDIV(x) (((x)&0x3F)<< 8)   /* Set MDC Clock Divisor                                 */
-
-/* EMAC_SYSTAT Masks */
-
-#define PHYINT            0x00000001    /* PHY_INT Interrupt Status                               */
-#define MMCINT            0x00000002    /* MMC Counter Interrupt Status                           */
-#define RXFSINT           0x00000004    /* RX Frame-Status Interrupt Status                       */
-#define TXFSINT           0x00000008    /* TX Frame-Status Interrupt Status                       */
-#define WAKEDET           0x00000010    /* Wake-Up Detected Status                                */
-#define RXDMAERR          0x00000020    /* RX DMA Direction Error Status                          */
-#define TXDMAERR          0x00000040    /* TX DMA Direction Error Status                          */
-#define STMDONE           0x00000080    /* Station Mgt. Transfer Done Interrupt Status            */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks */
-
-#define RX_FRLEN          0x000007FF    /* Frame Length In Bytes                                  */
-#define RX_COMP           0x00001000    /* RX Frame Complete                                      */
-#define RX_OK             0x00002000    /* RX Frame Received With No Errors                       */
-#define RX_LONG           0x00004000    /* RX Frame Too Long Error                                */
-#define RX_ALIGN          0x00008000    /* RX Frame Alignment Error                               */
-#define RX_CRC            0x00010000    /* RX Frame CRC Error                                     */
-#define RX_LEN            0x00020000    /* RX Frame Length Error                                  */
-#define RX_FRAG           0x00040000    /* RX Frame Fragment Error                                */
-#define RX_ADDR           0x00080000    /* RX Frame Address Filter Failed Error                   */
-#define RX_DMAO           0x00100000    /* RX Frame DMA Overrun Error                             */
-#define RX_PHY            0x00200000    /* RX Frame PHY Error                                     */
-#define RX_LATE           0x00400000    /* RX Frame Late Collision Error                          */
-#define RX_RANGE          0x00800000    /* RX Frame Length Field Out of Range Error               */
-#define RX_MULTI          0x01000000    /* RX Multicast Frame Indicator                           */
-#define RX_BROAD          0x02000000    /* RX Broadcast Frame Indicator                           */
-#define RX_CTL            0x04000000    /* RX Control Frame Indicator                             */
-#define RX_UCTL           0x08000000    /* Unsupported RX Control Frame Indicator                 */
-#define RX_TYPE           0x10000000    /* RX Typed Frame Indicator                               */
-#define RX_VLAN1          0x20000000    /* RX VLAN1 Frame Indicator                               */
-#define RX_VLAN2          0x40000000    /* RX VLAN2 Frame Indicator                               */
-#define RX_ACCEPT         0x80000000    /* RX Frame Accepted Indicator                            */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks  */
-
-#define TX_COMP           0x00000001    /* TX Frame Complete                                      */
-#define TX_OK             0x00000002    /* TX Frame Sent With No Errors                           */
-#define TX_ECOLL          0x00000004    /* TX Frame Excessive Collision Error                     */
-#define TX_LATE           0x00000008    /* TX Frame Late Collision Error                          */
-#define TX_DMAU           0x00000010    /* TX Frame DMA Underrun Error (STAT)                     */
-#define TX_MACE           0x00000010    /* Internal MAC Error Detected (STKY and IRQE)            */
-#define TX_EDEFER         0x00000020    /* TX Frame Excessive Deferral Error                      */
-#define TX_BROAD          0x00000040    /* TX Broadcast Frame Indicator                           */
-#define TX_MULTI          0x00000080    /* TX Multicast Frame Indicator                           */
-#define TX_CCNT           0x00000F00    /* TX Frame Collision Count                               */
-#define TX_DEFER          0x00001000    /* TX Frame Deferred Indicator                            */
-#define TX_CRS            0x00002000    /* TX Frame Carrier Sense Not Asserted Error              */
-#define TX_LOSS           0x00004000    /* TX Frame Carrier Lost During TX Error                  */
-#define TX_RETRY          0x00008000    /* TX Frame Successful After Retry                        */
-#define TX_FRLEN          0x07FF0000    /* TX Frame Length (Bytes)                                */
-
-/* EMAC_MMC_CTL Masks */
-#define RSTC              0x00000001    /* Reset All Counters                                     */
-#define CROLL             0x00000002    /* Counter Roll-Over Enable                               */
-#define CCOR              0x00000004    /* Counter Clear-On-Read Mode Enable                      */
-#define MMCE              0x00000008    /* Enable MMC Counter Operation                           */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks */
-#define RX_OK_CNT         0x00000001    /* RX Frames Received With No Errors                      */
-#define RX_FCS_CNT        0x00000002    /* RX Frames W/Frame Check Sequence Errors                */
-#define RX_ALIGN_CNT      0x00000004    /* RX Frames With Alignment Errors                        */
-#define RX_OCTET_CNT      0x00000008    /* RX Octets Received OK                                  */
-#define RX_LOST_CNT       0x00000010    /* RX Frames Lost Due To Internal MAC RX Error            */
-#define RX_UNI_CNT        0x00000020    /* Unicast RX Frames Received OK                          */
-#define RX_MULTI_CNT      0x00000040    /* Multicast RX Frames Received OK                        */
-#define RX_BROAD_CNT      0x00000080    /* Broadcast RX Frames Received OK                        */
-#define RX_IRL_CNT        0x00000100    /* RX Frames With In-Range Length Errors                  */
-#define RX_ORL_CNT        0x00000200    /* RX Frames With Out-Of-Range Length Errors              */
-#define RX_LONG_CNT       0x00000400    /* RX Frames With Frame Too Long Errors                   */
-#define RX_MACCTL_CNT     0x00000800    /* MAC Control RX Frames Received                         */
-#define RX_OPCODE_CTL     0x00001000    /* Unsupported Op-Code RX Frames Received                 */
-#define RX_PAUSE_CNT      0x00002000    /* PAUSEMAC Control RX Frames Received                    */
-#define RX_ALLF_CNT       0x00004000    /* All RX Frames Received                                 */
-#define RX_ALLO_CNT       0x00008000    /* All RX Octets Received                                 */
-#define RX_TYPED_CNT      0x00010000    /* Typed RX Frames Received                               */
-#define RX_SHORT_CNT      0x00020000    /* RX Frame Fragments (< 64 Bytes) Received               */
-#define RX_EQ64_CNT       0x00040000    /* 64-Byte RX Frames Received                             */
-#define RX_LT128_CNT      0x00080000    /* 65-127-Byte RX Frames Received                         */
-#define RX_LT256_CNT      0x00100000    /* 128-255-Byte RX Frames Received                        */
-#define RX_LT512_CNT      0x00200000    /* 256-511-Byte RX Frames Received                        */
-#define RX_LT1024_CNT     0x00400000    /* 512-1023-Byte RX Frames Received                       */
-#define RX_GE1024_CNT     0x00800000    /* 1024-Max-Byte RX Frames Received                       */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks  */
-
-#define TX_OK_CNT         0x00000001    /* TX Frames Sent OK                                      */
-#define TX_SCOLL_CNT      0x00000002    /* TX Frames With Single Collisions                       */
-#define TX_MCOLL_CNT      0x00000004    /* TX Frames With Multiple Collisions                     */
-#define TX_OCTET_CNT      0x00000008    /* TX Octets Sent OK                                      */
-#define TX_DEFER_CNT      0x00000010    /* TX Frames With Deferred Transmission                   */
-#define TX_LATE_CNT       0x00000020    /* TX Frames With Late Collisions                         */
-#define TX_ABORTC_CNT     0x00000040    /* TX Frames Aborted Due To Excess Collisions             */
-#define TX_LOST_CNT       0x00000080    /* TX Frames Lost Due To Internal MAC TX Error            */
-#define TX_CRS_CNT        0x00000100    /* TX Frames With Carrier Sense Errors                    */
-#define TX_UNI_CNT        0x00000200    /* Unicast TX Frames Sent                                 */
-#define TX_MULTI_CNT      0x00000400    /* Multicast TX Frames Sent                               */
-#define TX_BROAD_CNT      0x00000800    /* Broadcast TX Frames Sent                               */
-#define TX_EXDEF_CTL      0x00001000    /* TX Frames With Excessive Deferral                      */
-#define TX_MACCTL_CNT     0x00002000    /* MAC Control TX Frames Sent                             */
-#define TX_ALLF_CNT       0x00004000    /* All TX Frames Sent                                     */
-#define TX_ALLO_CNT       0x00008000    /* All TX Octets Sent                                     */
-#define TX_EQ64_CNT       0x00010000    /* 64-Byte TX Frames Sent                                 */
-#define TX_LT128_CNT      0x00020000    /* 65-127-Byte TX Frames Sent                             */
-#define TX_LT256_CNT      0x00040000    /* 128-255-Byte TX Frames Sent                            */
-#define TX_LT512_CNT      0x00080000    /* 256-511-Byte TX Frames Sent                            */
-#define TX_LT1024_CNT     0x00100000    /* 512-1023-Byte TX Frames Sent                           */
-#define TX_GE1024_CNT     0x00200000    /* 1024-Max-Byte TX Frames Sent                           */
-#define TX_ABORT_CNT      0x00400000    /* TX Frames Aborted                                      */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03800   /* Function address register */
-#define                        USB_POWER  0xffc03804   /* Power management register */
-#define                       USB_INTRTX  0xffc03808   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc0380c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03810   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03814   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03818   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc0381c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03820   /* USB frame number */
-#define                        USB_INDEX  0xffc03824   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03828   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc0382c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03830   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03840   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03844   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03848   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc0384c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03850   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03854   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03858   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc0385c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03860   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03868   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03880   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03888   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03890   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03898   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc038a0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc038a8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc038b0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc038b8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03900   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03904   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03908   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03948   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc0394c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03950   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03954   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03958   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc039e0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc039e4   /* Register used to set some calibration values */
-
-#define                  USB_APHY_CNTRL2  0xffc039e8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc039ec   /* Used for reducing simulation time and simplifies FIFO testability */
-
-#define                  USB_PLLOSC_CTRL  0xffc039f0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc039f4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03a00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03a04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03a08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03a0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03a10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03a14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03a18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03a1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03a20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define               USB_EP_NI0_TXCOUNT  0xffc03a28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-
-/* USB Endpoint 1 Control Registers */
-
-#define                USB_EP_NI1_TXMAXP  0xffc03a40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03a44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03a48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03a4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03a50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03a54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03a58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03a5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03a60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define               USB_EP_NI1_TXCOUNT  0xffc03a68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-
-/* USB Endpoint 2 Control Registers */
-
-#define                USB_EP_NI2_TXMAXP  0xffc03a80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03a84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03a88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03a8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03a90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03a94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03a98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03a9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03aa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define               USB_EP_NI2_TXCOUNT  0xffc03aa8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-
-/* USB Endpoint 3 Control Registers */
-
-#define                USB_EP_NI3_TXMAXP  0xffc03ac0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ac4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ac8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03acc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ad0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ad4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ad8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03adc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ae0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define               USB_EP_NI3_TXCOUNT  0xffc03ae8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-
-/* USB Endpoint 4 Control Registers */
-
-#define                USB_EP_NI4_TXMAXP  0xffc03b00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03b04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03b08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03b0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03b10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03b14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03b18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03b1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03b20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define               USB_EP_NI4_TXCOUNT  0xffc03b28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-
-/* USB Endpoint 5 Control Registers */
-
-#define                USB_EP_NI5_TXMAXP  0xffc03b40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03b44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03b48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03b4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03b50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03b54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03b58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03b5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03b60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define               USB_EP_NI5_TXCOUNT  0xffc03b68   /* Number of bytes to be written to the endpoint5 Tx FIFO */
-
-/* USB Endpoint 6 Control Registers */
-
-#define                USB_EP_NI6_TXMAXP  0xffc03b80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03b84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03b88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03b8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03b90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03b94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03b98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03b9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03ba0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define               USB_EP_NI6_TXCOUNT  0xffc03ba8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-
-/* USB Endpoint 7 Control Registers */
-
-#define                USB_EP_NI7_TXMAXP  0xffc03bc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03bc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03bc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03bcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03bd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03bd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03bd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03bdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03bf0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03bf8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-
-#define                USB_DMA_INTERRUPT  0xffc03c00   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc03c04   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc03c08   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc03c0c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc03c10   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc03c14   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc03c24   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc03c28   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc03c2c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc03c30   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc03c34   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc03c44   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc03c48   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc03c4c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc03c50   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc03c54   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc03c64   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc03c68   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc03c6c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc03c70   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc03c74   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc03c84   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc03c88   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc03c8c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc03c90   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc03c94   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc03ca4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc03ca8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc03cac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc03cb0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc03cb4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc03cc4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc03cc8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc03ccc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc03cd0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc03cd4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc03ce4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc03ce8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc03cec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc03cf0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc03cf4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define          nENABLE_SUSPENDM  0x0       
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define             nSUSPEND_MODE  0x0       
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define              nRESUME_MODE  0x0       
-#define                     RESET  0x8        /* Reset indicator */
-#define                    nRESET  0x0       
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                  nHS_MODE  0x0       
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                nHS_ENABLE  0x0       
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                nSOFT_CONN  0x0       
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-#define               nISO_UPDATE  0x0       
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                   nEP0_TX  0x0       
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                   nEP1_TX  0x0       
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                   nEP2_TX  0x0       
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                   nEP3_TX  0x0       
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                   nEP4_TX  0x0       
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                   nEP5_TX  0x0       
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                   nEP6_TX  0x0       
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-#define                   nEP7_TX  0x0       
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                   nEP1_RX  0x0       
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                   nEP2_RX  0x0       
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                   nEP3_RX  0x0       
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                   nEP4_RX  0x0       
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                   nEP5_RX  0x0       
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                   nEP6_RX  0x0       
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-#define                   nEP7_RX  0x0       
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                 nEP0_TX_E  0x0       
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                 nEP1_TX_E  0x0       
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                 nEP2_TX_E  0x0       
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                 nEP3_TX_E  0x0       
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                 nEP4_TX_E  0x0       
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                 nEP5_TX_E  0x0       
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                 nEP6_TX_E  0x0       
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-#define                 nEP7_TX_E  0x0       
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                 nEP1_RX_E  0x0       
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                 nEP2_RX_E  0x0       
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                 nEP3_RX_E  0x0       
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                 nEP4_RX_E  0x0       
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                 nEP5_RX_E  0x0       
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                 nEP6_RX_E  0x0       
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-#define                 nEP7_RX_E  0x0       
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                nSUSPEND_B  0x0       
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define                 nRESUME_B  0x0       
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define         nRESET_OR_BABLE_B  0x0       
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    nSOF_B  0x0       
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                   nCONN_B  0x0       
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define                 nDISCON_B  0x0       
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define            nSESSION_REQ_B  0x0       
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-#define             nVBUS_ERROR_B  0x0       
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define               nSUSPEND_BE  0x0       
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define                nRESUME_BE  0x0       
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define        nRESET_OR_BABLE_BE  0x0       
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   nSOF_BE  0x0       
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                  nCONN_BE  0x0       
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define                nDISCON_BE  0x0       
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define           nSESSION_REQ_BE  0x0       
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-#define            nVBUS_ERROR_BE  0x0       
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define               nGLOBAL_ENA  0x0       
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define               nEP1_TX_ENA  0x0       
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define               nEP2_TX_ENA  0x0       
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define               nEP3_TX_ENA  0x0       
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define               nEP4_TX_ENA  0x0       
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define               nEP5_TX_ENA  0x0       
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define               nEP6_TX_ENA  0x0       
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define               nEP7_TX_ENA  0x0       
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define               nEP1_RX_ENA  0x0       
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define               nEP2_RX_ENA  0x0       
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define               nEP3_RX_ENA  0x0       
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define               nEP4_RX_ENA  0x0       
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define               nEP5_RX_ENA  0x0       
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define               nEP6_RX_ENA  0x0       
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-#define               nEP7_RX_ENA  0x0       
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  nSESSION  0x0       
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 nHOST_REQ  0x0       
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                nHOST_MODE  0x0       
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                    nVBUS0  0x0       
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                    nVBUS1  0x0       
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                    nLSDEV  0x0       
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                    nFSDEV  0x0       
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-#define                 nB_DEVICE  0x0       
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            nDRIVE_VBUS_ON  0x0       
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           nDRIVE_VBUS_OFF  0x0       
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define          nCHRG_VBUS_START  0x0       
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define            nCHRG_VBUS_END  0x0       
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define       nDISCHRG_VBUS_START  0x0       
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-#define         nDISCHRG_VBUS_END  0x0       
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        nDRIVE_VBUS_ON_ENA  0x0       
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       nDRIVE_VBUS_OFF_ENA  0x0       
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define      nCHRG_VBUS_START_ENA  0x0       
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define        nCHRG_VBUS_END_ENA  0x0       
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define   nDISCHRG_VBUS_START_ENA  0x0       
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-#define     nDISCHRG_VBUS_END_ENA  0x0       
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                 nRXPKTRDY  0x0       
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                 nTXPKTRDY  0x0       
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define               nSTALL_SENT  0x0       
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  nDATAEND  0x0       
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 nSETUPEND  0x0       
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define                nSENDSTALL  0x0       
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define        nSERVICED_RXPKTRDY  0x0       
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define        nSERVICED_SETUPEND  0x0       
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define                nFLUSHFIFO  0x0       
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define         nSTALL_RECEIVED_H  0x0       
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define               nSETUPPKT_H  0x0       
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  nERROR_H  0x0       
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define                 nREQPKT_H  0x0       
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define              nSTATUSPKT_H  0x0       
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-#define            nNAK_TIMEOUT_H  0x0       
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define               nTXPKTRDY_T  0x0       
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define         nFIFO_NOT_EMPTY_T  0x0       
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               nUNDERRUN_T  0x0       
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              nFLUSHFIFO_T  0x0       
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define             nSTALL_SEND_T  0x0       
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define             nSTALL_SENT_T  0x0       
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_T  0x0       
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define               nINCOMPTX_T  0x0       
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_T  0x0       
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define       nFORCE_DATATOGGLE_T  0x0       
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_T  0x0       
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                    nISO_T  0x0       
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                nAUTOSET_T  0x0       
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define                 nERROR_TH  0x0       
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_TH  0x0       
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-#define           nNAK_TIMEOUT_TH  0x0       
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               nRXPKTRDY_R  0x0       
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define              nFIFO_FULL_R  0x0       
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define                nOVERRUN_R  0x0       
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define              nDATAERROR_R  0x0       
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              nFLUSHFIFO_R  0x0       
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define             nSTALL_SEND_R  0x0       
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define             nSTALL_SENT_R  0x0       
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define       nCLEAR_DATATOGGLE_R  0x0       
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define               nINCOMPRX_R  0x0       
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define             nDMAREQMODE_R  0x0       
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define                nDISNYET_R  0x0       
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define             nDMAREQ_ENA_R  0x0       
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define                    nISO_R  0x0       
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define              nAUTOCLEAR_R  0x0       
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 nERROR_RH  0x0       
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define                nREQPKT_RH  0x0       
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define        nSTALL_RECEIVED_RH  0x0       
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define              nINCOMPRX_RH  0x0       
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define            nDMAREQMODE_RH  0x0       
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-#define               nAUTOREQ_RH  0x0       
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                 nDMA0_INT  0x0       
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                 nDMA1_INT  0x0       
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                 nDMA2_INT  0x0       
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                 nDMA3_INT  0x0       
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                 nDMA4_INT  0x0       
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                 nDMA5_INT  0x0       
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                 nDMA6_INT  0x0       
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-#define                 nDMA7_INT  0x0       
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                  nDMA_ENA  0x0       
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                nDIRECTION  0x0       
-#define                      MODE  0x4        /* DMA Bus error */
-#define                     nMODE  0x0       
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                  nINT_ENA  0x0       
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-#define                 nBUSERROR  0x0       
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-#endif /* _DEF_BF527_H */
diff --git a/include/asm-blackfin/mach-bf527/defBF52x_base.h b/include/asm-blackfin/mach-bf527/defBF52x_base.h
deleted file mode 100644
index fc69cf93f149..000000000000
--- a/include/asm-blackfin/mach-bf527/defBF52x_base.h
+++ /dev/null
@@ -1,2014 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/defBF52x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF52X_H
-#define _DEF_BF52X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF52x    */
-/* ************************************************************** */
-
-/* ==== begin from defBF534.h ==== */
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID        0xFFC00014  /* Device ID Register */
-
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
-
-#define SIC_IMASK0                      0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
-#define SIC_ISR0                                0xFFC00120      /* Interrupt Status Register                            */
-#define SIC_IWR0                                0xFFC00124      /* Interrupt Wakeup Register                            */
-
-/* SIC Additions to ADSP-BF52x (0xFFC0014C - 0xFFC00162) */
-#define SIC_IMASK1                      0xFFC0014C     /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                        0xFFC00150     /* Interrupt Assignment register4 */
-#define SIC_IAR5                        0xFFC00154     /* Interrupt Assignment register5 */
-#define SIC_IAR6                        0xFFC00158     /* Interrupt Assignment register6 */
-#define SIC_IAR7                        0xFFC0015C     /* Interrupt Assignment register7 */
-#define SIC_ISR1                        0xFFC00160     /* Interrupt Statur register */
-#define SIC_IWR1                        0xFFC00164     /* Interrupt Wakeup register */
-
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-
-/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */   
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-
-/* Omit CAN register sets from the defBF534.h (CAN is not in the ADSP-BF52x processor) */
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-/* GPIO PIN mux (0xFFC03210 - OxFFC03288) */
-#define PORTF_MUX               0xFFC03210      /* Port F mux control */
-#define PORTG_MUX               0xFFC03214      /* Port G mux control */
-#define PORTH_MUX               0xFFC03218      /* Port H mux control */
-#define PORTF_DRIVE             0xFFC03220      /* Port F drive strength control */
-#define PORTG_DRIVE             0xFFC03224      /* Port G drive strength control */
-#define PORTH_DRIVE             0xFFC03228      /* Port H drive strength control */
-#define PORTF_SLEW              0xFFC03230      /* Port F slew control */
-#define PORTG_SLEW              0xFFC03234      /* Port G slew control */
-#define PORTH_SLEW              0xFFC03238      /* Port H slew control */
-#define PORTF_HYSTERISIS        0xFFC03240      /* Port F Schmitt trigger control */
-#define PORTG_HYSTERISIS        0xFFC03244      /* Port G Schmitt trigger control */
-#define PORTH_HYSTERISIS        0xFFC03248      /* Port H Schmitt trigger control */
-#define MISCPORT_DRIVE          0xFFC03280      /* Misc Port drive strength control */
-#define MISCPORT_SLEW           0xFFC03284      /* Misc Port slew control */
-#define MISCPORT_HYSTERISIS     0xFFC03288      /* Misc Port Schmitt trigger control */
-
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)               /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-/* Peripheral Masks For SIC_ISR, SIC_IWR, SIC_IMASK                                                                             */
-
-#if 0
-#define IRQ_PLL_WAKEUP  0x00000001      /* PLL Wakeup Interrupt                                                         */
-
-#define IRQ_ERROR1      0x00000002  /* Error Interrupt (DMA, DMARx Block, DMARx Overflow) */
-#define IRQ_ERROR2      0x00000004  /* Error Interrupt (CAN, Ethernet, SPORTx, PPI, SPI, UARTx) */
-#define IRQ_RTC                 0x00000008      /* Real Time Clock Interrupt                                            */ 
-#define IRQ_DMA0                0x00000010      /* DMA Channel 0 (PPI) Interrupt                                        */ 
-#define IRQ_DMA3                0x00000020      /* DMA Channel 3 (SPORT0 RX) Interrupt                          */ 
-#define IRQ_DMA4                0x00000040      /* DMA Channel 4 (SPORT0 TX) Interrupt                          */
-#define IRQ_DMA5                0x00000080      /* DMA Channel 5 (SPORT1 RX) Interrupt                          */
-
-#define IRQ_DMA6                0x00000100      /* DMA Channel 6 (SPORT1 TX) Interrupt                          */
-#define IRQ_TWI                 0x00000200      /* TWI Interrupt                                                                        */
-#define IRQ_DMA7                0x00000400      /* DMA Channel 7 (SPI) Interrupt                                        */
-#define IRQ_DMA8                0x00000800      /* DMA Channel 8 (UART0 RX) Interrupt                           */ 
-#define IRQ_DMA9                0x00001000      /* DMA Channel 9 (UART0 TX) Interrupt                           */
-#define IRQ_DMA10               0x00002000      /* DMA Channel 10 (UART1 RX) Interrupt                          */
-#define IRQ_DMA11               0x00004000      /* DMA Channel 11 (UART1 TX) Interrupt                          */
-#define IRQ_CAN_RX              0x00008000      /* CAN Receive Interrupt                                                        */
-
-#define IRQ_CAN_TX              0x00010000      /* CAN Transmit Interrupt                                                       */
-#define IRQ_DMA1                0x00020000      /* DMA Channel 1 (Ethernet RX) Interrupt                        */
-#define IRQ_PFA_PORTH   0x00020000      /* PF Port H (PF47:32) Interrupt A                                      */
-#define IRQ_DMA2                0x00040000      /* DMA Channel 2 (Ethernet TX) Interrupt                        */
-#define IRQ_PFB_PORTH   0x00040000      /* PF Port H (PF47:32) Interrupt B                                      */
-#define IRQ_TIMER0              0x00080000      /* Timer 0 Interrupt                                                            */
-#define IRQ_TIMER1              0x00100000      /* Timer 1 Interrupt                                                            */
-#define IRQ_TIMER2              0x00200000      /* Timer 2 Interrupt                                                            */
-#define IRQ_TIMER3              0x00400000      /* Timer 3 Interrupt                                                            */
-#define IRQ_TIMER4              0x00800000      /* Timer 4 Interrupt                                                            */
-
-#define IRQ_TIMER5              0x01000000      /* Timer 5 Interrupt                                                            */
-#define IRQ_TIMER6              0x02000000      /* Timer 6 Interrupt                                                            */
-#define IRQ_TIMER7              0x04000000      /* Timer 7 Interrupt                                                            */
-#define IRQ_PFA_PORTFG  0x08000000      /* PF Ports F&G (PF31:0) Interrupt A                            */
-#define IRQ_PFB_PORTF   0x80000000      /* PF Port F (PF15:0) Interrupt B                                       */
-#define IRQ_DMA12               0x20000000      /* DMA Channels 12 (MDMA1 Source) RX Interrupt          */
-#define IRQ_DMA13               0x20000000      /* DMA Channels 13 (MDMA1 Destination) TX Interrupt */
-#define IRQ_DMA14               0x40000000      /* DMA Channels 14 (MDMA0 Source) RX Interrupt          */
-#define IRQ_DMA15               0x40000000      /* DMA Channels 15 (MDMA0 Destination) TX Interrupt */
-#define IRQ_WDOG                0x80000000      /* Software Watchdog Timer Interrupt                            */
-#define IRQ_PFB_PORTG   0x10000000      /* PF Port G (PF31:16) Interrupt B                                      */
-#endif
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)                   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)                   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000                                      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF                                      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))                                       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000                                      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF                                      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))                                       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-
-/* ********* WATCHDOG TIMER MASKS ******************** */
-
-/* Watchdog Timer WDOG_CTL Register Masks */
-
-#define WDEV(x) (((x)<<1) & 0x0006) /* event generated on roll over */
-#define WDEV_RESET 0x0000 /* generate reset event on roll over */
-#define WDEV_NMI 0x0002 /* generate NMI event on roll over */
-#define WDEV_GPI 0x0004 /* generate GP IRQ on roll over */
-#define WDEV_NONE 0x0006 /* no event on roll over */
-#define WDEN 0x0FF0 /* enable watchdog */
-#define WDDIS 0x0AD0 /* disable watchdog */
-#define WDRO 0x8000 /* watchdog rolled over latch */ 
-
-/* depreciated WDOG_CTL Register Masks for legacy code */
-
-
-#define ICTL WDEV
-#define ENABLE_RESET WDEV_RESET
-#define WDOG_RESET WDEV_RESET
-#define ENABLE_NMI WDEV_NMI
-#define WDOG_NMI WDEV_NMI
-#define ENABLE_GPI WDEV_GPI
-#define WDOG_GPI WDEV_GPI
-#define DISABLE_EVT WDEV_NONE
-#define WDOG_NONE WDEV_NONE
-
-#define TMR_EN WDEN
-#define TMR_DIS WDDIS
-#define TRO WDRO
-#define ICTL_P0 0x01
- #define ICTL_P1 0x02
-#define TRO_P 0x0F
-
-
-
-/* ***************  REAL TIME CLOCK MASKS  **************************/
-/* RTC_STAT and RTC_ALARM Masks                                                                         */
-#define RTC_SEC                         0x0000003F      /* Real-Time Clock Seconds      */
-#define RTC_MIN                         0x00000FC0      /* Real-Time Clock Minutes      */
-#define RTC_HR                          0x0001F000      /* Real-Time Clock Hours        */
-#define RTC_DAY                         0xFFFE0000      /* Real-Time Clock Days         */
-
-/* RTC_ALARM Macro                      z=day           y=hr    x=min   w=sec           */
-#define SET_ALARM(z,y,x,w)      ((((z)&0x7FFF)<<0x11)|(((y)&0x1F)<<0xC)|(((x)&0x3F)<<0x6)|((w)&0x3F))
-
-/* RTC_ICTL and RTC_ISTAT Masks                                                                                                                                         */
-#define STOPWATCH                       0x0001          /* Stopwatch Interrupt Enable                                                           */
-#define ALARM                           0x0002          /* Alarm Interrupt Enable                                                                       */
-#define SECOND                          0x0004          /* Seconds (1 Hz) Interrupt Enable                                                      */
-#define MINUTE                          0x0008          /* Minutes Interrupt Enable                                                                     */
-#define HOUR                            0x0010          /* Hours Interrupt Enable                                                                       */
-#define DAY                                     0x0020          /* 24 Hours (Days) Interrupt Enable                                                     */
-#define DAY_ALARM                       0x0040          /* Day Alarm (Day, Hour, Minute, Second) Interrupt Enable       */
-#define WRITE_PENDING           0x4000          /* Write Pending Status                                                                         */
-#define WRITE_COMPLETE          0x8000          /* Write Complete Interrupt Enable                                                      */
-
-/* RTC_FAST / RTC_PREN Mask                                                                                             */
-#define PREN                            0x0001  /* Enable Prescaler, RTC Runs @1 Hz     */
-
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select */
-#define STB                     0x04                            /* Stop Bits                    */
-#define PEN                     0x08                            /* Parity Enable                */
-#define EPS                     0x10                            /* Even Parity Select   */
-#define STP                     0x20                            /* Stick Parity                 */
-#define SB                      0x40                            /* Set Break                    */
-#define DLAB            0x80                            /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA        0x10    /* Loopback Mode Enable */
-#define LOOP_ENA_P      0x04
-
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01            /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02            /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04            /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01            /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02            /* UART_THR empty                               */
-#define IIR_RX_READY    0x04            /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06            /* Receive line status                          */ 
-#define IIR_STATUS      0x06            /* Highest Priority Pending Interrupt   */
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01            /* Enable UARTx Clocks                          */
-#define IREN            0x02            /* Enable IrDA Mode                                     */
-#define TPOLC           0x04            /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08            /* IrDA RX Polarity Change                      */
-#define FPE                     0x10            /* Force Parity Error On Transmit       */
-#define FFE                     0x20            /* Force Framing Error On Transmit      */
-
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks                                                                                                                                        */
-#define TIMOD           0x0003          /* Transfer Initiate Mode                                                       */
-#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                      0x0004          /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
-#define GM                      0x0008          /* Get More (When RDBR Full, Overwrite/Discard*)        */
-#define PSSE            0x0010          /* Slave-Select Input Enable                                            */
-#define EMISO           0x0020          /* Enable MISO As Output                                                        */
-#define SIZE            0x0100          /* Size of Words (16/8* Bits)                                           */
-#define LSBF            0x0200          /* LSB First                                                                            */
-#define CPHA            0x0400          /* Clock Phase                                                                          */
-#define CPOL            0x0800          /* Clock Polarity                                                                       */
-#define MSTR            0x1000          /* Master/Slave*                                                                        */
-#define WOM                     0x2000          /* Write Open Drain Master                                                      */
-#define SPE                     0x4000          /* SPI Enable                                                                           */
-
-/* SPI_FLG Masks                                                                                                                                        */
-#define FLS1            0x0002          /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
-#define FLS2            0x0004          /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
-#define FLS3            0x0008          /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
-#define FLS4            0x0010          /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
-#define FLS5            0x0020          /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
-#define FLS6            0x0040          /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
-#define FLS7            0x0080          /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
-#define FLG1            0xFDFF          /* Activates SPI_FLOUT1                                                         */
-#define FLG2            0xFBFF          /* Activates SPI_FLOUT2                                                         */
-#define FLG3            0xF7FF          /* Activates SPI_FLOUT3                                                         */
-#define FLG4            0xEFFF          /* Activates SPI_FLOUT4                                                         */
-#define FLG5            0xDFFF          /* Activates SPI_FLOUT5                                                         */
-#define FLG6            0xBFFF          /* Activates SPI_FLOUT6                                                         */
-#define FLG7            0x7FFF          /* Activates SPI_FLOUT7                                                         */
-
-/* SPI_STAT Masks                                                                                                                                                               */
-#define SPIF            0x0001          /* SPI Finished (Single-Word Transfer Complete)                                 */
-#define MODF            0x0002          /* Mode Fault Error (Another Device Tried To Become Master)             */
-#define TXE                     0x0004          /* Transmission Error (Data Sent With No New Data In TDBR)              */
-#define TXS                     0x0008          /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
-#define RBSY            0x0010          /* Receive Error (Data Received With RDBR Full)                                 */
-#define RXS                     0x0020          /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
-#define TXCOL           0x0040          /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
-
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001          /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002          /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004          /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008          /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010          /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020          /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040          /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080          /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0          /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1          /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2          /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3          /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4          /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5          /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6          /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7          /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001          /* Transmit Enable                                                              */
-#define ITCLK           0x0002          /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010          /* Transmit Bit Order                                                   */
-#define ITFS            0x0200          /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400          /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800          /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000          /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000          /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100          /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200          /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400          /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001          /* Receive Enable                                                               */
-#define IRCLK           0x0002          /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010          /* Receive Bit Order                                                    */
-#define IRFS            0x0200          /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400          /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000          /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000          /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000          /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100          /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200          /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400          /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001          /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002          /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004          /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008          /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010          /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020          /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040          /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)      ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004          /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008          /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010          /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080          /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001  /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002  /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004  /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008  /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C  /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000  /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010  /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020  /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030  /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000  /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040  /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080  /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0  /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000  /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100  /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200  /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300  /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400  /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500  /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600  /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700  /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800  /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900  /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00  /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00  /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00  /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00  /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00  /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00  /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000  /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000  /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000  /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000  /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000  /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000  /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000  /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000  /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000  /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000  /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000  /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000  /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000  /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000  /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000  /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000  /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000  /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000  /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000  /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000  /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000  /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000  /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000  /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000  /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000  /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000  /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000  /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000  /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000  /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000  /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000  /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000  /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000  /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000  /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000  /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000  /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000  /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000  /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000  /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000  /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000  /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000  /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000  /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000  /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000  /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000  /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000  /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000  /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000  /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000  /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000  /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000  /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000  /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000  /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000  /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000  /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000  /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000  /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000  /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001  /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002  /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004  /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008  /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C  /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000  /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010  /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020  /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030  /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000  /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040  /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080  /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0  /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000  /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100  /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200  /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300  /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400  /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500  /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600  /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700  /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800  /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900  /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00  /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00  /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00  /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00  /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00  /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00  /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000  /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000  /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000  /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000  /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000  /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000  /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000  /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000  /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000  /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000  /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000  /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000  /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000  /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000  /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000  /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000  /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000  /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000  /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000  /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000  /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000  /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000  /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000  /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000  /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000  /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000  /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000  /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000  /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000  /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000  /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000  /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000  /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000  /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000  /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000  /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000  /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000  /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000  /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000  /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000  /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000  /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000  /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000  /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000  /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000  /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000  /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000  /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000  /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000  /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000  /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000  /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000  /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000  /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000  /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000  /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000  /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000  /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000  /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000  /* B3 Write Access Time = 15 cycles                                 */
-
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001          /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000          /* SDRAM External Bank Size = 16MB      */
-#define EBSZ_32                 0x0002          /* SDRAM External Bank Size = 32MB      */
-#define EBSZ_64                 0x0004          /* SDRAM External Bank Size = 64MB      */
-#define EBSZ_128                0x0006          /* SDRAM External Bank Size = 128MB             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000          /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010          /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020          /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030          /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001          /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002          /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004          /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008          /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010          /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020          /* Bus Grant Status                                             */
-
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001          /* DMA Channel Enable                                                   */
-#define WNR                             0x0002          /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000          /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004          /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008          /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010          /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020          /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040          /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080          /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000          /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100          /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200          /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300          /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400          /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500          /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600          /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700          /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800          /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900          /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000          /* Stop Mode                                                                    */
-#define DMAFLOW_AUTO            0x1000          /* Autobuffer Mode                                                              */
-#define DMAFLOW_ARRAY           0x4000          /* Descriptor Array Mode                                                */
-#define DMAFLOW_SMALL           0x6000          /* Small Model Descriptor List Mode                             */
-#define DMAFLOW_LARGE           0x7000          /* Large Model Descriptor List Mode                             */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001          /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002          /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C          /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030          /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040          /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080          /* PPI Packing Mode                                     */
-#define DMA32                   0x0100          /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200          /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400          /* PPI Skip Even/Odd Elements           */
-#define DLEN_8                  0x0000          /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800          /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000          /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800          /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000          /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800          /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000          /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800          /* Data Length = 16 Bits                        */
-#define DLENGTH                 0x3800          /* PPI Data Length  */
-#define POLC                    0x4000          /* PPI Clock Polarity                           */
-#define POLS                    0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400          /* Field Indicator                                      */
-#define FT_ERR                  0x0800          /* Frame Track Error                            */
-#define OVR                             0x1000          /* FIFO Overflow Error                          */
-#define UNDR                    0x2000          /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000          /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000          /* Error Not Corrected Indicator        */
-
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)            /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F          /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080          /* TWI Enable                                                                   */
-#define SCCB            0x0200          /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTRL Masks                                                                                                                 */
-#define SEN                     0x0001          /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002          /* Slave Address Length                                                 */
-#define STDVAL          0x0004          /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008          /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010          /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001          /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002          /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTRL Masks                                                                                                        */
-#define MEN                     0x0001          /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002          /* Master Address Length                                        */
-#define MDIR            0x0004          /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008          /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010          /* Issue Stop Condition                                         */
-#define RSTART          0x0020          /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0          /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000          /* Serial Data Override                                         */
-#define SCLOVR          0x8000          /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001          /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002          /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004          /* Address Not Acknowledged                                             */
-#define DNAK            0x0008          /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010          /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020          /* Buffer Write Error                                                   */
-#define SDASEN          0x0040          /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080          /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100          /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001          /* Slave Transfer Initiated     */
-#define SCOMP           0x0002          /* Slave Transfer Complete      */
-#define SERR            0x0004          /* Slave Transfer Error         */
-#define SOVF            0x0008          /* Slave Overflow                       */
-#define MCOMP           0x0010          /* Master Transfer Complete     */
-#define MERR            0x0020          /* Master Transfer Error        */
-#define XMTSERV         0x0040          /* Transmit FIFO Service        */
-#define RCVSERV         0x0080          /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001          /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002          /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004          /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008          /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003          /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000          /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001          /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003          /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C          /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000          /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004          /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C          /*              Receive FIFO Full (2 Bytes To Read)             */
-
-
-/* Omit CAN masks from defBF534.h */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001                  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000                  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001                  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000                  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002                  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004                  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008                  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000                  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008                  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010                  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000                  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010                  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020                  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000                  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020                  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040                  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000                  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040                  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080                  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000                  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080                  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100                  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000                  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100                  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200                  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000                  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200                  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400                  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000                  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400                  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800                  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000                  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800                  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000 
-#define _BOOTROM_FINAL_INIT 0xEF000002 
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-
-/* ==== end from defBF534.h ==== */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03400   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03404   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03408   /* HOST Acknowledge Mode Timeout Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc03500   /* Configuration Register */
-#define                        CNT_IMASK  0xffc03504   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc03508   /* Status Register */
-#define                      CNT_COMMAND  0xffc0350c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc03510   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc03514   /* Counter Register */
-#define                          CNT_MAX  0xffc03518   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0351c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc03600   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc03604   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc03608   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0360c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc03620   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc03624   /* Secure Control */
-#define                    SECURE_STATUS  0xffc03628   /* Secure Status */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc03680   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc03684   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc03688   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0368c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03700   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03704   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03708   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc0370c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03710   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03714   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03718   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc0371c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03720   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03724   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03728   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc0372c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03740   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03744   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03748   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc0374c   /* NAND Data Read Register */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_CNTR_HOST_EN  0x1        /* Host Enable */
-#define                  HOST_CNTR_nHOST_EN  0x0
-#define                  HOST_CNTR_HOST_END  0x2        /* Host Endianess */
-#define                 HOST_CNTR_nHOST_END  0x0
-#define                 HOST_CNTR_DATA_SIZE  0x4        /* Data Size */
-#define                HOST_CNTR_nDATA_SIZE  0x0
-#define                  HOST_CNTR_HOST_RST  0x8        /* Host Reset */
-#define                 HOST_CNTR_nHOST_RST  0x0
-#define                  HOST_CNTR_HRDY_OVR  0x20       /* Host Ready Override */
-#define                 HOST_CNTR_nHRDY_OVR  0x0
-#define                  HOST_CNTR_INT_MODE  0x40       /* Interrupt Mode */
-#define                 HOST_CNTR_nINT_MODE  0x0
-#define                     HOST_CNTR_BT_EN  0x80       /* Bus Timeout Enable */
-#define                   HOST_CNTR_ nBT_EN  0x0
-#define                       HOST_CNTR_EHW  0x100      /* Enable Host Write */
-#define                      HOST_CNTR_nEHW  0x0
-#define                       HOST_CNTR_EHR  0x200      /* Enable Host Read */
-#define                      HOST_CNTR_nEHR  0x0
-#define                       HOST_CNTR_BDR  0x400      /* Burst DMA Requests */
-#define                      HOST_CNTR_nBDR  0x0
-
-/* Bit masks for HOST_STATUS */
-
-#define                     HOST_STAT_READY  0x1        /* DMA Ready */
-#define                    HOST_STAT_nREADY  0x0
-#define                  HOST_STAT_FIFOFULL  0x2        /* FIFO Full */
-#define                 HOST_STAT_nFIFOFULL  0x0
-#define                 HOST_STAT_FIFOEMPTY  0x4        /* FIFO Empty */
-#define                HOST_STAT_nFIFOEMPTY  0x0
-#define                  HOST_STAT_COMPLETE  0x8        /* DMA Complete */
-#define                 HOST_STAT_nCOMPLETE  0x0
-#define                      HOST_STAT_HSHK  0x10       /* Host Handshake */
-#define                     HOST_STAT_nHSHK  0x0
-#define                   HOST_STAT_TIMEOUT  0x20       /* Host Timeout */
-#define                  HOST_STAT_nTIMEOUT  0x0
-#define                      HOST_STAT_HIRQ  0x40       /* Host Interrupt Request */
-#define                     HOST_STAT_nHIRQ  0x0
-#define                HOST_STAT_ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define               HOST_STAT_nALLOW_CNFG  0x0
-#define                   HOST_STAT_DMA_DIR  0x100      /* DMA Direction */
-#define                  HOST_STAT_nDMA_DIR  0x0
-#define                       HOST_STAT_BTE  0x200      /* Bus Timeout Enabled */
-#define                      HOST_STAT_nBTE  0x0
-#define               HOST_STAT_HOSTRD_DONE  0x8000     /* Host Read Completion Interrupt */
-#define              HOST_STAT_nHOSTRD_DONE  0x0
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             HOST_COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                     nCNTE  0x0       
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                     nDEBE  0x0       
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                   nCDGINV  0x0       
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                   nCUDINV  0x0       
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   nCZMINV  0x0       
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                     nZMZC  0x0       
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-#define                   nINPDIS  0x0       
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                     nICIE  0x0       
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                     nUCIE  0x0       
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                     nDCIE  0x0       
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                   nMINCIE  0x0       
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   nMAXCIE  0x0       
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                  nCOV31IE  0x0       
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                  nCOV15IE  0x0       
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                  nCZEROIE  0x0       
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    nCZMIE  0x0       
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                   nCZMEIE  0x0       
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-#define                   nCZMZIE  0x0       
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                     nICII  0x0       
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                     nUCII  0x0       
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                     nDCII  0x0       
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                   nMINCII  0x0       
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   nMAXCII  0x0       
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                  nCOV31II  0x0       
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                  nCOV15II  0x0       
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                  nCZEROII  0x0       
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    nCZMII  0x0       
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                   nCZMEII  0x0       
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-#define                   nCZMZII  0x0       
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-#define                 nW1ZMONCE  0x0       
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                     nFIEN  0x0       
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                 nFTESTDEC  0x0       
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                  nFWRTEST  0x0       
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                    nFRDEN  0x0       
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-#define                    nFWREN  0x0       
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    nFCOMP  0x0       
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                   nFERROR  0x0       
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                 nMMRGLOAD  0x0       
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                 nMMRGLOCK  0x0       
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-#define                   nFPGMEN  0x0       
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                  nEMUDABL  0x0       
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                  nRSTDABL  0x0       
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                  nDMA0OVR  0x0       
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                  nDMA1OVR  0x0       
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                   nEMUOVR  0x0       
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                   nOTPSEN  0x0       
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                  nSECURE0  0x0       
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                  nSECURE1  0x0       
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                  nSECURE2  0x0       
-#define                   SECURE3  0x8        /* SECURE 3 */
-#define                  nSECURE3  0x0       
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                      nNMI  0x0       
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                  nAFVALID  0x0       
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   nAFEXIT  0x0       
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   nNWIDTH  0x0       
-#define                   PG_SIZE  0x200      /* Page Size */
-#define                  nPG_SIZE  0x0       
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                    nNBUSY  0x0       
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                  nWB_FULL  0x0       
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define               nPG_WR_STAT  0x0       
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define               nPG_RD_STAT  0x0       
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-#define                 nWB_EMPTY  0x0       
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                 nNBUSYIRQ  0x0       
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   nWB_OVF  0x0       
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                  nWB_EDGE  0x0       
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   nRD_RDY  0x0       
-#define                   WR_DONE  0x10       /* Page Write Done */
-#define                  nWR_DONE  0x0       
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define             nMASK_BUSYIRQ  0x0       
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define               nMASK_WBOVF  0x0       
-#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define             nMASK_WBEMPTY  0x0       
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               nMASK_RDRDY  0x0       
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-#define              nMASK_WRDONE  0x0       
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-#define                  nECC_RST  0x0       
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define              nPG_RD_START  0x0       
-#define               PG_WR_START  0x2        /* Page Write Start */
-#define              nPG_WR_START  0x0       
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-
-#endif /* _DEF_BF52X_H */
diff --git a/include/asm-blackfin/mach-bf527/dma.h b/include/asm-blackfin/mach-bf527/dma.h
deleted file mode 100644
index 49dd693223e8..000000000000
--- a/include/asm-blackfin/mach-bf527/dma.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/dma.h
- * based on:    include/asm-blackfin/mach-bf537/dma.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * created:
- * description:
- *      system DMA map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 16
-
-#define CH_PPI                  0       /* PPI receive/transmit or NFC */
-#define CH_EMAC_RX              1       /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_HOSTDP          1       /* Ethernet MAC receive or HOSTDP */
-#define CH_EMAC_TX              2       /* Ethernet MAC transmit or NFC */
-#define CH_SPORT0_RX            3       /* SPORT0 receive */
-#define CH_SPORT0_TX            4       /* SPORT0 transmit */
-#define CH_SPORT1_RX            5       /* SPORT1 receive */
-#define CH_SPORT1_TX            6       /* SPORT1 transmit */
-#define CH_SPI                  7       /* SPI transmit/receive */
-#define CH_UART0_RX             8       /* UART0 receive */
-#define CH_UART0_TX             9       /* UART0 transmit */
-#define CH_UART1_RX             10      /* UART1 receive */
-#define CH_UART1_TX             11      /* UART1 transmit */
-
-#define CH_MEM_STREAM0_DEST     12      /* TX */
-#define CH_MEM_STREAM0_SRC      13      /* RX */
-#define CH_MEM_STREAM1_DEST     14      /* TX */
-#define CH_MEM_STREAM1_SRC      15      /* RX */
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define CH_NFC                  CH_PPI  /* PPI receive/transmit or NFC */
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define CH_NFC                  CH_EMAC_TX /* PPI receive/transmit or NFC */
-#endif
-
-#endif
diff --git a/include/asm-blackfin/mach-bf527/irq.h b/include/asm-blackfin/mach-bf527/irq.h
deleted file mode 100644
index 4e2b3f2020e5..000000000000
--- a/include/asm-blackfin/mach-bf527/irq.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf527/irq.h
- * based on:    include/asm-blackfin/mach-bf537/irq.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _BF527_IRQ_H_
-#define _BF527_IRQ_H_
-
-/*
- * Interrupt source definitions
-        Event Source    Core Event Name
-        Core        Emulation               **
-        Events         (highest priority)  EMU         0
-        Reset                   RST         1
-        NMI                     NMI         2
-        Exception               EVX         3
-        Reserved                --          4
-        Hardware Error          IVHW        5
-        Core Timer              IVTMR       6 *
-
-        .....
-
-         Software Interrupt 1    IVG14       31
-         Software Interrupt 2    --
-         (lowest priority)  IVG15       32 *
-*/
-
-#define NR_PERI_INTS    (2 * 32)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt */
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
-
-#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
-#define IRQ_DMA0_ERROR          BFIN_IRQ(1)     /* DMA Error 0 (generic) */
-#define IRQ_DMAR0_BLK           BFIN_IRQ(2)     /* DMAR0 Block Interrupt */
-#define IRQ_DMAR1_BLK           BFIN_IRQ(3)     /* DMAR1 Block Interrupt */
-#define IRQ_DMAR0_OVR           BFIN_IRQ(4)     /* DMAR0 Overflow Error */
-#define IRQ_DMAR1_OVR           BFIN_IRQ(5)     /* DMAR1 Overflow Error */
-#define IRQ_PPI_ERROR           BFIN_IRQ(6)     /* PPI Error */
-#define IRQ_MAC_ERROR           BFIN_IRQ(7)     /* MAC Status */
-#define IRQ_SPORT0_ERROR        BFIN_IRQ(8)     /* SPORT0 Status */
-#define IRQ_SPORT1_ERROR        BFIN_IRQ(9)     /* SPORT1 Status */
-#define IRQ_UART0_ERROR         BFIN_IRQ(12)    /* UART0 Status */
-#define IRQ_UART1_ERROR         BFIN_IRQ(13)    /* UART1 Status */
-#define IRQ_RTC                 BFIN_IRQ(14)    /* RTC */
-#define IRQ_PPI                 BFIN_IRQ(15)    /* DMA Channel 0 (PPI/NAND) */
-#define IRQ_SPORT0_RX           BFIN_IRQ(16)    /* DMA 3 Channel (SPORT0 RX) */
-#define IRQ_SPORT0_TX           BFIN_IRQ(17)    /* DMA 4 Channel (SPORT0 TX) */
-#define IRQ_SPORT1_RX           BFIN_IRQ(18)    /* DMA 5 Channel (SPORT1 RX) */
-#define IRQ_SPORT1_TX           BFIN_IRQ(19)    /* DMA 6 Channel (SPORT1 TX) */
-#define IRQ_TWI                 BFIN_IRQ(20)    /* TWI */
-#define IRQ_SPI                 BFIN_IRQ(21)    /* DMA 7 Channel (SPI) */
-#define IRQ_UART0_RX            BFIN_IRQ(22)    /* DMA8 Channel (UART0 RX) */
-#define IRQ_UART0_TX            BFIN_IRQ(23)    /* DMA9 Channel (UART0 TX) */
-#define IRQ_UART1_RX            BFIN_IRQ(24)    /* DMA10 Channel (UART1 RX) */
-#define IRQ_UART1_TX            BFIN_IRQ(25)    /* DMA11 Channel (UART1 TX) */
-#define IRQ_OPTSEC              BFIN_IRQ(26)    /* OTPSEC Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(27)    /* GP Counter */
-#define IRQ_MAC_RX              BFIN_IRQ(28)    /* DMA1 Channel (MAC RX/HDMA) */
-#define IRQ_PORTH_INTA          BFIN_IRQ(29)    /* Port H Interrupt A */
-#define IRQ_MAC_TX              BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_NFC                 BFIN_IRQ(30)    /* DMA2 Channel (MAC TX/NAND) */
-#define IRQ_PORTH_INTB          BFIN_IRQ(31)    /* Port H Interrupt B */
-#define IRQ_TMR0                BFIN_IRQ(32)    /* Timer 0 */
-#define IRQ_TMR1                BFIN_IRQ(33)    /* Timer 1 */
-#define IRQ_TMR2                BFIN_IRQ(34)    /* Timer 2 */
-#define IRQ_TMR3                BFIN_IRQ(35)    /* Timer 3 */
-#define IRQ_TMR4                BFIN_IRQ(36)    /* Timer 4 */
-#define IRQ_TMR5                BFIN_IRQ(37)    /* Timer 5 */
-#define IRQ_TMR6                BFIN_IRQ(38)    /* Timer 6 */
-#define IRQ_TMR7                BFIN_IRQ(39)    /* Timer 7 */
-#define IRQ_PORTG_INTA          BFIN_IRQ(40)    /* Port G Interrupt A */
-#define IRQ_PORTG_INTB          BFIN_IRQ(41)    /* Port G Interrupt B */
-#define IRQ_MEM_DMA0            BFIN_IRQ(42)    /* MDMA Stream 0 */
-#define IRQ_MEM_DMA1            BFIN_IRQ(43)    /* MDMA Stream 1 */
-#define IRQ_WATCH               BFIN_IRQ(44)    /* Software Watchdog Timer */
-#define IRQ_PORTF_INTA          BFIN_IRQ(45)    /* Port F Interrupt A */
-#define IRQ_PORTF_INTB          BFIN_IRQ(46)    /* Port F Interrupt B */
-#define IRQ_SPI_ERROR           BFIN_IRQ(47)    /* SPI Status */
-#define IRQ_NFC_ERROR           BFIN_IRQ(48)    /* NAND Error */
-#define IRQ_HDMA_ERROR          BFIN_IRQ(49)    /* HDMA Error */
-#define IRQ_HDMA                BFIN_IRQ(50)    /* HDMA (TFI) */
-#define IRQ_USB_EINT            BFIN_IRQ(51)    /* USB_EINT Interrupt */
-#define IRQ_USB_INT0            BFIN_IRQ(52)    /* USB_INT0 Interrupt */
-#define IRQ_USB_INT1            BFIN_IRQ(53)    /* USB_INT1 Interrupt */
-#define IRQ_USB_INT2            BFIN_IRQ(54)    /* USB_INT2 Interrupt */
-#define IRQ_USB_DMA             BFIN_IRQ(55)    /* USB_DMAINT Interrupt */
-
-#define SYS_IRQS                BFIN_IRQ(63)    /* 70 */
-
-#define IRQ_PF0         71
-#define IRQ_PF1         72
-#define IRQ_PF2         73
-#define IRQ_PF3         74
-#define IRQ_PF4         75
-#define IRQ_PF5         76
-#define IRQ_PF6         77
-#define IRQ_PF7         78
-#define IRQ_PF8         79
-#define IRQ_PF9         80
-#define IRQ_PF10        81
-#define IRQ_PF11        82
-#define IRQ_PF12        83
-#define IRQ_PF13        84
-#define IRQ_PF14        85
-#define IRQ_PF15        86
-
-#define IRQ_PG0         87
-#define IRQ_PG1         88
-#define IRQ_PG2         89
-#define IRQ_PG3         90
-#define IRQ_PG4         91
-#define IRQ_PG5         92
-#define IRQ_PG6         93
-#define IRQ_PG7         94
-#define IRQ_PG8         95
-#define IRQ_PG9         96
-#define IRQ_PG10        97
-#define IRQ_PG11        98
-#define IRQ_PG12        99
-#define IRQ_PG13        100
-#define IRQ_PG14        101
-#define IRQ_PG15        102
-
-#define IRQ_PH0         103
-#define IRQ_PH1         104
-#define IRQ_PH2         105
-#define IRQ_PH3         106
-#define IRQ_PH4         107
-#define IRQ_PH5         108
-#define IRQ_PH6         109
-#define IRQ_PH7         110
-#define IRQ_PH8         111
-#define IRQ_PH9         112
-#define IRQ_PH10        113
-#define IRQ_PH11        114
-#define IRQ_PH12        115
-#define IRQ_PH13        116
-#define IRQ_PH14        117
-#define IRQ_PH15        118
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define NR_IRQS     (IRQ_PH15+1)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS      0
-#define IRQ_DMA0_ERROR_POS      4
-#define IRQ_DMAR0_BLK_POS       8
-#define IRQ_DMAR1_BLK_POS       12
-#define IRQ_DMAR0_OVR_POS       16
-#define IRQ_DMAR1_OVR_POS       20
-#define IRQ_PPI_ERROR_POS       24
-#define IRQ_MAC_ERROR_POS       28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_SPORT0_ERROR_POS    0
-#define IRQ_SPORT1_ERROR_POS    4
-#define IRQ_UART0_ERROR_POS     16
-#define IRQ_UART1_ERROR_POS     20
-#define IRQ_RTC_POS             24
-#define IRQ_PPI_POS             28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_SPORT0_RX_POS       0
-#define IRQ_SPORT0_TX_POS       4
-#define IRQ_SPORT1_RX_POS       8
-#define IRQ_SPORT1_TX_POS       12
-#define IRQ_TWI_POS             16
-#define IRQ_SPI_POS             20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_UART1_RX_POS        0
-#define IRQ_UART1_TX_POS        4
-#define IRQ_OPTSEC_POS          8
-#define IRQ_CNT_POS             12
-#define IRQ_MAC_RX_POS          16
-#define IRQ_PORTH_INTA_POS      20
-#define IRQ_MAC_TX_POS          24
-#define IRQ_PORTH_INTB_POS      28
-
-/* IAR4 BIT FIELDS */
-#define IRQ_TMR0_POS            0
-#define IRQ_TMR1_POS            4
-#define IRQ_TMR2_POS            8
-#define IRQ_TMR3_POS            12
-#define IRQ_TMR4_POS            16
-#define IRQ_TMR5_POS            20
-#define IRQ_TMR6_POS            24
-#define IRQ_TMR7_POS            28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_PORTG_INTA_POS      0
-#define IRQ_PORTG_INTB_POS      4
-#define IRQ_MEM_DMA0_POS        8
-#define IRQ_MEM_DMA1_POS        12
-#define IRQ_WATCH_POS           16
-#define IRQ_PORTF_INTA_POS      20
-#define IRQ_PORTF_INTB_POS      24
-#define IRQ_SPI_ERROR_POS       28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_NFC_ERROR_POS       0
-#define IRQ_HDMA_ERROR_POS      4
-#define IRQ_HDMA_POS            8
-#define IRQ_USB_EINT_POS        12
-#define IRQ_USB_INT0_POS        16
-#define IRQ_USB_INT1_POS        20
-#define IRQ_USB_INT2_POS        24
-#define IRQ_USB_DMA_POS         28
-
-#endif                          /* _BF527_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf527/mem_init.h b/include/asm-blackfin/mach-bf527/mem_init.h
deleted file mode 100644
index cbe03f4a5698..000000000000
--- a/include/asm-blackfin/mach-bf527/mem_init.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf527/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75 || CONFIG_MEM_MT48LC32M16A2TG_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf527/mem_map.h b/include/asm-blackfin/mach-bf527/mem_map.h
deleted file mode 100644
index ef46dc991cd4..000000000000
--- a/include/asm-blackfin/mach-bf527/mem_map.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf527/mem_map.h
- * based on:    include/asm-blackfin/mach-bf537/mem_map.h
- * author:      Michael Hennerich (michael.hennerich@analog.com)
- *
- * created:
- * description:
- *      Memory MAP Common header file for blackfin BF527/5/2 of processors.
- * rev:
- *
- * modified:
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MEM_MAP_527_H_
-#define _MEM_MAP_527_H_
-
-#define COREMMR_BASE           0xFFE00000       /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000       /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x20300000      /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK2_BASE        0x20200000      /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK1_BASE        0x20100000      /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK0_BASE        0x20000000      /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x8000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF527 ADSP-BF525 ADSP-BF522 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif                          /*CONFIG_BFIN_DCACHE */
-
-/* Level 2 Memory - none */
-
-#define L2_START        0
-#define L2_LENGTH       0
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_527_H_ */
diff --git a/include/asm-blackfin/mach-bf527/portmux.h b/include/asm-blackfin/mach-bf527/portmux.h
deleted file mode 100644
index ae4d205bfcf5..000000000000
--- a/include/asm-blackfin/mach-bf527/portmux.h
+++ /dev/null
@@ -1,207 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if defined(CONFIG_BF527_SPORT0_PORTF)
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if defined(CONFIG_BF527_SPORT0_TSCLK_PG10)
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#elif defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_UART1_PORTF)
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_HWAIT         (P_DONTCARE)
-
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7               (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC           (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR     (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD       (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE       (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#elif defined(CONFIG_BF527_NAND_D_PORTH)
-#define P_NAND_D0       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1       (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2       (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5       (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6       (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7       (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE       (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE       (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE       (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB       (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE      (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0       (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1       (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2       (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5       (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6       (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7       (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8       (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9       (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10      (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11      (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12      (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13      (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14      (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO          (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL      (P_DONTCARE)
-#define P_TWI0_SDA      (P_DONTCARE)
-#define P_PPI0_FS1      (P_DONTCARE)
-#define P_TMR0          (P_DONTCARE)
-#define P_TMRCLK        (P_DONTCARE)
-#define P_PPI0_CLK      (P_DONTCARE)
-
-#define P_MII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxD2, \
-        P_MII0_ETxD3, \
-        P_MII0_ETxEN, \
-        P_MII0_TxCLK, \
-        P_MII0_PHYINT, \
-        P_MII0_COL, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxD2, \
-        P_MII0_ERxD3, \
-        P_MII0_ERxDV, \
-        P_MII0_ERxCLK, \
-        P_MII0_ERxER, \
-        P_MII0_CRS, \
-        P_MDC, \
-        P_MDIO, 0}
-
-#define P_RMII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxEN, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxER, \
-        P_RMII0_REF_CLK, \
-        P_RMII0_MDINT, \
-        P_RMII0_CRS_DV, \
-        P_MDC, \
-        P_MDIO, 0}
-
-#endif                          /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
deleted file mode 100644
index 8f7ea112fd3a..000000000000
--- a/include/asm-blackfin/mach-bf533/anomaly.h
+++ /dev/null
@@ -1,272 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf533/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning Serial Ports on with External Frame Syncs */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses When Stalled by Preceding Memory Read */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ < 4)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 4)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 4)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent Spurious Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ < 4)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (1)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (1)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (1)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (1)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (1)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (1)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available On Older Silicon) */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ >= 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-
-
-/* These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* Reserved bits in SYSCFG register not set at power on */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Trace Buffers may record discontinuities into emulation mode and/or exception, NMI, reset handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST_COMMAND initiated memory access may be incorrect if data cache or DMA is active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous exception when enabling cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL is not set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* An Infinite Stall occurs with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* The source MDMA descriptor may stop with a DMA Error */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from a 16-bit asynchronous memory device, the upper 8-bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal is active in Multi-channel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* A killed 32-bit System MMR write will lead to the next system MMR access thinking it should be 32-bit. */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT transmit data is not gated by external frame sync in certain conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* SDRAM auto-refresh and subsequent Power Ups */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB page miss can result in lost write-through cache data writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI resets the PPI configuration registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* PPI TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000323 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
deleted file mode 100644
index 12a416931991..000000000000
--- a/include/asm-blackfin/mach-bf533/bf533.h
+++ /dev/null
@@ -1,161 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/bf533.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF533_H__
-#define __MACH_BF533_H__
-
-#define SUPPORTED_REVID 2
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR            0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_BIT                   0x0FFFFFFF
-#define UART_ERROR_BIT                  0xF0FFFFFF
-#define SPORT1_ERROR_BIT                0xFF0FFFFF
-#define SPI_ERROR_BIT                   0xFFF0FFFF
-#define SPORT0_ERROR_BIT                0xFFFF0FFF
-#define PPI_ERROR_BIT                   0xFFFFF0FF
-#define DMA_ERROR_BIT                   0xFFFFFF0F
-#define PLLWAKE_ERROR_BIT               0xFFFFFFFF
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_BIT                 0x0FFFFFFF
-#define DMA6_UARTRX_BIT                 0xF0FFFFFF
-#define DMA5_SPI_BIT                    0xFF0FFFFF
-#define DMA4_SPORT1TX_BIT               0xFFF0FFFF
-#define DMA3_SPORT1RX_BIT               0xFFFF0FFF
-#define DMA2_SPORT0TX_BIT               0xFFFFF0FF
-#define DMA1_SPORT0RX_BIT               0xFFFFFF0F
-#define DMA0_PPI_BIT                    0xFFFFFFFF
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_BIT                     0x0FFFFFFF
-#define MEMDMA1_BIT                     0xF0FFFFFF
-#define MEMDMA0_BIT                     0xFF0FFFFF
-#define PFB_BIT                         0xFFF0FFFF
-#define PFA_BIT                         0xFFFF0FFF
-#define TIMER2_BIT                      0xFFFFF0FF
-#define TIMER1_BIT                      0xFFFFFF0F
-#define TIMER0_BIT                      0xFFFFFFFF
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF533
-#define CPU "BF533"
-#define CPUID 0x027a5000
-#endif
-#ifdef CONFIG_BF532
-#define CPU "BF532"
-#define CPUID 0x0275A000
-#endif
-#ifdef CONFIG_BF531
-#define CPU "BF531"
-#define CPUID 0x027a5000
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF533_H__  */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
deleted file mode 100644
index ebf592b59aab..000000000000
--- a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-# define CONFIG_SERIAL_BFIN_CTSRTS
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000230
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART_TX,
-        CH_UART_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        }
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-int nr_ports = BFIN_UART_NR_PORTS;
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf533/bfin_sir.h b/include/asm-blackfin/mach-bf533/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/include/asm-blackfin/mach-bf533/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        CH_UART_RX,
-        CH_UART_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
deleted file mode 100644
index d80971b4e3aa..000000000000
--- a/include/asm-blackfin/mach-bf533/blackfin.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF533_FAMILY
-
-#include "bf533.h"
-#include "mem_map.h"
-#include "defBF532.h"
-#include "anomaly.h"
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF532.h"
-#endif
-
-#define BFIN_UART_NR_PORTS      1
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-#endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
deleted file mode 100644
index 154655452d4c..000000000000
--- a/include/asm-blackfin/mach-bf533/cdefBF532.h
+++ /dev/null
@@ -1,767 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/cdefBF532.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF532_H
-#define _CDEF_BF532_H
-
-#include <asm/blackfin.h>
-
-/*include all Core registers and bit definitions*/
-#include "defBF532.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-#include <asm/system.h>
-
-/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
-#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-
-/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
-#define bfin_read_SWRST()                    bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
-#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
-#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
-#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
-#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
-
-/* DMA Traffic controls */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
-
-/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
-#define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
-#define bfin_read_FIO_MASKA_C()              bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val)          bfin_write16(FIO_MASKA_C,val)
-#define bfin_read_FIO_MASKA_S()              bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val)          bfin_write16(FIO_MASKA_S,val)
-#define bfin_read_FIO_MASKB_C()              bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val)          bfin_write16(FIO_MASKB_C,val)
-#define bfin_read_FIO_MASKB_S()              bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val)          bfin_write16(FIO_MASKB_S,val)
-#define bfin_read_FIO_POLAR()                bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val)            bfin_write16(FIO_POLAR,val)
-#define bfin_read_FIO_EDGE()                 bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val)             bfin_write16(FIO_EDGE,val)
-#define bfin_read_FIO_BOTH()                 bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val)             bfin_write16(FIO_BOTH,val)
-#define bfin_read_FIO_INEN()                 bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val)             bfin_write16(FIO_INEN,val)
-#define bfin_read_FIO_MASKA_D()              bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val)          bfin_write16(FIO_MASKA_D,val)
-#define bfin_read_FIO_MASKA_T()              bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val)          bfin_write16(FIO_MASKA_T,val)
-#define bfin_read_FIO_MASKB_D()              bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val)          bfin_write16(FIO_MASKB_D,val)
-#define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
-
-
-#if ANOMALY_05000311
-#define BFIN_WRITE_FIO_FLAG(name) \
-static __inline__ void bfin_write_FIO_FLAG_ ## name (unsigned short val)\
-{\
-        unsigned long flags;\
-        local_irq_save(flags);\
-        bfin_write16(FIO_FLAG_ ## name,val);\
-        bfin_read_CHIPID();\
-        local_irq_restore(flags);\
-}
-BFIN_WRITE_FIO_FLAG(D)
-BFIN_WRITE_FIO_FLAG(C)
-BFIN_WRITE_FIO_FLAG(S)
-BFIN_WRITE_FIO_FLAG(T)
-
-#define BFIN_READ_FIO_FLAG(name) \
-static __inline__ unsigned short bfin_read_FIO_FLAG_ ## name (void)\
-{\
-        unsigned long flags;\
-        unsigned short ret;\
-        local_irq_save(flags);\
-        ret = bfin_read16(FIO_FLAG_ ## name);\
-        bfin_read_CHIPID();\
-        local_irq_restore(flags);\
-        return ret;\
-}
-BFIN_READ_FIO_FLAG(D)
-BFIN_READ_FIO_FLAG(C)
-BFIN_READ_FIO_FLAG(S)
-BFIN_READ_FIO_FLAG(T)
-
-#else
-#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D,val)
-#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C,val)
-#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S,val)
-#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T,val)
-#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
-#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
-#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
-#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
-#endif
-
-
-/* DMA Controller */
-#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)      bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()      bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)  bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG()              bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)          bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()       bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR()          bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT()             bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)         bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT()             bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)         bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY()            bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)        bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY()            bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)        bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR()       bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR()           bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT()        bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)    bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT()        bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)    bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS()          bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)      bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()      bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)  bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG()              bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)          bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()       bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR()          bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT()             bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)         bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT()             bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)         bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY()            bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)        bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY()            bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)        bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR()       bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR()           bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT()        bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)    bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT()        bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)    bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS()          bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)      bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()      bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)  bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG()           bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)       bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()    bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR()       bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT()          bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)      bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT()          bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)      bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY()         bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)     bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY()         bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)     bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()    bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR()        bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()     bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()     bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()       bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)   bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()   bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG()           bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)       bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()    bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR()       bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT()          bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)      bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT()          bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)      bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY()         bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)     bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY()         bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)     bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()    bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR()        bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()     bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()     bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()       bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)   bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()   bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG()           bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)       bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()    bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR()       bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT()          bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)      bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT()          bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)      bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY()         bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)     bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY()         bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)     bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()    bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR()        bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()     bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()     bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()       bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)   bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()   bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG()           bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)       bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()    bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR()       bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT()          bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)      bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT()          bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)      bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY()         bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)     bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY()         bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)     bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()    bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR()        bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()     bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()     bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()       bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)   bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()   bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
-#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
-#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
-#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)
-
-/* UART Controller */
-#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
-/*
-#define UART_MSR
-*/
-#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
-
-/* SPI Controller */
-#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
-
-/* TIMER 0, 1, 2 Registers */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE()             bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)         bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE()            bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)        bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS()             bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)         bfin_write16(TIMER_STATUS,val)
-
-/* SPORT0 Controller */
-#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller */
-#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
-
-/* Parallel Peripheral Interface (PPI) */
-#define bfin_read_PPI_CONTROL()              bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)          bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS()               bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)           bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS()              bfin_read_PPI_STATUS()
-#define bfin_read_PPI_DELAY()                bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)            bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT()                bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)            bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
-
-#endif                          /* _CDEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
deleted file mode 100644
index 0ab4dd7494cf..000000000000
--- a/include/asm-blackfin/mach-bf533/defBF532.h
+++ /dev/null
@@ -1,1266 +0,0 @@
-/************************************************************************
- *
- * This file is subject to the terms and conditions of the GNU Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Non-GPL License also available as part of VisualDSP++
- * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
- *
- * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
- *
- * This file under source code control, please send bugs or changes to:
- * dsptools.support@analog.com
- *
- ************************************************************************/
-/*
- * File:         include/asm-blackfin/mach-bf533/defBF532.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
-
-#ifndef _DEF_BF532_H
-#define _DEF_BF532_H
-
-/* include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
-#define PLL_DIV                  0xFFC00004     /* PLL Divide Register (16-bit) */
-#define VR_CTL                   0xFFC00008     /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
-#define CHIPID                 0xFFC00014       /* Chip ID Register */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
-#define SWRST                   0xFFC00100  /* Software Reset Register (16-bit) */
-#define SYSCR                   0xFFC00104  /* System Configuration registe */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2 */
-#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register */
-#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register */
-
-/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register */
-
-/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Register (alternate macro) */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART_*.
- */
-#define BFIN_UART_THR                   0xFFC00400      /* Transmit Holding register */
-#define BFIN_UART_RBR                   0xFFC00400      /* Receive Buffer register */
-#define BFIN_UART_DLL                   0xFFC00400      /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER                   0xFFC00404      /* Interrupt Enable Register */
-#define BFIN_UART_DLH                   0xFFC00404      /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR                   0xFFC00408      /* Interrupt Identification Register */
-#define BFIN_UART_LCR                   0xFFC0040C      /* Line Control Register */
-#define BFIN_UART_MCR                   0xFFC00410      /* Modem Control Register */
-#define BFIN_UART_LSR                   0xFFC00414      /* Line Status Register */
-#if 0
-#define BFIN_UART_MSR                   0xFFC00418      /* Modem Status Register (UNUSED in ADSP-BF532) */
-#endif
-#define BFIN_UART_SCR                   0xFFC0041C      /* SCR Scratch Register */
-#define BFIN_UART_GCTL                  0xFFC00424      /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
-
-/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
-
-#define TIMER0_CONFIG                   0xFFC00600      /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                  0xFFC00604      /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                   0xFFC00608      /* Timer 0 Period Register */
-#define TIMER0_WIDTH                    0xFFC0060C      /* Timer 0 Width Register */
-
-#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
-#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
-#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
-#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
-
-#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
-#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
-#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
-#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
-
-#define TIMER_ENABLE                    0xFFC00640      /* Timer Enable Register */
-#define TIMER_DISABLE                   0xFFC00644      /* Timer Disable Register */
-#define TIMER_STATUS                    0xFFC00648      /* Timer Status Register */
-
-/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
-
-#define FIO_FLAG_D                      0xFFC00700      /* Flag Mask to directly specify state of pins */
-#define FIO_FLAG_C                      0xFFC00704      /* Peripheral Interrupt Flag Register (clear) */
-#define FIO_FLAG_S                      0xFFC00708      /* Peripheral Interrupt Flag Register (set) */
-#define FIO_FLAG_T                      0xFFC0070C      /* Flag Mask to directly toggle state of pins */
-#define FIO_MASKA_D                     0xFFC00710      /* Flag Mask Interrupt A Register (set directly) */
-#define FIO_MASKA_C                     0xFFC00714      /* Flag Mask Interrupt A Register (clear) */
-#define FIO_MASKA_S                     0xFFC00718      /* Flag Mask Interrupt A Register (set) */
-#define FIO_MASKA_T                     0xFFC0071C      /* Flag Mask Interrupt A Register (toggle) */
-#define FIO_MASKB_D                     0xFFC00720      /* Flag Mask Interrupt B Register (set directly) */
-#define FIO_MASKB_C                     0xFFC00724      /* Flag Mask Interrupt B Register (clear) */
-#define FIO_MASKB_S                     0xFFC00728      /* Flag Mask Interrupt B Register (set) */
-#define FIO_MASKB_T                     0xFFC0072C      /* Flag Mask Interrupt B Register (toggle) */
-#define FIO_DIR                         0xFFC00730      /* Peripheral Flag Direction Register */
-#define FIO_POLAR                       0xFFC00734      /* Flag Source Polarity Register */
-#define FIO_EDGE                        0xFFC00738      /* Flag Source Sensitivity Register */
-#define FIO_BOTH                        0xFFC0073C      /* Flag Set on BOTH Edges Register */
-#define FIO_INEN                                        0xFFC00740      /* Flag Input Enable Register  */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit  */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                    0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                    0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register */
-
-/* DMA Traffic controls */
-#define DMA_TC_PER 0xFFC00B0C   /* Traffic Control Periods Register */
-#define DMA_TC_CNT 0xFFC00B10   /* Traffic Control Current Counts Register */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
-#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
-#define DMA0_CONFIG             0xFFC00C08      /* DMA Channel 0 Configuration Register */
-#define DMA0_NEXT_DESC_PTR      0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR         0xFFC00C04      /* DMA Channel 0 Start Address Register */
-#define DMA0_X_COUNT            0xFFC00C10      /* DMA Channel 0 X Count Register */
-#define DMA0_Y_COUNT            0xFFC00C18      /* DMA Channel 0 Y Count Register */
-#define DMA0_X_MODIFY           0xFFC00C14      /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_MODIFY           0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR      0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR          0xFFC00C24      /* DMA Channel 0 Current Address Register */
-#define DMA0_CURR_X_COUNT       0xFFC00C30      /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT       0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
-#define DMA0_IRQ_STATUS         0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP     0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
-
-#define DMA1_CONFIG             0xFFC00C48      /* DMA Channel 1 Configuration Register */
-#define DMA1_NEXT_DESC_PTR      0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR         0xFFC00C44      /* DMA Channel 1 Start Address Register */
-#define DMA1_X_COUNT            0xFFC00C50      /* DMA Channel 1 X Count Register */
-#define DMA1_Y_COUNT            0xFFC00C58      /* DMA Channel 1 Y Count Register */
-#define DMA1_X_MODIFY           0xFFC00C54      /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_MODIFY           0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR      0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR          0xFFC00C64      /* DMA Channel 1 Current Address Register */
-#define DMA1_CURR_X_COUNT       0xFFC00C70      /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT       0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
-#define DMA1_IRQ_STATUS         0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP     0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
-
-#define DMA2_CONFIG             0xFFC00C88      /* DMA Channel 2 Configuration Register */
-#define DMA2_NEXT_DESC_PTR      0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR         0xFFC00C84      /* DMA Channel 2 Start Address Register */
-#define DMA2_X_COUNT            0xFFC00C90      /* DMA Channel 2 X Count Register */
-#define DMA2_Y_COUNT            0xFFC00C98      /* DMA Channel 2 Y Count Register */
-#define DMA2_X_MODIFY           0xFFC00C94      /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_MODIFY           0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR      0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR          0xFFC00CA4      /* DMA Channel 2 Current Address Register */
-#define DMA2_CURR_X_COUNT       0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT       0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
-#define DMA2_IRQ_STATUS         0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP     0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
-
-#define DMA3_CONFIG             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
-#define DMA3_NEXT_DESC_PTR      0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR         0xFFC00CC4      /* DMA Channel 3 Start Address Register */
-#define DMA3_X_COUNT            0xFFC00CD0      /* DMA Channel 3 X Count Register */
-#define DMA3_Y_COUNT            0xFFC00CD8      /* DMA Channel 3 Y Count Register */
-#define DMA3_X_MODIFY           0xFFC00CD4      /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_MODIFY           0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR      0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR          0xFFC00CE4      /* DMA Channel 3 Current Address Register */
-#define DMA3_CURR_X_COUNT       0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT       0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
-#define DMA3_IRQ_STATUS         0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP     0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
-
-#define DMA4_CONFIG             0xFFC00D08      /* DMA Channel 4 Configuration Register */
-#define DMA4_NEXT_DESC_PTR      0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR         0xFFC00D04      /* DMA Channel 4 Start Address Register */
-#define DMA4_X_COUNT            0xFFC00D10      /* DMA Channel 4 X Count Register */
-#define DMA4_Y_COUNT            0xFFC00D18      /* DMA Channel 4 Y Count Register */
-#define DMA4_X_MODIFY           0xFFC00D14      /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_MODIFY           0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR      0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR          0xFFC00D24      /* DMA Channel 4 Current Address Register */
-#define DMA4_CURR_X_COUNT       0xFFC00D30      /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT       0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
-#define DMA4_IRQ_STATUS         0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP     0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
-
-#define DMA5_CONFIG             0xFFC00D48      /* DMA Channel 5 Configuration Register */
-#define DMA5_NEXT_DESC_PTR      0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR         0xFFC00D44      /* DMA Channel 5 Start Address Register */
-#define DMA5_X_COUNT            0xFFC00D50      /* DMA Channel 5 X Count Register */
-#define DMA5_Y_COUNT            0xFFC00D58      /* DMA Channel 5 Y Count Register */
-#define DMA5_X_MODIFY           0xFFC00D54      /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_MODIFY           0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR      0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR          0xFFC00D64      /* DMA Channel 5 Current Address Register */
-#define DMA5_CURR_X_COUNT       0xFFC00D70      /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT       0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
-#define DMA5_IRQ_STATUS         0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP     0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
-
-#define DMA6_CONFIG             0xFFC00D88      /* DMA Channel 6 Configuration Register */
-#define DMA6_NEXT_DESC_PTR      0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR         0xFFC00D84      /* DMA Channel 6 Start Address Register */
-#define DMA6_X_COUNT            0xFFC00D90      /* DMA Channel 6 X Count Register */
-#define DMA6_Y_COUNT            0xFFC00D98      /* DMA Channel 6 Y Count Register */
-#define DMA6_X_MODIFY           0xFFC00D94      /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_MODIFY           0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR      0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR          0xFFC00DA4      /* DMA Channel 6 Current Address Register */
-#define DMA6_CURR_X_COUNT       0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT       0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
-#define DMA6_IRQ_STATUS         0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP     0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
-
-#define DMA7_CONFIG             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
-#define DMA7_NEXT_DESC_PTR      0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR         0xFFC00DC4      /* DMA Channel 7 Start Address Register */
-#define DMA7_X_COUNT            0xFFC00DD0      /* DMA Channel 7 X Count Register */
-#define DMA7_Y_COUNT            0xFFC00DD8      /* DMA Channel 7 Y Count Register */
-#define DMA7_X_MODIFY           0xFFC00DD4      /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_MODIFY           0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR      0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR          0xFFC00DE4      /* DMA Channel 7 Current Address Register */
-#define DMA7_CURR_X_COUNT       0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT       0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
-#define DMA7_IRQ_STATUS         0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP     0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
-
-#define MDMA_D1_CONFIG          0xFFC00E88      /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00E80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR      0xFFC00E84      /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_X_COUNT         0xFFC00E90      /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_Y_COUNT         0xFFC00E98      /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_X_MODIFY        0xFFC00E94      /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_MODIFY        0xFFC00E9C      /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00EA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR       0xFFC00EA4      /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00EB0      /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00EB8      /* MemDMA Stream 1 Destination Current Y Count Register */
-#define MDMA_D1_IRQ_STATUS      0xFFC00EA8      /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00EAC      /* MemDMA Stream 1 Destination Peripheral Map Register */
-
-#define MDMA_S1_CONFIG          0xFFC00EC8      /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00EC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR      0xFFC00EC4      /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_X_COUNT         0xFFC00ED0      /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_Y_COUNT         0xFFC00ED8      /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_X_MODIFY        0xFFC00ED4      /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_MODIFY        0xFFC00EDC      /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00EE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR       0xFFC00EE4      /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00EF0      /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00EF8      /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_S1_IRQ_STATUS      0xFFC00EE8      /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00EEC      /* MemDMA Stream 1 Source Peripheral Map Register */
-
-#define MDMA_D0_CONFIG          0xFFC00E08      /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00E00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR      0xFFC00E04      /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_X_COUNT         0xFFC00E10      /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_Y_COUNT         0xFFC00E18      /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_X_MODIFY        0xFFC00E14      /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_MODIFY        0xFFC00E1C      /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00E20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR       0xFFC00E24      /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00E30      /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00E38      /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_D0_IRQ_STATUS      0xFFC00E28      /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00E2C      /* MemDMA Stream 0 Destination Peripheral Map Register */
-
-#define MDMA_S0_CONFIG          0xFFC00E48      /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00E40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR      0xFFC00E44      /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_X_COUNT         0xFFC00E50      /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_Y_COUNT         0xFFC00E58      /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_X_MODIFY        0xFFC00E54      /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_MODIFY        0xFFC00E5C      /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00E60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR       0xFFC00E64      /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00E70      /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00E78      /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_S0_IRQ_STATUS      0xFFC00E68      /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00E6C      /* MemDMA Stream 0 Source Peripheral Map Register */
-
-/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
-
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN                       0x0000  /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2                  0x0001  /* Pass CLKIN/2 to PLL */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                         0x0002  /* Shut off PLL clocks */
-#define STOPCK_OFF                      0x0008  /* Core clock off */
-#define STOPCK                          0x0008  /* Core Clock Off                                                                       */
-#define PDWN                            0x0020  /* Put the PLL in a Deep Sleep state */
-#if !defined(__ADSPBF538__)
-/* this file is included in defBF538.h but IN_DELAY/OUT_DELAY are different */
-# define IN_DELAY        0x0040  /* Add 200ps Delay To EBIU Input Latches */
-# define OUT_DELAY       0x0080  /* Add 200ps Delay To EBIU Output Signals */
-#endif
-#define BYPASS                          0x0100  /* Bypass the PLL */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks */
-#define SSEL                            0x000F  /* System Select                                                */
-#define CSEL                            0x0030  /* Core Select                                                  */
-
-#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
-
-#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)                     ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Mask */
-#define SYSTEM_RESET    0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT    0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE    0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE  0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                   0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                  0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-    /* SIC_IAR0 Masks */
-
-#define P0_IVG(x)    ((x)-7)    /* Peripheral #0 assigned IVG #x  */
-#define P1_IVG(x)    ((x)-7) << 0x4     /* Peripheral #1 assigned IVG #x  */
-#define P2_IVG(x)    ((x)-7) << 0x8     /* Peripheral #2 assigned IVG #x  */
-#define P3_IVG(x)    ((x)-7) << 0xC     /* Peripheral #3 assigned IVG #x  */
-#define P4_IVG(x)    ((x)-7) << 0x10    /* Peripheral #4 assigned IVG #x  */
-#define P5_IVG(x)    ((x)-7) << 0x14    /* Peripheral #5 assigned IVG #x  */
-#define P6_IVG(x)    ((x)-7) << 0x18    /* Peripheral #6 assigned IVG #x  */
-#define P7_IVG(x)    ((x)-7) << 0x1C    /* Peripheral #7 assigned IVG #x  */
-
-/* SIC_IAR1 Masks */
-
-#define P8_IVG(x)     ((x)-7)   /* Peripheral #8 assigned IVG #x  */
-#define P9_IVG(x)     ((x)-7) << 0x4    /* Peripheral #9 assigned IVG #x  */
-#define P10_IVG(x)    ((x)-7) << 0x8    /* Peripheral #10 assigned IVG #x  */
-#define P11_IVG(x)    ((x)-7) << 0xC    /* Peripheral #11 assigned IVG #x  */
-#define P12_IVG(x)    ((x)-7) << 0x10   /* Peripheral #12 assigned IVG #x  */
-#define P13_IVG(x)    ((x)-7) << 0x14   /* Peripheral #13 assigned IVG #x  */
-#define P14_IVG(x)    ((x)-7) << 0x18   /* Peripheral #14 assigned IVG #x  */
-#define P15_IVG(x)    ((x)-7) << 0x1C   /* Peripheral #15 assigned IVG #x  */
-
-/* SIC_IAR2 Masks */
-#define P16_IVG(x)    ((x)-7)   /* Peripheral #16 assigned IVG #x  */
-#define P17_IVG(x)    ((x)-7) << 0x4    /* Peripheral #17 assigned IVG #x  */
-#define P18_IVG(x)    ((x)-7) << 0x8    /* Peripheral #18 assigned IVG #x  */
-#define P19_IVG(x)    ((x)-7) << 0xC    /* Peripheral #19 assigned IVG #x  */
-#define P20_IVG(x)    ((x)-7) << 0x10   /* Peripheral #20 assigned IVG #x  */
-#define P21_IVG(x)    ((x)-7) << 0x14   /* Peripheral #21 assigned IVG #x  */
-#define P22_IVG(x)    ((x)-7) << 0x18   /* Peripheral #22 assigned IVG #x  */
-#define P23_IVG(x)    ((x)-7) << 0x1C   /* Peripheral #23 assigned IVG #x  */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
-#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001         /* TX enable  */
-#define ITCLK    0x0002         /* Internal TX Clock Select  */
-#define TDTYPE   0x000C         /* TX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define TLSBIT   0x0010         /* TX Bit Order */
-#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400         /* TX Frame Sync Required Select  */
-#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000         /* Low TX Frame Sync Select  */
-#define LATFS    0x2000         /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || \
-    defined(__ADSPBF533__)
-# define SLEN       0x001F      /*TX Word Length  */
-#else
-# define SLEN(x)                ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#endif
-#define TXSE        0x0100      /*TX Secondary Enable */
-#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400      /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001         /* RX enable  */
-#define IRCLK    0x0002         /* Internal RX Clock Select  */
-#define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define DTYPE_NORM      0x0000          /* no companding                                                        */
-#define DTYPE_ULAW      0x0008          /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C          /* Compand Using A-Law                                                  */
-#define RLSBIT   0x0010         /* RX Bit Order */
-#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400         /* RX Frame Sync Required Select  */
-#define LRFS     0x1000         /* Low RX Frame Sync Select  */
-#define LARFS    0x2000         /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-/* SLEN defined above */
-#define RXSE        0x0100      /*RX Secondary Enable */
-#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400      /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001  /*RX FIFO Not Empty Status */
-#define RUVF            0x0002  /*RX Underflow Status */
-#define ROVF            0x0004  /*RX Overflow Status */
-#define TXF             0x0008  /*TX FIFO Full Status */
-#define TUVF            0x0010  /*TX Underflow Status */
-#define TOVF            0x0020  /*TX Overflow Status */
-#define TXHRE           0x0040  /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
-#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SET_SP_WOFF(x)  ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-/* Only use SET_WSIZE Macro With Logic OR While Setting Lower Order Bits                                                */
-#define SET_SP_WSIZE(x) (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define REC_BYPASS      0x0000          /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002          /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003          /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
-#define MFD_0           0x0000          /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000          /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000          /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000          /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000          /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000          /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000          /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000          /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000          /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000          /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000          /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000          /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000          /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000          /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000          /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000          /* Multichannel Frame Delay = 15                                */
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-
-/*  PPI_CONTROL Masks         */
-#define PORT_EN              0x00000001 /* PPI Port Enable  */
-#define PORT_DIR             0x00000002 /* PPI Port Direction       */
-#define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
-#define PORT_CFG             0x00000030 /* PPI Port Configuration */
-#define FLD_SEL              0x00000040 /* PPI Active Field Select */
-#define PACK_EN              0x00000080 /* PPI Packing Mode */
-#define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH              0x00003800 /* PPI Data Length  */
-#define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
-#define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#define POL                  0x0000C000 /* PPI Signal Polarities       */
-#define POLC            0x4000          /* PPI Clock Polarity                           */
-#define POLS            0x8000          /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                          */
-#define FLD                  0x00000400 /* Field Indicator   */
-#define FT_ERR               0x00000800 /* Frame Track Error */
-#define OVR                  0x00001000 /* FIFO Overflow Error */
-#define UNDR                 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET              0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
-
-/* **********  DMA CONTROLLER MASKS  *********************8 */
-
-/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
-#define DMAEN           0x00000001      /* Channel Enable */
-#define WNR             0x00000002      /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
-#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
-#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
-#define DMA2D           0x00000010      /* 2D/1D* Mode */
-#define RESTART         0x00000020      /* Restart */
-#define DI_SEL          0x00000040      /* Data Interrupt Select */
-#define DI_EN           0x00000080      /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE          0x00000900      /* Next Descriptor Size */
-#define DMAFLOW         0x00007000      /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P                 0       /* Channel Enable */
-#define WNR_P                   1       /* Channel Direction (W/R*) */
-#define DMA2D_P                 4       /* 2D/1D* Mode */
-#define RESTART_P               5       /* Restart */
-#define DI_SEL_P                6       /* Data Interrupt Select */
-#define DI_EN_P                 7       /* Data Interrupt Enable */
-
-/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE                0x00000001      /* DMA Done Indicator */
-#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
-#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
-#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
-
-#define DMA_DONE_P              0       /* DMA Done Indicator */
-#define DMA_ERR_P               1       /* DMA Error Indicator */
-#define DFETCH_P                2       /* Descriptor Fetch Indicator */
-#define DMA_RUN_P               3       /* DMA Running Indicator */
-
-/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE               0x00000040  /* DMA Channel Type Indicator */
-#define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
-#define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
-#define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
-#define PMAP                0x00007000  /* DMA Peripheral Map Field */
-
-#define PMAP_PPI                0x0000  /* PMAP PPI Port DMA */
-#define PMAP_SPORT0RX           0x1000  /* PMAP SPORT0 Receive DMA */
-#define PMAP_SPORT0TX           0x2000  /* PMAP SPORT0 Transmit DMA */
-#define PMAP_SPORT1RX           0x3000  /* PMAP SPORT1 Receive DMA */
-#define PMAP_SPORT1TX           0x4000  /* PMAP SPORT1 Transmit DMA */
-#define PMAP_SPI                0x5000  /* PMAP SPI DMA */
-#define PMAP_UARTRX             0x6000  /* PMAP UART Receive DMA */
-#define PMAP_UARTTX             0x7000  /* PMAP UART Transmit DMA */
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0  0x0001
-#define TIMEN1  0x0002
-#define TIMEN2  0x0004
-
-#define TIMEN0_P        0x00
-#define TIMEN1_P        0x01
-#define TIMEN2_P        0x02
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0 0x0001
-#define TIMDIS1 0x0002
-#define TIMDIS2 0x0004
-
-#define TIMDIS0_P       0x00
-#define TIMDIS1_P       0x01
-#define TIMDIS2_P       0x02
-
-/* TIMER_STATUS Register */
-#define TIMIL0          0x0001
-#define TIMIL1          0x0002
-#define TIMIL2          0x0004
-#define TOVF_ERR0               0x0010  /* Timer 0 Counter Overflow             */
-#define TOVF_ERR1               0x0020  /* Timer 1 Counter Overflow             */
-#define TOVF_ERR2               0x0040  /* Timer 2 Counter Overflow             */
-#define TRUN0           0x1000
-#define TRUN1           0x2000
-#define TRUN2           0x4000
-
-#define TIMIL0_P        0x00
-#define TIMIL1_P        0x01
-#define TIMIL2_P        0x02
-#define TOVF_ERR0_P             0x04
-#define TOVF_ERR1_P             0x05
-#define TOVF_ERR2_P             0x06
-#define TRUN0_P         0x0C
-#define TRUN1_P         0x0D
-#define TRUN2_P         0x0E
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0               TOVF_ERR0
-#define TOVL_ERR1               TOVF_ERR1
-#define TOVL_ERR2               TOVF_ERR2
-#define TOVL_ERR0_P             TOVF_ERR0_P
-#define TOVL_ERR1_P             TOVF_ERR1_P
-#define TOVL_ERR2_P             TOVF_ERR2_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT         0x0001
-#define WDTH_CAP        0x0002
-#define EXT_CLK         0x0003
-#define PULSE_HI        0x0004
-#define PERIOD_CNT      0x0008
-#define IRQ_ENA         0x0010
-#define TIN_SEL         0x0020
-#define OUT_DIS         0x0040
-#define CLK_SEL         0x0080
-#define TOGGLE_HI       0x0100
-#define EMU_RUN         0x0200
-#define ERR_TYP(x)      ((x & 0x03) << 14)
-
-#define TMODE_P0                0x00
-#define TMODE_P1                0x01
-#define PULSE_HI_P              0x02
-#define PERIOD_CNT_P            0x03
-#define IRQ_ENA_P               0x04
-#define TIN_SEL_P               0x05
-#define OUT_DIS_P               0x06
-#define CLK_SEL_P               0x07
-#define TOGGLE_HI_P             0x08
-#define EMU_RUN_P               0x09
-#define ERR_TYP_P0              0x0E
-#define ERR_TYP_P1              0x0F
-
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-
-/* SPI_CTL Masks */
-#define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
-#define RDBR_CORE       0x0000          /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define TDBR_CORE       0x0001          /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA        0x0002          /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA        0x0003          /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
-#define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
-#define SIZE                   0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR                   0x00001000       /* Configures SPI as master (=1) or slave (=0) */
-#define WOM                    0x00002000       /* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE                    0x00004000       /* SPI module enable (=1), disable (=0) */
-
-/* SPI_FLG Masks */
-#define FLS1                   0x00000002       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2                   0x00000004       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3                   0x00000008       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4                   0x00000010       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5                   0x00000020       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6                   0x00000040       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7                   0x00000080       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1                   0x00000200       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2                   0x00000400       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3                   0x00000800       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4                   0x00001000       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5                   0x00002000       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6                   0x00004000       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7                   0x00008000       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P                 0x00000001       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P                 0x00000002       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P                 0x00000003       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P                 0x00000004       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P                 0x00000005       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P                 0x00000006       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P                 0x00000007       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P                 0x00000009       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P                 0x0000000A       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P                 0x0000000B       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P                 0x0000000C       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P                 0x0000000D       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P                 0x0000000E       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P                 0x0000000F       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF                   0x00000001       /* Set (=1) when SPI single-word transfer complete */
-#define MODF                   0x00000002       /* Set (=1) in a master device when some other device tries to become master */
-#define TXE                    0x00000004       /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS                    0x00000008       /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY                   0x00000010       /* Set (=1) when data is received with RDBR full */
-#define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
-
-/* SPIx_FLG Masks                                                                                                                                       */
-#define FLG1E   0xFDFF          /* Activates SPI_FLOUT1                                                         */
-#define FLG2E   0xFBFF          /* Activates SPI_FLOUT2                                                         */
-#define FLG3E   0xF7FF          /* Activates SPI_FLOUT3                                                         */
-#define FLG4E   0xEFFF          /* Activates SPI_FLOUT4                                                         */
-#define FLG5E   0xDFFF          /* Activates SPI_FLOUT5                                                         */
-#define FLG6E   0xBFFF          /* Activates SPI_FLOUT6                                                         */
-#define FLG7E   0x7FFF          /* Activates SPI_FLOUT7                                                         */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN                  0x00000001      /* Enable CLKOUT */
-#define AMBEN_NONE              0x00000000      /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x00000002      /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1             0x00000004      /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2          0x00000006      /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL               0x00000008      /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P                0x00000000      /* Enable CLKOUT */
-#define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-
-/* SDGCTL Masks */
-#define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
-#define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
-#define PFE                     0x00000010      /* Enable SDRAM prefetch */
-#define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
-#define PUPSD                   0x00200000      /*Power-up start delay */
-#define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
-#define EBUFE                   0x02000000      /* Enable external buffering timing */
-#define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
-#define EMREN                   0x10000000      /* Extended mode register enable */
-#define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
-#define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EBE                     0x00000001      /* Enable SDRAM external bank */
-#define EBSZ_16                 0x00000000      /* SDRAM external bank size = 16MB */
-#define EBSZ_32                 0x00000002      /* SDRAM external bank size = 32MB */
-#define EBSZ_64                 0x00000004      /* SDRAM external bank size = 64MB */
-#define EBSZ_128                        0x00000006      /* SDRAM external bank size = 128MB */
-#define EBCAW_8                 0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EBCAW_9                 0x00000010      /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_10                        0x00000020      /* SDRAM external bank column address width = 9 bits */
-#define EBCAW_11                        0x00000030      /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI                    0x00000001      /* SDRAM controller is idle  */
-#define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
-#define SDPUA                   0x00000004      /* SDRAM power up active  */
-#define SDRS                    0x00000008      /* SDRAM is in reset state */
-#define SDEASE                0x00000010        /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT                  0x00000020      /* Bus granted */
-
-
-#endif                          /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
deleted file mode 100644
index bd9d5e94307d..000000000000
--- a/include/asm-blackfin/mach-bf533/dma.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*****************************************************************************
-*
-*        BF-533/2/1 Specific Declarations
-*
-****************************************************************************/
-/*
- * File:         include/asm-blackfin/mach-bf533/dma.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 12
-
-#define CH_PPI          0
-#define CH_SPORT0_RX    1
-#define CH_SPORT0_TX    2
-#define CH_SPORT1_RX    3
-#define CH_SPORT1_TX    4
-#define CH_SPI          5
-#define CH_UART_RX      6
-#define CH_UART_TX      7
-#define CH_MEM_STREAM0_DEST     8        /* TX */
-#define CH_MEM_STREAM0_SRC      9        /* RX */
-#define CH_MEM_STREAM1_DEST     10       /* TX */
-#define CH_MEM_STREAM1_SRC      11       /* RX */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
deleted file mode 100644
index 5aa38e5da6b7..000000000000
--- a/include/asm-blackfin/mach-bf533/irq.h
+++ /dev/null
@@ -1,173 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/defBF532.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BF533_IRQ_H_
-#define _BF533_IRQ_H_
-
-/*
- * Interrupt source definitions
-             Event Source    Core Event Name
-Core        Emulation               **
- Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-            PLL Wakeup Interrupt    IVG7        7
-            DMA Error (generic)     IVG7        8
-            PPI Error Interrupt     IVG7        9
-            SPORT0 Error Interrupt  IVG7        10
-            SPORT1 Error Interrupt  IVG7        11
-            SPI Error Interrupt     IVG7        12
-            UART Error Interrupt    IVG7        13
-            RTC Interrupt           IVG8        14
-            DMA0 Interrupt (PPI)    IVG8        15
-            DMA1 (SPORT0 RX)        IVG9        16
-            DMA2 (SPORT0 TX)        IVG9        17
-            DMA3 (SPORT1 RX)        IVG9        18
-            DMA4 (SPORT1 TX)        IVG9        19
-            DMA5 (PPI)              IVG10       20
-            DMA6 (UART RX)          IVG10       21
-            DMA7 (UART TX)          IVG10       22
-            Timer0                  IVG11       23
-            Timer1                  IVG11       24
-            Timer2                  IVG11       25
-            PF Interrupt A          IVG12       26
-            PF Interrupt B          IVG12       27
-            DMA8/9 Interrupt        IVG13       28
-            DMA10/11 Interrupt      IVG13       29
-            Watchdog Timer          IVG13       30
-
-            Softirq                 IVG14       31
-            System Call    --
-                 (lowest priority)  IVG15       32 *
- */
-#define SYS_IRQS        31
-#define NR_PERI_INTS    24
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /*Emulation */
-#define IRQ_RST                 1       /*reset */
-#define IRQ_NMI                 2       /*Non Maskable */
-#define IRQ_EVX                 3       /*Exception */
-#define IRQ_UNUSED              4       /*- unused interrupt*/
-#define IRQ_HWERR               5       /*Hardware Error */
-#define IRQ_CORETMR             6       /*Core timer */
-
-#define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR           8       /*DMA Error (general) */
-#define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
-#define IRQ_UART_ERROR          13      /*UART Error Interrupt */
-#define IRQ_RTC                 14      /*RTC Interrupt */
-#define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
-#define         IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
-#define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
-#define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
-#define IRQ_TMR0                23      /*Timer 0 */
-#define IRQ_TMR1                24      /*Timer 1 */
-#define IRQ_TMR2                25      /*Timer 2 */
-#define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
-#define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
-#define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
-#define IRQ_WATCH               30      /*Watch Dog Timer */
-
-#define IRQ_PF0                 33
-#define IRQ_PF1                 34
-#define IRQ_PF2                 35
-#define IRQ_PF3                 36
-#define IRQ_PF4                 37
-#define IRQ_PF5                 38
-#define IRQ_PF6                 39
-#define IRQ_PF7                 40
-#define IRQ_PF8                 41
-#define IRQ_PF9                 42
-#define IRQ_PF10                43
-#define IRQ_PF11                44
-#define IRQ_PF12                45
-#define IRQ_PF13                46
-#define IRQ_PF14                47
-#define IRQ_PF15                48
-
-#define GPIO_IRQ_BASE           IRQ_PF0
-
-#define NR_IRQS         (IRQ_PF15+1)
-
-#define IVG7                    7
-#define IVG8                    8
-#define IVG9                    9
-#define IVG10                   10
-#define IVG11                   11
-#define IVG12                   12
-#define IVG13                   13
-#define IVG14                   14
-#define IVG15                   15
-
-/* IAR0 BIT FIELDS*/
-#define RTC_ERROR_POS                   28
-#define UART_ERROR_POS                  24
-#define SPORT1_ERROR_POS                20
-#define SPI_ERROR_POS                   16
-#define SPORT0_ERROR_POS                12
-#define PPI_ERROR_POS                   8
-#define DMA_ERROR_POS                   4
-#define PLLWAKE_ERROR_POS               0
-
-/* IAR1 BIT FIELDS*/
-#define DMA7_UARTTX_POS                 28
-#define DMA6_UARTRX_POS                 24
-#define DMA5_SPI_POS                    20
-#define DMA4_SPORT1TX_POS               16
-#define DMA3_SPORT1RX_POS               12
-#define DMA2_SPORT0TX_POS               8
-#define DMA1_SPORT0RX_POS               4
-#define DMA0_PPI_POS                    0
-
-/* IAR2 BIT FIELDS*/
-#define WDTIMER_POS                     28
-#define MEMDMA1_POS                     24
-#define MEMDMA0_POS                     20
-#define PFB_POS                         16
-#define PFA_POS                         12
-#define TIMER2_POS                      8
-#define TIMER1_POS                      4
-#define TIMER0_POS                      0
-
-#endif                          /* _BF533_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
deleted file mode 100644
index ed2034bf10ec..000000000000
--- a/include/asm-blackfin/mach-bf533/mem_init.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || \
-     CONFIG_MEM_MT48LC32M16A2TG_75 || CONFIG_MEM_GENERIC_BOARD)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
deleted file mode 100644
index 581fc6eea789..000000000000
--- a/include/asm-blackfin/mach-bf533/mem_map.h
+++ /dev/null
@@ -1,171 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf533/mem_map.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MEM_MAP_533_H_
-#define _MEM_MAP_533_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x400
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF533 processors */
-
-#ifdef CONFIG_BF533
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH      (0x14000 - 0x4000)
-#else
-#define L1_CODE_LENGTH      0x14000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF532 processors */
-
-#ifdef CONFIG_BF532
-#define L1_CODE_START       0xFFA08000
-#define L1_DATA_A_START     0xFF804000
-#define L1_DATA_B_START     0xFF904000
-
-#ifdef CONFIG_BFIN_ICACHE
-#define L1_CODE_LENGTH      (0xC000 - 0x4000)
-#else
-#define L1_CODE_LENGTH      0xC000
-#endif
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x4000
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Memory Map for ADSP-BF531 processors */
-
-#ifdef CONFIG_BF531
-#define L1_CODE_START       0xFFA08000
-#define L1_DATA_A_START     0xFF804000
-#define L1_DATA_B_START     0xFF904000
-#define L1_CODE_LENGTH      0x4000
-#define L1_DATA_B_LENGTH      0x0000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB  | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB  | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif
-
-#endif
-
-/* Level 2 Memory - none */
-
-#define L2_START        0
-#define L2_LENGTH       0
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf533/portmux.h b/include/asm-blackfin/mach-bf533/portmux.h
deleted file mode 100644
index 685a2651dcda..000000000000
--- a/include/asm-blackfin/mach-bf533/portmux.h
+++ /dev/null
@@ -1,67 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK      (P_DONTCARE)
-#define P_PPI0_FS1      (P_DONTCARE)
-#define P_PPI0_FS2      (P_DONTCARE)
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0       (P_DONTCARE)
-#define P_PPI0_D1       (P_DONTCARE)
-#define P_PPI0_D2       (P_DONTCARE)
-#define P_PPI0_D3       (P_DONTCARE)
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK  (P_DONTCARE)
-#define P_SPORT1_RSCLK  (P_DONTCARE)
-#define P_SPORT0_TSCLK  (P_DONTCARE)
-#define P_SPORT0_RSCLK  (P_DONTCARE)
-#define P_UART0_RX      (P_DONTCARE)
-#define P_UART0_TX      (P_DONTCARE)
-#define P_SPORT1_DRSEC  (P_DONTCARE)
-#define P_SPORT1_RFS    (P_DONTCARE)
-#define P_SPORT1_DTPRI  (P_DONTCARE)
-#define P_SPORT1_DTSEC  (P_DONTCARE)
-#define P_SPORT1_TFS    (P_DONTCARE)
-#define P_SPORT1_DRPRI  (P_DONTCARE)
-#define P_SPORT0_DRSEC  (P_DONTCARE)
-#define P_SPORT0_RFS    (P_DONTCARE)
-#define P_SPORT0_DTPRI  (P_DONTCARE)
-#define P_SPORT0_DTSEC  (P_DONTCARE)
-#define P_SPORT0_TFS    (P_DONTCARE)
-#define P_SPORT0_DRPRI  (P_DONTCARE)
-
-#define P_SPI0_MOSI     (P_DONTCARE)
-#define P_SPI0_MISO     (P_DONTCARE)
-#define P_SPI0_SCK      (P_DONTCARE)
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
-
-#define P_TMR2          (P_DONTCARE)
-#define P_TMR1          (P_DONTCARE)
-#define P_TMR0          (P_DONTCARE)
-#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF1))
-
-
-
-
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
deleted file mode 100644
index 8460ab9c324f..000000000000
--- a/include/asm-blackfin/mach-bf537/anomaly.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf537/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision C, 02/08/2008; ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 silicon - sorry */
-#if __SILICON_REVISION__ < 2
-# error will not work on BF537 silicon version 0.0 or 0.1
-#endif
-
-#if defined(__ADSPBF534__)
-# define ANOMALY_BF534 1
-#else
-# define ANOMALY_BF534 0
-#endif
-#if defined(__ADSPBF536__)
-# define ANOMALY_BF536 1
-#else
-# define ANOMALY_BF536 0
-#endif
-#if defined(__ADSPBF537__)
-# define ANOMALY_BF537 1
-#else
-# define ANOMALY_BF537 0
-#endif
-
-/* Multi-issue instruction with dsp32shiftimm in slot1 and P-reg store in slot 2 not supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN bit is not valid after a Peripheral Receive Channel DMA stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H cannot be used to access 16-bit System MMR registers */
-#define ANOMALY_05000122 (1)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 2)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_DELAY not functional in PPI modes with 0 frame syncs */
-#define ANOMALY_05000180 (1)
-/* Instruction Cache Is Not Functional */
-#define ANOMALY_05000237 (__SILICON_REVISION__ < 2)
-/* If i-cache is on, CSYNC/SSYNC/IDLE around Change of Control causes failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 3)
-/* Spurious Hardware Error from an access in the shadow of a conditional branch */
-#define ANOMALY_05000245 (1)
-/* CLKIN Buffer Output Enable Reset Behavior Is Changed */
-#define ANOMALY_05000247 (1)
-/* Incorrect Bit-Shift of Data Word in Multichannel (TDM) mode in certain conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ < 3)
-/* EMAC Tx DMA error after an early frame abort */
-#define ANOMALY_05000252 (__SILICON_REVISION__ < 3)
-/* Maximum external clock speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 3)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT mode with external clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 2)
-/* Entering Hibernate Mode with RTC Seconds event interrupt not functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 3)
-/* EMAC MDIO input latched on wrong MDC edge */
-#define ANOMALY_05000256 (__SILICON_REVISION__ < 3)
-/* Interrupt/Exception during short hardware loop may cause bad instruction fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 3)
-/* Instruction Cache is corrupted when bits 9 and 12 of the ICPLB Data registers differ */
-#define ANOMALY_05000258 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ == 1) || __SILICON_REVISION__ == 2)
-/* ICPLB_STATUS MMR register may be corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ == 2)
-/* DCPLB_FAULT_ADDR MMR register may be corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 3)
-/* Stores to data cache may be lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 3)
-/* Hardware loop corrupted when taking an ICPLB exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ == 2)
-/* CSYNC/SSYNC/IDLE causes infinite stall in second to last instruction in hardware loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 3)
-/* Sensitivity to noise with slow input edge rates on external SPORT TX and RX clocks */
-#define ANOMALY_05000265 (1)
-/* Memory DMA error when peripheral DMA is running with non-zero DEB_TRAFFIC_PERIOD */
-#define ANOMALY_05000268 (__SILICON_REVISION__ < 3)
-/* High I/O activity causes output voltage of internal voltage regulator (VDDint) to decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 3)
-/* Certain data cache write through modes fail for VDDint <=0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM memory may be lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 3)
-/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA running may cause DMA system instability */
-#define ANOMALY_05000278 (((ANOMALY_BF536 || ANOMALY_BF537) && __SILICON_REVISION__ < 3) || (ANOMALY_BF534 && __SILICON_REVISION__ < 2))
-/* SPI Master boot mode does not work well with Atmel Data flash devices */
-#define ANOMALY_05000280 (1)
-/* False Hardware Error Exception when ISR context is not restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 3)
-/* Memory DMA corruption with 32-bit data and traffic control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 3)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 3)
-/* New Feature: EMAC TX DMA Word Alignment (Not Available On Older Silicon) */
-#define ANOMALY_05000285 (__SILICON_REVISION__ < 3)
-/* SPORTs may receive bad data if FIFOs fill up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 3)
-/* Memory to memory DMA source/destination descriptors must be in same memory space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 3)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 3)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 3)
-/* Writing UART_THR while UART clock is disabled sends erroneous start bit */
-#define ANOMALY_05000309 (__SILICON_REVISION__ < 3)
-/* False hardware errors caused by fetches at the boundary of reserved memory */
-#define ANOMALY_05000310 (1)
-/* Errors when SSYNC, CSYNC, or loads to LT, LB and LC registers are interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI is level sensitive on first transfer */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode: collisions occur in Full Duplex mode */
-#define ANOMALY_05000316 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode: TX frames in half duplex fail with status No Carrier */
-#define ANOMALY_05000321 (__SILICON_REVISION__ < 3)
-/* EMAC RMII mode at 10-Base-T speed: RX frames not received properly */
-#define ANOMALY_05000322 (1)
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (__SILICON_REVISION__ >= 3)
-/* New Feature: UART Remains Enabled after UART Boot */
-#define ANOMALY_05000350 (__SILICON_REVISION__ >= 3)
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000359 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ >= 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
deleted file mode 100644
index cfe2a221112e..000000000000
--- a/include/asm-blackfin/mach-bf537/bf537.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/bf537.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF537_H__
-#define __MACH_BF537_H__
-
-#define SUPPORTED_REVID 2
-
-/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
-
-#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE)        /* SPI_STAT */
-#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORTx_STAT */
-#define PPI_ERR_MASK (0xFFFF & ~FLD)    /* PPI_STATUS */
-#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)   /* EMAC_SYSTAT */
-#define UART_ERR_MASK_STAT1 (0x4)       /* UARTx_IIR */
-#define UART_ERR_MASK_STAT0 (0x2)       /* UARTx_IIR */
-#define CAN_ERR_MASK  (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)        /* CAN_GIF */
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR    0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
-
-#ifdef CONFIG_BF537
-#define CPU "BF537"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF536
-#define CPU "BF536"
-#define CPUID 0x027c8000
-#endif
-#ifdef CONFIG_BF534
-#define CPU "BF534"
-#define CPUID 0x027c6000
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF537_H__  */
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
deleted file mode 100644
index 1bf56ffa22f9..000000000000
--- a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
+++ /dev/null
@@ -1,195 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver header files
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int     uart_cts_pin;
-        int     uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-        CONFIG_UART1_CTS_PIN,
-        CONFIG_UART1_RTS_PIN,
-#endif
-        },
-#endif
-};
-
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
-#define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf537/bfin_sir.h b/include/asm-blackfin/mach-bf537/bfin_sir.h
deleted file mode 100644
index cfd8ad4f1f2c..000000000000
--- a/include/asm-blackfin/mach-bf537/bfin_sir.h
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
deleted file mode 100644
index cffc786b2a2b..000000000000
--- a/include/asm-blackfin/mach-bf537/blackfin.h
+++ /dev/null
@@ -1,165 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF537_FAMILY
-
-#include "bf537.h"
-#include "mem_map.h"
-#include "defBF534.h"
-#include "anomaly.h"
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "defBF537.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF534.h"
-
-/* UART 0*/
-#define bfin_read_UART_THR() bfin_read_UART0_THR()
-#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
-#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
-#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
-#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
-#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
-#define bfin_read_UART_IER() bfin_read_UART0_IER()
-#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
-#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
-#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
-#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
-#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
-#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
-#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
-#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
-#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
-#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
-#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
-#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
-#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
-#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
-#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
-
-#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
-#include "cdefBF537.h"
-#endif
-#endif
-
-/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-/* DMA Channnel */
-#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
-#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
-#define CH_UART_RX CH_UART0_RX
-#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
-#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
-#define CH_UART_TX CH_UART0_TX
-
-/* System Interrupt Controller */
-#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
-#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
-#define IRQ_UART_RX IRQ_UART0_RX
-#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
-#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
-#define IRQ_UART_TX IRQ_UART0_TX
-#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
-#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
-#define IRQ_UART_ERROR IRQ_UART0_ERROR
-
-/* MMR Registers*/
-#define bfin_read_UART_THR() bfin_read_UART0_THR()
-#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
-#define BFIN_UART_THR UART0_THR
-#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
-#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
-#define BFIN_UART_RBR UART0_RBR
-#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
-#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
-#define BFIN_UART_DLL UART0_DLL
-#define bfin_read_UART_IER() bfin_read_UART0_IER()
-#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
-#define BFIN_UART_IER UART0_IER
-#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
-#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
-#define BFIN_UART_DLH UART0_DLH
-#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
-#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
-#define BFIN_UART_IIR UART0_IIR
-#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
-#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
-#define BFIN_UART_LCR UART0_LCR
-#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
-#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
-#define BFIN_UART_MCR UART0_MCR
-#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
-#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
-#define BFIN_UART_LSR UART0_LSR
-#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
-#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
-#define BFIN_UART_SCR  UART0_SCR
-#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
-#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
-#define BFIN_UART_GCTL UART0_GCTL
-
-#define BFIN_UART_NR_PORTS      2
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-/* DPMC*/
-#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
-#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
-#define STOPCK_OFF STOPCK
-
-/* PLL_DIV Masks                                                                                                        */
-#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
-#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
-#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
-#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
deleted file mode 100644
index 82de526f8097..000000000000
--- a/include/asm-blackfin/mach-bf537/cdefBF534.h
+++ /dev/null
@@ -1,1819 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/cdefbf534.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  system mmr register map
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF534_H
-#define _CDEF_BF534_H
-
-#include <asm/blackfin.h>
-
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF534.h"
-
-/* Include core specific register pointer definitions                                                           */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-#include <asm/system.h>
-
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr = bfin_read32(SIC_IWR);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR, IWR_ENABLE(0));
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR, iwr);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define bfin_read_SWRST()                    bfin_read16(SWRST)
-#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
-#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
-#define bfin_read_SIC_RVECT()                bfin_read32(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)            bfin_write32(SIC_RVECT,val)
-#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
-#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
-#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
-#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
-#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
-#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
-#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
-
-/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
-#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
-#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
-#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
-#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
-#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
-#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
-#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
-#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
-#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
-#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define bfin_read_UART0_THR()                bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)            bfin_write16(UART0_THR,val)
-#define bfin_read_UART0_RBR()                bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)            bfin_write16(UART0_RBR,val)
-#define bfin_read_UART0_DLL()                bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)            bfin_write16(UART0_DLL,val)
-#define bfin_read_UART0_IER()                bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)            bfin_write16(UART0_IER,val)
-#define bfin_read_UART0_DLH()                bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)            bfin_write16(UART0_DLH,val)
-#define bfin_read_UART0_IIR()                bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)            bfin_write16(UART0_IIR,val)
-#define bfin_read_UART0_LCR()                bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)            bfin_write16(UART0_LCR,val)
-#define bfin_read_UART0_MCR()                bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)            bfin_write16(UART0_MCR,val)
-#define bfin_read_UART0_LSR()                bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)            bfin_write16(UART0_LSR,val)
-#define bfin_read_UART0_MSR()                bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)            bfin_write16(UART0_MSR,val)
-#define bfin_read_UART0_SCR()                bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)            bfin_write16(UART0_SCR,val)
-#define bfin_read_UART0_GCTL()               bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)           bfin_write16(UART0_GCTL,val)
-
-/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
-#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
-
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
-
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
-
-#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
-
-#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
-
-#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
-
-#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
-
-#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
-
-#define bfin_read_TIMER_ENABLE()             bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)         bfin_write16(TIMER_ENABLE,val)
-#define bfin_read_TIMER_DISABLE()            bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)        bfin_write16(TIMER_DISABLE,val)
-#define bfin_read_TIMER_STATUS()             bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)         bfin_write32(TIMER_STATUS,val)
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
-#define bfin_read_PORTFIO()                  bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)              bfin_write16(PORTFIO,val)
-#define bfin_read_PORTFIO_CLEAR()            bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)        bfin_write16(PORTFIO_CLEAR,val)
-#define bfin_read_PORTFIO_SET()              bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)          bfin_write16(PORTFIO_SET,val)
-#define bfin_read_PORTFIO_TOGGLE()           bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val)       bfin_write16(PORTFIO_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKA()            bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)        bfin_write16(PORTFIO_MASKA,val)
-#define bfin_read_PORTFIO_MASKA_CLEAR()      bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val)  bfin_write16(PORTFIO_MASKA_CLEAR,val)
-#define bfin_read_PORTFIO_MASKA_SET()        bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val)    bfin_write16(PORTFIO_MASKA_SET,val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE()     bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTFIO_MASKB()            bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)        bfin_write16(PORTFIO_MASKB,val)
-#define bfin_read_PORTFIO_MASKB_CLEAR()      bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val)  bfin_write16(PORTFIO_MASKB_CLEAR,val)
-#define bfin_read_PORTFIO_MASKB_SET()        bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val)    bfin_write16(PORTFIO_MASKB_SET,val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE()     bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTFIO_DIR()              bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)          bfin_write16(PORTFIO_DIR,val)
-#define bfin_read_PORTFIO_POLAR()            bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)        bfin_write16(PORTFIO_POLAR,val)
-#define bfin_read_PORTFIO_EDGE()             bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)         bfin_write16(PORTFIO_EDGE,val)
-#define bfin_read_PORTFIO_BOTH()             bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)         bfin_write16(PORTFIO_BOTH,val)
-#define bfin_read_PORTFIO_INEN()             bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)         bfin_write16(PORTFIO_INEN,val)
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
-#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
-#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
-#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
-#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define bfin_read_DMA_TC_PER()                bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)            bfin_write16(DMA_TC_PER,val)
-#define bfin_read_DMA_TC_CNT()                bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)            bfin_write16(DMA_TC_CNT,val)
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
-#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
-#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
-#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
-
-/* DMA Controller                                                                                                                                       */
-#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
-#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
-#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
-#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
-#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
-#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
-#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
-#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
-#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
-#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
-#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
-#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
-#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
-#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
-#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
-#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
-#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
-#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
-#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
-#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
-#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
-#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
-#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
-#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
-#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
-#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
-#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)
-#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)
-#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)
-#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)
-#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
-#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
-#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)
-#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)
-#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)
-#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
-#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)
-#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)
-#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)
-#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)
-#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
-#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
-#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)
-#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)
-#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)
-#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
-#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)
-#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)
-#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)
-#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)
-#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
-#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
-#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)
-#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)
-#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)      bfin_write16(DMA5_IRQ_STATUS,val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()      bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)  bfin_write16(DMA5_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA6_CONFIG()              bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)          bfin_write16(DMA6_CONFIG,val)
-#define bfin_read_DMA6_NEXT_DESC_PTR()       bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA6_START_ADDR()          bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
-#define bfin_read_DMA6_X_COUNT()             bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)         bfin_write16(DMA6_X_COUNT,val)
-#define bfin_read_DMA6_Y_COUNT()             bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)         bfin_write16(DMA6_Y_COUNT,val)
-#define bfin_read_DMA6_X_MODIFY()            bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)        bfin_write16(DMA6_X_MODIFY,val)
-#define bfin_read_DMA6_Y_MODIFY()            bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)        bfin_write16(DMA6_Y_MODIFY,val)
-#define bfin_read_DMA6_CURR_DESC_PTR()       bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
-#define bfin_read_DMA6_CURR_ADDR()           bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
-#define bfin_read_DMA6_CURR_X_COUNT()        bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)    bfin_write16(DMA6_CURR_X_COUNT,val)
-#define bfin_read_DMA6_CURR_Y_COUNT()        bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)    bfin_write16(DMA6_CURR_Y_COUNT,val)
-#define bfin_read_DMA6_IRQ_STATUS()          bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)      bfin_write16(DMA6_IRQ_STATUS,val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()      bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)  bfin_write16(DMA6_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA7_CONFIG()              bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)          bfin_write16(DMA7_CONFIG,val)
-#define bfin_read_DMA7_NEXT_DESC_PTR()       bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA7_START_ADDR()          bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
-#define bfin_read_DMA7_X_COUNT()             bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)         bfin_write16(DMA7_X_COUNT,val)
-#define bfin_read_DMA7_Y_COUNT()             bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)         bfin_write16(DMA7_Y_COUNT,val)
-#define bfin_read_DMA7_X_MODIFY()            bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)        bfin_write16(DMA7_X_MODIFY,val)
-#define bfin_read_DMA7_Y_MODIFY()            bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)        bfin_write16(DMA7_Y_MODIFY,val)
-#define bfin_read_DMA7_CURR_DESC_PTR()       bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
-#define bfin_read_DMA7_CURR_ADDR()           bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
-#define bfin_read_DMA7_CURR_X_COUNT()        bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)    bfin_write16(DMA7_CURR_X_COUNT,val)
-#define bfin_read_DMA7_CURR_Y_COUNT()        bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)    bfin_write16(DMA7_CURR_Y_COUNT,val)
-#define bfin_read_DMA7_IRQ_STATUS()          bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)      bfin_write16(DMA7_IRQ_STATUS,val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()      bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)  bfin_write16(DMA7_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA8_CONFIG()              bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)          bfin_write16(DMA8_CONFIG,val)
-#define bfin_read_DMA8_NEXT_DESC_PTR()       bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)   bfin_write32(DMA8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA8_START_ADDR()          bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)      bfin_write32(DMA8_START_ADDR,val)
-#define bfin_read_DMA8_X_COUNT()             bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)         bfin_write16(DMA8_X_COUNT,val)
-#define bfin_read_DMA8_Y_COUNT()             bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)         bfin_write16(DMA8_Y_COUNT,val)
-#define bfin_read_DMA8_X_MODIFY()            bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)        bfin_write16(DMA8_X_MODIFY,val)
-#define bfin_read_DMA8_Y_MODIFY()            bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)        bfin_write16(DMA8_Y_MODIFY,val)
-#define bfin_read_DMA8_CURR_DESC_PTR()       bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)   bfin_write32(DMA8_CURR_DESC_PTR,val)
-#define bfin_read_DMA8_CURR_ADDR()           bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)       bfin_write32(DMA8_CURR_ADDR,val)
-#define bfin_read_DMA8_CURR_X_COUNT()        bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)    bfin_write16(DMA8_CURR_X_COUNT,val)
-#define bfin_read_DMA8_CURR_Y_COUNT()        bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)    bfin_write16(DMA8_CURR_Y_COUNT,val)
-#define bfin_read_DMA8_IRQ_STATUS()          bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)      bfin_write16(DMA8_IRQ_STATUS,val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()      bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)  bfin_write16(DMA8_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA9_CONFIG()              bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)          bfin_write16(DMA9_CONFIG,val)
-#define bfin_read_DMA9_NEXT_DESC_PTR()       bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)   bfin_write32(DMA9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA9_START_ADDR()          bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)      bfin_write32(DMA9_START_ADDR,val)
-#define bfin_read_DMA9_X_COUNT()             bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)         bfin_write16(DMA9_X_COUNT,val)
-#define bfin_read_DMA9_Y_COUNT()             bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)         bfin_write16(DMA9_Y_COUNT,val)
-#define bfin_read_DMA9_X_MODIFY()            bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)        bfin_write16(DMA9_X_MODIFY,val)
-#define bfin_read_DMA9_Y_MODIFY()            bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)        bfin_write16(DMA9_Y_MODIFY,val)
-#define bfin_read_DMA9_CURR_DESC_PTR()       bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)   bfin_write32(DMA9_CURR_DESC_PTR,val)
-#define bfin_read_DMA9_CURR_ADDR()           bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)       bfin_write32(DMA9_CURR_ADDR,val)
-#define bfin_read_DMA9_CURR_X_COUNT()        bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)    bfin_write16(DMA9_CURR_X_COUNT,val)
-#define bfin_read_DMA9_CURR_Y_COUNT()        bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)    bfin_write16(DMA9_CURR_Y_COUNT,val)
-#define bfin_read_DMA9_IRQ_STATUS()          bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)      bfin_write16(DMA9_IRQ_STATUS,val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()      bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)  bfin_write16(DMA9_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA10_CONFIG()             bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)         bfin_write16(DMA10_CONFIG,val)
-#define bfin_read_DMA10_NEXT_DESC_PTR()      bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)  bfin_write32(DMA10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA10_START_ADDR()         bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)     bfin_write32(DMA10_START_ADDR,val)
-#define bfin_read_DMA10_X_COUNT()            bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)        bfin_write16(DMA10_X_COUNT,val)
-#define bfin_read_DMA10_Y_COUNT()            bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)        bfin_write16(DMA10_Y_COUNT,val)
-#define bfin_read_DMA10_X_MODIFY()           bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)       bfin_write16(DMA10_X_MODIFY,val)
-#define bfin_read_DMA10_Y_MODIFY()           bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)       bfin_write16(DMA10_Y_MODIFY,val)
-#define bfin_read_DMA10_CURR_DESC_PTR()      bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)  bfin_write32(DMA10_CURR_DESC_PTR,val)
-#define bfin_read_DMA10_CURR_ADDR()          bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)      bfin_write32(DMA10_CURR_ADDR,val)
-#define bfin_read_DMA10_CURR_X_COUNT()       bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)   bfin_write16(DMA10_CURR_X_COUNT,val)
-#define bfin_read_DMA10_CURR_Y_COUNT()       bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)   bfin_write16(DMA10_CURR_Y_COUNT,val)
-#define bfin_read_DMA10_IRQ_STATUS()         bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)     bfin_write16(DMA10_IRQ_STATUS,val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()     bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
-
-#define bfin_read_DMA11_CONFIG()             bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)         bfin_write16(DMA11_CONFIG,val)
-#define bfin_read_DMA11_NEXT_DESC_PTR()      bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)  bfin_write32(DMA11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA11_START_ADDR()         bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)     bfin_write32(DMA11_START_ADDR,val)
-#define bfin_read_DMA11_X_COUNT()            bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)        bfin_write16(DMA11_X_COUNT,val)
-#define bfin_read_DMA11_Y_COUNT()            bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)        bfin_write16(DMA11_Y_COUNT,val)
-#define bfin_read_DMA11_X_MODIFY()           bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)       bfin_write16(DMA11_X_MODIFY,val)
-#define bfin_read_DMA11_Y_MODIFY()           bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)       bfin_write16(DMA11_Y_MODIFY,val)
-#define bfin_read_DMA11_CURR_DESC_PTR()      bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)  bfin_write32(DMA11_CURR_DESC_PTR,val)
-#define bfin_read_DMA11_CURR_ADDR()          bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)      bfin_write32(DMA11_CURR_ADDR,val)
-#define bfin_read_DMA11_CURR_X_COUNT()       bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)   bfin_write16(DMA11_CURR_X_COUNT,val)
-#define bfin_read_DMA11_CURR_Y_COUNT()       bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)   bfin_write16(DMA11_CURR_Y_COUNT,val)
-#define bfin_read_DMA11_IRQ_STATUS()         bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)     bfin_write16(DMA11_IRQ_STATUS,val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()     bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D0_CONFIG()           bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)       bfin_write16(MDMA_D0_CONFIG,val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()    bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D0_START_ADDR()       bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
-#define bfin_read_MDMA_D0_X_COUNT()          bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)      bfin_write16(MDMA_D0_X_COUNT,val)
-#define bfin_read_MDMA_D0_Y_COUNT()          bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)      bfin_write16(MDMA_D0_Y_COUNT,val)
-#define bfin_read_MDMA_D0_X_MODIFY()         bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)     bfin_write16(MDMA_D0_X_MODIFY,val)
-#define bfin_read_MDMA_D0_Y_MODIFY()         bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)     bfin_write16(MDMA_D0_Y_MODIFY,val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()    bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D0_CURR_ADDR()        bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()     bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()     bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()       bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)   bfin_write16(MDMA_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()   bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S0_CONFIG()           bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)       bfin_write16(MDMA_S0_CONFIG,val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()    bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S0_START_ADDR()       bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
-#define bfin_read_MDMA_S0_X_COUNT()          bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)      bfin_write16(MDMA_S0_X_COUNT,val)
-#define bfin_read_MDMA_S0_Y_COUNT()          bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)      bfin_write16(MDMA_S0_Y_COUNT,val)
-#define bfin_read_MDMA_S0_X_MODIFY()         bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)     bfin_write16(MDMA_S0_X_MODIFY,val)
-#define bfin_read_MDMA_S0_Y_MODIFY()         bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)     bfin_write16(MDMA_S0_Y_MODIFY,val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()    bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S0_CURR_ADDR()        bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()     bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()     bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()       bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)   bfin_write16(MDMA_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()   bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_D1_CONFIG()           bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)       bfin_write16(MDMA_D1_CONFIG,val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()    bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_D1_START_ADDR()       bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
-#define bfin_read_MDMA_D1_X_COUNT()          bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)      bfin_write16(MDMA_D1_X_COUNT,val)
-#define bfin_read_MDMA_D1_Y_COUNT()          bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)      bfin_write16(MDMA_D1_Y_COUNT,val)
-#define bfin_read_MDMA_D1_X_MODIFY()         bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)     bfin_write16(MDMA_D1_X_MODIFY,val)
-#define bfin_read_MDMA_D1_Y_MODIFY()         bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)     bfin_write16(MDMA_D1_Y_MODIFY,val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()    bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_D1_CURR_ADDR()        bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()     bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()     bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()       bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)   bfin_write16(MDMA_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()   bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
-
-#define bfin_read_MDMA_S1_CONFIG()           bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)       bfin_write16(MDMA_S1_CONFIG,val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()    bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA_S1_START_ADDR()       bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
-#define bfin_read_MDMA_S1_X_COUNT()          bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)      bfin_write16(MDMA_S1_X_COUNT,val)
-#define bfin_read_MDMA_S1_Y_COUNT()          bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)      bfin_write16(MDMA_S1_Y_COUNT,val)
-#define bfin_read_MDMA_S1_X_MODIFY()         bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)     bfin_write16(MDMA_S1_X_MODIFY,val)
-#define bfin_read_MDMA_S1_Y_MODIFY()         bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)     bfin_write16(MDMA_S1_Y_MODIFY,val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()    bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA_S1_CURR_ADDR()        bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()     bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()     bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()       bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)   bfin_write16(MDMA_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()   bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
-#define bfin_read_PPI_CONTROL()              bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)          bfin_write16(PPI_CONTROL,val)
-#define bfin_read_PPI_STATUS()               bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)           bfin_write16(PPI_STATUS,val)
-#define bfin_clear_PPI_STATUS()              bfin_write_PPI_STATUS(0xFFFF)
-#define bfin_read_PPI_DELAY()                bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)            bfin_write16(PPI_DELAY,val)
-#define bfin_read_PPI_COUNT()                bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)            bfin_write16(PPI_COUNT,val)
-#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
-
-/* Two-Wire Interface (0xFFC01400 - 0xFFC014FF) */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
-#define bfin_read_PORTGIO()                  bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)              bfin_write16(PORTGIO,val)
-#define bfin_read_PORTGIO_CLEAR()            bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)        bfin_write16(PORTGIO_CLEAR,val)
-#define bfin_read_PORTGIO_SET()              bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)          bfin_write16(PORTGIO_SET,val)
-#define bfin_read_PORTGIO_TOGGLE()           bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val)       bfin_write16(PORTGIO_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKA()            bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)        bfin_write16(PORTGIO_MASKA,val)
-#define bfin_read_PORTGIO_MASKA_CLEAR()      bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val)  bfin_write16(PORTGIO_MASKA_CLEAR,val)
-#define bfin_read_PORTGIO_MASKA_SET()        bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val)    bfin_write16(PORTGIO_MASKA_SET,val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE()     bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTGIO_MASKB()            bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)        bfin_write16(PORTGIO_MASKB,val)
-#define bfin_read_PORTGIO_MASKB_CLEAR()      bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val)  bfin_write16(PORTGIO_MASKB_CLEAR,val)
-#define bfin_read_PORTGIO_MASKB_SET()        bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val)    bfin_write16(PORTGIO_MASKB_SET,val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE()     bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTGIO_DIR()              bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)          bfin_write16(PORTGIO_DIR,val)
-#define bfin_read_PORTGIO_POLAR()            bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)        bfin_write16(PORTGIO_POLAR,val)
-#define bfin_read_PORTGIO_EDGE()             bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)         bfin_write16(PORTGIO_EDGE,val)
-#define bfin_read_PORTGIO_BOTH()             bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)         bfin_write16(PORTGIO_BOTH,val)
-#define bfin_read_PORTGIO_INEN()             bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)         bfin_write16(PORTGIO_INEN,val)
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
-#define bfin_read_PORTHIO()                  bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)              bfin_write16(PORTHIO,val)
-#define bfin_read_PORTHIO_CLEAR()            bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)        bfin_write16(PORTHIO_CLEAR,val)
-#define bfin_read_PORTHIO_SET()              bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)          bfin_write16(PORTHIO_SET,val)
-#define bfin_read_PORTHIO_TOGGLE()           bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val)       bfin_write16(PORTHIO_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKA()            bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)        bfin_write16(PORTHIO_MASKA,val)
-#define bfin_read_PORTHIO_MASKA_CLEAR()      bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val)  bfin_write16(PORTHIO_MASKA_CLEAR,val)
-#define bfin_read_PORTHIO_MASKA_SET()        bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val)    bfin_write16(PORTHIO_MASKA_SET,val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE()     bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
-#define bfin_read_PORTHIO_MASKB()            bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)        bfin_write16(PORTHIO_MASKB,val)
-#define bfin_read_PORTHIO_MASKB_CLEAR()      bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val)  bfin_write16(PORTHIO_MASKB_CLEAR,val)
-#define bfin_read_PORTHIO_MASKB_SET()        bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val)    bfin_write16(PORTHIO_MASKB_SET,val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE()     bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
-#define bfin_read_PORTHIO_DIR()              bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)          bfin_write16(PORTHIO_DIR,val)
-#define bfin_read_PORTHIO_POLAR()            bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)        bfin_write16(PORTHIO_POLAR,val)
-#define bfin_read_PORTHIO_EDGE()             bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)         bfin_write16(PORTHIO_EDGE,val)
-#define bfin_read_PORTHIO_BOTH()             bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)         bfin_write16(PORTHIO_BOTH,val)
-#define bfin_read_PORTHIO_INEN()             bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)         bfin_write16(PORTHIO_INEN,val)
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define bfin_read_UART1_THR()                bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)            bfin_write16(UART1_THR,val)
-#define bfin_read_UART1_RBR()                bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)            bfin_write16(UART1_RBR,val)
-#define bfin_read_UART1_DLL()                bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)            bfin_write16(UART1_DLL,val)
-#define bfin_read_UART1_IER()                bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)            bfin_write16(UART1_IER,val)
-#define bfin_read_UART1_DLH()                bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)            bfin_write16(UART1_DLH,val)
-#define bfin_read_UART1_IIR()                bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)            bfin_write16(UART1_IIR,val)
-#define bfin_read_UART1_LCR()                bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)            bfin_write16(UART1_LCR,val)
-#define bfin_read_UART1_MCR()                bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)            bfin_write16(UART1_MCR,val)
-#define bfin_read_UART1_LSR()                bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)            bfin_write16(UART1_LSR,val)
-#define bfin_read_UART1_MSR()                bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)            bfin_write16(UART1_MSR,val)
-#define bfin_read_UART1_SCR()                bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)            bfin_write16(UART1_SCR,val)
-#define bfin_read_UART1_GCTL()               bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)           bfin_write16(UART1_GCTL,val)
-
-/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                               */
-/* For Mailboxes 0-15 */
-#define bfin_read_CAN_MC1()                  bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val)              bfin_write16(CAN_MC1,val)
-#define bfin_read_CAN_MD1()                  bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val)              bfin_write16(CAN_MD1,val)
-#define bfin_read_CAN_TRS1()                 bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val)             bfin_write16(CAN_TRS1,val)
-#define bfin_read_CAN_TRR1()                 bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val)             bfin_write16(CAN_TRR1,val)
-#define bfin_read_CAN_TA1()                  bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val)              bfin_write16(CAN_TA1,val)
-#define bfin_read_CAN_AA1()                  bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val)              bfin_write16(CAN_AA1,val)
-#define bfin_read_CAN_RMP1()                 bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val)             bfin_write16(CAN_RMP1,val)
-#define bfin_read_CAN_RML1()                 bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val)             bfin_write16(CAN_RML1,val)
-#define bfin_read_CAN_MBTIF1()               bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val)           bfin_write16(CAN_MBTIF1,val)
-#define bfin_read_CAN_MBRIF1()               bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val)           bfin_write16(CAN_MBRIF1,val)
-#define bfin_read_CAN_MBIM1()                bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val)            bfin_write16(CAN_MBIM1,val)
-#define bfin_read_CAN_RFH1()                 bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val)             bfin_write16(CAN_RFH1,val)
-#define bfin_read_CAN_OPSS1()                bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val)            bfin_write16(CAN_OPSS1,val)
-
-/* For Mailboxes 16-31 */
-#define bfin_read_CAN_MC2()                  bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val)              bfin_write16(CAN_MC2,val)
-#define bfin_read_CAN_MD2()                  bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val)              bfin_write16(CAN_MD2,val)
-#define bfin_read_CAN_TRS2()                 bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val)             bfin_write16(CAN_TRS2,val)
-#define bfin_read_CAN_TRR2()                 bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val)             bfin_write16(CAN_TRR2,val)
-#define bfin_read_CAN_TA2()                  bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val)              bfin_write16(CAN_TA2,val)
-#define bfin_read_CAN_AA2()                  bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val)              bfin_write16(CAN_AA2,val)
-#define bfin_read_CAN_RMP2()                 bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val)             bfin_write16(CAN_RMP2,val)
-#define bfin_read_CAN_RML2()                 bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val)             bfin_write16(CAN_RML2,val)
-#define bfin_read_CAN_MBTIF2()               bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val)           bfin_write16(CAN_MBTIF2,val)
-#define bfin_read_CAN_MBRIF2()               bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val)           bfin_write16(CAN_MBRIF2,val)
-#define bfin_read_CAN_MBIM2()                bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val)            bfin_write16(CAN_MBIM2,val)
-#define bfin_read_CAN_RFH2()                 bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val)             bfin_write16(CAN_RFH2,val)
-#define bfin_read_CAN_OPSS2()                bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val)            bfin_write16(CAN_OPSS2,val)
-
-#define bfin_read_CAN_CLOCK()                bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val)            bfin_write16(CAN_CLOCK,val)
-#define bfin_read_CAN_TIMING()               bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val)           bfin_write16(CAN_TIMING,val)
-#define bfin_read_CAN_DEBUG()                bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val)            bfin_write16(CAN_DEBUG,val)
-#define bfin_read_CAN_STATUS()               bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val)           bfin_write16(CAN_STATUS,val)
-#define bfin_read_CAN_CEC()                  bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val)              bfin_write16(CAN_CEC,val)
-#define bfin_read_CAN_GIS()                  bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val)              bfin_write16(CAN_GIS,val)
-#define bfin_read_CAN_GIM()                  bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val)              bfin_write16(CAN_GIM,val)
-#define bfin_read_CAN_GIF()                  bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val)              bfin_write16(CAN_GIF,val)
-#define bfin_read_CAN_CONTROL()              bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val)          bfin_write16(CAN_CONTROL,val)
-#define bfin_read_CAN_INTR()                 bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val)             bfin_write16(CAN_INTR,val)
-#define bfin_read_CAN_SFCMVER()              bfin_read16(CAN_SFCMVER)
-#define bfin_write_CAN_SFCMVER(val)          bfin_write16(CAN_SFCMVER,val)
-#define bfin_read_CAN_MBTD()                 bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val)             bfin_write16(CAN_MBTD,val)
-#define bfin_read_CAN_EWR()                  bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val)              bfin_write16(CAN_EWR,val)
-#define bfin_read_CAN_ESR()                  bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val)              bfin_write16(CAN_ESR,val)
-#define bfin_read_CAN_UCREG()                bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val)            bfin_write16(CAN_UCREG,val)
-#define bfin_read_CAN_UCCNT()                bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val)            bfin_write16(CAN_UCCNT,val)
-#define bfin_read_CAN_UCRC()                 bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val)             bfin_write16(CAN_UCRC,val)
-#define bfin_read_CAN_UCCNF()                bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val)            bfin_write16(CAN_UCCNF,val)
-
-/* Mailbox Acceptance Masks */
-#define bfin_read_CAN_AM00L()                bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val)            bfin_write16(CAN_AM00L,val)
-#define bfin_read_CAN_AM00H()                bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val)            bfin_write16(CAN_AM00H,val)
-#define bfin_read_CAN_AM01L()                bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val)            bfin_write16(CAN_AM01L,val)
-#define bfin_read_CAN_AM01H()                bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val)            bfin_write16(CAN_AM01H,val)
-#define bfin_read_CAN_AM02L()                bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val)            bfin_write16(CAN_AM02L,val)
-#define bfin_read_CAN_AM02H()                bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val)            bfin_write16(CAN_AM02H,val)
-#define bfin_read_CAN_AM03L()                bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val)            bfin_write16(CAN_AM03L,val)
-#define bfin_read_CAN_AM03H()                bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val)            bfin_write16(CAN_AM03H,val)
-#define bfin_read_CAN_AM04L()                bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val)            bfin_write16(CAN_AM04L,val)
-#define bfin_read_CAN_AM04H()                bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val)            bfin_write16(CAN_AM04H,val)
-#define bfin_read_CAN_AM05L()                bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val)            bfin_write16(CAN_AM05L,val)
-#define bfin_read_CAN_AM05H()                bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val)            bfin_write16(CAN_AM05H,val)
-#define bfin_read_CAN_AM06L()                bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val)            bfin_write16(CAN_AM06L,val)
-#define bfin_read_CAN_AM06H()                bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val)            bfin_write16(CAN_AM06H,val)
-#define bfin_read_CAN_AM07L()                bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val)            bfin_write16(CAN_AM07L,val)
-#define bfin_read_CAN_AM07H()                bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val)            bfin_write16(CAN_AM07H,val)
-#define bfin_read_CAN_AM08L()                bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val)            bfin_write16(CAN_AM08L,val)
-#define bfin_read_CAN_AM08H()                bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val)            bfin_write16(CAN_AM08H,val)
-#define bfin_read_CAN_AM09L()                bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val)            bfin_write16(CAN_AM09L,val)
-#define bfin_read_CAN_AM09H()                bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val)            bfin_write16(CAN_AM09H,val)
-#define bfin_read_CAN_AM10L()                bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val)            bfin_write16(CAN_AM10L,val)
-#define bfin_read_CAN_AM10H()                bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val)            bfin_write16(CAN_AM10H,val)
-#define bfin_read_CAN_AM11L()                bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val)            bfin_write16(CAN_AM11L,val)
-#define bfin_read_CAN_AM11H()                bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val)            bfin_write16(CAN_AM11H,val)
-#define bfin_read_CAN_AM12L()                bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val)            bfin_write16(CAN_AM12L,val)
-#define bfin_read_CAN_AM12H()                bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val)            bfin_write16(CAN_AM12H,val)
-#define bfin_read_CAN_AM13L()                bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val)            bfin_write16(CAN_AM13L,val)
-#define bfin_read_CAN_AM13H()                bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val)            bfin_write16(CAN_AM13H,val)
-#define bfin_read_CAN_AM14L()                bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val)            bfin_write16(CAN_AM14L,val)
-#define bfin_read_CAN_AM14H()                bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val)            bfin_write16(CAN_AM14H,val)
-#define bfin_read_CAN_AM15L()                bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val)            bfin_write16(CAN_AM15L,val)
-#define bfin_read_CAN_AM15H()                bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val)            bfin_write16(CAN_AM15H,val)
-
-#define bfin_read_CAN_AM16L()                bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val)            bfin_write16(CAN_AM16L,val)
-#define bfin_read_CAN_AM16H()                bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val)            bfin_write16(CAN_AM16H,val)
-#define bfin_read_CAN_AM17L()                bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val)            bfin_write16(CAN_AM17L,val)
-#define bfin_read_CAN_AM17H()                bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val)            bfin_write16(CAN_AM17H,val)
-#define bfin_read_CAN_AM18L()                bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val)            bfin_write16(CAN_AM18L,val)
-#define bfin_read_CAN_AM18H()                bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val)            bfin_write16(CAN_AM18H,val)
-#define bfin_read_CAN_AM19L()                bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val)            bfin_write16(CAN_AM19L,val)
-#define bfin_read_CAN_AM19H()                bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val)            bfin_write16(CAN_AM19H,val)
-#define bfin_read_CAN_AM20L()                bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val)            bfin_write16(CAN_AM20L,val)
-#define bfin_read_CAN_AM20H()                bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val)            bfin_write16(CAN_AM20H,val)
-#define bfin_read_CAN_AM21L()                bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val)            bfin_write16(CAN_AM21L,val)
-#define bfin_read_CAN_AM21H()                bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val)            bfin_write16(CAN_AM21H,val)
-#define bfin_read_CAN_AM22L()                bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val)            bfin_write16(CAN_AM22L,val)
-#define bfin_read_CAN_AM22H()                bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val)            bfin_write16(CAN_AM22H,val)
-#define bfin_read_CAN_AM23L()                bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val)            bfin_write16(CAN_AM23L,val)
-#define bfin_read_CAN_AM23H()                bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val)            bfin_write16(CAN_AM23H,val)
-#define bfin_read_CAN_AM24L()                bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val)            bfin_write16(CAN_AM24L,val)
-#define bfin_read_CAN_AM24H()                bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val)            bfin_write16(CAN_AM24H,val)
-#define bfin_read_CAN_AM25L()                bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val)            bfin_write16(CAN_AM25L,val)
-#define bfin_read_CAN_AM25H()                bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val)            bfin_write16(CAN_AM25H,val)
-#define bfin_read_CAN_AM26L()                bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val)            bfin_write16(CAN_AM26L,val)
-#define bfin_read_CAN_AM26H()                bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val)            bfin_write16(CAN_AM26H,val)
-#define bfin_read_CAN_AM27L()                bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val)            bfin_write16(CAN_AM27L,val)
-#define bfin_read_CAN_AM27H()                bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val)            bfin_write16(CAN_AM27H,val)
-#define bfin_read_CAN_AM28L()                bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val)            bfin_write16(CAN_AM28L,val)
-#define bfin_read_CAN_AM28H()                bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val)            bfin_write16(CAN_AM28H,val)
-#define bfin_read_CAN_AM29L()                bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val)            bfin_write16(CAN_AM29L,val)
-#define bfin_read_CAN_AM29H()                bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val)            bfin_write16(CAN_AM29H,val)
-#define bfin_read_CAN_AM30L()                bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val)            bfin_write16(CAN_AM30L,val)
-#define bfin_read_CAN_AM30H()                bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val)            bfin_write16(CAN_AM30H,val)
-#define bfin_read_CAN_AM31L()                bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val)            bfin_write16(CAN_AM31L,val)
-#define bfin_read_CAN_AM31H()                bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val)            bfin_write16(CAN_AM31H,val)
-
-/* CAN Acceptance Mask Area Macros      */
-#define bfin_read_CAN_AM_L(x)()              bfin_read16(CAN_AM_L(x))
-#define bfin_write_CAN_AM_L(x)(val)          bfin_write16(CAN_AM_L(x),val)
-#define bfin_read_CAN_AM_H(x)()              bfin_read16(CAN_AM_H(x))
-#define bfin_write_CAN_AM_H(x)(val)          bfin_write16(CAN_AM_H(x),val)
-
-/* Mailbox Registers */
-#define bfin_read_CAN_MB00_ID1()             bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val)         bfin_write16(CAN_MB00_ID1,val)
-#define bfin_read_CAN_MB00_ID0()             bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val)         bfin_write16(CAN_MB00_ID0,val)
-#define bfin_read_CAN_MB00_TIMESTAMP()       bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val)   bfin_write16(CAN_MB00_TIMESTAMP,val)
-#define bfin_read_CAN_MB00_LENGTH()          bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val)      bfin_write16(CAN_MB00_LENGTH,val)
-#define bfin_read_CAN_MB00_DATA3()           bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val)       bfin_write16(CAN_MB00_DATA3,val)
-#define bfin_read_CAN_MB00_DATA2()           bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val)       bfin_write16(CAN_MB00_DATA2,val)
-#define bfin_read_CAN_MB00_DATA1()           bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val)       bfin_write16(CAN_MB00_DATA1,val)
-#define bfin_read_CAN_MB00_DATA0()           bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val)       bfin_write16(CAN_MB00_DATA0,val)
-
-#define bfin_read_CAN_MB01_ID1()             bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val)         bfin_write16(CAN_MB01_ID1,val)
-#define bfin_read_CAN_MB01_ID0()             bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val)         bfin_write16(CAN_MB01_ID0,val)
-#define bfin_read_CAN_MB01_TIMESTAMP()       bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val)   bfin_write16(CAN_MB01_TIMESTAMP,val)
-#define bfin_read_CAN_MB01_LENGTH()          bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val)      bfin_write16(CAN_MB01_LENGTH,val)
-#define bfin_read_CAN_MB01_DATA3()           bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val)       bfin_write16(CAN_MB01_DATA3,val)
-#define bfin_read_CAN_MB01_DATA2()           bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val)       bfin_write16(CAN_MB01_DATA2,val)
-#define bfin_read_CAN_MB01_DATA1()           bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val)       bfin_write16(CAN_MB01_DATA1,val)
-#define bfin_read_CAN_MB01_DATA0()           bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val)       bfin_write16(CAN_MB01_DATA0,val)
-
-#define bfin_read_CAN_MB02_ID1()             bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val)         bfin_write16(CAN_MB02_ID1,val)
-#define bfin_read_CAN_MB02_ID0()             bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val)         bfin_write16(CAN_MB02_ID0,val)
-#define bfin_read_CAN_MB02_TIMESTAMP()       bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val)   bfin_write16(CAN_MB02_TIMESTAMP,val)
-#define bfin_read_CAN_MB02_LENGTH()          bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val)      bfin_write16(CAN_MB02_LENGTH,val)
-#define bfin_read_CAN_MB02_DATA3()           bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val)       bfin_write16(CAN_MB02_DATA3,val)
-#define bfin_read_CAN_MB02_DATA2()           bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val)       bfin_write16(CAN_MB02_DATA2,val)
-#define bfin_read_CAN_MB02_DATA1()           bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val)       bfin_write16(CAN_MB02_DATA1,val)
-#define bfin_read_CAN_MB02_DATA0()           bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val)       bfin_write16(CAN_MB02_DATA0,val)
-
-#define bfin_read_CAN_MB03_ID1()             bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val)         bfin_write16(CAN_MB03_ID1,val)
-#define bfin_read_CAN_MB03_ID0()             bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val)         bfin_write16(CAN_MB03_ID0,val)
-#define bfin_read_CAN_MB03_TIMESTAMP()       bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val)   bfin_write16(CAN_MB03_TIMESTAMP,val)
-#define bfin_read_CAN_MB03_LENGTH()          bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val)      bfin_write16(CAN_MB03_LENGTH,val)
-#define bfin_read_CAN_MB03_DATA3()           bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val)       bfin_write16(CAN_MB03_DATA3,val)
-#define bfin_read_CAN_MB03_DATA2()           bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val)       bfin_write16(CAN_MB03_DATA2,val)
-#define bfin_read_CAN_MB03_DATA1()           bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val)       bfin_write16(CAN_MB03_DATA1,val)
-#define bfin_read_CAN_MB03_DATA0()           bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val)       bfin_write16(CAN_MB03_DATA0,val)
-
-#define bfin_read_CAN_MB04_ID1()             bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val)         bfin_write16(CAN_MB04_ID1,val)
-#define bfin_read_CAN_MB04_ID0()             bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val)         bfin_write16(CAN_MB04_ID0,val)
-#define bfin_read_CAN_MB04_TIMESTAMP()       bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val)   bfin_write16(CAN_MB04_TIMESTAMP,val)
-#define bfin_read_CAN_MB04_LENGTH()          bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val)      bfin_write16(CAN_MB04_LENGTH,val)
-#define bfin_read_CAN_MB04_DATA3()           bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val)       bfin_write16(CAN_MB04_DATA3,val)
-#define bfin_read_CAN_MB04_DATA2()           bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val)       bfin_write16(CAN_MB04_DATA2,val)
-#define bfin_read_CAN_MB04_DATA1()           bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val)       bfin_write16(CAN_MB04_DATA1,val)
-#define bfin_read_CAN_MB04_DATA0()           bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val)       bfin_write16(CAN_MB04_DATA0,val)
-
-#define bfin_read_CAN_MB05_ID1()             bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val)         bfin_write16(CAN_MB05_ID1,val)
-#define bfin_read_CAN_MB05_ID0()             bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val)         bfin_write16(CAN_MB05_ID0,val)
-#define bfin_read_CAN_MB05_TIMESTAMP()       bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val)   bfin_write16(CAN_MB05_TIMESTAMP,val)
-#define bfin_read_CAN_MB05_LENGTH()          bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val)      bfin_write16(CAN_MB05_LENGTH,val)
-#define bfin_read_CAN_MB05_DATA3()           bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val)       bfin_write16(CAN_MB05_DATA3,val)
-#define bfin_read_CAN_MB05_DATA2()           bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val)       bfin_write16(CAN_MB05_DATA2,val)
-#define bfin_read_CAN_MB05_DATA1()           bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val)       bfin_write16(CAN_MB05_DATA1,val)
-#define bfin_read_CAN_MB05_DATA0()           bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val)       bfin_write16(CAN_MB05_DATA0,val)
-
-#define bfin_read_CAN_MB06_ID1()             bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val)         bfin_write16(CAN_MB06_ID1,val)
-#define bfin_read_CAN_MB06_ID0()             bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val)         bfin_write16(CAN_MB06_ID0,val)
-#define bfin_read_CAN_MB06_TIMESTAMP()       bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val)   bfin_write16(CAN_MB06_TIMESTAMP,val)
-#define bfin_read_CAN_MB06_LENGTH()          bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val)      bfin_write16(CAN_MB06_LENGTH,val)
-#define bfin_read_CAN_MB06_DATA3()           bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val)       bfin_write16(CAN_MB06_DATA3,val)
-#define bfin_read_CAN_MB06_DATA2()           bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val)       bfin_write16(CAN_MB06_DATA2,val)
-#define bfin_read_CAN_MB06_DATA1()           bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val)       bfin_write16(CAN_MB06_DATA1,val)
-#define bfin_read_CAN_MB06_DATA0()           bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val)       bfin_write16(CAN_MB06_DATA0,val)
-
-#define bfin_read_CAN_MB07_ID1()             bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val)         bfin_write16(CAN_MB07_ID1,val)
-#define bfin_read_CAN_MB07_ID0()             bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val)         bfin_write16(CAN_MB07_ID0,val)
-#define bfin_read_CAN_MB07_TIMESTAMP()       bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val)   bfin_write16(CAN_MB07_TIMESTAMP,val)
-#define bfin_read_CAN_MB07_LENGTH()          bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val)      bfin_write16(CAN_MB07_LENGTH,val)
-#define bfin_read_CAN_MB07_DATA3()           bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val)       bfin_write16(CAN_MB07_DATA3,val)
-#define bfin_read_CAN_MB07_DATA2()           bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val)       bfin_write16(CAN_MB07_DATA2,val)
-#define bfin_read_CAN_MB07_DATA1()           bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val)       bfin_write16(CAN_MB07_DATA1,val)
-#define bfin_read_CAN_MB07_DATA0()           bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val)       bfin_write16(CAN_MB07_DATA0,val)
-
-#define bfin_read_CAN_MB08_ID1()             bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val)         bfin_write16(CAN_MB08_ID1,val)
-#define bfin_read_CAN_MB08_ID0()             bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val)         bfin_write16(CAN_MB08_ID0,val)
-#define bfin_read_CAN_MB08_TIMESTAMP()       bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val)   bfin_write16(CAN_MB08_TIMESTAMP,val)
-#define bfin_read_CAN_MB08_LENGTH()          bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val)      bfin_write16(CAN_MB08_LENGTH,val)
-#define bfin_read_CAN_MB08_DATA3()           bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val)       bfin_write16(CAN_MB08_DATA3,val)
-#define bfin_read_CAN_MB08_DATA2()           bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val)       bfin_write16(CAN_MB08_DATA2,val)
-#define bfin_read_CAN_MB08_DATA1()           bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val)       bfin_write16(CAN_MB08_DATA1,val)
-#define bfin_read_CAN_MB08_DATA0()           bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val)       bfin_write16(CAN_MB08_DATA0,val)
-
-#define bfin_read_CAN_MB09_ID1()             bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val)         bfin_write16(CAN_MB09_ID1,val)
-#define bfin_read_CAN_MB09_ID0()             bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val)         bfin_write16(CAN_MB09_ID0,val)
-#define bfin_read_CAN_MB09_TIMESTAMP()       bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val)   bfin_write16(CAN_MB09_TIMESTAMP,val)
-#define bfin_read_CAN_MB09_LENGTH()          bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val)      bfin_write16(CAN_MB09_LENGTH,val)
-#define bfin_read_CAN_MB09_DATA3()           bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val)       bfin_write16(CAN_MB09_DATA3,val)
-#define bfin_read_CAN_MB09_DATA2()           bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val)       bfin_write16(CAN_MB09_DATA2,val)
-#define bfin_read_CAN_MB09_DATA1()           bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val)       bfin_write16(CAN_MB09_DATA1,val)
-#define bfin_read_CAN_MB09_DATA0()           bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val)       bfin_write16(CAN_MB09_DATA0,val)
-
-#define bfin_read_CAN_MB10_ID1()             bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val)         bfin_write16(CAN_MB10_ID1,val)
-#define bfin_read_CAN_MB10_ID0()             bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val)         bfin_write16(CAN_MB10_ID0,val)
-#define bfin_read_CAN_MB10_TIMESTAMP()       bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val)   bfin_write16(CAN_MB10_TIMESTAMP,val)
-#define bfin_read_CAN_MB10_LENGTH()          bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val)      bfin_write16(CAN_MB10_LENGTH,val)
-#define bfin_read_CAN_MB10_DATA3()           bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val)       bfin_write16(CAN_MB10_DATA3,val)
-#define bfin_read_CAN_MB10_DATA2()           bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val)       bfin_write16(CAN_MB10_DATA2,val)
-#define bfin_read_CAN_MB10_DATA1()           bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val)       bfin_write16(CAN_MB10_DATA1,val)
-#define bfin_read_CAN_MB10_DATA0()           bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val)       bfin_write16(CAN_MB10_DATA0,val)
-
-#define bfin_read_CAN_MB11_ID1()             bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val)         bfin_write16(CAN_MB11_ID1,val)
-#define bfin_read_CAN_MB11_ID0()             bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val)         bfin_write16(CAN_MB11_ID0,val)
-#define bfin_read_CAN_MB11_TIMESTAMP()       bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val)   bfin_write16(CAN_MB11_TIMESTAMP,val)
-#define bfin_read_CAN_MB11_LENGTH()          bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val)      bfin_write16(CAN_MB11_LENGTH,val)
-#define bfin_read_CAN_MB11_DATA3()           bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val)       bfin_write16(CAN_MB11_DATA3,val)
-#define bfin_read_CAN_MB11_DATA2()           bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val)       bfin_write16(CAN_MB11_DATA2,val)
-#define bfin_read_CAN_MB11_DATA1()           bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val)       bfin_write16(CAN_MB11_DATA1,val)
-#define bfin_read_CAN_MB11_DATA0()           bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val)       bfin_write16(CAN_MB11_DATA0,val)
-
-#define bfin_read_CAN_MB12_ID1()             bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val)         bfin_write16(CAN_MB12_ID1,val)
-#define bfin_read_CAN_MB12_ID0()             bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val)         bfin_write16(CAN_MB12_ID0,val)
-#define bfin_read_CAN_MB12_TIMESTAMP()       bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val)   bfin_write16(CAN_MB12_TIMESTAMP,val)
-#define bfin_read_CAN_MB12_LENGTH()          bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val)      bfin_write16(CAN_MB12_LENGTH,val)
-#define bfin_read_CAN_MB12_DATA3()           bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val)       bfin_write16(CAN_MB12_DATA3,val)
-#define bfin_read_CAN_MB12_DATA2()           bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val)       bfin_write16(CAN_MB12_DATA2,val)
-#define bfin_read_CAN_MB12_DATA1()           bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val)       bfin_write16(CAN_MB12_DATA1,val)
-#define bfin_read_CAN_MB12_DATA0()           bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val)       bfin_write16(CAN_MB12_DATA0,val)
-
-#define bfin_read_CAN_MB13_ID1()             bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val)         bfin_write16(CAN_MB13_ID1,val)
-#define bfin_read_CAN_MB13_ID0()             bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val)         bfin_write16(CAN_MB13_ID0,val)
-#define bfin_read_CAN_MB13_TIMESTAMP()       bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val)   bfin_write16(CAN_MB13_TIMESTAMP,val)
-#define bfin_read_CAN_MB13_LENGTH()          bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val)      bfin_write16(CAN_MB13_LENGTH,val)
-#define bfin_read_CAN_MB13_DATA3()           bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val)       bfin_write16(CAN_MB13_DATA3,val)
-#define bfin_read_CAN_MB13_DATA2()           bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val)       bfin_write16(CAN_MB13_DATA2,val)
-#define bfin_read_CAN_MB13_DATA1()           bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val)       bfin_write16(CAN_MB13_DATA1,val)
-#define bfin_read_CAN_MB13_DATA0()           bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val)       bfin_write16(CAN_MB13_DATA0,val)
-
-#define bfin_read_CAN_MB14_ID1()             bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val)         bfin_write16(CAN_MB14_ID1,val)
-#define bfin_read_CAN_MB14_ID0()             bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val)         bfin_write16(CAN_MB14_ID0,val)
-#define bfin_read_CAN_MB14_TIMESTAMP()       bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val)   bfin_write16(CAN_MB14_TIMESTAMP,val)
-#define bfin_read_CAN_MB14_LENGTH()          bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val)      bfin_write16(CAN_MB14_LENGTH,val)
-#define bfin_read_CAN_MB14_DATA3()           bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val)       bfin_write16(CAN_MB14_DATA3,val)
-#define bfin_read_CAN_MB14_DATA2()           bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val)       bfin_write16(CAN_MB14_DATA2,val)
-#define bfin_read_CAN_MB14_DATA1()           bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val)       bfin_write16(CAN_MB14_DATA1,val)
-#define bfin_read_CAN_MB14_DATA0()           bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val)       bfin_write16(CAN_MB14_DATA0,val)
-
-#define bfin_read_CAN_MB15_ID1()             bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val)         bfin_write16(CAN_MB15_ID1,val)
-#define bfin_read_CAN_MB15_ID0()             bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val)         bfin_write16(CAN_MB15_ID0,val)
-#define bfin_read_CAN_MB15_TIMESTAMP()       bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val)   bfin_write16(CAN_MB15_TIMESTAMP,val)
-#define bfin_read_CAN_MB15_LENGTH()          bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val)      bfin_write16(CAN_MB15_LENGTH,val)
-#define bfin_read_CAN_MB15_DATA3()           bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val)       bfin_write16(CAN_MB15_DATA3,val)
-#define bfin_read_CAN_MB15_DATA2()           bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val)       bfin_write16(CAN_MB15_DATA2,val)
-#define bfin_read_CAN_MB15_DATA1()           bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val)       bfin_write16(CAN_MB15_DATA1,val)
-#define bfin_read_CAN_MB15_DATA0()           bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val)       bfin_write16(CAN_MB15_DATA0,val)
-
-#define bfin_read_CAN_MB16_ID1()             bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val)         bfin_write16(CAN_MB16_ID1,val)
-#define bfin_read_CAN_MB16_ID0()             bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val)         bfin_write16(CAN_MB16_ID0,val)
-#define bfin_read_CAN_MB16_TIMESTAMP()       bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val)   bfin_write16(CAN_MB16_TIMESTAMP,val)
-#define bfin_read_CAN_MB16_LENGTH()          bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val)      bfin_write16(CAN_MB16_LENGTH,val)
-#define bfin_read_CAN_MB16_DATA3()           bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val)       bfin_write16(CAN_MB16_DATA3,val)
-#define bfin_read_CAN_MB16_DATA2()           bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val)       bfin_write16(CAN_MB16_DATA2,val)
-#define bfin_read_CAN_MB16_DATA1()           bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val)       bfin_write16(CAN_MB16_DATA1,val)
-#define bfin_read_CAN_MB16_DATA0()           bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val)       bfin_write16(CAN_MB16_DATA0,val)
-
-#define bfin_read_CAN_MB17_ID1()             bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val)         bfin_write16(CAN_MB17_ID1,val)
-#define bfin_read_CAN_MB17_ID0()             bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val)         bfin_write16(CAN_MB17_ID0,val)
-#define bfin_read_CAN_MB17_TIMESTAMP()       bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val)   bfin_write16(CAN_MB17_TIMESTAMP,val)
-#define bfin_read_CAN_MB17_LENGTH()          bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val)      bfin_write16(CAN_MB17_LENGTH,val)
-#define bfin_read_CAN_MB17_DATA3()           bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val)       bfin_write16(CAN_MB17_DATA3,val)
-#define bfin_read_CAN_MB17_DATA2()           bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val)       bfin_write16(CAN_MB17_DATA2,val)
-#define bfin_read_CAN_MB17_DATA1()           bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val)       bfin_write16(CAN_MB17_DATA1,val)
-#define bfin_read_CAN_MB17_DATA0()           bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val)       bfin_write16(CAN_MB17_DATA0,val)
-
-#define bfin_read_CAN_MB18_ID1()             bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val)         bfin_write16(CAN_MB18_ID1,val)
-#define bfin_read_CAN_MB18_ID0()             bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val)         bfin_write16(CAN_MB18_ID0,val)
-#define bfin_read_CAN_MB18_TIMESTAMP()       bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val)   bfin_write16(CAN_MB18_TIMESTAMP,val)
-#define bfin_read_CAN_MB18_LENGTH()          bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val)      bfin_write16(CAN_MB18_LENGTH,val)
-#define bfin_read_CAN_MB18_DATA3()           bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val)       bfin_write16(CAN_MB18_DATA3,val)
-#define bfin_read_CAN_MB18_DATA2()           bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val)       bfin_write16(CAN_MB18_DATA2,val)
-#define bfin_read_CAN_MB18_DATA1()           bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val)       bfin_write16(CAN_MB18_DATA1,val)
-#define bfin_read_CAN_MB18_DATA0()           bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val)       bfin_write16(CAN_MB18_DATA0,val)
-
-#define bfin_read_CAN_MB19_ID1()             bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val)         bfin_write16(CAN_MB19_ID1,val)
-#define bfin_read_CAN_MB19_ID0()             bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val)         bfin_write16(CAN_MB19_ID0,val)
-#define bfin_read_CAN_MB19_TIMESTAMP()       bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val)   bfin_write16(CAN_MB19_TIMESTAMP,val)
-#define bfin_read_CAN_MB19_LENGTH()          bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val)      bfin_write16(CAN_MB19_LENGTH,val)
-#define bfin_read_CAN_MB19_DATA3()           bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val)       bfin_write16(CAN_MB19_DATA3,val)
-#define bfin_read_CAN_MB19_DATA2()           bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val)       bfin_write16(CAN_MB19_DATA2,val)
-#define bfin_read_CAN_MB19_DATA1()           bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val)       bfin_write16(CAN_MB19_DATA1,val)
-#define bfin_read_CAN_MB19_DATA0()           bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val)       bfin_write16(CAN_MB19_DATA0,val)
-
-#define bfin_read_CAN_MB20_ID1()             bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val)         bfin_write16(CAN_MB20_ID1,val)
-#define bfin_read_CAN_MB20_ID0()             bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val)         bfin_write16(CAN_MB20_ID0,val)
-#define bfin_read_CAN_MB20_TIMESTAMP()       bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val)   bfin_write16(CAN_MB20_TIMESTAMP,val)
-#define bfin_read_CAN_MB20_LENGTH()          bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val)      bfin_write16(CAN_MB20_LENGTH,val)
-#define bfin_read_CAN_MB20_DATA3()           bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val)       bfin_write16(CAN_MB20_DATA3,val)
-#define bfin_read_CAN_MB20_DATA2()           bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val)       bfin_write16(CAN_MB20_DATA2,val)
-#define bfin_read_CAN_MB20_DATA1()           bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val)       bfin_write16(CAN_MB20_DATA1,val)
-#define bfin_read_CAN_MB20_DATA0()           bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val)       bfin_write16(CAN_MB20_DATA0,val)
-
-#define bfin_read_CAN_MB21_ID1()             bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val)         bfin_write16(CAN_MB21_ID1,val)
-#define bfin_read_CAN_MB21_ID0()             bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val)         bfin_write16(CAN_MB21_ID0,val)
-#define bfin_read_CAN_MB21_TIMESTAMP()       bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val)   bfin_write16(CAN_MB21_TIMESTAMP,val)
-#define bfin_read_CAN_MB21_LENGTH()          bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val)      bfin_write16(CAN_MB21_LENGTH,val)
-#define bfin_read_CAN_MB21_DATA3()           bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val)       bfin_write16(CAN_MB21_DATA3,val)
-#define bfin_read_CAN_MB21_DATA2()           bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val)       bfin_write16(CAN_MB21_DATA2,val)
-#define bfin_read_CAN_MB21_DATA1()           bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val)       bfin_write16(CAN_MB21_DATA1,val)
-#define bfin_read_CAN_MB21_DATA0()           bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val)       bfin_write16(CAN_MB21_DATA0,val)
-
-#define bfin_read_CAN_MB22_ID1()             bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val)         bfin_write16(CAN_MB22_ID1,val)
-#define bfin_read_CAN_MB22_ID0()             bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val)         bfin_write16(CAN_MB22_ID0,val)
-#define bfin_read_CAN_MB22_TIMESTAMP()       bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val)   bfin_write16(CAN_MB22_TIMESTAMP,val)
-#define bfin_read_CAN_MB22_LENGTH()          bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val)      bfin_write16(CAN_MB22_LENGTH,val)
-#define bfin_read_CAN_MB22_DATA3()           bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val)       bfin_write16(CAN_MB22_DATA3,val)
-#define bfin_read_CAN_MB22_DATA2()           bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val)       bfin_write16(CAN_MB22_DATA2,val)
-#define bfin_read_CAN_MB22_DATA1()           bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val)       bfin_write16(CAN_MB22_DATA1,val)
-#define bfin_read_CAN_MB22_DATA0()           bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val)       bfin_write16(CAN_MB22_DATA0,val)
-
-#define bfin_read_CAN_MB23_ID1()             bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val)         bfin_write16(CAN_MB23_ID1,val)
-#define bfin_read_CAN_MB23_ID0()             bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val)         bfin_write16(CAN_MB23_ID0,val)
-#define bfin_read_CAN_MB23_TIMESTAMP()       bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val)   bfin_write16(CAN_MB23_TIMESTAMP,val)
-#define bfin_read_CAN_MB23_LENGTH()          bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val)      bfin_write16(CAN_MB23_LENGTH,val)
-#define bfin_read_CAN_MB23_DATA3()           bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val)       bfin_write16(CAN_MB23_DATA3,val)
-#define bfin_read_CAN_MB23_DATA2()           bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val)       bfin_write16(CAN_MB23_DATA2,val)
-#define bfin_read_CAN_MB23_DATA1()           bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val)       bfin_write16(CAN_MB23_DATA1,val)
-#define bfin_read_CAN_MB23_DATA0()           bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val)       bfin_write16(CAN_MB23_DATA0,val)
-
-#define bfin_read_CAN_MB24_ID1()             bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val)         bfin_write16(CAN_MB24_ID1,val)
-#define bfin_read_CAN_MB24_ID0()             bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val)         bfin_write16(CAN_MB24_ID0,val)
-#define bfin_read_CAN_MB24_TIMESTAMP()       bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val)   bfin_write16(CAN_MB24_TIMESTAMP,val)
-#define bfin_read_CAN_MB24_LENGTH()          bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val)      bfin_write16(CAN_MB24_LENGTH,val)
-#define bfin_read_CAN_MB24_DATA3()           bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val)       bfin_write16(CAN_MB24_DATA3,val)
-#define bfin_read_CAN_MB24_DATA2()           bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val)       bfin_write16(CAN_MB24_DATA2,val)
-#define bfin_read_CAN_MB24_DATA1()           bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val)       bfin_write16(CAN_MB24_DATA1,val)
-#define bfin_read_CAN_MB24_DATA0()           bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val)       bfin_write16(CAN_MB24_DATA0,val)
-
-#define bfin_read_CAN_MB25_ID1()             bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val)         bfin_write16(CAN_MB25_ID1,val)
-#define bfin_read_CAN_MB25_ID0()             bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val)         bfin_write16(CAN_MB25_ID0,val)
-#define bfin_read_CAN_MB25_TIMESTAMP()       bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val)   bfin_write16(CAN_MB25_TIMESTAMP,val)
-#define bfin_read_CAN_MB25_LENGTH()          bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val)      bfin_write16(CAN_MB25_LENGTH,val)
-#define bfin_read_CAN_MB25_DATA3()           bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val)       bfin_write16(CAN_MB25_DATA3,val)
-#define bfin_read_CAN_MB25_DATA2()           bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val)       bfin_write16(CAN_MB25_DATA2,val)
-#define bfin_read_CAN_MB25_DATA1()           bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val)       bfin_write16(CAN_MB25_DATA1,val)
-#define bfin_read_CAN_MB25_DATA0()           bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val)       bfin_write16(CAN_MB25_DATA0,val)
-
-#define bfin_read_CAN_MB26_ID1()             bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val)         bfin_write16(CAN_MB26_ID1,val)
-#define bfin_read_CAN_MB26_ID0()             bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val)         bfin_write16(CAN_MB26_ID0,val)
-#define bfin_read_CAN_MB26_TIMESTAMP()       bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val)   bfin_write16(CAN_MB26_TIMESTAMP,val)
-#define bfin_read_CAN_MB26_LENGTH()          bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val)      bfin_write16(CAN_MB26_LENGTH,val)
-#define bfin_read_CAN_MB26_DATA3()           bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val)       bfin_write16(CAN_MB26_DATA3,val)
-#define bfin_read_CAN_MB26_DATA2()           bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val)       bfin_write16(CAN_MB26_DATA2,val)
-#define bfin_read_CAN_MB26_DATA1()           bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val)       bfin_write16(CAN_MB26_DATA1,val)
-#define bfin_read_CAN_MB26_DATA0()           bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val)       bfin_write16(CAN_MB26_DATA0,val)
-
-#define bfin_read_CAN_MB27_ID1()             bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val)         bfin_write16(CAN_MB27_ID1,val)
-#define bfin_read_CAN_MB27_ID0()             bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val)         bfin_write16(CAN_MB27_ID0,val)
-#define bfin_read_CAN_MB27_TIMESTAMP()       bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val)   bfin_write16(CAN_MB27_TIMESTAMP,val)
-#define bfin_read_CAN_MB27_LENGTH()          bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val)      bfin_write16(CAN_MB27_LENGTH,val)
-#define bfin_read_CAN_MB27_DATA3()           bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val)       bfin_write16(CAN_MB27_DATA3,val)
-#define bfin_read_CAN_MB27_DATA2()           bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val)       bfin_write16(CAN_MB27_DATA2,val)
-#define bfin_read_CAN_MB27_DATA1()           bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val)       bfin_write16(CAN_MB27_DATA1,val)
-#define bfin_read_CAN_MB27_DATA0()           bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val)       bfin_write16(CAN_MB27_DATA0,val)
-
-#define bfin_read_CAN_MB28_ID1()             bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val)         bfin_write16(CAN_MB28_ID1,val)
-#define bfin_read_CAN_MB28_ID0()             bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val)         bfin_write16(CAN_MB28_ID0,val)
-#define bfin_read_CAN_MB28_TIMESTAMP()       bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val)   bfin_write16(CAN_MB28_TIMESTAMP,val)
-#define bfin_read_CAN_MB28_LENGTH()          bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val)      bfin_write16(CAN_MB28_LENGTH,val)
-#define bfin_read_CAN_MB28_DATA3()           bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val)       bfin_write16(CAN_MB28_DATA3,val)
-#define bfin_read_CAN_MB28_DATA2()           bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val)       bfin_write16(CAN_MB28_DATA2,val)
-#define bfin_read_CAN_MB28_DATA1()           bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val)       bfin_write16(CAN_MB28_DATA1,val)
-#define bfin_read_CAN_MB28_DATA0()           bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val)       bfin_write16(CAN_MB28_DATA0,val)
-
-#define bfin_read_CAN_MB29_ID1()             bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val)         bfin_write16(CAN_MB29_ID1,val)
-#define bfin_read_CAN_MB29_ID0()             bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val)         bfin_write16(CAN_MB29_ID0,val)
-#define bfin_read_CAN_MB29_TIMESTAMP()       bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val)   bfin_write16(CAN_MB29_TIMESTAMP,val)
-#define bfin_read_CAN_MB29_LENGTH()          bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val)      bfin_write16(CAN_MB29_LENGTH,val)
-#define bfin_read_CAN_MB29_DATA3()           bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val)       bfin_write16(CAN_MB29_DATA3,val)
-#define bfin_read_CAN_MB29_DATA2()           bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val)       bfin_write16(CAN_MB29_DATA2,val)
-#define bfin_read_CAN_MB29_DATA1()           bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val)       bfin_write16(CAN_MB29_DATA1,val)
-#define bfin_read_CAN_MB29_DATA0()           bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val)       bfin_write16(CAN_MB29_DATA0,val)
-
-#define bfin_read_CAN_MB30_ID1()             bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val)         bfin_write16(CAN_MB30_ID1,val)
-#define bfin_read_CAN_MB30_ID0()             bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val)         bfin_write16(CAN_MB30_ID0,val)
-#define bfin_read_CAN_MB30_TIMESTAMP()       bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val)   bfin_write16(CAN_MB30_TIMESTAMP,val)
-#define bfin_read_CAN_MB30_LENGTH()          bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val)      bfin_write16(CAN_MB30_LENGTH,val)
-#define bfin_read_CAN_MB30_DATA3()           bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val)       bfin_write16(CAN_MB30_DATA3,val)
-#define bfin_read_CAN_MB30_DATA2()           bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val)       bfin_write16(CAN_MB30_DATA2,val)
-#define bfin_read_CAN_MB30_DATA1()           bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val)       bfin_write16(CAN_MB30_DATA1,val)
-#define bfin_read_CAN_MB30_DATA0()           bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val)       bfin_write16(CAN_MB30_DATA0,val)
-
-#define bfin_read_CAN_MB31_ID1()             bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val)         bfin_write16(CAN_MB31_ID1,val)
-#define bfin_read_CAN_MB31_ID0()             bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val)         bfin_write16(CAN_MB31_ID0,val)
-#define bfin_read_CAN_MB31_TIMESTAMP()       bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val)   bfin_write16(CAN_MB31_TIMESTAMP,val)
-#define bfin_read_CAN_MB31_LENGTH()          bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val)      bfin_write16(CAN_MB31_LENGTH,val)
-#define bfin_read_CAN_MB31_DATA3()           bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val)       bfin_write16(CAN_MB31_DATA3,val)
-#define bfin_read_CAN_MB31_DATA2()           bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val)       bfin_write16(CAN_MB31_DATA2,val)
-#define bfin_read_CAN_MB31_DATA1()           bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val)       bfin_write16(CAN_MB31_DATA1,val)
-#define bfin_read_CAN_MB31_DATA0()           bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val)       bfin_write16(CAN_MB31_DATA0,val)
-
-/* CAN Mailbox Area Macros              */
-#define bfin_read_CAN_MB_ID1(x)()            bfin_read16(CAN_MB_ID1(x))
-#define bfin_write_CAN_MB_ID1(x)(val)        bfin_write16(CAN_MB_ID1(x),val)
-#define bfin_read_CAN_MB_ID0(x)()            bfin_read16(CAN_MB_ID0(x))
-#define bfin_write_CAN_MB_ID0(x)(val)        bfin_write16(CAN_MB_ID0(x),val)
-#define bfin_read_CAN_MB_TIMESTAMP(x)()      bfin_read16(CAN_MB_TIMESTAMP(x))
-#define bfin_write_CAN_MB_TIMESTAMP(x)(val)  bfin_write16(CAN_MB_TIMESTAMP(x),val)
-#define bfin_read_CAN_MB_LENGTH(x)()         bfin_read16(CAN_MB_LENGTH(x))
-#define bfin_write_CAN_MB_LENGTH(x)(val)     bfin_write16(CAN_MB_LENGTH(x),val)
-#define bfin_read_CAN_MB_DATA3(x)()          bfin_read16(CAN_MB_DATA3(x))
-#define bfin_write_CAN_MB_DATA3(x)(val)      bfin_write16(CAN_MB_DATA3(x),val)
-#define bfin_read_CAN_MB_DATA2(x)()          bfin_read16(CAN_MB_DATA2(x))
-#define bfin_write_CAN_MB_DATA2(x)(val)      bfin_write16(CAN_MB_DATA2(x),val)
-#define bfin_read_CAN_MB_DATA1(x)()          bfin_read16(CAN_MB_DATA1(x))
-#define bfin_write_CAN_MB_DATA1(x)(val)      bfin_write16(CAN_MB_DATA1(x),val)
-#define bfin_read_CAN_MB_DATA0(x)()          bfin_read16(CAN_MB_DATA0(x))
-#define bfin_write_CAN_MB_DATA0(x)(val)      bfin_write16(CAN_MB_DATA0(x),val)
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
-#define bfin_read_PORTF_FER()                bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)            bfin_write16(PORTF_FER,val)
-#define bfin_read_PORTG_FER()                bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)            bfin_write16(PORTG_FER,val)
-#define bfin_read_PORTH_FER()                bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)            bfin_write16(PORTH_FER,val)
-#define bfin_read_PORT_MUX()                 bfin_read16(BFIN_PORT_MUX)
-#define bfin_write_PORT_MUX(val)             bfin_write16(BFIN_PORT_MUX,val)
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
-#define bfin_read_HMDMA0_CONTROL()           bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)       bfin_write16(HMDMA0_CONTROL,val)
-#define bfin_read_HMDMA0_ECINIT()            bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)        bfin_write16(HMDMA0_ECINIT,val)
-#define bfin_read_HMDMA0_BCINIT()            bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)        bfin_write16(HMDMA0_BCINIT,val)
-#define bfin_read_HMDMA0_ECURGENT()          bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)      bfin_write16(HMDMA0_ECURGENT,val)
-#define bfin_read_HMDMA0_ECOVERFLOW()        bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)    bfin_write16(HMDMA0_ECOVERFLOW,val)
-#define bfin_read_HMDMA0_ECOUNT()            bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)        bfin_write16(HMDMA0_ECOUNT,val)
-#define bfin_read_HMDMA0_BCOUNT()            bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)        bfin_write16(HMDMA0_BCOUNT,val)
-
-#define bfin_read_HMDMA1_CONTROL()           bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)       bfin_write16(HMDMA1_CONTROL,val)
-#define bfin_read_HMDMA1_ECINIT()            bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)        bfin_write16(HMDMA1_ECINIT,val)
-#define bfin_read_HMDMA1_BCINIT()            bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)        bfin_write16(HMDMA1_BCINIT,val)
-#define bfin_read_HMDMA1_ECURGENT()          bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)      bfin_write16(HMDMA1_ECURGENT,val)
-#define bfin_read_HMDMA1_ECOVERFLOW()        bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)    bfin_write16(HMDMA1_ECOVERFLOW,val)
-#define bfin_read_HMDMA1_ECOUNT()            bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)        bfin_write16(HMDMA1_ECOUNT,val)
-#define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)
-
-#endif                          /* _CDEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF537.h b/include/asm-blackfin/mach-bf537/cdefBF537.h
deleted file mode 100644
index b8fc949a991f..000000000000
--- a/include/asm-blackfin/mach-bf537/cdefBF537.h
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *      System MMR Register Map
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF537_H
-#define _CDEF_BF537_H
-
-/* Include MMRs Common to BF534                                                                 */
-#include "cdefBF534.h"
-
-/* Include all Core registers and bit definitions                                                                       */
-#include "defBF537.h"
-
-/* Include Macro "Defines" For EMAC (Unique to BF536/BF537              */
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                               */
-#define bfin_read_EMAC_OPMODE()              bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)          bfin_write32(EMAC_OPMODE,val)
-#define bfin_read_EMAC_ADDRLO()              bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)          bfin_write32(EMAC_ADDRLO,val)
-#define bfin_read_EMAC_ADDRHI()              bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)          bfin_write32(EMAC_ADDRHI,val)
-#define bfin_read_EMAC_HASHLO()              bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)          bfin_write32(EMAC_HASHLO,val)
-#define bfin_read_EMAC_HASHHI()              bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)          bfin_write32(EMAC_HASHHI,val)
-#define bfin_read_EMAC_STAADD()              bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)          bfin_write32(EMAC_STAADD,val)
-#define bfin_read_EMAC_STADAT()              bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)          bfin_write32(EMAC_STADAT,val)
-#define bfin_read_EMAC_FLC()                 bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)             bfin_write32(EMAC_FLC,val)
-#define bfin_read_EMAC_VLAN1()               bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)           bfin_write32(EMAC_VLAN1,val)
-#define bfin_read_EMAC_VLAN2()               bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)           bfin_write32(EMAC_VLAN2,val)
-#define bfin_read_EMAC_WKUP_CTL()            bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)        bfin_write32(EMAC_WKUP_CTL,val)
-#define bfin_read_EMAC_WKUP_FFMSK0()         bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val)     bfin_write32(EMAC_WKUP_FFMSK0,val)
-#define bfin_read_EMAC_WKUP_FFMSK1()         bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val)     bfin_write32(EMAC_WKUP_FFMSK1,val)
-#define bfin_read_EMAC_WKUP_FFMSK2()         bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val)     bfin_write32(EMAC_WKUP_FFMSK2,val)
-#define bfin_read_EMAC_WKUP_FFMSK3()         bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val)     bfin_write32(EMAC_WKUP_FFMSK3,val)
-#define bfin_read_EMAC_WKUP_FFCMD()          bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val)      bfin_write32(EMAC_WKUP_FFCMD,val)
-#define bfin_read_EMAC_WKUP_FFOFF()          bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val)      bfin_write32(EMAC_WKUP_FFOFF,val)
-#define bfin_read_EMAC_WKUP_FFCRC0()         bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val)     bfin_write32(EMAC_WKUP_FFCRC0,val)
-#define bfin_read_EMAC_WKUP_FFCRC1()         bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val)     bfin_write32(EMAC_WKUP_FFCRC1,val)
-
-#define bfin_read_EMAC_SYSCTL()              bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)          bfin_write32(EMAC_SYSCTL,val)
-#define bfin_read_EMAC_SYSTAT()              bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)          bfin_write32(EMAC_SYSTAT,val)
-#define bfin_read_EMAC_RX_STAT()             bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)         bfin_write32(EMAC_RX_STAT,val)
-#define bfin_read_EMAC_RX_STKY()             bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)         bfin_write32(EMAC_RX_STKY,val)
-#define bfin_read_EMAC_RX_IRQE()             bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)         bfin_write32(EMAC_RX_IRQE,val)
-#define bfin_read_EMAC_TX_STAT()             bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)         bfin_write32(EMAC_TX_STAT,val)
-#define bfin_read_EMAC_TX_STKY()             bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)         bfin_write32(EMAC_TX_STKY,val)
-#define bfin_read_EMAC_TX_IRQE()             bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)         bfin_write32(EMAC_TX_IRQE,val)
-
-#define bfin_read_EMAC_MMC_CTL()             bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)         bfin_write32(EMAC_MMC_CTL,val)
-#define bfin_read_EMAC_MMC_RIRQS()           bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val)       bfin_write32(EMAC_MMC_RIRQS,val)
-#define bfin_read_EMAC_MMC_RIRQE()           bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val)       bfin_write32(EMAC_MMC_RIRQE,val)
-#define bfin_read_EMAC_MMC_TIRQS()           bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val)       bfin_write32(EMAC_MMC_TIRQS,val)
-#define bfin_read_EMAC_MMC_TIRQE()           bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val)       bfin_write32(EMAC_MMC_TIRQE,val)
-
-#define bfin_read_EMAC_RXC_OK()              bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)          bfin_write32(EMAC_RXC_OK,val)
-#define bfin_read_EMAC_RXC_FCS()             bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)         bfin_write32(EMAC_RXC_FCS,val)
-#define bfin_read_EMAC_RXC_ALIGN()           bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val)       bfin_write32(EMAC_RXC_ALIGN,val)
-#define bfin_read_EMAC_RXC_OCTET()           bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val)       bfin_write32(EMAC_RXC_OCTET,val)
-#define bfin_read_EMAC_RXC_DMAOVF()          bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val)      bfin_write32(EMAC_RXC_DMAOVF,val)
-#define bfin_read_EMAC_RXC_UNICST()          bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val)      bfin_write32(EMAC_RXC_UNICST,val)
-#define bfin_read_EMAC_RXC_MULTI()           bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val)       bfin_write32(EMAC_RXC_MULTI,val)
-#define bfin_read_EMAC_RXC_BROAD()           bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val)       bfin_write32(EMAC_RXC_BROAD,val)
-#define bfin_read_EMAC_RXC_LNERRI()          bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val)      bfin_write32(EMAC_RXC_LNERRI,val)
-#define bfin_read_EMAC_RXC_LNERRO()          bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val)      bfin_write32(EMAC_RXC_LNERRO,val)
-#define bfin_read_EMAC_RXC_LONG()            bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)        bfin_write32(EMAC_RXC_LONG,val)
-#define bfin_read_EMAC_RXC_MACCTL()          bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val)      bfin_write32(EMAC_RXC_MACCTL,val)
-#define bfin_read_EMAC_RXC_OPCODE()          bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val)      bfin_write32(EMAC_RXC_OPCODE,val)
-#define bfin_read_EMAC_RXC_PAUSE()           bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val)       bfin_write32(EMAC_RXC_PAUSE,val)
-#define bfin_read_EMAC_RXC_ALLFRM()          bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val)      bfin_write32(EMAC_RXC_ALLFRM,val)
-#define bfin_read_EMAC_RXC_ALLOCT()          bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val)      bfin_write32(EMAC_RXC_ALLOCT,val)
-#define bfin_read_EMAC_RXC_TYPED()           bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val)       bfin_write32(EMAC_RXC_TYPED,val)
-#define bfin_read_EMAC_RXC_SHORT()           bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val)       bfin_write32(EMAC_RXC_SHORT,val)
-#define bfin_read_EMAC_RXC_EQ64()            bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)        bfin_write32(EMAC_RXC_EQ64,val)
-#define bfin_read_EMAC_RXC_LT128()           bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val)       bfin_write32(EMAC_RXC_LT128,val)
-#define bfin_read_EMAC_RXC_LT256()           bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val)       bfin_write32(EMAC_RXC_LT256,val)
-#define bfin_read_EMAC_RXC_LT512()           bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val)       bfin_write32(EMAC_RXC_LT512,val)
-#define bfin_read_EMAC_RXC_LT1024()          bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val)      bfin_write32(EMAC_RXC_LT1024,val)
-#define bfin_read_EMAC_RXC_GE1024()          bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val)      bfin_write32(EMAC_RXC_GE1024,val)
-
-#define bfin_read_EMAC_TXC_OK()              bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)          bfin_write32(EMAC_TXC_OK,val)
-#define bfin_read_EMAC_TXC_1COL()            bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)        bfin_write32(EMAC_TXC_1COL,val)
-#define bfin_read_EMAC_TXC_GT1COL()          bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val)      bfin_write32(EMAC_TXC_GT1COL,val)
-#define bfin_read_EMAC_TXC_OCTET()           bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val)       bfin_write32(EMAC_TXC_OCTET,val)
-#define bfin_read_EMAC_TXC_DEFER()           bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val)       bfin_write32(EMAC_TXC_DEFER,val)
-#define bfin_read_EMAC_TXC_LATECL()          bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val)      bfin_write32(EMAC_TXC_LATECL,val)
-#define bfin_read_EMAC_TXC_XS_COL()          bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val)      bfin_write32(EMAC_TXC_XS_COL,val)
-#define bfin_read_EMAC_TXC_DMAUND()          bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val)      bfin_write32(EMAC_TXC_DMAUND,val)
-#define bfin_read_EMAC_TXC_CRSERR()          bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val)      bfin_write32(EMAC_TXC_CRSERR,val)
-#define bfin_read_EMAC_TXC_UNICST()          bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val)      bfin_write32(EMAC_TXC_UNICST,val)
-#define bfin_read_EMAC_TXC_MULTI()           bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val)       bfin_write32(EMAC_TXC_MULTI,val)
-#define bfin_read_EMAC_TXC_BROAD()           bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val)       bfin_write32(EMAC_TXC_BROAD,val)
-#define bfin_read_EMAC_TXC_XS_DFR()          bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val)      bfin_write32(EMAC_TXC_XS_DFR,val)
-#define bfin_read_EMAC_TXC_MACCTL()          bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val)      bfin_write32(EMAC_TXC_MACCTL,val)
-#define bfin_read_EMAC_TXC_ALLFRM()          bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val)      bfin_write32(EMAC_TXC_ALLFRM,val)
-#define bfin_read_EMAC_TXC_ALLOCT()          bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val)      bfin_write32(EMAC_TXC_ALLOCT,val)
-#define bfin_read_EMAC_TXC_EQ64()            bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)        bfin_write32(EMAC_TXC_EQ64,val)
-#define bfin_read_EMAC_TXC_LT128()           bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val)       bfin_write32(EMAC_TXC_LT128,val)
-#define bfin_read_EMAC_TXC_LT256()           bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val)       bfin_write32(EMAC_TXC_LT256,val)
-#define bfin_read_EMAC_TXC_LT512()           bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val)       bfin_write32(EMAC_TXC_LT512,val)
-#define bfin_read_EMAC_TXC_LT1024()          bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val)      bfin_write32(EMAC_TXC_LT1024,val)
-#define bfin_read_EMAC_TXC_GE1024()          bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val)      bfin_write32(EMAC_TXC_GE1024,val)
-#define bfin_read_EMAC_TXC_ABORT()           bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val)       bfin_write32(EMAC_TXC_ABORT,val)
-
-#endif                          /* _CDEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
deleted file mode 100644
index d0d80d3152ba..000000000000
--- a/include/asm-blackfin/mach-bf537/defBF534.h
+++ /dev/null
@@ -1,2527 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF534_H
-#define _DEF_BF534_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/************************************************************************************
-** System MMR Register Map
-*************************************************************************************/
-/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
-#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
-#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
-#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
-#define CHIPID                          0xFFC00014      /* Chip ID Register                                             */
-
-/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
-#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
-#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
-#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
-#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register                                      */
-#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
-#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
-#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
-#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
-#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register                            */
-#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register                            */
-
-/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
-#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
-#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
-#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
-
-/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
-#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
-#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
-#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
-#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
-#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
-#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
-#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
-
-/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
-#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
-#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
-#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
-#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
-#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
-#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
-#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
-#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
-#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
-#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
-#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
-#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
-
-/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
-
-/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
-#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
-#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
-#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
-#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
-
-#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
-#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
-#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
-#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
-
-#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
-#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
-#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
-#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
-
-#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
-#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
-#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
-#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
-
-#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
-#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
-#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
-#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
-
-#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
-#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
-#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
-#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
-
-#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
-#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
-#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
-#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
-
-#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
-#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
-#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
-#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
-
-#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
-#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
-#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
-
-/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
-#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
-#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
-#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
-#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
-#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
-#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
-#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
-#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
-#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
-#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
-#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
-#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
-#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
-#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
-#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
-
-/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
-#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
-#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
-#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
-#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
-#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
-#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
-#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
-#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
-#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
-#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
-#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
-#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
-#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
-#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
-#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
-
-/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
-#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
-#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
-#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
-#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
-#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
-#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
-#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
-#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
-#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
-#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
-#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
-#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
-#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
-#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
-#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
-#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
-
-/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
-#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
-#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
-#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
-#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
-#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
-#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
-#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
-
-/* DMA Traffic Control Registers                                                                                                        */
-#define DMA_TC_PER                      0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TC_CNT                      0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* Alternate deprecated register names (below) provided for backwards code compatibility */
-#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
-#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
-
-/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
-#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
-#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
-#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
-#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
-#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
-#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
-#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
-#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
-#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
-#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
-#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
-#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
-#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
-
-#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
-#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
-#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
-#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
-#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
-#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
-#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
-#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
-#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
-#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
-#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
-#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
-#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
-
-#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
-#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
-#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
-#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
-#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
-#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
-#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
-#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
-#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
-#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
-#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
-#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
-#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
-
-#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
-#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
-#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
-#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
-#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
-#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
-#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
-#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
-#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
-#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
-#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
-#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
-#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
-
-#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
-#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
-#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
-#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
-#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
-#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
-#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
-#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
-#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
-#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
-#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
-#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
-#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
-
-#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
-#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
-#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
-#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
-#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
-#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
-#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
-#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
-#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
-#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
-#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
-#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
-#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
-
-#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
-#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
-#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
-#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
-#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
-#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
-#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
-#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
-#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
-#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
-#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
-#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
-#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
-
-#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
-#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
-#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
-#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
-#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
-#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
-#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
-#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
-#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
-#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
-#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
-#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
-#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
-
-#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
-#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
-#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
-#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
-#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
-#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
-#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
-#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
-#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
-#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
-#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
-#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
-#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
-
-#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
-#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
-#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
-#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
-#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
-#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
-#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
-#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
-#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
-#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
-#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
-#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
-#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
-
-#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
-#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
-#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
-#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
-#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
-#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
-#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
-#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
-#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
-#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
-#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
-#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
-#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
-
-#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
-#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
-#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
-#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
-#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
-#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
-#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
-#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
-#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
-#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
-#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
-#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
-#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
-
-#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
-#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
-#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
-#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
-#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
-#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
-#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
-#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
-#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
-#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
-#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
-#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
-#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
-
-#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
-#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
-#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
-#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
-#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
-#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
-#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
-#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
-#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
-#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
-#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
-#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
-#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
-
-#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
-#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
-#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
-#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
-#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
-#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
-#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
-#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
-#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
-#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
-#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
-#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
-#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
-
-#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
-#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
-#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
-#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
-#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
-#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
-#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
-#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
-#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
-#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
-#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
-#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
-#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
-
-/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
-#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
-#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
-#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
-#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
-#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
-
-/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
-#define TWI0_REGBASE                    0xFFC01400
-#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
-#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
-#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
-#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
-#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
-#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
-#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
-#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
-#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
-#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
-#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
-#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
-#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
-#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
-#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
-#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
-
-/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
-#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
-#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
-#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
-#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
-#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
-#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
-#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
-#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
-#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
-#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
-#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
-#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
-#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
-#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
-#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
-
-/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
-#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
-#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
-#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
-#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
-#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
-#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
-#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
-#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
-#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
-#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
-#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
-#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
-#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
-#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
-#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
-#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
-#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
-
-/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
-#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
-#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
-#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
-#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
-#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
-#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
-#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
-#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
-#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
-#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
-#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
-#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
-
-/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                                               */
-/* For Mailboxes 0-15                                                                                                                                   */
-#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1                                                 */
-#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1                                              */
-#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1                                   */
-#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1                                 */
-#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1                                   */
-#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1                             */
-#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1                                */
-#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1                                   */
-#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1                */
-#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1                */
-#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1                                 */
-#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1                                  */
-#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmit reg 1  */
-
-/* For Mailboxes 16-31                                                                                                                                  */
-#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2                                                 */
-#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2                                              */
-#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2                                   */
-#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2                                 */
-#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2                                   */
-#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2                             */
-#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2                                */
-#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2                                   */
-#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2                */
-#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2                */
-#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2                                 */
-#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2                                  */
-#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmit reg 2  */
-
-/* CAN Configuration, Control, and Status Registers                                                                             */
-#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0                  */
-#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1                  */
-#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                                                               */
-#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register                                               */
-#define CAN_CEC                         0xFFC02A90      /* Error Counter Register                                               */
-#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register                             */
-#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register                               */
-#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register                               */
-#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register                                              */
-#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register                                   */
-
-#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature                    */
-#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level                                   */
-#define CAN_ESR                         0xFFC02AB4      /* Error Status Register                                                */
-#define CAN_UCREG                       0xFFC02AC0      /* Universal Counter Register/Capture Register  */
-#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter                                                    */
-#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Force Reload Register              */
-#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register             */
-
-/* Mailbox Acceptance Masks                                                                                             */
-#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask        */
-#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask       */
-#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask        */
-#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask       */
-#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask        */
-#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask       */
-#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask        */
-#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask       */
-#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask        */
-#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask       */
-#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask        */
-#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask       */
-#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask        */
-#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask       */
-#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask        */
-#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask       */
-#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask        */
-#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask       */
-#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask        */
-#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask       */
-#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask       */
-#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask      */
-#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask       */
-#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask      */
-#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask       */
-#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask      */
-#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask       */
-#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask      */
-#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask       */
-#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask      */
-#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask       */
-#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask      */
-
-#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask       */
-#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask      */
-#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask       */
-#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask      */
-#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask       */
-#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask      */
-#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask       */
-#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask      */
-#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask       */
-#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask      */
-#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask       */
-#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask      */
-#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask       */
-#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask      */
-#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask       */
-#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask      */
-#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask       */
-#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask      */
-#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask       */
-#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask      */
-#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask       */
-#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask      */
-#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask       */
-#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask      */
-#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask       */
-#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask      */
-#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask       */
-#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask      */
-#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask       */
-#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask      */
-#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask       */
-#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask      */
-
-/* CAN Acceptance Mask Macros                           */
-#define CAN_AM_L(x)             (CAN_AM00L+((x)*0x8))
-#define CAN_AM_H(x)             (CAN_AM00H+((x)*0x8))
-
-/* Mailbox Registers                                                                                                                            */
-#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register        */
-#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register       */
-#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register       */
-#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register       */
-#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register          */
-#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register          */
-#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register            */
-#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register           */
-
-#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register        */
-#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register       */
-#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register       */
-#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register       */
-#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register          */
-#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register          */
-#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register            */
-#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register           */
-
-#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register        */
-#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register       */
-#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register       */
-#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register       */
-#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register          */
-#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register          */
-#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register            */
-#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register           */
-
-#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register        */
-#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register       */
-#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register       */
-#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register       */
-#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register          */
-#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register          */
-#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register            */
-#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register           */
-
-#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register        */
-#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register       */
-#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register       */
-#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register       */
-#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register          */
-#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register          */
-#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register            */
-#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register           */
-
-#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register        */
-#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register       */
-#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register       */
-#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register       */
-#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register          */
-#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register          */
-#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register            */
-#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register           */
-
-#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register        */
-#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register       */
-#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register       */
-#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register       */
-#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register          */
-#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register          */
-#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register            */
-#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register           */
-
-#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register        */
-#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register       */
-#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register       */
-#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register       */
-#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register          */
-#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register          */
-#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register            */
-#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register           */
-
-#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register        */
-#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register       */
-#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register       */
-#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register       */
-#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register          */
-#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register          */
-#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register            */
-#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register           */
-
-#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register        */
-#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register       */
-#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register       */
-#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register       */
-#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register          */
-#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register          */
-#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register            */
-#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register           */
-
-#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register       */
-#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register      */
-#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register      */
-#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register      */
-#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register         */
-#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register         */
-#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register           */
-#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register          */
-
-#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register       */
-#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register      */
-#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register      */
-#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register      */
-#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register         */
-#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register         */
-#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register           */
-#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register          */
-
-#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register       */
-#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register      */
-#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register      */
-#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register      */
-#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register         */
-#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register         */
-#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register           */
-#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register          */
-
-#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register       */
-#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register      */
-#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register      */
-#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register      */
-#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register         */
-#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register         */
-#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register           */
-#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register          */
-
-#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register       */
-#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register      */
-#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register      */
-#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register      */
-#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register         */
-#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register         */
-#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register           */
-#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register          */
-
-#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register       */
-#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register      */
-#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register      */
-#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register      */
-#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register         */
-#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register         */
-#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register           */
-#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register          */
-
-#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register       */
-#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register      */
-#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register      */
-#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register      */
-#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register         */
-#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register         */
-#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register           */
-#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register          */
-
-#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register       */
-#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register      */
-#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register      */
-#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register      */
-#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register         */
-#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register         */
-#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register           */
-#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register          */
-
-#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register       */
-#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register      */
-#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register      */
-#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register      */
-#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register         */
-#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register         */
-#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register           */
-#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register          */
-
-#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register       */
-#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register      */
-#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register      */
-#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register      */
-#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register         */
-#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register         */
-#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register           */
-#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register          */
-
-#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register       */
-#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register      */
-#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register      */
-#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register      */
-#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register         */
-#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register         */
-#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register           */
-#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register          */
-
-#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register       */
-#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register      */
-#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register      */
-#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register      */
-#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register         */
-#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register         */
-#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register           */
-#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register          */
-
-#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register       */
-#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register      */
-#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register      */
-#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register      */
-#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register         */
-#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register         */
-#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register           */
-#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register          */
-
-#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register       */
-#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register      */
-#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register      */
-#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register      */
-#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register         */
-#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register         */
-#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register           */
-#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register          */
-
-#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register       */
-#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register      */
-#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register      */
-#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register      */
-#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register         */
-#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register         */
-#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register           */
-#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register          */
-
-#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register       */
-#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register      */
-#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register      */
-#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register      */
-#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register         */
-#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register         */
-#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register           */
-#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register          */
-
-#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register       */
-#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register      */
-#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register      */
-#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register      */
-#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register         */
-#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register         */
-#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register           */
-#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register          */
-
-#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register       */
-#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register      */
-#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register      */
-#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register      */
-#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register         */
-#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register         */
-#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register           */
-#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register          */
-
-#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register       */
-#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register      */
-#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register      */
-#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register      */
-#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register         */
-#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register         */
-#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register           */
-#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register          */
-
-#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register       */
-#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register      */
-#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register      */
-#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register      */
-#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register         */
-#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register         */
-#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register           */
-#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register          */
-
-#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register       */
-#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register      */
-#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register      */
-#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register      */
-#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register         */
-#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register         */
-#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register           */
-#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register          */
-
-#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register       */
-#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register      */
-#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register      */
-#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register      */
-#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register         */
-#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register         */
-#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register           */
-#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register          */
-
-/* CAN Mailbox Area Macros                              */
-#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
-#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
-#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
-#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
-#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
-#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
-#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
-#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
-
-/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
-#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
-#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
-#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
-#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
-
-/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
-#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
-#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
-#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
-#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
-#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
-#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
-#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
-
-#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
-#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
-#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
-#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
-#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
-#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
-#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-/*
-** ********************* PLL AND RESET MASKS ****************************************/
-/* PLL_CTL Masks                                                                                                                                        */
-#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
-#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
-#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
-#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
-#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
-#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
-#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
-#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
-/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
-#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
-
-/* PLL_DIV Masks                                                                                                                */
-#define SSEL                    0x000F  /* System Select                                                */
-#define CSEL                    0x0030  /* Core Select                                                  */
-#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
-#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
-#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
-#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
-/* PLL_DIV Macros                                                                                                               */
-#define SET_SSEL(x)             ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
-#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
-#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
-#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /*              GAIN = 5                */
-#define GAIN_10                 0x0004  /*              GAIN = 10               */
-#define GAIN_20                 0x0008  /*              GAIN = 20               */
-#define GAIN_50                 0x000C  /*              GAIN = 50               */
-
-#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
-#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
-#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
-#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
-#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
-#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
-#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
-#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
-#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
-#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
-#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
-#define CANWE                   0x0200  /* Enable CAN Wakeup From Hibernate                     */
-#define PHYWE                   0x0400  /* Enable PHY Wakeup From Hibernate                     */
-#define CLKBUFOE                0x4000  /* CLKIN Buffer Output Enable */
-#define PHYCLKOE                CLKBUFOE        /* Alternative legacy name for the above */
-#define SCKELOW         0x8000  /* Enable Drive CKE Low During Reset            */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* SWRST Masks                                                                                                                                          */
-#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
-#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
-#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
-#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
-#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
-
-/* SYSCR Masks                                                                                                                                                          */
-#define BMODE                           0x0007  /* Boot Mode - Latched During HW Reset From Mode Pins   */
-#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
-
-/* SIC_IAR0 Macros                                                                                                                      */
-#define P0_IVG(x)               (((x)&0xF)-7)   /* Peripheral #0 assigned IVG #x        */
-#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
-#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
-#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
-#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
-#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
-#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
-#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
-
-/* SIC_IAR1 Macros                                                                                                                      */
-#define P8_IVG(x)               (((x)&0xF)-7)   /* Peripheral #8 assigned IVG #x        */
-#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
-#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
-#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
-#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
-#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
-#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
-#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
-
-/* SIC_IAR2 Macros                                                                                                                      */
-#define P16_IVG(x)              (((x)&0xF)-7)   /* Peripheral #16 assigned IVG #x       */
-#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
-#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
-#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
-#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
-#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
-#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
-#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
-
-/* SIC_IAR3 Macros                                                                                                                      */
-#define P24_IVG(x)              (((x)&0xF)-7)   /* Peripheral #24 assigned IVG #x       */
-#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
-#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
-#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
-#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
-#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
-#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
-#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
-
-/* SIC_IMASK Masks                                                                                                                                              */
-#define SIC_UNMASK_ALL  0x00000000      /* Unmask all peripheral interrupts     */
-#define SIC_MASK_ALL    0xFFFFFFFF      /* Mask all peripheral interrupts       */
-#define SIC_MASK(x)             (1 << ((x)&0x1F))       /* Mask Peripheral #x interrupt         */
-#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
-
-/* SIC_IWR Masks                                                                                                                                                */
-#define IWR_DISABLE_ALL 0x00000000      /* Wakeup Disable all peripherals       */
-#define IWR_ENABLE_ALL  0xFFFFFFFF      /* Wakeup Enable all peripherals        */
-#define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
-#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
-
-/* ************** UART CONTROLLER MASKS *************************/
-/* UARTx_LCR Masks                                                                                              */
-#define WLS(x)          (((x)-5) & 0x03)        /* Word Length Select   */
-#define STB                     0x04    /* Stop Bits                    */
-#define PEN                     0x08    /* Parity Enable                */
-#define EPS                     0x10    /* Even Parity Select   */
-#define STP                     0x20    /* Stick Parity                 */
-#define SB                      0x40    /* Set Break                    */
-#define DLAB            0x80    /* Divisor Latch Access */
-
-/* UARTx_MCR Mask                                                                               */
-#define LOOP_ENA                0x10    /* Loopback Mode Enable         */
-#define LOOP_ENA_P      0x04
-/* UARTx_LSR Masks                                                                              */
-#define DR                      0x01    /* Data Ready                           */
-#define OE                      0x02    /* Overrun Error                        */
-#define PE                      0x04    /* Parity Error                         */
-#define FE                      0x08    /* Framing Error                        */
-#define BI                      0x10    /* Break Interrupt                      */
-#define THRE            0x20    /* THR Empty                            */
-#define TEMT            0x40    /* TSR and UART_THR Empty       */
-
-/* UARTx_IER Masks                                                                                                                      */
-#define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
-#define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
-#define ELSI            0x04    /* Enable RX Status Interrupt                           */
-
-/* UARTx_IIR Masks                                                                                                              */
-#define NINT            0x01    /* Pending Interrupt                                    */
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UARTx_GCTL Masks                                                                                                     */
-#define UCEN            0x01    /* Enable UARTx Clocks                          */
-#define IREN            0x02    /* Enable IrDA Mode                                     */
-#define TPOLC           0x04    /* IrDA TX Polarity Change                      */
-#define RPOLC           0x08    /* IrDA RX Polarity Change                      */
-#define FPE                     0x10    /* Force Parity Error On Transmit       */
-#define FFE                     0x20    /* Force Framing Error On Transmit      */
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
-/* SPI_CTL Masks                                                                                                                                        */
-#define TIMOD           0x0003  /* Transfer Initiate Mode                                                       */
-#define RDBR_CORE       0x0000  /*              RDBR Read Initiates, IRQ When RDBR Full         */
-#define TDBR_CORE       0x0001  /*              TDBR Write Initiates, IRQ When TDBR Empty       */
-#define RDBR_DMA        0x0002  /*              DMA Read, DMA Until FIFO Empty                          */
-#define TDBR_DMA        0x0003  /*              DMA Write, DMA Until FIFO Full                          */
-#define SZ                      0x0004  /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
-#define GM                      0x0008  /* Get More (When RDBR Full, Overwrite/Discard*)        */
-#define PSSE            0x0010  /* Slave-Select Input Enable                                            */
-#define EMISO           0x0020  /* Enable MISO As Output                                                        */
-#define SIZE            0x0100  /* Size of Words (16/8* Bits)                                           */
-#define LSBF            0x0200  /* LSB First                                                                            */
-#define CPHA            0x0400  /* Clock Phase                                                                          */
-#define CPOL            0x0800  /* Clock Polarity                                                                       */
-#define MSTR            0x1000  /* Master/Slave*                                                                        */
-#define WOM                     0x2000  /* Write Open Drain Master                                                      */
-#define SPE                     0x4000  /* SPI Enable                                                                           */
-
-/* SPI_FLG Masks                                                                                                                                        */
-#define FLS1            0x0002  /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
-#define FLS2            0x0004  /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
-#define FLS3            0x0008  /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
-#define FLS4            0x0010  /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
-#define FLS5            0x0020  /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
-#define FLS6            0x0040  /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
-#define FLS7            0x0080  /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
-#define FLG1            0xFDFF  /* Activates SPI_FLOUT1                                                         */
-#define FLG2            0xFBFF  /* Activates SPI_FLOUT2                                                         */
-#define FLG3            0xF7FF  /* Activates SPI_FLOUT3                                                         */
-#define FLG4            0xEFFF  /* Activates SPI_FLOUT4                                                         */
-#define FLG5            0xDFFF  /* Activates SPI_FLOUT5                                                         */
-#define FLG6            0xBFFF  /* Activates SPI_FLOUT6                                                         */
-#define FLG7            0x7FFF  /* Activates SPI_FLOUT7                                                         */
-
-/* SPI_STAT Masks                                                                                                                                                               */
-#define SPIF            0x0001  /* SPI Finished (Single-Word Transfer Complete)                                 */
-#define MODF            0x0002  /* Mode Fault Error (Another Device Tried To Become Master)             */
-#define TXE                     0x0004  /* Transmission Error (Data Sent With No New Data In TDBR)              */
-#define TXS                     0x0008  /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
-#define RBSY            0x0010  /* Receive Error (Data Received With RDBR Full)                                 */
-#define RXS                     0x0020  /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
-#define TXCOL           0x0040  /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
-
-/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
-/* TIMER_ENABLE Masks                                                                                                   */
-#define TIMEN0                  0x0001  /* Enable Timer 0                                       */
-#define TIMEN1                  0x0002  /* Enable Timer 1                                       */
-#define TIMEN2                  0x0004  /* Enable Timer 2                                       */
-#define TIMEN3                  0x0008  /* Enable Timer 3                                       */
-#define TIMEN4                  0x0010  /* Enable Timer 4                                       */
-#define TIMEN5                  0x0020  /* Enable Timer 5                                       */
-#define TIMEN6                  0x0040  /* Enable Timer 6                                       */
-#define TIMEN7                  0x0080  /* Enable Timer 7                                       */
-
-/* TIMER_DISABLE Masks                                                                                                  */
-#define TIMDIS0                 TIMEN0  /* Disable Timer 0                                      */
-#define TIMDIS1                 TIMEN1  /* Disable Timer 1                                      */
-#define TIMDIS2                 TIMEN2  /* Disable Timer 2                                      */
-#define TIMDIS3                 TIMEN3  /* Disable Timer 3                                      */
-#define TIMDIS4                 TIMEN4  /* Disable Timer 4                                      */
-#define TIMDIS5                 TIMEN5  /* Disable Timer 5                                      */
-#define TIMDIS6                 TIMEN6  /* Disable Timer 6                                      */
-#define TIMDIS7                 TIMEN7  /* Disable Timer 7                                      */
-
-/* TIMER_STATUS Masks                                                                                                   */
-#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
-#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
-#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
-#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
-#define TOVF_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
-#define TOVF_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
-#define TOVF_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
-#define TOVF_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
-#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
-#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
-#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
-#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
-#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
-#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
-#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
-#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
-#define TOVF_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
-#define TOVF_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
-#define TOVF_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
-#define TOVF_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
-#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
-#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
-#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
-#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-/* TIMERx_CONFIG Masks                                                                                                  */
-#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
-#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
-#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
-#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
-#define PERIOD_CNT              0x0008  /* Period Count                                                 */
-#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
-#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
-#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
-#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
-#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
-#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
-#define ERR_TYP                 0xC000  /* Error Type                                                   */
-
-/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
-/* Port F Masks                                                                                                                 */
-#define PF0             0x0001
-#define PF1             0x0002
-#define PF2             0x0004
-#define PF3             0x0008
-#define PF4             0x0010
-#define PF5             0x0020
-#define PF6             0x0040
-#define PF7             0x0080
-#define PF8             0x0100
-#define PF9             0x0200
-#define PF10    0x0400
-#define PF11    0x0800
-#define PF12    0x1000
-#define PF13    0x2000
-#define PF14    0x4000
-#define PF15    0x8000
-
-/* Port G Masks                                                                                                                 */
-#define PG0             0x0001
-#define PG1             0x0002
-#define PG2             0x0004
-#define PG3             0x0008
-#define PG4             0x0010
-#define PG5             0x0020
-#define PG6             0x0040
-#define PG7             0x0080
-#define PG8             0x0100
-#define PG9             0x0200
-#define PG10    0x0400
-#define PG11    0x0800
-#define PG12    0x1000
-#define PG13    0x2000
-#define PG14    0x4000
-#define PG15    0x8000
-
-/* Port H Masks                                                                                                                 */
-#define PH0             0x0001
-#define PH1             0x0002
-#define PH2             0x0004
-#define PH3             0x0008
-#define PH4             0x0010
-#define PH5             0x0020
-#define PH6             0x0040
-#define PH7             0x0080
-#define PH8             0x0100
-#define PH9             0x0200
-#define PH10    0x0400
-#define PH11    0x0800
-#define PH12    0x1000
-#define PH13    0x2000
-#define PH14    0x4000
-#define PH15    0x8000
-
-/* *******************  SERIAL PORT MASKS  **************************************/
-/* SPORTx_TCR1 Masks                                                                                                                    */
-#define TSPEN           0x0001  /* Transmit Enable                                                              */
-#define ITCLK           0x0002  /* Internal Transmit Clock Select                               */
-#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
-#define TLSBIT          0x0010  /* Transmit Bit Order                                                   */
-#define ITFS            0x0200  /* Internal Transmit Frame Sync Select                  */
-#define TFSR            0x0400  /* Transmit Frame Sync Required Select                  */
-#define DITFS           0x0800  /* Data-Independent Transmit Frame Sync Select  */
-#define LTFS            0x1000  /* Low Transmit Frame Sync Select                               */
-#define LATFS           0x2000  /* Late Transmit Frame Sync Select                              */
-#define TCKFE           0x4000  /* Clock Falling Edge Select                                    */
-
-/* SPORTx_TCR2 Masks and Macro                                                                                                  */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
-#define TXSE            0x0100  /* TX Secondary Enable                                                  */
-#define TSFSE           0x0200  /* Transmit Stereo Frame Sync Enable                    */
-#define TRFST           0x0400  /* Left/Right Order (1 = Right Channel 1st)             */
-
-/* SPORTx_RCR1 Masks                                                                                                                    */
-#define RSPEN           0x0001  /* Receive Enable                                                               */
-#define IRCLK           0x0002  /* Internal Receive Clock Select                                */
-#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
-#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
-#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
-#define RLSBIT          0x0010  /* Receive Bit Order                                                    */
-#define IRFS            0x0200  /* Internal Receive Frame Sync Select                   */
-#define RFSR            0x0400  /* Receive Frame Sync Required Select                   */
-#define LRFS            0x1000  /* Low Receive Frame Sync Select                                */
-#define LARFS           0x2000  /* Late Receive Frame Sync Select                               */
-#define RCKFE           0x4000  /* Clock Falling Edge Select                                    */
-
-/* SPORTx_RCR2 Masks                                                                                                                    */
-#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
-#define RXSE            0x0100  /* RX Secondary Enable                                                  */
-#define RSFSE           0x0200  /* RX Stereo Frame Sync Enable                                  */
-#define RRFST           0x0400  /* Right-First Data Order                                               */
-
-/* SPORTx_STAT Masks                                                                                                                    */
-#define RXNE            0x0001  /* Receive FIFO Not Empty Status                                */
-#define RUVF            0x0002  /* Sticky Receive Underflow Status                              */
-#define ROVF            0x0004  /* Sticky Receive Overflow Status                               */
-#define TXF                     0x0008  /* Transmit FIFO Full Status                                    */
-#define TUVF            0x0010  /* Sticky Transmit Underflow Status                             */
-#define TOVF            0x0020  /* Sticky Transmit Overflow Status                              */
-#define TXHRE           0x0040  /* Transmit Hold Register Empty                                 */
-
-/* SPORTx_MCMC1 Macros                                                                                                                  */
-#define SP_WOFF(x)              ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
-
-/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
-#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
-
-/* SPORTx_MCMC2 Masks                                                                                                                   */
-#define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery)                              */
-#define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock                 */
-#define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock                */
-#define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing                    */
-#define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing                             */
-#define MCMEN           0x0010  /* Multichannel Frame Mode Enable                               */
-#define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
-#define MFD_0           0x0000  /* Multichannel Frame Delay = 0                                 */
-#define MFD_1           0x1000  /* Multichannel Frame Delay = 1                                 */
-#define MFD_2           0x2000  /* Multichannel Frame Delay = 2                                 */
-#define MFD_3           0x3000  /* Multichannel Frame Delay = 3                                 */
-#define MFD_4           0x4000  /* Multichannel Frame Delay = 4                                 */
-#define MFD_5           0x5000  /* Multichannel Frame Delay = 5                                 */
-#define MFD_6           0x6000  /* Multichannel Frame Delay = 6                                 */
-#define MFD_7           0x7000  /* Multichannel Frame Delay = 7                                 */
-#define MFD_8           0x8000  /* Multichannel Frame Delay = 8                                 */
-#define MFD_9           0x9000  /* Multichannel Frame Delay = 9                                 */
-#define MFD_10          0xA000  /* Multichannel Frame Delay = 10                                */
-#define MFD_11          0xB000  /* Multichannel Frame Delay = 11                                */
-#define MFD_12          0xC000  /* Multichannel Frame Delay = 12                                */
-#define MFD_13          0xD000  /* Multichannel Frame Delay = 13                                */
-#define MFD_14          0xE000  /* Multichannel Frame Delay = 14                                */
-#define MFD_15          0xF000  /* Multichannel Frame Delay = 15                                */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000  /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002  /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004  /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008  /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-/* EBIU_AMBCTL0 Masks                                                                                                                                   */
-#define B0RDYEN                 0x00000001      /* Bank 0 (B0) RDY Enable                                                   */
-#define B0RDYPOL                0x00000002      /* B0 RDY Active High                                                               */
-#define B0TT_1                  0x00000004      /* B0 Transition Time (Read to Write) = 1 cycle             */
-#define B0TT_2                  0x00000008      /* B0 Transition Time (Read to Write) = 2 cycles    */
-#define B0TT_3                  0x0000000C      /* B0 Transition Time (Read to Write) = 3 cycles    */
-#define B0TT_4                  0x00000000      /* B0 Transition Time (Read to Write) = 4 cycles    */
-#define B0ST_1                  0x00000010      /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B0ST_2                  0x00000020      /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B0ST_3                  0x00000030      /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B0ST_4                  0x00000000      /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B0HT_1                  0x00000040      /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B0HT_2                  0x00000080      /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B0HT_3                  0x000000C0      /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B0HT_0                  0x00000000      /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B0RAT_1                 0x00000100      /* B0 Read Access Time = 1 cycle                                    */
-#define B0RAT_2                 0x00000200      /* B0 Read Access Time = 2 cycles                                   */
-#define B0RAT_3                 0x00000300      /* B0 Read Access Time = 3 cycles                                   */
-#define B0RAT_4                 0x00000400      /* B0 Read Access Time = 4 cycles                                   */
-#define B0RAT_5                 0x00000500      /* B0 Read Access Time = 5 cycles                                   */
-#define B0RAT_6                 0x00000600      /* B0 Read Access Time = 6 cycles                                   */
-#define B0RAT_7                 0x00000700      /* B0 Read Access Time = 7 cycles                                   */
-#define B0RAT_8                 0x00000800      /* B0 Read Access Time = 8 cycles                                   */
-#define B0RAT_9                 0x00000900      /* B0 Read Access Time = 9 cycles                                   */
-#define B0RAT_10                0x00000A00      /* B0 Read Access Time = 10 cycles                                  */
-#define B0RAT_11                0x00000B00      /* B0 Read Access Time = 11 cycles                                  */
-#define B0RAT_12                0x00000C00      /* B0 Read Access Time = 12 cycles                                  */
-#define B0RAT_13                0x00000D00      /* B0 Read Access Time = 13 cycles                                  */
-#define B0RAT_14                0x00000E00      /* B0 Read Access Time = 14 cycles                                  */
-#define B0RAT_15                0x00000F00      /* B0 Read Access Time = 15 cycles                                  */
-#define B0WAT_1                 0x00001000      /* B0 Write Access Time = 1 cycle                                   */
-#define B0WAT_2                 0x00002000      /* B0 Write Access Time = 2 cycles                                  */
-#define B0WAT_3                 0x00003000      /* B0 Write Access Time = 3 cycles                                  */
-#define B0WAT_4                 0x00004000      /* B0 Write Access Time = 4 cycles                                  */
-#define B0WAT_5                 0x00005000      /* B0 Write Access Time = 5 cycles                                  */
-#define B0WAT_6                 0x00006000      /* B0 Write Access Time = 6 cycles                                  */
-#define B0WAT_7                 0x00007000      /* B0 Write Access Time = 7 cycles                                  */
-#define B0WAT_8                 0x00008000      /* B0 Write Access Time = 8 cycles                                  */
-#define B0WAT_9                 0x00009000      /* B0 Write Access Time = 9 cycles                                  */
-#define B0WAT_10                0x0000A000      /* B0 Write Access Time = 10 cycles                                 */
-#define B0WAT_11                0x0000B000      /* B0 Write Access Time = 11 cycles                                 */
-#define B0WAT_12                0x0000C000      /* B0 Write Access Time = 12 cycles                                 */
-#define B0WAT_13                0x0000D000      /* B0 Write Access Time = 13 cycles                                 */
-#define B0WAT_14                0x0000E000      /* B0 Write Access Time = 14 cycles                                 */
-#define B0WAT_15                0x0000F000      /* B0 Write Access Time = 15 cycles                                 */
-
-#define B1RDYEN                 0x00010000      /* Bank 1 (B1) RDY Enable                           */
-#define B1RDYPOL                0x00020000      /* B1 RDY Active High                               */
-#define B1TT_1                  0x00040000      /* B1 Transition Time (Read to Write) = 1 cycle     */
-#define B1TT_2                  0x00080000      /* B1 Transition Time (Read to Write) = 2 cycles    */
-#define B1TT_3                  0x000C0000      /* B1 Transition Time (Read to Write) = 3 cycles    */
-#define B1TT_4                  0x00000000      /* B1 Transition Time (Read to Write) = 4 cycles    */
-#define B1ST_1                  0x00100000      /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
-#define B1ST_2                  0x00200000      /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
-#define B1ST_3                  0x00300000      /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
-#define B1ST_4                  0x00000000      /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
-#define B1HT_1                  0x00400000      /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
-#define B1HT_2                  0x00800000      /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B1HT_3                  0x00C00000      /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B1HT_0                  0x00000000      /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B1RAT_1                 0x01000000      /* B1 Read Access Time = 1 cycle                                    */
-#define B1RAT_2                 0x02000000      /* B1 Read Access Time = 2 cycles                                   */
-#define B1RAT_3                 0x03000000      /* B1 Read Access Time = 3 cycles                                   */
-#define B1RAT_4                 0x04000000      /* B1 Read Access Time = 4 cycles                                   */
-#define B1RAT_5                 0x05000000      /* B1 Read Access Time = 5 cycles                                   */
-#define B1RAT_6                 0x06000000      /* B1 Read Access Time = 6 cycles                                   */
-#define B1RAT_7                 0x07000000      /* B1 Read Access Time = 7 cycles                                   */
-#define B1RAT_8                 0x08000000      /* B1 Read Access Time = 8 cycles                                   */
-#define B1RAT_9                 0x09000000      /* B1 Read Access Time = 9 cycles                                   */
-#define B1RAT_10                0x0A000000      /* B1 Read Access Time = 10 cycles                                  */
-#define B1RAT_11                0x0B000000      /* B1 Read Access Time = 11 cycles                                  */
-#define B1RAT_12                0x0C000000      /* B1 Read Access Time = 12 cycles                                  */
-#define B1RAT_13                0x0D000000      /* B1 Read Access Time = 13 cycles                                  */
-#define B1RAT_14                0x0E000000      /* B1 Read Access Time = 14 cycles                                  */
-#define B1RAT_15                0x0F000000      /* B1 Read Access Time = 15 cycles                                  */
-#define B1WAT_1                 0x10000000      /* B1 Write Access Time = 1 cycle                                   */
-#define B1WAT_2                 0x20000000      /* B1 Write Access Time = 2 cycles                                  */
-#define B1WAT_3                 0x30000000      /* B1 Write Access Time = 3 cycles                                  */
-#define B1WAT_4                 0x40000000      /* B1 Write Access Time = 4 cycles                                  */
-#define B1WAT_5                 0x50000000      /* B1 Write Access Time = 5 cycles                                  */
-#define B1WAT_6                 0x60000000      /* B1 Write Access Time = 6 cycles                                  */
-#define B1WAT_7                 0x70000000      /* B1 Write Access Time = 7 cycles                                  */
-#define B1WAT_8                 0x80000000      /* B1 Write Access Time = 8 cycles                                  */
-#define B1WAT_9                 0x90000000      /* B1 Write Access Time = 9 cycles                                  */
-#define B1WAT_10                0xA0000000      /* B1 Write Access Time = 10 cycles                                 */
-#define B1WAT_11                0xB0000000      /* B1 Write Access Time = 11 cycles                                 */
-#define B1WAT_12                0xC0000000      /* B1 Write Access Time = 12 cycles                                 */
-#define B1WAT_13                0xD0000000      /* B1 Write Access Time = 13 cycles                                 */
-#define B1WAT_14                0xE0000000      /* B1 Write Access Time = 14 cycles                                 */
-#define B1WAT_15                0xF0000000      /* B1 Write Access Time = 15 cycles                                 */
-
-/* EBIU_AMBCTL1 Masks                                                                                                                                   */
-#define B2RDYEN                 0x00000001      /* Bank 2 (B2) RDY Enable                                                   */
-#define B2RDYPOL                0x00000002      /* B2 RDY Active High                                                               */
-#define B2TT_1                  0x00000004      /* B2 Transition Time (Read to Write) = 1 cycle             */
-#define B2TT_2                  0x00000008      /* B2 Transition Time (Read to Write) = 2 cycles    */
-#define B2TT_3                  0x0000000C      /* B2 Transition Time (Read to Write) = 3 cycles    */
-#define B2TT_4                  0x00000000      /* B2 Transition Time (Read to Write) = 4 cycles    */
-#define B2ST_1                  0x00000010      /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B2ST_2                  0x00000020      /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B2ST_3                  0x00000030      /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B2ST_4                  0x00000000      /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B2HT_1                  0x00000040      /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B2HT_2                  0x00000080      /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B2HT_3                  0x000000C0      /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B2HT_0                  0x00000000      /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B2RAT_1                 0x00000100      /* B2 Read Access Time = 1 cycle                                    */
-#define B2RAT_2                 0x00000200      /* B2 Read Access Time = 2 cycles                                   */
-#define B2RAT_3                 0x00000300      /* B2 Read Access Time = 3 cycles                                   */
-#define B2RAT_4                 0x00000400      /* B2 Read Access Time = 4 cycles                                   */
-#define B2RAT_5                 0x00000500      /* B2 Read Access Time = 5 cycles                                   */
-#define B2RAT_6                 0x00000600      /* B2 Read Access Time = 6 cycles                                   */
-#define B2RAT_7                 0x00000700      /* B2 Read Access Time = 7 cycles                                   */
-#define B2RAT_8                 0x00000800      /* B2 Read Access Time = 8 cycles                                   */
-#define B2RAT_9                 0x00000900      /* B2 Read Access Time = 9 cycles                                   */
-#define B2RAT_10                0x00000A00      /* B2 Read Access Time = 10 cycles                                  */
-#define B2RAT_11                0x00000B00      /* B2 Read Access Time = 11 cycles                                  */
-#define B2RAT_12                0x00000C00      /* B2 Read Access Time = 12 cycles                                  */
-#define B2RAT_13                0x00000D00      /* B2 Read Access Time = 13 cycles                                  */
-#define B2RAT_14                0x00000E00      /* B2 Read Access Time = 14 cycles                                  */
-#define B2RAT_15                0x00000F00      /* B2 Read Access Time = 15 cycles                                  */
-#define B2WAT_1                 0x00001000      /* B2 Write Access Time = 1 cycle                                   */
-#define B2WAT_2                 0x00002000      /* B2 Write Access Time = 2 cycles                                  */
-#define B2WAT_3                 0x00003000      /* B2 Write Access Time = 3 cycles                                  */
-#define B2WAT_4                 0x00004000      /* B2 Write Access Time = 4 cycles                                  */
-#define B2WAT_5                 0x00005000      /* B2 Write Access Time = 5 cycles                                  */
-#define B2WAT_6                 0x00006000      /* B2 Write Access Time = 6 cycles                                  */
-#define B2WAT_7                 0x00007000      /* B2 Write Access Time = 7 cycles                                  */
-#define B2WAT_8                 0x00008000      /* B2 Write Access Time = 8 cycles                                  */
-#define B2WAT_9                 0x00009000      /* B2 Write Access Time = 9 cycles                                  */
-#define B2WAT_10                0x0000A000      /* B2 Write Access Time = 10 cycles                                 */
-#define B2WAT_11                0x0000B000      /* B2 Write Access Time = 11 cycles                                 */
-#define B2WAT_12                0x0000C000      /* B2 Write Access Time = 12 cycles                                 */
-#define B2WAT_13                0x0000D000      /* B2 Write Access Time = 13 cycles                                 */
-#define B2WAT_14                0x0000E000      /* B2 Write Access Time = 14 cycles                                 */
-#define B2WAT_15                0x0000F000      /* B2 Write Access Time = 15 cycles                                 */
-
-#define B3RDYEN                 0x00010000      /* Bank 3 (B3) RDY Enable                                                   */
-#define B3RDYPOL                0x00020000      /* B3 RDY Active High                                                               */
-#define B3TT_1                  0x00040000      /* B3 Transition Time (Read to Write) = 1 cycle             */
-#define B3TT_2                  0x00080000      /* B3 Transition Time (Read to Write) = 2 cycles    */
-#define B3TT_3                  0x000C0000      /* B3 Transition Time (Read to Write) = 3 cycles    */
-#define B3TT_4                  0x00000000      /* B3 Transition Time (Read to Write) = 4 cycles    */
-#define B3ST_1                  0x00100000      /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
-#define B3ST_2                  0x00200000      /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
-#define B3ST_3                  0x00300000      /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
-#define B3ST_4                  0x00000000      /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
-#define B3HT_1                  0x00400000      /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
-#define B3HT_2                  0x00800000      /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
-#define B3HT_3                  0x00C00000      /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
-#define B3HT_0                  0x00000000      /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
-#define B3RAT_1                 0x01000000      /* B3 Read Access Time = 1 cycle                                    */
-#define B3RAT_2                 0x02000000      /* B3 Read Access Time = 2 cycles                                   */
-#define B3RAT_3                 0x03000000      /* B3 Read Access Time = 3 cycles                                   */
-#define B3RAT_4                 0x04000000      /* B3 Read Access Time = 4 cycles                                   */
-#define B3RAT_5                 0x05000000      /* B3 Read Access Time = 5 cycles                                   */
-#define B3RAT_6                 0x06000000      /* B3 Read Access Time = 6 cycles                                   */
-#define B3RAT_7                 0x07000000      /* B3 Read Access Time = 7 cycles                                   */
-#define B3RAT_8                 0x08000000      /* B3 Read Access Time = 8 cycles                                   */
-#define B3RAT_9                 0x09000000      /* B3 Read Access Time = 9 cycles                                   */
-#define B3RAT_10                0x0A000000      /* B3 Read Access Time = 10 cycles                                  */
-#define B3RAT_11                0x0B000000      /* B3 Read Access Time = 11 cycles                                  */
-#define B3RAT_12                0x0C000000      /* B3 Read Access Time = 12 cycles                                  */
-#define B3RAT_13                0x0D000000      /* B3 Read Access Time = 13 cycles                                  */
-#define B3RAT_14                0x0E000000      /* B3 Read Access Time = 14 cycles                                  */
-#define B3RAT_15                0x0F000000      /* B3 Read Access Time = 15 cycles                                  */
-#define B3WAT_1                 0x10000000      /* B3 Write Access Time = 1 cycle                                   */
-#define B3WAT_2                 0x20000000      /* B3 Write Access Time = 2 cycles                                  */
-#define B3WAT_3                 0x30000000      /* B3 Write Access Time = 3 cycles                                  */
-#define B3WAT_4                 0x40000000      /* B3 Write Access Time = 4 cycles                                  */
-#define B3WAT_5                 0x50000000      /* B3 Write Access Time = 5 cycles                                  */
-#define B3WAT_6                 0x60000000      /* B3 Write Access Time = 6 cycles                                  */
-#define B3WAT_7                 0x70000000      /* B3 Write Access Time = 7 cycles                                  */
-#define B3WAT_8                 0x80000000      /* B3 Write Access Time = 8 cycles                                  */
-#define B3WAT_9                 0x90000000      /* B3 Write Access Time = 9 cycles                                  */
-#define B3WAT_10                0xA0000000      /* B3 Write Access Time = 10 cycles                                 */
-#define B3WAT_11                0xB0000000      /* B3 Write Access Time = 11 cycles                                 */
-#define B3WAT_12                0xC0000000      /* B3 Write Access Time = 12 cycles                                 */
-#define B3WAT_13                0xD0000000      /* B3 Write Access Time = 13 cycles                                 */
-#define B3WAT_14                0xE0000000      /* B3 Write Access Time = 14 cycles                                 */
-#define B3WAT_15                0xF0000000      /* B3 Write Access Time = 15 cycles                                 */
-
-/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
-/* EBIU_SDGCTL Masks                                                                                                                                                    */
-#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
-#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
-#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
-#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
-#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
-#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
-#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
-#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
-#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
-#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
-#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
-#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
-#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
-#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
-#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
-
-/* EBIU_SDBCTL Masks                                                                                                                                            */
-#define EBE                             0x0001  /* Enable SDRAM External Bank                                                   */
-#define EBSZ_16                 0x0000  /* SDRAM External Bank Size = 16MB                                              */
-#define EBSZ_32                 0x0002  /* SDRAM External Bank Size = 32MB                                              */
-#define EBSZ_64                 0x0004  /* SDRAM External Bank Size = 64MB                                              */
-#define EBSZ_128                0x0006  /* SDRAM External Bank Size = 128MB                                             */
-#define EBSZ_256                0x0008          /* SDRAM External Bank Size = 256MB     */
-#define EBSZ_512                0x000A          /* SDRAM External Bank Size = 512MB             */
-#define EBCAW_8                 0x0000  /* SDRAM External Bank Column Address Width = 8 Bits    */
-#define EBCAW_9                 0x0010  /* SDRAM External Bank Column Address Width = 9 Bits    */
-#define EBCAW_10                0x0020  /* SDRAM External Bank Column Address Width = 10 Bits   */
-#define EBCAW_11                0x0030  /* SDRAM External Bank Column Address Width = 11 Bits   */
-
-/* EBIU_SDSTAT Masks                                                                                                            */
-#define SDCI                    0x0001  /* SDRAM Controller Idle                                */
-#define SDSRA                   0x0002  /* SDRAM Self-Refresh Active                    */
-#define SDPUA                   0x0004  /* SDRAM Power-Up Active                                */
-#define SDRS                    0x0008  /* SDRAM Will Power-Up On Next Access   */
-#define SDEASE                  0x0010  /* SDRAM EAB Sticky Error Status                */
-#define BGSTAT                  0x0020  /* Bus Grant Status                                             */
-
-/* **************************  DMA CONTROLLER MASKS  ********************************/
-/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
-#define DMAEN                   0x0001  /* DMA Channel Enable                                                   */
-#define WNR                             0x0002  /* Channel Direction (W/R*)                                             */
-#define WDSIZE_8                0x0000  /* Transfer Word Size = 8                                               */
-#define WDSIZE_16               0x0004  /* Transfer Word Size = 16                                              */
-#define WDSIZE_32               0x0008  /* Transfer Word Size = 32                                              */
-#define DMA2D                   0x0010  /* DMA Mode (2D/1D*)                                                    */
-#define RESTART                 0x0020  /* DMA Buffer Clear                                                             */
-#define DI_SEL                  0x0040  /* Data Interrupt Timing Select                                 */
-#define DI_EN                   0x0080  /* Data Interrupt Enable                                                */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE                  0x0900  /* Next Descriptor Size */
-
-#define DMAFLOW                 0x7000  /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
-#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
-#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
-#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
-#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
-#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
-#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
-#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
-#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
-#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
-#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
-#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
-#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
-#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
-#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
-#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
-#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
-#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
-#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
-
-/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
-/*  PPI_CONTROL Masks                                                                                                   */
-#define PORT_EN                 0x0001  /* PPI Port Enable                                      */
-#define PORT_DIR                0x0002  /* PPI Port Direction                           */
-#define XFR_TYPE                0x000C  /* PPI Transfer Type                            */
-#define PORT_CFG                0x0030  /* PPI Port Configuration                       */
-#define FLD_SEL                 0x0040  /* PPI Active Field Select                      */
-#define PACK_EN                 0x0080  /* PPI Packing Mode                                     */
-#define DMA32                   0x0100  /* PPI 32-bit DMA Enable                        */
-#define SKIP_EN                 0x0200  /* PPI Skip Element Enable                      */
-#define SKIP_EO                 0x0400  /* PPI Skip Even/Odd Elements           */
-#define DLENGTH         0x3800  /* PPI Data Length  */
-#define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
-#define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
-#define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
-#define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
-#define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
-#define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
-#define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
-#define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
-#define POLC                    0x4000  /* PPI Clock Polarity                           */
-#define POLS                    0x8000  /* PPI Frame Sync Polarity                      */
-
-/* PPI_STATUS Masks                                                                                                             */
-#define FLD                             0x0400  /* Field Indicator                                      */
-#define FT_ERR                  0x0800  /* Frame Track Error                            */
-#define OVR                             0x1000  /* FIFO Overflow Error                          */
-#define UNDR                    0x2000  /* FIFO Underrun Error                          */
-#define ERR_DET                 0x4000  /* Error Detected Indicator                     */
-#define ERR_NCOR                0x8000  /* Error Not Corrected Indicator        */
-
-/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
-/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
-#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
-#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
-
-/* TWI_PRESCALE Masks                                                                                                                   */
-#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
-#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
-#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
-
-/* TWI_SLAVE_CTRL Masks                                                                                                                 */
-#define SEN                     0x0001  /* Slave Enable                                                                 */
-#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
-#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
-#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
-#define GEN                     0x0010  /* General Call Adrress Matching Enabled                */
-
-/* TWI_SLAVE_STAT Masks                                                                                                                 */
-#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
-#define GCALL           0x0002  /* General Call Indicator                                               */
-
-/* TWI_MASTER_CTRL Masks                                                                                                        */
-#define MEN                     0x0001  /* Master Mode Enable                                           */
-#define MADD_LEN        0x0002  /* Master Address Length                                        */
-#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
-#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
-#define STOP            0x0010  /* Issue Stop Condition                                         */
-#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
-#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
-#define SDAOVR          0x4000  /* Serial Data Override                                         */
-#define SCLOVR          0x8000  /* Serial Clock Override                                        */
-
-/* TWI_MASTER_STAT Masks                                                                                                                */
-#define MPROG           0x0001  /* Master Transfer In Progress                                  */
-#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
-#define ANAK            0x0004  /* Address Not Acknowledged                                             */
-#define DNAK            0x0008  /* Data Not Acknowledged                                                */
-#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
-#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
-#define SDASEN          0x0040  /* Serial Data Sense                                                    */
-#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
-#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
-
-/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
-#define SINIT           0x0001  /* Slave Transfer Initiated     */
-#define SCOMP           0x0002  /* Slave Transfer Complete      */
-#define SERR            0x0004  /* Slave Transfer Error         */
-#define SOVF            0x0008  /* Slave Overflow                       */
-#define MCOMP           0x0010  /* Master Transfer Complete     */
-#define MERR            0x0020  /* Master Transfer Error        */
-#define XMTSERV         0x0040  /* Transmit FIFO Service        */
-#define RCVSERV         0x0080  /* Receive FIFO Service         */
-
-/* TWI_FIFO_CTRL Masks                                                                                          */
-#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
-#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
-#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
-#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
-
-/* TWI_FIFO_STAT Masks                                                                                                                  */
-#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
-#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
-#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
-#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
-
-#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
-#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
-#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
-#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
-
-/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
-/* CAN_CONTROL Masks                                                                                            */
-#define SRS                     0x0001  /* Software Reset                                               */
-#define DNM                     0x0002  /* Device Net Mode                                              */
-#define ABO                     0x0004  /* Auto-Bus On Enable                                   */
-#define TXPRIO          0x0008  /* TX Priority (Priority/Mailbox*)              */
-#define WBA                     0x0010  /* Wake-Up On CAN Bus Activity Enable   */
-#define SMR                     0x0020  /* Sleep Mode Request                                   */
-#define CSR                     0x0040  /* CAN Suspend Mode Request                             */
-#define CCR                     0x0080  /* CAN Configuration Mode Request               */
-
-/* CAN_STATUS Masks                                                                                             */
-#define WT                      0x0001  /* TX Warning Flag                                      */
-#define WR                      0x0002  /* RX Warning Flag                                      */
-#define EP                      0x0004  /* Error Passive Mode                           */
-#define EBO                     0x0008  /* Error Bus Off Mode                           */
-#define SMA                     0x0020  /* Sleep Mode Acknowledge                       */
-#define CSA                     0x0040  /* Suspend Mode Acknowledge                     */
-#define CCA                     0x0080  /* Configuration Mode Acknowledge       */
-#define MBPTR           0x1F00  /* Mailbox Pointer                                      */
-#define TRM                     0x4000  /* Transmit Mode                                        */
-#define REC                     0x8000  /* Receive Mode                                         */
-
-/* CAN_CLOCK Masks                                                                      */
-#define BRP                     0x03FF  /* Bit-Rate Pre-Scaler  */
-
-/* CAN_TIMING Masks                                                                                     */
-#define TSEG1           0x000F  /* Time Segment 1                               */
-#define TSEG2           0x0070  /* Time Segment 2                               */
-#define SAM                     0x0080  /* Sampling                                             */
-#define SJW                     0x0300  /* Synchronization Jump Width   */
-
-/* CAN_DEBUG Masks                                                                                      */
-#define DEC                     0x0001  /* Disable CAN Error Counters   */
-#define DRI                     0x0002  /* Disable CAN RX Input                 */
-#define DTO                     0x0004  /* Disable CAN TX Output                */
-#define DIL                     0x0008  /* Disable CAN Internal Loop    */
-#define MAA                     0x0010  /* Mode Auto-Acknowledge Enable */
-#define MRB                     0x0020  /* Mode Read Back Enable                */
-#define CDE                     0x8000  /* CAN Debug Enable                             */
-
-/* CAN_CEC Masks                                                                                */
-#define RXECNT          0x00FF  /* Receive Error Counter        */
-#define TXECNT          0xFF00  /* Transmit Error Counter       */
-
-/* CAN_INTR Masks                                                                                       */
-#define MBRIRQ  0x0001  /* Mailbox Receive Interrupt    */
-#define MBRIF           MBRIRQ  /* legacy */
-#define MBTIRQ  0x0002  /* Mailbox Transmit Interrupt   */
-#define MBTIF           MBTIRQ  /* legacy */
-#define GIRQ            0x0004  /* Global Interrupt                             */
-#define SMACK           0x0008  /* Sleep Mode Acknowledge               */
-#define CANTX           0x0040  /* CAN TX Bus Value                             */
-#define CANRX           0x0080  /* CAN RX Bus Value                             */
-
-/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks                                                                          */
-#define DFC                     0xFFFF  /* Data Filtering Code (If Enabled) (ID0)               */
-#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (ID0)   */
-#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (ID1)    */
-#define BASEID          0x1FFC  /* Base Identifier                                                              */
-#define IDE                     0x2000  /* Identifier Extension                                                 */
-#define RTR                     0x4000  /* Remote Frame Transmission Request                    */
-#define AME                     0x8000  /* Acceptance Mask Enable                                               */
-
-/* CAN_MBxx_TIMESTAMP Masks                                     */
-#define TSV                     0xFFFF  /* Timestamp    */
-
-/* CAN_MBxx_LENGTH Masks                                                */
-#define DLC                     0x000F  /* Data Length Code     */
-
-/* CAN_AMxxH and CAN_AMxxL Masks                                                                                                */
-#define DFM                     0xFFFF  /* Data Field Mask (If Enabled) (CAN_AMxxL)                     */
-#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (CAN_AMxxL)     */
-#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (CAN_AMxxH)      */
-#define BASEID          0x1FFC  /* Base Identifier                                                                      */
-#define AMIDE           0x2000  /* Acceptance Mask ID Extension Enable                          */
-#define FMD                     0x4000  /* Full Mask Data Field Enable                                          */
-#define FDF                     0x8000  /* Filter On Data Field Enable                                          */
-
-/* CAN_MC1 Masks                                                                        */
-#define MC0                     0x0001  /* Enable Mailbox 0             */
-#define MC1                     0x0002  /* Enable Mailbox 1             */
-#define MC2                     0x0004  /* Enable Mailbox 2             */
-#define MC3                     0x0008  /* Enable Mailbox 3             */
-#define MC4                     0x0010  /* Enable Mailbox 4             */
-#define MC5                     0x0020  /* Enable Mailbox 5             */
-#define MC6                     0x0040  /* Enable Mailbox 6             */
-#define MC7                     0x0080  /* Enable Mailbox 7             */
-#define MC8                     0x0100  /* Enable Mailbox 8             */
-#define MC9                     0x0200  /* Enable Mailbox 9             */
-#define MC10            0x0400  /* Enable Mailbox 10    */
-#define MC11            0x0800  /* Enable Mailbox 11    */
-#define MC12            0x1000  /* Enable Mailbox 12    */
-#define MC13            0x2000  /* Enable Mailbox 13    */
-#define MC14            0x4000  /* Enable Mailbox 14    */
-#define MC15            0x8000  /* Enable Mailbox 15    */
-
-/* CAN_MC2 Masks                                                                        */
-#define MC16            0x0001  /* Enable Mailbox 16    */
-#define MC17            0x0002  /* Enable Mailbox 17    */
-#define MC18            0x0004  /* Enable Mailbox 18    */
-#define MC19            0x0008  /* Enable Mailbox 19    */
-#define MC20            0x0010  /* Enable Mailbox 20    */
-#define MC21            0x0020  /* Enable Mailbox 21    */
-#define MC22            0x0040  /* Enable Mailbox 22    */
-#define MC23            0x0080  /* Enable Mailbox 23    */
-#define MC24            0x0100  /* Enable Mailbox 24    */
-#define MC25            0x0200  /* Enable Mailbox 25    */
-#define MC26            0x0400  /* Enable Mailbox 26    */
-#define MC27            0x0800  /* Enable Mailbox 27    */
-#define MC28            0x1000  /* Enable Mailbox 28    */
-#define MC29            0x2000  /* Enable Mailbox 29    */
-#define MC30            0x4000  /* Enable Mailbox 30    */
-#define MC31            0x8000  /* Enable Mailbox 31    */
-
-/* CAN_MD1 Masks                                                                                                */
-#define MD0                     0x0001  /* Enable Mailbox 0 For Receive         */
-#define MD1                     0x0002  /* Enable Mailbox 1 For Receive         */
-#define MD2                     0x0004  /* Enable Mailbox 2 For Receive         */
-#define MD3                     0x0008  /* Enable Mailbox 3 For Receive         */
-#define MD4                     0x0010  /* Enable Mailbox 4 For Receive         */
-#define MD5                     0x0020  /* Enable Mailbox 5 For Receive         */
-#define MD6                     0x0040  /* Enable Mailbox 6 For Receive         */
-#define MD7                     0x0080  /* Enable Mailbox 7 For Receive         */
-#define MD8                     0x0100  /* Enable Mailbox 8 For Receive         */
-#define MD9                     0x0200  /* Enable Mailbox 9 For Receive         */
-#define MD10            0x0400  /* Enable Mailbox 10 For Receive        */
-#define MD11            0x0800  /* Enable Mailbox 11 For Receive        */
-#define MD12            0x1000  /* Enable Mailbox 12 For Receive        */
-#define MD13            0x2000  /* Enable Mailbox 13 For Receive        */
-#define MD14            0x4000  /* Enable Mailbox 14 For Receive        */
-#define MD15            0x8000  /* Enable Mailbox 15 For Receive        */
-
-/* CAN_MD2 Masks                                                                                                */
-#define MD16            0x0001  /* Enable Mailbox 16 For Receive        */
-#define MD17            0x0002  /* Enable Mailbox 17 For Receive        */
-#define MD18            0x0004  /* Enable Mailbox 18 For Receive        */
-#define MD19            0x0008  /* Enable Mailbox 19 For Receive        */
-#define MD20            0x0010  /* Enable Mailbox 20 For Receive        */
-#define MD21            0x0020  /* Enable Mailbox 21 For Receive        */
-#define MD22            0x0040  /* Enable Mailbox 22 For Receive        */
-#define MD23            0x0080  /* Enable Mailbox 23 For Receive        */
-#define MD24            0x0100  /* Enable Mailbox 24 For Receive        */
-#define MD25            0x0200  /* Enable Mailbox 25 For Receive        */
-#define MD26            0x0400  /* Enable Mailbox 26 For Receive        */
-#define MD27            0x0800  /* Enable Mailbox 27 For Receive        */
-#define MD28            0x1000  /* Enable Mailbox 28 For Receive        */
-#define MD29            0x2000  /* Enable Mailbox 29 For Receive        */
-#define MD30            0x4000  /* Enable Mailbox 30 For Receive        */
-#define MD31            0x8000  /* Enable Mailbox 31 For Receive        */
-
-/* CAN_RMP1 Masks                                                                                               */
-#define RMP0            0x0001  /* RX Message Pending In Mailbox 0      */
-#define RMP1            0x0002  /* RX Message Pending In Mailbox 1      */
-#define RMP2            0x0004  /* RX Message Pending In Mailbox 2      */
-#define RMP3            0x0008  /* RX Message Pending In Mailbox 3      */
-#define RMP4            0x0010  /* RX Message Pending In Mailbox 4      */
-#define RMP5            0x0020  /* RX Message Pending In Mailbox 5      */
-#define RMP6            0x0040  /* RX Message Pending In Mailbox 6      */
-#define RMP7            0x0080  /* RX Message Pending In Mailbox 7      */
-#define RMP8            0x0100  /* RX Message Pending In Mailbox 8      */
-#define RMP9            0x0200  /* RX Message Pending In Mailbox 9      */
-#define RMP10           0x0400  /* RX Message Pending In Mailbox 10     */
-#define RMP11           0x0800  /* RX Message Pending In Mailbox 11     */
-#define RMP12           0x1000  /* RX Message Pending In Mailbox 12     */
-#define RMP13           0x2000  /* RX Message Pending In Mailbox 13     */
-#define RMP14           0x4000  /* RX Message Pending In Mailbox 14     */
-#define RMP15           0x8000  /* RX Message Pending In Mailbox 15     */
-
-/* CAN_RMP2 Masks                                                                                               */
-#define RMP16           0x0001  /* RX Message Pending In Mailbox 16     */
-#define RMP17           0x0002  /* RX Message Pending In Mailbox 17     */
-#define RMP18           0x0004  /* RX Message Pending In Mailbox 18     */
-#define RMP19           0x0008  /* RX Message Pending In Mailbox 19     */
-#define RMP20           0x0010  /* RX Message Pending In Mailbox 20     */
-#define RMP21           0x0020  /* RX Message Pending In Mailbox 21     */
-#define RMP22           0x0040  /* RX Message Pending In Mailbox 22     */
-#define RMP23           0x0080  /* RX Message Pending In Mailbox 23     */
-#define RMP24           0x0100  /* RX Message Pending In Mailbox 24     */
-#define RMP25           0x0200  /* RX Message Pending In Mailbox 25     */
-#define RMP26           0x0400  /* RX Message Pending In Mailbox 26     */
-#define RMP27           0x0800  /* RX Message Pending In Mailbox 27     */
-#define RMP28           0x1000  /* RX Message Pending In Mailbox 28     */
-#define RMP29           0x2000  /* RX Message Pending In Mailbox 29     */
-#define RMP30           0x4000  /* RX Message Pending In Mailbox 30     */
-#define RMP31           0x8000  /* RX Message Pending In Mailbox 31     */
-
-/* CAN_RML1 Masks                                                                                               */
-#define RML0            0x0001  /* RX Message Lost In Mailbox 0         */
-#define RML1            0x0002  /* RX Message Lost In Mailbox 1         */
-#define RML2            0x0004  /* RX Message Lost In Mailbox 2         */
-#define RML3            0x0008  /* RX Message Lost In Mailbox 3         */
-#define RML4            0x0010  /* RX Message Lost In Mailbox 4         */
-#define RML5            0x0020  /* RX Message Lost In Mailbox 5         */
-#define RML6            0x0040  /* RX Message Lost In Mailbox 6         */
-#define RML7            0x0080  /* RX Message Lost In Mailbox 7         */
-#define RML8            0x0100  /* RX Message Lost In Mailbox 8         */
-#define RML9            0x0200  /* RX Message Lost In Mailbox 9         */
-#define RML10           0x0400  /* RX Message Lost In Mailbox 10        */
-#define RML11           0x0800  /* RX Message Lost In Mailbox 11        */
-#define RML12           0x1000  /* RX Message Lost In Mailbox 12        */
-#define RML13           0x2000  /* RX Message Lost In Mailbox 13        */
-#define RML14           0x4000  /* RX Message Lost In Mailbox 14        */
-#define RML15           0x8000  /* RX Message Lost In Mailbox 15        */
-
-/* CAN_RML2 Masks                                                                                               */
-#define RML16           0x0001  /* RX Message Lost In Mailbox 16        */
-#define RML17           0x0002  /* RX Message Lost In Mailbox 17        */
-#define RML18           0x0004  /* RX Message Lost In Mailbox 18        */
-#define RML19           0x0008  /* RX Message Lost In Mailbox 19        */
-#define RML20           0x0010  /* RX Message Lost In Mailbox 20        */
-#define RML21           0x0020  /* RX Message Lost In Mailbox 21        */
-#define RML22           0x0040  /* RX Message Lost In Mailbox 22        */
-#define RML23           0x0080  /* RX Message Lost In Mailbox 23        */
-#define RML24           0x0100  /* RX Message Lost In Mailbox 24        */
-#define RML25           0x0200  /* RX Message Lost In Mailbox 25        */
-#define RML26           0x0400  /* RX Message Lost In Mailbox 26        */
-#define RML27           0x0800  /* RX Message Lost In Mailbox 27        */
-#define RML28           0x1000  /* RX Message Lost In Mailbox 28        */
-#define RML29           0x2000  /* RX Message Lost In Mailbox 29        */
-#define RML30           0x4000  /* RX Message Lost In Mailbox 30        */
-#define RML31           0x8000  /* RX Message Lost In Mailbox 31        */
-
-/* CAN_OPSS1 Masks                                                                                                                                                              */
-#define OPSS0           0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0       */
-#define OPSS1           0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1       */
-#define OPSS2           0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2       */
-#define OPSS3           0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3       */
-#define OPSS4           0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4       */
-#define OPSS5           0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5       */
-#define OPSS6           0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6       */
-#define OPSS7           0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7       */
-#define OPSS8           0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8       */
-#define OPSS9           0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9       */
-#define OPSS10          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10      */
-#define OPSS11          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11      */
-#define OPSS12          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12      */
-#define OPSS13          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13      */
-#define OPSS14          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14      */
-#define OPSS15          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15      */
-
-/* CAN_OPSS2 Masks                                                                                                                                                              */
-#define OPSS16          0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16      */
-#define OPSS17          0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17      */
-#define OPSS18          0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18      */
-#define OPSS19          0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19      */
-#define OPSS20          0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20      */
-#define OPSS21          0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21      */
-#define OPSS22          0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22      */
-#define OPSS23          0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23      */
-#define OPSS24          0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24      */
-#define OPSS25          0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25      */
-#define OPSS26          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26      */
-#define OPSS27          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27      */
-#define OPSS28          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28      */
-#define OPSS29          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29      */
-#define OPSS30          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30      */
-#define OPSS31          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31      */
-
-/* CAN_TRR1 Masks                                                                                                               */
-#define TRR0            0x0001  /* Deny But Don't Lock Access To Mailbox 0      */
-#define TRR1            0x0002  /* Deny But Don't Lock Access To Mailbox 1      */
-#define TRR2            0x0004  /* Deny But Don't Lock Access To Mailbox 2      */
-#define TRR3            0x0008  /* Deny But Don't Lock Access To Mailbox 3      */
-#define TRR4            0x0010  /* Deny But Don't Lock Access To Mailbox 4      */
-#define TRR5            0x0020  /* Deny But Don't Lock Access To Mailbox 5      */
-#define TRR6            0x0040  /* Deny But Don't Lock Access To Mailbox 6      */
-#define TRR7            0x0080  /* Deny But Don't Lock Access To Mailbox 7      */
-#define TRR8            0x0100  /* Deny But Don't Lock Access To Mailbox 8      */
-#define TRR9            0x0200  /* Deny But Don't Lock Access To Mailbox 9      */
-#define TRR10           0x0400  /* Deny But Don't Lock Access To Mailbox 10     */
-#define TRR11           0x0800  /* Deny But Don't Lock Access To Mailbox 11     */
-#define TRR12           0x1000  /* Deny But Don't Lock Access To Mailbox 12     */
-#define TRR13           0x2000  /* Deny But Don't Lock Access To Mailbox 13     */
-#define TRR14           0x4000  /* Deny But Don't Lock Access To Mailbox 14     */
-#define TRR15           0x8000  /* Deny But Don't Lock Access To Mailbox 15     */
-
-/* CAN_TRR2 Masks                                                                                                               */
-#define TRR16           0x0001  /* Deny But Don't Lock Access To Mailbox 16     */
-#define TRR17           0x0002  /* Deny But Don't Lock Access To Mailbox 17     */
-#define TRR18           0x0004  /* Deny But Don't Lock Access To Mailbox 18     */
-#define TRR19           0x0008  /* Deny But Don't Lock Access To Mailbox 19     */
-#define TRR20           0x0010  /* Deny But Don't Lock Access To Mailbox 20     */
-#define TRR21           0x0020  /* Deny But Don't Lock Access To Mailbox 21     */
-#define TRR22           0x0040  /* Deny But Don't Lock Access To Mailbox 22     */
-#define TRR23           0x0080  /* Deny But Don't Lock Access To Mailbox 23     */
-#define TRR24           0x0100  /* Deny But Don't Lock Access To Mailbox 24     */
-#define TRR25           0x0200  /* Deny But Don't Lock Access To Mailbox 25     */
-#define TRR26           0x0400  /* Deny But Don't Lock Access To Mailbox 26     */
-#define TRR27           0x0800  /* Deny But Don't Lock Access To Mailbox 27     */
-#define TRR28           0x1000  /* Deny But Don't Lock Access To Mailbox 28     */
-#define TRR29           0x2000  /* Deny But Don't Lock Access To Mailbox 29     */
-#define TRR30           0x4000  /* Deny But Don't Lock Access To Mailbox 30     */
-#define TRR31           0x8000  /* Deny But Don't Lock Access To Mailbox 31     */
-
-/* CAN_TRS1 Masks                                                                                                       */
-#define TRS0            0x0001  /* Remote Frame Request For Mailbox 0   */
-#define TRS1            0x0002  /* Remote Frame Request For Mailbox 1   */
-#define TRS2            0x0004  /* Remote Frame Request For Mailbox 2   */
-#define TRS3            0x0008  /* Remote Frame Request For Mailbox 3   */
-#define TRS4            0x0010  /* Remote Frame Request For Mailbox 4   */
-#define TRS5            0x0020  /* Remote Frame Request For Mailbox 5   */
-#define TRS6            0x0040  /* Remote Frame Request For Mailbox 6   */
-#define TRS7            0x0080  /* Remote Frame Request For Mailbox 7   */
-#define TRS8            0x0100  /* Remote Frame Request For Mailbox 8   */
-#define TRS9            0x0200  /* Remote Frame Request For Mailbox 9   */
-#define TRS10           0x0400  /* Remote Frame Request For Mailbox 10  */
-#define TRS11           0x0800  /* Remote Frame Request For Mailbox 11  */
-#define TRS12           0x1000  /* Remote Frame Request For Mailbox 12  */
-#define TRS13           0x2000  /* Remote Frame Request For Mailbox 13  */
-#define TRS14           0x4000  /* Remote Frame Request For Mailbox 14  */
-#define TRS15           0x8000  /* Remote Frame Request For Mailbox 15  */
-
-/* CAN_TRS2 Masks                                                                                                       */
-#define TRS16           0x0001  /* Remote Frame Request For Mailbox 16  */
-#define TRS17           0x0002  /* Remote Frame Request For Mailbox 17  */
-#define TRS18           0x0004  /* Remote Frame Request For Mailbox 18  */
-#define TRS19           0x0008  /* Remote Frame Request For Mailbox 19  */
-#define TRS20           0x0010  /* Remote Frame Request For Mailbox 20  */
-#define TRS21           0x0020  /* Remote Frame Request For Mailbox 21  */
-#define TRS22           0x0040  /* Remote Frame Request For Mailbox 22  */
-#define TRS23           0x0080  /* Remote Frame Request For Mailbox 23  */
-#define TRS24           0x0100  /* Remote Frame Request For Mailbox 24  */
-#define TRS25           0x0200  /* Remote Frame Request For Mailbox 25  */
-#define TRS26           0x0400  /* Remote Frame Request For Mailbox 26  */
-#define TRS27           0x0800  /* Remote Frame Request For Mailbox 27  */
-#define TRS28           0x1000  /* Remote Frame Request For Mailbox 28  */
-#define TRS29           0x2000  /* Remote Frame Request For Mailbox 29  */
-#define TRS30           0x4000  /* Remote Frame Request For Mailbox 30  */
-#define TRS31           0x8000  /* Remote Frame Request For Mailbox 31  */
-
-/* CAN_AA1 Masks                                                                                                */
-#define AA0                     0x0001  /* Aborted Message In Mailbox 0         */
-#define AA1                     0x0002  /* Aborted Message In Mailbox 1         */
-#define AA2                     0x0004  /* Aborted Message In Mailbox 2         */
-#define AA3                     0x0008  /* Aborted Message In Mailbox 3         */
-#define AA4                     0x0010  /* Aborted Message In Mailbox 4         */
-#define AA5                     0x0020  /* Aborted Message In Mailbox 5         */
-#define AA6                     0x0040  /* Aborted Message In Mailbox 6         */
-#define AA7                     0x0080  /* Aborted Message In Mailbox 7         */
-#define AA8                     0x0100  /* Aborted Message In Mailbox 8         */
-#define AA9                     0x0200  /* Aborted Message In Mailbox 9         */
-#define AA10            0x0400  /* Aborted Message In Mailbox 10        */
-#define AA11            0x0800  /* Aborted Message In Mailbox 11        */
-#define AA12            0x1000  /* Aborted Message In Mailbox 12        */
-#define AA13            0x2000  /* Aborted Message In Mailbox 13        */
-#define AA14            0x4000  /* Aborted Message In Mailbox 14        */
-#define AA15            0x8000  /* Aborted Message In Mailbox 15        */
-
-/* CAN_AA2 Masks                                                                                                */
-#define AA16            0x0001  /* Aborted Message In Mailbox 16        */
-#define AA17            0x0002  /* Aborted Message In Mailbox 17        */
-#define AA18            0x0004  /* Aborted Message In Mailbox 18        */
-#define AA19            0x0008  /* Aborted Message In Mailbox 19        */
-#define AA20            0x0010  /* Aborted Message In Mailbox 20        */
-#define AA21            0x0020  /* Aborted Message In Mailbox 21        */
-#define AA22            0x0040  /* Aborted Message In Mailbox 22        */
-#define AA23            0x0080  /* Aborted Message In Mailbox 23        */
-#define AA24            0x0100  /* Aborted Message In Mailbox 24        */
-#define AA25            0x0200  /* Aborted Message In Mailbox 25        */
-#define AA26            0x0400  /* Aborted Message In Mailbox 26        */
-#define AA27            0x0800  /* Aborted Message In Mailbox 27        */
-#define AA28            0x1000  /* Aborted Message In Mailbox 28        */
-#define AA29            0x2000  /* Aborted Message In Mailbox 29        */
-#define AA30            0x4000  /* Aborted Message In Mailbox 30        */
-#define AA31            0x8000  /* Aborted Message In Mailbox 31        */
-
-/* CAN_TA1 Masks                                                                                                        */
-#define TA0                     0x0001  /* Transmit Successful From Mailbox 0   */
-#define TA1                     0x0002  /* Transmit Successful From Mailbox 1   */
-#define TA2                     0x0004  /* Transmit Successful From Mailbox 2   */
-#define TA3                     0x0008  /* Transmit Successful From Mailbox 3   */
-#define TA4                     0x0010  /* Transmit Successful From Mailbox 4   */
-#define TA5                     0x0020  /* Transmit Successful From Mailbox 5   */
-#define TA6                     0x0040  /* Transmit Successful From Mailbox 6   */
-#define TA7                     0x0080  /* Transmit Successful From Mailbox 7   */
-#define TA8                     0x0100  /* Transmit Successful From Mailbox 8   */
-#define TA9                     0x0200  /* Transmit Successful From Mailbox 9   */
-#define TA10            0x0400  /* Transmit Successful From Mailbox 10  */
-#define TA11            0x0800  /* Transmit Successful From Mailbox 11  */
-#define TA12            0x1000  /* Transmit Successful From Mailbox 12  */
-#define TA13            0x2000  /* Transmit Successful From Mailbox 13  */
-#define TA14            0x4000  /* Transmit Successful From Mailbox 14  */
-#define TA15            0x8000  /* Transmit Successful From Mailbox 15  */
-
-/* CAN_TA2 Masks                                                                                                        */
-#define TA16            0x0001  /* Transmit Successful From Mailbox 16  */
-#define TA17            0x0002  /* Transmit Successful From Mailbox 17  */
-#define TA18            0x0004  /* Transmit Successful From Mailbox 18  */
-#define TA19            0x0008  /* Transmit Successful From Mailbox 19  */
-#define TA20            0x0010  /* Transmit Successful From Mailbox 20  */
-#define TA21            0x0020  /* Transmit Successful From Mailbox 21  */
-#define TA22            0x0040  /* Transmit Successful From Mailbox 22  */
-#define TA23            0x0080  /* Transmit Successful From Mailbox 23  */
-#define TA24            0x0100  /* Transmit Successful From Mailbox 24  */
-#define TA25            0x0200  /* Transmit Successful From Mailbox 25  */
-#define TA26            0x0400  /* Transmit Successful From Mailbox 26  */
-#define TA27            0x0800  /* Transmit Successful From Mailbox 27  */
-#define TA28            0x1000  /* Transmit Successful From Mailbox 28  */
-#define TA29            0x2000  /* Transmit Successful From Mailbox 29  */
-#define TA30            0x4000  /* Transmit Successful From Mailbox 30  */
-#define TA31            0x8000  /* Transmit Successful From Mailbox 31  */
-
-/* CAN_MBTD Masks                                                                                               */
-#define TDPTR           0x001F  /* Mailbox To Temporarily Disable       */
-#define TDA                     0x0040  /* Temporary Disable Acknowledge        */
-#define TDR                     0x0080  /* Temporary Disable Request            */
-
-/* CAN_RFH1 Masks                                                                                                                                               */
-#define RFH0            0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 0         */
-#define RFH1            0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 1         */
-#define RFH2            0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 2         */
-#define RFH3            0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 3         */
-#define RFH4            0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 4         */
-#define RFH5            0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 5         */
-#define RFH6            0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 6         */
-#define RFH7            0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 7         */
-#define RFH8            0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 8         */
-#define RFH9            0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 9         */
-#define RFH10           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 10        */
-#define RFH11           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 11        */
-#define RFH12           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 12        */
-#define RFH13           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 13        */
-#define RFH14           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 14        */
-#define RFH15           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 15        */
-
-/* CAN_RFH2 Masks                                                                                                                                               */
-#define RFH16           0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 16        */
-#define RFH17           0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 17        */
-#define RFH18           0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 18        */
-#define RFH19           0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 19        */
-#define RFH20           0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 20        */
-#define RFH21           0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 21        */
-#define RFH22           0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 22        */
-#define RFH23           0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 23        */
-#define RFH24           0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 24        */
-#define RFH25           0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 25        */
-#define RFH26           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 26        */
-#define RFH27           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 27        */
-#define RFH28           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 28        */
-#define RFH29           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 29        */
-#define RFH30           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 30        */
-#define RFH31           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 31        */
-
-/* CAN_MBTIF1 Masks                                                                                                     */
-#define MBTIF0          0x0001  /* TX Interrupt Active In Mailbox 0             */
-#define MBTIF1          0x0002  /* TX Interrupt Active In Mailbox 1             */
-#define MBTIF2          0x0004  /* TX Interrupt Active In Mailbox 2             */
-#define MBTIF3          0x0008  /* TX Interrupt Active In Mailbox 3             */
-#define MBTIF4          0x0010  /* TX Interrupt Active In Mailbox 4             */
-#define MBTIF5          0x0020  /* TX Interrupt Active In Mailbox 5             */
-#define MBTIF6          0x0040  /* TX Interrupt Active In Mailbox 6             */
-#define MBTIF7          0x0080  /* TX Interrupt Active In Mailbox 7             */
-#define MBTIF8          0x0100  /* TX Interrupt Active In Mailbox 8             */
-#define MBTIF9          0x0200  /* TX Interrupt Active In Mailbox 9             */
-#define MBTIF10         0x0400  /* TX Interrupt Active In Mailbox 10    */
-#define MBTIF11         0x0800  /* TX Interrupt Active In Mailbox 11    */
-#define MBTIF12         0x1000  /* TX Interrupt Active In Mailbox 12    */
-#define MBTIF13         0x2000  /* TX Interrupt Active In Mailbox 13    */
-#define MBTIF14         0x4000  /* TX Interrupt Active In Mailbox 14    */
-#define MBTIF15         0x8000  /* TX Interrupt Active In Mailbox 15    */
-
-/* CAN_MBTIF2 Masks                                                                                                     */
-#define MBTIF16         0x0001  /* TX Interrupt Active In Mailbox 16    */
-#define MBTIF17         0x0002  /* TX Interrupt Active In Mailbox 17    */
-#define MBTIF18         0x0004  /* TX Interrupt Active In Mailbox 18    */
-#define MBTIF19         0x0008  /* TX Interrupt Active In Mailbox 19    */
-#define MBTIF20         0x0010  /* TX Interrupt Active In Mailbox 20    */
-#define MBTIF21         0x0020  /* TX Interrupt Active In Mailbox 21    */
-#define MBTIF22         0x0040  /* TX Interrupt Active In Mailbox 22    */
-#define MBTIF23         0x0080  /* TX Interrupt Active In Mailbox 23    */
-#define MBTIF24         0x0100  /* TX Interrupt Active In Mailbox 24    */
-#define MBTIF25         0x0200  /* TX Interrupt Active In Mailbox 25    */
-#define MBTIF26         0x0400  /* TX Interrupt Active In Mailbox 26    */
-#define MBTIF27         0x0800  /* TX Interrupt Active In Mailbox 27    */
-#define MBTIF28         0x1000  /* TX Interrupt Active In Mailbox 28    */
-#define MBTIF29         0x2000  /* TX Interrupt Active In Mailbox 29    */
-#define MBTIF30         0x4000  /* TX Interrupt Active In Mailbox 30    */
-#define MBTIF31         0x8000  /* TX Interrupt Active In Mailbox 31    */
-
-/* CAN_MBRIF1 Masks                                                                                                     */
-#define MBRIF0          0x0001  /* RX Interrupt Active In Mailbox 0             */
-#define MBRIF1          0x0002  /* RX Interrupt Active In Mailbox 1             */
-#define MBRIF2          0x0004  /* RX Interrupt Active In Mailbox 2             */
-#define MBRIF3          0x0008  /* RX Interrupt Active In Mailbox 3             */
-#define MBRIF4          0x0010  /* RX Interrupt Active In Mailbox 4             */
-#define MBRIF5          0x0020  /* RX Interrupt Active In Mailbox 5             */
-#define MBRIF6          0x0040  /* RX Interrupt Active In Mailbox 6             */
-#define MBRIF7          0x0080  /* RX Interrupt Active In Mailbox 7             */
-#define MBRIF8          0x0100  /* RX Interrupt Active In Mailbox 8             */
-#define MBRIF9          0x0200  /* RX Interrupt Active In Mailbox 9             */
-#define MBRIF10         0x0400  /* RX Interrupt Active In Mailbox 10    */
-#define MBRIF11         0x0800  /* RX Interrupt Active In Mailbox 11    */
-#define MBRIF12         0x1000  /* RX Interrupt Active In Mailbox 12    */
-#define MBRIF13         0x2000  /* RX Interrupt Active In Mailbox 13    */
-#define MBRIF14         0x4000  /* RX Interrupt Active In Mailbox 14    */
-#define MBRIF15         0x8000  /* RX Interrupt Active In Mailbox 15    */
-
-/* CAN_MBRIF2 Masks                                                                                                     */
-#define MBRIF16         0x0001  /* RX Interrupt Active In Mailbox 16    */
-#define MBRIF17         0x0002  /* RX Interrupt Active In Mailbox 17    */
-#define MBRIF18         0x0004  /* RX Interrupt Active In Mailbox 18    */
-#define MBRIF19         0x0008  /* RX Interrupt Active In Mailbox 19    */
-#define MBRIF20         0x0010  /* RX Interrupt Active In Mailbox 20    */
-#define MBRIF21         0x0020  /* RX Interrupt Active In Mailbox 21    */
-#define MBRIF22         0x0040  /* RX Interrupt Active In Mailbox 22    */
-#define MBRIF23         0x0080  /* RX Interrupt Active In Mailbox 23    */
-#define MBRIF24         0x0100  /* RX Interrupt Active In Mailbox 24    */
-#define MBRIF25         0x0200  /* RX Interrupt Active In Mailbox 25    */
-#define MBRIF26         0x0400  /* RX Interrupt Active In Mailbox 26    */
-#define MBRIF27         0x0800  /* RX Interrupt Active In Mailbox 27    */
-#define MBRIF28         0x1000  /* RX Interrupt Active In Mailbox 28    */
-#define MBRIF29         0x2000  /* RX Interrupt Active In Mailbox 29    */
-#define MBRIF30         0x4000  /* RX Interrupt Active In Mailbox 30    */
-#define MBRIF31         0x8000  /* RX Interrupt Active In Mailbox 31    */
-
-/* CAN_MBIM1 Masks                                                                                              */
-#define MBIM0           0x0001  /* Enable Interrupt For Mailbox 0       */
-#define MBIM1           0x0002  /* Enable Interrupt For Mailbox 1       */
-#define MBIM2           0x0004  /* Enable Interrupt For Mailbox 2       */
-#define MBIM3           0x0008  /* Enable Interrupt For Mailbox 3       */
-#define MBIM4           0x0010  /* Enable Interrupt For Mailbox 4       */
-#define MBIM5           0x0020  /* Enable Interrupt For Mailbox 5       */
-#define MBIM6           0x0040  /* Enable Interrupt For Mailbox 6       */
-#define MBIM7           0x0080  /* Enable Interrupt For Mailbox 7       */
-#define MBIM8           0x0100  /* Enable Interrupt For Mailbox 8       */
-#define MBIM9           0x0200  /* Enable Interrupt For Mailbox 9       */
-#define MBIM10          0x0400  /* Enable Interrupt For Mailbox 10      */
-#define MBIM11          0x0800  /* Enable Interrupt For Mailbox 11      */
-#define MBIM12          0x1000  /* Enable Interrupt For Mailbox 12      */
-#define MBIM13          0x2000  /* Enable Interrupt For Mailbox 13      */
-#define MBIM14          0x4000  /* Enable Interrupt For Mailbox 14      */
-#define MBIM15          0x8000  /* Enable Interrupt For Mailbox 15      */
-
-/* CAN_MBIM2 Masks                                                                                              */
-#define MBIM16          0x0001  /* Enable Interrupt For Mailbox 16      */
-#define MBIM17          0x0002  /* Enable Interrupt For Mailbox 17      */
-#define MBIM18          0x0004  /* Enable Interrupt For Mailbox 18      */
-#define MBIM19          0x0008  /* Enable Interrupt For Mailbox 19      */
-#define MBIM20          0x0010  /* Enable Interrupt For Mailbox 20      */
-#define MBIM21          0x0020  /* Enable Interrupt For Mailbox 21      */
-#define MBIM22          0x0040  /* Enable Interrupt For Mailbox 22      */
-#define MBIM23          0x0080  /* Enable Interrupt For Mailbox 23      */
-#define MBIM24          0x0100  /* Enable Interrupt For Mailbox 24      */
-#define MBIM25          0x0200  /* Enable Interrupt For Mailbox 25      */
-#define MBIM26          0x0400  /* Enable Interrupt For Mailbox 26      */
-#define MBIM27          0x0800  /* Enable Interrupt For Mailbox 27      */
-#define MBIM28          0x1000  /* Enable Interrupt For Mailbox 28      */
-#define MBIM29          0x2000  /* Enable Interrupt For Mailbox 29      */
-#define MBIM30          0x4000  /* Enable Interrupt For Mailbox 30      */
-#define MBIM31          0x8000  /* Enable Interrupt For Mailbox 31      */
-
-/* CAN_GIM Masks                                                                                                                                */
-#define EWTIM           0x0001  /* Enable TX Error Count Interrupt                                      */
-#define EWRIM           0x0002  /* Enable RX Error Count Interrupt                                      */
-#define EPIM            0x0004  /* Enable Error-Passive Mode Interrupt                          */
-#define BOIM            0x0008  /* Enable Bus Off Interrupt                                                     */
-#define WUIM            0x0010  /* Enable Wake-Up Interrupt                                                     */
-#define UIAIM           0x0020  /* Enable Access To Unimplemented Address Interrupt     */
-#define AAIM            0x0040  /* Enable Abort Acknowledge Interrupt                           */
-#define RMLIM           0x0080  /* Enable RX Message Lost Interrupt                                     */
-#define UCEIM           0x0100  /* Enable Universal Counter Overflow Interrupt          */
-#define EXTIM           0x0200  /* Enable External Trigger Output Interrupt                     */
-#define ADIM            0x0400  /* Enable Access Denied Interrupt                                       */
-
-/* CAN_GIS Masks                                                                                                                        */
-#define EWTIS           0x0001  /* TX Error Count IRQ Status                                    */
-#define EWRIS           0x0002  /* RX Error Count IRQ Status                                    */
-#define EPIS            0x0004  /* Error-Passive Mode IRQ Status                                */
-#define BOIS            0x0008  /* Bus Off IRQ Status                                                   */
-#define WUIS            0x0010  /* Wake-Up IRQ Status                                                   */
-#define UIAIS           0x0020  /* Access To Unimplemented Address IRQ Status   */
-#define AAIS            0x0040  /* Abort Acknowledge IRQ Status                                 */
-#define RMLIS           0x0080  /* RX Message Lost IRQ Status                                   */
-#define UCEIS           0x0100  /* Universal Counter Overflow IRQ Status                */
-#define EXTIS           0x0200  /* External Trigger Output IRQ Status                   */
-#define ADIS            0x0400  /* Access Denied IRQ Status                                             */
-
-/* CAN_GIF Masks                                                                                                                        */
-#define EWTIF           0x0001  /* TX Error Count IRQ Flag                                              */
-#define EWRIF           0x0002  /* RX Error Count IRQ Flag                                              */
-#define EPIF            0x0004  /* Error-Passive Mode IRQ Flag                                  */
-#define BOIF            0x0008  /* Bus Off IRQ Flag                                                             */
-#define WUIF            0x0010  /* Wake-Up IRQ Flag                                                             */
-#define UIAIF           0x0020  /* Access To Unimplemented Address IRQ Flag             */
-#define AAIF            0x0040  /* Abort Acknowledge IRQ Flag                                   */
-#define RMLIF           0x0080  /* RX Message Lost IRQ Flag                                             */
-#define UCEIF           0x0100  /* Universal Counter Overflow IRQ Flag                  */
-#define EXTIF           0x0200  /* External Trigger Output IRQ Flag                             */
-#define ADIF            0x0400  /* Access Denied IRQ Flag                                               */
-
-/* CAN_UCCNF Masks                                                                                                                      */
-#define UCCNF           0x000F  /* Universal Counter Mode                                               */
-#define UC_STAMP        0x0001  /*              Timestamp Mode                                                  */
-#define UC_WDOG         0x0002  /*              Watchdog Mode                                                   */
-#define UC_AUTOTX       0x0003  /*              Auto-Transmit Mode                                              */
-#define UC_ERROR        0x0006  /*              CAN Error Frame Count                                   */
-#define UC_OVER         0x0007  /*              CAN Overload Frame Count                                */
-#define UC_LOST         0x0008  /*              Arbitration Lost During TX Count                */
-#define UC_AA           0x0009  /*              TX Abort Count                                                  */
-#define UC_TA           0x000A  /*              TX Successful Count                                             */
-#define UC_REJECT       0x000B  /*              RX Message Rejected Count                               */
-#define UC_RML          0x000C  /*              RX Message Lost Count                                   */
-#define UC_RX           0x000D  /*              Total Successful RX Messages Count              */
-#define UC_RMP          0x000E  /*              Successful RX W/Matching ID Count               */
-#define UC_ALL          0x000F  /*              Correct Message On CAN Bus Line Count   */
-#define UCRC            0x0020  /* Universal Counter Reload/Clear                               */
-#define UCCT            0x0040  /* Universal Counter CAN Trigger                                */
-#define UCE                     0x0080  /* Universal Counter Enable                                             */
-
-/* CAN_ESR Masks                                                                                */
-#define ACKE            0x0004  /* Acknowledge Error            */
-#define SER                     0x0008  /* Stuff Error                          */
-#define CRCE            0x0010  /* CRC Error                            */
-#define SA0                     0x0020  /* Stuck At Dominant Error      */
-#define BEF                     0x0040  /* Bit Error Flag                       */
-#define FER                     0x0080  /* Form Error Flag                      */
-
-/* CAN_EWR Masks                                                                                                */
-#define EWLREC          0x00FF  /* RX Error Count Limit (For EWRIS)     */
-#define EWLTEC          0xFF00  /* TX Error Count Limit (For EWTIS)     */
-
-/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
-/* PORT_MUX Masks                                                                                                                       */
-#define PJSE                    0x0001  /* Port J SPI/SPORT Enable                      */
-#define PJSE_SPORT              0x0000  /*              Enable TFS0/DT0PRI                      */
-#define PJSE_SPI                0x0001  /*              Enable SPI_SSEL3:2                      */
-
-#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
-#define PJCE_SPORT              0x0000  /*              Enable DR0SEC/DT0SEC            */
-#define PJCE_CAN                0x0002  /*              Enable CAN RX/TX                        */
-#define PJCE_SPI                0x0004  /*              Enable SPI_SSEL7                        */
-
-#define PFDE                    0x0008  /* Port F DMA Request Enable            */
-#define PFDE_UART               0x0000  /*              Enable UART0 RX/TX                      */
-#define PFDE_DMA                0x0008  /*              Enable DMAR1:0                          */
-
-#define PFTE                    0x0010  /* Port F Timer Enable                          */
-#define PFTE_UART               0x0000  /*              Enable UART1 RX/TX                      */
-#define PFTE_TIMER              0x0010  /*              Enable TMR7:6                           */
-
-#define PFS6E                   0x0020  /* Port F SPI SSEL 6 Enable                     */
-#define PFS6E_TIMER             0x0000  /*              Enable TMR5                                     */
-#define PFS6E_SPI               0x0020  /*              Enable SPI_SSEL6                        */
-
-#define PFS5E                   0x0040  /* Port F SPI SSEL 5 Enable                     */
-#define PFS5E_TIMER             0x0000  /*              Enable TMR4                                     */
-#define PFS5E_SPI               0x0040  /*              Enable SPI_SSEL5                        */
-
-#define PFS4E                   0x0080  /* Port F SPI SSEL 4 Enable                     */
-#define PFS4E_TIMER             0x0000  /*              Enable TMR3                                     */
-#define PFS4E_SPI               0x0080  /*              Enable SPI_SSEL4                        */
-
-#define PFFE                    0x0100  /* Port F PPI Frame Sync Enable         */
-#define PFFE_TIMER              0x0000  /*              Enable TMR2                                     */
-#define PFFE_PPI                0x0100  /*              Enable PPI FS3                          */
-
-#define PGSE                    0x0200  /* Port G SPORT1 Secondary Enable       */
-#define PGSE_PPI                0x0000  /*              Enable PPI D9:8                         */
-#define PGSE_SPORT              0x0200  /*              Enable DR1SEC/DT1SEC            */
-
-#define PGRE                    0x0400  /* Port G SPORT1 Receive Enable         */
-#define PGRE_PPI                0x0000  /*              Enable PPI D12:10                       */
-#define PGRE_SPORT              0x0400  /*              Enable DR1PRI/RFS1/RSCLK1       */
-
-#define PGTE                    0x0800  /* Port G SPORT1 Transmit Enable        */
-#define PGTE_PPI                0x0000  /*              Enable PPI D15:13                       */
-#define PGTE_SPORT              0x0800  /*              Enable DT1PRI/TFS1/TSCLK1       */
-
-/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
-/* HDMAx_CTL Masks                                                                                                              */
-#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
-#define REP                     0x0002  /* HDMA Request Polarity                                        */
-#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
-#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
-#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
-#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
-#define DRQ                     0x0300  /* HDMA Request Type                                            */
-#define DRQ_NONE        0x0000  /*              No Request                                                      */
-#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
-#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
-#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
-#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
-#define PS                      0x2000  /* HDMA Pin Status                                                      */
-#define OI                      0x4000  /* Overflow Interrupt Generated                         */
-#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
-
-/* entry addresses of the user-callable Boot ROM functions */
-
-#define _BOOTROM_RESET 0xEF000000 
-#define _BOOTROM_FINAL_INIT 0xEF000002 
-#define _BOOTROM_DO_MEMORY_DMA 0xEF000006
-#define _BOOTROM_BOOT_DXE_FLASH 0xEF000008 
-#define _BOOTROM_BOOT_DXE_SPI 0xEF00000A 
-#define _BOOTROM_BOOT_DXE_TWI 0xEF00000C 
-#define _BOOTROM_GET_DXE_ADDRESS_FLASH 0xEF000010
-#define _BOOTROM_GET_DXE_ADDRESS_SPI 0xEF000012
-#define _BOOTROM_GET_DXE_ADDRESS_TWI 0xEF000014
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define PGDE_UART   PFDE_UART
-#define PGDE_DMA    PFDE_DMA
-#define CKELOW          SCKELOW
-#endif                          /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
deleted file mode 100644
index abde24c6d3b1..000000000000
--- a/include/asm-blackfin/mach-bf537/defBF537.h
+++ /dev/null
@@ -1,405 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/defbf537.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _DEF_BF537_H
-#define _DEF_BF537_H
-
-/* Include all Core registers and bit definitions*/
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* Include all MMR and bit defines common to BF534 */
-#include "defBF534.h"
-
-/************************************************************************************
-** Define EMAC Section Unique to BF536/BF537
-*************************************************************************************/
-
-/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                                                               */
-#define EMAC_OPMODE                     0xFFC03000      /* Operating Mode Register                                                              */
-#define EMAC_ADDRLO                     0xFFC03004      /* Address Low (32 LSBs) Register                                               */
-#define EMAC_ADDRHI                     0xFFC03008      /* Address High (16 MSBs) Register                                              */
-#define EMAC_HASHLO                     0xFFC0300C      /* Multicast Hash Table Low (Bins 31-0) Register                */
-#define EMAC_HASHHI                     0xFFC03010      /* Multicast Hash Table High (Bins 63-32) Register              */
-#define EMAC_STAADD                     0xFFC03014      /* Station Management Address Register                                  */
-#define EMAC_STADAT                     0xFFC03018      /* Station Management Data Register                                     */
-#define EMAC_FLC                        0xFFC0301C      /* Flow Control Register                                                                */
-#define EMAC_VLAN1                      0xFFC03020      /* VLAN1 Tag Register                                                                   */
-#define EMAC_VLAN2                      0xFFC03024      /* VLAN2 Tag Register                                                                   */
-#define EMAC_WKUP_CTL           0xFFC0302C      /* Wake-Up Control/Status Register                                              */
-#define EMAC_WKUP_FFMSK0        0xFFC03030      /* Wake-Up Frame Filter 0 Byte Mask Register                    */
-#define EMAC_WKUP_FFMSK1        0xFFC03034      /* Wake-Up Frame Filter 1 Byte Mask Register                    */
-#define EMAC_WKUP_FFMSK2        0xFFC03038      /* Wake-Up Frame Filter 2 Byte Mask Register                    */
-#define EMAC_WKUP_FFMSK3        0xFFC0303C      /* Wake-Up Frame Filter 3 Byte Mask Register                    */
-#define EMAC_WKUP_FFCMD         0xFFC03040      /* Wake-Up Frame Filter Commands Register                               */
-#define EMAC_WKUP_FFOFF         0xFFC03044      /* Wake-Up Frame Filter Offsets Register                                */
-#define EMAC_WKUP_FFCRC0        0xFFC03048      /* Wake-Up Frame Filter 0,1 CRC-16 Register                             */
-#define EMAC_WKUP_FFCRC1        0xFFC0304C      /* Wake-Up Frame Filter 2,3 CRC-16 Register                             */
-
-#define EMAC_SYSCTL                     0xFFC03060      /* EMAC System Control Register                                                 */
-#define EMAC_SYSTAT                     0xFFC03064      /* EMAC System Status Register                                                  */
-#define EMAC_RX_STAT            0xFFC03068      /* RX Current Frame Status Register                                             */
-#define EMAC_RX_STKY            0xFFC0306C      /* RX Sticky Frame Status Register                                              */
-#define EMAC_RX_IRQE            0xFFC03070      /* RX Frame Status Interrupt Enables Register                   */
-#define EMAC_TX_STAT            0xFFC03074      /* TX Current Frame Status Register                                             */
-#define EMAC_TX_STKY            0xFFC03078      /* TX Sticky Frame Status Register                                              */
-#define EMAC_TX_IRQE            0xFFC0307C      /* TX Frame Status Interrupt Enables Register                   */
-
-#define EMAC_MMC_CTL            0xFFC03080      /* MMC Counter Control Register                                                 */
-#define EMAC_MMC_RIRQS          0xFFC03084      /* MMC RX Interrupt Status Register                                             */
-#define EMAC_MMC_RIRQE          0xFFC03088      /* MMC RX Interrupt Enables Register                                    */
-#define EMAC_MMC_TIRQS          0xFFC0308C      /* MMC TX Interrupt Status Register                                             */
-#define EMAC_MMC_TIRQE          0xFFC03090      /* MMC TX Interrupt Enables Register                                    */
-
-#define EMAC_RXC_OK                     0xFFC03100      /* RX Frame Successful Count                                                    */
-#define EMAC_RXC_FCS            0xFFC03104      /* RX Frame FCS Failure Count                                                   */
-#define EMAC_RXC_ALIGN          0xFFC03108      /* RX Alignment Error Count                                                             */
-#define EMAC_RXC_OCTET          0xFFC0310C      /* RX Octets Successfully Received Count                                */
-#define EMAC_RXC_DMAOVF         0xFFC03110      /* Internal MAC Sublayer Error RX Frame Count                   */
-#define EMAC_RXC_UNICST         0xFFC03114      /* Unicast RX Frame Count                                                               */
-#define EMAC_RXC_MULTI          0xFFC03118      /* Multicast RX Frame Count                                                             */
-#define EMAC_RXC_BROAD          0xFFC0311C      /* Broadcast RX Frame Count                                                             */
-#define EMAC_RXC_LNERRI         0xFFC03120      /* RX Frame In Range Error Count                                                */
-#define EMAC_RXC_LNERRO         0xFFC03124      /* RX Frame Out Of Range Error Count                                    */
-#define EMAC_RXC_LONG           0xFFC03128      /* RX Frame Too Long Count                                                              */
-#define EMAC_RXC_MACCTL         0xFFC0312C      /* MAC Control RX Frame Count                                                   */
-#define EMAC_RXC_OPCODE         0xFFC03130      /* Unsupported Op-Code RX Frame Count                                   */
-#define EMAC_RXC_PAUSE          0xFFC03134      /* MAC Control Pause RX Frame Count                                             */
-#define EMAC_RXC_ALLFRM         0xFFC03138      /* Overall RX Frame Count                                                               */
-#define EMAC_RXC_ALLOCT         0xFFC0313C      /* Overall RX Octet Count                                                               */
-#define EMAC_RXC_TYPED          0xFFC03140      /* Type/Length Consistent RX Frame Count                                */
-#define EMAC_RXC_SHORT          0xFFC03144      /* RX Frame Fragment Count - Byte Count x < 64                  */
-#define EMAC_RXC_EQ64           0xFFC03148      /* Good RX Frame Count - Byte Count x = 64                              */
-#define EMAC_RXC_LT128          0xFFC0314C      /* Good RX Frame Count - Byte Count  64 <= x < 128              */
-#define EMAC_RXC_LT256          0xFFC03150      /* Good RX Frame Count - Byte Count 128 <= x < 256              */
-#define EMAC_RXC_LT512          0xFFC03154      /* Good RX Frame Count - Byte Count 256 <= x < 512              */
-#define EMAC_RXC_LT1024         0xFFC03158      /* Good RX Frame Count - Byte Count 512 <= x < 1024             */
-#define EMAC_RXC_GE1024         0xFFC0315C      /* Good RX Frame Count - Byte Count x >= 1024                   */
-
-#define EMAC_TXC_OK                     0xFFC03180      /* TX Frame Successful Count                                                    */
-#define EMAC_TXC_1COL           0xFFC03184      /* TX Frames Successful After Single Collision Count    */
-#define EMAC_TXC_GT1COL         0xFFC03188      /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET          0xFFC0318C      /* TX Octets Successfully Received Count                                */
-#define EMAC_TXC_DEFER          0xFFC03190      /* TX Frame Delayed Due To Busy Count                                   */
-#define EMAC_TXC_LATECL         0xFFC03194      /* Late TX Collisions Count                                                             */
-#define EMAC_TXC_XS_COL         0xFFC03198      /* TX Frame Failed Due To Excessive Collisions Count    */
-#define EMAC_TXC_DMAUND         0xFFC0319C      /* Internal MAC Sublayer Error TX Frame Count                   */
-#define EMAC_TXC_CRSERR         0xFFC031A0      /* Carrier Sense Deasserted During TX Frame Count               */
-#define EMAC_TXC_UNICST         0xFFC031A4      /* Unicast TX Frame Count                                                               */
-#define EMAC_TXC_MULTI          0xFFC031A8      /* Multicast TX Frame Count                                                             */
-#define EMAC_TXC_BROAD          0xFFC031AC      /* Broadcast TX Frame Count                                                             */
-#define EMAC_TXC_XS_DFR         0xFFC031B0      /* TX Frames With Excessive Deferral Count                              */
-#define EMAC_TXC_MACCTL         0xFFC031B4      /* MAC Control TX Frame Count                                                   */
-#define EMAC_TXC_ALLFRM         0xFFC031B8      /* Overall TX Frame Count                                                               */
-#define EMAC_TXC_ALLOCT         0xFFC031BC      /* Overall TX Octet Count                                                               */
-#define EMAC_TXC_EQ64           0xFFC031C0      /* Good TX Frame Count - Byte Count x = 64                              */
-#define EMAC_TXC_LT128          0xFFC031C4      /* Good TX Frame Count - Byte Count  64 <= x < 128              */
-#define EMAC_TXC_LT256          0xFFC031C8      /* Good TX Frame Count - Byte Count 128 <= x < 256              */
-#define EMAC_TXC_LT512          0xFFC031CC      /* Good TX Frame Count - Byte Count 256 <= x < 512              */
-#define EMAC_TXC_LT1024         0xFFC031D0      /* Good TX Frame Count - Byte Count 512 <= x < 1024             */
-#define EMAC_TXC_GE1024         0xFFC031D4      /* Good TX Frame Count - Byte Count x >= 1024                   */
-#define EMAC_TXC_ABORT          0xFFC031D8      /* Total TX Frames Aborted Count                                                */
-
-/* Listing for IEEE-Supported Count Registers                                                                                                                                   */
-#define FramesReceivedOK                                EMAC_RXC_OK     /* RX Frame Successful Count                                                    */
-#define FrameCheckSequenceErrors                EMAC_RXC_FCS    /* RX Frame FCS Failure Count                                                   */
-#define AlignmentErrors                                 EMAC_RXC_ALIGN  /* RX Alignment Error Count                                                             */
-#define OctetsReceivedOK                                EMAC_RXC_OCTET  /* RX Octets Successfully Received Count                                */
-#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count                   */
-#define UnicastFramesReceivedOK                 EMAC_RXC_UNICST /* Unicast RX Frame Count                                                               */
-#define MulticastFramesReceivedOK               EMAC_RXC_MULTI  /* Multicast RX Frame Count                                                             */
-#define BroadcastFramesReceivedOK               EMAC_RXC_BROAD  /* Broadcast RX Frame Count                                                             */
-#define InRangeLengthErrors                             EMAC_RXC_LNERRI /* RX Frame In Range Error Count                                                */
-#define OutOfRangeLengthField                   EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count                                    */
-#define FrameTooLongErrors                              EMAC_RXC_LONG   /* RX Frame Too Long Count                                                              */
-#define MACControlFramesReceived                EMAC_RXC_MACCTL /* MAC Control RX Frame Count                                                   */
-#define UnsupportedOpcodesReceived              EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count                                   */
-#define PAUSEMACCtrlFramesReceived              EMAC_RXC_PAUSE  /* MAC Control Pause RX Frame Count                                             */
-#define FramesReceivedAll                               EMAC_RXC_ALLFRM /* Overall RX Frame Count                                                               */
-#define OctetsReceivedAll                               EMAC_RXC_ALLOCT /* Overall RX Octet Count                                                               */
-#define TypedFramesReceived                             EMAC_RXC_TYPED  /* Type/Length Consistent RX Frame Count                                */
-#define FramesLenLt64Received                   EMAC_RXC_SHORT  /* RX Frame Fragment Count - Byte Count x < 64                  */
-#define FramesLenEq64Received                   EMAC_RXC_EQ64   /* Good RX Frame Count - Byte Count x = 64                              */
-#define FramesLen65_127Received                 EMAC_RXC_LT128  /* Good RX Frame Count - Byte Count  64 <= x < 128              */
-#define FramesLen128_255Received                EMAC_RXC_LT256  /* Good RX Frame Count - Byte Count 128 <= x < 256              */
-#define FramesLen256_511Received                EMAC_RXC_LT512  /* Good RX Frame Count - Byte Count 256 <= x < 512              */
-#define FramesLen512_1023Received               EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024             */
-#define FramesLen1024_MaxReceived               EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024                   */
-
-#define FramesTransmittedOK                             EMAC_TXC_OK     /* TX Frame Successful Count                                                    */
-#define SingleCollisionFrames                   EMAC_TXC_1COL   /* TX Frames Successful After Single Collision Count    */
-#define MultipleCollisionFrames                 EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
-#define OctetsTransmittedOK                             EMAC_TXC_OCTET  /* TX Octets Successfully Received Count                                */
-#define FramesWithDeferredXmissions             EMAC_TXC_DEFER  /* TX Frame Delayed Due To Busy Count                                   */
-#define LateCollisions                                  EMAC_TXC_LATECL /* Late TX Collisions Count                                                             */
-#define FramesAbortedDueToXSColls               EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count    */
-#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count                   */
-#define CarrierSenseErrors                              EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count               */
-#define UnicastFramesXmittedOK                  EMAC_TXC_UNICST /* Unicast TX Frame Count                                                               */
-#define MulticastFramesXmittedOK                EMAC_TXC_MULTI  /* Multicast TX Frame Count                                                             */
-#define BroadcastFramesXmittedOK                EMAC_TXC_BROAD  /* Broadcast TX Frame Count                                                             */
-#define FramesWithExcessiveDeferral             EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count                              */
-#define MACControlFramesTransmitted             EMAC_TXC_MACCTL /* MAC Control TX Frame Count                                                   */
-#define FramesTransmittedAll                    EMAC_TXC_ALLFRM /* Overall TX Frame Count                                                               */
-#define OctetsTransmittedAll                    EMAC_TXC_ALLOCT /* Overall TX Octet Count                                                               */
-#define FramesLenEq64Transmitted                EMAC_TXC_EQ64   /* Good TX Frame Count - Byte Count x = 64                              */
-#define FramesLen65_127Transmitted              EMAC_TXC_LT128  /* Good TX Frame Count - Byte Count  64 <= x < 128              */
-#define FramesLen128_255Transmitted             EMAC_TXC_LT256  /* Good TX Frame Count - Byte Count 128 <= x < 256              */
-#define FramesLen256_511Transmitted             EMAC_TXC_LT512  /* Good TX Frame Count - Byte Count 256 <= x < 512              */
-#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024             */
-#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024                   */
-#define TxAbortedFrames                                 EMAC_TXC_ABORT  /* Total TX Frames Aborted Count                                                */
-
-/***********************************************************************************
-** System MMR Register Bits And Macros
-**
-** Disclaimer:  All macros are intended to make C and Assembly code more readable.
-**                              Use these macros carefully, as any that do left shifts for field
-**                              depositing will result in the lower order bits being destroyed.  Any
-**                              macro that shifts left to properly position the bit-field should be
-**                              used as part of an OR to initialize a register and NOT as a dynamic
-**                              modifier UNLESS the lower order bits are saved and ORed back in when
-**                              the macro is used.
-*************************************************************************************/
-/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
-/* EMAC_OPMODE Masks                                                                                                                            */
-#define RE                      0x00000001      /* Receiver Enable                                                                      */
-#define ASTP            0x00000002      /* Enable Automatic Pad Stripping On RX Frames          */
-#define HU                      0x00000010      /* Hash Filter Unicast Address                                          */
-#define HM                      0x00000020      /* Hash Filter Multicast Address                                        */
-#define PAM                     0x00000040      /* Pass-All-Multicast Mode Enable                                       */
-#define PR                      0x00000080      /* Promiscuous Mode Enable                                                      */
-#define IFE                     0x00000100      /* Inverse Filtering Enable                                                     */
-#define DBF                     0x00000200      /* Disable Broadcast Frame Reception                            */
-#define PBF                     0x00000400      /* Pass Bad Frames Enable                                                       */
-#define PSF                     0x00000800      /* Pass Short Frames Enable                                                     */
-#define RAF                     0x00001000      /* Receive-All Mode                                                                     */
-#define TE                      0x00010000      /* Transmitter Enable                                                           */
-#define DTXPAD          0x00020000      /* Disable Automatic TX Padding                                         */
-#define DTXCRC          0x00040000      /* Disable Automatic TX CRC Generation                          */
-#define DC                      0x00080000      /* Deferral Check                                                                       */
-#define BOLMT           0x00300000      /* Back-Off Limit                                                                       */
-#define BOLMT_10        0x00000000      /*              10-bit range                                                            */
-#define BOLMT_8         0x00100000      /*              8-bit range                                                                     */
-#define BOLMT_4         0x00200000      /*              4-bit range                                                                     */
-#define BOLMT_1         0x00300000      /*              1-bit range                                                                     */
-#define DRTY            0x00400000      /* Disable TX Retry On Collision                                        */
-#define LCTRE           0x00800000      /* Enable TX Retry On Late Collision                            */
-#define RMII            0x01000000      /* RMII/MII* Mode                                                                       */
-#define RMII_10         0x02000000      /* Speed Select for RMII Port (10MBit/100MBit*)         */
-#define FDMODE          0x04000000      /* Duplex Mode Enable (Full/Half*)                                      */
-#define LB                      0x08000000      /* Internal Loopback Enable                                                     */
-#define DRO                     0x10000000      /* Disable Receive Own Frames (Half-Duplex Mode)        */
-
-/* EMAC_STAADD Masks                                                                                                                            */
-#define STABUSY         0x00000001      /* Initiate Station Mgt Reg Access / STA Busy Stat      */
-#define STAOP           0x00000002      /* Station Management Operation Code (Write/Read*)      */
-#define STADISPRE       0x00000004      /* Disable Preamble Generation                                          */
-#define STAIE           0x00000008      /* Station Mgt. Transfer Done Interrupt Enable          */
-#define REGAD           0x000007C0      /* STA Register Address                                                         */
-#define PHYAD           0x0000F800      /* PHY Device Address                                                           */
-
-#define SET_REGAD(x)    (((x)&0x1F)<<  6 )      /* Set STA Register Address                             */
-#define SET_PHYAD(x)    (((x)&0x1F)<< 11 )      /* Set PHY Device Address                               */
-
-/* EMAC_STADAT Mask                                                                                     */
-#define STADATA         0x0000FFFF      /* Station Management Data      */
-
-/* EMAC_FLC Masks                                                                                                                                       */
-#define FLCBUSY         0x00000001      /* Send Flow Ctrl Frame / Flow Ctrl Busy Status         */
-#define FLCE            0x00000002      /* Flow Control Enable                                                          */
-#define PCF                     0x00000004      /* Pass Control Frames                                                          */
-#define BKPRSEN         0x00000008      /* Enable Backpressure                                                          */
-#define FLCPAUSE        0xFFFF0000      /* Pause Time                                                                           */
-
-#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16)     /* Set Pause Time                                               */
-
-/* EMAC_WKUP_CTL Masks                                                                                                                          */
-#define CAPWKFRM        0x00000001      /* Capture Wake-Up Frames                                                       */
-#define MPKE            0x00000002      /* Magic Packet Enable                                                          */
-#define RWKE            0x00000004      /* Remote Wake-Up Frame Enable                                          */
-#define GUWKE           0x00000008      /* Global Unicast Wake Enable                                           */
-#define MPKS            0x00000020      /* Magic Packet Received Status                                         */
-#define RWKS            0x00000F00      /* Wake-Up Frame Received Status, Filters 3:0           */
-
-/* EMAC_WKUP_FFCMD Masks                                                                                                                        */
-#define WF0_E           0x00000001      /* Enable Wake-Up Filter 0                                                      */
-#define WF0_T           0x00000008      /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
-#define WF1_E           0x00000100      /* Enable Wake-Up Filter 1                                                      */
-#define WF1_T           0x00000800      /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
-#define WF2_E           0x00010000      /* Enable Wake-Up Filter 2                                                      */
-#define WF2_T           0x00080000      /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
-#define WF3_E           0x01000000      /* Enable Wake-Up Filter 3                                                      */
-#define WF3_T           0x08000000      /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
-
-/* EMAC_WKUP_FFOFF Masks                                                                                                                        */
-#define WF0_OFF         0x000000FF      /* Wake-Up Filter 0 Pattern Offset                                      */
-#define WF1_OFF         0x0000FF00      /* Wake-Up Filter 1 Pattern Offset                                      */
-#define WF2_OFF         0x00FF0000      /* Wake-Up Filter 2 Pattern Offset                                      */
-#define WF3_OFF         0xFF000000      /* Wake-Up Filter 3 Pattern Offset                                      */
-
-#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 )       /* Set Wake-Up Filter 0 Byte Offset           */
-#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 )       /* Set Wake-Up Filter 1 Byte Offset           */
-#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 )       /* Set Wake-Up Filter 2 Byte Offset           */
-#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 )       /* Set Wake-Up Filter 3 Byte Offset           */
-/* Set ALL Offsets                                                                                                                                      */
-#define SET_WF_OFFS(x0,x1,x2,x3)        (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
-
-/* EMAC_WKUP_FFCRC0 Masks                                                                                                                       */
-#define WF0_CRC         0x0000FFFF      /* Wake-Up Filter 0 Pattern CRC                                         */
-#define WF1_CRC         0xFFFF0000      /* Wake-Up Filter 1 Pattern CRC                                         */
-
-#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 )    /* Set Wake-Up Filter 0 Target CRC         */
-#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 )    /* Set Wake-Up Filter 1 Target CRC         */
-
-/* EMAC_WKUP_FFCRC1 Masks                                                                                                                       */
-#define WF2_CRC         0x0000FFFF      /* Wake-Up Filter 2 Pattern CRC                                         */
-#define WF3_CRC         0xFFFF0000      /* Wake-Up Filter 3 Pattern CRC                                         */
-
-#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 )    /* Set Wake-Up Filter 2 Target CRC         */
-#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 )    /* Set Wake-Up Filter 3 Target CRC         */
-
-/* EMAC_SYSCTL Masks                                                                                                                            */
-#define PHYIE           0x00000001      /* PHY_INT Interrupt Enable                                                     */
-#define RXDWA           0x00000002      /* Receive Frame DMA Word Alignment (Odd/Even*)         */
-#define RXCKS           0x00000004      /* Enable RX Frame TCP/UDP Checksum Computation         */
-#define TXDWA           0x00000010      /* Transmit Frame DMA Word Alignment (Odd/Even*)        */
-#define MDCDIV          0x00003F00      /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]          */
-
-#define SET_MDCDIV(x)   (((x)&0x3F)<< 8)        /* Set MDC Clock Divisor                                */
-
-/* EMAC_SYSTAT Masks                                                                                                                    */
-#define PHYINT          0x00000001      /* PHY_INT Interrupt Status                                             */
-#define MMCINT          0x00000002      /* MMC Counter Interrupt Status                                 */
-#define RXFSINT         0x00000004      /* RX Frame-Status Interrupt Status                             */
-#define TXFSINT         0x00000008      /* TX Frame-Status Interrupt Status                             */
-#define WAKEDET         0x00000010      /* Wake-Up Detected Status                                              */
-#define RXDMAERR        0x00000020      /* RX DMA Direction Error Status                                */
-#define TXDMAERR        0x00000040      /* TX DMA Direction Error Status                                */
-#define STMDONE         0x00000080      /* Station Mgt. Transfer Done Interrupt Status  */
-
-/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks                                                   */
-#define RX_FRLEN        0x000007FF      /* Frame Length In Bytes                                                */
-#define RX_COMP         0x00001000      /* RX Frame Complete                                                    */
-#define RX_OK           0x00002000      /* RX Frame Received With No Errors                             */
-#define RX_LONG         0x00004000      /* RX Frame Too Long Error                                              */
-#define RX_ALIGN        0x00008000      /* RX Frame Alignment Error                                             */
-#define RX_CRC          0x00010000      /* RX Frame CRC Error                                                   */
-#define RX_LEN          0x00020000      /* RX Frame Length Error                                                */
-#define RX_FRAG         0x00040000      /* RX Frame Fragment Error                                              */
-#define RX_ADDR         0x00080000      /* RX Frame Address Filter Failed Error                 */
-#define RX_DMAO         0x00100000      /* RX Frame DMA Overrun Error                                   */
-#define RX_PHY          0x00200000      /* RX Frame PHY Error                                                   */
-#define RX_LATE         0x00400000      /* RX Frame Late Collision Error                                */
-#define RX_RANGE        0x00800000      /* RX Frame Length Field Out of Range Error             */
-#define RX_MULTI        0x01000000      /* RX Multicast Frame Indicator                                 */
-#define RX_BROAD        0x02000000      /* RX Broadcast Frame Indicator                                 */
-#define RX_CTL          0x04000000      /* RX Control Frame Indicator                                   */
-#define RX_UCTL         0x08000000      /* Unsupported RX Control Frame Indicator               */
-#define RX_TYPE         0x10000000      /* RX Typed Frame Indicator                                             */
-#define RX_VLAN1        0x20000000      /* RX VLAN1 Frame Indicator                                             */
-#define RX_VLAN2        0x40000000      /* RX VLAN2 Frame Indicator                                             */
-#define RX_ACCEPT       0x80000000      /* RX Frame Accepted Indicator                                  */
-
-/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks                                                  */
-#define TX_COMP         0x00000001      /* TX Frame Complete                                                    */
-#define TX_OK           0x00000002      /* TX Frame Sent With No Errors                                 */
-#define TX_ECOLL        0x00000004      /* TX Frame Excessive Collision Error                   */
-#define TX_LATE         0x00000008      /* TX Frame Late Collision Error                                */
-#define TX_DMAU         0x00000010      /* TX Frame DMA Underrun Error (STAT)                   */
-#define TX_MACE         0x00000010      /* Internal MAC Error Detected (STKY and IRQE)  */
-#define TX_EDEFER       0x00000020      /* TX Frame Excessive Deferral Error                    */
-#define TX_BROAD        0x00000040      /* TX Broadcast Frame Indicator                                 */
-#define TX_MULTI        0x00000080      /* TX Multicast Frame Indicator                                 */
-#define TX_CCNT         0x00000F00      /* TX Frame Collision Count                                             */
-#define TX_DEFER        0x00001000      /* TX Frame Deferred Indicator                                  */
-#define TX_CRS          0x00002000      /* TX Frame Carrier Sense Not Asserted Error    */
-#define TX_LOSS         0x00004000      /* TX Frame Carrier Lost During TX Error                */
-#define TX_RETRY        0x00008000      /* TX Frame Successful After Retry                              */
-#define TX_FRLEN        0x07FF0000      /* TX Frame Length (Bytes)                                              */
-
-/* EMAC_MMC_CTL Masks                                                                                                                   */
-#define RSTC            0x00000001      /* Reset All Counters                                                   */
-#define CROLL           0x00000002      /* Counter Roll-Over Enable                                             */
-#define CCOR            0x00000004      /* Counter Clear-On-Read Mode Enable                    */
-#define MMCE            0x00000008      /* Enable MMC Counter Operation                                 */
-
-/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks                                                                                      */
-#define RX_OK_CNT               0x00000001      /* RX Frames Received With No Errors                    */
-#define RX_FCS_CNT              0x00000002      /* RX Frames W/Frame Check Sequence Errors              */
-#define RX_ALIGN_CNT    0x00000004      /* RX Frames With Alignment Errors                              */
-#define RX_OCTET_CNT    0x00000008      /* RX Octets Received OK                                                */
-#define RX_LOST_CNT             0x00000010      /* RX Frames Lost Due To Internal MAC RX Error  */
-#define RX_UNI_CNT              0x00000020      /* Unicast RX Frames Received OK                                */
-#define RX_MULTI_CNT    0x00000040      /* Multicast RX Frames Received OK                              */
-#define RX_BROAD_CNT    0x00000080      /* Broadcast RX Frames Received OK                              */
-#define RX_IRL_CNT              0x00000100      /* RX Frames With In-Range Length Errors                */
-#define RX_ORL_CNT              0x00000200      /* RX Frames With Out-Of-Range Length Errors    */
-#define RX_LONG_CNT             0x00000400      /* RX Frames With Frame Too Long Errors                 */
-#define RX_MACCTL_CNT   0x00000800      /* MAC Control RX Frames Received                               */
-#define RX_OPCODE_CTL   0x00001000      /* Unsupported Op-Code RX Frames Received               */
-#define RX_PAUSE_CNT    0x00002000      /* PAUSEMAC Control RX Frames Received                  */
-#define RX_ALLF_CNT             0x00004000      /* All RX Frames Received                                               */
-#define RX_ALLO_CNT             0x00008000      /* All RX Octets Received                                               */
-#define RX_TYPED_CNT    0x00010000      /* Typed RX Frames Received                                             */
-#define RX_SHORT_CNT    0x00020000      /* RX Frame Fragments (< 64 Bytes) Received             */
-#define RX_EQ64_CNT             0x00040000      /* 64-Byte RX Frames Received                                   */
-#define RX_LT128_CNT    0x00080000      /* 65-127-Byte RX Frames Received                               */
-#define RX_LT256_CNT    0x00100000      /* 128-255-Byte RX Frames Received                              */
-#define RX_LT512_CNT    0x00200000      /* 256-511-Byte RX Frames Received                              */
-#define RX_LT1024_CNT   0x00400000      /* 512-1023-Byte RX Frames Received                             */
-#define RX_GE1024_CNT   0x00800000      /* 1024-Max-Byte RX Frames Received                             */
-
-/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks                                                                                      */
-#define TX_OK_CNT               0x00000001      /* TX Frames Sent OK                                                    */
-#define TX_SCOLL_CNT    0x00000002      /* TX Frames With Single Collisions                             */
-#define TX_MCOLL_CNT    0x00000004      /* TX Frames With Multiple Collisions                   */
-#define TX_OCTET_CNT    0x00000008      /* TX Octets Sent OK                                                    */
-#define TX_DEFER_CNT    0x00000010      /* TX Frames With Deferred Transmission                 */
-#define TX_LATE_CNT             0x00000020      /* TX Frames With Late Collisions                               */
-#define TX_ABORTC_CNT   0x00000040      /* TX Frames Aborted Due To Excess Collisions   */
-#define TX_LOST_CNT             0x00000080      /* TX Frames Lost Due To Internal MAC TX Error  */
-#define TX_CRS_CNT              0x00000100      /* TX Frames With Carrier Sense Errors                  */
-#define TX_UNI_CNT              0x00000200      /* Unicast TX Frames Sent                                               */
-#define TX_MULTI_CNT    0x00000400      /* Multicast TX Frames Sent                                             */
-#define TX_BROAD_CNT    0x00000800      /* Broadcast TX Frames Sent                                             */
-#define TX_EXDEF_CTL    0x00001000      /* TX Frames With Excessive Deferral                    */
-#define TX_MACCTL_CNT   0x00002000      /* MAC Control TX Frames Sent                                   */
-#define TX_ALLF_CNT             0x00004000      /* All TX Frames Sent                                                   */
-#define TX_ALLO_CNT             0x00008000      /* All TX Octets Sent                                                   */
-#define TX_EQ64_CNT             0x00010000      /* 64-Byte TX Frames Sent                                               */
-#define TX_LT128_CNT    0x00020000      /* 65-127-Byte TX Frames Sent                                   */
-#define TX_LT256_CNT    0x00040000      /* 128-255-Byte TX Frames Sent                                  */
-#define TX_LT512_CNT    0x00080000      /* 256-511-Byte TX Frames Sent                                  */
-#define TX_LT1024_CNT   0x00100000      /* 512-1023-Byte TX Frames Sent                                 */
-#define TX_GE1024_CNT   0x00200000      /* 1024-Max-Byte TX Frames Sent                                 */
-#define TX_ABORT_CNT    0x00400000      /* TX Frames Aborted                                                    */
-
-#endif                          /* _DEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
deleted file mode 100644
index 7a964040870a..000000000000
--- a/include/asm-blackfin/mach-bf537/dma.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/dma.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 16
-
-#define CH_PPI                      0
-#define CH_EMAC_RX                  1
-#define CH_EMAC_TX                  2
-#define CH_SPORT0_RX            3
-#define CH_SPORT0_TX            4
-#define CH_SPORT1_RX            5
-#define CH_SPORT1_TX            6
-#define CH_SPI                      7
-#define CH_UART0_RX             8
-#define CH_UART0_TX             9
-#define CH_UART1_RX             10
-#define CH_UART1_TX             11
-
-#define CH_MEM_STREAM0_DEST     12       /* TX */
-#define CH_MEM_STREAM0_SRC      13       /* RX */
-#define CH_MEM_STREAM1_DEST     14       /* TX */
-#define CH_MEM_STREAM1_SRC      15       /* RX */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
deleted file mode 100644
index 2e68a8a1e730..000000000000
--- a/include/asm-blackfin/mach-bf537/irq.h
+++ /dev/null
@@ -1,214 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/irq.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _BF537_IRQ_H_
-#define _BF537_IRQ_H_
-
-/*
- * Interrupt source definitions
- *            Event Source    Core Event Name
- * Core       Emulation               **
- * Events         (highest priority)  EMU         0
- *            Reset                   RST         1
- *            NMI                     NMI         2
- *            Exception               EVX         3
- *            Reserved                --          4
- *            Hardware Error          IVHW        5
- *            Core Timer              IVTMR       6
- *  .....
- *
- *            Softirq                 IVG14
- *            System Call    --
- *               (lowest priority)    IVG15
- */
-
-#define SYS_IRQS        39
-#define NR_PERI_INTS    32
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU             0   /*Emulation */
-#define IRQ_RST             1   /*reset */
-#define IRQ_NMI             2   /*Non Maskable */
-#define IRQ_EVX             3   /*Exception */
-#define IRQ_UNUSED          4   /*- unused interrupt*/
-#define IRQ_HWERR           5   /*Hardware Error */
-#define IRQ_CORETMR         6   /*Core timer */
-
-#define IRQ_PLL_WAKEUP      7   /*PLL Wakeup Interrupt */
-#define IRQ_DMA_ERROR       8   /*DMA Error (general) */
-#define IRQ_GENERIC_ERROR   9   /*GENERIC Error Interrupt */
-#define IRQ_RTC             10  /*RTC Interrupt */
-#define IRQ_PPI             11  /*DMA0 Interrupt (PPI) */
-#define IRQ_SPORT0_RX       12  /*DMA3 Interrupt (SPORT0 RX) */
-#define IRQ_SPORT0_TX       13  /*DMA4 Interrupt (SPORT0 TX) */
-#define IRQ_SPORT1_RX       14  /*DMA5 Interrupt (SPORT1 RX) */
-#define IRQ_SPORT1_TX       15  /*DMA6 Interrupt (SPORT1 TX) */
-#define IRQ_TWI             16  /*TWI Interrupt */
-#define IRQ_SPI             17  /*DMA7 Interrupt (SPI) */
-#define IRQ_UART0_RX        18  /*DMA8 Interrupt (UART0 RX) */
-#define IRQ_UART0_TX        19  /*DMA9 Interrupt (UART0 TX) */
-#define IRQ_UART1_RX        20  /*DMA10 Interrupt (UART1 RX) */
-#define IRQ_UART1_TX        21  /*DMA11 Interrupt (UART1 TX) */
-#define IRQ_CAN_RX          22  /*CAN Receive Interrupt */
-#define IRQ_CAN_TX          23  /*CAN Transmit Interrupt */
-#define IRQ_MAC_RX          24  /*DMA1 (Ethernet RX) Interrupt */
-#define IRQ_MAC_TX          25  /*DMA2 (Ethernet TX) Interrupt */
-#define IRQ_TMR0            26  /*Timer 0 */
-#define IRQ_TMR1            27  /*Timer 1 */
-#define IRQ_TMR2            28  /*Timer 2 */
-#define IRQ_TMR3            29  /*Timer 3 */
-#define IRQ_TMR4            30  /*Timer 4 */
-#define IRQ_TMR5            31  /*Timer 5 */
-#define IRQ_TMR6            32  /*Timer 6 */
-#define IRQ_TMR7            33  /*Timer 7 */
-#define IRQ_PROG_INTA       34  /* PF Ports F&G (PF15:0) Interrupt A */
-#define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
-#define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
-#define IRQ_MEM_DMA1        37  /*(Memory DMA Stream 1) */
-#define IRQ_PROG_INTB         38        /* PF Ports F (PF15:0) Interrupt B */
-#define IRQ_WATCH           38  /*Watch Dog Timer */
-
-#define IRQ_PPI_ERROR       42  /*PPI Error Interrupt */
-#define IRQ_CAN_ERROR       43  /*CAN Error Interrupt */
-#define IRQ_MAC_ERROR       44  /*PPI Error Interrupt */
-#define IRQ_SPORT0_ERROR    45  /*SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR    46  /*SPORT1 Error Interrupt */
-#define IRQ_SPI_ERROR       47  /*SPI Error Interrupt */
-#define IRQ_UART0_ERROR     48  /*UART Error Interrupt */
-#define IRQ_UART1_ERROR     49  /*UART Error Interrupt */
-
-#define IRQ_PF0         50
-#define IRQ_PF1         51
-#define IRQ_PF2         52
-#define IRQ_PF3         53
-#define IRQ_PF4         54
-#define IRQ_PF5         55
-#define IRQ_PF6         56
-#define IRQ_PF7         57
-#define IRQ_PF8         58
-#define IRQ_PF9         59
-#define IRQ_PF10        60
-#define IRQ_PF11        61
-#define IRQ_PF12        62
-#define IRQ_PF13        63
-#define IRQ_PF14        64
-#define IRQ_PF15        65
-
-#define IRQ_PG0         66
-#define IRQ_PG1         67
-#define IRQ_PG2         68
-#define IRQ_PG3         69
-#define IRQ_PG4         70
-#define IRQ_PG5         71
-#define IRQ_PG6         72
-#define IRQ_PG7         73
-#define IRQ_PG8         74
-#define IRQ_PG9         75
-#define IRQ_PG10        76
-#define IRQ_PG11        77
-#define IRQ_PG12        78
-#define IRQ_PG13        79
-#define IRQ_PG14        80
-#define IRQ_PG15        81
-
-#define IRQ_PH0         82
-#define IRQ_PH1         83
-#define IRQ_PH2         84
-#define IRQ_PH3         85
-#define IRQ_PH4         86
-#define IRQ_PH5         87
-#define IRQ_PH6         88
-#define IRQ_PH7         89
-#define IRQ_PH8         90
-#define IRQ_PH9         91
-#define IRQ_PH10        92
-#define IRQ_PH11        93
-#define IRQ_PH12        94
-#define IRQ_PH13        95
-#define IRQ_PH14        96
-#define IRQ_PH15        97
-
-#define GPIO_IRQ_BASE   IRQ_PF0
-
-#define NR_IRQS     (IRQ_PH15+1)
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS*/
-#define IRQ_PLL_WAKEUP_POS  0
-#define IRQ_DMA_ERROR_POS   4
-#define IRQ_ERROR_POS       8
-#define IRQ_RTC_POS         12
-#define IRQ_PPI_POS         16
-#define IRQ_SPORT0_RX_POS   20
-#define IRQ_SPORT0_TX_POS   24
-#define IRQ_SPORT1_RX_POS   28
-
-/* IAR1 BIT FIELDS*/
-#define IRQ_SPORT1_TX_POS   0
-#define IRQ_TWI_POS         4
-#define IRQ_SPI_POS         8
-#define IRQ_UART0_RX_POS    12
-#define IRQ_UART0_TX_POS    16
-#define IRQ_UART1_RX_POS    20
-#define IRQ_UART1_TX_POS    24
-#define IRQ_CAN_RX_POS      28
-
-/* IAR2 BIT FIELDS*/
-#define IRQ_CAN_TX_POS      0
-#define IRQ_MAC_RX_POS      4
-#define IRQ_MAC_TX_POS      8
-#define IRQ_TMR0_POS        12
-#define IRQ_TMR1_POS        16
-#define IRQ_TMR2_POS        20
-#define IRQ_TMR3_POS        24
-#define IRQ_TMR4_POS        28
-
-/* IAR3 BIT FIELDS*/
-#define IRQ_TMR5_POS        0
-#define IRQ_TMR6_POS        4
-#define IRQ_TMR7_POS        8
-#define IRQ_PROG_INTA_POS   12
-#define IRQ_PORTG_INTB_POS   16
-#define IRQ_MEM_DMA0_POS    20
-#define IRQ_MEM_DMA1_POS    24
-#define IRQ_WATCH_POS       28
-
-#endif                          /* _BF537_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
deleted file mode 100644
index f67698f670ca..000000000000
--- a/include/asm-blackfin/mach-bf537/mem_init.h
+++ /dev/null
@@ -1,303 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf537/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC16M8A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC32M8A2_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
deleted file mode 100644
index 5078b669431f..000000000000
--- a/include/asm-blackfin/mach-bf537/mem_map.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf537/mem_map.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
- * rev:
- *
- * modified:
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MEM_MAP_537_H_
-#define _MEM_MAP_537_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x800
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF537 processors */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-
-#ifdef CONFIG_BF537
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif /*CONFIG_BF537*/
-
-/* Memory Map for ADSP-BF536 processors */
-
-#ifdef CONFIG_BF536
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF804000
-#define L1_DATA_B_START     0xFF904000
-
-#define L1_CODE_LENGTH      0xC000
-
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x4000
-#define L1_DATA_B_LENGTH      0x4000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Memory Map for ADSP-BF534 processors */
-
-#ifdef CONFIG_BF534
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-#endif
-
-/* Level 2 Memory - none */
-
-#define L2_START        0
-#define L2_LENGTH       0
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf537/portmux.h b/include/asm-blackfin/mach-bf537/portmux.h
deleted file mode 100644
index 78fee6e0f237..000000000000
--- a/include/asm-blackfin/mach-bf537/portmux.h
+++ /dev/null
@@ -1,144 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   (MAX_BLACKFIN_GPIOS + GPIO_BANKSIZE)    /* We additionally handle PORTJ */
-
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_DMAR0         (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_DMAR1         (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_TACLK0        (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_MII0_ETxD0    (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_MII0_ETxD1    (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_MII0_ETxD2    (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_MII0_ETxD3    (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_MII0_ETxEN    (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MII0_TxCLK    (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MII0_PHYINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MII0_COL      (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_MII0_ERxD0    (P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_MII0_ERxD1    (P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_MII0_ERxD2    (P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_MII0_ERxD3    (P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_MII0_ERxDV    (P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_MII0_ERxCLK   (P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_MII0_ERxER    (P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_MII0_CRS      (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-#define P_RMII0_REF_CLK (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_RMII0_MDINT   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_RMII0_CRS_DV  (P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-
-#define PORT_PJ0        (GPIO_PH15 + 1)
-#define PORT_PJ1        (GPIO_PH15 + 2)
-#define PORT_PJ2        (GPIO_PH15 + 3)
-#define PORT_PJ3        (GPIO_PH15 + 4)
-#define PORT_PJ4        (GPIO_PH15 + 5)
-#define PORT_PJ5        (GPIO_PH15 + 6)
-#define PORT_PJ6        (GPIO_PH15 + 7)
-#define PORT_PJ7        (GPIO_PH15 + 8)
-#define PORT_PJ8        (GPIO_PH15 + 9)
-#define PORT_PJ9        (GPIO_PH15 + 10)
-#define PORT_PJ10       (GPIO_PH15 + 11)
-#define PORT_PJ11       (GPIO_PH15 + 12)
-
-#define P_MDC           (P_DEFINED | P_IDENT(PORT_PJ0) | P_FUNCT(0))
-#define P_MDIO          (P_DEFINED | P_IDENT(PORT_PJ1) | P_FUNCT(0))
-#define P_TWI0_SCL      (P_DEFINED | P_IDENT(PORT_PJ2) | P_FUNCT(0))
-#define P_TWI0_SDA      (P_DEFINED | P_IDENT(PORT_PJ3) | P_FUNCT(0))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(0))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(PORT_PJ6) | P_FUNCT(0))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(PORT_PJ7) | P_FUNCT(0))
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(PORT_PJ8) | P_FUNCT(0))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(PORT_PJ9) | P_FUNCT(0))
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(0))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(0))
-#define P_CAN0_RX       (P_DEFINED | P_IDENT(PORT_PJ4) | P_FUNCT(1))
-#define P_CAN0_TX       (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(1))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(PORT_PJ10) | P_FUNCT(1))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(PORT_PJ11) | P_FUNCT(1))
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(PORT_PJ5) | P_FUNCT(2))
-
-#define P_MII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxD2, \
-        P_MII0_ETxD3, \
-        P_MII0_ETxEN, \
-        P_MII0_TxCLK, \
-        P_MII0_PHYINT, \
-        P_MII0_COL, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxD2, \
-        P_MII0_ERxD3, \
-        P_MII0_ERxDV, \
-        P_MII0_ERxCLK, \
-        P_MII0_ERxER, \
-        P_MII0_CRS, \
-        P_MDC, \
-        P_MDIO, 0}
-
-
-#define P_RMII0 {\
-        P_MII0_ETxD0, \
-        P_MII0_ETxD1, \
-        P_MII0_ETxEN, \
-        P_MII0_ERxD0, \
-        P_MII0_ERxD1, \
-        P_MII0_ERxER, \
-        P_RMII0_REF_CLK, \
-        P_RMII0_MDINT, \
-        P_RMII0_CRS_DV, \
-        P_MDC, \
-        P_MDIO, 0}
-#endif                                  /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h
deleted file mode 100644
index 3ad59655881a..000000000000
--- a/include/asm-blackfin/mach-bf548/anomaly.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf548/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2007 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision E, 11/28/2007; ADSP-BF542/BF544/BF547/BF548/BF549 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* False Hardware Error Exception when ISR context is not restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 1)
-/* SSYNCs After Writes To CAN/DMA MMR Registers Are Not Always Handled Correctly */
-#define ANOMALY_05000304 (__SILICON_REVISION__ < 1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 1)
-/* TWI Slave Boot Mode Is Not Functional */
-#define ANOMALY_05000324 (__SILICON_REVISION__ < 1)
-/* External FIFO Boot Mode Is Not Functional */
-#define ANOMALY_05000325 (__SILICON_REVISION__ < 1)
-/* Data Lost When Core and DMA Accesses Are Made to the USB FIFO Simultaneously */
-#define ANOMALY_05000327 (__SILICON_REVISION__ < 1)
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (__SILICON_REVISION__ < 1)
-/* Synchronous Burst Flash Boot Mode Is Not Functional */
-#define ANOMALY_05000329 (__SILICON_REVISION__ < 1)
-/* Host DMA Boot Mode Is Not Functional */
-#define ANOMALY_05000330 (__SILICON_REVISION__ < 1)
-/* Inadequate Timing Margins on DDR DQS to DQ and DQM Skew */
-#define ANOMALY_05000334 (__SILICON_REVISION__ < 1)
-/* Inadequate Rotary Debounce Logic Duration */
-#define ANOMALY_05000335 (__SILICON_REVISION__ < 1)
-/* Phantom Interrupt Occurs After First Configuration of Host DMA Port */
-#define ANOMALY_05000336 (__SILICON_REVISION__ < 1)
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (__SILICON_REVISION__ < 1)
-/* Slave-Mode SPI0 MISO Failure With CPHA = 0 */
-#define ANOMALY_05000338 (__SILICON_REVISION__ < 1)
-/* If Memory Reads Are Enabled on SDH or HOSTDP, Other DMAC1 Peripherals Cannot Read */
-#define ANOMALY_05000340 (__SILICON_REVISION__ < 1)
-/* Boot Host Wait (HWAIT) and Boot Host Wait Alternate (HWAITA) Signals Are Swapped */
-#define ANOMALY_05000344 (__SILICON_REVISION__ < 1)
-/* USB Calibration Value Is Not Intialized */
-#define ANOMALY_05000346 (__SILICON_REVISION__ < 1)
-/* Boot ROM Kernel Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (__SILICON_REVISION__ < 1)
-/* Data Lost when Core Reads SDH Data FIFO */
-#define ANOMALY_05000349 (__SILICON_REVISION__ < 1)
-/* PLL Status Register Is Inaccurate */
-#define ANOMALY_05000351 (__SILICON_REVISION__ < 1)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* External Memory Read Access Hangs Core With PLL Bypass */
-#define ANOMALY_05000360 (1)
-/* DMAs that Go Urgent during Tight Core Writes to External Memory Are Blocked */
-#define ANOMALY_05000365 (1)
-/* Addressing Conflict between Boot ROM and Asynchronous Memory */
-#define ANOMALY_05000369 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Mobile DDR Operation Not Functional */
-#define ANOMALY_05000377 (1)
-/* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */
-#define ANOMALY_05000378 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000363 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/bf548.h b/include/asm-blackfin/mach-bf548/bf548.h
deleted file mode 100644
index e748588e8930..000000000000
--- a/include/asm-blackfin/mach-bf548/bf548.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/bf548.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  System MMR register and memory map for ADSP-BF548
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF548_H__
-#define __MACH_BF548_H__
-
-#define SUPPORTED_REVID 0
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR    0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************/
-
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/********************************* EBIU Settings ************************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#ifdef CONFIG_C_AMBEN_ALL
-#define V_AMBEN AMBEN_ALL
-#endif
-#ifdef CONFIG_C_AMBEN
-#define V_AMBEN 0x0
-#endif
-#ifdef CONFIG_C_AMBEN_B0
-#define V_AMBEN AMBEN_B0
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1
-#define V_AMBEN AMBEN_B0_B1
-#endif
-#ifdef CONFIG_C_AMBEN_B0_B1_B2
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN)
-
-#if defined(CONFIG_BF542)
-# define CPU   "BF542"
-# define CPUID 0x027c8000
-#elif defined(CONFIG_BF544)
-# define CPU "BF544"
-# define CPUID 0x027c8000
-#elif defined(CONFIG_BF547)
-# define CPU "BF547"
-#elif defined(CONFIG_BF548)
-# define CPU "BF548"
-# define CPUID 0x027c6000
-#elif defined(CONFIG_BF549)
-# define CPU "BF549"
-#else
-# define CPU "UNKNOWN"
-# define CPUID 0x0
-#endif
-
-#endif  /* __MACH_BF48_H__  */
diff --git a/include/asm-blackfin/mach-bf548/bf54x-lq043.h b/include/asm-blackfin/mach-bf548/bf54x-lq043.h
deleted file mode 100644
index 9c7ca62a45eb..000000000000
--- a/include/asm-blackfin/mach-bf548/bf54x-lq043.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef BF54X_LQ043_H
-#define BF54X_LQ043_H
-
-struct bfin_bf54xfb_val {
-        unsigned int    defval;
-        unsigned int    min;
-        unsigned int    max;
-};
-
-struct bfin_bf54xfb_mach_info {
-        unsigned char   fixed_syncs;    /* do not update sync/border */
-
-        /* LCD types */
-        int             type;
-
-        /* Screen size */
-        int             width;
-        int             height;
-
-        /* Screen info */
-        struct bfin_bf54xfb_val xres;
-        struct bfin_bf54xfb_val yres;
-        struct bfin_bf54xfb_val bpp;
-
-        /* GPIOs */
-        unsigned short          disp;
-
-};
-
-#endif /* BF54X_LQ043_H */
diff --git a/include/asm-blackfin/mach-bf548/bf54x_keys.h b/include/asm-blackfin/mach-bf548/bf54x_keys.h
deleted file mode 100644
index 1fb4ec77cc25..000000000000
--- a/include/asm-blackfin/mach-bf548/bf54x_keys.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef _BFIN_KPAD_H
-#define _BFIN_KPAD_H
-
-struct bfin_kpad_platform_data {
-        int rows;
-        int cols;
-        const unsigned int *keymap;
-        unsigned short keymapsize;
-        unsigned short repeat;
-        u32 debounce_time;      /* in ns */
-        u32 coldrive_time;      /* in ns */
-        u32 keyup_test_interval; /* in ms */
-};
-
-#define KEYVAL(col, row, val) (((1 << col) << 24) | ((1 << row) << 16) | (val))
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
deleted file mode 100644
index 5e29446a8e03..000000000000
--- a/include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf548/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER_SET))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-#define UART_GET_MSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MSR))
-#define UART_GET_MCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_MCR))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_SET_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_SET),v)
-#define UART_CLEAR_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER_CLEAR),v)
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LSR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LSR),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_CLEAR_LSR(uart)    bfin_write16(((uart)->port.membase + OFFSET_LSR), -1)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-#define UART_PUT_MCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_MCR),v)
-
-#define UART_SET_DLAB(uart)     /* MMRs not muxed on BF54x */
-#define UART_CLEAR_DLAB(uart)   /* MMRs not muxed on BF54x */
-
-#define UART_GET_CTS(x) (UART_GET_MSR(x) & CTS)
-#define UART_SET_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) | MRTS))
-#define UART_CLEAR_RTS(x) (UART_PUT_MCR(x, UART_GET_MCR(x) & ~MRTS))
-#define UART_ENABLE_INTS(x, v) UART_SET_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_CLEAR_IER(x, 0xF)
-
-#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
-# define CONFIG_SERIAL_BFIN_CTSRTS
-
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_CTS_PIN
-#  define CONFIG_UART1_CTS_PIN -1
-# endif
-
-# ifndef CONFIG_UART1_RTS_PIN
-#  define CONFIG_UART1_RTS_PIN -1
-# endif
-#endif
-/*
- * The pin configuration is different from schematic
- */
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int             cts_pin;
-        int             rts_pin;
-#endif
-};
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int     uart_cts_pin;
-        int     uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART0_TX,
-        CH_UART0_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART1_TX,
-        CH_UART1_RX,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART2_TX,
-        CH_UART2_RX,
-#endif
-#ifdef CONFIG_BFIN_UART2_CTSRTS
-        CONFIG_UART2_CTS_PIN,
-        CONFIG_UART2_RTS_PIN,
-#endif
-        },
-#endif
-#ifdef CONFIG_SERIAL_BFIN_UART3
-        {
-        0xFFC03100,
-        IRQ_UART3_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART3_TX,
-        CH_UART3_RX,
-#endif
-        },
-#endif
-};
-
-int nr_ports = ARRAY_SIZE(bfin_serial_resource);
-
-#define DRIVER_NAME "bfin-uart"
-
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART1
-        peripheral_request(P_UART1_TX, DRIVER_NAME);
-        peripheral_request(P_UART1_RX, DRIVER_NAME);
-
-#ifdef CONFIG_BFIN_UART1_CTSRTS
-        peripheral_request(P_UART1_RTS, DRIVER_NAME);
-        peripheral_request(P_UART1_CTS, DRIVER_NAME);
-#endif
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART2
-        peripheral_request(P_UART2_TX, DRIVER_NAME);
-        peripheral_request(P_UART2_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_UART3
-        peripheral_request(P_UART3_TX, DRIVER_NAME);
-        peripheral_request(P_UART3_RX, DRIVER_NAME);
-
-#ifdef CONFIG_BFIN_UART3_CTSRTS
-        peripheral_request(P_UART3_RTS, DRIVER_NAME);
-        peripheral_request(P_UART3_CTS, DRIVER_NAME);
-#endif
-#endif
-        SSYNC();
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_output(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf548/bfin_sir.h b/include/asm-blackfin/mach-bf548/bfin_sir.h
deleted file mode 100644
index c41f9cf00268..000000000000
--- a/include/asm-blackfin/mach-bf548/bfin_sir.h
+++ /dev/null
@@ -1,166 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER_SET)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_LSR(port)    bfin_read16((port)->membase + OFFSET_LSR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_SET_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER_SET), v)
-#define SIR_UART_CLEAR_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER_CLEAR), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LSR(port, v)  bfin_write16(((port)->membase + OFFSET_LSR), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_CLEAR_LSR(port)  bfin_write16(((port)->membase + OFFSET_LSR), -1)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART0_RX,
-        CH_UART0_RX,
-        CH_UART0_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR1
-        {
-        0xFFC02000,
-        IRQ_UART1_RX,
-        CH_UART1_RX,
-        CH_UART1_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR2
-        {
-        0xFFC02100,
-        IRQ_UART2_RX,
-        CH_UART2_RX,
-        CH_UART2_TX,
-        },
-#endif
-#ifdef CONFIG_BFIN_SIR3
-        {
-        0xFFC03100,
-        IRQ_UART3_RX,
-        CH_UART3_RX,
-        CH_UART3_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR1
-        ret = peripheral_request(P_UART1_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART1_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR2
-        ret = peripheral_request(P_UART2_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART2_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-
-#ifdef CONFIG_BFIN_SIR3
-        ret = peripheral_request(P_UART3_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART3_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf548/blackfin.h b/include/asm-blackfin/mach-bf548/blackfin.h
deleted file mode 100644
index d6ee74ac0460..000000000000
--- a/include/asm-blackfin/mach-bf548/blackfin.h
+++ /dev/null
@@ -1,190 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF548_FAMILY
-
-#include "bf548.h"
-#include "mem_map.h"
-#include "anomaly.h"
-
-#ifdef CONFIG_BF542
-#include "defBF542.h"
-#endif
-
-#ifdef CONFIG_BF544
-#include "defBF544.h"
-#endif
-
-#ifdef CONFIG_BF547
-#include "defBF547.h"
-#endif
-
-#ifdef CONFIG_BF548
-#include "defBF548.h"
-#endif
-
-#ifdef CONFIG_BF549
-#include "defBF549.h"
-#endif
-
-#if !defined(__ASSEMBLY__)
-#ifdef CONFIG_BF542
-#include "cdefBF542.h"
-#endif
-#ifdef CONFIG_BF544
-#include "cdefBF544.h"
-#endif
-#ifdef CONFIG_BF547
-#include "cdefBF547.h"
-#endif
-#ifdef CONFIG_BF548
-#include "cdefBF548.h"
-#endif
-#ifdef CONFIG_BF549
-#include "cdefBF549.h"
-#endif
-
-/* UART 1*/
-#define bfin_read_UART_THR()            bfin_read_UART1_THR()
-#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
-#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
-#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
-#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
-#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
-#define bfin_read_UART_IER()            bfin_read_UART1_IER()
-#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
-#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
-#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
-#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
-#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
-#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
-#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
-#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
-#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
-#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
-#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
-#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
-#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
-#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
-#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-
-#endif
-
-/* MAP used DEFINES from BF533 to BF54x - so we don't need to change 
- * them in the driver, kernel, etc. */
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-
-/* UART 0*/
-
-/* DMA Channnel */
-#define bfin_read_CH_UART_RX()          bfin_read_CH_UART1_RX()
-#define bfin_write_CH_UART_RX(val)      bfin_write_CH_UART1_RX(val)
-#define bfin_read_CH_UART_TX()          bfin_read_CH_UART1_TX()
-#define bfin_write_CH_UART_TX(val)      bfin_write_CH_UART1_TX(val)
-#define CH_UART_RX                      CH_UART1_RX
-#define CH_UART_TX                      CH_UART1_TX
-
-/* System Interrupt Controller */
-#define bfin_read_IRQ_UART_RX()         bfin_read_IRQ_UART1_RX()
-#define bfin_write_IRQ_UART_RX(val)     bfin_write_IRQ_UART1_RX(val)
-#define bfin_read_IRQ_UART_TX()         bfin_read_IRQ_UART1_TX()
-#define bfin_write_IRQ_UART_TX(val)     bfin_write_IRQ_UART1_TX(val)
-#define bfin_read_IRQ_UART_ERROR()      bfin_read_IRQ_UART1_ERROR()
-#define bfin_write_IRQ_UART_ERROR(val)  bfin_write_IRQ_UART1_ERROR(val)
-#define IRQ_UART_RX                     IRQ_UART1_RX
-#define IRQ_UART_TX                     IRQ_UART1_TX
-#define IRQ_UART_ERROR                  IRQ_UART1_ERROR
-
-/* MMR Registers*/
-#define bfin_read_UART_THR()            bfin_read_UART1_THR()
-#define bfin_write_UART_THR(val)        bfin_write_UART1_THR(val)
-#define bfin_read_UART_RBR()            bfin_read_UART1_RBR()
-#define bfin_write_UART_RBR(val)        bfin_write_UART1_RBR(val)
-#define bfin_read_UART_DLL()            bfin_read_UART1_DLL()
-#define bfin_write_UART_DLL(val)        bfin_write_UART1_DLL(val)
-#define bfin_read_UART_IER()            bfin_read_UART1_IER()
-#define bfin_write_UART_IER(val)        bfin_write_UART1_IER(val)
-#define bfin_read_UART_DLH()            bfin_read_UART1_DLH()
-#define bfin_write_UART_DLH(val)        bfin_write_UART1_DLH(val)
-#define bfin_read_UART_IIR()            bfin_read_UART1_IIR()
-#define bfin_write_UART_IIR(val)        bfin_write_UART1_IIR(val)
-#define bfin_read_UART_LCR()            bfin_read_UART1_LCR()
-#define bfin_write_UART_LCR(val)        bfin_write_UART1_LCR(val)
-#define bfin_read_UART_MCR()            bfin_read_UART1_MCR()
-#define bfin_write_UART_MCR(val)        bfin_write_UART1_MCR(val)
-#define bfin_read_UART_LSR()            bfin_read_UART1_LSR()
-#define bfin_write_UART_LSR(val)        bfin_write_UART1_LSR(val)
-#define bfin_read_UART_SCR()            bfin_read_UART1_SCR()
-#define bfin_write_UART_SCR(val)        bfin_write_UART1_SCR(val)
-#define bfin_read_UART_GCTL()           bfin_read_UART1_GCTL()
-#define bfin_write_UART_GCTL(val)       bfin_write_UART1_GCTL(val)
-
-#define BFIN_UART_THR                   UART1_THR
-#define BFIN_UART_RBR                   UART1_RBR
-#define BFIN_UART_DLL                   UART1_DLL
-#define BFIN_UART_IER                   UART1_IER
-#define BFIN_UART_DLH                   UART1_DLH
-#define BFIN_UART_IIR                   UART1_IIR
-#define BFIN_UART_LCR                   UART1_LCR
-#define BFIN_UART_MCR                   UART1_MCR
-#define BFIN_UART_LSR                   UART1_LSR
-#define BFIN_UART_SCR                   UART1_SCR
-#define BFIN_UART_GCTL                  UART1_GCTL
-
-#define BFIN_UART_NR_PORTS      4
-
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_GCTL             0x08    /* Global Control Register              */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_IER_SET          0x20    /* Set Interrupt Enable Register        */
-#define OFFSET_IER_CLEAR        0x24    /* Clear Interrupt Enable Register      */
-#define OFFSET_THR              0x28    /* Transmit Holding register            */
-#define OFFSET_RBR              0x2C    /* Receive Buffer register              */
-
-/* PLL_DIV Masks */
-#define CCLK_DIV1 CSEL_DIV1     /* CCLK = VCO / 1 */
-#define CCLK_DIV2 CSEL_DIV2     /* CCLK = VCO / 2 */
-#define CCLK_DIV4 CSEL_DIV4     /* CCLK = VCO / 4 */
-#define CCLK_DIV8 CSEL_DIV8     /* CCLK = VCO / 8 */
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/cdefBF542.h b/include/asm-blackfin/mach-bf548/cdefBF542.h
deleted file mode 100644
index 60b9f77576f1..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF542.h
+++ /dev/null
@@ -1,590 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF542.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF542_H
-#define _CDEF_BF542_H
-
-/* include all Core registers and bit definitions */
-#include "defBF542.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()                    bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)                bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()               bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)           bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()                   bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)               bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()                 bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)             bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()                   bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)               bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()               bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)           bfin_write16(KPAD_SOFTEVAL, val)
-
-#endif /* _CDEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF544.h b/include/asm-blackfin/mach-bf548/cdefBF544.h
deleted file mode 100644
index ea9b4ab496f3..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF544.h
+++ /dev/null
@@ -1,945 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF544.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF544_H
-#define _CDEF_BF544_H
-
-/* include all Core registers and bit definitions */
-#include "defBF544.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()                bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)            bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)             bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()                bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)            bfin_write16(HOST_TIMEOUT, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF547.h b/include/asm-blackfin/mach-bf548/cdefBF547.h
deleted file mode 100644
index ba716277c00d..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF547.h
+++ /dev/null
@@ -1,832 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF547.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include all Core registers and bit definitions */
-#include "defBF548.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()       bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()      bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)  bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()       bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()        bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)    bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()       bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()      bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)  bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()       bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()        bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)    bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()      bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)  bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()     bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()      bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)  bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()       bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()       bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)   bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()      bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)  bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()       bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)   bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()         bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)     bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()         bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)     bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()      bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)  bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()       bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()           bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)       bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()           bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)       bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()         bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)     bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()         bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)     bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()      bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)  bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()       bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()         bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)     bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()         bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)     bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()        bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)    bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()        bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)    bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()        bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)    bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()        bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)    bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()        bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)    bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()        bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)    bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()        bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)    bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()        bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)    bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()        bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)    bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()        bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)    bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()        bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)    bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()        bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)    bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()        bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)    bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()        bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)    bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()        bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)    bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()         bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)     bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()          bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)      bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()        bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)    bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()       bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)   bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()      bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)  bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()     bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()      bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)  bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()     bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()          bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)      bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()           bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)       bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()           bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)       bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()          bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)      bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()           bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)       bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()           bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)       bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()           bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)       bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()           bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)       bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()           bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)       bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()       bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)   bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()     bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()           bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)       bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2  Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()            bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)        bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()           bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)       bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()           bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)       bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()          bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)      bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()         bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)     bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()          bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)      bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()       bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)   bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()      bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)  bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()          bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)      bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()      bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)  bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()         bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)     bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()        bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)    bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()        bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)    bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()        bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)    bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()        bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)    bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()        bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)    bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()        bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)    bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()        bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)    bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()        bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)    bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()        bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)    bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()           bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)       bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()         bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)     bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()         bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)     bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()         bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)     bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF548.h b/include/asm-blackfin/mach-bf548/cdefBF548.h
deleted file mode 100644
index ae971ebff6a0..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF548.h
+++ /dev/null
@@ -1,1577 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF548.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF548_H
-#define _CDEF_BF548_H
-
-/* include all Core registers and bit definitions */
-#include "defBF548.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()       bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)   bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()      bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)  bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()       bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)   bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()        bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)    bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()       bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)   bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()      bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)  bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()       bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)   bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()        bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)    bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()      bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)  bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()     bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val) bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()      bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)  bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()       bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)   bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()       bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)   bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()      bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)  bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()       bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)   bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()         bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)     bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()         bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)     bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()      bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)  bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()       bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)   bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()           bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)       bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()           bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)       bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()         bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)     bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()         bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)     bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()      bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)  bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()       bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)   bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()         bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)     bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()         bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)     bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()        bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)    bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()        bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)    bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()        bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)    bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()        bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)    bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()        bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)    bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()        bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)    bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()        bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)    bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()        bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)    bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()        bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)    bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()        bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)    bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()        bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)    bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()        bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)    bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()        bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)    bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()        bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)    bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()        bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)    bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()         bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)     bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()          bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)      bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()        bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)    bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()       bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)   bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()      bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)  bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()     bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val) bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()      bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)  bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()     bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val) bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()          bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)      bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()           bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)       bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()           bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)       bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()          bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)      bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()           bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)       bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()           bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)       bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()           bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)       bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()           bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)       bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()           bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)       bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()       bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)   bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()     bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val) bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()           bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)       bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2  Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)          bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()            bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)        bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()           bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)       bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()           bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)       bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()          bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)      bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()         bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)     bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()          bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)      bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()       bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)   bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()      bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)  bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()          bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)      bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()      bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)  bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()         bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)     bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()        bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)    bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()        bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)    bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()        bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)    bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()        bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)    bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()        bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)    bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()        bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)    bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()        bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)    bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()        bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)    bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()        bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)    bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()           bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)       bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()         bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)     bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()         bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)     bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()         bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)     bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)        bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF549.h b/include/asm-blackfin/mach-bf548/cdefBF549.h
deleted file mode 100644
index 92d07d961999..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF549.h
+++ /dev/null
@@ -1,1863 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf549/cdefBF549.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF549_H
-#define _CDEF_BF549_H
-
-/* include all Core registers and bit definitions */
-#include "defBF549.h"
-
-/* include core sbfin_read_()ecific register pointer definitions */
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* include cdefBF54x_base.h for the set of #defines that are common to all ADSP-BF54x bfin_read_()rocessors */
-#include "cdefBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define bfin_read_TIMER8_CONFIG()               bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)           bfin_write16(TIMER8_CONFIG, val)
-#define bfin_read_TIMER8_COUNTER()              bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)          bfin_write32(TIMER8_COUNTER, val)
-#define bfin_read_TIMER8_PERIOD()               bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)           bfin_write32(TIMER8_PERIOD, val)
-#define bfin_read_TIMER8_WIDTH()                bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)            bfin_write32(TIMER8_WIDTH, val)
-#define bfin_read_TIMER9_CONFIG()               bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)           bfin_write16(TIMER9_CONFIG, val)
-#define bfin_read_TIMER9_COUNTER()              bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)          bfin_write32(TIMER9_COUNTER, val)
-#define bfin_read_TIMER9_PERIOD()               bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)           bfin_write32(TIMER9_PERIOD, val)
-#define bfin_read_TIMER9_WIDTH()                bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)            bfin_write32(TIMER9_WIDTH, val)
-#define bfin_read_TIMER10_CONFIG()              bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)          bfin_write16(TIMER10_CONFIG, val)
-#define bfin_read_TIMER10_COUNTER()             bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)         bfin_write32(TIMER10_COUNTER, val)
-#define bfin_read_TIMER10_PERIOD()              bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)          bfin_write32(TIMER10_PERIOD, val)
-#define bfin_read_TIMER10_WIDTH()               bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)           bfin_write32(TIMER10_WIDTH, val)
-
-/* Timer Groubfin_read_() of 3 */
-
-#define bfin_read_TIMER_ENABLE1()               bfin_read16(TIMER_ENABLE1)
-#define bfin_write_TIMER_ENABLE1(val)           bfin_write16(TIMER_ENABLE1, val)
-#define bfin_read_TIMER_DISABLE1()              bfin_read16(TIMER_DISABLE1)
-#define bfin_write_TIMER_DISABLE1(val)          bfin_write16(TIMER_DISABLE1, val)
-#define bfin_read_TIMER_STATUS1()               bfin_read32(TIMER_STATUS1)
-#define bfin_write_TIMER_STATUS1(val)           bfin_write32(TIMER_STATUS1, val)
-
-/* SPORT0 Registers */
-
-#define bfin_read_SPORT0_TCR1()                 bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)             bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()                 bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)             bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()              bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)          bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()               bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)           bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_read_SPORT0_TX()                   bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)               bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()                   bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)               bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()                 bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)             bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()                 bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)             bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()              bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)          bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()               bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)           bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()                 bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)             bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()                 bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)             bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()                bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)            bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()                bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)            bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()                bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)            bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()                bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)            bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()                bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)            bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()                bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)            bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()                bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)            bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()                bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)            bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()                bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)            bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()                bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)            bfin_write32(SPORT0_MRCS3, val)
-
-/* EPPI0 Registers */
-
-#define bfin_read_EPPI0_STATUS()                bfin_read16(EPPI0_STATUS)
-#define bfin_write_EPPI0_STATUS(val)            bfin_write16(EPPI0_STATUS, val)
-#define bfin_read_EPPI0_HCOUNT()                bfin_read16(EPPI0_HCOUNT)
-#define bfin_write_EPPI0_HCOUNT(val)            bfin_write16(EPPI0_HCOUNT, val)
-#define bfin_read_EPPI0_HDELAY()                bfin_read16(EPPI0_HDELAY)
-#define bfin_write_EPPI0_HDELAY(val)            bfin_write16(EPPI0_HDELAY, val)
-#define bfin_read_EPPI0_VCOUNT()                bfin_read16(EPPI0_VCOUNT)
-#define bfin_write_EPPI0_VCOUNT(val)            bfin_write16(EPPI0_VCOUNT, val)
-#define bfin_read_EPPI0_VDELAY()                bfin_read16(EPPI0_VDELAY)
-#define bfin_write_EPPI0_VDELAY(val)            bfin_write16(EPPI0_VDELAY, val)
-#define bfin_read_EPPI0_FRAME()                 bfin_read16(EPPI0_FRAME)
-#define bfin_write_EPPI0_FRAME(val)             bfin_write16(EPPI0_FRAME, val)
-#define bfin_read_EPPI0_LINE()                  bfin_read16(EPPI0_LINE)
-#define bfin_write_EPPI0_LINE(val)              bfin_write16(EPPI0_LINE, val)
-#define bfin_read_EPPI0_CLKDIV()                bfin_read16(EPPI0_CLKDIV)
-#define bfin_write_EPPI0_CLKDIV(val)            bfin_write16(EPPI0_CLKDIV, val)
-#define bfin_read_EPPI0_CONTROL()               bfin_read32(EPPI0_CONTROL)
-#define bfin_write_EPPI0_CONTROL(val)           bfin_write32(EPPI0_CONTROL, val)
-#define bfin_read_EPPI0_FS1W_HBL()              bfin_read32(EPPI0_FS1W_HBL)
-#define bfin_write_EPPI0_FS1W_HBL(val)          bfin_write32(EPPI0_FS1W_HBL, val)
-#define bfin_read_EPPI0_FS1P_AVPL()             bfin_read32(EPPI0_FS1P_AVPL)
-#define bfin_write_EPPI0_FS1P_AVPL(val)         bfin_write32(EPPI0_FS1P_AVPL, val)
-#define bfin_read_EPPI0_FS2W_LVB()              bfin_read32(EPPI0_FS2W_LVB)
-#define bfin_write_EPPI0_FS2W_LVB(val)          bfin_write32(EPPI0_FS2W_LVB, val)
-#define bfin_read_EPPI0_FS2P_LAVF()             bfin_read32(EPPI0_FS2P_LAVF)
-#define bfin_write_EPPI0_FS2P_LAVF(val)         bfin_write32(EPPI0_FS2P_LAVF, val)
-#define bfin_read_EPPI0_CLIP()                  bfin_read32(EPPI0_CLIP)
-#define bfin_write_EPPI0_CLIP(val)              bfin_write32(EPPI0_CLIP, val)
-
-/* UART2 Registers */
-
-#define bfin_read_UART2_DLL()                   bfin_read16(UART2_DLL)
-#define bfin_write_UART2_DLL(val)               bfin_write16(UART2_DLL, val)
-#define bfin_read_UART2_DLH()                   bfin_read16(UART2_DLH)
-#define bfin_write_UART2_DLH(val)               bfin_write16(UART2_DLH, val)
-#define bfin_read_UART2_GCTL()                  bfin_read16(UART2_GCTL)
-#define bfin_write_UART2_GCTL(val)              bfin_write16(UART2_GCTL, val)
-#define bfin_read_UART2_LCR()                   bfin_read16(UART2_LCR)
-#define bfin_write_UART2_LCR(val)               bfin_write16(UART2_LCR, val)
-#define bfin_read_UART2_MCR()                   bfin_read16(UART2_MCR)
-#define bfin_write_UART2_MCR(val)               bfin_write16(UART2_MCR, val)
-#define bfin_read_UART2_LSR()                   bfin_read16(UART2_LSR)
-#define bfin_write_UART2_LSR(val)               bfin_write16(UART2_LSR, val)
-#define bfin_read_UART2_MSR()                   bfin_read16(UART2_MSR)
-#define bfin_write_UART2_MSR(val)               bfin_write16(UART2_MSR, val)
-#define bfin_read_UART2_SCR()                   bfin_read16(UART2_SCR)
-#define bfin_write_UART2_SCR(val)               bfin_write16(UART2_SCR, val)
-#define bfin_read_UART2_IER_SET()               bfin_read16(UART2_IER_SET)
-#define bfin_write_UART2_IER_SET(val)           bfin_write16(UART2_IER_SET, val)
-#define bfin_read_UART2_IER_CLEAR()             bfin_read16(UART2_IER_CLEAR)
-#define bfin_write_UART2_IER_CLEAR(val)         bfin_write16(UART2_IER_CLEAR, val)
-#define bfin_read_UART2_RBR()                   bfin_read16(UART2_RBR)
-#define bfin_write_UART2_RBR(val)               bfin_write16(UART2_RBR, val)
-
-/* Two Wire Interface Registers (TWI1) */
-
-/* SPI2 Registers */
-
-#define bfin_read_SPI2_CTL()            bfin_read16(SPI2_CTL)
-#define bfin_write_SPI2_CTL(val)        bfin_write16(SPI2_CTL, val)
-#define bfin_read_SPI2_FLG()            bfin_read16(SPI2_FLG)
-#define bfin_write_SPI2_FLG(val)        bfin_write16(SPI2_FLG, val)
-#define bfin_read_SPI2_STAT()           bfin_read16(SPI2_STAT)
-#define bfin_write_SPI2_STAT(val)       bfin_write16(SPI2_STAT, val)
-#define bfin_read_SPI2_TDBR()           bfin_read16(SPI2_TDBR)
-#define bfin_write_SPI2_TDBR(val)       bfin_write16(SPI2_TDBR, val)
-#define bfin_read_SPI2_RDBR()           bfin_read16(SPI2_RDBR)
-#define bfin_write_SPI2_RDBR(val)       bfin_write16(SPI2_RDBR, val)
-#define bfin_read_SPI2_BAUD()           bfin_read16(SPI2_BAUD)
-#define bfin_write_SPI2_BAUD(val)       bfin_write16(SPI2_BAUD, val)
-#define bfin_read_SPI2_SHADOW()         bfin_read16(SPI2_SHADOW)
-#define bfin_write_SPI2_SHADOW(val)     bfin_write16(SPI2_SHADOW, val)
-
-/* MXVR Registers */
-
-#define bfin_read_MXVR_CONFIG()                 bfin_read16(MXVR_CONFIG)
-#define bfin_write_MXVR_CONFIG(val)             bfin_write16(MXVR_CONFIG, val)
-#define bfin_read_MXVR_STATE_0()                bfin_read32(MXVR_STATE_0)
-#define bfin_write_MXVR_STATE_0(val)            bfin_write32(MXVR_STATE_0, val)
-#define bfin_read_MXVR_STATE_1()                bfin_read32(MXVR_STATE_1)
-#define bfin_write_MXVR_STATE_1(val)            bfin_write32(MXVR_STATE_1, val)
-#define bfin_read_MXVR_INT_STAT_0()             bfin_read32(MXVR_INT_STAT_0)
-#define bfin_write_MXVR_INT_STAT_0(val)         bfin_write32(MXVR_INT_STAT_0, val)
-#define bfin_read_MXVR_INT_STAT_1()             bfin_read32(MXVR_INT_STAT_1)
-#define bfin_write_MXVR_INT_STAT_1(val)         bfin_write32(MXVR_INT_STAT_1, val)
-#define bfin_read_MXVR_INT_EN_0()               bfin_read32(MXVR_INT_EN_0)
-#define bfin_write_MXVR_INT_EN_0(val)           bfin_write32(MXVR_INT_EN_0, val)
-#define bfin_read_MXVR_INT_EN_1()               bfin_read32(MXVR_INT_EN_1)
-#define bfin_write_MXVR_INT_EN_1(val)           bfin_write32(MXVR_INT_EN_1, val)
-#define bfin_read_MXVR_POSITION()               bfin_read16(MXVR_POSITION)
-#define bfin_write_MXVR_POSITION(val)           bfin_write16(MXVR_POSITION, val)
-#define bfin_read_MXVR_MAX_POSITION()           bfin_read16(MXVR_MAX_POSITION)
-#define bfin_write_MXVR_MAX_POSITION(val)       bfin_write16(MXVR_MAX_POSITION, val)
-#define bfin_read_MXVR_DELAY()                  bfin_read16(MXVR_DELAY)
-#define bfin_write_MXVR_DELAY(val)              bfin_write16(MXVR_DELAY, val)
-#define bfin_read_MXVR_MAX_DELAY()              bfin_read16(MXVR_MAX_DELAY)
-#define bfin_write_MXVR_MAX_DELAY(val)          bfin_write16(MXVR_MAX_DELAY, val)
-#define bfin_read_MXVR_LADDR()                  bfin_read32(MXVR_LADDR)
-#define bfin_write_MXVR_LADDR(val)              bfin_write32(MXVR_LADDR, val)
-#define bfin_read_MXVR_GADDR()                  bfin_read16(MXVR_GADDR)
-#define bfin_write_MXVR_GADDR(val)              bfin_write16(MXVR_GADDR, val)
-#define bfin_read_MXVR_AADDR()                  bfin_read32(MXVR_AADDR)
-#define bfin_write_MXVR_AADDR(val)              bfin_write32(MXVR_AADDR, val)
-
-/* MXVR Allocation Table Registers */
-
-#define bfin_read_MXVR_ALLOC_0()                bfin_read32(MXVR_ALLOC_0)
-#define bfin_write_MXVR_ALLOC_0(val)            bfin_write32(MXVR_ALLOC_0, val)
-#define bfin_read_MXVR_ALLOC_1()                bfin_read32(MXVR_ALLOC_1)
-#define bfin_write_MXVR_ALLOC_1(val)            bfin_write32(MXVR_ALLOC_1, val)
-#define bfin_read_MXVR_ALLOC_2()                bfin_read32(MXVR_ALLOC_2)
-#define bfin_write_MXVR_ALLOC_2(val)            bfin_write32(MXVR_ALLOC_2, val)
-#define bfin_read_MXVR_ALLOC_3()                bfin_read32(MXVR_ALLOC_3)
-#define bfin_write_MXVR_ALLOC_3(val)            bfin_write32(MXVR_ALLOC_3, val)
-#define bfin_read_MXVR_ALLOC_4()                bfin_read32(MXVR_ALLOC_4)
-#define bfin_write_MXVR_ALLOC_4(val)            bfin_write32(MXVR_ALLOC_4, val)
-#define bfin_read_MXVR_ALLOC_5()                bfin_read32(MXVR_ALLOC_5)
-#define bfin_write_MXVR_ALLOC_5(val)            bfin_write32(MXVR_ALLOC_5, val)
-#define bfin_read_MXVR_ALLOC_6()                bfin_read32(MXVR_ALLOC_6)
-#define bfin_write_MXVR_ALLOC_6(val)            bfin_write32(MXVR_ALLOC_6, val)
-#define bfin_read_MXVR_ALLOC_7()                bfin_read32(MXVR_ALLOC_7)
-#define bfin_write_MXVR_ALLOC_7(val)            bfin_write32(MXVR_ALLOC_7, val)
-#define bfin_read_MXVR_ALLOC_8()                bfin_read32(MXVR_ALLOC_8)
-#define bfin_write_MXVR_ALLOC_8(val)            bfin_write32(MXVR_ALLOC_8, val)
-#define bfin_read_MXVR_ALLOC_9()                bfin_read32(MXVR_ALLOC_9)
-#define bfin_write_MXVR_ALLOC_9(val)            bfin_write32(MXVR_ALLOC_9, val)
-#define bfin_read_MXVR_ALLOC_10()               bfin_read32(MXVR_ALLOC_10)
-#define bfin_write_MXVR_ALLOC_10(val)           bfin_write32(MXVR_ALLOC_10, val)
-#define bfin_read_MXVR_ALLOC_11()               bfin_read32(MXVR_ALLOC_11)
-#define bfin_write_MXVR_ALLOC_11(val)           bfin_write32(MXVR_ALLOC_11, val)
-#define bfin_read_MXVR_ALLOC_12()               bfin_read32(MXVR_ALLOC_12)
-#define bfin_write_MXVR_ALLOC_12(val)           bfin_write32(MXVR_ALLOC_12, val)
-#define bfin_read_MXVR_ALLOC_13()               bfin_read32(MXVR_ALLOC_13)
-#define bfin_write_MXVR_ALLOC_13(val)           bfin_write32(MXVR_ALLOC_13, val)
-#define bfin_read_MXVR_ALLOC_14()               bfin_read32(MXVR_ALLOC_14)
-#define bfin_write_MXVR_ALLOC_14(val)           bfin_write32(MXVR_ALLOC_14, val)
-
-/* MXVR Channel Assign Registers */
-
-#define bfin_read_MXVR_SYNC_LCHAN_0()           bfin_read32(MXVR_SYNC_LCHAN_0)
-#define bfin_write_MXVR_SYNC_LCHAN_0(val)       bfin_write32(MXVR_SYNC_LCHAN_0, val)
-#define bfin_read_MXVR_SYNC_LCHAN_1()           bfin_read32(MXVR_SYNC_LCHAN_1)
-#define bfin_write_MXVR_SYNC_LCHAN_1(val)       bfin_write32(MXVR_SYNC_LCHAN_1, val)
-#define bfin_read_MXVR_SYNC_LCHAN_2()           bfin_read32(MXVR_SYNC_LCHAN_2)
-#define bfin_write_MXVR_SYNC_LCHAN_2(val)       bfin_write32(MXVR_SYNC_LCHAN_2, val)
-#define bfin_read_MXVR_SYNC_LCHAN_3()           bfin_read32(MXVR_SYNC_LCHAN_3)
-#define bfin_write_MXVR_SYNC_LCHAN_3(val)       bfin_write32(MXVR_SYNC_LCHAN_3, val)
-#define bfin_read_MXVR_SYNC_LCHAN_4()           bfin_read32(MXVR_SYNC_LCHAN_4)
-#define bfin_write_MXVR_SYNC_LCHAN_4(val)       bfin_write32(MXVR_SYNC_LCHAN_4, val)
-#define bfin_read_MXVR_SYNC_LCHAN_5()           bfin_read32(MXVR_SYNC_LCHAN_5)
-#define bfin_write_MXVR_SYNC_LCHAN_5(val)       bfin_write32(MXVR_SYNC_LCHAN_5, val)
-#define bfin_read_MXVR_SYNC_LCHAN_6()           bfin_read32(MXVR_SYNC_LCHAN_6)
-#define bfin_write_MXVR_SYNC_LCHAN_6(val)       bfin_write32(MXVR_SYNC_LCHAN_6, val)
-#define bfin_read_MXVR_SYNC_LCHAN_7()           bfin_read32(MXVR_SYNC_LCHAN_7)
-#define bfin_write_MXVR_SYNC_LCHAN_7(val)       bfin_write32(MXVR_SYNC_LCHAN_7, val)
-
-/* MXVR DMA0 Registers */
-
-#define bfin_read_MXVR_DMA0_CONFIG()            bfin_read32(MXVR_DMA0_CONFIG)
-#define bfin_write_MXVR_DMA0_CONFIG(val)        bfin_write32(MXVR_DMA0_CONFIG, val)
-#define bfin_read_MXVR_DMA0_START_ADDR()        bfin_read32(MXVR_DMA0_START_ADDR)
-#define bfin_write_MXVR_DMA0_START_ADDR(val)    bfin_write32(MXVR_DMA0_START_ADDR)
-#define bfin_read_MXVR_DMA0_COUNT()             bfin_read16(MXVR_DMA0_COUNT)
-#define bfin_write_MXVR_DMA0_COUNT(val)         bfin_write16(MXVR_DMA0_COUNT, val)
-#define bfin_read_MXVR_DMA0_CURR_ADDR()         bfin_read32(MXVR_DMA0_CURR_ADDR)
-#define bfin_write_MXVR_DMA0_CURR_ADDR(val)     bfin_write32(MXVR_DMA0_CURR_ADDR)
-#define bfin_read_MXVR_DMA0_CURR_COUNT()        bfin_read16(MXVR_DMA0_CURR_COUNT)
-#define bfin_write_MXVR_DMA0_CURR_COUNT(val)    bfin_write16(MXVR_DMA0_CURR_COUNT, val)
-
-/* MXVR DMA1 Registers */
-
-#define bfin_read_MXVR_DMA1_CONFIG()            bfin_read32(MXVR_DMA1_CONFIG)
-#define bfin_write_MXVR_DMA1_CONFIG(val)        bfin_write32(MXVR_DMA1_CONFIG, val)
-#define bfin_read_MXVR_DMA1_START_ADDR()        bfin_read32(MXVR_DMA1_START_ADDR)
-#define bfin_write_MXVR_DMA1_START_ADDR(val)    bfin_write32(MXVR_DMA1_START_ADDR)
-#define bfin_read_MXVR_DMA1_COUNT()             bfin_read16(MXVR_DMA1_COUNT)
-#define bfin_write_MXVR_DMA1_COUNT(val)         bfin_write16(MXVR_DMA1_COUNT, val)
-#define bfin_read_MXVR_DMA1_CURR_ADDR()         bfin_read32(MXVR_DMA1_CURR_ADDR)
-#define bfin_write_MXVR_DMA1_CURR_ADDR(val)     bfin_write32(MXVR_DMA1_CURR_ADDR)
-#define bfin_read_MXVR_DMA1_CURR_COUNT()        bfin_read16(MXVR_DMA1_CURR_COUNT)
-#define bfin_write_MXVR_DMA1_CURR_COUNT(val)    bfin_write16(MXVR_DMA1_CURR_COUNT, val)
-
-/* MXVR DMA2 Registers */
-
-#define bfin_read_MXVR_DMA2_CONFIG()            bfin_read32(MXVR_DMA2_CONFIG)
-#define bfin_write_MXVR_DMA2_CONFIG(val)        bfin_write32(MXVR_DMA2_CONFIG, val)
-#define bfin_read_MXVR_DMA2_START_ADDR()        bfin_read32(MXVR_DMA2_START_ADDR)
-#define bfin_write_MXVR_DMA2_START_ADDR(val)    bfin_write32(MXVR_DMA2_START_ADDR)
-#define bfin_read_MXVR_DMA2_COUNT()             bfin_read16(MXVR_DMA2_COUNT)
-#define bfin_write_MXVR_DMA2_COUNT(val)         bfin_write16(MXVR_DMA2_COUNT, val)
-#define bfin_read_MXVR_DMA2_CURR_ADDR()         bfin_read32(MXVR_DMA2_CURR_ADDR)
-#define bfin_write_MXVR_DMA2_CURR_ADDR(val)     bfin_write32(MXVR_DMA2_CURR_ADDR)
-#define bfin_read_MXVR_DMA2_CURR_COUNT()        bfin_read16(MXVR_DMA2_CURR_COUNT)
-#define bfin_write_MXVR_DMA2_CURR_COUNT(val)    bfin_write16(MXVR_DMA2_CURR_COUNT, val)
-
-/* MXVR DMA3 Registers */
-
-#define bfin_read_MXVR_DMA3_CONFIG()            bfin_read32(MXVR_DMA3_CONFIG)
-#define bfin_write_MXVR_DMA3_CONFIG(val)        bfin_write32(MXVR_DMA3_CONFIG, val)
-#define bfin_read_MXVR_DMA3_START_ADDR()        bfin_read32(MXVR_DMA3_START_ADDR)
-#define bfin_write_MXVR_DMA3_START_ADDR(val)    bfin_write32(MXVR_DMA3_START_ADDR)
-#define bfin_read_MXVR_DMA3_COUNT()             bfin_read16(MXVR_DMA3_COUNT)
-#define bfin_write_MXVR_DMA3_COUNT(val)         bfin_write16(MXVR_DMA3_COUNT, val)
-#define bfin_read_MXVR_DMA3_CURR_ADDR()         bfin_read32(MXVR_DMA3_CURR_ADDR)
-#define bfin_write_MXVR_DMA3_CURR_ADDR(val)     bfin_write32(MXVR_DMA3_CURR_ADDR)
-#define bfin_read_MXVR_DMA3_CURR_COUNT()        bfin_read16(MXVR_DMA3_CURR_COUNT)
-#define bfin_write_MXVR_DMA3_CURR_COUNT(val)    bfin_write16(MXVR_DMA3_CURR_COUNT, val)
-
-/* MXVR DMA4 Registers */
-
-#define bfin_read_MXVR_DMA4_CONFIG()            bfin_read32(MXVR_DMA4_CONFIG)
-#define bfin_write_MXVR_DMA4_CONFIG(val)        bfin_write32(MXVR_DMA4_CONFIG, val)
-#define bfin_read_MXVR_DMA4_START_ADDR()        bfin_read32(MXVR_DMA4_START_ADDR)
-#define bfin_write_MXVR_DMA4_START_ADDR(val)    bfin_write32(MXVR_DMA4_START_ADDR)
-#define bfin_read_MXVR_DMA4_COUNT()             bfin_read16(MXVR_DMA4_COUNT)
-#define bfin_write_MXVR_DMA4_COUNT(val)         bfin_write16(MXVR_DMA4_COUNT, val)
-#define bfin_read_MXVR_DMA4_CURR_ADDR()         bfin_read32(MXVR_DMA4_CURR_ADDR)
-#define bfin_write_MXVR_DMA4_CURR_ADDR(val)     bfin_write32(MXVR_DMA4_CURR_ADDR)
-#define bfin_read_MXVR_DMA4_CURR_COUNT()        bfin_read16(MXVR_DMA4_CURR_COUNT)
-#define bfin_write_MXVR_DMA4_CURR_COUNT(val)    bfin_write16(MXVR_DMA4_CURR_COUNT, val)
-
-/* MXVR DMA5 Registers */
-
-#define bfin_read_MXVR_DMA5_CONFIG()            bfin_read32(MXVR_DMA5_CONFIG)
-#define bfin_write_MXVR_DMA5_CONFIG(val)        bfin_write32(MXVR_DMA5_CONFIG, val)
-#define bfin_read_MXVR_DMA5_START_ADDR()        bfin_read32(MXVR_DMA5_START_ADDR)
-#define bfin_write_MXVR_DMA5_START_ADDR(val)    bfin_write32(MXVR_DMA5_START_ADDR)
-#define bfin_read_MXVR_DMA5_COUNT()             bfin_read16(MXVR_DMA5_COUNT)
-#define bfin_write_MXVR_DMA5_COUNT(val)         bfin_write16(MXVR_DMA5_COUNT, val)
-#define bfin_read_MXVR_DMA5_CURR_ADDR()         bfin_read32(MXVR_DMA5_CURR_ADDR)
-#define bfin_write_MXVR_DMA5_CURR_ADDR(val)     bfin_write32(MXVR_DMA5_CURR_ADDR)
-#define bfin_read_MXVR_DMA5_CURR_COUNT()        bfin_read16(MXVR_DMA5_CURR_COUNT)
-#define bfin_write_MXVR_DMA5_CURR_COUNT(val)    bfin_write16(MXVR_DMA5_CURR_COUNT, val)
-
-/* MXVR DMA6 Registers */
-
-#define bfin_read_MXVR_DMA6_CONFIG()            bfin_read32(MXVR_DMA6_CONFIG)
-#define bfin_write_MXVR_DMA6_CONFIG(val)        bfin_write32(MXVR_DMA6_CONFIG, val)
-#define bfin_read_MXVR_DMA6_START_ADDR()        bfin_read32(MXVR_DMA6_START_ADDR)
-#define bfin_write_MXVR_DMA6_START_ADDR(val)    bfin_write32(MXVR_DMA6_START_ADDR)
-#define bfin_read_MXVR_DMA6_COUNT()             bfin_read16(MXVR_DMA6_COUNT)
-#define bfin_write_MXVR_DMA6_COUNT(val)         bfin_write16(MXVR_DMA6_COUNT, val)
-#define bfin_read_MXVR_DMA6_CURR_ADDR()         bfin_read32(MXVR_DMA6_CURR_ADDR)
-#define bfin_write_MXVR_DMA6_CURR_ADDR(val)     bfin_write32(MXVR_DMA6_CURR_ADDR)
-#define bfin_read_MXVR_DMA6_CURR_COUNT()        bfin_read16(MXVR_DMA6_CURR_COUNT)
-#define bfin_write_MXVR_DMA6_CURR_COUNT(val)    bfin_write16(MXVR_DMA6_CURR_COUNT, val)
-
-/* MXVR DMA7 Registers */
-
-#define bfin_read_MXVR_DMA7_CONFIG()            bfin_read32(MXVR_DMA7_CONFIG)
-#define bfin_write_MXVR_DMA7_CONFIG(val)        bfin_write32(MXVR_DMA7_CONFIG, val)
-#define bfin_read_MXVR_DMA7_START_ADDR()        bfin_read32(MXVR_DMA7_START_ADDR)
-#define bfin_write_MXVR_DMA7_START_ADDR(val)    bfin_write32(MXVR_DMA7_START_ADDR)
-#define bfin_read_MXVR_DMA7_COUNT()             bfin_read16(MXVR_DMA7_COUNT)
-#define bfin_write_MXVR_DMA7_COUNT(val)         bfin_write16(MXVR_DMA7_COUNT, val)
-#define bfin_read_MXVR_DMA7_CURR_ADDR()         bfin_read32(MXVR_DMA7_CURR_ADDR)
-#define bfin_write_MXVR_DMA7_CURR_ADDR(val)     bfin_write32(MXVR_DMA7_CURR_ADDR)
-#define bfin_read_MXVR_DMA7_CURR_COUNT()        bfin_read16(MXVR_DMA7_CURR_COUNT)
-#define bfin_write_MXVR_DMA7_CURR_COUNT(val)    bfin_write16(MXVR_DMA7_CURR_COUNT, val)
-
-/* MXVR Asynch Packet Registers */
-
-#define bfin_read_MXVR_AP_CTL()                 bfin_read16(MXVR_AP_CTL)
-#define bfin_write_MXVR_AP_CTL(val)             bfin_write16(MXVR_AP_CTL, val)
-#define bfin_read_MXVR_APRB_START_ADDR()        bfin_read32(MXVR_APRB_START_ADDR)
-#define bfin_write_MXVR_APRB_START_ADDR(val)    bfin_write32(MXVR_APRB_START_ADDR)
-#define bfin_read_MXVR_APRB_CURR_ADDR()         bfin_read32(MXVR_APRB_CURR_ADDR)
-#define bfin_write_MXVR_APRB_CURR_ADDR(val)     bfin_write32(MXVR_APRB_CURR_ADDR)
-#define bfin_read_MXVR_APTB_START_ADDR()        bfin_read32(MXVR_APTB_START_ADDR)
-#define bfin_write_MXVR_APTB_START_ADDR(val)    bfin_write32(MXVR_APTB_START_ADDR)
-#define bfin_read_MXVR_APTB_CURR_ADDR()         bfin_read32(MXVR_APTB_CURR_ADDR)
-#define bfin_write_MXVR_APTB_CURR_ADDR(val)     bfin_write32(MXVR_APTB_CURR_ADDR)
-
-/* MXVR Control Message Registers */
-
-#define bfin_read_MXVR_CM_CTL()                 bfin_read32(MXVR_CM_CTL)
-#define bfin_write_MXVR_CM_CTL(val)             bfin_write32(MXVR_CM_CTL, val)
-#define bfin_read_MXVR_CMRB_START_ADDR()        bfin_read32(MXVR_CMRB_START_ADDR)
-#define bfin_write_MXVR_CMRB_START_ADDR(val)    bfin_write32(MXVR_CMRB_START_ADDR)
-#define bfin_read_MXVR_CMRB_CURR_ADDR()         bfin_read32(MXVR_CMRB_CURR_ADDR)
-#define bfin_write_MXVR_CMRB_CURR_ADDR(val)     bfin_write32(MXVR_CMRB_CURR_ADDR)
-#define bfin_read_MXVR_CMTB_START_ADDR()        bfin_read32(MXVR_CMTB_START_ADDR)
-#define bfin_write_MXVR_CMTB_START_ADDR(val)    bfin_write32(MXVR_CMTB_START_ADDR)
-#define bfin_read_MXVR_CMTB_CURR_ADDR()         bfin_read32(MXVR_CMTB_CURR_ADDR)
-#define bfin_write_MXVR_CMTB_CURR_ADDR(val)     bfin_write32(MXVR_CMTB_CURR_ADDR)
-
-/* MXVR Remote Read Registers */
-
-#define bfin_read_MXVR_RRDB_START_ADDR()        bfin_read32(MXVR_RRDB_START_ADDR)
-#define bfin_write_MXVR_RRDB_START_ADDR(val)    bfin_write32(MXVR_RRDB_START_ADDR)
-#define bfin_read_MXVR_RRDB_CURR_ADDR()         bfin_read32(MXVR_RRDB_CURR_ADDR)
-#define bfin_write_MXVR_RRDB_CURR_ADDR(val)     bfin_write32(MXVR_RRDB_CURR_ADDR)
-
-/* MXVR Pattern Data Registers */
-
-#define bfin_read_MXVR_PAT_DATA_0()             bfin_read32(MXVR_PAT_DATA_0)
-#define bfin_write_MXVR_PAT_DATA_0(val)         bfin_write32(MXVR_PAT_DATA_0, val)
-#define bfin_read_MXVR_PAT_EN_0()               bfin_read32(MXVR_PAT_EN_0)
-#define bfin_write_MXVR_PAT_EN_0(val)           bfin_write32(MXVR_PAT_EN_0, val)
-#define bfin_read_MXVR_PAT_DATA_1()             bfin_read32(MXVR_PAT_DATA_1)
-#define bfin_write_MXVR_PAT_DATA_1(val)         bfin_write32(MXVR_PAT_DATA_1, val)
-#define bfin_read_MXVR_PAT_EN_1()               bfin_read32(MXVR_PAT_EN_1)
-#define bfin_write_MXVR_PAT_EN_1(val)           bfin_write32(MXVR_PAT_EN_1, val)
-
-/* MXVR Frame Counter Registers */
-
-#define bfin_read_MXVR_FRAME_CNT_0()            bfin_read16(MXVR_FRAME_CNT_0)
-#define bfin_write_MXVR_FRAME_CNT_0(val)        bfin_write16(MXVR_FRAME_CNT_0, val)
-#define bfin_read_MXVR_FRAME_CNT_1()            bfin_read16(MXVR_FRAME_CNT_1)
-#define bfin_write_MXVR_FRAME_CNT_1(val)        bfin_write16(MXVR_FRAME_CNT_1, val)
-
-/* MXVR Routing Table Registers */
-
-#define bfin_read_MXVR_ROUTING_0()              bfin_read32(MXVR_ROUTING_0)
-#define bfin_write_MXVR_ROUTING_0(val)          bfin_write32(MXVR_ROUTING_0, val)
-#define bfin_read_MXVR_ROUTING_1()              bfin_read32(MXVR_ROUTING_1)
-#define bfin_write_MXVR_ROUTING_1(val)          bfin_write32(MXVR_ROUTING_1, val)
-#define bfin_read_MXVR_ROUTING_2()              bfin_read32(MXVR_ROUTING_2)
-#define bfin_write_MXVR_ROUTING_2(val)          bfin_write32(MXVR_ROUTING_2, val)
-#define bfin_read_MXVR_ROUTING_3()              bfin_read32(MXVR_ROUTING_3)
-#define bfin_write_MXVR_ROUTING_3(val)          bfin_write32(MXVR_ROUTING_3, val)
-#define bfin_read_MXVR_ROUTING_4()              bfin_read32(MXVR_ROUTING_4)
-#define bfin_write_MXVR_ROUTING_4(val)          bfin_write32(MXVR_ROUTING_4, val)
-#define bfin_read_MXVR_ROUTING_5()              bfin_read32(MXVR_ROUTING_5)
-#define bfin_write_MXVR_ROUTING_5(val)          bfin_write32(MXVR_ROUTING_5, val)
-#define bfin_read_MXVR_ROUTING_6()              bfin_read32(MXVR_ROUTING_6)
-#define bfin_write_MXVR_ROUTING_6(val)          bfin_write32(MXVR_ROUTING_6, val)
-#define bfin_read_MXVR_ROUTING_7()              bfin_read32(MXVR_ROUTING_7)
-#define bfin_write_MXVR_ROUTING_7(val)          bfin_write32(MXVR_ROUTING_7, val)
-#define bfin_read_MXVR_ROUTING_8()              bfin_read32(MXVR_ROUTING_8)
-#define bfin_write_MXVR_ROUTING_8(val)          bfin_write32(MXVR_ROUTING_8, val)
-#define bfin_read_MXVR_ROUTING_9()              bfin_read32(MXVR_ROUTING_9)
-#define bfin_write_MXVR_ROUTING_9(val)          bfin_write32(MXVR_ROUTING_9, val)
-#define bfin_read_MXVR_ROUTING_10()             bfin_read32(MXVR_ROUTING_10)
-#define bfin_write_MXVR_ROUTING_10(val)         bfin_write32(MXVR_ROUTING_10, val)
-#define bfin_read_MXVR_ROUTING_11()             bfin_read32(MXVR_ROUTING_11)
-#define bfin_write_MXVR_ROUTING_11(val)         bfin_write32(MXVR_ROUTING_11, val)
-#define bfin_read_MXVR_ROUTING_12()             bfin_read32(MXVR_ROUTING_12)
-#define bfin_write_MXVR_ROUTING_12(val)         bfin_write32(MXVR_ROUTING_12, val)
-#define bfin_read_MXVR_ROUTING_13()             bfin_read32(MXVR_ROUTING_13)
-#define bfin_write_MXVR_ROUTING_13(val)         bfin_write32(MXVR_ROUTING_13, val)
-#define bfin_read_MXVR_ROUTING_14()             bfin_read32(MXVR_ROUTING_14)
-#define bfin_write_MXVR_ROUTING_14(val)         bfin_write32(MXVR_ROUTING_14, val)
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define bfin_read_MXVR_BLOCK_CNT()              bfin_read16(MXVR_BLOCK_CNT)
-#define bfin_write_MXVR_BLOCK_CNT(val)          bfin_write16(MXVR_BLOCK_CNT, val)
-#define bfin_read_MXVR_CLK_CTL()                bfin_read32(MXVR_CLK_CTL)
-#define bfin_write_MXVR_CLK_CTL(val)            bfin_write32(MXVR_CLK_CTL, val)
-#define bfin_read_MXVR_CDRPLL_CTL()             bfin_read32(MXVR_CDRPLL_CTL)
-#define bfin_write_MXVR_CDRPLL_CTL(val)         bfin_write32(MXVR_CDRPLL_CTL, val)
-#define bfin_read_MXVR_FMPLL_CTL()              bfin_read32(MXVR_FMPLL_CTL)
-#define bfin_write_MXVR_FMPLL_CTL(val)          bfin_write32(MXVR_FMPLL_CTL, val)
-#define bfin_read_MXVR_PIN_CTL()                bfin_read16(MXVR_PIN_CTL)
-#define bfin_write_MXVR_PIN_CTL(val)            bfin_write16(MXVR_PIN_CTL, val)
-#define bfin_read_MXVR_SCLK_CNT()               bfin_read16(MXVR_SCLK_CNT)
-#define bfin_write_MXVR_SCLK_CNT(val)           bfin_write16(MXVR_SCLK_CNT, val)
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define bfin_read_CAN1_MC1()            bfin_read16(CAN1_MC1)
-#define bfin_write_CAN1_MC1(val)        bfin_write16(CAN1_MC1, val)
-#define bfin_read_CAN1_MD1()            bfin_read16(CAN1_MD1)
-#define bfin_write_CAN1_MD1(val)        bfin_write16(CAN1_MD1, val)
-#define bfin_read_CAN1_TRS1()           bfin_read16(CAN1_TRS1)
-#define bfin_write_CAN1_TRS1(val)       bfin_write16(CAN1_TRS1, val)
-#define bfin_read_CAN1_TRR1()           bfin_read16(CAN1_TRR1)
-#define bfin_write_CAN1_TRR1(val)       bfin_write16(CAN1_TRR1, val)
-#define bfin_read_CAN1_TA1()            bfin_read16(CAN1_TA1)
-#define bfin_write_CAN1_TA1(val)        bfin_write16(CAN1_TA1, val)
-#define bfin_read_CAN1_AA1()            bfin_read16(CAN1_AA1)
-#define bfin_write_CAN1_AA1(val)        bfin_write16(CAN1_AA1, val)
-#define bfin_read_CAN1_RMP1()           bfin_read16(CAN1_RMP1)
-#define bfin_write_CAN1_RMP1(val)       bfin_write16(CAN1_RMP1, val)
-#define bfin_read_CAN1_RML1()           bfin_read16(CAN1_RML1)
-#define bfin_write_CAN1_RML1(val)       bfin_write16(CAN1_RML1, val)
-#define bfin_read_CAN1_MBTIF1()         bfin_read16(CAN1_MBTIF1)
-#define bfin_write_CAN1_MBTIF1(val)     bfin_write16(CAN1_MBTIF1, val)
-#define bfin_read_CAN1_MBRIF1()         bfin_read16(CAN1_MBRIF1)
-#define bfin_write_CAN1_MBRIF1(val)     bfin_write16(CAN1_MBRIF1, val)
-#define bfin_read_CAN1_MBIM1()          bfin_read16(CAN1_MBIM1)
-#define bfin_write_CAN1_MBIM1(val)      bfin_write16(CAN1_MBIM1, val)
-#define bfin_read_CAN1_RFH1()           bfin_read16(CAN1_RFH1)
-#define bfin_write_CAN1_RFH1(val)       bfin_write16(CAN1_RFH1, val)
-#define bfin_read_CAN1_OPSS1()          bfin_read16(CAN1_OPSS1)
-#define bfin_write_CAN1_OPSS1(val)      bfin_write16(CAN1_OPSS1, val)
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define bfin_read_CAN1_MC2()            bfin_read16(CAN1_MC2)
-#define bfin_write_CAN1_MC2(val)        bfin_write16(CAN1_MC2, val)
-#define bfin_read_CAN1_MD2()            bfin_read16(CAN1_MD2)
-#define bfin_write_CAN1_MD2(val)        bfin_write16(CAN1_MD2, val)
-#define bfin_read_CAN1_TRS2()           bfin_read16(CAN1_TRS2)
-#define bfin_write_CAN1_TRS2(val)       bfin_write16(CAN1_TRS2, val)
-#define bfin_read_CAN1_TRR2()           bfin_read16(CAN1_TRR2)
-#define bfin_write_CAN1_TRR2(val)       bfin_write16(CAN1_TRR2, val)
-#define bfin_read_CAN1_TA2()            bfin_read16(CAN1_TA2)
-#define bfin_write_CAN1_TA2(val)        bfin_write16(CAN1_TA2, val)
-#define bfin_read_CAN1_AA2()            bfin_read16(CAN1_AA2)
-#define bfin_write_CAN1_AA2(val)        bfin_write16(CAN1_AA2, val)
-#define bfin_read_CAN1_RMP2()           bfin_read16(CAN1_RMP2)
-#define bfin_write_CAN1_RMP2(val)       bfin_write16(CAN1_RMP2, val)
-#define bfin_read_CAN1_RML2()           bfin_read16(CAN1_RML2)
-#define bfin_write_CAN1_RML2(val)       bfin_write16(CAN1_RML2, val)
-#define bfin_read_CAN1_MBTIF2()         bfin_read16(CAN1_MBTIF2)
-#define bfin_write_CAN1_MBTIF2(val)     bfin_write16(CAN1_MBTIF2, val)
-#define bfin_read_CAN1_MBRIF2()         bfin_read16(CAN1_MBRIF2)
-#define bfin_write_CAN1_MBRIF2(val)     bfin_write16(CAN1_MBRIF2, val)
-#define bfin_read_CAN1_MBIM2()          bfin_read16(CAN1_MBIM2)
-#define bfin_write_CAN1_MBIM2(val)      bfin_write16(CAN1_MBIM2, val)
-#define bfin_read_CAN1_RFH2()           bfin_read16(CAN1_RFH2)
-#define bfin_write_CAN1_RFH2(val)       bfin_write16(CAN1_RFH2, val)
-#define bfin_read_CAN1_OPSS2()          bfin_read16(CAN1_OPSS2)
-#define bfin_write_CAN1_OPSS2(val)      bfin_write16(CAN1_OPSS2, val)
-
-/* CAN Controller 1 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN1_CLOCK()          bfin_read16(CAN1_CLOCK)
-#define bfin_write_CAN1_CLOCK(val)      bfin_write16(CAN1_CLOCK, val)
-#define bfin_read_CAN1_TIMING()         bfin_read16(CAN1_TIMING)
-#define bfin_write_CAN1_TIMING(val)     bfin_write16(CAN1_TIMING, val)
-#define bfin_read_CAN1_DEBUG()          bfin_read16(CAN1_DEBUG)
-#define bfin_write_CAN1_DEBUG(val)      bfin_write16(CAN1_DEBUG, val)
-#define bfin_read_CAN1_STATUS()         bfin_read16(CAN1_STATUS)
-#define bfin_write_CAN1_STATUS(val)     bfin_write16(CAN1_STATUS, val)
-#define bfin_read_CAN1_CEC()            bfin_read16(CAN1_CEC)
-#define bfin_write_CAN1_CEC(val)        bfin_write16(CAN1_CEC, val)
-#define bfin_read_CAN1_GIS()            bfin_read16(CAN1_GIS)
-#define bfin_write_CAN1_GIS(val)        bfin_write16(CAN1_GIS, val)
-#define bfin_read_CAN1_GIM()            bfin_read16(CAN1_GIM)
-#define bfin_write_CAN1_GIM(val)        bfin_write16(CAN1_GIM, val)
-#define bfin_read_CAN1_GIF()            bfin_read16(CAN1_GIF)
-#define bfin_write_CAN1_GIF(val)        bfin_write16(CAN1_GIF, val)
-#define bfin_read_CAN1_CONTROL()        bfin_read16(CAN1_CONTROL)
-#define bfin_write_CAN1_CONTROL(val)    bfin_write16(CAN1_CONTROL, val)
-#define bfin_read_CAN1_INTR()           bfin_read16(CAN1_INTR)
-#define bfin_write_CAN1_INTR(val)       bfin_write16(CAN1_INTR, val)
-#define bfin_read_CAN1_MBTD()           bfin_read16(CAN1_MBTD)
-#define bfin_write_CAN1_MBTD(val)       bfin_write16(CAN1_MBTD, val)
-#define bfin_read_CAN1_EWR()            bfin_read16(CAN1_EWR)
-#define bfin_write_CAN1_EWR(val)        bfin_write16(CAN1_EWR, val)
-#define bfin_read_CAN1_ESR()            bfin_read16(CAN1_ESR)
-#define bfin_write_CAN1_ESR(val)        bfin_write16(CAN1_ESR, val)
-#define bfin_read_CAN1_UCCNT()          bfin_read16(CAN1_UCCNT)
-#define bfin_write_CAN1_UCCNT(val)      bfin_write16(CAN1_UCCNT, val)
-#define bfin_read_CAN1_UCRC()           bfin_read16(CAN1_UCRC)
-#define bfin_write_CAN1_UCRC(val)       bfin_write16(CAN1_UCRC, val)
-#define bfin_read_CAN1_UCCNF()          bfin_read16(CAN1_UCCNF)
-#define bfin_write_CAN1_UCCNF(val)      bfin_write16(CAN1_UCCNF, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM00L()          bfin_read16(CAN1_AM00L)
-#define bfin_write_CAN1_AM00L(val)      bfin_write16(CAN1_AM00L, val)
-#define bfin_read_CAN1_AM00H()          bfin_read16(CAN1_AM00H)
-#define bfin_write_CAN1_AM00H(val)      bfin_write16(CAN1_AM00H, val)
-#define bfin_read_CAN1_AM01L()          bfin_read16(CAN1_AM01L)
-#define bfin_write_CAN1_AM01L(val)      bfin_write16(CAN1_AM01L, val)
-#define bfin_read_CAN1_AM01H()          bfin_read16(CAN1_AM01H)
-#define bfin_write_CAN1_AM01H(val)      bfin_write16(CAN1_AM01H, val)
-#define bfin_read_CAN1_AM02L()          bfin_read16(CAN1_AM02L)
-#define bfin_write_CAN1_AM02L(val)      bfin_write16(CAN1_AM02L, val)
-#define bfin_read_CAN1_AM02H()          bfin_read16(CAN1_AM02H)
-#define bfin_write_CAN1_AM02H(val)      bfin_write16(CAN1_AM02H, val)
-#define bfin_read_CAN1_AM03L()          bfin_read16(CAN1_AM03L)
-#define bfin_write_CAN1_AM03L(val)      bfin_write16(CAN1_AM03L, val)
-#define bfin_read_CAN1_AM03H()          bfin_read16(CAN1_AM03H)
-#define bfin_write_CAN1_AM03H(val)      bfin_write16(CAN1_AM03H, val)
-#define bfin_read_CAN1_AM04L()          bfin_read16(CAN1_AM04L)
-#define bfin_write_CAN1_AM04L(val)      bfin_write16(CAN1_AM04L, val)
-#define bfin_read_CAN1_AM04H()          bfin_read16(CAN1_AM04H)
-#define bfin_write_CAN1_AM04H(val)      bfin_write16(CAN1_AM04H, val)
-#define bfin_read_CAN1_AM05L()          bfin_read16(CAN1_AM05L)
-#define bfin_write_CAN1_AM05L(val)      bfin_write16(CAN1_AM05L, val)
-#define bfin_read_CAN1_AM05H()          bfin_read16(CAN1_AM05H)
-#define bfin_write_CAN1_AM05H(val)      bfin_write16(CAN1_AM05H, val)
-#define bfin_read_CAN1_AM06L()          bfin_read16(CAN1_AM06L)
-#define bfin_write_CAN1_AM06L(val)      bfin_write16(CAN1_AM06L, val)
-#define bfin_read_CAN1_AM06H()          bfin_read16(CAN1_AM06H)
-#define bfin_write_CAN1_AM06H(val)      bfin_write16(CAN1_AM06H, val)
-#define bfin_read_CAN1_AM07L()          bfin_read16(CAN1_AM07L)
-#define bfin_write_CAN1_AM07L(val)      bfin_write16(CAN1_AM07L, val)
-#define bfin_read_CAN1_AM07H()          bfin_read16(CAN1_AM07H)
-#define bfin_write_CAN1_AM07H(val)      bfin_write16(CAN1_AM07H, val)
-#define bfin_read_CAN1_AM08L()          bfin_read16(CAN1_AM08L)
-#define bfin_write_CAN1_AM08L(val)      bfin_write16(CAN1_AM08L, val)
-#define bfin_read_CAN1_AM08H()          bfin_read16(CAN1_AM08H)
-#define bfin_write_CAN1_AM08H(val)      bfin_write16(CAN1_AM08H, val)
-#define bfin_read_CAN1_AM09L()          bfin_read16(CAN1_AM09L)
-#define bfin_write_CAN1_AM09L(val)      bfin_write16(CAN1_AM09L, val)
-#define bfin_read_CAN1_AM09H()          bfin_read16(CAN1_AM09H)
-#define bfin_write_CAN1_AM09H(val)      bfin_write16(CAN1_AM09H, val)
-#define bfin_read_CAN1_AM10L()          bfin_read16(CAN1_AM10L)
-#define bfin_write_CAN1_AM10L(val)      bfin_write16(CAN1_AM10L, val)
-#define bfin_read_CAN1_AM10H()          bfin_read16(CAN1_AM10H)
-#define bfin_write_CAN1_AM10H(val)      bfin_write16(CAN1_AM10H, val)
-#define bfin_read_CAN1_AM11L()          bfin_read16(CAN1_AM11L)
-#define bfin_write_CAN1_AM11L(val)      bfin_write16(CAN1_AM11L, val)
-#define bfin_read_CAN1_AM11H()          bfin_read16(CAN1_AM11H)
-#define bfin_write_CAN1_AM11H(val)      bfin_write16(CAN1_AM11H, val)
-#define bfin_read_CAN1_AM12L()          bfin_read16(CAN1_AM12L)
-#define bfin_write_CAN1_AM12L(val)      bfin_write16(CAN1_AM12L, val)
-#define bfin_read_CAN1_AM12H()          bfin_read16(CAN1_AM12H)
-#define bfin_write_CAN1_AM12H(val)      bfin_write16(CAN1_AM12H, val)
-#define bfin_read_CAN1_AM13L()          bfin_read16(CAN1_AM13L)
-#define bfin_write_CAN1_AM13L(val)      bfin_write16(CAN1_AM13L, val)
-#define bfin_read_CAN1_AM13H()          bfin_read16(CAN1_AM13H)
-#define bfin_write_CAN1_AM13H(val)      bfin_write16(CAN1_AM13H, val)
-#define bfin_read_CAN1_AM14L()          bfin_read16(CAN1_AM14L)
-#define bfin_write_CAN1_AM14L(val)      bfin_write16(CAN1_AM14L, val)
-#define bfin_read_CAN1_AM14H()          bfin_read16(CAN1_AM14H)
-#define bfin_write_CAN1_AM14H(val)      bfin_write16(CAN1_AM14H, val)
-#define bfin_read_CAN1_AM15L()          bfin_read16(CAN1_AM15L)
-#define bfin_write_CAN1_AM15L(val)      bfin_write16(CAN1_AM15L, val)
-#define bfin_read_CAN1_AM15H()          bfin_read16(CAN1_AM15H)
-#define bfin_write_CAN1_AM15H(val)      bfin_write16(CAN1_AM15H, val)
-
-/* CAN Controller 1 Mailbox Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN1_AM16L()          bfin_read16(CAN1_AM16L)
-#define bfin_write_CAN1_AM16L(val)      bfin_write16(CAN1_AM16L, val)
-#define bfin_read_CAN1_AM16H()          bfin_read16(CAN1_AM16H)
-#define bfin_write_CAN1_AM16H(val)      bfin_write16(CAN1_AM16H, val)
-#define bfin_read_CAN1_AM17L()          bfin_read16(CAN1_AM17L)
-#define bfin_write_CAN1_AM17L(val)      bfin_write16(CAN1_AM17L, val)
-#define bfin_read_CAN1_AM17H()          bfin_read16(CAN1_AM17H)
-#define bfin_write_CAN1_AM17H(val)      bfin_write16(CAN1_AM17H, val)
-#define bfin_read_CAN1_AM18L()          bfin_read16(CAN1_AM18L)
-#define bfin_write_CAN1_AM18L(val)      bfin_write16(CAN1_AM18L, val)
-#define bfin_read_CAN1_AM18H()          bfin_read16(CAN1_AM18H)
-#define bfin_write_CAN1_AM18H(val)      bfin_write16(CAN1_AM18H, val)
-#define bfin_read_CAN1_AM19L()          bfin_read16(CAN1_AM19L)
-#define bfin_write_CAN1_AM19L(val)      bfin_write16(CAN1_AM19L, val)
-#define bfin_read_CAN1_AM19H()          bfin_read16(CAN1_AM19H)
-#define bfin_write_CAN1_AM19H(val)      bfin_write16(CAN1_AM19H, val)
-#define bfin_read_CAN1_AM20L()          bfin_read16(CAN1_AM20L)
-#define bfin_write_CAN1_AM20L(val)      bfin_write16(CAN1_AM20L, val)
-#define bfin_read_CAN1_AM20H()          bfin_read16(CAN1_AM20H)
-#define bfin_write_CAN1_AM20H(val)      bfin_write16(CAN1_AM20H, val)
-#define bfin_read_CAN1_AM21L()          bfin_read16(CAN1_AM21L)
-#define bfin_write_CAN1_AM21L(val)      bfin_write16(CAN1_AM21L, val)
-#define bfin_read_CAN1_AM21H()          bfin_read16(CAN1_AM21H)
-#define bfin_write_CAN1_AM21H(val)      bfin_write16(CAN1_AM21H, val)
-#define bfin_read_CAN1_AM22L()          bfin_read16(CAN1_AM22L)
-#define bfin_write_CAN1_AM22L(val)      bfin_write16(CAN1_AM22L, val)
-#define bfin_read_CAN1_AM22H()          bfin_read16(CAN1_AM22H)
-#define bfin_write_CAN1_AM22H(val)      bfin_write16(CAN1_AM22H, val)
-#define bfin_read_CAN1_AM23L()          bfin_read16(CAN1_AM23L)
-#define bfin_write_CAN1_AM23L(val)      bfin_write16(CAN1_AM23L, val)
-#define bfin_read_CAN1_AM23H()          bfin_read16(CAN1_AM23H)
-#define bfin_write_CAN1_AM23H(val)      bfin_write16(CAN1_AM23H, val)
-#define bfin_read_CAN1_AM24L()          bfin_read16(CAN1_AM24L)
-#define bfin_write_CAN1_AM24L(val)      bfin_write16(CAN1_AM24L, val)
-#define bfin_read_CAN1_AM24H()          bfin_read16(CAN1_AM24H)
-#define bfin_write_CAN1_AM24H(val)      bfin_write16(CAN1_AM24H, val)
-#define bfin_read_CAN1_AM25L()          bfin_read16(CAN1_AM25L)
-#define bfin_write_CAN1_AM25L(val)      bfin_write16(CAN1_AM25L, val)
-#define bfin_read_CAN1_AM25H()          bfin_read16(CAN1_AM25H)
-#define bfin_write_CAN1_AM25H(val)      bfin_write16(CAN1_AM25H, val)
-#define bfin_read_CAN1_AM26L()          bfin_read16(CAN1_AM26L)
-#define bfin_write_CAN1_AM26L(val)      bfin_write16(CAN1_AM26L, val)
-#define bfin_read_CAN1_AM26H()          bfin_read16(CAN1_AM26H)
-#define bfin_write_CAN1_AM26H(val)      bfin_write16(CAN1_AM26H, val)
-#define bfin_read_CAN1_AM27L()          bfin_read16(CAN1_AM27L)
-#define bfin_write_CAN1_AM27L(val)      bfin_write16(CAN1_AM27L, val)
-#define bfin_read_CAN1_AM27H()          bfin_read16(CAN1_AM27H)
-#define bfin_write_CAN1_AM27H(val)      bfin_write16(CAN1_AM27H, val)
-#define bfin_read_CAN1_AM28L()          bfin_read16(CAN1_AM28L)
-#define bfin_write_CAN1_AM28L(val)      bfin_write16(CAN1_AM28L, val)
-#define bfin_read_CAN1_AM28H()          bfin_read16(CAN1_AM28H)
-#define bfin_write_CAN1_AM28H(val)      bfin_write16(CAN1_AM28H, val)
-#define bfin_read_CAN1_AM29L()          bfin_read16(CAN1_AM29L)
-#define bfin_write_CAN1_AM29L(val)      bfin_write16(CAN1_AM29L, val)
-#define bfin_read_CAN1_AM29H()          bfin_read16(CAN1_AM29H)
-#define bfin_write_CAN1_AM29H(val)      bfin_write16(CAN1_AM29H, val)
-#define bfin_read_CAN1_AM30L()          bfin_read16(CAN1_AM30L)
-#define bfin_write_CAN1_AM30L(val)      bfin_write16(CAN1_AM30L, val)
-#define bfin_read_CAN1_AM30H()          bfin_read16(CAN1_AM30H)
-#define bfin_write_CAN1_AM30H(val)      bfin_write16(CAN1_AM30H, val)
-#define bfin_read_CAN1_AM31L()          bfin_read16(CAN1_AM31L)
-#define bfin_write_CAN1_AM31L(val)      bfin_write16(CAN1_AM31L, val)
-#define bfin_read_CAN1_AM31H()          bfin_read16(CAN1_AM31H)
-#define bfin_write_CAN1_AM31H(val)      bfin_write16(CAN1_AM31H, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB00_DATA0()             bfin_read16(CAN1_MB00_DATA0)
-#define bfin_write_CAN1_MB00_DATA0(val)         bfin_write16(CAN1_MB00_DATA0, val)
-#define bfin_read_CAN1_MB00_DATA1()             bfin_read16(CAN1_MB00_DATA1)
-#define bfin_write_CAN1_MB00_DATA1(val)         bfin_write16(CAN1_MB00_DATA1, val)
-#define bfin_read_CAN1_MB00_DATA2()             bfin_read16(CAN1_MB00_DATA2)
-#define bfin_write_CAN1_MB00_DATA2(val)         bfin_write16(CAN1_MB00_DATA2, val)
-#define bfin_read_CAN1_MB00_DATA3()             bfin_read16(CAN1_MB00_DATA3)
-#define bfin_write_CAN1_MB00_DATA3(val)         bfin_write16(CAN1_MB00_DATA3, val)
-#define bfin_read_CAN1_MB00_LENGTH()            bfin_read16(CAN1_MB00_LENGTH)
-#define bfin_write_CAN1_MB00_LENGTH(val)        bfin_write16(CAN1_MB00_LENGTH, val)
-#define bfin_read_CAN1_MB00_TIMESTAMP()         bfin_read16(CAN1_MB00_TIMESTAMP)
-#define bfin_write_CAN1_MB00_TIMESTAMP(val)     bfin_write16(CAN1_MB00_TIMESTAMP, val)
-#define bfin_read_CAN1_MB00_ID0()               bfin_read16(CAN1_MB00_ID0)
-#define bfin_write_CAN1_MB00_ID0(val)           bfin_write16(CAN1_MB00_ID0, val)
-#define bfin_read_CAN1_MB00_ID1()               bfin_read16(CAN1_MB00_ID1)
-#define bfin_write_CAN1_MB00_ID1(val)           bfin_write16(CAN1_MB00_ID1, val)
-#define bfin_read_CAN1_MB01_DATA0()             bfin_read16(CAN1_MB01_DATA0)
-#define bfin_write_CAN1_MB01_DATA0(val)         bfin_write16(CAN1_MB01_DATA0, val)
-#define bfin_read_CAN1_MB01_DATA1()             bfin_read16(CAN1_MB01_DATA1)
-#define bfin_write_CAN1_MB01_DATA1(val)         bfin_write16(CAN1_MB01_DATA1, val)
-#define bfin_read_CAN1_MB01_DATA2()             bfin_read16(CAN1_MB01_DATA2)
-#define bfin_write_CAN1_MB01_DATA2(val)         bfin_write16(CAN1_MB01_DATA2, val)
-#define bfin_read_CAN1_MB01_DATA3()             bfin_read16(CAN1_MB01_DATA3)
-#define bfin_write_CAN1_MB01_DATA3(val)         bfin_write16(CAN1_MB01_DATA3, val)
-#define bfin_read_CAN1_MB01_LENGTH()            bfin_read16(CAN1_MB01_LENGTH)
-#define bfin_write_CAN1_MB01_LENGTH(val)        bfin_write16(CAN1_MB01_LENGTH, val)
-#define bfin_read_CAN1_MB01_TIMESTAMP()         bfin_read16(CAN1_MB01_TIMESTAMP)
-#define bfin_write_CAN1_MB01_TIMESTAMP(val)     bfin_write16(CAN1_MB01_TIMESTAMP, val)
-#define bfin_read_CAN1_MB01_ID0()               bfin_read16(CAN1_MB01_ID0)
-#define bfin_write_CAN1_MB01_ID0(val)           bfin_write16(CAN1_MB01_ID0, val)
-#define bfin_read_CAN1_MB01_ID1()               bfin_read16(CAN1_MB01_ID1)
-#define bfin_write_CAN1_MB01_ID1(val)           bfin_write16(CAN1_MB01_ID1, val)
-#define bfin_read_CAN1_MB02_DATA0()             bfin_read16(CAN1_MB02_DATA0)
-#define bfin_write_CAN1_MB02_DATA0(val)         bfin_write16(CAN1_MB02_DATA0, val)
-#define bfin_read_CAN1_MB02_DATA1()             bfin_read16(CAN1_MB02_DATA1)
-#define bfin_write_CAN1_MB02_DATA1(val)         bfin_write16(CAN1_MB02_DATA1, val)
-#define bfin_read_CAN1_MB02_DATA2()             bfin_read16(CAN1_MB02_DATA2)
-#define bfin_write_CAN1_MB02_DATA2(val)         bfin_write16(CAN1_MB02_DATA2, val)
-#define bfin_read_CAN1_MB02_DATA3()             bfin_read16(CAN1_MB02_DATA3)
-#define bfin_write_CAN1_MB02_DATA3(val)         bfin_write16(CAN1_MB02_DATA3, val)
-#define bfin_read_CAN1_MB02_LENGTH()            bfin_read16(CAN1_MB02_LENGTH)
-#define bfin_write_CAN1_MB02_LENGTH(val)        bfin_write16(CAN1_MB02_LENGTH, val)
-#define bfin_read_CAN1_MB02_TIMESTAMP()         bfin_read16(CAN1_MB02_TIMESTAMP)
-#define bfin_write_CAN1_MB02_TIMESTAMP(val)     bfin_write16(CAN1_MB02_TIMESTAMP, val)
-#define bfin_read_CAN1_MB02_ID0()               bfin_read16(CAN1_MB02_ID0)
-#define bfin_write_CAN1_MB02_ID0(val)           bfin_write16(CAN1_MB02_ID0, val)
-#define bfin_read_CAN1_MB02_ID1()               bfin_read16(CAN1_MB02_ID1)
-#define bfin_write_CAN1_MB02_ID1(val)           bfin_write16(CAN1_MB02_ID1, val)
-#define bfin_read_CAN1_MB03_DATA0()             bfin_read16(CAN1_MB03_DATA0)
-#define bfin_write_CAN1_MB03_DATA0(val)         bfin_write16(CAN1_MB03_DATA0, val)
-#define bfin_read_CAN1_MB03_DATA1()             bfin_read16(CAN1_MB03_DATA1)
-#define bfin_write_CAN1_MB03_DATA1(val)         bfin_write16(CAN1_MB03_DATA1, val)
-#define bfin_read_CAN1_MB03_DATA2()             bfin_read16(CAN1_MB03_DATA2)
-#define bfin_write_CAN1_MB03_DATA2(val)         bfin_write16(CAN1_MB03_DATA2, val)
-#define bfin_read_CAN1_MB03_DATA3()             bfin_read16(CAN1_MB03_DATA3)
-#define bfin_write_CAN1_MB03_DATA3(val)         bfin_write16(CAN1_MB03_DATA3, val)
-#define bfin_read_CAN1_MB03_LENGTH()            bfin_read16(CAN1_MB03_LENGTH)
-#define bfin_write_CAN1_MB03_LENGTH(val)        bfin_write16(CAN1_MB03_LENGTH, val)
-#define bfin_read_CAN1_MB03_TIMESTAMP()         bfin_read16(CAN1_MB03_TIMESTAMP)
-#define bfin_write_CAN1_MB03_TIMESTAMP(val)     bfin_write16(CAN1_MB03_TIMESTAMP, val)
-#define bfin_read_CAN1_MB03_ID0()               bfin_read16(CAN1_MB03_ID0)
-#define bfin_write_CAN1_MB03_ID0(val)           bfin_write16(CAN1_MB03_ID0, val)
-#define bfin_read_CAN1_MB03_ID1()               bfin_read16(CAN1_MB03_ID1)
-#define bfin_write_CAN1_MB03_ID1(val)           bfin_write16(CAN1_MB03_ID1, val)
-#define bfin_read_CAN1_MB04_DATA0()             bfin_read16(CAN1_MB04_DATA0)
-#define bfin_write_CAN1_MB04_DATA0(val)         bfin_write16(CAN1_MB04_DATA0, val)
-#define bfin_read_CAN1_MB04_DATA1()             bfin_read16(CAN1_MB04_DATA1)
-#define bfin_write_CAN1_MB04_DATA1(val)         bfin_write16(CAN1_MB04_DATA1, val)
-#define bfin_read_CAN1_MB04_DATA2()             bfin_read16(CAN1_MB04_DATA2)
-#define bfin_write_CAN1_MB04_DATA2(val)         bfin_write16(CAN1_MB04_DATA2, val)
-#define bfin_read_CAN1_MB04_DATA3()             bfin_read16(CAN1_MB04_DATA3)
-#define bfin_write_CAN1_MB04_DATA3(val)         bfin_write16(CAN1_MB04_DATA3, val)
-#define bfin_read_CAN1_MB04_LENGTH()            bfin_read16(CAN1_MB04_LENGTH)
-#define bfin_write_CAN1_MB04_LENGTH(val)        bfin_write16(CAN1_MB04_LENGTH, val)
-#define bfin_read_CAN1_MB04_TIMESTAMP()         bfin_read16(CAN1_MB04_TIMESTAMP)
-#define bfin_write_CAN1_MB04_TIMESTAMP(val)     bfin_write16(CAN1_MB04_TIMESTAMP, val)
-#define bfin_read_CAN1_MB04_ID0()               bfin_read16(CAN1_MB04_ID0)
-#define bfin_write_CAN1_MB04_ID0(val)           bfin_write16(CAN1_MB04_ID0, val)
-#define bfin_read_CAN1_MB04_ID1()               bfin_read16(CAN1_MB04_ID1)
-#define bfin_write_CAN1_MB04_ID1(val)           bfin_write16(CAN1_MB04_ID1, val)
-#define bfin_read_CAN1_MB05_DATA0()             bfin_read16(CAN1_MB05_DATA0)
-#define bfin_write_CAN1_MB05_DATA0(val)         bfin_write16(CAN1_MB05_DATA0, val)
-#define bfin_read_CAN1_MB05_DATA1()             bfin_read16(CAN1_MB05_DATA1)
-#define bfin_write_CAN1_MB05_DATA1(val)         bfin_write16(CAN1_MB05_DATA1, val)
-#define bfin_read_CAN1_MB05_DATA2()             bfin_read16(CAN1_MB05_DATA2)
-#define bfin_write_CAN1_MB05_DATA2(val)         bfin_write16(CAN1_MB05_DATA2, val)
-#define bfin_read_CAN1_MB05_DATA3()             bfin_read16(CAN1_MB05_DATA3)
-#define bfin_write_CAN1_MB05_DATA3(val)         bfin_write16(CAN1_MB05_DATA3, val)
-#define bfin_read_CAN1_MB05_LENGTH()            bfin_read16(CAN1_MB05_LENGTH)
-#define bfin_write_CAN1_MB05_LENGTH(val)        bfin_write16(CAN1_MB05_LENGTH, val)
-#define bfin_read_CAN1_MB05_TIMESTAMP()         bfin_read16(CAN1_MB05_TIMESTAMP)
-#define bfin_write_CAN1_MB05_TIMESTAMP(val)     bfin_write16(CAN1_MB05_TIMESTAMP, val)
-#define bfin_read_CAN1_MB05_ID0()               bfin_read16(CAN1_MB05_ID0)
-#define bfin_write_CAN1_MB05_ID0(val)           bfin_write16(CAN1_MB05_ID0, val)
-#define bfin_read_CAN1_MB05_ID1()               bfin_read16(CAN1_MB05_ID1)
-#define bfin_write_CAN1_MB05_ID1(val)           bfin_write16(CAN1_MB05_ID1, val)
-#define bfin_read_CAN1_MB06_DATA0()             bfin_read16(CAN1_MB06_DATA0)
-#define bfin_write_CAN1_MB06_DATA0(val)         bfin_write16(CAN1_MB06_DATA0, val)
-#define bfin_read_CAN1_MB06_DATA1()             bfin_read16(CAN1_MB06_DATA1)
-#define bfin_write_CAN1_MB06_DATA1(val)         bfin_write16(CAN1_MB06_DATA1, val)
-#define bfin_read_CAN1_MB06_DATA2()             bfin_read16(CAN1_MB06_DATA2)
-#define bfin_write_CAN1_MB06_DATA2(val)         bfin_write16(CAN1_MB06_DATA2, val)
-#define bfin_read_CAN1_MB06_DATA3()             bfin_read16(CAN1_MB06_DATA3)
-#define bfin_write_CAN1_MB06_DATA3(val)         bfin_write16(CAN1_MB06_DATA3, val)
-#define bfin_read_CAN1_MB06_LENGTH()            bfin_read16(CAN1_MB06_LENGTH)
-#define bfin_write_CAN1_MB06_LENGTH(val)        bfin_write16(CAN1_MB06_LENGTH, val)
-#define bfin_read_CAN1_MB06_TIMESTAMP()         bfin_read16(CAN1_MB06_TIMESTAMP)
-#define bfin_write_CAN1_MB06_TIMESTAMP(val)     bfin_write16(CAN1_MB06_TIMESTAMP, val)
-#define bfin_read_CAN1_MB06_ID0()               bfin_read16(CAN1_MB06_ID0)
-#define bfin_write_CAN1_MB06_ID0(val)           bfin_write16(CAN1_MB06_ID0, val)
-#define bfin_read_CAN1_MB06_ID1()               bfin_read16(CAN1_MB06_ID1)
-#define bfin_write_CAN1_MB06_ID1(val)           bfin_write16(CAN1_MB06_ID1, val)
-#define bfin_read_CAN1_MB07_DATA0()             bfin_read16(CAN1_MB07_DATA0)
-#define bfin_write_CAN1_MB07_DATA0(val)         bfin_write16(CAN1_MB07_DATA0, val)
-#define bfin_read_CAN1_MB07_DATA1()             bfin_read16(CAN1_MB07_DATA1)
-#define bfin_write_CAN1_MB07_DATA1(val)         bfin_write16(CAN1_MB07_DATA1, val)
-#define bfin_read_CAN1_MB07_DATA2()             bfin_read16(CAN1_MB07_DATA2)
-#define bfin_write_CAN1_MB07_DATA2(val)         bfin_write16(CAN1_MB07_DATA2, val)
-#define bfin_read_CAN1_MB07_DATA3()             bfin_read16(CAN1_MB07_DATA3)
-#define bfin_write_CAN1_MB07_DATA3(val)         bfin_write16(CAN1_MB07_DATA3, val)
-#define bfin_read_CAN1_MB07_LENGTH()            bfin_read16(CAN1_MB07_LENGTH)
-#define bfin_write_CAN1_MB07_LENGTH(val)        bfin_write16(CAN1_MB07_LENGTH, val)
-#define bfin_read_CAN1_MB07_TIMESTAMP()         bfin_read16(CAN1_MB07_TIMESTAMP)
-#define bfin_write_CAN1_MB07_TIMESTAMP(val)     bfin_write16(CAN1_MB07_TIMESTAMP, val)
-#define bfin_read_CAN1_MB07_ID0()               bfin_read16(CAN1_MB07_ID0)
-#define bfin_write_CAN1_MB07_ID0(val)           bfin_write16(CAN1_MB07_ID0, val)
-#define bfin_read_CAN1_MB07_ID1()               bfin_read16(CAN1_MB07_ID1)
-#define bfin_write_CAN1_MB07_ID1(val)           bfin_write16(CAN1_MB07_ID1, val)
-#define bfin_read_CAN1_MB08_DATA0()             bfin_read16(CAN1_MB08_DATA0)
-#define bfin_write_CAN1_MB08_DATA0(val)         bfin_write16(CAN1_MB08_DATA0, val)
-#define bfin_read_CAN1_MB08_DATA1()             bfin_read16(CAN1_MB08_DATA1)
-#define bfin_write_CAN1_MB08_DATA1(val)         bfin_write16(CAN1_MB08_DATA1, val)
-#define bfin_read_CAN1_MB08_DATA2()             bfin_read16(CAN1_MB08_DATA2)
-#define bfin_write_CAN1_MB08_DATA2(val)         bfin_write16(CAN1_MB08_DATA2, val)
-#define bfin_read_CAN1_MB08_DATA3()             bfin_read16(CAN1_MB08_DATA3)
-#define bfin_write_CAN1_MB08_DATA3(val)         bfin_write16(CAN1_MB08_DATA3, val)
-#define bfin_read_CAN1_MB08_LENGTH()            bfin_read16(CAN1_MB08_LENGTH)
-#define bfin_write_CAN1_MB08_LENGTH(val)        bfin_write16(CAN1_MB08_LENGTH, val)
-#define bfin_read_CAN1_MB08_TIMESTAMP()         bfin_read16(CAN1_MB08_TIMESTAMP)
-#define bfin_write_CAN1_MB08_TIMESTAMP(val)     bfin_write16(CAN1_MB08_TIMESTAMP, val)
-#define bfin_read_CAN1_MB08_ID0()               bfin_read16(CAN1_MB08_ID0)
-#define bfin_write_CAN1_MB08_ID0(val)           bfin_write16(CAN1_MB08_ID0, val)
-#define bfin_read_CAN1_MB08_ID1()               bfin_read16(CAN1_MB08_ID1)
-#define bfin_write_CAN1_MB08_ID1(val)           bfin_write16(CAN1_MB08_ID1, val)
-#define bfin_read_CAN1_MB09_DATA0()             bfin_read16(CAN1_MB09_DATA0)
-#define bfin_write_CAN1_MB09_DATA0(val)         bfin_write16(CAN1_MB09_DATA0, val)
-#define bfin_read_CAN1_MB09_DATA1()             bfin_read16(CAN1_MB09_DATA1)
-#define bfin_write_CAN1_MB09_DATA1(val)         bfin_write16(CAN1_MB09_DATA1, val)
-#define bfin_read_CAN1_MB09_DATA2()             bfin_read16(CAN1_MB09_DATA2)
-#define bfin_write_CAN1_MB09_DATA2(val)         bfin_write16(CAN1_MB09_DATA2, val)
-#define bfin_read_CAN1_MB09_DATA3()             bfin_read16(CAN1_MB09_DATA3)
-#define bfin_write_CAN1_MB09_DATA3(val)         bfin_write16(CAN1_MB09_DATA3, val)
-#define bfin_read_CAN1_MB09_LENGTH()            bfin_read16(CAN1_MB09_LENGTH)
-#define bfin_write_CAN1_MB09_LENGTH(val)        bfin_write16(CAN1_MB09_LENGTH, val)
-#define bfin_read_CAN1_MB09_TIMESTAMP()         bfin_read16(CAN1_MB09_TIMESTAMP)
-#define bfin_write_CAN1_MB09_TIMESTAMP(val)     bfin_write16(CAN1_MB09_TIMESTAMP, val)
-#define bfin_read_CAN1_MB09_ID0()               bfin_read16(CAN1_MB09_ID0)
-#define bfin_write_CAN1_MB09_ID0(val)           bfin_write16(CAN1_MB09_ID0, val)
-#define bfin_read_CAN1_MB09_ID1()               bfin_read16(CAN1_MB09_ID1)
-#define bfin_write_CAN1_MB09_ID1(val)           bfin_write16(CAN1_MB09_ID1, val)
-#define bfin_read_CAN1_MB10_DATA0()             bfin_read16(CAN1_MB10_DATA0)
-#define bfin_write_CAN1_MB10_DATA0(val)         bfin_write16(CAN1_MB10_DATA0, val)
-#define bfin_read_CAN1_MB10_DATA1()             bfin_read16(CAN1_MB10_DATA1)
-#define bfin_write_CAN1_MB10_DATA1(val)         bfin_write16(CAN1_MB10_DATA1, val)
-#define bfin_read_CAN1_MB10_DATA2()             bfin_read16(CAN1_MB10_DATA2)
-#define bfin_write_CAN1_MB10_DATA2(val)         bfin_write16(CAN1_MB10_DATA2, val)
-#define bfin_read_CAN1_MB10_DATA3()             bfin_read16(CAN1_MB10_DATA3)
-#define bfin_write_CAN1_MB10_DATA3(val)         bfin_write16(CAN1_MB10_DATA3, val)
-#define bfin_read_CAN1_MB10_LENGTH()            bfin_read16(CAN1_MB10_LENGTH)
-#define bfin_write_CAN1_MB10_LENGTH(val)        bfin_write16(CAN1_MB10_LENGTH, val)
-#define bfin_read_CAN1_MB10_TIMESTAMP()         bfin_read16(CAN1_MB10_TIMESTAMP)
-#define bfin_write_CAN1_MB10_TIMESTAMP(val)     bfin_write16(CAN1_MB10_TIMESTAMP, val)
-#define bfin_read_CAN1_MB10_ID0()               bfin_read16(CAN1_MB10_ID0)
-#define bfin_write_CAN1_MB10_ID0(val)           bfin_write16(CAN1_MB10_ID0, val)
-#define bfin_read_CAN1_MB10_ID1()               bfin_read16(CAN1_MB10_ID1)
-#define bfin_write_CAN1_MB10_ID1(val)           bfin_write16(CAN1_MB10_ID1, val)
-#define bfin_read_CAN1_MB11_DATA0()             bfin_read16(CAN1_MB11_DATA0)
-#define bfin_write_CAN1_MB11_DATA0(val)         bfin_write16(CAN1_MB11_DATA0, val)
-#define bfin_read_CAN1_MB11_DATA1()             bfin_read16(CAN1_MB11_DATA1)
-#define bfin_write_CAN1_MB11_DATA1(val)         bfin_write16(CAN1_MB11_DATA1, val)
-#define bfin_read_CAN1_MB11_DATA2()             bfin_read16(CAN1_MB11_DATA2)
-#define bfin_write_CAN1_MB11_DATA2(val)         bfin_write16(CAN1_MB11_DATA2, val)
-#define bfin_read_CAN1_MB11_DATA3()             bfin_read16(CAN1_MB11_DATA3)
-#define bfin_write_CAN1_MB11_DATA3(val)         bfin_write16(CAN1_MB11_DATA3, val)
-#define bfin_read_CAN1_MB11_LENGTH()            bfin_read16(CAN1_MB11_LENGTH)
-#define bfin_write_CAN1_MB11_LENGTH(val)        bfin_write16(CAN1_MB11_LENGTH, val)
-#define bfin_read_CAN1_MB11_TIMESTAMP()         bfin_read16(CAN1_MB11_TIMESTAMP)
-#define bfin_write_CAN1_MB11_TIMESTAMP(val)     bfin_write16(CAN1_MB11_TIMESTAMP, val)
-#define bfin_read_CAN1_MB11_ID0()               bfin_read16(CAN1_MB11_ID0)
-#define bfin_write_CAN1_MB11_ID0(val)           bfin_write16(CAN1_MB11_ID0, val)
-#define bfin_read_CAN1_MB11_ID1()               bfin_read16(CAN1_MB11_ID1)
-#define bfin_write_CAN1_MB11_ID1(val)           bfin_write16(CAN1_MB11_ID1, val)
-#define bfin_read_CAN1_MB12_DATA0()             bfin_read16(CAN1_MB12_DATA0)
-#define bfin_write_CAN1_MB12_DATA0(val)         bfin_write16(CAN1_MB12_DATA0, val)
-#define bfin_read_CAN1_MB12_DATA1()             bfin_read16(CAN1_MB12_DATA1)
-#define bfin_write_CAN1_MB12_DATA1(val)         bfin_write16(CAN1_MB12_DATA1, val)
-#define bfin_read_CAN1_MB12_DATA2()             bfin_read16(CAN1_MB12_DATA2)
-#define bfin_write_CAN1_MB12_DATA2(val)         bfin_write16(CAN1_MB12_DATA2, val)
-#define bfin_read_CAN1_MB12_DATA3()             bfin_read16(CAN1_MB12_DATA3)
-#define bfin_write_CAN1_MB12_DATA3(val)         bfin_write16(CAN1_MB12_DATA3, val)
-#define bfin_read_CAN1_MB12_LENGTH()            bfin_read16(CAN1_MB12_LENGTH)
-#define bfin_write_CAN1_MB12_LENGTH(val)        bfin_write16(CAN1_MB12_LENGTH, val)
-#define bfin_read_CAN1_MB12_TIMESTAMP()         bfin_read16(CAN1_MB12_TIMESTAMP)
-#define bfin_write_CAN1_MB12_TIMESTAMP(val)     bfin_write16(CAN1_MB12_TIMESTAMP, val)
-#define bfin_read_CAN1_MB12_ID0()               bfin_read16(CAN1_MB12_ID0)
-#define bfin_write_CAN1_MB12_ID0(val)           bfin_write16(CAN1_MB12_ID0, val)
-#define bfin_read_CAN1_MB12_ID1()               bfin_read16(CAN1_MB12_ID1)
-#define bfin_write_CAN1_MB12_ID1(val)           bfin_write16(CAN1_MB12_ID1, val)
-#define bfin_read_CAN1_MB13_DATA0()             bfin_read16(CAN1_MB13_DATA0)
-#define bfin_write_CAN1_MB13_DATA0(val)         bfin_write16(CAN1_MB13_DATA0, val)
-#define bfin_read_CAN1_MB13_DATA1()             bfin_read16(CAN1_MB13_DATA1)
-#define bfin_write_CAN1_MB13_DATA1(val)         bfin_write16(CAN1_MB13_DATA1, val)
-#define bfin_read_CAN1_MB13_DATA2()             bfin_read16(CAN1_MB13_DATA2)
-#define bfin_write_CAN1_MB13_DATA2(val)         bfin_write16(CAN1_MB13_DATA2, val)
-#define bfin_read_CAN1_MB13_DATA3()             bfin_read16(CAN1_MB13_DATA3)
-#define bfin_write_CAN1_MB13_DATA3(val)         bfin_write16(CAN1_MB13_DATA3, val)
-#define bfin_read_CAN1_MB13_LENGTH()            bfin_read16(CAN1_MB13_LENGTH)
-#define bfin_write_CAN1_MB13_LENGTH(val)        bfin_write16(CAN1_MB13_LENGTH, val)
-#define bfin_read_CAN1_MB13_TIMESTAMP()         bfin_read16(CAN1_MB13_TIMESTAMP)
-#define bfin_write_CAN1_MB13_TIMESTAMP(val)     bfin_write16(CAN1_MB13_TIMESTAMP, val)
-#define bfin_read_CAN1_MB13_ID0()               bfin_read16(CAN1_MB13_ID0)
-#define bfin_write_CAN1_MB13_ID0(val)           bfin_write16(CAN1_MB13_ID0, val)
-#define bfin_read_CAN1_MB13_ID1()               bfin_read16(CAN1_MB13_ID1)
-#define bfin_write_CAN1_MB13_ID1(val)           bfin_write16(CAN1_MB13_ID1, val)
-#define bfin_read_CAN1_MB14_DATA0()             bfin_read16(CAN1_MB14_DATA0)
-#define bfin_write_CAN1_MB14_DATA0(val)         bfin_write16(CAN1_MB14_DATA0, val)
-#define bfin_read_CAN1_MB14_DATA1()             bfin_read16(CAN1_MB14_DATA1)
-#define bfin_write_CAN1_MB14_DATA1(val)         bfin_write16(CAN1_MB14_DATA1, val)
-#define bfin_read_CAN1_MB14_DATA2()             bfin_read16(CAN1_MB14_DATA2)
-#define bfin_write_CAN1_MB14_DATA2(val)         bfin_write16(CAN1_MB14_DATA2, val)
-#define bfin_read_CAN1_MB14_DATA3()             bfin_read16(CAN1_MB14_DATA3)
-#define bfin_write_CAN1_MB14_DATA3(val)         bfin_write16(CAN1_MB14_DATA3, val)
-#define bfin_read_CAN1_MB14_LENGTH()            bfin_read16(CAN1_MB14_LENGTH)
-#define bfin_write_CAN1_MB14_LENGTH(val)        bfin_write16(CAN1_MB14_LENGTH, val)
-#define bfin_read_CAN1_MB14_TIMESTAMP()         bfin_read16(CAN1_MB14_TIMESTAMP)
-#define bfin_write_CAN1_MB14_TIMESTAMP(val)     bfin_write16(CAN1_MB14_TIMESTAMP, val)
-#define bfin_read_CAN1_MB14_ID0()               bfin_read16(CAN1_MB14_ID0)
-#define bfin_write_CAN1_MB14_ID0(val)           bfin_write16(CAN1_MB14_ID0, val)
-#define bfin_read_CAN1_MB14_ID1()               bfin_read16(CAN1_MB14_ID1)
-#define bfin_write_CAN1_MB14_ID1(val)           bfin_write16(CAN1_MB14_ID1, val)
-#define bfin_read_CAN1_MB15_DATA0()             bfin_read16(CAN1_MB15_DATA0)
-#define bfin_write_CAN1_MB15_DATA0(val)         bfin_write16(CAN1_MB15_DATA0, val)
-#define bfin_read_CAN1_MB15_DATA1()             bfin_read16(CAN1_MB15_DATA1)
-#define bfin_write_CAN1_MB15_DATA1(val)         bfin_write16(CAN1_MB15_DATA1, val)
-#define bfin_read_CAN1_MB15_DATA2()             bfin_read16(CAN1_MB15_DATA2)
-#define bfin_write_CAN1_MB15_DATA2(val)         bfin_write16(CAN1_MB15_DATA2, val)
-#define bfin_read_CAN1_MB15_DATA3()             bfin_read16(CAN1_MB15_DATA3)
-#define bfin_write_CAN1_MB15_DATA3(val)         bfin_write16(CAN1_MB15_DATA3, val)
-#define bfin_read_CAN1_MB15_LENGTH()            bfin_read16(CAN1_MB15_LENGTH)
-#define bfin_write_CAN1_MB15_LENGTH(val)        bfin_write16(CAN1_MB15_LENGTH, val)
-#define bfin_read_CAN1_MB15_TIMESTAMP()         bfin_read16(CAN1_MB15_TIMESTAMP)
-#define bfin_write_CAN1_MB15_TIMESTAMP(val)     bfin_write16(CAN1_MB15_TIMESTAMP, val)
-#define bfin_read_CAN1_MB15_ID0()               bfin_read16(CAN1_MB15_ID0)
-#define bfin_write_CAN1_MB15_ID0(val)           bfin_write16(CAN1_MB15_ID0, val)
-#define bfin_read_CAN1_MB15_ID1()               bfin_read16(CAN1_MB15_ID1)
-#define bfin_write_CAN1_MB15_ID1(val)           bfin_write16(CAN1_MB15_ID1, val)
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define bfin_read_CAN1_MB16_DATA0()             bfin_read16(CAN1_MB16_DATA0)
-#define bfin_write_CAN1_MB16_DATA0(val)         bfin_write16(CAN1_MB16_DATA0, val)
-#define bfin_read_CAN1_MB16_DATA1()             bfin_read16(CAN1_MB16_DATA1)
-#define bfin_write_CAN1_MB16_DATA1(val)         bfin_write16(CAN1_MB16_DATA1, val)
-#define bfin_read_CAN1_MB16_DATA2()             bfin_read16(CAN1_MB16_DATA2)
-#define bfin_write_CAN1_MB16_DATA2(val)         bfin_write16(CAN1_MB16_DATA2, val)
-#define bfin_read_CAN1_MB16_DATA3()             bfin_read16(CAN1_MB16_DATA3)
-#define bfin_write_CAN1_MB16_DATA3(val)         bfin_write16(CAN1_MB16_DATA3, val)
-#define bfin_read_CAN1_MB16_LENGTH()            bfin_read16(CAN1_MB16_LENGTH)
-#define bfin_write_CAN1_MB16_LENGTH(val)        bfin_write16(CAN1_MB16_LENGTH, val)
-#define bfin_read_CAN1_MB16_TIMESTAMP()         bfin_read16(CAN1_MB16_TIMESTAMP)
-#define bfin_write_CAN1_MB16_TIMESTAMP(val)     bfin_write16(CAN1_MB16_TIMESTAMP, val)
-#define bfin_read_CAN1_MB16_ID0()               bfin_read16(CAN1_MB16_ID0)
-#define bfin_write_CAN1_MB16_ID0(val)           bfin_write16(CAN1_MB16_ID0, val)
-#define bfin_read_CAN1_MB16_ID1()               bfin_read16(CAN1_MB16_ID1)
-#define bfin_write_CAN1_MB16_ID1(val)           bfin_write16(CAN1_MB16_ID1, val)
-#define bfin_read_CAN1_MB17_DATA0()             bfin_read16(CAN1_MB17_DATA0)
-#define bfin_write_CAN1_MB17_DATA0(val)         bfin_write16(CAN1_MB17_DATA0, val)
-#define bfin_read_CAN1_MB17_DATA1()             bfin_read16(CAN1_MB17_DATA1)
-#define bfin_write_CAN1_MB17_DATA1(val)         bfin_write16(CAN1_MB17_DATA1, val)
-#define bfin_read_CAN1_MB17_DATA2()             bfin_read16(CAN1_MB17_DATA2)
-#define bfin_write_CAN1_MB17_DATA2(val)         bfin_write16(CAN1_MB17_DATA2, val)
-#define bfin_read_CAN1_MB17_DATA3()             bfin_read16(CAN1_MB17_DATA3)
-#define bfin_write_CAN1_MB17_DATA3(val)         bfin_write16(CAN1_MB17_DATA3, val)
-#define bfin_read_CAN1_MB17_LENGTH()            bfin_read16(CAN1_MB17_LENGTH)
-#define bfin_write_CAN1_MB17_LENGTH(val)        bfin_write16(CAN1_MB17_LENGTH, val)
-#define bfin_read_CAN1_MB17_TIMESTAMP()         bfin_read16(CAN1_MB17_TIMESTAMP)
-#define bfin_write_CAN1_MB17_TIMESTAMP(val)     bfin_write16(CAN1_MB17_TIMESTAMP, val)
-#define bfin_read_CAN1_MB17_ID0()               bfin_read16(CAN1_MB17_ID0)
-#define bfin_write_CAN1_MB17_ID0(val)           bfin_write16(CAN1_MB17_ID0, val)
-#define bfin_read_CAN1_MB17_ID1()               bfin_read16(CAN1_MB17_ID1)
-#define bfin_write_CAN1_MB17_ID1(val)           bfin_write16(CAN1_MB17_ID1, val)
-#define bfin_read_CAN1_MB18_DATA0()             bfin_read16(CAN1_MB18_DATA0)
-#define bfin_write_CAN1_MB18_DATA0(val)         bfin_write16(CAN1_MB18_DATA0, val)
-#define bfin_read_CAN1_MB18_DATA1()             bfin_read16(CAN1_MB18_DATA1)
-#define bfin_write_CAN1_MB18_DATA1(val)         bfin_write16(CAN1_MB18_DATA1, val)
-#define bfin_read_CAN1_MB18_DATA2()             bfin_read16(CAN1_MB18_DATA2)
-#define bfin_write_CAN1_MB18_DATA2(val)         bfin_write16(CAN1_MB18_DATA2, val)
-#define bfin_read_CAN1_MB18_DATA3()             bfin_read16(CAN1_MB18_DATA3)
-#define bfin_write_CAN1_MB18_DATA3(val)         bfin_write16(CAN1_MB18_DATA3, val)
-#define bfin_read_CAN1_MB18_LENGTH()            bfin_read16(CAN1_MB18_LENGTH)
-#define bfin_write_CAN1_MB18_LENGTH(val)        bfin_write16(CAN1_MB18_LENGTH, val)
-#define bfin_read_CAN1_MB18_TIMESTAMP()         bfin_read16(CAN1_MB18_TIMESTAMP)
-#define bfin_write_CAN1_MB18_TIMESTAMP(val)     bfin_write16(CAN1_MB18_TIMESTAMP, val)
-#define bfin_read_CAN1_MB18_ID0()               bfin_read16(CAN1_MB18_ID0)
-#define bfin_write_CAN1_MB18_ID0(val)           bfin_write16(CAN1_MB18_ID0, val)
-#define bfin_read_CAN1_MB18_ID1()               bfin_read16(CAN1_MB18_ID1)
-#define bfin_write_CAN1_MB18_ID1(val)           bfin_write16(CAN1_MB18_ID1, val)
-#define bfin_read_CAN1_MB19_DATA0()             bfin_read16(CAN1_MB19_DATA0)
-#define bfin_write_CAN1_MB19_DATA0(val)         bfin_write16(CAN1_MB19_DATA0, val)
-#define bfin_read_CAN1_MB19_DATA1()             bfin_read16(CAN1_MB19_DATA1)
-#define bfin_write_CAN1_MB19_DATA1(val)         bfin_write16(CAN1_MB19_DATA1, val)
-#define bfin_read_CAN1_MB19_DATA2()             bfin_read16(CAN1_MB19_DATA2)
-#define bfin_write_CAN1_MB19_DATA2(val)         bfin_write16(CAN1_MB19_DATA2, val)
-#define bfin_read_CAN1_MB19_DATA3()             bfin_read16(CAN1_MB19_DATA3)
-#define bfin_write_CAN1_MB19_DATA3(val)         bfin_write16(CAN1_MB19_DATA3, val)
-#define bfin_read_CAN1_MB19_LENGTH()            bfin_read16(CAN1_MB19_LENGTH)
-#define bfin_write_CAN1_MB19_LENGTH(val)        bfin_write16(CAN1_MB19_LENGTH, val)
-#define bfin_read_CAN1_MB19_TIMESTAMP()         bfin_read16(CAN1_MB19_TIMESTAMP)
-#define bfin_write_CAN1_MB19_TIMESTAMP(val)     bfin_write16(CAN1_MB19_TIMESTAMP, val)
-#define bfin_read_CAN1_MB19_ID0()               bfin_read16(CAN1_MB19_ID0)
-#define bfin_write_CAN1_MB19_ID0(val)           bfin_write16(CAN1_MB19_ID0, val)
-#define bfin_read_CAN1_MB19_ID1()               bfin_read16(CAN1_MB19_ID1)
-#define bfin_write_CAN1_MB19_ID1(val)           bfin_write16(CAN1_MB19_ID1, val)
-#define bfin_read_CAN1_MB20_DATA0()             bfin_read16(CAN1_MB20_DATA0)
-#define bfin_write_CAN1_MB20_DATA0(val)         bfin_write16(CAN1_MB20_DATA0, val)
-#define bfin_read_CAN1_MB20_DATA1()             bfin_read16(CAN1_MB20_DATA1)
-#define bfin_write_CAN1_MB20_DATA1(val)         bfin_write16(CAN1_MB20_DATA1, val)
-#define bfin_read_CAN1_MB20_DATA2()             bfin_read16(CAN1_MB20_DATA2)
-#define bfin_write_CAN1_MB20_DATA2(val)         bfin_write16(CAN1_MB20_DATA2, val)
-#define bfin_read_CAN1_MB20_DATA3()             bfin_read16(CAN1_MB20_DATA3)
-#define bfin_write_CAN1_MB20_DATA3(val)         bfin_write16(CAN1_MB20_DATA3, val)
-#define bfin_read_CAN1_MB20_LENGTH()            bfin_read16(CAN1_MB20_LENGTH)
-#define bfin_write_CAN1_MB20_LENGTH(val)        bfin_write16(CAN1_MB20_LENGTH, val)
-#define bfin_read_CAN1_MB20_TIMESTAMP()         bfin_read16(CAN1_MB20_TIMESTAMP)
-#define bfin_write_CAN1_MB20_TIMESTAMP(val)     bfin_write16(CAN1_MB20_TIMESTAMP, val)
-#define bfin_read_CAN1_MB20_ID0()               bfin_read16(CAN1_MB20_ID0)
-#define bfin_write_CAN1_MB20_ID0(val)           bfin_write16(CAN1_MB20_ID0, val)
-#define bfin_read_CAN1_MB20_ID1()               bfin_read16(CAN1_MB20_ID1)
-#define bfin_write_CAN1_MB20_ID1(val)           bfin_write16(CAN1_MB20_ID1, val)
-#define bfin_read_CAN1_MB21_DATA0()             bfin_read16(CAN1_MB21_DATA0)
-#define bfin_write_CAN1_MB21_DATA0(val)         bfin_write16(CAN1_MB21_DATA0, val)
-#define bfin_read_CAN1_MB21_DATA1()             bfin_read16(CAN1_MB21_DATA1)
-#define bfin_write_CAN1_MB21_DATA1(val)         bfin_write16(CAN1_MB21_DATA1, val)
-#define bfin_read_CAN1_MB21_DATA2()             bfin_read16(CAN1_MB21_DATA2)
-#define bfin_write_CAN1_MB21_DATA2(val)         bfin_write16(CAN1_MB21_DATA2, val)
-#define bfin_read_CAN1_MB21_DATA3()             bfin_read16(CAN1_MB21_DATA3)
-#define bfin_write_CAN1_MB21_DATA3(val)         bfin_write16(CAN1_MB21_DATA3, val)
-#define bfin_read_CAN1_MB21_LENGTH()            bfin_read16(CAN1_MB21_LENGTH)
-#define bfin_write_CAN1_MB21_LENGTH(val)        bfin_write16(CAN1_MB21_LENGTH, val)
-#define bfin_read_CAN1_MB21_TIMESTAMP()         bfin_read16(CAN1_MB21_TIMESTAMP)
-#define bfin_write_CAN1_MB21_TIMESTAMP(val)     bfin_write16(CAN1_MB21_TIMESTAMP, val)
-#define bfin_read_CAN1_MB21_ID0()               bfin_read16(CAN1_MB21_ID0)
-#define bfin_write_CAN1_MB21_ID0(val)           bfin_write16(CAN1_MB21_ID0, val)
-#define bfin_read_CAN1_MB21_ID1()               bfin_read16(CAN1_MB21_ID1)
-#define bfin_write_CAN1_MB21_ID1(val)           bfin_write16(CAN1_MB21_ID1, val)
-#define bfin_read_CAN1_MB22_DATA0()             bfin_read16(CAN1_MB22_DATA0)
-#define bfin_write_CAN1_MB22_DATA0(val)         bfin_write16(CAN1_MB22_DATA0, val)
-#define bfin_read_CAN1_MB22_DATA1()             bfin_read16(CAN1_MB22_DATA1)
-#define bfin_write_CAN1_MB22_DATA1(val)         bfin_write16(CAN1_MB22_DATA1, val)
-#define bfin_read_CAN1_MB22_DATA2()             bfin_read16(CAN1_MB22_DATA2)
-#define bfin_write_CAN1_MB22_DATA2(val)         bfin_write16(CAN1_MB22_DATA2, val)
-#define bfin_read_CAN1_MB22_DATA3()             bfin_read16(CAN1_MB22_DATA3)
-#define bfin_write_CAN1_MB22_DATA3(val)         bfin_write16(CAN1_MB22_DATA3, val)
-#define bfin_read_CAN1_MB22_LENGTH()            bfin_read16(CAN1_MB22_LENGTH)
-#define bfin_write_CAN1_MB22_LENGTH(val)        bfin_write16(CAN1_MB22_LENGTH, val)
-#define bfin_read_CAN1_MB22_TIMESTAMP()         bfin_read16(CAN1_MB22_TIMESTAMP)
-#define bfin_write_CAN1_MB22_TIMESTAMP(val)     bfin_write16(CAN1_MB22_TIMESTAMP, val)
-#define bfin_read_CAN1_MB22_ID0()               bfin_read16(CAN1_MB22_ID0)
-#define bfin_write_CAN1_MB22_ID0(val)           bfin_write16(CAN1_MB22_ID0, val)
-#define bfin_read_CAN1_MB22_ID1()               bfin_read16(CAN1_MB22_ID1)
-#define bfin_write_CAN1_MB22_ID1(val)           bfin_write16(CAN1_MB22_ID1, val)
-#define bfin_read_CAN1_MB23_DATA0()             bfin_read16(CAN1_MB23_DATA0)
-#define bfin_write_CAN1_MB23_DATA0(val)         bfin_write16(CAN1_MB23_DATA0, val)
-#define bfin_read_CAN1_MB23_DATA1()             bfin_read16(CAN1_MB23_DATA1)
-#define bfin_write_CAN1_MB23_DATA1(val)         bfin_write16(CAN1_MB23_DATA1, val)
-#define bfin_read_CAN1_MB23_DATA2()             bfin_read16(CAN1_MB23_DATA2)
-#define bfin_write_CAN1_MB23_DATA2(val)         bfin_write16(CAN1_MB23_DATA2, val)
-#define bfin_read_CAN1_MB23_DATA3()             bfin_read16(CAN1_MB23_DATA3)
-#define bfin_write_CAN1_MB23_DATA3(val)         bfin_write16(CAN1_MB23_DATA3, val)
-#define bfin_read_CAN1_MB23_LENGTH()            bfin_read16(CAN1_MB23_LENGTH)
-#define bfin_write_CAN1_MB23_LENGTH(val)        bfin_write16(CAN1_MB23_LENGTH, val)
-#define bfin_read_CAN1_MB23_TIMESTAMP()         bfin_read16(CAN1_MB23_TIMESTAMP)
-#define bfin_write_CAN1_MB23_TIMESTAMP(val)     bfin_write16(CAN1_MB23_TIMESTAMP, val)
-#define bfin_read_CAN1_MB23_ID0()               bfin_read16(CAN1_MB23_ID0)
-#define bfin_write_CAN1_MB23_ID0(val)           bfin_write16(CAN1_MB23_ID0, val)
-#define bfin_read_CAN1_MB23_ID1()               bfin_read16(CAN1_MB23_ID1)
-#define bfin_write_CAN1_MB23_ID1(val)           bfin_write16(CAN1_MB23_ID1, val)
-#define bfin_read_CAN1_MB24_DATA0()             bfin_read16(CAN1_MB24_DATA0)
-#define bfin_write_CAN1_MB24_DATA0(val)         bfin_write16(CAN1_MB24_DATA0, val)
-#define bfin_read_CAN1_MB24_DATA1()             bfin_read16(CAN1_MB24_DATA1)
-#define bfin_write_CAN1_MB24_DATA1(val)         bfin_write16(CAN1_MB24_DATA1, val)
-#define bfin_read_CAN1_MB24_DATA2()             bfin_read16(CAN1_MB24_DATA2)
-#define bfin_write_CAN1_MB24_DATA2(val)         bfin_write16(CAN1_MB24_DATA2, val)
-#define bfin_read_CAN1_MB24_DATA3()             bfin_read16(CAN1_MB24_DATA3)
-#define bfin_write_CAN1_MB24_DATA3(val)         bfin_write16(CAN1_MB24_DATA3, val)
-#define bfin_read_CAN1_MB24_LENGTH()            bfin_read16(CAN1_MB24_LENGTH)
-#define bfin_write_CAN1_MB24_LENGTH(val)        bfin_write16(CAN1_MB24_LENGTH, val)
-#define bfin_read_CAN1_MB24_TIMESTAMP()         bfin_read16(CAN1_MB24_TIMESTAMP)
-#define bfin_write_CAN1_MB24_TIMESTAMP(val)     bfin_write16(CAN1_MB24_TIMESTAMP, val)
-#define bfin_read_CAN1_MB24_ID0()               bfin_read16(CAN1_MB24_ID0)
-#define bfin_write_CAN1_MB24_ID0(val)           bfin_write16(CAN1_MB24_ID0, val)
-#define bfin_read_CAN1_MB24_ID1()               bfin_read16(CAN1_MB24_ID1)
-#define bfin_write_CAN1_MB24_ID1(val)           bfin_write16(CAN1_MB24_ID1, val)
-#define bfin_read_CAN1_MB25_DATA0()             bfin_read16(CAN1_MB25_DATA0)
-#define bfin_write_CAN1_MB25_DATA0(val)         bfin_write16(CAN1_MB25_DATA0, val)
-#define bfin_read_CAN1_MB25_DATA1()             bfin_read16(CAN1_MB25_DATA1)
-#define bfin_write_CAN1_MB25_DATA1(val)         bfin_write16(CAN1_MB25_DATA1, val)
-#define bfin_read_CAN1_MB25_DATA2()             bfin_read16(CAN1_MB25_DATA2)
-#define bfin_write_CAN1_MB25_DATA2(val)         bfin_write16(CAN1_MB25_DATA2, val)
-#define bfin_read_CAN1_MB25_DATA3()             bfin_read16(CAN1_MB25_DATA3)
-#define bfin_write_CAN1_MB25_DATA3(val)         bfin_write16(CAN1_MB25_DATA3, val)
-#define bfin_read_CAN1_MB25_LENGTH()            bfin_read16(CAN1_MB25_LENGTH)
-#define bfin_write_CAN1_MB25_LENGTH(val)        bfin_write16(CAN1_MB25_LENGTH, val)
-#define bfin_read_CAN1_MB25_TIMESTAMP()         bfin_read16(CAN1_MB25_TIMESTAMP)
-#define bfin_write_CAN1_MB25_TIMESTAMP(val)     bfin_write16(CAN1_MB25_TIMESTAMP, val)
-#define bfin_read_CAN1_MB25_ID0()               bfin_read16(CAN1_MB25_ID0)
-#define bfin_write_CAN1_MB25_ID0(val)           bfin_write16(CAN1_MB25_ID0, val)
-#define bfin_read_CAN1_MB25_ID1()               bfin_read16(CAN1_MB25_ID1)
-#define bfin_write_CAN1_MB25_ID1(val)           bfin_write16(CAN1_MB25_ID1, val)
-#define bfin_read_CAN1_MB26_DATA0()             bfin_read16(CAN1_MB26_DATA0)
-#define bfin_write_CAN1_MB26_DATA0(val)         bfin_write16(CAN1_MB26_DATA0, val)
-#define bfin_read_CAN1_MB26_DATA1()             bfin_read16(CAN1_MB26_DATA1)
-#define bfin_write_CAN1_MB26_DATA1(val)         bfin_write16(CAN1_MB26_DATA1, val)
-#define bfin_read_CAN1_MB26_DATA2()             bfin_read16(CAN1_MB26_DATA2)
-#define bfin_write_CAN1_MB26_DATA2(val)         bfin_write16(CAN1_MB26_DATA2, val)
-#define bfin_read_CAN1_MB26_DATA3()             bfin_read16(CAN1_MB26_DATA3)
-#define bfin_write_CAN1_MB26_DATA3(val)         bfin_write16(CAN1_MB26_DATA3, val)
-#define bfin_read_CAN1_MB26_LENGTH()            bfin_read16(CAN1_MB26_LENGTH)
-#define bfin_write_CAN1_MB26_LENGTH(val)        bfin_write16(CAN1_MB26_LENGTH, val)
-#define bfin_read_CAN1_MB26_TIMESTAMP()         bfin_read16(CAN1_MB26_TIMESTAMP)
-#define bfin_write_CAN1_MB26_TIMESTAMP(val)     bfin_write16(CAN1_MB26_TIMESTAMP, val)
-#define bfin_read_CAN1_MB26_ID0()               bfin_read16(CAN1_MB26_ID0)
-#define bfin_write_CAN1_MB26_ID0(val)           bfin_write16(CAN1_MB26_ID0, val)
-#define bfin_read_CAN1_MB26_ID1()               bfin_read16(CAN1_MB26_ID1)
-#define bfin_write_CAN1_MB26_ID1(val)           bfin_write16(CAN1_MB26_ID1, val)
-#define bfin_read_CAN1_MB27_DATA0()             bfin_read16(CAN1_MB27_DATA0)
-#define bfin_write_CAN1_MB27_DATA0(val)         bfin_write16(CAN1_MB27_DATA0, val)
-#define bfin_read_CAN1_MB27_DATA1()             bfin_read16(CAN1_MB27_DATA1)
-#define bfin_write_CAN1_MB27_DATA1(val)         bfin_write16(CAN1_MB27_DATA1, val)
-#define bfin_read_CAN1_MB27_DATA2()             bfin_read16(CAN1_MB27_DATA2)
-#define bfin_write_CAN1_MB27_DATA2(val)         bfin_write16(CAN1_MB27_DATA2, val)
-#define bfin_read_CAN1_MB27_DATA3()             bfin_read16(CAN1_MB27_DATA3)
-#define bfin_write_CAN1_MB27_DATA3(val)         bfin_write16(CAN1_MB27_DATA3, val)
-#define bfin_read_CAN1_MB27_LENGTH()            bfin_read16(CAN1_MB27_LENGTH)
-#define bfin_write_CAN1_MB27_LENGTH(val)        bfin_write16(CAN1_MB27_LENGTH, val)
-#define bfin_read_CAN1_MB27_TIMESTAMP()         bfin_read16(CAN1_MB27_TIMESTAMP)
-#define bfin_write_CAN1_MB27_TIMESTAMP(val)     bfin_write16(CAN1_MB27_TIMESTAMP, val)
-#define bfin_read_CAN1_MB27_ID0()               bfin_read16(CAN1_MB27_ID0)
-#define bfin_write_CAN1_MB27_ID0(val)           bfin_write16(CAN1_MB27_ID0, val)
-#define bfin_read_CAN1_MB27_ID1()               bfin_read16(CAN1_MB27_ID1)
-#define bfin_write_CAN1_MB27_ID1(val)           bfin_write16(CAN1_MB27_ID1, val)
-#define bfin_read_CAN1_MB28_DATA0()             bfin_read16(CAN1_MB28_DATA0)
-#define bfin_write_CAN1_MB28_DATA0(val)         bfin_write16(CAN1_MB28_DATA0, val)
-#define bfin_read_CAN1_MB28_DATA1()             bfin_read16(CAN1_MB28_DATA1)
-#define bfin_write_CAN1_MB28_DATA1(val)         bfin_write16(CAN1_MB28_DATA1, val)
-#define bfin_read_CAN1_MB28_DATA2()             bfin_read16(CAN1_MB28_DATA2)
-#define bfin_write_CAN1_MB28_DATA2(val)         bfin_write16(CAN1_MB28_DATA2, val)
-#define bfin_read_CAN1_MB28_DATA3()             bfin_read16(CAN1_MB28_DATA3)
-#define bfin_write_CAN1_MB28_DATA3(val)         bfin_write16(CAN1_MB28_DATA3, val)
-#define bfin_read_CAN1_MB28_LENGTH()            bfin_read16(CAN1_MB28_LENGTH)
-#define bfin_write_CAN1_MB28_LENGTH(val)        bfin_write16(CAN1_MB28_LENGTH, val)
-#define bfin_read_CAN1_MB28_TIMESTAMP()         bfin_read16(CAN1_MB28_TIMESTAMP)
-#define bfin_write_CAN1_MB28_TIMESTAMP(val)     bfin_write16(CAN1_MB28_TIMESTAMP, val)
-#define bfin_read_CAN1_MB28_ID0()               bfin_read16(CAN1_MB28_ID0)
-#define bfin_write_CAN1_MB28_ID0(val)           bfin_write16(CAN1_MB28_ID0, val)
-#define bfin_read_CAN1_MB28_ID1()               bfin_read16(CAN1_MB28_ID1)
-#define bfin_write_CAN1_MB28_ID1(val)           bfin_write16(CAN1_MB28_ID1, val)
-#define bfin_read_CAN1_MB29_DATA0()             bfin_read16(CAN1_MB29_DATA0)
-#define bfin_write_CAN1_MB29_DATA0(val)         bfin_write16(CAN1_MB29_DATA0, val)
-#define bfin_read_CAN1_MB29_DATA1()             bfin_read16(CAN1_MB29_DATA1)
-#define bfin_write_CAN1_MB29_DATA1(val)         bfin_write16(CAN1_MB29_DATA1, val)
-#define bfin_read_CAN1_MB29_DATA2()             bfin_read16(CAN1_MB29_DATA2)
-#define bfin_write_CAN1_MB29_DATA2(val)         bfin_write16(CAN1_MB29_DATA2, val)
-#define bfin_read_CAN1_MB29_DATA3()             bfin_read16(CAN1_MB29_DATA3)
-#define bfin_write_CAN1_MB29_DATA3(val)         bfin_write16(CAN1_MB29_DATA3, val)
-#define bfin_read_CAN1_MB29_LENGTH()            bfin_read16(CAN1_MB29_LENGTH)
-#define bfin_write_CAN1_MB29_LENGTH(val)        bfin_write16(CAN1_MB29_LENGTH, val)
-#define bfin_read_CAN1_MB29_TIMESTAMP()         bfin_read16(CAN1_MB29_TIMESTAMP)
-#define bfin_write_CAN1_MB29_TIMESTAMP(val)     bfin_write16(CAN1_MB29_TIMESTAMP, val)
-#define bfin_read_CAN1_MB29_ID0()               bfin_read16(CAN1_MB29_ID0)
-#define bfin_write_CAN1_MB29_ID0(val)           bfin_write16(CAN1_MB29_ID0, val)
-#define bfin_read_CAN1_MB29_ID1()               bfin_read16(CAN1_MB29_ID1)
-#define bfin_write_CAN1_MB29_ID1(val)           bfin_write16(CAN1_MB29_ID1, val)
-#define bfin_read_CAN1_MB30_DATA0()             bfin_read16(CAN1_MB30_DATA0)
-#define bfin_write_CAN1_MB30_DATA0(val)         bfin_write16(CAN1_MB30_DATA0, val)
-#define bfin_read_CAN1_MB30_DATA1()             bfin_read16(CAN1_MB30_DATA1)
-#define bfin_write_CAN1_MB30_DATA1(val)         bfin_write16(CAN1_MB30_DATA1, val)
-#define bfin_read_CAN1_MB30_DATA2()             bfin_read16(CAN1_MB30_DATA2)
-#define bfin_write_CAN1_MB30_DATA2(val)         bfin_write16(CAN1_MB30_DATA2, val)
-#define bfin_read_CAN1_MB30_DATA3()             bfin_read16(CAN1_MB30_DATA3)
-#define bfin_write_CAN1_MB30_DATA3(val)         bfin_write16(CAN1_MB30_DATA3, val)
-#define bfin_read_CAN1_MB30_LENGTH()            bfin_read16(CAN1_MB30_LENGTH)
-#define bfin_write_CAN1_MB30_LENGTH(val)        bfin_write16(CAN1_MB30_LENGTH, val)
-#define bfin_read_CAN1_MB30_TIMESTAMP()         bfin_read16(CAN1_MB30_TIMESTAMP)
-#define bfin_write_CAN1_MB30_TIMESTAMP(val)     bfin_write16(CAN1_MB30_TIMESTAMP, val)
-#define bfin_read_CAN1_MB30_ID0()               bfin_read16(CAN1_MB30_ID0)
-#define bfin_write_CAN1_MB30_ID0(val)           bfin_write16(CAN1_MB30_ID0, val)
-#define bfin_read_CAN1_MB30_ID1()               bfin_read16(CAN1_MB30_ID1)
-#define bfin_write_CAN1_MB30_ID1(val)           bfin_write16(CAN1_MB30_ID1, val)
-#define bfin_read_CAN1_MB31_DATA0()             bfin_read16(CAN1_MB31_DATA0)
-#define bfin_write_CAN1_MB31_DATA0(val)         bfin_write16(CAN1_MB31_DATA0, val)
-#define bfin_read_CAN1_MB31_DATA1()             bfin_read16(CAN1_MB31_DATA1)
-#define bfin_write_CAN1_MB31_DATA1(val)         bfin_write16(CAN1_MB31_DATA1, val)
-#define bfin_read_CAN1_MB31_DATA2()             bfin_read16(CAN1_MB31_DATA2)
-#define bfin_write_CAN1_MB31_DATA2(val)         bfin_write16(CAN1_MB31_DATA2, val)
-#define bfin_read_CAN1_MB31_DATA3()             bfin_read16(CAN1_MB31_DATA3)
-#define bfin_write_CAN1_MB31_DATA3(val)         bfin_write16(CAN1_MB31_DATA3, val)
-#define bfin_read_CAN1_MB31_LENGTH()            bfin_read16(CAN1_MB31_LENGTH)
-#define bfin_write_CAN1_MB31_LENGTH(val)        bfin_write16(CAN1_MB31_LENGTH, val)
-#define bfin_read_CAN1_MB31_TIMESTAMP()         bfin_read16(CAN1_MB31_TIMESTAMP)
-#define bfin_write_CAN1_MB31_TIMESTAMP(val)     bfin_write16(CAN1_MB31_TIMESTAMP, val)
-#define bfin_read_CAN1_MB31_ID0()               bfin_read16(CAN1_MB31_ID0)
-#define bfin_write_CAN1_MB31_ID0(val)           bfin_write16(CAN1_MB31_ID0, val)
-#define bfin_read_CAN1_MB31_ID1()               bfin_read16(CAN1_MB31_ID1)
-#define bfin_write_CAN1_MB31_ID1(val)           bfin_write16(CAN1_MB31_ID1, val)
-
-/* ATAPI Registers */
-
-#define bfin_read_ATAPI_CONTROL()               bfin_read16(ATAPI_CONTROL)
-#define bfin_write_ATAPI_CONTROL(val)           bfin_write16(ATAPI_CONTROL, val)
-#define bfin_read_ATAPI_STATUS()                bfin_read16(ATAPI_STATUS)
-#define bfin_write_ATAPI_STATUS(val)            bfin_write16(ATAPI_STATUS, val)
-#define bfin_read_ATAPI_DEV_ADDR()              bfin_read16(ATAPI_DEV_ADDR)
-#define bfin_write_ATAPI_DEV_ADDR(val)          bfin_write16(ATAPI_DEV_ADDR, val)
-#define bfin_read_ATAPI_DEV_TXBUF()             bfin_read16(ATAPI_DEV_TXBUF)
-#define bfin_write_ATAPI_DEV_TXBUF(val)         bfin_write16(ATAPI_DEV_TXBUF, val)
-#define bfin_read_ATAPI_DEV_RXBUF()             bfin_read16(ATAPI_DEV_RXBUF)
-#define bfin_write_ATAPI_DEV_RXBUF(val)         bfin_write16(ATAPI_DEV_RXBUF, val)
-#define bfin_read_ATAPI_INT_MASK()              bfin_read16(ATAPI_INT_MASK)
-#define bfin_write_ATAPI_INT_MASK(val)          bfin_write16(ATAPI_INT_MASK, val)
-#define bfin_read_ATAPI_INT_STATUS()            bfin_read16(ATAPI_INT_STATUS)
-#define bfin_write_ATAPI_INT_STATUS(val)        bfin_write16(ATAPI_INT_STATUS, val)
-#define bfin_read_ATAPI_XFER_LEN()              bfin_read16(ATAPI_XFER_LEN)
-#define bfin_write_ATAPI_XFER_LEN(val)          bfin_write16(ATAPI_XFER_LEN, val)
-#define bfin_read_ATAPI_LINE_STATUS()           bfin_read16(ATAPI_LINE_STATUS)
-#define bfin_write_ATAPI_LINE_STATUS(val)       bfin_write16(ATAPI_LINE_STATUS, val)
-#define bfin_read_ATAPI_SM_STATE()              bfin_read16(ATAPI_SM_STATE)
-#define bfin_write_ATAPI_SM_STATE(val)          bfin_write16(ATAPI_SM_STATE, val)
-#define bfin_read_ATAPI_TERMINATE()             bfin_read16(ATAPI_TERMINATE)
-#define bfin_write_ATAPI_TERMINATE(val)         bfin_write16(ATAPI_TERMINATE, val)
-#define bfin_read_ATAPI_PIO_TFRCNT()            bfin_read16(ATAPI_PIO_TFRCNT)
-#define bfin_write_ATAPI_PIO_TFRCNT(val)        bfin_write16(ATAPI_PIO_TFRCNT, val)
-#define bfin_read_ATAPI_DMA_TFRCNT()            bfin_read16(ATAPI_DMA_TFRCNT)
-#define bfin_write_ATAPI_DMA_TFRCNT(val)        bfin_write16(ATAPI_DMA_TFRCNT, val)
-#define bfin_read_ATAPI_UMAIN_TFRCNT()          bfin_read16(ATAPI_UMAIN_TFRCNT)
-#define bfin_write_ATAPI_UMAIN_TFRCNT(val)      bfin_write16(ATAPI_UMAIN_TFRCNT, val)
-#define bfin_read_ATAPI_UDMAOUT_TFRCNT()        bfin_read16(ATAPI_UDMAOUT_TFRCNT)
-#define bfin_write_ATAPI_UDMAOUT_TFRCNT(val)    bfin_write16(ATAPI_UDMAOUT_TFRCNT, val)
-#define bfin_read_ATAPI_REG_TIM_0()             bfin_read16(ATAPI_REG_TIM_0)
-#define bfin_write_ATAPI_REG_TIM_0(val)         bfin_write16(ATAPI_REG_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_0()             bfin_read16(ATAPI_PIO_TIM_0)
-#define bfin_write_ATAPI_PIO_TIM_0(val)         bfin_write16(ATAPI_PIO_TIM_0, val)
-#define bfin_read_ATAPI_PIO_TIM_1()             bfin_read16(ATAPI_PIO_TIM_1)
-#define bfin_write_ATAPI_PIO_TIM_1(val)         bfin_write16(ATAPI_PIO_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_0()           bfin_read16(ATAPI_MULTI_TIM_0)
-#define bfin_write_ATAPI_MULTI_TIM_0(val)       bfin_write16(ATAPI_MULTI_TIM_0, val)
-#define bfin_read_ATAPI_MULTI_TIM_1()           bfin_read16(ATAPI_MULTI_TIM_1)
-#define bfin_write_ATAPI_MULTI_TIM_1(val)       bfin_write16(ATAPI_MULTI_TIM_1, val)
-#define bfin_read_ATAPI_MULTI_TIM_2()           bfin_read16(ATAPI_MULTI_TIM_2)
-#define bfin_write_ATAPI_MULTI_TIM_2(val)       bfin_write16(ATAPI_MULTI_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_0()           bfin_read16(ATAPI_ULTRA_TIM_0)
-#define bfin_write_ATAPI_ULTRA_TIM_0(val)       bfin_write16(ATAPI_ULTRA_TIM_0, val)
-#define bfin_read_ATAPI_ULTRA_TIM_1()           bfin_read16(ATAPI_ULTRA_TIM_1)
-#define bfin_write_ATAPI_ULTRA_TIM_1(val)       bfin_write16(ATAPI_ULTRA_TIM_1, val)
-#define bfin_read_ATAPI_ULTRA_TIM_2()           bfin_read16(ATAPI_ULTRA_TIM_2)
-#define bfin_write_ATAPI_ULTRA_TIM_2(val)       bfin_write16(ATAPI_ULTRA_TIM_2, val)
-#define bfin_read_ATAPI_ULTRA_TIM_3()           bfin_read16(ATAPI_ULTRA_TIM_3)
-#define bfin_write_ATAPI_ULTRA_TIM_3(val)       bfin_write16(ATAPI_ULTRA_TIM_3, val)
-
-/* SDH Registers */
-
-#define bfin_read_SDH_PWR_CTL()         bfin_read16(SDH_PWR_CTL)
-#define bfin_write_SDH_PWR_CTL(val)     bfin_write16(SDH_PWR_CTL, val)
-#define bfin_read_SDH_CLK_CTL()         bfin_read16(SDH_CLK_CTL)
-#define bfin_write_SDH_CLK_CTL(val)     bfin_write16(SDH_CLK_CTL, val)
-#define bfin_read_SDH_ARGUMENT()        bfin_read32(SDH_ARGUMENT)
-#define bfin_write_SDH_ARGUMENT(val)    bfin_write32(SDH_ARGUMENT, val)
-#define bfin_read_SDH_COMMAND()         bfin_read16(SDH_COMMAND)
-#define bfin_write_SDH_COMMAND(val)     bfin_write16(SDH_COMMAND, val)
-#define bfin_read_SDH_RESP_CMD()        bfin_read16(SDH_RESP_CMD)
-#define bfin_write_SDH_RESP_CMD(val)    bfin_write16(SDH_RESP_CMD, val)
-#define bfin_read_SDH_RESPONSE0()       bfin_read32(SDH_RESPONSE0)
-#define bfin_write_SDH_RESPONSE0(val)   bfin_write32(SDH_RESPONSE0, val)
-#define bfin_read_SDH_RESPONSE1()       bfin_read32(SDH_RESPONSE1)
-#define bfin_write_SDH_RESPONSE1(val)   bfin_write32(SDH_RESPONSE1, val)
-#define bfin_read_SDH_RESPONSE2()       bfin_read32(SDH_RESPONSE2)
-#define bfin_write_SDH_RESPONSE2(val)   bfin_write32(SDH_RESPONSE2, val)
-#define bfin_read_SDH_RESPONSE3()       bfin_read32(SDH_RESPONSE3)
-#define bfin_write_SDH_RESPONSE3(val)   bfin_write32(SDH_RESPONSE3, val)
-#define bfin_read_SDH_DATA_TIMER()      bfin_read32(SDH_DATA_TIMER)
-#define bfin_write_SDH_DATA_TIMER(val)  bfin_write32(SDH_DATA_TIMER, val)
-#define bfin_read_SDH_DATA_LGTH()       bfin_read16(SDH_DATA_LGTH)
-#define bfin_write_SDH_DATA_LGTH(val)   bfin_write16(SDH_DATA_LGTH, val)
-#define bfin_read_SDH_DATA_CTL()        bfin_read16(SDH_DATA_CTL)
-#define bfin_write_SDH_DATA_CTL(val)    bfin_write16(SDH_DATA_CTL, val)
-#define bfin_read_SDH_DATA_CNT()        bfin_read16(SDH_DATA_CNT)
-#define bfin_write_SDH_DATA_CNT(val)    bfin_write16(SDH_DATA_CNT, val)
-#define bfin_read_SDH_STATUS()          bfin_read32(SDH_STATUS)
-#define bfin_write_SDH_STATUS(val)      bfin_write32(SDH_STATUS, val)
-#define bfin_read_SDH_STATUS_CLR()      bfin_read16(SDH_STATUS_CLR)
-#define bfin_write_SDH_STATUS_CLR(val)  bfin_write16(SDH_STATUS_CLR, val)
-#define bfin_read_SDH_MASK0()           bfin_read32(SDH_MASK0)
-#define bfin_write_SDH_MASK0(val)       bfin_write32(SDH_MASK0, val)
-#define bfin_read_SDH_MASK1()           bfin_read32(SDH_MASK1)
-#define bfin_write_SDH_MASK1(val)       bfin_write32(SDH_MASK1, val)
-#define bfin_read_SDH_FIFO_CNT()        bfin_read16(SDH_FIFO_CNT)
-#define bfin_write_SDH_FIFO_CNT(val)    bfin_write16(SDH_FIFO_CNT, val)
-#define bfin_read_SDH_FIFO()            bfin_read32(SDH_FIFO)
-#define bfin_write_SDH_FIFO(val)        bfin_write32(SDH_FIFO, val)
-#define bfin_read_SDH_E_STATUS()        bfin_read16(SDH_E_STATUS)
-#define bfin_write_SDH_E_STATUS(val)    bfin_write16(SDH_E_STATUS, val)
-#define bfin_read_SDH_E_MASK()          bfin_read16(SDH_E_MASK)
-#define bfin_write_SDH_E_MASK(val)      bfin_write16(SDH_E_MASK, val)
-#define bfin_read_SDH_CFG()             bfin_read16(SDH_CFG)
-#define bfin_write_SDH_CFG(val)         bfin_write16(SDH_CFG, val)
-#define bfin_read_SDH_RD_WAIT_EN()      bfin_read16(SDH_RD_WAIT_EN)
-#define bfin_write_SDH_RD_WAIT_EN(val)  bfin_write16(SDH_RD_WAIT_EN, val)
-#define bfin_read_SDH_PID0()            bfin_read16(SDH_PID0)
-#define bfin_write_SDH_PID0(val)        bfin_write16(SDH_PID0, val)
-#define bfin_read_SDH_PID1()            bfin_read16(SDH_PID1)
-#define bfin_write_SDH_PID1(val)        bfin_write16(SDH_PID1, val)
-#define bfin_read_SDH_PID2()            bfin_read16(SDH_PID2)
-#define bfin_write_SDH_PID2(val)        bfin_write16(SDH_PID2, val)
-#define bfin_read_SDH_PID3()            bfin_read16(SDH_PID3)
-#define bfin_write_SDH_PID3(val)        bfin_write16(SDH_PID3, val)
-#define bfin_read_SDH_PID4()            bfin_read16(SDH_PID4)
-#define bfin_write_SDH_PID4(val)        bfin_write16(SDH_PID4, val)
-#define bfin_read_SDH_PID5()            bfin_read16(SDH_PID5)
-#define bfin_write_SDH_PID5(val)        bfin_write16(SDH_PID5, val)
-#define bfin_read_SDH_PID6()            bfin_read16(SDH_PID6)
-#define bfin_write_SDH_PID6(val)        bfin_write16(SDH_PID6, val)
-#define bfin_read_SDH_PID7()            bfin_read16(SDH_PID7)
-#define bfin_write_SDH_PID7(val)        bfin_write16(SDH_PID7, val)
-
-/* HOST Port Registers */
-
-#define bfin_read_HOST_CONTROL()        bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)    bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()         bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)     bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()        bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)    bfin_write16(HOST_TIMEOUT, val)
-
-/* USB Control Registers */
-
-#define bfin_read_USB_FADDR()           bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)       bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()           bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)       bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()          bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)      bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()          bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)      bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()         bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)     bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()         bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)     bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()         bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)     bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()        bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)    bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()           bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)       bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()           bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)       bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()        bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)    bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()        bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)    bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()      bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val)  bfin_write16(USB_GLOBAL_CTL, val)
-
-/* USB Packet Control Registers */
-
-#define bfin_read_USB_TX_MAX_PACKET()           bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val)       bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()                    bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)                bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()                   bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)               bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()           bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val)       bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()                   bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)               bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()                  bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)              bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()                 bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)             bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()                  bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)              bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()               bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)           bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()              bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val)          bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()                  bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)              bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()              bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val)          bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()                 bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)             bfin_write16(USB_TXCOUNT, val)
-
-/* USB Endbfin_read_()oint FIFO Registers */
-
-#define bfin_read_USB_EP0_FIFO()                bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)            bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()                bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)            bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()                bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)            bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()                bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)            bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()                bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)            bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()                bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)            bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()                bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)            bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()                bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)            bfin_write16(USB_EP7_FIFO, val)
-
-/* USB OTG Control Registers */
-
-#define bfin_read_USB_OTG_DEV_CTL()             bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val)         bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()            bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val)        bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()           bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val)       bfin_write16(USB_OTG_VBUS_MASK, val)
-
-/* USB Phy Control Registers */
-
-#define bfin_read_USB_LINKINFO()                bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)            bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()                   bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)               bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()                 bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)             bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()                 bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)             bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()                 bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)             bfin_write16(USB_LS_EOF1, val)
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CNTRL()              bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val)          bfin_write16(USB_APHY_CNTRL, val)
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define bfin_read_USB_APHY_CALIB()              bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val)          bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()             bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val)         bfin_write16(USB_APHY_CNTRL2, val)
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define bfin_read_USB_PHY_TEST()                bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)            bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()             bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val)         bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()              bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val)          bfin_write16(USB_SRP_CLKDIV, val)
-
-/* USB Endbfin_read_()oint 0 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXMAXP()           bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val)       bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()            bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val)        bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()           bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val)       bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()            bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val)        bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT()          bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val)      bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()           bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val)       bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL()       bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val)   bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()           bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val)       bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL()       bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val)   bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 1 Control Registers */
-
-#define bfin_read_USB_EP_NI0_TXCOUNT()          bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val)      bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()           bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val)       bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()            bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val)        bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()           bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val)       bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()            bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val)        bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT()          bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val)      bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()           bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val)       bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL()       bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val)   bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()           bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val)       bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL()       bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val)   bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 2 Control Registers */
-
-#define bfin_read_USB_EP_NI1_TXCOUNT()          bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val)      bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()           bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val)       bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()            bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val)        bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()           bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val)       bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()            bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val)        bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT()          bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val)      bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()           bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val)       bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL()       bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val)   bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()           bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val)       bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL()       bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val)   bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 3 Control Registers */
-
-#define bfin_read_USB_EP_NI2_TXCOUNT()          bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val)      bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()           bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val)       bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()            bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val)        bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()           bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val)       bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()            bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val)        bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT()          bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val)      bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()           bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val)       bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL()       bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val)   bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()           bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val)       bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL()       bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val)   bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 4 Control Registers */
-
-#define bfin_read_USB_EP_NI3_TXCOUNT()          bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val)      bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()           bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val)       bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()            bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val)        bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()           bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val)       bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()            bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val)        bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT()          bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val)      bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()           bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val)       bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL()       bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val)   bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()           bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val)       bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL()       bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val)   bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 5 Control Registers */
-
-#define bfin_read_USB_EP_NI4_TXCOUNT()          bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val)      bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()           bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val)       bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()            bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val)        bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()           bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val)       bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()            bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val)        bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT()          bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val)      bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()           bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val)       bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL()       bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val)   bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()           bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val)       bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL()       bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val)   bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 6 Control Registers */
-
-#define bfin_read_USB_EP_NI5_TXCOUNT()          bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val)      bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()           bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val)       bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()            bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val)        bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()           bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val)       bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()            bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val)        bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT()          bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val)      bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()           bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val)       bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL()       bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val)   bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()           bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val)       bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL()       bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val)   bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-
-/* USB Endbfin_read_()oint 7 Control Registers */
-
-#define bfin_read_USB_EP_NI6_TXCOUNT()          bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val)      bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()           bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val)       bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()            bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val)        bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()           bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val)       bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()            bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val)        bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT()          bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val)      bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()           bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val)       bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL()       bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val)   bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()           bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val)       bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL()       bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val)   bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT()          bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val)      bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()           bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val)       bfin_write16(USB_DMA_INTERRUPT, val)
-
-/* USB Channel 0 Config Registers */
-
-#define bfin_read_USB_DMA0CONTROL()             bfin_read16(USB_DMA0CONTROL)
-#define bfin_write_USB_DMA0CONTROL(val)         bfin_write16(USB_DMA0CONTROL, val)
-#define bfin_read_USB_DMA0ADDRLOW()             bfin_read16(USB_DMA0ADDRLOW)
-#define bfin_write_USB_DMA0ADDRLOW(val)         bfin_write16(USB_DMA0ADDRLOW, val)
-#define bfin_read_USB_DMA0ADDRHIGH()            bfin_read16(USB_DMA0ADDRHIGH)
-#define bfin_write_USB_DMA0ADDRHIGH(val)        bfin_write16(USB_DMA0ADDRHIGH, val)
-#define bfin_read_USB_DMA0COUNTLOW()            bfin_read16(USB_DMA0COUNTLOW)
-#define bfin_write_USB_DMA0COUNTLOW(val)        bfin_write16(USB_DMA0COUNTLOW, val)
-#define bfin_read_USB_DMA0COUNTHIGH()           bfin_read16(USB_DMA0COUNTHIGH)
-#define bfin_write_USB_DMA0COUNTHIGH(val)       bfin_write16(USB_DMA0COUNTHIGH, val)
-
-/* USB Channel 1 Config Registers */
-
-#define bfin_read_USB_DMA1CONTROL()             bfin_read16(USB_DMA1CONTROL)
-#define bfin_write_USB_DMA1CONTROL(val)         bfin_write16(USB_DMA1CONTROL, val)
-#define bfin_read_USB_DMA1ADDRLOW()             bfin_read16(USB_DMA1ADDRLOW)
-#define bfin_write_USB_DMA1ADDRLOW(val)         bfin_write16(USB_DMA1ADDRLOW, val)
-#define bfin_read_USB_DMA1ADDRHIGH()            bfin_read16(USB_DMA1ADDRHIGH)
-#define bfin_write_USB_DMA1ADDRHIGH(val)        bfin_write16(USB_DMA1ADDRHIGH, val)
-#define bfin_read_USB_DMA1COUNTLOW()            bfin_read16(USB_DMA1COUNTLOW)
-#define bfin_write_USB_DMA1COUNTLOW(val)        bfin_write16(USB_DMA1COUNTLOW, val)
-#define bfin_read_USB_DMA1COUNTHIGH()           bfin_read16(USB_DMA1COUNTHIGH)
-#define bfin_write_USB_DMA1COUNTHIGH(val)       bfin_write16(USB_DMA1COUNTHIGH, val)
-
-/* USB Channel 2 Config Registers */
-
-#define bfin_read_USB_DMA2CONTROL()             bfin_read16(USB_DMA2CONTROL)
-#define bfin_write_USB_DMA2CONTROL(val)         bfin_write16(USB_DMA2CONTROL, val)
-#define bfin_read_USB_DMA2ADDRLOW()             bfin_read16(USB_DMA2ADDRLOW)
-#define bfin_write_USB_DMA2ADDRLOW(val)         bfin_write16(USB_DMA2ADDRLOW, val)
-#define bfin_read_USB_DMA2ADDRHIGH()            bfin_read16(USB_DMA2ADDRHIGH)
-#define bfin_write_USB_DMA2ADDRHIGH(val)        bfin_write16(USB_DMA2ADDRHIGH, val)
-#define bfin_read_USB_DMA2COUNTLOW()            bfin_read16(USB_DMA2COUNTLOW)
-#define bfin_write_USB_DMA2COUNTLOW(val)        bfin_write16(USB_DMA2COUNTLOW, val)
-#define bfin_read_USB_DMA2COUNTHIGH()           bfin_read16(USB_DMA2COUNTHIGH)
-#define bfin_write_USB_DMA2COUNTHIGH(val)       bfin_write16(USB_DMA2COUNTHIGH, val)
-
-/* USB Channel 3 Config Registers */
-
-#define bfin_read_USB_DMA3CONTROL()             bfin_read16(USB_DMA3CONTROL)
-#define bfin_write_USB_DMA3CONTROL(val)         bfin_write16(USB_DMA3CONTROL, val)
-#define bfin_read_USB_DMA3ADDRLOW()             bfin_read16(USB_DMA3ADDRLOW)
-#define bfin_write_USB_DMA3ADDRLOW(val)         bfin_write16(USB_DMA3ADDRLOW, val)
-#define bfin_read_USB_DMA3ADDRHIGH()            bfin_read16(USB_DMA3ADDRHIGH)
-#define bfin_write_USB_DMA3ADDRHIGH(val)        bfin_write16(USB_DMA3ADDRHIGH, val)
-#define bfin_read_USB_DMA3COUNTLOW()            bfin_read16(USB_DMA3COUNTLOW)
-#define bfin_write_USB_DMA3COUNTLOW(val)        bfin_write16(USB_DMA3COUNTLOW, val)
-#define bfin_read_USB_DMA3COUNTHIGH()           bfin_read16(USB_DMA3COUNTHIGH)
-#define bfin_write_USB_DMA3COUNTHIGH(val)       bfin_write16(USB_DMA3COUNTHIGH, val)
-
-/* USB Channel 4 Config Registers */
-
-#define bfin_read_USB_DMA4CONTROL()             bfin_read16(USB_DMA4CONTROL)
-#define bfin_write_USB_DMA4CONTROL(val)         bfin_write16(USB_DMA4CONTROL, val)
-#define bfin_read_USB_DMA4ADDRLOW()             bfin_read16(USB_DMA4ADDRLOW)
-#define bfin_write_USB_DMA4ADDRLOW(val)         bfin_write16(USB_DMA4ADDRLOW, val)
-#define bfin_read_USB_DMA4ADDRHIGH()            bfin_read16(USB_DMA4ADDRHIGH)
-#define bfin_write_USB_DMA4ADDRHIGH(val)        bfin_write16(USB_DMA4ADDRHIGH, val)
-#define bfin_read_USB_DMA4COUNTLOW()            bfin_read16(USB_DMA4COUNTLOW)
-#define bfin_write_USB_DMA4COUNTLOW(val)        bfin_write16(USB_DMA4COUNTLOW, val)
-#define bfin_read_USB_DMA4COUNTHIGH()           bfin_read16(USB_DMA4COUNTHIGH)
-#define bfin_write_USB_DMA4COUNTHIGH(val)       bfin_write16(USB_DMA4COUNTHIGH, val)
-
-/* USB Channel 5 Config Registers */
-
-#define bfin_read_USB_DMA5CONTROL()             bfin_read16(USB_DMA5CONTROL)
-#define bfin_write_USB_DMA5CONTROL(val)         bfin_write16(USB_DMA5CONTROL, val)
-#define bfin_read_USB_DMA5ADDRLOW()             bfin_read16(USB_DMA5ADDRLOW)
-#define bfin_write_USB_DMA5ADDRLOW(val)         bfin_write16(USB_DMA5ADDRLOW, val)
-#define bfin_read_USB_DMA5ADDRHIGH()            bfin_read16(USB_DMA5ADDRHIGH)
-#define bfin_write_USB_DMA5ADDRHIGH(val)                bfin_write16(USB_DMA5ADDRHIGH, val)
-#define bfin_read_USB_DMA5COUNTLOW()            bfin_read16(USB_DMA5COUNTLOW)
-#define bfin_write_USB_DMA5COUNTLOW(val)        bfin_write16(USB_DMA5COUNTLOW, val)
-#define bfin_read_USB_DMA5COUNTHIGH()           bfin_read16(USB_DMA5COUNTHIGH)
-#define bfin_write_USB_DMA5COUNTHIGH(val)       bfin_write16(USB_DMA5COUNTHIGH, val)
-
-/* USB Channel 6 Config Registers */
-
-#define bfin_read_USB_DMA6CONTROL()             bfin_read16(USB_DMA6CONTROL)
-#define bfin_write_USB_DMA6CONTROL(val)         bfin_write16(USB_DMA6CONTROL, val)
-#define bfin_read_USB_DMA6ADDRLOW()             bfin_read16(USB_DMA6ADDRLOW)
-#define bfin_write_USB_DMA6ADDRLOW(val)         bfin_write16(USB_DMA6ADDRLOW, val)
-#define bfin_read_USB_DMA6ADDRHIGH()            bfin_read16(USB_DMA6ADDRHIGH)
-#define bfin_write_USB_DMA6ADDRHIGH(val)        bfin_write16(USB_DMA6ADDRHIGH, val)
-#define bfin_read_USB_DMA6COUNTLOW()            bfin_read16(USB_DMA6COUNTLOW)
-#define bfin_write_USB_DMA6COUNTLOW(val)        bfin_write16(USB_DMA6COUNTLOW, val)
-#define bfin_read_USB_DMA6COUNTHIGH()           bfin_read16(USB_DMA6COUNTHIGH)
-#define bfin_write_USB_DMA6COUNTHIGH(val)       bfin_write16(USB_DMA6COUNTHIGH, val)
-
-/* USB Channel 7 Config Registers */
-
-#define bfin_read_USB_DMA7CONTROL()             bfin_read16(USB_DMA7CONTROL)
-#define bfin_write_USB_DMA7CONTROL(val)         bfin_write16(USB_DMA7CONTROL, val)
-#define bfin_read_USB_DMA7ADDRLOW()             bfin_read16(USB_DMA7ADDRLOW)
-#define bfin_write_USB_DMA7ADDRLOW(val)         bfin_write16(USB_DMA7ADDRLOW, val)
-#define bfin_read_USB_DMA7ADDRHIGH()            bfin_read16(USB_DMA7ADDRHIGH)
-#define bfin_write_USB_DMA7ADDRHIGH(val)        bfin_write16(USB_DMA7ADDRHIGH, val)
-#define bfin_read_USB_DMA7COUNTLOW()            bfin_read16(USB_DMA7COUNTLOW)
-#define bfin_write_USB_DMA7COUNTLOW(val)        bfin_write16(USB_DMA7COUNTLOW, val)
-#define bfin_read_USB_DMA7COUNTHIGH()           bfin_read16(USB_DMA7COUNTHIGH)
-#define bfin_write_USB_DMA7COUNTHIGH(val)       bfin_write16(USB_DMA7COUNTHIGH, val)
-
-/* Keybfin_read_()ad Registers */
-
-#define bfin_read_KPAD_CTL()            bfin_read16(KPAD_CTL)
-#define bfin_write_KPAD_CTL(val)        bfin_write16(KPAD_CTL, val)
-#define bfin_read_KPAD_PRESCALE()       bfin_read16(KPAD_PRESCALE)
-#define bfin_write_KPAD_PRESCALE(val)   bfin_write16(KPAD_PRESCALE, val)
-#define bfin_read_KPAD_MSEL()           bfin_read16(KPAD_MSEL)
-#define bfin_write_KPAD_MSEL(val)       bfin_write16(KPAD_MSEL, val)
-#define bfin_read_KPAD_ROWCOL()         bfin_read16(KPAD_ROWCOL)
-#define bfin_write_KPAD_ROWCOL(val)     bfin_write16(KPAD_ROWCOL, val)
-#define bfin_read_KPAD_STAT()           bfin_read16(KPAD_STAT)
-#define bfin_write_KPAD_STAT(val)       bfin_write16(KPAD_STAT, val)
-#define bfin_read_KPAD_SOFTEVAL()       bfin_read16(KPAD_SOFTEVAL)
-#define bfin_write_KPAD_SOFTEVAL(val)   bfin_write16(KPAD_SOFTEVAL, val)
-
-/* Pixel Combfin_read_()ositor (PIXC) Registers */
-
-#define bfin_read_PIXC_CTL()            bfin_read16(PIXC_CTL)
-#define bfin_write_PIXC_CTL(val)        bfin_write16(PIXC_CTL, val)
-#define bfin_read_PIXC_PPL()            bfin_read16(PIXC_PPL)
-#define bfin_write_PIXC_PPL(val)        bfin_write16(PIXC_PPL, val)
-#define bfin_read_PIXC_LPF()            bfin_read16(PIXC_LPF)
-#define bfin_write_PIXC_LPF(val)        bfin_write16(PIXC_LPF, val)
-#define bfin_read_PIXC_AHSTART()        bfin_read16(PIXC_AHSTART)
-#define bfin_write_PIXC_AHSTART(val)    bfin_write16(PIXC_AHSTART, val)
-#define bfin_read_PIXC_AHEND()          bfin_read16(PIXC_AHEND)
-#define bfin_write_PIXC_AHEND(val)      bfin_write16(PIXC_AHEND, val)
-#define bfin_read_PIXC_AVSTART()        bfin_read16(PIXC_AVSTART)
-#define bfin_write_PIXC_AVSTART(val)    bfin_write16(PIXC_AVSTART, val)
-#define bfin_read_PIXC_AVEND()          bfin_read16(PIXC_AVEND)
-#define bfin_write_PIXC_AVEND(val)      bfin_write16(PIXC_AVEND, val)
-#define bfin_read_PIXC_ATRANSP()        bfin_read16(PIXC_ATRANSP)
-#define bfin_write_PIXC_ATRANSP(val)    bfin_write16(PIXC_ATRANSP, val)
-#define bfin_read_PIXC_BHSTART()        bfin_read16(PIXC_BHSTART)
-#define bfin_write_PIXC_BHSTART(val)    bfin_write16(PIXC_BHSTART, val)
-#define bfin_read_PIXC_BHEND()          bfin_read16(PIXC_BHEND)
-#define bfin_write_PIXC_BHEND(val)      bfin_write16(PIXC_BHEND, val)
-#define bfin_read_PIXC_BVSTART()        bfin_read16(PIXC_BVSTART)
-#define bfin_write_PIXC_BVSTART(val)    bfin_write16(PIXC_BVSTART, val)
-#define bfin_read_PIXC_BVEND()          bfin_read16(PIXC_BVEND)
-#define bfin_write_PIXC_BVEND(val)      bfin_write16(PIXC_BVEND, val)
-#define bfin_read_PIXC_BTRANSP()        bfin_read16(PIXC_BTRANSP)
-#define bfin_write_PIXC_BTRANSP(val)    bfin_write16(PIXC_BTRANSP, val)
-#define bfin_read_PIXC_INTRSTAT()       bfin_read16(PIXC_INTRSTAT)
-#define bfin_write_PIXC_INTRSTAT(val)   bfin_write16(PIXC_INTRSTAT, val)
-#define bfin_read_PIXC_RYCON()          bfin_read32(PIXC_RYCON)
-#define bfin_write_PIXC_RYCON(val)      bfin_write32(PIXC_RYCON, val)
-#define bfin_read_PIXC_GUCON()          bfin_read32(PIXC_GUCON)
-#define bfin_write_PIXC_GUCON(val)      bfin_write32(PIXC_GUCON, val)
-#define bfin_read_PIXC_BVCON()          bfin_read32(PIXC_BVCON)
-#define bfin_write_PIXC_BVCON(val)      bfin_write32(PIXC_BVCON, val)
-#define bfin_read_PIXC_CCBIAS()         bfin_read32(PIXC_CCBIAS)
-#define bfin_write_PIXC_CCBIAS(val)     bfin_write32(PIXC_CCBIAS, val)
-#define bfin_read_PIXC_TC()             bfin_read32(PIXC_TC)
-#define bfin_write_PIXC_TC(val)         bfin_write32(PIXC_TC, val)
-
-/* Handshake MDMA 0 Registers */
-
-#define bfin_read_HMDMA0_CONTROL()              bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val)          bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()               bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)           bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()               bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)           bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()             bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val)         bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()           bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val)       bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()               bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)           bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()               bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)           bfin_write16(HMDMA0_BCOUNT, val)
-
-/* Handshake MDMA 1 Registers */
-
-#define bfin_read_HMDMA1_CONTROL()              bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val)          bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()               bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)           bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()               bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)           bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()             bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val)         bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()           bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val)       bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()               bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)           bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()               bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)           bfin_write16(HMDMA1_BCOUNT, val)
-
-#endif /* _CDEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h b/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
deleted file mode 100644
index 57ac8cb9b1f6..000000000000
--- a/include/asm-blackfin/mach-bf548/cdefBF54x_base.h
+++ /dev/null
@@ -1,2750 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/cdefBF54x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF54X_H
-#define _CDEF_BF54X_H
-
-#include <asm/blackfin.h>
-
-#include "defBF54x_base.h"
-#include <asm/system.h>
-
-/* ************************************************************** */
-/* SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define bfin_read_PLL_CTL()             bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()             bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)         bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()              bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1, iwr2;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SIC_IWR0);
-        iwr1 = bfin_read32(SIC_IWR1);
-        iwr2 = bfin_read32(SIC_IWR2);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SIC_IWR0, IWR_ENABLE(0));
-        bfin_write32(SIC_IWR1, 0);
-        bfin_write32(SIC_IWR2, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SIC_IWR0, iwr0);
-        bfin_write32(SIC_IWR1, iwr1);
-        bfin_write32(SIC_IWR2, iwr2);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()            bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)        bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()         bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)     bfin_write16(PLL_LOCKCNT, val)
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define bfin_read_CHIPID()              bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)          bfin_write32(CHIPID, val)
-
-/* System Reset and Interrubfin_read_()t Controller (0xFFC00100 - 0xFFC00104) */
-
-#define bfin_read_SWRST()               bfin_read16(SWRST)
-#define bfin_write_SWRST(val)           bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()               bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)           bfin_write16(SYSCR, val)
-
-/* SIC Registers */
-
-#define bfin_read_SIC_IMASK0()          bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)      bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IMASK1()          bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)      bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IMASK2()          bfin_read32(SIC_IMASK2)
-#define bfin_write_SIC_IMASK2(val)      bfin_write32(SIC_IMASK2, val)
-#define bfin_read_SIC_IMASK(x)          bfin_read32(SIC_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val)    bfin_write32((SIC_IMASK0 + (x << 2)), val)
-
-#define bfin_read_SIC_ISR0()            bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)        bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_ISR1()            bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)        bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_ISR2()            bfin_read32(SIC_ISR2)
-#define bfin_write_SIC_ISR2(val)        bfin_write32(SIC_ISR2, val)
-#define bfin_read_SIC_ISR(x)            bfin_read32(SIC_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val)      bfin_write32((SIC_ISR0 + (x << 2)), val)
-
-#define bfin_read_SIC_IWR0()            bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)        bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IWR1()            bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)        bfin_write32(SIC_IWR1, val)
-#define bfin_read_SIC_IWR2()            bfin_read32(SIC_IWR2)
-#define bfin_write_SIC_IWR2(val)        bfin_write32(SIC_IWR2, val)
-#define bfin_read_SIC_IAR0()            bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)        bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()            bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)        bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()            bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)        bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()            bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)        bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_IAR4()            bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)        bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()            bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)        bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()            bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)        bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()            bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)        bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_IAR8()            bfin_read32(SIC_IAR8)
-#define bfin_write_SIC_IAR8(val)        bfin_write32(SIC_IAR8, val)
-#define bfin_read_SIC_IAR9()            bfin_read32(SIC_IAR9)
-#define bfin_write_SIC_IAR9(val)        bfin_write32(SIC_IAR9, val)
-#define bfin_read_SIC_IAR10()           bfin_read32(SIC_IAR10)
-#define bfin_write_SIC_IAR10(val)       bfin_write32(SIC_IAR10, val)
-#define bfin_read_SIC_IAR11()           bfin_read32(SIC_IAR11)
-#define bfin_write_SIC_IAR11(val)       bfin_write32(SIC_IAR11, val)
-
-/* Watchdog Timer Registers */
-
-#define bfin_read_WDOG_CTL()            bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)        bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()            bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)        bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()           bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)       bfin_write32(WDOG_STAT, val)
-
-/* RTC Registers */
-
-#define bfin_read_RTC_STAT()            bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)        bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()            bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)        bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()           bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)       bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()           bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)       bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()           bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)       bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()            bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)        bfin_write16(RTC_PREN, val)
-
-/* UART0 Registers */
-
-#define bfin_read_UART0_DLL()           bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)       bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH()           bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)       bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL()          bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)      bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR()           bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)       bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()           bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)       bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()           bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)       bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()           bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)       bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()           bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)       bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET()       bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val)   bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR()     bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR()           bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)       bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()           bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)       bfin_write16(UART0_RBR, val)
-
-/* SPI0 Registers */
-
-#define bfin_read_SPI0_CTL()            bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)        bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()            bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)        bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()           bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)       bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()           bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)       bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()           bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)       bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()           bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)       bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()         bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)     bfin_write16(SPI0_SHADOW, val)
-
-/* Timer Groubfin_read_() of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPORT1 Registers */
-
-#define bfin_read_SPORT1_TCR1()         bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)     bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()         bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)     bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()      bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)  bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()       bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)   bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_read_SPORT1_TX()           bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)       bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()           bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)       bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()         bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)     bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()         bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)     bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()      bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)  bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()       bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)   bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()         bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)     bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()         bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)     bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()        bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)    bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()        bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)    bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()        bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)    bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()        bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)    bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()        bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)    bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()        bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)    bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()        bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)    bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()        bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)    bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()        bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)    bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()        bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)    bfin_write32(SPORT1_MRCS3, val)
-
-/* Asynchronous Memory Control Registers */
-
-#define bfin_read_EBIU_AMGCTL()         bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)     bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()        bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)    bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()        bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)    bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MBSCTL()         bfin_read16(EBIU_MBSCTL)
-#define bfin_write_EBIU_MBSCTL(val)     bfin_write16(EBIU_MBSCTL, val)
-#define bfin_read_EBIU_ARBSTAT()        bfin_read32(EBIU_ARBSTAT)
-#define bfin_write_EBIU_ARBSTAT(val)    bfin_write32(EBIU_ARBSTAT, val)
-#define bfin_read_EBIU_MODE()           bfin_read32(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val)       bfin_write32(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL()           bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val)       bfin_write16(EBIU_FCTL, val)
-
-/* DDR Memory Control Registers */
-
-#define bfin_read_EBIU_DDRCTL0()        bfin_read32(EBIU_DDRCTL0)
-#define bfin_write_EBIU_DDRCTL0(val)    bfin_write32(EBIU_DDRCTL0, val)
-#define bfin_read_EBIU_DDRCTL1()        bfin_read32(EBIU_DDRCTL1)
-#define bfin_write_EBIU_DDRCTL1(val)    bfin_write32(EBIU_DDRCTL1, val)
-#define bfin_read_EBIU_DDRCTL2()        bfin_read32(EBIU_DDRCTL2)
-#define bfin_write_EBIU_DDRCTL2(val)    bfin_write32(EBIU_DDRCTL2, val)
-#define bfin_read_EBIU_DDRCTL3()        bfin_read32(EBIU_DDRCTL3)
-#define bfin_write_EBIU_DDRCTL3(val)    bfin_write32(EBIU_DDRCTL3, val)
-#define bfin_read_EBIU_DDRQUE()         bfin_read32(EBIU_DDRQUE)
-#define bfin_write_EBIU_DDRQUE(val)     bfin_write32(EBIU_DDRQUE, val)
-#define bfin_read_EBIU_ERRADD()         bfin_read32(EBIU_ERRADD)
-#define bfin_write_EBIU_ERRADD(val)     bfin_write32(EBIU_ERRADD, val)
-#define bfin_read_EBIU_ERRMST()         bfin_read16(EBIU_ERRMST)
-#define bfin_write_EBIU_ERRMST(val)     bfin_write16(EBIU_ERRMST, val)
-#define bfin_read_EBIU_RSTCTL()         bfin_read16(EBIU_RSTCTL)
-#define bfin_write_EBIU_RSTCTL(val)     bfin_write16(EBIU_RSTCTL, val)
-
-/* DDR BankRead and Write Count Registers */
-
-#define bfin_read_EBIU_DDRBRC0()        bfin_read32(EBIU_DDRBRC0)
-#define bfin_write_EBIU_DDRBRC0(val)    bfin_write32(EBIU_DDRBRC0, val)
-#define bfin_read_EBIU_DDRBRC1()        bfin_read32(EBIU_DDRBRC1)
-#define bfin_write_EBIU_DDRBRC1(val)    bfin_write32(EBIU_DDRBRC1, val)
-#define bfin_read_EBIU_DDRBRC2()        bfin_read32(EBIU_DDRBRC2)
-#define bfin_write_EBIU_DDRBRC2(val)    bfin_write32(EBIU_DDRBRC2, val)
-#define bfin_read_EBIU_DDRBRC3()        bfin_read32(EBIU_DDRBRC3)
-#define bfin_write_EBIU_DDRBRC3(val)    bfin_write32(EBIU_DDRBRC3, val)
-#define bfin_read_EBIU_DDRBRC4()        bfin_read32(EBIU_DDRBRC4)
-#define bfin_write_EBIU_DDRBRC4(val)    bfin_write32(EBIU_DDRBRC4, val)
-#define bfin_read_EBIU_DDRBRC5()        bfin_read32(EBIU_DDRBRC5)
-#define bfin_write_EBIU_DDRBRC5(val)    bfin_write32(EBIU_DDRBRC5, val)
-#define bfin_read_EBIU_DDRBRC6()        bfin_read32(EBIU_DDRBRC6)
-#define bfin_write_EBIU_DDRBRC6(val)    bfin_write32(EBIU_DDRBRC6, val)
-#define bfin_read_EBIU_DDRBRC7()        bfin_read32(EBIU_DDRBRC7)
-#define bfin_write_EBIU_DDRBRC7(val)    bfin_write32(EBIU_DDRBRC7, val)
-#define bfin_read_EBIU_DDRBWC0()        bfin_read32(EBIU_DDRBWC0)
-#define bfin_write_EBIU_DDRBWC0(val)    bfin_write32(EBIU_DDRBWC0, val)
-#define bfin_read_EBIU_DDRBWC1()        bfin_read32(EBIU_DDRBWC1)
-#define bfin_write_EBIU_DDRBWC1(val)    bfin_write32(EBIU_DDRBWC1, val)
-#define bfin_read_EBIU_DDRBWC2()        bfin_read32(EBIU_DDRBWC2)
-#define bfin_write_EBIU_DDRBWC2(val)    bfin_write32(EBIU_DDRBWC2, val)
-#define bfin_read_EBIU_DDRBWC3()        bfin_read32(EBIU_DDRBWC3)
-#define bfin_write_EBIU_DDRBWC3(val)    bfin_write32(EBIU_DDRBWC3, val)
-#define bfin_read_EBIU_DDRBWC4()        bfin_read32(EBIU_DDRBWC4)
-#define bfin_write_EBIU_DDRBWC4(val)    bfin_write32(EBIU_DDRBWC4, val)
-#define bfin_read_EBIU_DDRBWC5()        bfin_read32(EBIU_DDRBWC5)
-#define bfin_write_EBIU_DDRBWC5(val)    bfin_write32(EBIU_DDRBWC5, val)
-#define bfin_read_EBIU_DDRBWC6()        bfin_read32(EBIU_DDRBWC6)
-#define bfin_write_EBIU_DDRBWC6(val)    bfin_write32(EBIU_DDRBWC6, val)
-#define bfin_read_EBIU_DDRBWC7()        bfin_read32(EBIU_DDRBWC7)
-#define bfin_write_EBIU_DDRBWC7(val)    bfin_write32(EBIU_DDRBWC7, val)
-#define bfin_read_EBIU_DDRACCT()        bfin_read32(EBIU_DDRACCT)
-#define bfin_write_EBIU_DDRACCT(val)    bfin_write32(EBIU_DDRACCT, val)
-#define bfin_read_EBIU_DDRTACT()        bfin_read32(EBIU_DDRTACT)
-#define bfin_write_EBIU_DDRTACT(val)    bfin_write32(EBIU_DDRTACT, val)
-#define bfin_read_EBIU_DDRARCT()        bfin_read32(EBIU_DDRARCT)
-#define bfin_write_EBIU_DDRARCT(val)    bfin_write32(EBIU_DDRARCT, val)
-#define bfin_read_EBIU_DDRGC0()         bfin_read32(EBIU_DDRGC0)
-#define bfin_write_EBIU_DDRGC0(val)     bfin_write32(EBIU_DDRGC0, val)
-#define bfin_read_EBIU_DDRGC1()         bfin_read32(EBIU_DDRGC1)
-#define bfin_write_EBIU_DDRGC1(val)     bfin_write32(EBIU_DDRGC1, val)
-#define bfin_read_EBIU_DDRGC2()         bfin_read32(EBIU_DDRGC2)
-#define bfin_write_EBIU_DDRGC2(val)     bfin_write32(EBIU_DDRGC2, val)
-#define bfin_read_EBIU_DDRGC3()         bfin_read32(EBIU_DDRGC3)
-#define bfin_write_EBIU_DDRGC3(val)     bfin_write32(EBIU_DDRGC3, val)
-#define bfin_read_EBIU_DDRMCEN()        bfin_read32(EBIU_DDRMCEN)
-#define bfin_write_EBIU_DDRMCEN(val)    bfin_write32(EBIU_DDRMCEN, val)
-#define bfin_read_EBIU_DDRMCCL()        bfin_read32(EBIU_DDRMCCL)
-#define bfin_write_EBIU_DDRMCCL(val)    bfin_write32(EBIU_DDRMCCL, val)
-
-/* DMAC0 Registers */
-
-#define bfin_read_DMAC0_TCPER()         bfin_read16(DMAC0_TCPER)
-#define bfin_write_DMAC0_TCPER(val)     bfin_write16(DMAC0_TCPER, val)
-#define bfin_read_DMAC0_TCCNT()         bfin_read16(DMAC0_TCCNT)
-#define bfin_write_DMAC0_TCCNT(val)     bfin_write16(DMAC0_TCCNT, val)
-
-/* DMA Channel 0 Registers */
-
-#define bfin_read_DMA0_NEXT_DESC_PTR()          bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val)      bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()             bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val)         bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()                 bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)             bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()                bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)            bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()               bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)           bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()                bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)            bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()               bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)           bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR()          bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val)      bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()              bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val)          bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()             bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val)         bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP()         bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val)     bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()           bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val)       bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()           bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val)       bfin_write16(DMA0_CURR_Y_COUNT, val)
-
-/* DMA Channel 1 Registers */
-
-#define bfin_read_DMA1_NEXT_DESC_PTR()          bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val)      bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()             bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val)         bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()                 bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)             bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()                bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)            bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()               bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)           bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()                bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)            bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()               bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)           bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR()          bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val)      bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()              bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val)          bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()             bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val)         bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP()         bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val)     bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()           bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val)       bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()           bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val)       bfin_write16(DMA1_CURR_Y_COUNT, val)
-
-/* DMA Channel 2 Registers */
-
-#define bfin_read_DMA2_NEXT_DESC_PTR()          bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val)      bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()             bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val)         bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()                 bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)             bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()                bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)            bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()               bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)           bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()                bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)            bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()               bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)           bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR()          bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val)      bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()              bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val)          bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()             bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val)         bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP()         bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val)     bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()           bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val)       bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()           bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val)       bfin_write16(DMA2_CURR_Y_COUNT, val)
-
-/* DMA Channel 3 Registers */
-
-#define bfin_read_DMA3_NEXT_DESC_PTR()          bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val)      bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()             bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val)         bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()                 bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)             bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()                bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)            bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()               bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)           bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()                bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)            bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()               bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)           bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR()          bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val)      bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()              bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val)          bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()             bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val)         bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP()         bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val)     bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()           bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val)       bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()           bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val)       bfin_write16(DMA3_CURR_Y_COUNT, val)
-
-/* DMA Channel 4 Registers */
-
-#define bfin_read_DMA4_NEXT_DESC_PTR()          bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val)      bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()             bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val)         bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()                 bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)             bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()                bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)            bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()               bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)           bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()                bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)            bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()               bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)           bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR()          bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val)      bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()              bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val)          bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()             bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val)         bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP()         bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val)     bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()           bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val)       bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()           bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val)       bfin_write16(DMA4_CURR_Y_COUNT, val)
-
-/* DMA Channel 5 Registers */
-
-#define bfin_read_DMA5_NEXT_DESC_PTR()          bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val)      bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()             bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val)         bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()                 bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)             bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()                bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)            bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()               bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)           bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()                bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)            bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()               bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)           bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR()          bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val)      bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()              bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val)          bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()             bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val)         bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP()         bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val)     bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()           bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val)       bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()           bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val)       bfin_write16(DMA5_CURR_Y_COUNT, val)
-
-/* DMA Channel 6 Registers */
-
-#define bfin_read_DMA6_NEXT_DESC_PTR()          bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val)      bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()             bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val)         bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()                 bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)             bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()                bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)            bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()               bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)           bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()                bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)            bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()               bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)           bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR()          bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val)      bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()              bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val)          bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()             bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val)         bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP()         bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val)     bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()           bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val)       bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()           bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val)       bfin_write16(DMA6_CURR_Y_COUNT, val)
-
-/* DMA Channel 7 Registers */
-
-#define bfin_read_DMA7_NEXT_DESC_PTR()          bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val)      bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()             bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val)         bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()                 bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)             bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()                bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)            bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()               bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)           bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()                bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)            bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()               bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)           bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR()          bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val)      bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()              bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val)          bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()             bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val)         bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP()         bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val)     bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()           bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val)       bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()           bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val)       bfin_write16(DMA7_CURR_Y_COUNT, val)
-
-/* DMA Channel 8 Registers */
-
-#define bfin_read_DMA8_NEXT_DESC_PTR()          bfin_read32(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val)      bfin_write32(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()             bfin_read32(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val)         bfin_write32(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()                 bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)             bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()                bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)            bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()               bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)           bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()                bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)            bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()               bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)           bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR()          bfin_read32(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val)      bfin_write32(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()              bfin_read32(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val)          bfin_write32(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()             bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val)         bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP()         bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val)     bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()           bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val)       bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()           bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val)       bfin_write16(DMA8_CURR_Y_COUNT, val)
-
-/* DMA Channel 9 Registers */
-
-#define bfin_read_DMA9_NEXT_DESC_PTR()          bfin_read32(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val)      bfin_write32(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()             bfin_read32(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val)         bfin_write32(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()                 bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)             bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()                bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)            bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()               bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)           bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()                bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)            bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()               bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)           bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR()          bfin_read32(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val)      bfin_write32(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()              bfin_read32(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val)          bfin_write32(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()             bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val)         bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP()         bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val)     bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()           bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val)       bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()           bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val)       bfin_write16(DMA9_CURR_Y_COUNT, val)
-
-/* DMA Channel 10 Registers */
-
-#define bfin_read_DMA10_NEXT_DESC_PTR()         bfin_read32(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val)     bfin_write32(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()            bfin_read32(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val)        bfin_write32(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()                bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)            bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()               bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)           bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()              bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val)          bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()               bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)           bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()              bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val)          bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR()         bfin_read32(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val)     bfin_write32(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()             bfin_read32(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val)         bfin_write32(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()            bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val)        bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP()        bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val)    bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT()          bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val)      bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT()          bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val)      bfin_write16(DMA10_CURR_Y_COUNT, val)
-
-/* DMA Channel 11 Registers */
-
-#define bfin_read_DMA11_NEXT_DESC_PTR()         bfin_read32(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val)     bfin_write32(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()            bfin_read32(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val)        bfin_write32(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()                bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)            bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()               bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)           bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()              bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val)          bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()               bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)           bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()              bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val)          bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR()         bfin_read32(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val)     bfin_write32(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()             bfin_read32(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val)         bfin_write32(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()            bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val)        bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP()        bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val)    bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT()          bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val)      bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT()          bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val)      bfin_write16(DMA11_CURR_Y_COUNT, val)
-
-/* MDMA Stream 0 Registers */
-
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR()       bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR()          bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val)      bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()              bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val)          bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()             bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val)         bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()            bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val)        bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()             bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val)         bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()            bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val)        bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR()       bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val)   bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()           bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val)       bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()          bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val)      bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP()      bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT()        bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val)    bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT()        bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val)    bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR()       bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR()          bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val)      bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()              bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val)          bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()             bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val)         bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()            bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val)        bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()             bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val)         bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()            bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val)        bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR()       bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val)   bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()           bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val)       bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()          bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val)      bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP()      bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT()        bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val)    bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT()        bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val)    bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-
-/* MDMA Stream 1 Registers */
-
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR()       bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR()          bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val)      bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()              bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val)          bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()             bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val)         bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()            bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val)        bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()             bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val)         bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()            bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val)        bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR()       bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val)   bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()           bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val)       bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS()          bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val)      bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP()      bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT()        bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val)    bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT()        bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val)    bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR()       bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val)   bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR()          bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val)      bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()              bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val)          bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()             bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val)         bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()            bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val)        bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()             bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val)         bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()            bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val)        bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR()       bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val)   bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()           bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val)       bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS()          bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val)      bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP()      bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val)  bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT()        bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val)    bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT()        bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val)    bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-
-/* EPPI1 Registers */
-
-#define bfin_read_EPPI1_STATUS()                bfin_read16(EPPI1_STATUS)
-#define bfin_write_EPPI1_STATUS(val)            bfin_write16(EPPI1_STATUS, val)
-#define bfin_read_EPPI1_HCOUNT()                bfin_read16(EPPI1_HCOUNT)
-#define bfin_write_EPPI1_HCOUNT(val)            bfin_write16(EPPI1_HCOUNT, val)
-#define bfin_read_EPPI1_HDELAY()                bfin_read16(EPPI1_HDELAY)
-#define bfin_write_EPPI1_HDELAY(val)            bfin_write16(EPPI1_HDELAY, val)
-#define bfin_read_EPPI1_VCOUNT()                bfin_read16(EPPI1_VCOUNT)
-#define bfin_write_EPPI1_VCOUNT(val)            bfin_write16(EPPI1_VCOUNT, val)
-#define bfin_read_EPPI1_VDELAY()                bfin_read16(EPPI1_VDELAY)
-#define bfin_write_EPPI1_VDELAY(val)            bfin_write16(EPPI1_VDELAY, val)
-#define bfin_read_EPPI1_FRAME()                 bfin_read16(EPPI1_FRAME)
-#define bfin_write_EPPI1_FRAME(val)             bfin_write16(EPPI1_FRAME, val)
-#define bfin_read_EPPI1_LINE()                  bfin_read16(EPPI1_LINE)
-#define bfin_write_EPPI1_LINE(val)              bfin_write16(EPPI1_LINE, val)
-#define bfin_read_EPPI1_CLKDIV()                bfin_read16(EPPI1_CLKDIV)
-#define bfin_write_EPPI1_CLKDIV(val)            bfin_write16(EPPI1_CLKDIV, val)
-#define bfin_read_EPPI1_CONTROL()               bfin_read32(EPPI1_CONTROL)
-#define bfin_write_EPPI1_CONTROL(val)           bfin_write32(EPPI1_CONTROL, val)
-#define bfin_read_EPPI1_FS1W_HBL()              bfin_read32(EPPI1_FS1W_HBL)
-#define bfin_write_EPPI1_FS1W_HBL(val)          bfin_write32(EPPI1_FS1W_HBL, val)
-#define bfin_read_EPPI1_FS1P_AVPL()             bfin_read32(EPPI1_FS1P_AVPL)
-#define bfin_write_EPPI1_FS1P_AVPL(val)         bfin_write32(EPPI1_FS1P_AVPL, val)
-#define bfin_read_EPPI1_FS2W_LVB()              bfin_read32(EPPI1_FS2W_LVB)
-#define bfin_write_EPPI1_FS2W_LVB(val)          bfin_write32(EPPI1_FS2W_LVB, val)
-#define bfin_read_EPPI1_FS2P_LAVF()             bfin_read32(EPPI1_FS2P_LAVF)
-#define bfin_write_EPPI1_FS2P_LAVF(val)         bfin_write32(EPPI1_FS2P_LAVF, val)
-#define bfin_read_EPPI1_CLIP()                  bfin_read32(EPPI1_CLIP)
-#define bfin_write_EPPI1_CLIP(val)              bfin_write32(EPPI1_CLIP, val)
-
-/* Port Interrubfin_read_()t 0 Registers (32-bit) */
-
-#define bfin_read_PINT0_MASK_SET()              bfin_read32(PINT0_MASK_SET)
-#define bfin_write_PINT0_MASK_SET(val)          bfin_write32(PINT0_MASK_SET, val)
-#define bfin_read_PINT0_MASK_CLEAR()            bfin_read32(PINT0_MASK_CLEAR)
-#define bfin_write_PINT0_MASK_CLEAR(val)        bfin_write32(PINT0_MASK_CLEAR, val)
-#define bfin_read_PINT0_REQUEST()               bfin_read32(PINT0_REQUEST)
-#define bfin_write_PINT0_REQUEST(val)           bfin_write32(PINT0_REQUEST, val)
-#define bfin_read_PINT0_ASSIGN()                bfin_read32(PINT0_ASSIGN)
-#define bfin_write_PINT0_ASSIGN(val)            bfin_write32(PINT0_ASSIGN, val)
-#define bfin_read_PINT0_EDGE_SET()              bfin_read32(PINT0_EDGE_SET)
-#define bfin_write_PINT0_EDGE_SET(val)          bfin_write32(PINT0_EDGE_SET, val)
-#define bfin_read_PINT0_EDGE_CLEAR()            bfin_read32(PINT0_EDGE_CLEAR)
-#define bfin_write_PINT0_EDGE_CLEAR(val)        bfin_write32(PINT0_EDGE_CLEAR, val)
-#define bfin_read_PINT0_INVERT_SET()            bfin_read32(PINT0_INVERT_SET)
-#define bfin_write_PINT0_INVERT_SET(val)        bfin_write32(PINT0_INVERT_SET, val)
-#define bfin_read_PINT0_INVERT_CLEAR()          bfin_read32(PINT0_INVERT_CLEAR)
-#define bfin_write_PINT0_INVERT_CLEAR(val)      bfin_write32(PINT0_INVERT_CLEAR, val)
-#define bfin_read_PINT0_PINSTATE()              bfin_read32(PINT0_PINSTATE)
-#define bfin_write_PINT0_PINSTATE(val)          bfin_write32(PINT0_PINSTATE, val)
-#define bfin_read_PINT0_LATCH()                 bfin_read32(PINT0_LATCH)
-#define bfin_write_PINT0_LATCH(val)             bfin_write32(PINT0_LATCH, val)
-
-/* Port Interrubfin_read_()t 1 Registers (32-bit) */
-
-#define bfin_read_PINT1_MASK_SET()              bfin_read32(PINT1_MASK_SET)
-#define bfin_write_PINT1_MASK_SET(val)          bfin_write32(PINT1_MASK_SET, val)
-#define bfin_read_PINT1_MASK_CLEAR()            bfin_read32(PINT1_MASK_CLEAR)
-#define bfin_write_PINT1_MASK_CLEAR(val)        bfin_write32(PINT1_MASK_CLEAR, val)
-#define bfin_read_PINT1_REQUEST()               bfin_read32(PINT1_REQUEST)
-#define bfin_write_PINT1_REQUEST(val)           bfin_write32(PINT1_REQUEST, val)
-#define bfin_read_PINT1_ASSIGN()                bfin_read32(PINT1_ASSIGN)
-#define bfin_write_PINT1_ASSIGN(val)            bfin_write32(PINT1_ASSIGN, val)
-#define bfin_read_PINT1_EDGE_SET()              bfin_read32(PINT1_EDGE_SET)
-#define bfin_write_PINT1_EDGE_SET(val)          bfin_write32(PINT1_EDGE_SET, val)
-#define bfin_read_PINT1_EDGE_CLEAR()            bfin_read32(PINT1_EDGE_CLEAR)
-#define bfin_write_PINT1_EDGE_CLEAR(val)        bfin_write32(PINT1_EDGE_CLEAR, val)
-#define bfin_read_PINT1_INVERT_SET()            bfin_read32(PINT1_INVERT_SET)
-#define bfin_write_PINT1_INVERT_SET(val)        bfin_write32(PINT1_INVERT_SET, val)
-#define bfin_read_PINT1_INVERT_CLEAR()          bfin_read32(PINT1_INVERT_CLEAR)
-#define bfin_write_PINT1_INVERT_CLEAR(val)      bfin_write32(PINT1_INVERT_CLEAR, val)
-#define bfin_read_PINT1_PINSTATE()              bfin_read32(PINT1_PINSTATE)
-#define bfin_write_PINT1_PINSTATE(val)          bfin_write32(PINT1_PINSTATE, val)
-#define bfin_read_PINT1_LATCH()                 bfin_read32(PINT1_LATCH)
-#define bfin_write_PINT1_LATCH(val)             bfin_write32(PINT1_LATCH, val)
-
-/* Port Interrubfin_read_()t 2 Registers (32-bit) */
-
-#define bfin_read_PINT2_MASK_SET()              bfin_read32(PINT2_MASK_SET)
-#define bfin_write_PINT2_MASK_SET(val)          bfin_write32(PINT2_MASK_SET, val)
-#define bfin_read_PINT2_MASK_CLEAR()            bfin_read32(PINT2_MASK_CLEAR)
-#define bfin_write_PINT2_MASK_CLEAR(val)        bfin_write32(PINT2_MASK_CLEAR, val)
-#define bfin_read_PINT2_REQUEST()               bfin_read32(PINT2_REQUEST)
-#define bfin_write_PINT2_REQUEST(val)           bfin_write32(PINT2_REQUEST, val)
-#define bfin_read_PINT2_ASSIGN()                bfin_read32(PINT2_ASSIGN)
-#define bfin_write_PINT2_ASSIGN(val)            bfin_write32(PINT2_ASSIGN, val)
-#define bfin_read_PINT2_EDGE_SET()              bfin_read32(PINT2_EDGE_SET)
-#define bfin_write_PINT2_EDGE_SET(val)          bfin_write32(PINT2_EDGE_SET, val)
-#define bfin_read_PINT2_EDGE_CLEAR()            bfin_read32(PINT2_EDGE_CLEAR)
-#define bfin_write_PINT2_EDGE_CLEAR(val)        bfin_write32(PINT2_EDGE_CLEAR, val)
-#define bfin_read_PINT2_INVERT_SET()            bfin_read32(PINT2_INVERT_SET)
-#define bfin_write_PINT2_INVERT_SET(val)        bfin_write32(PINT2_INVERT_SET, val)
-#define bfin_read_PINT2_INVERT_CLEAR()          bfin_read32(PINT2_INVERT_CLEAR)
-#define bfin_write_PINT2_INVERT_CLEAR(val)      bfin_write32(PINT2_INVERT_CLEAR, val)
-#define bfin_read_PINT2_PINSTATE()              bfin_read32(PINT2_PINSTATE)
-#define bfin_write_PINT2_PINSTATE(val)          bfin_write32(PINT2_PINSTATE, val)
-#define bfin_read_PINT2_LATCH()                 bfin_read32(PINT2_LATCH)
-#define bfin_write_PINT2_LATCH(val)             bfin_write32(PINT2_LATCH, val)
-
-/* Port Interrubfin_read_()t 3 Registers (32-bit) */
-
-#define bfin_read_PINT3_MASK_SET()              bfin_read32(PINT3_MASK_SET)
-#define bfin_write_PINT3_MASK_SET(val)          bfin_write32(PINT3_MASK_SET, val)
-#define bfin_read_PINT3_MASK_CLEAR()            bfin_read32(PINT3_MASK_CLEAR)
-#define bfin_write_PINT3_MASK_CLEAR(val)        bfin_write32(PINT3_MASK_CLEAR, val)
-#define bfin_read_PINT3_REQUEST()               bfin_read32(PINT3_REQUEST)
-#define bfin_write_PINT3_REQUEST(val)           bfin_write32(PINT3_REQUEST, val)
-#define bfin_read_PINT3_ASSIGN()                bfin_read32(PINT3_ASSIGN)
-#define bfin_write_PINT3_ASSIGN(val)            bfin_write32(PINT3_ASSIGN, val)
-#define bfin_read_PINT3_EDGE_SET()              bfin_read32(PINT3_EDGE_SET)
-#define bfin_write_PINT3_EDGE_SET(val)          bfin_write32(PINT3_EDGE_SET, val)
-#define bfin_read_PINT3_EDGE_CLEAR()            bfin_read32(PINT3_EDGE_CLEAR)
-#define bfin_write_PINT3_EDGE_CLEAR(val)        bfin_write32(PINT3_EDGE_CLEAR, val)
-#define bfin_read_PINT3_INVERT_SET()            bfin_read32(PINT3_INVERT_SET)
-#define bfin_write_PINT3_INVERT_SET(val)        bfin_write32(PINT3_INVERT_SET, val)
-#define bfin_read_PINT3_INVERT_CLEAR()          bfin_read32(PINT3_INVERT_CLEAR)
-#define bfin_write_PINT3_INVERT_CLEAR(val)      bfin_write32(PINT3_INVERT_CLEAR, val)
-#define bfin_read_PINT3_PINSTATE()              bfin_read32(PINT3_PINSTATE)
-#define bfin_write_PINT3_PINSTATE(val)          bfin_write32(PINT3_PINSTATE, val)
-#define bfin_read_PINT3_LATCH()                 bfin_read32(PINT3_LATCH)
-#define bfin_write_PINT3_LATCH(val)             bfin_write32(PINT3_LATCH, val)
-
-/* Port A Registers */
-
-#define bfin_read_PORTA_FER()           bfin_read16(PORTA_FER)
-#define bfin_write_PORTA_FER(val)       bfin_write16(PORTA_FER, val)
-#define bfin_read_PORTA()               bfin_read16(PORTA)
-#define bfin_write_PORTA(val)           bfin_write16(PORTA, val)
-#define bfin_read_PORTA_SET()           bfin_read16(PORTA_SET)
-#define bfin_write_PORTA_SET(val)       bfin_write16(PORTA_SET, val)
-#define bfin_read_PORTA_CLEAR()         bfin_read16(PORTA_CLEAR)
-#define bfin_write_PORTA_CLEAR(val)     bfin_write16(PORTA_CLEAR, val)
-#define bfin_read_PORTA_DIR_SET()       bfin_read16(PORTA_DIR_SET)
-#define bfin_write_PORTA_DIR_SET(val)   bfin_write16(PORTA_DIR_SET, val)
-#define bfin_read_PORTA_DIR_CLEAR()     bfin_read16(PORTA_DIR_CLEAR)
-#define bfin_write_PORTA_DIR_CLEAR(val) bfin_write16(PORTA_DIR_CLEAR, val)
-#define bfin_read_PORTA_INEN()          bfin_read16(PORTA_INEN)
-#define bfin_write_PORTA_INEN(val)      bfin_write16(PORTA_INEN, val)
-#define bfin_read_PORTA_MUX()           bfin_read32(PORTA_MUX)
-#define bfin_write_PORTA_MUX(val)       bfin_write32(PORTA_MUX, val)
-
-/* Port B Registers */
-
-#define bfin_read_PORTB_FER()           bfin_read16(PORTB_FER)
-#define bfin_write_PORTB_FER(val)       bfin_write16(PORTB_FER, val)
-#define bfin_read_PORTB()               bfin_read16(PORTB)
-#define bfin_write_PORTB(val)           bfin_write16(PORTB, val)
-#define bfin_read_PORTB_SET()           bfin_read16(PORTB_SET)
-#define bfin_write_PORTB_SET(val)       bfin_write16(PORTB_SET, val)
-#define bfin_read_PORTB_CLEAR()         bfin_read16(PORTB_CLEAR)
-#define bfin_write_PORTB_CLEAR(val)     bfin_write16(PORTB_CLEAR, val)
-#define bfin_read_PORTB_DIR_SET()       bfin_read16(PORTB_DIR_SET)
-#define bfin_write_PORTB_DIR_SET(val)   bfin_write16(PORTB_DIR_SET, val)
-#define bfin_read_PORTB_DIR_CLEAR()     bfin_read16(PORTB_DIR_CLEAR)
-#define bfin_write_PORTB_DIR_CLEAR(val) bfin_write16(PORTB_DIR_CLEAR, val)
-#define bfin_read_PORTB_INEN()          bfin_read16(PORTB_INEN)
-#define bfin_write_PORTB_INEN(val)      bfin_write16(PORTB_INEN, val)
-#define bfin_read_PORTB_MUX()           bfin_read32(PORTB_MUX)
-#define bfin_write_PORTB_MUX(val)       bfin_write32(PORTB_MUX, val)
-
-/* Port C Registers */
-
-#define bfin_read_PORTC_FER()           bfin_read16(PORTC_FER)
-#define bfin_write_PORTC_FER(val)       bfin_write16(PORTC_FER, val)
-#define bfin_read_PORTC()               bfin_read16(PORTC)
-#define bfin_write_PORTC(val)           bfin_write16(PORTC, val)
-#define bfin_read_PORTC_SET()           bfin_read16(PORTC_SET)
-#define bfin_write_PORTC_SET(val)       bfin_write16(PORTC_SET, val)
-#define bfin_read_PORTC_CLEAR()         bfin_read16(PORTC_CLEAR)
-#define bfin_write_PORTC_CLEAR(val)     bfin_write16(PORTC_CLEAR, val)
-#define bfin_read_PORTC_DIR_SET()       bfin_read16(PORTC_DIR_SET)
-#define bfin_write_PORTC_DIR_SET(val)   bfin_write16(PORTC_DIR_SET, val)
-#define bfin_read_PORTC_DIR_CLEAR()     bfin_read16(PORTC_DIR_CLEAR)
-#define bfin_write_PORTC_DIR_CLEAR(val) bfin_write16(PORTC_DIR_CLEAR, val)
-#define bfin_read_PORTC_INEN()          bfin_read16(PORTC_INEN)
-#define bfin_write_PORTC_INEN(val)      bfin_write16(PORTC_INEN, val)
-#define bfin_read_PORTC_MUX()           bfin_read32(PORTC_MUX)
-#define bfin_write_PORTC_MUX(val)       bfin_write32(PORTC_MUX, val)
-
-/* Port D Registers */
-
-#define bfin_read_PORTD_FER()           bfin_read16(PORTD_FER)
-#define bfin_write_PORTD_FER(val)       bfin_write16(PORTD_FER, val)
-#define bfin_read_PORTD()               bfin_read16(PORTD)
-#define bfin_write_PORTD(val)           bfin_write16(PORTD, val)
-#define bfin_read_PORTD_SET()           bfin_read16(PORTD_SET)
-#define bfin_write_PORTD_SET(val)       bfin_write16(PORTD_SET, val)
-#define bfin_read_PORTD_CLEAR()         bfin_read16(PORTD_CLEAR)
-#define bfin_write_PORTD_CLEAR(val)     bfin_write16(PORTD_CLEAR, val)
-#define bfin_read_PORTD_DIR_SET()       bfin_read16(PORTD_DIR_SET)
-#define bfin_write_PORTD_DIR_SET(val)   bfin_write16(PORTD_DIR_SET, val)
-#define bfin_read_PORTD_DIR_CLEAR()     bfin_read16(PORTD_DIR_CLEAR)
-#define bfin_write_PORTD_DIR_CLEAR(val) bfin_write16(PORTD_DIR_CLEAR, val)
-#define bfin_read_PORTD_INEN()          bfin_read16(PORTD_INEN)
-#define bfin_write_PORTD_INEN(val)      bfin_write16(PORTD_INEN, val)
-#define bfin_read_PORTD_MUX()           bfin_read32(PORTD_MUX)
-#define bfin_write_PORTD_MUX(val)       bfin_write32(PORTD_MUX, val)
-
-/* Port E Registers */
-
-#define bfin_read_PORTE_FER()           bfin_read16(PORTE_FER)
-#define bfin_write_PORTE_FER(val)       bfin_write16(PORTE_FER, val)
-#define bfin_read_PORTE()               bfin_read16(PORTE)
-#define bfin_write_PORTE(val)           bfin_write16(PORTE, val)
-#define bfin_read_PORTE_SET()           bfin_read16(PORTE_SET)
-#define bfin_write_PORTE_SET(val)       bfin_write16(PORTE_SET, val)
-#define bfin_read_PORTE_CLEAR()         bfin_read16(PORTE_CLEAR)
-#define bfin_write_PORTE_CLEAR(val)     bfin_write16(PORTE_CLEAR, val)
-#define bfin_read_PORTE_DIR_SET()       bfin_read16(PORTE_DIR_SET)
-#define bfin_write_PORTE_DIR_SET(val)   bfin_write16(PORTE_DIR_SET, val)
-#define bfin_read_PORTE_DIR_CLEAR()     bfin_read16(PORTE_DIR_CLEAR)
-#define bfin_write_PORTE_DIR_CLEAR(val) bfin_write16(PORTE_DIR_CLEAR, val)
-#define bfin_read_PORTE_INEN()          bfin_read16(PORTE_INEN)
-#define bfin_write_PORTE_INEN(val)      bfin_write16(PORTE_INEN, val)
-#define bfin_read_PORTE_MUX()           bfin_read32(PORTE_MUX)
-#define bfin_write_PORTE_MUX(val)       bfin_write32(PORTE_MUX, val)
-
-/* Port F Registers */
-
-#define bfin_read_PORTF_FER()           bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)       bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTF()               bfin_read16(PORTF)
-#define bfin_write_PORTF(val)           bfin_write16(PORTF, val)
-#define bfin_read_PORTF_SET()           bfin_read16(PORTF_SET)
-#define bfin_write_PORTF_SET(val)       bfin_write16(PORTF_SET, val)
-#define bfin_read_PORTF_CLEAR()         bfin_read16(PORTF_CLEAR)
-#define bfin_write_PORTF_CLEAR(val)     bfin_write16(PORTF_CLEAR, val)
-#define bfin_read_PORTF_DIR_SET()       bfin_read16(PORTF_DIR_SET)
-#define bfin_write_PORTF_DIR_SET(val)   bfin_write16(PORTF_DIR_SET, val)
-#define bfin_read_PORTF_DIR_CLEAR()     bfin_read16(PORTF_DIR_CLEAR)
-#define bfin_write_PORTF_DIR_CLEAR(val) bfin_write16(PORTF_DIR_CLEAR, val)
-#define bfin_read_PORTF_INEN()          bfin_read16(PORTF_INEN)
-#define bfin_write_PORTF_INEN(val)      bfin_write16(PORTF_INEN, val)
-#define bfin_read_PORTF_MUX()           bfin_read32(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)       bfin_write32(PORTF_MUX, val)
-
-/* Port G Registers */
-
-#define bfin_read_PORTG_FER()           bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)       bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTG()               bfin_read16(PORTG)
-#define bfin_write_PORTG(val)           bfin_write16(PORTG, val)
-#define bfin_read_PORTG_SET()           bfin_read16(PORTG_SET)
-#define bfin_write_PORTG_SET(val)       bfin_write16(PORTG_SET, val)
-#define bfin_read_PORTG_CLEAR()         bfin_read16(PORTG_CLEAR)
-#define bfin_write_PORTG_CLEAR(val)     bfin_write16(PORTG_CLEAR, val)
-#define bfin_read_PORTG_DIR_SET()       bfin_read16(PORTG_DIR_SET)
-#define bfin_write_PORTG_DIR_SET(val)   bfin_write16(PORTG_DIR_SET, val)
-#define bfin_read_PORTG_DIR_CLEAR()     bfin_read16(PORTG_DIR_CLEAR)
-#define bfin_write_PORTG_DIR_CLEAR(val) bfin_write16(PORTG_DIR_CLEAR, val)
-#define bfin_read_PORTG_INEN()          bfin_read16(PORTG_INEN)
-#define bfin_write_PORTG_INEN(val)      bfin_write16(PORTG_INEN, val)
-#define bfin_read_PORTG_MUX()           bfin_read32(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)       bfin_write32(PORTG_MUX, val)
-
-/* Port H Registers */
-
-#define bfin_read_PORTH_FER()           bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)       bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTH()               bfin_read16(PORTH)
-#define bfin_write_PORTH(val)           bfin_write16(PORTH, val)
-#define bfin_read_PORTH_SET()           bfin_read16(PORTH_SET)
-#define bfin_write_PORTH_SET(val)       bfin_write16(PORTH_SET, val)
-#define bfin_read_PORTH_CLEAR()         bfin_read16(PORTH_CLEAR)
-#define bfin_write_PORTH_CLEAR(val)     bfin_write16(PORTH_CLEAR, val)
-#define bfin_read_PORTH_DIR_SET()       bfin_read16(PORTH_DIR_SET)
-#define bfin_write_PORTH_DIR_SET(val)   bfin_write16(PORTH_DIR_SET, val)
-#define bfin_read_PORTH_DIR_CLEAR()     bfin_read16(PORTH_DIR_CLEAR)
-#define bfin_write_PORTH_DIR_CLEAR(val) bfin_write16(PORTH_DIR_CLEAR, val)
-#define bfin_read_PORTH_INEN()          bfin_read16(PORTH_INEN)
-#define bfin_write_PORTH_INEN(val)      bfin_write16(PORTH_INEN, val)
-#define bfin_read_PORTH_MUX()           bfin_read32(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)       bfin_write32(PORTH_MUX, val)
-
-/* Port I Registers */
-
-#define bfin_read_PORTI_FER()           bfin_read16(PORTI_FER)
-#define bfin_write_PORTI_FER(val)       bfin_write16(PORTI_FER, val)
-#define bfin_read_PORTI()               bfin_read16(PORTI)
-#define bfin_write_PORTI(val)           bfin_write16(PORTI, val)
-#define bfin_read_PORTI_SET()           bfin_read16(PORTI_SET)
-#define bfin_write_PORTI_SET(val)       bfin_write16(PORTI_SET, val)
-#define bfin_read_PORTI_CLEAR()         bfin_read16(PORTI_CLEAR)
-#define bfin_write_PORTI_CLEAR(val)     bfin_write16(PORTI_CLEAR, val)
-#define bfin_read_PORTI_DIR_SET()       bfin_read16(PORTI_DIR_SET)
-#define bfin_write_PORTI_DIR_SET(val)   bfin_write16(PORTI_DIR_SET, val)
-#define bfin_read_PORTI_DIR_CLEAR()     bfin_read16(PORTI_DIR_CLEAR)
-#define bfin_write_PORTI_DIR_CLEAR(val) bfin_write16(PORTI_DIR_CLEAR, val)
-#define bfin_read_PORTI_INEN()          bfin_read16(PORTI_INEN)
-#define bfin_write_PORTI_INEN(val)      bfin_write16(PORTI_INEN, val)
-#define bfin_read_PORTI_MUX()           bfin_read32(PORTI_MUX)
-#define bfin_write_PORTI_MUX(val)       bfin_write32(PORTI_MUX, val)
-
-/* Port J Registers */
-
-#define bfin_read_PORTJ_FER()           bfin_read16(PORTJ_FER)
-#define bfin_write_PORTJ_FER(val)       bfin_write16(PORTJ_FER, val)
-#define bfin_read_PORTJ()               bfin_read16(PORTJ)
-#define bfin_write_PORTJ(val)           bfin_write16(PORTJ, val)
-#define bfin_read_PORTJ_SET()           bfin_read16(PORTJ_SET)
-#define bfin_write_PORTJ_SET(val)       bfin_write16(PORTJ_SET, val)
-#define bfin_read_PORTJ_CLEAR()         bfin_read16(PORTJ_CLEAR)
-#define bfin_write_PORTJ_CLEAR(val)     bfin_write16(PORTJ_CLEAR, val)
-#define bfin_read_PORTJ_DIR_SET()       bfin_read16(PORTJ_DIR_SET)
-#define bfin_write_PORTJ_DIR_SET(val)   bfin_write16(PORTJ_DIR_SET, val)
-#define bfin_read_PORTJ_DIR_CLEAR()     bfin_read16(PORTJ_DIR_CLEAR)
-#define bfin_write_PORTJ_DIR_CLEAR(val) bfin_write16(PORTJ_DIR_CLEAR, val)
-#define bfin_read_PORTJ_INEN()          bfin_read16(PORTJ_INEN)
-#define bfin_write_PORTJ_INEN(val)      bfin_write16(PORTJ_INEN, val)
-#define bfin_read_PORTJ_MUX()           bfin_read32(PORTJ_MUX)
-#define bfin_write_PORTJ_MUX(val)       bfin_write32(PORTJ_MUX, val)
-
-/* PWM Timer Registers */
-
-#define bfin_read_TIMER0_CONFIG()               bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)           bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()              bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)          bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()               bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)           bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()                bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)            bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()               bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)           bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()              bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)          bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()               bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)           bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()                bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)            bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()               bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)           bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()              bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)          bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()               bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)           bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()                bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)            bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()               bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)           bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()              bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)          bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()               bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)           bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()                bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)            bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()               bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)           bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()              bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)          bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()               bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)           bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()                bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)            bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()               bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)           bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()              bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)          bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()               bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)           bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()                bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)            bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()               bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)           bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()              bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)          bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()               bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)           bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()                bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)            bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()               bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)           bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()              bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)          bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()               bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)           bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()                bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)            bfin_write32(TIMER7_WIDTH, val)
-
-/* Timer Groubfin_read_() of 8 */
-
-#define bfin_read_TIMER_ENABLE0()               bfin_read16(TIMER_ENABLE0)
-#define bfin_write_TIMER_ENABLE0(val)           bfin_write16(TIMER_ENABLE0, val)
-#define bfin_read_TIMER_DISABLE0()              bfin_read16(TIMER_DISABLE0)
-#define bfin_write_TIMER_DISABLE0(val)          bfin_write16(TIMER_DISABLE0, val)
-#define bfin_read_TIMER_STATUS0()               bfin_read32(TIMER_STATUS0)
-#define bfin_write_TIMER_STATUS0(val)           bfin_write32(TIMER_STATUS0, val)
-
-/* DMAC1 Registers */
-
-#define bfin_read_DMAC1_TCPER()                 bfin_read16(DMAC1_TCPER)
-#define bfin_write_DMAC1_TCPER(val)             bfin_write16(DMAC1_TCPER, val)
-#define bfin_read_DMAC1_TCCNT()                 bfin_read16(DMAC1_TCCNT)
-#define bfin_write_DMAC1_TCCNT(val)             bfin_write16(DMAC1_TCCNT, val)
-
-/* DMA Channel 12 Registers */
-
-#define bfin_read_DMA12_NEXT_DESC_PTR()         bfin_read32(DMA12_NEXT_DESC_PTR)
-#define bfin_write_DMA12_NEXT_DESC_PTR(val)     bfin_write32(DMA12_NEXT_DESC_PTR, val)
-#define bfin_read_DMA12_START_ADDR()            bfin_read32(DMA12_START_ADDR)
-#define bfin_write_DMA12_START_ADDR(val)        bfin_write32(DMA12_START_ADDR, val)
-#define bfin_read_DMA12_CONFIG()                bfin_read16(DMA12_CONFIG)
-#define bfin_write_DMA12_CONFIG(val)            bfin_write16(DMA12_CONFIG, val)
-#define bfin_read_DMA12_X_COUNT()               bfin_read16(DMA12_X_COUNT)
-#define bfin_write_DMA12_X_COUNT(val)           bfin_write16(DMA12_X_COUNT, val)
-#define bfin_read_DMA12_X_MODIFY()              bfin_read16(DMA12_X_MODIFY)
-#define bfin_write_DMA12_X_MODIFY(val)          bfin_write16(DMA12_X_MODIFY, val)
-#define bfin_read_DMA12_Y_COUNT()               bfin_read16(DMA12_Y_COUNT)
-#define bfin_write_DMA12_Y_COUNT(val)           bfin_write16(DMA12_Y_COUNT, val)
-#define bfin_read_DMA12_Y_MODIFY()              bfin_read16(DMA12_Y_MODIFY)
-#define bfin_write_DMA12_Y_MODIFY(val)          bfin_write16(DMA12_Y_MODIFY, val)
-#define bfin_read_DMA12_CURR_DESC_PTR()         bfin_read32(DMA12_CURR_DESC_PTR)
-#define bfin_write_DMA12_CURR_DESC_PTR(val)     bfin_write32(DMA12_CURR_DESC_PTR, val)
-#define bfin_read_DMA12_CURR_ADDR()             bfin_read32(DMA12_CURR_ADDR)
-#define bfin_write_DMA12_CURR_ADDR(val)         bfin_write32(DMA12_CURR_ADDR, val)
-#define bfin_read_DMA12_IRQ_STATUS()            bfin_read16(DMA12_IRQ_STATUS)
-#define bfin_write_DMA12_IRQ_STATUS(val)        bfin_write16(DMA12_IRQ_STATUS, val)
-#define bfin_read_DMA12_PERIPHERAL_MAP()        bfin_read16(DMA12_PERIPHERAL_MAP)
-#define bfin_write_DMA12_PERIPHERAL_MAP(val)    bfin_write16(DMA12_PERIPHERAL_MAP, val)
-#define bfin_read_DMA12_CURR_X_COUNT()          bfin_read16(DMA12_CURR_X_COUNT)
-#define bfin_write_DMA12_CURR_X_COUNT(val)      bfin_write16(DMA12_CURR_X_COUNT, val)
-#define bfin_read_DMA12_CURR_Y_COUNT()          bfin_read16(DMA12_CURR_Y_COUNT)
-#define bfin_write_DMA12_CURR_Y_COUNT(val)      bfin_write16(DMA12_CURR_Y_COUNT, val)
-
-/* DMA Channel 13 Registers */
-
-#define bfin_read_DMA13_NEXT_DESC_PTR()         bfin_read32(DMA13_NEXT_DESC_PTR)
-#define bfin_write_DMA13_NEXT_DESC_PTR(val)     bfin_write32(DMA13_NEXT_DESC_PTR, val)
-#define bfin_read_DMA13_START_ADDR()            bfin_read32(DMA13_START_ADDR)
-#define bfin_write_DMA13_START_ADDR(val)        bfin_write32(DMA13_START_ADDR, val)
-#define bfin_read_DMA13_CONFIG()                bfin_read16(DMA13_CONFIG)
-#define bfin_write_DMA13_CONFIG(val)            bfin_write16(DMA13_CONFIG, val)
-#define bfin_read_DMA13_X_COUNT()               bfin_read16(DMA13_X_COUNT)
-#define bfin_write_DMA13_X_COUNT(val)           bfin_write16(DMA13_X_COUNT, val)
-#define bfin_read_DMA13_X_MODIFY()              bfin_read16(DMA13_X_MODIFY)
-#define bfin_write_DMA13_X_MODIFY(val)          bfin_write16(DMA13_X_MODIFY, val)
-#define bfin_read_DMA13_Y_COUNT()               bfin_read16(DMA13_Y_COUNT)
-#define bfin_write_DMA13_Y_COUNT(val)           bfin_write16(DMA13_Y_COUNT, val)
-#define bfin_read_DMA13_Y_MODIFY()              bfin_read16(DMA13_Y_MODIFY)
-#define bfin_write_DMA13_Y_MODIFY(val)          bfin_write16(DMA13_Y_MODIFY, val)
-#define bfin_read_DMA13_CURR_DESC_PTR()         bfin_read32(DMA13_CURR_DESC_PTR)
-#define bfin_write_DMA13_CURR_DESC_PTR(val)     bfin_write32(DMA13_CURR_DESC_PTR, val)
-#define bfin_read_DMA13_CURR_ADDR()             bfin_read32(DMA13_CURR_ADDR)
-#define bfin_write_DMA13_CURR_ADDR(val)         bfin_write32(DMA13_CURR_ADDR, val)
-#define bfin_read_DMA13_IRQ_STATUS()            bfin_read16(DMA13_IRQ_STATUS)
-#define bfin_write_DMA13_IRQ_STATUS(val)        bfin_write16(DMA13_IRQ_STATUS, val)
-#define bfin_read_DMA13_PERIPHERAL_MAP()        bfin_read16(DMA13_PERIPHERAL_MAP)
-#define bfin_write_DMA13_PERIPHERAL_MAP(val)    bfin_write16(DMA13_PERIPHERAL_MAP, val)
-#define bfin_read_DMA13_CURR_X_COUNT()          bfin_read16(DMA13_CURR_X_COUNT)
-#define bfin_write_DMA13_CURR_X_COUNT(val)      bfin_write16(DMA13_CURR_X_COUNT, val)
-#define bfin_read_DMA13_CURR_Y_COUNT()          bfin_read16(DMA13_CURR_Y_COUNT)
-#define bfin_write_DMA13_CURR_Y_COUNT(val)      bfin_write16(DMA13_CURR_Y_COUNT, val)
-
-/* DMA Channel 14 Registers */
-
-#define bfin_read_DMA14_NEXT_DESC_PTR()         bfin_read32(DMA14_NEXT_DESC_PTR)
-#define bfin_write_DMA14_NEXT_DESC_PTR(val)     bfin_write32(DMA14_NEXT_DESC_PTR, val)
-#define bfin_read_DMA14_START_ADDR()            bfin_read32(DMA14_START_ADDR)
-#define bfin_write_DMA14_START_ADDR(val)        bfin_write32(DMA14_START_ADDR, val)
-#define bfin_read_DMA14_CONFIG()                bfin_read16(DMA14_CONFIG)
-#define bfin_write_DMA14_CONFIG(val)            bfin_write16(DMA14_CONFIG, val)
-#define bfin_read_DMA14_X_COUNT()               bfin_read16(DMA14_X_COUNT)
-#define bfin_write_DMA14_X_COUNT(val)           bfin_write16(DMA14_X_COUNT, val)
-#define bfin_read_DMA14_X_MODIFY()              bfin_read16(DMA14_X_MODIFY)
-#define bfin_write_DMA14_X_MODIFY(val)          bfin_write16(DMA14_X_MODIFY, val)
-#define bfin_read_DMA14_Y_COUNT()               bfin_read16(DMA14_Y_COUNT)
-#define bfin_write_DMA14_Y_COUNT(val)           bfin_write16(DMA14_Y_COUNT, val)
-#define bfin_read_DMA14_Y_MODIFY()              bfin_read16(DMA14_Y_MODIFY)
-#define bfin_write_DMA14_Y_MODIFY(val)          bfin_write16(DMA14_Y_MODIFY, val)
-#define bfin_read_DMA14_CURR_DESC_PTR()         bfin_read32(DMA14_CURR_DESC_PTR)
-#define bfin_write_DMA14_CURR_DESC_PTR(val)     bfin_write32(DMA14_CURR_DESC_PTR, val)
-#define bfin_read_DMA14_CURR_ADDR()             bfin_read32(DMA14_CURR_ADDR)
-#define bfin_write_DMA14_CURR_ADDR(val)         bfin_write32(DMA14_CURR_ADDR, val)
-#define bfin_read_DMA14_IRQ_STATUS()            bfin_read16(DMA14_IRQ_STATUS)
-#define bfin_write_DMA14_IRQ_STATUS(val)        bfin_write16(DMA14_IRQ_STATUS, val)
-#define bfin_read_DMA14_PERIPHERAL_MAP()        bfin_read16(DMA14_PERIPHERAL_MAP)
-#define bfin_write_DMA14_PERIPHERAL_MAP(val)    bfin_write16(DMA14_PERIPHERAL_MAP, val)
-#define bfin_read_DMA14_CURR_X_COUNT()          bfin_read16(DMA14_CURR_X_COUNT)
-#define bfin_write_DMA14_CURR_X_COUNT(val)      bfin_write16(DMA14_CURR_X_COUNT, val)
-#define bfin_read_DMA14_CURR_Y_COUNT()          bfin_read16(DMA14_CURR_Y_COUNT)
-#define bfin_write_DMA14_CURR_Y_COUNT(val)      bfin_write16(DMA14_CURR_Y_COUNT, val)
-
-/* DMA Channel 15 Registers */
-
-#define bfin_read_DMA15_NEXT_DESC_PTR()         bfin_read32(DMA15_NEXT_DESC_PTR)
-#define bfin_write_DMA15_NEXT_DESC_PTR(val)     bfin_write32(DMA15_NEXT_DESC_PTR, val)
-#define bfin_read_DMA15_START_ADDR()            bfin_read32(DMA15_START_ADDR)
-#define bfin_write_DMA15_START_ADDR(val)        bfin_write32(DMA15_START_ADDR, val)
-#define bfin_read_DMA15_CONFIG()                bfin_read16(DMA15_CONFIG)
-#define bfin_write_DMA15_CONFIG(val)            bfin_write16(DMA15_CONFIG, val)
-#define bfin_read_DMA15_X_COUNT()               bfin_read16(DMA15_X_COUNT)
-#define bfin_write_DMA15_X_COUNT(val)           bfin_write16(DMA15_X_COUNT, val)
-#define bfin_read_DMA15_X_MODIFY()              bfin_read16(DMA15_X_MODIFY)
-#define bfin_write_DMA15_X_MODIFY(val)          bfin_write16(DMA15_X_MODIFY, val)
-#define bfin_read_DMA15_Y_COUNT()               bfin_read16(DMA15_Y_COUNT)
-#define bfin_write_DMA15_Y_COUNT(val)           bfin_write16(DMA15_Y_COUNT, val)
-#define bfin_read_DMA15_Y_MODIFY()              bfin_read16(DMA15_Y_MODIFY)
-#define bfin_write_DMA15_Y_MODIFY(val)          bfin_write16(DMA15_Y_MODIFY, val)
-#define bfin_read_DMA15_CURR_DESC_PTR()         bfin_read32(DMA15_CURR_DESC_PTR)
-#define bfin_write_DMA15_CURR_DESC_PTR(val)     bfin_write32(DMA15_CURR_DESC_PTR, val)
-#define bfin_read_DMA15_CURR_ADDR()             bfin_read32(DMA15_CURR_ADDR)
-#define bfin_write_DMA15_CURR_ADDR(val)         bfin_write32(DMA15_CURR_ADDR, val)
-#define bfin_read_DMA15_IRQ_STATUS()            bfin_read16(DMA15_IRQ_STATUS)
-#define bfin_write_DMA15_IRQ_STATUS(val)        bfin_write16(DMA15_IRQ_STATUS, val)
-#define bfin_read_DMA15_PERIPHERAL_MAP()        bfin_read16(DMA15_PERIPHERAL_MAP)
-#define bfin_write_DMA15_PERIPHERAL_MAP(val)    bfin_write16(DMA15_PERIPHERAL_MAP, val)
-#define bfin_read_DMA15_CURR_X_COUNT()          bfin_read16(DMA15_CURR_X_COUNT)
-#define bfin_write_DMA15_CURR_X_COUNT(val)      bfin_write16(DMA15_CURR_X_COUNT, val)
-#define bfin_read_DMA15_CURR_Y_COUNT()          bfin_read16(DMA15_CURR_Y_COUNT)
-#define bfin_write_DMA15_CURR_Y_COUNT(val)      bfin_write16(DMA15_CURR_Y_COUNT, val)
-
-/* DMA Channel 16 Registers */
-
-#define bfin_read_DMA16_NEXT_DESC_PTR()         bfin_read32(DMA16_NEXT_DESC_PTR)
-#define bfin_write_DMA16_NEXT_DESC_PTR(val)     bfin_write32(DMA16_NEXT_DESC_PTR, val)
-#define bfin_read_DMA16_START_ADDR()            bfin_read32(DMA16_START_ADDR)
-#define bfin_write_DMA16_START_ADDR(val)        bfin_write32(DMA16_START_ADDR, val)
-#define bfin_read_DMA16_CONFIG()                bfin_read16(DMA16_CONFIG)
-#define bfin_write_DMA16_CONFIG(val)            bfin_write16(DMA16_CONFIG, val)
-#define bfin_read_DMA16_X_COUNT()               bfin_read16(DMA16_X_COUNT)
-#define bfin_write_DMA16_X_COUNT(val)           bfin_write16(DMA16_X_COUNT, val)
-#define bfin_read_DMA16_X_MODIFY()              bfin_read16(DMA16_X_MODIFY)
-#define bfin_write_DMA16_X_MODIFY(val)          bfin_write16(DMA16_X_MODIFY, val)
-#define bfin_read_DMA16_Y_COUNT()               bfin_read16(DMA16_Y_COUNT)
-#define bfin_write_DMA16_Y_COUNT(val)           bfin_write16(DMA16_Y_COUNT, val)
-#define bfin_read_DMA16_Y_MODIFY()              bfin_read16(DMA16_Y_MODIFY)
-#define bfin_write_DMA16_Y_MODIFY(val)          bfin_write16(DMA16_Y_MODIFY, val)
-#define bfin_read_DMA16_CURR_DESC_PTR()         bfin_read32(DMA16_CURR_DESC_PTR)
-#define bfin_write_DMA16_CURR_DESC_PTR(val)     bfin_write32(DMA16_CURR_DESC_PTR, val)
-#define bfin_read_DMA16_CURR_ADDR()             bfin_read32(DMA16_CURR_ADDR)
-#define bfin_write_DMA16_CURR_ADDR(val)         bfin_write32(DMA16_CURR_ADDR, val)
-#define bfin_read_DMA16_IRQ_STATUS()            bfin_read16(DMA16_IRQ_STATUS)
-#define bfin_write_DMA16_IRQ_STATUS(val)        bfin_write16(DMA16_IRQ_STATUS, val)
-#define bfin_read_DMA16_PERIPHERAL_MAP()        bfin_read16(DMA16_PERIPHERAL_MAP)
-#define bfin_write_DMA16_PERIPHERAL_MAP(val)    bfin_write16(DMA16_PERIPHERAL_MAP, val)
-#define bfin_read_DMA16_CURR_X_COUNT()          bfin_read16(DMA16_CURR_X_COUNT)
-#define bfin_write_DMA16_CURR_X_COUNT(val)      bfin_write16(DMA16_CURR_X_COUNT, val)
-#define bfin_read_DMA16_CURR_Y_COUNT()          bfin_read16(DMA16_CURR_Y_COUNT)
-#define bfin_write_DMA16_CURR_Y_COUNT(val)      bfin_write16(DMA16_CURR_Y_COUNT, val)
-
-/* DMA Channel 17 Registers */
-
-#define bfin_read_DMA17_NEXT_DESC_PTR()         bfin_read32(DMA17_NEXT_DESC_PTR)
-#define bfin_write_DMA17_NEXT_DESC_PTR(val)     bfin_write32(DMA17_NEXT_DESC_PTR, val)
-#define bfin_read_DMA17_START_ADDR()            bfin_read32(DMA17_START_ADDR)
-#define bfin_write_DMA17_START_ADDR(val)        bfin_write32(DMA17_START_ADDR, val)
-#define bfin_read_DMA17_CONFIG()                bfin_read16(DMA17_CONFIG)
-#define bfin_write_DMA17_CONFIG(val)            bfin_write16(DMA17_CONFIG, val)
-#define bfin_read_DMA17_X_COUNT()               bfin_read16(DMA17_X_COUNT)
-#define bfin_write_DMA17_X_COUNT(val)           bfin_write16(DMA17_X_COUNT, val)
-#define bfin_read_DMA17_X_MODIFY()              bfin_read16(DMA17_X_MODIFY)
-#define bfin_write_DMA17_X_MODIFY(val)          bfin_write16(DMA17_X_MODIFY, val)
-#define bfin_read_DMA17_Y_COUNT()               bfin_read16(DMA17_Y_COUNT)
-#define bfin_write_DMA17_Y_COUNT(val)           bfin_write16(DMA17_Y_COUNT, val)
-#define bfin_read_DMA17_Y_MODIFY()              bfin_read16(DMA17_Y_MODIFY)
-#define bfin_write_DMA17_Y_MODIFY(val)          bfin_write16(DMA17_Y_MODIFY, val)
-#define bfin_read_DMA17_CURR_DESC_PTR()         bfin_read32(DMA17_CURR_DESC_PTR)
-#define bfin_write_DMA17_CURR_DESC_PTR(val)     bfin_write32(DMA17_CURR_DESC_PTR, val)
-#define bfin_read_DMA17_CURR_ADDR()             bfin_read32(DMA17_CURR_ADDR)
-#define bfin_write_DMA17_CURR_ADDR(val)         bfin_write32(DMA17_CURR_ADDR, val)
-#define bfin_read_DMA17_IRQ_STATUS()            bfin_read16(DMA17_IRQ_STATUS)
-#define bfin_write_DMA17_IRQ_STATUS(val)        bfin_write16(DMA17_IRQ_STATUS, val)
-#define bfin_read_DMA17_PERIPHERAL_MAP()        bfin_read16(DMA17_PERIPHERAL_MAP)
-#define bfin_write_DMA17_PERIPHERAL_MAP(val)    bfin_write16(DMA17_PERIPHERAL_MAP, val)
-#define bfin_read_DMA17_CURR_X_COUNT()          bfin_read16(DMA17_CURR_X_COUNT)
-#define bfin_write_DMA17_CURR_X_COUNT(val)      bfin_write16(DMA17_CURR_X_COUNT, val)
-#define bfin_read_DMA17_CURR_Y_COUNT()          bfin_read16(DMA17_CURR_Y_COUNT)
-#define bfin_write_DMA17_CURR_Y_COUNT(val)      bfin_write16(DMA17_CURR_Y_COUNT, val)
-
-/* DMA Channel 18 Registers */
-
-#define bfin_read_DMA18_NEXT_DESC_PTR()         bfin_read32(DMA18_NEXT_DESC_PTR)
-#define bfin_write_DMA18_NEXT_DESC_PTR(val)     bfin_write32(DMA18_NEXT_DESC_PTR, val)
-#define bfin_read_DMA18_START_ADDR()            bfin_read32(DMA18_START_ADDR)
-#define bfin_write_DMA18_START_ADDR(val)        bfin_write32(DMA18_START_ADDR, val)
-#define bfin_read_DMA18_CONFIG()                bfin_read16(DMA18_CONFIG)
-#define bfin_write_DMA18_CONFIG(val)            bfin_write16(DMA18_CONFIG, val)
-#define bfin_read_DMA18_X_COUNT()               bfin_read16(DMA18_X_COUNT)
-#define bfin_write_DMA18_X_COUNT(val)           bfin_write16(DMA18_X_COUNT, val)
-#define bfin_read_DMA18_X_MODIFY()              bfin_read16(DMA18_X_MODIFY)
-#define bfin_write_DMA18_X_MODIFY(val)          bfin_write16(DMA18_X_MODIFY, val)
-#define bfin_read_DMA18_Y_COUNT()               bfin_read16(DMA18_Y_COUNT)
-#define bfin_write_DMA18_Y_COUNT(val)           bfin_write16(DMA18_Y_COUNT, val)
-#define bfin_read_DMA18_Y_MODIFY()              bfin_read16(DMA18_Y_MODIFY)
-#define bfin_write_DMA18_Y_MODIFY(val)          bfin_write16(DMA18_Y_MODIFY, val)
-#define bfin_read_DMA18_CURR_DESC_PTR()         bfin_read32(DMA18_CURR_DESC_PTR)
-#define bfin_write_DMA18_CURR_DESC_PTR(val)     bfin_write32(DMA18_CURR_DESC_PTR, val)
-#define bfin_read_DMA18_CURR_ADDR()             bfin_read32(DMA18_CURR_ADDR)
-#define bfin_write_DMA18_CURR_ADDR(val)         bfin_write32(DMA18_CURR_ADDR, val)
-#define bfin_read_DMA18_IRQ_STATUS()            bfin_read16(DMA18_IRQ_STATUS)
-#define bfin_write_DMA18_IRQ_STATUS(val)        bfin_write16(DMA18_IRQ_STATUS, val)
-#define bfin_read_DMA18_PERIPHERAL_MAP()        bfin_read16(DMA18_PERIPHERAL_MAP)
-#define bfin_write_DMA18_PERIPHERAL_MAP(val)    bfin_write16(DMA18_PERIPHERAL_MAP, val)
-#define bfin_read_DMA18_CURR_X_COUNT()          bfin_read16(DMA18_CURR_X_COUNT)
-#define bfin_write_DMA18_CURR_X_COUNT(val)      bfin_write16(DMA18_CURR_X_COUNT, val)
-#define bfin_read_DMA18_CURR_Y_COUNT()          bfin_read16(DMA18_CURR_Y_COUNT)
-#define bfin_write_DMA18_CURR_Y_COUNT(val)      bfin_write16(DMA18_CURR_Y_COUNT, val)
-
-/* DMA Channel 19 Registers */
-
-#define bfin_read_DMA19_NEXT_DESC_PTR()         bfin_read32(DMA19_NEXT_DESC_PTR)
-#define bfin_write_DMA19_NEXT_DESC_PTR(val)     bfin_write32(DMA19_NEXT_DESC_PTR, val)
-#define bfin_read_DMA19_START_ADDR()            bfin_read32(DMA19_START_ADDR)
-#define bfin_write_DMA19_START_ADDR(val)        bfin_write32(DMA19_START_ADDR, val)
-#define bfin_read_DMA19_CONFIG()                bfin_read16(DMA19_CONFIG)
-#define bfin_write_DMA19_CONFIG(val)            bfin_write16(DMA19_CONFIG, val)
-#define bfin_read_DMA19_X_COUNT()               bfin_read16(DMA19_X_COUNT)
-#define bfin_write_DMA19_X_COUNT(val)           bfin_write16(DMA19_X_COUNT, val)
-#define bfin_read_DMA19_X_MODIFY()              bfin_read16(DMA19_X_MODIFY)
-#define bfin_write_DMA19_X_MODIFY(val)          bfin_write16(DMA19_X_MODIFY, val)
-#define bfin_read_DMA19_Y_COUNT()               bfin_read16(DMA19_Y_COUNT)
-#define bfin_write_DMA19_Y_COUNT(val)           bfin_write16(DMA19_Y_COUNT, val)
-#define bfin_read_DMA19_Y_MODIFY()              bfin_read16(DMA19_Y_MODIFY)
-#define bfin_write_DMA19_Y_MODIFY(val)          bfin_write16(DMA19_Y_MODIFY, val)
-#define bfin_read_DMA19_CURR_DESC_PTR()         bfin_read32(DMA19_CURR_DESC_PTR)
-#define bfin_write_DMA19_CURR_DESC_PTR(val)     bfin_write32(DMA19_CURR_DESC_PTR, val)
-#define bfin_read_DMA19_CURR_ADDR()             bfin_read32(DMA19_CURR_ADDR)
-#define bfin_write_DMA19_CURR_ADDR(val)         bfin_write32(DMA19_CURR_ADDR, val)
-#define bfin_read_DMA19_IRQ_STATUS()            bfin_read16(DMA19_IRQ_STATUS)
-#define bfin_write_DMA19_IRQ_STATUS(val)        bfin_write16(DMA19_IRQ_STATUS, val)
-#define bfin_read_DMA19_PERIPHERAL_MAP()        bfin_read16(DMA19_PERIPHERAL_MAP)
-#define bfin_write_DMA19_PERIPHERAL_MAP(val)    bfin_write16(DMA19_PERIPHERAL_MAP, val)
-#define bfin_read_DMA19_CURR_X_COUNT()          bfin_read16(DMA19_CURR_X_COUNT)
-#define bfin_write_DMA19_CURR_X_COUNT(val)      bfin_write16(DMA19_CURR_X_COUNT, val)
-#define bfin_read_DMA19_CURR_Y_COUNT()          bfin_read16(DMA19_CURR_Y_COUNT)
-#define bfin_write_DMA19_CURR_Y_COUNT(val)      bfin_write16(DMA19_CURR_Y_COUNT, val)
-
-/* DMA Channel 20 Registers */
-
-#define bfin_read_DMA20_NEXT_DESC_PTR()         bfin_read32(DMA20_NEXT_DESC_PTR)
-#define bfin_write_DMA20_NEXT_DESC_PTR(val)     bfin_write32(DMA20_NEXT_DESC_PTR, val)
-#define bfin_read_DMA20_START_ADDR()            bfin_read32(DMA20_START_ADDR)
-#define bfin_write_DMA20_START_ADDR(val)        bfin_write32(DMA20_START_ADDR, val)
-#define bfin_read_DMA20_CONFIG()                bfin_read16(DMA20_CONFIG)
-#define bfin_write_DMA20_CONFIG(val)            bfin_write16(DMA20_CONFIG, val)
-#define bfin_read_DMA20_X_COUNT()               bfin_read16(DMA20_X_COUNT)
-#define bfin_write_DMA20_X_COUNT(val)           bfin_write16(DMA20_X_COUNT, val)
-#define bfin_read_DMA20_X_MODIFY()              bfin_read16(DMA20_X_MODIFY)
-#define bfin_write_DMA20_X_MODIFY(val)          bfin_write16(DMA20_X_MODIFY, val)
-#define bfin_read_DMA20_Y_COUNT()               bfin_read16(DMA20_Y_COUNT)
-#define bfin_write_DMA20_Y_COUNT(val)           bfin_write16(DMA20_Y_COUNT, val)
-#define bfin_read_DMA20_Y_MODIFY()              bfin_read16(DMA20_Y_MODIFY)
-#define bfin_write_DMA20_Y_MODIFY(val)          bfin_write16(DMA20_Y_MODIFY, val)
-#define bfin_read_DMA20_CURR_DESC_PTR()         bfin_read32(DMA20_CURR_DESC_PTR)
-#define bfin_write_DMA20_CURR_DESC_PTR(val)     bfin_write32(DMA20_CURR_DESC_PTR, val)
-#define bfin_read_DMA20_CURR_ADDR()             bfin_read32(DMA20_CURR_ADDR)
-#define bfin_write_DMA20_CURR_ADDR(val)         bfin_write32(DMA20_CURR_ADDR, val)
-#define bfin_read_DMA20_IRQ_STATUS()            bfin_read16(DMA20_IRQ_STATUS)
-#define bfin_write_DMA20_IRQ_STATUS(val)        bfin_write16(DMA20_IRQ_STATUS, val)
-#define bfin_read_DMA20_PERIPHERAL_MAP()        bfin_read16(DMA20_PERIPHERAL_MAP)
-#define bfin_write_DMA20_PERIPHERAL_MAP(val)    bfin_write16(DMA20_PERIPHERAL_MAP, val)
-#define bfin_read_DMA20_CURR_X_COUNT()          bfin_read16(DMA20_CURR_X_COUNT)
-#define bfin_write_DMA20_CURR_X_COUNT(val)      bfin_write16(DMA20_CURR_X_COUNT, val)
-#define bfin_read_DMA20_CURR_Y_COUNT()          bfin_read16(DMA20_CURR_Y_COUNT)
-#define bfin_write_DMA20_CURR_Y_COUNT(val)      bfin_write16(DMA20_CURR_Y_COUNT, val)
-
-/* DMA Channel 21 Registers */
-
-#define bfin_read_DMA21_NEXT_DESC_PTR()         bfin_read32(DMA21_NEXT_DESC_PTR)
-#define bfin_write_DMA21_NEXT_DESC_PTR(val)     bfin_write32(DMA21_NEXT_DESC_PTR, val)
-#define bfin_read_DMA21_START_ADDR()            bfin_read32(DMA21_START_ADDR)
-#define bfin_write_DMA21_START_ADDR(val)        bfin_write32(DMA21_START_ADDR, val)
-#define bfin_read_DMA21_CONFIG()                bfin_read16(DMA21_CONFIG)
-#define bfin_write_DMA21_CONFIG(val)            bfin_write16(DMA21_CONFIG, val)
-#define bfin_read_DMA21_X_COUNT()               bfin_read16(DMA21_X_COUNT)
-#define bfin_write_DMA21_X_COUNT(val)           bfin_write16(DMA21_X_COUNT, val)
-#define bfin_read_DMA21_X_MODIFY()              bfin_read16(DMA21_X_MODIFY)
-#define bfin_write_DMA21_X_MODIFY(val)          bfin_write16(DMA21_X_MODIFY, val)
-#define bfin_read_DMA21_Y_COUNT()               bfin_read16(DMA21_Y_COUNT)
-#define bfin_write_DMA21_Y_COUNT(val)           bfin_write16(DMA21_Y_COUNT, val)
-#define bfin_read_DMA21_Y_MODIFY()              bfin_read16(DMA21_Y_MODIFY)
-#define bfin_write_DMA21_Y_MODIFY(val)          bfin_write16(DMA21_Y_MODIFY, val)
-#define bfin_read_DMA21_CURR_DESC_PTR()         bfin_read32(DMA21_CURR_DESC_PTR)
-#define bfin_write_DMA21_CURR_DESC_PTR(val)     bfin_write32(DMA21_CURR_DESC_PTR, val)
-#define bfin_read_DMA21_CURR_ADDR()             bfin_read32(DMA21_CURR_ADDR)
-#define bfin_write_DMA21_CURR_ADDR(val)         bfin_write32(DMA21_CURR_ADDR, val)
-#define bfin_read_DMA21_IRQ_STATUS()            bfin_read16(DMA21_IRQ_STATUS)
-#define bfin_write_DMA21_IRQ_STATUS(val)        bfin_write16(DMA21_IRQ_STATUS, val)
-#define bfin_read_DMA21_PERIPHERAL_MAP()        bfin_read16(DMA21_PERIPHERAL_MAP)
-#define bfin_write_DMA21_PERIPHERAL_MAP(val)    bfin_write16(DMA21_PERIPHERAL_MAP, val)
-#define bfin_read_DMA21_CURR_X_COUNT()          bfin_read16(DMA21_CURR_X_COUNT)
-#define bfin_write_DMA21_CURR_X_COUNT(val)      bfin_write16(DMA21_CURR_X_COUNT, val)
-#define bfin_read_DMA21_CURR_Y_COUNT()          bfin_read16(DMA21_CURR_Y_COUNT)
-#define bfin_write_DMA21_CURR_Y_COUNT(val)      bfin_write16(DMA21_CURR_Y_COUNT, val)
-
-/* DMA Channel 22 Registers */
-
-#define bfin_read_DMA22_NEXT_DESC_PTR()         bfin_read32(DMA22_NEXT_DESC_PTR)
-#define bfin_write_DMA22_NEXT_DESC_PTR(val)     bfin_write32(DMA22_NEXT_DESC_PTR, val)
-#define bfin_read_DMA22_START_ADDR()            bfin_read32(DMA22_START_ADDR)
-#define bfin_write_DMA22_START_ADDR(val)        bfin_write32(DMA22_START_ADDR, val)
-#define bfin_read_DMA22_CONFIG()                bfin_read16(DMA22_CONFIG)
-#define bfin_write_DMA22_CONFIG(val)            bfin_write16(DMA22_CONFIG, val)
-#define bfin_read_DMA22_X_COUNT()               bfin_read16(DMA22_X_COUNT)
-#define bfin_write_DMA22_X_COUNT(val)           bfin_write16(DMA22_X_COUNT, val)
-#define bfin_read_DMA22_X_MODIFY()              bfin_read16(DMA22_X_MODIFY)
-#define bfin_write_DMA22_X_MODIFY(val)          bfin_write16(DMA22_X_MODIFY, val)
-#define bfin_read_DMA22_Y_COUNT()               bfin_read16(DMA22_Y_COUNT)
-#define bfin_write_DMA22_Y_COUNT(val)           bfin_write16(DMA22_Y_COUNT, val)
-#define bfin_read_DMA22_Y_MODIFY()              bfin_read16(DMA22_Y_MODIFY)
-#define bfin_write_DMA22_Y_MODIFY(val)          bfin_write16(DMA22_Y_MODIFY, val)
-#define bfin_read_DMA22_CURR_DESC_PTR()         bfin_read32(DMA22_CURR_DESC_PTR)
-#define bfin_write_DMA22_CURR_DESC_PTR(val)     bfin_write32(DMA22_CURR_DESC_PTR, val)
-#define bfin_read_DMA22_CURR_ADDR()             bfin_read32(DMA22_CURR_ADDR)
-#define bfin_write_DMA22_CURR_ADDR(val)         bfin_write32(DMA22_CURR_ADDR, val)
-#define bfin_read_DMA22_IRQ_STATUS()            bfin_read16(DMA22_IRQ_STATUS)
-#define bfin_write_DMA22_IRQ_STATUS(val)        bfin_write16(DMA22_IRQ_STATUS, val)
-#define bfin_read_DMA22_PERIPHERAL_MAP()        bfin_read16(DMA22_PERIPHERAL_MAP)
-#define bfin_write_DMA22_PERIPHERAL_MAP(val)    bfin_write16(DMA22_PERIPHERAL_MAP, val)
-#define bfin_read_DMA22_CURR_X_COUNT()          bfin_read16(DMA22_CURR_X_COUNT)
-#define bfin_write_DMA22_CURR_X_COUNT(val)      bfin_write16(DMA22_CURR_X_COUNT, val)
-#define bfin_read_DMA22_CURR_Y_COUNT()          bfin_read16(DMA22_CURR_Y_COUNT)
-#define bfin_write_DMA22_CURR_Y_COUNT(val)      bfin_write16(DMA22_CURR_Y_COUNT, val)
-
-/* DMA Channel 23 Registers */
-
-#define bfin_read_DMA23_NEXT_DESC_PTR()                 bfin_read32(DMA23_NEXT_DESC_PTR)
-#define bfin_write_DMA23_NEXT_DESC_PTR(val)             bfin_write32(DMA23_NEXT_DESC_PTR, val)
-#define bfin_read_DMA23_START_ADDR()                    bfin_read32(DMA23_START_ADDR)
-#define bfin_write_DMA23_START_ADDR(val)                bfin_write32(DMA23_START_ADDR, val)
-#define bfin_read_DMA23_CONFIG()                        bfin_read16(DMA23_CONFIG)
-#define bfin_write_DMA23_CONFIG(val)                    bfin_write16(DMA23_CONFIG, val)
-#define bfin_read_DMA23_X_COUNT()                       bfin_read16(DMA23_X_COUNT)
-#define bfin_write_DMA23_X_COUNT(val)                   bfin_write16(DMA23_X_COUNT, val)
-#define bfin_read_DMA23_X_MODIFY()                      bfin_read16(DMA23_X_MODIFY)
-#define bfin_write_DMA23_X_MODIFY(val)                  bfin_write16(DMA23_X_MODIFY, val)
-#define bfin_read_DMA23_Y_COUNT()                       bfin_read16(DMA23_Y_COUNT)
-#define bfin_write_DMA23_Y_COUNT(val)                   bfin_write16(DMA23_Y_COUNT, val)
-#define bfin_read_DMA23_Y_MODIFY()                      bfin_read16(DMA23_Y_MODIFY)
-#define bfin_write_DMA23_Y_MODIFY(val)                  bfin_write16(DMA23_Y_MODIFY, val)
-#define bfin_read_DMA23_CURR_DESC_PTR()                 bfin_read32(DMA23_CURR_DESC_PTR)
-#define bfin_write_DMA23_CURR_DESC_PTR(val)             bfin_write32(DMA23_CURR_DESC_PTR, val)
-#define bfin_read_DMA23_CURR_ADDR()                     bfin_read32(DMA23_CURR_ADDR)
-#define bfin_write_DMA23_CURR_ADDR(val)                 bfin_write32(DMA23_CURR_ADDR, val)
-#define bfin_read_DMA23_IRQ_STATUS()                    bfin_read16(DMA23_IRQ_STATUS)
-#define bfin_write_DMA23_IRQ_STATUS(val)                bfin_write16(DMA23_IRQ_STATUS, val)
-#define bfin_read_DMA23_PERIPHERAL_MAP()                bfin_read16(DMA23_PERIPHERAL_MAP)
-#define bfin_write_DMA23_PERIPHERAL_MAP(val)            bfin_write16(DMA23_PERIPHERAL_MAP, val)
-#define bfin_read_DMA23_CURR_X_COUNT()                  bfin_read16(DMA23_CURR_X_COUNT)
-#define bfin_write_DMA23_CURR_X_COUNT(val)              bfin_write16(DMA23_CURR_X_COUNT, val)
-#define bfin_read_DMA23_CURR_Y_COUNT()                  bfin_read16(DMA23_CURR_Y_COUNT)
-#define bfin_write_DMA23_CURR_Y_COUNT(val)              bfin_write16(DMA23_CURR_Y_COUNT, val)
-
-/* MDMA Stream 2 Registers */
-
-#define bfin_read_MDMA_D2_NEXT_DESC_PTR()               bfin_read32(MDMA_D2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D2_NEXT_DESC_PTR(val)           bfin_write32(MDMA_D2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D2_START_ADDR()                  bfin_read32(MDMA_D2_START_ADDR)
-#define bfin_write_MDMA_D2_START_ADDR(val)              bfin_write32(MDMA_D2_START_ADDR, val)
-#define bfin_read_MDMA_D2_CONFIG()                      bfin_read16(MDMA_D2_CONFIG)
-#define bfin_write_MDMA_D2_CONFIG(val)                  bfin_write16(MDMA_D2_CONFIG, val)
-#define bfin_read_MDMA_D2_X_COUNT()                     bfin_read16(MDMA_D2_X_COUNT)
-#define bfin_write_MDMA_D2_X_COUNT(val)                 bfin_write16(MDMA_D2_X_COUNT, val)
-#define bfin_read_MDMA_D2_X_MODIFY()                    bfin_read16(MDMA_D2_X_MODIFY)
-#define bfin_write_MDMA_D2_X_MODIFY(val)                bfin_write16(MDMA_D2_X_MODIFY, val)
-#define bfin_read_MDMA_D2_Y_COUNT()                     bfin_read16(MDMA_D2_Y_COUNT)
-#define bfin_write_MDMA_D2_Y_COUNT(val)                 bfin_write16(MDMA_D2_Y_COUNT, val)
-#define bfin_read_MDMA_D2_Y_MODIFY()                    bfin_read16(MDMA_D2_Y_MODIFY)
-#define bfin_write_MDMA_D2_Y_MODIFY(val)                bfin_write16(MDMA_D2_Y_MODIFY, val)
-#define bfin_read_MDMA_D2_CURR_DESC_PTR()               bfin_read32(MDMA_D2_CURR_DESC_PTR)
-#define bfin_write_MDMA_D2_CURR_DESC_PTR(val)           bfin_write32(MDMA_D2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D2_CURR_ADDR()                   bfin_read32(MDMA_D2_CURR_ADDR)
-#define bfin_write_MDMA_D2_CURR_ADDR(val)               bfin_write32(MDMA_D2_CURR_ADDR, val)
-#define bfin_read_MDMA_D2_IRQ_STATUS()                  bfin_read16(MDMA_D2_IRQ_STATUS)
-#define bfin_write_MDMA_D2_IRQ_STATUS(val)              bfin_write16(MDMA_D2_IRQ_STATUS, val)
-#define bfin_read_MDMA_D2_PERIPHERAL_MAP()              bfin_read16(MDMA_D2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D2_PERIPHERAL_MAP(val)          bfin_write16(MDMA_D2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D2_CURR_X_COUNT()                bfin_read16(MDMA_D2_CURR_X_COUNT)
-#define bfin_write_MDMA_D2_CURR_X_COUNT(val)            bfin_write16(MDMA_D2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D2_CURR_Y_COUNT()                bfin_read16(MDMA_D2_CURR_Y_COUNT)
-#define bfin_write_MDMA_D2_CURR_Y_COUNT(val)            bfin_write16(MDMA_D2_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S2_NEXT_DESC_PTR()               bfin_read32(MDMA_S2_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S2_NEXT_DESC_PTR(val)           bfin_write32(MDMA_S2_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S2_START_ADDR()                  bfin_read32(MDMA_S2_START_ADDR)
-#define bfin_write_MDMA_S2_START_ADDR(val)              bfin_write32(MDMA_S2_START_ADDR, val)
-#define bfin_read_MDMA_S2_CONFIG()                      bfin_read16(MDMA_S2_CONFIG)
-#define bfin_write_MDMA_S2_CONFIG(val)                  bfin_write16(MDMA_S2_CONFIG, val)
-#define bfin_read_MDMA_S2_X_COUNT()                     bfin_read16(MDMA_S2_X_COUNT)
-#define bfin_write_MDMA_S2_X_COUNT(val)                 bfin_write16(MDMA_S2_X_COUNT, val)
-#define bfin_read_MDMA_S2_X_MODIFY()                    bfin_read16(MDMA_S2_X_MODIFY)
-#define bfin_write_MDMA_S2_X_MODIFY(val)                bfin_write16(MDMA_S2_X_MODIFY, val)
-#define bfin_read_MDMA_S2_Y_COUNT()                     bfin_read16(MDMA_S2_Y_COUNT)
-#define bfin_write_MDMA_S2_Y_COUNT(val)                 bfin_write16(MDMA_S2_Y_COUNT, val)
-#define bfin_read_MDMA_S2_Y_MODIFY()                    bfin_read16(MDMA_S2_Y_MODIFY)
-#define bfin_write_MDMA_S2_Y_MODIFY(val)                bfin_write16(MDMA_S2_Y_MODIFY, val)
-#define bfin_read_MDMA_S2_CURR_DESC_PTR()               bfin_read32(MDMA_S2_CURR_DESC_PTR)
-#define bfin_write_MDMA_S2_CURR_DESC_PTR(val)           bfin_write32(MDMA_S2_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S2_CURR_ADDR()                   bfin_read32(MDMA_S2_CURR_ADDR)
-#define bfin_write_MDMA_S2_CURR_ADDR(val)               bfin_write32(MDMA_S2_CURR_ADDR, val)
-#define bfin_read_MDMA_S2_IRQ_STATUS()                  bfin_read16(MDMA_S2_IRQ_STATUS)
-#define bfin_write_MDMA_S2_IRQ_STATUS(val)              bfin_write16(MDMA_S2_IRQ_STATUS, val)
-#define bfin_read_MDMA_S2_PERIPHERAL_MAP()              bfin_read16(MDMA_S2_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S2_PERIPHERAL_MAP(val)          bfin_write16(MDMA_S2_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S2_CURR_X_COUNT()                bfin_read16(MDMA_S2_CURR_X_COUNT)
-#define bfin_write_MDMA_S2_CURR_X_COUNT(val)            bfin_write16(MDMA_S2_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S2_CURR_Y_COUNT()                bfin_read16(MDMA_S2_CURR_Y_COUNT)
-#define bfin_write_MDMA_S2_CURR_Y_COUNT(val)            bfin_write16(MDMA_S2_CURR_Y_COUNT, val)
-
-/* MDMA Stream 3 Registers */
-
-#define bfin_read_MDMA_D3_NEXT_DESC_PTR()               bfin_read32(MDMA_D3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D3_NEXT_DESC_PTR(val)           bfin_write32(MDMA_D3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D3_START_ADDR()                  bfin_read32(MDMA_D3_START_ADDR)
-#define bfin_write_MDMA_D3_START_ADDR(val)              bfin_write32(MDMA_D3_START_ADDR, val)
-#define bfin_read_MDMA_D3_CONFIG()                      bfin_read16(MDMA_D3_CONFIG)
-#define bfin_write_MDMA_D3_CONFIG(val)                  bfin_write16(MDMA_D3_CONFIG, val)
-#define bfin_read_MDMA_D3_X_COUNT()                     bfin_read16(MDMA_D3_X_COUNT)
-#define bfin_write_MDMA_D3_X_COUNT(val)                 bfin_write16(MDMA_D3_X_COUNT, val)
-#define bfin_read_MDMA_D3_X_MODIFY()                    bfin_read16(MDMA_D3_X_MODIFY)
-#define bfin_write_MDMA_D3_X_MODIFY(val)                bfin_write16(MDMA_D3_X_MODIFY, val)
-#define bfin_read_MDMA_D3_Y_COUNT()                     bfin_read16(MDMA_D3_Y_COUNT)
-#define bfin_write_MDMA_D3_Y_COUNT(val)                 bfin_write16(MDMA_D3_Y_COUNT, val)
-#define bfin_read_MDMA_D3_Y_MODIFY()                    bfin_read16(MDMA_D3_Y_MODIFY)
-#define bfin_write_MDMA_D3_Y_MODIFY(val)                bfin_write16(MDMA_D3_Y_MODIFY, val)
-#define bfin_read_MDMA_D3_CURR_DESC_PTR()               bfin_read32(MDMA_D3_CURR_DESC_PTR)
-#define bfin_write_MDMA_D3_CURR_DESC_PTR(val)           bfin_write32(MDMA_D3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D3_CURR_ADDR()                   bfin_read32(MDMA_D3_CURR_ADDR)
-#define bfin_write_MDMA_D3_CURR_ADDR(val)               bfin_write32(MDMA_D3_CURR_ADDR, val)
-#define bfin_read_MDMA_D3_IRQ_STATUS()                  bfin_read16(MDMA_D3_IRQ_STATUS)
-#define bfin_write_MDMA_D3_IRQ_STATUS(val)              bfin_write16(MDMA_D3_IRQ_STATUS, val)
-#define bfin_read_MDMA_D3_PERIPHERAL_MAP()              bfin_read16(MDMA_D3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D3_PERIPHERAL_MAP(val)          bfin_write16(MDMA_D3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D3_CURR_X_COUNT()                bfin_read16(MDMA_D3_CURR_X_COUNT)
-#define bfin_write_MDMA_D3_CURR_X_COUNT(val)            bfin_write16(MDMA_D3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D3_CURR_Y_COUNT()                bfin_read16(MDMA_D3_CURR_Y_COUNT)
-#define bfin_write_MDMA_D3_CURR_Y_COUNT(val)            bfin_write16(MDMA_D3_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S3_NEXT_DESC_PTR()               bfin_read32(MDMA_S3_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S3_NEXT_DESC_PTR(val)           bfin_write32(MDMA_S3_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S3_START_ADDR()                  bfin_read32(MDMA_S3_START_ADDR)
-#define bfin_write_MDMA_S3_START_ADDR(val)              bfin_write32(MDMA_S3_START_ADDR, val)
-#define bfin_read_MDMA_S3_CONFIG()                      bfin_read16(MDMA_S3_CONFIG)
-#define bfin_write_MDMA_S3_CONFIG(val)                  bfin_write16(MDMA_S3_CONFIG, val)
-#define bfin_read_MDMA_S3_X_COUNT()                     bfin_read16(MDMA_S3_X_COUNT)
-#define bfin_write_MDMA_S3_X_COUNT(val)                 bfin_write16(MDMA_S3_X_COUNT, val)
-#define bfin_read_MDMA_S3_X_MODIFY()                    bfin_read16(MDMA_S3_X_MODIFY)
-#define bfin_write_MDMA_S3_X_MODIFY(val)                bfin_write16(MDMA_S3_X_MODIFY, val)
-#define bfin_read_MDMA_S3_Y_COUNT()                     bfin_read16(MDMA_S3_Y_COUNT)
-#define bfin_write_MDMA_S3_Y_COUNT(val)                 bfin_write16(MDMA_S3_Y_COUNT, val)
-#define bfin_read_MDMA_S3_Y_MODIFY()                    bfin_read16(MDMA_S3_Y_MODIFY)
-#define bfin_write_MDMA_S3_Y_MODIFY(val)                bfin_write16(MDMA_S3_Y_MODIFY, val)
-#define bfin_read_MDMA_S3_CURR_DESC_PTR()               bfin_read32(MDMA_S3_CURR_DESC_PTR)
-#define bfin_write_MDMA_S3_CURR_DESC_PTR(val)           bfin_write32(MDMA_S3_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S3_CURR_ADDR()                   bfin_read32(MDMA_S3_CURR_ADDR)
-#define bfin_write_MDMA_S3_CURR_ADDR(val)               bfin_write32(MDMA_S3_CURR_ADDR, val)
-#define bfin_read_MDMA_S3_IRQ_STATUS()                  bfin_read16(MDMA_S3_IRQ_STATUS)
-#define bfin_write_MDMA_S3_IRQ_STATUS(val)              bfin_write16(MDMA_S3_IRQ_STATUS, val)
-#define bfin_read_MDMA_S3_PERIPHERAL_MAP()              bfin_read16(MDMA_S3_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S3_PERIPHERAL_MAP(val)          bfin_write16(MDMA_S3_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S3_CURR_X_COUNT()                bfin_read16(MDMA_S3_CURR_X_COUNT)
-#define bfin_write_MDMA_S3_CURR_X_COUNT(val)            bfin_write16(MDMA_S3_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S3_CURR_Y_COUNT()                bfin_read16(MDMA_S3_CURR_Y_COUNT)
-#define bfin_write_MDMA_S3_CURR_Y_COUNT(val)            bfin_write16(MDMA_S3_CURR_Y_COUNT, val)
-
-/* UART1 Registers */
-
-#define bfin_read_UART1_DLL()                   bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)               bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH()                   bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)               bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL()                  bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)              bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR()                   bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)               bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()                   bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)               bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()                   bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)               bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()                   bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)               bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()                   bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)               bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET()               bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val)           bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR()             bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val)         bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR()                   bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)               bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()                   bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)               bfin_write16(UART1_RBR, val)
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 bfin_read_()rocessors */
-
-/* SPI1 Registers */
-
-#define bfin_read_SPI1_CTL()                    bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)                bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()                    bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)                bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()                   bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)               bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()                   bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)               bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()                   bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)               bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()                   bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)               bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()                 bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)             bfin_write16(SPI1_SHADOW, val)
-
-/* SPORT2 Registers */
-
-#define bfin_read_SPORT2_TCR1()                 bfin_read16(SPORT2_TCR1)
-#define bfin_write_SPORT2_TCR1(val)             bfin_write16(SPORT2_TCR1, val)
-#define bfin_read_SPORT2_TCR2()                 bfin_read16(SPORT2_TCR2)
-#define bfin_write_SPORT2_TCR2(val)             bfin_write16(SPORT2_TCR2, val)
-#define bfin_read_SPORT2_TCLKDIV()              bfin_read16(SPORT2_TCLKDIV)
-#define bfin_write_SPORT2_TCLKDIV(val)          bfin_write16(SPORT2_TCLKDIV, val)
-#define bfin_read_SPORT2_TFSDIV()               bfin_read16(SPORT2_TFSDIV)
-#define bfin_write_SPORT2_TFSDIV(val)           bfin_write16(SPORT2_TFSDIV, val)
-#define bfin_read_SPORT2_TX()                   bfin_read32(SPORT2_TX)
-#define bfin_write_SPORT2_TX(val)               bfin_write32(SPORT2_TX, val)
-#define bfin_read_SPORT2_RX()                   bfin_read32(SPORT2_RX)
-#define bfin_write_SPORT2_RX(val)               bfin_write32(SPORT2_RX, val)
-#define bfin_read_SPORT2_RCR1()                 bfin_read16(SPORT2_RCR1)
-#define bfin_write_SPORT2_RCR1(val)             bfin_write16(SPORT2_RCR1, val)
-#define bfin_read_SPORT2_RCR2()                 bfin_read16(SPORT2_RCR2)
-#define bfin_write_SPORT2_RCR2(val)             bfin_write16(SPORT2_RCR2, val)
-#define bfin_read_SPORT2_RCLKDIV()              bfin_read16(SPORT2_RCLKDIV)
-#define bfin_write_SPORT2_RCLKDIV(val)          bfin_write16(SPORT2_RCLKDIV, val)
-#define bfin_read_SPORT2_RFSDIV()               bfin_read16(SPORT2_RFSDIV)
-#define bfin_write_SPORT2_RFSDIV(val)           bfin_write16(SPORT2_RFSDIV, val)
-#define bfin_read_SPORT2_STAT()                 bfin_read16(SPORT2_STAT)
-#define bfin_write_SPORT2_STAT(val)             bfin_write16(SPORT2_STAT, val)
-#define bfin_read_SPORT2_CHNL()                 bfin_read16(SPORT2_CHNL)
-#define bfin_write_SPORT2_CHNL(val)             bfin_write16(SPORT2_CHNL, val)
-#define bfin_read_SPORT2_MCMC1()                bfin_read16(SPORT2_MCMC1)
-#define bfin_write_SPORT2_MCMC1(val)            bfin_write16(SPORT2_MCMC1, val)
-#define bfin_read_SPORT2_MCMC2()                bfin_read16(SPORT2_MCMC2)
-#define bfin_write_SPORT2_MCMC2(val)            bfin_write16(SPORT2_MCMC2, val)
-#define bfin_read_SPORT2_MTCS0()                bfin_read32(SPORT2_MTCS0)
-#define bfin_write_SPORT2_MTCS0(val)            bfin_write32(SPORT2_MTCS0, val)
-#define bfin_read_SPORT2_MTCS1()                bfin_read32(SPORT2_MTCS1)
-#define bfin_write_SPORT2_MTCS1(val)            bfin_write32(SPORT2_MTCS1, val)
-#define bfin_read_SPORT2_MTCS2()                bfin_read32(SPORT2_MTCS2)
-#define bfin_write_SPORT2_MTCS2(val)            bfin_write32(SPORT2_MTCS2, val)
-#define bfin_read_SPORT2_MTCS3()                bfin_read32(SPORT2_MTCS3)
-#define bfin_write_SPORT2_MTCS3(val)            bfin_write32(SPORT2_MTCS3, val)
-#define bfin_read_SPORT2_MRCS0()                bfin_read32(SPORT2_MRCS0)
-#define bfin_write_SPORT2_MRCS0(val)            bfin_write32(SPORT2_MRCS0, val)
-#define bfin_read_SPORT2_MRCS1()                bfin_read32(SPORT2_MRCS1)
-#define bfin_write_SPORT2_MRCS1(val)            bfin_write32(SPORT2_MRCS1, val)
-#define bfin_read_SPORT2_MRCS2()                bfin_read32(SPORT2_MRCS2)
-#define bfin_write_SPORT2_MRCS2(val)            bfin_write32(SPORT2_MRCS2, val)
-#define bfin_read_SPORT2_MRCS3()                bfin_read32(SPORT2_MRCS3)
-#define bfin_write_SPORT2_MRCS3(val)            bfin_write32(SPORT2_MRCS3, val)
-
-/* SPORT3 Registers */
-
-#define bfin_read_SPORT3_TCR1()                 bfin_read16(SPORT3_TCR1)
-#define bfin_write_SPORT3_TCR1(val)             bfin_write16(SPORT3_TCR1, val)
-#define bfin_read_SPORT3_TCR2()                 bfin_read16(SPORT3_TCR2)
-#define bfin_write_SPORT3_TCR2(val)             bfin_write16(SPORT3_TCR2, val)
-#define bfin_read_SPORT3_TCLKDIV()              bfin_read16(SPORT3_TCLKDIV)
-#define bfin_write_SPORT3_TCLKDIV(val)          bfin_write16(SPORT3_TCLKDIV, val)
-#define bfin_read_SPORT3_TFSDIV()               bfin_read16(SPORT3_TFSDIV)
-#define bfin_write_SPORT3_TFSDIV(val)           bfin_write16(SPORT3_TFSDIV, val)
-#define bfin_read_SPORT3_TX()                   bfin_read32(SPORT3_TX)
-#define bfin_write_SPORT3_TX(val)               bfin_write32(SPORT3_TX, val)
-#define bfin_read_SPORT3_RX()                   bfin_read32(SPORT3_RX)
-#define bfin_write_SPORT3_RX(val)               bfin_write32(SPORT3_RX, val)
-#define bfin_read_SPORT3_RCR1()                 bfin_read16(SPORT3_RCR1)
-#define bfin_write_SPORT3_RCR1(val)             bfin_write16(SPORT3_RCR1, val)
-#define bfin_read_SPORT3_RCR2()                 bfin_read16(SPORT3_RCR2)
-#define bfin_write_SPORT3_RCR2(val)             bfin_write16(SPORT3_RCR2, val)
-#define bfin_read_SPORT3_RCLKDIV()              bfin_read16(SPORT3_RCLKDIV)
-#define bfin_write_SPORT3_RCLKDIV(val)          bfin_write16(SPORT3_RCLKDIV, val)
-#define bfin_read_SPORT3_RFSDIV()               bfin_read16(SPORT3_RFSDIV)
-#define bfin_write_SPORT3_RFSDIV(val)           bfin_write16(SPORT3_RFSDIV, val)
-#define bfin_read_SPORT3_STAT()                 bfin_read16(SPORT3_STAT)
-#define bfin_write_SPORT3_STAT(val)             bfin_write16(SPORT3_STAT, val)
-#define bfin_read_SPORT3_CHNL()                 bfin_read16(SPORT3_CHNL)
-#define bfin_write_SPORT3_CHNL(val)             bfin_write16(SPORT3_CHNL, val)
-#define bfin_read_SPORT3_MCMC1()                bfin_read16(SPORT3_MCMC1)
-#define bfin_write_SPORT3_MCMC1(val)            bfin_write16(SPORT3_MCMC1, val)
-#define bfin_read_SPORT3_MCMC2()                bfin_read16(SPORT3_MCMC2)
-#define bfin_write_SPORT3_MCMC2(val)            bfin_write16(SPORT3_MCMC2, val)
-#define bfin_read_SPORT3_MTCS0()                bfin_read32(SPORT3_MTCS0)
-#define bfin_write_SPORT3_MTCS0(val)            bfin_write32(SPORT3_MTCS0, val)
-#define bfin_read_SPORT3_MTCS1()                bfin_read32(SPORT3_MTCS1)
-#define bfin_write_SPORT3_MTCS1(val)            bfin_write32(SPORT3_MTCS1, val)
-#define bfin_read_SPORT3_MTCS2()                bfin_read32(SPORT3_MTCS2)
-#define bfin_write_SPORT3_MTCS2(val)            bfin_write32(SPORT3_MTCS2, val)
-#define bfin_read_SPORT3_MTCS3()                bfin_read32(SPORT3_MTCS3)
-#define bfin_write_SPORT3_MTCS3(val)            bfin_write32(SPORT3_MTCS3, val)
-#define bfin_read_SPORT3_MRCS0()                bfin_read32(SPORT3_MRCS0)
-#define bfin_write_SPORT3_MRCS0(val)            bfin_write32(SPORT3_MRCS0, val)
-#define bfin_read_SPORT3_MRCS1()                bfin_read32(SPORT3_MRCS1)
-#define bfin_write_SPORT3_MRCS1(val)            bfin_write32(SPORT3_MRCS1, val)
-#define bfin_read_SPORT3_MRCS2()                bfin_read32(SPORT3_MRCS2)
-#define bfin_write_SPORT3_MRCS2(val)            bfin_write32(SPORT3_MRCS2, val)
-#define bfin_read_SPORT3_MRCS3()                bfin_read32(SPORT3_MRCS3)
-#define bfin_write_SPORT3_MRCS3(val)            bfin_write32(SPORT3_MRCS3, val)
-
-/* EPPI2 Registers */
-
-#define bfin_read_EPPI2_STATUS()                bfin_read16(EPPI2_STATUS)
-#define bfin_write_EPPI2_STATUS(val)            bfin_write16(EPPI2_STATUS, val)
-#define bfin_read_EPPI2_HCOUNT()                bfin_read16(EPPI2_HCOUNT)
-#define bfin_write_EPPI2_HCOUNT(val)            bfin_write16(EPPI2_HCOUNT, val)
-#define bfin_read_EPPI2_HDELAY()                bfin_read16(EPPI2_HDELAY)
-#define bfin_write_EPPI2_HDELAY(val)            bfin_write16(EPPI2_HDELAY, val)
-#define bfin_read_EPPI2_VCOUNT()                bfin_read16(EPPI2_VCOUNT)
-#define bfin_write_EPPI2_VCOUNT(val)            bfin_write16(EPPI2_VCOUNT, val)
-#define bfin_read_EPPI2_VDELAY()                bfin_read16(EPPI2_VDELAY)
-#define bfin_write_EPPI2_VDELAY(val)            bfin_write16(EPPI2_VDELAY, val)
-#define bfin_read_EPPI2_FRAME()                 bfin_read16(EPPI2_FRAME)
-#define bfin_write_EPPI2_FRAME(val)             bfin_write16(EPPI2_FRAME, val)
-#define bfin_read_EPPI2_LINE()                  bfin_read16(EPPI2_LINE)
-#define bfin_write_EPPI2_LINE(val)              bfin_write16(EPPI2_LINE, val)
-#define bfin_read_EPPI2_CLKDIV()                bfin_read16(EPPI2_CLKDIV)
-#define bfin_write_EPPI2_CLKDIV(val)            bfin_write16(EPPI2_CLKDIV, val)
-#define bfin_read_EPPI2_CONTROL()               bfin_read32(EPPI2_CONTROL)
-#define bfin_write_EPPI2_CONTROL(val)           bfin_write32(EPPI2_CONTROL, val)
-#define bfin_read_EPPI2_FS1W_HBL()              bfin_read32(EPPI2_FS1W_HBL)
-#define bfin_write_EPPI2_FS1W_HBL(val)          bfin_write32(EPPI2_FS1W_HBL, val)
-#define bfin_read_EPPI2_FS1P_AVPL()             bfin_read32(EPPI2_FS1P_AVPL)
-#define bfin_write_EPPI2_FS1P_AVPL(val)         bfin_write32(EPPI2_FS1P_AVPL, val)
-#define bfin_read_EPPI2_FS2W_LVB()              bfin_read32(EPPI2_FS2W_LVB)
-#define bfin_write_EPPI2_FS2W_LVB(val)          bfin_write32(EPPI2_FS2W_LVB, val)
-#define bfin_read_EPPI2_FS2P_LAVF()             bfin_read32(EPPI2_FS2P_LAVF)
-#define bfin_write_EPPI2_FS2P_LAVF(val)         bfin_write32(EPPI2_FS2P_LAVF, val)
-#define bfin_read_EPPI2_CLIP()                  bfin_read32(EPPI2_CLIP)
-#define bfin_write_EPPI2_CLIP(val)              bfin_write32(EPPI2_CLIP, val)
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define bfin_read_CAN0_MC1()            bfin_read16(CAN0_MC1)
-#define bfin_write_CAN0_MC1(val)        bfin_write16(CAN0_MC1, val)
-#define bfin_read_CAN0_MD1()            bfin_read16(CAN0_MD1)
-#define bfin_write_CAN0_MD1(val)        bfin_write16(CAN0_MD1, val)
-#define bfin_read_CAN0_TRS1()           bfin_read16(CAN0_TRS1)
-#define bfin_write_CAN0_TRS1(val)       bfin_write16(CAN0_TRS1, val)
-#define bfin_read_CAN0_TRR1()           bfin_read16(CAN0_TRR1)
-#define bfin_write_CAN0_TRR1(val)       bfin_write16(CAN0_TRR1, val)
-#define bfin_read_CAN0_TA1()            bfin_read16(CAN0_TA1)
-#define bfin_write_CAN0_TA1(val)        bfin_write16(CAN0_TA1, val)
-#define bfin_read_CAN0_AA1()            bfin_read16(CAN0_AA1)
-#define bfin_write_CAN0_AA1(val)        bfin_write16(CAN0_AA1, val)
-#define bfin_read_CAN0_RMP1()           bfin_read16(CAN0_RMP1)
-#define bfin_write_CAN0_RMP1(val)       bfin_write16(CAN0_RMP1, val)
-#define bfin_read_CAN0_RML1()           bfin_read16(CAN0_RML1)
-#define bfin_write_CAN0_RML1(val)       bfin_write16(CAN0_RML1, val)
-#define bfin_read_CAN0_MBTIF1()         bfin_read16(CAN0_MBTIF1)
-#define bfin_write_CAN0_MBTIF1(val)     bfin_write16(CAN0_MBTIF1, val)
-#define bfin_read_CAN0_MBRIF1()         bfin_read16(CAN0_MBRIF1)
-#define bfin_write_CAN0_MBRIF1(val)     bfin_write16(CAN0_MBRIF1, val)
-#define bfin_read_CAN0_MBIM1()          bfin_read16(CAN0_MBIM1)
-#define bfin_write_CAN0_MBIM1(val)      bfin_write16(CAN0_MBIM1, val)
-#define bfin_read_CAN0_RFH1()           bfin_read16(CAN0_RFH1)
-#define bfin_write_CAN0_RFH1(val)       bfin_write16(CAN0_RFH1, val)
-#define bfin_read_CAN0_OPSS1()          bfin_read16(CAN0_OPSS1)
-#define bfin_write_CAN0_OPSS1(val)      bfin_write16(CAN0_OPSS1, val)
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define bfin_read_CAN0_MC2()            bfin_read16(CAN0_MC2)
-#define bfin_write_CAN0_MC2(val)        bfin_write16(CAN0_MC2, val)
-#define bfin_read_CAN0_MD2()            bfin_read16(CAN0_MD2)
-#define bfin_write_CAN0_MD2(val)        bfin_write16(CAN0_MD2, val)
-#define bfin_read_CAN0_TRS2()           bfin_read16(CAN0_TRS2)
-#define bfin_write_CAN0_TRS2(val)       bfin_write16(CAN0_TRS2, val)
-#define bfin_read_CAN0_TRR2()           bfin_read16(CAN0_TRR2)
-#define bfin_write_CAN0_TRR2(val)       bfin_write16(CAN0_TRR2, val)
-#define bfin_read_CAN0_TA2()            bfin_read16(CAN0_TA2)
-#define bfin_write_CAN0_TA2(val)        bfin_write16(CAN0_TA2, val)
-#define bfin_read_CAN0_AA2()            bfin_read16(CAN0_AA2)
-#define bfin_write_CAN0_AA2(val)        bfin_write16(CAN0_AA2, val)
-#define bfin_read_CAN0_RMP2()           bfin_read16(CAN0_RMP2)
-#define bfin_write_CAN0_RMP2(val)       bfin_write16(CAN0_RMP2, val)
-#define bfin_read_CAN0_RML2()           bfin_read16(CAN0_RML2)
-#define bfin_write_CAN0_RML2(val)       bfin_write16(CAN0_RML2, val)
-#define bfin_read_CAN0_MBTIF2()         bfin_read16(CAN0_MBTIF2)
-#define bfin_write_CAN0_MBTIF2(val)     bfin_write16(CAN0_MBTIF2, val)
-#define bfin_read_CAN0_MBRIF2()         bfin_read16(CAN0_MBRIF2)
-#define bfin_write_CAN0_MBRIF2(val)     bfin_write16(CAN0_MBRIF2, val)
-#define bfin_read_CAN0_MBIM2()          bfin_read16(CAN0_MBIM2)
-#define bfin_write_CAN0_MBIM2(val)      bfin_write16(CAN0_MBIM2, val)
-#define bfin_read_CAN0_RFH2()           bfin_read16(CAN0_RFH2)
-#define bfin_write_CAN0_RFH2(val)       bfin_write16(CAN0_RFH2, val)
-#define bfin_read_CAN0_OPSS2()          bfin_read16(CAN0_OPSS2)
-#define bfin_write_CAN0_OPSS2(val)      bfin_write16(CAN0_OPSS2, val)
-
-/* CAN Controller 0 Clock/Interrubfin_read_()t/Counter Registers */
-
-#define bfin_read_CAN0_CLOCK()          bfin_read16(CAN0_CLOCK)
-#define bfin_write_CAN0_CLOCK(val)      bfin_write16(CAN0_CLOCK, val)
-#define bfin_read_CAN0_TIMING()         bfin_read16(CAN0_TIMING)
-#define bfin_write_CAN0_TIMING(val)     bfin_write16(CAN0_TIMING, val)
-#define bfin_read_CAN0_DEBUG()          bfin_read16(CAN0_DEBUG)
-#define bfin_write_CAN0_DEBUG(val)      bfin_write16(CAN0_DEBUG, val)
-#define bfin_read_CAN0_STATUS()         bfin_read16(CAN0_STATUS)
-#define bfin_write_CAN0_STATUS(val)     bfin_write16(CAN0_STATUS, val)
-#define bfin_read_CAN0_CEC()            bfin_read16(CAN0_CEC)
-#define bfin_write_CAN0_CEC(val)        bfin_write16(CAN0_CEC, val)
-#define bfin_read_CAN0_GIS()            bfin_read16(CAN0_GIS)
-#define bfin_write_CAN0_GIS(val)        bfin_write16(CAN0_GIS, val)
-#define bfin_read_CAN0_GIM()            bfin_read16(CAN0_GIM)
-#define bfin_write_CAN0_GIM(val)        bfin_write16(CAN0_GIM, val)
-#define bfin_read_CAN0_GIF()            bfin_read16(CAN0_GIF)
-#define bfin_write_CAN0_GIF(val)        bfin_write16(CAN0_GIF, val)
-#define bfin_read_CAN0_CONTROL()        bfin_read16(CAN0_CONTROL)
-#define bfin_write_CAN0_CONTROL(val)    bfin_write16(CAN0_CONTROL, val)
-#define bfin_read_CAN0_INTR()           bfin_read16(CAN0_INTR)
-#define bfin_write_CAN0_INTR(val)       bfin_write16(CAN0_INTR, val)
-#define bfin_read_CAN0_MBTD()           bfin_read16(CAN0_MBTD)
-#define bfin_write_CAN0_MBTD(val)       bfin_write16(CAN0_MBTD, val)
-#define bfin_read_CAN0_EWR()            bfin_read16(CAN0_EWR)
-#define bfin_write_CAN0_EWR(val)        bfin_write16(CAN0_EWR, val)
-#define bfin_read_CAN0_ESR()            bfin_read16(CAN0_ESR)
-#define bfin_write_CAN0_ESR(val)        bfin_write16(CAN0_ESR, val)
-#define bfin_read_CAN0_UCCNT()          bfin_read16(CAN0_UCCNT)
-#define bfin_write_CAN0_UCCNT(val)      bfin_write16(CAN0_UCCNT, val)
-#define bfin_read_CAN0_UCRC()           bfin_read16(CAN0_UCRC)
-#define bfin_write_CAN0_UCRC(val)       bfin_write16(CAN0_UCRC, val)
-#define bfin_read_CAN0_UCCNF()          bfin_read16(CAN0_UCCNF)
-#define bfin_write_CAN0_UCCNF(val)      bfin_write16(CAN0_UCCNF, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM00L()          bfin_read16(CAN0_AM00L)
-#define bfin_write_CAN0_AM00L(val)      bfin_write16(CAN0_AM00L, val)
-#define bfin_read_CAN0_AM00H()          bfin_read16(CAN0_AM00H)
-#define bfin_write_CAN0_AM00H(val)      bfin_write16(CAN0_AM00H, val)
-#define bfin_read_CAN0_AM01L()          bfin_read16(CAN0_AM01L)
-#define bfin_write_CAN0_AM01L(val)      bfin_write16(CAN0_AM01L, val)
-#define bfin_read_CAN0_AM01H()          bfin_read16(CAN0_AM01H)
-#define bfin_write_CAN0_AM01H(val)      bfin_write16(CAN0_AM01H, val)
-#define bfin_read_CAN0_AM02L()          bfin_read16(CAN0_AM02L)
-#define bfin_write_CAN0_AM02L(val)      bfin_write16(CAN0_AM02L, val)
-#define bfin_read_CAN0_AM02H()          bfin_read16(CAN0_AM02H)
-#define bfin_write_CAN0_AM02H(val)      bfin_write16(CAN0_AM02H, val)
-#define bfin_read_CAN0_AM03L()          bfin_read16(CAN0_AM03L)
-#define bfin_write_CAN0_AM03L(val)      bfin_write16(CAN0_AM03L, val)
-#define bfin_read_CAN0_AM03H()          bfin_read16(CAN0_AM03H)
-#define bfin_write_CAN0_AM03H(val)      bfin_write16(CAN0_AM03H, val)
-#define bfin_read_CAN0_AM04L()          bfin_read16(CAN0_AM04L)
-#define bfin_write_CAN0_AM04L(val)      bfin_write16(CAN0_AM04L, val)
-#define bfin_read_CAN0_AM04H()          bfin_read16(CAN0_AM04H)
-#define bfin_write_CAN0_AM04H(val)      bfin_write16(CAN0_AM04H, val)
-#define bfin_read_CAN0_AM05L()          bfin_read16(CAN0_AM05L)
-#define bfin_write_CAN0_AM05L(val)      bfin_write16(CAN0_AM05L, val)
-#define bfin_read_CAN0_AM05H()          bfin_read16(CAN0_AM05H)
-#define bfin_write_CAN0_AM05H(val)      bfin_write16(CAN0_AM05H, val)
-#define bfin_read_CAN0_AM06L()          bfin_read16(CAN0_AM06L)
-#define bfin_write_CAN0_AM06L(val)      bfin_write16(CAN0_AM06L, val)
-#define bfin_read_CAN0_AM06H()          bfin_read16(CAN0_AM06H)
-#define bfin_write_CAN0_AM06H(val)      bfin_write16(CAN0_AM06H, val)
-#define bfin_read_CAN0_AM07L()          bfin_read16(CAN0_AM07L)
-#define bfin_write_CAN0_AM07L(val)      bfin_write16(CAN0_AM07L, val)
-#define bfin_read_CAN0_AM07H()          bfin_read16(CAN0_AM07H)
-#define bfin_write_CAN0_AM07H(val)      bfin_write16(CAN0_AM07H, val)
-#define bfin_read_CAN0_AM08L()          bfin_read16(CAN0_AM08L)
-#define bfin_write_CAN0_AM08L(val)      bfin_write16(CAN0_AM08L, val)
-#define bfin_read_CAN0_AM08H()          bfin_read16(CAN0_AM08H)
-#define bfin_write_CAN0_AM08H(val)      bfin_write16(CAN0_AM08H, val)
-#define bfin_read_CAN0_AM09L()          bfin_read16(CAN0_AM09L)
-#define bfin_write_CAN0_AM09L(val)      bfin_write16(CAN0_AM09L, val)
-#define bfin_read_CAN0_AM09H()          bfin_read16(CAN0_AM09H)
-#define bfin_write_CAN0_AM09H(val)      bfin_write16(CAN0_AM09H, val)
-#define bfin_read_CAN0_AM10L()          bfin_read16(CAN0_AM10L)
-#define bfin_write_CAN0_AM10L(val)      bfin_write16(CAN0_AM10L, val)
-#define bfin_read_CAN0_AM10H()          bfin_read16(CAN0_AM10H)
-#define bfin_write_CAN0_AM10H(val)      bfin_write16(CAN0_AM10H, val)
-#define bfin_read_CAN0_AM11L()          bfin_read16(CAN0_AM11L)
-#define bfin_write_CAN0_AM11L(val)      bfin_write16(CAN0_AM11L, val)
-#define bfin_read_CAN0_AM11H()          bfin_read16(CAN0_AM11H)
-#define bfin_write_CAN0_AM11H(val)      bfin_write16(CAN0_AM11H, val)
-#define bfin_read_CAN0_AM12L()          bfin_read16(CAN0_AM12L)
-#define bfin_write_CAN0_AM12L(val)      bfin_write16(CAN0_AM12L, val)
-#define bfin_read_CAN0_AM12H()          bfin_read16(CAN0_AM12H)
-#define bfin_write_CAN0_AM12H(val)      bfin_write16(CAN0_AM12H, val)
-#define bfin_read_CAN0_AM13L()          bfin_read16(CAN0_AM13L)
-#define bfin_write_CAN0_AM13L(val)      bfin_write16(CAN0_AM13L, val)
-#define bfin_read_CAN0_AM13H()          bfin_read16(CAN0_AM13H)
-#define bfin_write_CAN0_AM13H(val)      bfin_write16(CAN0_AM13H, val)
-#define bfin_read_CAN0_AM14L()          bfin_read16(CAN0_AM14L)
-#define bfin_write_CAN0_AM14L(val)      bfin_write16(CAN0_AM14L, val)
-#define bfin_read_CAN0_AM14H()          bfin_read16(CAN0_AM14H)
-#define bfin_write_CAN0_AM14H(val)      bfin_write16(CAN0_AM14H, val)
-#define bfin_read_CAN0_AM15L()          bfin_read16(CAN0_AM15L)
-#define bfin_write_CAN0_AM15L(val)      bfin_write16(CAN0_AM15L, val)
-#define bfin_read_CAN0_AM15H()          bfin_read16(CAN0_AM15H)
-#define bfin_write_CAN0_AM15H(val)      bfin_write16(CAN0_AM15H, val)
-
-/* CAN Controller 0 Accebfin_read_()tance Registers */
-
-#define bfin_read_CAN0_AM16L()          bfin_read16(CAN0_AM16L)
-#define bfin_write_CAN0_AM16L(val)      bfin_write16(CAN0_AM16L, val)
-#define bfin_read_CAN0_AM16H()          bfin_read16(CAN0_AM16H)
-#define bfin_write_CAN0_AM16H(val)      bfin_write16(CAN0_AM16H, val)
-#define bfin_read_CAN0_AM17L()          bfin_read16(CAN0_AM17L)
-#define bfin_write_CAN0_AM17L(val)      bfin_write16(CAN0_AM17L, val)
-#define bfin_read_CAN0_AM17H()          bfin_read16(CAN0_AM17H)
-#define bfin_write_CAN0_AM17H(val)      bfin_write16(CAN0_AM17H, val)
-#define bfin_read_CAN0_AM18L()          bfin_read16(CAN0_AM18L)
-#define bfin_write_CAN0_AM18L(val)      bfin_write16(CAN0_AM18L, val)
-#define bfin_read_CAN0_AM18H()          bfin_read16(CAN0_AM18H)
-#define bfin_write_CAN0_AM18H(val)      bfin_write16(CAN0_AM18H, val)
-#define bfin_read_CAN0_AM19L()          bfin_read16(CAN0_AM19L)
-#define bfin_write_CAN0_AM19L(val)      bfin_write16(CAN0_AM19L, val)
-#define bfin_read_CAN0_AM19H()          bfin_read16(CAN0_AM19H)
-#define bfin_write_CAN0_AM19H(val)      bfin_write16(CAN0_AM19H, val)
-#define bfin_read_CAN0_AM20L()          bfin_read16(CAN0_AM20L)
-#define bfin_write_CAN0_AM20L(val)      bfin_write16(CAN0_AM20L, val)
-#define bfin_read_CAN0_AM20H()          bfin_read16(CAN0_AM20H)
-#define bfin_write_CAN0_AM20H(val)      bfin_write16(CAN0_AM20H, val)
-#define bfin_read_CAN0_AM21L()          bfin_read16(CAN0_AM21L)
-#define bfin_write_CAN0_AM21L(val)      bfin_write16(CAN0_AM21L, val)
-#define bfin_read_CAN0_AM21H()          bfin_read16(CAN0_AM21H)
-#define bfin_write_CAN0_AM21H(val)      bfin_write16(CAN0_AM21H, val)
-#define bfin_read_CAN0_AM22L()          bfin_read16(CAN0_AM22L)
-#define bfin_write_CAN0_AM22L(val)      bfin_write16(CAN0_AM22L, val)
-#define bfin_read_CAN0_AM22H()          bfin_read16(CAN0_AM22H)
-#define bfin_write_CAN0_AM22H(val)      bfin_write16(CAN0_AM22H, val)
-#define bfin_read_CAN0_AM23L()          bfin_read16(CAN0_AM23L)
-#define bfin_write_CAN0_AM23L(val)      bfin_write16(CAN0_AM23L, val)
-#define bfin_read_CAN0_AM23H()          bfin_read16(CAN0_AM23H)
-#define bfin_write_CAN0_AM23H(val)      bfin_write16(CAN0_AM23H, val)
-#define bfin_read_CAN0_AM24L()          bfin_read16(CAN0_AM24L)
-#define bfin_write_CAN0_AM24L(val)      bfin_write16(CAN0_AM24L, val)
-#define bfin_read_CAN0_AM24H()          bfin_read16(CAN0_AM24H)
-#define bfin_write_CAN0_AM24H(val)      bfin_write16(CAN0_AM24H, val)
-#define bfin_read_CAN0_AM25L()          bfin_read16(CAN0_AM25L)
-#define bfin_write_CAN0_AM25L(val)      bfin_write16(CAN0_AM25L, val)
-#define bfin_read_CAN0_AM25H()          bfin_read16(CAN0_AM25H)
-#define bfin_write_CAN0_AM25H(val)      bfin_write16(CAN0_AM25H, val)
-#define bfin_read_CAN0_AM26L()          bfin_read16(CAN0_AM26L)
-#define bfin_write_CAN0_AM26L(val)      bfin_write16(CAN0_AM26L, val)
-#define bfin_read_CAN0_AM26H()          bfin_read16(CAN0_AM26H)
-#define bfin_write_CAN0_AM26H(val)      bfin_write16(CAN0_AM26H, val)
-#define bfin_read_CAN0_AM27L()          bfin_read16(CAN0_AM27L)
-#define bfin_write_CAN0_AM27L(val)      bfin_write16(CAN0_AM27L, val)
-#define bfin_read_CAN0_AM27H()          bfin_read16(CAN0_AM27H)
-#define bfin_write_CAN0_AM27H(val)      bfin_write16(CAN0_AM27H, val)
-#define bfin_read_CAN0_AM28L()          bfin_read16(CAN0_AM28L)
-#define bfin_write_CAN0_AM28L(val)      bfin_write16(CAN0_AM28L, val)
-#define bfin_read_CAN0_AM28H()          bfin_read16(CAN0_AM28H)
-#define bfin_write_CAN0_AM28H(val)      bfin_write16(CAN0_AM28H, val)
-#define bfin_read_CAN0_AM29L()          bfin_read16(CAN0_AM29L)
-#define bfin_write_CAN0_AM29L(val)      bfin_write16(CAN0_AM29L, val)
-#define bfin_read_CAN0_AM29H()          bfin_read16(CAN0_AM29H)
-#define bfin_write_CAN0_AM29H(val)      bfin_write16(CAN0_AM29H, val)
-#define bfin_read_CAN0_AM30L()          bfin_read16(CAN0_AM30L)
-#define bfin_write_CAN0_AM30L(val)      bfin_write16(CAN0_AM30L, val)
-#define bfin_read_CAN0_AM30H()          bfin_read16(CAN0_AM30H)
-#define bfin_write_CAN0_AM30H(val)      bfin_write16(CAN0_AM30H, val)
-#define bfin_read_CAN0_AM31L()          bfin_read16(CAN0_AM31L)
-#define bfin_write_CAN0_AM31L(val)      bfin_write16(CAN0_AM31L, val)
-#define bfin_read_CAN0_AM31H()          bfin_read16(CAN0_AM31H)
-#define bfin_write_CAN0_AM31H(val)      bfin_write16(CAN0_AM31H, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB00_DATA0()             bfin_read16(CAN0_MB00_DATA0)
-#define bfin_write_CAN0_MB00_DATA0(val)         bfin_write16(CAN0_MB00_DATA0, val)
-#define bfin_read_CAN0_MB00_DATA1()             bfin_read16(CAN0_MB00_DATA1)
-#define bfin_write_CAN0_MB00_DATA1(val)         bfin_write16(CAN0_MB00_DATA1, val)
-#define bfin_read_CAN0_MB00_DATA2()             bfin_read16(CAN0_MB00_DATA2)
-#define bfin_write_CAN0_MB00_DATA2(val)         bfin_write16(CAN0_MB00_DATA2, val)
-#define bfin_read_CAN0_MB00_DATA3()             bfin_read16(CAN0_MB00_DATA3)
-#define bfin_write_CAN0_MB00_DATA3(val)         bfin_write16(CAN0_MB00_DATA3, val)
-#define bfin_read_CAN0_MB00_LENGTH()            bfin_read16(CAN0_MB00_LENGTH)
-#define bfin_write_CAN0_MB00_LENGTH(val)        bfin_write16(CAN0_MB00_LENGTH, val)
-#define bfin_read_CAN0_MB00_TIMESTAMP()         bfin_read16(CAN0_MB00_TIMESTAMP)
-#define bfin_write_CAN0_MB00_TIMESTAMP(val)     bfin_write16(CAN0_MB00_TIMESTAMP, val)
-#define bfin_read_CAN0_MB00_ID0()               bfin_read16(CAN0_MB00_ID0)
-#define bfin_write_CAN0_MB00_ID0(val)           bfin_write16(CAN0_MB00_ID0, val)
-#define bfin_read_CAN0_MB00_ID1()               bfin_read16(CAN0_MB00_ID1)
-#define bfin_write_CAN0_MB00_ID1(val)           bfin_write16(CAN0_MB00_ID1, val)
-#define bfin_read_CAN0_MB01_DATA0()             bfin_read16(CAN0_MB01_DATA0)
-#define bfin_write_CAN0_MB01_DATA0(val)         bfin_write16(CAN0_MB01_DATA0, val)
-#define bfin_read_CAN0_MB01_DATA1()             bfin_read16(CAN0_MB01_DATA1)
-#define bfin_write_CAN0_MB01_DATA1(val)         bfin_write16(CAN0_MB01_DATA1, val)
-#define bfin_read_CAN0_MB01_DATA2()             bfin_read16(CAN0_MB01_DATA2)
-#define bfin_write_CAN0_MB01_DATA2(val)         bfin_write16(CAN0_MB01_DATA2, val)
-#define bfin_read_CAN0_MB01_DATA3()             bfin_read16(CAN0_MB01_DATA3)
-#define bfin_write_CAN0_MB01_DATA3(val)         bfin_write16(CAN0_MB01_DATA3, val)
-#define bfin_read_CAN0_MB01_LENGTH()            bfin_read16(CAN0_MB01_LENGTH)
-#define bfin_write_CAN0_MB01_LENGTH(val)        bfin_write16(CAN0_MB01_LENGTH, val)
-#define bfin_read_CAN0_MB01_TIMESTAMP()         bfin_read16(CAN0_MB01_TIMESTAMP)
-#define bfin_write_CAN0_MB01_TIMESTAMP(val)     bfin_write16(CAN0_MB01_TIMESTAMP, val)
-#define bfin_read_CAN0_MB01_ID0()               bfin_read16(CAN0_MB01_ID0)
-#define bfin_write_CAN0_MB01_ID0(val)           bfin_write16(CAN0_MB01_ID0, val)
-#define bfin_read_CAN0_MB01_ID1()               bfin_read16(CAN0_MB01_ID1)
-#define bfin_write_CAN0_MB01_ID1(val)           bfin_write16(CAN0_MB01_ID1, val)
-#define bfin_read_CAN0_MB02_DATA0()             bfin_read16(CAN0_MB02_DATA0)
-#define bfin_write_CAN0_MB02_DATA0(val)         bfin_write16(CAN0_MB02_DATA0, val)
-#define bfin_read_CAN0_MB02_DATA1()             bfin_read16(CAN0_MB02_DATA1)
-#define bfin_write_CAN0_MB02_DATA1(val)         bfin_write16(CAN0_MB02_DATA1, val)
-#define bfin_read_CAN0_MB02_DATA2()             bfin_read16(CAN0_MB02_DATA2)
-#define bfin_write_CAN0_MB02_DATA2(val)         bfin_write16(CAN0_MB02_DATA2, val)
-#define bfin_read_CAN0_MB02_DATA3()             bfin_read16(CAN0_MB02_DATA3)
-#define bfin_write_CAN0_MB02_DATA3(val)         bfin_write16(CAN0_MB02_DATA3, val)
-#define bfin_read_CAN0_MB02_LENGTH()            bfin_read16(CAN0_MB02_LENGTH)
-#define bfin_write_CAN0_MB02_LENGTH(val)        bfin_write16(CAN0_MB02_LENGTH, val)
-#define bfin_read_CAN0_MB02_TIMESTAMP()         bfin_read16(CAN0_MB02_TIMESTAMP)
-#define bfin_write_CAN0_MB02_TIMESTAMP(val)     bfin_write16(CAN0_MB02_TIMESTAMP, val)
-#define bfin_read_CAN0_MB02_ID0()               bfin_read16(CAN0_MB02_ID0)
-#define bfin_write_CAN0_MB02_ID0(val)           bfin_write16(CAN0_MB02_ID0, val)
-#define bfin_read_CAN0_MB02_ID1()               bfin_read16(CAN0_MB02_ID1)
-#define bfin_write_CAN0_MB02_ID1(val)           bfin_write16(CAN0_MB02_ID1, val)
-#define bfin_read_CAN0_MB03_DATA0()             bfin_read16(CAN0_MB03_DATA0)
-#define bfin_write_CAN0_MB03_DATA0(val)         bfin_write16(CAN0_MB03_DATA0, val)
-#define bfin_read_CAN0_MB03_DATA1()             bfin_read16(CAN0_MB03_DATA1)
-#define bfin_write_CAN0_MB03_DATA1(val)         bfin_write16(CAN0_MB03_DATA1, val)
-#define bfin_read_CAN0_MB03_DATA2()             bfin_read16(CAN0_MB03_DATA2)
-#define bfin_write_CAN0_MB03_DATA2(val)         bfin_write16(CAN0_MB03_DATA2, val)
-#define bfin_read_CAN0_MB03_DATA3()             bfin_read16(CAN0_MB03_DATA3)
-#define bfin_write_CAN0_MB03_DATA3(val)         bfin_write16(CAN0_MB03_DATA3, val)
-#define bfin_read_CAN0_MB03_LENGTH()            bfin_read16(CAN0_MB03_LENGTH)
-#define bfin_write_CAN0_MB03_LENGTH(val)        bfin_write16(CAN0_MB03_LENGTH, val)
-#define bfin_read_CAN0_MB03_TIMESTAMP()         bfin_read16(CAN0_MB03_TIMESTAMP)
-#define bfin_write_CAN0_MB03_TIMESTAMP(val)     bfin_write16(CAN0_MB03_TIMESTAMP, val)
-#define bfin_read_CAN0_MB03_ID0()               bfin_read16(CAN0_MB03_ID0)
-#define bfin_write_CAN0_MB03_ID0(val)           bfin_write16(CAN0_MB03_ID0, val)
-#define bfin_read_CAN0_MB03_ID1()               bfin_read16(CAN0_MB03_ID1)
-#define bfin_write_CAN0_MB03_ID1(val)           bfin_write16(CAN0_MB03_ID1, val)
-#define bfin_read_CAN0_MB04_DATA0()             bfin_read16(CAN0_MB04_DATA0)
-#define bfin_write_CAN0_MB04_DATA0(val)         bfin_write16(CAN0_MB04_DATA0, val)
-#define bfin_read_CAN0_MB04_DATA1()             bfin_read16(CAN0_MB04_DATA1)
-#define bfin_write_CAN0_MB04_DATA1(val)         bfin_write16(CAN0_MB04_DATA1, val)
-#define bfin_read_CAN0_MB04_DATA2()             bfin_read16(CAN0_MB04_DATA2)
-#define bfin_write_CAN0_MB04_DATA2(val)         bfin_write16(CAN0_MB04_DATA2, val)
-#define bfin_read_CAN0_MB04_DATA3()             bfin_read16(CAN0_MB04_DATA3)
-#define bfin_write_CAN0_MB04_DATA3(val)         bfin_write16(CAN0_MB04_DATA3, val)
-#define bfin_read_CAN0_MB04_LENGTH()            bfin_read16(CAN0_MB04_LENGTH)
-#define bfin_write_CAN0_MB04_LENGTH(val)        bfin_write16(CAN0_MB04_LENGTH, val)
-#define bfin_read_CAN0_MB04_TIMESTAMP()         bfin_read16(CAN0_MB04_TIMESTAMP)
-#define bfin_write_CAN0_MB04_TIMESTAMP(val)     bfin_write16(CAN0_MB04_TIMESTAMP, val)
-#define bfin_read_CAN0_MB04_ID0()               bfin_read16(CAN0_MB04_ID0)
-#define bfin_write_CAN0_MB04_ID0(val)           bfin_write16(CAN0_MB04_ID0, val)
-#define bfin_read_CAN0_MB04_ID1()               bfin_read16(CAN0_MB04_ID1)
-#define bfin_write_CAN0_MB04_ID1(val)           bfin_write16(CAN0_MB04_ID1, val)
-#define bfin_read_CAN0_MB05_DATA0()             bfin_read16(CAN0_MB05_DATA0)
-#define bfin_write_CAN0_MB05_DATA0(val)         bfin_write16(CAN0_MB05_DATA0, val)
-#define bfin_read_CAN0_MB05_DATA1()             bfin_read16(CAN0_MB05_DATA1)
-#define bfin_write_CAN0_MB05_DATA1(val)         bfin_write16(CAN0_MB05_DATA1, val)
-#define bfin_read_CAN0_MB05_DATA2()             bfin_read16(CAN0_MB05_DATA2)
-#define bfin_write_CAN0_MB05_DATA2(val)         bfin_write16(CAN0_MB05_DATA2, val)
-#define bfin_read_CAN0_MB05_DATA3()             bfin_read16(CAN0_MB05_DATA3)
-#define bfin_write_CAN0_MB05_DATA3(val)         bfin_write16(CAN0_MB05_DATA3, val)
-#define bfin_read_CAN0_MB05_LENGTH()            bfin_read16(CAN0_MB05_LENGTH)
-#define bfin_write_CAN0_MB05_LENGTH(val)        bfin_write16(CAN0_MB05_LENGTH, val)
-#define bfin_read_CAN0_MB05_TIMESTAMP()         bfin_read16(CAN0_MB05_TIMESTAMP)
-#define bfin_write_CAN0_MB05_TIMESTAMP(val)     bfin_write16(CAN0_MB05_TIMESTAMP, val)
-#define bfin_read_CAN0_MB05_ID0()               bfin_read16(CAN0_MB05_ID0)
-#define bfin_write_CAN0_MB05_ID0(val)           bfin_write16(CAN0_MB05_ID0, val)
-#define bfin_read_CAN0_MB05_ID1()               bfin_read16(CAN0_MB05_ID1)
-#define bfin_write_CAN0_MB05_ID1(val)           bfin_write16(CAN0_MB05_ID1, val)
-#define bfin_read_CAN0_MB06_DATA0()             bfin_read16(CAN0_MB06_DATA0)
-#define bfin_write_CAN0_MB06_DATA0(val)         bfin_write16(CAN0_MB06_DATA0, val)
-#define bfin_read_CAN0_MB06_DATA1()             bfin_read16(CAN0_MB06_DATA1)
-#define bfin_write_CAN0_MB06_DATA1(val)         bfin_write16(CAN0_MB06_DATA1, val)
-#define bfin_read_CAN0_MB06_DATA2()             bfin_read16(CAN0_MB06_DATA2)
-#define bfin_write_CAN0_MB06_DATA2(val)         bfin_write16(CAN0_MB06_DATA2, val)
-#define bfin_read_CAN0_MB06_DATA3()             bfin_read16(CAN0_MB06_DATA3)
-#define bfin_write_CAN0_MB06_DATA3(val)         bfin_write16(CAN0_MB06_DATA3, val)
-#define bfin_read_CAN0_MB06_LENGTH()            bfin_read16(CAN0_MB06_LENGTH)
-#define bfin_write_CAN0_MB06_LENGTH(val)        bfin_write16(CAN0_MB06_LENGTH, val)
-#define bfin_read_CAN0_MB06_TIMESTAMP()         bfin_read16(CAN0_MB06_TIMESTAMP)
-#define bfin_write_CAN0_MB06_TIMESTAMP(val)     bfin_write16(CAN0_MB06_TIMESTAMP, val)
-#define bfin_read_CAN0_MB06_ID0()               bfin_read16(CAN0_MB06_ID0)
-#define bfin_write_CAN0_MB06_ID0(val)           bfin_write16(CAN0_MB06_ID0, val)
-#define bfin_read_CAN0_MB06_ID1()               bfin_read16(CAN0_MB06_ID1)
-#define bfin_write_CAN0_MB06_ID1(val)           bfin_write16(CAN0_MB06_ID1, val)
-#define bfin_read_CAN0_MB07_DATA0()             bfin_read16(CAN0_MB07_DATA0)
-#define bfin_write_CAN0_MB07_DATA0(val)         bfin_write16(CAN0_MB07_DATA0, val)
-#define bfin_read_CAN0_MB07_DATA1()             bfin_read16(CAN0_MB07_DATA1)
-#define bfin_write_CAN0_MB07_DATA1(val)         bfin_write16(CAN0_MB07_DATA1, val)
-#define bfin_read_CAN0_MB07_DATA2()             bfin_read16(CAN0_MB07_DATA2)
-#define bfin_write_CAN0_MB07_DATA2(val)         bfin_write16(CAN0_MB07_DATA2, val)
-#define bfin_read_CAN0_MB07_DATA3()             bfin_read16(CAN0_MB07_DATA3)
-#define bfin_write_CAN0_MB07_DATA3(val)         bfin_write16(CAN0_MB07_DATA3, val)
-#define bfin_read_CAN0_MB07_LENGTH()            bfin_read16(CAN0_MB07_LENGTH)
-#define bfin_write_CAN0_MB07_LENGTH(val)        bfin_write16(CAN0_MB07_LENGTH, val)
-#define bfin_read_CAN0_MB07_TIMESTAMP()         bfin_read16(CAN0_MB07_TIMESTAMP)
-#define bfin_write_CAN0_MB07_TIMESTAMP(val)     bfin_write16(CAN0_MB07_TIMESTAMP, val)
-#define bfin_read_CAN0_MB07_ID0()               bfin_read16(CAN0_MB07_ID0)
-#define bfin_write_CAN0_MB07_ID0(val)           bfin_write16(CAN0_MB07_ID0, val)
-#define bfin_read_CAN0_MB07_ID1()               bfin_read16(CAN0_MB07_ID1)
-#define bfin_write_CAN0_MB07_ID1(val)           bfin_write16(CAN0_MB07_ID1, val)
-#define bfin_read_CAN0_MB08_DATA0()             bfin_read16(CAN0_MB08_DATA0)
-#define bfin_write_CAN0_MB08_DATA0(val)         bfin_write16(CAN0_MB08_DATA0, val)
-#define bfin_read_CAN0_MB08_DATA1()             bfin_read16(CAN0_MB08_DATA1)
-#define bfin_write_CAN0_MB08_DATA1(val)         bfin_write16(CAN0_MB08_DATA1, val)
-#define bfin_read_CAN0_MB08_DATA2()             bfin_read16(CAN0_MB08_DATA2)
-#define bfin_write_CAN0_MB08_DATA2(val)         bfin_write16(CAN0_MB08_DATA2, val)
-#define bfin_read_CAN0_MB08_DATA3()             bfin_read16(CAN0_MB08_DATA3)
-#define bfin_write_CAN0_MB08_DATA3(val)         bfin_write16(CAN0_MB08_DATA3, val)
-#define bfin_read_CAN0_MB08_LENGTH()            bfin_read16(CAN0_MB08_LENGTH)
-#define bfin_write_CAN0_MB08_LENGTH(val)        bfin_write16(CAN0_MB08_LENGTH, val)
-#define bfin_read_CAN0_MB08_TIMESTAMP()         bfin_read16(CAN0_MB08_TIMESTAMP)
-#define bfin_write_CAN0_MB08_TIMESTAMP(val)     bfin_write16(CAN0_MB08_TIMESTAMP, val)
-#define bfin_read_CAN0_MB08_ID0()               bfin_read16(CAN0_MB08_ID0)
-#define bfin_write_CAN0_MB08_ID0(val)           bfin_write16(CAN0_MB08_ID0, val)
-#define bfin_read_CAN0_MB08_ID1()               bfin_read16(CAN0_MB08_ID1)
-#define bfin_write_CAN0_MB08_ID1(val)           bfin_write16(CAN0_MB08_ID1, val)
-#define bfin_read_CAN0_MB09_DATA0()             bfin_read16(CAN0_MB09_DATA0)
-#define bfin_write_CAN0_MB09_DATA0(val)         bfin_write16(CAN0_MB09_DATA0, val)
-#define bfin_read_CAN0_MB09_DATA1()             bfin_read16(CAN0_MB09_DATA1)
-#define bfin_write_CAN0_MB09_DATA1(val)         bfin_write16(CAN0_MB09_DATA1, val)
-#define bfin_read_CAN0_MB09_DATA2()             bfin_read16(CAN0_MB09_DATA2)
-#define bfin_write_CAN0_MB09_DATA2(val)         bfin_write16(CAN0_MB09_DATA2, val)
-#define bfin_read_CAN0_MB09_DATA3()             bfin_read16(CAN0_MB09_DATA3)
-#define bfin_write_CAN0_MB09_DATA3(val)         bfin_write16(CAN0_MB09_DATA3, val)
-#define bfin_read_CAN0_MB09_LENGTH()            bfin_read16(CAN0_MB09_LENGTH)
-#define bfin_write_CAN0_MB09_LENGTH(val)        bfin_write16(CAN0_MB09_LENGTH, val)
-#define bfin_read_CAN0_MB09_TIMESTAMP()         bfin_read16(CAN0_MB09_TIMESTAMP)
-#define bfin_write_CAN0_MB09_TIMESTAMP(val)     bfin_write16(CAN0_MB09_TIMESTAMP, val)
-#define bfin_read_CAN0_MB09_ID0()               bfin_read16(CAN0_MB09_ID0)
-#define bfin_write_CAN0_MB09_ID0(val)           bfin_write16(CAN0_MB09_ID0, val)
-#define bfin_read_CAN0_MB09_ID1()               bfin_read16(CAN0_MB09_ID1)
-#define bfin_write_CAN0_MB09_ID1(val)           bfin_write16(CAN0_MB09_ID1, val)
-#define bfin_read_CAN0_MB10_DATA0()             bfin_read16(CAN0_MB10_DATA0)
-#define bfin_write_CAN0_MB10_DATA0(val)         bfin_write16(CAN0_MB10_DATA0, val)
-#define bfin_read_CAN0_MB10_DATA1()             bfin_read16(CAN0_MB10_DATA1)
-#define bfin_write_CAN0_MB10_DATA1(val)         bfin_write16(CAN0_MB10_DATA1, val)
-#define bfin_read_CAN0_MB10_DATA2()             bfin_read16(CAN0_MB10_DATA2)
-#define bfin_write_CAN0_MB10_DATA2(val)         bfin_write16(CAN0_MB10_DATA2, val)
-#define bfin_read_CAN0_MB10_DATA3()             bfin_read16(CAN0_MB10_DATA3)
-#define bfin_write_CAN0_MB10_DATA3(val)         bfin_write16(CAN0_MB10_DATA3, val)
-#define bfin_read_CAN0_MB10_LENGTH()            bfin_read16(CAN0_MB10_LENGTH)
-#define bfin_write_CAN0_MB10_LENGTH(val)        bfin_write16(CAN0_MB10_LENGTH, val)
-#define bfin_read_CAN0_MB10_TIMESTAMP()         bfin_read16(CAN0_MB10_TIMESTAMP)
-#define bfin_write_CAN0_MB10_TIMESTAMP(val)     bfin_write16(CAN0_MB10_TIMESTAMP, val)
-#define bfin_read_CAN0_MB10_ID0()               bfin_read16(CAN0_MB10_ID0)
-#define bfin_write_CAN0_MB10_ID0(val)           bfin_write16(CAN0_MB10_ID0, val)
-#define bfin_read_CAN0_MB10_ID1()               bfin_read16(CAN0_MB10_ID1)
-#define bfin_write_CAN0_MB10_ID1(val)           bfin_write16(CAN0_MB10_ID1, val)
-#define bfin_read_CAN0_MB11_DATA0()             bfin_read16(CAN0_MB11_DATA0)
-#define bfin_write_CAN0_MB11_DATA0(val)         bfin_write16(CAN0_MB11_DATA0, val)
-#define bfin_read_CAN0_MB11_DATA1()             bfin_read16(CAN0_MB11_DATA1)
-#define bfin_write_CAN0_MB11_DATA1(val)         bfin_write16(CAN0_MB11_DATA1, val)
-#define bfin_read_CAN0_MB11_DATA2()             bfin_read16(CAN0_MB11_DATA2)
-#define bfin_write_CAN0_MB11_DATA2(val)         bfin_write16(CAN0_MB11_DATA2, val)
-#define bfin_read_CAN0_MB11_DATA3()             bfin_read16(CAN0_MB11_DATA3)
-#define bfin_write_CAN0_MB11_DATA3(val)         bfin_write16(CAN0_MB11_DATA3, val)
-#define bfin_read_CAN0_MB11_LENGTH()            bfin_read16(CAN0_MB11_LENGTH)
-#define bfin_write_CAN0_MB11_LENGTH(val)        bfin_write16(CAN0_MB11_LENGTH, val)
-#define bfin_read_CAN0_MB11_TIMESTAMP()         bfin_read16(CAN0_MB11_TIMESTAMP)
-#define bfin_write_CAN0_MB11_TIMESTAMP(val)     bfin_write16(CAN0_MB11_TIMESTAMP, val)
-#define bfin_read_CAN0_MB11_ID0()               bfin_read16(CAN0_MB11_ID0)
-#define bfin_write_CAN0_MB11_ID0(val)           bfin_write16(CAN0_MB11_ID0, val)
-#define bfin_read_CAN0_MB11_ID1()               bfin_read16(CAN0_MB11_ID1)
-#define bfin_write_CAN0_MB11_ID1(val)           bfin_write16(CAN0_MB11_ID1, val)
-#define bfin_read_CAN0_MB12_DATA0()             bfin_read16(CAN0_MB12_DATA0)
-#define bfin_write_CAN0_MB12_DATA0(val)         bfin_write16(CAN0_MB12_DATA0, val)
-#define bfin_read_CAN0_MB12_DATA1()             bfin_read16(CAN0_MB12_DATA1)
-#define bfin_write_CAN0_MB12_DATA1(val)         bfin_write16(CAN0_MB12_DATA1, val)
-#define bfin_read_CAN0_MB12_DATA2()             bfin_read16(CAN0_MB12_DATA2)
-#define bfin_write_CAN0_MB12_DATA2(val)         bfin_write16(CAN0_MB12_DATA2, val)
-#define bfin_read_CAN0_MB12_DATA3()             bfin_read16(CAN0_MB12_DATA3)
-#define bfin_write_CAN0_MB12_DATA3(val)         bfin_write16(CAN0_MB12_DATA3, val)
-#define bfin_read_CAN0_MB12_LENGTH()            bfin_read16(CAN0_MB12_LENGTH)
-#define bfin_write_CAN0_MB12_LENGTH(val)        bfin_write16(CAN0_MB12_LENGTH, val)
-#define bfin_read_CAN0_MB12_TIMESTAMP()         bfin_read16(CAN0_MB12_TIMESTAMP)
-#define bfin_write_CAN0_MB12_TIMESTAMP(val)     bfin_write16(CAN0_MB12_TIMESTAMP, val)
-#define bfin_read_CAN0_MB12_ID0()               bfin_read16(CAN0_MB12_ID0)
-#define bfin_write_CAN0_MB12_ID0(val)           bfin_write16(CAN0_MB12_ID0, val)
-#define bfin_read_CAN0_MB12_ID1()               bfin_read16(CAN0_MB12_ID1)
-#define bfin_write_CAN0_MB12_ID1(val)           bfin_write16(CAN0_MB12_ID1, val)
-#define bfin_read_CAN0_MB13_DATA0()             bfin_read16(CAN0_MB13_DATA0)
-#define bfin_write_CAN0_MB13_DATA0(val)         bfin_write16(CAN0_MB13_DATA0, val)
-#define bfin_read_CAN0_MB13_DATA1()             bfin_read16(CAN0_MB13_DATA1)
-#define bfin_write_CAN0_MB13_DATA1(val)         bfin_write16(CAN0_MB13_DATA1, val)
-#define bfin_read_CAN0_MB13_DATA2()             bfin_read16(CAN0_MB13_DATA2)
-#define bfin_write_CAN0_MB13_DATA2(val)         bfin_write16(CAN0_MB13_DATA2, val)
-#define bfin_read_CAN0_MB13_DATA3()             bfin_read16(CAN0_MB13_DATA3)
-#define bfin_write_CAN0_MB13_DATA3(val)         bfin_write16(CAN0_MB13_DATA3, val)
-#define bfin_read_CAN0_MB13_LENGTH()            bfin_read16(CAN0_MB13_LENGTH)
-#define bfin_write_CAN0_MB13_LENGTH(val)        bfin_write16(CAN0_MB13_LENGTH, val)
-#define bfin_read_CAN0_MB13_TIMESTAMP()         bfin_read16(CAN0_MB13_TIMESTAMP)
-#define bfin_write_CAN0_MB13_TIMESTAMP(val)     bfin_write16(CAN0_MB13_TIMESTAMP, val)
-#define bfin_read_CAN0_MB13_ID0()               bfin_read16(CAN0_MB13_ID0)
-#define bfin_write_CAN0_MB13_ID0(val)           bfin_write16(CAN0_MB13_ID0, val)
-#define bfin_read_CAN0_MB13_ID1()               bfin_read16(CAN0_MB13_ID1)
-#define bfin_write_CAN0_MB13_ID1(val)           bfin_write16(CAN0_MB13_ID1, val)
-#define bfin_read_CAN0_MB14_DATA0()             bfin_read16(CAN0_MB14_DATA0)
-#define bfin_write_CAN0_MB14_DATA0(val)         bfin_write16(CAN0_MB14_DATA0, val)
-#define bfin_read_CAN0_MB14_DATA1()             bfin_read16(CAN0_MB14_DATA1)
-#define bfin_write_CAN0_MB14_DATA1(val)         bfin_write16(CAN0_MB14_DATA1, val)
-#define bfin_read_CAN0_MB14_DATA2()             bfin_read16(CAN0_MB14_DATA2)
-#define bfin_write_CAN0_MB14_DATA2(val)         bfin_write16(CAN0_MB14_DATA2, val)
-#define bfin_read_CAN0_MB14_DATA3()             bfin_read16(CAN0_MB14_DATA3)
-#define bfin_write_CAN0_MB14_DATA3(val)         bfin_write16(CAN0_MB14_DATA3, val)
-#define bfin_read_CAN0_MB14_LENGTH()            bfin_read16(CAN0_MB14_LENGTH)
-#define bfin_write_CAN0_MB14_LENGTH(val)        bfin_write16(CAN0_MB14_LENGTH, val)
-#define bfin_read_CAN0_MB14_TIMESTAMP()         bfin_read16(CAN0_MB14_TIMESTAMP)
-#define bfin_write_CAN0_MB14_TIMESTAMP(val)     bfin_write16(CAN0_MB14_TIMESTAMP, val)
-#define bfin_read_CAN0_MB14_ID0()               bfin_read16(CAN0_MB14_ID0)
-#define bfin_write_CAN0_MB14_ID0(val)           bfin_write16(CAN0_MB14_ID0, val)
-#define bfin_read_CAN0_MB14_ID1()               bfin_read16(CAN0_MB14_ID1)
-#define bfin_write_CAN0_MB14_ID1(val)           bfin_write16(CAN0_MB14_ID1, val)
-#define bfin_read_CAN0_MB15_DATA0()             bfin_read16(CAN0_MB15_DATA0)
-#define bfin_write_CAN0_MB15_DATA0(val)         bfin_write16(CAN0_MB15_DATA0, val)
-#define bfin_read_CAN0_MB15_DATA1()             bfin_read16(CAN0_MB15_DATA1)
-#define bfin_write_CAN0_MB15_DATA1(val)         bfin_write16(CAN0_MB15_DATA1, val)
-#define bfin_read_CAN0_MB15_DATA2()             bfin_read16(CAN0_MB15_DATA2)
-#define bfin_write_CAN0_MB15_DATA2(val)         bfin_write16(CAN0_MB15_DATA2, val)
-#define bfin_read_CAN0_MB15_DATA3()             bfin_read16(CAN0_MB15_DATA3)
-#define bfin_write_CAN0_MB15_DATA3(val)         bfin_write16(CAN0_MB15_DATA3, val)
-#define bfin_read_CAN0_MB15_LENGTH()            bfin_read16(CAN0_MB15_LENGTH)
-#define bfin_write_CAN0_MB15_LENGTH(val)        bfin_write16(CAN0_MB15_LENGTH, val)
-#define bfin_read_CAN0_MB15_TIMESTAMP()         bfin_read16(CAN0_MB15_TIMESTAMP)
-#define bfin_write_CAN0_MB15_TIMESTAMP(val)     bfin_write16(CAN0_MB15_TIMESTAMP, val)
-#define bfin_read_CAN0_MB15_ID0()               bfin_read16(CAN0_MB15_ID0)
-#define bfin_write_CAN0_MB15_ID0(val)           bfin_write16(CAN0_MB15_ID0, val)
-#define bfin_read_CAN0_MB15_ID1()               bfin_read16(CAN0_MB15_ID1)
-#define bfin_write_CAN0_MB15_ID1(val)           bfin_write16(CAN0_MB15_ID1, val)
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define bfin_read_CAN0_MB16_DATA0()             bfin_read16(CAN0_MB16_DATA0)
-#define bfin_write_CAN0_MB16_DATA0(val)         bfin_write16(CAN0_MB16_DATA0, val)
-#define bfin_read_CAN0_MB16_DATA1()             bfin_read16(CAN0_MB16_DATA1)
-#define bfin_write_CAN0_MB16_DATA1(val)         bfin_write16(CAN0_MB16_DATA1, val)
-#define bfin_read_CAN0_MB16_DATA2()             bfin_read16(CAN0_MB16_DATA2)
-#define bfin_write_CAN0_MB16_DATA2(val)         bfin_write16(CAN0_MB16_DATA2, val)
-#define bfin_read_CAN0_MB16_DATA3()             bfin_read16(CAN0_MB16_DATA3)
-#define bfin_write_CAN0_MB16_DATA3(val)         bfin_write16(CAN0_MB16_DATA3, val)
-#define bfin_read_CAN0_MB16_LENGTH()            bfin_read16(CAN0_MB16_LENGTH)
-#define bfin_write_CAN0_MB16_LENGTH(val)        bfin_write16(CAN0_MB16_LENGTH, val)
-#define bfin_read_CAN0_MB16_TIMESTAMP()         bfin_read16(CAN0_MB16_TIMESTAMP)
-#define bfin_write_CAN0_MB16_TIMESTAMP(val)     bfin_write16(CAN0_MB16_TIMESTAMP, val)
-#define bfin_read_CAN0_MB16_ID0()               bfin_read16(CAN0_MB16_ID0)
-#define bfin_write_CAN0_MB16_ID0(val)           bfin_write16(CAN0_MB16_ID0, val)
-#define bfin_read_CAN0_MB16_ID1()               bfin_read16(CAN0_MB16_ID1)
-#define bfin_write_CAN0_MB16_ID1(val)           bfin_write16(CAN0_MB16_ID1, val)
-#define bfin_read_CAN0_MB17_DATA0()             bfin_read16(CAN0_MB17_DATA0)
-#define bfin_write_CAN0_MB17_DATA0(val)         bfin_write16(CAN0_MB17_DATA0, val)
-#define bfin_read_CAN0_MB17_DATA1()             bfin_read16(CAN0_MB17_DATA1)
-#define bfin_write_CAN0_MB17_DATA1(val)         bfin_write16(CAN0_MB17_DATA1, val)
-#define bfin_read_CAN0_MB17_DATA2()             bfin_read16(CAN0_MB17_DATA2)
-#define bfin_write_CAN0_MB17_DATA2(val)         bfin_write16(CAN0_MB17_DATA2, val)
-#define bfin_read_CAN0_MB17_DATA3()             bfin_read16(CAN0_MB17_DATA3)
-#define bfin_write_CAN0_MB17_DATA3(val)         bfin_write16(CAN0_MB17_DATA3, val)
-#define bfin_read_CAN0_MB17_LENGTH()            bfin_read16(CAN0_MB17_LENGTH)
-#define bfin_write_CAN0_MB17_LENGTH(val)        bfin_write16(CAN0_MB17_LENGTH, val)
-#define bfin_read_CAN0_MB17_TIMESTAMP()         bfin_read16(CAN0_MB17_TIMESTAMP)
-#define bfin_write_CAN0_MB17_TIMESTAMP(val)     bfin_write16(CAN0_MB17_TIMESTAMP, val)
-#define bfin_read_CAN0_MB17_ID0()               bfin_read16(CAN0_MB17_ID0)
-#define bfin_write_CAN0_MB17_ID0(val)           bfin_write16(CAN0_MB17_ID0, val)
-#define bfin_read_CAN0_MB17_ID1()               bfin_read16(CAN0_MB17_ID1)
-#define bfin_write_CAN0_MB17_ID1(val)           bfin_write16(CAN0_MB17_ID1, val)
-#define bfin_read_CAN0_MB18_DATA0()             bfin_read16(CAN0_MB18_DATA0)
-#define bfin_write_CAN0_MB18_DATA0(val)         bfin_write16(CAN0_MB18_DATA0, val)
-#define bfin_read_CAN0_MB18_DATA1()             bfin_read16(CAN0_MB18_DATA1)
-#define bfin_write_CAN0_MB18_DATA1(val)         bfin_write16(CAN0_MB18_DATA1, val)
-#define bfin_read_CAN0_MB18_DATA2()             bfin_read16(CAN0_MB18_DATA2)
-#define bfin_write_CAN0_MB18_DATA2(val)         bfin_write16(CAN0_MB18_DATA2, val)
-#define bfin_read_CAN0_MB18_DATA3()             bfin_read16(CAN0_MB18_DATA3)
-#define bfin_write_CAN0_MB18_DATA3(val)         bfin_write16(CAN0_MB18_DATA3, val)
-#define bfin_read_CAN0_MB18_LENGTH()            bfin_read16(CAN0_MB18_LENGTH)
-#define bfin_write_CAN0_MB18_LENGTH(val)        bfin_write16(CAN0_MB18_LENGTH, val)
-#define bfin_read_CAN0_MB18_TIMESTAMP()         bfin_read16(CAN0_MB18_TIMESTAMP)
-#define bfin_write_CAN0_MB18_TIMESTAMP(val)     bfin_write16(CAN0_MB18_TIMESTAMP, val)
-#define bfin_read_CAN0_MB18_ID0()               bfin_read16(CAN0_MB18_ID0)
-#define bfin_write_CAN0_MB18_ID0(val)           bfin_write16(CAN0_MB18_ID0, val)
-#define bfin_read_CAN0_MB18_ID1()               bfin_read16(CAN0_MB18_ID1)
-#define bfin_write_CAN0_MB18_ID1(val)           bfin_write16(CAN0_MB18_ID1, val)
-#define bfin_read_CAN0_MB19_DATA0()             bfin_read16(CAN0_MB19_DATA0)
-#define bfin_write_CAN0_MB19_DATA0(val)         bfin_write16(CAN0_MB19_DATA0, val)
-#define bfin_read_CAN0_MB19_DATA1()             bfin_read16(CAN0_MB19_DATA1)
-#define bfin_write_CAN0_MB19_DATA1(val)         bfin_write16(CAN0_MB19_DATA1, val)
-#define bfin_read_CAN0_MB19_DATA2()             bfin_read16(CAN0_MB19_DATA2)
-#define bfin_write_CAN0_MB19_DATA2(val)         bfin_write16(CAN0_MB19_DATA2, val)
-#define bfin_read_CAN0_MB19_DATA3()             bfin_read16(CAN0_MB19_DATA3)
-#define bfin_write_CAN0_MB19_DATA3(val)         bfin_write16(CAN0_MB19_DATA3, val)
-#define bfin_read_CAN0_MB19_LENGTH()            bfin_read16(CAN0_MB19_LENGTH)
-#define bfin_write_CAN0_MB19_LENGTH(val)        bfin_write16(CAN0_MB19_LENGTH, val)
-#define bfin_read_CAN0_MB19_TIMESTAMP()         bfin_read16(CAN0_MB19_TIMESTAMP)
-#define bfin_write_CAN0_MB19_TIMESTAMP(val)     bfin_write16(CAN0_MB19_TIMESTAMP, val)
-#define bfin_read_CAN0_MB19_ID0()               bfin_read16(CAN0_MB19_ID0)
-#define bfin_write_CAN0_MB19_ID0(val)           bfin_write16(CAN0_MB19_ID0, val)
-#define bfin_read_CAN0_MB19_ID1()               bfin_read16(CAN0_MB19_ID1)
-#define bfin_write_CAN0_MB19_ID1(val)           bfin_write16(CAN0_MB19_ID1, val)
-#define bfin_read_CAN0_MB20_DATA0()             bfin_read16(CAN0_MB20_DATA0)
-#define bfin_write_CAN0_MB20_DATA0(val)         bfin_write16(CAN0_MB20_DATA0, val)
-#define bfin_read_CAN0_MB20_DATA1()             bfin_read16(CAN0_MB20_DATA1)
-#define bfin_write_CAN0_MB20_DATA1(val)         bfin_write16(CAN0_MB20_DATA1, val)
-#define bfin_read_CAN0_MB20_DATA2()             bfin_read16(CAN0_MB20_DATA2)
-#define bfin_write_CAN0_MB20_DATA2(val)         bfin_write16(CAN0_MB20_DATA2, val)
-#define bfin_read_CAN0_MB20_DATA3()             bfin_read16(CAN0_MB20_DATA3)
-#define bfin_write_CAN0_MB20_DATA3(val)         bfin_write16(CAN0_MB20_DATA3, val)
-#define bfin_read_CAN0_MB20_LENGTH()            bfin_read16(CAN0_MB20_LENGTH)
-#define bfin_write_CAN0_MB20_LENGTH(val)        bfin_write16(CAN0_MB20_LENGTH, val)
-#define bfin_read_CAN0_MB20_TIMESTAMP()         bfin_read16(CAN0_MB20_TIMESTAMP)
-#define bfin_write_CAN0_MB20_TIMESTAMP(val)     bfin_write16(CAN0_MB20_TIMESTAMP, val)
-#define bfin_read_CAN0_MB20_ID0()               bfin_read16(CAN0_MB20_ID0)
-#define bfin_write_CAN0_MB20_ID0(val)           bfin_write16(CAN0_MB20_ID0, val)
-#define bfin_read_CAN0_MB20_ID1()               bfin_read16(CAN0_MB20_ID1)
-#define bfin_write_CAN0_MB20_ID1(val)           bfin_write16(CAN0_MB20_ID1, val)
-#define bfin_read_CAN0_MB21_DATA0()             bfin_read16(CAN0_MB21_DATA0)
-#define bfin_write_CAN0_MB21_DATA0(val)         bfin_write16(CAN0_MB21_DATA0, val)
-#define bfin_read_CAN0_MB21_DATA1()             bfin_read16(CAN0_MB21_DATA1)
-#define bfin_write_CAN0_MB21_DATA1(val)         bfin_write16(CAN0_MB21_DATA1, val)
-#define bfin_read_CAN0_MB21_DATA2()             bfin_read16(CAN0_MB21_DATA2)
-#define bfin_write_CAN0_MB21_DATA2(val)         bfin_write16(CAN0_MB21_DATA2, val)
-#define bfin_read_CAN0_MB21_DATA3()             bfin_read16(CAN0_MB21_DATA3)
-#define bfin_write_CAN0_MB21_DATA3(val)         bfin_write16(CAN0_MB21_DATA3, val)
-#define bfin_read_CAN0_MB21_LENGTH()            bfin_read16(CAN0_MB21_LENGTH)
-#define bfin_write_CAN0_MB21_LENGTH(val)        bfin_write16(CAN0_MB21_LENGTH, val)
-#define bfin_read_CAN0_MB21_TIMESTAMP()         bfin_read16(CAN0_MB21_TIMESTAMP)
-#define bfin_write_CAN0_MB21_TIMESTAMP(val)     bfin_write16(CAN0_MB21_TIMESTAMP, val)
-#define bfin_read_CAN0_MB21_ID0()               bfin_read16(CAN0_MB21_ID0)
-#define bfin_write_CAN0_MB21_ID0(val)           bfin_write16(CAN0_MB21_ID0, val)
-#define bfin_read_CAN0_MB21_ID1()               bfin_read16(CAN0_MB21_ID1)
-#define bfin_write_CAN0_MB21_ID1(val)           bfin_write16(CAN0_MB21_ID1, val)
-#define bfin_read_CAN0_MB22_DATA0()             bfin_read16(CAN0_MB22_DATA0)
-#define bfin_write_CAN0_MB22_DATA0(val)         bfin_write16(CAN0_MB22_DATA0, val)
-#define bfin_read_CAN0_MB22_DATA1()             bfin_read16(CAN0_MB22_DATA1)
-#define bfin_write_CAN0_MB22_DATA1(val)         bfin_write16(CAN0_MB22_DATA1, val)
-#define bfin_read_CAN0_MB22_DATA2()             bfin_read16(CAN0_MB22_DATA2)
-#define bfin_write_CAN0_MB22_DATA2(val)         bfin_write16(CAN0_MB22_DATA2, val)
-#define bfin_read_CAN0_MB22_DATA3()             bfin_read16(CAN0_MB22_DATA3)
-#define bfin_write_CAN0_MB22_DATA3(val)         bfin_write16(CAN0_MB22_DATA3, val)
-#define bfin_read_CAN0_MB22_LENGTH()            bfin_read16(CAN0_MB22_LENGTH)
-#define bfin_write_CAN0_MB22_LENGTH(val)        bfin_write16(CAN0_MB22_LENGTH, val)
-#define bfin_read_CAN0_MB22_TIMESTAMP()         bfin_read16(CAN0_MB22_TIMESTAMP)
-#define bfin_write_CAN0_MB22_TIMESTAMP(val)     bfin_write16(CAN0_MB22_TIMESTAMP, val)
-#define bfin_read_CAN0_MB22_ID0()               bfin_read16(CAN0_MB22_ID0)
-#define bfin_write_CAN0_MB22_ID0(val)           bfin_write16(CAN0_MB22_ID0, val)
-#define bfin_read_CAN0_MB22_ID1()               bfin_read16(CAN0_MB22_ID1)
-#define bfin_write_CAN0_MB22_ID1(val)           bfin_write16(CAN0_MB22_ID1, val)
-#define bfin_read_CAN0_MB23_DATA0()             bfin_read16(CAN0_MB23_DATA0)
-#define bfin_write_CAN0_MB23_DATA0(val)         bfin_write16(CAN0_MB23_DATA0, val)
-#define bfin_read_CAN0_MB23_DATA1()             bfin_read16(CAN0_MB23_DATA1)
-#define bfin_write_CAN0_MB23_DATA1(val)         bfin_write16(CAN0_MB23_DATA1, val)
-#define bfin_read_CAN0_MB23_DATA2()             bfin_read16(CAN0_MB23_DATA2)
-#define bfin_write_CAN0_MB23_DATA2(val)         bfin_write16(CAN0_MB23_DATA2, val)
-#define bfin_read_CAN0_MB23_DATA3()             bfin_read16(CAN0_MB23_DATA3)
-#define bfin_write_CAN0_MB23_DATA3(val)         bfin_write16(CAN0_MB23_DATA3, val)
-#define bfin_read_CAN0_MB23_LENGTH()            bfin_read16(CAN0_MB23_LENGTH)
-#define bfin_write_CAN0_MB23_LENGTH(val)        bfin_write16(CAN0_MB23_LENGTH, val)
-#define bfin_read_CAN0_MB23_TIMESTAMP()         bfin_read16(CAN0_MB23_TIMESTAMP)
-#define bfin_write_CAN0_MB23_TIMESTAMP(val)     bfin_write16(CAN0_MB23_TIMESTAMP, val)
-#define bfin_read_CAN0_MB23_ID0()               bfin_read16(CAN0_MB23_ID0)
-#define bfin_write_CAN0_MB23_ID0(val)           bfin_write16(CAN0_MB23_ID0, val)
-#define bfin_read_CAN0_MB23_ID1()               bfin_read16(CAN0_MB23_ID1)
-#define bfin_write_CAN0_MB23_ID1(val)           bfin_write16(CAN0_MB23_ID1, val)
-#define bfin_read_CAN0_MB24_DATA0()             bfin_read16(CAN0_MB24_DATA0)
-#define bfin_write_CAN0_MB24_DATA0(val)         bfin_write16(CAN0_MB24_DATA0, val)
-#define bfin_read_CAN0_MB24_DATA1()             bfin_read16(CAN0_MB24_DATA1)
-#define bfin_write_CAN0_MB24_DATA1(val)         bfin_write16(CAN0_MB24_DATA1, val)
-#define bfin_read_CAN0_MB24_DATA2()             bfin_read16(CAN0_MB24_DATA2)
-#define bfin_write_CAN0_MB24_DATA2(val)         bfin_write16(CAN0_MB24_DATA2, val)
-#define bfin_read_CAN0_MB24_DATA3()             bfin_read16(CAN0_MB24_DATA3)
-#define bfin_write_CAN0_MB24_DATA3(val)         bfin_write16(CAN0_MB24_DATA3, val)
-#define bfin_read_CAN0_MB24_LENGTH()            bfin_read16(CAN0_MB24_LENGTH)
-#define bfin_write_CAN0_MB24_LENGTH(val)        bfin_write16(CAN0_MB24_LENGTH, val)
-#define bfin_read_CAN0_MB24_TIMESTAMP()         bfin_read16(CAN0_MB24_TIMESTAMP)
-#define bfin_write_CAN0_MB24_TIMESTAMP(val)     bfin_write16(CAN0_MB24_TIMESTAMP, val)
-#define bfin_read_CAN0_MB24_ID0()               bfin_read16(CAN0_MB24_ID0)
-#define bfin_write_CAN0_MB24_ID0(val)           bfin_write16(CAN0_MB24_ID0, val)
-#define bfin_read_CAN0_MB24_ID1()               bfin_read16(CAN0_MB24_ID1)
-#define bfin_write_CAN0_MB24_ID1(val)           bfin_write16(CAN0_MB24_ID1, val)
-#define bfin_read_CAN0_MB25_DATA0()             bfin_read16(CAN0_MB25_DATA0)
-#define bfin_write_CAN0_MB25_DATA0(val)         bfin_write16(CAN0_MB25_DATA0, val)
-#define bfin_read_CAN0_MB25_DATA1()             bfin_read16(CAN0_MB25_DATA1)
-#define bfin_write_CAN0_MB25_DATA1(val)         bfin_write16(CAN0_MB25_DATA1, val)
-#define bfin_read_CAN0_MB25_DATA2()             bfin_read16(CAN0_MB25_DATA2)
-#define bfin_write_CAN0_MB25_DATA2(val)         bfin_write16(CAN0_MB25_DATA2, val)
-#define bfin_read_CAN0_MB25_DATA3()             bfin_read16(CAN0_MB25_DATA3)
-#define bfin_write_CAN0_MB25_DATA3(val)         bfin_write16(CAN0_MB25_DATA3, val)
-#define bfin_read_CAN0_MB25_LENGTH()            bfin_read16(CAN0_MB25_LENGTH)
-#define bfin_write_CAN0_MB25_LENGTH(val)        bfin_write16(CAN0_MB25_LENGTH, val)
-#define bfin_read_CAN0_MB25_TIMESTAMP()         bfin_read16(CAN0_MB25_TIMESTAMP)
-#define bfin_write_CAN0_MB25_TIMESTAMP(val)     bfin_write16(CAN0_MB25_TIMESTAMP, val)
-#define bfin_read_CAN0_MB25_ID0()               bfin_read16(CAN0_MB25_ID0)
-#define bfin_write_CAN0_MB25_ID0(val)           bfin_write16(CAN0_MB25_ID0, val)
-#define bfin_read_CAN0_MB25_ID1()               bfin_read16(CAN0_MB25_ID1)
-#define bfin_write_CAN0_MB25_ID1(val)           bfin_write16(CAN0_MB25_ID1, val)
-#define bfin_read_CAN0_MB26_DATA0()             bfin_read16(CAN0_MB26_DATA0)
-#define bfin_write_CAN0_MB26_DATA0(val)         bfin_write16(CAN0_MB26_DATA0, val)
-#define bfin_read_CAN0_MB26_DATA1()             bfin_read16(CAN0_MB26_DATA1)
-#define bfin_write_CAN0_MB26_DATA1(val)         bfin_write16(CAN0_MB26_DATA1, val)
-#define bfin_read_CAN0_MB26_DATA2()             bfin_read16(CAN0_MB26_DATA2)
-#define bfin_write_CAN0_MB26_DATA2(val)         bfin_write16(CAN0_MB26_DATA2, val)
-#define bfin_read_CAN0_MB26_DATA3()             bfin_read16(CAN0_MB26_DATA3)
-#define bfin_write_CAN0_MB26_DATA3(val)         bfin_write16(CAN0_MB26_DATA3, val)
-#define bfin_read_CAN0_MB26_LENGTH()            bfin_read16(CAN0_MB26_LENGTH)
-#define bfin_write_CAN0_MB26_LENGTH(val)        bfin_write16(CAN0_MB26_LENGTH, val)
-#define bfin_read_CAN0_MB26_TIMESTAMP()         bfin_read16(CAN0_MB26_TIMESTAMP)
-#define bfin_write_CAN0_MB26_TIMESTAMP(val)     bfin_write16(CAN0_MB26_TIMESTAMP, val)
-#define bfin_read_CAN0_MB26_ID0()               bfin_read16(CAN0_MB26_ID0)
-#define bfin_write_CAN0_MB26_ID0(val)           bfin_write16(CAN0_MB26_ID0, val)
-#define bfin_read_CAN0_MB26_ID1()               bfin_read16(CAN0_MB26_ID1)
-#define bfin_write_CAN0_MB26_ID1(val)           bfin_write16(CAN0_MB26_ID1, val)
-#define bfin_read_CAN0_MB27_DATA0()             bfin_read16(CAN0_MB27_DATA0)
-#define bfin_write_CAN0_MB27_DATA0(val)         bfin_write16(CAN0_MB27_DATA0, val)
-#define bfin_read_CAN0_MB27_DATA1()             bfin_read16(CAN0_MB27_DATA1)
-#define bfin_write_CAN0_MB27_DATA1(val)         bfin_write16(CAN0_MB27_DATA1, val)
-#define bfin_read_CAN0_MB27_DATA2()             bfin_read16(CAN0_MB27_DATA2)
-#define bfin_write_CAN0_MB27_DATA2(val)         bfin_write16(CAN0_MB27_DATA2, val)
-#define bfin_read_CAN0_MB27_DATA3()             bfin_read16(CAN0_MB27_DATA3)
-#define bfin_write_CAN0_MB27_DATA3(val)         bfin_write16(CAN0_MB27_DATA3, val)
-#define bfin_read_CAN0_MB27_LENGTH()            bfin_read16(CAN0_MB27_LENGTH)
-#define bfin_write_CAN0_MB27_LENGTH(val)        bfin_write16(CAN0_MB27_LENGTH, val)
-#define bfin_read_CAN0_MB27_TIMESTAMP()         bfin_read16(CAN0_MB27_TIMESTAMP)
-#define bfin_write_CAN0_MB27_TIMESTAMP(val)     bfin_write16(CAN0_MB27_TIMESTAMP, val)
-#define bfin_read_CAN0_MB27_ID0()               bfin_read16(CAN0_MB27_ID0)
-#define bfin_write_CAN0_MB27_ID0(val)           bfin_write16(CAN0_MB27_ID0, val)
-#define bfin_read_CAN0_MB27_ID1()               bfin_read16(CAN0_MB27_ID1)
-#define bfin_write_CAN0_MB27_ID1(val)           bfin_write16(CAN0_MB27_ID1, val)
-#define bfin_read_CAN0_MB28_DATA0()             bfin_read16(CAN0_MB28_DATA0)
-#define bfin_write_CAN0_MB28_DATA0(val)         bfin_write16(CAN0_MB28_DATA0, val)
-#define bfin_read_CAN0_MB28_DATA1()             bfin_read16(CAN0_MB28_DATA1)
-#define bfin_write_CAN0_MB28_DATA1(val)         bfin_write16(CAN0_MB28_DATA1, val)
-#define bfin_read_CAN0_MB28_DATA2()             bfin_read16(CAN0_MB28_DATA2)
-#define bfin_write_CAN0_MB28_DATA2(val)         bfin_write16(CAN0_MB28_DATA2, val)
-#define bfin_read_CAN0_MB28_DATA3()             bfin_read16(CAN0_MB28_DATA3)
-#define bfin_write_CAN0_MB28_DATA3(val)         bfin_write16(CAN0_MB28_DATA3, val)
-#define bfin_read_CAN0_MB28_LENGTH()            bfin_read16(CAN0_MB28_LENGTH)
-#define bfin_write_CAN0_MB28_LENGTH(val)        bfin_write16(CAN0_MB28_LENGTH, val)
-#define bfin_read_CAN0_MB28_TIMESTAMP()         bfin_read16(CAN0_MB28_TIMESTAMP)
-#define bfin_write_CAN0_MB28_TIMESTAMP(val)     bfin_write16(CAN0_MB28_TIMESTAMP, val)
-#define bfin_read_CAN0_MB28_ID0()               bfin_read16(CAN0_MB28_ID0)
-#define bfin_write_CAN0_MB28_ID0(val)           bfin_write16(CAN0_MB28_ID0, val)
-#define bfin_read_CAN0_MB28_ID1()               bfin_read16(CAN0_MB28_ID1)
-#define bfin_write_CAN0_MB28_ID1(val)           bfin_write16(CAN0_MB28_ID1, val)
-#define bfin_read_CAN0_MB29_DATA0()             bfin_read16(CAN0_MB29_DATA0)
-#define bfin_write_CAN0_MB29_DATA0(val)         bfin_write16(CAN0_MB29_DATA0, val)
-#define bfin_read_CAN0_MB29_DATA1()             bfin_read16(CAN0_MB29_DATA1)
-#define bfin_write_CAN0_MB29_DATA1(val)         bfin_write16(CAN0_MB29_DATA1, val)
-#define bfin_read_CAN0_MB29_DATA2()             bfin_read16(CAN0_MB29_DATA2)
-#define bfin_write_CAN0_MB29_DATA2(val)         bfin_write16(CAN0_MB29_DATA2, val)
-#define bfin_read_CAN0_MB29_DATA3()             bfin_read16(CAN0_MB29_DATA3)
-#define bfin_write_CAN0_MB29_DATA3(val)         bfin_write16(CAN0_MB29_DATA3, val)
-#define bfin_read_CAN0_MB29_LENGTH()            bfin_read16(CAN0_MB29_LENGTH)
-#define bfin_write_CAN0_MB29_LENGTH(val)        bfin_write16(CAN0_MB29_LENGTH, val)
-#define bfin_read_CAN0_MB29_TIMESTAMP()         bfin_read16(CAN0_MB29_TIMESTAMP)
-#define bfin_write_CAN0_MB29_TIMESTAMP(val)     bfin_write16(CAN0_MB29_TIMESTAMP, val)
-#define bfin_read_CAN0_MB29_ID0()               bfin_read16(CAN0_MB29_ID0)
-#define bfin_write_CAN0_MB29_ID0(val)           bfin_write16(CAN0_MB29_ID0, val)
-#define bfin_read_CAN0_MB29_ID1()               bfin_read16(CAN0_MB29_ID1)
-#define bfin_write_CAN0_MB29_ID1(val)           bfin_write16(CAN0_MB29_ID1, val)
-#define bfin_read_CAN0_MB30_DATA0()             bfin_read16(CAN0_MB30_DATA0)
-#define bfin_write_CAN0_MB30_DATA0(val)         bfin_write16(CAN0_MB30_DATA0, val)
-#define bfin_read_CAN0_MB30_DATA1()             bfin_read16(CAN0_MB30_DATA1)
-#define bfin_write_CAN0_MB30_DATA1(val)         bfin_write16(CAN0_MB30_DATA1, val)
-#define bfin_read_CAN0_MB30_DATA2()             bfin_read16(CAN0_MB30_DATA2)
-#define bfin_write_CAN0_MB30_DATA2(val)         bfin_write16(CAN0_MB30_DATA2, val)
-#define bfin_read_CAN0_MB30_DATA3()             bfin_read16(CAN0_MB30_DATA3)
-#define bfin_write_CAN0_MB30_DATA3(val)         bfin_write16(CAN0_MB30_DATA3, val)
-#define bfin_read_CAN0_MB30_LENGTH()            bfin_read16(CAN0_MB30_LENGTH)
-#define bfin_write_CAN0_MB30_LENGTH(val)        bfin_write16(CAN0_MB30_LENGTH, val)
-#define bfin_read_CAN0_MB30_TIMESTAMP()         bfin_read16(CAN0_MB30_TIMESTAMP)
-#define bfin_write_CAN0_MB30_TIMESTAMP(val)     bfin_write16(CAN0_MB30_TIMESTAMP, val)
-#define bfin_read_CAN0_MB30_ID0()               bfin_read16(CAN0_MB30_ID0)
-#define bfin_write_CAN0_MB30_ID0(val)           bfin_write16(CAN0_MB30_ID0, val)
-#define bfin_read_CAN0_MB30_ID1()               bfin_read16(CAN0_MB30_ID1)
-#define bfin_write_CAN0_MB30_ID1(val)           bfin_write16(CAN0_MB30_ID1, val)
-#define bfin_read_CAN0_MB31_DATA0()             bfin_read16(CAN0_MB31_DATA0)
-#define bfin_write_CAN0_MB31_DATA0(val)         bfin_write16(CAN0_MB31_DATA0, val)
-#define bfin_read_CAN0_MB31_DATA1()             bfin_read16(CAN0_MB31_DATA1)
-#define bfin_write_CAN0_MB31_DATA1(val)         bfin_write16(CAN0_MB31_DATA1, val)
-#define bfin_read_CAN0_MB31_DATA2()             bfin_read16(CAN0_MB31_DATA2)
-#define bfin_write_CAN0_MB31_DATA2(val)         bfin_write16(CAN0_MB31_DATA2, val)
-#define bfin_read_CAN0_MB31_DATA3()             bfin_read16(CAN0_MB31_DATA3)
-#define bfin_write_CAN0_MB31_DATA3(val)         bfin_write16(CAN0_MB31_DATA3, val)
-#define bfin_read_CAN0_MB31_LENGTH()            bfin_read16(CAN0_MB31_LENGTH)
-#define bfin_write_CAN0_MB31_LENGTH(val)        bfin_write16(CAN0_MB31_LENGTH, val)
-#define bfin_read_CAN0_MB31_TIMESTAMP()         bfin_read16(CAN0_MB31_TIMESTAMP)
-#define bfin_write_CAN0_MB31_TIMESTAMP(val)     bfin_write16(CAN0_MB31_TIMESTAMP, val)
-#define bfin_read_CAN0_MB31_ID0()               bfin_read16(CAN0_MB31_ID0)
-#define bfin_write_CAN0_MB31_ID0(val)           bfin_write16(CAN0_MB31_ID0, val)
-#define bfin_read_CAN0_MB31_ID1()               bfin_read16(CAN0_MB31_ID1)
-#define bfin_write_CAN0_MB31_ID1(val)           bfin_write16(CAN0_MB31_ID1, val)
-
-/* UART3 Registers */
-
-#define bfin_read_UART3_DLL()           bfin_read16(UART3_DLL)
-#define bfin_write_UART3_DLL(val)       bfin_write16(UART3_DLL, val)
-#define bfin_read_UART3_DLH()           bfin_read16(UART3_DLH)
-#define bfin_write_UART3_DLH(val)       bfin_write16(UART3_DLH, val)
-#define bfin_read_UART3_GCTL()          bfin_read16(UART3_GCTL)
-#define bfin_write_UART3_GCTL(val)      bfin_write16(UART3_GCTL, val)
-#define bfin_read_UART3_LCR()           bfin_read16(UART3_LCR)
-#define bfin_write_UART3_LCR(val)       bfin_write16(UART3_LCR, val)
-#define bfin_read_UART3_MCR()           bfin_read16(UART3_MCR)
-#define bfin_write_UART3_MCR(val)       bfin_write16(UART3_MCR, val)
-#define bfin_read_UART3_LSR()           bfin_read16(UART3_LSR)
-#define bfin_write_UART3_LSR(val)       bfin_write16(UART3_LSR, val)
-#define bfin_read_UART3_MSR()           bfin_read16(UART3_MSR)
-#define bfin_write_UART3_MSR(val)       bfin_write16(UART3_MSR, val)
-#define bfin_read_UART3_SCR()           bfin_read16(UART3_SCR)
-#define bfin_write_UART3_SCR(val)       bfin_write16(UART3_SCR, val)
-#define bfin_read_UART3_IER_SET()       bfin_read16(UART3_IER_SET)
-#define bfin_write_UART3_IER_SET(val)   bfin_write16(UART3_IER_SET, val)
-#define bfin_read_UART3_IER_CLEAR()     bfin_read16(UART3_IER_CLEAR)
-#define bfin_write_UART3_IER_CLEAR(val) bfin_write16(UART3_IER_CLEAR, val)
-#define bfin_read_UART3_THR()           bfin_read16(UART3_THR)
-#define bfin_write_UART3_THR(val)       bfin_write16(UART3_THR, val)
-#define bfin_read_UART3_RBR()           bfin_read16(UART3_RBR)
-#define bfin_write_UART3_RBR(val)       bfin_write16(UART3_RBR, val)
-
-/* NFC Registers */
-
-#define bfin_read_NFC_CTL()             bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)         bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()            bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)        bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()         bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)     bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()         bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)     bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()            bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)        bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()            bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)        bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()            bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)        bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()            bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)        bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()           bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)       bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()             bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)         bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()           bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)       bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()            bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)        bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()            bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)        bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()             bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)         bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()         bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)     bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()         bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)     bfin_write16(NFC_DATA_RD, val)
-
-/* Counter Registers */
-
-#define bfin_read_CNT_CONFIG()          bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)      bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()           bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)       bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()          bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)      bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()         bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)     bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()        bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)    bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()         bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)     bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()             bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)         bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()             bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)         bfin_write32(CNT_MIN, val)
-
-/* OTP/FUSE Registers */
-
-#define bfin_read_OTP_CONTROL()         bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)     bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()             bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)         bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()          bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)      bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()          bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)      bfin_write32(OTP_TIMING, val)
-
-/* Security Registers */
-
-#define bfin_read_SECURE_SYSSWT()       bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)   bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()      bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val)  bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()       bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)   bfin_write16(SECURE_STATUS, val)
-
-/* DMA Peribfin_read_()heral Mux Register */
-
-#define bfin_read_DMAC1_PERIMUX()       bfin_read16(DMAC1_PERIMUX)
-#define bfin_write_DMAC1_PERIMUX(val)   bfin_write16(DMAC1_PERIMUX, val)
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define bfin_read_OTP_DATA0()           bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)       bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()           bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)       bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()           bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)       bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()           bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)       bfin_write32(OTP_DATA3, val)
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 bfin_read_()rocessor */
-
-/* legacy definitions */
-#define bfin_read_EBIU_AMCBCTL0         bfin_read_EBIU_AMBCTL0
-#define bfin_write_EBIU_AMCBCTL0        bfin_write_EBIU_AMBCTL0
-#define bfin_read_EBIU_AMCBCTL1         bfin_read_EBIU_AMBCTL1
-#define bfin_write_EBIU_AMCBCTL1        bfin_write_EBIU_AMBCTL1
-#define bfin_read_PINT0_IRQ             bfin_read_PINT0_REQUEST
-#define bfin_write_PINT0_IRQ            bfin_write_PINT0_REQUEST
-#define bfin_read_PINT1_IRQ             bfin_read_PINT1_REQUEST
-#define bfin_write_PINT1_IRQ            bfin_write_PINT1_REQUEST
-#define bfin_read_PINT2_IRQ             bfin_read_PINT2_REQUEST
-#define bfin_write_PINT2_IRQ            bfin_write_PINT2_REQUEST
-#define bfin_read_PINT3_IRQ             bfin_read_PINT3_REQUEST
-#define bfin_write_PINT3_IRQ            bfin_write_PINT3_REQUEST
-
-#endif /* _CDEF_BF54X_H */
-
diff --git a/include/asm-blackfin/mach-bf548/defBF542.h b/include/asm-blackfin/mach-bf548/defBF542.h
deleted file mode 100644
index a7c809f29ede..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF542.h
+++ /dev/null
@@ -1,925 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF542.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF542_H
-#define _DEF_BF542_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF542 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF542 that are not in the common header */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF542_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF544.h b/include/asm-blackfin/mach-bf548/defBF544.h
deleted file mode 100644
index b8b9870e2697..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF544.h
+++ /dev/null
@@ -1,707 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF544.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF544_H
-#define _DEF_BF544_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF544 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF544 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define                  COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                   TIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-#endif /* _DEF_BF544_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF547.h b/include/asm-blackfin/mach-bf548/defBF547.h
deleted file mode 100644
index 3a3a18ebb10e..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF547.h
+++ /dev/null
@@ -1,1244 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF547.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF548.h b/include/asm-blackfin/mach-bf548/defBF548.h
deleted file mode 100644
index 1d7c96edb038..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF548.h
+++ /dev/null
@@ -1,1627 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF548.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF548_H
-#define _DEF_BF548_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF548 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF548 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                 HSTIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-
-#endif /* _DEF_BF548_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF549.h b/include/asm-blackfin/mach-bf548/defBF549.h
deleted file mode 100644
index fcb72b41e007..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF549.h
+++ /dev/null
@@ -1,2737 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF549.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF549_H
-#define _DEF_BF549_H
-
-/* Include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-
-/* SYSTEM & MMR ADDRESS DEFINITIONS FOR ADSP-BF549 */
-
-/* Include defBF54x_base.h for the set of #defines that are common to all ADSP-BF54x processors */
-#include "defBF54x_base.h"
-
-/* The following are the #defines needed by ADSP-BF549 that are not in the common header */
-
-/* Timer Registers */
-
-#define                    TIMER8_CONFIG  0xffc00600   /* Timer 8 Configuration Register */
-#define                   TIMER8_COUNTER  0xffc00604   /* Timer 8 Counter Register */
-#define                    TIMER8_PERIOD  0xffc00608   /* Timer 8 Period Register */
-#define                     TIMER8_WIDTH  0xffc0060c   /* Timer 8 Width Register */
-#define                    TIMER9_CONFIG  0xffc00610   /* Timer 9 Configuration Register */
-#define                   TIMER9_COUNTER  0xffc00614   /* Timer 9 Counter Register */
-#define                    TIMER9_PERIOD  0xffc00618   /* Timer 9 Period Register */
-#define                     TIMER9_WIDTH  0xffc0061c   /* Timer 9 Width Register */
-#define                   TIMER10_CONFIG  0xffc00620   /* Timer 10 Configuration Register */
-#define                  TIMER10_COUNTER  0xffc00624   /* Timer 10 Counter Register */
-#define                   TIMER10_PERIOD  0xffc00628   /* Timer 10 Period Register */
-#define                    TIMER10_WIDTH  0xffc0062c   /* Timer 10 Width Register */
-
-/* Timer Group of 3 Registers */
-
-#define                    TIMER_ENABLE1  0xffc00640   /* Timer Group of 3 Enable Register */
-#define                   TIMER_DISABLE1  0xffc00644   /* Timer Group of 3 Disable Register */
-#define                    TIMER_STATUS1  0xffc00648   /* Timer Group of 3 Status Register */
-
-/* SPORT0 Registers */
-
-#define                      SPORT0_TCR1  0xffc00800   /* SPORT0 Transmit Configuration 1 Register */
-#define                      SPORT0_TCR2  0xffc00804   /* SPORT0 Transmit Configuration 2 Register */
-#define                   SPORT0_TCLKDIV  0xffc00808   /* SPORT0 Transmit Serial Clock Divider Register */
-#define                    SPORT0_TFSDIV  0xffc0080c   /* SPORT0 Transmit Frame Sync Divider Register */
-#define                        SPORT0_TX  0xffc00810   /* SPORT0 Transmit Data Register */
-#define                        SPORT0_RX  0xffc00818   /* SPORT0 Receive Data Register */
-#define                      SPORT0_RCR1  0xffc00820   /* SPORT0 Receive Configuration 1 Register */
-#define                      SPORT0_RCR2  0xffc00824   /* SPORT0 Receive Configuration 2 Register */
-#define                   SPORT0_RCLKDIV  0xffc00828   /* SPORT0 Receive Serial Clock Divider Register */
-#define                    SPORT0_RFSDIV  0xffc0082c   /* SPORT0 Receive Frame Sync Divider Register */
-#define                      SPORT0_STAT  0xffc00830   /* SPORT0 Status Register */
-#define                      SPORT0_CHNL  0xffc00834   /* SPORT0 Current Channel Register */
-#define                     SPORT0_MCMC1  0xffc00838   /* SPORT0 Multi channel Configuration Register 1 */
-#define                     SPORT0_MCMC2  0xffc0083c   /* SPORT0 Multi channel Configuration Register 2 */
-#define                     SPORT0_MTCS0  0xffc00840   /* SPORT0 Multi channel Transmit Select Register 0 */
-#define                     SPORT0_MTCS1  0xffc00844   /* SPORT0 Multi channel Transmit Select Register 1 */
-#define                     SPORT0_MTCS2  0xffc00848   /* SPORT0 Multi channel Transmit Select Register 2 */
-#define                     SPORT0_MTCS3  0xffc0084c   /* SPORT0 Multi channel Transmit Select Register 3 */
-#define                     SPORT0_MRCS0  0xffc00850   /* SPORT0 Multi channel Receive Select Register 0 */
-#define                     SPORT0_MRCS1  0xffc00854   /* SPORT0 Multi channel Receive Select Register 1 */
-#define                     SPORT0_MRCS2  0xffc00858   /* SPORT0 Multi channel Receive Select Register 2 */
-#define                     SPORT0_MRCS3  0xffc0085c   /* SPORT0 Multi channel Receive Select Register 3 */
-
-/* EPPI0 Registers */
-
-#define                     EPPI0_STATUS  0xffc01000   /* EPPI0 Status Register */
-#define                     EPPI0_HCOUNT  0xffc01004   /* EPPI0 Horizontal Transfer Count Register */
-#define                     EPPI0_HDELAY  0xffc01008   /* EPPI0 Horizontal Delay Count Register */
-#define                     EPPI0_VCOUNT  0xffc0100c   /* EPPI0 Vertical Transfer Count Register */
-#define                     EPPI0_VDELAY  0xffc01010   /* EPPI0 Vertical Delay Count Register */
-#define                      EPPI0_FRAME  0xffc01014   /* EPPI0 Lines per Frame Register */
-#define                       EPPI0_LINE  0xffc01018   /* EPPI0 Samples per Line Register */
-#define                     EPPI0_CLKDIV  0xffc0101c   /* EPPI0 Clock Divide Register */
-#define                    EPPI0_CONTROL  0xffc01020   /* EPPI0 Control Register */
-#define                   EPPI0_FS1W_HBL  0xffc01024   /* EPPI0 FS1 Width Register / EPPI0 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI0_FS1P_AVPL  0xffc01028   /* EPPI0 FS1 Period Register / EPPI0 Active Video Samples Per Line Register */
-#define                   EPPI0_FS2W_LVB  0xffc0102c   /* EPPI0 FS2 Width Register / EPPI0 Lines of Vertical Blanking Register */
-#define                  EPPI0_FS2P_LAVF  0xffc01030   /* EPPI0 FS2 Period Register/ EPPI0 Lines of Active Video Per Field Register */
-#define                       EPPI0_CLIP  0xffc01034   /* EPPI0 Clipping Register */
-
-/* UART2 Registers */
-
-#define                        UART2_DLL  0xffc02100   /* Divisor Latch Low Byte */
-#define                        UART2_DLH  0xffc02104   /* Divisor Latch High Byte */
-#define                       UART2_GCTL  0xffc02108   /* Global Control Register */
-#define                        UART2_LCR  0xffc0210c   /* Line Control Register */
-#define                        UART2_MCR  0xffc02110   /* Modem Control Register */
-#define                        UART2_LSR  0xffc02114   /* Line Status Register */
-#define                        UART2_MSR  0xffc02118   /* Modem Status Register */
-#define                        UART2_SCR  0xffc0211c   /* Scratch Register */
-#define                    UART2_IER_SET  0xffc02120   /* Interrupt Enable Register Set */
-#define                  UART2_IER_CLEAR  0xffc02124   /* Interrupt Enable Register Clear */
-#define                        UART2_RBR  0xffc0212c   /* Receive Buffer Register */
-
-/* Two Wire Interface Registers (TWI1) */
-
-#define                     TWI1_REGBASE  0xffc02200
-#define                      TWI1_CLKDIV  0xffc02200   /* Clock Divider Register */
-#define                     TWI1_CONTROL  0xffc02204   /* TWI Control Register */
-#define                  TWI1_SLAVE_CTRL  0xffc02208   /* TWI Slave Mode Control Register */
-#define                  TWI1_SLAVE_STAT  0xffc0220c   /* TWI Slave Mode Status Register */
-#define                  TWI1_SLAVE_ADDR  0xffc02210   /* TWI Slave Mode Address Register */
-#define                 TWI1_MASTER_CTRL  0xffc02214   /* TWI Master Mode Control Register */
-#define                 TWI1_MASTER_STAT  0xffc02218   /* TWI Master Mode Status Register */
-#define                 TWI1_MASTER_ADDR  0xffc0221c   /* TWI Master Mode Address Register */
-#define                    TWI1_INT_STAT  0xffc02220   /* TWI Interrupt Status Register */
-#define                    TWI1_INT_MASK  0xffc02224   /* TWI Interrupt Mask Register */
-#define                   TWI1_FIFO_CTRL  0xffc02228   /* TWI FIFO Control Register */
-#define                   TWI1_FIFO_STAT  0xffc0222c   /* TWI FIFO Status Register */
-#define                   TWI1_XMT_DATA8  0xffc02280   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI1_XMT_DATA16  0xffc02284   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI1_RCV_DATA8  0xffc02288   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI1_RCV_DATA16  0xffc0228c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPI2  Registers */
-
-#define                     SPI2_REGBASE  0xffc02400
-#define                         SPI2_CTL  0xffc02400   /* SPI2 Control Register */
-#define                         SPI2_FLG  0xffc02404   /* SPI2 Flag Register */
-#define                        SPI2_STAT  0xffc02408   /* SPI2 Status Register */
-#define                        SPI2_TDBR  0xffc0240c   /* SPI2 Transmit Data Buffer Register */
-#define                        SPI2_RDBR  0xffc02410   /* SPI2 Receive Data Buffer Register */
-#define                        SPI2_BAUD  0xffc02414   /* SPI2 Baud Rate Register */
-#define                      SPI2_SHADOW  0xffc02418   /* SPI2 Receive Data Buffer Shadow Register */
-
-/* MXVR Registers */
-
-#define                      MXVR_CONFIG  0xffc02700   /* MXVR Configuration Register */
-#define                     MXVR_STATE_0  0xffc02708   /* MXVR State Register 0 */
-#define                     MXVR_STATE_1  0xffc0270c   /* MXVR State Register 1 */
-#define                  MXVR_INT_STAT_0  0xffc02710   /* MXVR Interrupt Status Register 0 */
-#define                  MXVR_INT_STAT_1  0xffc02714   /* MXVR Interrupt Status Register 1 */
-#define                    MXVR_INT_EN_0  0xffc02718   /* MXVR Interrupt Enable Register 0 */
-#define                    MXVR_INT_EN_1  0xffc0271c   /* MXVR Interrupt Enable Register 1 */
-#define                    MXVR_POSITION  0xffc02720   /* MXVR Node Position Register */
-#define                MXVR_MAX_POSITION  0xffc02724   /* MXVR Maximum Node Position Register */
-#define                       MXVR_DELAY  0xffc02728   /* MXVR Node Frame Delay Register */
-#define                   MXVR_MAX_DELAY  0xffc0272c   /* MXVR Maximum Node Frame Delay Register */
-#define                       MXVR_LADDR  0xffc02730   /* MXVR Logical Address Register */
-#define                       MXVR_GADDR  0xffc02734   /* MXVR Group Address Register */
-#define                       MXVR_AADDR  0xffc02738   /* MXVR Alternate Address Register */
-
-/* MXVR Allocation Table Registers */
-
-#define                     MXVR_ALLOC_0  0xffc0273c   /* MXVR Allocation Table Register 0 */
-#define                     MXVR_ALLOC_1  0xffc02740   /* MXVR Allocation Table Register 1 */
-#define                     MXVR_ALLOC_2  0xffc02744   /* MXVR Allocation Table Register 2 */
-#define                     MXVR_ALLOC_3  0xffc02748   /* MXVR Allocation Table Register 3 */
-#define                     MXVR_ALLOC_4  0xffc0274c   /* MXVR Allocation Table Register 4 */
-#define                     MXVR_ALLOC_5  0xffc02750   /* MXVR Allocation Table Register 5 */
-#define                     MXVR_ALLOC_6  0xffc02754   /* MXVR Allocation Table Register 6 */
-#define                     MXVR_ALLOC_7  0xffc02758   /* MXVR Allocation Table Register 7 */
-#define                     MXVR_ALLOC_8  0xffc0275c   /* MXVR Allocation Table Register 8 */
-#define                     MXVR_ALLOC_9  0xffc02760   /* MXVR Allocation Table Register 9 */
-#define                    MXVR_ALLOC_10  0xffc02764   /* MXVR Allocation Table Register 10 */
-#define                    MXVR_ALLOC_11  0xffc02768   /* MXVR Allocation Table Register 11 */
-#define                    MXVR_ALLOC_12  0xffc0276c   /* MXVR Allocation Table Register 12 */
-#define                    MXVR_ALLOC_13  0xffc02770   /* MXVR Allocation Table Register 13 */
-#define                    MXVR_ALLOC_14  0xffc02774   /* MXVR Allocation Table Register 14 */
-
-/* MXVR Channel Assign Registers */
-
-#define                MXVR_SYNC_LCHAN_0  0xffc02778   /* MXVR Sync Data Logical Channel Assign Register 0 */
-#define                MXVR_SYNC_LCHAN_1  0xffc0277c   /* MXVR Sync Data Logical Channel Assign Register 1 */
-#define                MXVR_SYNC_LCHAN_2  0xffc02780   /* MXVR Sync Data Logical Channel Assign Register 2 */
-#define                MXVR_SYNC_LCHAN_3  0xffc02784   /* MXVR Sync Data Logical Channel Assign Register 3 */
-#define                MXVR_SYNC_LCHAN_4  0xffc02788   /* MXVR Sync Data Logical Channel Assign Register 4 */
-#define                MXVR_SYNC_LCHAN_5  0xffc0278c   /* MXVR Sync Data Logical Channel Assign Register 5 */
-#define                MXVR_SYNC_LCHAN_6  0xffc02790   /* MXVR Sync Data Logical Channel Assign Register 6 */
-#define                MXVR_SYNC_LCHAN_7  0xffc02794   /* MXVR Sync Data Logical Channel Assign Register 7 */
-
-/* MXVR DMA0 Registers */
-
-#define                 MXVR_DMA0_CONFIG  0xffc02798   /* MXVR Sync Data DMA0 Config Register */
-#define             MXVR_DMA0_START_ADDR  0xffc0279c   /* MXVR Sync Data DMA0 Start Address */
-#define                  MXVR_DMA0_COUNT  0xffc027a0   /* MXVR Sync Data DMA0 Loop Count Register */
-#define              MXVR_DMA0_CURR_ADDR  0xffc027a4   /* MXVR Sync Data DMA0 Current Address */
-#define             MXVR_DMA0_CURR_COUNT  0xffc027a8   /* MXVR Sync Data DMA0 Current Loop Count */
-
-/* MXVR DMA1 Registers */
-
-#define                 MXVR_DMA1_CONFIG  0xffc027ac   /* MXVR Sync Data DMA1 Config Register */
-#define             MXVR_DMA1_START_ADDR  0xffc027b0   /* MXVR Sync Data DMA1 Start Address */
-#define                  MXVR_DMA1_COUNT  0xffc027b4   /* MXVR Sync Data DMA1 Loop Count Register */
-#define              MXVR_DMA1_CURR_ADDR  0xffc027b8   /* MXVR Sync Data DMA1 Current Address */
-#define             MXVR_DMA1_CURR_COUNT  0xffc027bc   /* MXVR Sync Data DMA1 Current Loop Count */
-
-/* MXVR DMA2 Registers */
-
-#define                 MXVR_DMA2_CONFIG  0xffc027c0   /* MXVR Sync Data DMA2 Config Register */
-#define             MXVR_DMA2_START_ADDR  0xffc027c4   /* MXVR Sync Data DMA2 Start Address */
-#define                  MXVR_DMA2_COUNT  0xffc027c8   /* MXVR Sync Data DMA2 Loop Count Register */
-#define              MXVR_DMA2_CURR_ADDR  0xffc027cc   /* MXVR Sync Data DMA2 Current Address */
-#define             MXVR_DMA2_CURR_COUNT  0xffc027d0   /* MXVR Sync Data DMA2 Current Loop Count */
-
-/* MXVR DMA3 Registers */
-
-#define                 MXVR_DMA3_CONFIG  0xffc027d4   /* MXVR Sync Data DMA3 Config Register */
-#define             MXVR_DMA3_START_ADDR  0xffc027d8   /* MXVR Sync Data DMA3 Start Address */
-#define                  MXVR_DMA3_COUNT  0xffc027dc   /* MXVR Sync Data DMA3 Loop Count Register */
-#define              MXVR_DMA3_CURR_ADDR  0xffc027e0   /* MXVR Sync Data DMA3 Current Address */
-#define             MXVR_DMA3_CURR_COUNT  0xffc027e4   /* MXVR Sync Data DMA3 Current Loop Count */
-
-/* MXVR DMA4 Registers */
-
-#define                 MXVR_DMA4_CONFIG  0xffc027e8   /* MXVR Sync Data DMA4 Config Register */
-#define             MXVR_DMA4_START_ADDR  0xffc027ec   /* MXVR Sync Data DMA4 Start Address */
-#define                  MXVR_DMA4_COUNT  0xffc027f0   /* MXVR Sync Data DMA4 Loop Count Register */
-#define              MXVR_DMA4_CURR_ADDR  0xffc027f4   /* MXVR Sync Data DMA4 Current Address */
-#define             MXVR_DMA4_CURR_COUNT  0xffc027f8   /* MXVR Sync Data DMA4 Current Loop Count */
-
-/* MXVR DMA5 Registers */
-
-#define                 MXVR_DMA5_CONFIG  0xffc027fc   /* MXVR Sync Data DMA5 Config Register */
-#define             MXVR_DMA5_START_ADDR  0xffc02800   /* MXVR Sync Data DMA5 Start Address */
-#define                  MXVR_DMA5_COUNT  0xffc02804   /* MXVR Sync Data DMA5 Loop Count Register */
-#define              MXVR_DMA5_CURR_ADDR  0xffc02808   /* MXVR Sync Data DMA5 Current Address */
-#define             MXVR_DMA5_CURR_COUNT  0xffc0280c   /* MXVR Sync Data DMA5 Current Loop Count */
-
-/* MXVR DMA6 Registers */
-
-#define                 MXVR_DMA6_CONFIG  0xffc02810   /* MXVR Sync Data DMA6 Config Register */
-#define             MXVR_DMA6_START_ADDR  0xffc02814   /* MXVR Sync Data DMA6 Start Address */
-#define                  MXVR_DMA6_COUNT  0xffc02818   /* MXVR Sync Data DMA6 Loop Count Register */
-#define              MXVR_DMA6_CURR_ADDR  0xffc0281c   /* MXVR Sync Data DMA6 Current Address */
-#define             MXVR_DMA6_CURR_COUNT  0xffc02820   /* MXVR Sync Data DMA6 Current Loop Count */
-
-/* MXVR DMA7 Registers */
-
-#define                 MXVR_DMA7_CONFIG  0xffc02824   /* MXVR Sync Data DMA7 Config Register */
-#define             MXVR_DMA7_START_ADDR  0xffc02828   /* MXVR Sync Data DMA7 Start Address */
-#define                  MXVR_DMA7_COUNT  0xffc0282c   /* MXVR Sync Data DMA7 Loop Count Register */
-#define              MXVR_DMA7_CURR_ADDR  0xffc02830   /* MXVR Sync Data DMA7 Current Address */
-#define             MXVR_DMA7_CURR_COUNT  0xffc02834   /* MXVR Sync Data DMA7 Current Loop Count */
-
-/* MXVR Asynch Packet Registers */
-
-#define                      MXVR_AP_CTL  0xffc02838   /* MXVR Async Packet Control Register */
-#define             MXVR_APRB_START_ADDR  0xffc0283c   /* MXVR Async Packet RX Buffer Start Addr Register */
-#define              MXVR_APRB_CURR_ADDR  0xffc02840   /* MXVR Async Packet RX Buffer Current Addr Register */
-#define             MXVR_APTB_START_ADDR  0xffc02844   /* MXVR Async Packet TX Buffer Start Addr Register */
-#define              MXVR_APTB_CURR_ADDR  0xffc02848   /* MXVR Async Packet TX Buffer Current Addr Register */
-
-/* MXVR Control Message Registers */
-
-#define                      MXVR_CM_CTL  0xffc0284c   /* MXVR Control Message Control Register */
-#define             MXVR_CMRB_START_ADDR  0xffc02850   /* MXVR Control Message RX Buffer Start Addr Register */
-#define              MXVR_CMRB_CURR_ADDR  0xffc02854   /* MXVR Control Message RX Buffer Current Address */
-#define             MXVR_CMTB_START_ADDR  0xffc02858   /* MXVR Control Message TX Buffer Start Addr Register */
-#define              MXVR_CMTB_CURR_ADDR  0xffc0285c   /* MXVR Control Message TX Buffer Current Address */
-
-/* MXVR Remote Read Registers */
-
-#define             MXVR_RRDB_START_ADDR  0xffc02860   /* MXVR Remote Read Buffer Start Addr Register */
-#define              MXVR_RRDB_CURR_ADDR  0xffc02864   /* MXVR Remote Read Buffer Current Addr Register */
-
-/* MXVR Pattern Data Registers */
-
-#define                  MXVR_PAT_DATA_0  0xffc02868   /* MXVR Pattern Data Register 0 */
-#define                    MXVR_PAT_EN_0  0xffc0286c   /* MXVR Pattern Enable Register 0 */
-#define                  MXVR_PAT_DATA_1  0xffc02870   /* MXVR Pattern Data Register 1 */
-#define                    MXVR_PAT_EN_1  0xffc02874   /* MXVR Pattern Enable Register 1 */
-
-/* MXVR Frame Counter Registers */
-
-#define                 MXVR_FRAME_CNT_0  0xffc02878   /* MXVR Frame Counter 0 */
-#define                 MXVR_FRAME_CNT_1  0xffc0287c   /* MXVR Frame Counter 1 */
-
-/* MXVR Routing Table Registers */
-
-#define                   MXVR_ROUTING_0  0xffc02880   /* MXVR Routing Table Register 0 */
-#define                   MXVR_ROUTING_1  0xffc02884   /* MXVR Routing Table Register 1 */
-#define                   MXVR_ROUTING_2  0xffc02888   /* MXVR Routing Table Register 2 */
-#define                   MXVR_ROUTING_3  0xffc0288c   /* MXVR Routing Table Register 3 */
-#define                   MXVR_ROUTING_4  0xffc02890   /* MXVR Routing Table Register 4 */
-#define                   MXVR_ROUTING_5  0xffc02894   /* MXVR Routing Table Register 5 */
-#define                   MXVR_ROUTING_6  0xffc02898   /* MXVR Routing Table Register 6 */
-#define                   MXVR_ROUTING_7  0xffc0289c   /* MXVR Routing Table Register 7 */
-#define                   MXVR_ROUTING_8  0xffc028a0   /* MXVR Routing Table Register 8 */
-#define                   MXVR_ROUTING_9  0xffc028a4   /* MXVR Routing Table Register 9 */
-#define                  MXVR_ROUTING_10  0xffc028a8   /* MXVR Routing Table Register 10 */
-#define                  MXVR_ROUTING_11  0xffc028ac   /* MXVR Routing Table Register 11 */
-#define                  MXVR_ROUTING_12  0xffc028b0   /* MXVR Routing Table Register 12 */
-#define                  MXVR_ROUTING_13  0xffc028b4   /* MXVR Routing Table Register 13 */
-#define                  MXVR_ROUTING_14  0xffc028b8   /* MXVR Routing Table Register 14 */
-
-/* MXVR Counter-Clock-Control Registers */
-
-#define                   MXVR_BLOCK_CNT  0xffc028c0   /* MXVR Block Counter */
-#define                     MXVR_CLK_CTL  0xffc028d0   /* MXVR Clock Control Register */
-#define                  MXVR_CDRPLL_CTL  0xffc028d4   /* MXVR Clock/Data Recovery PLL Control Register */
-#define                   MXVR_FMPLL_CTL  0xffc028d8   /* MXVR Frequency Multiply PLL Control Register */
-#define                     MXVR_PIN_CTL  0xffc028dc   /* MXVR Pin Control Register */
-#define                    MXVR_SCLK_CNT  0xffc028e0   /* MXVR System Clock Counter Register */
-
-/* CAN Controller 1 Config 1 Registers */
-
-#define                         CAN1_MC1  0xffc03200   /* CAN Controller 1 Mailbox Configuration Register 1 */
-#define                         CAN1_MD1  0xffc03204   /* CAN Controller 1 Mailbox Direction Register 1 */
-#define                        CAN1_TRS1  0xffc03208   /* CAN Controller 1 Transmit Request Set Register 1 */
-#define                        CAN1_TRR1  0xffc0320c   /* CAN Controller 1 Transmit Request Reset Register 1 */
-#define                         CAN1_TA1  0xffc03210   /* CAN Controller 1 Transmit Acknowledge Register 1 */
-#define                         CAN1_AA1  0xffc03214   /* CAN Controller 1 Abort Acknowledge Register 1 */
-#define                        CAN1_RMP1  0xffc03218   /* CAN Controller 1 Receive Message Pending Register 1 */
-#define                        CAN1_RML1  0xffc0321c   /* CAN Controller 1 Receive Message Lost Register 1 */
-#define                      CAN1_MBTIF1  0xffc03220   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN1_MBRIF1  0xffc03224   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN1_MBIM1  0xffc03228   /* CAN Controller 1 Mailbox Interrupt Mask Register 1 */
-#define                        CAN1_RFH1  0xffc0322c   /* CAN Controller 1 Remote Frame Handling Enable Register 1 */
-#define                       CAN1_OPSS1  0xffc03230   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 1 Config 2 Registers */
-
-#define                         CAN1_MC2  0xffc03240   /* CAN Controller 1 Mailbox Configuration Register 2 */
-#define                         CAN1_MD2  0xffc03244   /* CAN Controller 1 Mailbox Direction Register 2 */
-#define                        CAN1_TRS2  0xffc03248   /* CAN Controller 1 Transmit Request Set Register 2 */
-#define                        CAN1_TRR2  0xffc0324c   /* CAN Controller 1 Transmit Request Reset Register 2 */
-#define                         CAN1_TA2  0xffc03250   /* CAN Controller 1 Transmit Acknowledge Register 2 */
-#define                         CAN1_AA2  0xffc03254   /* CAN Controller 1 Abort Acknowledge Register 2 */
-#define                        CAN1_RMP2  0xffc03258   /* CAN Controller 1 Receive Message Pending Register 2 */
-#define                        CAN1_RML2  0xffc0325c   /* CAN Controller 1 Receive Message Lost Register 2 */
-#define                      CAN1_MBTIF2  0xffc03260   /* CAN Controller 1 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN1_MBRIF2  0xffc03264   /* CAN Controller 1 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN1_MBIM2  0xffc03268   /* CAN Controller 1 Mailbox Interrupt Mask Register 2 */
-#define                        CAN1_RFH2  0xffc0326c   /* CAN Controller 1 Remote Frame Handling Enable Register 2 */
-#define                       CAN1_OPSS2  0xffc03270   /* CAN Controller 1 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 1 Clock/Interrupt/Counter Registers */
-
-#define                       CAN1_CLOCK  0xffc03280   /* CAN Controller 1 Clock Register */
-#define                      CAN1_TIMING  0xffc03284   /* CAN Controller 1 Timing Register */
-#define                       CAN1_DEBUG  0xffc03288   /* CAN Controller 1 Debug Register */
-#define                      CAN1_STATUS  0xffc0328c   /* CAN Controller 1 Global Status Register */
-#define                         CAN1_CEC  0xffc03290   /* CAN Controller 1 Error Counter Register */
-#define                         CAN1_GIS  0xffc03294   /* CAN Controller 1 Global Interrupt Status Register */
-#define                         CAN1_GIM  0xffc03298   /* CAN Controller 1 Global Interrupt Mask Register */
-#define                         CAN1_GIF  0xffc0329c   /* CAN Controller 1 Global Interrupt Flag Register */
-#define                     CAN1_CONTROL  0xffc032a0   /* CAN Controller 1 Master Control Register */
-#define                        CAN1_INTR  0xffc032a4   /* CAN Controller 1 Interrupt Pending Register */
-#define                        CAN1_MBTD  0xffc032ac   /* CAN Controller 1 Mailbox Temporary Disable Register */
-#define                         CAN1_EWR  0xffc032b0   /* CAN Controller 1 Programmable Warning Level Register */
-#define                         CAN1_ESR  0xffc032b4   /* CAN Controller 1 Error Status Register */
-#define                       CAN1_UCCNT  0xffc032c4   /* CAN Controller 1 Universal Counter Register */
-#define                        CAN1_UCRC  0xffc032c8   /* CAN Controller 1 Universal Counter Force Reload Register */
-#define                       CAN1_UCCNF  0xffc032cc   /* CAN Controller 1 Universal Counter Configuration Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM00L  0xffc03300   /* CAN Controller 1 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN1_AM00H  0xffc03304   /* CAN Controller 1 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN1_AM01L  0xffc03308   /* CAN Controller 1 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN1_AM01H  0xffc0330c   /* CAN Controller 1 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN1_AM02L  0xffc03310   /* CAN Controller 1 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN1_AM02H  0xffc03314   /* CAN Controller 1 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN1_AM03L  0xffc03318   /* CAN Controller 1 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN1_AM03H  0xffc0331c   /* CAN Controller 1 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN1_AM04L  0xffc03320   /* CAN Controller 1 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN1_AM04H  0xffc03324   /* CAN Controller 1 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN1_AM05L  0xffc03328   /* CAN Controller 1 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN1_AM05H  0xffc0332c   /* CAN Controller 1 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN1_AM06L  0xffc03330   /* CAN Controller 1 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN1_AM06H  0xffc03334   /* CAN Controller 1 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN1_AM07L  0xffc03338   /* CAN Controller 1 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN1_AM07H  0xffc0333c   /* CAN Controller 1 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN1_AM08L  0xffc03340   /* CAN Controller 1 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN1_AM08H  0xffc03344   /* CAN Controller 1 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN1_AM09L  0xffc03348   /* CAN Controller 1 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN1_AM09H  0xffc0334c   /* CAN Controller 1 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN1_AM10L  0xffc03350   /* CAN Controller 1 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN1_AM10H  0xffc03354   /* CAN Controller 1 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN1_AM11L  0xffc03358   /* CAN Controller 1 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN1_AM11H  0xffc0335c   /* CAN Controller 1 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN1_AM12L  0xffc03360   /* CAN Controller 1 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN1_AM12H  0xffc03364   /* CAN Controller 1 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN1_AM13L  0xffc03368   /* CAN Controller 1 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN1_AM13H  0xffc0336c   /* CAN Controller 1 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN1_AM14L  0xffc03370   /* CAN Controller 1 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN1_AM14H  0xffc03374   /* CAN Controller 1 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN1_AM15L  0xffc03378   /* CAN Controller 1 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN1_AM15H  0xffc0337c   /* CAN Controller 1 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Acceptance Registers */
-
-#define                       CAN1_AM16L  0xffc03380   /* CAN Controller 1 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN1_AM16H  0xffc03384   /* CAN Controller 1 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN1_AM17L  0xffc03388   /* CAN Controller 1 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN1_AM17H  0xffc0338c   /* CAN Controller 1 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN1_AM18L  0xffc03390   /* CAN Controller 1 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN1_AM18H  0xffc03394   /* CAN Controller 1 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN1_AM19L  0xffc03398   /* CAN Controller 1 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN1_AM19H  0xffc0339c   /* CAN Controller 1 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN1_AM20L  0xffc033a0   /* CAN Controller 1 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN1_AM20H  0xffc033a4   /* CAN Controller 1 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN1_AM21L  0xffc033a8   /* CAN Controller 1 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN1_AM21H  0xffc033ac   /* CAN Controller 1 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN1_AM22L  0xffc033b0   /* CAN Controller 1 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN1_AM22H  0xffc033b4   /* CAN Controller 1 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN1_AM23L  0xffc033b8   /* CAN Controller 1 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN1_AM23H  0xffc033bc   /* CAN Controller 1 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN1_AM24L  0xffc033c0   /* CAN Controller 1 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN1_AM24H  0xffc033c4   /* CAN Controller 1 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN1_AM25L  0xffc033c8   /* CAN Controller 1 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN1_AM25H  0xffc033cc   /* CAN Controller 1 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN1_AM26L  0xffc033d0   /* CAN Controller 1 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN1_AM26H  0xffc033d4   /* CAN Controller 1 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN1_AM27L  0xffc033d8   /* CAN Controller 1 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN1_AM27H  0xffc033dc   /* CAN Controller 1 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN1_AM28L  0xffc033e0   /* CAN Controller 1 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN1_AM28H  0xffc033e4   /* CAN Controller 1 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN1_AM29L  0xffc033e8   /* CAN Controller 1 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN1_AM29H  0xffc033ec   /* CAN Controller 1 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN1_AM30L  0xffc033f0   /* CAN Controller 1 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN1_AM30H  0xffc033f4   /* CAN Controller 1 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN1_AM31L  0xffc033f8   /* CAN Controller 1 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN1_AM31H  0xffc033fc   /* CAN Controller 1 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB00_DATA0  0xffc03400   /* CAN Controller 1 Mailbox 0 Data 0 Register */
-#define                  CAN1_MB00_DATA1  0xffc03404   /* CAN Controller 1 Mailbox 0 Data 1 Register */
-#define                  CAN1_MB00_DATA2  0xffc03408   /* CAN Controller 1 Mailbox 0 Data 2 Register */
-#define                  CAN1_MB00_DATA3  0xffc0340c   /* CAN Controller 1 Mailbox 0 Data 3 Register */
-#define                 CAN1_MB00_LENGTH  0xffc03410   /* CAN Controller 1 Mailbox 0 Length Register */
-#define              CAN1_MB00_TIMESTAMP  0xffc03414   /* CAN Controller 1 Mailbox 0 Timestamp Register */
-#define                    CAN1_MB00_ID0  0xffc03418   /* CAN Controller 1 Mailbox 0 ID0 Register */
-#define                    CAN1_MB00_ID1  0xffc0341c   /* CAN Controller 1 Mailbox 0 ID1 Register */
-#define                  CAN1_MB01_DATA0  0xffc03420   /* CAN Controller 1 Mailbox 1 Data 0 Register */
-#define                  CAN1_MB01_DATA1  0xffc03424   /* CAN Controller 1 Mailbox 1 Data 1 Register */
-#define                  CAN1_MB01_DATA2  0xffc03428   /* CAN Controller 1 Mailbox 1 Data 2 Register */
-#define                  CAN1_MB01_DATA3  0xffc0342c   /* CAN Controller 1 Mailbox 1 Data 3 Register */
-#define                 CAN1_MB01_LENGTH  0xffc03430   /* CAN Controller 1 Mailbox 1 Length Register */
-#define              CAN1_MB01_TIMESTAMP  0xffc03434   /* CAN Controller 1 Mailbox 1 Timestamp Register */
-#define                    CAN1_MB01_ID0  0xffc03438   /* CAN Controller 1 Mailbox 1 ID0 Register */
-#define                    CAN1_MB01_ID1  0xffc0343c   /* CAN Controller 1 Mailbox 1 ID1 Register */
-#define                  CAN1_MB02_DATA0  0xffc03440   /* CAN Controller 1 Mailbox 2 Data 0 Register */
-#define                  CAN1_MB02_DATA1  0xffc03444   /* CAN Controller 1 Mailbox 2 Data 1 Register */
-#define                  CAN1_MB02_DATA2  0xffc03448   /* CAN Controller 1 Mailbox 2 Data 2 Register */
-#define                  CAN1_MB02_DATA3  0xffc0344c   /* CAN Controller 1 Mailbox 2 Data 3 Register */
-#define                 CAN1_MB02_LENGTH  0xffc03450   /* CAN Controller 1 Mailbox 2 Length Register */
-#define              CAN1_MB02_TIMESTAMP  0xffc03454   /* CAN Controller 1 Mailbox 2 Timestamp Register */
-#define                    CAN1_MB02_ID0  0xffc03458   /* CAN Controller 1 Mailbox 2 ID0 Register */
-#define                    CAN1_MB02_ID1  0xffc0345c   /* CAN Controller 1 Mailbox 2 ID1 Register */
-#define                  CAN1_MB03_DATA0  0xffc03460   /* CAN Controller 1 Mailbox 3 Data 0 Register */
-#define                  CAN1_MB03_DATA1  0xffc03464   /* CAN Controller 1 Mailbox 3 Data 1 Register */
-#define                  CAN1_MB03_DATA2  0xffc03468   /* CAN Controller 1 Mailbox 3 Data 2 Register */
-#define                  CAN1_MB03_DATA3  0xffc0346c   /* CAN Controller 1 Mailbox 3 Data 3 Register */
-#define                 CAN1_MB03_LENGTH  0xffc03470   /* CAN Controller 1 Mailbox 3 Length Register */
-#define              CAN1_MB03_TIMESTAMP  0xffc03474   /* CAN Controller 1 Mailbox 3 Timestamp Register */
-#define                    CAN1_MB03_ID0  0xffc03478   /* CAN Controller 1 Mailbox 3 ID0 Register */
-#define                    CAN1_MB03_ID1  0xffc0347c   /* CAN Controller 1 Mailbox 3 ID1 Register */
-#define                  CAN1_MB04_DATA0  0xffc03480   /* CAN Controller 1 Mailbox 4 Data 0 Register */
-#define                  CAN1_MB04_DATA1  0xffc03484   /* CAN Controller 1 Mailbox 4 Data 1 Register */
-#define                  CAN1_MB04_DATA2  0xffc03488   /* CAN Controller 1 Mailbox 4 Data 2 Register */
-#define                  CAN1_MB04_DATA3  0xffc0348c   /* CAN Controller 1 Mailbox 4 Data 3 Register */
-#define                 CAN1_MB04_LENGTH  0xffc03490   /* CAN Controller 1 Mailbox 4 Length Register */
-#define              CAN1_MB04_TIMESTAMP  0xffc03494   /* CAN Controller 1 Mailbox 4 Timestamp Register */
-#define                    CAN1_MB04_ID0  0xffc03498   /* CAN Controller 1 Mailbox 4 ID0 Register */
-#define                    CAN1_MB04_ID1  0xffc0349c   /* CAN Controller 1 Mailbox 4 ID1 Register */
-#define                  CAN1_MB05_DATA0  0xffc034a0   /* CAN Controller 1 Mailbox 5 Data 0 Register */
-#define                  CAN1_MB05_DATA1  0xffc034a4   /* CAN Controller 1 Mailbox 5 Data 1 Register */
-#define                  CAN1_MB05_DATA2  0xffc034a8   /* CAN Controller 1 Mailbox 5 Data 2 Register */
-#define                  CAN1_MB05_DATA3  0xffc034ac   /* CAN Controller 1 Mailbox 5 Data 3 Register */
-#define                 CAN1_MB05_LENGTH  0xffc034b0   /* CAN Controller 1 Mailbox 5 Length Register */
-#define              CAN1_MB05_TIMESTAMP  0xffc034b4   /* CAN Controller 1 Mailbox 5 Timestamp Register */
-#define                    CAN1_MB05_ID0  0xffc034b8   /* CAN Controller 1 Mailbox 5 ID0 Register */
-#define                    CAN1_MB05_ID1  0xffc034bc   /* CAN Controller 1 Mailbox 5 ID1 Register */
-#define                  CAN1_MB06_DATA0  0xffc034c0   /* CAN Controller 1 Mailbox 6 Data 0 Register */
-#define                  CAN1_MB06_DATA1  0xffc034c4   /* CAN Controller 1 Mailbox 6 Data 1 Register */
-#define                  CAN1_MB06_DATA2  0xffc034c8   /* CAN Controller 1 Mailbox 6 Data 2 Register */
-#define                  CAN1_MB06_DATA3  0xffc034cc   /* CAN Controller 1 Mailbox 6 Data 3 Register */
-#define                 CAN1_MB06_LENGTH  0xffc034d0   /* CAN Controller 1 Mailbox 6 Length Register */
-#define              CAN1_MB06_TIMESTAMP  0xffc034d4   /* CAN Controller 1 Mailbox 6 Timestamp Register */
-#define                    CAN1_MB06_ID0  0xffc034d8   /* CAN Controller 1 Mailbox 6 ID0 Register */
-#define                    CAN1_MB06_ID1  0xffc034dc   /* CAN Controller 1 Mailbox 6 ID1 Register */
-#define                  CAN1_MB07_DATA0  0xffc034e0   /* CAN Controller 1 Mailbox 7 Data 0 Register */
-#define                  CAN1_MB07_DATA1  0xffc034e4   /* CAN Controller 1 Mailbox 7 Data 1 Register */
-#define                  CAN1_MB07_DATA2  0xffc034e8   /* CAN Controller 1 Mailbox 7 Data 2 Register */
-#define                  CAN1_MB07_DATA3  0xffc034ec   /* CAN Controller 1 Mailbox 7 Data 3 Register */
-#define                 CAN1_MB07_LENGTH  0xffc034f0   /* CAN Controller 1 Mailbox 7 Length Register */
-#define              CAN1_MB07_TIMESTAMP  0xffc034f4   /* CAN Controller 1 Mailbox 7 Timestamp Register */
-#define                    CAN1_MB07_ID0  0xffc034f8   /* CAN Controller 1 Mailbox 7 ID0 Register */
-#define                    CAN1_MB07_ID1  0xffc034fc   /* CAN Controller 1 Mailbox 7 ID1 Register */
-#define                  CAN1_MB08_DATA0  0xffc03500   /* CAN Controller 1 Mailbox 8 Data 0 Register */
-#define                  CAN1_MB08_DATA1  0xffc03504   /* CAN Controller 1 Mailbox 8 Data 1 Register */
-#define                  CAN1_MB08_DATA2  0xffc03508   /* CAN Controller 1 Mailbox 8 Data 2 Register */
-#define                  CAN1_MB08_DATA3  0xffc0350c   /* CAN Controller 1 Mailbox 8 Data 3 Register */
-#define                 CAN1_MB08_LENGTH  0xffc03510   /* CAN Controller 1 Mailbox 8 Length Register */
-#define              CAN1_MB08_TIMESTAMP  0xffc03514   /* CAN Controller 1 Mailbox 8 Timestamp Register */
-#define                    CAN1_MB08_ID0  0xffc03518   /* CAN Controller 1 Mailbox 8 ID0 Register */
-#define                    CAN1_MB08_ID1  0xffc0351c   /* CAN Controller 1 Mailbox 8 ID1 Register */
-#define                  CAN1_MB09_DATA0  0xffc03520   /* CAN Controller 1 Mailbox 9 Data 0 Register */
-#define                  CAN1_MB09_DATA1  0xffc03524   /* CAN Controller 1 Mailbox 9 Data 1 Register */
-#define                  CAN1_MB09_DATA2  0xffc03528   /* CAN Controller 1 Mailbox 9 Data 2 Register */
-#define                  CAN1_MB09_DATA3  0xffc0352c   /* CAN Controller 1 Mailbox 9 Data 3 Register */
-#define                 CAN1_MB09_LENGTH  0xffc03530   /* CAN Controller 1 Mailbox 9 Length Register */
-#define              CAN1_MB09_TIMESTAMP  0xffc03534   /* CAN Controller 1 Mailbox 9 Timestamp Register */
-#define                    CAN1_MB09_ID0  0xffc03538   /* CAN Controller 1 Mailbox 9 ID0 Register */
-#define                    CAN1_MB09_ID1  0xffc0353c   /* CAN Controller 1 Mailbox 9 ID1 Register */
-#define                  CAN1_MB10_DATA0  0xffc03540   /* CAN Controller 1 Mailbox 10 Data 0 Register */
-#define                  CAN1_MB10_DATA1  0xffc03544   /* CAN Controller 1 Mailbox 10 Data 1 Register */
-#define                  CAN1_MB10_DATA2  0xffc03548   /* CAN Controller 1 Mailbox 10 Data 2 Register */
-#define                  CAN1_MB10_DATA3  0xffc0354c   /* CAN Controller 1 Mailbox 10 Data 3 Register */
-#define                 CAN1_MB10_LENGTH  0xffc03550   /* CAN Controller 1 Mailbox 10 Length Register */
-#define              CAN1_MB10_TIMESTAMP  0xffc03554   /* CAN Controller 1 Mailbox 10 Timestamp Register */
-#define                    CAN1_MB10_ID0  0xffc03558   /* CAN Controller 1 Mailbox 10 ID0 Register */
-#define                    CAN1_MB10_ID1  0xffc0355c   /* CAN Controller 1 Mailbox 10 ID1 Register */
-#define                  CAN1_MB11_DATA0  0xffc03560   /* CAN Controller 1 Mailbox 11 Data 0 Register */
-#define                  CAN1_MB11_DATA1  0xffc03564   /* CAN Controller 1 Mailbox 11 Data 1 Register */
-#define                  CAN1_MB11_DATA2  0xffc03568   /* CAN Controller 1 Mailbox 11 Data 2 Register */
-#define                  CAN1_MB11_DATA3  0xffc0356c   /* CAN Controller 1 Mailbox 11 Data 3 Register */
-#define                 CAN1_MB11_LENGTH  0xffc03570   /* CAN Controller 1 Mailbox 11 Length Register */
-#define              CAN1_MB11_TIMESTAMP  0xffc03574   /* CAN Controller 1 Mailbox 11 Timestamp Register */
-#define                    CAN1_MB11_ID0  0xffc03578   /* CAN Controller 1 Mailbox 11 ID0 Register */
-#define                    CAN1_MB11_ID1  0xffc0357c   /* CAN Controller 1 Mailbox 11 ID1 Register */
-#define                  CAN1_MB12_DATA0  0xffc03580   /* CAN Controller 1 Mailbox 12 Data 0 Register */
-#define                  CAN1_MB12_DATA1  0xffc03584   /* CAN Controller 1 Mailbox 12 Data 1 Register */
-#define                  CAN1_MB12_DATA2  0xffc03588   /* CAN Controller 1 Mailbox 12 Data 2 Register */
-#define                  CAN1_MB12_DATA3  0xffc0358c   /* CAN Controller 1 Mailbox 12 Data 3 Register */
-#define                 CAN1_MB12_LENGTH  0xffc03590   /* CAN Controller 1 Mailbox 12 Length Register */
-#define              CAN1_MB12_TIMESTAMP  0xffc03594   /* CAN Controller 1 Mailbox 12 Timestamp Register */
-#define                    CAN1_MB12_ID0  0xffc03598   /* CAN Controller 1 Mailbox 12 ID0 Register */
-#define                    CAN1_MB12_ID1  0xffc0359c   /* CAN Controller 1 Mailbox 12 ID1 Register */
-#define                  CAN1_MB13_DATA0  0xffc035a0   /* CAN Controller 1 Mailbox 13 Data 0 Register */
-#define                  CAN1_MB13_DATA1  0xffc035a4   /* CAN Controller 1 Mailbox 13 Data 1 Register */
-#define                  CAN1_MB13_DATA2  0xffc035a8   /* CAN Controller 1 Mailbox 13 Data 2 Register */
-#define                  CAN1_MB13_DATA3  0xffc035ac   /* CAN Controller 1 Mailbox 13 Data 3 Register */
-#define                 CAN1_MB13_LENGTH  0xffc035b0   /* CAN Controller 1 Mailbox 13 Length Register */
-#define              CAN1_MB13_TIMESTAMP  0xffc035b4   /* CAN Controller 1 Mailbox 13 Timestamp Register */
-#define                    CAN1_MB13_ID0  0xffc035b8   /* CAN Controller 1 Mailbox 13 ID0 Register */
-#define                    CAN1_MB13_ID1  0xffc035bc   /* CAN Controller 1 Mailbox 13 ID1 Register */
-#define                  CAN1_MB14_DATA0  0xffc035c0   /* CAN Controller 1 Mailbox 14 Data 0 Register */
-#define                  CAN1_MB14_DATA1  0xffc035c4   /* CAN Controller 1 Mailbox 14 Data 1 Register */
-#define                  CAN1_MB14_DATA2  0xffc035c8   /* CAN Controller 1 Mailbox 14 Data 2 Register */
-#define                  CAN1_MB14_DATA3  0xffc035cc   /* CAN Controller 1 Mailbox 14 Data 3 Register */
-#define                 CAN1_MB14_LENGTH  0xffc035d0   /* CAN Controller 1 Mailbox 14 Length Register */
-#define              CAN1_MB14_TIMESTAMP  0xffc035d4   /* CAN Controller 1 Mailbox 14 Timestamp Register */
-#define                    CAN1_MB14_ID0  0xffc035d8   /* CAN Controller 1 Mailbox 14 ID0 Register */
-#define                    CAN1_MB14_ID1  0xffc035dc   /* CAN Controller 1 Mailbox 14 ID1 Register */
-#define                  CAN1_MB15_DATA0  0xffc035e0   /* CAN Controller 1 Mailbox 15 Data 0 Register */
-#define                  CAN1_MB15_DATA1  0xffc035e4   /* CAN Controller 1 Mailbox 15 Data 1 Register */
-#define                  CAN1_MB15_DATA2  0xffc035e8   /* CAN Controller 1 Mailbox 15 Data 2 Register */
-#define                  CAN1_MB15_DATA3  0xffc035ec   /* CAN Controller 1 Mailbox 15 Data 3 Register */
-#define                 CAN1_MB15_LENGTH  0xffc035f0   /* CAN Controller 1 Mailbox 15 Length Register */
-#define              CAN1_MB15_TIMESTAMP  0xffc035f4   /* CAN Controller 1 Mailbox 15 Timestamp Register */
-#define                    CAN1_MB15_ID0  0xffc035f8   /* CAN Controller 1 Mailbox 15 ID0 Register */
-#define                    CAN1_MB15_ID1  0xffc035fc   /* CAN Controller 1 Mailbox 15 ID1 Register */
-
-/* CAN Controller 1 Mailbox Data Registers */
-
-#define                  CAN1_MB16_DATA0  0xffc03600   /* CAN Controller 1 Mailbox 16 Data 0 Register */
-#define                  CAN1_MB16_DATA1  0xffc03604   /* CAN Controller 1 Mailbox 16 Data 1 Register */
-#define                  CAN1_MB16_DATA2  0xffc03608   /* CAN Controller 1 Mailbox 16 Data 2 Register */
-#define                  CAN1_MB16_DATA3  0xffc0360c   /* CAN Controller 1 Mailbox 16 Data 3 Register */
-#define                 CAN1_MB16_LENGTH  0xffc03610   /* CAN Controller 1 Mailbox 16 Length Register */
-#define              CAN1_MB16_TIMESTAMP  0xffc03614   /* CAN Controller 1 Mailbox 16 Timestamp Register */
-#define                    CAN1_MB16_ID0  0xffc03618   /* CAN Controller 1 Mailbox 16 ID0 Register */
-#define                    CAN1_MB16_ID1  0xffc0361c   /* CAN Controller 1 Mailbox 16 ID1 Register */
-#define                  CAN1_MB17_DATA0  0xffc03620   /* CAN Controller 1 Mailbox 17 Data 0 Register */
-#define                  CAN1_MB17_DATA1  0xffc03624   /* CAN Controller 1 Mailbox 17 Data 1 Register */
-#define                  CAN1_MB17_DATA2  0xffc03628   /* CAN Controller 1 Mailbox 17 Data 2 Register */
-#define                  CAN1_MB17_DATA3  0xffc0362c   /* CAN Controller 1 Mailbox 17 Data 3 Register */
-#define                 CAN1_MB17_LENGTH  0xffc03630   /* CAN Controller 1 Mailbox 17 Length Register */
-#define              CAN1_MB17_TIMESTAMP  0xffc03634   /* CAN Controller 1 Mailbox 17 Timestamp Register */
-#define                    CAN1_MB17_ID0  0xffc03638   /* CAN Controller 1 Mailbox 17 ID0 Register */
-#define                    CAN1_MB17_ID1  0xffc0363c   /* CAN Controller 1 Mailbox 17 ID1 Register */
-#define                  CAN1_MB18_DATA0  0xffc03640   /* CAN Controller 1 Mailbox 18 Data 0 Register */
-#define                  CAN1_MB18_DATA1  0xffc03644   /* CAN Controller 1 Mailbox 18 Data 1 Register */
-#define                  CAN1_MB18_DATA2  0xffc03648   /* CAN Controller 1 Mailbox 18 Data 2 Register */
-#define                  CAN1_MB18_DATA3  0xffc0364c   /* CAN Controller 1 Mailbox 18 Data 3 Register */
-#define                 CAN1_MB18_LENGTH  0xffc03650   /* CAN Controller 1 Mailbox 18 Length Register */
-#define              CAN1_MB18_TIMESTAMP  0xffc03654   /* CAN Controller 1 Mailbox 18 Timestamp Register */
-#define                    CAN1_MB18_ID0  0xffc03658   /* CAN Controller 1 Mailbox 18 ID0 Register */
-#define                    CAN1_MB18_ID1  0xffc0365c   /* CAN Controller 1 Mailbox 18 ID1 Register */
-#define                  CAN1_MB19_DATA0  0xffc03660   /* CAN Controller 1 Mailbox 19 Data 0 Register */
-#define                  CAN1_MB19_DATA1  0xffc03664   /* CAN Controller 1 Mailbox 19 Data 1 Register */
-#define                  CAN1_MB19_DATA2  0xffc03668   /* CAN Controller 1 Mailbox 19 Data 2 Register */
-#define                  CAN1_MB19_DATA3  0xffc0366c   /* CAN Controller 1 Mailbox 19 Data 3 Register */
-#define                 CAN1_MB19_LENGTH  0xffc03670   /* CAN Controller 1 Mailbox 19 Length Register */
-#define              CAN1_MB19_TIMESTAMP  0xffc03674   /* CAN Controller 1 Mailbox 19 Timestamp Register */
-#define                    CAN1_MB19_ID0  0xffc03678   /* CAN Controller 1 Mailbox 19 ID0 Register */
-#define                    CAN1_MB19_ID1  0xffc0367c   /* CAN Controller 1 Mailbox 19 ID1 Register */
-#define                  CAN1_MB20_DATA0  0xffc03680   /* CAN Controller 1 Mailbox 20 Data 0 Register */
-#define                  CAN1_MB20_DATA1  0xffc03684   /* CAN Controller 1 Mailbox 20 Data 1 Register */
-#define                  CAN1_MB20_DATA2  0xffc03688   /* CAN Controller 1 Mailbox 20 Data 2 Register */
-#define                  CAN1_MB20_DATA3  0xffc0368c   /* CAN Controller 1 Mailbox 20 Data 3 Register */
-#define                 CAN1_MB20_LENGTH  0xffc03690   /* CAN Controller 1 Mailbox 20 Length Register */
-#define              CAN1_MB20_TIMESTAMP  0xffc03694   /* CAN Controller 1 Mailbox 20 Timestamp Register */
-#define                    CAN1_MB20_ID0  0xffc03698   /* CAN Controller 1 Mailbox 20 ID0 Register */
-#define                    CAN1_MB20_ID1  0xffc0369c   /* CAN Controller 1 Mailbox 20 ID1 Register */
-#define                  CAN1_MB21_DATA0  0xffc036a0   /* CAN Controller 1 Mailbox 21 Data 0 Register */
-#define                  CAN1_MB21_DATA1  0xffc036a4   /* CAN Controller 1 Mailbox 21 Data 1 Register */
-#define                  CAN1_MB21_DATA2  0xffc036a8   /* CAN Controller 1 Mailbox 21 Data 2 Register */
-#define                  CAN1_MB21_DATA3  0xffc036ac   /* CAN Controller 1 Mailbox 21 Data 3 Register */
-#define                 CAN1_MB21_LENGTH  0xffc036b0   /* CAN Controller 1 Mailbox 21 Length Register */
-#define              CAN1_MB21_TIMESTAMP  0xffc036b4   /* CAN Controller 1 Mailbox 21 Timestamp Register */
-#define                    CAN1_MB21_ID0  0xffc036b8   /* CAN Controller 1 Mailbox 21 ID0 Register */
-#define                    CAN1_MB21_ID1  0xffc036bc   /* CAN Controller 1 Mailbox 21 ID1 Register */
-#define                  CAN1_MB22_DATA0  0xffc036c0   /* CAN Controller 1 Mailbox 22 Data 0 Register */
-#define                  CAN1_MB22_DATA1  0xffc036c4   /* CAN Controller 1 Mailbox 22 Data 1 Register */
-#define                  CAN1_MB22_DATA2  0xffc036c8   /* CAN Controller 1 Mailbox 22 Data 2 Register */
-#define                  CAN1_MB22_DATA3  0xffc036cc   /* CAN Controller 1 Mailbox 22 Data 3 Register */
-#define                 CAN1_MB22_LENGTH  0xffc036d0   /* CAN Controller 1 Mailbox 22 Length Register */
-#define              CAN1_MB22_TIMESTAMP  0xffc036d4   /* CAN Controller 1 Mailbox 22 Timestamp Register */
-#define                    CAN1_MB22_ID0  0xffc036d8   /* CAN Controller 1 Mailbox 22 ID0 Register */
-#define                    CAN1_MB22_ID1  0xffc036dc   /* CAN Controller 1 Mailbox 22 ID1 Register */
-#define                  CAN1_MB23_DATA0  0xffc036e0   /* CAN Controller 1 Mailbox 23 Data 0 Register */
-#define                  CAN1_MB23_DATA1  0xffc036e4   /* CAN Controller 1 Mailbox 23 Data 1 Register */
-#define                  CAN1_MB23_DATA2  0xffc036e8   /* CAN Controller 1 Mailbox 23 Data 2 Register */
-#define                  CAN1_MB23_DATA3  0xffc036ec   /* CAN Controller 1 Mailbox 23 Data 3 Register */
-#define                 CAN1_MB23_LENGTH  0xffc036f0   /* CAN Controller 1 Mailbox 23 Length Register */
-#define              CAN1_MB23_TIMESTAMP  0xffc036f4   /* CAN Controller 1 Mailbox 23 Timestamp Register */
-#define                    CAN1_MB23_ID0  0xffc036f8   /* CAN Controller 1 Mailbox 23 ID0 Register */
-#define                    CAN1_MB23_ID1  0xffc036fc   /* CAN Controller 1 Mailbox 23 ID1 Register */
-#define                  CAN1_MB24_DATA0  0xffc03700   /* CAN Controller 1 Mailbox 24 Data 0 Register */
-#define                  CAN1_MB24_DATA1  0xffc03704   /* CAN Controller 1 Mailbox 24 Data 1 Register */
-#define                  CAN1_MB24_DATA2  0xffc03708   /* CAN Controller 1 Mailbox 24 Data 2 Register */
-#define                  CAN1_MB24_DATA3  0xffc0370c   /* CAN Controller 1 Mailbox 24 Data 3 Register */
-#define                 CAN1_MB24_LENGTH  0xffc03710   /* CAN Controller 1 Mailbox 24 Length Register */
-#define              CAN1_MB24_TIMESTAMP  0xffc03714   /* CAN Controller 1 Mailbox 24 Timestamp Register */
-#define                    CAN1_MB24_ID0  0xffc03718   /* CAN Controller 1 Mailbox 24 ID0 Register */
-#define                    CAN1_MB24_ID1  0xffc0371c   /* CAN Controller 1 Mailbox 24 ID1 Register */
-#define                  CAN1_MB25_DATA0  0xffc03720   /* CAN Controller 1 Mailbox 25 Data 0 Register */
-#define                  CAN1_MB25_DATA1  0xffc03724   /* CAN Controller 1 Mailbox 25 Data 1 Register */
-#define                  CAN1_MB25_DATA2  0xffc03728   /* CAN Controller 1 Mailbox 25 Data 2 Register */
-#define                  CAN1_MB25_DATA3  0xffc0372c   /* CAN Controller 1 Mailbox 25 Data 3 Register */
-#define                 CAN1_MB25_LENGTH  0xffc03730   /* CAN Controller 1 Mailbox 25 Length Register */
-#define              CAN1_MB25_TIMESTAMP  0xffc03734   /* CAN Controller 1 Mailbox 25 Timestamp Register */
-#define                    CAN1_MB25_ID0  0xffc03738   /* CAN Controller 1 Mailbox 25 ID0 Register */
-#define                    CAN1_MB25_ID1  0xffc0373c   /* CAN Controller 1 Mailbox 25 ID1 Register */
-#define                  CAN1_MB26_DATA0  0xffc03740   /* CAN Controller 1 Mailbox 26 Data 0 Register */
-#define                  CAN1_MB26_DATA1  0xffc03744   /* CAN Controller 1 Mailbox 26 Data 1 Register */
-#define                  CAN1_MB26_DATA2  0xffc03748   /* CAN Controller 1 Mailbox 26 Data 2 Register */
-#define                  CAN1_MB26_DATA3  0xffc0374c   /* CAN Controller 1 Mailbox 26 Data 3 Register */
-#define                 CAN1_MB26_LENGTH  0xffc03750   /* CAN Controller 1 Mailbox 26 Length Register */
-#define              CAN1_MB26_TIMESTAMP  0xffc03754   /* CAN Controller 1 Mailbox 26 Timestamp Register */
-#define                    CAN1_MB26_ID0  0xffc03758   /* CAN Controller 1 Mailbox 26 ID0 Register */
-#define                    CAN1_MB26_ID1  0xffc0375c   /* CAN Controller 1 Mailbox 26 ID1 Register */
-#define                  CAN1_MB27_DATA0  0xffc03760   /* CAN Controller 1 Mailbox 27 Data 0 Register */
-#define                  CAN1_MB27_DATA1  0xffc03764   /* CAN Controller 1 Mailbox 27 Data 1 Register */
-#define                  CAN1_MB27_DATA2  0xffc03768   /* CAN Controller 1 Mailbox 27 Data 2 Register */
-#define                  CAN1_MB27_DATA3  0xffc0376c   /* CAN Controller 1 Mailbox 27 Data 3 Register */
-#define                 CAN1_MB27_LENGTH  0xffc03770   /* CAN Controller 1 Mailbox 27 Length Register */
-#define              CAN1_MB27_TIMESTAMP  0xffc03774   /* CAN Controller 1 Mailbox 27 Timestamp Register */
-#define                    CAN1_MB27_ID0  0xffc03778   /* CAN Controller 1 Mailbox 27 ID0 Register */
-#define                    CAN1_MB27_ID1  0xffc0377c   /* CAN Controller 1 Mailbox 27 ID1 Register */
-#define                  CAN1_MB28_DATA0  0xffc03780   /* CAN Controller 1 Mailbox 28 Data 0 Register */
-#define                  CAN1_MB28_DATA1  0xffc03784   /* CAN Controller 1 Mailbox 28 Data 1 Register */
-#define                  CAN1_MB28_DATA2  0xffc03788   /* CAN Controller 1 Mailbox 28 Data 2 Register */
-#define                  CAN1_MB28_DATA3  0xffc0378c   /* CAN Controller 1 Mailbox 28 Data 3 Register */
-#define                 CAN1_MB28_LENGTH  0xffc03790   /* CAN Controller 1 Mailbox 28 Length Register */
-#define              CAN1_MB28_TIMESTAMP  0xffc03794   /* CAN Controller 1 Mailbox 28 Timestamp Register */
-#define                    CAN1_MB28_ID0  0xffc03798   /* CAN Controller 1 Mailbox 28 ID0 Register */
-#define                    CAN1_MB28_ID1  0xffc0379c   /* CAN Controller 1 Mailbox 28 ID1 Register */
-#define                  CAN1_MB29_DATA0  0xffc037a0   /* CAN Controller 1 Mailbox 29 Data 0 Register */
-#define                  CAN1_MB29_DATA1  0xffc037a4   /* CAN Controller 1 Mailbox 29 Data 1 Register */
-#define                  CAN1_MB29_DATA2  0xffc037a8   /* CAN Controller 1 Mailbox 29 Data 2 Register */
-#define                  CAN1_MB29_DATA3  0xffc037ac   /* CAN Controller 1 Mailbox 29 Data 3 Register */
-#define                 CAN1_MB29_LENGTH  0xffc037b0   /* CAN Controller 1 Mailbox 29 Length Register */
-#define              CAN1_MB29_TIMESTAMP  0xffc037b4   /* CAN Controller 1 Mailbox 29 Timestamp Register */
-#define                    CAN1_MB29_ID0  0xffc037b8   /* CAN Controller 1 Mailbox 29 ID0 Register */
-#define                    CAN1_MB29_ID1  0xffc037bc   /* CAN Controller 1 Mailbox 29 ID1 Register */
-#define                  CAN1_MB30_DATA0  0xffc037c0   /* CAN Controller 1 Mailbox 30 Data 0 Register */
-#define                  CAN1_MB30_DATA1  0xffc037c4   /* CAN Controller 1 Mailbox 30 Data 1 Register */
-#define                  CAN1_MB30_DATA2  0xffc037c8   /* CAN Controller 1 Mailbox 30 Data 2 Register */
-#define                  CAN1_MB30_DATA3  0xffc037cc   /* CAN Controller 1 Mailbox 30 Data 3 Register */
-#define                 CAN1_MB30_LENGTH  0xffc037d0   /* CAN Controller 1 Mailbox 30 Length Register */
-#define              CAN1_MB30_TIMESTAMP  0xffc037d4   /* CAN Controller 1 Mailbox 30 Timestamp Register */
-#define                    CAN1_MB30_ID0  0xffc037d8   /* CAN Controller 1 Mailbox 30 ID0 Register */
-#define                    CAN1_MB30_ID1  0xffc037dc   /* CAN Controller 1 Mailbox 30 ID1 Register */
-#define                  CAN1_MB31_DATA0  0xffc037e0   /* CAN Controller 1 Mailbox 31 Data 0 Register */
-#define                  CAN1_MB31_DATA1  0xffc037e4   /* CAN Controller 1 Mailbox 31 Data 1 Register */
-#define                  CAN1_MB31_DATA2  0xffc037e8   /* CAN Controller 1 Mailbox 31 Data 2 Register */
-#define                  CAN1_MB31_DATA3  0xffc037ec   /* CAN Controller 1 Mailbox 31 Data 3 Register */
-#define                 CAN1_MB31_LENGTH  0xffc037f0   /* CAN Controller 1 Mailbox 31 Length Register */
-#define              CAN1_MB31_TIMESTAMP  0xffc037f4   /* CAN Controller 1 Mailbox 31 Timestamp Register */
-#define                    CAN1_MB31_ID0  0xffc037f8   /* CAN Controller 1 Mailbox 31 ID0 Register */
-#define                    CAN1_MB31_ID1  0xffc037fc   /* CAN Controller 1 Mailbox 31 ID1 Register */
-
-/* ATAPI Registers */
-
-#define                    ATAPI_CONTROL  0xffc03800   /* ATAPI Control Register */
-#define                     ATAPI_STATUS  0xffc03804   /* ATAPI Status Register */
-#define                   ATAPI_DEV_ADDR  0xffc03808   /* ATAPI Device Register Address */
-#define                  ATAPI_DEV_TXBUF  0xffc0380c   /* ATAPI Device Register Write Data */
-#define                  ATAPI_DEV_RXBUF  0xffc03810   /* ATAPI Device Register Read Data */
-#define                   ATAPI_INT_MASK  0xffc03814   /* ATAPI Interrupt Mask Register */
-#define                 ATAPI_INT_STATUS  0xffc03818   /* ATAPI Interrupt Status Register */
-#define                   ATAPI_XFER_LEN  0xffc0381c   /* ATAPI Length of Transfer */
-#define                ATAPI_LINE_STATUS  0xffc03820   /* ATAPI Line Status */
-#define                   ATAPI_SM_STATE  0xffc03824   /* ATAPI State Machine Status */
-#define                  ATAPI_TERMINATE  0xffc03828   /* ATAPI Host Terminate */
-#define                 ATAPI_PIO_TFRCNT  0xffc0382c   /* ATAPI PIO mode transfer count */
-#define                 ATAPI_DMA_TFRCNT  0xffc03830   /* ATAPI DMA mode transfer count */
-#define               ATAPI_UMAIN_TFRCNT  0xffc03834   /* ATAPI UDMAIN transfer count */
-#define             ATAPI_UDMAOUT_TFRCNT  0xffc03838   /* ATAPI UDMAOUT transfer count */
-#define                  ATAPI_REG_TIM_0  0xffc03840   /* ATAPI Register Transfer Timing 0 */
-#define                  ATAPI_PIO_TIM_0  0xffc03844   /* ATAPI PIO Timing 0 Register */
-#define                  ATAPI_PIO_TIM_1  0xffc03848   /* ATAPI PIO Timing 1 Register */
-#define                ATAPI_MULTI_TIM_0  0xffc03850   /* ATAPI Multi-DMA Timing 0 Register */
-#define                ATAPI_MULTI_TIM_1  0xffc03854   /* ATAPI Multi-DMA Timing 1 Register */
-#define                ATAPI_MULTI_TIM_2  0xffc03858   /* ATAPI Multi-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_0  0xffc03860   /* ATAPI Ultra-DMA Timing 0 Register */
-#define                ATAPI_ULTRA_TIM_1  0xffc03864   /* ATAPI Ultra-DMA Timing 1 Register */
-#define                ATAPI_ULTRA_TIM_2  0xffc03868   /* ATAPI Ultra-DMA Timing 2 Register */
-#define                ATAPI_ULTRA_TIM_3  0xffc0386c   /* ATAPI Ultra-DMA Timing 3 Register */
-
-/* SDH Registers */
-
-#define                      SDH_PWR_CTL  0xffc03900   /* SDH Power Control */
-#define                      SDH_CLK_CTL  0xffc03904   /* SDH Clock Control */
-#define                     SDH_ARGUMENT  0xffc03908   /* SDH Argument */
-#define                      SDH_COMMAND  0xffc0390c   /* SDH Command */
-#define                     SDH_RESP_CMD  0xffc03910   /* SDH Response Command */
-#define                    SDH_RESPONSE0  0xffc03914   /* SDH Response0 */
-#define                    SDH_RESPONSE1  0xffc03918   /* SDH Response1 */
-#define                    SDH_RESPONSE2  0xffc0391c   /* SDH Response2 */
-#define                    SDH_RESPONSE3  0xffc03920   /* SDH Response3 */
-#define                   SDH_DATA_TIMER  0xffc03924   /* SDH Data Timer */
-#define                    SDH_DATA_LGTH  0xffc03928   /* SDH Data Length */
-#define                     SDH_DATA_CTL  0xffc0392c   /* SDH Data Control */
-#define                     SDH_DATA_CNT  0xffc03930   /* SDH Data Counter */
-#define                       SDH_STATUS  0xffc03934   /* SDH Status */
-#define                   SDH_STATUS_CLR  0xffc03938   /* SDH Status Clear */
-#define                        SDH_MASK0  0xffc0393c   /* SDH Interrupt0 Mask */
-#define                        SDH_MASK1  0xffc03940   /* SDH Interrupt1 Mask */
-#define                     SDH_FIFO_CNT  0xffc03948   /* SDH FIFO Counter */
-#define                         SDH_FIFO  0xffc03980   /* SDH Data FIFO */
-#define                     SDH_E_STATUS  0xffc039c0   /* SDH Exception Status */
-#define                       SDH_E_MASK  0xffc039c4   /* SDH Exception Mask */
-#define                          SDH_CFG  0xffc039c8   /* SDH Configuration */
-#define                   SDH_RD_WAIT_EN  0xffc039cc   /* SDH Read Wait Enable */
-#define                         SDH_PID0  0xffc039d0   /* SDH Peripheral Identification0 */
-#define                         SDH_PID1  0xffc039d4   /* SDH Peripheral Identification1 */
-#define                         SDH_PID2  0xffc039d8   /* SDH Peripheral Identification2 */
-#define                         SDH_PID3  0xffc039dc   /* SDH Peripheral Identification3 */
-#define                         SDH_PID4  0xffc039e0   /* SDH Peripheral Identification4 */
-#define                         SDH_PID5  0xffc039e4   /* SDH Peripheral Identification5 */
-#define                         SDH_PID6  0xffc039e8   /* SDH Peripheral Identification6 */
-#define                         SDH_PID7  0xffc039ec   /* SDH Peripheral Identification7 */
-
-/* HOST Port Registers */
-
-#define                     HOST_CONTROL  0xffc03a00   /* HOST Control Register */
-#define                      HOST_STATUS  0xffc03a04   /* HOST Status Register */
-#define                     HOST_TIMEOUT  0xffc03a08   /* HOST Acknowledge Mode Timeout Register */
-
-/* USB Control Registers */
-
-#define                        USB_FADDR  0xffc03c00   /* Function address register */
-#define                        USB_POWER  0xffc03c04   /* Power management register */
-#define                       USB_INTRTX  0xffc03c08   /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define                       USB_INTRRX  0xffc03c0c   /* Interrupt register for Rx endpoints 1 to 7 */
-#define                      USB_INTRTXE  0xffc03c10   /* Interrupt enable register for IntrTx */
-#define                      USB_INTRRXE  0xffc03c14   /* Interrupt enable register for IntrRx */
-#define                      USB_INTRUSB  0xffc03c18   /* Interrupt register for common USB interrupts */
-#define                     USB_INTRUSBE  0xffc03c1c   /* Interrupt enable register for IntrUSB */
-#define                        USB_FRAME  0xffc03c20   /* USB frame number */
-#define                        USB_INDEX  0xffc03c24   /* Index register for selecting the indexed endpoint registers */
-#define                     USB_TESTMODE  0xffc03c28   /* Enabled USB 20 test modes */
-#define                     USB_GLOBINTR  0xffc03c2c   /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define                   USB_GLOBAL_CTL  0xffc03c30   /* Global Clock Control for the core */
-
-/* USB Packet Control Registers */
-
-#define                USB_TX_MAX_PACKET  0xffc03c40   /* Maximum packet size for Host Tx endpoint */
-#define                         USB_CSR0  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                        USB_TXCSR  0xffc03c44   /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define                USB_RX_MAX_PACKET  0xffc03c48   /* Maximum packet size for Host Rx endpoint */
-#define                        USB_RXCSR  0xffc03c4c   /* Control Status register for Host Rx endpoint */
-#define                       USB_COUNT0  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                      USB_RXCOUNT  0xffc03c50   /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define                       USB_TXTYPE  0xffc03c54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define                    USB_NAKLIMIT0  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                   USB_TXINTERVAL  0xffc03c58   /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define                       USB_RXTYPE  0xffc03c5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define                   USB_RXINTERVAL  0xffc03c60   /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define                      USB_TXCOUNT  0xffc03c68   /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* USB Endpoint FIFO Registers */
-
-#define                     USB_EP0_FIFO  0xffc03c80   /* Endpoint 0 FIFO */
-#define                     USB_EP1_FIFO  0xffc03c88   /* Endpoint 1 FIFO */
-#define                     USB_EP2_FIFO  0xffc03c90   /* Endpoint 2 FIFO */
-#define                     USB_EP3_FIFO  0xffc03c98   /* Endpoint 3 FIFO */
-#define                     USB_EP4_FIFO  0xffc03ca0   /* Endpoint 4 FIFO */
-#define                     USB_EP5_FIFO  0xffc03ca8   /* Endpoint 5 FIFO */
-#define                     USB_EP6_FIFO  0xffc03cb0   /* Endpoint 6 FIFO */
-#define                     USB_EP7_FIFO  0xffc03cb8   /* Endpoint 7 FIFO */
-
-/* USB OTG Control Registers */
-
-#define                  USB_OTG_DEV_CTL  0xffc03d00   /* OTG Device Control Register */
-#define                 USB_OTG_VBUS_IRQ  0xffc03d04   /* OTG VBUS Control Interrupts */
-#define                USB_OTG_VBUS_MASK  0xffc03d08   /* VBUS Control Interrupt Enable */
-
-/* USB Phy Control Registers */
-
-#define                     USB_LINKINFO  0xffc03d48   /* Enables programming of some PHY-side delays */
-#define                        USB_VPLEN  0xffc03d4c   /* Determines duration of VBUS pulse for VBUS charging */
-#define                      USB_HS_EOF1  0xffc03d50   /* Time buffer for High-Speed transactions */
-#define                      USB_FS_EOF1  0xffc03d54   /* Time buffer for Full-Speed transactions */
-#define                      USB_LS_EOF1  0xffc03d58   /* Time buffer for Low-Speed transactions */
-
-/* (APHY_CNTRL is for ADI usage only) */
-
-#define                   USB_APHY_CNTRL  0xffc03de0   /* Register that increases visibility of Analog PHY */
-
-/* (APHY_CALIB is for ADI usage only) */
-
-#define                   USB_APHY_CALIB  0xffc03de4   /* Register used to set some calibration values */
-#define                  USB_APHY_CNTRL2  0xffc03de8   /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-
-/* (PHY_TEST is for ADI usage only) */
-
-#define                     USB_PHY_TEST  0xffc03dec   /* Used for reducing simulation time and simplifies FIFO testability */
-#define                  USB_PLLOSC_CTRL  0xffc03df0   /* Used to program different parameters for USB PLL and Oscillator */
-#define                   USB_SRP_CLKDIV  0xffc03df4   /* Used to program clock divide value for the clock fed to the SRP detection logic */
-
-/* USB Endpoint 0 Control Registers */
-
-#define                USB_EP_NI0_TXMAXP  0xffc03e00   /* Maximum packet size for Host Tx endpoint0 */
-#define                 USB_EP_NI0_TXCSR  0xffc03e04   /* Control Status register for endpoint 0 */
-#define                USB_EP_NI0_RXMAXP  0xffc03e08   /* Maximum packet size for Host Rx endpoint0 */
-#define                 USB_EP_NI0_RXCSR  0xffc03e0c   /* Control Status register for Host Rx endpoint0 */
-#define               USB_EP_NI0_RXCOUNT  0xffc03e10   /* Number of bytes received in endpoint 0 FIFO */
-#define                USB_EP_NI0_TXTYPE  0xffc03e14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define            USB_EP_NI0_TXINTERVAL  0xffc03e18   /* Sets the NAK response timeout on Endpoint 0 */
-#define                USB_EP_NI0_RXTYPE  0xffc03e1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define            USB_EP_NI0_RXINTERVAL  0xffc03e20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-
-/* USB Endpoint 1 Control Registers */
-
-#define               USB_EP_NI0_TXCOUNT  0xffc03e28   /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define                USB_EP_NI1_TXMAXP  0xffc03e40   /* Maximum packet size for Host Tx endpoint1 */
-#define                 USB_EP_NI1_TXCSR  0xffc03e44   /* Control Status register for endpoint1 */
-#define                USB_EP_NI1_RXMAXP  0xffc03e48   /* Maximum packet size for Host Rx endpoint1 */
-#define                 USB_EP_NI1_RXCSR  0xffc03e4c   /* Control Status register for Host Rx endpoint1 */
-#define               USB_EP_NI1_RXCOUNT  0xffc03e50   /* Number of bytes received in endpoint1 FIFO */
-#define                USB_EP_NI1_TXTYPE  0xffc03e54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define            USB_EP_NI1_TXINTERVAL  0xffc03e58   /* Sets the NAK response timeout on Endpoint1 */
-#define                USB_EP_NI1_RXTYPE  0xffc03e5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define            USB_EP_NI1_RXINTERVAL  0xffc03e60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-
-/* USB Endpoint 2 Control Registers */
-
-#define               USB_EP_NI1_TXCOUNT  0xffc03e68   /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define                USB_EP_NI2_TXMAXP  0xffc03e80   /* Maximum packet size for Host Tx endpoint2 */
-#define                 USB_EP_NI2_TXCSR  0xffc03e84   /* Control Status register for endpoint2 */
-#define                USB_EP_NI2_RXMAXP  0xffc03e88   /* Maximum packet size for Host Rx endpoint2 */
-#define                 USB_EP_NI2_RXCSR  0xffc03e8c   /* Control Status register for Host Rx endpoint2 */
-#define               USB_EP_NI2_RXCOUNT  0xffc03e90   /* Number of bytes received in endpoint2 FIFO */
-#define                USB_EP_NI2_TXTYPE  0xffc03e94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define            USB_EP_NI2_TXINTERVAL  0xffc03e98   /* Sets the NAK response timeout on Endpoint2 */
-#define                USB_EP_NI2_RXTYPE  0xffc03e9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define            USB_EP_NI2_RXINTERVAL  0xffc03ea0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-
-/* USB Endpoint 3 Control Registers */
-
-#define               USB_EP_NI2_TXCOUNT  0xffc03ea8   /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define                USB_EP_NI3_TXMAXP  0xffc03ec0   /* Maximum packet size for Host Tx endpoint3 */
-#define                 USB_EP_NI3_TXCSR  0xffc03ec4   /* Control Status register for endpoint3 */
-#define                USB_EP_NI3_RXMAXP  0xffc03ec8   /* Maximum packet size for Host Rx endpoint3 */
-#define                 USB_EP_NI3_RXCSR  0xffc03ecc   /* Control Status register for Host Rx endpoint3 */
-#define               USB_EP_NI3_RXCOUNT  0xffc03ed0   /* Number of bytes received in endpoint3 FIFO */
-#define                USB_EP_NI3_TXTYPE  0xffc03ed4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define            USB_EP_NI3_TXINTERVAL  0xffc03ed8   /* Sets the NAK response timeout on Endpoint3 */
-#define                USB_EP_NI3_RXTYPE  0xffc03edc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define            USB_EP_NI3_RXINTERVAL  0xffc03ee0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-
-/* USB Endpoint 4 Control Registers */
-
-#define               USB_EP_NI3_TXCOUNT  0xffc03ee8   /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define                USB_EP_NI4_TXMAXP  0xffc03f00   /* Maximum packet size for Host Tx endpoint4 */
-#define                 USB_EP_NI4_TXCSR  0xffc03f04   /* Control Status register for endpoint4 */
-#define                USB_EP_NI4_RXMAXP  0xffc03f08   /* Maximum packet size for Host Rx endpoint4 */
-#define                 USB_EP_NI4_RXCSR  0xffc03f0c   /* Control Status register for Host Rx endpoint4 */
-#define               USB_EP_NI4_RXCOUNT  0xffc03f10   /* Number of bytes received in endpoint4 FIFO */
-#define                USB_EP_NI4_TXTYPE  0xffc03f14   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define            USB_EP_NI4_TXINTERVAL  0xffc03f18   /* Sets the NAK response timeout on Endpoint4 */
-#define                USB_EP_NI4_RXTYPE  0xffc03f1c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define            USB_EP_NI4_RXINTERVAL  0xffc03f20   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-
-/* USB Endpoint 5 Control Registers */
-
-#define               USB_EP_NI4_TXCOUNT  0xffc03f28   /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define                USB_EP_NI5_TXMAXP  0xffc03f40   /* Maximum packet size for Host Tx endpoint5 */
-#define                 USB_EP_NI5_TXCSR  0xffc03f44   /* Control Status register for endpoint5 */
-#define                USB_EP_NI5_RXMAXP  0xffc03f48   /* Maximum packet size for Host Rx endpoint5 */
-#define                 USB_EP_NI5_RXCSR  0xffc03f4c   /* Control Status register for Host Rx endpoint5 */
-#define               USB_EP_NI5_RXCOUNT  0xffc03f50   /* Number of bytes received in endpoint5 FIFO */
-#define                USB_EP_NI5_TXTYPE  0xffc03f54   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define            USB_EP_NI5_TXINTERVAL  0xffc03f58   /* Sets the NAK response timeout on Endpoint5 */
-#define                USB_EP_NI5_RXTYPE  0xffc03f5c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define            USB_EP_NI5_RXINTERVAL  0xffc03f60   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-
-/* USB Endpoint 6 Control Registers */
-
-#define               USB_EP_NI5_TXCOUNT  0xffc03f68   /* Number of bytes to be written to the H145endpoint5 Tx FIFO */
-#define                USB_EP_NI6_TXMAXP  0xffc03f80   /* Maximum packet size for Host Tx endpoint6 */
-#define                 USB_EP_NI6_TXCSR  0xffc03f84   /* Control Status register for endpoint6 */
-#define                USB_EP_NI6_RXMAXP  0xffc03f88   /* Maximum packet size for Host Rx endpoint6 */
-#define                 USB_EP_NI6_RXCSR  0xffc03f8c   /* Control Status register for Host Rx endpoint6 */
-#define               USB_EP_NI6_RXCOUNT  0xffc03f90   /* Number of bytes received in endpoint6 FIFO */
-#define                USB_EP_NI6_TXTYPE  0xffc03f94   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define            USB_EP_NI6_TXINTERVAL  0xffc03f98   /* Sets the NAK response timeout on Endpoint6 */
-#define                USB_EP_NI6_RXTYPE  0xffc03f9c   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define            USB_EP_NI6_RXINTERVAL  0xffc03fa0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-
-/* USB Endpoint 7 Control Registers */
-
-#define               USB_EP_NI6_TXCOUNT  0xffc03fa8   /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define                USB_EP_NI7_TXMAXP  0xffc03fc0   /* Maximum packet size for Host Tx endpoint7 */
-#define                 USB_EP_NI7_TXCSR  0xffc03fc4   /* Control Status register for endpoint7 */
-#define                USB_EP_NI7_RXMAXP  0xffc03fc8   /* Maximum packet size for Host Rx endpoint7 */
-#define                 USB_EP_NI7_RXCSR  0xffc03fcc   /* Control Status register for Host Rx endpoint7 */
-#define               USB_EP_NI7_RXCOUNT  0xffc03fd0   /* Number of bytes received in endpoint7 FIFO */
-#define                USB_EP_NI7_TXTYPE  0xffc03fd4   /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define            USB_EP_NI7_TXINTERVAL  0xffc03fd8   /* Sets the NAK response timeout on Endpoint7 */
-#define                USB_EP_NI7_RXTYPE  0xffc03fdc   /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define            USB_EP_NI7_RXINTERVAL  0xffc03ff0   /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define               USB_EP_NI7_TXCOUNT  0xffc03ff8   /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define                USB_DMA_INTERRUPT  0xffc04000   /* Indicates pending interrupts for the DMA channels */
-
-/* USB Channel 0 Config Registers */
-
-#define                  USB_DMA0CONTROL  0xffc04004   /* DMA master channel 0 configuration */
-#define                  USB_DMA0ADDRLOW  0xffc04008   /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0ADDRHIGH  0xffc0400c   /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define                 USB_DMA0COUNTLOW  0xffc04010   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define                USB_DMA0COUNTHIGH  0xffc04014   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-
-/* USB Channel 1 Config Registers */
-
-#define                  USB_DMA1CONTROL  0xffc04024   /* DMA master channel 1 configuration */
-#define                  USB_DMA1ADDRLOW  0xffc04028   /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1ADDRHIGH  0xffc0402c   /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define                 USB_DMA1COUNTLOW  0xffc04030   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define                USB_DMA1COUNTHIGH  0xffc04034   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-
-/* USB Channel 2 Config Registers */
-
-#define                  USB_DMA2CONTROL  0xffc04044   /* DMA master channel 2 configuration */
-#define                  USB_DMA2ADDRLOW  0xffc04048   /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2ADDRHIGH  0xffc0404c   /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define                 USB_DMA2COUNTLOW  0xffc04050   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define                USB_DMA2COUNTHIGH  0xffc04054   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-
-/* USB Channel 3 Config Registers */
-
-#define                  USB_DMA3CONTROL  0xffc04064   /* DMA master channel 3 configuration */
-#define                  USB_DMA3ADDRLOW  0xffc04068   /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3ADDRHIGH  0xffc0406c   /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define                 USB_DMA3COUNTLOW  0xffc04070   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define                USB_DMA3COUNTHIGH  0xffc04074   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-
-/* USB Channel 4 Config Registers */
-
-#define                  USB_DMA4CONTROL  0xffc04084   /* DMA master channel 4 configuration */
-#define                  USB_DMA4ADDRLOW  0xffc04088   /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4ADDRHIGH  0xffc0408c   /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define                 USB_DMA4COUNTLOW  0xffc04090   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define                USB_DMA4COUNTHIGH  0xffc04094   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-
-/* USB Channel 5 Config Registers */
-
-#define                  USB_DMA5CONTROL  0xffc040a4   /* DMA master channel 5 configuration */
-#define                  USB_DMA5ADDRLOW  0xffc040a8   /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5ADDRHIGH  0xffc040ac   /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define                 USB_DMA5COUNTLOW  0xffc040b0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define                USB_DMA5COUNTHIGH  0xffc040b4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-
-/* USB Channel 6 Config Registers */
-
-#define                  USB_DMA6CONTROL  0xffc040c4   /* DMA master channel 6 configuration */
-#define                  USB_DMA6ADDRLOW  0xffc040c8   /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6ADDRHIGH  0xffc040cc   /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define                 USB_DMA6COUNTLOW  0xffc040d0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define                USB_DMA6COUNTHIGH  0xffc040d4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-
-/* USB Channel 7 Config Registers */
-
-#define                  USB_DMA7CONTROL  0xffc040e4   /* DMA master channel 7 configuration */
-#define                  USB_DMA7ADDRLOW  0xffc040e8   /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7ADDRHIGH  0xffc040ec   /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define                 USB_DMA7COUNTLOW  0xffc040f0   /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define                USB_DMA7COUNTHIGH  0xffc040f4   /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-/* Keypad Registers */
-
-#define                         KPAD_CTL  0xffc04100   /* Controls keypad module enable and disable */
-#define                    KPAD_PRESCALE  0xffc04104   /* Establish a time base for programing the KPAD_MSEL register */
-#define                        KPAD_MSEL  0xffc04108   /* Selects delay parameters for keypad interface sensitivity */
-#define                      KPAD_ROWCOL  0xffc0410c   /* Captures the row and column output values of the keys pressed */
-#define                        KPAD_STAT  0xffc04110   /* Holds and clears the status of the keypad interface interrupt */
-#define                    KPAD_SOFTEVAL  0xffc04114   /* Lets software force keypad interface to check for keys being pressed */
-
-/* Pixel Compositor (PIXC) Registers */
-
-#define                         PIXC_CTL  0xffc04400   /* Overlay enable, resampling mode, I/O data format, transparency enable, watermark level, FIFO status */
-#define                         PIXC_PPL  0xffc04404   /* Holds the number of pixels per line of the display */
-#define                         PIXC_LPF  0xffc04408   /* Holds the number of lines per frame of the display */
-#define                     PIXC_AHSTART  0xffc0440c   /* Contains horizontal start pixel information of the overlay data (set A) */
-#define                       PIXC_AHEND  0xffc04410   /* Contains horizontal end pixel information of the overlay data (set A) */
-#define                     PIXC_AVSTART  0xffc04414   /* Contains vertical start pixel information of the overlay data (set A) */
-#define                       PIXC_AVEND  0xffc04418   /* Contains vertical end pixel information of the overlay data (set A) */
-#define                     PIXC_ATRANSP  0xffc0441c   /* Contains the transparency ratio (set A) */
-#define                     PIXC_BHSTART  0xffc04420   /* Contains horizontal start pixel information of the overlay data (set B) */
-#define                       PIXC_BHEND  0xffc04424   /* Contains horizontal end pixel information of the overlay data (set B) */
-#define                     PIXC_BVSTART  0xffc04428   /* Contains vertical start pixel information of the overlay data (set B) */
-#define                       PIXC_BVEND  0xffc0442c   /* Contains vertical end pixel information of the overlay data (set B) */
-#define                     PIXC_BTRANSP  0xffc04430   /* Contains the transparency ratio (set B) */
-#define                    PIXC_INTRSTAT  0xffc0443c   /* Overlay interrupt configuration/status */
-#define                       PIXC_RYCON  0xffc04440   /* Color space conversion matrix register. Contains the R/Y conversion coefficients */
-#define                       PIXC_GUCON  0xffc04444   /* Color space conversion matrix register. Contains the G/U conversion coefficients */
-#define                       PIXC_BVCON  0xffc04448   /* Color space conversion matrix register. Contains the B/V conversion coefficients */
-#define                      PIXC_CCBIAS  0xffc0444c   /* Bias values for the color space conversion matrix */
-#define                          PIXC_TC  0xffc04450   /* Holds the transparent color value */
-
-/* Handshake MDMA 0 Registers */
-
-#define                   HMDMA0_CONTROL  0xffc04500   /* Handshake MDMA0 Control Register */
-#define                    HMDMA0_ECINIT  0xffc04504   /* Handshake MDMA0 Initial Edge Count Register */
-#define                    HMDMA0_BCINIT  0xffc04508   /* Handshake MDMA0 Initial Block Count Register */
-#define                  HMDMA0_ECURGENT  0xffc0450c   /* Handshake MDMA0 Urgent Edge Count Threshhold Register */
-#define                HMDMA0_ECOVERFLOW  0xffc04510   /* Handshake MDMA0 Edge Count Overflow Interrupt Register */
-#define                    HMDMA0_ECOUNT  0xffc04514   /* Handshake MDMA0 Current Edge Count Register */
-#define                    HMDMA0_BCOUNT  0xffc04518   /* Handshake MDMA0 Current Block Count Register */
-
-/* Handshake MDMA 1 Registers */
-
-#define                   HMDMA1_CONTROL  0xffc04540   /* Handshake MDMA1 Control Register */
-#define                    HMDMA1_ECINIT  0xffc04544   /* Handshake MDMA1 Initial Edge Count Register */
-#define                    HMDMA1_BCINIT  0xffc04548   /* Handshake MDMA1 Initial Block Count Register */
-#define                  HMDMA1_ECURGENT  0xffc0454c   /* Handshake MDMA1 Urgent Edge Count Threshhold Register */
-#define                HMDMA1_ECOVERFLOW  0xffc04550   /* Handshake MDMA1 Edge Count Overflow Interrupt Register */
-#define                    HMDMA1_ECOUNT  0xffc04554   /* Handshake MDMA1 Current Edge Count Register */
-#define                    HMDMA1_BCOUNT  0xffc04558   /* Handshake MDMA1 Current Block Count Register */
-
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* Bit masks for PIXC_CTL */
-
-#define                   PIXC_EN  0x1        /* Pixel Compositor Enable */
-#define                  OVR_A_EN  0x2        /* Overlay A Enable */
-#define                  OVR_B_EN  0x4        /* Overlay B Enable */
-#define                  IMG_FORM  0x8        /* Image Data Format */
-#define                  OVR_FORM  0x10       /* Overlay Data Format */
-#define                  OUT_FORM  0x20       /* Output Data Format */
-#define                   UDS_MOD  0x40       /* Resampling Mode */
-#define                     TC_EN  0x80       /* Transparent Color Enable */
-#define                  IMG_STAT  0x300      /* Image FIFO Status */
-#define                  OVR_STAT  0xc00      /* Overlay FIFO Status */
-#define                    WM_LVL  0x3000     /* FIFO Watermark Level */
-
-/* Bit masks for PIXC_AHSTART */
-
-#define                  A_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_AHEND */
-
-#define                    A_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_AVSTART */
-
-#define                  A_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_AVEND */
-
-#define                    A_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_ATRANSP */
-
-#define                  A_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_BHSTART */
-
-#define                  B_HSTART  0xfff      /* Horizontal Start Coordinates */
-
-/* Bit masks for PIXC_BHEND */
-
-#define                    B_HEND  0xfff      /* Horizontal End Coordinates */
-
-/* Bit masks for PIXC_BVSTART */
-
-#define                  B_VSTART  0x3ff      /* Vertical Start Coordinates */
-
-/* Bit masks for PIXC_BVEND */
-
-#define                    B_VEND  0x3ff      /* Vertical End Coordinates */
-
-/* Bit masks for PIXC_BTRANSP */
-
-#define                  B_TRANSP  0xf        /* Transparency Value */
-
-/* Bit masks for PIXC_INTRSTAT */
-
-#define                OVR_INT_EN  0x1        /* Interrupt at End of Last Valid Overlay */
-#define                FRM_INT_EN  0x2        /* Interrupt at End of Frame */
-#define              OVR_INT_STAT  0x4        /* Overlay Interrupt Status */
-#define              FRM_INT_STAT  0x8        /* Frame Interrupt Status */
-
-/* Bit masks for PIXC_RYCON */
-
-#define                       A11  0x3ff      /* A11 in the Coefficient Matrix */
-#define                       A12  0xffc00    /* A12 in the Coefficient Matrix */
-#define                       A13  0x3ff00000 /* A13 in the Coefficient Matrix */
-#define                  RY_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_GUCON */
-
-#define                       A21  0x3ff      /* A21 in the Coefficient Matrix */
-#define                       A22  0xffc00    /* A22 in the Coefficient Matrix */
-#define                       A23  0x3ff00000 /* A23 in the Coefficient Matrix */
-#define                  GU_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_BVCON */
-
-#define                       A31  0x3ff      /* A31 in the Coefficient Matrix */
-#define                       A32  0xffc00    /* A32 in the Coefficient Matrix */
-#define                       A33  0x3ff00000 /* A33 in the Coefficient Matrix */
-#define                  BV_MULT4  0x40000000 /* Multiply Row by 4 */
-
-/* Bit masks for PIXC_CCBIAS */
-
-#define                       A14  0x3ff      /* A14 in the Bias Vector */
-#define                       A24  0xffc00    /* A24 in the Bias Vector */
-#define                       A34  0x3ff00000 /* A34 in the Bias Vector */
-
-/* Bit masks for PIXC_TC */
-
-#define                  RY_TRANS  0xff       /* Transparent Color - R/Y Component */
-#define                  GU_TRANS  0xff00     /* Transparent Color - G/U Component */
-#define                  BV_TRANS  0xff0000   /* Transparent Color - B/V Component */
-
-/* Bit masks for HOST_CONTROL */
-
-#define                   HOST_EN  0x1        /* Host Enable */
-#define                  HOST_END  0x2        /* Host Endianess */
-#define                 DATA_SIZE  0x4        /* Data Size */
-#define                  HOST_RST  0x8        /* Host Reset */
-#define                  HRDY_OVR  0x20       /* Host Ready Override */
-#define                  INT_MODE  0x40       /* Interrupt Mode */
-#define                     BT_EN  0x80       /* Bus Timeout Enable */
-#define                       EHW  0x100      /* Enable Host Write */
-#define                       EHR  0x200      /* Enable Host Read */
-#define                       BDR  0x400      /* Burst DMA Requests */
-
-/* Bit masks for HOST_STATUS */
-
-#define                 DMA_READY  0x1        /* DMA Ready */
-#define                  FIFOFULL  0x2        /* FIFO Full */
-#define                 FIFOEMPTY  0x4        /* FIFO Empty */
-#define              DMA_COMPLETE  0x8        /* DMA Complete */
-#define                      HSHK  0x10       /* Host Handshake */
-#define                   TIMEOUT  0x20       /* Host Timeout */
-#define                      HIRQ  0x40       /* Host Interrupt Request */
-#define                ALLOW_CNFG  0x80       /* Allow New Configuration */
-#define                   DMA_DIR  0x100      /* DMA Direction */
-#define                       BTE  0x200      /* Bus Timeout Enabled */
-
-/* Bit masks for HOST_TIMEOUT */
-
-#define             COUNT_TIMEOUT  0x7ff      /* Host Timeout count */
-
-/* Bit masks for MXVR_CONFIG */
-
-#define                    MXVREN  0x1        /* MXVR Enable */
-#define                      MMSM  0x2        /* MXVR Master/Slave Mode Select */
-#define                    ACTIVE  0x4        /* Active Mode */
-#define                    SDELAY  0x8        /* Synchronous Data Delay */
-#define                   NCMRXEN  0x10       /* Normal Control Message Receive Enable */
-#define                   RWRRXEN  0x20       /* Remote Write Receive Enable */
-#define                     MTXEN  0x40       /* MXVR Transmit Data Enable */
-#define                    MTXONB  0x80       /* MXVR Phy Transmitter On */
-#define                   EPARITY  0x100      /* Even Parity Select */
-#define                       MSB  0x1e00     /* Master Synchronous Boundary */
-#define                    APRXEN  0x2000     /* Asynchronous Packet Receive Enable */
-#define                    WAKEUP  0x4000     /* Wake-Up */
-#define                     LMECH  0x8000     /* Lock Mechanism Select */
-
-/* Bit masks for MXVR_STATE_0 */
-
-#define                      NACT  0x1        /* Network Activity */
-#define                    SBLOCK  0x2        /* Super Block Lock */
-#define                   FMPLLST  0xc        /* Frequency Multiply PLL SM State */
-#define                  CDRPLLST  0xe0       /* Clock/Data Recovery PLL SM State */
-#define                     APBSY  0x100      /* Asynchronous Packet Transmit Buffer Busy */
-#define                     APARB  0x200      /* Asynchronous Packet Arbitrating */
-#define                      APTX  0x400      /* Asynchronous Packet Transmitting */
-#define                      APRX  0x800      /* Receiving Asynchronous Packet */
-#define                     CMBSY  0x1000     /* Control Message Transmit Buffer Busy */
-#define                     CMARB  0x2000     /* Control Message Arbitrating */
-#define                      CMTX  0x4000     /* Control Message Transmitting */
-#define                      CMRX  0x8000     /* Receiving Control Message */
-#define                    MRXONB  0x10000    /* MRXONB Pin State */
-#define                     RGSIP  0x20000    /* Remote Get Source In Progress */
-#define                     DALIP  0x40000    /* Resource Deallocate In Progress */
-#define                      ALIP  0x80000    /* Resource Allocate In Progress */
-#define                     RRDIP  0x100000   /* Remote Read In Progress */
-#define                     RWRIP  0x200000   /* Remote Write In Progress */
-#define                     FLOCK  0x400000   /* Frame Lock */
-#define                     BLOCK  0x800000   /* Block Lock */
-#define                       RSB  0xf000000  /* Received Synchronous Boundary */
-#define                   DERRNUM  0xf0000000 /* DMA Error Channel Number */
-
-/* Bit masks for MXVR_STATE_1 */
-
-#define                   SRXNUMB  0xf        /* Synchronous Receive FIFO Number of Bytes */
-#define                   STXNUMB  0xf0       /* Synchronous Transmit FIFO Number of Bytes */
-#define                    APCONT  0x100      /* Asynchronous Packet Continuation */
-#define                  OBERRNUM  0xe00      /* DMA Out of Bounds Error Channel Number */
-#define                DMAACTIVE0  0x10000    /* DMA0 Active */
-#define                DMAACTIVE1  0x20000    /* DMA1 Active */
-#define                DMAACTIVE2  0x40000    /* DMA2 Active */
-#define                DMAACTIVE3  0x80000    /* DMA3 Active */
-#define                DMAACTIVE4  0x100000   /* DMA4 Active */
-#define                DMAACTIVE5  0x200000   /* DMA5 Active */
-#define                DMAACTIVE6  0x400000   /* DMA6 Active */
-#define                DMAACTIVE7  0x800000   /* DMA7 Active */
-#define                  DMAPMEN0  0x1000000  /* DMA0 Pattern Matching Enabled */
-#define                  DMAPMEN1  0x2000000  /* DMA1 Pattern Matching Enabled */
-#define                  DMAPMEN2  0x4000000  /* DMA2 Pattern Matching Enabled */
-#define                  DMAPMEN3  0x8000000  /* DMA3 Pattern Matching Enabled */
-#define                  DMAPMEN4  0x10000000 /* DMA4 Pattern Matching Enabled */
-#define                  DMAPMEN5  0x20000000 /* DMA5 Pattern Matching Enabled */
-#define                  DMAPMEN6  0x40000000 /* DMA6 Pattern Matching Enabled */
-#define                  DMAPMEN7  0x80000000 /* DMA7 Pattern Matching Enabled */
-
-/* Bit masks for MXVR_INT_STAT_0 */
-
-#define                      NI2A  0x1        /* Network Inactive to Active */
-#define                      NA2I  0x2        /* Network Active to Inactive */
-#define                     SBU2L  0x4        /* Super Block Unlock to Lock */
-#define                     SBL2U  0x8        /* Super Block Lock to Unlock */
-#define                       PRU  0x10       /* Position Register Updated */
-#define                      MPRU  0x20       /* Maximum Position Register Updated */
-#define                       DRU  0x40       /* Delay Register Updated */
-#define                      MDRU  0x80       /* Maximum Delay Register Updated */
-#define                       SBU  0x100      /* Synchronous Boundary Updated */
-#define                       ATU  0x200      /* Allocation Table Updated */
-#define                      FCZ0  0x400      /* Frame Counter 0 Zero */
-#define                      FCZ1  0x800      /* Frame Counter 1 Zero */
-#define                      PERR  0x1000     /* Parity Error */
-#define                      MH2L  0x2000     /* MRXONB High to Low */
-#define                      ML2H  0x4000     /* MRXONB Low to High */
-#define                       WUP  0x8000     /* Wake-Up Preamble Received */
-#define                      FU2L  0x10000    /* Frame Unlock to Lock */
-#define                      FL2U  0x20000    /* Frame Lock to Unlock */
-#define                      BU2L  0x40000    /* Block Unlock to Lock */
-#define                      BL2U  0x80000    /* Block Lock to Unlock */
-#define                     OBERR  0x100000   /* DMA Out of Bounds Error */
-#define                       PFL  0x200000   /* PLL Frequency Locked */
-#define                       SCZ  0x400000   /* System Clock Counter Zero */
-#define                      FERR  0x800000   /* FIFO Error */
-#define                       CMR  0x1000000  /* Control Message Received */
-#define                     CMROF  0x2000000  /* Control Message Receive Buffer Overflow */
-#define                      CMTS  0x4000000  /* Control Message Transmit Buffer Successfully Sent */
-#define                      CMTC  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled */
-#define                      RWRC  0x10000000 /* Remote Write Control Message Completed */
-#define                       BCZ  0x20000000 /* Block Counter Zero */
-#define                     BMERR  0x40000000 /* Biphase Mark Coding Error */
-#define                      DERR  0x80000000 /* DMA Error */
-
-/* Bit masks for MXVR_INT_STAT_1 */
-
-#define                    HDONE0  0x1        /* DMA0 Half Done */
-#define                     DONE0  0x2        /* DMA0 Done */
-#define                       APR  0x4        /* Asynchronous Packet Received */
-#define                     APROF  0x8        /* Asynchronous Packet Receive Buffer Overflow */
-#define                    HDONE1  0x10       /* DMA1 Half Done */
-#define                     DONE1  0x20       /* DMA1 Done */
-#define                      APTS  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent */
-#define                      APTC  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled */
-#define                    HDONE2  0x100      /* DMA2 Half Done */
-#define                     DONE2  0x200      /* DMA2 Done */
-#define                     APRCE  0x400      /* Asynchronous Packet Receive CRC Error */
-#define                     APRPE  0x800      /* Asynchronous Packet Receive Packet Error */
-#define                    HDONE3  0x1000     /* DMA3 Half Done */
-#define                     DONE3  0x2000     /* DMA3 Done */
-#define                    HDONE4  0x10000    /* DMA4 Half Done */
-#define                     DONE4  0x20000    /* DMA4 Done */
-#define                    HDONE5  0x100000   /* DMA5 Half Done */
-#define                     DONE5  0x200000   /* DMA5 Done */
-#define                    HDONE6  0x1000000  /* DMA6 Half Done */
-#define                     DONE6  0x2000000  /* DMA6 Done */
-#define                    HDONE7  0x10000000 /* DMA7 Half Done */
-#define                     DONE7  0x20000000 /* DMA7 Done */
-
-/* Bit masks for MXVR_INT_EN_0 */
-
-#define                    NI2AEN  0x1        /* Network Inactive to Active Interrupt Enable */
-#define                    NA2IEN  0x2        /* Network Active to Inactive Interrupt Enable */
-#define                   SBU2LEN  0x4        /* Super Block Unlock to Lock Interrupt Enable */
-#define                   SBL2UEN  0x8        /* Super Block Lock to Unlock Interrupt Enable */
-#define                     PRUEN  0x10       /* Position Register Updated Interrupt Enable */
-#define                    MPRUEN  0x20       /* Maximum Position Register Updated Interrupt Enable */
-#define                     DRUEN  0x40       /* Delay Register Updated Interrupt Enable */
-#define                    MDRUEN  0x80       /* Maximum Delay Register Updated Interrupt Enable */
-#define                     SBUEN  0x100      /* Synchronous Boundary Updated Interrupt Enable */
-#define                     ATUEN  0x200      /* Allocation Table Updated Interrupt Enable */
-#define                    FCZ0EN  0x400      /* Frame Counter 0 Zero Interrupt Enable */
-#define                    FCZ1EN  0x800      /* Frame Counter 1 Zero Interrupt Enable */
-#define                    PERREN  0x1000     /* Parity Error Interrupt Enable */
-#define                    MH2LEN  0x2000     /* MRXONB High to Low Interrupt Enable */
-#define                    ML2HEN  0x4000     /* MRXONB Low to High Interrupt Enable */
-#define                     WUPEN  0x8000     /* Wake-Up Preamble Received Interrupt Enable */
-#define                    FU2LEN  0x10000    /* Frame Unlock to Lock Interrupt Enable */
-#define                    FL2UEN  0x20000    /* Frame Lock to Unlock Interrupt Enable */
-#define                    BU2LEN  0x40000    /* Block Unlock to Lock Interrupt Enable */
-#define                    BL2UEN  0x80000    /* Block Lock to Unlock Interrupt Enable */
-#define                   OBERREN  0x100000   /* DMA Out of Bounds Error Interrupt Enable */
-#define                     PFLEN  0x200000   /* PLL Frequency Locked Interrupt Enable */
-#define                     SCZEN  0x400000   /* System Clock Counter Zero Interrupt Enable */
-#define                    FERREN  0x800000   /* FIFO Error Interrupt Enable */
-#define                     CMREN  0x1000000  /* Control Message Received Interrupt Enable */
-#define                   CMROFEN  0x2000000  /* Control Message Receive Buffer Overflow Interrupt Enable */
-#define                    CMTSEN  0x4000000  /* Control Message Transmit Buffer Successfully Sent Interrupt Enable */
-#define                    CMTCEN  0x8000000  /* Control Message Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                    RWRCEN  0x10000000 /* Remote Write Control Message Completed Interrupt Enable */
-#define                     BCZEN  0x20000000 /* Block Counter Zero Interrupt Enable */
-#define                   BMERREN  0x40000000 /* Biphase Mark Coding Error Interrupt Enable */
-#define                    DERREN  0x80000000 /* DMA Error Interrupt Enable */
-
-/* Bit masks for MXVR_INT_EN_1 */
-
-#define                  HDONEEN0  0x1        /* DMA0 Half Done Interrupt Enable */
-#define                   DONEEN0  0x2        /* DMA0 Done Interrupt Enable */
-#define                     APREN  0x4        /* Asynchronous Packet Received Interrupt Enable */
-#define                   APROFEN  0x8        /* Asynchronous Packet Receive Buffer Overflow Interrupt Enable */
-#define                  HDONEEN1  0x10       /* DMA1 Half Done Interrupt Enable */
-#define                   DONEEN1  0x20       /* DMA1 Done Interrupt Enable */
-#define                    APTSEN  0x40       /* Asynchronous Packet Transmit Buffer Successfully Sent Interrupt Enable */
-#define                    APTCEN  0x80       /* Asynchronous Packet Transmit Buffer Successfully Cancelled Interrupt Enable */
-#define                  HDONEEN2  0x100      /* DMA2 Half Done Interrupt Enable */
-#define                   DONEEN2  0x200      /* DMA2 Done Interrupt Enable */
-#define                   APRCEEN  0x400      /* Asynchronous Packet Receive CRC Error Interrupt Enable */
-#define                   APRPEEN  0x800      /* Asynchronous Packet Receive Packet Error Interrupt Enable */
-#define                  HDONEEN3  0x1000     /* DMA3 Half Done Interrupt Enable */
-#define                   DONEEN3  0x2000     /* DMA3 Done Interrupt Enable */
-#define                  HDONEEN4  0x10000    /* DMA4 Half Done Interrupt Enable */
-#define                   DONEEN4  0x20000    /* DMA4 Done Interrupt Enable */
-#define                  HDONEEN5  0x100000   /* DMA5 Half Done Interrupt Enable */
-#define                   DONEEN5  0x200000   /* DMA5 Done Interrupt Enable */
-#define                  HDONEEN6  0x1000000  /* DMA6 Half Done Interrupt Enable */
-#define                   DONEEN6  0x2000000  /* DMA6 Done Interrupt Enable */
-#define                  HDONEEN7  0x10000000 /* DMA7 Half Done Interrupt Enable */
-#define                   DONEEN7  0x20000000 /* DMA7 Done Interrupt Enable */
-
-/* Bit masks for MXVR_POSITION */
-
-#define                  POSITION  0x3f       /* Node Position */
-#define                    PVALID  0x8000     /* Node Position Valid */
-
-/* Bit masks for MXVR_MAX_POSITION */
-
-#define                 MPOSITION  0x3f       /* Maximum Node Position */
-#define                   MPVALID  0x8000     /* Maximum Node Position Valid */
-
-/* Bit masks for MXVR_DELAY */
-
-#define                     DELAY  0x3f       /* Node Frame Delay */
-#define                    DVALID  0x8000     /* Node Frame Delay Valid */
-
-/* Bit masks for MXVR_MAX_DELAY */
-
-#define                    MDELAY  0x3f       /* Maximum Node Frame Delay */
-#define                   MDVALID  0x8000     /* Maximum Node Frame Delay Valid */
-
-/* Bit masks for MXVR_LADDR */
-
-#define                     LADDR  0xffff     /* Logical Address */
-#define                    LVALID  0x80000000 /* Logical Address Valid */
-
-/* Bit masks for MXVR_GADDR */
-
-#define                    GADDRL  0xff       /* Group Address Lower Byte */
-#define                    GVALID  0x8000     /* Group Address Valid */
-
-/* Bit masks for MXVR_AADDR */
-
-#define                     AADDR  0xffff     /* Alternate Address */
-#define                    AVALID  0x80000000 /* Alternate Address Valid */
-
-/* Bit masks for MXVR_ALLOC_0 */
-
-#define                       CL0  0x7f       /* Channel 0 Connection Label */
-#define                      CIU0  0x80       /* Channel 0 In Use */
-#define                       CL1  0x7f00     /* Channel 0 Connection Label */
-#define                      CIU1  0x8000     /* Channel 0 In Use */
-#define                       CL2  0x7f0000   /* Channel 0 Connection Label */
-#define                      CIU2  0x800000   /* Channel 0 In Use */
-#define                       CL3  0x7f000000 /* Channel 0 Connection Label */
-#define                      CIU3  0x80000000 /* Channel 0 In Use */
-
-/* Bit masks for MXVR_ALLOC_1 */
-
-#define                       CL4  0x7f       /* Channel 4 Connection Label */
-#define                      CIU4  0x80       /* Channel 4 In Use */
-#define                       CL5  0x7f00     /* Channel 5 Connection Label */
-#define                      CIU5  0x8000     /* Channel 5 In Use */
-#define                       CL6  0x7f0000   /* Channel 6 Connection Label */
-#define                      CIU6  0x800000   /* Channel 6 In Use */
-#define                       CL7  0x7f000000 /* Channel 7 Connection Label */
-#define                      CIU7  0x80000000 /* Channel 7 In Use */
-
-/* Bit masks for MXVR_ALLOC_2 */
-
-#define                       CL8  0x7f       /* Channel 8 Connection Label */
-#define                      CIU8  0x80       /* Channel 8 In Use */
-#define                       CL9  0x7f00     /* Channel 9 Connection Label */
-#define                      CIU9  0x8000     /* Channel 9 In Use */
-#define                      CL10  0x7f0000   /* Channel 10 Connection Label */
-#define                     CIU10  0x800000   /* Channel 10 In Use */
-#define                      CL11  0x7f000000 /* Channel 11 Connection Label */
-#define                     CIU11  0x80000000 /* Channel 11 In Use */
-
-/* Bit masks for MXVR_ALLOC_3 */
-
-#define                      CL12  0x7f       /* Channel 12 Connection Label */
-#define                     CIU12  0x80       /* Channel 12 In Use */
-#define                      CL13  0x7f00     /* Channel 13 Connection Label */
-#define                     CIU13  0x8000     /* Channel 13 In Use */
-#define                      CL14  0x7f0000   /* Channel 14 Connection Label */
-#define                     CIU14  0x800000   /* Channel 14 In Use */
-#define                      CL15  0x7f000000 /* Channel 15 Connection Label */
-#define                     CIU15  0x80000000 /* Channel 15 In Use */
-
-/* Bit masks for MXVR_ALLOC_4 */
-
-#define                      CL16  0x7f       /* Channel 16 Connection Label */
-#define                     CIU16  0x80       /* Channel 16 In Use */
-#define                      CL17  0x7f00     /* Channel 17 Connection Label */
-#define                     CIU17  0x8000     /* Channel 17 In Use */
-#define                      CL18  0x7f0000   /* Channel 18 Connection Label */
-#define                     CIU18  0x800000   /* Channel 18 In Use */
-#define                      CL19  0x7f000000 /* Channel 19 Connection Label */
-#define                     CIU19  0x80000000 /* Channel 19 In Use */
-
-/* Bit masks for MXVR_ALLOC_5 */
-
-#define                      CL20  0x7f       /* Channel 20 Connection Label */
-#define                     CIU20  0x80       /* Channel 20 In Use */
-#define                      CL21  0x7f00     /* Channel 21 Connection Label */
-#define                     CIU21  0x8000     /* Channel 21 In Use */
-#define                      CL22  0x7f0000   /* Channel 22 Connection Label */
-#define                     CIU22  0x800000   /* Channel 22 In Use */
-#define                      CL23  0x7f000000 /* Channel 23 Connection Label */
-#define                     CIU23  0x80000000 /* Channel 23 In Use */
-
-/* Bit masks for MXVR_ALLOC_6 */
-
-#define                      CL24  0x7f       /* Channel 24 Connection Label */
-#define                     CIU24  0x80       /* Channel 24 In Use */
-#define                      CL25  0x7f00     /* Channel 25 Connection Label */
-#define                     CIU25  0x8000     /* Channel 25 In Use */
-#define                      CL26  0x7f0000   /* Channel 26 Connection Label */
-#define                     CIU26  0x800000   /* Channel 26 In Use */
-#define                      CL27  0x7f000000 /* Channel 27 Connection Label */
-#define                     CIU27  0x80000000 /* Channel 27 In Use */
-
-/* Bit masks for MXVR_ALLOC_7 */
-
-#define                      CL28  0x7f       /* Channel 28 Connection Label */
-#define                     CIU28  0x80       /* Channel 28 In Use */
-#define                      CL29  0x7f00     /* Channel 29 Connection Label */
-#define                     CIU29  0x8000     /* Channel 29 In Use */
-#define                      CL30  0x7f0000   /* Channel 30 Connection Label */
-#define                     CIU30  0x800000   /* Channel 30 In Use */
-#define                      CL31  0x7f000000 /* Channel 31 Connection Label */
-#define                     CIU31  0x80000000 /* Channel 31 In Use */
-
-/* Bit masks for MXVR_ALLOC_8 */
-
-#define                      CL32  0x7f       /* Channel 32 Connection Label */
-#define                     CIU32  0x80       /* Channel 32 In Use */
-#define                      CL33  0x7f00     /* Channel 33 Connection Label */
-#define                     CIU33  0x8000     /* Channel 33 In Use */
-#define                      CL34  0x7f0000   /* Channel 34 Connection Label */
-#define                     CIU34  0x800000   /* Channel 34 In Use */
-#define                      CL35  0x7f000000 /* Channel 35 Connection Label */
-#define                     CIU35  0x80000000 /* Channel 35 In Use */
-
-/* Bit masks for MXVR_ALLOC_9 */
-
-#define                      CL36  0x7f       /* Channel 36 Connection Label */
-#define                     CIU36  0x80       /* Channel 36 In Use */
-#define                      CL37  0x7f00     /* Channel 37 Connection Label */
-#define                     CIU37  0x8000     /* Channel 37 In Use */
-#define                      CL38  0x7f0000   /* Channel 38 Connection Label */
-#define                     CIU38  0x800000   /* Channel 38 In Use */
-#define                      CL39  0x7f000000 /* Channel 39 Connection Label */
-#define                     CIU39  0x80000000 /* Channel 39 In Use */
-
-/* Bit masks for MXVR_ALLOC_10 */
-
-#define                      CL40  0x7f       /* Channel 40 Connection Label */
-#define                     CIU40  0x80       /* Channel 40 In Use */
-#define                      CL41  0x7f00     /* Channel 41 Connection Label */
-#define                     CIU41  0x8000     /* Channel 41 In Use */
-#define                      CL42  0x7f0000   /* Channel 42 Connection Label */
-#define                     CIU42  0x800000   /* Channel 42 In Use */
-#define                      CL43  0x7f000000 /* Channel 43 Connection Label */
-#define                     CIU43  0x80000000 /* Channel 43 In Use */
-
-/* Bit masks for MXVR_ALLOC_11 */
-
-#define                      CL44  0x7f       /* Channel 44 Connection Label */
-#define                     CIU44  0x80       /* Channel 44 In Use */
-#define                      CL45  0x7f00     /* Channel 45 Connection Label */
-#define                     CIU45  0x8000     /* Channel 45 In Use */
-#define                      CL46  0x7f0000   /* Channel 46 Connection Label */
-#define                     CIU46  0x800000   /* Channel 46 In Use */
-#define                      CL47  0x7f000000 /* Channel 47 Connection Label */
-#define                     CIU47  0x80000000 /* Channel 47 In Use */
-
-/* Bit masks for MXVR_ALLOC_12 */
-
-#define                      CL48  0x7f       /* Channel 48 Connection Label */
-#define                     CIU48  0x80       /* Channel 48 In Use */
-#define                      CL49  0x7f00     /* Channel 49 Connection Label */
-#define                     CIU49  0x8000     /* Channel 49 In Use */
-#define                      CL50  0x7f0000   /* Channel 50 Connection Label */
-#define                     CIU50  0x800000   /* Channel 50 In Use */
-#define                      CL51  0x7f000000 /* Channel 51 Connection Label */
-#define                     CIU51  0x80000000 /* Channel 51 In Use */
-
-/* Bit masks for MXVR_ALLOC_13 */
-
-#define                      CL52  0x7f       /* Channel 52 Connection Label */
-#define                     CIU52  0x80       /* Channel 52 In Use */
-#define                      CL53  0x7f00     /* Channel 53 Connection Label */
-#define                     CIU53  0x8000     /* Channel 53 In Use */
-#define                      CL54  0x7f0000   /* Channel 54 Connection Label */
-#define                     CIU54  0x800000   /* Channel 54 In Use */
-#define                      CL55  0x7f000000 /* Channel 55 Connection Label */
-#define                     CIU55  0x80000000 /* Channel 55 In Use */
-
-/* Bit masks for MXVR_ALLOC_14 */
-
-#define                      CL56  0x7f       /* Channel 56 Connection Label */
-#define                     CIU56  0x80       /* Channel 56 In Use */
-#define                      CL57  0x7f00     /* Channel 57 Connection Label */
-#define                     CIU57  0x8000     /* Channel 57 In Use */
-#define                      CL58  0x7f0000   /* Channel 58 Connection Label */
-#define                     CIU58  0x800000   /* Channel 58 In Use */
-#define                      CL59  0x7f000000 /* Channel 59 Connection Label */
-#define                     CIU59  0x80000000 /* Channel 59 In Use */
-
-/* MXVR_SYNC_LCHAN_0 Masks */
-
-#define LCHANPC0     0x0000000Flu
-#define LCHANPC1     0x000000F0lu
-#define LCHANPC2     0x00000F00lu
-#define LCHANPC3     0x0000F000lu
-#define LCHANPC4     0x000F0000lu
-#define LCHANPC5     0x00F00000lu
-#define LCHANPC6     0x0F000000lu
-#define LCHANPC7     0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_1 Masks */
-
-#define LCHANPC8     0x0000000Flu
-#define LCHANPC9     0x000000F0lu
-#define LCHANPC10    0x00000F00lu
-#define LCHANPC11    0x0000F000lu
-#define LCHANPC12    0x000F0000lu
-#define LCHANPC13    0x00F00000lu
-#define LCHANPC14    0x0F000000lu
-#define LCHANPC15    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_2 Masks */
-
-#define LCHANPC16    0x0000000Flu
-#define LCHANPC17    0x000000F0lu
-#define LCHANPC18    0x00000F00lu
-#define LCHANPC19    0x0000F000lu
-#define LCHANPC20    0x000F0000lu
-#define LCHANPC21    0x00F00000lu
-#define LCHANPC22    0x0F000000lu
-#define LCHANPC23    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_3 Masks */
-
-#define LCHANPC24    0x0000000Flu
-#define LCHANPC25    0x000000F0lu
-#define LCHANPC26    0x00000F00lu
-#define LCHANPC27    0x0000F000lu
-#define LCHANPC28    0x000F0000lu
-#define LCHANPC29    0x00F00000lu
-#define LCHANPC30    0x0F000000lu
-#define LCHANPC31    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_4 Masks */
-
-#define LCHANPC32    0x0000000Flu
-#define LCHANPC33    0x000000F0lu
-#define LCHANPC34    0x00000F00lu
-#define LCHANPC35    0x0000F000lu
-#define LCHANPC36    0x000F0000lu
-#define LCHANPC37    0x00F00000lu
-#define LCHANPC38    0x0F000000lu
-#define LCHANPC39    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_5 Masks */
-
-#define LCHANPC40    0x0000000Flu
-#define LCHANPC41    0x000000F0lu
-#define LCHANPC42    0x00000F00lu
-#define LCHANPC43    0x0000F000lu
-#define LCHANPC44    0x000F0000lu
-#define LCHANPC45    0x00F00000lu
-#define LCHANPC46    0x0F000000lu
-#define LCHANPC47    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_6 Masks */
-
-#define LCHANPC48    0x0000000Flu
-#define LCHANPC49    0x000000F0lu
-#define LCHANPC50    0x00000F00lu
-#define LCHANPC51    0x0000F000lu
-#define LCHANPC52    0x000F0000lu
-#define LCHANPC53    0x00F00000lu
-#define LCHANPC54    0x0F000000lu
-#define LCHANPC55    0xF0000000lu
-
-
-/* MXVR_SYNC_LCHAN_7 Masks */
-
-#define LCHANPC56    0x0000000Flu
-#define LCHANPC57    0x000000F0lu
-#define LCHANPC58    0x00000F00lu
-#define LCHANPC59    0x0000F000lu
-
-/* Bit masks for MXVR_DMAx_CONFIG */
-
-#define                    MDMAEN  0x1        /* DMA Channel Enable */
-#define                     DMADD  0x2        /* DMA Channel Direction */
-#define                 BY4SWAPEN  0x20       /* DMA Channel Four Byte Swap Enable */
-#define                     LCHAN  0x3c0      /* DMA Channel Logical Channel */
-#define                 BITSWAPEN  0x400      /* DMA Channel Bit Swap Enable */
-#define                 BY2SWAPEN  0x800      /* DMA Channel Two Byte Swap Enable */
-#define                     MFLOW  0x7000     /* DMA Channel Operation Flow */
-#define                   FIXEDPM  0x80000    /* DMA Channel Fixed Pattern Matching Select */
-#define                  STARTPAT  0x300000   /* DMA Channel Start Pattern Select */
-#define                   STOPPAT  0xc00000   /* DMA Channel Stop Pattern Select */
-#define                  COUNTPOS  0x1c000000 /* DMA Channel Count Position */
-
-/* Bit masks for MXVR_AP_CTL */
-
-#define                   STARTAP  0x1        /* Start Asynchronous Packet Transmission */
-#define                  CANCELAP  0x2        /* Cancel Asynchronous Packet Transmission */
-#define                   RESETAP  0x4        /* Reset Asynchronous Packet Arbitration */
-#define                    APRBE0  0x4000     /* Asynchronous Packet Receive Buffer Entry 0 */
-#define                    APRBE1  0x8000     /* Asynchronous Packet Receive Buffer Entry 1 */
-
-/* Bit masks for MXVR_APRB_START_ADDR */
-
-#define      MXVR_APRB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Receive Buffer Start Address */
-
-/* Bit masks for MXVR_APRB_CURR_ADDR */
-
-#define       MXVR_APRB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Receive Buffer Current Address */
-
-/* Bit masks for MXVR_APTB_START_ADDR */
-
-#define       MXVR_APTB_START_ADDR_MASK  0x1fffffe  /* Asynchronous Packet Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_APTB_CURR_ADDR */
-
-#define        MXVR_APTB_CURR_ADDR_MASK  0xffffffff /* Asynchronous Packet Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_CM_CTL */
-
-#define                   STARTCM  0x1        /* Start Control Message Transmission */
-#define                  CANCELCM  0x2        /* Cancel Control Message Transmission */
-#define                    CMRBE0  0x10000    /* Control Message Receive Buffer Entry 0 */
-#define                    CMRBE1  0x20000    /* Control Message Receive Buffer Entry 1 */
-#define                    CMRBE2  0x40000    /* Control Message Receive Buffer Entry 2 */
-#define                    CMRBE3  0x80000    /* Control Message Receive Buffer Entry 3 */
-#define                    CMRBE4  0x100000   /* Control Message Receive Buffer Entry 4 */
-#define                    CMRBE5  0x200000   /* Control Message Receive Buffer Entry 5 */
-#define                    CMRBE6  0x400000   /* Control Message Receive Buffer Entry 6 */
-#define                    CMRBE7  0x800000   /* Control Message Receive Buffer Entry 7 */
-#define                    CMRBE8  0x1000000  /* Control Message Receive Buffer Entry 8 */
-#define                    CMRBE9  0x2000000  /* Control Message Receive Buffer Entry 9 */
-#define                   CMRBE10  0x4000000  /* Control Message Receive Buffer Entry 10 */
-#define                   CMRBE11  0x8000000  /* Control Message Receive Buffer Entry 11 */
-#define                   CMRBE12  0x10000000 /* Control Message Receive Buffer Entry 12 */
-#define                   CMRBE13  0x20000000 /* Control Message Receive Buffer Entry 13 */
-#define                   CMRBE14  0x40000000 /* Control Message Receive Buffer Entry 14 */
-#define                   CMRBE15  0x80000000 /* Control Message Receive Buffer Entry 15 */
-
-/* Bit masks for MXVR_CMRB_START_ADDR */
-
-#define      MXVR_CMRB_START_ADDR_MASK  0x1fffffe  /* Control Message Receive Buffer Start Address */
-
-/* Bit masks for MXVR_CMRB_CURR_ADDR */
-
-#define       MXVR_CMRB_CURR_ADDR_MASK  0xffffffff /* Control Message Receive Buffer Current Address */
-
-/* Bit masks for MXVR_CMTB_START_ADDR */
-
-#define      MXVR_CMTB_START_ADDR_MASK  0x1fffffe  /* Control Message Transmit Buffer Start Address */
-
-/* Bit masks for MXVR_CMTB_CURR_ADDR */
-
-#define       MXVR_CMTB_CURR_ADDR_MASK  0xffffffff /* Control Message Transmit Buffer Current Address */
-
-/* Bit masks for MXVR_RRDB_START_ADDR */
-
-#define      MXVR_RRDB_START_ADDR_MASK  0x1fffffe  /* Remote Read Buffer Start Address */
-
-/* Bit masks for MXVR_RRDB_CURR_ADDR */
-
-#define       MXVR_RRDB_CURR_ADDR_MASK  0xffffffff /* Remote Read Buffer Current Address */
-
-/* Bit masks for MXVR_PAT_DATAx */
-
-#define              MATCH_DATA_0  0xff       /* Pattern Match Data Byte 0 */
-#define              MATCH_DATA_1  0xff00     /* Pattern Match Data Byte 1 */
-#define              MATCH_DATA_2  0xff0000   /* Pattern Match Data Byte 2 */
-#define              MATCH_DATA_3  0xff000000 /* Pattern Match Data Byte 3 */
-
-/* Bit masks for MXVR_PAT_EN_0 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-
-/* Bit masks for MXVR_PAT_EN_1 */
-
-#define              MATCH_EN_0_0  0x1        /* Pattern Match Enable Byte 0 Bit 0 */
-#define              MATCH_EN_0_1  0x2        /* Pattern Match Enable Byte 0 Bit 1 */
-#define              MATCH_EN_0_2  0x4        /* Pattern Match Enable Byte 0 Bit 2 */
-#define              MATCH_EN_0_3  0x8        /* Pattern Match Enable Byte 0 Bit 3 */
-#define              MATCH_EN_0_4  0x10       /* Pattern Match Enable Byte 0 Bit 4 */
-#define              MATCH_EN_0_5  0x20       /* Pattern Match Enable Byte 0 Bit 5 */
-#define              MATCH_EN_0_6  0x40       /* Pattern Match Enable Byte 0 Bit 6 */
-#define              MATCH_EN_0_7  0x80       /* Pattern Match Enable Byte 0 Bit 7 */
-#define              MATCH_EN_1_0  0x100      /* Pattern Match Enable Byte 1 Bit 0 */
-#define              MATCH_EN_1_1  0x200      /* Pattern Match Enable Byte 1 Bit 1 */
-#define              MATCH_EN_1_2  0x400      /* Pattern Match Enable Byte 1 Bit 2 */
-#define              MATCH_EN_1_3  0x800      /* Pattern Match Enable Byte 1 Bit 3 */
-#define              MATCH_EN_1_4  0x1000     /* Pattern Match Enable Byte 1 Bit 4 */
-#define              MATCH_EN_1_5  0x2000     /* Pattern Match Enable Byte 1 Bit 5 */
-#define              MATCH_EN_1_6  0x4000     /* Pattern Match Enable Byte 1 Bit 6 */
-#define              MATCH_EN_1_7  0x8000     /* Pattern Match Enable Byte 1 Bit 7 */
-#define              MATCH_EN_2_0  0x10000    /* Pattern Match Enable Byte 2 Bit 0 */
-#define              MATCH_EN_2_1  0x20000    /* Pattern Match Enable Byte 2 Bit 1 */
-#define              MATCH_EN_2_2  0x40000    /* Pattern Match Enable Byte 2 Bit 2 */
-#define              MATCH_EN_2_3  0x80000    /* Pattern Match Enable Byte 2 Bit 3 */
-#define              MATCH_EN_2_4  0x100000   /* Pattern Match Enable Byte 2 Bit 4 */
-#define              MATCH_EN_2_5  0x200000   /* Pattern Match Enable Byte 2 Bit 5 */
-#define              MATCH_EN_2_6  0x400000   /* Pattern Match Enable Byte 2 Bit 6 */
-#define              MATCH_EN_2_7  0x800000   /* Pattern Match Enable Byte 2 Bit 7 */
-#define              MATCH_EN_3_0  0x1000000  /* Pattern Match Enable Byte 3 Bit 0 */
-#define              MATCH_EN_3_1  0x2000000  /* Pattern Match Enable Byte 3 Bit 1 */
-#define              MATCH_EN_3_2  0x4000000  /* Pattern Match Enable Byte 3 Bit 2 */
-#define              MATCH_EN_3_3  0x8000000  /* Pattern Match Enable Byte 3 Bit 3 */
-#define              MATCH_EN_3_4  0x10000000 /* Pattern Match Enable Byte 3 Bit 4 */
-#define              MATCH_EN_3_5  0x20000000 /* Pattern Match Enable Byte 3 Bit 5 */
-#define              MATCH_EN_3_6  0x40000000 /* Pattern Match Enable Byte 3 Bit 6 */
-#define              MATCH_EN_3_7  0x80000000 /* Pattern Match Enable Byte 3 Bit 7 */
-
-/* Bit masks for MXVR_FRAME_CNT_0 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_FRAME_CNT_1 */
-
-#define                      FCNT  0xffff     /* Frame Count */
-
-/* Bit masks for MXVR_ROUTING_0 */
-
-#define                    TX_CH0  0x3f       /* Transmit Channel 0 */
-#define                  MUTE_CH0  0x80       /* Mute Channel 0 */
-#define                    TX_CH1  0x3f00     /* Transmit Channel 0 */
-#define                  MUTE_CH1  0x8000     /* Mute Channel 0 */
-#define                    TX_CH2  0x3f0000   /* Transmit Channel 0 */
-#define                  MUTE_CH2  0x800000   /* Mute Channel 0 */
-#define                    TX_CH3  0x3f000000 /* Transmit Channel 0 */
-#define                  MUTE_CH3  0x80000000 /* Mute Channel 0 */
-
-/* Bit masks for MXVR_ROUTING_1 */
-
-#define                    TX_CH4  0x3f       /* Transmit Channel 4 */
-#define                  MUTE_CH4  0x80       /* Mute Channel 4 */
-#define                    TX_CH5  0x3f00     /* Transmit Channel 5 */
-#define                  MUTE_CH5  0x8000     /* Mute Channel 5 */
-#define                    TX_CH6  0x3f0000   /* Transmit Channel 6 */
-#define                  MUTE_CH6  0x800000   /* Mute Channel 6 */
-#define                    TX_CH7  0x3f000000 /* Transmit Channel 7 */
-#define                  MUTE_CH7  0x80000000 /* Mute Channel 7 */
-
-/* Bit masks for MXVR_ROUTING_2 */
-
-#define                    TX_CH8  0x3f       /* Transmit Channel 8 */
-#define                  MUTE_CH8  0x80       /* Mute Channel 8 */
-#define                    TX_CH9  0x3f00     /* Transmit Channel 9 */
-#define                  MUTE_CH9  0x8000     /* Mute Channel 9 */
-#define                   TX_CH10  0x3f0000   /* Transmit Channel 10 */
-#define                 MUTE_CH10  0x800000   /* Mute Channel 10 */
-#define                   TX_CH11  0x3f000000 /* Transmit Channel 11 */
-#define                 MUTE_CH11  0x80000000 /* Mute Channel 11 */
-
-/* Bit masks for MXVR_ROUTING_3 */
-
-#define                   TX_CH12  0x3f       /* Transmit Channel 12 */
-#define                 MUTE_CH12  0x80       /* Mute Channel 12 */
-#define                   TX_CH13  0x3f00     /* Transmit Channel 13 */
-#define                 MUTE_CH13  0x8000     /* Mute Channel 13 */
-#define                   TX_CH14  0x3f0000   /* Transmit Channel 14 */
-#define                 MUTE_CH14  0x800000   /* Mute Channel 14 */
-#define                   TX_CH15  0x3f000000 /* Transmit Channel 15 */
-#define                 MUTE_CH15  0x80000000 /* Mute Channel 15 */
-
-/* Bit masks for MXVR_ROUTING_4 */
-
-#define                   TX_CH16  0x3f       /* Transmit Channel 16 */
-#define                 MUTE_CH16  0x80       /* Mute Channel 16 */
-#define                   TX_CH17  0x3f00     /* Transmit Channel 17 */
-#define                 MUTE_CH17  0x8000     /* Mute Channel 17 */
-#define                   TX_CH18  0x3f0000   /* Transmit Channel 18 */
-#define                 MUTE_CH18  0x800000   /* Mute Channel 18 */
-#define                   TX_CH19  0x3f000000 /* Transmit Channel 19 */
-#define                 MUTE_CH19  0x80000000 /* Mute Channel 19 */
-
-/* Bit masks for MXVR_ROUTING_5 */
-
-#define                   TX_CH20  0x3f       /* Transmit Channel 20 */
-#define                 MUTE_CH20  0x80       /* Mute Channel 20 */
-#define                   TX_CH21  0x3f00     /* Transmit Channel 21 */
-#define                 MUTE_CH21  0x8000     /* Mute Channel 21 */
-#define                   TX_CH22  0x3f0000   /* Transmit Channel 22 */
-#define                 MUTE_CH22  0x800000   /* Mute Channel 22 */
-#define                   TX_CH23  0x3f000000 /* Transmit Channel 23 */
-#define                 MUTE_CH23  0x80000000 /* Mute Channel 23 */
-
-/* Bit masks for MXVR_ROUTING_6 */
-
-#define                   TX_CH24  0x3f       /* Transmit Channel 24 */
-#define                 MUTE_CH24  0x80       /* Mute Channel 24 */
-#define                   TX_CH25  0x3f00     /* Transmit Channel 25 */
-#define                 MUTE_CH25  0x8000     /* Mute Channel 25 */
-#define                   TX_CH26  0x3f0000   /* Transmit Channel 26 */
-#define                 MUTE_CH26  0x800000   /* Mute Channel 26 */
-#define                   TX_CH27  0x3f000000 /* Transmit Channel 27 */
-#define                 MUTE_CH27  0x80000000 /* Mute Channel 27 */
-
-/* Bit masks for MXVR_ROUTING_7 */
-
-#define                   TX_CH28  0x3f       /* Transmit Channel 28 */
-#define                 MUTE_CH28  0x80       /* Mute Channel 28 */
-#define                   TX_CH29  0x3f00     /* Transmit Channel 29 */
-#define                 MUTE_CH29  0x8000     /* Mute Channel 29 */
-#define                   TX_CH30  0x3f0000   /* Transmit Channel 30 */
-#define                 MUTE_CH30  0x800000   /* Mute Channel 30 */
-#define                   TX_CH31  0x3f000000 /* Transmit Channel 31 */
-#define                 MUTE_CH31  0x80000000 /* Mute Channel 31 */
-
-/* Bit masks for MXVR_ROUTING_8 */
-
-#define                   TX_CH32  0x3f       /* Transmit Channel 32 */
-#define                 MUTE_CH32  0x80       /* Mute Channel 32 */
-#define                   TX_CH33  0x3f00     /* Transmit Channel 33 */
-#define                 MUTE_CH33  0x8000     /* Mute Channel 33 */
-#define                   TX_CH34  0x3f0000   /* Transmit Channel 34 */
-#define                 MUTE_CH34  0x800000   /* Mute Channel 34 */
-#define                   TX_CH35  0x3f000000 /* Transmit Channel 35 */
-#define                 MUTE_CH35  0x80000000 /* Mute Channel 35 */
-
-/* Bit masks for MXVR_ROUTING_9 */
-
-#define                   TX_CH36  0x3f       /* Transmit Channel 36 */
-#define                 MUTE_CH36  0x80       /* Mute Channel 36 */
-#define                   TX_CH37  0x3f00     /* Transmit Channel 37 */
-#define                 MUTE_CH37  0x8000     /* Mute Channel 37 */
-#define                   TX_CH38  0x3f0000   /* Transmit Channel 38 */
-#define                 MUTE_CH38  0x800000   /* Mute Channel 38 */
-#define                   TX_CH39  0x3f000000 /* Transmit Channel 39 */
-#define                 MUTE_CH39  0x80000000 /* Mute Channel 39 */
-
-/* Bit masks for MXVR_ROUTING_10 */
-
-#define                   TX_CH40  0x3f       /* Transmit Channel 40 */
-#define                 MUTE_CH40  0x80       /* Mute Channel 40 */
-#define                   TX_CH41  0x3f00     /* Transmit Channel 41 */
-#define                 MUTE_CH41  0x8000     /* Mute Channel 41 */
-#define                   TX_CH42  0x3f0000   /* Transmit Channel 42 */
-#define                 MUTE_CH42  0x800000   /* Mute Channel 42 */
-#define                   TX_CH43  0x3f000000 /* Transmit Channel 43 */
-#define                 MUTE_CH43  0x80000000 /* Mute Channel 43 */
-
-/* Bit masks for MXVR_ROUTING_11 */
-
-#define                   TX_CH44  0x3f       /* Transmit Channel 44 */
-#define                 MUTE_CH44  0x80       /* Mute Channel 44 */
-#define                   TX_CH45  0x3f00     /* Transmit Channel 45 */
-#define                 MUTE_CH45  0x8000     /* Mute Channel 45 */
-#define                   TX_CH46  0x3f0000   /* Transmit Channel 46 */
-#define                 MUTE_CH46  0x800000   /* Mute Channel 46 */
-#define                   TX_CH47  0x3f000000 /* Transmit Channel 47 */
-#define                 MUTE_CH47  0x80000000 /* Mute Channel 47 */
-
-/* Bit masks for MXVR_ROUTING_12 */
-
-#define                   TX_CH48  0x3f       /* Transmit Channel 48 */
-#define                 MUTE_CH48  0x80       /* Mute Channel 48 */
-#define                   TX_CH49  0x3f00     /* Transmit Channel 49 */
-#define                 MUTE_CH49  0x8000     /* Mute Channel 49 */
-#define                   TX_CH50  0x3f0000   /* Transmit Channel 50 */
-#define                 MUTE_CH50  0x800000   /* Mute Channel 50 */
-#define                   TX_CH51  0x3f000000 /* Transmit Channel 51 */
-#define                 MUTE_CH51  0x80000000 /* Mute Channel 51 */
-
-/* Bit masks for MXVR_ROUTING_13 */
-
-#define                   TX_CH52  0x3f       /* Transmit Channel 52 */
-#define                 MUTE_CH52  0x80       /* Mute Channel 52 */
-#define                   TX_CH53  0x3f00     /* Transmit Channel 53 */
-#define                 MUTE_CH53  0x8000     /* Mute Channel 53 */
-#define                   TX_CH54  0x3f0000   /* Transmit Channel 54 */
-#define                 MUTE_CH54  0x800000   /* Mute Channel 54 */
-#define                   TX_CH55  0x3f000000 /* Transmit Channel 55 */
-#define                 MUTE_CH55  0x80000000 /* Mute Channel 55 */
-
-/* Bit masks for MXVR_ROUTING_14 */
-
-#define                   TX_CH56  0x3f       /* Transmit Channel 56 */
-#define                 MUTE_CH56  0x80       /* Mute Channel 56 */
-#define                   TX_CH57  0x3f00     /* Transmit Channel 57 */
-#define                 MUTE_CH57  0x8000     /* Mute Channel 57 */
-#define                   TX_CH58  0x3f0000   /* Transmit Channel 58 */
-#define                 MUTE_CH58  0x800000   /* Mute Channel 58 */
-#define                   TX_CH59  0x3f000000 /* Transmit Channel 59 */
-#define                 MUTE_CH59  0x80000000 /* Mute Channel 59 */
-
-/* Bit masks for MXVR_BLOCK_CNT */
-
-#define                      BCNT  0xffff     /* Block Count */
-
-/* Bit masks for MXVR_CLK_CTL */
-
-#define                  MXTALCEN  0x1        /* MXVR Crystal Oscillator Clock Enable */
-#define                  MXTALFEN  0x2        /* MXVR Crystal Oscillator Feedback Enable */
-#define                  MXTALMUL  0x30       /* MXVR Crystal Multiplier */
-#define                  CLKX3SEL  0x80       /* Clock Generation Source Select */
-#define                   MMCLKEN  0x100      /* Master Clock Enable */
-#define                  MMCLKMUL  0x1e00     /* Master Clock Multiplication Factor */
-#define                   PLLSMPS  0xe000     /* MXVR PLL State Machine Prescaler */
-#define                   MBCLKEN  0x10000    /* Bit Clock Enable */
-#define                  MBCLKDIV  0x1e0000   /* Bit Clock Divide Factor */
-#define                     INVRX  0x800000   /* Invert Receive Data */
-#define                     MFSEN  0x1000000  /* Frame Sync Enable */
-#define                    MFSDIV  0x1e000000 /* Frame Sync Divide Factor */
-#define                    MFSSEL  0x60000000 /* Frame Sync Select */
-#define                   MFSSYNC  0x80000000 /* Frame Sync Synchronization Select */
-
-/* Bit masks for MXVR_CDRPLL_CTL */
-
-#define                   CDRSMEN  0x1        /* MXVR CDRPLL State Machine Enable */
-#define                   CDRRSTB  0x2        /* MXVR CDRPLL Reset */
-#define                   CDRSVCO  0x4        /* MXVR CDRPLL Start VCO */
-#define                   CDRMODE  0x8        /* MXVR CDRPLL CDR Mode Select */
-#define                   CDRSCNT  0x3f0      /* MXVR CDRPLL Start Counter */
-#define                   CDRLCNT  0xfc00     /* MXVR CDRPLL Lock Counter */
-#define                 CDRSHPSEL  0x3f0000   /* MXVR CDRPLL Shaper Select */
-#define                  CDRSHPEN  0x800000   /* MXVR CDRPLL Shaper Enable */
-#define                  CDRCPSEL  0xff000000 /* MXVR CDRPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_FMPLL_CTL */
-
-#define                    FMSMEN  0x1        /* MXVR FMPLL State Machine Enable */
-#define                    FMRSTB  0x2        /* MXVR FMPLL Reset */
-#define                    FMSVCO  0x4        /* MXVR FMPLL Start VCO */
-#define                    FMSCNT  0x3f0      /* MXVR FMPLL Start Counter */
-#define                    FMLCNT  0xfc00     /* MXVR FMPLL Lock Counter */
-#define                   FMCPSEL  0xff000000 /* MXVR FMPLL Charge Pump Current Select */
-
-/* Bit masks for MXVR_PIN_CTL */
-
-#define                  MTXONBOD  0x1        /* MTXONB Open Drain Select */
-#define                   MTXONBG  0x2        /* MTXONB Gates MTX Select */
-#define                     MFSOE  0x10       /* MFS Output Enable */
-#define                  MFSGPSEL  0x20       /* MFS General Purpose Output Select */
-#define                  MFSGPDAT  0x40       /* MFS General Purpose Output Data */
-
-/* Bit masks for MXVR_SCLK_CNT */
-
-#define                      SCNT  0xffff     /* System Clock Count */
-
-/* Bit masks for KPAD_CTL */
-
-#define                   KPAD_EN  0x1        /* Keypad Enable */
-#define              KPAD_IRQMODE  0x6        /* Key Press Interrupt Enable */
-#define                KPAD_ROWEN  0x1c00     /* Row Enable Width */
-#define                KPAD_COLEN  0xe000     /* Column Enable Width */
-
-/* Bit masks for KPAD_PRESCALE */
-
-#define         KPAD_PRESCALE_VAL  0x3f       /* Key Prescale Value */
-
-/* Bit masks for KPAD_MSEL */
-
-#define                DBON_SCALE  0xff       /* Debounce Scale Value */
-#define              COLDRV_SCALE  0xff00     /* Column Driver Scale Value */
-
-/* Bit masks for KPAD_ROWCOL */
-
-#define                  KPAD_ROW  0xff       /* Rows Pressed */
-#define                  KPAD_COL  0xff00     /* Columns Pressed */
-
-/* Bit masks for KPAD_STAT */
-
-#define                  KPAD_IRQ  0x1        /* Keypad Interrupt Status */
-#define              KPAD_MROWCOL  0x6        /* Multiple Row/Column Keypress Status */
-#define              KPAD_PRESSED  0x8        /* Key press current status */
-
-/* Bit masks for KPAD_SOFTEVAL */
-
-#define           KPAD_SOFTEVAL_E  0x2        /* Software Programmable Force Evaluate */
-
-/* Bit masks for SDH_COMMAND */
-
-#define                   CMD_IDX  0x3f       /* Command Index */
-#define                   CMD_RSP  0x40       /* Response */
-#define                 CMD_L_RSP  0x80       /* Long Response */
-#define                 CMD_INT_E  0x100      /* Command Interrupt */
-#define                CMD_PEND_E  0x200      /* Command Pending */
-#define                     CMD_E  0x400      /* Command Enable */
-
-/* Bit masks for SDH_PWR_CTL */
-
-#define                    PWR_ON  0x3        /* Power On */
-#if 0
-#define                       TBD  0x3c       /* TBD */
-#endif
-#define                 SD_CMD_OD  0x40       /* Open Drain Output */
-#define                   ROD_CTL  0x80       /* Rod Control */
-
-/* Bit masks for SDH_CLK_CTL */
-
-#define                    CLKDIV  0xff       /* MC_CLK Divisor */
-#define                     CLK_E  0x100      /* MC_CLK Bus Clock Enable */
-#define                  PWR_SV_E  0x200      /* Power Save Enable */
-#define             CLKDIV_BYPASS  0x400      /* Bypass Divisor */
-#define                  WIDE_BUS  0x800      /* Wide Bus Mode Enable */
-
-/* Bit masks for SDH_RESP_CMD */
-
-#define                  RESP_CMD  0x3f       /* Response Command */
-
-/* Bit masks for SDH_DATA_CTL */
-
-#define                     DTX_E  0x1        /* Data Transfer Enable */
-#define                   DTX_DIR  0x2        /* Data Transfer Direction */
-#define                  DTX_MODE  0x4        /* Data Transfer Mode */
-#define                 DTX_DMA_E  0x8        /* Data Transfer DMA Enable */
-#define              DTX_BLK_LGTH  0xf0       /* Data Transfer Block Length */
-
-/* Bit masks for SDH_STATUS */
-
-#define              CMD_CRC_FAIL  0x1        /* CMD CRC Fail */
-#define              DAT_CRC_FAIL  0x2        /* Data CRC Fail */
-#define               CMD_TIME_OUT  0x4        /* CMD Time Out */
-#define               DAT_TIME_OUT  0x8        /* Data Time Out */
-#define               TX_UNDERRUN  0x10       /* Transmit Underrun */
-#define                RX_OVERRUN  0x20       /* Receive Overrun */
-#define              CMD_RESP_END  0x40       /* CMD Response End */
-#define                  CMD_SENT  0x80       /* CMD Sent */
-#define                   DAT_END  0x100      /* Data End */
-#define             START_BIT_ERR  0x200      /* Start Bit Error */
-#define               DAT_BLK_END  0x400      /* Data Block End */
-#define                   CMD_ACT  0x800      /* CMD Active */
-#define                    TX_ACT  0x1000     /* Transmit Active */
-#define                    RX_ACT  0x2000     /* Receive Active */
-#define              TX_FIFO_STAT  0x4000     /* Transmit FIFO Status */
-#define              RX_FIFO_STAT  0x8000     /* Receive FIFO Status */
-#define              TX_FIFO_FULL  0x10000    /* Transmit FIFO Full */
-#define              RX_FIFO_FULL  0x20000    /* Receive FIFO Full */
-#define              TX_FIFO_ZERO  0x40000    /* Transmit FIFO Empty */
-#define               RX_DAT_ZERO  0x80000    /* Receive FIFO Empty */
-#define                TX_DAT_RDY  0x100000   /* Transmit Data Available */
-#define               RX_FIFO_RDY  0x200000   /* Receive Data Available */
-
-/* Bit masks for SDH_STATUS_CLR */
-
-#define         CMD_CRC_FAIL_STAT  0x1        /* CMD CRC Fail Status */
-#define         DAT_CRC_FAIL_STAT  0x2        /* Data CRC Fail Status */
-#define          CMD_TIMEOUT_STAT  0x4        /* CMD Time Out Status */
-#define          DAT_TIMEOUT_STAT  0x8        /* Data Time Out status */
-#define          TX_UNDERRUN_STAT  0x10       /* Transmit Underrun Status */
-#define           RX_OVERRUN_STAT  0x20       /* Receive Overrun Status */
-#define         CMD_RESP_END_STAT  0x40       /* CMD Response End Status */
-#define             CMD_SENT_STAT  0x80       /* CMD Sent Status */
-#define              DAT_END_STAT  0x100      /* Data End Status */
-#define        START_BIT_ERR_STAT  0x200      /* Start Bit Error Status */
-#define          DAT_BLK_END_STAT  0x400      /* Data Block End Status */
-
-/* Bit masks for SDH_MASK0 */
-
-#define         CMD_CRC_FAIL_MASK  0x1        /* CMD CRC Fail Mask */
-#define         DAT_CRC_FAIL_MASK  0x2        /* Data CRC Fail Mask */
-#define          CMD_TIMEOUT_MASK  0x4        /* CMD Time Out Mask */
-#define          DAT_TIMEOUT_MASK  0x8        /* Data Time Out Mask */
-#define          TX_UNDERRUN_MASK  0x10       /* Transmit Underrun Mask */
-#define           RX_OVERRUN_MASK  0x20       /* Receive Overrun Mask */
-#define         CMD_RESP_END_MASK  0x40       /* CMD Response End Mask */
-#define             CMD_SENT_MASK  0x80       /* CMD Sent Mask */
-#define              DAT_END_MASK  0x100      /* Data End Mask */
-#define        START_BIT_ERR_MASK  0x200      /* Start Bit Error Mask */
-#define          DAT_BLK_END_MASK  0x400      /* Data Block End Mask */
-#define              CMD_ACT_MASK  0x800      /* CMD Active Mask */
-#define               TX_ACT_MASK  0x1000     /* Transmit Active Mask */
-#define               RX_ACT_MASK  0x2000     /* Receive Active Mask */
-#define         TX_FIFO_STAT_MASK  0x4000     /* Transmit FIFO Status Mask */
-#define         RX_FIFO_STAT_MASK  0x8000     /* Receive FIFO Status Mask */
-#define         TX_FIFO_FULL_MASK  0x10000    /* Transmit FIFO Full Mask */
-#define         RX_FIFO_FULL_MASK  0x20000    /* Receive FIFO Full Mask */
-#define         TX_FIFO_ZERO_MASK  0x40000    /* Transmit FIFO Empty Mask */
-#define          RX_DAT_ZERO_MASK  0x80000    /* Receive FIFO Empty Mask */
-#define           TX_DAT_RDY_MASK  0x100000   /* Transmit Data Available Mask */
-#define          RX_FIFO_RDY_MASK  0x200000   /* Receive Data Available Mask */
-
-/* Bit masks for SDH_FIFO_CNT */
-
-#define                FIFO_COUNT  0x7fff     /* FIFO Count */
-
-/* Bit masks for SDH_E_STATUS */
-
-#define              SDIO_INT_DET  0x2        /* SDIO Int Detected */
-#define               SD_CARD_DET  0x10       /* SD Card Detect */
-
-/* Bit masks for SDH_E_MASK */
-
-#define                  SDIO_MSK  0x2        /* Mask SDIO Int Detected */
-#define                   SCD_MSK  0x40       /* Mask Card Detect */
-
-/* Bit masks for SDH_CFG */
-
-#define                   CLKS_EN  0x1        /* Clocks Enable */
-#define                      SD4E  0x4        /* SDIO 4-Bit Enable */
-#define                       MWE  0x8        /* Moving Window Enable */
-#define                    SD_RST  0x10       /* SDMMC Reset */
-#define                 PUP_SDDAT  0x20       /* Pull-up SD_DAT */
-#define                PUP_SDDAT3  0x40       /* Pull-up SD_DAT3 */
-#define                 PD_SDDAT3  0x80       /* Pull-down SD_DAT3 */
-
-/* Bit masks for SDH_RD_WAIT_EN */
-
-#define                       RWR  0x1        /* Read Wait Request */
-
-/* Bit masks for ATAPI_CONTROL */
-
-#define                 PIO_START  0x1        /* Start PIO/Reg Op */
-#define               MULTI_START  0x2        /* Start Multi-DMA Op */
-#define               ULTRA_START  0x4        /* Start Ultra-DMA Op */
-#define                  XFER_DIR  0x8        /* Transfer Direction */
-#define                  IORDY_EN  0x10       /* IORDY Enable */
-#define                FIFO_FLUSH  0x20       /* Flush FIFOs */
-#define                  SOFT_RST  0x40       /* Soft Reset */
-#define                   DEV_RST  0x80       /* Device Reset */
-#define                TFRCNT_RST  0x100      /* Trans Count Reset */
-#define               END_ON_TERM  0x200      /* End/Terminate Select */
-#define               PIO_USE_DMA  0x400      /* PIO-DMA Enable */
-#define          UDMAIN_FIFO_THRS  0xf000     /* Ultra DMA-IN FIFO Threshold */
-
-/* Bit masks for ATAPI_STATUS */
-
-#define               PIO_XFER_ON  0x1        /* PIO transfer in progress */
-#define             MULTI_XFER_ON  0x2        /* Multi-word DMA transfer in progress */
-#define             ULTRA_XFER_ON  0x4        /* Ultra DMA transfer in progress */
-#define               ULTRA_IN_FL  0xf0       /* Ultra DMA Input FIFO Level */
-
-/* Bit masks for ATAPI_DEV_ADDR */
-
-#define                  DEV_ADDR  0x1f       /* Device Address */
-
-/* Bit masks for ATAPI_INT_MASK */
-
-#define        ATAPI_DEV_INT_MASK  0x1        /* Device interrupt mask */
-#define             PIO_DONE_MASK  0x2        /* PIO transfer done interrupt mask */
-#define           MULTI_DONE_MASK  0x4        /* Multi-DMA transfer done interrupt mask */
-#define          UDMAIN_DONE_MASK  0x8        /* Ultra-DMA in transfer done interrupt mask */
-#define         UDMAOUT_DONE_MASK  0x10       /* Ultra-DMA out transfer done interrupt mask */
-#define       HOST_TERM_XFER_MASK  0x20       /* Host terminate current transfer interrupt mask */
-#define           MULTI_TERM_MASK  0x40       /* Device terminate Multi-DMA transfer interrupt mask */
-#define          UDMAIN_TERM_MASK  0x80       /* Device terminate Ultra-DMA-in transfer interrupt mask */
-#define         UDMAOUT_TERM_MASK  0x100      /* Device terminate Ultra-DMA-out transfer interrupt mask */
-
-/* Bit masks for ATAPI_INT_STATUS */
-
-#define             ATAPI_DEV_INT  0x1        /* Device interrupt status */
-#define              PIO_DONE_INT  0x2        /* PIO transfer done interrupt status */
-#define            MULTI_DONE_INT  0x4        /* Multi-DMA transfer done interrupt status */
-#define           UDMAIN_DONE_INT  0x8        /* Ultra-DMA in transfer done interrupt status */
-#define          UDMAOUT_DONE_INT  0x10       /* Ultra-DMA out transfer done interrupt status */
-#define        HOST_TERM_XFER_INT  0x20       /* Host terminate current transfer interrupt status */
-#define            MULTI_TERM_INT  0x40       /* Device terminate Multi-DMA transfer interrupt status */
-#define           UDMAIN_TERM_INT  0x80       /* Device terminate Ultra-DMA-in transfer interrupt status */
-#define          UDMAOUT_TERM_INT  0x100      /* Device terminate Ultra-DMA-out transfer interrupt status */
-
-/* Bit masks for ATAPI_LINE_STATUS */
-
-#define                ATAPI_INTR  0x1        /* Device interrupt to host line status */
-#define                ATAPI_DASP  0x2        /* Device dasp to host line status */
-#define                ATAPI_CS0N  0x4        /* ATAPI chip select 0 line status */
-#define                ATAPI_CS1N  0x8        /* ATAPI chip select 1 line status */
-#define                ATAPI_ADDR  0x70       /* ATAPI address line status */
-#define              ATAPI_DMAREQ  0x80       /* ATAPI DMA request line status */
-#define             ATAPI_DMAACKN  0x100      /* ATAPI DMA acknowledge line status */
-#define               ATAPI_DIOWN  0x200      /* ATAPI write line status */
-#define               ATAPI_DIORN  0x400      /* ATAPI read line status */
-#define               ATAPI_IORDY  0x800      /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_SM_STATE */
-
-#define                PIO_CSTATE  0xf        /* PIO mode state machine current state */
-#define                DMA_CSTATE  0xf0       /* DMA mode state machine current state */
-#define             UDMAIN_CSTATE  0xf00      /* Ultra DMA-In mode state machine current state */
-#define            UDMAOUT_CSTATE  0xf000     /* ATAPI IORDY line status */
-
-/* Bit masks for ATAPI_TERMINATE */
-
-#define           ATAPI_HOST_TERM  0x1        /* Host terminationation */
-
-/* Bit masks for ATAPI_REG_TIM_0 */
-
-#define                    T2_REG  0xff       /* End of cycle time for register access transfers */
-#define                  TEOC_REG  0xff00     /* Selects DIOR/DIOW pulsewidth */
-
-/* Bit masks for ATAPI_PIO_TIM_0 */
-
-#define                    T1_REG  0xf        /* Time from address valid to DIOR/DIOW */
-#define                T2_REG_PIO  0xff0      /* DIOR/DIOW pulsewidth */
-#define                    T4_REG  0xf000     /* DIOW data hold */
-
-/* Bit masks for ATAPI_PIO_TIM_1 */
-
-#define              TEOC_REG_PIO  0xff       /* End of cycle time for PIO access transfers. */
-
-/* Bit masks for ATAPI_MULTI_TIM_0 */
-
-#define                        TD  0xff       /* DIOR/DIOW asserted pulsewidth */
-#define                        TM  0xff00     /* Time from address valid to DIOR/DIOW */
-
-/* Bit masks for ATAPI_MULTI_TIM_1 */
-
-#define                       TKW  0xff       /* Selects DIOW negated pulsewidth */
-#define                       TKR  0xff00     /* Selects DIOR negated pulsewidth */
-
-/* Bit masks for ATAPI_MULTI_TIM_2 */
-
-#define                        TH  0xff       /* Selects DIOW data hold */
-#define                      TEOC  0xff00     /* Selects end of cycle for DMA */
-
-/* Bit masks for ATAPI_ULTRA_TIM_0 */
-
-#define                      TACK  0xff       /* Selects setup and hold times for TACK */
-#define                      TENV  0xff00     /* Selects envelope time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_1 */
-
-#define                      TDVS  0xff       /* Selects data valid setup time */
-#define                 TCYC_TDVS  0xff00     /* Selects cycle time - TDVS time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_2 */
-
-#define                       TSS  0xff       /* Selects time from STROBE edge to negation of DMARQ or assertion of STOP */
-#define                      TMLI  0xff00     /* Selects interlock time */
-
-/* Bit masks for ATAPI_ULTRA_TIM_3 */
-
-#define                      TZAH  0xff       /* Selects minimum delay required for output */
-#define               READY_PAUSE  0xff00     /* Selects ready to pause */
-
-/* Bit masks for TIMER_ENABLE1 */
-
-#define                    TIMEN8  0x1        /* Timer 8 Enable */
-#define                    TIMEN9  0x2        /* Timer 9 Enable */
-#define                   TIMEN10  0x4        /* Timer 10 Enable */
-
-/* Bit masks for TIMER_DISABLE1 */
-
-#define                   TIMDIS8  0x1        /* Timer 8 Disable */
-#define                   TIMDIS9  0x2        /* Timer 9 Disable */
-#define                  TIMDIS10  0x4        /* Timer 10 Disable */
-
-/* Bit masks for TIMER_STATUS1 */
-
-#define                    TIMIL8  0x1        /* Timer 8 Interrupt */
-#define                    TIMIL9  0x2        /* Timer 9 Interrupt */
-#define                   TIMIL10  0x4        /* Timer 10 Interrupt */
-#define                 TOVF_ERR8  0x10       /* Timer 8 Counter Overflow */
-#define                 TOVF_ERR9  0x20       /* Timer 9 Counter Overflow */
-#define                TOVF_ERR10  0x40       /* Timer 10 Counter Overflow */
-#define                     TRUN8  0x1000     /* Timer 8 Slave Enable Status */
-#define                     TRUN9  0x2000     /* Timer 9 Slave Enable Status */
-#define                    TRUN10  0x4000     /* Timer 10 Slave Enable Status */
-
-/* Bit masks for EPPI0 are obtained from common base header for EPPIx (EPPI1 and EPPI2) */
-
-/* Bit masks for USB_FADDR */
-
-#define          FUNCTION_ADDRESS  0x7f       /* Function address */
-
-/* Bit masks for USB_POWER */
-
-#define           ENABLE_SUSPENDM  0x1        /* enable SuspendM output */
-#define              SUSPEND_MODE  0x2        /* Suspend Mode indicator */
-#define               RESUME_MODE  0x4        /* DMA Mode */
-#define                     RESET  0x8        /* Reset indicator */
-#define                   HS_MODE  0x10       /* High Speed mode indicator */
-#define                 HS_ENABLE  0x20       /* high Speed Enable */
-#define                 SOFT_CONN  0x40       /* Soft connect */
-#define                ISO_UPDATE  0x80       /* Isochronous update */
-
-/* Bit masks for USB_INTRTX */
-
-#define                    EP0_TX  0x1        /* Tx Endpoint 0 interrupt */
-#define                    EP1_TX  0x2        /* Tx Endpoint 1 interrupt */
-#define                    EP2_TX  0x4        /* Tx Endpoint 2 interrupt */
-#define                    EP3_TX  0x8        /* Tx Endpoint 3 interrupt */
-#define                    EP4_TX  0x10       /* Tx Endpoint 4 interrupt */
-#define                    EP5_TX  0x20       /* Tx Endpoint 5 interrupt */
-#define                    EP6_TX  0x40       /* Tx Endpoint 6 interrupt */
-#define                    EP7_TX  0x80       /* Tx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRRX */
-
-#define                    EP1_RX  0x2        /* Rx Endpoint 1 interrupt */
-#define                    EP2_RX  0x4        /* Rx Endpoint 2 interrupt */
-#define                    EP3_RX  0x8        /* Rx Endpoint 3 interrupt */
-#define                    EP4_RX  0x10       /* Rx Endpoint 4 interrupt */
-#define                    EP5_RX  0x20       /* Rx Endpoint 5 interrupt */
-#define                    EP6_RX  0x40       /* Rx Endpoint 6 interrupt */
-#define                    EP7_RX  0x80       /* Rx Endpoint 7 interrupt */
-
-/* Bit masks for USB_INTRTXE */
-
-#define                  EP0_TX_E  0x1        /* Endpoint 0 interrupt Enable */
-#define                  EP1_TX_E  0x2        /* Tx Endpoint 1 interrupt  Enable */
-#define                  EP2_TX_E  0x4        /* Tx Endpoint 2 interrupt  Enable */
-#define                  EP3_TX_E  0x8        /* Tx Endpoint 3 interrupt  Enable */
-#define                  EP4_TX_E  0x10       /* Tx Endpoint 4 interrupt  Enable */
-#define                  EP5_TX_E  0x20       /* Tx Endpoint 5 interrupt  Enable */
-#define                  EP6_TX_E  0x40       /* Tx Endpoint 6 interrupt  Enable */
-#define                  EP7_TX_E  0x80       /* Tx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRRXE */
-
-#define                  EP1_RX_E  0x2        /* Rx Endpoint 1 interrupt  Enable */
-#define                  EP2_RX_E  0x4        /* Rx Endpoint 2 interrupt  Enable */
-#define                  EP3_RX_E  0x8        /* Rx Endpoint 3 interrupt  Enable */
-#define                  EP4_RX_E  0x10       /* Rx Endpoint 4 interrupt  Enable */
-#define                  EP5_RX_E  0x20       /* Rx Endpoint 5 interrupt  Enable */
-#define                  EP6_RX_E  0x40       /* Rx Endpoint 6 interrupt  Enable */
-#define                  EP7_RX_E  0x80       /* Rx Endpoint 7 interrupt  Enable */
-
-/* Bit masks for USB_INTRUSB */
-
-#define                 SUSPEND_B  0x1        /* Suspend indicator */
-#define                  RESUME_B  0x2        /* Resume indicator */
-#define          RESET_OR_BABLE_B  0x4        /* Reset/babble indicator */
-#define                     SOF_B  0x8        /* Start of frame */
-#define                    CONN_B  0x10       /* Connection indicator */
-#define                  DISCON_B  0x20       /* Disconnect indicator */
-#define             SESSION_REQ_B  0x40       /* Session Request */
-#define              VBUS_ERROR_B  0x80       /* Vbus threshold indicator */
-
-/* Bit masks for USB_INTRUSBE */
-
-#define                SUSPEND_BE  0x1        /* Suspend indicator int enable */
-#define                 RESUME_BE  0x2        /* Resume indicator int enable */
-#define         RESET_OR_BABLE_BE  0x4        /* Reset/babble indicator int enable */
-#define                    SOF_BE  0x8        /* Start of frame int enable */
-#define                   CONN_BE  0x10       /* Connection indicator int enable */
-#define                 DISCON_BE  0x20       /* Disconnect indicator int enable */
-#define            SESSION_REQ_BE  0x40       /* Session Request int enable */
-#define             VBUS_ERROR_BE  0x80       /* Vbus threshold indicator int enable */
-
-/* Bit masks for USB_FRAME */
-
-#define              FRAME_NUMBER  0x7ff      /* Frame number */
-
-/* Bit masks for USB_INDEX */
-
-#define         SELECTED_ENDPOINT  0xf        /* selected endpoint */
-
-/* Bit masks for USB_GLOBAL_CTL */
-
-#define                GLOBAL_ENA  0x1        /* enables USB module */
-#define                EP1_TX_ENA  0x2        /* Transmit endpoint 1 enable */
-#define                EP2_TX_ENA  0x4        /* Transmit endpoint 2 enable */
-#define                EP3_TX_ENA  0x8        /* Transmit endpoint 3 enable */
-#define                EP4_TX_ENA  0x10       /* Transmit endpoint 4 enable */
-#define                EP5_TX_ENA  0x20       /* Transmit endpoint 5 enable */
-#define                EP6_TX_ENA  0x40       /* Transmit endpoint 6 enable */
-#define                EP7_TX_ENA  0x80       /* Transmit endpoint 7 enable */
-#define                EP1_RX_ENA  0x100      /* Receive endpoint 1 enable */
-#define                EP2_RX_ENA  0x200      /* Receive endpoint 2 enable */
-#define                EP3_RX_ENA  0x400      /* Receive endpoint 3 enable */
-#define                EP4_RX_ENA  0x800      /* Receive endpoint 4 enable */
-#define                EP5_RX_ENA  0x1000     /* Receive endpoint 5 enable */
-#define                EP6_RX_ENA  0x2000     /* Receive endpoint 6 enable */
-#define                EP7_RX_ENA  0x4000     /* Receive endpoint 7 enable */
-
-/* Bit masks for USB_OTG_DEV_CTL */
-
-#define                   SESSION  0x1        /* session indicator */
-#define                  HOST_REQ  0x2        /* Host negotiation request */
-#define                 HOST_MODE  0x4        /* indicates USBDRC is a host */
-#define                     VBUS0  0x8        /* Vbus level indicator[0] */
-#define                     VBUS1  0x10       /* Vbus level indicator[1] */
-#define                     LSDEV  0x20       /* Low-speed indicator */
-#define                     FSDEV  0x40       /* Full or High-speed indicator */
-#define                  B_DEVICE  0x80       /* A' or 'B' device indicator */
-
-/* Bit masks for USB_OTG_VBUS_IRQ */
-
-#define             DRIVE_VBUS_ON  0x1        /* indicator to drive VBUS control circuit */
-#define            DRIVE_VBUS_OFF  0x2        /* indicator to shut off charge pump */
-#define           CHRG_VBUS_START  0x4        /* indicator for external circuit to start charging VBUS */
-#define             CHRG_VBUS_END  0x8        /* indicator for external circuit to end charging VBUS */
-#define        DISCHRG_VBUS_START  0x10       /* indicator to start discharging VBUS */
-#define          DISCHRG_VBUS_END  0x20       /* indicator to stop discharging VBUS */
-
-/* Bit masks for USB_OTG_VBUS_MASK */
-
-#define         DRIVE_VBUS_ON_ENA  0x1        /* enable DRIVE_VBUS_ON interrupt */
-#define        DRIVE_VBUS_OFF_ENA  0x2        /* enable DRIVE_VBUS_OFF interrupt */
-#define       CHRG_VBUS_START_ENA  0x4        /* enable CHRG_VBUS_START interrupt */
-#define         CHRG_VBUS_END_ENA  0x8        /* enable CHRG_VBUS_END interrupt */
-#define    DISCHRG_VBUS_START_ENA  0x10       /* enable DISCHRG_VBUS_START interrupt */
-#define      DISCHRG_VBUS_END_ENA  0x20       /* enable DISCHRG_VBUS_END interrupt */
-
-/* Bit masks for USB_CSR0 */
-
-#define                  RXPKTRDY  0x1        /* data packet receive indicator */
-#define                  TXPKTRDY  0x2        /* data packet in FIFO indicator */
-#define                STALL_SENT  0x4        /* STALL handshake sent */
-#define                   DATAEND  0x8        /* Data end indicator */
-#define                  SETUPEND  0x10       /* Setup end */
-#define                 SENDSTALL  0x20       /* Send STALL handshake */
-#define         SERVICED_RXPKTRDY  0x40       /* used to clear the RxPktRdy bit */
-#define         SERVICED_SETUPEND  0x80       /* used to clear the SetupEnd bit */
-#define                 FLUSHFIFO  0x100      /* flush endpoint FIFO */
-#define          STALL_RECEIVED_H  0x4        /* STALL handshake received host mode */
-#define                SETUPPKT_H  0x8        /* send Setup token host mode */
-#define                   ERROR_H  0x10       /* timeout error indicator host mode */
-#define                  REQPKT_H  0x20       /* Request an IN transaction host mode */
-#define               STATUSPKT_H  0x40       /* Status stage transaction host mode */
-#define             NAK_TIMEOUT_H  0x80       /* EP0 halted after a NAK host mode */
-
-/* Bit masks for USB_COUNT0 */
-
-#define              EP0_RX_COUNT  0x7f       /* number of received bytes in EP0 FIFO */
-
-/* Bit masks for USB_NAKLIMIT0 */
-
-#define             EP0_NAK_LIMIT  0x1f       /* number of frames/micro frames after which EP0 timeouts */
-
-/* Bit masks for USB_TX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_T  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_RX_MAX_PACKET */
-
-#define         MAX_PACKET_SIZE_R  0x7ff      /* maximum data pay load in a frame */
-
-/* Bit masks for USB_TXCSR */
-
-#define                TXPKTRDY_T  0x1        /* data packet in FIFO indicator */
-#define          FIFO_NOT_EMPTY_T  0x2        /* FIFO not empty */
-#define                UNDERRUN_T  0x4        /* TxPktRdy not set  for an IN token */
-#define               FLUSHFIFO_T  0x8        /* flush endpoint FIFO */
-#define              STALL_SEND_T  0x10       /* issue a Stall handshake */
-#define              STALL_SENT_T  0x20       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_T  0x40       /* clear endpoint data toggle */
-#define                INCOMPTX_T  0x80       /* indicates that a large packet is split */
-#define              DMAREQMODE_T  0x400      /* DMA mode (0 or 1) selection */
-#define        FORCE_DATATOGGLE_T  0x800      /* Force data toggle */
-#define              DMAREQ_ENA_T  0x1000     /* Enable DMA request for Tx EP */
-#define                     ISO_T  0x4000     /* enable Isochronous transfers */
-#define                 AUTOSET_T  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_TH  0x4        /* error condition host mode */
-#define         STALL_RECEIVED_TH  0x20       /* Stall handshake received host mode */
-#define            NAK_TIMEOUT_TH  0x80       /* NAK timeout host mode */
-
-/* Bit masks for USB_TXCOUNT */
-
-#define                  TX_COUNT  0x1fff     /* Number of bytes to be written to the selected endpoint Tx FIFO */
-
-/* Bit masks for USB_RXCSR */
-
-#define                RXPKTRDY_R  0x1        /* data packet in FIFO indicator */
-#define               FIFO_FULL_R  0x2        /* FIFO not empty */
-#define                 OVERRUN_R  0x4        /* TxPktRdy not set  for an IN token */
-#define               DATAERROR_R  0x8        /* Out packet cannot be loaded into Rx  FIFO */
-#define               FLUSHFIFO_R  0x10       /* flush endpoint FIFO */
-#define              STALL_SEND_R  0x20       /* issue a Stall handshake */
-#define              STALL_SENT_R  0x40       /* Stall handshake transmitted */
-#define        CLEAR_DATATOGGLE_R  0x80       /* clear endpoint data toggle */
-#define                INCOMPRX_R  0x100      /* indicates that a large packet is split */
-#define              DMAREQMODE_R  0x800      /* DMA mode (0 or 1) selection */
-#define                 DISNYET_R  0x1000     /* disable Nyet handshakes */
-#define              DMAREQ_ENA_R  0x2000     /* Enable DMA request for Tx EP */
-#define                     ISO_R  0x4000     /* enable Isochronous transfers */
-#define               AUTOCLEAR_R  0x8000     /* allows TxPktRdy to be set automatically */
-#define                  ERROR_RH  0x4        /* TxPktRdy not set  for an IN token host mode */
-#define                 REQPKT_RH  0x20       /* request an IN transaction host mode */
-#define         STALL_RECEIVED_RH  0x40       /* Stall handshake received host mode */
-#define               INCOMPRX_RH  0x100      /* indicates that a large packet is split host mode */
-#define             DMAREQMODE_RH  0x800      /* DMA mode (0 or 1) selection host mode */
-#define                AUTOREQ_RH  0x4000     /* sets ReqPkt automatically host mode */
-
-/* Bit masks for USB_RXCOUNT */
-
-#define                  RX_COUNT  0x1fff     /* Number of received bytes in the packet in the Rx FIFO */
-
-/* Bit masks for USB_TXTYPE */
-
-#define            TARGET_EP_NO_T  0xf        /* EP number */
-#define                PROTOCOL_T  0xc        /* transfer type */
-
-/* Bit masks for USB_TXINTERVAL */
-
-#define          TX_POLL_INTERVAL  0xff       /* polling interval for selected Tx EP */
-
-/* Bit masks for USB_RXTYPE */
-
-#define            TARGET_EP_NO_R  0xf        /* EP number */
-#define                PROTOCOL_R  0xc        /* transfer type */
-
-/* Bit masks for USB_RXINTERVAL */
-
-#define          RX_POLL_INTERVAL  0xff       /* polling interval for selected Rx EP */
-
-/* Bit masks for USB_DMA_INTERRUPT */
-
-#define                  DMA0_INT  0x1        /* DMA0 pending interrupt */
-#define                  DMA1_INT  0x2        /* DMA1 pending interrupt */
-#define                  DMA2_INT  0x4        /* DMA2 pending interrupt */
-#define                  DMA3_INT  0x8        /* DMA3 pending interrupt */
-#define                  DMA4_INT  0x10       /* DMA4 pending interrupt */
-#define                  DMA5_INT  0x20       /* DMA5 pending interrupt */
-#define                  DMA6_INT  0x40       /* DMA6 pending interrupt */
-#define                  DMA7_INT  0x80       /* DMA7 pending interrupt */
-
-/* Bit masks for USB_DMAxCONTROL */
-
-#define                   DMA_ENA  0x1        /* DMA enable */
-#define                 DIRECTION  0x2        /* direction of DMA transfer */
-#define                      MODE  0x4        /* DMA Bus error */
-#define                   INT_ENA  0x8        /* Interrupt enable */
-#define                     EPNUM  0xf0       /* EP number */
-#define                  BUSERROR  0x100      /* DMA Bus error */
-
-/* Bit masks for USB_DMAxADDRHIGH */
-
-#define             DMA_ADDR_HIGH  0xffff     /* Upper 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxADDRLOW */
-
-#define              DMA_ADDR_LOW  0xffff     /* Lower 16-bits of memory source/destination address for the DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTHIGH */
-
-#define            DMA_COUNT_HIGH  0xffff     /* Upper 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for USB_DMAxCOUNTLOW */
-
-#define             DMA_COUNT_LOW  0xffff     /* Lower 16-bits of byte count of DMA transfer for DMA master channel */
-
-/* Bit masks for HMDMAx_CONTROL */
-
-#define                   HMDMAEN  0x1        /* Handshake MDMA Enable */
-#define                       REP  0x2        /* Handshake MDMA Request Polarity */
-#define                       UTE  0x8        /* Urgency Threshold Enable */
-#define                       OIE  0x10       /* Overflow Interrupt Enable */
-#define                      BDIE  0x20       /* Block Done Interrupt Enable */
-#define                      MBDI  0x40       /* Mask Block Done Interrupt */
-#define                       DRQ  0x300      /* Handshake MDMA Request Type */
-#define                       RBC  0x1000     /* Force Reload of BCOUNT */
-#define                        PS  0x2000     /* Pin Status */
-#define                        OI  0x4000     /* Overflow Interrupt Generated */
-#define                       BDI  0x8000     /* Block Done Interrupt Generated */
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* ************************ */
-/*   MXVR Address Offsets   */
-/* ************************ */
-
-/* Control Message Receive Buffer (CMRB) Address Offsets */
-
-#define CMRB_STRIDE       0x00000016lu
-
-#define CMRB_DST_OFFSET   0x00000000lu
-#define CMRB_SRC_OFFSET   0x00000002lu
-#define CMRB_DATA_OFFSET  0x00000005lu
-
-/* Control Message Transmit Buffer (CMTB) Address Offsets */
-
-#define CMTB_PRIO_OFFSET    0x00000000lu
-#define CMTB_DST_OFFSET     0x00000002lu
-#define CMTB_SRC_OFFSET     0x00000004lu
-#define CMTB_TYPE_OFFSET    0x00000006lu
-#define CMTB_DATA_OFFSET    0x00000007lu
-
-#define CMTB_ANSWER_OFFSET  0x0000000Alu
-
-#define CMTB_STAT_N_OFFSET  0x00000018lu
-#define CMTB_STAT_A_OFFSET  0x00000016lu
-#define CMTB_STAT_D_OFFSET  0x0000000Elu
-#define CMTB_STAT_R_OFFSET  0x00000014lu
-#define CMTB_STAT_W_OFFSET  0x00000014lu
-#define CMTB_STAT_G_OFFSET  0x00000014lu
-
-/* Asynchronous Packet Receive Buffer (APRB) Address Offsets */
-
-#define APRB_STRIDE       0x00000400lu
-
-#define APRB_DST_OFFSET   0x00000000lu
-#define APRB_LEN_OFFSET   0x00000002lu
-#define APRB_SRC_OFFSET   0x00000004lu
-#define APRB_DATA_OFFSET  0x00000006lu
-
-/* Asynchronous Packet Transmit Buffer (APTB) Address Offsets */
-
-#define APTB_PRIO_OFFSET  0x00000000lu
-#define APTB_DST_OFFSET   0x00000002lu
-#define APTB_LEN_OFFSET   0x00000004lu
-#define APTB_SRC_OFFSET   0x00000006lu
-#define APTB_DATA_OFFSET  0x00000008lu
-
-/* Remote Read Buffer (RRDB) Address Offsets */
-
-#define RRDB_WADDR_OFFSET 0x00000100lu
-#define RRDB_WLEN_OFFSET  0x00000101lu
-
-/* **************** */
-/*   MXVR Macros    */
-/* **************** */
-
-/* MXVR_CONFIG Macros */
-
-#define SET_MSB(x)       ( ( (x) & 0xF  ) << 9)
-
-/* MXVR_INT_STAT_1 Macros */
-
-#define DONEX(x)         (0x00000002 << (4 * (x)))
-#define HDONEX(x)        (0x00000001 << (4 * (x)))
-
-/* MXVR_INT_EN_1 Macros */
-
-#define DONEENX(x)       (0x00000002 << (4 * (x)))
-#define HDONEENX(x)      (0x00000001 << (4 * (x)))
-
-/* MXVR_CDRPLL_CTL Macros */
-
-#define SET_CDRSHPSEL(x) ( ( (x) & 0x3F ) << 16)
-
-/* MXVR_FMPLL_CTL Macros */
-
-#define SET_CDRCPSEL(x)  ( ( (x) & 0xFF ) << 24)
-#define SET_FMCPSEL(x)   ( ( (x) & 0xFF ) << 24)
-
-#endif /* _DEF_BF549_H */
diff --git a/include/asm-blackfin/mach-bf548/defBF54x_base.h b/include/asm-blackfin/mach-bf548/defBF54x_base.h
deleted file mode 100644
index e022e896cb18..000000000000
--- a/include/asm-blackfin/mach-bf548/defBF54x_base.h
+++ /dev/null
@@ -1,3956 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/defBF54x_base.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF54X_H
-#define _DEF_BF54X_H
-
-
-/* ************************************************************** */
-/*   SYSTEM & MMR ADDRESS DEFINITIONS COMMON TO ALL ADSP-BF54x    */
-/* ************************************************************** */
-
-/* PLL Registers */
-
-#define                          PLL_CTL  0xffc00000   /* PLL Control Register */
-#define                          PLL_DIV  0xffc00004   /* PLL Divisor Register */
-#define                           VR_CTL  0xffc00008   /* Voltage Regulator Control Register */
-#define                         PLL_STAT  0xffc0000c   /* PLL Status Register */
-#define                      PLL_LOCKCNT  0xffc00010   /* PLL Lock Count Register */
-
-/* Debug/MP/Emulation Registers (0xFFC00014 - 0xFFC00014) */
-
-#define                           CHIPID  0xffc00014
-/* CHIPID Masks */
-#define                   CHIPID_VERSION  0xF0000000
-#define                    CHIPID_FAMILY  0x0FFFF000
-#define               CHIPID_MANUFACTURE  0x00000FFE
-
-/* System Reset and Interrupt Controller (0xFFC00100 - 0xFFC00104) */
-
-#define                            SWRST  0xffc00100   /* Software Reset Register */
-#define                            SYSCR  0xffc00104   /* System Configuration register */
-
-/* SIC Registers */
-
-#define                       SIC_IMASK0  0xffc0010c   /* System Interrupt Mask Register 0 */
-#define                       SIC_IMASK1  0xffc00110   /* System Interrupt Mask Register 1 */
-#define                       SIC_IMASK2  0xffc00114   /* System Interrupt Mask Register 2 */
-#define                         SIC_ISR0  0xffc00118   /* System Interrupt Status Register 0 */
-#define                         SIC_ISR1  0xffc0011c   /* System Interrupt Status Register 1 */
-#define                         SIC_ISR2  0xffc00120   /* System Interrupt Status Register 2 */
-#define                         SIC_IWR0  0xffc00124   /* System Interrupt Wakeup Register 0 */
-#define                         SIC_IWR1  0xffc00128   /* System Interrupt Wakeup Register 1 */
-#define                         SIC_IWR2  0xffc0012c   /* System Interrupt Wakeup Register 2 */
-#define                         SIC_IAR0  0xffc00130   /* System Interrupt Assignment Register 0 */
-#define                         SIC_IAR1  0xffc00134   /* System Interrupt Assignment Register 1 */
-#define                         SIC_IAR2  0xffc00138   /* System Interrupt Assignment Register 2 */
-#define                         SIC_IAR3  0xffc0013c   /* System Interrupt Assignment Register 3 */
-#define                         SIC_IAR4  0xffc00140   /* System Interrupt Assignment Register 4 */
-#define                         SIC_IAR5  0xffc00144   /* System Interrupt Assignment Register 5 */
-#define                         SIC_IAR6  0xffc00148   /* System Interrupt Assignment Register 6 */
-#define                         SIC_IAR7  0xffc0014c   /* System Interrupt Assignment Register 7 */
-#define                         SIC_IAR8  0xffc00150   /* System Interrupt Assignment Register 8 */
-#define                         SIC_IAR9  0xffc00154   /* System Interrupt Assignment Register 9 */
-#define                        SIC_IAR10  0xffc00158   /* System Interrupt Assignment Register 10 */
-#define                        SIC_IAR11  0xffc0015c   /* System Interrupt Assignment Register 11 */
-
-/* Watchdog Timer Registers */
-
-#define                         WDOG_CTL  0xffc00200   /* Watchdog Control Register */
-#define                         WDOG_CNT  0xffc00204   /* Watchdog Count Register */
-#define                        WDOG_STAT  0xffc00208   /* Watchdog Status Register */
-
-/* RTC Registers */
-
-#define                         RTC_STAT  0xffc00300   /* RTC Status Register */
-#define                         RTC_ICTL  0xffc00304   /* RTC Interrupt Control Register */
-#define                        RTC_ISTAT  0xffc00308   /* RTC Interrupt Status Register */
-#define                        RTC_SWCNT  0xffc0030c   /* RTC Stopwatch Count Register */
-#define                        RTC_ALARM  0xffc00310   /* RTC Alarm Register */
-#define                         RTC_PREN  0xffc00314   /* RTC Prescaler Enable Register */
-
-/* UART0 Registers */
-
-#define                        UART0_DLL  0xffc00400   /* Divisor Latch Low Byte */
-#define                        UART0_DLH  0xffc00404   /* Divisor Latch High Byte */
-#define                       UART0_GCTL  0xffc00408   /* Global Control Register */
-#define                        UART0_LCR  0xffc0040c   /* Line Control Register */
-#define                        UART0_MCR  0xffc00410   /* Modem Control Register */
-#define                        UART0_LSR  0xffc00414   /* Line Status Register */
-#define                        UART0_MSR  0xffc00418   /* Modem Status Register */
-#define                        UART0_SCR  0xffc0041c   /* Scratch Register */
-#define                    UART0_IER_SET  0xffc00420   /* Interrupt Enable Register Set */
-#define                  UART0_IER_CLEAR  0xffc00424   /* Interrupt Enable Register Clear */
-#define                        UART0_THR  0xffc00428   /* Transmit Hold Register */
-#define                        UART0_RBR  0xffc0042c   /* Receive Buffer Register */
-
-/* SPI0 Registers */
-
-#define                     SPI0_REGBASE  0xffc00500
-#define                         SPI0_CTL  0xffc00500   /* SPI0 Control Register */
-#define                         SPI0_FLG  0xffc00504   /* SPI0 Flag Register */
-#define                        SPI0_STAT  0xffc00508   /* SPI0 Status Register */
-#define                        SPI0_TDBR  0xffc0050c   /* SPI0 Transmit Data Buffer Register */
-#define                        SPI0_RDBR  0xffc00510   /* SPI0 Receive Data Buffer Register */
-#define                        SPI0_BAUD  0xffc00514   /* SPI0 Baud Rate Register */
-#define                      SPI0_SHADOW  0xffc00518   /* SPI0 Receive Data Buffer Shadow Register */
-
-/* Timer Group of 3 registers are not defined in the shared file because they are not available on the ADSP-BF542 processor */
-
-/* Two Wire Interface Registers (TWI0) */
-
-#define                     TWI0_REGBASE  0xffc00700
-#define                      TWI0_CLKDIV  0xffc00700   /* Clock Divider Register */
-#define                     TWI0_CONTROL  0xffc00704   /* TWI Control Register */
-#define                  TWI0_SLAVE_CTRL  0xffc00708   /* TWI Slave Mode Control Register */
-#define                  TWI0_SLAVE_STAT  0xffc0070c   /* TWI Slave Mode Status Register */
-#define                  TWI0_SLAVE_ADDR  0xffc00710   /* TWI Slave Mode Address Register */
-#define                 TWI0_MASTER_CTRL  0xffc00714   /* TWI Master Mode Control Register */
-#define                 TWI0_MASTER_STAT  0xffc00718   /* TWI Master Mode Status Register */
-#define                 TWI0_MASTER_ADDR  0xffc0071c   /* TWI Master Mode Address Register */
-#define                    TWI0_INT_STAT  0xffc00720   /* TWI Interrupt Status Register */
-#define                    TWI0_INT_MASK  0xffc00724   /* TWI Interrupt Mask Register */
-#define                   TWI0_FIFO_CTRL  0xffc00728   /* TWI FIFO Control Register */
-#define                   TWI0_FIFO_STAT  0xffc0072c   /* TWI FIFO Status Register */
-#define                   TWI0_XMT_DATA8  0xffc00780   /* TWI FIFO Transmit Data Single Byte Register */
-#define                  TWI0_XMT_DATA16  0xffc00784   /* TWI FIFO Transmit Data Double Byte Register */
-#define                   TWI0_RCV_DATA8  0xffc00788   /* TWI FIFO Receive Data Single Byte Register */
-#define                  TWI0_RCV_DATA16  0xffc0078c   /* TWI FIFO Receive Data Double Byte Register */
-
-/* SPORT0 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPORT1 Registers */
-
-#define                      SPORT1_TCR1  0xffc00900   /* SPORT1 Transmit Configuration 1 Register */
-#define                      SPORT1_TCR2  0xffc00904   /* SPORT1 Transmit Configuration 2 Register */
-#define                   SPORT1_TCLKDIV  0xffc00908   /* SPORT1 Transmit Serial Clock Divider Register */
-#define                    SPORT1_TFSDIV  0xffc0090c   /* SPORT1 Transmit Frame Sync Divider Register */
-#define                        SPORT1_TX  0xffc00910   /* SPORT1 Transmit Data Register */
-#define                        SPORT1_RX  0xffc00918   /* SPORT1 Receive Data Register */
-#define                      SPORT1_RCR1  0xffc00920   /* SPORT1 Receive Configuration 1 Register */
-#define                      SPORT1_RCR2  0xffc00924   /* SPORT1 Receive Configuration 2 Register */
-#define                   SPORT1_RCLKDIV  0xffc00928   /* SPORT1 Receive Serial Clock Divider Register */
-#define                    SPORT1_RFSDIV  0xffc0092c   /* SPORT1 Receive Frame Sync Divider Register */
-#define                      SPORT1_STAT  0xffc00930   /* SPORT1 Status Register */
-#define                      SPORT1_CHNL  0xffc00934   /* SPORT1 Current Channel Register */
-#define                     SPORT1_MCMC1  0xffc00938   /* SPORT1 Multi channel Configuration Register 1 */
-#define                     SPORT1_MCMC2  0xffc0093c   /* SPORT1 Multi channel Configuration Register 2 */
-#define                     SPORT1_MTCS0  0xffc00940   /* SPORT1 Multi channel Transmit Select Register 0 */
-#define                     SPORT1_MTCS1  0xffc00944   /* SPORT1 Multi channel Transmit Select Register 1 */
-#define                     SPORT1_MTCS2  0xffc00948   /* SPORT1 Multi channel Transmit Select Register 2 */
-#define                     SPORT1_MTCS3  0xffc0094c   /* SPORT1 Multi channel Transmit Select Register 3 */
-#define                     SPORT1_MRCS0  0xffc00950   /* SPORT1 Multi channel Receive Select Register 0 */
-#define                     SPORT1_MRCS1  0xffc00954   /* SPORT1 Multi channel Receive Select Register 1 */
-#define                     SPORT1_MRCS2  0xffc00958   /* SPORT1 Multi channel Receive Select Register 2 */
-#define                     SPORT1_MRCS3  0xffc0095c   /* SPORT1 Multi channel Receive Select Register 3 */
-
-/* Asynchronous Memory Control Registers */
-
-#define                      EBIU_AMGCTL  0xffc00a00   /* Asynchronous Memory Global Control Register */
-#define                    EBIU_AMBCTL0   0xffc00a04   /* Asynchronous Memory Bank Control Register */
-#define                    EBIU_AMBCTL1   0xffc00a08   /* Asynchronous Memory Bank Control Register */
-#define                      EBIU_MBSCTL  0xffc00a0c   /* Asynchronous Memory Bank Select Control Register */
-#define                     EBIU_ARBSTAT  0xffc00a10   /* Asynchronous Memory Arbiter Status Register */
-#define                        EBIU_MODE  0xffc00a14   /* Asynchronous Mode Control Register */
-#define                        EBIU_FCTL  0xffc00a18   /* Asynchronous Memory Flash Control Register */
-
-/* DDR Memory Control Registers */
-
-#define                     EBIU_DDRCTL0  0xffc00a20   /* DDR Memory Control 0 Register */
-#define                     EBIU_DDRCTL1  0xffc00a24   /* DDR Memory Control 1 Register */
-#define                     EBIU_DDRCTL2  0xffc00a28   /* DDR Memory Control 2 Register */
-#define                     EBIU_DDRCTL3  0xffc00a2c   /* DDR Memory Control 3 Register */
-#define                      EBIU_DDRQUE  0xffc00a30   /* DDR Queue Configuration Register */
-#define                      EBIU_ERRADD  0xffc00a34   /* DDR Error Address Register */
-#define                      EBIU_ERRMST  0xffc00a38   /* DDR Error Master Register */
-#define                      EBIU_RSTCTL  0xffc00a3c   /* DDR Reset Control Register */
-
-/* DDR BankRead and Write Count Registers */
-
-#define                     EBIU_DDRBRC0  0xffc00a60   /* DDR Bank0 Read Count Register */
-#define                     EBIU_DDRBRC1  0xffc00a64   /* DDR Bank1 Read Count Register */
-#define                     EBIU_DDRBRC2  0xffc00a68   /* DDR Bank2 Read Count Register */
-#define                     EBIU_DDRBRC3  0xffc00a6c   /* DDR Bank3 Read Count Register */
-#define                     EBIU_DDRBRC4  0xffc00a70   /* DDR Bank4 Read Count Register */
-#define                     EBIU_DDRBRC5  0xffc00a74   /* DDR Bank5 Read Count Register */
-#define                     EBIU_DDRBRC6  0xffc00a78   /* DDR Bank6 Read Count Register */
-#define                     EBIU_DDRBRC7  0xffc00a7c   /* DDR Bank7 Read Count Register */
-#define                     EBIU_DDRBWC0  0xffc00a80   /* DDR Bank0 Write Count Register */
-#define                     EBIU_DDRBWC1  0xffc00a84   /* DDR Bank1 Write Count Register */
-#define                     EBIU_DDRBWC2  0xffc00a88   /* DDR Bank2 Write Count Register */
-#define                     EBIU_DDRBWC3  0xffc00a8c   /* DDR Bank3 Write Count Register */
-#define                     EBIU_DDRBWC4  0xffc00a90   /* DDR Bank4 Write Count Register */
-#define                     EBIU_DDRBWC5  0xffc00a94   /* DDR Bank5 Write Count Register */
-#define                     EBIU_DDRBWC6  0xffc00a98   /* DDR Bank6 Write Count Register */
-#define                     EBIU_DDRBWC7  0xffc00a9c   /* DDR Bank7 Write Count Register */
-#define                     EBIU_DDRACCT  0xffc00aa0   /* DDR Activation Count Register */
-#define                     EBIU_DDRTACT  0xffc00aa8   /* DDR Turn Around Count Register */
-#define                     EBIU_DDRARCT  0xffc00aac   /* DDR Auto-refresh Count Register */
-#define                      EBIU_DDRGC0  0xffc00ab0   /* DDR Grant Count 0 Register */
-#define                      EBIU_DDRGC1  0xffc00ab4   /* DDR Grant Count 1 Register */
-#define                      EBIU_DDRGC2  0xffc00ab8   /* DDR Grant Count 2 Register */
-#define                      EBIU_DDRGC3  0xffc00abc   /* DDR Grant Count 3 Register */
-#define                     EBIU_DDRMCEN  0xffc00ac0   /* DDR Metrics Counter Enable Register */
-#define                     EBIU_DDRMCCL  0xffc00ac4   /* DDR Metrics Counter Clear Register */
-
-/* DMAC0 Registers */
-
-#define                      DMAC0_TCPER  0xffc00b0c   /* DMA Controller 0 Traffic Control Periods Register */
-#define                      DMAC0_TCCNT  0xffc00b10   /* DMA Controller 0 Current Counts Register */
-
-/* DMA Channel 0 Registers */
-
-#define               DMA0_NEXT_DESC_PTR  0xffc00c00   /* DMA Channel 0 Next Descriptor Pointer Register */
-#define                  DMA0_START_ADDR  0xffc00c04   /* DMA Channel 0 Start Address Register */
-#define                      DMA0_CONFIG  0xffc00c08   /* DMA Channel 0 Configuration Register */
-#define                     DMA0_X_COUNT  0xffc00c10   /* DMA Channel 0 X Count Register */
-#define                    DMA0_X_MODIFY  0xffc00c14   /* DMA Channel 0 X Modify Register */
-#define                     DMA0_Y_COUNT  0xffc00c18   /* DMA Channel 0 Y Count Register */
-#define                    DMA0_Y_MODIFY  0xffc00c1c   /* DMA Channel 0 Y Modify Register */
-#define               DMA0_CURR_DESC_PTR  0xffc00c20   /* DMA Channel 0 Current Descriptor Pointer Register */
-#define                   DMA0_CURR_ADDR  0xffc00c24   /* DMA Channel 0 Current Address Register */
-#define                  DMA0_IRQ_STATUS  0xffc00c28   /* DMA Channel 0 Interrupt/Status Register */
-#define              DMA0_PERIPHERAL_MAP  0xffc00c2c   /* DMA Channel 0 Peripheral Map Register */
-#define                DMA0_CURR_X_COUNT  0xffc00c30   /* DMA Channel 0 Current X Count Register */
-#define                DMA0_CURR_Y_COUNT  0xffc00c38   /* DMA Channel 0 Current Y Count Register */
-
-/* DMA Channel 1 Registers */
-
-#define               DMA1_NEXT_DESC_PTR  0xffc00c40   /* DMA Channel 1 Next Descriptor Pointer Register */
-#define                  DMA1_START_ADDR  0xffc00c44   /* DMA Channel 1 Start Address Register */
-#define                      DMA1_CONFIG  0xffc00c48   /* DMA Channel 1 Configuration Register */
-#define                     DMA1_X_COUNT  0xffc00c50   /* DMA Channel 1 X Count Register */
-#define                    DMA1_X_MODIFY  0xffc00c54   /* DMA Channel 1 X Modify Register */
-#define                     DMA1_Y_COUNT  0xffc00c58   /* DMA Channel 1 Y Count Register */
-#define                    DMA1_Y_MODIFY  0xffc00c5c   /* DMA Channel 1 Y Modify Register */
-#define               DMA1_CURR_DESC_PTR  0xffc00c60   /* DMA Channel 1 Current Descriptor Pointer Register */
-#define                   DMA1_CURR_ADDR  0xffc00c64   /* DMA Channel 1 Current Address Register */
-#define                  DMA1_IRQ_STATUS  0xffc00c68   /* DMA Channel 1 Interrupt/Status Register */
-#define              DMA1_PERIPHERAL_MAP  0xffc00c6c   /* DMA Channel 1 Peripheral Map Register */
-#define                DMA1_CURR_X_COUNT  0xffc00c70   /* DMA Channel 1 Current X Count Register */
-#define                DMA1_CURR_Y_COUNT  0xffc00c78   /* DMA Channel 1 Current Y Count Register */
-
-/* DMA Channel 2 Registers */
-
-#define               DMA2_NEXT_DESC_PTR  0xffc00c80   /* DMA Channel 2 Next Descriptor Pointer Register */
-#define                  DMA2_START_ADDR  0xffc00c84   /* DMA Channel 2 Start Address Register */
-#define                      DMA2_CONFIG  0xffc00c88   /* DMA Channel 2 Configuration Register */
-#define                     DMA2_X_COUNT  0xffc00c90   /* DMA Channel 2 X Count Register */
-#define                    DMA2_X_MODIFY  0xffc00c94   /* DMA Channel 2 X Modify Register */
-#define                     DMA2_Y_COUNT  0xffc00c98   /* DMA Channel 2 Y Count Register */
-#define                    DMA2_Y_MODIFY  0xffc00c9c   /* DMA Channel 2 Y Modify Register */
-#define               DMA2_CURR_DESC_PTR  0xffc00ca0   /* DMA Channel 2 Current Descriptor Pointer Register */
-#define                   DMA2_CURR_ADDR  0xffc00ca4   /* DMA Channel 2 Current Address Register */
-#define                  DMA2_IRQ_STATUS  0xffc00ca8   /* DMA Channel 2 Interrupt/Status Register */
-#define              DMA2_PERIPHERAL_MAP  0xffc00cac   /* DMA Channel 2 Peripheral Map Register */
-#define                DMA2_CURR_X_COUNT  0xffc00cb0   /* DMA Channel 2 Current X Count Register */
-#define                DMA2_CURR_Y_COUNT  0xffc00cb8   /* DMA Channel 2 Current Y Count Register */
-
-/* DMA Channel 3 Registers */
-
-#define               DMA3_NEXT_DESC_PTR  0xffc00cc0   /* DMA Channel 3 Next Descriptor Pointer Register */
-#define                  DMA3_START_ADDR  0xffc00cc4   /* DMA Channel 3 Start Address Register */
-#define                      DMA3_CONFIG  0xffc00cc8   /* DMA Channel 3 Configuration Register */
-#define                     DMA3_X_COUNT  0xffc00cd0   /* DMA Channel 3 X Count Register */
-#define                    DMA3_X_MODIFY  0xffc00cd4   /* DMA Channel 3 X Modify Register */
-#define                     DMA3_Y_COUNT  0xffc00cd8   /* DMA Channel 3 Y Count Register */
-#define                    DMA3_Y_MODIFY  0xffc00cdc   /* DMA Channel 3 Y Modify Register */
-#define               DMA3_CURR_DESC_PTR  0xffc00ce0   /* DMA Channel 3 Current Descriptor Pointer Register */
-#define                   DMA3_CURR_ADDR  0xffc00ce4   /* DMA Channel 3 Current Address Register */
-#define                  DMA3_IRQ_STATUS  0xffc00ce8   /* DMA Channel 3 Interrupt/Status Register */
-#define              DMA3_PERIPHERAL_MAP  0xffc00cec   /* DMA Channel 3 Peripheral Map Register */
-#define                DMA3_CURR_X_COUNT  0xffc00cf0   /* DMA Channel 3 Current X Count Register */
-#define                DMA3_CURR_Y_COUNT  0xffc00cf8   /* DMA Channel 3 Current Y Count Register */
-
-/* DMA Channel 4 Registers */
-
-#define               DMA4_NEXT_DESC_PTR  0xffc00d00   /* DMA Channel 4 Next Descriptor Pointer Register */
-#define                  DMA4_START_ADDR  0xffc00d04   /* DMA Channel 4 Start Address Register */
-#define                      DMA4_CONFIG  0xffc00d08   /* DMA Channel 4 Configuration Register */
-#define                     DMA4_X_COUNT  0xffc00d10   /* DMA Channel 4 X Count Register */
-#define                    DMA4_X_MODIFY  0xffc00d14   /* DMA Channel 4 X Modify Register */
-#define                     DMA4_Y_COUNT  0xffc00d18   /* DMA Channel 4 Y Count Register */
-#define                    DMA4_Y_MODIFY  0xffc00d1c   /* DMA Channel 4 Y Modify Register */
-#define               DMA4_CURR_DESC_PTR  0xffc00d20   /* DMA Channel 4 Current Descriptor Pointer Register */
-#define                   DMA4_CURR_ADDR  0xffc00d24   /* DMA Channel 4 Current Address Register */
-#define                  DMA4_IRQ_STATUS  0xffc00d28   /* DMA Channel 4 Interrupt/Status Register */
-#define              DMA4_PERIPHERAL_MAP  0xffc00d2c   /* DMA Channel 4 Peripheral Map Register */
-#define                DMA4_CURR_X_COUNT  0xffc00d30   /* DMA Channel 4 Current X Count Register */
-#define                DMA4_CURR_Y_COUNT  0xffc00d38   /* DMA Channel 4 Current Y Count Register */
-
-/* DMA Channel 5 Registers */
-
-#define               DMA5_NEXT_DESC_PTR  0xffc00d40   /* DMA Channel 5 Next Descriptor Pointer Register */
-#define                  DMA5_START_ADDR  0xffc00d44   /* DMA Channel 5 Start Address Register */
-#define                      DMA5_CONFIG  0xffc00d48   /* DMA Channel 5 Configuration Register */
-#define                     DMA5_X_COUNT  0xffc00d50   /* DMA Channel 5 X Count Register */
-#define                    DMA5_X_MODIFY  0xffc00d54   /* DMA Channel 5 X Modify Register */
-#define                     DMA5_Y_COUNT  0xffc00d58   /* DMA Channel 5 Y Count Register */
-#define                    DMA5_Y_MODIFY  0xffc00d5c   /* DMA Channel 5 Y Modify Register */
-#define               DMA5_CURR_DESC_PTR  0xffc00d60   /* DMA Channel 5 Current Descriptor Pointer Register */
-#define                   DMA5_CURR_ADDR  0xffc00d64   /* DMA Channel 5 Current Address Register */
-#define                  DMA5_IRQ_STATUS  0xffc00d68   /* DMA Channel 5 Interrupt/Status Register */
-#define              DMA5_PERIPHERAL_MAP  0xffc00d6c   /* DMA Channel 5 Peripheral Map Register */
-#define                DMA5_CURR_X_COUNT  0xffc00d70   /* DMA Channel 5 Current X Count Register */
-#define                DMA5_CURR_Y_COUNT  0xffc00d78   /* DMA Channel 5 Current Y Count Register */
-
-/* DMA Channel 6 Registers */
-
-#define               DMA6_NEXT_DESC_PTR  0xffc00d80   /* DMA Channel 6 Next Descriptor Pointer Register */
-#define                  DMA6_START_ADDR  0xffc00d84   /* DMA Channel 6 Start Address Register */
-#define                      DMA6_CONFIG  0xffc00d88   /* DMA Channel 6 Configuration Register */
-#define                     DMA6_X_COUNT  0xffc00d90   /* DMA Channel 6 X Count Register */
-#define                    DMA6_X_MODIFY  0xffc00d94   /* DMA Channel 6 X Modify Register */
-#define                     DMA6_Y_COUNT  0xffc00d98   /* DMA Channel 6 Y Count Register */
-#define                    DMA6_Y_MODIFY  0xffc00d9c   /* DMA Channel 6 Y Modify Register */
-#define               DMA6_CURR_DESC_PTR  0xffc00da0   /* DMA Channel 6 Current Descriptor Pointer Register */
-#define                   DMA6_CURR_ADDR  0xffc00da4   /* DMA Channel 6 Current Address Register */
-#define                  DMA6_IRQ_STATUS  0xffc00da8   /* DMA Channel 6 Interrupt/Status Register */
-#define              DMA6_PERIPHERAL_MAP  0xffc00dac   /* DMA Channel 6 Peripheral Map Register */
-#define                DMA6_CURR_X_COUNT  0xffc00db0   /* DMA Channel 6 Current X Count Register */
-#define                DMA6_CURR_Y_COUNT  0xffc00db8   /* DMA Channel 6 Current Y Count Register */
-
-/* DMA Channel 7 Registers */
-
-#define               DMA7_NEXT_DESC_PTR  0xffc00dc0   /* DMA Channel 7 Next Descriptor Pointer Register */
-#define                  DMA7_START_ADDR  0xffc00dc4   /* DMA Channel 7 Start Address Register */
-#define                      DMA7_CONFIG  0xffc00dc8   /* DMA Channel 7 Configuration Register */
-#define                     DMA7_X_COUNT  0xffc00dd0   /* DMA Channel 7 X Count Register */
-#define                    DMA7_X_MODIFY  0xffc00dd4   /* DMA Channel 7 X Modify Register */
-#define                     DMA7_Y_COUNT  0xffc00dd8   /* DMA Channel 7 Y Count Register */
-#define                    DMA7_Y_MODIFY  0xffc00ddc   /* DMA Channel 7 Y Modify Register */
-#define               DMA7_CURR_DESC_PTR  0xffc00de0   /* DMA Channel 7 Current Descriptor Pointer Register */
-#define                   DMA7_CURR_ADDR  0xffc00de4   /* DMA Channel 7 Current Address Register */
-#define                  DMA7_IRQ_STATUS  0xffc00de8   /* DMA Channel 7 Interrupt/Status Register */
-#define              DMA7_PERIPHERAL_MAP  0xffc00dec   /* DMA Channel 7 Peripheral Map Register */
-#define                DMA7_CURR_X_COUNT  0xffc00df0   /* DMA Channel 7 Current X Count Register */
-#define                DMA7_CURR_Y_COUNT  0xffc00df8   /* DMA Channel 7 Current Y Count Register */
-
-/* DMA Channel 8 Registers */
-
-#define               DMA8_NEXT_DESC_PTR  0xffc00e00   /* DMA Channel 8 Next Descriptor Pointer Register */
-#define                  DMA8_START_ADDR  0xffc00e04   /* DMA Channel 8 Start Address Register */
-#define                      DMA8_CONFIG  0xffc00e08   /* DMA Channel 8 Configuration Register */
-#define                     DMA8_X_COUNT  0xffc00e10   /* DMA Channel 8 X Count Register */
-#define                    DMA8_X_MODIFY  0xffc00e14   /* DMA Channel 8 X Modify Register */
-#define                     DMA8_Y_COUNT  0xffc00e18   /* DMA Channel 8 Y Count Register */
-#define                    DMA8_Y_MODIFY  0xffc00e1c   /* DMA Channel 8 Y Modify Register */
-#define               DMA8_CURR_DESC_PTR  0xffc00e20   /* DMA Channel 8 Current Descriptor Pointer Register */
-#define                   DMA8_CURR_ADDR  0xffc00e24   /* DMA Channel 8 Current Address Register */
-#define                  DMA8_IRQ_STATUS  0xffc00e28   /* DMA Channel 8 Interrupt/Status Register */
-#define              DMA8_PERIPHERAL_MAP  0xffc00e2c   /* DMA Channel 8 Peripheral Map Register */
-#define                DMA8_CURR_X_COUNT  0xffc00e30   /* DMA Channel 8 Current X Count Register */
-#define                DMA8_CURR_Y_COUNT  0xffc00e38   /* DMA Channel 8 Current Y Count Register */
-
-/* DMA Channel 9 Registers */
-
-#define               DMA9_NEXT_DESC_PTR  0xffc00e40   /* DMA Channel 9 Next Descriptor Pointer Register */
-#define                  DMA9_START_ADDR  0xffc00e44   /* DMA Channel 9 Start Address Register */
-#define                      DMA9_CONFIG  0xffc00e48   /* DMA Channel 9 Configuration Register */
-#define                     DMA9_X_COUNT  0xffc00e50   /* DMA Channel 9 X Count Register */
-#define                    DMA9_X_MODIFY  0xffc00e54   /* DMA Channel 9 X Modify Register */
-#define                     DMA9_Y_COUNT  0xffc00e58   /* DMA Channel 9 Y Count Register */
-#define                    DMA9_Y_MODIFY  0xffc00e5c   /* DMA Channel 9 Y Modify Register */
-#define               DMA9_CURR_DESC_PTR  0xffc00e60   /* DMA Channel 9 Current Descriptor Pointer Register */
-#define                   DMA9_CURR_ADDR  0xffc00e64   /* DMA Channel 9 Current Address Register */
-#define                  DMA9_IRQ_STATUS  0xffc00e68   /* DMA Channel 9 Interrupt/Status Register */
-#define              DMA9_PERIPHERAL_MAP  0xffc00e6c   /* DMA Channel 9 Peripheral Map Register */
-#define                DMA9_CURR_X_COUNT  0xffc00e70   /* DMA Channel 9 Current X Count Register */
-#define                DMA9_CURR_Y_COUNT  0xffc00e78   /* DMA Channel 9 Current Y Count Register */
-
-/* DMA Channel 10 Registers */
-
-#define              DMA10_NEXT_DESC_PTR  0xffc00e80   /* DMA Channel 10 Next Descriptor Pointer Register */
-#define                 DMA10_START_ADDR  0xffc00e84   /* DMA Channel 10 Start Address Register */
-#define                     DMA10_CONFIG  0xffc00e88   /* DMA Channel 10 Configuration Register */
-#define                    DMA10_X_COUNT  0xffc00e90   /* DMA Channel 10 X Count Register */
-#define                   DMA10_X_MODIFY  0xffc00e94   /* DMA Channel 10 X Modify Register */
-#define                    DMA10_Y_COUNT  0xffc00e98   /* DMA Channel 10 Y Count Register */
-#define                   DMA10_Y_MODIFY  0xffc00e9c   /* DMA Channel 10 Y Modify Register */
-#define              DMA10_CURR_DESC_PTR  0xffc00ea0   /* DMA Channel 10 Current Descriptor Pointer Register */
-#define                  DMA10_CURR_ADDR  0xffc00ea4   /* DMA Channel 10 Current Address Register */
-#define                 DMA10_IRQ_STATUS  0xffc00ea8   /* DMA Channel 10 Interrupt/Status Register */
-#define             DMA10_PERIPHERAL_MAP  0xffc00eac   /* DMA Channel 10 Peripheral Map Register */
-#define               DMA10_CURR_X_COUNT  0xffc00eb0   /* DMA Channel 10 Current X Count Register */
-#define               DMA10_CURR_Y_COUNT  0xffc00eb8   /* DMA Channel 10 Current Y Count Register */
-
-/* DMA Channel 11 Registers */
-
-#define              DMA11_NEXT_DESC_PTR  0xffc00ec0   /* DMA Channel 11 Next Descriptor Pointer Register */
-#define                 DMA11_START_ADDR  0xffc00ec4   /* DMA Channel 11 Start Address Register */
-#define                     DMA11_CONFIG  0xffc00ec8   /* DMA Channel 11 Configuration Register */
-#define                    DMA11_X_COUNT  0xffc00ed0   /* DMA Channel 11 X Count Register */
-#define                   DMA11_X_MODIFY  0xffc00ed4   /* DMA Channel 11 X Modify Register */
-#define                    DMA11_Y_COUNT  0xffc00ed8   /* DMA Channel 11 Y Count Register */
-#define                   DMA11_Y_MODIFY  0xffc00edc   /* DMA Channel 11 Y Modify Register */
-#define              DMA11_CURR_DESC_PTR  0xffc00ee0   /* DMA Channel 11 Current Descriptor Pointer Register */
-#define                  DMA11_CURR_ADDR  0xffc00ee4   /* DMA Channel 11 Current Address Register */
-#define                 DMA11_IRQ_STATUS  0xffc00ee8   /* DMA Channel 11 Interrupt/Status Register */
-#define             DMA11_PERIPHERAL_MAP  0xffc00eec   /* DMA Channel 11 Peripheral Map Register */
-#define               DMA11_CURR_X_COUNT  0xffc00ef0   /* DMA Channel 11 Current X Count Register */
-#define               DMA11_CURR_Y_COUNT  0xffc00ef8   /* DMA Channel 11 Current Y Count Register */
-
-/* MDMA Stream 0 Registers */
-
-#define            MDMA_D0_NEXT_DESC_PTR  0xffc00f00   /* Memory DMA Stream 0 Destination Next Descriptor Pointer Register */
-#define               MDMA_D0_START_ADDR  0xffc00f04   /* Memory DMA Stream 0 Destination Start Address Register */
-#define                   MDMA_D0_CONFIG  0xffc00f08   /* Memory DMA Stream 0 Destination Configuration Register */
-#define                  MDMA_D0_X_COUNT  0xffc00f10   /* Memory DMA Stream 0 Destination X Count Register */
-#define                 MDMA_D0_X_MODIFY  0xffc00f14   /* Memory DMA Stream 0 Destination X Modify Register */
-#define                  MDMA_D0_Y_COUNT  0xffc00f18   /* Memory DMA Stream 0 Destination Y Count Register */
-#define                 MDMA_D0_Y_MODIFY  0xffc00f1c   /* Memory DMA Stream 0 Destination Y Modify Register */
-#define            MDMA_D0_CURR_DESC_PTR  0xffc00f20   /* Memory DMA Stream 0 Destination Current Descriptor Pointer Register */
-#define                MDMA_D0_CURR_ADDR  0xffc00f24   /* Memory DMA Stream 0 Destination Current Address Register */
-#define               MDMA_D0_IRQ_STATUS  0xffc00f28   /* Memory DMA Stream 0 Destination Interrupt/Status Register */
-#define           MDMA_D0_PERIPHERAL_MAP  0xffc00f2c   /* Memory DMA Stream 0 Destination Peripheral Map Register */
-#define             MDMA_D0_CURR_X_COUNT  0xffc00f30   /* Memory DMA Stream 0 Destination Current X Count Register */
-#define             MDMA_D0_CURR_Y_COUNT  0xffc00f38   /* Memory DMA Stream 0 Destination Current Y Count Register */
-#define            MDMA_S0_NEXT_DESC_PTR  0xffc00f40   /* Memory DMA Stream 0 Source Next Descriptor Pointer Register */
-#define               MDMA_S0_START_ADDR  0xffc00f44   /* Memory DMA Stream 0 Source Start Address Register */
-#define                   MDMA_S0_CONFIG  0xffc00f48   /* Memory DMA Stream 0 Source Configuration Register */
-#define                  MDMA_S0_X_COUNT  0xffc00f50   /* Memory DMA Stream 0 Source X Count Register */
-#define                 MDMA_S0_X_MODIFY  0xffc00f54   /* Memory DMA Stream 0 Source X Modify Register */
-#define                  MDMA_S0_Y_COUNT  0xffc00f58   /* Memory DMA Stream 0 Source Y Count Register */
-#define                 MDMA_S0_Y_MODIFY  0xffc00f5c   /* Memory DMA Stream 0 Source Y Modify Register */
-#define            MDMA_S0_CURR_DESC_PTR  0xffc00f60   /* Memory DMA Stream 0 Source Current Descriptor Pointer Register */
-#define                MDMA_S0_CURR_ADDR  0xffc00f64   /* Memory DMA Stream 0 Source Current Address Register */
-#define               MDMA_S0_IRQ_STATUS  0xffc00f68   /* Memory DMA Stream 0 Source Interrupt/Status Register */
-#define           MDMA_S0_PERIPHERAL_MAP  0xffc00f6c   /* Memory DMA Stream 0 Source Peripheral Map Register */
-#define             MDMA_S0_CURR_X_COUNT  0xffc00f70   /* Memory DMA Stream 0 Source Current X Count Register */
-#define             MDMA_S0_CURR_Y_COUNT  0xffc00f78   /* Memory DMA Stream 0 Source Current Y Count Register */
-
-/* MDMA Stream 1 Registers */
-
-#define            MDMA_D1_NEXT_DESC_PTR  0xffc00f80   /* Memory DMA Stream 1 Destination Next Descriptor Pointer Register */
-#define               MDMA_D1_START_ADDR  0xffc00f84   /* Memory DMA Stream 1 Destination Start Address Register */
-#define                   MDMA_D1_CONFIG  0xffc00f88   /* Memory DMA Stream 1 Destination Configuration Register */
-#define                  MDMA_D1_X_COUNT  0xffc00f90   /* Memory DMA Stream 1 Destination X Count Register */
-#define                 MDMA_D1_X_MODIFY  0xffc00f94   /* Memory DMA Stream 1 Destination X Modify Register */
-#define                  MDMA_D1_Y_COUNT  0xffc00f98   /* Memory DMA Stream 1 Destination Y Count Register */
-#define                 MDMA_D1_Y_MODIFY  0xffc00f9c   /* Memory DMA Stream 1 Destination Y Modify Register */
-#define            MDMA_D1_CURR_DESC_PTR  0xffc00fa0   /* Memory DMA Stream 1 Destination Current Descriptor Pointer Register */
-#define                MDMA_D1_CURR_ADDR  0xffc00fa4   /* Memory DMA Stream 1 Destination Current Address Register */
-#define               MDMA_D1_IRQ_STATUS  0xffc00fa8   /* Memory DMA Stream 1 Destination Interrupt/Status Register */
-#define           MDMA_D1_PERIPHERAL_MAP  0xffc00fac   /* Memory DMA Stream 1 Destination Peripheral Map Register */
-#define             MDMA_D1_CURR_X_COUNT  0xffc00fb0   /* Memory DMA Stream 1 Destination Current X Count Register */
-#define             MDMA_D1_CURR_Y_COUNT  0xffc00fb8   /* Memory DMA Stream 1 Destination Current Y Count Register */
-#define            MDMA_S1_NEXT_DESC_PTR  0xffc00fc0   /* Memory DMA Stream 1 Source Next Descriptor Pointer Register */
-#define               MDMA_S1_START_ADDR  0xffc00fc4   /* Memory DMA Stream 1 Source Start Address Register */
-#define                   MDMA_S1_CONFIG  0xffc00fc8   /* Memory DMA Stream 1 Source Configuration Register */
-#define                  MDMA_S1_X_COUNT  0xffc00fd0   /* Memory DMA Stream 1 Source X Count Register */
-#define                 MDMA_S1_X_MODIFY  0xffc00fd4   /* Memory DMA Stream 1 Source X Modify Register */
-#define                  MDMA_S1_Y_COUNT  0xffc00fd8   /* Memory DMA Stream 1 Source Y Count Register */
-#define                 MDMA_S1_Y_MODIFY  0xffc00fdc   /* Memory DMA Stream 1 Source Y Modify Register */
-#define            MDMA_S1_CURR_DESC_PTR  0xffc00fe0   /* Memory DMA Stream 1 Source Current Descriptor Pointer Register */
-#define                MDMA_S1_CURR_ADDR  0xffc00fe4   /* Memory DMA Stream 1 Source Current Address Register */
-#define               MDMA_S1_IRQ_STATUS  0xffc00fe8   /* Memory DMA Stream 1 Source Interrupt/Status Register */
-#define           MDMA_S1_PERIPHERAL_MAP  0xffc00fec   /* Memory DMA Stream 1 Source Peripheral Map Register */
-#define             MDMA_S1_CURR_X_COUNT  0xffc00ff0   /* Memory DMA Stream 1 Source Current X Count Register */
-#define             MDMA_S1_CURR_Y_COUNT  0xffc00ff8   /* Memory DMA Stream 1 Source Current Y Count Register */
-
-/* UART3 Registers */
-
-#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
-#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
-#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
-#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
-#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
-#define                        UART3_LSR  0xffc03114   /* Line Status Register */
-#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
-#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
-#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
-#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
-#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
-#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
-
-/* EPPI1 Registers */
-
-#define                     EPPI1_STATUS  0xffc01300   /* EPPI1 Status Register */
-#define                     EPPI1_HCOUNT  0xffc01304   /* EPPI1 Horizontal Transfer Count Register */
-#define                     EPPI1_HDELAY  0xffc01308   /* EPPI1 Horizontal Delay Count Register */
-#define                     EPPI1_VCOUNT  0xffc0130c   /* EPPI1 Vertical Transfer Count Register */
-#define                     EPPI1_VDELAY  0xffc01310   /* EPPI1 Vertical Delay Count Register */
-#define                      EPPI1_FRAME  0xffc01314   /* EPPI1 Lines per Frame Register */
-#define                       EPPI1_LINE  0xffc01318   /* EPPI1 Samples per Line Register */
-#define                     EPPI1_CLKDIV  0xffc0131c   /* EPPI1 Clock Divide Register */
-#define                    EPPI1_CONTROL  0xffc01320   /* EPPI1 Control Register */
-#define                   EPPI1_FS1W_HBL  0xffc01324   /* EPPI1 FS1 Width Register / EPPI1 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI1_FS1P_AVPL  0xffc01328   /* EPPI1 FS1 Period Register / EPPI1 Active Video Samples Per Line Register */
-#define                   EPPI1_FS2W_LVB  0xffc0132c   /* EPPI1 FS2 Width Register / EPPI1 Lines of Vertical Blanking Register */
-#define                  EPPI1_FS2P_LAVF  0xffc01330   /* EPPI1 FS2 Period Register/ EPPI1 Lines of Active Video Per Field Register */
-#define                       EPPI1_CLIP  0xffc01334   /* EPPI1 Clipping Register */
-
-/* Port Interrupt 0 Registers (32-bit) */
-
-#define                   PINT0_MASK_SET  0xffc01400   /* Pin Interrupt 0 Mask Set Register */
-#define                 PINT0_MASK_CLEAR  0xffc01404   /* Pin Interrupt 0 Mask Clear Register */
-#define                    PINT0_REQUEST  0xffc01408   /* Pin Interrupt 0 Interrupt Request Register */
-#define                     PINT0_ASSIGN  0xffc0140c   /* Pin Interrupt 0 Port Assign Register */
-#define                   PINT0_EDGE_SET  0xffc01410   /* Pin Interrupt 0 Edge-sensitivity Set Register */
-#define                 PINT0_EDGE_CLEAR  0xffc01414   /* Pin Interrupt 0 Edge-sensitivity Clear Register */
-#define                 PINT0_INVERT_SET  0xffc01418   /* Pin Interrupt 0 Inversion Set Register */
-#define               PINT0_INVERT_CLEAR  0xffc0141c   /* Pin Interrupt 0 Inversion Clear Register */
-#define                   PINT0_PINSTATE  0xffc01420   /* Pin Interrupt 0 Pin Status Register */
-#define                      PINT0_LATCH  0xffc01424   /* Pin Interrupt 0 Latch Register */
-
-/* Port Interrupt 1 Registers (32-bit) */
-
-#define                   PINT1_MASK_SET  0xffc01430   /* Pin Interrupt 1 Mask Set Register */
-#define                 PINT1_MASK_CLEAR  0xffc01434   /* Pin Interrupt 1 Mask Clear Register */
-#define                    PINT1_REQUEST  0xffc01438   /* Pin Interrupt 1 Interrupt Request Register */
-#define                     PINT1_ASSIGN  0xffc0143c   /* Pin Interrupt 1 Port Assign Register */
-#define                   PINT1_EDGE_SET  0xffc01440   /* Pin Interrupt 1 Edge-sensitivity Set Register */
-#define                 PINT1_EDGE_CLEAR  0xffc01444   /* Pin Interrupt 1 Edge-sensitivity Clear Register */
-#define                 PINT1_INVERT_SET  0xffc01448   /* Pin Interrupt 1 Inversion Set Register */
-#define               PINT1_INVERT_CLEAR  0xffc0144c   /* Pin Interrupt 1 Inversion Clear Register */
-#define                   PINT1_PINSTATE  0xffc01450   /* Pin Interrupt 1 Pin Status Register */
-#define                      PINT1_LATCH  0xffc01454   /* Pin Interrupt 1 Latch Register */
-
-/* Port Interrupt 2 Registers (32-bit) */
-
-#define                   PINT2_MASK_SET  0xffc01460   /* Pin Interrupt 2 Mask Set Register */
-#define                 PINT2_MASK_CLEAR  0xffc01464   /* Pin Interrupt 2 Mask Clear Register */
-#define                    PINT2_REQUEST  0xffc01468   /* Pin Interrupt 2 Interrupt Request Register */
-#define                     PINT2_ASSIGN  0xffc0146c   /* Pin Interrupt 2 Port Assign Register */
-#define                   PINT2_EDGE_SET  0xffc01470   /* Pin Interrupt 2 Edge-sensitivity Set Register */
-#define                 PINT2_EDGE_CLEAR  0xffc01474   /* Pin Interrupt 2 Edge-sensitivity Clear Register */
-#define                 PINT2_INVERT_SET  0xffc01478   /* Pin Interrupt 2 Inversion Set Register */
-#define               PINT2_INVERT_CLEAR  0xffc0147c   /* Pin Interrupt 2 Inversion Clear Register */
-#define                   PINT2_PINSTATE  0xffc01480   /* Pin Interrupt 2 Pin Status Register */
-#define                      PINT2_LATCH  0xffc01484   /* Pin Interrupt 2 Latch Register */
-
-/* Port Interrupt 3 Registers (32-bit) */
-
-#define                   PINT3_MASK_SET  0xffc01490   /* Pin Interrupt 3 Mask Set Register */
-#define                 PINT3_MASK_CLEAR  0xffc01494   /* Pin Interrupt 3 Mask Clear Register */
-#define                    PINT3_REQUEST  0xffc01498   /* Pin Interrupt 3 Interrupt Request Register */
-#define                     PINT3_ASSIGN  0xffc0149c   /* Pin Interrupt 3 Port Assign Register */
-#define                   PINT3_EDGE_SET  0xffc014a0   /* Pin Interrupt 3 Edge-sensitivity Set Register */
-#define                 PINT3_EDGE_CLEAR  0xffc014a4   /* Pin Interrupt 3 Edge-sensitivity Clear Register */
-#define                 PINT3_INVERT_SET  0xffc014a8   /* Pin Interrupt 3 Inversion Set Register */
-#define               PINT3_INVERT_CLEAR  0xffc014ac   /* Pin Interrupt 3 Inversion Clear Register */
-#define                   PINT3_PINSTATE  0xffc014b0   /* Pin Interrupt 3 Pin Status Register */
-#define                      PINT3_LATCH  0xffc014b4   /* Pin Interrupt 3 Latch Register */
-
-/* Port A Registers */
-
-#define                        PORTA_FER  0xffc014c0   /* Function Enable Register */
-#define                            PORTA  0xffc014c4   /* GPIO Data Register */
-#define                        PORTA_SET  0xffc014c8   /* GPIO Data Set Register */
-#define                      PORTA_CLEAR  0xffc014cc   /* GPIO Data Clear Register */
-#define                    PORTA_DIR_SET  0xffc014d0   /* GPIO Direction Set Register */
-#define                  PORTA_DIR_CLEAR  0xffc014d4   /* GPIO Direction Clear Register */
-#define                       PORTA_INEN  0xffc014d8   /* GPIO Input Enable Register */
-#define                        PORTA_MUX  0xffc014dc   /* Multiplexer Control Register */
-
-/* Port B Registers */
-
-#define                        PORTB_FER  0xffc014e0   /* Function Enable Register */
-#define                            PORTB  0xffc014e4   /* GPIO Data Register */
-#define                        PORTB_SET  0xffc014e8   /* GPIO Data Set Register */
-#define                      PORTB_CLEAR  0xffc014ec   /* GPIO Data Clear Register */
-#define                    PORTB_DIR_SET  0xffc014f0   /* GPIO Direction Set Register */
-#define                  PORTB_DIR_CLEAR  0xffc014f4   /* GPIO Direction Clear Register */
-#define                       PORTB_INEN  0xffc014f8   /* GPIO Input Enable Register */
-#define                        PORTB_MUX  0xffc014fc   /* Multiplexer Control Register */
-
-/* Port C Registers */
-
-#define                        PORTC_FER  0xffc01500   /* Function Enable Register */
-#define                            PORTC  0xffc01504   /* GPIO Data Register */
-#define                        PORTC_SET  0xffc01508   /* GPIO Data Set Register */
-#define                      PORTC_CLEAR  0xffc0150c   /* GPIO Data Clear Register */
-#define                    PORTC_DIR_SET  0xffc01510   /* GPIO Direction Set Register */
-#define                  PORTC_DIR_CLEAR  0xffc01514   /* GPIO Direction Clear Register */
-#define                       PORTC_INEN  0xffc01518   /* GPIO Input Enable Register */
-#define                        PORTC_MUX  0xffc0151c   /* Multiplexer Control Register */
-
-/* Port D Registers */
-
-#define                        PORTD_FER  0xffc01520   /* Function Enable Register */
-#define                            PORTD  0xffc01524   /* GPIO Data Register */
-#define                        PORTD_SET  0xffc01528   /* GPIO Data Set Register */
-#define                      PORTD_CLEAR  0xffc0152c   /* GPIO Data Clear Register */
-#define                    PORTD_DIR_SET  0xffc01530   /* GPIO Direction Set Register */
-#define                  PORTD_DIR_CLEAR  0xffc01534   /* GPIO Direction Clear Register */
-#define                       PORTD_INEN  0xffc01538   /* GPIO Input Enable Register */
-#define                        PORTD_MUX  0xffc0153c   /* Multiplexer Control Register */
-
-/* Port E Registers */
-
-#define                        PORTE_FER  0xffc01540   /* Function Enable Register */
-#define                            PORTE  0xffc01544   /* GPIO Data Register */
-#define                        PORTE_SET  0xffc01548   /* GPIO Data Set Register */
-#define                      PORTE_CLEAR  0xffc0154c   /* GPIO Data Clear Register */
-#define                    PORTE_DIR_SET  0xffc01550   /* GPIO Direction Set Register */
-#define                  PORTE_DIR_CLEAR  0xffc01554   /* GPIO Direction Clear Register */
-#define                       PORTE_INEN  0xffc01558   /* GPIO Input Enable Register */
-#define                        PORTE_MUX  0xffc0155c   /* Multiplexer Control Register */
-
-/* Port F Registers */
-
-#define                        PORTF_FER  0xffc01560   /* Function Enable Register */
-#define                            PORTF  0xffc01564   /* GPIO Data Register */
-#define                        PORTF_SET  0xffc01568   /* GPIO Data Set Register */
-#define                      PORTF_CLEAR  0xffc0156c   /* GPIO Data Clear Register */
-#define                    PORTF_DIR_SET  0xffc01570   /* GPIO Direction Set Register */
-#define                  PORTF_DIR_CLEAR  0xffc01574   /* GPIO Direction Clear Register */
-#define                       PORTF_INEN  0xffc01578   /* GPIO Input Enable Register */
-#define                        PORTF_MUX  0xffc0157c   /* Multiplexer Control Register */
-
-/* Port G Registers */
-
-#define                        PORTG_FER  0xffc01580   /* Function Enable Register */
-#define                            PORTG  0xffc01584   /* GPIO Data Register */
-#define                        PORTG_SET  0xffc01588   /* GPIO Data Set Register */
-#define                      PORTG_CLEAR  0xffc0158c   /* GPIO Data Clear Register */
-#define                    PORTG_DIR_SET  0xffc01590   /* GPIO Direction Set Register */
-#define                  PORTG_DIR_CLEAR  0xffc01594   /* GPIO Direction Clear Register */
-#define                       PORTG_INEN  0xffc01598   /* GPIO Input Enable Register */
-#define                        PORTG_MUX  0xffc0159c   /* Multiplexer Control Register */
-
-/* Port H Registers */
-
-#define                        PORTH_FER  0xffc015a0   /* Function Enable Register */
-#define                            PORTH  0xffc015a4   /* GPIO Data Register */
-#define                        PORTH_SET  0xffc015a8   /* GPIO Data Set Register */
-#define                      PORTH_CLEAR  0xffc015ac   /* GPIO Data Clear Register */
-#define                    PORTH_DIR_SET  0xffc015b0   /* GPIO Direction Set Register */
-#define                  PORTH_DIR_CLEAR  0xffc015b4   /* GPIO Direction Clear Register */
-#define                       PORTH_INEN  0xffc015b8   /* GPIO Input Enable Register */
-#define                        PORTH_MUX  0xffc015bc   /* Multiplexer Control Register */
-
-/* Port I Registers */
-
-#define                        PORTI_FER  0xffc015c0   /* Function Enable Register */
-#define                            PORTI  0xffc015c4   /* GPIO Data Register */
-#define                        PORTI_SET  0xffc015c8   /* GPIO Data Set Register */
-#define                      PORTI_CLEAR  0xffc015cc   /* GPIO Data Clear Register */
-#define                    PORTI_DIR_SET  0xffc015d0   /* GPIO Direction Set Register */
-#define                  PORTI_DIR_CLEAR  0xffc015d4   /* GPIO Direction Clear Register */
-#define                       PORTI_INEN  0xffc015d8   /* GPIO Input Enable Register */
-#define                        PORTI_MUX  0xffc015dc   /* Multiplexer Control Register */
-
-/* Port J Registers */
-
-#define                        PORTJ_FER  0xffc015e0   /* Function Enable Register */
-#define                            PORTJ  0xffc015e4   /* GPIO Data Register */
-#define                        PORTJ_SET  0xffc015e8   /* GPIO Data Set Register */
-#define                      PORTJ_CLEAR  0xffc015ec   /* GPIO Data Clear Register */
-#define                    PORTJ_DIR_SET  0xffc015f0   /* GPIO Direction Set Register */
-#define                  PORTJ_DIR_CLEAR  0xffc015f4   /* GPIO Direction Clear Register */
-#define                       PORTJ_INEN  0xffc015f8   /* GPIO Input Enable Register */
-#define                        PORTJ_MUX  0xffc015fc   /* Multiplexer Control Register */
-
-/* PWM Timer Registers */
-
-#define                    TIMER0_CONFIG  0xffc01600   /* Timer 0 Configuration Register */
-#define                   TIMER0_COUNTER  0xffc01604   /* Timer 0 Counter Register */
-#define                    TIMER0_PERIOD  0xffc01608   /* Timer 0 Period Register */
-#define                     TIMER0_WIDTH  0xffc0160c   /* Timer 0 Width Register */
-#define                    TIMER1_CONFIG  0xffc01610   /* Timer 1 Configuration Register */
-#define                   TIMER1_COUNTER  0xffc01614   /* Timer 1 Counter Register */
-#define                    TIMER1_PERIOD  0xffc01618   /* Timer 1 Period Register */
-#define                     TIMER1_WIDTH  0xffc0161c   /* Timer 1 Width Register */
-#define                    TIMER2_CONFIG  0xffc01620   /* Timer 2 Configuration Register */
-#define                   TIMER2_COUNTER  0xffc01624   /* Timer 2 Counter Register */
-#define                    TIMER2_PERIOD  0xffc01628   /* Timer 2 Period Register */
-#define                     TIMER2_WIDTH  0xffc0162c   /* Timer 2 Width Register */
-#define                    TIMER3_CONFIG  0xffc01630   /* Timer 3 Configuration Register */
-#define                   TIMER3_COUNTER  0xffc01634   /* Timer 3 Counter Register */
-#define                    TIMER3_PERIOD  0xffc01638   /* Timer 3 Period Register */
-#define                     TIMER3_WIDTH  0xffc0163c   /* Timer 3 Width Register */
-#define                    TIMER4_CONFIG  0xffc01640   /* Timer 4 Configuration Register */
-#define                   TIMER4_COUNTER  0xffc01644   /* Timer 4 Counter Register */
-#define                    TIMER4_PERIOD  0xffc01648   /* Timer 4 Period Register */
-#define                     TIMER4_WIDTH  0xffc0164c   /* Timer 4 Width Register */
-#define                    TIMER5_CONFIG  0xffc01650   /* Timer 5 Configuration Register */
-#define                   TIMER5_COUNTER  0xffc01654   /* Timer 5 Counter Register */
-#define                    TIMER5_PERIOD  0xffc01658   /* Timer 5 Period Register */
-#define                     TIMER5_WIDTH  0xffc0165c   /* Timer 5 Width Register */
-#define                    TIMER6_CONFIG  0xffc01660   /* Timer 6 Configuration Register */
-#define                   TIMER6_COUNTER  0xffc01664   /* Timer 6 Counter Register */
-#define                    TIMER6_PERIOD  0xffc01668   /* Timer 6 Period Register */
-#define                     TIMER6_WIDTH  0xffc0166c   /* Timer 6 Width Register */
-#define                    TIMER7_CONFIG  0xffc01670   /* Timer 7 Configuration Register */
-#define                   TIMER7_COUNTER  0xffc01674   /* Timer 7 Counter Register */
-#define                    TIMER7_PERIOD  0xffc01678   /* Timer 7 Period Register */
-#define                     TIMER7_WIDTH  0xffc0167c   /* Timer 7 Width Register */
-
-/* Timer Group of 8 */
-
-#define                    TIMER_ENABLE0  0xffc01680   /* Timer Group of 8 Enable Register */
-#define                   TIMER_DISABLE0  0xffc01684   /* Timer Group of 8 Disable Register */
-#define                    TIMER_STATUS0  0xffc01688   /* Timer Group of 8 Status Register */
-
-/* DMAC1 Registers */
-
-#define                      DMAC1_TCPER  0xffc01b0c   /* DMA Controller 1 Traffic Control Periods Register */
-#define                      DMAC1_TCCNT  0xffc01b10   /* DMA Controller 1 Current Counts Register */
-
-/* DMA Channel 12 Registers */
-
-#define              DMA12_NEXT_DESC_PTR  0xffc01c00   /* DMA Channel 12 Next Descriptor Pointer Register */
-#define                 DMA12_START_ADDR  0xffc01c04   /* DMA Channel 12 Start Address Register */
-#define                     DMA12_CONFIG  0xffc01c08   /* DMA Channel 12 Configuration Register */
-#define                    DMA12_X_COUNT  0xffc01c10   /* DMA Channel 12 X Count Register */
-#define                   DMA12_X_MODIFY  0xffc01c14   /* DMA Channel 12 X Modify Register */
-#define                    DMA12_Y_COUNT  0xffc01c18   /* DMA Channel 12 Y Count Register */
-#define                   DMA12_Y_MODIFY  0xffc01c1c   /* DMA Channel 12 Y Modify Register */
-#define              DMA12_CURR_DESC_PTR  0xffc01c20   /* DMA Channel 12 Current Descriptor Pointer Register */
-#define                  DMA12_CURR_ADDR  0xffc01c24   /* DMA Channel 12 Current Address Register */
-#define                 DMA12_IRQ_STATUS  0xffc01c28   /* DMA Channel 12 Interrupt/Status Register */
-#define             DMA12_PERIPHERAL_MAP  0xffc01c2c   /* DMA Channel 12 Peripheral Map Register */
-#define               DMA12_CURR_X_COUNT  0xffc01c30   /* DMA Channel 12 Current X Count Register */
-#define               DMA12_CURR_Y_COUNT  0xffc01c38   /* DMA Channel 12 Current Y Count Register */
-
-/* DMA Channel 13 Registers */
-
-#define              DMA13_NEXT_DESC_PTR  0xffc01c40   /* DMA Channel 13 Next Descriptor Pointer Register */
-#define                 DMA13_START_ADDR  0xffc01c44   /* DMA Channel 13 Start Address Register */
-#define                     DMA13_CONFIG  0xffc01c48   /* DMA Channel 13 Configuration Register */
-#define                    DMA13_X_COUNT  0xffc01c50   /* DMA Channel 13 X Count Register */
-#define                   DMA13_X_MODIFY  0xffc01c54   /* DMA Channel 13 X Modify Register */
-#define                    DMA13_Y_COUNT  0xffc01c58   /* DMA Channel 13 Y Count Register */
-#define                   DMA13_Y_MODIFY  0xffc01c5c   /* DMA Channel 13 Y Modify Register */
-#define              DMA13_CURR_DESC_PTR  0xffc01c60   /* DMA Channel 13 Current Descriptor Pointer Register */
-#define                  DMA13_CURR_ADDR  0xffc01c64   /* DMA Channel 13 Current Address Register */
-#define                 DMA13_IRQ_STATUS  0xffc01c68   /* DMA Channel 13 Interrupt/Status Register */
-#define             DMA13_PERIPHERAL_MAP  0xffc01c6c   /* DMA Channel 13 Peripheral Map Register */
-#define               DMA13_CURR_X_COUNT  0xffc01c70   /* DMA Channel 13 Current X Count Register */
-#define               DMA13_CURR_Y_COUNT  0xffc01c78   /* DMA Channel 13 Current Y Count Register */
-
-/* DMA Channel 14 Registers */
-
-#define              DMA14_NEXT_DESC_PTR  0xffc01c80   /* DMA Channel 14 Next Descriptor Pointer Register */
-#define                 DMA14_START_ADDR  0xffc01c84   /* DMA Channel 14 Start Address Register */
-#define                     DMA14_CONFIG  0xffc01c88   /* DMA Channel 14 Configuration Register */
-#define                    DMA14_X_COUNT  0xffc01c90   /* DMA Channel 14 X Count Register */
-#define                   DMA14_X_MODIFY  0xffc01c94   /* DMA Channel 14 X Modify Register */
-#define                    DMA14_Y_COUNT  0xffc01c98   /* DMA Channel 14 Y Count Register */
-#define                   DMA14_Y_MODIFY  0xffc01c9c   /* DMA Channel 14 Y Modify Register */
-#define              DMA14_CURR_DESC_PTR  0xffc01ca0   /* DMA Channel 14 Current Descriptor Pointer Register */
-#define                  DMA14_CURR_ADDR  0xffc01ca4   /* DMA Channel 14 Current Address Register */
-#define                 DMA14_IRQ_STATUS  0xffc01ca8   /* DMA Channel 14 Interrupt/Status Register */
-#define             DMA14_PERIPHERAL_MAP  0xffc01cac   /* DMA Channel 14 Peripheral Map Register */
-#define               DMA14_CURR_X_COUNT  0xffc01cb0   /* DMA Channel 14 Current X Count Register */
-#define               DMA14_CURR_Y_COUNT  0xffc01cb8   /* DMA Channel 14 Current Y Count Register */
-
-/* DMA Channel 15 Registers */
-
-#define              DMA15_NEXT_DESC_PTR  0xffc01cc0   /* DMA Channel 15 Next Descriptor Pointer Register */
-#define                 DMA15_START_ADDR  0xffc01cc4   /* DMA Channel 15 Start Address Register */
-#define                     DMA15_CONFIG  0xffc01cc8   /* DMA Channel 15 Configuration Register */
-#define                    DMA15_X_COUNT  0xffc01cd0   /* DMA Channel 15 X Count Register */
-#define                   DMA15_X_MODIFY  0xffc01cd4   /* DMA Channel 15 X Modify Register */
-#define                    DMA15_Y_COUNT  0xffc01cd8   /* DMA Channel 15 Y Count Register */
-#define                   DMA15_Y_MODIFY  0xffc01cdc   /* DMA Channel 15 Y Modify Register */
-#define              DMA15_CURR_DESC_PTR  0xffc01ce0   /* DMA Channel 15 Current Descriptor Pointer Register */
-#define                  DMA15_CURR_ADDR  0xffc01ce4   /* DMA Channel 15 Current Address Register */
-#define                 DMA15_IRQ_STATUS  0xffc01ce8   /* DMA Channel 15 Interrupt/Status Register */
-#define             DMA15_PERIPHERAL_MAP  0xffc01cec   /* DMA Channel 15 Peripheral Map Register */
-#define               DMA15_CURR_X_COUNT  0xffc01cf0   /* DMA Channel 15 Current X Count Register */
-#define               DMA15_CURR_Y_COUNT  0xffc01cf8   /* DMA Channel 15 Current Y Count Register */
-
-/* DMA Channel 16 Registers */
-
-#define              DMA16_NEXT_DESC_PTR  0xffc01d00   /* DMA Channel 16 Next Descriptor Pointer Register */
-#define                 DMA16_START_ADDR  0xffc01d04   /* DMA Channel 16 Start Address Register */
-#define                     DMA16_CONFIG  0xffc01d08   /* DMA Channel 16 Configuration Register */
-#define                    DMA16_X_COUNT  0xffc01d10   /* DMA Channel 16 X Count Register */
-#define                   DMA16_X_MODIFY  0xffc01d14   /* DMA Channel 16 X Modify Register */
-#define                    DMA16_Y_COUNT  0xffc01d18   /* DMA Channel 16 Y Count Register */
-#define                   DMA16_Y_MODIFY  0xffc01d1c   /* DMA Channel 16 Y Modify Register */
-#define              DMA16_CURR_DESC_PTR  0xffc01d20   /* DMA Channel 16 Current Descriptor Pointer Register */
-#define                  DMA16_CURR_ADDR  0xffc01d24   /* DMA Channel 16 Current Address Register */
-#define                 DMA16_IRQ_STATUS  0xffc01d28   /* DMA Channel 16 Interrupt/Status Register */
-#define             DMA16_PERIPHERAL_MAP  0xffc01d2c   /* DMA Channel 16 Peripheral Map Register */
-#define               DMA16_CURR_X_COUNT  0xffc01d30   /* DMA Channel 16 Current X Count Register */
-#define               DMA16_CURR_Y_COUNT  0xffc01d38   /* DMA Channel 16 Current Y Count Register */
-
-/* DMA Channel 17 Registers */
-
-#define              DMA17_NEXT_DESC_PTR  0xffc01d40   /* DMA Channel 17 Next Descriptor Pointer Register */
-#define                 DMA17_START_ADDR  0xffc01d44   /* DMA Channel 17 Start Address Register */
-#define                     DMA17_CONFIG  0xffc01d48   /* DMA Channel 17 Configuration Register */
-#define                    DMA17_X_COUNT  0xffc01d50   /* DMA Channel 17 X Count Register */
-#define                   DMA17_X_MODIFY  0xffc01d54   /* DMA Channel 17 X Modify Register */
-#define                    DMA17_Y_COUNT  0xffc01d58   /* DMA Channel 17 Y Count Register */
-#define                   DMA17_Y_MODIFY  0xffc01d5c   /* DMA Channel 17 Y Modify Register */
-#define              DMA17_CURR_DESC_PTR  0xffc01d60   /* DMA Channel 17 Current Descriptor Pointer Register */
-#define                  DMA17_CURR_ADDR  0xffc01d64   /* DMA Channel 17 Current Address Register */
-#define                 DMA17_IRQ_STATUS  0xffc01d68   /* DMA Channel 17 Interrupt/Status Register */
-#define             DMA17_PERIPHERAL_MAP  0xffc01d6c   /* DMA Channel 17 Peripheral Map Register */
-#define               DMA17_CURR_X_COUNT  0xffc01d70   /* DMA Channel 17 Current X Count Register */
-#define               DMA17_CURR_Y_COUNT  0xffc01d78   /* DMA Channel 17 Current Y Count Register */
-
-/* DMA Channel 18 Registers */
-
-#define              DMA18_NEXT_DESC_PTR  0xffc01d80   /* DMA Channel 18 Next Descriptor Pointer Register */
-#define                 DMA18_START_ADDR  0xffc01d84   /* DMA Channel 18 Start Address Register */
-#define                     DMA18_CONFIG  0xffc01d88   /* DMA Channel 18 Configuration Register */
-#define                    DMA18_X_COUNT  0xffc01d90   /* DMA Channel 18 X Count Register */
-#define                   DMA18_X_MODIFY  0xffc01d94   /* DMA Channel 18 X Modify Register */
-#define                    DMA18_Y_COUNT  0xffc01d98   /* DMA Channel 18 Y Count Register */
-#define                   DMA18_Y_MODIFY  0xffc01d9c   /* DMA Channel 18 Y Modify Register */
-#define              DMA18_CURR_DESC_PTR  0xffc01da0   /* DMA Channel 18 Current Descriptor Pointer Register */
-#define                  DMA18_CURR_ADDR  0xffc01da4   /* DMA Channel 18 Current Address Register */
-#define                 DMA18_IRQ_STATUS  0xffc01da8   /* DMA Channel 18 Interrupt/Status Register */
-#define             DMA18_PERIPHERAL_MAP  0xffc01dac   /* DMA Channel 18 Peripheral Map Register */
-#define               DMA18_CURR_X_COUNT  0xffc01db0   /* DMA Channel 18 Current X Count Register */
-#define               DMA18_CURR_Y_COUNT  0xffc01db8   /* DMA Channel 18 Current Y Count Register */
-
-/* DMA Channel 19 Registers */
-
-#define              DMA19_NEXT_DESC_PTR  0xffc01dc0   /* DMA Channel 19 Next Descriptor Pointer Register */
-#define                 DMA19_START_ADDR  0xffc01dc4   /* DMA Channel 19 Start Address Register */
-#define                     DMA19_CONFIG  0xffc01dc8   /* DMA Channel 19 Configuration Register */
-#define                    DMA19_X_COUNT  0xffc01dd0   /* DMA Channel 19 X Count Register */
-#define                   DMA19_X_MODIFY  0xffc01dd4   /* DMA Channel 19 X Modify Register */
-#define                    DMA19_Y_COUNT  0xffc01dd8   /* DMA Channel 19 Y Count Register */
-#define                   DMA19_Y_MODIFY  0xffc01ddc   /* DMA Channel 19 Y Modify Register */
-#define              DMA19_CURR_DESC_PTR  0xffc01de0   /* DMA Channel 19 Current Descriptor Pointer Register */
-#define                  DMA19_CURR_ADDR  0xffc01de4   /* DMA Channel 19 Current Address Register */
-#define                 DMA19_IRQ_STATUS  0xffc01de8   /* DMA Channel 19 Interrupt/Status Register */
-#define             DMA19_PERIPHERAL_MAP  0xffc01dec   /* DMA Channel 19 Peripheral Map Register */
-#define               DMA19_CURR_X_COUNT  0xffc01df0   /* DMA Channel 19 Current X Count Register */
-#define               DMA19_CURR_Y_COUNT  0xffc01df8   /* DMA Channel 19 Current Y Count Register */
-
-/* DMA Channel 20 Registers */
-
-#define              DMA20_NEXT_DESC_PTR  0xffc01e00   /* DMA Channel 20 Next Descriptor Pointer Register */
-#define                 DMA20_START_ADDR  0xffc01e04   /* DMA Channel 20 Start Address Register */
-#define                     DMA20_CONFIG  0xffc01e08   /* DMA Channel 20 Configuration Register */
-#define                    DMA20_X_COUNT  0xffc01e10   /* DMA Channel 20 X Count Register */
-#define                   DMA20_X_MODIFY  0xffc01e14   /* DMA Channel 20 X Modify Register */
-#define                    DMA20_Y_COUNT  0xffc01e18   /* DMA Channel 20 Y Count Register */
-#define                   DMA20_Y_MODIFY  0xffc01e1c   /* DMA Channel 20 Y Modify Register */
-#define              DMA20_CURR_DESC_PTR  0xffc01e20   /* DMA Channel 20 Current Descriptor Pointer Register */
-#define                  DMA20_CURR_ADDR  0xffc01e24   /* DMA Channel 20 Current Address Register */
-#define                 DMA20_IRQ_STATUS  0xffc01e28   /* DMA Channel 20 Interrupt/Status Register */
-#define             DMA20_PERIPHERAL_MAP  0xffc01e2c   /* DMA Channel 20 Peripheral Map Register */
-#define               DMA20_CURR_X_COUNT  0xffc01e30   /* DMA Channel 20 Current X Count Register */
-#define               DMA20_CURR_Y_COUNT  0xffc01e38   /* DMA Channel 20 Current Y Count Register */
-
-/* DMA Channel 21 Registers */
-
-#define              DMA21_NEXT_DESC_PTR  0xffc01e40   /* DMA Channel 21 Next Descriptor Pointer Register */
-#define                 DMA21_START_ADDR  0xffc01e44   /* DMA Channel 21 Start Address Register */
-#define                     DMA21_CONFIG  0xffc01e48   /* DMA Channel 21 Configuration Register */
-#define                    DMA21_X_COUNT  0xffc01e50   /* DMA Channel 21 X Count Register */
-#define                   DMA21_X_MODIFY  0xffc01e54   /* DMA Channel 21 X Modify Register */
-#define                    DMA21_Y_COUNT  0xffc01e58   /* DMA Channel 21 Y Count Register */
-#define                   DMA21_Y_MODIFY  0xffc01e5c   /* DMA Channel 21 Y Modify Register */
-#define              DMA21_CURR_DESC_PTR  0xffc01e60   /* DMA Channel 21 Current Descriptor Pointer Register */
-#define                  DMA21_CURR_ADDR  0xffc01e64   /* DMA Channel 21 Current Address Register */
-#define                 DMA21_IRQ_STATUS  0xffc01e68   /* DMA Channel 21 Interrupt/Status Register */
-#define             DMA21_PERIPHERAL_MAP  0xffc01e6c   /* DMA Channel 21 Peripheral Map Register */
-#define               DMA21_CURR_X_COUNT  0xffc01e70   /* DMA Channel 21 Current X Count Register */
-#define               DMA21_CURR_Y_COUNT  0xffc01e78   /* DMA Channel 21 Current Y Count Register */
-
-/* DMA Channel 22 Registers */
-
-#define              DMA22_NEXT_DESC_PTR  0xffc01e80   /* DMA Channel 22 Next Descriptor Pointer Register */
-#define                 DMA22_START_ADDR  0xffc01e84   /* DMA Channel 22 Start Address Register */
-#define                     DMA22_CONFIG  0xffc01e88   /* DMA Channel 22 Configuration Register */
-#define                    DMA22_X_COUNT  0xffc01e90   /* DMA Channel 22 X Count Register */
-#define                   DMA22_X_MODIFY  0xffc01e94   /* DMA Channel 22 X Modify Register */
-#define                    DMA22_Y_COUNT  0xffc01e98   /* DMA Channel 22 Y Count Register */
-#define                   DMA22_Y_MODIFY  0xffc01e9c   /* DMA Channel 22 Y Modify Register */
-#define              DMA22_CURR_DESC_PTR  0xffc01ea0   /* DMA Channel 22 Current Descriptor Pointer Register */
-#define                  DMA22_CURR_ADDR  0xffc01ea4   /* DMA Channel 22 Current Address Register */
-#define                 DMA22_IRQ_STATUS  0xffc01ea8   /* DMA Channel 22 Interrupt/Status Register */
-#define             DMA22_PERIPHERAL_MAP  0xffc01eac   /* DMA Channel 22 Peripheral Map Register */
-#define               DMA22_CURR_X_COUNT  0xffc01eb0   /* DMA Channel 22 Current X Count Register */
-#define               DMA22_CURR_Y_COUNT  0xffc01eb8   /* DMA Channel 22 Current Y Count Register */
-
-/* DMA Channel 23 Registers */
-
-#define              DMA23_NEXT_DESC_PTR  0xffc01ec0   /* DMA Channel 23 Next Descriptor Pointer Register */
-#define                 DMA23_START_ADDR  0xffc01ec4   /* DMA Channel 23 Start Address Register */
-#define                     DMA23_CONFIG  0xffc01ec8   /* DMA Channel 23 Configuration Register */
-#define                    DMA23_X_COUNT  0xffc01ed0   /* DMA Channel 23 X Count Register */
-#define                   DMA23_X_MODIFY  0xffc01ed4   /* DMA Channel 23 X Modify Register */
-#define                    DMA23_Y_COUNT  0xffc01ed8   /* DMA Channel 23 Y Count Register */
-#define                   DMA23_Y_MODIFY  0xffc01edc   /* DMA Channel 23 Y Modify Register */
-#define              DMA23_CURR_DESC_PTR  0xffc01ee0   /* DMA Channel 23 Current Descriptor Pointer Register */
-#define                  DMA23_CURR_ADDR  0xffc01ee4   /* DMA Channel 23 Current Address Register */
-#define                 DMA23_IRQ_STATUS  0xffc01ee8   /* DMA Channel 23 Interrupt/Status Register */
-#define             DMA23_PERIPHERAL_MAP  0xffc01eec   /* DMA Channel 23 Peripheral Map Register */
-#define               DMA23_CURR_X_COUNT  0xffc01ef0   /* DMA Channel 23 Current X Count Register */
-#define               DMA23_CURR_Y_COUNT  0xffc01ef8   /* DMA Channel 23 Current Y Count Register */
-
-/* MDMA Stream 2 Registers */
-
-#define            MDMA_D2_NEXT_DESC_PTR  0xffc01f00   /* Memory DMA Stream 2 Destination Next Descriptor Pointer Register */
-#define               MDMA_D2_START_ADDR  0xffc01f04   /* Memory DMA Stream 2 Destination Start Address Register */
-#define                   MDMA_D2_CONFIG  0xffc01f08   /* Memory DMA Stream 2 Destination Configuration Register */
-#define                  MDMA_D2_X_COUNT  0xffc01f10   /* Memory DMA Stream 2 Destination X Count Register */
-#define                 MDMA_D2_X_MODIFY  0xffc01f14   /* Memory DMA Stream 2 Destination X Modify Register */
-#define                  MDMA_D2_Y_COUNT  0xffc01f18   /* Memory DMA Stream 2 Destination Y Count Register */
-#define                 MDMA_D2_Y_MODIFY  0xffc01f1c   /* Memory DMA Stream 2 Destination Y Modify Register */
-#define            MDMA_D2_CURR_DESC_PTR  0xffc01f20   /* Memory DMA Stream 2 Destination Current Descriptor Pointer Register */
-#define                MDMA_D2_CURR_ADDR  0xffc01f24   /* Memory DMA Stream 2 Destination Current Address Register */
-#define               MDMA_D2_IRQ_STATUS  0xffc01f28   /* Memory DMA Stream 2 Destination Interrupt/Status Register */
-#define           MDMA_D2_PERIPHERAL_MAP  0xffc01f2c   /* Memory DMA Stream 2 Destination Peripheral Map Register */
-#define             MDMA_D2_CURR_X_COUNT  0xffc01f30   /* Memory DMA Stream 2 Destination Current X Count Register */
-#define             MDMA_D2_CURR_Y_COUNT  0xffc01f38   /* Memory DMA Stream 2 Destination Current Y Count Register */
-#define            MDMA_S2_NEXT_DESC_PTR  0xffc01f40   /* Memory DMA Stream 2 Source Next Descriptor Pointer Register */
-#define               MDMA_S2_START_ADDR  0xffc01f44   /* Memory DMA Stream 2 Source Start Address Register */
-#define                   MDMA_S2_CONFIG  0xffc01f48   /* Memory DMA Stream 2 Source Configuration Register */
-#define                  MDMA_S2_X_COUNT  0xffc01f50   /* Memory DMA Stream 2 Source X Count Register */
-#define                 MDMA_S2_X_MODIFY  0xffc01f54   /* Memory DMA Stream 2 Source X Modify Register */
-#define                  MDMA_S2_Y_COUNT  0xffc01f58   /* Memory DMA Stream 2 Source Y Count Register */
-#define                 MDMA_S2_Y_MODIFY  0xffc01f5c   /* Memory DMA Stream 2 Source Y Modify Register */
-#define            MDMA_S2_CURR_DESC_PTR  0xffc01f60   /* Memory DMA Stream 2 Source Current Descriptor Pointer Register */
-#define                MDMA_S2_CURR_ADDR  0xffc01f64   /* Memory DMA Stream 2 Source Current Address Register */
-#define               MDMA_S2_IRQ_STATUS  0xffc01f68   /* Memory DMA Stream 2 Source Interrupt/Status Register */
-#define           MDMA_S2_PERIPHERAL_MAP  0xffc01f6c   /* Memory DMA Stream 2 Source Peripheral Map Register */
-#define             MDMA_S2_CURR_X_COUNT  0xffc01f70   /* Memory DMA Stream 2 Source Current X Count Register */
-#define             MDMA_S2_CURR_Y_COUNT  0xffc01f78   /* Memory DMA Stream 2 Source Current Y Count Register */
-
-/* MDMA Stream 3 Registers */
-
-#define            MDMA_D3_NEXT_DESC_PTR  0xffc01f80   /* Memory DMA Stream 3 Destination Next Descriptor Pointer Register */
-#define               MDMA_D3_START_ADDR  0xffc01f84   /* Memory DMA Stream 3 Destination Start Address Register */
-#define                   MDMA_D3_CONFIG  0xffc01f88   /* Memory DMA Stream 3 Destination Configuration Register */
-#define                  MDMA_D3_X_COUNT  0xffc01f90   /* Memory DMA Stream 3 Destination X Count Register */
-#define                 MDMA_D3_X_MODIFY  0xffc01f94   /* Memory DMA Stream 3 Destination X Modify Register */
-#define                  MDMA_D3_Y_COUNT  0xffc01f98   /* Memory DMA Stream 3 Destination Y Count Register */
-#define                 MDMA_D3_Y_MODIFY  0xffc01f9c   /* Memory DMA Stream 3 Destination Y Modify Register */
-#define            MDMA_D3_CURR_DESC_PTR  0xffc01fa0   /* Memory DMA Stream 3 Destination Current Descriptor Pointer Register */
-#define                MDMA_D3_CURR_ADDR  0xffc01fa4   /* Memory DMA Stream 3 Destination Current Address Register */
-#define               MDMA_D3_IRQ_STATUS  0xffc01fa8   /* Memory DMA Stream 3 Destination Interrupt/Status Register */
-#define           MDMA_D3_PERIPHERAL_MAP  0xffc01fac   /* Memory DMA Stream 3 Destination Peripheral Map Register */
-#define             MDMA_D3_CURR_X_COUNT  0xffc01fb0   /* Memory DMA Stream 3 Destination Current X Count Register */
-#define             MDMA_D3_CURR_Y_COUNT  0xffc01fb8   /* Memory DMA Stream 3 Destination Current Y Count Register */
-#define            MDMA_S3_NEXT_DESC_PTR  0xffc01fc0   /* Memory DMA Stream 3 Source Next Descriptor Pointer Register */
-#define               MDMA_S3_START_ADDR  0xffc01fc4   /* Memory DMA Stream 3 Source Start Address Register */
-#define                   MDMA_S3_CONFIG  0xffc01fc8   /* Memory DMA Stream 3 Source Configuration Register */
-#define                  MDMA_S3_X_COUNT  0xffc01fd0   /* Memory DMA Stream 3 Source X Count Register */
-#define                 MDMA_S3_X_MODIFY  0xffc01fd4   /* Memory DMA Stream 3 Source X Modify Register */
-#define                  MDMA_S3_Y_COUNT  0xffc01fd8   /* Memory DMA Stream 3 Source Y Count Register */
-#define                 MDMA_S3_Y_MODIFY  0xffc01fdc   /* Memory DMA Stream 3 Source Y Modify Register */
-#define            MDMA_S3_CURR_DESC_PTR  0xffc01fe0   /* Memory DMA Stream 3 Source Current Descriptor Pointer Register */
-#define                MDMA_S3_CURR_ADDR  0xffc01fe4   /* Memory DMA Stream 3 Source Current Address Register */
-#define               MDMA_S3_IRQ_STATUS  0xffc01fe8   /* Memory DMA Stream 3 Source Interrupt/Status Register */
-#define           MDMA_S3_PERIPHERAL_MAP  0xffc01fec   /* Memory DMA Stream 3 Source Peripheral Map Register */
-#define             MDMA_S3_CURR_X_COUNT  0xffc01ff0   /* Memory DMA Stream 3 Source Current X Count Register */
-#define             MDMA_S3_CURR_Y_COUNT  0xffc01ff8   /* Memory DMA Stream 3 Source Current Y Count Register */
-
-/* UART1 Registers */
-
-#define                        UART1_DLL  0xffc02000   /* Divisor Latch Low Byte */
-#define                        UART1_DLH  0xffc02004   /* Divisor Latch High Byte */
-#define                       UART1_GCTL  0xffc02008   /* Global Control Register */
-#define                        UART1_LCR  0xffc0200c   /* Line Control Register */
-#define                        UART1_MCR  0xffc02010   /* Modem Control Register */
-#define                        UART1_LSR  0xffc02014   /* Line Status Register */
-#define                        UART1_MSR  0xffc02018   /* Modem Status Register */
-#define                        UART1_SCR  0xffc0201c   /* Scratch Register */
-#define                    UART1_IER_SET  0xffc02020   /* Interrupt Enable Register Set */
-#define                  UART1_IER_CLEAR  0xffc02024   /* Interrupt Enable Register Clear */
-#define                        UART1_THR  0xffc02028   /* Transmit Hold Register */
-#define                        UART1_RBR  0xffc0202c   /* Receive Buffer Register */
-
-/* UART2 is not defined in the shared file because it is not available on the ADSP-BF542 and ADSP-BF544 processors */
-
-/* SPI1 Registers */
-
-#define                     SPI1_REGBASE  0xffc02300
-#define                         SPI1_CTL  0xffc02300   /* SPI1 Control Register */
-#define                         SPI1_FLG  0xffc02304   /* SPI1 Flag Register */
-#define                        SPI1_STAT  0xffc02308   /* SPI1 Status Register */
-#define                        SPI1_TDBR  0xffc0230c   /* SPI1 Transmit Data Buffer Register */
-#define                        SPI1_RDBR  0xffc02310   /* SPI1 Receive Data Buffer Register */
-#define                        SPI1_BAUD  0xffc02314   /* SPI1 Baud Rate Register */
-#define                      SPI1_SHADOW  0xffc02318   /* SPI1 Receive Data Buffer Shadow Register */
-
-/* SPORT2 Registers */
-
-#define                      SPORT2_TCR1  0xffc02500   /* SPORT2 Transmit Configuration 1 Register */
-#define                      SPORT2_TCR2  0xffc02504   /* SPORT2 Transmit Configuration 2 Register */
-#define                   SPORT2_TCLKDIV  0xffc02508   /* SPORT2 Transmit Serial Clock Divider Register */
-#define                    SPORT2_TFSDIV  0xffc0250c   /* SPORT2 Transmit Frame Sync Divider Register */
-#define                        SPORT2_TX  0xffc02510   /* SPORT2 Transmit Data Register */
-#define                        SPORT2_RX  0xffc02518   /* SPORT2 Receive Data Register */
-#define                      SPORT2_RCR1  0xffc02520   /* SPORT2 Receive Configuration 1 Register */
-#define                      SPORT2_RCR2  0xffc02524   /* SPORT2 Receive Configuration 2 Register */
-#define                   SPORT2_RCLKDIV  0xffc02528   /* SPORT2 Receive Serial Clock Divider Register */
-#define                    SPORT2_RFSDIV  0xffc0252c   /* SPORT2 Receive Frame Sync Divider Register */
-#define                      SPORT2_STAT  0xffc02530   /* SPORT2 Status Register */
-#define                      SPORT2_CHNL  0xffc02534   /* SPORT2 Current Channel Register */
-#define                     SPORT2_MCMC1  0xffc02538   /* SPORT2 Multi channel Configuration Register 1 */
-#define                     SPORT2_MCMC2  0xffc0253c   /* SPORT2 Multi channel Configuration Register 2 */
-#define                     SPORT2_MTCS0  0xffc02540   /* SPORT2 Multi channel Transmit Select Register 0 */
-#define                     SPORT2_MTCS1  0xffc02544   /* SPORT2 Multi channel Transmit Select Register 1 */
-#define                     SPORT2_MTCS2  0xffc02548   /* SPORT2 Multi channel Transmit Select Register 2 */
-#define                     SPORT2_MTCS3  0xffc0254c   /* SPORT2 Multi channel Transmit Select Register 3 */
-#define                     SPORT2_MRCS0  0xffc02550   /* SPORT2 Multi channel Receive Select Register 0 */
-#define                     SPORT2_MRCS1  0xffc02554   /* SPORT2 Multi channel Receive Select Register 1 */
-#define                     SPORT2_MRCS2  0xffc02558   /* SPORT2 Multi channel Receive Select Register 2 */
-#define                     SPORT2_MRCS3  0xffc0255c   /* SPORT2 Multi channel Receive Select Register 3 */
-
-/* SPORT3 Registers */
-
-#define                      SPORT3_TCR1  0xffc02600   /* SPORT3 Transmit Configuration 1 Register */
-#define                      SPORT3_TCR2  0xffc02604   /* SPORT3 Transmit Configuration 2 Register */
-#define                   SPORT3_TCLKDIV  0xffc02608   /* SPORT3 Transmit Serial Clock Divider Register */
-#define                    SPORT3_TFSDIV  0xffc0260c   /* SPORT3 Transmit Frame Sync Divider Register */
-#define                        SPORT3_TX  0xffc02610   /* SPORT3 Transmit Data Register */
-#define                        SPORT3_RX  0xffc02618   /* SPORT3 Receive Data Register */
-#define                      SPORT3_RCR1  0xffc02620   /* SPORT3 Receive Configuration 1 Register */
-#define                      SPORT3_RCR2  0xffc02624   /* SPORT3 Receive Configuration 2 Register */
-#define                   SPORT3_RCLKDIV  0xffc02628   /* SPORT3 Receive Serial Clock Divider Register */
-#define                    SPORT3_RFSDIV  0xffc0262c   /* SPORT3 Receive Frame Sync Divider Register */
-#define                      SPORT3_STAT  0xffc02630   /* SPORT3 Status Register */
-#define                      SPORT3_CHNL  0xffc02634   /* SPORT3 Current Channel Register */
-#define                     SPORT3_MCMC1  0xffc02638   /* SPORT3 Multi channel Configuration Register 1 */
-#define                     SPORT3_MCMC2  0xffc0263c   /* SPORT3 Multi channel Configuration Register 2 */
-#define                     SPORT3_MTCS0  0xffc02640   /* SPORT3 Multi channel Transmit Select Register 0 */
-#define                     SPORT3_MTCS1  0xffc02644   /* SPORT3 Multi channel Transmit Select Register 1 */
-#define                     SPORT3_MTCS2  0xffc02648   /* SPORT3 Multi channel Transmit Select Register 2 */
-#define                     SPORT3_MTCS3  0xffc0264c   /* SPORT3 Multi channel Transmit Select Register 3 */
-#define                     SPORT3_MRCS0  0xffc02650   /* SPORT3 Multi channel Receive Select Register 0 */
-#define                     SPORT3_MRCS1  0xffc02654   /* SPORT3 Multi channel Receive Select Register 1 */
-#define                     SPORT3_MRCS2  0xffc02658   /* SPORT3 Multi channel Receive Select Register 2 */
-#define                     SPORT3_MRCS3  0xffc0265c   /* SPORT3 Multi channel Receive Select Register 3 */
-
-/* EPPI2 Registers */
-
-#define                     EPPI2_STATUS  0xffc02900   /* EPPI2 Status Register */
-#define                     EPPI2_HCOUNT  0xffc02904   /* EPPI2 Horizontal Transfer Count Register */
-#define                     EPPI2_HDELAY  0xffc02908   /* EPPI2 Horizontal Delay Count Register */
-#define                     EPPI2_VCOUNT  0xffc0290c   /* EPPI2 Vertical Transfer Count Register */
-#define                     EPPI2_VDELAY  0xffc02910   /* EPPI2 Vertical Delay Count Register */
-#define                      EPPI2_FRAME  0xffc02914   /* EPPI2 Lines per Frame Register */
-#define                       EPPI2_LINE  0xffc02918   /* EPPI2 Samples per Line Register */
-#define                     EPPI2_CLKDIV  0xffc0291c   /* EPPI2 Clock Divide Register */
-#define                    EPPI2_CONTROL  0xffc02920   /* EPPI2 Control Register */
-#define                   EPPI2_FS1W_HBL  0xffc02924   /* EPPI2 FS1 Width Register / EPPI2 Horizontal Blanking Samples Per Line Register */
-#define                  EPPI2_FS1P_AVPL  0xffc02928   /* EPPI2 FS1 Period Register / EPPI2 Active Video Samples Per Line Register */
-#define                   EPPI2_FS2W_LVB  0xffc0292c   /* EPPI2 FS2 Width Register / EPPI2 Lines of Vertical Blanking Register */
-#define                  EPPI2_FS2P_LAVF  0xffc02930   /* EPPI2 FS2 Period Register/ EPPI2 Lines of Active Video Per Field Register */
-#define                       EPPI2_CLIP  0xffc02934   /* EPPI2 Clipping Register */
-
-/* CAN Controller 0 Config 1 Registers */
-
-#define                         CAN0_MC1  0xffc02a00   /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define                         CAN0_MD1  0xffc02a04   /* CAN Controller 0 Mailbox Direction Register 1 */
-#define                        CAN0_TRS1  0xffc02a08   /* CAN Controller 0 Transmit Request Set Register 1 */
-#define                        CAN0_TRR1  0xffc02a0c   /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define                         CAN0_TA1  0xffc02a10   /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define                         CAN0_AA1  0xffc02a14   /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define                        CAN0_RMP1  0xffc02a18   /* CAN Controller 0 Receive Message Pending Register 1 */
-#define                        CAN0_RML1  0xffc02a1c   /* CAN Controller 0 Receive Message Lost Register 1 */
-#define                      CAN0_MBTIF1  0xffc02a20   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define                      CAN0_MBRIF1  0xffc02a24   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define                       CAN0_MBIM1  0xffc02a28   /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define                        CAN0_RFH1  0xffc02a2c   /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define                       CAN0_OPSS1  0xffc02a30   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-
-/* CAN Controller 0 Config 2 Registers */
-
-#define                         CAN0_MC2  0xffc02a40   /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define                         CAN0_MD2  0xffc02a44   /* CAN Controller 0 Mailbox Direction Register 2 */
-#define                        CAN0_TRS2  0xffc02a48   /* CAN Controller 0 Transmit Request Set Register 2 */
-#define                        CAN0_TRR2  0xffc02a4c   /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define                         CAN0_TA2  0xffc02a50   /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define                         CAN0_AA2  0xffc02a54   /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define                        CAN0_RMP2  0xffc02a58   /* CAN Controller 0 Receive Message Pending Register 2 */
-#define                        CAN0_RML2  0xffc02a5c   /* CAN Controller 0 Receive Message Lost Register 2 */
-#define                      CAN0_MBTIF2  0xffc02a60   /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define                      CAN0_MBRIF2  0xffc02a64   /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define                       CAN0_MBIM2  0xffc02a68   /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define                        CAN0_RFH2  0xffc02a6c   /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define                       CAN0_OPSS2  0xffc02a70   /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-
-/* CAN Controller 0 Clock/Interrupt/Counter Registers */
-
-#define                       CAN0_CLOCK  0xffc02a80   /* CAN Controller 0 Clock Register */
-#define                      CAN0_TIMING  0xffc02a84   /* CAN Controller 0 Timing Register */
-#define                       CAN0_DEBUG  0xffc02a88   /* CAN Controller 0 Debug Register */
-#define                      CAN0_STATUS  0xffc02a8c   /* CAN Controller 0 Global Status Register */
-#define                         CAN0_CEC  0xffc02a90   /* CAN Controller 0 Error Counter Register */
-#define                         CAN0_GIS  0xffc02a94   /* CAN Controller 0 Global Interrupt Status Register */
-#define                         CAN0_GIM  0xffc02a98   /* CAN Controller 0 Global Interrupt Mask Register */
-#define                         CAN0_GIF  0xffc02a9c   /* CAN Controller 0 Global Interrupt Flag Register */
-#define                     CAN0_CONTROL  0xffc02aa0   /* CAN Controller 0 Master Control Register */
-#define                        CAN0_INTR  0xffc02aa4   /* CAN Controller 0 Interrupt Pending Register */
-#define                        CAN0_MBTD  0xffc02aac   /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define                         CAN0_EWR  0xffc02ab0   /* CAN Controller 0 Programmable Warning Level Register */
-#define                         CAN0_ESR  0xffc02ab4   /* CAN Controller 0 Error Status Register */
-#define                       CAN0_UCCNT  0xffc02ac4   /* CAN Controller 0 Universal Counter Register */
-#define                        CAN0_UCRC  0xffc02ac8   /* CAN Controller 0 Universal Counter Force Reload Register */
-#define                       CAN0_UCCNF  0xffc02acc   /* CAN Controller 0 Universal Counter Configuration Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       CAN0_AM00L  0xffc02b00   /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define                       CAN0_AM00H  0xffc02b04   /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define                       CAN0_AM01L  0xffc02b08   /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define                       CAN0_AM01H  0xffc02b0c   /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define                       CAN0_AM02L  0xffc02b10   /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define                       CAN0_AM02H  0xffc02b14   /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define                       CAN0_AM03L  0xffc02b18   /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define                       CAN0_AM03H  0xffc02b1c   /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define                       CAN0_AM04L  0xffc02b20   /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define                       CAN0_AM04H  0xffc02b24   /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define                       CAN0_AM05L  0xffc02b28   /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define                       CAN0_AM05H  0xffc02b2c   /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define                       CAN0_AM06L  0xffc02b30   /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define                       CAN0_AM06H  0xffc02b34   /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define                       CAN0_AM07L  0xffc02b38   /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define                       CAN0_AM07H  0xffc02b3c   /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define                       CAN0_AM08L  0xffc02b40   /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define                       CAN0_AM08H  0xffc02b44   /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define                       CAN0_AM09L  0xffc02b48   /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define                       CAN0_AM09H  0xffc02b4c   /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define                       CAN0_AM10L  0xffc02b50   /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define                       CAN0_AM10H  0xffc02b54   /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define                       CAN0_AM11L  0xffc02b58   /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define                       CAN0_AM11H  0xffc02b5c   /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define                       CAN0_AM12L  0xffc02b60   /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define                       CAN0_AM12H  0xffc02b64   /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define                       CAN0_AM13L  0xffc02b68   /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define                       CAN0_AM13H  0xffc02b6c   /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define                       CAN0_AM14L  0xffc02b70   /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define                       CAN0_AM14H  0xffc02b74   /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define                       CAN0_AM15L  0xffc02b78   /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define                       CAN0_AM15H  0xffc02b7c   /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Acceptance Registers */
-
-#define                       CAN0_AM16L  0xffc02b80   /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define                       CAN0_AM16H  0xffc02b84   /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define                       CAN0_AM17L  0xffc02b88   /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define                       CAN0_AM17H  0xffc02b8c   /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define                       CAN0_AM18L  0xffc02b90   /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define                       CAN0_AM18H  0xffc02b94   /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define                       CAN0_AM19L  0xffc02b98   /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define                       CAN0_AM19H  0xffc02b9c   /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define                       CAN0_AM20L  0xffc02ba0   /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define                       CAN0_AM20H  0xffc02ba4   /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define                       CAN0_AM21L  0xffc02ba8   /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define                       CAN0_AM21H  0xffc02bac   /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define                       CAN0_AM22L  0xffc02bb0   /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define                       CAN0_AM22H  0xffc02bb4   /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define                       CAN0_AM23L  0xffc02bb8   /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define                       CAN0_AM23H  0xffc02bbc   /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define                       CAN0_AM24L  0xffc02bc0   /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define                       CAN0_AM24H  0xffc02bc4   /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define                       CAN0_AM25L  0xffc02bc8   /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define                       CAN0_AM25H  0xffc02bcc   /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define                       CAN0_AM26L  0xffc02bd0   /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define                       CAN0_AM26H  0xffc02bd4   /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define                       CAN0_AM27L  0xffc02bd8   /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define                       CAN0_AM27H  0xffc02bdc   /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define                       CAN0_AM28L  0xffc02be0   /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define                       CAN0_AM28H  0xffc02be4   /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define                       CAN0_AM29L  0xffc02be8   /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define                       CAN0_AM29H  0xffc02bec   /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define                       CAN0_AM30L  0xffc02bf0   /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define                       CAN0_AM30H  0xffc02bf4   /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define                       CAN0_AM31L  0xffc02bf8   /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define                       CAN0_AM31H  0xffc02bfc   /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  CAN0_MB00_DATA0  0xffc02c00   /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define                  CAN0_MB00_DATA1  0xffc02c04   /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define                  CAN0_MB00_DATA2  0xffc02c08   /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define                  CAN0_MB00_DATA3  0xffc02c0c   /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define                 CAN0_MB00_LENGTH  0xffc02c10   /* CAN Controller 0 Mailbox 0 Length Register */
-#define              CAN0_MB00_TIMESTAMP  0xffc02c14   /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define                    CAN0_MB00_ID0  0xffc02c18   /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define                    CAN0_MB00_ID1  0xffc02c1c   /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define                  CAN0_MB01_DATA0  0xffc02c20   /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define                  CAN0_MB01_DATA1  0xffc02c24   /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define                  CAN0_MB01_DATA2  0xffc02c28   /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define                  CAN0_MB01_DATA3  0xffc02c2c   /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define                 CAN0_MB01_LENGTH  0xffc02c30   /* CAN Controller 0 Mailbox 1 Length Register */
-#define              CAN0_MB01_TIMESTAMP  0xffc02c34   /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define                    CAN0_MB01_ID0  0xffc02c38   /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define                    CAN0_MB01_ID1  0xffc02c3c   /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define                  CAN0_MB02_DATA0  0xffc02c40   /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define                  CAN0_MB02_DATA1  0xffc02c44   /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define                  CAN0_MB02_DATA2  0xffc02c48   /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define                  CAN0_MB02_DATA3  0xffc02c4c   /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define                 CAN0_MB02_LENGTH  0xffc02c50   /* CAN Controller 0 Mailbox 2 Length Register */
-#define              CAN0_MB02_TIMESTAMP  0xffc02c54   /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define                    CAN0_MB02_ID0  0xffc02c58   /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define                    CAN0_MB02_ID1  0xffc02c5c   /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define                  CAN0_MB03_DATA0  0xffc02c60   /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define                  CAN0_MB03_DATA1  0xffc02c64   /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define                  CAN0_MB03_DATA2  0xffc02c68   /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define                  CAN0_MB03_DATA3  0xffc02c6c   /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define                 CAN0_MB03_LENGTH  0xffc02c70   /* CAN Controller 0 Mailbox 3 Length Register */
-#define              CAN0_MB03_TIMESTAMP  0xffc02c74   /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define                    CAN0_MB03_ID0  0xffc02c78   /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define                    CAN0_MB03_ID1  0xffc02c7c   /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define                  CAN0_MB04_DATA0  0xffc02c80   /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define                  CAN0_MB04_DATA1  0xffc02c84   /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define                  CAN0_MB04_DATA2  0xffc02c88   /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define                  CAN0_MB04_DATA3  0xffc02c8c   /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define                 CAN0_MB04_LENGTH  0xffc02c90   /* CAN Controller 0 Mailbox 4 Length Register */
-#define              CAN0_MB04_TIMESTAMP  0xffc02c94   /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define                    CAN0_MB04_ID0  0xffc02c98   /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define                    CAN0_MB04_ID1  0xffc02c9c   /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define                  CAN0_MB05_DATA0  0xffc02ca0   /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define                  CAN0_MB05_DATA1  0xffc02ca4   /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define                  CAN0_MB05_DATA2  0xffc02ca8   /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define                  CAN0_MB05_DATA3  0xffc02cac   /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define                 CAN0_MB05_LENGTH  0xffc02cb0   /* CAN Controller 0 Mailbox 5 Length Register */
-#define              CAN0_MB05_TIMESTAMP  0xffc02cb4   /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define                    CAN0_MB05_ID0  0xffc02cb8   /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define                    CAN0_MB05_ID1  0xffc02cbc   /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define                  CAN0_MB06_DATA0  0xffc02cc0   /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define                  CAN0_MB06_DATA1  0xffc02cc4   /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define                  CAN0_MB06_DATA2  0xffc02cc8   /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define                  CAN0_MB06_DATA3  0xffc02ccc   /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define                 CAN0_MB06_LENGTH  0xffc02cd0   /* CAN Controller 0 Mailbox 6 Length Register */
-#define              CAN0_MB06_TIMESTAMP  0xffc02cd4   /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define                    CAN0_MB06_ID0  0xffc02cd8   /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define                    CAN0_MB06_ID1  0xffc02cdc   /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define                  CAN0_MB07_DATA0  0xffc02ce0   /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define                  CAN0_MB07_DATA1  0xffc02ce4   /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define                  CAN0_MB07_DATA2  0xffc02ce8   /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define                  CAN0_MB07_DATA3  0xffc02cec   /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define                 CAN0_MB07_LENGTH  0xffc02cf0   /* CAN Controller 0 Mailbox 7 Length Register */
-#define              CAN0_MB07_TIMESTAMP  0xffc02cf4   /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define                    CAN0_MB07_ID0  0xffc02cf8   /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define                    CAN0_MB07_ID1  0xffc02cfc   /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define                  CAN0_MB08_DATA0  0xffc02d00   /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define                  CAN0_MB08_DATA1  0xffc02d04   /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define                  CAN0_MB08_DATA2  0xffc02d08   /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define                  CAN0_MB08_DATA3  0xffc02d0c   /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define                 CAN0_MB08_LENGTH  0xffc02d10   /* CAN Controller 0 Mailbox 8 Length Register */
-#define              CAN0_MB08_TIMESTAMP  0xffc02d14   /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define                    CAN0_MB08_ID0  0xffc02d18   /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define                    CAN0_MB08_ID1  0xffc02d1c   /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define                  CAN0_MB09_DATA0  0xffc02d20   /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define                  CAN0_MB09_DATA1  0xffc02d24   /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define                  CAN0_MB09_DATA2  0xffc02d28   /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define                  CAN0_MB09_DATA3  0xffc02d2c   /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define                 CAN0_MB09_LENGTH  0xffc02d30   /* CAN Controller 0 Mailbox 9 Length Register */
-#define              CAN0_MB09_TIMESTAMP  0xffc02d34   /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define                    CAN0_MB09_ID0  0xffc02d38   /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define                    CAN0_MB09_ID1  0xffc02d3c   /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define                  CAN0_MB10_DATA0  0xffc02d40   /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define                  CAN0_MB10_DATA1  0xffc02d44   /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define                  CAN0_MB10_DATA2  0xffc02d48   /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define                  CAN0_MB10_DATA3  0xffc02d4c   /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define                 CAN0_MB10_LENGTH  0xffc02d50   /* CAN Controller 0 Mailbox 10 Length Register */
-#define              CAN0_MB10_TIMESTAMP  0xffc02d54   /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define                    CAN0_MB10_ID0  0xffc02d58   /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define                    CAN0_MB10_ID1  0xffc02d5c   /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define                  CAN0_MB11_DATA0  0xffc02d60   /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define                  CAN0_MB11_DATA1  0xffc02d64   /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define                  CAN0_MB11_DATA2  0xffc02d68   /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define                  CAN0_MB11_DATA3  0xffc02d6c   /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define                 CAN0_MB11_LENGTH  0xffc02d70   /* CAN Controller 0 Mailbox 11 Length Register */
-#define              CAN0_MB11_TIMESTAMP  0xffc02d74   /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define                    CAN0_MB11_ID0  0xffc02d78   /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define                    CAN0_MB11_ID1  0xffc02d7c   /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define                  CAN0_MB12_DATA0  0xffc02d80   /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define                  CAN0_MB12_DATA1  0xffc02d84   /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define                  CAN0_MB12_DATA2  0xffc02d88   /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define                  CAN0_MB12_DATA3  0xffc02d8c   /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define                 CAN0_MB12_LENGTH  0xffc02d90   /* CAN Controller 0 Mailbox 12 Length Register */
-#define              CAN0_MB12_TIMESTAMP  0xffc02d94   /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define                    CAN0_MB12_ID0  0xffc02d98   /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define                    CAN0_MB12_ID1  0xffc02d9c   /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define                  CAN0_MB13_DATA0  0xffc02da0   /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define                  CAN0_MB13_DATA1  0xffc02da4   /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define                  CAN0_MB13_DATA2  0xffc02da8   /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define                  CAN0_MB13_DATA3  0xffc02dac   /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define                 CAN0_MB13_LENGTH  0xffc02db0   /* CAN Controller 0 Mailbox 13 Length Register */
-#define              CAN0_MB13_TIMESTAMP  0xffc02db4   /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define                    CAN0_MB13_ID0  0xffc02db8   /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define                    CAN0_MB13_ID1  0xffc02dbc   /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define                  CAN0_MB14_DATA0  0xffc02dc0   /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define                  CAN0_MB14_DATA1  0xffc02dc4   /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define                  CAN0_MB14_DATA2  0xffc02dc8   /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define                  CAN0_MB14_DATA3  0xffc02dcc   /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define                 CAN0_MB14_LENGTH  0xffc02dd0   /* CAN Controller 0 Mailbox 14 Length Register */
-#define              CAN0_MB14_TIMESTAMP  0xffc02dd4   /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define                    CAN0_MB14_ID0  0xffc02dd8   /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define                    CAN0_MB14_ID1  0xffc02ddc   /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define                  CAN0_MB15_DATA0  0xffc02de0   /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define                  CAN0_MB15_DATA1  0xffc02de4   /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define                  CAN0_MB15_DATA2  0xffc02de8   /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define                  CAN0_MB15_DATA3  0xffc02dec   /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define                 CAN0_MB15_LENGTH  0xffc02df0   /* CAN Controller 0 Mailbox 15 Length Register */
-#define              CAN0_MB15_TIMESTAMP  0xffc02df4   /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define                    CAN0_MB15_ID0  0xffc02df8   /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define                    CAN0_MB15_ID1  0xffc02dfc   /* CAN Controller 0 Mailbox 15 ID1 Register */
-
-/* CAN Controller 0 Mailbox Data Registers */
-
-#define                  CAN0_MB16_DATA0  0xffc02e00   /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define                  CAN0_MB16_DATA1  0xffc02e04   /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define                  CAN0_MB16_DATA2  0xffc02e08   /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define                  CAN0_MB16_DATA3  0xffc02e0c   /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define                 CAN0_MB16_LENGTH  0xffc02e10   /* CAN Controller 0 Mailbox 16 Length Register */
-#define              CAN0_MB16_TIMESTAMP  0xffc02e14   /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define                    CAN0_MB16_ID0  0xffc02e18   /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define                    CAN0_MB16_ID1  0xffc02e1c   /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define                  CAN0_MB17_DATA0  0xffc02e20   /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define                  CAN0_MB17_DATA1  0xffc02e24   /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define                  CAN0_MB17_DATA2  0xffc02e28   /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define                  CAN0_MB17_DATA3  0xffc02e2c   /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define                 CAN0_MB17_LENGTH  0xffc02e30   /* CAN Controller 0 Mailbox 17 Length Register */
-#define              CAN0_MB17_TIMESTAMP  0xffc02e34   /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define                    CAN0_MB17_ID0  0xffc02e38   /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define                    CAN0_MB17_ID1  0xffc02e3c   /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define                  CAN0_MB18_DATA0  0xffc02e40   /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define                  CAN0_MB18_DATA1  0xffc02e44   /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define                  CAN0_MB18_DATA2  0xffc02e48   /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define                  CAN0_MB18_DATA3  0xffc02e4c   /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define                 CAN0_MB18_LENGTH  0xffc02e50   /* CAN Controller 0 Mailbox 18 Length Register */
-#define              CAN0_MB18_TIMESTAMP  0xffc02e54   /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define                    CAN0_MB18_ID0  0xffc02e58   /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define                    CAN0_MB18_ID1  0xffc02e5c   /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define                  CAN0_MB19_DATA0  0xffc02e60   /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define                  CAN0_MB19_DATA1  0xffc02e64   /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define                  CAN0_MB19_DATA2  0xffc02e68   /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define                  CAN0_MB19_DATA3  0xffc02e6c   /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define                 CAN0_MB19_LENGTH  0xffc02e70   /* CAN Controller 0 Mailbox 19 Length Register */
-#define              CAN0_MB19_TIMESTAMP  0xffc02e74   /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define                    CAN0_MB19_ID0  0xffc02e78   /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define                    CAN0_MB19_ID1  0xffc02e7c   /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define                  CAN0_MB20_DATA0  0xffc02e80   /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define                  CAN0_MB20_DATA1  0xffc02e84   /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define                  CAN0_MB20_DATA2  0xffc02e88   /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define                  CAN0_MB20_DATA3  0xffc02e8c   /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define                 CAN0_MB20_LENGTH  0xffc02e90   /* CAN Controller 0 Mailbox 20 Length Register */
-#define              CAN0_MB20_TIMESTAMP  0xffc02e94   /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define                    CAN0_MB20_ID0  0xffc02e98   /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define                    CAN0_MB20_ID1  0xffc02e9c   /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define                  CAN0_MB21_DATA0  0xffc02ea0   /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define                  CAN0_MB21_DATA1  0xffc02ea4   /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define                  CAN0_MB21_DATA2  0xffc02ea8   /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define                  CAN0_MB21_DATA3  0xffc02eac   /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define                 CAN0_MB21_LENGTH  0xffc02eb0   /* CAN Controller 0 Mailbox 21 Length Register */
-#define              CAN0_MB21_TIMESTAMP  0xffc02eb4   /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define                    CAN0_MB21_ID0  0xffc02eb8   /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define                    CAN0_MB21_ID1  0xffc02ebc   /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define                  CAN0_MB22_DATA0  0xffc02ec0   /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define                  CAN0_MB22_DATA1  0xffc02ec4   /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define                  CAN0_MB22_DATA2  0xffc02ec8   /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define                  CAN0_MB22_DATA3  0xffc02ecc   /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define                 CAN0_MB22_LENGTH  0xffc02ed0   /* CAN Controller 0 Mailbox 22 Length Register */
-#define              CAN0_MB22_TIMESTAMP  0xffc02ed4   /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define                    CAN0_MB22_ID0  0xffc02ed8   /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define                    CAN0_MB22_ID1  0xffc02edc   /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define                  CAN0_MB23_DATA0  0xffc02ee0   /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define                  CAN0_MB23_DATA1  0xffc02ee4   /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define                  CAN0_MB23_DATA2  0xffc02ee8   /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define                  CAN0_MB23_DATA3  0xffc02eec   /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define                 CAN0_MB23_LENGTH  0xffc02ef0   /* CAN Controller 0 Mailbox 23 Length Register */
-#define              CAN0_MB23_TIMESTAMP  0xffc02ef4   /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define                    CAN0_MB23_ID0  0xffc02ef8   /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define                    CAN0_MB23_ID1  0xffc02efc   /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define                  CAN0_MB24_DATA0  0xffc02f00   /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define                  CAN0_MB24_DATA1  0xffc02f04   /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define                  CAN0_MB24_DATA2  0xffc02f08   /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define                  CAN0_MB24_DATA3  0xffc02f0c   /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define                 CAN0_MB24_LENGTH  0xffc02f10   /* CAN Controller 0 Mailbox 24 Length Register */
-#define              CAN0_MB24_TIMESTAMP  0xffc02f14   /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define                    CAN0_MB24_ID0  0xffc02f18   /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define                    CAN0_MB24_ID1  0xffc02f1c   /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define                  CAN0_MB25_DATA0  0xffc02f20   /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define                  CAN0_MB25_DATA1  0xffc02f24   /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define                  CAN0_MB25_DATA2  0xffc02f28   /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define                  CAN0_MB25_DATA3  0xffc02f2c   /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define                 CAN0_MB25_LENGTH  0xffc02f30   /* CAN Controller 0 Mailbox 25 Length Register */
-#define              CAN0_MB25_TIMESTAMP  0xffc02f34   /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define                    CAN0_MB25_ID0  0xffc02f38   /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define                    CAN0_MB25_ID1  0xffc02f3c   /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define                  CAN0_MB26_DATA0  0xffc02f40   /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define                  CAN0_MB26_DATA1  0xffc02f44   /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define                  CAN0_MB26_DATA2  0xffc02f48   /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define                  CAN0_MB26_DATA3  0xffc02f4c   /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define                 CAN0_MB26_LENGTH  0xffc02f50   /* CAN Controller 0 Mailbox 26 Length Register */
-#define              CAN0_MB26_TIMESTAMP  0xffc02f54   /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define                    CAN0_MB26_ID0  0xffc02f58   /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define                    CAN0_MB26_ID1  0xffc02f5c   /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define                  CAN0_MB27_DATA0  0xffc02f60   /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define                  CAN0_MB27_DATA1  0xffc02f64   /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define                  CAN0_MB27_DATA2  0xffc02f68   /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define                  CAN0_MB27_DATA3  0xffc02f6c   /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define                 CAN0_MB27_LENGTH  0xffc02f70   /* CAN Controller 0 Mailbox 27 Length Register */
-#define              CAN0_MB27_TIMESTAMP  0xffc02f74   /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define                    CAN0_MB27_ID0  0xffc02f78   /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define                    CAN0_MB27_ID1  0xffc02f7c   /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define                  CAN0_MB28_DATA0  0xffc02f80   /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define                  CAN0_MB28_DATA1  0xffc02f84   /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define                  CAN0_MB28_DATA2  0xffc02f88   /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define                  CAN0_MB28_DATA3  0xffc02f8c   /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define                 CAN0_MB28_LENGTH  0xffc02f90   /* CAN Controller 0 Mailbox 28 Length Register */
-#define              CAN0_MB28_TIMESTAMP  0xffc02f94   /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define                    CAN0_MB28_ID0  0xffc02f98   /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define                    CAN0_MB28_ID1  0xffc02f9c   /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define                  CAN0_MB29_DATA0  0xffc02fa0   /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define                  CAN0_MB29_DATA1  0xffc02fa4   /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define                  CAN0_MB29_DATA2  0xffc02fa8   /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define                  CAN0_MB29_DATA3  0xffc02fac   /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define                 CAN0_MB29_LENGTH  0xffc02fb0   /* CAN Controller 0 Mailbox 29 Length Register */
-#define              CAN0_MB29_TIMESTAMP  0xffc02fb4   /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define                    CAN0_MB29_ID0  0xffc02fb8   /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define                    CAN0_MB29_ID1  0xffc02fbc   /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define                  CAN0_MB30_DATA0  0xffc02fc0   /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define                  CAN0_MB30_DATA1  0xffc02fc4   /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define                  CAN0_MB30_DATA2  0xffc02fc8   /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define                  CAN0_MB30_DATA3  0xffc02fcc   /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define                 CAN0_MB30_LENGTH  0xffc02fd0   /* CAN Controller 0 Mailbox 30 Length Register */
-#define              CAN0_MB30_TIMESTAMP  0xffc02fd4   /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define                    CAN0_MB30_ID0  0xffc02fd8   /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define                    CAN0_MB30_ID1  0xffc02fdc   /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define                  CAN0_MB31_DATA0  0xffc02fe0   /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define                  CAN0_MB31_DATA1  0xffc02fe4   /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define                  CAN0_MB31_DATA2  0xffc02fe8   /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define                  CAN0_MB31_DATA3  0xffc02fec   /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define                 CAN0_MB31_LENGTH  0xffc02ff0   /* CAN Controller 0 Mailbox 31 Length Register */
-#define              CAN0_MB31_TIMESTAMP  0xffc02ff4   /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define                    CAN0_MB31_ID0  0xffc02ff8   /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define                    CAN0_MB31_ID1  0xffc02ffc   /* CAN Controller 0 Mailbox 31 ID1 Register */
-
-/* UART3 Registers */
-
-#define                        UART3_DLL  0xffc03100   /* Divisor Latch Low Byte */
-#define                        UART3_DLH  0xffc03104   /* Divisor Latch High Byte */
-#define                       UART3_GCTL  0xffc03108   /* Global Control Register */
-#define                        UART3_LCR  0xffc0310c   /* Line Control Register */
-#define                        UART3_MCR  0xffc03110   /* Modem Control Register */
-#define                        UART3_LSR  0xffc03114   /* Line Status Register */
-#define                        UART3_MSR  0xffc03118   /* Modem Status Register */
-#define                        UART3_SCR  0xffc0311c   /* Scratch Register */
-#define                    UART3_IER_SET  0xffc03120   /* Interrupt Enable Register Set */
-#define                  UART3_IER_CLEAR  0xffc03124   /* Interrupt Enable Register Clear */
-#define                        UART3_THR  0xffc03128   /* Transmit Hold Register */
-#define                        UART3_RBR  0xffc0312c   /* Receive Buffer Register */
-
-/* NFC Registers */
-
-#define                          NFC_CTL  0xffc03b00   /* NAND Control Register */
-#define                         NFC_STAT  0xffc03b04   /* NAND Status Register */
-#define                      NFC_IRQSTAT  0xffc03b08   /* NAND Interrupt Status Register */
-#define                      NFC_IRQMASK  0xffc03b0c   /* NAND Interrupt Mask Register */
-#define                         NFC_ECC0  0xffc03b10   /* NAND ECC Register 0 */
-#define                         NFC_ECC1  0xffc03b14   /* NAND ECC Register 1 */
-#define                         NFC_ECC2  0xffc03b18   /* NAND ECC Register 2 */
-#define                         NFC_ECC3  0xffc03b1c   /* NAND ECC Register 3 */
-#define                        NFC_COUNT  0xffc03b20   /* NAND ECC Count Register */
-#define                          NFC_RST  0xffc03b24   /* NAND ECC Reset Register */
-#define                        NFC_PGCTL  0xffc03b28   /* NAND Page Control Register */
-#define                         NFC_READ  0xffc03b2c   /* NAND Read Data Register */
-#define                         NFC_ADDR  0xffc03b40   /* NAND Address Register */
-#define                          NFC_CMD  0xffc03b44   /* NAND Command Register */
-#define                      NFC_DATA_WR  0xffc03b48   /* NAND Data Write Register */
-#define                      NFC_DATA_RD  0xffc03b4c   /* NAND Data Read Register */
-
-/* Counter Registers */
-
-#define                       CNT_CONFIG  0xffc04200   /* Configuration Register */
-#define                        CNT_IMASK  0xffc04204   /* Interrupt Mask Register */
-#define                       CNT_STATUS  0xffc04208   /* Status Register */
-#define                      CNT_COMMAND  0xffc0420c   /* Command Register */
-#define                     CNT_DEBOUNCE  0xffc04210   /* Debounce Register */
-#define                      CNT_COUNTER  0xffc04214   /* Counter Register */
-#define                          CNT_MAX  0xffc04218   /* Maximal Count Register */
-#define                          CNT_MIN  0xffc0421c   /* Minimal Count Register */
-
-/* OTP/FUSE Registers */
-
-#define                      OTP_CONTROL  0xffc04300   /* OTP/Fuse Control Register */
-#define                          OTP_BEN  0xffc04304   /* OTP/Fuse Byte Enable */
-#define                       OTP_STATUS  0xffc04308   /* OTP/Fuse Status */
-#define                       OTP_TIMING  0xffc0430c   /* OTP/Fuse Access Timing */
-
-/* Security Registers */
-
-#define                    SECURE_SYSSWT  0xffc04320   /* Secure System Switches */
-#define                   SECURE_CONTROL  0xffc04324   /* Secure Control */
-#define                    SECURE_STATUS  0xffc04328   /* Secure Status */
-
-/* DMA Peripheral Mux Register */
-
-#define                    DMAC1_PERIMUX  0xffc04340   /* DMA Controller 1 Peripheral Multiplexer Register */
-
-/* OTP Read/Write Data Buffer Registers */
-
-#define                        OTP_DATA0  0xffc04380   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA1  0xffc04384   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA2  0xffc04388   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define                        OTP_DATA3  0xffc0438c   /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-
-/* Handshake MDMA is not defined in the shared file because it is not available on the ADSP-BF542 processor */
-
-/* ********************************************************** */
-/*     SINGLE BIT MACRO PAIRS (bit mask and negated one)      */
-/*     and MULTI BIT READ MACROS                              */
-/* ********************************************************** */
-
-/* SIC_IMASK Masks */
-#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
-#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
-#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
-
-/* Bit masks for SIC_IAR0 */
-
-#define            PLL_WAKEUP  0x1        /* PLL Wakeup */
-
-/* Bit masks for SIC_IWR0, SIC_IMASK0, SIC_ISR0 */
-
-#define              DMA0_ERR  0x2        /* DMA Controller 0 Error */
-#define             EPPI0_ERR  0x4        /* EPPI0 Error */
-#define            SPORT0_ERR  0x8        /* SPORT0 Error */
-#define            SPORT1_ERR  0x10       /* SPORT1 Error */
-#define              SPI0_ERR  0x20       /* SPI0 Error */
-#define             UART0_ERR  0x40       /* UART0 Error */
-#define                   RTC  0x80       /* Real-Time Clock */
-#define                 DMA12  0x100      /* DMA Channel 12 */
-#define                  DMA0  0x200      /* DMA Channel 0 */
-#define                  DMA1  0x400      /* DMA Channel 1 */
-#define                  DMA2  0x800      /* DMA Channel 2 */
-#define                  DMA3  0x1000     /* DMA Channel 3 */
-#define                  DMA4  0x2000     /* DMA Channel 4 */
-#define                  DMA6  0x4000     /* DMA Channel 6 */
-#define                  DMA7  0x8000     /* DMA Channel 7 */
-#define                 PINT0  0x80000    /* Pin Interrupt 0 */
-#define                 PINT1  0x100000   /* Pin Interrupt 1 */
-#define                 MDMA0  0x200000   /* Memory DMA Stream 0 */
-#define                 MDMA1  0x400000   /* Memory DMA Stream 1 */
-#define                  WDOG  0x800000   /* Watchdog Timer */
-#define              DMA1_ERR  0x1000000  /* DMA Controller 1 Error */
-#define            SPORT2_ERR  0x2000000  /* SPORT2 Error */
-#define            SPORT3_ERR  0x4000000  /* SPORT3 Error */
-#define               MXVR_SD  0x8000000  /* MXVR Synchronous Data */
-#define              SPI1_ERR  0x10000000 /* SPI1 Error */
-#define              SPI2_ERR  0x20000000 /* SPI2 Error */
-#define             UART1_ERR  0x40000000 /* UART1 Error */
-#define             UART2_ERR  0x80000000 /* UART2 Error */
-
-/* Bit masks for SIC_IWR1, SIC_IMASK1, SIC_ISR1 */
-
-#define              CAN0_ERR  0x1        /* CAN0 Error */
-#define                 DMA18  0x2        /* DMA Channel 18 */
-#define                 DMA19  0x4        /* DMA Channel 19 */
-#define                 DMA20  0x8        /* DMA Channel 20 */
-#define                 DMA21  0x10       /* DMA Channel 21 */
-#define                 DMA13  0x20       /* DMA Channel 13 */
-#define                 DMA14  0x40       /* DMA Channel 14 */
-#define                  DMA5  0x80       /* DMA Channel 5 */
-#define                 DMA23  0x100      /* DMA Channel 23 */
-#define                  DMA8  0x200      /* DMA Channel 8 */
-#define                  DMA9  0x400      /* DMA Channel 9 */
-#define                 DMA10  0x800      /* DMA Channel 10 */
-#define                 DMA11  0x1000     /* DMA Channel 11 */
-#define                  TWI0  0x2000     /* TWI0 */
-#define                  TWI1  0x4000     /* TWI1 */
-#define               CAN0_RX  0x8000     /* CAN0 Receive */
-#define               CAN0_TX  0x10000    /* CAN0 Transmit */
-#define                 MDMA2  0x20000    /* Memory DMA Stream 0 */
-#define                 MDMA3  0x40000    /* Memory DMA Stream 1 */
-#define             MXVR_STAT  0x80000    /* MXVR Status */
-#define               MXVR_CM  0x100000   /* MXVR Control Message */
-#define               MXVR_AP  0x200000   /* MXVR Asynchronous Packet */
-#define             EPPI1_ERR  0x400000   /* EPPI1 Error */
-#define             EPPI2_ERR  0x800000   /* EPPI2 Error */
-#define             UART3_ERR  0x1000000  /* UART3 Error */
-#define              HOST_ERR  0x2000000  /* Host DMA Port Error */
-#define               USB_ERR  0x4000000  /* USB Error */
-#define              PIXC_ERR  0x8000000  /* Pixel Compositor Error */
-#define               NFC_ERR  0x10000000 /* Nand Flash Controller Error */
-#define             ATAPI_ERR  0x20000000 /* ATAPI Error */
-#define              CAN1_ERR  0x40000000 /* CAN1 Error */
-#define             DMAR0_ERR  0x80000000 /* DMAR0 Overflow Error */
-#define             DMAR1_ERR  0x80000000 /* DMAR1 Overflow Error */
-#define                 DMAR0  0x80000000 /* DMAR0 Block */
-#define                 DMAR1  0x80000000 /* DMAR1 Block */
-
-/* Bit masks for SIC_IWR2, SIC_IMASK2, SIC_ISR2 */
-
-#define                 DMA15  0x1        /* DMA Channel 15 */
-#define                 DMA16  0x2        /* DMA Channel 16 */
-#define                 DMA17  0x4        /* DMA Channel 17 */
-#define                 DMA22  0x8        /* DMA Channel 22 */
-#define                   CNT  0x10       /* Counter */
-#define                   KEY  0x20       /* Keypad */
-#define               CAN1_RX  0x40       /* CAN1 Receive */
-#define               CAN1_TX  0x80       /* CAN1 Transmit */
-#define             SDH_INT_MASK0  0x100      /* SDH Mask 0 */
-#define             SDH_INT_MASK1  0x200      /* SDH Mask 1 */
-#define              USB_EINT  0x400      /* USB Exception */
-#define              USB_INT0  0x800      /* USB Interrupt 0 */
-#define              USB_INT1  0x1000     /* USB Interrupt 1 */
-#define              USB_INT2  0x2000     /* USB Interrupt 2 */
-#define            USB_DMAINT  0x4000     /* USB DMA */
-#define                OTPSEC  0x8000     /* OTP Access Complete */
-#define                TIMER0  0x400000   /* Timer 0 */
-#define                TIMER1  0x800000   /* Timer 1 */
-#define                TIMER2  0x1000000  /* Timer 2 */
-#define                TIMER3  0x2000000  /* Timer 3 */
-#define                TIMER4  0x4000000  /* Timer 4 */
-#define                TIMER5  0x8000000  /* Timer 5 */
-#define                TIMER6  0x10000000 /* Timer 6 */
-#define                TIMER7  0x20000000 /* Timer 7 */
-#define                 PINT2  0x40000000 /* Pin Interrupt 2 */
-#define                 PINT3  0x80000000 /* Pin Interrupt 3 */
-
-/* Bit masks for DMAx_CONFIG, MDMA_Sx_CONFIG, MDMA_Dx_CONFIG */
-
-#define                     DMAEN  0x1        /* DMA Channel Enable */
-#define                       WNR  0x2        /* DMA Direction */
-#define                  WDSIZE_8  0x0        /* Transfer Word Size = 8 */
-#define                 WDSIZE_16  0x4        /* Transfer Word Size = 16 */
-#define                 WDSIZE_32  0x8        /* Transfer Word Size = 32 */
-#define                     DMA2D  0x10       /* DMA Mode */
-#define                   RESTART  0x20       /* Work Unit Transitions */
-#define                    DI_SEL  0x40       /* Data Interrupt Timing Select */
-#define                     DI_EN  0x80       /* Data Interrupt Enable */
-
-#define                    NDSIZE  0xf00      /* Flex Descriptor Size */
-#define                  NDSIZE_0 0x0000      /* Next Descriptor Size = 0 (Stop/Autobuffer) */
-#define                  NDSIZE_1 0x0100      /* Next Descriptor Size = 1 */
-#define                  NDSIZE_2 0x0200      /* Next Descriptor Size = 2 */
-#define                  NDSIZE_3 0x0300      /* Next Descriptor Size = 3 */
-#define                  NDSIZE_4 0x0400      /* Next Descriptor Size = 4 */
-#define                  NDSIZE_5 0x0500      /* Next Descriptor Size = 5 */
-#define                  NDSIZE_6 0x0600      /* Next Descriptor Size = 6 */
-#define                  NDSIZE_7 0x0700      /* Next Descriptor Size = 7 */
-#define                  NDSIZE_8 0x0800      /* Next Descriptor Size = 8 */
-#define                  NDSIZE_9 0x0900      /* Next Descriptor Size = 9 */
-
-#define                   DMAFLOW  0xf000     /* Next Operation */
-#define              DMAFLOW_STOP  0x0000     /* Stop Mode */
-#define              DMAFLOW_AUTO  0x1000     /* Autobuffer Mode */
-#define             DMAFLOW_ARRAY  0x4000     /* Descriptor Array Mode */
-#define             DMAFLOW_SMALL  0x6000     /* Small Model Descriptor List Mode */
-#define             DMAFLOW_LARGE  0x7000     /* Large Model Descriptor List Mode */
-
-/* Bit masks for DMAx_IRQ_STATUS, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                  DMA_DONE  0x1        /* DMA Completion Interrupt Status */
-#define                   DMA_ERR  0x2        /* DMA Error Interrupt Status */
-#define                    DFETCH  0x4        /* DMA Descriptor Fetch */
-#define                   DMA_RUN  0x8        /* DMA Channel Running */
-
-/* Bit masks for DMAx_PERIPHERAL_MAP, MDMA_Sx_IRQ_STATUS, MDMA_Dx_IRQ_STATUS */
-
-#define                     CTYPE  0x40       /* DMA Channel Type */
-#define                      PMAP  0xf000     /* Peripheral Mapped To This Channel */
-
-/* Bit masks for DMACx_TCPER */
-
-#define        DCB_TRAFFIC_PERIOD  0xf        /* DCB Traffic Control Period */
-#define        DEB_TRAFFIC_PERIOD  0xf0       /* DEB Traffic Control Period */
-#define        DAB_TRAFFIC_PERIOD  0x700      /* DAB Traffic Control Period */
-#define   MDMA_ROUND_ROBIN_PERIOD  0xf800     /* MDMA Round Robin Period */
-
-/* Bit masks for DMACx_TCCNT */
-
-#define         DCB_TRAFFIC_COUNT  0xf        /* DCB Traffic Control Count */
-#define         DEB_TRAFFIC_COUNT  0xf0       /* DEB Traffic Control Count */
-#define         DAB_TRAFFIC_COUNT  0x700      /* DAB Traffic Control Count */
-#define    MDMA_ROUND_ROBIN_COUNT  0xf800     /* MDMA Round Robin Count */
-
-/* Bit masks for DMAC1_PERIMUX */
-
-#define                   PMUXSDH  0x1        /* Peripheral Select for DMA22 channel */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
-/* EBIU_AMGCTL Masks                                                                                                                                    */
-#define AMCKEN                  0x0001          /* Enable CLKOUT                                                                        */
-#define AMBEN_NONE              0x0000          /* All Banks Disabled                                                           */
-#define AMBEN_B0                0x0002          /* Enable Async Memory Bank 0 only                                      */
-#define AMBEN_B0_B1             0x0004          /* Enable Async Memory Banks 0 & 1 only                         */
-#define AMBEN_B0_B1_B2  0x0006          /* Enable Async Memory Banks 0, 1, and 2                        */
-#define AMBEN_ALL               0x0008          /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
-
-
-/* Bit masks for EBIU_AMBCTL0 */
-
-#define                   B0RDYEN  0x1        /* Bank 0 ARDY Enable */
-#define                  B0RDYPOL  0x2        /* Bank 0 ARDY Polarity */
-#define                      B0TT  0xc        /* Bank 0 transition time */
-#define                      B0ST  0x30       /* Bank 0 Setup time */
-#define                      B0HT  0xc0       /* Bank 0 Hold time */
-#define                     B0RAT  0xf00      /* Bank 0 Read access time */
-#define                     B0WAT  0xf000     /* Bank 0 write access time */
-#define                   B1RDYEN  0x10000    /* Bank 1 ARDY Enable */
-#define                  B1RDYPOL  0x20000    /* Bank 1 ARDY Polarity */
-#define                      B1TT  0xc0000    /* Bank 1 transition time */
-#define                      B1ST  0x300000   /* Bank 1 Setup time */
-#define                      B1HT  0xc00000   /* Bank 1 Hold time */
-#define                     B1RAT  0xf000000  /* Bank 1 Read access time */
-#define                     B1WAT  0xf0000000 /* Bank 1 write access time */
-
-/* Bit masks for EBIU_AMBCTL1 */
-
-#define                   B2RDYEN  0x1        /* Bank 2 ARDY Enable */
-#define                  B2RDYPOL  0x2        /* Bank 2 ARDY Polarity */
-#define                      B2TT  0xc        /* Bank 2 transition time */
-#define                      B2ST  0x30       /* Bank 2 Setup time */
-#define                      B2HT  0xc0       /* Bank 2 Hold time */
-#define                     B2RAT  0xf00      /* Bank 2 Read access time */
-#define                     B2WAT  0xf000     /* Bank 2 write access time */
-#define                   B3RDYEN  0x10000    /* Bank 3 ARDY Enable */
-#define                  B3RDYPOL  0x20000    /* Bank 3 ARDY Polarity */
-#define                      B3TT  0xc0000    /* Bank 3 transition time */
-#define                      B3ST  0x300000   /* Bank 3 Setup time */
-#define                      B3HT  0xc00000   /* Bank 3 Hold time */
-#define                     B3RAT  0xf000000  /* Bank 3 Read access time */
-#define                     B3WAT  0xf0000000 /* Bank 3 write access time */
-
-/* Bit masks for EBIU_MBSCTL */
-
-#define                  AMSB0CTL  0x3        /* Async Memory Bank 0 select */
-#define                  AMSB1CTL  0xc        /* Async Memory Bank 1 select */
-#define                  AMSB2CTL  0x30       /* Async Memory Bank 2 select */
-#define                  AMSB3CTL  0xc0       /* Async Memory Bank 3 select */
-
-/* Bit masks for EBIU_MODE */
-
-#define                    B0MODE  0x3        /* Async Memory Bank 0 Access Mode */
-#define                    B1MODE  0xc        /* Async Memory Bank 1 Access Mode */
-#define                    B2MODE  0x30       /* Async Memory Bank 2 Access Mode */
-#define                    B3MODE  0xc0       /* Async Memory Bank 3 Access Mode */
-
-/* Bit masks for EBIU_FCTL */
-
-#define               TESTSETLOCK  0x1        /* Test set lock */
-#define                      BCLK  0x6        /* Burst clock frequency */
-#define                      PGWS  0x38       /* Page wait states */
-#define                      PGSZ  0x40       /* Page size */
-#define                      RDDL  0x380      /* Read data delay */
-
-/* Bit masks for EBIU_ARBSTAT */
-
-#define                   ARBSTAT  0x1        /* Arbitration status */
-#define                    BGSTAT  0x2        /* Bus grant status */
-
-/* Bit masks for EBIU_DDRCTL0 */
-
-#define                     TREFI  0x3fff     /* Refresh Interval */
-#define                      TRFC  0x3c000    /* Auto-refresh command period */
-#define                       TRP  0x3c0000   /* Pre charge-to-active command period */
-#define                      TRAS  0x3c00000  /* Min Active-to-pre charge time */
-#define                       TRC  0x3c000000 /* Active-to-active time */
-#define DDR_TRAS(x)             ((x<<22)&TRAS)  /* DDR tRAS = (1~15) cycles */
-#define DDR_TRP(x)              ((x<<18)&TRP)   /* DDR tRP = (1~15) cycles */
-#define DDR_TRC(x)              ((x<<26)&TRC)   /* DDR tRC = (1~15) cycles */
-#define DDR_TRFC(x)             ((x<<14)&TRFC)  /* DDR tRFC = (1~15) cycles */
-#define DDR_TREFI(x)            (x&TREFI)       /* DDR tRFC = (1~15) cycles */
-
-/* Bit masks for EBIU_DDRCTL1 */
-
-#define                      TRCD  0xf        /* Active-to-Read/write delay */
-#define                      TMRD  0xf0       /* Mode register set to active */
-#define                       TWR  0x300      /* Write Recovery time */
-#define               DDRDATWIDTH  0x3000     /* DDR data width */
-#define                  EXTBANKS  0xc000     /* External banks */
-#define               DDRDEVWIDTH  0x30000    /* DDR device width */
-#define                DDRDEVSIZE  0xc0000    /* DDR device size */
-#define                      TWTR  0xf0000000 /* Write-to-read delay */
-#define DDR_TWTR(x)             ((x<<28)&TWTR)  /* DDR tWTR = (1~15) cycles */
-#define DDR_TMRD(x)             ((x<<4)&TMRD)   /* DDR tMRD = (1~15) cycles */
-#define DDR_TWR(x)              ((x<<8)&TWR)    /* DDR tWR = (1~15) cycles */
-#define DDR_TRCD(x)             (x&TRCD)        /* DDR tRCD = (1~15) cycles */
-#define DDR_DATWIDTH            0x2000          /* DDR data width */
-#define EXTBANK_1               0               /* 1 external bank */
-#define EXTBANK_2               0x4000          /* 2 external banks */
-#define DEVSZ_64                0x40000         /* DDR External Bank Size = 64MB */
-#define DEVSZ_128               0x80000         /* DDR External Bank Size = 128MB */
-#define DEVSZ_256               0xc0000         /* DDR External Bank Size = 256MB */
-#define DEVSZ_512               0               /* DDR External Bank Size = 512MB */
-#define DEVWD_4                 0               /* DDR Device Width = 4 Bits    */
-#define DEVWD_8                 0x10000         /* DDR Device Width = 8 Bits    */
-#define DEVWD_16                0x20000         /* DDR Device Width = 16 Bits    */
-
-/* Bit masks for EBIU_DDRCTL2 */
-
-#define               BURSTLENGTH  0x7        /* Burst length */
-#define                CASLATENCY  0x70       /* CAS latency */
-#define                  DLLRESET  0x100      /* DLL Reset */
-#define                      REGE  0x1000     /* Register mode enable */
-#define CL_1_5                  0x50            /* DDR CAS Latency = 1.5 cycles */
-#define CL_2                    0x20            /* DDR CAS Latency = 2 cycles */
-#define CL_2_5                  0x60            /* DDR CAS Latency = 2.5 cycles */
-#define CL_3                    0x30            /* DDR CAS Latency = 3 cycles */
-
-/* Bit masks for EBIU_DDRCTL3 */
-
-#define                      PASR  0x7        /* Partial array self-refresh */
-
-/* Bit masks for EBIU_DDRQUE */
-
-#define                DEB1_PFLEN  0x3        /* Pre fetch length for DEB1 accesses */
-#define                DEB2_PFLEN  0xc        /* Pre fetch length for DEB2 accesses */
-#define                DEB3_PFLEN  0x30       /* Pre fetch length for DEB3 accesses */
-#define          DEB_ARB_PRIORITY  0x700      /* Arbitration between DEB busses */
-#define               DEB1_URGENT  0x1000     /* DEB1 Urgent */
-#define               DEB2_URGENT  0x2000     /* DEB2 Urgent */
-#define               DEB3_URGENT  0x4000     /* DEB3 Urgent */
-
-/* Bit masks for EBIU_ERRMST */
-
-#define                DEB1_ERROR  0x1        /* DEB1 Error */
-#define                DEB2_ERROR  0x2        /* DEB2 Error */
-#define                DEB3_ERROR  0x4        /* DEB3 Error */
-#define                CORE_ERROR  0x8        /* Core error */
-#define                DEB_MERROR  0x10       /* DEB1 Error (2nd) */
-#define               DEB2_MERROR  0x20       /* DEB2 Error (2nd) */
-#define               DEB3_MERROR  0x40       /* DEB3 Error (2nd) */
-#define               CORE_MERROR  0x80       /* Core Error (2nd) */
-
-/* Bit masks for EBIU_ERRADD */
-
-#define             ERROR_ADDRESS  0xffffffff /* Error Address */
-
-/* Bit masks for EBIU_RSTCTL */
-
-#define                 DDRSRESET  0x1        /* DDR soft reset */
-#define               PFTCHSRESET  0x4        /* DDR prefetch reset */
-#define                     SRREQ  0x8        /* Self-refresh request */
-#define                     SRACK  0x10       /* Self-refresh acknowledge */
-#define                MDDRENABLE  0x20       /* Mobile DDR enable */
-
-/* Bit masks for EBIU_DDRBRC0 */
-
-#define                      BRC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC1 */
-
-#define                      BRC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC2 */
-
-#define                      BRC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC3 */
-
-#define                      BRC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC4 */
-
-#define                      BRC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC5 */
-
-#define                      BRC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC6 */
-
-#define                      BRC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBRC7 */
-
-#define                      BRC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC0 */
-
-#define                      BWC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC1 */
-
-#define                      BWC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC2 */
-
-#define                      BWC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC3 */
-
-#define                      BWC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC4 */
-
-#define                      BWC4  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC5 */
-
-#define                      BWC5  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC6 */
-
-#define                      BWC6  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRBWC7 */
-
-#define                      BWC7  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRACCT */
-
-#define                      ACCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRTACT */
-
-#define                      TECT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRARCT */
-
-#define                      ARCT  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC0 */
-
-#define                       GC0  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC1 */
-
-#define                       GC1  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC2 */
-
-#define                       GC2  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRGC3 */
-
-#define                       GC3  0xffffffff /* Count */
-
-/* Bit masks for EBIU_DDRMCEN */
-
-#define                B0WCENABLE  0x1        /* Bank 0 write count enable */
-#define                B1WCENABLE  0x2        /* Bank 1 write count enable */
-#define                B2WCENABLE  0x4        /* Bank 2 write count enable */
-#define                B3WCENABLE  0x8        /* Bank 3 write count enable */
-#define                B4WCENABLE  0x10       /* Bank 4 write count enable */
-#define                B5WCENABLE  0x20       /* Bank 5 write count enable */
-#define                B6WCENABLE  0x40       /* Bank 6 write count enable */
-#define                B7WCENABLE  0x80       /* Bank 7 write count enable */
-#define                B0RCENABLE  0x100      /* Bank 0 read count enable */
-#define                B1RCENABLE  0x200      /* Bank 1 read count enable */
-#define                B2RCENABLE  0x400      /* Bank 2 read count enable */
-#define                B3RCENABLE  0x800      /* Bank 3 read count enable */
-#define                B4RCENABLE  0x1000     /* Bank 4 read count enable */
-#define                B5RCENABLE  0x2000     /* Bank 5 read count enable */
-#define                B6RCENABLE  0x4000     /* Bank 6 read count enable */
-#define                B7RCENABLE  0x8000     /* Bank 7 read count enable */
-#define             ROWACTCENABLE  0x10000    /* DDR Row activate count enable */
-#define                RWTCENABLE  0x20000    /* DDR R/W Turn around count enable */
-#define                 ARCENABLE  0x40000    /* DDR Auto-refresh count enable */
-#define                 GC0ENABLE  0x100000   /* DDR Grant count 0 enable */
-#define                 GC1ENABLE  0x200000   /* DDR Grant count 1 enable */
-#define                 GC2ENABLE  0x400000   /* DDR Grant count 2 enable */
-#define                 GC3ENABLE  0x800000   /* DDR Grant count 3 enable */
-#define                 GCCONTROL  0x3000000  /* DDR Grant Count Control */
-
-/* Bit masks for EBIU_DDRMCCL */
-
-#define                 CB0WCOUNT  0x1        /* Clear write count 0 */
-#define                 CB1WCOUNT  0x2        /* Clear write count 1 */
-#define                 CB2WCOUNT  0x4        /* Clear write count 2 */
-#define                 CB3WCOUNT  0x8        /* Clear write count 3 */
-#define                 CB4WCOUNT  0x10       /* Clear write count 4 */
-#define                 CB5WCOUNT  0x20       /* Clear write count 5 */
-#define                 CB6WCOUNT  0x40       /* Clear write count 6 */
-#define                 CB7WCOUNT  0x80       /* Clear write count 7 */
-#define                  CBRCOUNT  0x100      /* Clear read count 0 */
-#define                 CB1RCOUNT  0x200      /* Clear read count 1 */
-#define                 CB2RCOUNT  0x400      /* Clear read count 2 */
-#define                 CB3RCOUNT  0x800      /* Clear read count 3 */
-#define                 CB4RCOUNT  0x1000     /* Clear read count 4 */
-#define                 CB5RCOUNT  0x2000     /* Clear read count 5 */
-#define                 CB6RCOUNT  0x4000     /* Clear read count 6 */
-#define                 CB7RCOUNT  0x8000     /* Clear read count 7 */
-#define                  CRACOUNT  0x10000    /* Clear row activation count */
-#define                CRWTACOUNT  0x20000    /* Clear R/W turn-around count */
-#define                  CARCOUNT  0x40000    /* Clear auto-refresh count */
-#define                  CG0COUNT  0x100000   /* Clear grant count 0 */
-#define                  CG1COUNT  0x200000   /* Clear grant count 1 */
-#define                  CG2COUNT  0x400000   /* Clear grant count 2 */
-#define                  CG3COUNT  0x800000   /* Clear grant count 3 */
-
-/* Bit masks for (PORTx is PORTA - PORTJ) includes PORTx_FER, PORTx_SET, PORTx_CLEAR, PORTx_DIR_SET, PORTx_DIR_CLEAR, PORTx_INEN */
-
-#define                       Px0  0x1        /* GPIO 0 */
-#define                       Px1  0x2        /* GPIO 1 */
-#define                       Px2  0x4        /* GPIO 2 */
-#define                       Px3  0x8        /* GPIO 3 */
-#define                       Px4  0x10       /* GPIO 4 */
-#define                       Px5  0x20       /* GPIO 5 */
-#define                       Px6  0x40       /* GPIO 6 */
-#define                       Px7  0x80       /* GPIO 7 */
-#define                       Px8  0x100      /* GPIO 8 */
-#define                       Px9  0x200      /* GPIO 9 */
-#define                      Px10  0x400      /* GPIO 10 */
-#define                      Px11  0x800      /* GPIO 11 */
-#define                      Px12  0x1000     /* GPIO 12 */
-#define                      Px13  0x2000     /* GPIO 13 */
-#define                      Px14  0x4000     /* GPIO 14 */
-#define                      Px15  0x8000     /* GPIO 15 */
-
-/* Bit masks for PORTA_MUX - PORTJ_MUX */
-
-#define                      PxM0  0x3        /* GPIO Mux 0 */
-#define                      PxM1  0xc        /* GPIO Mux 1 */
-#define                      PxM2  0x30       /* GPIO Mux 2 */
-#define                      PxM3  0xc0       /* GPIO Mux 3 */
-#define                      PxM4  0x300      /* GPIO Mux 4 */
-#define                      PxM5  0xc00      /* GPIO Mux 5 */
-#define                      PxM6  0x3000     /* GPIO Mux 6 */
-#define                      PxM7  0xc000     /* GPIO Mux 7 */
-#define                      PxM8  0x30000    /* GPIO Mux 8 */
-#define                      PxM9  0xc0000    /* GPIO Mux 9 */
-#define                     PxM10  0x300000   /* GPIO Mux 10 */
-#define                     PxM11  0xc00000   /* GPIO Mux 11 */
-#define                     PxM12  0x3000000  /* GPIO Mux 12 */
-#define                     PxM13  0xc000000  /* GPIO Mux 13 */
-#define                     PxM14  0x30000000 /* GPIO Mux 14 */
-#define                     PxM15  0xc0000000 /* GPIO Mux 15 */
-
-
-/* Bit masks for PINTx_MASK_SET/CLEAR, PINTx_REQUEST, PINTx_LATCH, PINTx_EDGE_SET/CLEAR, PINTx_INVERT_SET/CLEAR, PINTx_PINTSTATE */
-
-#define                       IB0  0x1        /* Interrupt Bit 0 */
-#define                       IB1  0x2        /* Interrupt Bit 1 */
-#define                       IB2  0x4        /* Interrupt Bit 2 */
-#define                       IB3  0x8        /* Interrupt Bit 3 */
-#define                       IB4  0x10       /* Interrupt Bit 4 */
-#define                       IB5  0x20       /* Interrupt Bit 5 */
-#define                       IB6  0x40       /* Interrupt Bit 6 */
-#define                       IB7  0x80       /* Interrupt Bit 7 */
-#define                       IB8  0x100      /* Interrupt Bit 8 */
-#define                       IB9  0x200      /* Interrupt Bit 9 */
-#define                      IB10  0x400      /* Interrupt Bit 10 */
-#define                      IB11  0x800      /* Interrupt Bit 11 */
-#define                      IB12  0x1000     /* Interrupt Bit 12 */
-#define                      IB13  0x2000     /* Interrupt Bit 13 */
-#define                      IB14  0x4000     /* Interrupt Bit 14 */
-#define                      IB15  0x8000     /* Interrupt Bit 15 */
-
-/* Bit masks for TIMERx_CONFIG */
-
-#define                     TMODE  0x3        /* Timer Mode */
-#define                  PULSE_HI  0x4        /* Pulse Polarity */
-#define                PERIOD_CNT  0x8        /* Period Count */
-#define                   IRQ_ENA  0x10       /* Interrupt Request Enable */
-#define                   TIN_SEL  0x20       /* Timer Input Select */
-#define                   OUT_DIS  0x40       /* Output Pad Disable */
-#define                   CLK_SEL  0x80       /* Timer Clock Select */
-#define                 TOGGLE_HI  0x100      /* Toggle Mode */
-#define                   EMU_RUN  0x200      /* Emulation Behavior Select */
-#define                   ERR_TYP  0xc000     /* Error Type */
-
-/* Bit masks for TIMER_ENABLE0 */
-
-#define                    TIMEN0  0x1        /* Timer 0 Enable */
-#define                    TIMEN1  0x2        /* Timer 1 Enable */
-#define                    TIMEN2  0x4        /* Timer 2 Enable */
-#define                    TIMEN3  0x8        /* Timer 3 Enable */
-#define                    TIMEN4  0x10       /* Timer 4 Enable */
-#define                    TIMEN5  0x20       /* Timer 5 Enable */
-#define                    TIMEN6  0x40       /* Timer 6 Enable */
-#define                    TIMEN7  0x80       /* Timer 7 Enable */
-
-/* Bit masks for TIMER_DISABLE0 */
-
-#define                   TIMDIS0  0x1        /* Timer 0 Disable */
-#define                   TIMDIS1  0x2        /* Timer 1 Disable */
-#define                   TIMDIS2  0x4        /* Timer 2 Disable */
-#define                   TIMDIS3  0x8        /* Timer 3 Disable */
-#define                   TIMDIS4  0x10       /* Timer 4 Disable */
-#define                   TIMDIS5  0x20       /* Timer 5 Disable */
-#define                   TIMDIS6  0x40       /* Timer 6 Disable */
-#define                   TIMDIS7  0x80       /* Timer 7 Disable */
-
-/* Bit masks for TIMER_STATUS0 */
-
-#define                    TIMIL0  0x1        /* Timer 0 Interrupt */
-#define                    TIMIL1  0x2        /* Timer 1 Interrupt */
-#define                    TIMIL2  0x4        /* Timer 2 Interrupt */
-#define                    TIMIL3  0x8        /* Timer 3 Interrupt */
-#define                 TOVF_ERR0  0x10       /* Timer 0 Counter Overflow */
-#define                 TOVF_ERR1  0x20       /* Timer 1 Counter Overflow */
-#define                 TOVF_ERR2  0x40       /* Timer 2 Counter Overflow */
-#define                 TOVF_ERR3  0x80       /* Timer 3 Counter Overflow */
-#define                     TRUN0  0x1000     /* Timer 0 Slave Enable Status */
-#define                     TRUN1  0x2000     /* Timer 1 Slave Enable Status */
-#define                     TRUN2  0x4000     /* Timer 2 Slave Enable Status */
-#define                     TRUN3  0x8000     /* Timer 3 Slave Enable Status */
-#define                    TIMIL4  0x10000    /* Timer 4 Interrupt */
-#define                    TIMIL5  0x20000    /* Timer 5 Interrupt */
-#define                    TIMIL6  0x40000    /* Timer 6 Interrupt */
-#define                    TIMIL7  0x80000    /* Timer 7 Interrupt */
-#define                 TOVF_ERR4  0x100000   /* Timer 4 Counter Overflow */
-#define                 TOVF_ERR5  0x200000   /* Timer 5 Counter Overflow */
-#define                 TOVF_ERR6  0x400000   /* Timer 6 Counter Overflow */
-#define                 TOVF_ERR7  0x800000   /* Timer 7 Counter Overflow */
-#define                     TRUN4  0x10000000 /* Timer 4 Slave Enable Status */
-#define                     TRUN5  0x20000000 /* Timer 5 Slave Enable Status */
-#define                     TRUN6  0x40000000 /* Timer 6 Slave Enable Status */
-#define                     TRUN7  0x80000000 /* Timer 7 Slave Enable Status */
-
-/* Bit masks for WDOG_CTL */
-
-#define                      WDEV  0x6        /* Watchdog Event */
-#define                      WDEN  0xff0      /* Watchdog Enable */
-#define                      WDRO  0x8000     /* Watchdog Rolled Over */
-
-/* Bit masks for CNT_CONFIG */
-
-#define                      CNTE  0x1        /* Counter Enable */
-#define                      DEBE  0x2        /* Debounce Enable */
-#define                    CDGINV  0x10       /* CDG Pin Polarity Invert */
-#define                    CUDINV  0x20       /* CUD Pin Polarity Invert */
-#define                    CZMINV  0x40       /* CZM Pin Polarity Invert */
-#define                   CNTMODE  0x700      /* Counter Operating Mode */
-#define                      ZMZC  0x800      /* CZM Zeroes Counter Enable */
-#define                   BNDMODE  0x3000     /* Boundary register Mode */
-#define                    INPDIS  0x8000     /* CUG and CDG Input Disable */
-
-/* Bit masks for CNT_IMASK */
-
-#define                      ICIE  0x1        /* Illegal Gray/Binary Code Interrupt Enable */
-#define                      UCIE  0x2        /* Up count Interrupt Enable */
-#define                      DCIE  0x4        /* Down count Interrupt Enable */
-#define                    MINCIE  0x8        /* Min Count Interrupt Enable */
-#define                    MAXCIE  0x10       /* Max Count Interrupt Enable */
-#define                   COV31IE  0x20       /* Bit 31 Overflow Interrupt Enable */
-#define                   COV15IE  0x40       /* Bit 15 Overflow Interrupt Enable */
-#define                   CZEROIE  0x80       /* Count to Zero Interrupt Enable */
-#define                     CZMIE  0x100      /* CZM Pin Interrupt Enable */
-#define                    CZMEIE  0x200      /* CZM Error Interrupt Enable */
-#define                    CZMZIE  0x400      /* CZM Zeroes Counter Interrupt Enable */
-
-/* Bit masks for CNT_STATUS */
-
-#define                      ICII  0x1        /* Illegal Gray/Binary Code Interrupt Identifier */
-#define                      UCII  0x2        /* Up count Interrupt Identifier */
-#define                      DCII  0x4        /* Down count Interrupt Identifier */
-#define                    MINCII  0x8        /* Min Count Interrupt Identifier */
-#define                    MAXCII  0x10       /* Max Count Interrupt Identifier */
-#define                   COV31II  0x20       /* Bit 31 Overflow Interrupt Identifier */
-#define                   COV15II  0x40       /* Bit 15 Overflow Interrupt Identifier */
-#define                   CZEROII  0x80       /* Count to Zero Interrupt Identifier */
-#define                     CZMII  0x100      /* CZM Pin Interrupt Identifier */
-#define                    CZMEII  0x200      /* CZM Error Interrupt Identifier */
-#define                    CZMZII  0x400      /* CZM Zeroes Counter Interrupt Identifier */
-
-/* Bit masks for CNT_COMMAND */
-
-#define                    W1LCNT  0xf        /* Load Counter Register */
-#define                    W1LMIN  0xf0       /* Load Min Register */
-#define                    W1LMAX  0xf00      /* Load Max Register */
-#define                  W1ZMONCE  0x1000     /* Enable CZM Clear Counter Once */
-
-/* Bit masks for CNT_DEBOUNCE */
-
-#define                 DPRESCALE  0xf        /* Load Counter Register */
-
-/* Bit masks for RTC_STAT */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define               DAY_COUNTER  0xfffe0000 /* Day Counter */
-
-/* Bit masks for RTC_ICTL */
-
-#define STOPWATCH_INTERRUPT_ENABLE  0x1        /* Stopwatch Interrupt Enable */
-#define    ALARM_INTERRUPT_ENABLE  0x2        /* Alarm Interrupt Enable */
-#define  SECONDS_INTERRUPT_ENABLE  0x4        /* Seconds Interrupt Enable */
-#define  MINUTES_INTERRUPT_ENABLE  0x8        /* Minutes Interrupt Enable */
-#define    HOURS_INTERRUPT_ENABLE  0x10       /* Hours Interrupt Enable */
-#define TWENTY_FOUR_HOURS_INTERRUPT_ENABLE  0x20       /* 24 Hours Interrupt Enable */
-#define DAY_ALARM_INTERRUPT_ENABLE  0x40       /* Day Alarm Interrupt Enable */
-#define WRITE_COMPLETE_INTERRUPT_ENABLE  0x8000     /* Write Complete Interrupt Enable */
-
-/* Bit masks for RTC_ISTAT */
-
-#define      STOPWATCH_EVENT_FLAG  0x1        /* Stopwatch Event Flag */
-#define          ALARM_EVENT_FLAG  0x2        /* Alarm Event Flag */
-#define        SECONDS_EVENT_FLAG  0x4        /* Seconds Event Flag */
-#define        MINUTES_EVENT_FLAG  0x8        /* Minutes Event Flag */
-#define          HOURS_EVENT_FLAG  0x10       /* Hours Event Flag */
-#define TWENTY_FOUR_HOURS_EVENT_FLAG  0x20       /* 24 Hours Event Flag */
-#define      DAY_ALARM_EVENT_FLAG  0x40       /* Day Alarm Event Flag */
-#define     WRITE_PENDING__STATUS  0x4000     /* Write Pending  Status */
-#define            WRITE_COMPLETE  0x8000     /* Write Complete */
-
-/* Bit masks for RTC_SWCNT */
-
-#define           STOPWATCH_COUNT  0xffff     /* Stopwatch Count */
-
-/* Bit masks for RTC_ALARM */
-
-#define                   SECONDS  0x3f       /* Seconds */
-#define                   MINUTES  0xfc0      /* Minutes */
-#define                     HOURS  0x1f000    /* Hours */
-#define                       DAY  0xfffe0000 /* Day */
-
-/* Bit masks for RTC_PREN */
-
-#define                      PREN  0x1        /* Prescaler Enable */
-
-/* Bit masks for OTP_CONTROL */
-
-#define                FUSE_FADDR  0x1ff      /* OTP/Fuse Address */
-#define                      FIEN  0x800      /* OTP/Fuse Interrupt Enable */
-#define                  FTESTDEC  0x1000     /* OTP/Fuse Test Decoder */
-#define                   FWRTEST  0x2000     /* OTP/Fuse Write Test */
-#define                     FRDEN  0x4000     /* OTP/Fuse Read Enable */
-#define                     FWREN  0x8000     /* OTP/Fuse Write Enable */
-
-/* Bit masks for OTP_BEN */
-
-#define                      FBEN  0xffff     /* OTP/Fuse Byte Enable */
-
-/* Bit masks for OTP_STATUS */
-
-#define                     FCOMP  0x1        /* OTP/Fuse Access Complete */
-#define                    FERROR  0x2        /* OTP/Fuse Access Error */
-#define                  MMRGLOAD  0x10       /* Memory Mapped Register Gasket Load */
-#define                  MMRGLOCK  0x20       /* Memory Mapped Register Gasket Lock */
-#define                    FPGMEN  0x40       /* OTP/Fuse Program Enable */
-
-/* Bit masks for OTP_TIMING */
-
-#define                   USECDIV  0xff       /* Micro Second Divider */
-#define                   READACC  0x7f00     /* Read Access Time */
-#define                   CPUMPRL  0x38000    /* Charge Pump Release Time */
-#define                   CPUMPSU  0xc0000    /* Charge Pump Setup Time */
-#define                   CPUMPHD  0xf00000   /* Charge Pump Hold Time */
-#define                   PGMTIME  0xff000000 /* Program Time */
-
-/* Bit masks for SECURE_SYSSWT */
-
-#define                   EMUDABL  0x1        /* Emulation Disable. */
-#define                   RSTDABL  0x2        /* Reset Disable */
-#define                   L1IDABL  0x1c       /* L1 Instruction Memory Disable. */
-#define                  L1DADABL  0xe0       /* L1 Data Bank A Memory Disable. */
-#define                  L1DBDABL  0x700      /* L1 Data Bank B Memory Disable. */
-#define                   DMA0OVR  0x800      /* DMA0 Memory Access Override */
-#define                   DMA1OVR  0x1000     /* DMA1 Memory Access Override */
-#define                    EMUOVR  0x4000     /* Emulation Override */
-#define                    OTPSEN  0x8000     /* OTP Secrets Enable. */
-#define                    L2DABL  0x70000    /* L2 Memory Disable. */
-
-/* Bit masks for SECURE_CONTROL */
-
-#define                   SECURE0  0x1        /* SECURE 0 */
-#define                   SECURE1  0x2        /* SECURE 1 */
-#define                   SECURE2  0x4        /* SECURE 2 */
-#define                   SECURE3  0x8        /* SECURE 3 */
-
-/* Bit masks for SECURE_STATUS */
-
-#define                   SECMODE  0x3        /* Secured Mode Control State */
-#define                       NMI  0x4        /* Non Maskable Interrupt */
-#define                   AFVALID  0x8        /* Authentication Firmware Valid */
-#define                    AFEXIT  0x10       /* Authentication Firmware Exit */
-#define                   SECSTAT  0xe0       /* Secure Status */
-
-/* Bit masks for PLL_DIV */
-
-#define                      CSEL  0x30       /* Core Select */
-#define                      SSEL  0xf        /* System Select */
-#define                 CSEL_DIV1       0x0000  /* CCLK = VCO / 1 */
-#define                 CSEL_DIV2       0x0010  /* CCLK = VCO / 2 */
-#define                 CSEL_DIV4       0x0020  /* CCLK = VCO / 4 */
-#define                 CSEL_DIV8       0x0030  /* CCLK = VCO / 8 */
-
-/* Bit masks for PLL_CTL */
-
-#define                      MSEL  0x7e00     /* Multiplier Select */
-#define                    BYPASS  0x100      /* PLL Bypass Enable */
-#define              OUTPUT_DELAY  0x80       /* External Memory Output Delay Enable */
-#define               INPUT_DELAY  0x40       /* External Memory Input Delay Enable */
-#define                      PDWN  0x20       /* Power Down */
-#define                    STOPCK  0x8        /* Stop Clock */
-#define                   PLL_OFF  0x2        /* Disable PLL */
-#define                        DF  0x1        /* Divide Frequency */
-
-/* SWRST Masks */
-#define              SYSTEM_RESET 0x0007       /* Initiates A System Software Reset */
-#define              DOUBLE_FAULT 0x0008       /* Core Double Fault Causes Reset */
-#define              RESET_DOUBLE 0x2000       /* SW Reset Generated By Core Double-Fault */
-#define                RESET_WDOG 0x4000       /* SW Reset Generated By Watchdog Timer */
-#define            RESET_SOFTWARE 0x8000       /* SW Reset Occurred Since Last Read Of SWRST */
-
-/* Bit masks for PLL_STAT */
-
-#define                PLL_LOCKED  0x20       /* PLL Locked Status */
-#define        ACTIVE_PLLDISABLED  0x4        /* Active Mode With PLL Disabled */
-#define                   FULL_ON  0x2        /* Full-On Mode */
-#define         ACTIVE_PLLENABLED  0x1        /* Active Mode With PLL Enabled */
-#define                     RTCWS  0x400      /* RTC/Reset Wake-Up Status */
-#define                     CANWS  0x800      /* CAN Wake-Up Status */
-#define                     USBWS  0x2000     /* USB Wake-Up Status */
-#define                    KPADWS  0x4000     /* Keypad Wake-Up Status */
-#define                     ROTWS  0x8000     /* Rotary Wake-Up Status */
-#define                      GPWS  0x1000     /* General-Purpose Wake-Up Status */
-
-/* Bit masks for VR_CTL */
-
-#define                      FREQ  0x3        /* Regulator Switching Frequency */
-#define                      GAIN  0xc        /* Voltage Output Level Gain */
-#define                      VLEV  0xf0       /* Internal Voltage Level */
-#define                   SCKELOW  0x8000     /* Drive SCKE Low During Reset Enable */
-#define                      WAKE  0x100      /* RTC/Reset Wake-Up Enable */
-#define                     CANWE  0x200      /* CAN0/1 Wake-Up Enable */
-#define                      GPWE  0x400      /* General-Purpose Wake-Up Enable */
-#define                     USBWE  0x800      /* USB Wake-Up Enable */
-#define                    KPADWE  0x1000     /* Keypad Wake-Up Enable */
-#define                     ROTWE  0x2000     /* Rotary Wake-Up Enable */
-
-#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
-
-#define GAIN_5                  0x0000  /* GAIN = 5*/
-#define GAIN_10                 0x0004  /* GAIN = 1*/
-#define GAIN_20                 0x0008  /* GAIN = 2*/
-#define GAIN_50                 0x000C  /* GAIN = 5*/
-
-#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
-/* Bit masks for NFC_CTL */
-
-#define                    WR_DLY  0xf        /* Write Strobe Delay */
-#define                    RD_DLY  0xf0       /* Read Strobe Delay */
-#define                    NWIDTH  0x100      /* NAND Data Width */
-#define                   PG_SIZE  0x200      /* Page Size */
-
-/* Bit masks for NFC_STAT */
-
-#define                     NBUSY  0x1        /* Not Busy */
-#define                   WB_FULL  0x2        /* Write Buffer Full */
-#define                PG_WR_STAT  0x4        /* Page Write Pending */
-#define                PG_RD_STAT  0x8        /* Page Read Pending */
-#define                  WB_EMPTY  0x10       /* Write Buffer Empty */
-
-/* Bit masks for NFC_IRQSTAT */
-
-#define                  NBUSYIRQ  0x1        /* Not Busy IRQ */
-#define                    WB_OVF  0x2        /* Write Buffer Overflow */
-#define                   WB_EDGE  0x4        /* Write Buffer Edge Detect */
-#define                    RD_RDY  0x8        /* Read Data Ready */
-#define                   WR_DONE  0x10       /* Page Write Done */
-
-/* Bit masks for NFC_IRQMASK */
-
-#define              MASK_BUSYIRQ  0x1        /* Mask Not Busy IRQ */
-#define                MASK_WBOVF  0x2        /* Mask Write Buffer Overflow */
-#define              MASK_WBEMPTY  0x4        /* Mask Write Buffer Empty */
-#define                MASK_RDRDY  0x8        /* Mask Read Data Ready */
-#define               MASK_WRDONE  0x10       /* Mask Write Done */
-
-/* Bit masks for NFC_RST */
-
-#define                   ECC_RST  0x1        /* ECC (and NFC counters) Reset */
-
-/* Bit masks for NFC_PGCTL */
-
-#define               PG_RD_START  0x1        /* Page Read Start */
-#define               PG_WR_START  0x2        /* Page Write Start */
-
-/* Bit masks for NFC_ECC0 */
-
-#define                      ECC0  0x7ff      /* Parity Calculation Result0 */
-
-/* Bit masks for NFC_ECC1 */
-
-#define                      ECC1  0x7ff      /* Parity Calculation Result1 */
-
-/* Bit masks for NFC_ECC2 */
-
-#define                      ECC2  0x7ff      /* Parity Calculation Result2 */
-
-/* Bit masks for NFC_ECC3 */
-
-#define                      ECC3  0x7ff      /* Parity Calculation Result3 */
-
-/* Bit masks for NFC_COUNT */
-
-#define                    ECCCNT  0x3ff      /* Transfer Count */
-
-/* Bit masks for CAN0_CONTROL */
-
-#define                       SRS  0x1        /* Software Reset */
-#define                       DNM  0x2        /* DeviceNet Mode */
-#define                       ABO  0x4        /* Auto Bus On */
-#define                       WBA  0x10       /* Wakeup On CAN Bus Activity */
-#define                       SMR  0x20       /* Sleep Mode Request */
-#define                       CSR  0x40       /* CAN Suspend Mode Request */
-#define                       CCR  0x80       /* CAN Configuration Mode Request */
-
-/* Bit masks for CAN0_STATUS */
-
-#define                        WT  0x1        /* CAN Transmit Warning Flag */
-#define                        WR  0x2        /* CAN Receive Warning Flag */
-#define                        EP  0x4        /* CAN Error Passive Mode */
-#define                       EBO  0x8        /* CAN Error Bus Off Mode */
-#define                       CSA  0x40       /* CAN Suspend Mode Acknowledge */
-#define                       CCA  0x80       /* CAN Configuration Mode Acknowledge */
-#define                     MBPTR  0x1f00     /* Mailbox Pointer */
-#define                       TRM  0x4000     /* Transmit Mode Status */
-#define                       REC  0x8000     /* Receive Mode Status */
-
-/* Bit masks for CAN0_DEBUG */
-
-#define                       DEC  0x1        /* Disable Transmit/Receive Error Counters */
-#define                       DRI  0x2        /* Disable CANRX Input Pin */
-#define                       DTO  0x4        /* Disable CANTX Output Pin */
-#define                       DIL  0x8        /* Disable Internal Loop */
-#define                       MAA  0x10       /* Mode Auto-Acknowledge */
-#define                       MRB  0x20       /* Mode Read Back */
-#define                       CDE  0x8000     /* CAN Debug Mode Enable */
-
-/* Bit masks for CAN0_CLOCK */
-
-#define                       BRP  0x3ff      /* CAN Bit Rate Prescaler */
-
-/* Bit masks for CAN0_TIMING */
-
-#define                       SJW  0x300      /* Synchronization Jump Width */
-#define                       SAM  0x80       /* Sampling */
-#define                     TSEG2  0x70       /* Time Segment 2 */
-#define                     TSEG1  0xf        /* Time Segment 1 */
-
-/* Bit masks for CAN0_INTR */
-
-#define                     CANRX  0x80       /* Serial Input From Transceiver */
-#define                     CANTX  0x40       /* Serial Output To Transceiver */
-#define                     SMACK  0x8        /* Sleep Mode Acknowledge */
-#define                      GIRQ  0x4        /* Global Interrupt Request Status */
-#define                    MBTIRQ  0x2        /* Mailbox Transmit Interrupt Request */
-#define                    MBRIRQ  0x1        /* Mailbox Receive Interrupt Request */
-
-/* Bit masks for CAN0_GIM */
-
-#define                     EWTIM  0x1        /* Error Warning Transmit Interrupt Mask */
-#define                     EWRIM  0x2        /* Error Warning Receive Interrupt Mask */
-#define                      EPIM  0x4        /* Error Passive Interrupt Mask */
-#define                      BOIM  0x8        /* Bus Off Interrupt Mask */
-#define                      WUIM  0x10       /* Wakeup Interrupt Mask */
-#define                     UIAIM  0x20       /* Unimplemented Address Interrupt Mask */
-#define                      AAIM  0x40       /* Abort Acknowledge Interrupt Mask */
-#define                     RMLIM  0x80       /* Receive Message Lost Interrupt Mask */
-#define                     UCEIM  0x100      /* Universal Counter Exceeded Interrupt Mask */
-#define                      ADIM  0x400      /* Access Denied Interrupt Mask */
-
-/* Bit masks for CAN0_GIS */
-
-#define                     EWTIS  0x1        /* Error Warning Transmit Interrupt Status */
-#define                     EWRIS  0x2        /* Error Warning Receive Interrupt Status */
-#define                      EPIS  0x4        /* Error Passive Interrupt Status */
-#define                      BOIS  0x8        /* Bus Off Interrupt Status */
-#define                      WUIS  0x10       /* Wakeup Interrupt Status */
-#define                     UIAIS  0x20       /* Unimplemented Address Interrupt Status */
-#define                      AAIS  0x40       /* Abort Acknowledge Interrupt Status */
-#define                     RMLIS  0x80       /* Receive Message Lost Interrupt Status */
-#define                     UCEIS  0x100      /* Universal Counter Exceeded Interrupt Status */
-#define                      ADIS  0x400      /* Access Denied Interrupt Status */
-
-/* Bit masks for CAN0_GIF */
-
-#define                     EWTIF  0x1        /* Error Warning Transmit Interrupt Flag */
-#define                     EWRIF  0x2        /* Error Warning Receive Interrupt Flag */
-#define                      EPIF  0x4        /* Error Passive Interrupt Flag */
-#define                      BOIF  0x8        /* Bus Off Interrupt Flag */
-#define                      WUIF  0x10       /* Wakeup Interrupt Flag */
-#define                     UIAIF  0x20       /* Unimplemented Address Interrupt Flag */
-#define                      AAIF  0x40       /* Abort Acknowledge Interrupt Flag */
-#define                     RMLIF  0x80       /* Receive Message Lost Interrupt Flag */
-#define                     UCEIF  0x100      /* Universal Counter Exceeded Interrupt Flag */
-#define                      ADIF  0x400      /* Access Denied Interrupt Flag */
-
-/* Bit masks for CAN0_MBTD */
-
-#define                       TDR  0x80       /* Temporary Disable Request */
-#define                       TDA  0x40       /* Temporary Disable Acknowledge */
-#define                     TDPTR  0x1f       /* Temporary Disable Pointer */
-
-/* Bit masks for CAN0_UCCNF */
-
-#define                     UCCNF  0xf        /* Universal Counter Configuration */
-#define                      UCRC  0x20       /* Universal Counter Reload/Clear */
-#define                      UCCT  0x40       /* Universal Counter CAN Trigger */
-#define                       UCE  0x80       /* Universal Counter Enable */
-
-/* Bit masks for CAN0_UCCNT */
-
-#define                     UCCNT  0xffff     /* Universal Counter Count Value */
-
-/* Bit masks for CAN0_UCRC */
-
-#define                     UCVAL  0xffff     /* Universal Counter Reload/Capture Value */
-
-/* Bit masks for CAN0_CEC */
-
-#define                    RXECNT  0xff       /* Receive Error Counter */
-#define                    TXECNT  0xff00     /* Transmit Error Counter */
-
-/* Bit masks for CAN0_ESR */
-
-#define                       FER  0x80       /* Form Error */
-#define                       BEF  0x40       /* Bit Error Flag */
-#define                       SA0  0x20       /* Stuck At Dominant */
-#define                      CRCE  0x10       /* CRC Error */
-#define                       SER  0x8        /* Stuff Bit Error */
-#define                      ACKE  0x4        /* Acknowledge Error */
-
-/* Bit masks for CAN0_EWR */
-
-#define                    EWLTEC  0xff00     /* Transmit Error Warning Limit */
-#define                    EWLREC  0xff       /* Receive Error Warning Limit */
-
-/* Bit masks for CAN0_AMxx_H */
-
-#define                       FDF  0x8000     /* Filter On Data Field */
-#define                       FMD  0x4000     /* Full Mask Data */
-#define                     AMIDE  0x2000     /* Acceptance Mask Identifier Extension */
-#define                    BASEID  0x1ffc     /* Base Identifier */
-#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_AMxx_L */
-
-#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
-#define                       DFM  0xffff     /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_ID1 */
-
-#define                       AME  0x8000     /* Acceptance Mask Enable */
-#define                       RTR  0x4000     /* Remote Transmission Request */
-#define                       IDE  0x2000     /* Identifier Extension */
-#define                    BASEID  0x1ffc     /* Base Identifier */
-#define                  EXTID_HI  0x3        /* Extended Identifier High Bits */
-
-/* Bit masks for CAN0_MBxx_ID0 */
-
-#define                  EXTID_LO  0xffff     /* Extended Identifier Low Bits */
-#define                       DFM  0xffff     /* Data Field Mask */
-
-/* Bit masks for CAN0_MBxx_TIMESTAMP */
-
-#define                       TSV  0xffff     /* Time Stamp Value */
-
-/* Bit masks for CAN0_MBxx_LENGTH */
-
-#define                       DLC  0xf        /* Data Length Code */
-
-/* Bit masks for CAN0_MBxx_DATA3 */
-
-#define                 CAN_BYTE0  0xff00     /* Data Field Byte 0 */
-#define                 CAN_BYTE1  0xff       /* Data Field Byte 1 */
-
-/* Bit masks for CAN0_MBxx_DATA2 */
-
-#define                 CAN_BYTE2  0xff00     /* Data Field Byte 2 */
-#define                 CAN_BYTE3  0xff       /* Data Field Byte 3 */
-
-/* Bit masks for CAN0_MBxx_DATA1 */
-
-#define                 CAN_BYTE4  0xff00     /* Data Field Byte 4 */
-#define                 CAN_BYTE5  0xff       /* Data Field Byte 5 */
-
-/* Bit masks for CAN0_MBxx_DATA0 */
-
-#define                 CAN_BYTE6  0xff00     /* Data Field Byte 6 */
-#define                 CAN_BYTE7  0xff       /* Data Field Byte 7 */
-
-/* Bit masks for CAN0_MC1 */
-
-#define                       MC0  0x1        /* Mailbox 0 Enable */
-#define                       MC1  0x2        /* Mailbox 1 Enable */
-#define                       MC2  0x4        /* Mailbox 2 Enable */
-#define                       MC3  0x8        /* Mailbox 3 Enable */
-#define                       MC4  0x10       /* Mailbox 4 Enable */
-#define                       MC5  0x20       /* Mailbox 5 Enable */
-#define                       MC6  0x40       /* Mailbox 6 Enable */
-#define                       MC7  0x80       /* Mailbox 7 Enable */
-#define                       MC8  0x100      /* Mailbox 8 Enable */
-#define                       MC9  0x200      /* Mailbox 9 Enable */
-#define                      MC10  0x400      /* Mailbox 10 Enable */
-#define                      MC11  0x800      /* Mailbox 11 Enable */
-#define                      MC12  0x1000     /* Mailbox 12 Enable */
-#define                      MC13  0x2000     /* Mailbox 13 Enable */
-#define                      MC14  0x4000     /* Mailbox 14 Enable */
-#define                      MC15  0x8000     /* Mailbox 15 Enable */
-
-/* Bit masks for CAN0_MC2 */
-
-#define                      MC16  0x1        /* Mailbox 16 Enable */
-#define                      MC17  0x2        /* Mailbox 17 Enable */
-#define                      MC18  0x4        /* Mailbox 18 Enable */
-#define                      MC19  0x8        /* Mailbox 19 Enable */
-#define                      MC20  0x10       /* Mailbox 20 Enable */
-#define                      MC21  0x20       /* Mailbox 21 Enable */
-#define                      MC22  0x40       /* Mailbox 22 Enable */
-#define                      MC23  0x80       /* Mailbox 23 Enable */
-#define                      MC24  0x100      /* Mailbox 24 Enable */
-#define                      MC25  0x200      /* Mailbox 25 Enable */
-#define                      MC26  0x400      /* Mailbox 26 Enable */
-#define                      MC27  0x800      /* Mailbox 27 Enable */
-#define                      MC28  0x1000     /* Mailbox 28 Enable */
-#define                      MC29  0x2000     /* Mailbox 29 Enable */
-#define                      MC30  0x4000     /* Mailbox 30 Enable */
-#define                      MC31  0x8000     /* Mailbox 31 Enable */
-
-/* Bit masks for CAN0_MD1 */
-
-#define                       MD0  0x1        /* Mailbox 0 Receive Enable */
-#define                       MD1  0x2        /* Mailbox 1 Receive Enable */
-#define                       MD2  0x4        /* Mailbox 2 Receive Enable */
-#define                       MD3  0x8        /* Mailbox 3 Receive Enable */
-#define                       MD4  0x10       /* Mailbox 4 Receive Enable */
-#define                       MD5  0x20       /* Mailbox 5 Receive Enable */
-#define                       MD6  0x40       /* Mailbox 6 Receive Enable */
-#define                       MD7  0x80       /* Mailbox 7 Receive Enable */
-#define                       MD8  0x100      /* Mailbox 8 Receive Enable */
-#define                       MD9  0x200      /* Mailbox 9 Receive Enable */
-#define                      MD10  0x400      /* Mailbox 10 Receive Enable */
-#define                      MD11  0x800      /* Mailbox 11 Receive Enable */
-#define                      MD12  0x1000     /* Mailbox 12 Receive Enable */
-#define                      MD13  0x2000     /* Mailbox 13 Receive Enable */
-#define                      MD14  0x4000     /* Mailbox 14 Receive Enable */
-#define                      MD15  0x8000     /* Mailbox 15 Receive Enable */
-
-/* Bit masks for CAN0_MD2 */
-
-#define                      MD16  0x1        /* Mailbox 16 Receive Enable */
-#define                      MD17  0x2        /* Mailbox 17 Receive Enable */
-#define                      MD18  0x4        /* Mailbox 18 Receive Enable */
-#define                      MD19  0x8        /* Mailbox 19 Receive Enable */
-#define                      MD20  0x10       /* Mailbox 20 Receive Enable */
-#define                      MD21  0x20       /* Mailbox 21 Receive Enable */
-#define                      MD22  0x40       /* Mailbox 22 Receive Enable */
-#define                      MD23  0x80       /* Mailbox 23 Receive Enable */
-#define                      MD24  0x100      /* Mailbox 24 Receive Enable */
-#define                      MD25  0x200      /* Mailbox 25 Receive Enable */
-#define                      MD26  0x400      /* Mailbox 26 Receive Enable */
-#define                      MD27  0x800      /* Mailbox 27 Receive Enable */
-#define                      MD28  0x1000     /* Mailbox 28 Receive Enable */
-#define                      MD29  0x2000     /* Mailbox 29 Receive Enable */
-#define                      MD30  0x4000     /* Mailbox 30 Receive Enable */
-#define                      MD31  0x8000     /* Mailbox 31 Receive Enable */
-
-/* Bit masks for CAN0_RMP1 */
-
-#define                      RMP0  0x1        /* Mailbox 0 Receive Message Pending */
-#define                      RMP1  0x2        /* Mailbox 1 Receive Message Pending */
-#define                      RMP2  0x4        /* Mailbox 2 Receive Message Pending */
-#define                      RMP3  0x8        /* Mailbox 3 Receive Message Pending */
-#define                      RMP4  0x10       /* Mailbox 4 Receive Message Pending */
-#define                      RMP5  0x20       /* Mailbox 5 Receive Message Pending */
-#define                      RMP6  0x40       /* Mailbox 6 Receive Message Pending */
-#define                      RMP7  0x80       /* Mailbox 7 Receive Message Pending */
-#define                      RMP8  0x100      /* Mailbox 8 Receive Message Pending */
-#define                      RMP9  0x200      /* Mailbox 9 Receive Message Pending */
-#define                     RMP10  0x400      /* Mailbox 10 Receive Message Pending */
-#define                     RMP11  0x800      /* Mailbox 11 Receive Message Pending */
-#define                     RMP12  0x1000     /* Mailbox 12 Receive Message Pending */
-#define                     RMP13  0x2000     /* Mailbox 13 Receive Message Pending */
-#define                     RMP14  0x4000     /* Mailbox 14 Receive Message Pending */
-#define                     RMP15  0x8000     /* Mailbox 15 Receive Message Pending */
-
-/* Bit masks for CAN0_RMP2 */
-
-#define                     RMP16  0x1        /* Mailbox 16 Receive Message Pending */
-#define                     RMP17  0x2        /* Mailbox 17 Receive Message Pending */
-#define                     RMP18  0x4        /* Mailbox 18 Receive Message Pending */
-#define                     RMP19  0x8        /* Mailbox 19 Receive Message Pending */
-#define                     RMP20  0x10       /* Mailbox 20 Receive Message Pending */
-#define                     RMP21  0x20       /* Mailbox 21 Receive Message Pending */
-#define                     RMP22  0x40       /* Mailbox 22 Receive Message Pending */
-#define                     RMP23  0x80       /* Mailbox 23 Receive Message Pending */
-#define                     RMP24  0x100      /* Mailbox 24 Receive Message Pending */
-#define                     RMP25  0x200      /* Mailbox 25 Receive Message Pending */
-#define                     RMP26  0x400      /* Mailbox 26 Receive Message Pending */
-#define                     RMP27  0x800      /* Mailbox 27 Receive Message Pending */
-#define                     RMP28  0x1000     /* Mailbox 28 Receive Message Pending */
-#define                     RMP29  0x2000     /* Mailbox 29 Receive Message Pending */
-#define                     RMP30  0x4000     /* Mailbox 30 Receive Message Pending */
-#define                     RMP31  0x8000     /* Mailbox 31 Receive Message Pending */
-
-/* Bit masks for CAN0_RML1 */
-
-#define                      RML0  0x1        /* Mailbox 0 Receive Message Lost */
-#define                      RML1  0x2        /* Mailbox 1 Receive Message Lost */
-#define                      RML2  0x4        /* Mailbox 2 Receive Message Lost */
-#define                      RML3  0x8        /* Mailbox 3 Receive Message Lost */
-#define                      RML4  0x10       /* Mailbox 4 Receive Message Lost */
-#define                      RML5  0x20       /* Mailbox 5 Receive Message Lost */
-#define                      RML6  0x40       /* Mailbox 6 Receive Message Lost */
-#define                      RML7  0x80       /* Mailbox 7 Receive Message Lost */
-#define                      RML8  0x100      /* Mailbox 8 Receive Message Lost */
-#define                      RML9  0x200      /* Mailbox 9 Receive Message Lost */
-#define                     RML10  0x400      /* Mailbox 10 Receive Message Lost */
-#define                     RML11  0x800      /* Mailbox 11 Receive Message Lost */
-#define                     RML12  0x1000     /* Mailbox 12 Receive Message Lost */
-#define                     RML13  0x2000     /* Mailbox 13 Receive Message Lost */
-#define                     RML14  0x4000     /* Mailbox 14 Receive Message Lost */
-#define                     RML15  0x8000     /* Mailbox 15 Receive Message Lost */
-
-/* Bit masks for CAN0_RML2 */
-
-#define                     RML16  0x1        /* Mailbox 16 Receive Message Lost */
-#define                     RML17  0x2        /* Mailbox 17 Receive Message Lost */
-#define                     RML18  0x4        /* Mailbox 18 Receive Message Lost */
-#define                     RML19  0x8        /* Mailbox 19 Receive Message Lost */
-#define                     RML20  0x10       /* Mailbox 20 Receive Message Lost */
-#define                     RML21  0x20       /* Mailbox 21 Receive Message Lost */
-#define                     RML22  0x40       /* Mailbox 22 Receive Message Lost */
-#define                     RML23  0x80       /* Mailbox 23 Receive Message Lost */
-#define                     RML24  0x100      /* Mailbox 24 Receive Message Lost */
-#define                     RML25  0x200      /* Mailbox 25 Receive Message Lost */
-#define                     RML26  0x400      /* Mailbox 26 Receive Message Lost */
-#define                     RML27  0x800      /* Mailbox 27 Receive Message Lost */
-#define                     RML28  0x1000     /* Mailbox 28 Receive Message Lost */
-#define                     RML29  0x2000     /* Mailbox 29 Receive Message Lost */
-#define                     RML30  0x4000     /* Mailbox 30 Receive Message Lost */
-#define                     RML31  0x8000     /* Mailbox 31 Receive Message Lost */
-
-/* Bit masks for CAN0_OPSS1 */
-
-#define                     OPSS0  0x1        /* Mailbox 0 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS1  0x2        /* Mailbox 1 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS2  0x4        /* Mailbox 2 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS3  0x8        /* Mailbox 3 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS4  0x10       /* Mailbox 4 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS5  0x20       /* Mailbox 5 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS6  0x40       /* Mailbox 6 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS7  0x80       /* Mailbox 7 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS8  0x100      /* Mailbox 8 Overwrite Protection/Single-Shot Transmission Enable */
-#define                     OPSS9  0x200      /* Mailbox 9 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS10  0x400      /* Mailbox 10 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS11  0x800      /* Mailbox 11 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS12  0x1000     /* Mailbox 12 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS13  0x2000     /* Mailbox 13 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS14  0x4000     /* Mailbox 14 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS15  0x8000     /* Mailbox 15 Overwrite Protection/Single-Shot Transmission Enable */
-
-/* Bit masks for CAN0_OPSS2 */
-
-#define                    OPSS16  0x1        /* Mailbox 16 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS17  0x2        /* Mailbox 17 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS18  0x4        /* Mailbox 18 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS19  0x8        /* Mailbox 19 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS20  0x10       /* Mailbox 20 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS21  0x20       /* Mailbox 21 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS22  0x40       /* Mailbox 22 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS23  0x80       /* Mailbox 23 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS24  0x100      /* Mailbox 24 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS25  0x200      /* Mailbox 25 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS26  0x400      /* Mailbox 26 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS27  0x800      /* Mailbox 27 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS28  0x1000     /* Mailbox 28 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS29  0x2000     /* Mailbox 29 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS30  0x4000     /* Mailbox 30 Overwrite Protection/Single-Shot Transmission Enable */
-#define                    OPSS31  0x8000     /* Mailbox 31 Overwrite Protection/Single-Shot Transmission Enable */
-
-/* Bit masks for CAN0_TRS1 */
-
-#define                      TRS0  0x1        /* Mailbox 0 Transmit Request Set */
-#define                      TRS1  0x2        /* Mailbox 1 Transmit Request Set */
-#define                      TRS2  0x4        /* Mailbox 2 Transmit Request Set */
-#define                      TRS3  0x8        /* Mailbox 3 Transmit Request Set */
-#define                      TRS4  0x10       /* Mailbox 4 Transmit Request Set */
-#define                      TRS5  0x20       /* Mailbox 5 Transmit Request Set */
-#define                      TRS6  0x40       /* Mailbox 6 Transmit Request Set */
-#define                      TRS7  0x80       /* Mailbox 7 Transmit Request Set */
-#define                      TRS8  0x100      /* Mailbox 8 Transmit Request Set */
-#define                      TRS9  0x200      /* Mailbox 9 Transmit Request Set */
-#define                     TRS10  0x400      /* Mailbox 10 Transmit Request Set */
-#define                     TRS11  0x800      /* Mailbox 11 Transmit Request Set */
-#define                     TRS12  0x1000     /* Mailbox 12 Transmit Request Set */
-#define                     TRS13  0x2000     /* Mailbox 13 Transmit Request Set */
-#define                     TRS14  0x4000     /* Mailbox 14 Transmit Request Set */
-#define                     TRS15  0x8000     /* Mailbox 15 Transmit Request Set */
-
-/* Bit masks for CAN0_TRS2 */
-
-#define                     TRS16  0x1        /* Mailbox 16 Transmit Request Set */
-#define                     TRS17  0x2        /* Mailbox 17 Transmit Request Set */
-#define                     TRS18  0x4        /* Mailbox 18 Transmit Request Set */
-#define                     TRS19  0x8        /* Mailbox 19 Transmit Request Set */
-#define                     TRS20  0x10       /* Mailbox 20 Transmit Request Set */
-#define                     TRS21  0x20       /* Mailbox 21 Transmit Request Set */
-#define                     TRS22  0x40       /* Mailbox 22 Transmit Request Set */
-#define                     TRS23  0x80       /* Mailbox 23 Transmit Request Set */
-#define                     TRS24  0x100      /* Mailbox 24 Transmit Request Set */
-#define                     TRS25  0x200      /* Mailbox 25 Transmit Request Set */
-#define                     TRS26  0x400      /* Mailbox 26 Transmit Request Set */
-#define                     TRS27  0x800      /* Mailbox 27 Transmit Request Set */
-#define                     TRS28  0x1000     /* Mailbox 28 Transmit Request Set */
-#define                     TRS29  0x2000     /* Mailbox 29 Transmit Request Set */
-#define                     TRS30  0x4000     /* Mailbox 30 Transmit Request Set */
-#define                     TRS31  0x8000     /* Mailbox 31 Transmit Request Set */
-
-/* Bit masks for CAN0_TRR1 */
-
-#define                      TRR0  0x1        /* Mailbox 0 Transmit Request Reset */
-#define                      TRR1  0x2        /* Mailbox 1 Transmit Request Reset */
-#define                      TRR2  0x4        /* Mailbox 2 Transmit Request Reset */
-#define                      TRR3  0x8        /* Mailbox 3 Transmit Request Reset */
-#define                      TRR4  0x10       /* Mailbox 4 Transmit Request Reset */
-#define                      TRR5  0x20       /* Mailbox 5 Transmit Request Reset */
-#define                      TRR6  0x40       /* Mailbox 6 Transmit Request Reset */
-#define                      TRR7  0x80       /* Mailbox 7 Transmit Request Reset */
-#define                      TRR8  0x100      /* Mailbox 8 Transmit Request Reset */
-#define                      TRR9  0x200      /* Mailbox 9 Transmit Request Reset */
-#define                     TRR10  0x400      /* Mailbox 10 Transmit Request Reset */
-#define                     TRR11  0x800      /* Mailbox 11 Transmit Request Reset */
-#define                     TRR12  0x1000     /* Mailbox 12 Transmit Request Reset */
-#define                     TRR13  0x2000     /* Mailbox 13 Transmit Request Reset */
-#define                     TRR14  0x4000     /* Mailbox 14 Transmit Request Reset */
-#define                     TRR15  0x8000     /* Mailbox 15 Transmit Request Reset */
-
-/* Bit masks for CAN0_TRR2 */
-
-#define                     TRR16  0x1        /* Mailbox 16 Transmit Request Reset */
-#define                     TRR17  0x2        /* Mailbox 17 Transmit Request Reset */
-#define                     TRR18  0x4        /* Mailbox 18 Transmit Request Reset */
-#define                     TRR19  0x8        /* Mailbox 19 Transmit Request Reset */
-#define                     TRR20  0x10       /* Mailbox 20 Transmit Request Reset */
-#define                     TRR21  0x20       /* Mailbox 21 Transmit Request Reset */
-#define                     TRR22  0x40       /* Mailbox 22 Transmit Request Reset */
-#define                     TRR23  0x80       /* Mailbox 23 Transmit Request Reset */
-#define                     TRR24  0x100      /* Mailbox 24 Transmit Request Reset */
-#define                     TRR25  0x200      /* Mailbox 25 Transmit Request Reset */
-#define                     TRR26  0x400      /* Mailbox 26 Transmit Request Reset */
-#define                     TRR27  0x800      /* Mailbox 27 Transmit Request Reset */
-#define                     TRR28  0x1000     /* Mailbox 28 Transmit Request Reset */
-#define                     TRR29  0x2000     /* Mailbox 29 Transmit Request Reset */
-#define                     TRR30  0x4000     /* Mailbox 30 Transmit Request Reset */
-#define                     TRR31  0x8000     /* Mailbox 31 Transmit Request Reset */
-
-/* Bit masks for CAN0_AA1 */
-
-#define                       AA0  0x1        /* Mailbox 0 Abort Acknowledge */
-#define                       AA1  0x2        /* Mailbox 1 Abort Acknowledge */
-#define                       AA2  0x4        /* Mailbox 2 Abort Acknowledge */
-#define                       AA3  0x8        /* Mailbox 3 Abort Acknowledge */
-#define                       AA4  0x10       /* Mailbox 4 Abort Acknowledge */
-#define                       AA5  0x20       /* Mailbox 5 Abort Acknowledge */
-#define                       AA6  0x40       /* Mailbox 6 Abort Acknowledge */
-#define                       AA7  0x80       /* Mailbox 7 Abort Acknowledge */
-#define                       AA8  0x100      /* Mailbox 8 Abort Acknowledge */
-#define                       AA9  0x200      /* Mailbox 9 Abort Acknowledge */
-#define                      AA10  0x400      /* Mailbox 10 Abort Acknowledge */
-#define                      AA11  0x800      /* Mailbox 11 Abort Acknowledge */
-#define                      AA12  0x1000     /* Mailbox 12 Abort Acknowledge */
-#define                      AA13  0x2000     /* Mailbox 13 Abort Acknowledge */
-#define                      AA14  0x4000     /* Mailbox 14 Abort Acknowledge */
-#define                      AA15  0x8000     /* Mailbox 15 Abort Acknowledge */
-
-/* Bit masks for CAN0_AA2 */
-
-#define                      AA16  0x1        /* Mailbox 16 Abort Acknowledge */
-#define                      AA17  0x2        /* Mailbox 17 Abort Acknowledge */
-#define                      AA18  0x4        /* Mailbox 18 Abort Acknowledge */
-#define                      AA19  0x8        /* Mailbox 19 Abort Acknowledge */
-#define                      AA20  0x10       /* Mailbox 20 Abort Acknowledge */
-#define                      AA21  0x20       /* Mailbox 21 Abort Acknowledge */
-#define                      AA22  0x40       /* Mailbox 22 Abort Acknowledge */
-#define                      AA23  0x80       /* Mailbox 23 Abort Acknowledge */
-#define                      AA24  0x100      /* Mailbox 24 Abort Acknowledge */
-#define                      AA25  0x200      /* Mailbox 25 Abort Acknowledge */
-#define                      AA26  0x400      /* Mailbox 26 Abort Acknowledge */
-#define                      AA27  0x800      /* Mailbox 27 Abort Acknowledge */
-#define                      AA28  0x1000     /* Mailbox 28 Abort Acknowledge */
-#define                      AA29  0x2000     /* Mailbox 29 Abort Acknowledge */
-#define                      AA30  0x4000     /* Mailbox 30 Abort Acknowledge */
-#define                      AA31  0x8000     /* Mailbox 31 Abort Acknowledge */
-
-/* Bit masks for CAN0_TA1 */
-
-#define                       TA0  0x1        /* Mailbox 0 Transmit Acknowledge */
-#define                       TA1  0x2        /* Mailbox 1 Transmit Acknowledge */
-#define                       TA2  0x4        /* Mailbox 2 Transmit Acknowledge */
-#define                       TA3  0x8        /* Mailbox 3 Transmit Acknowledge */
-#define                       TA4  0x10       /* Mailbox 4 Transmit Acknowledge */
-#define                       TA5  0x20       /* Mailbox 5 Transmit Acknowledge */
-#define                       TA6  0x40       /* Mailbox 6 Transmit Acknowledge */
-#define                       TA7  0x80       /* Mailbox 7 Transmit Acknowledge */
-#define                       TA8  0x100      /* Mailbox 8 Transmit Acknowledge */
-#define                       TA9  0x200      /* Mailbox 9 Transmit Acknowledge */
-#define                      TA10  0x400      /* Mailbox 10 Transmit Acknowledge */
-#define                      TA11  0x800      /* Mailbox 11 Transmit Acknowledge */
-#define                      TA12  0x1000     /* Mailbox 12 Transmit Acknowledge */
-#define                      TA13  0x2000     /* Mailbox 13 Transmit Acknowledge */
-#define                      TA14  0x4000     /* Mailbox 14 Transmit Acknowledge */
-#define                      TA15  0x8000     /* Mailbox 15 Transmit Acknowledge */
-
-/* Bit masks for CAN0_TA2 */
-
-#define                      TA16  0x1        /* Mailbox 16 Transmit Acknowledge */
-#define                      TA17  0x2        /* Mailbox 17 Transmit Acknowledge */
-#define                      TA18  0x4        /* Mailbox 18 Transmit Acknowledge */
-#define                      TA19  0x8        /* Mailbox 19 Transmit Acknowledge */
-#define                      TA20  0x10       /* Mailbox 20 Transmit Acknowledge */
-#define                      TA21  0x20       /* Mailbox 21 Transmit Acknowledge */
-#define                      TA22  0x40       /* Mailbox 22 Transmit Acknowledge */
-#define                      TA23  0x80       /* Mailbox 23 Transmit Acknowledge */
-#define                      TA24  0x100      /* Mailbox 24 Transmit Acknowledge */
-#define                      TA25  0x200      /* Mailbox 25 Transmit Acknowledge */
-#define                      TA26  0x400      /* Mailbox 26 Transmit Acknowledge */
-#define                      TA27  0x800      /* Mailbox 27 Transmit Acknowledge */
-#define                      TA28  0x1000     /* Mailbox 28 Transmit Acknowledge */
-#define                      TA29  0x2000     /* Mailbox 29 Transmit Acknowledge */
-#define                      TA30  0x4000     /* Mailbox 30 Transmit Acknowledge */
-#define                      TA31  0x8000     /* Mailbox 31 Transmit Acknowledge */
-
-/* Bit masks for CAN0_RFH1 */
-
-#define                      RFH0  0x1        /* Mailbox 0 Remote Frame Handling Enable */
-#define                      RFH1  0x2        /* Mailbox 1 Remote Frame Handling Enable */
-#define                      RFH2  0x4        /* Mailbox 2 Remote Frame Handling Enable */
-#define                      RFH3  0x8        /* Mailbox 3 Remote Frame Handling Enable */
-#define                      RFH4  0x10       /* Mailbox 4 Remote Frame Handling Enable */
-#define                      RFH5  0x20       /* Mailbox 5 Remote Frame Handling Enable */
-#define                      RFH6  0x40       /* Mailbox 6 Remote Frame Handling Enable */
-#define                      RFH7  0x80       /* Mailbox 7 Remote Frame Handling Enable */
-#define                      RFH8  0x100      /* Mailbox 8 Remote Frame Handling Enable */
-#define                      RFH9  0x200      /* Mailbox 9 Remote Frame Handling Enable */
-#define                     RFH10  0x400      /* Mailbox 10 Remote Frame Handling Enable */
-#define                     RFH11  0x800      /* Mailbox 11 Remote Frame Handling Enable */
-#define                     RFH12  0x1000     /* Mailbox 12 Remote Frame Handling Enable */
-#define                     RFH13  0x2000     /* Mailbox 13 Remote Frame Handling Enable */
-#define                     RFH14  0x4000     /* Mailbox 14 Remote Frame Handling Enable */
-#define                     RFH15  0x8000     /* Mailbox 15 Remote Frame Handling Enable */
-
-/* Bit masks for CAN0_RFH2 */
-
-#define                     RFH16  0x1        /* Mailbox 16 Remote Frame Handling Enable */
-#define                     RFH17  0x2        /* Mailbox 17 Remote Frame Handling Enable */
-#define                     RFH18  0x4        /* Mailbox 18 Remote Frame Handling Enable */
-#define                     RFH19  0x8        /* Mailbox 19 Remote Frame Handling Enable */
-#define                     RFH20  0x10       /* Mailbox 20 Remote Frame Handling Enable */
-#define                     RFH21  0x20       /* Mailbox 21 Remote Frame Handling Enable */
-#define                     RFH22  0x40       /* Mailbox 22 Remote Frame Handling Enable */
-#define                     RFH23  0x80       /* Mailbox 23 Remote Frame Handling Enable */
-#define                     RFH24  0x100      /* Mailbox 24 Remote Frame Handling Enable */
-#define                     RFH25  0x200      /* Mailbox 25 Remote Frame Handling Enable */
-#define                     RFH26  0x400      /* Mailbox 26 Remote Frame Handling Enable */
-#define                     RFH27  0x800      /* Mailbox 27 Remote Frame Handling Enable */
-#define                     RFH28  0x1000     /* Mailbox 28 Remote Frame Handling Enable */
-#define                     RFH29  0x2000     /* Mailbox 29 Remote Frame Handling Enable */
-#define                     RFH30  0x4000     /* Mailbox 30 Remote Frame Handling Enable */
-#define                     RFH31  0x8000     /* Mailbox 31 Remote Frame Handling Enable */
-
-/* Bit masks for CAN0_MBIM1 */
-
-#define                     MBIM0  0x1        /* Mailbox 0 Mailbox Interrupt Mask */
-#define                     MBIM1  0x2        /* Mailbox 1 Mailbox Interrupt Mask */
-#define                     MBIM2  0x4        /* Mailbox 2 Mailbox Interrupt Mask */
-#define                     MBIM3  0x8        /* Mailbox 3 Mailbox Interrupt Mask */
-#define                     MBIM4  0x10       /* Mailbox 4 Mailbox Interrupt Mask */
-#define                     MBIM5  0x20       /* Mailbox 5 Mailbox Interrupt Mask */
-#define                     MBIM6  0x40       /* Mailbox 6 Mailbox Interrupt Mask */
-#define                     MBIM7  0x80       /* Mailbox 7 Mailbox Interrupt Mask */
-#define                     MBIM8  0x100      /* Mailbox 8 Mailbox Interrupt Mask */
-#define                     MBIM9  0x200      /* Mailbox 9 Mailbox Interrupt Mask */
-#define                    MBIM10  0x400      /* Mailbox 10 Mailbox Interrupt Mask */
-#define                    MBIM11  0x800      /* Mailbox 11 Mailbox Interrupt Mask */
-#define                    MBIM12  0x1000     /* Mailbox 12 Mailbox Interrupt Mask */
-#define                    MBIM13  0x2000     /* Mailbox 13 Mailbox Interrupt Mask */
-#define                    MBIM14  0x4000     /* Mailbox 14 Mailbox Interrupt Mask */
-#define                    MBIM15  0x8000     /* Mailbox 15 Mailbox Interrupt Mask */
-
-/* Bit masks for CAN0_MBIM2 */
-
-#define                    MBIM16  0x1        /* Mailbox 16 Mailbox Interrupt Mask */
-#define                    MBIM17  0x2        /* Mailbox 17 Mailbox Interrupt Mask */
-#define                    MBIM18  0x4        /* Mailbox 18 Mailbox Interrupt Mask */
-#define                    MBIM19  0x8        /* Mailbox 19 Mailbox Interrupt Mask */
-#define                    MBIM20  0x10       /* Mailbox 20 Mailbox Interrupt Mask */
-#define                    MBIM21  0x20       /* Mailbox 21 Mailbox Interrupt Mask */
-#define                    MBIM22  0x40       /* Mailbox 22 Mailbox Interrupt Mask */
-#define                    MBIM23  0x80       /* Mailbox 23 Mailbox Interrupt Mask */
-#define                    MBIM24  0x100      /* Mailbox 24 Mailbox Interrupt Mask */
-#define                    MBIM25  0x200      /* Mailbox 25 Mailbox Interrupt Mask */
-#define                    MBIM26  0x400      /* Mailbox 26 Mailbox Interrupt Mask */
-#define                    MBIM27  0x800      /* Mailbox 27 Mailbox Interrupt Mask */
-#define                    MBIM28  0x1000     /* Mailbox 28 Mailbox Interrupt Mask */
-#define                    MBIM29  0x2000     /* Mailbox 29 Mailbox Interrupt Mask */
-#define                    MBIM30  0x4000     /* Mailbox 30 Mailbox Interrupt Mask */
-#define                    MBIM31  0x8000     /* Mailbox 31 Mailbox Interrupt Mask */
-
-/* Bit masks for CAN0_MBTIF1 */
-
-#define                    MBTIF0  0x1        /* Mailbox 0 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF1  0x2        /* Mailbox 1 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF2  0x4        /* Mailbox 2 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF3  0x8        /* Mailbox 3 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF4  0x10       /* Mailbox 4 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF5  0x20       /* Mailbox 5 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF6  0x40       /* Mailbox 6 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF7  0x80       /* Mailbox 7 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF8  0x100      /* Mailbox 8 Mailbox Transmit Interrupt Flag */
-#define                    MBTIF9  0x200      /* Mailbox 9 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF10  0x400      /* Mailbox 10 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF11  0x800      /* Mailbox 11 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF12  0x1000     /* Mailbox 12 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF13  0x2000     /* Mailbox 13 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF14  0x4000     /* Mailbox 14 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF15  0x8000     /* Mailbox 15 Mailbox Transmit Interrupt Flag */
-
-/* Bit masks for CAN0_MBTIF2 */
-
-#define                   MBTIF16  0x1        /* Mailbox 16 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF17  0x2        /* Mailbox 17 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF18  0x4        /* Mailbox 18 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF19  0x8        /* Mailbox 19 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF20  0x10       /* Mailbox 20 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF21  0x20       /* Mailbox 21 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF22  0x40       /* Mailbox 22 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF23  0x80       /* Mailbox 23 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF24  0x100      /* Mailbox 24 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF25  0x200      /* Mailbox 25 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF26  0x400      /* Mailbox 26 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF27  0x800      /* Mailbox 27 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF28  0x1000     /* Mailbox 28 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF29  0x2000     /* Mailbox 29 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF30  0x4000     /* Mailbox 30 Mailbox Transmit Interrupt Flag */
-#define                   MBTIF31  0x8000     /* Mailbox 31 Mailbox Transmit Interrupt Flag */
-
-/* Bit masks for CAN0_MBRIF1 */
-
-#define                    MBRIF0  0x1        /* Mailbox 0 Mailbox Receive Interrupt Flag */
-#define                    MBRIF1  0x2        /* Mailbox 1 Mailbox Receive Interrupt Flag */
-#define                    MBRIF2  0x4        /* Mailbox 2 Mailbox Receive Interrupt Flag */
-#define                    MBRIF3  0x8        /* Mailbox 3 Mailbox Receive Interrupt Flag */
-#define                    MBRIF4  0x10       /* Mailbox 4 Mailbox Receive Interrupt Flag */
-#define                    MBRIF5  0x20       /* Mailbox 5 Mailbox Receive Interrupt Flag */
-#define                    MBRIF6  0x40       /* Mailbox 6 Mailbox Receive Interrupt Flag */
-#define                    MBRIF7  0x80       /* Mailbox 7 Mailbox Receive Interrupt Flag */
-#define                    MBRIF8  0x100      /* Mailbox 8 Mailbox Receive Interrupt Flag */
-#define                    MBRIF9  0x200      /* Mailbox 9 Mailbox Receive Interrupt Flag */
-#define                   MBRIF10  0x400      /* Mailbox 10 Mailbox Receive Interrupt Flag */
-#define                   MBRIF11  0x800      /* Mailbox 11 Mailbox Receive Interrupt Flag */
-#define                   MBRIF12  0x1000     /* Mailbox 12 Mailbox Receive Interrupt Flag */
-#define                   MBRIF13  0x2000     /* Mailbox 13 Mailbox Receive Interrupt Flag */
-#define                   MBRIF14  0x4000     /* Mailbox 14 Mailbox Receive Interrupt Flag */
-#define                   MBRIF15  0x8000     /* Mailbox 15 Mailbox Receive Interrupt Flag */
-
-/* Bit masks for CAN0_MBRIF2 */
-
-#define                   MBRIF16  0x1        /* Mailbox 16 Mailbox Receive Interrupt Flag */
-#define                   MBRIF17  0x2        /* Mailbox 17 Mailbox Receive Interrupt Flag */
-#define                   MBRIF18  0x4        /* Mailbox 18 Mailbox Receive Interrupt Flag */
-#define                   MBRIF19  0x8        /* Mailbox 19 Mailbox Receive Interrupt Flag */
-#define                   MBRIF20  0x10       /* Mailbox 20 Mailbox Receive Interrupt Flag */
-#define                   MBRIF21  0x20       /* Mailbox 21 Mailbox Receive Interrupt Flag */
-#define                   MBRIF22  0x40       /* Mailbox 22 Mailbox Receive Interrupt Flag */
-#define                   MBRIF23  0x80       /* Mailbox 23 Mailbox Receive Interrupt Flag */
-#define                   MBRIF24  0x100      /* Mailbox 24 Mailbox Receive Interrupt Flag */
-#define                   MBRIF25  0x200      /* Mailbox 25 Mailbox Receive Interrupt Flag */
-#define                   MBRIF26  0x400      /* Mailbox 26 Mailbox Receive Interrupt Flag */
-#define                   MBRIF27  0x800      /* Mailbox 27 Mailbox Receive Interrupt Flag */
-#define                   MBRIF28  0x1000     /* Mailbox 28 Mailbox Receive Interrupt Flag */
-#define                   MBRIF29  0x2000     /* Mailbox 29 Mailbox Receive Interrupt Flag */
-#define                   MBRIF30  0x4000     /* Mailbox 30 Mailbox Receive Interrupt Flag */
-#define                   MBRIF31  0x8000     /* Mailbox 31 Mailbox Receive Interrupt Flag */
-
-/* Bit masks for EPPIx_STATUS */
-
-#define                 CFIFO_ERR  0x1        /* Chroma FIFO Error */
-#define                 YFIFO_ERR  0x2        /* Luma FIFO Error */
-#define                 LTERR_OVR  0x4        /* Line Track Overflow */
-#define                LTERR_UNDR  0x8        /* Line Track Underflow */
-#define                 FTERR_OVR  0x10       /* Frame Track Overflow */
-#define                FTERR_UNDR  0x20       /* Frame Track Underflow */
-#define                  ERR_NCOR  0x40       /* Preamble Error Not Corrected */
-#define                   DMA1URQ  0x80       /* DMA1 Urgent Request */
-#define                   DMA0URQ  0x100      /* DMA0 Urgent Request */
-#define                   ERR_DET  0x4000     /* Preamble Error Detected */
-#define                       FLD  0x8000     /* Field */
-
-/* Bit masks for EPPIx_CONTROL */
-
-#define                   EPPI_EN  0x1        /* Enable */
-#define                  EPPI_DIR  0x2        /* Direction */
-#define                  XFR_TYPE  0xc        /* Operating Mode */
-#define                    FS_CFG  0x30       /* Frame Sync Configuration */
-#define                   FLD_SEL  0x40       /* Field Select/Trigger */
-#define                  ITU_TYPE  0x80       /* ITU Interlaced or Progressive */
-#define                  BLANKGEN  0x100      /* ITU Output Mode with Internal Blanking Generation */
-#define                   ICLKGEN  0x200      /* Internal Clock Generation */
-#define                    IFSGEN  0x400      /* Internal Frame Sync Generation */
-#define                      POLC  0x1800     /* Frame Sync and Data Driving/Sampling Edges */
-#define                      POLS  0x6000     /* Frame Sync Polarity */
-#define                   DLENGTH  0x38000    /* Data Length */
-#define                   SKIP_EN  0x40000    /* Skip Enable */
-#define                   SKIP_EO  0x80000    /* Skip Even or Odd */
-#define                    PACKEN  0x100000   /* Packing/Unpacking Enable */
-#define                    SWAPEN  0x200000   /* Swap Enable */
-#define                  SIGN_EXT  0x400000   /* Sign Extension or Zero-filled / Data Split Format */
-#define             SPLT_EVEN_ODD  0x800000   /* Split Even and Odd Data Samples */
-#define               SUBSPLT_ODD  0x1000000  /* Sub-split Odd Samples */
-#define                    DMACFG  0x2000000  /* One or Two DMA Channels Mode */
-#define                RGB_FMT_EN  0x4000000  /* RGB Formatting Enable */
-#define                  FIFO_RWM  0x18000000 /* FIFO Regular Watermarks */
-#define                  FIFO_UWM  0x60000000 /* FIFO Urgent Watermarks */
-
-#define DLEN_8          (0 << 15) /* 000 - 8 bits */
-#define DLEN_10         (1 << 15) /* 001 - 10 bits */
-#define DLEN_12         (2 << 15) /* 010 - 12 bits */
-#define DLEN_14         (3 << 15) /* 011 - 14 bits */
-#define DLEN_16         (4 << 15) /* 100 - 16 bits */
-#define DLEN_18         (5 << 15) /* 101 - 18 bits */
-#define DLEN_24         (6 << 15) /* 110 - 24 bits */
-
-
-/* Bit masks for EPPIx_FS2W_LVB */
-
-#define                   F1VB_BD  0xff       /* Vertical Blanking before Field 1 Active Data */
-#define                   F1VB_AD  0xff00     /* Vertical Blanking after Field 1 Active Data */
-#define                   F2VB_BD  0xff0000   /* Vertical Blanking before Field 2 Active Data */
-#define                   F2VB_AD  0xff000000 /* Vertical Blanking after Field 2 Active Data */
-
-/* Bit masks for EPPIx_FS2W_LAVF */
-
-#define                    F1_ACT  0xffff     /* Number of Lines of Active Data in Field 1 */
-#define                    F2_ACT  0xffff0000 /* Number of Lines of Active Data in Field 2 */
-
-/* Bit masks for EPPIx_CLIP */
-
-#define                   LOW_ODD  0xff       /* Lower Limit for Odd Bytes (Chroma) */
-#define                  HIGH_ODD  0xff00     /* Upper Limit for Odd Bytes (Chroma) */
-#define                  LOW_EVEN  0xff0000   /* Lower Limit for Even Bytes (Luma) */
-#define                 HIGH_EVEN  0xff000000 /* Upper Limit for Even Bytes (Luma) */
-
-/* Bit masks for SPIx_BAUD */
-
-#define                  SPI_BAUD  0xffff     /* Baud Rate */
-
-/* Bit masks for SPIx_CTL */
-
-#define                       SPE  0x4000     /* SPI Enable */
-#define                       WOM  0x2000     /* Write Open Drain Master */
-#define                      MSTR  0x1000     /* Master Mode */
-#define                      CPOL  0x800      /* Clock Polarity */
-#define                      CPHA  0x400      /* Clock Phase */
-#define                      LSBF  0x200      /* LSB First */
-#define                      SIZE  0x100      /* Size of Words */
-#define                     EMISO  0x20       /* Enable MISO Output */
-#define                      PSSE  0x10       /* Slave-Select Enable */
-#define                        GM  0x8        /* Get More Data */
-#define                        SZ  0x4        /* Send Zero */
-#define                     TIMOD  0x3        /* Transfer Initiation Mode */
-
-/* Bit masks for SPIx_FLG */
-
-#define                      FLS1  0x2        /* Slave Select Enable 1 */
-#define                      FLS2  0x4        /* Slave Select Enable 2 */
-#define                      FLS3  0x8        /* Slave Select Enable 3 */
-#define                      FLG1  0x200      /* Slave Select Value 1 */
-#define                      FLG2  0x400      /* Slave Select Value 2 */
-#define                      FLG3  0x800      /* Slave Select Value 3 */
-
-/* Bit masks for SPIx_STAT */
-
-#define                     TXCOL  0x40       /* Transmit Collision Error */
-#define                       RXS  0x20       /* RDBR Data Buffer Status */
-#define                      RBSY  0x10       /* Receive Error */
-#define                       TXS  0x8        /* TDBR Data Buffer Status */
-#define                       TXE  0x4        /* Transmission Error */
-#define                      MODF  0x2        /* Mode Fault Error */
-#define                      SPIF  0x1        /* SPI Finished */
-
-/* Bit masks for SPIx_TDBR */
-
-#define                      TDBR  0xffff     /* Transmit Data Buffer */
-
-/* Bit masks for SPIx_RDBR */
-
-#define                      RDBR  0xffff     /* Receive Data Buffer */
-
-/* Bit masks for SPIx_SHADOW */
-
-#define                    SHADOW  0xffff     /* RDBR Shadow */
-
-/* ************************************************ */
-/* The TWI bit masks fields are from the ADSP-BF538 */
-/* and they have not been verified as the final     */
-/* ones for the Moab processors ... bz 1/19/2007    */
-/* ************************************************ */
-
-/* Bit masks for TWIx_CONTROL */
-
-#define                  PRESCALE  0x7f       /* Prescale Value */
-#define                   TWI_ENA  0x80       /* TWI Enable */
-#define                      SCCB  0x200      /* Serial Camera Control Bus */
-
-/* Bit maskes for TWIx_CLKDIV */
-
-#define                    CLKLOW  0xff       /* Clock Low */
-#define                     CLKHI  0xff00     /* Clock High */
-
-/* Bit maskes for TWIx_SLAVE_CTL */
-
-#define                       SEN  0x1        /* Slave Enable */
-#define                    STDVAL  0x4        /* Slave Transmit Data Valid */
-#define                       NAK  0x8        /* Not Acknowledge */
-#define                       GEN  0x10       /* General Call Enable */
-
-/* Bit maskes for TWIx_SLAVE_ADDR */
-
-#define                     SADDR  0x7f       /* Slave Mode Address */
-
-/* Bit maskes for TWIx_SLAVE_STAT */
-
-#define                      SDIR  0x1        /* Slave Transfer Direction */
-#define                     GCALL  0x2        /* General Call */
-
-/* Bit maskes for TWIx_MASTER_CTL */
-
-#define                       MEN  0x1        /* Master Mode Enable */
-#define                      MDIR  0x4        /* Master Transfer Direction */
-#define                      FAST  0x8        /* Fast Mode */
-#define                      STOP  0x10       /* Issue Stop Condition */
-#define                    RSTART  0x20       /* Repeat Start */
-#define                      DCNT  0x3fc0     /* Data Transfer Count */
-#define                    SDAOVR  0x4000     /* Serial Data Override */
-#define                    SCLOVR  0x8000     /* Serial Clock Override */
-
-/* Bit maskes for TWIx_MASTER_ADDR */
-
-#define                     MADDR  0x7f       /* Master Mode Address */
-
-/* Bit maskes for TWIx_MASTER_STAT */
-
-#define                     MPROG  0x1        /* Master Transfer in Progress */
-#define                   LOSTARB  0x2        /* Lost Arbitration */
-#define                      ANAK  0x4        /* Address Not Acknowledged */
-#define                      DNAK  0x8        /* Data Not Acknowledged */
-#define                  BUFRDERR  0x10       /* Buffer Read Error */
-#define                  BUFWRERR  0x20       /* Buffer Write Error */
-#define                    SDASEN  0x40       /* Serial Data Sense */
-#define                    SCLSEN  0x80       /* Serial Clock Sense */
-#define                   BUSBUSY  0x100      /* Bus Busy */
-
-/* Bit maskes for TWIx_FIFO_CTL */
-
-#define                  XMTFLUSH  0x1        /* Transmit Buffer Flush */
-#define                  RCVFLUSH  0x2        /* Receive Buffer Flush */
-#define                 XMTINTLEN  0x4        /* Transmit Buffer Interrupt Length */
-#define                 RCVINTLEN  0x8        /* Receive Buffer Interrupt Length */
-
-/* Bit maskes for TWIx_FIFO_STAT */
-
-#define                   XMTSTAT  0x3        /* Transmit FIFO Status */
-#define                   RCVSTAT  0xc        /* Receive FIFO Status */
-
-/* Bit maskes for TWIx_INT_MASK */
-
-#define                    SINITM  0x1        /* Slave Transfer Initiated Interrupt Mask */
-#define                    SCOMPM  0x2        /* Slave Transfer Complete Interrupt Mask */
-#define                     SERRM  0x4        /* Slave Transfer Error Interrupt Mask */
-#define                     SOVFM  0x8        /* Slave Overflow Interrupt Mask */
-#define                    MCOMPM  0x10       /* Master Transfer Complete Interrupt Mask */
-#define                     MERRM  0x20       /* Master Transfer Error Interrupt Mask */
-#define                  XMTSERVM  0x40       /* Transmit FIFO Service Interrupt Mask */
-#define                  RCVSERVM  0x80       /* Receive FIFO Service Interrupt Mask */
-
-/* Bit maskes for TWIx_INT_STAT */
-
-#define                     SINIT  0x1        /* Slave Transfer Initiated */
-#define                     SCOMP  0x2        /* Slave Transfer Complete */
-#define                      SERR  0x4        /* Slave Transfer Error */
-#define                      SOVF  0x8        /* Slave Overflow */
-#define                     MCOMP  0x10       /* Master Transfer Complete */
-#define                      MERR  0x20       /* Master Transfer Error */
-#define                   XMTSERV  0x40       /* Transmit FIFO Service */
-#define                   RCVSERV  0x80       /* Receive FIFO Service */
-
-/* Bit maskes for TWIx_XMT_DATA8 */
-
-#define                  XMTDATA8  0xff       /* Transmit FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_XMT_DATA16 */
-
-#define                 XMTDATA16  0xffff     /* Transmit FIFO 16-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA8 */
-
-#define                  RCVDATA8  0xff       /* Receive FIFO 8-Bit Data */
-
-/* Bit maskes for TWIx_RCV_DATA16 */
-
-#define                 RCVDATA16  0xffff     /* Receive FIFO 16-Bit Data */
-
-/* Bit masks for SPORTx_TCR1 */
-
-#define                     TCKFE  0x4000     /* Clock Falling Edge Select */
-#define                     LATFS  0x2000     /* Late Transmit Frame Sync */
-#define                      LTFS  0x1000     /* Low Transmit Frame Sync Select */
-#define                     DITFS  0x800      /* Data-Independent Transmit Frame Sync Select */
-#define                      TFSR  0x400      /* Transmit Frame Sync Required Select */
-#define                      ITFS  0x200      /* Internal Transmit Frame Sync Select */
-#define                    TLSBIT  0x10       /* Transmit Bit Order */
-#define                    TDTYPE  0xc        /* Data Formatting Type Select */
-#define                     ITCLK  0x2        /* Internal Transmit Clock Select */
-#define                     TSPEN  0x1        /* Transmit Enable */
-
-/* Bit masks for SPORTx_TCR2 */
-
-#define                     TRFST  0x400      /* Left/Right Order */
-#define                     TSFSE  0x200      /* Transmit Stereo Frame Sync Enable */
-#define                      TXSE  0x100      /* TxSEC Enable */
-#define                    SLEN_T  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_RCR1 */
-
-#define                     RCKFE  0x4000     /* Clock Falling Edge Select */
-#define                     LARFS  0x2000     /* Late Receive Frame Sync */
-#define                      LRFS  0x1000     /* Low Receive Frame Sync Select */
-#define                      RFSR  0x400      /* Receive Frame Sync Required Select */
-#define                      IRFS  0x200      /* Internal Receive Frame Sync Select */
-#define                    RLSBIT  0x10       /* Receive Bit Order */
-#define                    RDTYPE  0xc        /* Data Formatting Type Select */
-#define                     IRCLK  0x2        /* Internal Receive Clock Select */
-#define                     RSPEN  0x1        /* Receive Enable */
-
-/* Bit masks for SPORTx_RCR2 */
-
-#define                     RRFST  0x400      /* Left/Right Order */
-#define                     RSFSE  0x200      /* Receive Stereo Frame Sync Enable */
-#define                      RXSE  0x100      /* RxSEC Enable */
-#define                    SLEN_R  0x1f       /* SPORT Word Length */
-
-/* Bit masks for SPORTx_STAT */
-
-#define                     TXHRE  0x40       /* Transmit Hold Register Empty */
-#define                      TOVF  0x20       /* Sticky Transmit Overflow Status */
-#define                      TUVF  0x10       /* Sticky Transmit Underflow Status */
-#define                       TXF  0x8        /* Transmit FIFO Full Status */
-#define                      ROVF  0x4        /* Sticky Receive Overflow Status */
-#define                      RUVF  0x2        /* Sticky Receive Underflow Status */
-#define                      RXNE  0x1        /* Receive FIFO Not Empty Status */
-
-/* Bit masks for SPORTx_MCMC1 */
-
-#define                  SP_WSIZE  0xf000     /* Window Size */
-#define                   SP_WOFF  0x3ff      /* Windows Offset */
-
-/* Bit masks for SPORTx_MCMC2 */
-
-#define                       MFD  0xf000     /* Multi channel Frame Delay */
-#define                      FSDR  0x80       /* Frame Sync to Data Relationship */
-#define                  MCMEN  0x10       /* Multi channel Frame Mode Enable */
-#define                   MCDRXPE  0x8        /* Multi channel DMA Receive Packing */
-#define                   MCDTXPE  0x4        /* Multi channel DMA Transmit Packing */
-#define                     MCCRM  0x3        /* 2X Clock Recovery Mode */
-
-/* Bit masks for SPORTx_CHNL */
-
-#define                  CUR_CHNL  0x3ff      /* Current Channel Indicator */
-
-/* Bit masks for UARTx_LCR */
-
-#if 0
-/* conflicts with legacy one in last section */
-#define                       WLS  0x3        /* Word Length Select */
-#endif
-#define                       STB  0x4        /* Stop Bits */
-#define                       PEN  0x8        /* Parity Enable */
-#define                       EPS  0x10       /* Even Parity Select */
-#define                       STP  0x20       /* Sticky Parity */
-#define                        SB  0x40       /* Set Break */
-
-/* Bit masks for UARTx_MCR */
-
-#define                      XOFF  0x1        /* Transmitter Off */
-#define                      MRTS  0x2        /* Manual Request To Send */
-#define                      RFIT  0x4        /* Receive FIFO IRQ Threshold */
-#define                      RFRT  0x8        /* Receive FIFO RTS Threshold */
-#define                  LOOP_ENA  0x10       /* Loopback Mode Enable */
-#define                     FCPOL  0x20       /* Flow Control Pin Polarity */
-#define                      ARTS  0x40       /* Automatic Request To Send */
-#define                      ACTS  0x80       /* Automatic Clear To Send */
-
-/* Bit masks for UARTx_LSR */
-
-#define                        DR  0x1        /* Data Ready */
-#define                        OE  0x2        /* Overrun Error */
-#define                        PE  0x4        /* Parity Error */
-#define                        FE  0x8        /* Framing Error */
-#define                        BI  0x10       /* Break Interrupt */
-#define                      THRE  0x20       /* THR Empty */
-#define                      TEMT  0x40       /* Transmitter Empty */
-#define                       TFI  0x80       /* Transmission Finished Indicator */
-
-/* Bit masks for UARTx_MSR */
-
-#define                      SCTS  0x1        /* Sticky CTS */
-#define                       CTS  0x10       /* Clear To Send */
-#define                      RFCS  0x20       /* Receive FIFO Count Status */
-
-/* Bit masks for UARTx_IER_SET & UARTx_IER_CLEAR */
-
-#define                   ERBFI  0x1        /* Enable Receive Buffer Full Interrupt */
-#define                   ETBEI  0x2        /* Enable Transmit Buffer Empty Interrupt */
-#define                    ELSI  0x4        /* Enable Receive Status Interrupt */
-#define                   EDSSI  0x8        /* Enable Modem Status Interrupt */
-#define                  EDTPTI  0x10       /* Enable DMA Transmit PIRQ Interrupt */
-#define                    ETFI  0x20       /* Enable Transmission Finished Interrupt */
-#define                   ERFCI  0x40       /* Enable Receive FIFO Count Interrupt */
-
-/* Bit masks for UARTx_GCTL */
-
-#define                      UCEN  0x1        /* UART Enable */
-#define                      IREN  0x2        /* IrDA Mode Enable */
-#define                     TPOLC  0x4        /* IrDA TX Polarity Change */
-#define                     RPOLC  0x8        /* IrDA RX Polarity Change */
-#define                       FPE  0x10       /* Force Parity Error */
-#define                       FFE  0x20       /* Force Framing Error */
-#define                      EDBO  0x40       /* Enable Divide-by-One */
-#define                     EGLSI  0x80       /* Enable Global LS Interrupt */
-
-
-/* ******************************************* */
-/*     MULTI BIT MACRO ENUMERATIONS            */
-/* ******************************************* */
-
-/* BCODE bit field options (SYSCFG register) */
-
-#define BCODE_WAKEUP    0x0000  /* boot according to wake-up condition */
-#define BCODE_FULLBOOT  0x0010  /* always perform full boot */
-#define BCODE_QUICKBOOT 0x0020  /* always perform quick boot */
-#define BCODE_NOBOOT    0x0030  /* always perform full boot */
-
-/* CNT_COMMAND bit field options */
-
-#define W1LCNT_ZERO   0x0001   /* write 1 to load CNT_COUNTER with zero */
-#define W1LCNT_MIN    0x0004   /* write 1 to load CNT_COUNTER from CNT_MIN */
-#define W1LCNT_MAX    0x0008   /* write 1 to load CNT_COUNTER from CNT_MAX */
-
-#define W1LMIN_ZERO   0x0010   /* write 1 to load CNT_MIN with zero */
-#define W1LMIN_CNT    0x0020   /* write 1 to load CNT_MIN from CNT_COUNTER */
-#define W1LMIN_MAX    0x0080   /* write 1 to load CNT_MIN from CNT_MAX */
-
-#define W1LMAX_ZERO   0x0100   /* write 1 to load CNT_MAX with zero */
-#define W1LMAX_CNT    0x0200   /* write 1 to load CNT_MAX from CNT_COUNTER */
-#define W1LMAX_MIN    0x0400   /* write 1 to load CNT_MAX from CNT_MIN */
-
-/* CNT_CONFIG bit field options */
-
-#define CNTMODE_QUADENC  0x0000  /* quadrature encoder mode */
-#define CNTMODE_BINENC   0x0100  /* binary encoder mode */
-#define CNTMODE_UDCNT    0x0200  /* up/down counter mode */
-#define CNTMODE_DIRCNT   0x0400  /* direction counter mode */
-#define CNTMODE_DIRTMR   0x0500  /* direction timer mode */
-
-#define BNDMODE_COMP     0x0000  /* boundary compare mode */
-#define BNDMODE_ZERO     0x1000  /* boundary compare and zero mode */
-#define BNDMODE_CAPT     0x2000  /* boundary capture mode */
-#define BNDMODE_AEXT     0x3000  /* boundary auto-extend mode */
-
-/* TMODE in TIMERx_CONFIG bit field options */
-
-#define PWM_OUT  0x0001
-#define WDTH_CAP 0x0002
-#define EXT_CLK  0x0003
-
-/* UARTx_LCR bit field options */
-
-#define WLS_5   0x0000    /* 5 data bits */
-#define WLS_6   0x0001    /* 6 data bits */
-#define WLS_7   0x0002    /* 7 data bits */
-#define WLS_8   0x0003    /* 8 data bits */
-
-/* PINTx Register Bit Definitions */
-
-#define PIQ0 0x00000001
-#define PIQ1 0x00000002
-#define PIQ2 0x00000004
-#define PIQ3 0x00000008
-
-#define PIQ4 0x00000010
-#define PIQ5 0x00000020
-#define PIQ6 0x00000040
-#define PIQ7 0x00000080
-
-#define PIQ8 0x00000100
-#define PIQ9 0x00000200
-#define PIQ10 0x00000400
-#define PIQ11 0x00000800
-
-#define PIQ12 0x00001000
-#define PIQ13 0x00002000
-#define PIQ14 0x00004000
-#define PIQ15 0x00008000
-
-#define PIQ16 0x00010000
-#define PIQ17 0x00020000
-#define PIQ18 0x00040000
-#define PIQ19 0x00080000
-
-#define PIQ20 0x00100000
-#define PIQ21 0x00200000
-#define PIQ22 0x00400000
-#define PIQ23 0x00800000
-
-#define PIQ24 0x01000000
-#define PIQ25 0x02000000
-#define PIQ26 0x04000000
-#define PIQ27 0x08000000
-
-#define PIQ28 0x10000000
-#define PIQ29 0x20000000
-#define PIQ30 0x40000000
-#define PIQ31 0x80000000
-
-/* PORT A Bit Definitions for the registers
-PORTA, PORTA_SET, PORTA_CLEAR,
-PORTA_DIR_SET, PORTA_DIR_CLEAR, PORTA_INEN,
-PORTA_FER registers
-*/
-
-#define PA0 0x0001
-#define PA1 0x0002
-#define PA2 0x0004
-#define PA3 0x0008
-#define PA4 0x0010
-#define PA5 0x0020
-#define PA6 0x0040
-#define PA7 0x0080
-#define PA8 0x0100
-#define PA9 0x0200
-#define PA10 0x0400
-#define PA11 0x0800
-#define PA12 0x1000
-#define PA13 0x2000
-#define PA14 0x4000
-#define PA15 0x8000
-
-/* PORT B Bit Definitions for the registers
-PORTB, PORTB_SET, PORTB_CLEAR,
-PORTB_DIR_SET, PORTB_DIR_CLEAR, PORTB_INEN,
-PORTB_FER registers
-*/
-
-#define PB0 0x0001
-#define PB1 0x0002
-#define PB2 0x0004
-#define PB3 0x0008
-#define PB4 0x0010
-#define PB5 0x0020
-#define PB6 0x0040
-#define PB7 0x0080
-#define PB8 0x0100
-#define PB9 0x0200
-#define PB10 0x0400
-#define PB11 0x0800
-#define PB12 0x1000
-#define PB13 0x2000
-#define PB14 0x4000
-
-
-/* PORT C Bit Definitions for the registers
-PORTC, PORTC_SET, PORTC_CLEAR,
-PORTC_DIR_SET, PORTC_DIR_CLEAR, PORTC_INEN,
-PORTC_FER registers
-*/
-
-
-#define PC0 0x0001
-#define PC1 0x0002
-#define PC2 0x0004
-#define PC3 0x0008
-#define PC4 0x0010
-#define PC5 0x0020
-#define PC6 0x0040
-#define PC7 0x0080
-#define PC8 0x0100
-#define PC9 0x0200
-#define PC10 0x0400
-#define PC11 0x0800
-#define PC12 0x1000
-#define PC13 0x2000
-
-
-/* PORT D Bit Definitions for the registers
-PORTD, PORTD_SET, PORTD_CLEAR,
-PORTD_DIR_SET, PORTD_DIR_CLEAR, PORTD_INEN,
-PORTD_FER registers
-*/
-
-#define PD0 0x0001
-#define PD1 0x0002
-#define PD2 0x0004
-#define PD3 0x0008
-#define PD4 0x0010
-#define PD5 0x0020
-#define PD6 0x0040
-#define PD7 0x0080
-#define PD8 0x0100
-#define PD9 0x0200
-#define PD10 0x0400
-#define PD11 0x0800
-#define PD12 0x1000
-#define PD13 0x2000
-#define PD14 0x4000
-#define PD15 0x8000
-
-/* PORT E Bit Definitions for the registers
-PORTE, PORTE_SET, PORTE_CLEAR,
-PORTE_DIR_SET, PORTE_DIR_CLEAR, PORTE_INEN,
-PORTE_FER registers
-*/
-
-
-#define PE0 0x0001
-#define PE1 0x0002
-#define PE2 0x0004
-#define PE3 0x0008
-#define PE4 0x0010
-#define PE5 0x0020
-#define PE6 0x0040
-#define PE7 0x0080
-#define PE8 0x0100
-#define PE9 0x0200
-#define PE10 0x0400
-#define PE11 0x0800
-#define PE12 0x1000
-#define PE13 0x2000
-#define PE14 0x4000
-#define PE15 0x8000
-
-/* PORT F Bit Definitions for the registers
-PORTF, PORTF_SET, PORTF_CLEAR,
-PORTF_DIR_SET, PORTF_DIR_CLEAR, PORTF_INEN,
-PORTF_FER registers
-*/
-
-
-#define PF0 0x0001
-#define PF1 0x0002
-#define PF2 0x0004
-#define PF3 0x0008
-#define PF4 0x0010
-#define PF5 0x0020
-#define PF6 0x0040
-#define PF7 0x0080
-#define PF8 0x0100
-#define PF9 0x0200
-#define PF10 0x0400
-#define PF11 0x0800
-#define PF12 0x1000
-#define PF13 0x2000
-#define PF14 0x4000
-#define PF15 0x8000
-
-/* PORT G Bit Definitions for the registers
-PORTG, PORTG_SET, PORTG_CLEAR,
-PORTG_DIR_SET, PORTG_DIR_CLEAR, PORTG_INEN,
-PORTG_FER registers
-*/
-
-
-#define PG0 0x0001
-#define PG1 0x0002
-#define PG2 0x0004
-#define PG3 0x0008
-#define PG4 0x0010
-#define PG5 0x0020
-#define PG6 0x0040
-#define PG7 0x0080
-#define PG8 0x0100
-#define PG9 0x0200
-#define PG10 0x0400
-#define PG11 0x0800
-#define PG12 0x1000
-#define PG13 0x2000
-#define PG14 0x4000
-#define PG15 0x8000
-
-/* PORT H Bit Definitions for the registers
-PORTH, PORTH_SET, PORTH_CLEAR,
-PORTH_DIR_SET, PORTH_DIR_CLEAR, PORTH_INEN,
-PORTH_FER registers
-*/
-
-
-#define PH0 0x0001
-#define PH1 0x0002
-#define PH2 0x0004
-#define PH3 0x0008
-#define PH4 0x0010
-#define PH5 0x0020
-#define PH6 0x0040
-#define PH7 0x0080
-#define PH8 0x0100
-#define PH9 0x0200
-#define PH10 0x0400
-#define PH11 0x0800
-#define PH12 0x1000
-#define PH13 0x2000
-
-
-/* PORT I Bit Definitions for the registers
-PORTI, PORTI_SET, PORTI_CLEAR,
-PORTI_DIR_SET, PORTI_DIR_CLEAR, PORTI_INEN,
-PORTI_FER registers
-*/
-
-
-#define PI0 0x0001
-#define PI1 0x0002
-#define PI2 0x0004
-#define PI3 0x0008
-#define PI4 0x0010
-#define PI5 0x0020
-#define PI6 0x0040
-#define PI7 0x0080
-#define PI8 0x0100
-#define PI9 0x0200
-#define PI10 0x0400
-#define PI11 0x0800
-#define PI12 0x1000
-#define PI13 0x2000
-#define PI14 0x4000
-#define PI15 0x8000
-
-/* PORT J Bit Definitions for the registers
-PORTJ, PORTJ_SET, PORTJ_CLEAR,
-PORTJ_DIR_SET, PORTJ_DIR_CLEAR, PORTJ_INEN,
-PORTJ_FER registers
-*/
-
-
-#define PJ0 0x0001
-#define PJ1 0x0002
-#define PJ2 0x0004
-#define PJ3 0x0008
-#define PJ4 0x0010
-#define PJ5 0x0020
-#define PJ6 0x0040
-#define PJ7 0x0080
-#define PJ8 0x0100
-#define PJ9 0x0200
-#define PJ10 0x0400
-#define PJ11 0x0800
-#define PJ12 0x1000
-#define PJ13 0x2000
-
-
-/* Port Muxing Bit Fields for PORTx_MUX Registers */
-
-#define MUX0 0x00000003
-#define MUX0_0 0x00000000
-#define MUX0_1 0x00000001
-#define MUX0_2 0x00000002
-#define MUX0_3 0x00000003
-
-#define MUX1 0x0000000C
-#define MUX1_0 0x00000000
-#define MUX1_1 0x00000004
-#define MUX1_2 0x00000008
-#define MUX1_3 0x0000000C
-
-#define MUX2 0x00000030
-#define MUX2_0 0x00000000
-#define MUX2_1 0x00000010
-#define MUX2_2 0x00000020
-#define MUX2_3 0x00000030
-
-#define MUX3 0x000000C0
-#define MUX3_0 0x00000000
-#define MUX3_1 0x00000040
-#define MUX3_2 0x00000080
-#define MUX3_3 0x000000C0
-
-#define MUX4 0x00000300
-#define MUX4_0 0x00000000
-#define MUX4_1 0x00000100
-#define MUX4_2 0x00000200
-#define MUX4_3 0x00000300
-
-#define MUX5 0x00000C00
-#define MUX5_0 0x00000000
-#define MUX5_1 0x00000400
-#define MUX5_2 0x00000800
-#define MUX5_3 0x00000C00
-
-#define MUX6 0x00003000
-#define MUX6_0 0x00000000
-#define MUX6_1 0x00001000
-#define MUX6_2 0x00002000
-#define MUX6_3 0x00003000
-
-#define MUX7 0x0000C000
-#define MUX7_0 0x00000000
-#define MUX7_1 0x00004000
-#define MUX7_2 0x00008000
-#define MUX7_3 0x0000C000
-
-#define MUX8 0x00030000
-#define MUX8_0 0x00000000
-#define MUX8_1 0x00010000
-#define MUX8_2 0x00020000
-#define MUX8_3 0x00030000
-
-#define MUX9 0x000C0000
-#define MUX9_0 0x00000000
-#define MUX9_1 0x00040000
-#define MUX9_2 0x00080000
-#define MUX9_3 0x000C0000
-
-#define MUX10 0x00300000
-#define MUX10_0 0x00000000
-#define MUX10_1 0x00100000
-#define MUX10_2 0x00200000
-#define MUX10_3 0x00300000
-
-#define MUX11 0x00C00000
-#define MUX11_0 0x00000000
-#define MUX11_1 0x00400000
-#define MUX11_2 0x00800000
-#define MUX11_3 0x00C00000
-
-#define MUX12 0x03000000
-#define MUX12_0 0x00000000
-#define MUX12_1 0x01000000
-#define MUX12_2 0x02000000
-#define MUX12_3 0x03000000
-
-#define MUX13 0x0C000000
-#define MUX13_0 0x00000000
-#define MUX13_1 0x04000000
-#define MUX13_2 0x08000000
-#define MUX13_3 0x0C000000
-
-#define MUX14 0x30000000
-#define MUX14_0 0x00000000
-#define MUX14_1 0x10000000
-#define MUX14_2 0x20000000
-#define MUX14_3 0x30000000
-
-#define MUX15 0xC0000000
-#define MUX15_0 0x00000000
-#define MUX15_1 0x40000000
-#define MUX15_2 0x80000000
-#define MUX15_3 0xC0000000
-
-#define MUX(b15,b14,b13,b12,b11,b10,b9,b8,b7,b6,b5,b4,b3,b2,b1,b0) \
-    ((((b15)&3) << 30) | \
-     (((b14)&3) << 28) | \
-     (((b13)&3) << 26) | \
-     (((b12)&3) << 24) | \
-     (((b11)&3) << 22) | \
-     (((b10)&3) << 20) | \
-     (((b9) &3) << 18) | \
-     (((b8) &3) << 16) | \
-     (((b7) &3) << 14) | \
-     (((b6) &3) << 12) | \
-     (((b5) &3) << 10) | \
-     (((b4) &3) << 8)  | \
-     (((b3) &3) << 6)  | \
-     (((b2) &3) << 4)  | \
-     (((b1) &3) << 2)  | \
-     (((b0) &3)))
-
-/* Bit fields for PINT0_ASSIGN and PINT1_ASSIGN registers */
-
-#define B0MAP 0x000000FF     /* Byte 0 Lower Half Port Mapping */
-#define B0MAP_PAL 0x00000000 /* Map Port A Low to Byte 0 */
-#define B0MAP_PBL 0x00000001 /* Map Port B Low to Byte 0 */
-#define B1MAP 0x0000FF00     /* Byte 1 Upper Half Port Mapping */
-#define B1MAP_PAH 0x00000000 /* Map Port A High to Byte 1 */
-#define B1MAP_PBH 0x00000100 /* Map Port B High to Byte 1 */
-#define B2MAP 0x00FF0000     /* Byte 2 Lower Half Port Mapping */
-#define B2MAP_PAL 0x00000000 /* Map Port A Low to Byte 2 */
-#define B2MAP_PBL 0x00010000 /* Map Port B Low to Byte 2 */
-#define B3MAP 0xFF000000     /* Byte 3 Upper Half Port Mapping */
-#define B3MAP_PAH 0x00000000 /* Map Port A High to Byte 3 */
-#define B3MAP_PBH 0x01000000 /* Map Port B High to Byte 3 */
-
-/* Bit fields for PINT2_ASSIGN and PINT3_ASSIGN registers */
-
-#define B0MAP_PCL 0x00000000 /* Map Port C Low to Byte 0 */
-#define B0MAP_PDL 0x00000001 /* Map Port D Low to Byte 0 */
-#define B0MAP_PEL 0x00000002 /* Map Port E Low to Byte 0 */
-#define B0MAP_PFL 0x00000003 /* Map Port F Low to Byte 0 */
-#define B0MAP_PGL 0x00000004 /* Map Port G Low to Byte 0 */
-#define B0MAP_PHL 0x00000005 /* Map Port H Low to Byte 0 */
-#define B0MAP_PIL 0x00000006 /* Map Port I Low to Byte 0 */
-#define B0MAP_PJL 0x00000007 /* Map Port J Low to Byte 0 */
-
-#define B1MAP_PCH 0x00000000 /* Map Port C High to Byte 1 */
-#define B1MAP_PDH 0x00000100 /* Map Port D High to Byte 1 */
-#define B1MAP_PEH 0x00000200 /* Map Port E High to Byte 1 */
-#define B1MAP_PFH 0x00000300 /* Map Port F High to Byte 1 */
-#define B1MAP_PGH 0x00000400 /* Map Port G High to Byte 1 */
-#define B1MAP_PHH 0x00000500 /* Map Port H High to Byte 1 */
-#define B1MAP_PIH 0x00000600 /* Map Port I High to Byte 1 */
-#define B1MAP_PJH 0x00000700 /* Map Port J High to Byte 1 */
-
-#define B2MAP_PCL 0x00000000 /* Map Port C Low to Byte 2 */
-#define B2MAP_PDL 0x00010000 /* Map Port D Low to Byte 2 */
-#define B2MAP_PEL 0x00020000 /* Map Port E Low to Byte 2 */
-#define B2MAP_PFL 0x00030000 /* Map Port F Low to Byte 2 */
-#define B2MAP_PGL 0x00040000 /* Map Port G Low to Byte 2 */
-#define B2MAP_PHL 0x00050000 /* Map Port H Low to Byte 2 */
-#define B2MAP_PIL 0x00060000 /* Map Port I Low to Byte 2 */
-#define B2MAP_PJL 0x00070000 /* Map Port J Low to Byte 2 */
-
-#define B3MAP_PCH 0x00000000 /* Map Port C High to Byte 3 */
-#define B3MAP_PDH 0x01000000 /* Map Port D High to Byte 3 */
-#define B3MAP_PEH 0x02000000 /* Map Port E High to Byte 3 */
-#define B3MAP_PFH 0x03000000 /* Map Port F High to Byte 3 */
-#define B3MAP_PGH 0x04000000 /* Map Port G High to Byte 3 */
-#define B3MAP_PHH 0x05000000 /* Map Port H High to Byte 3 */
-#define B3MAP_PIH 0x06000000 /* Map Port I High to Byte 3 */
-#define B3MAP_PJH 0x07000000 /* Map Port J High to Byte 3 */
-
-
-/* for legacy compatibility */
-
-#define WLS(x)  (((x)-5) & 0x03) /* Word Length Select */
-#define W1LMAX_MAX W1LMAX_MIN
-#define EBIU_AMCBCTL0 EBIU_AMBCTL0
-#define EBIU_AMCBCTL1 EBIU_AMBCTL1
-#define PINT0_IRQ PINT0_REQUEST
-#define PINT1_IRQ PINT1_REQUEST
-#define PINT2_IRQ PINT2_REQUEST
-#define PINT3_IRQ PINT3_REQUEST
-
-#endif /* _DEF_BF54X_H */
diff --git a/include/asm-blackfin/mach-bf548/dma.h b/include/asm-blackfin/mach-bf548/dma.h
deleted file mode 100644
index 36a2ef7e7849..000000000000
--- a/include/asm-blackfin/mach-bf548/dma.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf548/dma.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define CH_SPORT0_RX            0
-#define CH_SPORT0_TX            1
-#define CH_SPORT1_RX            2
-#define CH_SPORT1_TX            3
-#define CH_SPI0                 4
-#define CH_SPI1                 5
-#define CH_UART0_RX             6
-#define CH_UART0_TX             7
-#define CH_UART1_RX             8
-#define CH_UART1_TX             9
-#define CH_ATAPI_RX             10
-#define CH_ATAPI_TX             11
-#define CH_EPPI0                12
-#define CH_EPPI1                13
-#define CH_EPPI2                14
-#define CH_PIXC_IMAGE           15
-#define CH_PIXC_OVERLAY         16
-#define CH_PIXC_OUTPUT          17
-#define CH_SPORT2_RX            18
-#define CH_UART2_RX             18
-#define CH_SPORT2_TX            19
-#define CH_UART2_TX             19
-#define CH_SPORT3_RX            20
-#define CH_UART3_RX             20
-#define CH_SPORT3_TX            21
-#define CH_UART3_TX             21
-#define CH_SDH                  22
-#define CH_NFC                  22
-#define CH_SPI2                 23
-
-#define CH_MEM_STREAM0_DEST     24
-#define CH_MEM_STREAM0_SRC      25
-#define CH_MEM_STREAM1_DEST     26
-#define CH_MEM_STREAM1_SRC      27
-#define CH_MEM_STREAM2_DEST     28
-#define CH_MEM_STREAM2_SRC      29
-#define CH_MEM_STREAM3_DEST     30
-#define CH_MEM_STREAM3_SRC      31
-
-#define MAX_BLACKFIN_DMA_CHANNEL 32
-
-#endif
diff --git a/include/asm-blackfin/mach-bf548/gpio.h b/include/asm-blackfin/mach-bf548/gpio.h
deleted file mode 100644
index bba82dc75f16..000000000000
--- a/include/asm-blackfin/mach-bf548/gpio.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/gpio.h
- * Based on:
- * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-
-
-#define GPIO_PA0        0
-#define GPIO_PA1        1
-#define GPIO_PA2        2
-#define GPIO_PA3        3
-#define GPIO_PA4        4
-#define GPIO_PA5        5
-#define GPIO_PA6        6
-#define GPIO_PA7        7
-#define GPIO_PA8        8
-#define GPIO_PA9        9
-#define GPIO_PA10       10
-#define GPIO_PA11       11
-#define GPIO_PA12       12
-#define GPIO_PA13       13
-#define GPIO_PA14       14
-#define GPIO_PA15       15
-#define GPIO_PB0        16
-#define GPIO_PB1        17
-#define GPIO_PB2        18
-#define GPIO_PB3        19
-#define GPIO_PB4        20
-#define GPIO_PB5        21
-#define GPIO_PB6        22
-#define GPIO_PB7        23
-#define GPIO_PB8        24
-#define GPIO_PB9        25
-#define GPIO_PB10       26
-#define GPIO_PB11       27
-#define GPIO_PB12       28
-#define GPIO_PB13       29
-#define GPIO_PB14       30
-#define GPIO_PB15       31      /* N/A */
-#define GPIO_PC0        32
-#define GPIO_PC1        33
-#define GPIO_PC2        34
-#define GPIO_PC3        35
-#define GPIO_PC4        36
-#define GPIO_PC5        37
-#define GPIO_PC6        38
-#define GPIO_PC7        39
-#define GPIO_PC8        40
-#define GPIO_PC9        41
-#define GPIO_PC10       42
-#define GPIO_PC11       43
-#define GPIO_PC12       44
-#define GPIO_PC13       45
-#define GPIO_PC14       46      /* N/A */
-#define GPIO_PC15       47      /* N/A */
-#define GPIO_PD0        48
-#define GPIO_PD1        49
-#define GPIO_PD2        50
-#define GPIO_PD3        51
-#define GPIO_PD4        52
-#define GPIO_PD5        53
-#define GPIO_PD6        54
-#define GPIO_PD7        55
-#define GPIO_PD8        56
-#define GPIO_PD9        57
-#define GPIO_PD10       58
-#define GPIO_PD11       59
-#define GPIO_PD12       60
-#define GPIO_PD13       61
-#define GPIO_PD14       62
-#define GPIO_PD15       63
-#define GPIO_PE0        64
-#define GPIO_PE1        65
-#define GPIO_PE2        66
-#define GPIO_PE3        67
-#define GPIO_PE4        68
-#define GPIO_PE5        69
-#define GPIO_PE6        70
-#define GPIO_PE7        71
-#define GPIO_PE8        72
-#define GPIO_PE9        73
-#define GPIO_PE10       74
-#define GPIO_PE11       75
-#define GPIO_PE12       76
-#define GPIO_PE13       77
-#define GPIO_PE14       78
-#define GPIO_PE15       79
-#define GPIO_PF0        80
-#define GPIO_PF1        81
-#define GPIO_PF2        82
-#define GPIO_PF3        83
-#define GPIO_PF4        84
-#define GPIO_PF5        85
-#define GPIO_PF6        86
-#define GPIO_PF7        87
-#define GPIO_PF8        88
-#define GPIO_PF9        89
-#define GPIO_PF10       90
-#define GPIO_PF11       91
-#define GPIO_PF12       92
-#define GPIO_PF13       93
-#define GPIO_PF14       94
-#define GPIO_PF15       95
-#define GPIO_PG0        96
-#define GPIO_PG1        97
-#define GPIO_PG2        98
-#define GPIO_PG3        99
-#define GPIO_PG4        100
-#define GPIO_PG5        101
-#define GPIO_PG6        102
-#define GPIO_PG7        103
-#define GPIO_PG8        104
-#define GPIO_PG9        105
-#define GPIO_PG10       106
-#define GPIO_PG11       107
-#define GPIO_PG12       108
-#define GPIO_PG13       109
-#define GPIO_PG14       110
-#define GPIO_PG15       111
-#define GPIO_PH0        112
-#define GPIO_PH1        113
-#define GPIO_PH2        114
-#define GPIO_PH3        115
-#define GPIO_PH4        116
-#define GPIO_PH5        117
-#define GPIO_PH6        118
-#define GPIO_PH7        119
-#define GPIO_PH8        120
-#define GPIO_PH9        121
-#define GPIO_PH10       122
-#define GPIO_PH11       123
-#define GPIO_PH12       124
-#define GPIO_PH13       125
-#define GPIO_PH14       126     /* N/A */
-#define GPIO_PH15       127     /* N/A */
-#define GPIO_PI0        128
-#define GPIO_PI1        129
-#define GPIO_PI2        130
-#define GPIO_PI3        131
-#define GPIO_PI4        132
-#define GPIO_PI5        133
-#define GPIO_PI6        134
-#define GPIO_PI7        135
-#define GPIO_PI8        136
-#define GPIO_PI9        137
-#define GPIO_PI10       138
-#define GPIO_PI11       139
-#define GPIO_PI12       140
-#define GPIO_PI13       141
-#define GPIO_PI14       142
-#define GPIO_PI15       143
-#define GPIO_PJ0        144
-#define GPIO_PJ1        145
-#define GPIO_PJ2        146
-#define GPIO_PJ3        147
-#define GPIO_PJ4        148
-#define GPIO_PJ5        149
-#define GPIO_PJ6        150
-#define GPIO_PJ7        151
-#define GPIO_PJ8        152
-#define GPIO_PJ9        153
-#define GPIO_PJ10       154
-#define GPIO_PJ11       155
-#define GPIO_PJ12       156
-#define GPIO_PJ13       157
-#define GPIO_PJ14       158     /* N/A */
-#define GPIO_PJ15       159     /* N/A */
-
-#define MAX_BLACKFIN_GPIOS 160
-
-struct gpio_port_t {
-        unsigned short port_fer;
-        unsigned short dummy1;
-        unsigned short port_data;
-        unsigned short dummy2;
-        unsigned short port_set;
-        unsigned short dummy3;
-        unsigned short port_clear;
-        unsigned short dummy4;
-        unsigned short port_dir_set;
-        unsigned short dummy5;
-        unsigned short port_dir_clear;
-        unsigned short dummy6;
-        unsigned short port_inen;
-        unsigned short dummy7;
-        unsigned int port_mux;
-};
-
-struct gpio_port_s {
-        unsigned short fer;
-        unsigned short data;
-        unsigned short dir;
-        unsigned short inen;
-        unsigned int mux;
-};
diff --git a/include/asm-blackfin/mach-bf548/irq.h b/include/asm-blackfin/mach-bf548/irq.h
deleted file mode 100644
index ad380d1f5872..000000000000
--- a/include/asm-blackfin/mach-bf548/irq.h
+++ /dev/null
@@ -1,501 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf548/irq.h
- * based on:    include/asm-blackfin/mach-bf537/irq.h
- * author:      Roy Huang (roy.huang@analog.com)
- *
- * created:
- * description:
- *      system mmr register map
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _BF548_IRQ_H_
-#define _BF548_IRQ_H_
-
-/*
- * Interrupt source definitions
-            Event Source    Core Event Name
-Core        Emulation               **
-Events         (highest priority)  EMU         0
-            Reset                   RST         1
-            NMI                     NMI         2
-            Exception               EVX         3
-            Reserved                --          4
-            Hardware Error          IVHW        5
-            Core Timer              IVTMR       6 *
-
-.....
-
-            Software Interrupt 1    IVG14       31
-            Software Interrupt 2    --
-                 (lowest priority)  IVG15       32 *
- */
-
-#define NR_PERI_INTS    (32 * 3)
-
-/* The ABSTRACT IRQ definitions */
-/** the first seven of the following are fixed, the rest you change if you need to **/
-#define IRQ_EMU                 0       /* Emulation */
-#define IRQ_RST                 1       /* reset */
-#define IRQ_NMI                 2       /* Non Maskable */
-#define IRQ_EVX                 3       /* Exception */
-#define IRQ_UNUSED              4       /* - unused interrupt*/
-#define IRQ_HWERR               5       /* Hardware Error */
-#define IRQ_CORETMR             6       /* Core timer */
-
-#define BFIN_IRQ(x)             ((x) + 7)
-
-#define IRQ_PLL_WAKEUP          BFIN_IRQ(0)     /* PLL Wakeup Interrupt */
-#define IRQ_DMAC0_ERROR         BFIN_IRQ(1)     /* DMAC0 Status Interrupt */
-#define IRQ_EPPI0_ERROR         BFIN_IRQ(2)     /* EPPI0 Error Interrupt */
-#define IRQ_SPORT0_ERROR        BFIN_IRQ(3)     /* SPORT0 Error Interrupt */
-#define IRQ_SPORT1_ERROR        BFIN_IRQ(4)     /* SPORT1 Error Interrupt */
-#define IRQ_SPI0_ERROR          BFIN_IRQ(5)     /* SPI0 Status(Error) Interrupt */
-#define IRQ_UART0_ERROR         BFIN_IRQ(6)     /* UART0 Status(Error) Interrupt */
-#define IRQ_RTC                 BFIN_IRQ(7)     /* RTC Interrupt */
-#define IRQ_EPPI0               BFIN_IRQ(8)     /* EPPI0 Interrupt (DMA12) */
-#define IRQ_SPORT0_RX           BFIN_IRQ(9)     /* SPORT0 RX Interrupt (DMA0) */
-#define IRQ_SPORT0_TX           BFIN_IRQ(10)    /* SPORT0 TX Interrupt (DMA1) */
-#define IRQ_SPORT1_RX           BFIN_IRQ(11)    /* SPORT1 RX Interrupt (DMA2) */
-#define IRQ_SPORT1_TX           BFIN_IRQ(12)    /* SPORT1 TX Interrupt (DMA3) */
-#define IRQ_SPI0                BFIN_IRQ(13)    /* SPI0 Interrupt (DMA4) */
-#define IRQ_UART0_RX            BFIN_IRQ(14)    /* UART0 RX Interrupt (DMA6) */
-#define IRQ_UART0_TX            BFIN_IRQ(15)    /* UART0 TX Interrupt (DMA7) */
-#define IRQ_TIMER8              BFIN_IRQ(16)    /* TIMER 8 Interrupt */
-#define IRQ_TIMER9              BFIN_IRQ(17)    /* TIMER 9 Interrupt */
-#define IRQ_TIMER10             BFIN_IRQ(18)    /* TIMER 10 Interrupt */
-#define IRQ_PINT0               BFIN_IRQ(19)    /* PINT0 Interrupt */
-#define IRQ_PINT1               BFIN_IRQ(20)    /* PINT1 Interrupt */
-#define IRQ_MDMAS0              BFIN_IRQ(21)    /* MDMA Stream 0 Interrupt */
-#define IRQ_MDMAS1              BFIN_IRQ(22)    /* MDMA Stream 1 Interrupt */
-#define IRQ_WATCH               BFIN_IRQ(23)    /* Watchdog Interrupt */
-#define IRQ_DMAC1_ERROR         BFIN_IRQ(24)    /* DMAC1 Status (Error) Interrupt */
-#define IRQ_SPORT2_ERROR        BFIN_IRQ(25)    /* SPORT2 Error Interrupt */
-#define IRQ_SPORT3_ERROR        BFIN_IRQ(26)    /* SPORT3 Error Interrupt */
-#define IRQ_MXVR_DATA           BFIN_IRQ(27)    /* MXVR Data Interrupt */
-#define IRQ_SPI1_ERROR          BFIN_IRQ(28)    /* SPI1 Status (Error) Interrupt */
-#define IRQ_SPI2_ERROR          BFIN_IRQ(29)    /* SPI2 Status (Error) Interrupt */
-#define IRQ_UART1_ERROR         BFIN_IRQ(30)    /* UART1 Status (Error) Interrupt */
-#define IRQ_UART2_ERROR         BFIN_IRQ(31)    /* UART2 Status (Error) Interrupt */
-#define IRQ_CAN0_ERROR          BFIN_IRQ(32)    /* CAN0 Status (Error) Interrupt */
-#define IRQ_SPORT2_RX           BFIN_IRQ(33)    /* SPORT2 RX (DMA18) Interrupt */
-#define IRQ_UART2_RX            BFIN_IRQ(33)    /* UART2 RX (DMA18) Interrupt */
-#define IRQ_SPORT2_TX           BFIN_IRQ(34)    /* SPORT2 TX (DMA19) Interrupt */
-#define IRQ_UART2_TX            BFIN_IRQ(34)    /* UART2 TX (DMA19) Interrupt */
-#define IRQ_SPORT3_RX           BFIN_IRQ(35)    /* SPORT3 RX (DMA20) Interrupt */
-#define IRQ_UART3_RX            BFIN_IRQ(35)    /* UART3 RX (DMA20) Interrupt */
-#define IRQ_SPORT3_TX           BFIN_IRQ(36)    /* SPORT3 TX (DMA21) Interrupt */
-#define IRQ_UART3_TX            BFIN_IRQ(36)    /* UART3 TX (DMA21) Interrupt */
-#define IRQ_EPPI1               BFIN_IRQ(37)    /* EPP1 (DMA13) Interrupt */
-#define IRQ_EPPI2               BFIN_IRQ(38)    /* EPP2 (DMA14) Interrupt */
-#define IRQ_SPI1                BFIN_IRQ(39)    /* SPI1 (DMA5) Interrupt */
-#define IRQ_SPI2                BFIN_IRQ(40)    /* SPI2 (DMA23) Interrupt */
-#define IRQ_UART1_RX            BFIN_IRQ(41)    /* UART1 RX (DMA8) Interrupt */
-#define IRQ_UART1_TX            BFIN_IRQ(42)    /* UART1 TX (DMA9) Interrupt */
-#define IRQ_ATAPI_RX            BFIN_IRQ(43)    /* ATAPI RX (DMA10) Interrupt */
-#define IRQ_ATAPI_TX            BFIN_IRQ(44)    /* ATAPI TX (DMA11) Interrupt */
-#define IRQ_TWI0                BFIN_IRQ(45)    /* TWI0 Interrupt */
-#define IRQ_TWI1                BFIN_IRQ(46)    /* TWI1 Interrupt */
-#define IRQ_CAN0_RX             BFIN_IRQ(47)    /* CAN0 Receive Interrupt */
-#define IRQ_CAN0_TX             BFIN_IRQ(48)    /* CAN0 Transmit Interrupt */
-#define IRQ_MDMAS2              BFIN_IRQ(49)    /* MDMA Stream 2 Interrupt */
-#define IRQ_MDMAS3              BFIN_IRQ(50)    /* MDMA Stream 3 Interrupt */
-#define IRQ_MXVR_ERROR          BFIN_IRQ(51)    /* MXVR Status (Error) Interrupt */
-#define IRQ_MXVR_MSG            BFIN_IRQ(52)    /* MXVR Message Interrupt */
-#define IRQ_MXVR_PKT            BFIN_IRQ(53)    /* MXVR Packet Interrupt */
-#define IRQ_EPP1_ERROR          BFIN_IRQ(54)    /* EPPI1 Error Interrupt */
-#define IRQ_EPP2_ERROR          BFIN_IRQ(55)    /* EPPI2 Error Interrupt */
-#define IRQ_UART3_ERROR         BFIN_IRQ(56)    /* UART3 Status (Error) Interrupt */
-#define IRQ_HOST_ERROR          BFIN_IRQ(57)    /* HOST Status (Error) Interrupt */
-#define IRQ_PIXC_ERROR          BFIN_IRQ(59)    /* PIXC Status (Error) Interrupt */
-#define IRQ_NFC_ERROR           BFIN_IRQ(60)    /* NFC Error Interrupt */
-#define IRQ_ATAPI_ERROR         BFIN_IRQ(61)    /* ATAPI Error Interrupt */
-#define IRQ_CAN1_ERROR          BFIN_IRQ(62)    /* CAN1 Status (Error) Interrupt */
-#define IRQ_HS_DMA_ERROR        BFIN_IRQ(63)    /* Handshake DMA Status Interrupt */
-#define IRQ_PIXC_IN0            BFIN_IRQ(64)    /* PIXC IN0 (DMA15) Interrupt */
-#define IRQ_PIXC_IN1            BFIN_IRQ(65)    /* PIXC IN1 (DMA16) Interrupt */
-#define IRQ_PIXC_OUT            BFIN_IRQ(66)    /* PIXC OUT (DMA17) Interrupt */
-#define IRQ_SDH                 BFIN_IRQ(67)    /* SDH/NFC (DMA22) Interrupt */
-#define IRQ_CNT                 BFIN_IRQ(68)    /* CNT Interrupt */
-#define IRQ_KEY                 BFIN_IRQ(69)    /* KEY Interrupt */
-#define IRQ_CAN1_RX             BFIN_IRQ(70)    /* CAN1 RX Interrupt */
-#define IRQ_CAN1_TX             BFIN_IRQ(71)    /* CAN1 TX Interrupt */
-#define IRQ_SDH_MASK0           BFIN_IRQ(72)    /* SDH Mask 0 Interrupt */
-#define IRQ_SDH_MASK1           BFIN_IRQ(73)    /* SDH Mask 1 Interrupt */
-#define IRQ_USB_INT0            BFIN_IRQ(75)    /* USB INT0 Interrupt */
-#define IRQ_USB_INT1            BFIN_IRQ(76)    /* USB INT1 Interrupt */
-#define IRQ_USB_INT2            BFIN_IRQ(77)    /* USB INT2 Interrupt */
-#define IRQ_USB_DMA             BFIN_IRQ(78)    /* USB DMA Interrupt */
-#define IRQ_OPTSEC              BFIN_IRQ(79)    /* OTPSEC Interrupt */
-#define IRQ_TIMER0              BFIN_IRQ(86)    /* Timer 0 Interrupt */
-#define IRQ_TIMER1              BFIN_IRQ(87)    /* Timer 1 Interrupt */
-#define IRQ_TIMER2              BFIN_IRQ(88)    /* Timer 2 Interrupt */
-#define IRQ_TIMER3              BFIN_IRQ(89)    /* Timer 3 Interrupt */
-#define IRQ_TIMER4              BFIN_IRQ(90)    /* Timer 4 Interrupt */
-#define IRQ_TIMER5              BFIN_IRQ(91)    /* Timer 5 Interrupt */
-#define IRQ_TIMER6              BFIN_IRQ(92)    /* Timer 6 Interrupt */
-#define IRQ_TIMER7              BFIN_IRQ(93)    /* Timer 7 Interrupt */
-#define IRQ_PINT2               BFIN_IRQ(94)    /* PINT2 Interrupt */
-#define IRQ_PINT3               BFIN_IRQ(95)    /* PINT3 Interrupt */
-
-#define SYS_IRQS                IRQ_PINT3
-
-#define BFIN_PA_IRQ(x)          ((x) + SYS_IRQS + 1)
-#define IRQ_PA0                 BFIN_PA_IRQ(0)
-#define IRQ_PA1                 BFIN_PA_IRQ(1)
-#define IRQ_PA2                 BFIN_PA_IRQ(2)
-#define IRQ_PA3                 BFIN_PA_IRQ(3)
-#define IRQ_PA4                 BFIN_PA_IRQ(4)
-#define IRQ_PA5                 BFIN_PA_IRQ(5)
-#define IRQ_PA6                 BFIN_PA_IRQ(6)
-#define IRQ_PA7                 BFIN_PA_IRQ(7)
-#define IRQ_PA8                 BFIN_PA_IRQ(8)
-#define IRQ_PA9                 BFIN_PA_IRQ(9)
-#define IRQ_PA10                BFIN_PA_IRQ(10)
-#define IRQ_PA11                BFIN_PA_IRQ(11)
-#define IRQ_PA12                BFIN_PA_IRQ(12)
-#define IRQ_PA13                BFIN_PA_IRQ(13)
-#define IRQ_PA14                BFIN_PA_IRQ(14)
-#define IRQ_PA15                BFIN_PA_IRQ(15)
-
-#define BFIN_PB_IRQ(x)          ((x) + IRQ_PA15 + 1)
-#define IRQ_PB0                 BFIN_PB_IRQ(0)
-#define IRQ_PB1                 BFIN_PB_IRQ(1)
-#define IRQ_PB2                 BFIN_PB_IRQ(2)
-#define IRQ_PB3                 BFIN_PB_IRQ(3)
-#define IRQ_PB4                 BFIN_PB_IRQ(4)
-#define IRQ_PB5                 BFIN_PB_IRQ(5)
-#define IRQ_PB6                 BFIN_PB_IRQ(6)
-#define IRQ_PB7                 BFIN_PB_IRQ(7)
-#define IRQ_PB8                 BFIN_PB_IRQ(8)
-#define IRQ_PB9                 BFIN_PB_IRQ(9)
-#define IRQ_PB10                BFIN_PB_IRQ(10)
-#define IRQ_PB11                BFIN_PB_IRQ(11)
-#define IRQ_PB12                BFIN_PB_IRQ(12)
-#define IRQ_PB13                BFIN_PB_IRQ(13)
-#define IRQ_PB14                BFIN_PB_IRQ(14)
-#define IRQ_PB15                BFIN_PB_IRQ(15)         /* N/A */
-
-#define BFIN_PC_IRQ(x)          ((x) + IRQ_PB15 + 1)
-#define IRQ_PC0                 BFIN_PC_IRQ(0)
-#define IRQ_PC1                 BFIN_PC_IRQ(1)
-#define IRQ_PC2                 BFIN_PC_IRQ(2)
-#define IRQ_PC3                 BFIN_PC_IRQ(3)
-#define IRQ_PC4                 BFIN_PC_IRQ(4)
-#define IRQ_PC5                 BFIN_PC_IRQ(5)
-#define IRQ_PC6                 BFIN_PC_IRQ(6)
-#define IRQ_PC7                 BFIN_PC_IRQ(7)
-#define IRQ_PC8                 BFIN_PC_IRQ(8)
-#define IRQ_PC9                 BFIN_PC_IRQ(9)
-#define IRQ_PC10                BFIN_PC_IRQ(10)
-#define IRQ_PC11                BFIN_PC_IRQ(11)
-#define IRQ_PC12                BFIN_PC_IRQ(12)
-#define IRQ_PC13                BFIN_PC_IRQ(13)
-#define IRQ_PC14                BFIN_PC_IRQ(14)         /* N/A */
-#define IRQ_PC15                BFIN_PC_IRQ(15)         /* N/A */
-
-#define BFIN_PD_IRQ(x)          ((x) + IRQ_PC15 + 1)
-#define IRQ_PD0                 BFIN_PD_IRQ(0)
-#define IRQ_PD1                 BFIN_PD_IRQ(1)
-#define IRQ_PD2                 BFIN_PD_IRQ(2)
-#define IRQ_PD3                 BFIN_PD_IRQ(3)
-#define IRQ_PD4                 BFIN_PD_IRQ(4)
-#define IRQ_PD5                 BFIN_PD_IRQ(5)
-#define IRQ_PD6                 BFIN_PD_IRQ(6)
-#define IRQ_PD7                 BFIN_PD_IRQ(7)
-#define IRQ_PD8                 BFIN_PD_IRQ(8)
-#define IRQ_PD9                 BFIN_PD_IRQ(9)
-#define IRQ_PD10                BFIN_PD_IRQ(10)
-#define IRQ_PD11                BFIN_PD_IRQ(11)
-#define IRQ_PD12                BFIN_PD_IRQ(12)
-#define IRQ_PD13                BFIN_PD_IRQ(13)
-#define IRQ_PD14                BFIN_PD_IRQ(14)
-#define IRQ_PD15                BFIN_PD_IRQ(15)
-
-#define BFIN_PE_IRQ(x)          ((x) + IRQ_PD15 + 1)
-#define IRQ_PE0                 BFIN_PE_IRQ(0)
-#define IRQ_PE1                 BFIN_PE_IRQ(1)
-#define IRQ_PE2                 BFIN_PE_IRQ(2)
-#define IRQ_PE3                 BFIN_PE_IRQ(3)
-#define IRQ_PE4                 BFIN_PE_IRQ(4)
-#define IRQ_PE5                 BFIN_PE_IRQ(5)
-#define IRQ_PE6                 BFIN_PE_IRQ(6)
-#define IRQ_PE7                 BFIN_PE_IRQ(7)
-#define IRQ_PE8                 BFIN_PE_IRQ(8)
-#define IRQ_PE9                 BFIN_PE_IRQ(9)
-#define IRQ_PE10                BFIN_PE_IRQ(10)
-#define IRQ_PE11                BFIN_PE_IRQ(11)
-#define IRQ_PE12                BFIN_PE_IRQ(12)
-#define IRQ_PE13                BFIN_PE_IRQ(13)
-#define IRQ_PE14                BFIN_PE_IRQ(14)
-#define IRQ_PE15                BFIN_PE_IRQ(15)
-
-#define BFIN_PF_IRQ(x)          ((x) + IRQ_PE15 + 1)
-#define IRQ_PF0                 BFIN_PF_IRQ(0)
-#define IRQ_PF1                 BFIN_PF_IRQ(1)
-#define IRQ_PF2                 BFIN_PF_IRQ(2)
-#define IRQ_PF3                 BFIN_PF_IRQ(3)
-#define IRQ_PF4                 BFIN_PF_IRQ(4)
-#define IRQ_PF5                 BFIN_PF_IRQ(5)
-#define IRQ_PF6                 BFIN_PF_IRQ(6)
-#define IRQ_PF7                 BFIN_PF_IRQ(7)
-#define IRQ_PF8                 BFIN_PF_IRQ(8)
-#define IRQ_PF9                 BFIN_PF_IRQ(9)
-#define IRQ_PF10                BFIN_PF_IRQ(10)
-#define IRQ_PF11                BFIN_PF_IRQ(11)
-#define IRQ_PF12                BFIN_PF_IRQ(12)
-#define IRQ_PF13                BFIN_PF_IRQ(13)
-#define IRQ_PF14                BFIN_PF_IRQ(14)
-#define IRQ_PF15                BFIN_PF_IRQ(15)
-
-#define BFIN_PG_IRQ(x)          ((x) + IRQ_PF15 + 1)
-#define IRQ_PG0                 BFIN_PG_IRQ(0)
-#define IRQ_PG1                 BFIN_PG_IRQ(1)
-#define IRQ_PG2                 BFIN_PG_IRQ(2)
-#define IRQ_PG3                 BFIN_PG_IRQ(3)
-#define IRQ_PG4                 BFIN_PG_IRQ(4)
-#define IRQ_PG5                 BFIN_PG_IRQ(5)
-#define IRQ_PG6                 BFIN_PG_IRQ(6)
-#define IRQ_PG7                 BFIN_PG_IRQ(7)
-#define IRQ_PG8                 BFIN_PG_IRQ(8)
-#define IRQ_PG9                 BFIN_PG_IRQ(9)
-#define IRQ_PG10                BFIN_PG_IRQ(10)
-#define IRQ_PG11                BFIN_PG_IRQ(11)
-#define IRQ_PG12                BFIN_PG_IRQ(12)
-#define IRQ_PG13                BFIN_PG_IRQ(13)
-#define IRQ_PG14                BFIN_PG_IRQ(14)
-#define IRQ_PG15                BFIN_PG_IRQ(15)
-
-#define BFIN_PH_IRQ(x)          ((x) + IRQ_PG15 + 1)
-#define IRQ_PH0                 BFIN_PH_IRQ(0)
-#define IRQ_PH1                 BFIN_PH_IRQ(1)
-#define IRQ_PH2                 BFIN_PH_IRQ(2)
-#define IRQ_PH3                 BFIN_PH_IRQ(3)
-#define IRQ_PH4                 BFIN_PH_IRQ(4)
-#define IRQ_PH5                 BFIN_PH_IRQ(5)
-#define IRQ_PH6                 BFIN_PH_IRQ(6)
-#define IRQ_PH7                 BFIN_PH_IRQ(7)
-#define IRQ_PH8                 BFIN_PH_IRQ(8)
-#define IRQ_PH9                 BFIN_PH_IRQ(9)
-#define IRQ_PH10                BFIN_PH_IRQ(10)
-#define IRQ_PH11                BFIN_PH_IRQ(11)
-#define IRQ_PH12                BFIN_PH_IRQ(12)
-#define IRQ_PH13                BFIN_PH_IRQ(13)
-#define IRQ_PH14                BFIN_PH_IRQ(14)         /* N/A */
-#define IRQ_PH15                BFIN_PH_IRQ(15)         /* N/A */
-
-#define BFIN_PI_IRQ(x)          ((x) + IRQ_PH15 + 1)
-#define IRQ_PI0                 BFIN_PI_IRQ(0)
-#define IRQ_PI1                 BFIN_PI_IRQ(1)
-#define IRQ_PI2                 BFIN_PI_IRQ(2)
-#define IRQ_PI3                 BFIN_PI_IRQ(3)
-#define IRQ_PI4                 BFIN_PI_IRQ(4)
-#define IRQ_PI5                 BFIN_PI_IRQ(5)
-#define IRQ_PI6                 BFIN_PI_IRQ(6)
-#define IRQ_PI7                 BFIN_PI_IRQ(7)
-#define IRQ_PI8                 BFIN_PI_IRQ(8)
-#define IRQ_PI9                 BFIN_PI_IRQ(9)
-#define IRQ_PI10                BFIN_PI_IRQ(10)
-#define IRQ_PI11                BFIN_PI_IRQ(11)
-#define IRQ_PI12                BFIN_PI_IRQ(12)
-#define IRQ_PI13                BFIN_PI_IRQ(13)
-#define IRQ_PI14                BFIN_PI_IRQ(14)
-#define IRQ_PI15                BFIN_PI_IRQ(15)
-
-#define BFIN_PJ_IRQ(x)          ((x) + IRQ_PI15 + 1)
-#define IRQ_PJ0                 BFIN_PJ_IRQ(0)
-#define IRQ_PJ1                 BFIN_PJ_IRQ(1)
-#define IRQ_PJ2                 BFIN_PJ_IRQ(2)
-#define IRQ_PJ3                 BFIN_PJ_IRQ(3)
-#define IRQ_PJ4                 BFIN_PJ_IRQ(4)
-#define IRQ_PJ5                 BFIN_PJ_IRQ(5)
-#define IRQ_PJ6                 BFIN_PJ_IRQ(6)
-#define IRQ_PJ7                 BFIN_PJ_IRQ(7)
-#define IRQ_PJ8                 BFIN_PJ_IRQ(8)
-#define IRQ_PJ9                 BFIN_PJ_IRQ(9)
-#define IRQ_PJ10                BFIN_PJ_IRQ(10)
-#define IRQ_PJ11                BFIN_PJ_IRQ(11)
-#define IRQ_PJ12                BFIN_PJ_IRQ(12)
-#define IRQ_PJ13                BFIN_PJ_IRQ(13)
-#define IRQ_PJ14                BFIN_PJ_IRQ(14)         /* N/A */
-#define IRQ_PJ15                BFIN_PJ_IRQ(15)         /* N/A */
-
-#define GPIO_IRQ_BASE   IRQ_PA0
-
-#define NR_IRQS     (IRQ_PJ15+1)
-
-/* For compatibility reasons with existing code */
-
-#define IRQ_DMAC0_ERR           IRQ_DMAC0_ERROR
-#define IRQ_EPPI0_ERR           IRQ_EPPI0_ERROR
-#define IRQ_SPORT0_ERR          IRQ_SPORT0_ERROR
-#define IRQ_SPORT1_ERR          IRQ_SPORT1_ERROR
-#define IRQ_SPI0_ERR            IRQ_SPI0_ERROR
-#define IRQ_UART0_ERR           IRQ_UART0_ERROR
-#define IRQ_DMAC1_ERR           IRQ_DMAC1_ERROR
-#define IRQ_SPORT2_ERR          IRQ_SPORT2_ERROR
-#define IRQ_SPORT3_ERR          IRQ_SPORT3_ERROR
-#define IRQ_SPI1_ERR            IRQ_SPI1_ERROR
-#define IRQ_SPI2_ERR            IRQ_SPI2_ERROR
-#define IRQ_UART1_ERR           IRQ_UART1_ERROR
-#define IRQ_UART2_ERR           IRQ_UART2_ERROR
-#define IRQ_CAN0_ERR            IRQ_CAN0_ERROR
-#define IRQ_MXVR_ERR            IRQ_MXVR_ERROR
-#define IRQ_EPP1_ERR            IRQ_EPP1_ERROR
-#define IRQ_EPP2_ERR            IRQ_EPP2_ERROR
-#define IRQ_UART3_ERR           IRQ_UART3_ERROR
-#define IRQ_HOST_ERR            IRQ_HOST_ERROR
-#define IRQ_PIXC_ERR            IRQ_PIXC_ERROR
-#define IRQ_NFC_ERR             IRQ_NFC_ERROR
-#define IRQ_ATAPI_ERR           IRQ_ATAPI_ERROR
-#define IRQ_CAN1_ERR            IRQ_CAN1_ERROR
-#define IRQ_HS_DMA_ERR          IRQ_HS_DMA_ERROR
-
-
-#define IVG7            7
-#define IVG8            8
-#define IVG9            9
-#define IVG10           10
-#define IVG11           11
-#define IVG12           12
-#define IVG13           13
-#define IVG14           14
-#define IVG15           15
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS      0
-#define IRQ_DMAC0_ERR_POS       4
-#define IRQ_EPPI0_ERR_POS       8
-#define IRQ_SPORT0_ERR_POS      12
-#define IRQ_SPORT1_ERR_POS      16
-#define IRQ_SPI0_ERR_POS        20
-#define IRQ_UART0_ERR_POS       24
-#define IRQ_RTC_POS             28
-
-/* IAR1 BIT FIELDS */
-#define IRQ_EPPI0_POS           0
-#define IRQ_SPORT0_RX_POS       4
-#define IRQ_SPORT0_TX_POS       8
-#define IRQ_SPORT1_RX_POS       12
-#define IRQ_SPORT1_TX_POS       16
-#define IRQ_SPI0_POS            20
-#define IRQ_UART0_RX_POS        24
-#define IRQ_UART0_TX_POS        28
-
-/* IAR2 BIT FIELDS */
-#define IRQ_TIMER8_POS          0
-#define IRQ_TIMER9_POS          4
-#define IRQ_TIMER10_POS         8
-#define IRQ_PINT0_POS           12
-#define IRQ_PINT1_POS           16
-#define IRQ_MDMAS0_POS          20
-#define IRQ_MDMAS1_POS          24
-#define IRQ_WATCH_POS           28
-
-/* IAR3 BIT FIELDS */
-#define IRQ_DMAC1_ERR_POS       0
-#define IRQ_SPORT2_ERR_POS      4
-#define IRQ_SPORT3_ERR_POS      8
-#define IRQ_MXVR_DATA_POS       12
-#define IRQ_SPI1_ERR_POS        16
-#define IRQ_SPI2_ERR_POS        20
-#define IRQ_UART1_ERR_POS       24
-#define IRQ_UART2_ERR_POS       28
-
-/* IAR4 BIT FILEDS */
-#define IRQ_CAN0_ERR_POS        0
-#define IRQ_SPORT2_RX_POS       4
-#define IRQ_UART2_RX_POS        4
-#define IRQ_SPORT2_TX_POS       8
-#define IRQ_UART2_TX_POS        8
-#define IRQ_SPORT3_RX_POS       12
-#define IRQ_UART3_RX_POS        12
-#define IRQ_SPORT3_TX_POS       16
-#define IRQ_UART3_TX_POS        16
-#define IRQ_EPPI1_POS           20
-#define IRQ_EPPI2_POS           24
-#define IRQ_SPI1_POS            28
-
-/* IAR5 BIT FIELDS */
-#define IRQ_SPI2_POS            0
-#define IRQ_UART1_RX_POS        4
-#define IRQ_UART1_TX_POS        8
-#define IRQ_ATAPI_RX_POS        12
-#define IRQ_ATAPI_TX_POS        16
-#define IRQ_TWI0_POS            20
-#define IRQ_TWI1_POS            24
-#define IRQ_CAN0_RX_POS         28
-
-/* IAR6 BIT FIELDS */
-#define IRQ_CAN0_TX_POS         0
-#define IRQ_MDMAS2_POS          4
-#define IRQ_MDMAS3_POS          8
-#define IRQ_MXVR_ERR_POS        12
-#define IRQ_MXVR_MSG_POS        16
-#define IRQ_MXVR_PKT_POS        20
-#define IRQ_EPPI1_ERR_POS       24
-#define IRQ_EPPI2_ERR_POS       28
-
-/* IAR7 BIT FIELDS */
-#define IRQ_UART3_ERR_POS       0
-#define IRQ_HOST_ERR_POS        4
-#define IRQ_PIXC_ERR_POS        12
-#define IRQ_NFC_ERR_POS         16
-#define IRQ_ATAPI_ERR_POS       20
-#define IRQ_CAN1_ERR_POS        24
-#define IRQ_HS_DMA_ERR_POS      28
-
-/* IAR8 BIT FIELDS */
-#define IRQ_PIXC_IN0_POS        0
-#define IRQ_PIXC_IN1_POS        4
-#define IRQ_PIXC_OUT_POS        8
-#define IRQ_SDH_POS             12
-#define IRQ_CNT_POS             16
-#define IRQ_KEY_POS             20
-#define IRQ_CAN1_RX_POS         24
-#define IRQ_CAN1_TX_POS         28
-
-/* IAR9 BIT FIELDS */
-#define IRQ_SDH_MASK0_POS       0
-#define IRQ_SDH_MASK1_POS       4
-#define IRQ_USB_INT0_POS        12
-#define IRQ_USB_INT1_POS        16
-#define IRQ_USB_INT2_POS        20
-#define IRQ_USB_DMA_POS         24
-#define IRQ_OTPSEC_POS          28
-
-/* IAR10 BIT FIELDS */
-#define IRQ_TIMER0_POS          24
-#define IRQ_TIMER1_POS          28
-
-/* IAR11 BIT FIELDS */
-#define IRQ_TIMER2_POS          0
-#define IRQ_TIMER3_POS          4
-#define IRQ_TIMER4_POS          8
-#define IRQ_TIMER5_POS          12
-#define IRQ_TIMER6_POS          16
-#define IRQ_TIMER7_POS          20
-#define IRQ_PINT2_POS           24
-#define IRQ_PINT3_POS           28
-
-#endif /* _BF548_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf548/mem_init.h b/include/asm-blackfin/mach-bf548/mem_init.h
deleted file mode 100644
index ab0b863eee66..000000000000
--- a/include/asm-blackfin/mach-bf548/mem_init.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf548/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-#define MIN_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000 + 1)
-#define MAX_DDR_SCLK(x) (x*(CONFIG_SCLK_HZ/1000/1000)/1000)
-#define DDR_CLK_HZ(x)   (1000*1000*1000/x)
-
-#if (CONFIG_MEM_MT46V32M16_6T)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(60))
-#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(42))
-#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(72))
-#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR        DDR_TWTR(1)
-#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(12))
-#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_MEM_MT46V32M16_5B)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRC         DDR_TRC(MIN_DDR_SCLK(55))
-#define DDR_tRAS        DDR_TRAS(MIN_DDR_SCLK(40))
-#define DDR_tRP         DDR_TRP(MIN_DDR_SCLK(15))
-#define DDR_tRFC        DDR_TRFC(MIN_DDR_SCLK(70))
-#define DDR_tREFI       DDR_TREFI(MAX_DDR_SCLK(7800))
-
-#define DDR_tRCD        DDR_TRCD(MIN_DDR_SCLK(15))
-#define DDR_tWTR        DDR_TWTR(2)
-#define DDR_tMRD        DDR_TMRD(MIN_DDR_SCLK(10))
-#define DDR_tWR         DDR_TWR(MIN_DDR_SCLK(15))
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-#define DDR_SIZE        DEVSZ_512
-#define DDR_WIDTH       DEVWD_16
-#define DDR_MAX_tCK     13
-
-#define DDR_tRCD        DDR_TRCD(3)
-#define DDR_tWTR        DDR_TWTR(2)
-#define DDR_tWR         DDR_TWR(2)
-#define DDR_tMRD        DDR_TMRD(2)
-#define DDR_tRP         DDR_TRP(3)
-#define DDR_tRAS        DDR_TRAS(7)
-#define DDR_tRC         DDR_TRC(10)
-#define DDR_tRFC        DDR_TRFC(12)
-#define DDR_tREFI       DDR_TREFI(1288)
-#endif
-
-#if (CONFIG_SCLK_HZ < DDR_CLK_HZ(DDR_MAX_tCK))
-# error "CONFIG_SCLK_HZ is too small (<DDR_CLK_HZ(DDR_MAX_tCK) Hz)."
-#elif(CONFIG_SCLK_HZ <= 133333333)
-# define        DDR_CL          CL_2
-#else
-# error "CONFIG_SCLK_HZ is too large (>133333333 Hz)."
-#endif
-
-
-#define mem_DDRCTL0     (DDR_tRP | DDR_tRAS | DDR_tRC | DDR_tRFC | DDR_tREFI)
-#define mem_DDRCTL1     (DDR_DATWIDTH | EXTBANK_1 | DDR_SIZE | DDR_WIDTH | DDR_tWTR \
-                        | DDR_tMRD | DDR_tWR | DDR_tRCD)
-#define mem_DDRCTL2     DDR_CL
-
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf548/mem_map.h b/include/asm-blackfin/mach-bf548/mem_map.h
deleted file mode 100644
index f99f47bc3a07..000000000000
--- a/include/asm-blackfin/mach-bf548/mem_map.h
+++ /dev/null
@@ -1,111 +0,0 @@
-/*
- * file:         include/asm-blackfin/mach-bf548/mem_map.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
- * rev:
- *
- * modified:
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#ifndef _MEM_MAP_548_H_
-#define _MEM_MAP_548_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x1000
-
-/* L1 Instruction ROM */
-
-#define L1_ROM_START            0xFFA14000
-#define L1_ROM_LENGTH           0x10000
-
-/* Level 1 Memory */
-
-/* Memory Map for ADSP-BF548 processors */
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-#define L1_CODE_START       0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0xC000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-
-/* Level 2 Memory */
-#if !defined(CONFIG_BF542)
-# define L2_START          0xFEB00000
-# if defined(CONFIG_BF544)
-#  define L2_LENGTH        0x10000
-# else
-#  define L2_LENGTH        0x20000
-# endif
-#endif
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif/* _MEM_MAP_548_H_ */
diff --git a/include/asm-blackfin/mach-bf548/portmux.h b/include/asm-blackfin/mach-bf548/portmux.h
deleted file mode 100644
index 8177a567dcdb..000000000000
--- a/include/asm-blackfin/mach-bf548/portmux.h
+++ /dev/null
@@ -1,286 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_SPORT2_TFS    (P_DEFINED | P_IDENT(GPIO_PA0) | P_FUNCT(0))
-#define P_SPORT2_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(0))
-#define P_SPORT2_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA2) | P_FUNCT(0))
-#define P_SPORT2_TSCLK  (P_DEFINED | P_IDENT(GPIO_PA3) | P_FUNCT(0))
-#define P_SPORT2_RFS    (P_DEFINED | P_IDENT(GPIO_PA4) | P_FUNCT(0))
-#define P_SPORT2_DRSEC  (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(0))
-#define P_SPORT2_DRPRI  (P_DEFINED | P_IDENT(GPIO_PA6) | P_FUNCT(0))
-#define P_SPORT2_RSCLK  (P_DEFINED | P_IDENT(GPIO_PA7) | P_FUNCT(0))
-#define P_SPORT3_TFS    (P_DEFINED | P_IDENT(GPIO_PA8) | P_FUNCT(0))
-#define P_SPORT3_DTSEC  (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(0))
-#define P_SPORT3_DTPRI  (P_DEFINED | P_IDENT(GPIO_PA10) | P_FUNCT(0))
-#define P_SPORT3_TSCLK  (P_DEFINED | P_IDENT(GPIO_PA11) | P_FUNCT(0))
-#define P_SPORT3_RFS    (P_DEFINED | P_IDENT(GPIO_PA12) | P_FUNCT(0))
-#define P_SPORT3_DRSEC  (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(0))
-#define P_SPORT3_DRPRI  (P_DEFINED | P_IDENT(GPIO_PA14) | P_FUNCT(0))
-#define P_SPORT3_RSCLK  (P_DEFINED | P_IDENT(GPIO_PA15) | P_FUNCT(0))
-#define P_TMR4  (P_DEFINED | P_IDENT(GPIO_PA1) | P_FUNCT(1))
-#define P_TMR5  (P_DEFINED | P_IDENT(GPIO_PA5) | P_FUNCT(1))
-#define P_TMR6  (P_DEFINED | P_IDENT(GPIO_PA9) | P_FUNCT(1))
-#define P_TMR7  (P_DEFINED | P_IDENT(GPIO_PA13) | P_FUNCT(1))
-
-#define P_TWI1_SCL      (P_DEFINED | P_IDENT(GPIO_PB0) | P_FUNCT(0))
-#define P_TWI1_SDA      (P_DEFINED | P_IDENT(GPIO_PB1) | P_FUNCT(0))
-#define P_UART3_RTS     (P_DEFINED | P_IDENT(GPIO_PB2) | P_FUNCT(0))
-#define P_UART3_CTS     (P_DEFINED | P_IDENT(GPIO_PB3) | P_FUNCT(0))
-#define P_UART2_TX      (P_DEFINED | P_IDENT(GPIO_PB4) | P_FUNCT(0))
-#define P_UART2_RX      (P_DEFINED | P_IDENT(GPIO_PB5) | P_FUNCT(0))
-#define P_UART3_TX      (P_DEFINED | P_IDENT(GPIO_PB6) | P_FUNCT(0))
-#define P_UART3_RX      (P_DEFINED | P_IDENT(GPIO_PB7) | P_FUNCT(0))
-#define P_SPI2_SS       (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(0))
-#define P_SPI2_SSEL1    (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(0))
-#define P_SPI2_SSEL2    (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(0))
-#define P_SPI2_SSEL3    (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(0))
-#define P_SPI2_SCK      (P_DEFINED | P_IDENT(GPIO_PB12) | P_FUNCT(0))
-#define P_SPI2_MOSI     (P_DEFINED | P_IDENT(GPIO_PB13) | P_FUNCT(0))
-#define P_SPI2_MISO     (P_DEFINED | P_IDENT(GPIO_PB14) | P_FUNCT(0))
-#define P_TMR0  (P_DEFINED | P_IDENT(GPIO_PB8) | P_FUNCT(1))
-#define P_TMR1  (P_DEFINED | P_IDENT(GPIO_PB9) | P_FUNCT(1))
-#define P_TMR2  (P_DEFINED | P_IDENT(GPIO_PB10) | P_FUNCT(1))
-#define P_TMR3  (P_DEFINED | P_IDENT(GPIO_PB11) | P_FUNCT(1))
-
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PC0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(0))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PC2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PC3) | P_FUNCT(0))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PC4) | P_FUNCT(0))
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(0))
-#define P_SPORT0_DRPRI  (P_DEFINED | P_IDENT(GPIO_PC6) | P_FUNCT(0))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PC7) | P_FUNCT(0))
-#define P_SD_D0 (P_DEFINED | P_IDENT(GPIO_PC8) | P_FUNCT(0))
-#define P_SD_D1 (P_DEFINED | P_IDENT(GPIO_PC9) | P_FUNCT(0))
-#define P_SD_D2 (P_DEFINED | P_IDENT(GPIO_PC10) | P_FUNCT(0))
-#define P_SD_D3 (P_DEFINED | P_IDENT(GPIO_PC11) | P_FUNCT(0))
-#define P_SD_CLK        (P_DEFINED | P_IDENT(GPIO_PC12) | P_FUNCT(0))
-#define P_SD_CMD        (P_DEFINED | P_IDENT(GPIO_PC13) | P_FUNCT(0))
-#define P_MMCLK (P_DEFINED | P_IDENT(GPIO_PC1) | P_FUNCT(1))
-#define P_MBCLK (P_DEFINED | P_IDENT(GPIO_PC5) | P_FUNCT(1))
-
-#define P_PPI1_D0       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(0))
-#define P_PPI1_D1       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(0))
-#define P_PPI1_D2       (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(0))
-#define P_PPI1_D3       (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(0))
-#define P_PPI1_D4       (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(0))
-#define P_PPI1_D5       (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(0))
-#define P_PPI1_D6       (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(0))
-#define P_PPI1_D7       (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(0))
-#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(0))
-#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(0))
-#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(0))
-#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(0))
-#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(0))
-#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(0))
-#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(0))
-#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(0))
-
-#define P_HOST_D8       (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(1))
-#define P_HOST_D9       (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(1))
-#define P_HOST_D10      (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(1))
-#define P_HOST_D11      (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(1))
-#define P_HOST_D12      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(1))
-#define P_HOST_D13      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(1))
-#define P_HOST_D14      (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(1))
-#define P_HOST_D15      (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(1))
-#define P_HOST_D0       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(1))
-#define P_HOST_D1       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(1))
-#define P_HOST_D2       (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(1))
-#define P_HOST_D3       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(1))
-#define P_HOST_D4       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(1))
-#define P_HOST_D5       (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(1))
-#define P_HOST_D6       (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(1))
-#define P_HOST_D7       (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(1))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(2))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(2))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(2))
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(2))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(2))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(2))
-#define P_SPORT1_DRPRI  (P_DEFINED | P_IDENT(GPIO_PD6) | P_FUNCT(2))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PD7) | P_FUNCT(2))
-#define P_PPI2_D0       (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(2))
-#define P_PPI2_D1       (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(2))
-#define P_PPI2_D2       (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(2))
-#define P_PPI2_D3       (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(2))
-#define P_PPI2_D4       (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(2))
-#define P_PPI2_D5       (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(2))
-#define P_PPI2_D6       (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(2))
-#define P_PPI2_D7       (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(2))
-#define P_PPI0_D18      (P_DEFINED | P_IDENT(GPIO_PD0) | P_FUNCT(3))
-#define P_PPI0_D19      (P_DEFINED | P_IDENT(GPIO_PD1) | P_FUNCT(3))
-#define P_PPI0_D20      (P_DEFINED | P_IDENT(GPIO_PD2) | P_FUNCT(3))
-#define P_PPI0_D21      (P_DEFINED | P_IDENT(GPIO_PD3) | P_FUNCT(3))
-#define P_PPI0_D22      (P_DEFINED | P_IDENT(GPIO_PD4) | P_FUNCT(3))
-#define P_PPI0_D23      (P_DEFINED | P_IDENT(GPIO_PD5) | P_FUNCT(3))
-#define P_KEY_ROW0      (P_DEFINED | P_IDENT(GPIO_PD8) | P_FUNCT(3))
-#define P_KEY_ROW1      (P_DEFINED | P_IDENT(GPIO_PD9) | P_FUNCT(3))
-#define P_KEY_ROW2      (P_DEFINED | P_IDENT(GPIO_PD10) | P_FUNCT(3))
-#define P_KEY_ROW3      (P_DEFINED | P_IDENT(GPIO_PD11) | P_FUNCT(3))
-#define P_KEY_COL0      (P_DEFINED | P_IDENT(GPIO_PD12) | P_FUNCT(3))
-#define P_KEY_COL1      (P_DEFINED | P_IDENT(GPIO_PD13) | P_FUNCT(3))
-#define P_KEY_COL2      (P_DEFINED | P_IDENT(GPIO_PD14) | P_FUNCT(3))
-#define P_KEY_COL3      (P_DEFINED | P_IDENT(GPIO_PD15) | P_FUNCT(3))
-
-#define P_SPI0_SCK      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(0))
-#define P_SPI0_MISO     (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(0))
-#define P_SPI0_MOSI     (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(0))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(0))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(0))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(0))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(0))
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(0))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PE8) | P_FUNCT(0))
-#define P_UART1_RTS     (P_DEFINED | P_IDENT(GPIO_PE9) | P_FUNCT(0))
-#define P_UART1_CTS     (P_DEFINED | P_IDENT(GPIO_PE10) | P_FUNCT(0))
-#define P_PPI1_CLK      (P_DEFINED | P_IDENT(GPIO_PE11) | P_FUNCT(0))
-#define P_PPI1_FS1      (P_DEFINED | P_IDENT(GPIO_PE12) | P_FUNCT(0))
-#define P_PPI1_FS2      (P_DEFINED | P_IDENT(GPIO_PE13) | P_FUNCT(0))
-#define P_TWI0_SCL      (P_DEFINED | P_IDENT(GPIO_PE14) | P_FUNCT(0))
-#define P_TWI0_SDA      (P_DEFINED | P_IDENT(GPIO_PE15) | P_FUNCT(0))
-#define P_KEY_COL7      (P_DEFINED | P_IDENT(GPIO_PE0) | P_FUNCT(1))
-#define P_KEY_ROW6      (P_DEFINED | P_IDENT(GPIO_PE1) | P_FUNCT(1))
-#define P_KEY_COL6      (P_DEFINED | P_IDENT(GPIO_PE2) | P_FUNCT(1))
-#define P_KEY_ROW5      (P_DEFINED | P_IDENT(GPIO_PE3) | P_FUNCT(1))
-#define P_KEY_COL5      (P_DEFINED | P_IDENT(GPIO_PE4) | P_FUNCT(1))
-#define P_KEY_ROW4      (P_DEFINED | P_IDENT(GPIO_PE5) | P_FUNCT(1))
-#define P_KEY_COL4      (P_DEFINED | P_IDENT(GPIO_PE6) | P_FUNCT(1))
-#define P_KEY_ROW7      (P_DEFINED | P_IDENT(GPIO_PE7) | P_FUNCT(1))
-
-#define P_PPI0_D0       (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1       (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2       (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3       (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4       (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5       (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6       (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7       (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_ATAPI_D0A     (P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_ATAPI_D1A     (P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_ATAPI_D2A     (P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_ATAPI_D3A     (P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_ATAPI_D4A     (P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_ATAPI_D5A     (P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_ATAPI_D6A     (P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_ATAPI_D7A     (P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_ATAPI_D8A     (P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_ATAPI_D9A     (P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_ATAPI_D10A    (P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_ATAPI_D11A    (P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_ATAPI_D12A    (P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_ATAPI_D13A    (P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_ATAPI_D14A    (P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_ATAPI_D15A    (P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_CLK      (P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_PPI0_FS1      (P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_PPI0_FS2      (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_PPI0_D16      (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_PPI0_D17      (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPI1_SSEL1    (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_SSEL2    (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPI1_SSEL3    (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPI1_SCK      (P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPI1_MISO     (P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPI1_MOSI     (P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPI1_SS       (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_CAN0_TX       (P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_CAN0_RX       (P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_CAN1_TX       (P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_CAN1_RX       (P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_ATAPI_A0A     (P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-#define P_ATAPI_A1A     (P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_ATAPI_A2A     (P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_HOST_CE       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_HOST_RD       (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_HOST_WR       (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_MTXONB        (P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_PPI2_FS2      (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_PPI2_FS1      (P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PPI2_CLK      (P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_CNT_CZM       (P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(3))
-
-#define P_UART1_TX      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_UART1_RX      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ATAPI_RESET   (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_HOST_ADDR     (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_HOST_ACK      (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_MTX   (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_MRX   (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_MRXONB        (P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#define P_A4    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_A5    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_A6    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_A7    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_A8    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_A9    (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_PPI1_FS3      (P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_PPI2_FS3      (P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_TMR8  (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_TMR9  (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_TMR10 (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_DMAR0 (P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_DMAR1 (P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_PPI0_FS3      (P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_CNT_CDG       (P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_CNT_CUD       (P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-
-#define P_A10   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI0) | P_FUNCT(0))
-#define P_A11   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI1) | P_FUNCT(0))
-#define P_A12   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI2) | P_FUNCT(0))
-#define P_A13   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI3) | P_FUNCT(0))
-#define P_A14   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI4) | P_FUNCT(0))
-#define P_A15   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI5) | P_FUNCT(0))
-#define P_A16   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI6) | P_FUNCT(0))
-#define P_A17   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI7) | P_FUNCT(0))
-#define P_A18   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI8) | P_FUNCT(0))
-#define P_A19   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI9) | P_FUNCT(0))
-#define P_A20   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI10) | P_FUNCT(0))
-#define P_A21   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI11) | P_FUNCT(0))
-#define P_A22   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI12) | P_FUNCT(0))
-#define P_A23   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI13) | P_FUNCT(0))
-#define P_A24   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI14) | P_FUNCT(0))
-#define P_A25   (P_MAYSHARE | P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(0))
-#define P_NOR_CLK       (P_DEFINED | P_IDENT(GPIO_PI15) | P_FUNCT(1))
-
-#define P_AMC_ARDY_NOR_WAIT     (P_DEFINED | P_IDENT(GPIO_PJ0) | P_FUNCT(0))
-#define P_NAND_CE       (P_DEFINED | P_IDENT(GPIO_PJ1) | P_FUNCT(0))
-#define P_NAND_RB       (P_DEFINED | P_IDENT(GPIO_PJ2) | P_FUNCT(0))
-#define P_ATAPI_DIOR    (P_DEFINED | P_IDENT(GPIO_PJ3) | P_FUNCT(0))
-#define P_ATAPI_DIOW    (P_DEFINED | P_IDENT(GPIO_PJ4) | P_FUNCT(0))
-#define P_ATAPI_CS0     (P_DEFINED | P_IDENT(GPIO_PJ5) | P_FUNCT(0))
-#define P_ATAPI_CS1     (P_DEFINED | P_IDENT(GPIO_PJ6) | P_FUNCT(0))
-#define P_ATAPI_DMACK   (P_DEFINED | P_IDENT(GPIO_PJ7) | P_FUNCT(0))
-#define P_ATAPI_DMARQ   (P_DEFINED | P_IDENT(GPIO_PJ8) | P_FUNCT(0))
-#define P_ATAPI_INTRQ   (P_DEFINED | P_IDENT(GPIO_PJ9) | P_FUNCT(0))
-#define P_ATAPI_IORDY   (P_DEFINED | P_IDENT(GPIO_PJ10) | P_FUNCT(0))
-#define P_AMC_BR        (P_DEFINED | P_IDENT(GPIO_PJ11) | P_FUNCT(0))
-#define P_AMC_BG        (P_DEFINED | P_IDENT(GPIO_PJ12) | P_FUNCT(0))
-#define P_AMC_BGH       (P_DEFINED | P_IDENT(GPIO_PJ13) | P_FUNCT(0))
-
-
-#define P_NAND_D0       (P_DONTCARE)
-#define P_NAND_D1       (P_DONTCARE)
-#define P_NAND_D2       (P_DONTCARE)
-#define P_NAND_D3       (P_DONTCARE)
-#define P_NAND_D4       (P_DONTCARE)
-#define P_NAND_D5       (P_DONTCARE)
-#define P_NAND_D6       (P_DONTCARE)
-#define P_NAND_D7       (P_DONTCARE)
-#define P_NAND_WE       (P_DONTCARE)
-#define P_NAND_RE       (P_DONTCARE)
-#define P_NAND_CLE      (P_DONTCARE)
-#define P_NAND_ALE      (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
deleted file mode 100644
index 5c5d7d7d695f..000000000000
--- a/include/asm-blackfin/mach-bf561/anomaly.h
+++ /dev/null
@@ -1,274 +0,0 @@
-/*
- * File: include/asm-blackfin/mach-bf561/anomaly.h
- * Bugs: Enter bugs at http://blackfin.uclinux.org/
- *
- * Copyright (C) 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-/* This file shoule be up to date with:
- *  - Revision P, 02/08/2008; ADSP-BF561 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1, 0.2, or 0.4 silicon - sorry */
-#if __SILICON_REVISION__ < 3 || __SILICON_REVISION__ == 4
-# error will not work on BF561 silicon version 0.0, 0.1, 0.2, or 0.4
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot 2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Trace Buffers may contain errors in emulation mode and/or exception, NMI, reset handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* Testset instructions restricted to 32-bit aligned memory locations */
-#define ANOMALY_05000120 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Erroneous exception when enabling cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* Signbits instruction not functional under certain conditions */
-#define ANOMALY_05000127 (1)
-/* Two bits in the Watchpoint Status Register (WPSTAT) are swapped */
-#define ANOMALY_05000134 (__SILICON_REVISION__ < 3)
-/* Enable wires from the Data Watchpoint Address Control Register (WPDACTL) are swapped */
-#define ANOMALY_05000135 (__SILICON_REVISION__ < 3)
-/* Stall in multi-unit DMA operations */
-#define ANOMALY_05000136 (__SILICON_REVISION__ < 3)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* IMDMA S1/D1 channel may stall */
-#define ANOMALY_05000149 (1)
-/* DMA engine may lose data due to incorrect handshaking */
-#define ANOMALY_05000150 (__SILICON_REVISION__ < 3)
-/* DMA stalls when all three controllers read data from the same source */
-#define ANOMALY_05000151 (__SILICON_REVISION__ < 3)
-/* Execution stall when executing in L2 and doing external accesses */
-#define ANOMALY_05000152 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timers in PWM-Out Mode with PPI GP Receive (Input) Mode with 0 Frame Syncs */
-#define ANOMALY_05000156 (__SILICON_REVISION__ < 4)
-/* Killed 32-bit MMR write leads to next system MMR access thinking it should be 32-bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000159 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000160 (__SILICON_REVISION__ < 3)
-/* Data Cache Fill data can be corrupted after/during Instruction DMA if certain core stalls exist */
-#define ANOMALY_05000161 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> is not set on Reset */
-#define ANOMALY_05000162 (__SILICON_REVISION__ < 3)
-/* SPORT transmit data is not gated by external frame sync in certain conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* PPI Data Lengths Between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning Serial Ports on with External Frame Syncs */
-#define ANOMALY_05000167 (1)
-/* SDRAM auto-refresh and subsequent Power Ups */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 5)
-/* DATA CPLB page miss can result in lost write-through cache data writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 5)
-/* Boot-ROM code modifies SICA_IWRx wakeup registers */
-#define ANOMALY_05000171 (__SILICON_REVISION__ < 5)
-/* DSPID register values incorrect */
-#define ANOMALY_05000172 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 5)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 5)
-/* Multiplication of (-1) by (-1) followed by an accumulator saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 5)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Disabling the PPI resets the PPI configuration registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 5)
-/* IMDMA does not operate to full speed for 600MHz and higher devices */
-#define ANOMALY_05000182 (1)
-/* Timer Pin limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000184 (__SILICON_REVISION__ < 5)
-/* PPI TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 5)
-/* PPI packing with Data Length greater than 8 bits (not a meaningful mode) */
-#define ANOMALY_05000186 (__SILICON_REVISION__ < 5)
-/* IMDMA Corrupted Data after a Halt */
-#define ANOMALY_05000187 (1)
-/* IMDMA Restrictions on Descriptor and Buffer Placement in Memory */
-#define ANOMALY_05000188 (__SILICON_REVISION__ < 5)
-/* False Protection Exceptions */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 5)
-/* PPI not functional at core voltage < 1Volt */
-#define ANOMALY_05000190 (1)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 5)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 5)
-/* Failing MMR Accesses When Stalled by Preceding Memory Read */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 5)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ < 5)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Incorrect data read with write-through cache and allocate cache lines on reads only mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 5)
-/* Specific sequence that can cause DMA error or DMA stopping */
-#define ANOMALY_05000205 (__SILICON_REVISION__ < 5)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 5)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 5)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (__SILICON_REVISION__ < 5)
-/* Data Corruption with Cached External Memory and Non-Cached On-Chip L2 Memory */
-#define ANOMALY_05000220 (__SILICON_REVISION__ < 5)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* SPORT data transmit lines are incorrectly driven in multichannel mode */
-#define ANOMALY_05000232 (__SILICON_REVISION__ < 5)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (__SILICON_REVISION__ < 5)
-/* TESTSET operation forces stall on the other core */
-#define ANOMALY_05000248 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ > 2 && __SILICON_REVISION__ < 5)
-/* Exception Not Generated for MMR Accesses in Reserved Region */
-#define ANOMALY_05000251 (__SILICON_REVISION__ < 5)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 3)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (__SILICON_REVISION__ < 5)
-/* IMDMA destination IRQ status must be read prior to using IMDMA */
-#define ANOMALY_05000266 (__SILICON_REVISION__ > 3)
-/* IMDMA may corrupt data under certain conditions */
-#define ANOMALY_05000267 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (1)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Data cache write back to external synchronous memory may be lost */
-#define ANOMALY_05000274 (1)
-/* PPI Timing and Sampling Information Updates */
-#define ANOMALY_05000275 (__SILICON_REVISION__ > 2)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (__SILICON_REVISION__ < 5)
-/* Writes to an I/O data register one SCLK cycle after an edge is detected may clear interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 3)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 5)
-/* False Hardware Error Exception When ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 5)
-/* System MMR Write Is Stalled Indefinitely When Killed in a Particular Stage */
-#define ANOMALY_05000283 (1)
-/* A read will receive incorrect data under certain conditions */
-#define ANOMALY_05000287 (__SILICON_REVISION__ < 5)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 5)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (1)
-/* SSYNCs After Writes To DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (1)
-/* New Feature: Additional Hysteresis on SPORT Input Pins (Not Available On Older Silicon) */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (__SILICON_REVISION__ < 5)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Errors When SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (1)
-/* PPI Is Level-Sensitive on First Transfer */
-#define ANOMALY_05000313 (1)
-/* Killed System MMR Write Completes Erroneously On Next System MMR Access */
-#define ANOMALY_05000315 (1)
-/* PF2 Output Remains Asserted After SPI Master Boot */
-#define ANOMALY_05000320 (__SILICON_REVISION__ > 3)
-/* Erroneous GPIO Flag Pin Operations Under Specific Sequences */
-#define ANOMALY_05000323 (1)
-/* SPORT Secondary Receive Channel Not Functional When Word Length Exceeds 16 Bits */
-#define ANOMALY_05000326 (__SILICON_REVISION__ > 3)
-/* New Feature: 24-Bit SPI Boot Mode Support (Not Available On Older Silicon) */
-#define ANOMALY_05000331 (__SILICON_REVISION__ < 5)
-/* New Feature: Slave SPI Boot Mode Supported (Not Available On Older Silicon) */
-#define ANOMALY_05000332 (__SILICON_REVISION__ < 5)
-/* Flag Data Register Writes One SCLK Cycle After Edge Is Detected May Clear Interrupt Status */
-#define ANOMALY_05000333 (__SILICON_REVISION__ < 5)
-/* New Feature: Additional PPI Frame Sync Sampling Options (Not Available on Older Silicon) */
-#define ANOMALY_05000339 (__SILICON_REVISION__ < 5)
-/* Memory DMA FIFO Causes Throughput Degradation on Writes to External Memory */
-#define ANOMALY_05000343 (__SILICON_REVISION__ < 5)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (1)
-/* Conflicting Column Address Widths Causes SDRAM Errors */
-#define ANOMALY_05000362 (1)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (1)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000311 (0)
-
-#endif
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
deleted file mode 100644
index 3ef9e5f36136..000000000000
--- a/include/asm-blackfin/mach-bf561/bf561.h
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/bf561.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __MACH_BF561_H__
-#define __MACH_BF561_H__
-
-#define SUPPORTED_REVID         0x3
-
-#define OFFSET_(x) ((x) & 0x0000FFFF)
-
-/*some misc defines*/
-#define IMASK_IVG15             0x8000
-#define IMASK_IVG14             0x4000
-#define IMASK_IVG13             0x2000
-#define IMASK_IVG12             0x1000
-
-#define IMASK_IVG11             0x0800
-#define IMASK_IVG10             0x0400
-#define IMASK_IVG9              0x0200
-#define IMASK_IVG8              0x0100
-
-#define IMASK_IVG7              0x0080
-#define IMASK_IVGTMR            0x0040
-#define IMASK_IVGHW             0x0020
-
-/***************************
- * Blackfin Cache setup
- */
-
-
-#define BFIN_ISUBBANKS  4
-#define BFIN_IWAYS              4
-#define BFIN_ILINES             32
-
-#define BFIN_DSUBBANKS  4
-#define BFIN_DWAYS              2
-#define BFIN_DLINES             64
-
-#define WAY0_L                  0x1
-#define WAY1_L                  0x2
-#define WAY01_L                 0x3
-#define WAY2_L                  0x4
-#define WAY02_L                 0x5
-#define WAY12_L                 0x6
-#define WAY012_L                0x7
-
-#define WAY3_L                  0x8
-#define WAY03_L                 0x9
-#define WAY13_L                 0xA
-#define WAY013_L                0xB
-
-#define WAY32_L                 0xC
-#define WAY320_L                0xD
-#define WAY321_L                0xE
-#define WAYALL_L                0xF
-
-#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
-
-/* IAR0 BIT FIELDS */
-#define PLL_WAKEUP_BIT          0xFFFFFFFF
-#define DMA1_ERROR_BIT          0xFFFFFF0F
-#define DMA2_ERROR_BIT          0xFFFFF0FF
-#define IMDMA_ERROR_BIT         0xFFFF0FFF
-#define PPI1_ERROR_BIT          0xFFF0FFFF
-#define PPI2_ERROR_BIT          0xFF0FFFFF
-#define SPORT0_ERROR_BIT        0xF0FFFFFF
-#define SPORT1_ERROR_BIT        0x0FFFFFFF
-/* IAR1 BIT FIELDS */
-#define SPI_ERROR_BIT           0xFFFFFFFF
-#define UART_ERROR_BIT          0xFFFFFF0F
-#define RESERVED_ERROR_BIT      0xFFFFF0FF
-#define DMA1_0_BIT              0xFFFF0FFF
-#define DMA1_1_BIT              0xFFF0FFFF
-#define DMA1_2_BIT              0xFF0FFFFF
-#define DMA1_3_BIT              0xF0FFFFFF
-#define DMA1_4_BIT              0x0FFFFFFF
-/* IAR2 BIT FIELDS */
-#define DMA1_5_BIT              0xFFFFFFFF
-#define DMA1_6_BIT              0xFFFFFF0F
-#define DMA1_7_BIT              0xFFFFF0FF
-#define DMA1_8_BIT              0xFFFF0FFF
-#define DMA1_9_BIT              0xFFF0FFFF
-#define DMA1_10_BIT             0xFF0FFFFF
-#define DMA1_11_BIT             0xF0FFFFFF
-#define DMA2_0_BIT              0x0FFFFFFF
-/* IAR3 BIT FIELDS */
-#define DMA2_1_BIT              0xFFFFFFFF
-#define DMA2_2_BIT              0xFFFFFF0F
-#define DMA2_3_BIT              0xFFFFF0FF
-#define DMA2_4_BIT              0xFFFF0FFF
-#define DMA2_5_BIT              0xFFF0FFFF
-#define DMA2_6_BIT              0xFF0FFFFF
-#define DMA2_7_BIT              0xF0FFFFFF
-#define DMA2_8_BIT              0x0FFFFFFF
-/* IAR4 BIT FIELDS */
-#define DMA2_9_BIT              0xFFFFFFFF
-#define DMA2_10_BIT             0xFFFFFF0F
-#define DMA2_11_BIT             0xFFFFF0FF
-#define TIMER0_BIT              0xFFFF0FFF
-#define TIMER1_BIT              0xFFF0FFFF
-#define TIMER2_BIT              0xFF0FFFFF
-#define TIMER3_BIT              0xF0FFFFFF
-#define TIMER4_BIT              0x0FFFFFFF
-/* IAR5 BIT FIELDS */
-#define TIMER5_BIT              0xFFFFFFFF
-#define TIMER6_BIT              0xFFFFFF0F
-#define TIMER7_BIT              0xFFFFF0FF
-#define TIMER8_BIT              0xFFFF0FFF
-#define TIMER9_BIT              0xFFF0FFFF
-#define TIMER10_BIT             0xFF0FFFFF
-#define TIMER11_BIT             0xF0FFFFFF
-#define PROG0_INTA_BIT          0x0FFFFFFF
-/* IAR6 BIT FIELDS */
-#define PROG0_INTB_BIT          0xFFFFFFFF
-#define PROG1_INTA_BIT          0xFFFFFF0F
-#define PROG1_INTB_BIT          0xFFFFF0FF
-#define PROG2_INTA_BIT          0xFFFF0FFF
-#define PROG2_INTB_BIT          0xFFF0FFFF
-#define DMA1_WRRD0_BIT          0xFF0FFFFF
-#define DMA1_WRRD1_BIT          0xF0FFFFFF
-#define DMA2_WRRD0_BIT          0x0FFFFFFF
-/* IAR7 BIT FIELDS */
-#define DMA2_WRRD1_BIT          0xFFFFFFFF
-#define IMDMA_WRRD0_BIT         0xFFFFFF0F
-#define IMDMA_WRRD1_BIT         0xFFFFF0FF
-#define WATCH_BIT               0xFFFF0FFF
-#define RESERVED_1_BIT          0xFFF0FFFF
-#define RESERVED_2_BIT          0xFF0FFFFF
-#define SUPPLE_0_BIT            0xF0FFFFFF
-#define SUPPLE_1_BIT            0x0FFFFFFF
-
-/* Miscellaneous Values */
-
-/****************************** EBIU Settings ********************************/
-#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
-#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
-
-#if defined(CONFIG_C_AMBEN_ALL)
-#define V_AMBEN AMBEN_ALL
-#elif defined(CONFIG_C_AMBEN)
-#define V_AMBEN 0x0
-#elif defined(CONFIG_C_AMBEN_B0)
-#define V_AMBEN AMBEN_B0
-#elif defined(CONFIG_C_AMBEN_B0_B1)
-#define V_AMBEN AMBEN_B0_B1
-#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
-#define V_AMBEN AMBEN_B0_B1_B2
-#endif
-
-#ifdef CONFIG_C_AMCKEN
-#define V_AMCKEN AMCKEN
-#else
-#define V_AMCKEN 0x0
-#endif
-
-#ifdef CONFIG_C_B0PEN
-#define V_B0PEN 0x10
-#else
-#define V_B0PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B1PEN
-#define V_B1PEN 0x20
-#else
-#define V_B1PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B2PEN
-#define V_B2PEN 0x40
-#else
-#define V_B2PEN 0x00
-#endif
-
-#ifdef CONFIG_C_B3PEN
-#define V_B3PEN 0x80
-#else
-#define V_B3PEN 0x00
-#endif
-
-#ifdef CONFIG_C_CDPRIO
-#define V_CDPRIO 0x100
-#else
-#define V_CDPRIO 0x0
-#endif
-
-#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
-
-#ifdef CONFIG_BF561
-#define CPU "BF561"
-#define CPUID 0x027bb000
-#endif
-#ifndef CPU
-#define CPU "UNKNOWN"
-#define CPUID 0x0
-#endif
-
-#endif                          /* __MACH_BF561_H__  */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
deleted file mode 100644
index 8aa02780e642..000000000000
--- a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
+++ /dev/null
@@ -1,164 +0,0 @@
-/*
- * file:        include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
- * based on:
- * author:
- *
- * created:
- * description:
- *      blackfin serial driver head file
- * rev:
- *
- * modified:
- *
- *
- * bugs:         enter bugs at http://blackfin.uclinux.org/
- *
- * this program is free software; you can redistribute it and/or modify
- * it under the terms of the gnu general public license as published by
- * the free software foundation; either version 2, or (at your option)
- * any later version.
- *
- * this program is distributed in the hope that it will be useful,
- * but without any warranty; without even the implied warranty of
- * merchantability or fitness for a particular purpose.  see the
- * gnu general public license for more details.
- *
- * you should have received a copy of the gnu general public license
- * along with this program; see the file copying.
- * if not, write to the free software foundation,
- * 59 temple place - suite 330, boston, ma 02111-1307, usa.
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
-#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
-#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
-#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
-#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
-#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
-#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
-
-#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
-#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
-#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
-#define UART_SET_IER(uart,v)    UART_PUT_IER(uart, UART_GET_IER(uart) | (v))
-#define UART_CLEAR_IER(uart,v)  UART_PUT_IER(uart, UART_GET_IER(uart) & ~(v))
-#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
-#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
-#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
-
-#define UART_SET_DLAB(uart)     do { UART_PUT_LCR(uart, UART_GET_LCR(uart) | DLAB); SSYNC(); } while (0)
-#define UART_CLEAR_DLAB(uart)   do { UART_PUT_LCR(uart, UART_GET_LCR(uart) & ~DLAB); SSYNC(); } while (0)
-
-#define UART_GET_CTS(x) gpio_get_value(x->cts_pin)
-#define UART_SET_RTS(x) gpio_set_value(x->rts_pin, 1)
-#define UART_CLEAR_RTS(x) gpio_set_value(x->rts_pin, 0)
-#define UART_ENABLE_INTS(x, v) UART_PUT_IER(x, v)
-#define UART_DISABLE_INTS(x) UART_PUT_IER(x, 0)
-
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-# define CONFIG_SERIAL_BFIN_CTSRTS
-# ifndef CONFIG_UART0_CTS_PIN
-#  define CONFIG_UART0_CTS_PIN -1
-# endif
-# ifndef CONFIG_UART0_RTS_PIN
-#  define CONFIG_UART0_RTS_PIN -1
-# endif
-#endif
-
-struct bfin_serial_port {
-        struct uart_port        port;
-        unsigned int            old_status;
-        unsigned int lsr;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        int                     tx_done;
-        int                     tx_count;
-        struct circ_buf         rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-        struct work_struct      tx_dma_workqueue;
-#else
-# if ANOMALY_05000230
-        unsigned int anomaly_threshold;
-# endif
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        struct timer_list       cts_timer;
-        int                     cts_pin;
-        int                     rts_pin;
-#endif
-};
-
-/* The hardware clears the LSR bits upon read, so we need to cache
- * some of the more fun bits in software so they don't get lost
- * when checking the LSR in other code paths (TX).
- */
-static inline unsigned int UART_GET_LSR(struct bfin_serial_port *uart)
-{
-        unsigned int lsr = bfin_read16(uart->port.membase + OFFSET_LSR);
-        uart->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | uart->lsr;
-}
-
-static inline void UART_CLEAR_LSR(struct bfin_serial_port *uart)
-{
-        uart->lsr = 0;
-        bfin_write16(uart->port.membase + OFFSET_LSR, -1);
-}
-
-struct bfin_serial_port bfin_serial_ports[BFIN_UART_NR_PORTS];
-struct bfin_serial_res {
-        unsigned long   uart_base_addr;
-        int             uart_irq;
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        unsigned int    uart_tx_dma_channel;
-        unsigned int    uart_rx_dma_channel;
-#endif
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        int             uart_cts_pin;
-        int             uart_rts_pin;
-#endif
-};
-
-struct bfin_serial_res bfin_serial_resource[] = {
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-#ifdef CONFIG_SERIAL_BFIN_DMA
-        CH_UART_TX,
-        CH_UART_RX,
-#endif
-#ifdef CONFIG_BFIN_UART0_CTSRTS
-        CONFIG_UART0_CTS_PIN,
-        CONFIG_UART0_RTS_PIN,
-#endif
-        }
-};
-
-#define DRIVER_NAME "bfin-uart"
-
-int nr_ports = BFIN_UART_NR_PORTS;
-static void bfin_serial_hw_init(struct bfin_serial_port *uart)
-{
-
-#ifdef CONFIG_SERIAL_BFIN_UART0
-        peripheral_request(P_UART0_TX, DRIVER_NAME);
-        peripheral_request(P_UART0_RX, DRIVER_NAME);
-#endif
-
-#ifdef CONFIG_SERIAL_BFIN_CTSRTS
-        if (uart->cts_pin >= 0) {
-                gpio_request(uart->cts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->cts_pin);
-        }
-        if (uart->rts_pin >= 0) {
-                gpio_request(uart->rts_pin, DRIVER_NAME);
-                gpio_direction_input(uart->rts_pin, 0);
-        }
-#endif
-}
diff --git a/include/asm-blackfin/mach-bf561/bfin_sir.h b/include/asm-blackfin/mach-bf561/bfin_sir.h
deleted file mode 100644
index 9bb87e9e2e9b..000000000000
--- a/include/asm-blackfin/mach-bf561/bfin_sir.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Blackfin Infra-red Driver
- *
- * Copyright 2006-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- *
- */
-
-#include <linux/serial.h>
-#include <asm/dma.h>
-#include <asm/portmux.h>
-
-#define SIR_UART_GET_CHAR(port)   bfin_read16((port)->membase + OFFSET_RBR)
-#define SIR_UART_GET_DLL(port)    bfin_read16((port)->membase + OFFSET_DLL)
-#define SIR_UART_GET_IER(port)    bfin_read16((port)->membase + OFFSET_IER)
-#define SIR_UART_GET_DLH(port)    bfin_read16((port)->membase + OFFSET_DLH)
-#define SIR_UART_GET_IIR(port)    bfin_read16((port)->membase + OFFSET_IIR)
-#define SIR_UART_GET_LCR(port)    bfin_read16((port)->membase + OFFSET_LCR)
-#define SIR_UART_GET_GCTL(port)   bfin_read16((port)->membase + OFFSET_GCTL)
-
-#define SIR_UART_PUT_CHAR(port, v) bfin_write16(((port)->membase + OFFSET_THR), v)
-#define SIR_UART_PUT_DLL(port, v)  bfin_write16(((port)->membase + OFFSET_DLL), v)
-#define SIR_UART_PUT_IER(port, v)  bfin_write16(((port)->membase + OFFSET_IER), v)
-#define SIR_UART_PUT_DLH(port, v)  bfin_write16(((port)->membase + OFFSET_DLH), v)
-#define SIR_UART_PUT_LCR(port, v)  bfin_write16(((port)->membase + OFFSET_LCR), v)
-#define SIR_UART_PUT_GCTL(port, v) bfin_write16(((port)->membase + OFFSET_GCTL), v)
-
-#ifdef CONFIG_SIR_BFIN_DMA
-struct dma_rx_buf {
-        char *buf;
-        int head;
-        int tail;
-        };
-#endif /* CONFIG_SIR_BFIN_DMA */
-
-struct bfin_sir_port {
-        unsigned char __iomem   *membase;
-        unsigned int            irq;
-        unsigned int            lsr;
-        unsigned long           clk;
-        struct net_device       *dev;
-#ifdef CONFIG_SIR_BFIN_DMA
-        int                     tx_done;
-        struct dma_rx_buf       rx_dma_buf;
-        struct timer_list       rx_dma_timer;
-        int                     rx_dma_nrows;
-#endif /* CONFIG_SIR_BFIN_DMA */
-        unsigned int            tx_dma_channel;
-        unsigned int            rx_dma_channel;
-};
-
-struct bfin_sir_port sir_ports[BFIN_UART_NR_PORTS];
-
-struct bfin_sir_port_res {
-        unsigned long   base_addr;
-        int             irq;
-        unsigned int    rx_dma_channel;
-        unsigned int    tx_dma_channel;
-};
-
-struct bfin_sir_port_res bfin_sir_port_resource[] = {
-#ifdef CONFIG_BFIN_SIR0
-        {
-        0xFFC00400,
-        IRQ_UART_RX,
-        CH_UART_RX,
-        CH_UART_TX,
-        },
-#endif
-};
-
-int nr_sirs = ARRAY_SIZE(bfin_sir_port_resource);
-
-struct bfin_sir_self {
-        struct bfin_sir_port    *sir_port;
-        spinlock_t              lock;
-        unsigned int            open;
-        int                     speed;
-        int                     newspeed;
-
-        struct sk_buff          *txskb;
-        struct sk_buff          *rxskb;
-        struct net_device_stats stats;
-        struct device           *dev;
-        struct irlap_cb         *irlap;
-        struct qos_info         qos;
-
-        iobuff_t                tx_buff;
-        iobuff_t                rx_buff;
-
-        struct work_struct      work;
-        int                     mtt;
-};
-
-static inline unsigned int SIR_UART_GET_LSR(struct bfin_sir_port *port)
-{
-        unsigned int lsr = bfin_read16(port->membase + OFFSET_LSR);
-        port->lsr |= (lsr & (BI|FE|PE|OE));
-        return lsr | port->lsr;
-}
-
-static inline void SIR_UART_CLEAR_LSR(struct bfin_sir_port *port)
-{
-        port->lsr = 0;
-        bfin_read16(port->membase + OFFSET_LSR);
-}
-
-#define DRIVER_NAME "bfin_sir"
-
-static int bfin_sir_hw_init(void)
-{
-        int ret = -ENODEV;
-#ifdef CONFIG_BFIN_SIR0
-        ret = peripheral_request(P_UART0_TX, DRIVER_NAME);
-        if (ret)
-                return ret;
-        ret = peripheral_request(P_UART0_RX, DRIVER_NAME);
-        if (ret)
-                return ret;
-#endif
-        return ret;
-}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
deleted file mode 100644
index 0ea8666e6764..000000000000
--- a/include/asm-blackfin/mach-bf561/blackfin.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/blackfin.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _MACH_BLACKFIN_H_
-#define _MACH_BLACKFIN_H_
-
-#define BF561_FAMILY
-
-#include "bf561.h"
-#include "mem_map.h"
-#include "defBF561.h"
-#include "anomaly.h"
-
-#if !defined(__ASSEMBLY__)
-#include "cdefBF561.h"
-#endif
-
-#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
-#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
-#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
-#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
-#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
-#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
-
-#define SIC_IWR0 SICA_IWR0
-#define SIC_IWR1 SICA_IWR1
-#define SIC_IAR0 SICA_IAR0
-#define bfin_write_SIC_IMASK0 bfin_write_SICA_IMASK0
-#define bfin_write_SIC_IMASK1 bfin_write_SICA_IMASK1
-#define bfin_write_SIC_IWR0   bfin_write_SICA_IWR0
-#define bfin_write_SIC_IWR1   bfin_write_SICA_IWR1
-
-#define bfin_read_SIC_IMASK0 bfin_read_SICA_IMASK0
-#define bfin_read_SIC_IMASK1 bfin_read_SICA_IMASK1
-#define bfin_read_SIC_IWR0   bfin_read_SICA_IWR0
-#define bfin_read_SIC_IWR1   bfin_read_SICA_IWR1
-#define bfin_read_SIC_ISR0   bfin_read_SICA_ISR0
-#define bfin_read_SIC_ISR1   bfin_read_SICA_ISR1
-
-#define bfin_read_SIC_IMASK(x)          bfin_read32(SICA_IMASK0 + (x << 2))
-#define bfin_write_SIC_IMASK(x, val)    bfin_write32((SICA_IMASK0 + (x << 2)), val)
-#define bfin_read_SIC_ISR(x)            bfin_read32(SICA_ISR0 + (x << 2))
-#define bfin_write_SIC_ISR(x, val)      bfin_write32((SICA_ISR0 + (x << 2)), val)
-
-#define BFIN_UART_NR_PORTS      1
-
-#define OFFSET_THR              0x00    /* Transmit Holding register            */
-#define OFFSET_RBR              0x00    /* Receive Buffer register              */
-#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
-#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
-#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
-#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
-#define OFFSET_LCR              0x0C    /* Line Control Register                */
-#define OFFSET_MCR              0x10    /* Modem Control Register               */
-#define OFFSET_LSR              0x14    /* Line Status Register                 */
-#define OFFSET_MSR              0x18    /* Modem Status Register                */
-#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
-#define OFFSET_GCTL             0x24    /* Global Control Register              */
-
-#endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
deleted file mode 100644
index b07ffccd66dd..000000000000
--- a/include/asm-blackfin/mach-bf561/cdefBF561.h
+++ /dev/null
@@ -1,1579 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/cdefBF561.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:  C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _CDEF_BF561_H
-#define _CDEF_BF561_H
-
-#include <asm/blackfin.h>
-
-/* include all Core registers and bit definitions */
-#include "defBF561.h"
-
-/*include core specific register pointer definitions*/
-#include <asm/mach-common/cdef_LPBlackfin.h>
-
-#include <asm/system.h>
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
-/* Writing to PLL_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_PLL_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_PLL_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(PLL_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
-#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
-/* Writing to VR_CTL initiates a PLL relock sequence. */
-static __inline__ void bfin_write_VR_CTL(unsigned int val)
-{
-        unsigned long flags, iwr0, iwr1;
-
-        if (val == bfin_read_VR_CTL())
-                return;
-
-        local_irq_save(flags);
-        /* Enable the PLL Wakeup bit in SIC IWR */
-        iwr0 = bfin_read32(SICA_IWR0);
-        iwr1 = bfin_read32(SICA_IWR1);
-        /* Only allow PPL Wakeup) */
-        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
-        bfin_write32(SICA_IWR1, 0);
-
-        bfin_write16(VR_CTL, val);
-        SSYNC();
-        asm("IDLE;");
-
-        bfin_write32(SICA_IWR0, iwr0);
-        bfin_write32(SICA_IWR1, iwr1);
-        local_irq_restore(flags);
-}
-#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
-#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
-#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define bfin_read_SWRST()                    bfin_read_SICA_SWRST()
-#define bfin_write_SWRST(val)                bfin_write_SICA_SWRST(val)
-#define bfin_read_SYSCR()                    bfin_read_SICA_SYSCR()
-#define bfin_write_SYSCR(val)                bfin_write_SICA_SYSCR(val)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define bfin_read_SICA_SWRST()               bfin_read16(SICA_SWRST)
-#define bfin_write_SICA_SWRST(val)           bfin_write16(SICA_SWRST,val)
-#define bfin_read_SICA_SYSCR()               bfin_read16(SICA_SYSCR)
-#define bfin_write_SICA_SYSCR(val)           bfin_write16(SICA_SYSCR,val)
-#define bfin_read_SICA_RVECT()               bfin_read16(SICA_RVECT)
-#define bfin_write_SICA_RVECT(val)           bfin_write16(SICA_RVECT,val)
-#define bfin_read_SICA_IMASK()               bfin_read32(SICA_IMASK)
-#define bfin_write_SICA_IMASK(val)           bfin_write32(SICA_IMASK,val)
-#define bfin_read_SICA_IMASK0()              bfin_read32(SICA_IMASK0)
-#define bfin_write_SICA_IMASK0(val)          bfin_write32(SICA_IMASK0,val)
-#define bfin_read_SICA_IMASK1()              bfin_read32(SICA_IMASK1)
-#define bfin_write_SICA_IMASK1(val)          bfin_write32(SICA_IMASK1,val)
-#define bfin_read_SICA_IAR0()                bfin_read32(SICA_IAR0)
-#define bfin_write_SICA_IAR0(val)            bfin_write32(SICA_IAR0,val)
-#define bfin_read_SICA_IAR1()                bfin_read32(SICA_IAR1)
-#define bfin_write_SICA_IAR1(val)            bfin_write32(SICA_IAR1,val)
-#define bfin_read_SICA_IAR2()                bfin_read32(SICA_IAR2)
-#define bfin_write_SICA_IAR2(val)            bfin_write32(SICA_IAR2,val)
-#define bfin_read_SICA_IAR3()                bfin_read32(SICA_IAR3)
-#define bfin_write_SICA_IAR3(val)            bfin_write32(SICA_IAR3,val)
-#define bfin_read_SICA_IAR4()                bfin_read32(SICA_IAR4)
-#define bfin_write_SICA_IAR4(val)            bfin_write32(SICA_IAR4,val)
-#define bfin_read_SICA_IAR5()                bfin_read32(SICA_IAR5)
-#define bfin_write_SICA_IAR5(val)            bfin_write32(SICA_IAR5,val)
-#define bfin_read_SICA_IAR6()                bfin_read32(SICA_IAR6)
-#define bfin_write_SICA_IAR6(val)            bfin_write32(SICA_IAR6,val)
-#define bfin_read_SICA_IAR7()                bfin_read32(SICA_IAR7)
-#define bfin_write_SICA_IAR7(val)            bfin_write32(SICA_IAR7,val)
-#define bfin_read_SICA_ISR0()                bfin_read32(SICA_ISR0)
-#define bfin_write_SICA_ISR0(val)            bfin_write32(SICA_ISR0,val)
-#define bfin_read_SICA_ISR1()                bfin_read32(SICA_ISR1)
-#define bfin_write_SICA_ISR1(val)            bfin_write32(SICA_ISR1,val)
-#define bfin_read_SICA_IWR0()                bfin_read32(SICA_IWR0)
-#define bfin_write_SICA_IWR0(val)            bfin_write32(SICA_IWR0,val)
-#define bfin_read_SICA_IWR1()                bfin_read32(SICA_IWR1)
-#define bfin_write_SICA_IWR1(val)            bfin_write32(SICA_IWR1,val)
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define bfin_read_SICB_SWRST()               bfin_read16(SICB_SWRST)
-#define bfin_write_SICB_SWRST(val)           bfin_write16(SICB_SWRST,val)
-#define bfin_read_SICB_SYSCR()               bfin_read16(SICB_SYSCR)
-#define bfin_write_SICB_SYSCR(val)           bfin_write16(SICB_SYSCR,val)
-#define bfin_read_SICB_RVECT()               bfin_read16(SICB_RVECT)
-#define bfin_write_SICB_RVECT(val)           bfin_write16(SICB_RVECT,val)
-#define bfin_read_SICB_IMASK0()              bfin_read32(SICB_IMASK0)
-#define bfin_write_SICB_IMASK0(val)          bfin_write32(SICB_IMASK0,val)
-#define bfin_read_SICB_IMASK1()              bfin_read32(SICB_IMASK1)
-#define bfin_write_SICB_IMASK1(val)          bfin_write32(SICB_IMASK1,val)
-#define bfin_read_SICB_IAR0()                bfin_read32(SICB_IAR0)
-#define bfin_write_SICB_IAR0(val)            bfin_write32(SICB_IAR0,val)
-#define bfin_read_SICB_IAR1()                bfin_read32(SICB_IAR1)
-#define bfin_write_SICB_IAR1(val)            bfin_write32(SICB_IAR1,val)
-#define bfin_read_SICB_IAR2()                bfin_read32(SICB_IAR2)
-#define bfin_write_SICB_IAR2(val)            bfin_write32(SICB_IAR2,val)
-#define bfin_read_SICB_IAR3()                bfin_read32(SICB_IAR3)
-#define bfin_write_SICB_IAR3(val)            bfin_write32(SICB_IAR3,val)
-#define bfin_read_SICB_IAR4()                bfin_read32(SICB_IAR4)
-#define bfin_write_SICB_IAR4(val)            bfin_write32(SICB_IAR4,val)
-#define bfin_read_SICB_IAR5()                bfin_read32(SICB_IAR5)
-#define bfin_write_SICB_IAR5(val)            bfin_write32(SICB_IAR5,val)
-#define bfin_read_SICB_IAR6()                bfin_read32(SICB_IAR6)
-#define bfin_write_SICB_IAR6(val)            bfin_write32(SICB_IAR6,val)
-#define bfin_read_SICB_IAR7()                bfin_read32(SICB_IAR7)
-#define bfin_write_SICB_IAR7(val)            bfin_write32(SICB_IAR7,val)
-#define bfin_read_SICB_ISR0()                bfin_read32(SICB_ISR0)
-#define bfin_write_SICB_ISR0(val)            bfin_write32(SICB_ISR0,val)
-#define bfin_read_SICB_ISR1()                bfin_read32(SICB_ISR1)
-#define bfin_write_SICB_ISR1(val)            bfin_write32(SICB_ISR1,val)
-#define bfin_read_SICB_IWR0()                bfin_read32(SICB_IWR0)
-#define bfin_write_SICB_IWR0(val)            bfin_write32(SICB_IWR0,val)
-#define bfin_read_SICB_IWR1()                bfin_read32(SICB_IWR1)
-#define bfin_write_SICB_IWR1(val)            bfin_write32(SICB_IWR1,val)
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define bfin_read_WDOGA_CTL()                bfin_read16(WDOGA_CTL)
-#define bfin_write_WDOGA_CTL(val)            bfin_write16(WDOGA_CTL,val)
-#define bfin_read_WDOGA_CNT()                bfin_read32(WDOGA_CNT)
-#define bfin_write_WDOGA_CNT(val)            bfin_write32(WDOGA_CNT,val)
-#define bfin_read_WDOGA_STAT()               bfin_read32(WDOGA_STAT)
-#define bfin_write_WDOGA_STAT(val)           bfin_write32(WDOGA_STAT,val)
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define bfin_read_WDOGB_CTL()                bfin_read16(WDOGB_CTL)
-#define bfin_write_WDOGB_CTL(val)            bfin_write16(WDOGB_CTL,val)
-#define bfin_read_WDOGB_CNT()                bfin_read32(WDOGB_CNT)
-#define bfin_write_WDOGB_CNT(val)            bfin_write32(WDOGB_CNT,val)
-#define bfin_read_WDOGB_STAT()               bfin_read32(WDOGB_STAT)
-#define bfin_write_WDOGB_STAT(val)           bfin_write32(WDOGB_STAT,val)
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
-#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
-#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
-#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
-#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
-#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
-#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
-#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
-#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
-#define bfin_read_UART_MSR()                 bfin_read16(UART_MSR)
-#define bfin_write_UART_MSR(val)             bfin_write16(UART_MSR,val)
-#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
-#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
-#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
-#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
-#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
-#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
-#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
-#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
-#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
-#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
-#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
-#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
-#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
-#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
-#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
-#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
-#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
-#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
-#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
-#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
-#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
-#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
-#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
-#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
-#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
-#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
-#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
-#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
-#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
-#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
-#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
-#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
-#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
-#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
-#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
-#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
-#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
-#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
-#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define bfin_read_TMRS8_ENABLE()             bfin_read16(TMRS8_ENABLE)
-#define bfin_write_TMRS8_ENABLE(val)         bfin_write16(TMRS8_ENABLE,val)
-#define bfin_read_TMRS8_DISABLE()            bfin_read16(TMRS8_DISABLE)
-#define bfin_write_TMRS8_DISABLE(val)        bfin_write16(TMRS8_DISABLE,val)
-#define bfin_read_TMRS8_STATUS()             bfin_read32(TMRS8_STATUS)
-#define bfin_write_TMRS8_STATUS(val)         bfin_write32(TMRS8_STATUS,val)
-#define bfin_read_TIMER8_CONFIG()            bfin_read16(TIMER8_CONFIG)
-#define bfin_write_TIMER8_CONFIG(val)        bfin_write16(TIMER8_CONFIG,val)
-#define bfin_read_TIMER8_COUNTER()           bfin_read32(TIMER8_COUNTER)
-#define bfin_write_TIMER8_COUNTER(val)       bfin_write32(TIMER8_COUNTER,val)
-#define bfin_read_TIMER8_PERIOD()            bfin_read32(TIMER8_PERIOD)
-#define bfin_write_TIMER8_PERIOD(val)        bfin_write32(TIMER8_PERIOD,val)
-#define bfin_read_TIMER8_WIDTH()             bfin_read32(TIMER8_WIDTH)
-#define bfin_write_TIMER8_WIDTH(val)         bfin_write32(TIMER8_WIDTH,val)
-#define bfin_read_TIMER9_CONFIG()            bfin_read16(TIMER9_CONFIG)
-#define bfin_write_TIMER9_CONFIG(val)        bfin_write16(TIMER9_CONFIG,val)
-#define bfin_read_TIMER9_COUNTER()           bfin_read32(TIMER9_COUNTER)
-#define bfin_write_TIMER9_COUNTER(val)       bfin_write32(TIMER9_COUNTER,val)
-#define bfin_read_TIMER9_PERIOD()            bfin_read32(TIMER9_PERIOD)
-#define bfin_write_TIMER9_PERIOD(val)        bfin_write32(TIMER9_PERIOD,val)
-#define bfin_read_TIMER9_WIDTH()             bfin_read32(TIMER9_WIDTH)
-#define bfin_write_TIMER9_WIDTH(val)         bfin_write32(TIMER9_WIDTH,val)
-#define bfin_read_TIMER10_CONFIG()           bfin_read16(TIMER10_CONFIG)
-#define bfin_write_TIMER10_CONFIG(val)       bfin_write16(TIMER10_CONFIG,val)
-#define bfin_read_TIMER10_COUNTER()          bfin_read32(TIMER10_COUNTER)
-#define bfin_write_TIMER10_COUNTER(val)      bfin_write32(TIMER10_COUNTER,val)
-#define bfin_read_TIMER10_PERIOD()           bfin_read32(TIMER10_PERIOD)
-#define bfin_write_TIMER10_PERIOD(val)       bfin_write32(TIMER10_PERIOD,val)
-#define bfin_read_TIMER10_WIDTH()            bfin_read32(TIMER10_WIDTH)
-#define bfin_write_TIMER10_WIDTH(val)        bfin_write32(TIMER10_WIDTH,val)
-#define bfin_read_TIMER11_CONFIG()           bfin_read16(TIMER11_CONFIG)
-#define bfin_write_TIMER11_CONFIG(val)       bfin_write16(TIMER11_CONFIG,val)
-#define bfin_read_TIMER11_COUNTER()          bfin_read32(TIMER11_COUNTER)
-#define bfin_write_TIMER11_COUNTER(val)      bfin_write32(TIMER11_COUNTER,val)
-#define bfin_read_TIMER11_PERIOD()           bfin_read32(TIMER11_PERIOD)
-#define bfin_write_TIMER11_PERIOD(val)       bfin_write32(TIMER11_PERIOD,val)
-#define bfin_read_TIMER11_WIDTH()            bfin_read32(TIMER11_WIDTH)
-#define bfin_write_TIMER11_WIDTH(val)        bfin_write32(TIMER11_WIDTH,val)
-#define bfin_read_TMRS4_ENABLE()             bfin_read16(TMRS4_ENABLE)
-#define bfin_write_TMRS4_ENABLE(val)         bfin_write16(TMRS4_ENABLE,val)
-#define bfin_read_TMRS4_DISABLE()            bfin_read16(TMRS4_DISABLE)
-#define bfin_write_TMRS4_DISABLE(val)        bfin_write16(TMRS4_DISABLE,val)
-#define bfin_read_TMRS4_STATUS()             bfin_read32(TMRS4_STATUS)
-#define bfin_write_TMRS4_STATUS(val)         bfin_write32(TMRS4_STATUS,val)
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define bfin_read_FIO0_FLAG_D()              bfin_read16(FIO0_FLAG_D)
-#define bfin_write_FIO0_FLAG_D(val)          bfin_write16(FIO0_FLAG_D,val)
-#define bfin_read_FIO0_FLAG_C()              bfin_read16(FIO0_FLAG_C)
-#define bfin_write_FIO0_FLAG_C(val)          bfin_write16(FIO0_FLAG_C,val)
-#define bfin_read_FIO0_FLAG_S()              bfin_read16(FIO0_FLAG_S)
-#define bfin_write_FIO0_FLAG_S(val)          bfin_write16(FIO0_FLAG_S,val)
-#define bfin_read_FIO0_FLAG_T()              bfin_read16(FIO0_FLAG_T)
-#define bfin_write_FIO0_FLAG_T(val)          bfin_write16(FIO0_FLAG_T,val)
-#define bfin_read_FIO0_MASKA_D()             bfin_read16(FIO0_MASKA_D)
-#define bfin_write_FIO0_MASKA_D(val)         bfin_write16(FIO0_MASKA_D,val)
-#define bfin_read_FIO0_MASKA_C()             bfin_read16(FIO0_MASKA_C)
-#define bfin_write_FIO0_MASKA_C(val)         bfin_write16(FIO0_MASKA_C,val)
-#define bfin_read_FIO0_MASKA_S()             bfin_read16(FIO0_MASKA_S)
-#define bfin_write_FIO0_MASKA_S(val)         bfin_write16(FIO0_MASKA_S,val)
-#define bfin_read_FIO0_MASKA_T()             bfin_read16(FIO0_MASKA_T)
-#define bfin_write_FIO0_MASKA_T(val)         bfin_write16(FIO0_MASKA_T,val)
-#define bfin_read_FIO0_MASKB_D()             bfin_read16(FIO0_MASKB_D)
-#define bfin_write_FIO0_MASKB_D(val)         bfin_write16(FIO0_MASKB_D,val)
-#define bfin_read_FIO0_MASKB_C()             bfin_read16(FIO0_MASKB_C)
-#define bfin_write_FIO0_MASKB_C(val)         bfin_write16(FIO0_MASKB_C,val)
-#define bfin_read_FIO0_MASKB_S()             bfin_read16(FIO0_MASKB_S)
-#define bfin_write_FIO0_MASKB_S(val)         bfin_write16(FIO0_MASKB_S,val)
-#define bfin_read_FIO0_MASKB_T()             bfin_read16(FIO0_MASKB_T)
-#define bfin_write_FIO0_MASKB_T(val)         bfin_write16(FIO0_MASKB_T,val)
-#define bfin_read_FIO0_DIR()                 bfin_read16(FIO0_DIR)
-#define bfin_write_FIO0_DIR(val)             bfin_write16(FIO0_DIR,val)
-#define bfin_read_FIO0_POLAR()               bfin_read16(FIO0_POLAR)
-#define bfin_write_FIO0_POLAR(val)           bfin_write16(FIO0_POLAR,val)
-#define bfin_read_FIO0_EDGE()                bfin_read16(FIO0_EDGE)
-#define bfin_write_FIO0_EDGE(val)            bfin_write16(FIO0_EDGE,val)
-#define bfin_read_FIO0_BOTH()                bfin_read16(FIO0_BOTH)
-#define bfin_write_FIO0_BOTH(val)            bfin_write16(FIO0_BOTH,val)
-#define bfin_read_FIO0_INEN()                bfin_read16(FIO0_INEN)
-#define bfin_write_FIO0_INEN(val)            bfin_write16(FIO0_INEN,val)
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define bfin_read_FIO1_FLAG_D()              bfin_read16(FIO1_FLAG_D)
-#define bfin_write_FIO1_FLAG_D(val)          bfin_write16(FIO1_FLAG_D,val)
-#define bfin_read_FIO1_FLAG_C()              bfin_read16(FIO1_FLAG_C)
-#define bfin_write_FIO1_FLAG_C(val)          bfin_write16(FIO1_FLAG_C,val)
-#define bfin_read_FIO1_FLAG_S()              bfin_read16(FIO1_FLAG_S)
-#define bfin_write_FIO1_FLAG_S(val)          bfin_write16(FIO1_FLAG_S,val)
-#define bfin_read_FIO1_FLAG_T()              bfin_read16(FIO1_FLAG_T)
-#define bfin_write_FIO1_FLAG_T(val)          bfin_write16(FIO1_FLAG_T,val)
-#define bfin_read_FIO1_MASKA_D()             bfin_read16(FIO1_MASKA_D)
-#define bfin_write_FIO1_MASKA_D(val)         bfin_write16(FIO1_MASKA_D,val)
-#define bfin_read_FIO1_MASKA_C()             bfin_read16(FIO1_MASKA_C)
-#define bfin_write_FIO1_MASKA_C(val)         bfin_write16(FIO1_MASKA_C,val)
-#define bfin_read_FIO1_MASKA_S()             bfin_read16(FIO1_MASKA_S)
-#define bfin_write_FIO1_MASKA_S(val)         bfin_write16(FIO1_MASKA_S,val)
-#define bfin_read_FIO1_MASKA_T()             bfin_read16(FIO1_MASKA_T)
-#define bfin_write_FIO1_MASKA_T(val)         bfin_write16(FIO1_MASKA_T,val)
-#define bfin_read_FIO1_MASKB_D()             bfin_read16(FIO1_MASKB_D)
-#define bfin_write_FIO1_MASKB_D(val)         bfin_write16(FIO1_MASKB_D,val)
-#define bfin_read_FIO1_MASKB_C()             bfin_read16(FIO1_MASKB_C)
-#define bfin_write_FIO1_MASKB_C(val)         bfin_write16(FIO1_MASKB_C,val)
-#define bfin_read_FIO1_MASKB_S()             bfin_read16(FIO1_MASKB_S)
-#define bfin_write_FIO1_MASKB_S(val)         bfin_write16(FIO1_MASKB_S,val)
-#define bfin_read_FIO1_MASKB_T()             bfin_read16(FIO1_MASKB_T)
-#define bfin_write_FIO1_MASKB_T(val)         bfin_write16(FIO1_MASKB_T,val)
-#define bfin_read_FIO1_DIR()                 bfin_read16(FIO1_DIR)
-#define bfin_write_FIO1_DIR(val)             bfin_write16(FIO1_DIR,val)
-#define bfin_read_FIO1_POLAR()               bfin_read16(FIO1_POLAR)
-#define bfin_write_FIO1_POLAR(val)           bfin_write16(FIO1_POLAR,val)
-#define bfin_read_FIO1_EDGE()                bfin_read16(FIO1_EDGE)
-#define bfin_write_FIO1_EDGE(val)            bfin_write16(FIO1_EDGE,val)
-#define bfin_read_FIO1_BOTH()                bfin_read16(FIO1_BOTH)
-#define bfin_write_FIO1_BOTH(val)            bfin_write16(FIO1_BOTH,val)
-#define bfin_read_FIO1_INEN()                bfin_read16(FIO1_INEN)
-#define bfin_write_FIO1_INEN(val)            bfin_write16(FIO1_INEN,val)
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define bfin_read_FIO2_FLAG_D()              bfin_read16(FIO2_FLAG_D)
-#define bfin_write_FIO2_FLAG_D(val)          bfin_write16(FIO2_FLAG_D,val)
-#define bfin_read_FIO2_FLAG_C()              bfin_read16(FIO2_FLAG_C)
-#define bfin_write_FIO2_FLAG_C(val)          bfin_write16(FIO2_FLAG_C,val)
-#define bfin_read_FIO2_FLAG_S()              bfin_read16(FIO2_FLAG_S)
-#define bfin_write_FIO2_FLAG_S(val)          bfin_write16(FIO2_FLAG_S,val)
-#define bfin_read_FIO2_FLAG_T()              bfin_read16(FIO2_FLAG_T)
-#define bfin_write_FIO2_FLAG_T(val)          bfin_write16(FIO2_FLAG_T,val)
-#define bfin_read_FIO2_MASKA_D()             bfin_read16(FIO2_MASKA_D)
-#define bfin_write_FIO2_MASKA_D(val)         bfin_write16(FIO2_MASKA_D,val)
-#define bfin_read_FIO2_MASKA_C()             bfin_read16(FIO2_MASKA_C)
-#define bfin_write_FIO2_MASKA_C(val)         bfin_write16(FIO2_MASKA_C,val)
-#define bfin_read_FIO2_MASKA_S()             bfin_read16(FIO2_MASKA_S)
-#define bfin_write_FIO2_MASKA_S(val)         bfin_write16(FIO2_MASKA_S,val)
-#define bfin_read_FIO2_MASKA_T()             bfin_read16(FIO2_MASKA_T)
-#define bfin_write_FIO2_MASKA_T(val)         bfin_write16(FIO2_MASKA_T,val)
-#define bfin_read_FIO2_MASKB_D()             bfin_read16(FIO2_MASKB_D)
-#define bfin_write_FIO2_MASKB_D(val)         bfin_write16(FIO2_MASKB_D,val)
-#define bfin_read_FIO2_MASKB_C()             bfin_read16(FIO2_MASKB_C)
-#define bfin_write_FIO2_MASKB_C(val)         bfin_write16(FIO2_MASKB_C,val)
-#define bfin_read_FIO2_MASKB_S()             bfin_read16(FIO2_MASKB_S)
-#define bfin_write_FIO2_MASKB_S(val)         bfin_write16(FIO2_MASKB_S,val)
-#define bfin_read_FIO2_MASKB_T()             bfin_read16(FIO2_MASKB_T)
-#define bfin_write_FIO2_MASKB_T(val)         bfin_write16(FIO2_MASKB_T,val)
-#define bfin_read_FIO2_DIR()                 bfin_read16(FIO2_DIR)
-#define bfin_write_FIO2_DIR(val)             bfin_write16(FIO2_DIR,val)
-#define bfin_read_FIO2_POLAR()               bfin_read16(FIO2_POLAR)
-#define bfin_write_FIO2_POLAR(val)           bfin_write16(FIO2_POLAR,val)
-#define bfin_read_FIO2_EDGE()                bfin_read16(FIO2_EDGE)
-#define bfin_write_FIO2_EDGE(val)            bfin_write16(FIO2_EDGE,val)
-#define bfin_read_FIO2_BOTH()                bfin_read16(FIO2_BOTH)
-#define bfin_write_FIO2_BOTH(val)            bfin_write16(FIO2_BOTH,val)
-#define bfin_read_FIO2_INEN()                bfin_read16(FIO2_INEN)
-#define bfin_write_FIO2_INEN(val)            bfin_write16(FIO2_INEN,val)
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
-#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
-#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
-#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
-#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
-#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
-#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
-#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
-#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
-#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
-#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
-#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
-#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
-#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
-#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
-#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
-#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
-#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
-#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
-#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
-#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
-#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
-#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
-#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
-#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
-#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
-#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
-#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
-#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
-#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
-#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
-#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
-#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
-#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
-#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
-#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
-#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
-#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
-#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
-#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
-#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
-#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
-#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
-#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
-#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
-#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
-#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
-#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
-#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
-#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
-#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
-/* Asynchronous Memory Controller - External Bus Interface Unit */
-#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
-#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
-#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
-#define bfin_read_EBIU_SDBCTL()              bfin_read32(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)          bfin_write32(EBIU_SDBCTL,val)
-#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
-#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define bfin_read_PPI0_CONTROL()             bfin_read16(PPI0_CONTROL)
-#define bfin_write_PPI0_CONTROL(val)         bfin_write16(PPI0_CONTROL,val)
-#define bfin_read_PPI0_STATUS()              bfin_read16(PPI0_STATUS)
-#define bfin_write_PPI0_STATUS(val)          bfin_write16(PPI0_STATUS,val)
-#define bfin_clear_PPI0_STATUS()             bfin_read_PPI0_STATUS()
-#define bfin_read_PPI0_COUNT()               bfin_read16(PPI0_COUNT)
-#define bfin_write_PPI0_COUNT(val)           bfin_write16(PPI0_COUNT,val)
-#define bfin_read_PPI0_DELAY()               bfin_read16(PPI0_DELAY)
-#define bfin_write_PPI0_DELAY(val)           bfin_write16(PPI0_DELAY,val)
-#define bfin_read_PPI0_FRAME()               bfin_read16(PPI0_FRAME)
-#define bfin_write_PPI0_FRAME(val)           bfin_write16(PPI0_FRAME,val)
-/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define bfin_read_PPI1_CONTROL()             bfin_read16(PPI1_CONTROL)
-#define bfin_write_PPI1_CONTROL(val)         bfin_write16(PPI1_CONTROL,val)
-#define bfin_read_PPI1_STATUS()              bfin_read16(PPI1_STATUS)
-#define bfin_write_PPI1_STATUS(val)          bfin_write16(PPI1_STATUS,val)
-#define bfin_clear_PPI1_STATUS()             bfin_read_PPI1_STATUS()
-#define bfin_read_PPI1_COUNT()               bfin_read16(PPI1_COUNT)
-#define bfin_write_PPI1_COUNT(val)           bfin_write16(PPI1_COUNT,val)
-#define bfin_read_PPI1_DELAY()               bfin_read16(PPI1_DELAY)
-#define bfin_write_PPI1_DELAY(val)           bfin_write16(PPI1_DELAY,val)
-#define bfin_read_PPI1_FRAME()               bfin_read16(PPI1_FRAME)
-#define bfin_write_PPI1_FRAME(val)           bfin_write16(PPI1_FRAME,val)
-/*DMA traffic control registers */
-#define bfin_read_DMA1_TC_PER()              bfin_read16(DMA1_TC_PER)
-#define bfin_write_DMA1_TC_PER(val)          bfin_write16(DMA1_TC_PER,val)
-#define bfin_read_DMA1_TC_CNT()              bfin_read16(DMA1_TC_CNT)
-#define bfin_write_DMA1_TC_CNT(val)          bfin_write16(DMA1_TC_CNT,val)
-#define bfin_read_DMA2_TC_PER()              bfin_read16(DMA2_TC_PER)
-#define bfin_write_DMA2_TC_PER(val)          bfin_write16(DMA2_TC_PER,val)
-#define bfin_read_DMA2_TC_CNT()              bfin_read16(DMA2_TC_CNT)
-#define bfin_write_DMA2_TC_CNT(val)          bfin_write16(DMA2_TC_CNT,val)
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define bfin_read_DMA1_0_CONFIG()            bfin_read16(DMA1_0_CONFIG)
-#define bfin_write_DMA1_0_CONFIG(val)        bfin_write16(DMA1_0_CONFIG,val)
-#define bfin_read_DMA1_0_NEXT_DESC_PTR()     bfin_read32(DMA1_0_NEXT_DESC_PTR)
-#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_0_START_ADDR()        bfin_read32(DMA1_0_START_ADDR)
-#define bfin_write_DMA1_0_START_ADDR(val)    bfin_write32(DMA1_0_START_ADDR,val)
-#define bfin_read_DMA1_0_X_COUNT()           bfin_read16(DMA1_0_X_COUNT)
-#define bfin_write_DMA1_0_X_COUNT(val)       bfin_write16(DMA1_0_X_COUNT,val)
-#define bfin_read_DMA1_0_Y_COUNT()           bfin_read16(DMA1_0_Y_COUNT)
-#define bfin_write_DMA1_0_Y_COUNT(val)       bfin_write16(DMA1_0_Y_COUNT,val)
-#define bfin_read_DMA1_0_X_MODIFY()          bfin_read16(DMA1_0_X_MODIFY)
-#define bfin_write_DMA1_0_X_MODIFY(val)      bfin_write16(DMA1_0_X_MODIFY,val)
-#define bfin_read_DMA1_0_Y_MODIFY()          bfin_read16(DMA1_0_Y_MODIFY)
-#define bfin_write_DMA1_0_Y_MODIFY(val)      bfin_write16(DMA1_0_Y_MODIFY,val)
-#define bfin_read_DMA1_0_CURR_DESC_PTR()     bfin_read32(DMA1_0_CURR_DESC_PTR)
-#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_0_CURR_ADDR()         bfin_read32(DMA1_0_CURR_ADDR)
-#define bfin_write_DMA1_0_CURR_ADDR(val)     bfin_write32(DMA1_0_CURR_ADDR,val)
-#define bfin_read_DMA1_0_CURR_X_COUNT()      bfin_read16(DMA1_0_CURR_X_COUNT)
-#define bfin_write_DMA1_0_CURR_X_COUNT(val)  bfin_write16(DMA1_0_CURR_X_COUNT,val)
-#define bfin_read_DMA1_0_CURR_Y_COUNT()      bfin_read16(DMA1_0_CURR_Y_COUNT)
-#define bfin_write_DMA1_0_CURR_Y_COUNT(val)  bfin_write16(DMA1_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_0_IRQ_STATUS()        bfin_read16(DMA1_0_IRQ_STATUS)
-#define bfin_write_DMA1_0_IRQ_STATUS(val)    bfin_write16(DMA1_0_IRQ_STATUS,val)
-#define bfin_read_DMA1_0_PERIPHERAL_MAP()    bfin_read16(DMA1_0_PERIPHERAL_MAP)
-#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_1_CONFIG()            bfin_read16(DMA1_1_CONFIG)
-#define bfin_write_DMA1_1_CONFIG(val)        bfin_write16(DMA1_1_CONFIG,val)
-#define bfin_read_DMA1_1_NEXT_DESC_PTR()     bfin_read32(DMA1_1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_1_START_ADDR()        bfin_read32(DMA1_1_START_ADDR)
-#define bfin_write_DMA1_1_START_ADDR(val)    bfin_write32(DMA1_1_START_ADDR,val)
-#define bfin_read_DMA1_1_X_COUNT()           bfin_read16(DMA1_1_X_COUNT)
-#define bfin_write_DMA1_1_X_COUNT(val)       bfin_write16(DMA1_1_X_COUNT,val)
-#define bfin_read_DMA1_1_Y_COUNT()           bfin_read16(DMA1_1_Y_COUNT)
-#define bfin_write_DMA1_1_Y_COUNT(val)       bfin_write16(DMA1_1_Y_COUNT,val)
-#define bfin_read_DMA1_1_X_MODIFY()          bfin_read16(DMA1_1_X_MODIFY)
-#define bfin_write_DMA1_1_X_MODIFY(val)      bfin_write16(DMA1_1_X_MODIFY,val)
-#define bfin_read_DMA1_1_Y_MODIFY()          bfin_read16(DMA1_1_Y_MODIFY)
-#define bfin_write_DMA1_1_Y_MODIFY(val)      bfin_write16(DMA1_1_Y_MODIFY,val)
-#define bfin_read_DMA1_1_CURR_DESC_PTR()     bfin_read32(DMA1_1_CURR_DESC_PTR)
-#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_1_CURR_ADDR()         bfin_read32(DMA1_1_CURR_ADDR)
-#define bfin_write_DMA1_1_CURR_ADDR(val)     bfin_write32(DMA1_1_CURR_ADDR,val)
-#define bfin_read_DMA1_1_CURR_X_COUNT()      bfin_read16(DMA1_1_CURR_X_COUNT)
-#define bfin_write_DMA1_1_CURR_X_COUNT(val)  bfin_write16(DMA1_1_CURR_X_COUNT,val)
-#define bfin_read_DMA1_1_CURR_Y_COUNT()      bfin_read16(DMA1_1_CURR_Y_COUNT)
-#define bfin_write_DMA1_1_CURR_Y_COUNT(val)  bfin_write16(DMA1_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_1_IRQ_STATUS()        bfin_read16(DMA1_1_IRQ_STATUS)
-#define bfin_write_DMA1_1_IRQ_STATUS(val)    bfin_write16(DMA1_1_IRQ_STATUS,val)
-#define bfin_read_DMA1_1_PERIPHERAL_MAP()    bfin_read16(DMA1_1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_2_CONFIG()            bfin_read16(DMA1_2_CONFIG)
-#define bfin_write_DMA1_2_CONFIG(val)        bfin_write16(DMA1_2_CONFIG,val)
-#define bfin_read_DMA1_2_NEXT_DESC_PTR()     bfin_read32(DMA1_2_NEXT_DESC_PTR)
-#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_2_START_ADDR()        bfin_read32(DMA1_2_START_ADDR)
-#define bfin_write_DMA1_2_START_ADDR(val)    bfin_write32(DMA1_2_START_ADDR,val)
-#define bfin_read_DMA1_2_X_COUNT()           bfin_read16(DMA1_2_X_COUNT)
-#define bfin_write_DMA1_2_X_COUNT(val)       bfin_write16(DMA1_2_X_COUNT,val)
-#define bfin_read_DMA1_2_Y_COUNT()           bfin_read16(DMA1_2_Y_COUNT)
-#define bfin_write_DMA1_2_Y_COUNT(val)       bfin_write16(DMA1_2_Y_COUNT,val)
-#define bfin_read_DMA1_2_X_MODIFY()          bfin_read16(DMA1_2_X_MODIFY)
-#define bfin_write_DMA1_2_X_MODIFY(val)      bfin_write16(DMA1_2_X_MODIFY,val)
-#define bfin_read_DMA1_2_Y_MODIFY()          bfin_read16(DMA1_2_Y_MODIFY)
-#define bfin_write_DMA1_2_Y_MODIFY(val)      bfin_write16(DMA1_2_Y_MODIFY,val)
-#define bfin_read_DMA1_2_CURR_DESC_PTR()     bfin_read32(DMA1_2_CURR_DESC_PTR)
-#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_2_CURR_ADDR()         bfin_read32(DMA1_2_CURR_ADDR)
-#define bfin_write_DMA1_2_CURR_ADDR(val)     bfin_write32(DMA1_2_CURR_ADDR,val)
-#define bfin_read_DMA1_2_CURR_X_COUNT()      bfin_read16(DMA1_2_CURR_X_COUNT)
-#define bfin_write_DMA1_2_CURR_X_COUNT(val)  bfin_write16(DMA1_2_CURR_X_COUNT,val)
-#define bfin_read_DMA1_2_CURR_Y_COUNT()      bfin_read16(DMA1_2_CURR_Y_COUNT)
-#define bfin_write_DMA1_2_CURR_Y_COUNT(val)  bfin_write16(DMA1_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_2_IRQ_STATUS()        bfin_read16(DMA1_2_IRQ_STATUS)
-#define bfin_write_DMA1_2_IRQ_STATUS(val)    bfin_write16(DMA1_2_IRQ_STATUS,val)
-#define bfin_read_DMA1_2_PERIPHERAL_MAP()    bfin_read16(DMA1_2_PERIPHERAL_MAP)
-#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_3_CONFIG()            bfin_read16(DMA1_3_CONFIG)
-#define bfin_write_DMA1_3_CONFIG(val)        bfin_write16(DMA1_3_CONFIG,val)
-#define bfin_read_DMA1_3_NEXT_DESC_PTR()     bfin_read32(DMA1_3_NEXT_DESC_PTR)
-#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_3_START_ADDR()        bfin_read32(DMA1_3_START_ADDR)
-#define bfin_write_DMA1_3_START_ADDR(val)    bfin_write32(DMA1_3_START_ADDR,val)
-#define bfin_read_DMA1_3_X_COUNT()           bfin_read16(DMA1_3_X_COUNT)
-#define bfin_write_DMA1_3_X_COUNT(val)       bfin_write16(DMA1_3_X_COUNT,val)
-#define bfin_read_DMA1_3_Y_COUNT()           bfin_read16(DMA1_3_Y_COUNT)
-#define bfin_write_DMA1_3_Y_COUNT(val)       bfin_write16(DMA1_3_Y_COUNT,val)
-#define bfin_read_DMA1_3_X_MODIFY()          bfin_read16(DMA1_3_X_MODIFY)
-#define bfin_write_DMA1_3_X_MODIFY(val)      bfin_write16(DMA1_3_X_MODIFY,val)
-#define bfin_read_DMA1_3_Y_MODIFY()          bfin_read16(DMA1_3_Y_MODIFY)
-#define bfin_write_DMA1_3_Y_MODIFY(val)      bfin_write16(DMA1_3_Y_MODIFY,val)
-#define bfin_read_DMA1_3_CURR_DESC_PTR()     bfin_read32(DMA1_3_CURR_DESC_PTR)
-#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_3_CURR_ADDR()         bfin_read32(DMA1_3_CURR_ADDR)
-#define bfin_write_DMA1_3_CURR_ADDR(val)     bfin_write32(DMA1_3_CURR_ADDR,val)
-#define bfin_read_DMA1_3_CURR_X_COUNT()      bfin_read16(DMA1_3_CURR_X_COUNT)
-#define bfin_write_DMA1_3_CURR_X_COUNT(val)  bfin_write16(DMA1_3_CURR_X_COUNT,val)
-#define bfin_read_DMA1_3_CURR_Y_COUNT()      bfin_read16(DMA1_3_CURR_Y_COUNT)
-#define bfin_write_DMA1_3_CURR_Y_COUNT(val)  bfin_write16(DMA1_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_3_IRQ_STATUS()        bfin_read16(DMA1_3_IRQ_STATUS)
-#define bfin_write_DMA1_3_IRQ_STATUS(val)    bfin_write16(DMA1_3_IRQ_STATUS,val)
-#define bfin_read_DMA1_3_PERIPHERAL_MAP()    bfin_read16(DMA1_3_PERIPHERAL_MAP)
-#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_4_CONFIG()            bfin_read16(DMA1_4_CONFIG)
-#define bfin_write_DMA1_4_CONFIG(val)        bfin_write16(DMA1_4_CONFIG,val)
-#define bfin_read_DMA1_4_NEXT_DESC_PTR()     bfin_read32(DMA1_4_NEXT_DESC_PTR)
-#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_4_START_ADDR()        bfin_read32(DMA1_4_START_ADDR)
-#define bfin_write_DMA1_4_START_ADDR(val)    bfin_write32(DMA1_4_START_ADDR,val)
-#define bfin_read_DMA1_4_X_COUNT()           bfin_read16(DMA1_4_X_COUNT)
-#define bfin_write_DMA1_4_X_COUNT(val)       bfin_write16(DMA1_4_X_COUNT,val)
-#define bfin_read_DMA1_4_Y_COUNT()           bfin_read16(DMA1_4_Y_COUNT)
-#define bfin_write_DMA1_4_Y_COUNT(val)       bfin_write16(DMA1_4_Y_COUNT,val)
-#define bfin_read_DMA1_4_X_MODIFY()          bfin_read16(DMA1_4_X_MODIFY)
-#define bfin_write_DMA1_4_X_MODIFY(val)      bfin_write16(DMA1_4_X_MODIFY,val)
-#define bfin_read_DMA1_4_Y_MODIFY()          bfin_read16(DMA1_4_Y_MODIFY)
-#define bfin_write_DMA1_4_Y_MODIFY(val)      bfin_write16(DMA1_4_Y_MODIFY,val)
-#define bfin_read_DMA1_4_CURR_DESC_PTR()     bfin_read32(DMA1_4_CURR_DESC_PTR)
-#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_4_CURR_ADDR()         bfin_read32(DMA1_4_CURR_ADDR)
-#define bfin_write_DMA1_4_CURR_ADDR(val)     bfin_write32(DMA1_4_CURR_ADDR,val)
-#define bfin_read_DMA1_4_CURR_X_COUNT()      bfin_read16(DMA1_4_CURR_X_COUNT)
-#define bfin_write_DMA1_4_CURR_X_COUNT(val)  bfin_write16(DMA1_4_CURR_X_COUNT,val)
-#define bfin_read_DMA1_4_CURR_Y_COUNT()      bfin_read16(DMA1_4_CURR_Y_COUNT)
-#define bfin_write_DMA1_4_CURR_Y_COUNT(val)  bfin_write16(DMA1_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_4_IRQ_STATUS()        bfin_read16(DMA1_4_IRQ_STATUS)
-#define bfin_write_DMA1_4_IRQ_STATUS(val)    bfin_write16(DMA1_4_IRQ_STATUS,val)
-#define bfin_read_DMA1_4_PERIPHERAL_MAP()    bfin_read16(DMA1_4_PERIPHERAL_MAP)
-#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_5_CONFIG()            bfin_read16(DMA1_5_CONFIG)
-#define bfin_write_DMA1_5_CONFIG(val)        bfin_write16(DMA1_5_CONFIG,val)
-#define bfin_read_DMA1_5_NEXT_DESC_PTR()     bfin_read32(DMA1_5_NEXT_DESC_PTR)
-#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_5_START_ADDR()        bfin_read32(DMA1_5_START_ADDR)
-#define bfin_write_DMA1_5_START_ADDR(val)    bfin_write32(DMA1_5_START_ADDR,val)
-#define bfin_read_DMA1_5_X_COUNT()           bfin_read16(DMA1_5_X_COUNT)
-#define bfin_write_DMA1_5_X_COUNT(val)       bfin_write16(DMA1_5_X_COUNT,val)
-#define bfin_read_DMA1_5_Y_COUNT()           bfin_read16(DMA1_5_Y_COUNT)
-#define bfin_write_DMA1_5_Y_COUNT(val)       bfin_write16(DMA1_5_Y_COUNT,val)
-#define bfin_read_DMA1_5_X_MODIFY()          bfin_read16(DMA1_5_X_MODIFY)
-#define bfin_write_DMA1_5_X_MODIFY(val)      bfin_write16(DMA1_5_X_MODIFY,val)
-#define bfin_read_DMA1_5_Y_MODIFY()          bfin_read16(DMA1_5_Y_MODIFY)
-#define bfin_write_DMA1_5_Y_MODIFY(val)      bfin_write16(DMA1_5_Y_MODIFY,val)
-#define bfin_read_DMA1_5_CURR_DESC_PTR()     bfin_read32(DMA1_5_CURR_DESC_PTR)
-#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_5_CURR_ADDR()         bfin_read32(DMA1_5_CURR_ADDR)
-#define bfin_write_DMA1_5_CURR_ADDR(val)     bfin_write32(DMA1_5_CURR_ADDR,val)
-#define bfin_read_DMA1_5_CURR_X_COUNT()      bfin_read16(DMA1_5_CURR_X_COUNT)
-#define bfin_write_DMA1_5_CURR_X_COUNT(val)  bfin_write16(DMA1_5_CURR_X_COUNT,val)
-#define bfin_read_DMA1_5_CURR_Y_COUNT()      bfin_read16(DMA1_5_CURR_Y_COUNT)
-#define bfin_write_DMA1_5_CURR_Y_COUNT(val)  bfin_write16(DMA1_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_5_IRQ_STATUS()        bfin_read16(DMA1_5_IRQ_STATUS)
-#define bfin_write_DMA1_5_IRQ_STATUS(val)    bfin_write16(DMA1_5_IRQ_STATUS,val)
-#define bfin_read_DMA1_5_PERIPHERAL_MAP()    bfin_read16(DMA1_5_PERIPHERAL_MAP)
-#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_6_CONFIG()            bfin_read16(DMA1_6_CONFIG)
-#define bfin_write_DMA1_6_CONFIG(val)        bfin_write16(DMA1_6_CONFIG,val)
-#define bfin_read_DMA1_6_NEXT_DESC_PTR()     bfin_read32(DMA1_6_NEXT_DESC_PTR)
-#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_6_START_ADDR()        bfin_read32(DMA1_6_START_ADDR)
-#define bfin_write_DMA1_6_START_ADDR(val)    bfin_write32(DMA1_6_START_ADDR,val)
-#define bfin_read_DMA1_6_X_COUNT()           bfin_read16(DMA1_6_X_COUNT)
-#define bfin_write_DMA1_6_X_COUNT(val)       bfin_write16(DMA1_6_X_COUNT,val)
-#define bfin_read_DMA1_6_Y_COUNT()           bfin_read16(DMA1_6_Y_COUNT)
-#define bfin_write_DMA1_6_Y_COUNT(val)       bfin_write16(DMA1_6_Y_COUNT,val)
-#define bfin_read_DMA1_6_X_MODIFY()          bfin_read16(DMA1_6_X_MODIFY)
-#define bfin_write_DMA1_6_X_MODIFY(val)      bfin_write16(DMA1_6_X_MODIFY,val)
-#define bfin_read_DMA1_6_Y_MODIFY()          bfin_read16(DMA1_6_Y_MODIFY)
-#define bfin_write_DMA1_6_Y_MODIFY(val)      bfin_write16(DMA1_6_Y_MODIFY,val)
-#define bfin_read_DMA1_6_CURR_DESC_PTR()     bfin_read32(DMA1_6_CURR_DESC_PTR)
-#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_6_CURR_ADDR()         bfin_read32(DMA1_6_CURR_ADDR)
-#define bfin_write_DMA1_6_CURR_ADDR(val)     bfin_write32(DMA1_6_CURR_ADDR,val)
-#define bfin_read_DMA1_6_CURR_X_COUNT()      bfin_read16(DMA1_6_CURR_X_COUNT)
-#define bfin_write_DMA1_6_CURR_X_COUNT(val)  bfin_write16(DMA1_6_CURR_X_COUNT,val)
-#define bfin_read_DMA1_6_CURR_Y_COUNT()      bfin_read16(DMA1_6_CURR_Y_COUNT)
-#define bfin_write_DMA1_6_CURR_Y_COUNT(val)  bfin_write16(DMA1_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_6_IRQ_STATUS()        bfin_read16(DMA1_6_IRQ_STATUS)
-#define bfin_write_DMA1_6_IRQ_STATUS(val)    bfin_write16(DMA1_6_IRQ_STATUS,val)
-#define bfin_read_DMA1_6_PERIPHERAL_MAP()    bfin_read16(DMA1_6_PERIPHERAL_MAP)
-#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_7_CONFIG()            bfin_read16(DMA1_7_CONFIG)
-#define bfin_write_DMA1_7_CONFIG(val)        bfin_write16(DMA1_7_CONFIG,val)
-#define bfin_read_DMA1_7_NEXT_DESC_PTR()     bfin_read32(DMA1_7_NEXT_DESC_PTR)
-#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_7_START_ADDR()        bfin_read32(DMA1_7_START_ADDR)
-#define bfin_write_DMA1_7_START_ADDR(val)    bfin_write32(DMA1_7_START_ADDR,val)
-#define bfin_read_DMA1_7_X_COUNT()           bfin_read16(DMA1_7_X_COUNT)
-#define bfin_write_DMA1_7_X_COUNT(val)       bfin_write16(DMA1_7_X_COUNT,val)
-#define bfin_read_DMA1_7_Y_COUNT()           bfin_read16(DMA1_7_Y_COUNT)
-#define bfin_write_DMA1_7_Y_COUNT(val)       bfin_write16(DMA1_7_Y_COUNT,val)
-#define bfin_read_DMA1_7_X_MODIFY()          bfin_read16(DMA1_7_X_MODIFY)
-#define bfin_write_DMA1_7_X_MODIFY(val)      bfin_write16(DMA1_7_X_MODIFY,val)
-#define bfin_read_DMA1_7_Y_MODIFY()          bfin_read16(DMA1_7_Y_MODIFY)
-#define bfin_write_DMA1_7_Y_MODIFY(val)      bfin_write16(DMA1_7_Y_MODIFY,val)
-#define bfin_read_DMA1_7_CURR_DESC_PTR()     bfin_read32(DMA1_7_CURR_DESC_PTR)
-#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_7_CURR_ADDR()         bfin_read32(DMA1_7_CURR_ADDR)
-#define bfin_write_DMA1_7_CURR_ADDR(val)     bfin_write32(DMA1_7_CURR_ADDR,val)
-#define bfin_read_DMA1_7_CURR_X_COUNT()      bfin_read16(DMA1_7_CURR_X_COUNT)
-#define bfin_write_DMA1_7_CURR_X_COUNT(val)  bfin_write16(DMA1_7_CURR_X_COUNT,val)
-#define bfin_read_DMA1_7_CURR_Y_COUNT()      bfin_read16(DMA1_7_CURR_Y_COUNT)
-#define bfin_write_DMA1_7_CURR_Y_COUNT(val)  bfin_write16(DMA1_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_7_IRQ_STATUS()        bfin_read16(DMA1_7_IRQ_STATUS)
-#define bfin_write_DMA1_7_IRQ_STATUS(val)    bfin_write16(DMA1_7_IRQ_STATUS,val)
-#define bfin_read_DMA1_7_PERIPHERAL_MAP()    bfin_read16(DMA1_7_PERIPHERAL_MAP)
-#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_8_CONFIG()            bfin_read16(DMA1_8_CONFIG)
-#define bfin_write_DMA1_8_CONFIG(val)        bfin_write16(DMA1_8_CONFIG,val)
-#define bfin_read_DMA1_8_NEXT_DESC_PTR()     bfin_read32(DMA1_8_NEXT_DESC_PTR)
-#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_8_START_ADDR()        bfin_read32(DMA1_8_START_ADDR)
-#define bfin_write_DMA1_8_START_ADDR(val)    bfin_write32(DMA1_8_START_ADDR,val)
-#define bfin_read_DMA1_8_X_COUNT()           bfin_read16(DMA1_8_X_COUNT)
-#define bfin_write_DMA1_8_X_COUNT(val)       bfin_write16(DMA1_8_X_COUNT,val)
-#define bfin_read_DMA1_8_Y_COUNT()           bfin_read16(DMA1_8_Y_COUNT)
-#define bfin_write_DMA1_8_Y_COUNT(val)       bfin_write16(DMA1_8_Y_COUNT,val)
-#define bfin_read_DMA1_8_X_MODIFY()          bfin_read16(DMA1_8_X_MODIFY)
-#define bfin_write_DMA1_8_X_MODIFY(val)      bfin_write16(DMA1_8_X_MODIFY,val)
-#define bfin_read_DMA1_8_Y_MODIFY()          bfin_read16(DMA1_8_Y_MODIFY)
-#define bfin_write_DMA1_8_Y_MODIFY(val)      bfin_write16(DMA1_8_Y_MODIFY,val)
-#define bfin_read_DMA1_8_CURR_DESC_PTR()     bfin_read32(DMA1_8_CURR_DESC_PTR)
-#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_8_CURR_ADDR()         bfin_read32(DMA1_8_CURR_ADDR)
-#define bfin_write_DMA1_8_CURR_ADDR(val)     bfin_write32(DMA1_8_CURR_ADDR,val)
-#define bfin_read_DMA1_8_CURR_X_COUNT()      bfin_read16(DMA1_8_CURR_X_COUNT)
-#define bfin_write_DMA1_8_CURR_X_COUNT(val)  bfin_write16(DMA1_8_CURR_X_COUNT,val)
-#define bfin_read_DMA1_8_CURR_Y_COUNT()      bfin_read16(DMA1_8_CURR_Y_COUNT)
-#define bfin_write_DMA1_8_CURR_Y_COUNT(val)  bfin_write16(DMA1_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_8_IRQ_STATUS()        bfin_read16(DMA1_8_IRQ_STATUS)
-#define bfin_write_DMA1_8_IRQ_STATUS(val)    bfin_write16(DMA1_8_IRQ_STATUS,val)
-#define bfin_read_DMA1_8_PERIPHERAL_MAP()    bfin_read16(DMA1_8_PERIPHERAL_MAP)
-#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_9_CONFIG()            bfin_read16(DMA1_9_CONFIG)
-#define bfin_write_DMA1_9_CONFIG(val)        bfin_write16(DMA1_9_CONFIG,val)
-#define bfin_read_DMA1_9_NEXT_DESC_PTR()     bfin_read32(DMA1_9_NEXT_DESC_PTR)
-#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_9_START_ADDR()        bfin_read32(DMA1_9_START_ADDR)
-#define bfin_write_DMA1_9_START_ADDR(val)    bfin_write32(DMA1_9_START_ADDR,val)
-#define bfin_read_DMA1_9_X_COUNT()           bfin_read16(DMA1_9_X_COUNT)
-#define bfin_write_DMA1_9_X_COUNT(val)       bfin_write16(DMA1_9_X_COUNT,val)
-#define bfin_read_DMA1_9_Y_COUNT()           bfin_read16(DMA1_9_Y_COUNT)
-#define bfin_write_DMA1_9_Y_COUNT(val)       bfin_write16(DMA1_9_Y_COUNT,val)
-#define bfin_read_DMA1_9_X_MODIFY()          bfin_read16(DMA1_9_X_MODIFY)
-#define bfin_write_DMA1_9_X_MODIFY(val)      bfin_write16(DMA1_9_X_MODIFY,val)
-#define bfin_read_DMA1_9_Y_MODIFY()          bfin_read16(DMA1_9_Y_MODIFY)
-#define bfin_write_DMA1_9_Y_MODIFY(val)      bfin_write16(DMA1_9_Y_MODIFY,val)
-#define bfin_read_DMA1_9_CURR_DESC_PTR()     bfin_read32(DMA1_9_CURR_DESC_PTR)
-#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_9_CURR_ADDR()         bfin_read32(DMA1_9_CURR_ADDR)
-#define bfin_write_DMA1_9_CURR_ADDR(val)     bfin_write32(DMA1_9_CURR_ADDR,val)
-#define bfin_read_DMA1_9_CURR_X_COUNT()      bfin_read16(DMA1_9_CURR_X_COUNT)
-#define bfin_write_DMA1_9_CURR_X_COUNT(val)  bfin_write16(DMA1_9_CURR_X_COUNT,val)
-#define bfin_read_DMA1_9_CURR_Y_COUNT()      bfin_read16(DMA1_9_CURR_Y_COUNT)
-#define bfin_write_DMA1_9_CURR_Y_COUNT(val)  bfin_write16(DMA1_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_9_IRQ_STATUS()        bfin_read16(DMA1_9_IRQ_STATUS)
-#define bfin_write_DMA1_9_IRQ_STATUS(val)    bfin_write16(DMA1_9_IRQ_STATUS,val)
-#define bfin_read_DMA1_9_PERIPHERAL_MAP()    bfin_read16(DMA1_9_PERIPHERAL_MAP)
-#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_10_CONFIG()           bfin_read16(DMA1_10_CONFIG)
-#define bfin_write_DMA1_10_CONFIG(val)       bfin_write16(DMA1_10_CONFIG,val)
-#define bfin_read_DMA1_10_NEXT_DESC_PTR()    bfin_read32(DMA1_10_NEXT_DESC_PTR)
-#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_10_START_ADDR()       bfin_read32(DMA1_10_START_ADDR)
-#define bfin_write_DMA1_10_START_ADDR(val)   bfin_write32(DMA1_10_START_ADDR,val)
-#define bfin_read_DMA1_10_X_COUNT()          bfin_read16(DMA1_10_X_COUNT)
-#define bfin_write_DMA1_10_X_COUNT(val)      bfin_write16(DMA1_10_X_COUNT,val)
-#define bfin_read_DMA1_10_Y_COUNT()          bfin_read16(DMA1_10_Y_COUNT)
-#define bfin_write_DMA1_10_Y_COUNT(val)      bfin_write16(DMA1_10_Y_COUNT,val)
-#define bfin_read_DMA1_10_X_MODIFY()         bfin_read16(DMA1_10_X_MODIFY)
-#define bfin_write_DMA1_10_X_MODIFY(val)     bfin_write16(DMA1_10_X_MODIFY,val)
-#define bfin_read_DMA1_10_Y_MODIFY()         bfin_read16(DMA1_10_Y_MODIFY)
-#define bfin_write_DMA1_10_Y_MODIFY(val)     bfin_write16(DMA1_10_Y_MODIFY,val)
-#define bfin_read_DMA1_10_CURR_DESC_PTR()    bfin_read32(DMA1_10_CURR_DESC_PTR)
-#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_10_CURR_ADDR()        bfin_read32(DMA1_10_CURR_ADDR)
-#define bfin_write_DMA1_10_CURR_ADDR(val)    bfin_write32(DMA1_10_CURR_ADDR,val)
-#define bfin_read_DMA1_10_CURR_X_COUNT()     bfin_read16(DMA1_10_CURR_X_COUNT)
-#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
-#define bfin_read_DMA1_10_CURR_Y_COUNT()     bfin_read16(DMA1_10_CURR_Y_COUNT)
-#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_10_IRQ_STATUS()       bfin_read16(DMA1_10_IRQ_STATUS)
-#define bfin_write_DMA1_10_IRQ_STATUS(val)   bfin_write16(DMA1_10_IRQ_STATUS,val)
-#define bfin_read_DMA1_10_PERIPHERAL_MAP()   bfin_read16(DMA1_10_PERIPHERAL_MAP)
-#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA1_11_CONFIG()           bfin_read16(DMA1_11_CONFIG)
-#define bfin_write_DMA1_11_CONFIG(val)       bfin_write16(DMA1_11_CONFIG,val)
-#define bfin_read_DMA1_11_NEXT_DESC_PTR()    bfin_read32(DMA1_11_NEXT_DESC_PTR)
-#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA1_11_START_ADDR()       bfin_read32(DMA1_11_START_ADDR)
-#define bfin_write_DMA1_11_START_ADDR(val)   bfin_write32(DMA1_11_START_ADDR,val)
-#define bfin_read_DMA1_11_X_COUNT()          bfin_read16(DMA1_11_X_COUNT)
-#define bfin_write_DMA1_11_X_COUNT(val)      bfin_write16(DMA1_11_X_COUNT,val)
-#define bfin_read_DMA1_11_Y_COUNT()          bfin_read16(DMA1_11_Y_COUNT)
-#define bfin_write_DMA1_11_Y_COUNT(val)      bfin_write16(DMA1_11_Y_COUNT,val)
-#define bfin_read_DMA1_11_X_MODIFY()         bfin_read16(DMA1_11_X_MODIFY)
-#define bfin_write_DMA1_11_X_MODIFY(val)     bfin_write16(DMA1_11_X_MODIFY,val)
-#define bfin_read_DMA1_11_Y_MODIFY()         bfin_read16(DMA1_11_Y_MODIFY)
-#define bfin_write_DMA1_11_Y_MODIFY(val)     bfin_write16(DMA1_11_Y_MODIFY,val)
-#define bfin_read_DMA1_11_CURR_DESC_PTR()    bfin_read32(DMA1_11_CURR_DESC_PTR)
-#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA1_11_CURR_ADDR()        bfin_read32(DMA1_11_CURR_ADDR)
-#define bfin_write_DMA1_11_CURR_ADDR(val)    bfin_write32(DMA1_11_CURR_ADDR,val)
-#define bfin_read_DMA1_11_CURR_X_COUNT()     bfin_read16(DMA1_11_CURR_X_COUNT)
-#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
-#define bfin_read_DMA1_11_CURR_Y_COUNT()     bfin_read16(DMA1_11_CURR_Y_COUNT)
-#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA1_11_IRQ_STATUS()       bfin_read16(DMA1_11_IRQ_STATUS)
-#define bfin_write_DMA1_11_IRQ_STATUS(val)   bfin_write16(DMA1_11_IRQ_STATUS,val)
-#define bfin_read_DMA1_11_PERIPHERAL_MAP()   bfin_read16(DMA1_11_PERIPHERAL_MAP)
-#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define bfin_read_MDMA1_D0_CONFIG()          bfin_read16(MDMA1_D0_CONFIG)
-#define bfin_write_MDMA1_D0_CONFIG(val)      bfin_write16(MDMA1_D0_CONFIG,val)
-#define bfin_read_MDMA1_D0_NEXT_DESC_PTR()   bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_START_ADDR()      bfin_read32(MDMA1_D0_START_ADDR)
-#define bfin_write_MDMA1_D0_START_ADDR(val)  bfin_write32(MDMA1_D0_START_ADDR,val)
-#define bfin_read_MDMA1_D0_X_COUNT()         bfin_read16(MDMA1_D0_X_COUNT)
-#define bfin_write_MDMA1_D0_X_COUNT(val)     bfin_write16(MDMA1_D0_X_COUNT,val)
-#define bfin_read_MDMA1_D0_Y_COUNT()         bfin_read16(MDMA1_D0_Y_COUNT)
-#define bfin_write_MDMA1_D0_Y_COUNT(val)     bfin_write16(MDMA1_D0_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_X_MODIFY()        bfin_read16(MDMA1_D0_X_MODIFY)
-#define bfin_write_MDMA1_D0_X_MODIFY(val)    bfin_write16(MDMA1_D0_X_MODIFY,val)
-#define bfin_read_MDMA1_D0_Y_MODIFY()        bfin_read16(MDMA1_D0_Y_MODIFY)
-#define bfin_write_MDMA1_D0_Y_MODIFY(val)    bfin_write16(MDMA1_D0_Y_MODIFY,val)
-#define bfin_read_MDMA1_D0_CURR_DESC_PTR()   bfin_read32(MDMA1_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D0_CURR_ADDR()       bfin_read32(MDMA1_D0_CURR_ADDR)
-#define bfin_write_MDMA1_D0_CURR_ADDR(val)   bfin_write32(MDMA1_D0_CURR_ADDR,val)
-#define bfin_read_MDMA1_D0_CURR_X_COUNT()    bfin_read16(MDMA1_D0_CURR_X_COUNT)
-#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D0_CURR_Y_COUNT()    bfin_read16(MDMA1_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D0_IRQ_STATUS()      bfin_read16(MDMA1_D0_IRQ_STATUS)
-#define bfin_write_MDMA1_D0_IRQ_STATUS(val)  bfin_write16(MDMA1_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D0_PERIPHERAL_MAP()  bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S0_CONFIG()          bfin_read16(MDMA1_S0_CONFIG)
-#define bfin_write_MDMA1_S0_CONFIG(val)      bfin_write16(MDMA1_S0_CONFIG,val)
-#define bfin_read_MDMA1_S0_NEXT_DESC_PTR()   bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_START_ADDR()      bfin_read32(MDMA1_S0_START_ADDR)
-#define bfin_write_MDMA1_S0_START_ADDR(val)  bfin_write32(MDMA1_S0_START_ADDR,val)
-#define bfin_read_MDMA1_S0_X_COUNT()         bfin_read16(MDMA1_S0_X_COUNT)
-#define bfin_write_MDMA1_S0_X_COUNT(val)     bfin_write16(MDMA1_S0_X_COUNT,val)
-#define bfin_read_MDMA1_S0_Y_COUNT()         bfin_read16(MDMA1_S0_Y_COUNT)
-#define bfin_write_MDMA1_S0_Y_COUNT(val)     bfin_write16(MDMA1_S0_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_X_MODIFY()        bfin_read16(MDMA1_S0_X_MODIFY)
-#define bfin_write_MDMA1_S0_X_MODIFY(val)    bfin_write16(MDMA1_S0_X_MODIFY,val)
-#define bfin_read_MDMA1_S0_Y_MODIFY()        bfin_read16(MDMA1_S0_Y_MODIFY)
-#define bfin_write_MDMA1_S0_Y_MODIFY(val)    bfin_write16(MDMA1_S0_Y_MODIFY,val)
-#define bfin_read_MDMA1_S0_CURR_DESC_PTR()   bfin_read32(MDMA1_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S0_CURR_ADDR()       bfin_read32(MDMA1_S0_CURR_ADDR)
-#define bfin_write_MDMA1_S0_CURR_ADDR(val)   bfin_write32(MDMA1_S0_CURR_ADDR,val)
-#define bfin_read_MDMA1_S0_CURR_X_COUNT()    bfin_read16(MDMA1_S0_CURR_X_COUNT)
-#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S0_CURR_Y_COUNT()    bfin_read16(MDMA1_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S0_IRQ_STATUS()      bfin_read16(MDMA1_S0_IRQ_STATUS)
-#define bfin_write_MDMA1_S0_IRQ_STATUS(val)  bfin_write16(MDMA1_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S0_PERIPHERAL_MAP()  bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_D1_CONFIG()          bfin_read16(MDMA1_D1_CONFIG)
-#define bfin_write_MDMA1_D1_CONFIG(val)      bfin_write16(MDMA1_D1_CONFIG,val)
-#define bfin_read_MDMA1_D1_NEXT_DESC_PTR()   bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_START_ADDR()      bfin_read32(MDMA1_D1_START_ADDR)
-#define bfin_write_MDMA1_D1_START_ADDR(val)  bfin_write32(MDMA1_D1_START_ADDR,val)
-#define bfin_read_MDMA1_D1_X_COUNT()         bfin_read16(MDMA1_D1_X_COUNT)
-#define bfin_write_MDMA1_D1_X_COUNT(val)     bfin_write16(MDMA1_D1_X_COUNT,val)
-#define bfin_read_MDMA1_D1_Y_COUNT()         bfin_read16(MDMA1_D1_Y_COUNT)
-#define bfin_write_MDMA1_D1_Y_COUNT(val)     bfin_write16(MDMA1_D1_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_X_MODIFY()        bfin_read16(MDMA1_D1_X_MODIFY)
-#define bfin_write_MDMA1_D1_X_MODIFY(val)    bfin_write16(MDMA1_D1_X_MODIFY,val)
-#define bfin_read_MDMA1_D1_Y_MODIFY()        bfin_read16(MDMA1_D1_Y_MODIFY)
-#define bfin_write_MDMA1_D1_Y_MODIFY(val)    bfin_write16(MDMA1_D1_Y_MODIFY,val)
-#define bfin_read_MDMA1_D1_CURR_DESC_PTR()   bfin_read32(MDMA1_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_D1_CURR_ADDR()       bfin_read32(MDMA1_D1_CURR_ADDR)
-#define bfin_write_MDMA1_D1_CURR_ADDR(val)   bfin_write32(MDMA1_D1_CURR_ADDR,val)
-#define bfin_read_MDMA1_D1_CURR_X_COUNT()    bfin_read16(MDMA1_D1_CURR_X_COUNT)
-#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_D1_CURR_Y_COUNT()    bfin_read16(MDMA1_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_D1_IRQ_STATUS()      bfin_read16(MDMA1_D1_IRQ_STATUS)
-#define bfin_write_MDMA1_D1_IRQ_STATUS(val)  bfin_write16(MDMA1_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_D1_PERIPHERAL_MAP()  bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA1_S1_CONFIG()          bfin_read16(MDMA1_S1_CONFIG)
-#define bfin_write_MDMA1_S1_CONFIG(val)      bfin_write16(MDMA1_S1_CONFIG,val)
-#define bfin_read_MDMA1_S1_NEXT_DESC_PTR()   bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_START_ADDR()      bfin_read32(MDMA1_S1_START_ADDR)
-#define bfin_write_MDMA1_S1_START_ADDR(val)  bfin_write32(MDMA1_S1_START_ADDR,val)
-#define bfin_read_MDMA1_S1_X_COUNT()         bfin_read16(MDMA1_S1_X_COUNT)
-#define bfin_write_MDMA1_S1_X_COUNT(val)     bfin_write16(MDMA1_S1_X_COUNT,val)
-#define bfin_read_MDMA1_S1_Y_COUNT()         bfin_read16(MDMA1_S1_Y_COUNT)
-#define bfin_write_MDMA1_S1_Y_COUNT(val)     bfin_write16(MDMA1_S1_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_X_MODIFY()        bfin_read16(MDMA1_S1_X_MODIFY)
-#define bfin_write_MDMA1_S1_X_MODIFY(val)    bfin_write16(MDMA1_S1_X_MODIFY,val)
-#define bfin_read_MDMA1_S1_Y_MODIFY()        bfin_read16(MDMA1_S1_Y_MODIFY)
-#define bfin_write_MDMA1_S1_Y_MODIFY(val)    bfin_write16(MDMA1_S1_Y_MODIFY,val)
-#define bfin_read_MDMA1_S1_CURR_DESC_PTR()   bfin_read32(MDMA1_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA1_S1_CURR_ADDR()       bfin_read32(MDMA1_S1_CURR_ADDR)
-#define bfin_write_MDMA1_S1_CURR_ADDR(val)   bfin_write32(MDMA1_S1_CURR_ADDR,val)
-#define bfin_read_MDMA1_S1_CURR_X_COUNT()    bfin_read16(MDMA1_S1_CURR_X_COUNT)
-#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA1_S1_CURR_Y_COUNT()    bfin_read16(MDMA1_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA1_S1_IRQ_STATUS()      bfin_read16(MDMA1_S1_IRQ_STATUS)
-#define bfin_write_MDMA1_S1_IRQ_STATUS(val)  bfin_write16(MDMA1_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA1_S1_PERIPHERAL_MAP()  bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define bfin_read_DMA2_0_CONFIG()            bfin_read16(DMA2_0_CONFIG)
-#define bfin_write_DMA2_0_CONFIG(val)        bfin_write16(DMA2_0_CONFIG,val)
-#define bfin_read_DMA2_0_NEXT_DESC_PTR()     bfin_read32(DMA2_0_NEXT_DESC_PTR)
-#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_0_START_ADDR()        bfin_read32(DMA2_0_START_ADDR)
-#define bfin_write_DMA2_0_START_ADDR(val)    bfin_write32(DMA2_0_START_ADDR,val)
-#define bfin_read_DMA2_0_X_COUNT()           bfin_read16(DMA2_0_X_COUNT)
-#define bfin_write_DMA2_0_X_COUNT(val)       bfin_write16(DMA2_0_X_COUNT,val)
-#define bfin_read_DMA2_0_Y_COUNT()           bfin_read16(DMA2_0_Y_COUNT)
-#define bfin_write_DMA2_0_Y_COUNT(val)       bfin_write16(DMA2_0_Y_COUNT,val)
-#define bfin_read_DMA2_0_X_MODIFY()          bfin_read16(DMA2_0_X_MODIFY)
-#define bfin_write_DMA2_0_X_MODIFY(val)      bfin_write16(DMA2_0_X_MODIFY,val)
-#define bfin_read_DMA2_0_Y_MODIFY()          bfin_read16(DMA2_0_Y_MODIFY)
-#define bfin_write_DMA2_0_Y_MODIFY(val)      bfin_write16(DMA2_0_Y_MODIFY,val)
-#define bfin_read_DMA2_0_CURR_DESC_PTR()     bfin_read32(DMA2_0_CURR_DESC_PTR)
-#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_0_CURR_ADDR()         bfin_read32(DMA2_0_CURR_ADDR)
-#define bfin_write_DMA2_0_CURR_ADDR(val)     bfin_write32(DMA2_0_CURR_ADDR,val)
-#define bfin_read_DMA2_0_CURR_X_COUNT()      bfin_read16(DMA2_0_CURR_X_COUNT)
-#define bfin_write_DMA2_0_CURR_X_COUNT(val)  bfin_write16(DMA2_0_CURR_X_COUNT,val)
-#define bfin_read_DMA2_0_CURR_Y_COUNT()      bfin_read16(DMA2_0_CURR_Y_COUNT)
-#define bfin_write_DMA2_0_CURR_Y_COUNT(val)  bfin_write16(DMA2_0_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_0_IRQ_STATUS()        bfin_read16(DMA2_0_IRQ_STATUS)
-#define bfin_write_DMA2_0_IRQ_STATUS(val)    bfin_write16(DMA2_0_IRQ_STATUS,val)
-#define bfin_read_DMA2_0_PERIPHERAL_MAP()    bfin_read16(DMA2_0_PERIPHERAL_MAP)
-#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_1_CONFIG()            bfin_read16(DMA2_1_CONFIG)
-#define bfin_write_DMA2_1_CONFIG(val)        bfin_write16(DMA2_1_CONFIG,val)
-#define bfin_read_DMA2_1_NEXT_DESC_PTR()     bfin_read32(DMA2_1_NEXT_DESC_PTR)
-#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_1_START_ADDR()        bfin_read32(DMA2_1_START_ADDR)
-#define bfin_write_DMA2_1_START_ADDR(val)    bfin_write32(DMA2_1_START_ADDR,val)
-#define bfin_read_DMA2_1_X_COUNT()           bfin_read16(DMA2_1_X_COUNT)
-#define bfin_write_DMA2_1_X_COUNT(val)       bfin_write16(DMA2_1_X_COUNT,val)
-#define bfin_read_DMA2_1_Y_COUNT()           bfin_read16(DMA2_1_Y_COUNT)
-#define bfin_write_DMA2_1_Y_COUNT(val)       bfin_write16(DMA2_1_Y_COUNT,val)
-#define bfin_read_DMA2_1_X_MODIFY()          bfin_read16(DMA2_1_X_MODIFY)
-#define bfin_write_DMA2_1_X_MODIFY(val)      bfin_write16(DMA2_1_X_MODIFY,val)
-#define bfin_read_DMA2_1_Y_MODIFY()          bfin_read16(DMA2_1_Y_MODIFY)
-#define bfin_write_DMA2_1_Y_MODIFY(val)      bfin_write16(DMA2_1_Y_MODIFY,val)
-#define bfin_read_DMA2_1_CURR_DESC_PTR()     bfin_read32(DMA2_1_CURR_DESC_PTR)
-#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_1_CURR_ADDR()         bfin_read32(DMA2_1_CURR_ADDR)
-#define bfin_write_DMA2_1_CURR_ADDR(val)     bfin_write32(DMA2_1_CURR_ADDR,val)
-#define bfin_read_DMA2_1_CURR_X_COUNT()      bfin_read16(DMA2_1_CURR_X_COUNT)
-#define bfin_write_DMA2_1_CURR_X_COUNT(val)  bfin_write16(DMA2_1_CURR_X_COUNT,val)
-#define bfin_read_DMA2_1_CURR_Y_COUNT()      bfin_read16(DMA2_1_CURR_Y_COUNT)
-#define bfin_write_DMA2_1_CURR_Y_COUNT(val)  bfin_write16(DMA2_1_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_1_IRQ_STATUS()        bfin_read16(DMA2_1_IRQ_STATUS)
-#define bfin_write_DMA2_1_IRQ_STATUS(val)    bfin_write16(DMA2_1_IRQ_STATUS,val)
-#define bfin_read_DMA2_1_PERIPHERAL_MAP()    bfin_read16(DMA2_1_PERIPHERAL_MAP)
-#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_2_CONFIG()            bfin_read16(DMA2_2_CONFIG)
-#define bfin_write_DMA2_2_CONFIG(val)        bfin_write16(DMA2_2_CONFIG,val)
-#define bfin_read_DMA2_2_NEXT_DESC_PTR()     bfin_read32(DMA2_2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_2_START_ADDR()        bfin_read32(DMA2_2_START_ADDR)
-#define bfin_write_DMA2_2_START_ADDR(val)    bfin_write32(DMA2_2_START_ADDR,val)
-#define bfin_read_DMA2_2_X_COUNT()           bfin_read16(DMA2_2_X_COUNT)
-#define bfin_write_DMA2_2_X_COUNT(val)       bfin_write16(DMA2_2_X_COUNT,val)
-#define bfin_read_DMA2_2_Y_COUNT()           bfin_read16(DMA2_2_Y_COUNT)
-#define bfin_write_DMA2_2_Y_COUNT(val)       bfin_write16(DMA2_2_Y_COUNT,val)
-#define bfin_read_DMA2_2_X_MODIFY()          bfin_read16(DMA2_2_X_MODIFY)
-#define bfin_write_DMA2_2_X_MODIFY(val)      bfin_write16(DMA2_2_X_MODIFY,val)
-#define bfin_read_DMA2_2_Y_MODIFY()          bfin_read16(DMA2_2_Y_MODIFY)
-#define bfin_write_DMA2_2_Y_MODIFY(val)      bfin_write16(DMA2_2_Y_MODIFY,val)
-#define bfin_read_DMA2_2_CURR_DESC_PTR()     bfin_read32(DMA2_2_CURR_DESC_PTR)
-#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_2_CURR_ADDR()         bfin_read32(DMA2_2_CURR_ADDR)
-#define bfin_write_DMA2_2_CURR_ADDR(val)     bfin_write32(DMA2_2_CURR_ADDR,val)
-#define bfin_read_DMA2_2_CURR_X_COUNT()      bfin_read16(DMA2_2_CURR_X_COUNT)
-#define bfin_write_DMA2_2_CURR_X_COUNT(val)  bfin_write16(DMA2_2_CURR_X_COUNT,val)
-#define bfin_read_DMA2_2_CURR_Y_COUNT()      bfin_read16(DMA2_2_CURR_Y_COUNT)
-#define bfin_write_DMA2_2_CURR_Y_COUNT(val)  bfin_write16(DMA2_2_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_2_IRQ_STATUS()        bfin_read16(DMA2_2_IRQ_STATUS)
-#define bfin_write_DMA2_2_IRQ_STATUS(val)    bfin_write16(DMA2_2_IRQ_STATUS,val)
-#define bfin_read_DMA2_2_PERIPHERAL_MAP()    bfin_read16(DMA2_2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_3_CONFIG()            bfin_read16(DMA2_3_CONFIG)
-#define bfin_write_DMA2_3_CONFIG(val)        bfin_write16(DMA2_3_CONFIG,val)
-#define bfin_read_DMA2_3_NEXT_DESC_PTR()     bfin_read32(DMA2_3_NEXT_DESC_PTR)
-#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_3_START_ADDR()        bfin_read32(DMA2_3_START_ADDR)
-#define bfin_write_DMA2_3_START_ADDR(val)    bfin_write32(DMA2_3_START_ADDR,val)
-#define bfin_read_DMA2_3_X_COUNT()           bfin_read16(DMA2_3_X_COUNT)
-#define bfin_write_DMA2_3_X_COUNT(val)       bfin_write16(DMA2_3_X_COUNT,val)
-#define bfin_read_DMA2_3_Y_COUNT()           bfin_read16(DMA2_3_Y_COUNT)
-#define bfin_write_DMA2_3_Y_COUNT(val)       bfin_write16(DMA2_3_Y_COUNT,val)
-#define bfin_read_DMA2_3_X_MODIFY()          bfin_read16(DMA2_3_X_MODIFY)
-#define bfin_write_DMA2_3_X_MODIFY(val)      bfin_write16(DMA2_3_X_MODIFY,val)
-#define bfin_read_DMA2_3_Y_MODIFY()          bfin_read16(DMA2_3_Y_MODIFY)
-#define bfin_write_DMA2_3_Y_MODIFY(val)      bfin_write16(DMA2_3_Y_MODIFY,val)
-#define bfin_read_DMA2_3_CURR_DESC_PTR()     bfin_read32(DMA2_3_CURR_DESC_PTR)
-#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_3_CURR_ADDR()         bfin_read32(DMA2_3_CURR_ADDR)
-#define bfin_write_DMA2_3_CURR_ADDR(val)     bfin_write32(DMA2_3_CURR_ADDR,val)
-#define bfin_read_DMA2_3_CURR_X_COUNT()      bfin_read16(DMA2_3_CURR_X_COUNT)
-#define bfin_write_DMA2_3_CURR_X_COUNT(val)  bfin_write16(DMA2_3_CURR_X_COUNT,val)
-#define bfin_read_DMA2_3_CURR_Y_COUNT()      bfin_read16(DMA2_3_CURR_Y_COUNT)
-#define bfin_write_DMA2_3_CURR_Y_COUNT(val)  bfin_write16(DMA2_3_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_3_IRQ_STATUS()        bfin_read16(DMA2_3_IRQ_STATUS)
-#define bfin_write_DMA2_3_IRQ_STATUS(val)    bfin_write16(DMA2_3_IRQ_STATUS,val)
-#define bfin_read_DMA2_3_PERIPHERAL_MAP()    bfin_read16(DMA2_3_PERIPHERAL_MAP)
-#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_4_CONFIG()            bfin_read16(DMA2_4_CONFIG)
-#define bfin_write_DMA2_4_CONFIG(val)        bfin_write16(DMA2_4_CONFIG,val)
-#define bfin_read_DMA2_4_NEXT_DESC_PTR()     bfin_read32(DMA2_4_NEXT_DESC_PTR)
-#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_4_START_ADDR()        bfin_read32(DMA2_4_START_ADDR)
-#define bfin_write_DMA2_4_START_ADDR(val)    bfin_write32(DMA2_4_START_ADDR,val)
-#define bfin_read_DMA2_4_X_COUNT()           bfin_read16(DMA2_4_X_COUNT)
-#define bfin_write_DMA2_4_X_COUNT(val)       bfin_write16(DMA2_4_X_COUNT,val)
-#define bfin_read_DMA2_4_Y_COUNT()           bfin_read16(DMA2_4_Y_COUNT)
-#define bfin_write_DMA2_4_Y_COUNT(val)       bfin_write16(DMA2_4_Y_COUNT,val)
-#define bfin_read_DMA2_4_X_MODIFY()          bfin_read16(DMA2_4_X_MODIFY)
-#define bfin_write_DMA2_4_X_MODIFY(val)      bfin_write16(DMA2_4_X_MODIFY,val)
-#define bfin_read_DMA2_4_Y_MODIFY()          bfin_read16(DMA2_4_Y_MODIFY)
-#define bfin_write_DMA2_4_Y_MODIFY(val)      bfin_write16(DMA2_4_Y_MODIFY,val)
-#define bfin_read_DMA2_4_CURR_DESC_PTR()     bfin_read32(DMA2_4_CURR_DESC_PTR)
-#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_4_CURR_ADDR()         bfin_read32(DMA2_4_CURR_ADDR)
-#define bfin_write_DMA2_4_CURR_ADDR(val)     bfin_write32(DMA2_4_CURR_ADDR,val)
-#define bfin_read_DMA2_4_CURR_X_COUNT()      bfin_read16(DMA2_4_CURR_X_COUNT)
-#define bfin_write_DMA2_4_CURR_X_COUNT(val)  bfin_write16(DMA2_4_CURR_X_COUNT,val)
-#define bfin_read_DMA2_4_CURR_Y_COUNT()      bfin_read16(DMA2_4_CURR_Y_COUNT)
-#define bfin_write_DMA2_4_CURR_Y_COUNT(val)  bfin_write16(DMA2_4_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_4_IRQ_STATUS()        bfin_read16(DMA2_4_IRQ_STATUS)
-#define bfin_write_DMA2_4_IRQ_STATUS(val)    bfin_write16(DMA2_4_IRQ_STATUS,val)
-#define bfin_read_DMA2_4_PERIPHERAL_MAP()    bfin_read16(DMA2_4_PERIPHERAL_MAP)
-#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_5_CONFIG()            bfin_read16(DMA2_5_CONFIG)
-#define bfin_write_DMA2_5_CONFIG(val)        bfin_write16(DMA2_5_CONFIG,val)
-#define bfin_read_DMA2_5_NEXT_DESC_PTR()     bfin_read32(DMA2_5_NEXT_DESC_PTR)
-#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_5_START_ADDR()        bfin_read32(DMA2_5_START_ADDR)
-#define bfin_write_DMA2_5_START_ADDR(val)    bfin_write32(DMA2_5_START_ADDR,val)
-#define bfin_read_DMA2_5_X_COUNT()           bfin_read16(DMA2_5_X_COUNT)
-#define bfin_write_DMA2_5_X_COUNT(val)       bfin_write16(DMA2_5_X_COUNT,val)
-#define bfin_read_DMA2_5_Y_COUNT()           bfin_read16(DMA2_5_Y_COUNT)
-#define bfin_write_DMA2_5_Y_COUNT(val)       bfin_write16(DMA2_5_Y_COUNT,val)
-#define bfin_read_DMA2_5_X_MODIFY()          bfin_read16(DMA2_5_X_MODIFY)
-#define bfin_write_DMA2_5_X_MODIFY(val)      bfin_write16(DMA2_5_X_MODIFY,val)
-#define bfin_read_DMA2_5_Y_MODIFY()          bfin_read16(DMA2_5_Y_MODIFY)
-#define bfin_write_DMA2_5_Y_MODIFY(val)      bfin_write16(DMA2_5_Y_MODIFY,val)
-#define bfin_read_DMA2_5_CURR_DESC_PTR()     bfin_read32(DMA2_5_CURR_DESC_PTR)
-#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_5_CURR_ADDR()         bfin_read32(DMA2_5_CURR_ADDR)
-#define bfin_write_DMA2_5_CURR_ADDR(val)     bfin_write32(DMA2_5_CURR_ADDR,val)
-#define bfin_read_DMA2_5_CURR_X_COUNT()      bfin_read16(DMA2_5_CURR_X_COUNT)
-#define bfin_write_DMA2_5_CURR_X_COUNT(val)  bfin_write16(DMA2_5_CURR_X_COUNT,val)
-#define bfin_read_DMA2_5_CURR_Y_COUNT()      bfin_read16(DMA2_5_CURR_Y_COUNT)
-#define bfin_write_DMA2_5_CURR_Y_COUNT(val)  bfin_write16(DMA2_5_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_5_IRQ_STATUS()        bfin_read16(DMA2_5_IRQ_STATUS)
-#define bfin_write_DMA2_5_IRQ_STATUS(val)    bfin_write16(DMA2_5_IRQ_STATUS,val)
-#define bfin_read_DMA2_5_PERIPHERAL_MAP()    bfin_read16(DMA2_5_PERIPHERAL_MAP)
-#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_6_CONFIG()            bfin_read16(DMA2_6_CONFIG)
-#define bfin_write_DMA2_6_CONFIG(val)        bfin_write16(DMA2_6_CONFIG,val)
-#define bfin_read_DMA2_6_NEXT_DESC_PTR()     bfin_read32(DMA2_6_NEXT_DESC_PTR)
-#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_6_START_ADDR()        bfin_read32(DMA2_6_START_ADDR)
-#define bfin_write_DMA2_6_START_ADDR(val)    bfin_write32(DMA2_6_START_ADDR,val)
-#define bfin_read_DMA2_6_X_COUNT()           bfin_read16(DMA2_6_X_COUNT)
-#define bfin_write_DMA2_6_X_COUNT(val)       bfin_write16(DMA2_6_X_COUNT,val)
-#define bfin_read_DMA2_6_Y_COUNT()           bfin_read16(DMA2_6_Y_COUNT)
-#define bfin_write_DMA2_6_Y_COUNT(val)       bfin_write16(DMA2_6_Y_COUNT,val)
-#define bfin_read_DMA2_6_X_MODIFY()          bfin_read16(DMA2_6_X_MODIFY)
-#define bfin_write_DMA2_6_X_MODIFY(val)      bfin_write16(DMA2_6_X_MODIFY,val)
-#define bfin_read_DMA2_6_Y_MODIFY()          bfin_read16(DMA2_6_Y_MODIFY)
-#define bfin_write_DMA2_6_Y_MODIFY(val)      bfin_write16(DMA2_6_Y_MODIFY,val)
-#define bfin_read_DMA2_6_CURR_DESC_PTR()     bfin_read32(DMA2_6_CURR_DESC_PTR)
-#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_6_CURR_ADDR()         bfin_read32(DMA2_6_CURR_ADDR)
-#define bfin_write_DMA2_6_CURR_ADDR(val)     bfin_write32(DMA2_6_CURR_ADDR,val)
-#define bfin_read_DMA2_6_CURR_X_COUNT()      bfin_read16(DMA2_6_CURR_X_COUNT)
-#define bfin_write_DMA2_6_CURR_X_COUNT(val)  bfin_write16(DMA2_6_CURR_X_COUNT,val)
-#define bfin_read_DMA2_6_CURR_Y_COUNT()      bfin_read16(DMA2_6_CURR_Y_COUNT)
-#define bfin_write_DMA2_6_CURR_Y_COUNT(val)  bfin_write16(DMA2_6_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_6_IRQ_STATUS()        bfin_read16(DMA2_6_IRQ_STATUS)
-#define bfin_write_DMA2_6_IRQ_STATUS(val)    bfin_write16(DMA2_6_IRQ_STATUS,val)
-#define bfin_read_DMA2_6_PERIPHERAL_MAP()    bfin_read16(DMA2_6_PERIPHERAL_MAP)
-#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_7_CONFIG()            bfin_read16(DMA2_7_CONFIG)
-#define bfin_write_DMA2_7_CONFIG(val)        bfin_write16(DMA2_7_CONFIG,val)
-#define bfin_read_DMA2_7_NEXT_DESC_PTR()     bfin_read32(DMA2_7_NEXT_DESC_PTR)
-#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_7_START_ADDR()        bfin_read32(DMA2_7_START_ADDR)
-#define bfin_write_DMA2_7_START_ADDR(val)    bfin_write32(DMA2_7_START_ADDR,val)
-#define bfin_read_DMA2_7_X_COUNT()           bfin_read16(DMA2_7_X_COUNT)
-#define bfin_write_DMA2_7_X_COUNT(val)       bfin_write16(DMA2_7_X_COUNT,val)
-#define bfin_read_DMA2_7_Y_COUNT()           bfin_read16(DMA2_7_Y_COUNT)
-#define bfin_write_DMA2_7_Y_COUNT(val)       bfin_write16(DMA2_7_Y_COUNT,val)
-#define bfin_read_DMA2_7_X_MODIFY()          bfin_read16(DMA2_7_X_MODIFY)
-#define bfin_write_DMA2_7_X_MODIFY(val)      bfin_write16(DMA2_7_X_MODIFY,val)
-#define bfin_read_DMA2_7_Y_MODIFY()          bfin_read16(DMA2_7_Y_MODIFY)
-#define bfin_write_DMA2_7_Y_MODIFY(val)      bfin_write16(DMA2_7_Y_MODIFY,val)
-#define bfin_read_DMA2_7_CURR_DESC_PTR()     bfin_read32(DMA2_7_CURR_DESC_PTR)
-#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_7_CURR_ADDR()         bfin_read32(DMA2_7_CURR_ADDR)
-#define bfin_write_DMA2_7_CURR_ADDR(val)     bfin_write32(DMA2_7_CURR_ADDR,val)
-#define bfin_read_DMA2_7_CURR_X_COUNT()      bfin_read16(DMA2_7_CURR_X_COUNT)
-#define bfin_write_DMA2_7_CURR_X_COUNT(val)  bfin_write16(DMA2_7_CURR_X_COUNT,val)
-#define bfin_read_DMA2_7_CURR_Y_COUNT()      bfin_read16(DMA2_7_CURR_Y_COUNT)
-#define bfin_write_DMA2_7_CURR_Y_COUNT(val)  bfin_write16(DMA2_7_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_7_IRQ_STATUS()        bfin_read16(DMA2_7_IRQ_STATUS)
-#define bfin_write_DMA2_7_IRQ_STATUS(val)    bfin_write16(DMA2_7_IRQ_STATUS,val)
-#define bfin_read_DMA2_7_PERIPHERAL_MAP()    bfin_read16(DMA2_7_PERIPHERAL_MAP)
-#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_8_CONFIG()            bfin_read16(DMA2_8_CONFIG)
-#define bfin_write_DMA2_8_CONFIG(val)        bfin_write16(DMA2_8_CONFIG,val)
-#define bfin_read_DMA2_8_NEXT_DESC_PTR()     bfin_read32(DMA2_8_NEXT_DESC_PTR)
-#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_8_START_ADDR()        bfin_read32(DMA2_8_START_ADDR)
-#define bfin_write_DMA2_8_START_ADDR(val)    bfin_write32(DMA2_8_START_ADDR,val)
-#define bfin_read_DMA2_8_X_COUNT()           bfin_read16(DMA2_8_X_COUNT)
-#define bfin_write_DMA2_8_X_COUNT(val)       bfin_write16(DMA2_8_X_COUNT,val)
-#define bfin_read_DMA2_8_Y_COUNT()           bfin_read16(DMA2_8_Y_COUNT)
-#define bfin_write_DMA2_8_Y_COUNT(val)       bfin_write16(DMA2_8_Y_COUNT,val)
-#define bfin_read_DMA2_8_X_MODIFY()          bfin_read16(DMA2_8_X_MODIFY)
-#define bfin_write_DMA2_8_X_MODIFY(val)      bfin_write16(DMA2_8_X_MODIFY,val)
-#define bfin_read_DMA2_8_Y_MODIFY()          bfin_read16(DMA2_8_Y_MODIFY)
-#define bfin_write_DMA2_8_Y_MODIFY(val)      bfin_write16(DMA2_8_Y_MODIFY,val)
-#define bfin_read_DMA2_8_CURR_DESC_PTR()     bfin_read32(DMA2_8_CURR_DESC_PTR)
-#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_8_CURR_ADDR()         bfin_read32(DMA2_8_CURR_ADDR)
-#define bfin_write_DMA2_8_CURR_ADDR(val)     bfin_write32(DMA2_8_CURR_ADDR,val)
-#define bfin_read_DMA2_8_CURR_X_COUNT()      bfin_read16(DMA2_8_CURR_X_COUNT)
-#define bfin_write_DMA2_8_CURR_X_COUNT(val)  bfin_write16(DMA2_8_CURR_X_COUNT,val)
-#define bfin_read_DMA2_8_CURR_Y_COUNT()      bfin_read16(DMA2_8_CURR_Y_COUNT)
-#define bfin_write_DMA2_8_CURR_Y_COUNT(val)  bfin_write16(DMA2_8_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_8_IRQ_STATUS()        bfin_read16(DMA2_8_IRQ_STATUS)
-#define bfin_write_DMA2_8_IRQ_STATUS(val)    bfin_write16(DMA2_8_IRQ_STATUS,val)
-#define bfin_read_DMA2_8_PERIPHERAL_MAP()    bfin_read16(DMA2_8_PERIPHERAL_MAP)
-#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_9_CONFIG()            bfin_read16(DMA2_9_CONFIG)
-#define bfin_write_DMA2_9_CONFIG(val)        bfin_write16(DMA2_9_CONFIG,val)
-#define bfin_read_DMA2_9_NEXT_DESC_PTR()     bfin_read32(DMA2_9_NEXT_DESC_PTR)
-#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_9_START_ADDR()        bfin_read32(DMA2_9_START_ADDR)
-#define bfin_write_DMA2_9_START_ADDR(val)    bfin_write32(DMA2_9_START_ADDR,val)
-#define bfin_read_DMA2_9_X_COUNT()           bfin_read16(DMA2_9_X_COUNT)
-#define bfin_write_DMA2_9_X_COUNT(val)       bfin_write16(DMA2_9_X_COUNT,val)
-#define bfin_read_DMA2_9_Y_COUNT()           bfin_read16(DMA2_9_Y_COUNT)
-#define bfin_write_DMA2_9_Y_COUNT(val)       bfin_write16(DMA2_9_Y_COUNT,val)
-#define bfin_read_DMA2_9_X_MODIFY()          bfin_read16(DMA2_9_X_MODIFY)
-#define bfin_write_DMA2_9_X_MODIFY(val)      bfin_write16(DMA2_9_X_MODIFY,val)
-#define bfin_read_DMA2_9_Y_MODIFY()          bfin_read16(DMA2_9_Y_MODIFY)
-#define bfin_write_DMA2_9_Y_MODIFY(val)      bfin_write16(DMA2_9_Y_MODIFY,val)
-#define bfin_read_DMA2_9_CURR_DESC_PTR()     bfin_read32(DMA2_9_CURR_DESC_PTR)
-#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_9_CURR_ADDR()         bfin_read32(DMA2_9_CURR_ADDR)
-#define bfin_write_DMA2_9_CURR_ADDR(val)     bfin_write32(DMA2_9_CURR_ADDR,val)
-#define bfin_read_DMA2_9_CURR_X_COUNT()      bfin_read16(DMA2_9_CURR_X_COUNT)
-#define bfin_write_DMA2_9_CURR_X_COUNT(val)  bfin_write16(DMA2_9_CURR_X_COUNT,val)
-#define bfin_read_DMA2_9_CURR_Y_COUNT()      bfin_read16(DMA2_9_CURR_Y_COUNT)
-#define bfin_write_DMA2_9_CURR_Y_COUNT(val)  bfin_write16(DMA2_9_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_9_IRQ_STATUS()        bfin_read16(DMA2_9_IRQ_STATUS)
-#define bfin_write_DMA2_9_IRQ_STATUS(val)    bfin_write16(DMA2_9_IRQ_STATUS,val)
-#define bfin_read_DMA2_9_PERIPHERAL_MAP()    bfin_read16(DMA2_9_PERIPHERAL_MAP)
-#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_10_CONFIG()           bfin_read16(DMA2_10_CONFIG)
-#define bfin_write_DMA2_10_CONFIG(val)       bfin_write16(DMA2_10_CONFIG,val)
-#define bfin_read_DMA2_10_NEXT_DESC_PTR()    bfin_read32(DMA2_10_NEXT_DESC_PTR)
-#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_10_START_ADDR()       bfin_read32(DMA2_10_START_ADDR)
-#define bfin_write_DMA2_10_START_ADDR(val)   bfin_write32(DMA2_10_START_ADDR,val)
-#define bfin_read_DMA2_10_X_COUNT()          bfin_read16(DMA2_10_X_COUNT)
-#define bfin_write_DMA2_10_X_COUNT(val)      bfin_write16(DMA2_10_X_COUNT,val)
-#define bfin_read_DMA2_10_Y_COUNT()          bfin_read16(DMA2_10_Y_COUNT)
-#define bfin_write_DMA2_10_Y_COUNT(val)      bfin_write16(DMA2_10_Y_COUNT,val)
-#define bfin_read_DMA2_10_X_MODIFY()         bfin_read16(DMA2_10_X_MODIFY)
-#define bfin_write_DMA2_10_X_MODIFY(val)     bfin_write16(DMA2_10_X_MODIFY,val)
-#define bfin_read_DMA2_10_Y_MODIFY()         bfin_read16(DMA2_10_Y_MODIFY)
-#define bfin_write_DMA2_10_Y_MODIFY(val)     bfin_write16(DMA2_10_Y_MODIFY,val)
-#define bfin_read_DMA2_10_CURR_DESC_PTR()    bfin_read32(DMA2_10_CURR_DESC_PTR)
-#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_10_CURR_ADDR()        bfin_read32(DMA2_10_CURR_ADDR)
-#define bfin_write_DMA2_10_CURR_ADDR(val)    bfin_write32(DMA2_10_CURR_ADDR,val)
-#define bfin_read_DMA2_10_CURR_X_COUNT()     bfin_read16(DMA2_10_CURR_X_COUNT)
-#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
-#define bfin_read_DMA2_10_CURR_Y_COUNT()     bfin_read16(DMA2_10_CURR_Y_COUNT)
-#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_10_IRQ_STATUS()       bfin_read16(DMA2_10_IRQ_STATUS)
-#define bfin_write_DMA2_10_IRQ_STATUS(val)   bfin_write16(DMA2_10_IRQ_STATUS,val)
-#define bfin_read_DMA2_10_PERIPHERAL_MAP()   bfin_read16(DMA2_10_PERIPHERAL_MAP)
-#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
-#define bfin_read_DMA2_11_CONFIG()           bfin_read16(DMA2_11_CONFIG)
-#define bfin_write_DMA2_11_CONFIG(val)       bfin_write16(DMA2_11_CONFIG,val)
-#define bfin_read_DMA2_11_NEXT_DESC_PTR()    bfin_read32(DMA2_11_NEXT_DESC_PTR)
-#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
-#define bfin_read_DMA2_11_START_ADDR()       bfin_read32(DMA2_11_START_ADDR)
-#define bfin_write_DMA2_11_START_ADDR(val)   bfin_write32(DMA2_11_START_ADDR,val)
-#define bfin_read_DMA2_11_X_COUNT()          bfin_read16(DMA2_11_X_COUNT)
-#define bfin_write_DMA2_11_X_COUNT(val)      bfin_write16(DMA2_11_X_COUNT,val)
-#define bfin_read_DMA2_11_Y_COUNT()          bfin_read16(DMA2_11_Y_COUNT)
-#define bfin_write_DMA2_11_Y_COUNT(val)      bfin_write16(DMA2_11_Y_COUNT,val)
-#define bfin_read_DMA2_11_X_MODIFY()         bfin_read16(DMA2_11_X_MODIFY)
-#define bfin_write_DMA2_11_X_MODIFY(val)     bfin_write16(DMA2_11_X_MODIFY,val)
-#define bfin_read_DMA2_11_Y_MODIFY()         bfin_read16(DMA2_11_Y_MODIFY)
-#define bfin_write_DMA2_11_Y_MODIFY(val)     bfin_write16(DMA2_11_Y_MODIFY,val)
-#define bfin_read_DMA2_11_CURR_DESC_PTR()    bfin_read32(DMA2_11_CURR_DESC_PTR)
-#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
-#define bfin_read_DMA2_11_CURR_ADDR()        bfin_read32(DMA2_11_CURR_ADDR)
-#define bfin_write_DMA2_11_CURR_ADDR(val)    bfin_write32(DMA2_11_CURR_ADDR,val)
-#define bfin_read_DMA2_11_CURR_X_COUNT()     bfin_read16(DMA2_11_CURR_X_COUNT)
-#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
-#define bfin_read_DMA2_11_CURR_Y_COUNT()     bfin_read16(DMA2_11_CURR_Y_COUNT)
-#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
-#define bfin_read_DMA2_11_IRQ_STATUS()       bfin_read16(DMA2_11_IRQ_STATUS)
-#define bfin_write_DMA2_11_IRQ_STATUS(val)   bfin_write16(DMA2_11_IRQ_STATUS,val)
-#define bfin_read_DMA2_11_PERIPHERAL_MAP()   bfin_read16(DMA2_11_PERIPHERAL_MAP)
-#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define bfin_read_MDMA2_D0_CONFIG()          bfin_read16(MDMA2_D0_CONFIG)
-#define bfin_write_MDMA2_D0_CONFIG(val)      bfin_write16(MDMA2_D0_CONFIG,val)
-#define bfin_read_MDMA2_D0_NEXT_DESC_PTR()   bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_START_ADDR()      bfin_read32(MDMA2_D0_START_ADDR)
-#define bfin_write_MDMA2_D0_START_ADDR(val)  bfin_write32(MDMA2_D0_START_ADDR,val)
-#define bfin_read_MDMA2_D0_X_COUNT()         bfin_read16(MDMA2_D0_X_COUNT)
-#define bfin_write_MDMA2_D0_X_COUNT(val)     bfin_write16(MDMA2_D0_X_COUNT,val)
-#define bfin_read_MDMA2_D0_Y_COUNT()         bfin_read16(MDMA2_D0_Y_COUNT)
-#define bfin_write_MDMA2_D0_Y_COUNT(val)     bfin_write16(MDMA2_D0_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_X_MODIFY()        bfin_read16(MDMA2_D0_X_MODIFY)
-#define bfin_write_MDMA2_D0_X_MODIFY(val)    bfin_write16(MDMA2_D0_X_MODIFY,val)
-#define bfin_read_MDMA2_D0_Y_MODIFY()        bfin_read16(MDMA2_D0_Y_MODIFY)
-#define bfin_write_MDMA2_D0_Y_MODIFY(val)    bfin_write16(MDMA2_D0_Y_MODIFY,val)
-#define bfin_read_MDMA2_D0_CURR_DESC_PTR()   bfin_read32(MDMA2_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D0_CURR_ADDR()       bfin_read32(MDMA2_D0_CURR_ADDR)
-#define bfin_write_MDMA2_D0_CURR_ADDR(val)   bfin_write32(MDMA2_D0_CURR_ADDR,val)
-#define bfin_read_MDMA2_D0_CURR_X_COUNT()    bfin_read16(MDMA2_D0_CURR_X_COUNT)
-#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D0_CURR_Y_COUNT()    bfin_read16(MDMA2_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D0_IRQ_STATUS()      bfin_read16(MDMA2_D0_IRQ_STATUS)
-#define bfin_write_MDMA2_D0_IRQ_STATUS(val)  bfin_write16(MDMA2_D0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D0_PERIPHERAL_MAP()  bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S0_CONFIG()          bfin_read16(MDMA2_S0_CONFIG)
-#define bfin_write_MDMA2_S0_CONFIG(val)      bfin_write16(MDMA2_S0_CONFIG,val)
-#define bfin_read_MDMA2_S0_NEXT_DESC_PTR()   bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_START_ADDR()      bfin_read32(MDMA2_S0_START_ADDR)
-#define bfin_write_MDMA2_S0_START_ADDR(val)  bfin_write32(MDMA2_S0_START_ADDR,val)
-#define bfin_read_MDMA2_S0_X_COUNT()         bfin_read16(MDMA2_S0_X_COUNT)
-#define bfin_write_MDMA2_S0_X_COUNT(val)     bfin_write16(MDMA2_S0_X_COUNT,val)
-#define bfin_read_MDMA2_S0_Y_COUNT()         bfin_read16(MDMA2_S0_Y_COUNT)
-#define bfin_write_MDMA2_S0_Y_COUNT(val)     bfin_write16(MDMA2_S0_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_X_MODIFY()        bfin_read16(MDMA2_S0_X_MODIFY)
-#define bfin_write_MDMA2_S0_X_MODIFY(val)    bfin_write16(MDMA2_S0_X_MODIFY,val)
-#define bfin_read_MDMA2_S0_Y_MODIFY()        bfin_read16(MDMA2_S0_Y_MODIFY)
-#define bfin_write_MDMA2_S0_Y_MODIFY(val)    bfin_write16(MDMA2_S0_Y_MODIFY,val)
-#define bfin_read_MDMA2_S0_CURR_DESC_PTR()   bfin_read32(MDMA2_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S0_CURR_ADDR()       bfin_read32(MDMA2_S0_CURR_ADDR)
-#define bfin_write_MDMA2_S0_CURR_ADDR(val)   bfin_write32(MDMA2_S0_CURR_ADDR,val)
-#define bfin_read_MDMA2_S0_CURR_X_COUNT()    bfin_read16(MDMA2_S0_CURR_X_COUNT)
-#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S0_CURR_Y_COUNT()    bfin_read16(MDMA2_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S0_IRQ_STATUS()      bfin_read16(MDMA2_S0_IRQ_STATUS)
-#define bfin_write_MDMA2_S0_IRQ_STATUS(val)  bfin_write16(MDMA2_S0_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S0_PERIPHERAL_MAP()  bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_D1_CONFIG()          bfin_read16(MDMA2_D1_CONFIG)
-#define bfin_write_MDMA2_D1_CONFIG(val)      bfin_write16(MDMA2_D1_CONFIG,val)
-#define bfin_read_MDMA2_D1_NEXT_DESC_PTR()   bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_START_ADDR()      bfin_read32(MDMA2_D1_START_ADDR)
-#define bfin_write_MDMA2_D1_START_ADDR(val)  bfin_write32(MDMA2_D1_START_ADDR,val)
-#define bfin_read_MDMA2_D1_X_COUNT()         bfin_read16(MDMA2_D1_X_COUNT)
-#define bfin_write_MDMA2_D1_X_COUNT(val)     bfin_write16(MDMA2_D1_X_COUNT,val)
-#define bfin_read_MDMA2_D1_Y_COUNT()         bfin_read16(MDMA2_D1_Y_COUNT)
-#define bfin_write_MDMA2_D1_Y_COUNT(val)     bfin_write16(MDMA2_D1_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_X_MODIFY()        bfin_read16(MDMA2_D1_X_MODIFY)
-#define bfin_write_MDMA2_D1_X_MODIFY(val)    bfin_write16(MDMA2_D1_X_MODIFY,val)
-#define bfin_read_MDMA2_D1_Y_MODIFY()        bfin_read16(MDMA2_D1_Y_MODIFY)
-#define bfin_write_MDMA2_D1_Y_MODIFY(val)    bfin_write16(MDMA2_D1_Y_MODIFY,val)
-#define bfin_read_MDMA2_D1_CURR_DESC_PTR()   bfin_read32(MDMA2_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_D1_CURR_ADDR()       bfin_read32(MDMA2_D1_CURR_ADDR)
-#define bfin_write_MDMA2_D1_CURR_ADDR(val)   bfin_write32(MDMA2_D1_CURR_ADDR,val)
-#define bfin_read_MDMA2_D1_CURR_X_COUNT()    bfin_read16(MDMA2_D1_CURR_X_COUNT)
-#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_D1_CURR_Y_COUNT()    bfin_read16(MDMA2_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_D1_IRQ_STATUS()      bfin_read16(MDMA2_D1_IRQ_STATUS)
-#define bfin_write_MDMA2_D1_IRQ_STATUS(val)  bfin_write16(MDMA2_D1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_D1_PERIPHERAL_MAP()  bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
-#define bfin_read_MDMA2_S1_CONFIG()          bfin_read16(MDMA2_S1_CONFIG)
-#define bfin_write_MDMA2_S1_CONFIG(val)      bfin_write16(MDMA2_S1_CONFIG,val)
-#define bfin_read_MDMA2_S1_NEXT_DESC_PTR()   bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_START_ADDR()      bfin_read32(MDMA2_S1_START_ADDR)
-#define bfin_write_MDMA2_S1_START_ADDR(val)  bfin_write32(MDMA2_S1_START_ADDR,val)
-#define bfin_read_MDMA2_S1_X_COUNT()         bfin_read16(MDMA2_S1_X_COUNT)
-#define bfin_write_MDMA2_S1_X_COUNT(val)     bfin_write16(MDMA2_S1_X_COUNT,val)
-#define bfin_read_MDMA2_S1_Y_COUNT()         bfin_read16(MDMA2_S1_Y_COUNT)
-#define bfin_write_MDMA2_S1_Y_COUNT(val)     bfin_write16(MDMA2_S1_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_X_MODIFY()        bfin_read16(MDMA2_S1_X_MODIFY)
-#define bfin_write_MDMA2_S1_X_MODIFY(val)    bfin_write16(MDMA2_S1_X_MODIFY,val)
-#define bfin_read_MDMA2_S1_Y_MODIFY()        bfin_read16(MDMA2_S1_Y_MODIFY)
-#define bfin_write_MDMA2_S1_Y_MODIFY(val)    bfin_write16(MDMA2_S1_Y_MODIFY,val)
-#define bfin_read_MDMA2_S1_CURR_DESC_PTR()   bfin_read32(MDMA2_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
-#define bfin_read_MDMA2_S1_CURR_ADDR()       bfin_read32(MDMA2_S1_CURR_ADDR)
-#define bfin_write_MDMA2_S1_CURR_ADDR(val)   bfin_write32(MDMA2_S1_CURR_ADDR,val)
-#define bfin_read_MDMA2_S1_CURR_X_COUNT()    bfin_read16(MDMA2_S1_CURR_X_COUNT)
-#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
-#define bfin_read_MDMA2_S1_CURR_Y_COUNT()    bfin_read16(MDMA2_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
-#define bfin_read_MDMA2_S1_IRQ_STATUS()      bfin_read16(MDMA2_S1_IRQ_STATUS)
-#define bfin_write_MDMA2_S1_IRQ_STATUS(val)  bfin_write16(MDMA2_S1_IRQ_STATUS,val)
-#define bfin_read_MDMA2_S1_PERIPHERAL_MAP()  bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define bfin_read_IMDMA_D0_CONFIG()          bfin_read16(IMDMA_D0_CONFIG)
-#define bfin_write_IMDMA_D0_CONFIG(val)      bfin_write16(IMDMA_D0_CONFIG,val)
-#define bfin_read_IMDMA_D0_NEXT_DESC_PTR()   bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_START_ADDR()      bfin_read32(IMDMA_D0_START_ADDR)
-#define bfin_write_IMDMA_D0_START_ADDR(val)  bfin_write32(IMDMA_D0_START_ADDR,val)
-#define bfin_read_IMDMA_D0_X_COUNT()         bfin_read16(IMDMA_D0_X_COUNT)
-#define bfin_write_IMDMA_D0_X_COUNT(val)     bfin_write16(IMDMA_D0_X_COUNT,val)
-#define bfin_read_IMDMA_D0_Y_COUNT()         bfin_read16(IMDMA_D0_Y_COUNT)
-#define bfin_write_IMDMA_D0_Y_COUNT(val)     bfin_write16(IMDMA_D0_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_X_MODIFY()        bfin_read16(IMDMA_D0_X_MODIFY)
-#define bfin_write_IMDMA_D0_X_MODIFY(val)    bfin_write16(IMDMA_D0_X_MODIFY,val)
-#define bfin_read_IMDMA_D0_Y_MODIFY()        bfin_read16(IMDMA_D0_Y_MODIFY)
-#define bfin_write_IMDMA_D0_Y_MODIFY(val)    bfin_write16(IMDMA_D0_Y_MODIFY,val)
-#define bfin_read_IMDMA_D0_CURR_DESC_PTR()   bfin_read32(IMDMA_D0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D0_CURR_ADDR()       bfin_read32(IMDMA_D0_CURR_ADDR)
-#define bfin_write_IMDMA_D0_CURR_ADDR(val)   bfin_write32(IMDMA_D0_CURR_ADDR,val)
-#define bfin_read_IMDMA_D0_CURR_X_COUNT()    bfin_read16(IMDMA_D0_CURR_X_COUNT)
-#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D0_CURR_Y_COUNT()    bfin_read16(IMDMA_D0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D0_IRQ_STATUS()      bfin_read16(IMDMA_D0_IRQ_STATUS)
-#define bfin_write_IMDMA_D0_IRQ_STATUS(val)  bfin_write16(IMDMA_D0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S0_CONFIG()          bfin_read16(IMDMA_S0_CONFIG)
-#define bfin_write_IMDMA_S0_CONFIG(val)      bfin_write16(IMDMA_S0_CONFIG,val)
-#define bfin_read_IMDMA_S0_NEXT_DESC_PTR()   bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_START_ADDR()      bfin_read32(IMDMA_S0_START_ADDR)
-#define bfin_write_IMDMA_S0_START_ADDR(val)  bfin_write32(IMDMA_S0_START_ADDR,val)
-#define bfin_read_IMDMA_S0_X_COUNT()         bfin_read16(IMDMA_S0_X_COUNT)
-#define bfin_write_IMDMA_S0_X_COUNT(val)     bfin_write16(IMDMA_S0_X_COUNT,val)
-#define bfin_read_IMDMA_S0_Y_COUNT()         bfin_read16(IMDMA_S0_Y_COUNT)
-#define bfin_write_IMDMA_S0_Y_COUNT(val)     bfin_write16(IMDMA_S0_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_X_MODIFY()        bfin_read16(IMDMA_S0_X_MODIFY)
-#define bfin_write_IMDMA_S0_X_MODIFY(val)    bfin_write16(IMDMA_S0_X_MODIFY,val)
-#define bfin_read_IMDMA_S0_Y_MODIFY()        bfin_read16(IMDMA_S0_Y_MODIFY)
-#define bfin_write_IMDMA_S0_Y_MODIFY(val)    bfin_write16(IMDMA_S0_Y_MODIFY,val)
-#define bfin_read_IMDMA_S0_CURR_DESC_PTR()   bfin_read32(IMDMA_S0_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S0_CURR_ADDR()       bfin_read32(IMDMA_S0_CURR_ADDR)
-#define bfin_write_IMDMA_S0_CURR_ADDR(val)   bfin_write32(IMDMA_S0_CURR_ADDR,val)
-#define bfin_read_IMDMA_S0_CURR_X_COUNT()    bfin_read16(IMDMA_S0_CURR_X_COUNT)
-#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S0_CURR_Y_COUNT()    bfin_read16(IMDMA_S0_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S0_IRQ_STATUS()      bfin_read16(IMDMA_S0_IRQ_STATUS)
-#define bfin_write_IMDMA_S0_IRQ_STATUS(val)  bfin_write16(IMDMA_S0_IRQ_STATUS,val)
-#define bfin_read_IMDMA_D1_CONFIG()          bfin_read16(IMDMA_D1_CONFIG)
-#define bfin_write_IMDMA_D1_CONFIG(val)      bfin_write16(IMDMA_D1_CONFIG,val)
-#define bfin_read_IMDMA_D1_NEXT_DESC_PTR()   bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_START_ADDR()      bfin_read32(IMDMA_D1_START_ADDR)
-#define bfin_write_IMDMA_D1_START_ADDR(val)  bfin_write32(IMDMA_D1_START_ADDR,val)
-#define bfin_read_IMDMA_D1_X_COUNT()         bfin_read16(IMDMA_D1_X_COUNT)
-#define bfin_write_IMDMA_D1_X_COUNT(val)     bfin_write16(IMDMA_D1_X_COUNT,val)
-#define bfin_read_IMDMA_D1_Y_COUNT()         bfin_read16(IMDMA_D1_Y_COUNT)
-#define bfin_write_IMDMA_D1_Y_COUNT(val)     bfin_write16(IMDMA_D1_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_X_MODIFY()        bfin_read16(IMDMA_D1_X_MODIFY)
-#define bfin_write_IMDMA_D1_X_MODIFY(val)    bfin_write16(IMDMA_D1_X_MODIFY,val)
-#define bfin_read_IMDMA_D1_Y_MODIFY()        bfin_read16(IMDMA_D1_Y_MODIFY)
-#define bfin_write_IMDMA_D1_Y_MODIFY(val)    bfin_write16(IMDMA_D1_Y_MODIFY,val)
-#define bfin_read_IMDMA_D1_CURR_DESC_PTR()   bfin_read32(IMDMA_D1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_D1_CURR_ADDR()       bfin_read32(IMDMA_D1_CURR_ADDR)
-#define bfin_write_IMDMA_D1_CURR_ADDR(val)   bfin_write32(IMDMA_D1_CURR_ADDR,val)
-#define bfin_read_IMDMA_D1_CURR_X_COUNT()    bfin_read16(IMDMA_D1_CURR_X_COUNT)
-#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_D1_CURR_Y_COUNT()    bfin_read16(IMDMA_D1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_D1_IRQ_STATUS()      bfin_read16(IMDMA_D1_IRQ_STATUS)
-#define bfin_write_IMDMA_D1_IRQ_STATUS(val)  bfin_write16(IMDMA_D1_IRQ_STATUS,val)
-#define bfin_read_IMDMA_S1_CONFIG()          bfin_read16(IMDMA_S1_CONFIG)
-#define bfin_write_IMDMA_S1_CONFIG(val)      bfin_write16(IMDMA_S1_CONFIG,val)
-#define bfin_read_IMDMA_S1_NEXT_DESC_PTR()   bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_START_ADDR()      bfin_read32(IMDMA_S1_START_ADDR)
-#define bfin_write_IMDMA_S1_START_ADDR(val)  bfin_write32(IMDMA_S1_START_ADDR,val)
-#define bfin_read_IMDMA_S1_X_COUNT()         bfin_read16(IMDMA_S1_X_COUNT)
-#define bfin_write_IMDMA_S1_X_COUNT(val)     bfin_write16(IMDMA_S1_X_COUNT,val)
-#define bfin_read_IMDMA_S1_Y_COUNT()         bfin_read16(IMDMA_S1_Y_COUNT)
-#define bfin_write_IMDMA_S1_Y_COUNT(val)     bfin_write16(IMDMA_S1_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_X_MODIFY()        bfin_read16(IMDMA_S1_X_MODIFY)
-#define bfin_write_IMDMA_S1_X_MODIFY(val)    bfin_write16(IMDMA_S1_X_MODIFY,val)
-#define bfin_read_IMDMA_S1_Y_MODIFY()        bfin_read16(IMDMA_S1_Y_MODIFY)
-#define bfin_write_IMDMA_S1_Y_MODIFY(val)    bfin_write16(IMDMA_S1_Y_MODIFY,val)
-#define bfin_read_IMDMA_S1_CURR_DESC_PTR()   bfin_read32(IMDMA_S1_CURR_DESC_PTR)
-#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
-#define bfin_read_IMDMA_S1_CURR_ADDR()       bfin_read32(IMDMA_S1_CURR_ADDR)
-#define bfin_write_IMDMA_S1_CURR_ADDR(val)   bfin_write32(IMDMA_S1_CURR_ADDR,val)
-#define bfin_read_IMDMA_S1_CURR_X_COUNT()    bfin_read16(IMDMA_S1_CURR_X_COUNT)
-#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
-#define bfin_read_IMDMA_S1_CURR_Y_COUNT()    bfin_read16(IMDMA_S1_CURR_Y_COUNT)
-#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
-#define bfin_read_IMDMA_S1_IRQ_STATUS()      bfin_read16(IMDMA_S1_IRQ_STATUS)
-#define bfin_write_IMDMA_S1_IRQ_STATUS(val)  bfin_write16(IMDMA_S1_IRQ_STATUS,val)
-
-#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA1_S0_CONFIG()
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
-#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA1_S0_IRQ_STATUS()
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
-#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA1_S0_X_MODIFY()
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
-#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA1_S0_Y_MODIFY()
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
-#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA1_S0_X_COUNT()
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
-#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA1_S0_Y_COUNT()
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
-#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA1_S0_START_ADDR()
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
-#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA1_D0_CONFIG()
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
-#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA1_D0_IRQ_STATUS()
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
-#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA1_D0_X_MODIFY()
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
-#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA1_D0_Y_MODIFY()
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
-#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA1_D0_X_COUNT()
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
-#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA1_D0_Y_COUNT()
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
-#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
-
-#endif                          /* _CDEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
deleted file mode 100644
index 1ab50e906fe7..000000000000
--- a/include/asm-blackfin/mach-bf561/defBF561.h
+++ /dev/null
@@ -1,1758 +0,0 @@
-
-/*
- * File:         include/asm-blackfin/mach-bf561/defBF561.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _DEF_BF561_H
-#define _DEF_BF561_H
-/*
-#if !defined(__ADSPBF561__)
-#warning defBF561.h should only be included for BF561 chip.
-#endif
-*/
-/* include all Core registers and bit definitions */
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/*********************************************************************************** */
-/* System MMR Register Map */
-/*********************************************************************************** */
-
-/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
-
-#define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
-#define PLL_DIV                         0xFFC00004      /* PLL Divide Register (16-bit) */
-#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
-#define CHIPID                 0xFFC00014       /* Chip ID Register */
-
-/* For MMR's that are reserved on Core B, set up defines to better integrate with other ports */
-#define SWRST                   SICA_SWRST
-#define SYSCR                   SICA_SYSCR
-#define DOUBLE_FAULT            (DOUBLE_FAULT_B|DOUBLE_FAULT_A)
-#define RESET_DOUBLE            (SWRST_DBL_FAULT_B|SWRST_DBL_FAULT_A)
-#define RESET_WDOG              (SWRST_WDT_B|SWRST_WDT_A)
-#define RESET_SOFTWARE          (SWRST_OCCURRED)
-
-/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
-#define SICA_SWRST              0xFFC00100      /* Software Reset register */
-#define SICA_SYSCR              0xFFC00104      /* System Reset Configuration register */
-#define SICA_RVECT              0xFFC00108      /* SIC Reset Vector Address Register */
-#define SICA_IMASK              0xFFC0010C      /* SIC Interrupt Mask register 0 - hack to fix old tests */
-#define SICA_IMASK0             0xFFC0010C      /* SIC Interrupt Mask register 0 */
-#define SICA_IMASK1             0xFFC00110      /* SIC Interrupt Mask register 1 */
-#define SICA_IAR0               0xFFC00124      /* SIC Interrupt Assignment Register 0 */
-#define SICA_IAR1               0xFFC00128      /* SIC Interrupt Assignment Register 1 */
-#define SICA_IAR2               0xFFC0012C      /* SIC Interrupt Assignment Register 2 */
-#define SICA_IAR3               0xFFC00130      /* SIC Interrupt Assignment Register 3 */
-#define SICA_IAR4               0xFFC00134      /* SIC Interrupt Assignment Register 4 */
-#define SICA_IAR5               0xFFC00138      /* SIC Interrupt Assignment Register 5 */
-#define SICA_IAR6               0xFFC0013C      /* SIC Interrupt Assignment Register 6 */
-#define SICA_IAR7               0xFFC00140      /* SIC Interrupt Assignment Register 7 */
-#define SICA_ISR0               0xFFC00114      /* SIC Interrupt Status register 0 */
-#define SICA_ISR1               0xFFC00118      /* SIC Interrupt Status register 1 */
-#define SICA_IWR0               0xFFC0011C      /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICA_IWR1               0xFFC00120      /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
-#define SICB_SWRST              0xFFC01100      /* reserved */
-#define SICB_SYSCR              0xFFC01104      /* reserved */
-#define SICB_RVECT              0xFFC01108      /* SIC Reset Vector Address Register */
-#define SICB_IMASK0             0xFFC0110C      /* SIC Interrupt Mask register 0 */
-#define SICB_IMASK1             0xFFC01110      /* SIC Interrupt Mask register 1 */
-#define SICB_IAR0               0xFFC01124      /* SIC Interrupt Assignment Register 0 */
-#define SICB_IAR1               0xFFC01128      /* SIC Interrupt Assignment Register 1 */
-#define SICB_IAR2               0xFFC0112C      /* SIC Interrupt Assignment Register 2 */
-#define SICB_IAR3               0xFFC01130      /* SIC Interrupt Assignment Register 3 */
-#define SICB_IAR4               0xFFC01134      /* SIC Interrupt Assignment Register 4 */
-#define SICB_IAR5               0xFFC01138      /* SIC Interrupt Assignment Register 5 */
-#define SICB_IAR6               0xFFC0113C      /* SIC Interrupt Assignment Register 6 */
-#define SICB_IAR7               0xFFC01140      /* SIC Interrupt Assignment Register 7 */
-#define SICB_ISR0               0xFFC01114      /* SIC Interrupt Status register 0 */
-#define SICB_ISR1               0xFFC01118      /* SIC Interrupt Status register 1 */
-#define SICB_IWR0               0xFFC0111C      /* SIC Interrupt Wakeup-Enable register 0 */
-#define SICB_IWR1               0xFFC01120      /* SIC Interrupt Wakeup-Enable register 1 */
-
-/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
-#define WDOGA_CTL                               0xFFC00200      /* Watchdog Control register */
-#define WDOGA_CNT                               0xFFC00204      /* Watchdog Count register */
-#define WDOGA_STAT                              0xFFC00208      /* Watchdog Status register */
-
-/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
-#define WDOGB_CTL                               0xFFC01200      /* Watchdog Control register */
-#define WDOGB_CNT                               0xFFC01204      /* Watchdog Count register */
-#define WDOGB_STAT                              0xFFC01208      /* Watchdog Status register */
-
-/* UART Controller (0xFFC00400 - 0xFFC004FF) */
-
-/*
- * Because include/linux/serial_reg.h have defined UART_*,
- * So we define blackfin uart regs to BFIN_UART0_*.
- */
-#define BFIN_UART_THR                   0xFFC00400  /* Transmit Holding register */
-#define BFIN_UART_RBR                   0xFFC00400  /* Receive Buffer register */
-#define BFIN_UART_DLL                   0xFFC00400  /* Divisor Latch (Low-Byte) */
-#define BFIN_UART_IER                   0xFFC00404  /* Interrupt Enable Register */
-#define BFIN_UART_DLH                   0xFFC00404  /* Divisor Latch (High-Byte) */
-#define BFIN_UART_IIR                   0xFFC00408  /* Interrupt Identification Register */
-#define BFIN_UART_LCR                   0xFFC0040C  /* Line Control Register */
-#define BFIN_UART_MCR                   0xFFC00410  /* Modem Control Register */
-#define BFIN_UART_LSR                   0xFFC00414  /* Line Status Register */
-#define BFIN_UART_MSR                   0xFFC00418  /* Modem Status Register */
-#define BFIN_UART_SCR                   0xFFC0041C  /* SCR Scratch Register */
-#define BFIN_UART_GCTL                  0xFFC00424  /* Global Control Register */
-
-/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
-#define SPI0_REGBASE                    0xFFC00500
-#define SPI_CTL                         0xFFC00500      /* SPI Control Register */
-#define SPI_FLG                         0xFFC00504      /* SPI Flag register */
-#define SPI_STAT                        0xFFC00508      /* SPI Status register */
-#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
-#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
-
-/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
-#define TIMER0_CONFIG                           0xFFC00600      /* Timer0 Configuration register */
-#define TIMER0_COUNTER                          0xFFC00604      /* Timer0 Counter register */
-#define TIMER0_PERIOD                           0xFFC00608      /* Timer0 Period register */
-#define TIMER0_WIDTH                            0xFFC0060C      /* Timer0 Width register */
-
-#define TIMER1_CONFIG                           0xFFC00610      /* Timer1 Configuration register */
-#define TIMER1_COUNTER                          0xFFC00614      /* Timer1 Counter register */
-#define TIMER1_PERIOD                           0xFFC00618      /* Timer1 Period register */
-#define TIMER1_WIDTH                            0xFFC0061C      /* Timer1 Width register */
-
-#define TIMER2_CONFIG                           0xFFC00620      /* Timer2 Configuration register */
-#define TIMER2_COUNTER                          0xFFC00624      /* Timer2 Counter register */
-#define TIMER2_PERIOD                           0xFFC00628      /* Timer2 Period register */
-#define TIMER2_WIDTH                            0xFFC0062C      /* Timer2 Width register */
-
-#define TIMER3_CONFIG                           0xFFC00630      /* Timer3 Configuration register */
-#define TIMER3_COUNTER                          0xFFC00634      /* Timer3 Counter register */
-#define TIMER3_PERIOD                           0xFFC00638      /* Timer3 Period register */
-#define TIMER3_WIDTH                            0xFFC0063C      /* Timer3 Width register */
-
-#define TIMER4_CONFIG                           0xFFC00640      /* Timer4 Configuration register */
-#define TIMER4_COUNTER                          0xFFC00644      /* Timer4 Counter register */
-#define TIMER4_PERIOD                           0xFFC00648      /* Timer4 Period register */
-#define TIMER4_WIDTH                            0xFFC0064C      /* Timer4 Width register */
-
-#define TIMER5_CONFIG                           0xFFC00650      /* Timer5 Configuration register */
-#define TIMER5_COUNTER                          0xFFC00654      /* Timer5 Counter register */
-#define TIMER5_PERIOD                           0xFFC00658      /* Timer5 Period register */
-#define TIMER5_WIDTH                            0xFFC0065C      /* Timer5 Width register */
-
-#define TIMER6_CONFIG                           0xFFC00660      /* Timer6 Configuration register */
-#define TIMER6_COUNTER                          0xFFC00664      /* Timer6 Counter register */
-#define TIMER6_PERIOD                           0xFFC00668      /* Timer6 Period register */
-#define TIMER6_WIDTH                            0xFFC0066C      /* Timer6 Width register */
-
-#define TIMER7_CONFIG                           0xFFC00670      /* Timer7 Configuration register */
-#define TIMER7_COUNTER                          0xFFC00674      /* Timer7 Counter register */
-#define TIMER7_PERIOD                           0xFFC00678      /* Timer7 Period register */
-#define TIMER7_WIDTH                            0xFFC0067C      /* Timer7 Width register */
-
-#define TMRS8_ENABLE                            0xFFC00680      /* Timer Enable Register */
-#define TMRS8_DISABLE                           0xFFC00684      /* Timer Disable register */
-#define TMRS8_STATUS                            0xFFC00688      /* Timer Status register */
-
-/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
-#define TIMER8_CONFIG                           0xFFC01600      /* Timer8 Configuration register */
-#define TIMER8_COUNTER                          0xFFC01604      /* Timer8 Counter register */
-#define TIMER8_PERIOD                           0xFFC01608      /* Timer8 Period register */
-#define TIMER8_WIDTH                            0xFFC0160C      /* Timer8 Width register */
-
-#define TIMER9_CONFIG                           0xFFC01610      /* Timer9 Configuration register */
-#define TIMER9_COUNTER                          0xFFC01614      /* Timer9 Counter register */
-#define TIMER9_PERIOD                           0xFFC01618      /* Timer9 Period register */
-#define TIMER9_WIDTH                            0xFFC0161C      /* Timer9 Width register */
-
-#define TIMER10_CONFIG                          0xFFC01620      /* Timer10 Configuration register */
-#define TIMER10_COUNTER                         0xFFC01624      /* Timer10 Counter register */
-#define TIMER10_PERIOD                          0xFFC01628      /* Timer10 Period register */
-#define TIMER10_WIDTH                           0xFFC0162C      /* Timer10 Width register */
-
-#define TIMER11_CONFIG                          0xFFC01630      /* Timer11 Configuration register */
-#define TIMER11_COUNTER                         0xFFC01634      /* Timer11 Counter register */
-#define TIMER11_PERIOD                          0xFFC01638      /* Timer11 Period register */
-#define TIMER11_WIDTH                           0xFFC0163C      /* Timer11 Width register */
-
-#define TMRS4_ENABLE                            0xFFC01640      /* Timer Enable Register */
-#define TMRS4_DISABLE                           0xFFC01644      /* Timer Disable register */
-#define TMRS4_STATUS                            0xFFC01648      /* Timer Status register */
-
-/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
-#define FIO0_FLAG_D                             0xFFC00700      /* Flag Data register */
-#define FIO0_FLAG_C                             0xFFC00704      /* Flag Clear register */
-#define FIO0_FLAG_S                             0xFFC00708      /* Flag Set register */
-#define FIO0_FLAG_T                             0xFFC0070C      /* Flag Toggle register */
-#define FIO0_MASKA_D                            0xFFC00710      /* Flag Mask Interrupt A Data register */
-#define FIO0_MASKA_C                            0xFFC00714      /* Flag Mask Interrupt A Clear register */
-#define FIO0_MASKA_S                            0xFFC00718      /* Flag Mask Interrupt A Set register */
-#define FIO0_MASKA_T                            0xFFC0071C      /* Flag Mask Interrupt A Toggle register */
-#define FIO0_MASKB_D                            0xFFC00720      /* Flag Mask Interrupt B Data register */
-#define FIO0_MASKB_C                            0xFFC00724      /* Flag Mask Interrupt B Clear register */
-#define FIO0_MASKB_S                            0xFFC00728      /* Flag Mask Interrupt B Set register */
-#define FIO0_MASKB_T                            0xFFC0072C      /* Flag Mask Interrupt B Toggle register */
-#define FIO0_DIR                                        0xFFC00730      /* Flag Direction register */
-#define FIO0_POLAR                                      0xFFC00734      /* Flag Polarity register */
-#define FIO0_EDGE                                       0xFFC00738      /* Flag Interrupt Sensitivity register */
-#define FIO0_BOTH                                       0xFFC0073C      /* Flag Set on Both Edges register */
-#define FIO0_INEN                                       0xFFC00740      /* Flag Input Enable register */
-
-/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
-#define FIO1_FLAG_D                             0xFFC01500      /* Flag Data register (mask used to directly */
-#define FIO1_FLAG_C                             0xFFC01504      /* Flag Clear register */
-#define FIO1_FLAG_S                             0xFFC01508      /* Flag Set register */
-#define FIO1_FLAG_T                             0xFFC0150C      /* Flag Toggle register (mask used to */
-#define FIO1_MASKA_D                            0xFFC01510      /* Flag Mask Interrupt A Data register */
-#define FIO1_MASKA_C                            0xFFC01514      /* Flag Mask Interrupt A Clear register */
-#define FIO1_MASKA_S                            0xFFC01518      /* Flag Mask Interrupt A Set register */
-#define FIO1_MASKA_T                            0xFFC0151C      /* Flag Mask Interrupt A Toggle register */
-#define FIO1_MASKB_D                            0xFFC01520      /* Flag Mask Interrupt B Data register */
-#define FIO1_MASKB_C                            0xFFC01524      /* Flag Mask Interrupt B Clear register */
-#define FIO1_MASKB_S                            0xFFC01528      /* Flag Mask Interrupt B Set register */
-#define FIO1_MASKB_T                            0xFFC0152C      /* Flag Mask Interrupt B Toggle register */
-#define FIO1_DIR                                        0xFFC01530      /* Flag Direction register */
-#define FIO1_POLAR                                      0xFFC01534      /* Flag Polarity register */
-#define FIO1_EDGE                                       0xFFC01538      /* Flag Interrupt Sensitivity register */
-#define FIO1_BOTH                                       0xFFC0153C      /* Flag Set on Both Edges register */
-#define FIO1_INEN                                       0xFFC01540      /* Flag Input Enable register */
-
-/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
-#define FIO2_FLAG_D                             0xFFC01700      /* Flag Data register (mask used to directly */
-#define FIO2_FLAG_C                             0xFFC01704      /* Flag Clear register */
-#define FIO2_FLAG_S                             0xFFC01708      /* Flag Set register */
-#define FIO2_FLAG_T                             0xFFC0170C      /* Flag Toggle register (mask used to */
-#define FIO2_MASKA_D                            0xFFC01710      /* Flag Mask Interrupt A Data register */
-#define FIO2_MASKA_C                            0xFFC01714      /* Flag Mask Interrupt A Clear register */
-#define FIO2_MASKA_S                            0xFFC01718      /* Flag Mask Interrupt A Set register */
-#define FIO2_MASKA_T                            0xFFC0171C      /* Flag Mask Interrupt A Toggle register */
-#define FIO2_MASKB_D                            0xFFC01720      /* Flag Mask Interrupt B Data register */
-#define FIO2_MASKB_C                            0xFFC01724      /* Flag Mask Interrupt B Clear register */
-#define FIO2_MASKB_S                            0xFFC01728      /* Flag Mask Interrupt B Set register */
-#define FIO2_MASKB_T                            0xFFC0172C      /* Flag Mask Interrupt B Toggle register */
-#define FIO2_DIR                                        0xFFC01730      /* Flag Direction register */
-#define FIO2_POLAR                                      0xFFC01734      /* Flag Polarity register */
-#define FIO2_EDGE                                       0xFFC01738      /* Flag Interrupt Sensitivity register */
-#define FIO2_BOTH                                       0xFFC0173C      /* Flag Set on Both Edges register */
-#define FIO2_INEN                                       0xFFC01740      /* Flag Input Enable register */
-
-/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
-#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
-#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                             0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                             0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
-#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
-
-/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
-#define SPORT1_TCR1                             0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                             0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
-#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                             0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                             0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
-#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
-
-/* Asynchronous Memory Controller - External Bus Interface Unit  */
-#define EBIU_AMGCTL                                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
-
-/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
-#define EBIU_SDGCTL                                     0xFFC00A10      /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                                     0xFFC00A14      /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                                     0xFFC00A1C      /* SDRAM Status Register */
-
-/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
-#define PPI0_CONTROL                            0xFFC01000      /* PPI0 Control register */
-#define PPI0_STATUS                             0xFFC01004      /* PPI0 Status register */
-#define PPI0_COUNT                                      0xFFC01008      /* PPI0 Transfer Count register */
-#define PPI0_DELAY                                      0xFFC0100C      /* PPI0 Delay Count register */
-#define PPI0_FRAME                                      0xFFC01010      /* PPI0 Frame Length register */
-
-/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
-#define PPI1_CONTROL                            0xFFC01300      /* PPI1 Control register */
-#define PPI1_STATUS                             0xFFC01304      /* PPI1 Status register */
-#define PPI1_COUNT                                      0xFFC01308      /* PPI1 Transfer Count register */
-#define PPI1_DELAY                                      0xFFC0130C      /* PPI1 Delay Count register */
-#define PPI1_FRAME                                      0xFFC01310      /* PPI1 Frame Length register */
-
-/*DMA traffic control registers */
-#define DMA1_TC_PER  0xFFC01B0C /* Traffic control periods */
-#define DMA1_TC_CNT  0xFFC01B10 /* Traffic control current counts */
-#define DMA2_TC_PER  0xFFC00B0C /* Traffic control periods */
-#define DMA2_TC_CNT  0xFFC00B10 /* Traffic control current counts        */
-
-/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
-#define DMA1_0_CONFIG 0xFFC01C08        /* DMA1 Channel 0 Configuration register */
-#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
-#define DMA1_0_START_ADDR 0xFFC01C04    /* DMA1 Channel 0 Start Address */
-#define DMA1_0_X_COUNT 0xFFC01C10       /* DMA1 Channel 0 Inner Loop Count */
-#define DMA1_0_Y_COUNT 0xFFC01C18       /* DMA1 Channel 0 Outer Loop Count */
-#define DMA1_0_X_MODIFY 0xFFC01C14      /* DMA1 Channel 0 Inner Loop Addr Increment */
-#define DMA1_0_Y_MODIFY 0xFFC01C1C      /* DMA1 Channel 0 Outer Loop Addr Increment */
-#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
-#define DMA1_0_CURR_ADDR 0xFFC01C24     /* DMA1 Channel 0 Current Address Pointer */
-#define DMA1_0_CURR_X_COUNT 0xFFC01C30  /* DMA1 Channel 0 Current Inner Loop Count */
-#define DMA1_0_CURR_Y_COUNT 0xFFC01C38  /* DMA1 Channel 0 Current Outer Loop Count */
-#define DMA1_0_IRQ_STATUS 0xFFC01C28    /* DMA1 Channel 0 Interrupt/Status Register */
-#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C        /* DMA1 Channel 0 Peripheral Map Register */
-
-#define DMA1_1_CONFIG 0xFFC01C48        /* DMA1 Channel 1 Configuration register */
-#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
-#define DMA1_1_START_ADDR 0xFFC01C44    /* DMA1 Channel 1 Start Address */
-#define DMA1_1_X_COUNT 0xFFC01C50       /* DMA1 Channel 1 Inner Loop Count */
-#define DMA1_1_Y_COUNT 0xFFC01C58       /* DMA1 Channel 1 Outer Loop Count */
-#define DMA1_1_X_MODIFY 0xFFC01C54      /* DMA1 Channel 1 Inner Loop Addr Increment */
-#define DMA1_1_Y_MODIFY 0xFFC01C5C      /* DMA1 Channel 1 Outer Loop Addr Increment */
-#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
-#define DMA1_1_CURR_ADDR 0xFFC01C64     /* DMA1 Channel 1 Current Address Pointer */
-#define DMA1_1_CURR_X_COUNT 0xFFC01C70  /* DMA1 Channel 1 Current Inner Loop Count */
-#define DMA1_1_CURR_Y_COUNT 0xFFC01C78  /* DMA1 Channel 1 Current Outer Loop Count */
-#define DMA1_1_IRQ_STATUS 0xFFC01C68    /* DMA1 Channel 1 Interrupt/Status Register */
-#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C        /* DMA1 Channel 1 Peripheral Map Register */
-
-#define DMA1_2_CONFIG 0xFFC01C88        /* DMA1 Channel 2 Configuration register */
-#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
-#define DMA1_2_START_ADDR 0xFFC01C84    /* DMA1 Channel 2 Start Address */
-#define DMA1_2_X_COUNT 0xFFC01C90       /* DMA1 Channel 2 Inner Loop Count */
-#define DMA1_2_Y_COUNT 0xFFC01C98       /* DMA1 Channel 2 Outer Loop Count */
-#define DMA1_2_X_MODIFY 0xFFC01C94      /* DMA1 Channel 2 Inner Loop Addr Increment */
-#define DMA1_2_Y_MODIFY 0xFFC01C9C      /* DMA1 Channel 2 Outer Loop Addr Increment */
-#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
-#define DMA1_2_CURR_ADDR 0xFFC01CA4     /* DMA1 Channel 2 Current Address Pointer */
-#define DMA1_2_CURR_X_COUNT 0xFFC01CB0  /* DMA1 Channel 2 Current Inner Loop Count */
-#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8  /* DMA1 Channel 2 Current Outer Loop Count */
-#define DMA1_2_IRQ_STATUS 0xFFC01CA8    /* DMA1 Channel 2 Interrupt/Status Register */
-#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC        /* DMA1 Channel 2 Peripheral Map Register */
-
-#define DMA1_3_CONFIG 0xFFC01CC8        /* DMA1 Channel 3 Configuration register */
-#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
-#define DMA1_3_START_ADDR 0xFFC01CC4    /* DMA1 Channel 3 Start Address */
-#define DMA1_3_X_COUNT 0xFFC01CD0       /* DMA1 Channel 3 Inner Loop Count */
-#define DMA1_3_Y_COUNT 0xFFC01CD8       /* DMA1 Channel 3 Outer Loop Count */
-#define DMA1_3_X_MODIFY 0xFFC01CD4      /* DMA1 Channel 3 Inner Loop Addr Increment */
-#define DMA1_3_Y_MODIFY 0xFFC01CDC      /* DMA1 Channel 3 Outer Loop Addr Increment */
-#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
-#define DMA1_3_CURR_ADDR 0xFFC01CE4     /* DMA1 Channel 3 Current Address Pointer */
-#define DMA1_3_CURR_X_COUNT 0xFFC01CF0  /* DMA1 Channel 3 Current Inner Loop Count */
-#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8  /* DMA1 Channel 3 Current Outer Loop Count */
-#define DMA1_3_IRQ_STATUS 0xFFC01CE8    /* DMA1 Channel 3 Interrupt/Status Register */
-#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC        /* DMA1 Channel 3 Peripheral Map Register */
-
-#define DMA1_4_CONFIG 0xFFC01D08        /* DMA1 Channel 4 Configuration register */
-#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
-#define DMA1_4_START_ADDR 0xFFC01D04    /* DMA1 Channel 4 Start Address */
-#define DMA1_4_X_COUNT 0xFFC01D10       /* DMA1 Channel 4 Inner Loop Count */
-#define DMA1_4_Y_COUNT 0xFFC01D18       /* DMA1 Channel 4 Outer Loop Count */
-#define DMA1_4_X_MODIFY 0xFFC01D14      /* DMA1 Channel 4 Inner Loop Addr Increment */
-#define DMA1_4_Y_MODIFY 0xFFC01D1C      /* DMA1 Channel 4 Outer Loop Addr Increment */
-#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
-#define DMA1_4_CURR_ADDR 0xFFC01D24     /* DMA1 Channel 4 Current Address Pointer */
-#define DMA1_4_CURR_X_COUNT 0xFFC01D30  /* DMA1 Channel 4 Current Inner Loop Count */
-#define DMA1_4_CURR_Y_COUNT 0xFFC01D38  /* DMA1 Channel 4 Current Outer Loop Count */
-#define DMA1_4_IRQ_STATUS 0xFFC01D28    /* DMA1 Channel 4 Interrupt/Status Register */
-#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C        /* DMA1 Channel 4 Peripheral Map Register */
-
-#define DMA1_5_CONFIG 0xFFC01D48        /* DMA1 Channel 5 Configuration register */
-#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
-#define DMA1_5_START_ADDR 0xFFC01D44    /* DMA1 Channel 5 Start Address */
-#define DMA1_5_X_COUNT 0xFFC01D50       /* DMA1 Channel 5 Inner Loop Count */
-#define DMA1_5_Y_COUNT 0xFFC01D58       /* DMA1 Channel 5 Outer Loop Count */
-#define DMA1_5_X_MODIFY 0xFFC01D54      /* DMA1 Channel 5 Inner Loop Addr Increment */
-#define DMA1_5_Y_MODIFY 0xFFC01D5C      /* DMA1 Channel 5 Outer Loop Addr Increment */
-#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
-#define DMA1_5_CURR_ADDR 0xFFC01D64     /* DMA1 Channel 5 Current Address Pointer */
-#define DMA1_5_CURR_X_COUNT 0xFFC01D70  /* DMA1 Channel 5 Current Inner Loop Count */
-#define DMA1_5_CURR_Y_COUNT 0xFFC01D78  /* DMA1 Channel 5 Current Outer Loop Count */
-#define DMA1_5_IRQ_STATUS 0xFFC01D68    /* DMA1 Channel 5 Interrupt/Status Register */
-#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C        /* DMA1 Channel 5 Peripheral Map Register */
-
-#define DMA1_6_CONFIG 0xFFC01D88        /* DMA1 Channel 6 Configuration register */
-#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
-#define DMA1_6_START_ADDR 0xFFC01D84    /* DMA1 Channel 6 Start Address */
-#define DMA1_6_X_COUNT 0xFFC01D90       /* DMA1 Channel 6 Inner Loop Count */
-#define DMA1_6_Y_COUNT 0xFFC01D98       /* DMA1 Channel 6 Outer Loop Count */
-#define DMA1_6_X_MODIFY 0xFFC01D94      /* DMA1 Channel 6 Inner Loop Addr Increment */
-#define DMA1_6_Y_MODIFY 0xFFC01D9C      /* DMA1 Channel 6 Outer Loop Addr Increment */
-#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
-#define DMA1_6_CURR_ADDR 0xFFC01DA4     /* DMA1 Channel 6 Current Address Pointer */
-#define DMA1_6_CURR_X_COUNT 0xFFC01DB0  /* DMA1 Channel 6 Current Inner Loop Count */
-#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8  /* DMA1 Channel 6 Current Outer Loop Count */
-#define DMA1_6_IRQ_STATUS 0xFFC01DA8    /* DMA1 Channel 6 Interrupt/Status Register */
-#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC        /* DMA1 Channel 6 Peripheral Map Register */
-
-#define DMA1_7_CONFIG 0xFFC01DC8        /* DMA1 Channel 7 Configuration register */
-#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
-#define DMA1_7_START_ADDR 0xFFC01DC4    /* DMA1 Channel 7 Start Address */
-#define DMA1_7_X_COUNT 0xFFC01DD0       /* DMA1 Channel 7 Inner Loop Count */
-#define DMA1_7_Y_COUNT 0xFFC01DD8       /* DMA1 Channel 7 Outer Loop Count */
-#define DMA1_7_X_MODIFY 0xFFC01DD4      /* DMA1 Channel 7 Inner Loop Addr Increment */
-#define DMA1_7_Y_MODIFY 0xFFC01DDC      /* DMA1 Channel 7 Outer Loop Addr Increment */
-#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
-#define DMA1_7_CURR_ADDR 0xFFC01DE4     /* DMA1 Channel 7 Current Address Pointer */
-#define DMA1_7_CURR_X_COUNT 0xFFC01DF0  /* DMA1 Channel 7 Current Inner Loop Count */
-#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8  /* DMA1 Channel 7 Current Outer Loop Count */
-#define DMA1_7_IRQ_STATUS 0xFFC01DE8    /* DMA1 Channel 7 Interrupt/Status Register */
-#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC        /* DMA1 Channel 7 Peripheral Map Register */
-
-#define DMA1_8_CONFIG 0xFFC01E08        /* DMA1 Channel 8 Configuration register */
-#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
-#define DMA1_8_START_ADDR 0xFFC01E04    /* DMA1 Channel 8 Start Address */
-#define DMA1_8_X_COUNT 0xFFC01E10       /* DMA1 Channel 8 Inner Loop Count */
-#define DMA1_8_Y_COUNT 0xFFC01E18       /* DMA1 Channel 8 Outer Loop Count */
-#define DMA1_8_X_MODIFY 0xFFC01E14      /* DMA1 Channel 8 Inner Loop Addr Increment */
-#define DMA1_8_Y_MODIFY 0xFFC01E1C      /* DMA1 Channel 8 Outer Loop Addr Increment */
-#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
-#define DMA1_8_CURR_ADDR 0xFFC01E24     /* DMA1 Channel 8 Current Address Pointer */
-#define DMA1_8_CURR_X_COUNT 0xFFC01E30  /* DMA1 Channel 8 Current Inner Loop Count */
-#define DMA1_8_CURR_Y_COUNT 0xFFC01E38  /* DMA1 Channel 8 Current Outer Loop Count */
-#define DMA1_8_IRQ_STATUS 0xFFC01E28    /* DMA1 Channel 8 Interrupt/Status Register */
-#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C        /* DMA1 Channel 8 Peripheral Map Register */
-
-#define DMA1_9_CONFIG 0xFFC01E48        /* DMA1 Channel 9 Configuration register */
-#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
-#define DMA1_9_START_ADDR 0xFFC01E44    /* DMA1 Channel 9 Start Address */
-#define DMA1_9_X_COUNT 0xFFC01E50       /* DMA1 Channel 9 Inner Loop Count */
-#define DMA1_9_Y_COUNT 0xFFC01E58       /* DMA1 Channel 9 Outer Loop Count */
-#define DMA1_9_X_MODIFY 0xFFC01E54      /* DMA1 Channel 9 Inner Loop Addr Increment */
-#define DMA1_9_Y_MODIFY 0xFFC01E5C      /* DMA1 Channel 9 Outer Loop Addr Increment */
-#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
-#define DMA1_9_CURR_ADDR 0xFFC01E64     /* DMA1 Channel 9 Current Address Pointer */
-#define DMA1_9_CURR_X_COUNT 0xFFC01E70  /* DMA1 Channel 9 Current Inner Loop Count */
-#define DMA1_9_CURR_Y_COUNT 0xFFC01E78  /* DMA1 Channel 9 Current Outer Loop Count */
-#define DMA1_9_IRQ_STATUS 0xFFC01E68    /* DMA1 Channel 9 Interrupt/Status Register */
-#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C        /* DMA1 Channel 9 Peripheral Map Register */
-
-#define DMA1_10_CONFIG 0xFFC01E88       /* DMA1 Channel 10 Configuration register */
-#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80        /* DMA1 Channel 10 Next Descripter Ptr Reg */
-#define DMA1_10_START_ADDR 0xFFC01E84   /* DMA1 Channel 10 Start Address */
-#define DMA1_10_X_COUNT 0xFFC01E90      /* DMA1 Channel 10 Inner Loop Count */
-#define DMA1_10_Y_COUNT 0xFFC01E98      /* DMA1 Channel 10 Outer Loop Count */
-#define DMA1_10_X_MODIFY 0xFFC01E94     /* DMA1 Channel 10 Inner Loop Addr Increment */
-#define DMA1_10_Y_MODIFY 0xFFC01E9C     /* DMA1 Channel 10 Outer Loop Addr Increment */
-#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0        /* DMA1 Channel 10 Current Descriptor Pointer */
-#define DMA1_10_CURR_ADDR 0xFFC01EA4    /* DMA1 Channel 10 Current Address Pointer */
-#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
-#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
-#define DMA1_10_IRQ_STATUS 0xFFC01EA8   /* DMA1 Channel 10 Interrupt/Status Register */
-#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC       /* DMA1 Channel 10 Peripheral Map Register */
-
-#define DMA1_11_CONFIG 0xFFC01EC8       /* DMA1 Channel 11 Configuration register */
-#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0        /* DMA1 Channel 11 Next Descripter Ptr Reg */
-#define DMA1_11_START_ADDR 0xFFC01EC4   /* DMA1 Channel 11 Start Address */
-#define DMA1_11_X_COUNT 0xFFC01ED0      /* DMA1 Channel 11 Inner Loop Count */
-#define DMA1_11_Y_COUNT 0xFFC01ED8      /* DMA1 Channel 11 Outer Loop Count */
-#define DMA1_11_X_MODIFY 0xFFC01ED4     /* DMA1 Channel 11 Inner Loop Addr Increment */
-#define DMA1_11_Y_MODIFY 0xFFC01EDC     /* DMA1 Channel 11 Outer Loop Addr Increment */
-#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0        /* DMA1 Channel 11 Current Descriptor Pointer */
-#define DMA1_11_CURR_ADDR 0xFFC01EE4    /* DMA1 Channel 11 Current Address Pointer */
-#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
-#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
-#define DMA1_11_IRQ_STATUS 0xFFC01EE8   /* DMA1 Channel 11 Interrupt/Status Register */
-#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
-
-/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
-#define MDMA1_D0_CONFIG 0xFFC01F08      /*MemDMA1 Stream 0 Destination Configuration */
-#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00       /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D0_START_ADDR 0xFFC01F04  /*MemDMA1 Stream 0 Destination Start Address */
-#define MDMA1_D0_X_COUNT 0xFFC01F10     /*MemDMA1 Stream 0 Destination Inner-Loop Count */
-#define MDMA1_D0_Y_COUNT 0xFFC01F18     /*MemDMA1 Stream 0 Destination Outer-Loop Count */
-#define MDMA1_D0_X_MODIFY 0xFFC01F14    /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA1_D0_Y_MODIFY 0xFFC01F1C    /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20       /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA1_D0_CURR_ADDR 0xFFC01F24   /*MemDMA1 Stream 0 Destination Current Address */
-#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30        /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
-#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38        /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
-#define MDMA1_D0_IRQ_STATUS 0xFFC01F28  /*MemDMA1 Stream 0 Destination Interrupt/Status */
-#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /*MemDMA1 Stream 0 Destination Peripheral Map */
-
-#define MDMA1_S0_CONFIG 0xFFC01F48      /*MemDMA1 Stream 0 Source Configuration */
-#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40       /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA1_S0_START_ADDR 0xFFC01F44  /*MemDMA1 Stream 0 Source Start Address */
-#define MDMA1_S0_X_COUNT 0xFFC01F50     /*MemDMA1 Stream 0 Source Inner-Loop Count */
-#define MDMA1_S0_Y_COUNT 0xFFC01F58     /*MemDMA1 Stream 0 Source Outer-Loop Count */
-#define MDMA1_S0_X_MODIFY 0xFFC01F54    /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
-#define MDMA1_S0_Y_MODIFY 0xFFC01F5C    /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
-#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60       /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA1_S0_CURR_ADDR 0xFFC01F64   /*MemDMA1 Stream 0 Source Current Address */
-#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70        /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
-#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78        /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
-#define MDMA1_S0_IRQ_STATUS 0xFFC01F68  /*MemDMA1 Stream 0 Source Interrupt/Status */
-#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /*MemDMA1 Stream 0 Source Peripheral Map */
-
-#define MDMA1_D1_CONFIG 0xFFC01F88      /*MemDMA1 Stream 1 Destination Configuration */
-#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80       /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA1_D1_START_ADDR 0xFFC01F84  /*MemDMA1 Stream 1 Destination Start Address */
-#define MDMA1_D1_X_COUNT 0xFFC01F90     /*MemDMA1 Stream 1 Destination Inner-Loop Count */
-#define MDMA1_D1_Y_COUNT 0xFFC01F98     /*MemDMA1 Stream 1 Destination Outer-Loop Count */
-#define MDMA1_D1_X_MODIFY 0xFFC01F94    /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA1_D1_Y_MODIFY 0xFFC01F9C    /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0       /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
-#define MDMA1_D1_CURR_ADDR 0xFFC01FA4   /*MemDMA1 Stream 1 Dest Current Address */
-#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0        /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
-#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8        /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
-#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8  /*MemDMA1 Stream 1 Dest Interrupt/Status */
-#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /*MemDMA1 Stream 1 Dest Peripheral Map */
-
-#define MDMA1_S1_CONFIG 0xFFC01FC8      /*MemDMA1 Stream 1 Source Configuration */
-#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0       /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA1_S1_START_ADDR 0xFFC01FC4  /*MemDMA1 Stream 1 Source Start Address */
-#define MDMA1_S1_X_COUNT 0xFFC01FD0     /*MemDMA1 Stream 1 Source Inner-Loop Count */
-#define MDMA1_S1_Y_COUNT 0xFFC01FD8     /*MemDMA1 Stream 1 Source Outer-Loop Count */
-#define MDMA1_S1_X_MODIFY 0xFFC01FD4    /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
-#define MDMA1_S1_Y_MODIFY 0xFFC01FDC    /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0       /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA1_S1_CURR_ADDR 0xFFC01FE4   /*MemDMA1 Stream 1 Source Current Address */
-#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0        /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
-#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8        /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
-#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8  /*MemDMA1 Stream 1 Source Interrupt/Status */
-#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /*MemDMA1 Stream 1 Source Peripheral Map */
-
-/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
-#define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
-#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
-#define DMA2_0_START_ADDR 0xFFC00C04    /* DMA2 Channel 0 Start Address */
-#define DMA2_0_X_COUNT 0xFFC00C10       /* DMA2 Channel 0 Inner Loop Count */
-#define DMA2_0_Y_COUNT 0xFFC00C18       /* DMA2 Channel 0 Outer Loop Count */
-#define DMA2_0_X_MODIFY 0xFFC00C14      /* DMA2 Channel 0 Inner Loop Addr Increment */
-#define DMA2_0_Y_MODIFY 0xFFC00C1C      /* DMA2 Channel 0 Outer Loop Addr Increment */
-#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
-#define DMA2_0_CURR_ADDR 0xFFC00C24     /* DMA2 Channel 0 Current Address Pointer */
-#define DMA2_0_CURR_X_COUNT 0xFFC00C30  /* DMA2 Channel 0 Current Inner Loop Count */
-#define DMA2_0_CURR_Y_COUNT 0xFFC00C38  /* DMA2 Channel 0 Current Outer Loop Count */
-#define DMA2_0_IRQ_STATUS 0xFFC00C28    /* DMA2 Channel 0 Interrupt/Status Register */
-#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C        /* DMA2 Channel 0 Peripheral Map Register */
-
-#define DMA2_1_CONFIG 0xFFC00C48        /* DMA2 Channel 1 Configuration register */
-#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
-#define DMA2_1_START_ADDR 0xFFC00C44    /* DMA2 Channel 1 Start Address */
-#define DMA2_1_X_COUNT 0xFFC00C50       /* DMA2 Channel 1 Inner Loop Count */
-#define DMA2_1_Y_COUNT 0xFFC00C58       /* DMA2 Channel 1 Outer Loop Count */
-#define DMA2_1_X_MODIFY 0xFFC00C54      /* DMA2 Channel 1 Inner Loop Addr Increment */
-#define DMA2_1_Y_MODIFY 0xFFC00C5C      /* DMA2 Channel 1 Outer Loop Addr Increment */
-#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
-#define DMA2_1_CURR_ADDR 0xFFC00C64     /* DMA2 Channel 1 Current Address Pointer */
-#define DMA2_1_CURR_X_COUNT 0xFFC00C70  /* DMA2 Channel 1 Current Inner Loop Count */
-#define DMA2_1_CURR_Y_COUNT 0xFFC00C78  /* DMA2 Channel 1 Current Outer Loop Count */
-#define DMA2_1_IRQ_STATUS 0xFFC00C68    /* DMA2 Channel 1 Interrupt/Status Register */
-#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C        /* DMA2 Channel 1 Peripheral Map Register */
-
-#define DMA2_2_CONFIG 0xFFC00C88        /* DMA2 Channel 2 Configuration register */
-#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
-#define DMA2_2_START_ADDR 0xFFC00C84    /* DMA2 Channel 2 Start Address */
-#define DMA2_2_X_COUNT 0xFFC00C90       /* DMA2 Channel 2 Inner Loop Count */
-#define DMA2_2_Y_COUNT 0xFFC00C98       /* DMA2 Channel 2 Outer Loop Count */
-#define DMA2_2_X_MODIFY 0xFFC00C94      /* DMA2 Channel 2 Inner Loop Addr Increment */
-#define DMA2_2_Y_MODIFY 0xFFC00C9C      /* DMA2 Channel 2 Outer Loop Addr Increment */
-#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
-#define DMA2_2_CURR_ADDR 0xFFC00CA4     /* DMA2 Channel 2 Current Address Pointer */
-#define DMA2_2_CURR_X_COUNT 0xFFC00CB0  /* DMA2 Channel 2 Current Inner Loop Count */
-#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8  /* DMA2 Channel 2 Current Outer Loop Count */
-#define DMA2_2_IRQ_STATUS 0xFFC00CA8    /* DMA2 Channel 2 Interrupt/Status Register */
-#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC        /* DMA2 Channel 2 Peripheral Map Register */
-
-#define DMA2_3_CONFIG 0xFFC00CC8        /* DMA2 Channel 3 Configuration register */
-#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
-#define DMA2_3_START_ADDR 0xFFC00CC4    /* DMA2 Channel 3 Start Address */
-#define DMA2_3_X_COUNT 0xFFC00CD0       /* DMA2 Channel 3 Inner Loop Count */
-#define DMA2_3_Y_COUNT 0xFFC00CD8       /* DMA2 Channel 3 Outer Loop Count */
-#define DMA2_3_X_MODIFY 0xFFC00CD4      /* DMA2 Channel 3 Inner Loop Addr Increment */
-#define DMA2_3_Y_MODIFY 0xFFC00CDC      /* DMA2 Channel 3 Outer Loop Addr Increment */
-#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
-#define DMA2_3_CURR_ADDR 0xFFC00CE4     /* DMA2 Channel 3 Current Address Pointer */
-#define DMA2_3_CURR_X_COUNT 0xFFC00CF0  /* DMA2 Channel 3 Current Inner Loop Count */
-#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8  /* DMA2 Channel 3 Current Outer Loop Count */
-#define DMA2_3_IRQ_STATUS 0xFFC00CE8    /* DMA2 Channel 3 Interrupt/Status Register */
-#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC        /* DMA2 Channel 3 Peripheral Map Register */
-
-#define DMA2_4_CONFIG 0xFFC00D08        /* DMA2 Channel 4 Configuration register */
-#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
-#define DMA2_4_START_ADDR 0xFFC00D04    /* DMA2 Channel 4 Start Address */
-#define DMA2_4_X_COUNT 0xFFC00D10       /* DMA2 Channel 4 Inner Loop Count */
-#define DMA2_4_Y_COUNT 0xFFC00D18       /* DMA2 Channel 4 Outer Loop Count */
-#define DMA2_4_X_MODIFY 0xFFC00D14      /* DMA2 Channel 4 Inner Loop Addr Increment */
-#define DMA2_4_Y_MODIFY 0xFFC00D1C      /* DMA2 Channel 4 Outer Loop Addr Increment */
-#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
-#define DMA2_4_CURR_ADDR 0xFFC00D24     /* DMA2 Channel 4 Current Address Pointer */
-#define DMA2_4_CURR_X_COUNT 0xFFC00D30  /* DMA2 Channel 4 Current Inner Loop Count */
-#define DMA2_4_CURR_Y_COUNT 0xFFC00D38  /* DMA2 Channel 4 Current Outer Loop Count */
-#define DMA2_4_IRQ_STATUS 0xFFC00D28    /* DMA2 Channel 4 Interrupt/Status Register */
-#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C        /* DMA2 Channel 4 Peripheral Map Register */
-
-#define DMA2_5_CONFIG 0xFFC00D48        /* DMA2 Channel 5 Configuration register */
-#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
-#define DMA2_5_START_ADDR 0xFFC00D44    /* DMA2 Channel 5 Start Address */
-#define DMA2_5_X_COUNT 0xFFC00D50       /* DMA2 Channel 5 Inner Loop Count */
-#define DMA2_5_Y_COUNT 0xFFC00D58       /* DMA2 Channel 5 Outer Loop Count */
-#define DMA2_5_X_MODIFY 0xFFC00D54      /* DMA2 Channel 5 Inner Loop Addr Increment */
-#define DMA2_5_Y_MODIFY 0xFFC00D5C      /* DMA2 Channel 5 Outer Loop Addr Increment */
-#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
-#define DMA2_5_CURR_ADDR 0xFFC00D64     /* DMA2 Channel 5 Current Address Pointer */
-#define DMA2_5_CURR_X_COUNT 0xFFC00D70  /* DMA2 Channel 5 Current Inner Loop Count */
-#define DMA2_5_CURR_Y_COUNT 0xFFC00D78  /* DMA2 Channel 5 Current Outer Loop Count */
-#define DMA2_5_IRQ_STATUS 0xFFC00D68    /* DMA2 Channel 5 Interrupt/Status Register */
-#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C        /* DMA2 Channel 5 Peripheral Map Register */
-
-#define DMA2_6_CONFIG 0xFFC00D88        /* DMA2 Channel 6 Configuration register */
-#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
-#define DMA2_6_START_ADDR 0xFFC00D84    /* DMA2 Channel 6 Start Address */
-#define DMA2_6_X_COUNT 0xFFC00D90       /* DMA2 Channel 6 Inner Loop Count */
-#define DMA2_6_Y_COUNT 0xFFC00D98       /* DMA2 Channel 6 Outer Loop Count */
-#define DMA2_6_X_MODIFY 0xFFC00D94      /* DMA2 Channel 6 Inner Loop Addr Increment */
-#define DMA2_6_Y_MODIFY 0xFFC00D9C      /* DMA2 Channel 6 Outer Loop Addr Increment */
-#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
-#define DMA2_6_CURR_ADDR 0xFFC00DA4     /* DMA2 Channel 6 Current Address Pointer */
-#define DMA2_6_CURR_X_COUNT 0xFFC00DB0  /* DMA2 Channel 6 Current Inner Loop Count */
-#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8  /* DMA2 Channel 6 Current Outer Loop Count */
-#define DMA2_6_IRQ_STATUS 0xFFC00DA8    /* DMA2 Channel 6 Interrupt/Status Register */
-#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC        /* DMA2 Channel 6 Peripheral Map Register */
-
-#define DMA2_7_CONFIG 0xFFC00DC8        /* DMA2 Channel 7 Configuration register */
-#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
-#define DMA2_7_START_ADDR 0xFFC00DC4    /* DMA2 Channel 7 Start Address */
-#define DMA2_7_X_COUNT 0xFFC00DD0       /* DMA2 Channel 7 Inner Loop Count */
-#define DMA2_7_Y_COUNT 0xFFC00DD8       /* DMA2 Channel 7 Outer Loop Count */
-#define DMA2_7_X_MODIFY 0xFFC00DD4      /* DMA2 Channel 7 Inner Loop Addr Increment */
-#define DMA2_7_Y_MODIFY 0xFFC00DDC      /* DMA2 Channel 7 Outer Loop Addr Increment */
-#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
-#define DMA2_7_CURR_ADDR 0xFFC00DE4     /* DMA2 Channel 7 Current Address Pointer */
-#define DMA2_7_CURR_X_COUNT 0xFFC00DF0  /* DMA2 Channel 7 Current Inner Loop Count */
-#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8  /* DMA2 Channel 7 Current Outer Loop Count */
-#define DMA2_7_IRQ_STATUS 0xFFC00DE8    /* DMA2 Channel 7 Interrupt/Status Register */
-#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC        /* DMA2 Channel 7 Peripheral Map Register */
-
-#define DMA2_8_CONFIG 0xFFC00E08        /* DMA2 Channel 8 Configuration register */
-#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
-#define DMA2_8_START_ADDR 0xFFC00E04    /* DMA2 Channel 8 Start Address */
-#define DMA2_8_X_COUNT 0xFFC00E10       /* DMA2 Channel 8 Inner Loop Count */
-#define DMA2_8_Y_COUNT 0xFFC00E18       /* DMA2 Channel 8 Outer Loop Count */
-#define DMA2_8_X_MODIFY 0xFFC00E14      /* DMA2 Channel 8 Inner Loop Addr Increment */
-#define DMA2_8_Y_MODIFY 0xFFC00E1C      /* DMA2 Channel 8 Outer Loop Addr Increment */
-#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
-#define DMA2_8_CURR_ADDR 0xFFC00E24     /* DMA2 Channel 8 Current Address Pointer */
-#define DMA2_8_CURR_X_COUNT 0xFFC00E30  /* DMA2 Channel 8 Current Inner Loop Count */
-#define DMA2_8_CURR_Y_COUNT 0xFFC00E38  /* DMA2 Channel 8 Current Outer Loop Count */
-#define DMA2_8_IRQ_STATUS 0xFFC00E28    /* DMA2 Channel 8 Interrupt/Status Register */
-#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C        /* DMA2 Channel 8 Peripheral Map Register */
-
-#define DMA2_9_CONFIG 0xFFC00E48        /* DMA2 Channel 9 Configuration register */
-#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
-#define DMA2_9_START_ADDR 0xFFC00E44    /* DMA2 Channel 9 Start Address */
-#define DMA2_9_X_COUNT 0xFFC00E50       /* DMA2 Channel 9 Inner Loop Count */
-#define DMA2_9_Y_COUNT 0xFFC00E58       /* DMA2 Channel 9 Outer Loop Count */
-#define DMA2_9_X_MODIFY 0xFFC00E54      /* DMA2 Channel 9 Inner Loop Addr Increment */
-#define DMA2_9_Y_MODIFY 0xFFC00E5C      /* DMA2 Channel 9 Outer Loop Addr Increment */
-#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
-#define DMA2_9_CURR_ADDR 0xFFC00E64     /* DMA2 Channel 9 Current Address Pointer */
-#define DMA2_9_CURR_X_COUNT 0xFFC00E70  /* DMA2 Channel 9 Current Inner Loop Count */
-#define DMA2_9_CURR_Y_COUNT 0xFFC00E78  /* DMA2 Channel 9 Current Outer Loop Count */
-#define DMA2_9_IRQ_STATUS 0xFFC00E68    /* DMA2 Channel 9 Interrupt/Status Register */
-#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C        /* DMA2 Channel 9 Peripheral Map Register */
-
-#define DMA2_10_CONFIG 0xFFC00E88       /* DMA2 Channel 10 Configuration register */
-#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80        /* DMA2 Channel 10 Next Descripter Ptr Reg */
-#define DMA2_10_START_ADDR 0xFFC00E84   /* DMA2 Channel 10 Start Address */
-#define DMA2_10_X_COUNT 0xFFC00E90      /* DMA2 Channel 10 Inner Loop Count */
-#define DMA2_10_Y_COUNT 0xFFC00E98      /* DMA2 Channel 10 Outer Loop Count */
-#define DMA2_10_X_MODIFY 0xFFC00E94     /* DMA2 Channel 10 Inner Loop Addr Increment */
-#define DMA2_10_Y_MODIFY 0xFFC00E9C     /* DMA2 Channel 10 Outer Loop Addr Increment */
-#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0        /* DMA2 Channel 10 Current Descriptor Pointer */
-#define DMA2_10_CURR_ADDR 0xFFC00EA4    /* DMA2 Channel 10 Current Address Pointer */
-#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
-#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
-#define DMA2_10_IRQ_STATUS 0xFFC00EA8   /* DMA2 Channel 10 Interrupt/Status Register */
-#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC       /* DMA2 Channel 10 Peripheral Map Register */
-
-#define DMA2_11_CONFIG 0xFFC00EC8       /* DMA2 Channel 11 Configuration register */
-#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0        /* DMA2 Channel 11 Next Descripter Ptr Reg */
-#define DMA2_11_START_ADDR 0xFFC00EC4   /* DMA2 Channel 11 Start Address */
-#define DMA2_11_X_COUNT 0xFFC00ED0      /* DMA2 Channel 11 Inner Loop Count */
-#define DMA2_11_Y_COUNT 0xFFC00ED8      /* DMA2 Channel 11 Outer Loop Count */
-#define DMA2_11_X_MODIFY 0xFFC00ED4     /* DMA2 Channel 11 Inner Loop Addr Increment */
-#define DMA2_11_Y_MODIFY 0xFFC00EDC     /* DMA2 Channel 11 Outer Loop Addr Increment */
-#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0        /* DMA2 Channel 11 Current Descriptor Pointer */
-#define DMA2_11_CURR_ADDR 0xFFC00EE4    /* DMA2 Channel 11 Current Address Pointer */
-#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
-#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
-#define DMA2_11_IRQ_STATUS 0xFFC00EE8   /* DMA2 Channel 11 Interrupt/Status Register */
-#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
-
-/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
-#define MDMA2_D0_CONFIG 0xFFC00F08      /*MemDMA2 Stream 0 Destination Configuration register */
-#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00       /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D0_START_ADDR 0xFFC00F04  /*MemDMA2 Stream 0 Destination Start Address */
-#define MDMA2_D0_X_COUNT 0xFFC00F10     /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
-#define MDMA2_D0_Y_COUNT 0xFFC00F18     /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
-#define MDMA2_D0_X_MODIFY 0xFFC00F14    /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
-#define MDMA2_D0_Y_MODIFY 0xFFC00F1C    /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
-#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20       /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
-#define MDMA2_D0_CURR_ADDR 0xFFC00F24   /*MemDMA2 Stream 0 Destination Current Address */
-#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30        /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
-#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38        /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
-#define MDMA2_D0_IRQ_STATUS 0xFFC00F28  /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
-#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C      /*MemDMA2 Stream 0 Destination Peripheral Map register */
-
-#define MDMA2_S0_CONFIG 0xFFC00F48      /*MemDMA2 Stream 0 Source Configuration register */
-#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40       /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
-#define MDMA2_S0_START_ADDR 0xFFC00F44  /*MemDMA2 Stream 0 Source Start Address */
-#define MDMA2_S0_X_COUNT 0xFFC00F50     /*MemDMA2 Stream 0 Source Inner-Loop Count register */
-#define MDMA2_S0_Y_COUNT 0xFFC00F58     /*MemDMA2 Stream 0 Source Outer-Loop Count register */
-#define MDMA2_S0_X_MODIFY 0xFFC00F54    /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
-#define MDMA2_S0_Y_MODIFY 0xFFC00F5C    /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
-#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60       /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
-#define MDMA2_S0_CURR_ADDR 0xFFC00F64   /*MemDMA2 Stream 0 Source Current Address */
-#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70        /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
-#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78        /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
-#define MDMA2_S0_IRQ_STATUS 0xFFC00F68  /*MemDMA2 Stream 0 Source Interrupt/Status Register */
-#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C      /*MemDMA2 Stream 0 Source Peripheral Map register */
-
-#define MDMA2_D1_CONFIG 0xFFC00F88      /*MemDMA2 Stream 1 Destination Configuration register */
-#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80       /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
-#define MDMA2_D1_START_ADDR 0xFFC00F84  /*MemDMA2 Stream 1 Destination Start Address */
-#define MDMA2_D1_X_COUNT 0xFFC00F90     /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
-#define MDMA2_D1_Y_COUNT 0xFFC00F98     /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
-#define MDMA2_D1_X_MODIFY 0xFFC00F94    /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
-#define MDMA2_D1_Y_MODIFY 0xFFC00F9C    /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
-#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0       /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
-#define MDMA2_D1_CURR_ADDR 0xFFC00FA4   /*MemDMA2 Stream 1 Destination Current Address reg */
-#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0        /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
-#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8        /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
-#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8  /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
-#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC      /*MemDMA2 Stream 1 Destination Peripheral Map register */
-
-#define MDMA2_S1_CONFIG 0xFFC00FC8      /*MemDMA2 Stream 1 Source Configuration register */
-#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0       /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
-#define MDMA2_S1_START_ADDR 0xFFC00FC4  /*MemDMA2 Stream 1 Source Start Address */
-#define MDMA2_S1_X_COUNT 0xFFC00FD0     /*MemDMA2 Stream 1 Source Inner-Loop Count register */
-#define MDMA2_S1_Y_COUNT 0xFFC00FD8     /*MemDMA2 Stream 1 Source Outer-Loop Count register */
-#define MDMA2_S1_X_MODIFY 0xFFC00FD4    /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
-#define MDMA2_S1_Y_MODIFY 0xFFC00FDC    /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
-#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0       /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
-#define MDMA2_S1_CURR_ADDR 0xFFC00FE4   /*MemDMA2 Stream 1 Source Current Address */
-#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0        /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
-#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8        /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
-#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8  /*MemDMA2 Stream 1 Source Interrupt/Status Register */
-#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC      /*MemDMA2 Stream 1 Source Peripheral Map register */
-
-/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
-#define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
-#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800       /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D0_START_ADDR 0xFFC01804  /*IMDMA Stream 0 Destination Start Address */
-#define IMDMA_D0_X_COUNT 0xFFC01810     /*IMDMA Stream 0 Destination Inner-Loop Count */
-#define IMDMA_D0_Y_COUNT 0xFFC01818     /*IMDMA Stream 0 Destination Outer-Loop Count */
-#define IMDMA_D0_X_MODIFY 0xFFC01814    /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
-#define IMDMA_D0_Y_MODIFY 0xFFC0181C    /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
-#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820       /*IMDMA Stream 0 Destination Current Descriptor Ptr */
-#define IMDMA_D0_CURR_ADDR 0xFFC01824   /*IMDMA Stream 0 Destination Current Address */
-#define IMDMA_D0_CURR_X_COUNT 0xFFC01830        /*IMDMA Stream 0 Destination Current Inner-Loop Count */
-#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838        /*IMDMA Stream 0 Destination Current Outer-Loop Count */
-#define IMDMA_D0_IRQ_STATUS 0xFFC01828  /*IMDMA Stream 0 Destination Interrupt/Status */
-
-#define IMDMA_S0_CONFIG 0xFFC01848      /*IMDMA Stream 0 Source Configuration */
-#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840       /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
-#define IMDMA_S0_START_ADDR 0xFFC01844  /*IMDMA Stream 0 Source Start Address */
-#define IMDMA_S0_X_COUNT 0xFFC01850     /*IMDMA Stream 0 Source Inner-Loop Count */
-#define IMDMA_S0_Y_COUNT 0xFFC01858     /*IMDMA Stream 0 Source Outer-Loop Count */
-#define IMDMA_S0_X_MODIFY 0xFFC01854    /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
-#define IMDMA_S0_Y_MODIFY 0xFFC0185C    /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
-#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860       /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
-#define IMDMA_S0_CURR_ADDR 0xFFC01864   /*IMDMA Stream 0 Source Current Address */
-#define IMDMA_S0_CURR_X_COUNT 0xFFC01870        /*IMDMA Stream 0 Source Current Inner-Loop Count */
-#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878        /*IMDMA Stream 0 Source Current Outer-Loop Count */
-#define IMDMA_S0_IRQ_STATUS 0xFFC01868  /*IMDMA Stream 0 Source Interrupt/Status */
-
-#define IMDMA_D1_CONFIG 0xFFC01888      /*IMDMA Stream 1 Destination Configuration */
-#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880       /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
-#define IMDMA_D1_START_ADDR 0xFFC01884  /*IMDMA Stream 1 Destination Start Address */
-#define IMDMA_D1_X_COUNT 0xFFC01890     /*IMDMA Stream 1 Destination Inner-Loop Count */
-#define IMDMA_D1_Y_COUNT 0xFFC01898     /*IMDMA Stream 1 Destination Outer-Loop Count */
-#define IMDMA_D1_X_MODIFY 0xFFC01894    /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
-#define IMDMA_D1_Y_MODIFY 0xFFC0189C    /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
-#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0       /*IMDMA Stream 1 Destination Current Descriptor Ptr */
-#define IMDMA_D1_CURR_ADDR 0xFFC018A4   /*IMDMA Stream 1 Destination Current Address */
-#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0        /*IMDMA Stream 1 Destination Current Inner-Loop Count */
-#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8        /*IMDMA Stream 1 Destination Current Outer-Loop Count */
-#define IMDMA_D1_IRQ_STATUS 0xFFC018A8  /*IMDMA Stream 1 Destination Interrupt/Status */
-
-#define IMDMA_S1_CONFIG 0xFFC018C8      /*IMDMA Stream 1 Source Configuration */
-#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0       /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
-#define IMDMA_S1_START_ADDR 0xFFC018C4  /*IMDMA Stream 1 Source Start Address */
-#define IMDMA_S1_X_COUNT 0xFFC018D0     /*IMDMA Stream 1 Source Inner-Loop Count */
-#define IMDMA_S1_Y_COUNT 0xFFC018D8     /*IMDMA Stream 1 Source Outer-Loop Count */
-#define IMDMA_S1_X_MODIFY 0xFFC018D4    /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
-#define IMDMA_S1_Y_MODIFY 0xFFC018DC    /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
-#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0       /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
-#define IMDMA_S1_CURR_ADDR 0xFFC018E4   /*IMDMA Stream 1 Source Current Address */
-#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0        /*IMDMA Stream 1 Source Current Inner-Loop Count */
-#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8        /*IMDMA Stream 1 Source Current Outer-Loop Count */
-#define IMDMA_S1_IRQ_STATUS 0xFFC018E8  /*IMDMA Stream 1 Source Interrupt/Status */
-
-/*********************************************************************************** */
-/* System MMR Register Bits */
-/******************************************************************************* */
-
-/* ********************* PLL AND RESET MASKS ************************ */
-
-/* PLL_CTL Masks */
-#define PLL_CLKIN              0x00000000       /* Pass CLKIN to PLL */
-#define PLL_CLKIN_DIV2         0x00000001       /* Pass CLKIN/2 to PLL */
-#define PLL_OFF                0x00000002       /* Shut off PLL clocks */
-#define STOPCK_OFF             0x00000008       /* Core clock off */
-#define PDWN                   0x00000020       /* Put the PLL in a Deep Sleep state */
-#define BYPASS                 0x00000100       /* Bypass the PLL */
-
-/* CHIPID Masks */
-#define CHIPID_VERSION         0xF0000000
-#define CHIPID_FAMILY          0x0FFFF000
-#define CHIPID_MANUFACTURE     0x00000FFE
-
-/* VR_CTL Masks                                                                                                                                 */
-#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
-#define HIBERNATE               0x0000  /* Powerdown/Bypass On-Board Regulation */
-#define FREQ_333                0x0001  /* Switching Frequency Is 333 kHz */
-#define FREQ_667                0x0002  /* Switching Frequency Is 667 kHz */
-#define FREQ_1000               0x0003  /* Switching Frequency Is 1 MHz */
-
-#define GAIN                    0x000C  /* Voltage Level Gain   */
-#define GAIN_5                  0x0000  /* GAIN = 5*/
-#define GAIN_10                 0x0004  /* GAIN = 1*/
-#define GAIN_20                 0x0008  /* GAIN = 2*/
-#define GAIN_50                 0x000C  /* GAIN = 5*/
-
-#define VLEV                    0x00F0  /* Internal Voltage Level */
-#define VLEV_085                0x0060  /* VLEV = 0.85 V (-5% - +10% Accuracy) */
-#define VLEV_090                0x0070  /* VLEV = 0.90 V (-5% - +10% Accuracy) */
-#define VLEV_095                0x0080  /* VLEV = 0.95 V (-5% - +10% Accuracy) */
-#define VLEV_100                0x0090  /* VLEV = 1.00 V (-5% - +10% Accuracy) */
-#define VLEV_105                0x00A0  /* VLEV = 1.05 V (-5% - +10% Accuracy) */
-#define VLEV_110                0x00B0  /* VLEV = 1.10 V (-5% - +10% Accuracy) */
-#define VLEV_115                0x00C0  /* VLEV = 1.15 V (-5% - +10% Accuracy) */
-#define VLEV_120                0x00D0  /* VLEV = 1.20 V (-5% - +10% Accuracy) */
-#define VLEV_125                0x00E0  /* VLEV = 1.25 V (-5% - +10% Accuracy) */
-#define VLEV_130                0x00F0  /* VLEV = 1.30 V (-5% - +10% Accuracy) */
-
-#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate */
-#define SCKELOW                 0x8000  /* Do Not Drive SCKE High During Reset After Hibernate */
-
-/* PLL_DIV Masks */
-#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
-
-#define CSEL                    0x30            /* Core Select */
-#define SSEL                    0xf             /* System Select */
-#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
-#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
-#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
-#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
-
-/* PLL_STAT Masks                                                                                                                                       */
-#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
-#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
-#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
-#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
-
-/* SWRST Mask */
-#define SYSTEM_RESET           0x0007   /* Initiates a system software reset */
-#define DOUBLE_FAULT_A         0x0008   /* Core A Double Fault Causes Reset */
-#define DOUBLE_FAULT_B         0x0010   /* Core B Double Fault Causes Reset */
-#define SWRST_DBL_FAULT_A      0x0800   /* SWRST Core A Double Fault */
-#define SWRST_DBL_FAULT_B      0x1000   /* SWRST Core B Double Fault */
-#define SWRST_WDT_B                    0x2000   /* SWRST Watchdog B */
-#define SWRST_WDT_A                    0x4000   /* SWRST Watchdog A */
-#define SWRST_OCCURRED         0x8000   /* SWRST Status */
-
-/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
-
-/* SICu_IARv Masks       */
-/* u = A or B */
-/* v = 0 to 7 */
-/* w = 0 or 1 */
-
-/* Per_number = 0 to 63 */
-/* IVG_number = 7 to 15   */
-#define Peripheral_IVG(Per_number, IVG_number)    \
-    ((IVG_number) - 7) << (((Per_number) % 8) * 4)      /* Peripheral #Per_number assigned IVG #IVG_number  */
-    /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
-    /*        r0.h = hi(Peripheral_IVG(62, 10)); */
-
-/* SICx_IMASKw Masks */
-/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
-#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
-#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
-#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
-#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
-
-/* SIC_IWR Masks */
-#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
-#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
-/* x = pos 0 to 31, for 32-63 use value-32 */
-#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
-#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
-
-/* ***************************** UART CONTROLLER MASKS ********************** */
-
-/* UART_LCR Register */
-
-#define DLAB    0x80
-#define SB      0x40
-#define STP      0x20
-#define EPS     0x10
-#define PEN     0x08
-#define STB     0x04
-#define WLS(x)  ((x-5) & 0x03)
-
-#define DLAB_P  0x07
-#define SB_P    0x06
-#define STP_P   0x05
-#define EPS_P   0x04
-#define PEN_P   0x03
-#define STB_P   0x02
-#define WLS_P1  0x01
-#define WLS_P0  0x00
-
-/* UART_MCR Register */
-#define LOOP_ENA        0x10
-#define LOOP_ENA_P      0x04
-
-/* UART_LSR Register */
-#define TEMT    0x40
-#define THRE    0x20
-#define BI      0x10
-#define FE      0x08
-#define PE      0x04
-#define OE      0x02
-#define DR      0x01
-
-#define TEMP_P  0x06
-#define THRE_P  0x05
-#define BI_P    0x04
-#define FE_P    0x03
-#define PE_P    0x02
-#define OE_P    0x01
-#define DR_P    0x00
-
-/* UART_IER Register */
-#define ELSI    0x04
-#define ETBEI   0x02
-#define ERBFI   0x01
-
-#define ELSI_P  0x02
-#define ETBEI_P 0x01
-#define ERBFI_P 0x00
-
-/* UART_IIR Register */
-#define STATUS(x)       ((x << 1) & 0x06)
-#define NINT            0x01
-#define STATUS_P1       0x02
-#define STATUS_P0       0x01
-#define NINT_P          0x00
-#define IIR_TX_READY    0x02    /* UART_THR empty                               */
-#define IIR_RX_READY    0x04    /* Receive data ready                           */
-#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
-#define IIR_STATUS      0x06
-
-/* UART_GCTL Register */
-#define FFE     0x20
-#define FPE     0x10
-#define RPOLC   0x08
-#define TPOLC   0x04
-#define IREN    0x02
-#define UCEN    0x01
-
-#define FFE_P   0x05
-#define FPE_P   0x04
-#define RPOLC_P 0x03
-#define TPOLC_P 0x02
-#define IREN_P  0x01
-#define UCEN_P  0x00
-
-/* **********  SERIAL PORT MASKS  ********************** */
-
-/* SPORTx_TCR1 Masks */
-#define TSPEN    0x0001         /* TX enable  */
-#define ITCLK    0x0002         /* Internal TX Clock Select  */
-#define TDTYPE   0x000C         /* TX Data Formatting Select */
-#define TLSBIT   0x0010         /* TX Bit Order */
-#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
-#define TFSR     0x0400         /* TX Frame Sync Required Select  */
-#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
-#define LTFS     0x1000         /* Low TX Frame Sync Select  */
-#define LATFS    0x2000         /* Late TX Frame Sync Select  */
-#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
-
-/* SPORTx_TCR2 Masks */
-#define SLEN        0x001F      /*TX Word Length  */
-#define TXSE        0x0100      /*TX Secondary Enable */
-#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
-#define TRFST       0x0400      /*TX Right-First Data Order  */
-
-/* SPORTx_RCR1 Masks */
-#define RSPEN    0x0001         /* RX enable  */
-#define IRCLK    0x0002         /* Internal RX Clock Select  */
-#define RDTYPE   0x000C         /* RX Data Formatting Select */
-#define RULAW    0x0008         /* u-Law enable  */
-#define RALAW    0x000C         /* A-Law enable  */
-#define RLSBIT   0x0010         /* RX Bit Order */
-#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
-#define RFSR     0x0400         /* RX Frame Sync Required Select  */
-#define LRFS     0x1000         /* Low RX Frame Sync Select  */
-#define LARFS    0x2000         /* Late RX Frame Sync Select  */
-#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
-
-/* SPORTx_RCR2 Masks */
-#define SLEN        0x001F      /*RX Word Length  */
-#define RXSE        0x0100      /*RX Secondary Enable */
-#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
-#define RRFST       0x0400      /*Right-First Data Order  */
-
-/*SPORTx_STAT Masks */
-#define RXNE            0x0001  /*RX FIFO Not Empty Status */
-#define RUVF            0x0002  /*RX Underflow Status */
-#define ROVF            0x0004  /*RX Overflow Status */
-#define TXF             0x0008  /*TX FIFO Full Status */
-#define TUVF            0x0010  /*TX Underflow Status */
-#define TOVF            0x0020  /*TX Overflow Status */
-#define TXHRE           0x0040  /*TX Hold Register Empty */
-
-/*SPORTx_MCMC1 Masks */
-#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
-#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
-
-/*SPORTx_MCMC2 Masks */
-#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
-#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
-#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
-#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
-#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
-#define MFD             0x0000F000      /*Multichannel Frame Delay    */
-
-/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
-
-/*  PPI_CONTROL Masks         */
-#define PORT_EN              0x00000001 /* PPI Port Enable  */
-#define PORT_DIR             0x00000002 /* PPI Port Direction       */
-#define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
-#define PORT_CFG             0x00000030 /* PPI Port Configuration */
-#define FLD_SEL              0x00000040 /* PPI Active Field Select */
-#define PACK_EN              0x00000080 /* PPI Packing Mode */
-#define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
-#define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
-#define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
-#define DLENGTH              0x00003800 /* PPI Data Length  */
-#define DLEN_8               0x0        /* PPI Data Length mask for DLEN=8 */
-#define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
-#define POL                  0x0000C000 /* PPI Signal Polarities       */
-
-/* PPI_STATUS Masks */
-#define FLD                  0x00000400 /* Field Indicator   */
-#define FT_ERR               0x00000800 /* Frame Track Error */
-#define OVR                  0x00001000 /* FIFO Overflow Error */
-#define UNDR                 0x00002000 /* FIFO Underrun Error */
-#define ERR_DET              0x00004000 /* Error Detected Indicator */
-#define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
-
-/* **********  DMA CONTROLLER MASKS  *********************8 */
-
-/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
-#define DMAEN           0x00000001      /* Channel Enable */
-#define WNR             0x00000002      /* Channel Direction (W/R*) */
-#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
-#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
-#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
-#define DMA2D           0x00000010      /* 2D/1D* Mode */
-#define RESTART         0x00000020      /* Restart */
-#define DI_SEL          0x00000040      /* Data Interrupt Select */
-#define DI_EN           0x00000080      /* Data Interrupt Enable */
-#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
-#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
-#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
-#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
-#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
-#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
-#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
-#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
-#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
-#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
-#define NDSIZE          0x00000900      /* Next Descriptor Size */
-#define DMAFLOW         0x00007000      /* Flow Control */
-#define DMAFLOW_STOP            0x0000  /* Stop Mode */
-#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
-#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
-#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
-#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
-
-#define DMAEN_P                 0       /* Channel Enable */
-#define WNR_P                   1       /* Channel Direction (W/R*) */
-#define DMA2D_P                 4       /* 2D/1D* Mode */
-#define RESTART_P               5       /* Restart */
-#define DI_SEL_P                6       /* Data Interrupt Select */
-#define DI_EN_P                 7       /* Data Interrupt Enable */
-
-/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
-
-#define DMA_DONE                0x00000001      /* DMA Done Indicator */
-#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
-#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
-#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
-
-#define DMA_DONE_P              0       /* DMA Done Indicator */
-#define DMA_ERR_P               1       /* DMA Error Indicator */
-#define DFETCH_P                2       /* Descriptor Fetch Indicator */
-#define DMA_RUN_P               3       /* DMA Running Indicator */
-
-/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
-
-#define CTYPE               0x00000040  /* DMA Channel Type Indicator */
-#define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
-#define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
-#define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
-#define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
-#define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
-#define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
-#define PMAP                0x00007000  /* DMA Peripheral Map Field */
-
-/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
-
-/* PWM Timer bit definitions */
-
-/* TIMER_ENABLE Register */
-#define TIMEN0  0x0001
-#define TIMEN1  0x0002
-#define TIMEN2  0x0004
-#define TIMEN3  0x0008
-#define TIMEN4  0x0010
-#define TIMEN5  0x0020
-#define TIMEN6  0x0040
-#define TIMEN7  0x0080
-#define TIMEN8  0x0001
-#define TIMEN9  0x0002
-#define TIMEN10 0x0004
-#define TIMEN11 0x0008
-
-#define TIMEN0_P        0x00
-#define TIMEN1_P        0x01
-#define TIMEN2_P        0x02
-#define TIMEN3_P        0x03
-#define TIMEN4_P        0x04
-#define TIMEN5_P        0x05
-#define TIMEN6_P        0x06
-#define TIMEN7_P        0x07
-#define TIMEN8_P        0x00
-#define TIMEN9_P        0x01
-#define TIMEN10_P       0x02
-#define TIMEN11_P       0x03
-
-/* TIMER_DISABLE Register */
-#define TIMDIS0         0x0001
-#define TIMDIS1         0x0002
-#define TIMDIS2         0x0004
-#define TIMDIS3         0x0008
-#define TIMDIS4         0x0010
-#define TIMDIS5         0x0020
-#define TIMDIS6         0x0040
-#define TIMDIS7         0x0080
-#define TIMDIS8         0x0001
-#define TIMDIS9         0x0002
-#define TIMDIS10        0x0004
-#define TIMDIS11        0x0008
-
-#define TIMDIS0_P       0x00
-#define TIMDIS1_P       0x01
-#define TIMDIS2_P       0x02
-#define TIMDIS3_P       0x03
-#define TIMDIS4_P       0x04
-#define TIMDIS5_P       0x05
-#define TIMDIS6_P       0x06
-#define TIMDIS7_P       0x07
-#define TIMDIS8_P       0x00
-#define TIMDIS9_P       0x01
-#define TIMDIS10_P      0x02
-#define TIMDIS11_P      0x03
-
-/* TIMER_STATUS Register */
-#define TIMIL0          0x00000001
-#define TIMIL1          0x00000002
-#define TIMIL2          0x00000004
-#define TIMIL3          0x00000008
-#define TIMIL4          0x00010000
-#define TIMIL5          0x00020000
-#define TIMIL6          0x00040000
-#define TIMIL7          0x00080000
-#define TIMIL8          0x0001
-#define TIMIL9          0x0002
-#define TIMIL10         0x0004
-#define TIMIL11         0x0008
-#define TOVF_ERR0       0x00000010
-#define TOVF_ERR1       0x00000020
-#define TOVF_ERR2       0x00000040
-#define TOVF_ERR3       0x00000080
-#define TOVF_ERR4       0x00100000
-#define TOVF_ERR5       0x00200000
-#define TOVF_ERR6       0x00400000
-#define TOVF_ERR7       0x00800000
-#define TOVF_ERR8       0x0010
-#define TOVF_ERR9       0x0020
-#define TOVF_ERR10      0x0040
-#define TOVF_ERR11      0x0080
-#define TRUN0           0x00001000
-#define TRUN1           0x00002000
-#define TRUN2           0x00004000
-#define TRUN3           0x00008000
-#define TRUN4           0x10000000
-#define TRUN5           0x20000000
-#define TRUN6           0x40000000
-#define TRUN7           0x80000000
-#define TRUN8           0x1000
-#define TRUN9           0x2000
-#define TRUN10          0x4000
-#define TRUN11          0x8000
-
-#define TIMIL0_P        0x00
-#define TIMIL1_P        0x01
-#define TIMIL2_P        0x02
-#define TIMIL3_P        0x03
-#define TIMIL4_P        0x10
-#define TIMIL5_P        0x11
-#define TIMIL6_P        0x12
-#define TIMIL7_P        0x13
-#define TIMIL8_P        0x00
-#define TIMIL9_P        0x01
-#define TIMIL10_P       0x02
-#define TIMIL11_P       0x03
-#define TOVF_ERR0_P     0x04
-#define TOVF_ERR1_P     0x05
-#define TOVF_ERR2_P     0x06
-#define TOVF_ERR3_P     0x07
-#define TOVF_ERR4_P     0x14
-#define TOVF_ERR5_P     0x15
-#define TOVF_ERR6_P     0x16
-#define TOVF_ERR7_P     0x17
-#define TOVF_ERR8_P     0x04
-#define TOVF_ERR9_P     0x05
-#define TOVF_ERR10_P    0x06
-#define TOVF_ERR11_P    0x07
-#define TRUN0_P         0x0C
-#define TRUN1_P         0x0D
-#define TRUN2_P         0x0E
-#define TRUN3_P         0x0F
-#define TRUN4_P         0x1C
-#define TRUN5_P         0x1D
-#define TRUN6_P         0x1E
-#define TRUN7_P         0x1F
-#define TRUN8_P         0x0C
-#define TRUN9_P         0x0D
-#define TRUN10_P        0x0E
-#define TRUN11_P        0x0F
-
-/* Alternate Deprecated Macros Provided For Backwards Code Compatibility */
-#define TOVL_ERR0 TOVF_ERR0
-#define TOVL_ERR1 TOVF_ERR1
-#define TOVL_ERR2 TOVF_ERR2
-#define TOVL_ERR3 TOVF_ERR3
-#define TOVL_ERR4 TOVF_ERR4
-#define TOVL_ERR5 TOVF_ERR5
-#define TOVL_ERR6 TOVF_ERR6
-#define TOVL_ERR7 TOVF_ERR7
-#define TOVL_ERR8 TOVF_ERR8
-#define TOVL_ERR9 TOVF_ERR9
-#define TOVL_ERR10 TOVF_ERR10
-#define TOVL_ERR11 TOVF_ERR11
-#define TOVL_ERR0_P TOVF_ERR0_P
-#define TOVL_ERR1_P TOVF_ERR1_P
-#define TOVL_ERR2_P TOVF_ERR2_P
-#define TOVL_ERR3_P TOVF_ERR3_P
-#define TOVL_ERR4_P TOVF_ERR4_P
-#define TOVL_ERR5_P TOVF_ERR5_P
-#define TOVL_ERR6_P TOVF_ERR6_P
-#define TOVL_ERR7_P TOVF_ERR7_P
-#define TOVL_ERR8_P TOVF_ERR8_P
-#define TOVL_ERR9_P TOVF_ERR9_P
-#define TOVL_ERR10_P TOVF_ERR10_P
-#define TOVL_ERR11_P TOVF_ERR11_P
-
-/* TIMERx_CONFIG Registers */
-#define PWM_OUT         0x0001
-#define WDTH_CAP        0x0002
-#define EXT_CLK         0x0003
-#define PULSE_HI        0x0004
-#define PERIOD_CNT      0x0008
-#define IRQ_ENA         0x0010
-#define TIN_SEL         0x0020
-#define OUT_DIS         0x0040
-#define CLK_SEL         0x0080
-#define TOGGLE_HI       0x0100
-#define EMU_RUN         0x0200
-#define ERR_TYP(x)      ((x & 0x03) << 14)
-
-#define TMODE_P0                0x00
-#define TMODE_P1                0x01
-#define PULSE_HI_P              0x02
-#define PERIOD_CNT_P            0x03
-#define IRQ_ENA_P               0x04
-#define TIN_SEL_P               0x05
-#define OUT_DIS_P               0x06
-#define CLK_SEL_P               0x07
-#define TOGGLE_HI_P             0x08
-#define EMU_RUN_P               0x09
-#define ERR_TYP_P0              0x0E
-#define ERR_TYP_P1              0x0F
-
-/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
-#define PF0         0x0001
-#define PF1         0x0002
-#define PF2         0x0004
-#define PF3         0x0008
-#define PF4         0x0010
-#define PF5         0x0020
-#define PF6         0x0040
-#define PF7         0x0080
-#define PF8         0x0100
-#define PF9         0x0200
-#define PF10        0x0400
-#define PF11        0x0800
-#define PF12        0x1000
-#define PF13        0x2000
-#define PF14        0x4000
-#define PF15        0x8000
-
-/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
-#define PF0_P         0
-#define PF1_P         1
-#define PF2_P         2
-#define PF3_P         3
-#define PF4_P         4
-#define PF5_P         5
-#define PF6_P         6
-#define PF7_P         7
-#define PF8_P         8
-#define PF9_P         9
-#define PF10_P        10
-#define PF11_P        11
-#define PF12_P        12
-#define PF13_P        13
-#define PF14_P        14
-#define PF15_P        15
-
-/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
-
-/* SPI_CTL Masks */
-#define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
-#define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
-#define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
-#define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
-#define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
-#define SIZE                   0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
-#define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
-#define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
-#define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
-#define MSTR                   0x00001000       /* Configures SPI as master (=1) or slave (=0) */
-#define WOM                    0x00002000       /* Open drain (=1) data output enable (for MOSI and MISO) */
-#define SPE                    0x00004000       /* SPI module enable (=1), disable (=0) */
-
-/* SPI_FLG Masks */
-#define FLS1                   0x00000002       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2                   0x00000004       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3                   0x00000008       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4                   0x00000010       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5                   0x00000020       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6                   0x00000040       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7                   0x00000080       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1                   0x00000200       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2                   0x00000400       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3                   0x00000800       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4                   0x00001000       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5                   0x00002000       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6                   0x00004000       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7                   0x00008000       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_FLG Bit Positions */
-#define FLS1_P                 0x00000001       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
-#define FLS2_P                 0x00000002       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLS3_P                 0x00000003       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
-#define FLS4_P                 0x00000004       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
-#define FLS5_P                 0x00000005       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
-#define FLS6_P                 0x00000006       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
-#define FLS7_P                 0x00000007       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
-#define FLG1_P                 0x00000009       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
-#define FLG2_P                 0x0000000A       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
-#define FLG3_P                 0x0000000B       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
-#define FLG4_P                 0x0000000C       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
-#define FLG5_P                 0x0000000D       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
-#define FLG6_P                 0x0000000E       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
-#define FLG7_P                 0x0000000F       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
-
-/* SPI_STAT Masks */
-#define SPIF                   0x00000001       /* Set (=1) when SPI single-word transfer complete */
-#define MODF                   0x00000002       /* Set (=1) in a master device when some other device tries to become master */
-#define TXE                    0x00000004       /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
-#define TXS                    0x00000008       /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
-#define RBSY                   0x00000010       /* Set (=1) when data is received with RDBR full */
-#define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
-#define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
-
-/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
-
-/* AMGCTL Masks */
-#define AMCKEN                  0x0001  /* Enable CLKOUT */
-#define AMBEN_B0                0x0002  /* Enable Asynchronous Memory Bank 0 only */
-#define AMBEN_B0_B1             0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
-#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
-#define AMBEN_ALL               0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
-#define B0_PEN                  0x0010  /* Enable 16-bit packing Bank 0  */
-#define B1_PEN                  0x0020  /* Enable 16-bit packing Bank 1  */
-#define B2_PEN                  0x0040  /* Enable 16-bit packing Bank 2  */
-#define B3_PEN                  0x0080  /* Enable 16-bit packing Bank 3  */
-
-/* AMGCTL Bit Positions */
-#define AMCKEN_P                0x00000000      /* Enable CLKOUT */
-#define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
-#define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
-#define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
-#define B0_PEN_P                        0x004   /* Enable 16-bit packing Bank 0  */
-#define B1_PEN_P                        0x005   /* Enable 16-bit packing Bank 1  */
-#define B2_PEN_P                        0x006   /* Enable 16-bit packing Bank 2  */
-#define B3_PEN_P                        0x007   /* Enable 16-bit packing Bank 3  */
-
-/* AMBCTL0 Masks */
-#define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
-#define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
-#define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
-#define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
-#define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
-#define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
-#define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
-#define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
-#define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
-#define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
-#define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
-#define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
-#define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
-#define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
-#define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
-#define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
-#define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
-#define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
-#define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
-#define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
-#define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
-#define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
-#define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
-#define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
-#define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
-#define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
-#define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
-#define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
-#define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
-#define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
-#define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
-#define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
-#define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
-#define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
-#define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
-#define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
-#define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
-#define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
-#define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
-#define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
-#define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
-#define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
-#define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
-#define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
-#define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
-#define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
-#define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
-#define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
-#define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
-#define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
-#define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
-#define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
-#define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
-#define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
-#define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
-#define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
-#define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
-#define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
-#define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
-#define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
-#define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
-#define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
-#define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
-#define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
-#define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
-#define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
-#define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
-#define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
-#define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
-#define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
-#define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
-#define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
-#define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
-#define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
-#define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
-#define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
-#define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
-#define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
-#define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
-#define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
-
-/* AMBCTL1 Masks */
-#define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
-#define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
-#define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
-#define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
-#define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
-#define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
-#define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
-#define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
-#define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
-#define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
-#define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
-#define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
-#define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
-#define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
-#define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
-#define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
-#define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
-#define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
-#define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
-#define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
-#define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
-#define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
-#define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
-#define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
-#define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
-#define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
-#define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
-#define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
-#define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
-#define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
-#define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
-#define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
-#define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
-#define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
-#define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
-#define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
-#define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
-#define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
-#define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
-#define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
-#define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
-#define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
-#define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
-#define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
-#define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
-#define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
-#define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
-#define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
-#define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
-#define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
-#define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
-#define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
-#define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
-#define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
-#define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
-#define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
-#define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
-#define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
-#define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
-#define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
-#define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
-#define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
-#define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
-#define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
-#define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
-#define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
-#define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
-#define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
-#define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
-#define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
-#define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
-#define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
-#define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
-#define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
-#define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
-#define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
-#define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
-#define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
-#define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
-#define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
-
-/* **********************  SDRAM CONTROLLER MASKS  *************************** */
-
-/* EBIU_SDGCTL Masks */
-#define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
-#define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
-#define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
-#define PFE                     0x00000010      /* Enable SDRAM prefetch */
-#define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
-#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
-#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
-#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
-#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
-#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
-#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
-#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
-#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
-#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
-#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
-#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
-#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
-#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
-#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
-#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
-#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
-#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
-#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
-#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
-#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
-#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
-#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
-#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
-#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
-#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
-#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
-#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
-#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
-#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
-#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
-#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
-#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
-#define PUPSD                   0x00200000      /*Power-up start delay */
-#define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
-#define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
-#define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
-#define EBUFE                   0x02000000      /* Enable external buffering timing */
-#define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
-#define EMREN                   0x10000000      /* Extended mode register enable */
-#define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
-#define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
-
-/* EBIU_SDBCTL Masks */
-#define EB0_E                           0x00000001      /* Enable SDRAM external bank 0 */
-#define EB0_SZ_16                       0x00000000      /* SDRAM external bank size = 16MB */
-#define EB0_SZ_32                       0x00000002      /* SDRAM external bank size = 32MB */
-#define EB0_SZ_64                       0x00000004      /* SDRAM external bank size = 64MB */
-#define EB0_SZ_128                      0x00000006      /* SDRAM external bank size = 128MB */
-#define EB0_CAW_8                       0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB0_CAW_9                       0x00000010      /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_10                      0x00000020      /* SDRAM external bank column address width = 9 bits */
-#define EB0_CAW_11                      0x00000030      /* SDRAM external bank column address width = 9 bits */
-
-#define EB1_E                           0x00000100      /* Enable SDRAM external bank 1 */
-#define EB1__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
-#define EB1__SZ_32                      0x00000200      /* SDRAM external bank size = 32MB */
-#define EB1__SZ_64                      0x00000400      /* SDRAM external bank size = 64MB */
-#define EB1__SZ_128                     0x00000600      /* SDRAM external bank size = 128MB */
-#define EB1__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB1__CAW_9                      0x00001000      /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_10                     0x00002000      /* SDRAM external bank column address width = 9 bits */
-#define EB1__CAW_11                     0x00003000      /* SDRAM external bank column address width = 9 bits */
-
-#define EB2__E                          0x00010000      /* Enable SDRAM external bank 2 */
-#define EB2__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
-#define EB2__SZ_32                      0x00020000      /* SDRAM external bank size = 32MB */
-#define EB2__SZ_64                      0x00040000      /* SDRAM external bank size = 64MB */
-#define EB2__SZ_128                     0x00060000      /* SDRAM external bank size = 128MB */
-#define EB2__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB2__CAW_9                      0x00100000      /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_10                     0x00200000      /* SDRAM external bank column address width = 9 bits */
-#define EB2__CAW_11                     0x00300000      /* SDRAM external bank column address width = 9 bits */
-
-#define EB3__E                          0x01000000      /* Enable SDRAM external bank 3 */
-#define EB3__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
-#define EB3__SZ_32                      0x02000000      /* SDRAM external bank size = 32MB */
-#define EB3__SZ_64                      0x04000000      /* SDRAM external bank size = 64MB */
-#define EB3__SZ_128                     0x06000000      /* SDRAM external bank size = 128MB */
-#define EB3__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
-#define EB3__CAW_9                      0x10000000      /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_10                     0x20000000      /* SDRAM external bank column address width = 9 bits */
-#define EB3__CAW_11                     0x30000000      /* SDRAM external bank column address width = 9 bits */
-
-/* EBIU_SDSTAT Masks */
-#define SDCI                    0x00000001      /* SDRAM controller is idle  */
-#define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
-#define SDPUA                   0x00000004      /* SDRAM power up active  */
-#define SDRS                    0x00000008      /* SDRAM is in reset state */
-#define SDEASE              0x00000010  /* SDRAM EAB sticky error status - W1C */
-#define BGSTAT                  0x00000020      /* Bus granted */
-
-#endif                          /* _DEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
deleted file mode 100644
index 8bc46cd89a02..000000000000
--- a/include/asm-blackfin/mach-bf561/dma.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*****************************************************************************
-*
-*        BF-533/2/1 Specific Declarations
-*
-****************************************************************************/
-
-#ifndef _MACH_DMA_H_
-#define _MACH_DMA_H_
-
-#define MAX_BLACKFIN_DMA_CHANNEL 36
-
-#define CH_PPI0                 0
-#define CH_PPI                  (CH_PPI0)
-#define CH_PPI1                 1
-#define CH_SPORT0_RX            12
-#define CH_SPORT0_TX            13
-#define CH_SPORT1_RX            14
-#define CH_SPORT1_TX            15
-#define CH_SPI                  16
-#define CH_UART_RX              17
-#define CH_UART_TX              18
-#define CH_MEM_STREAM0_DEST     24       /* TX */
-#define CH_MEM_STREAM0_SRC      25       /* RX */
-#define CH_MEM_STREAM1_DEST     26       /* TX */
-#define CH_MEM_STREAM1_SRC      27       /* RX */
-#define CH_MEM_STREAM2_DEST     28
-#define CH_MEM_STREAM2_SRC      29
-#define CH_MEM_STREAM3_DEST     30
-#define CH_MEM_STREAM3_SRC      31
-#define CH_IMEM_STREAM0_DEST    32
-#define CH_IMEM_STREAM0_SRC     33
-#define CH_IMEM_STREAM1_DEST    34
-#define CH_IMEM_STREAM1_SRC     35
-
-#endif
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
deleted file mode 100644
index 6698389c5564..000000000000
--- a/include/asm-blackfin/mach-bf561/irq.h
+++ /dev/null
@@ -1,447 +0,0 @@
-
-/*
- * File:         include/asm-blackfin/mach-bf561/irq.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BF561_IRQ_H_
-#define _BF561_IRQ_H_
-
-/***********************************************************************
- * Interrupt source definitions:
-             Event Source               Core Event Name     IRQ No
-                                                (highest priority)
-            Emulation Events                    EMU         0
-            Reset                               RST         1
-            NMI                                 NMI         2
-            Exception                           EVX         3
-            Reserved                            --          4
-            Hardware Error                      IVHW        5
-            Core Timer                          IVTMR       6 *
-
-            PLL Wakeup Interrupt                IVG7        7
-            DMA1 Error (generic)                IVG7        8
-            DMA2 Error (generic)                IVG7        9
-            IMDMA Error (generic)               IVG7        10
-            PPI1 Error Interrupt                IVG7        11
-            PPI2 Error Interrupt                IVG7        12
-            SPORT0 Error Interrupt              IVG7        13
-            SPORT1 Error Interrupt              IVG7        14
-            SPI Error Interrupt                 IVG7        15
-            UART Error Interrupt                IVG7        16
-            Reserved Interrupt                  IVG7        17
-
-            DMA1 0  Interrupt(PPI1)             IVG8        18
-            DMA1 1  Interrupt(PPI2)             IVG8        19
-            DMA1 2  Interrupt                   IVG8        20
-            DMA1 3  Interrupt                   IVG8        21
-            DMA1 4  Interrupt                   IVG8        22
-            DMA1 5  Interrupt                   IVG8        23
-            DMA1 6  Interrupt                   IVG8        24
-            DMA1 7  Interrupt                   IVG8        25
-            DMA1 8  Interrupt                   IVG8        26
-            DMA1 9  Interrupt                   IVG8        27
-            DMA1 10 Interrupt                   IVG8        28
-            DMA1 11 Interrupt                   IVG8        29
-
-            DMA2 0  (SPORT0 RX)                 IVG9        30
-            DMA2 1  (SPORT0 TX)                 IVG9        31
-            DMA2 2  (SPORT1 RX)                 IVG9        32
-            DMA2 3  (SPORT2 TX)                 IVG9        33
-            DMA2 4  (SPI)                       IVG9        34
-            DMA2 5  (UART RX)                   IVG9        35
-            DMA2 6  (UART TX)                   IVG9        36
-            DMA2 7  Interrupt                   IVG9        37
-            DMA2 8  Interrupt                   IVG9        38
-            DMA2 9  Interrupt                   IVG9        39
-            DMA2 10 Interrupt                   IVG9        40
-            DMA2 11 Interrupt                   IVG9        41
-
-            TIMER 0  Interrupt                  IVG10       42
-            TIMER 1  Interrupt                  IVG10       43
-            TIMER 2  Interrupt                  IVG10       44
-            TIMER 3  Interrupt                  IVG10       45
-            TIMER 4  Interrupt                  IVG10       46
-            TIMER 5  Interrupt                  IVG10       47
-            TIMER 6  Interrupt                  IVG10       48
-            TIMER 7  Interrupt                  IVG10       49
-            TIMER 8  Interrupt                  IVG10       50
-            TIMER 9  Interrupt                  IVG10       51
-            TIMER 10 Interrupt                  IVG10       52
-            TIMER 11 Interrupt                  IVG10       53
-
-            Programmable Flags0 A (8)           IVG11       54
-            Programmable Flags0 B (8)           IVG11       55
-            Programmable Flags1 A (8)           IVG11       56
-            Programmable Flags1 B (8)           IVG11       57
-            Programmable Flags2 A (8)           IVG11       58
-            Programmable Flags2 B (8)           IVG11       59
-
-            MDMA1 0 write/read INT              IVG8        60
-            MDMA1 1 write/read INT              IVG8        61
-
-            MDMA2 0 write/read INT              IVG9        62
-            MDMA2 1 write/read INT              IVG9        63
-
-            IMDMA 0 write/read INT              IVG12       64
-            IMDMA 1 write/read INT              IVG12       65
-
-            Watch Dog Timer                     IVG13       66
-
-            Reserved interrupt                  IVG7        67
-            Reserved interrupt                  IVG7        68
-            Supplemental interrupt 0            IVG7        69
-            supplemental interrupt 1            IVG7        70
-
-            Softirq                             IVG14
-            System Call    --
-                 (lowest priority)              IVG15
-
- **********************************************************************/
-
-#define SYS_IRQS                71
-#define NR_PERI_INTS            64
-
-/*
- * The ABSTRACT IRQ definitions
- *  the first seven of the following are fixed,
- *  the rest you change if you need to.
- */
-/* IVG 0-6*/
-#define IRQ_EMU                 0       /* Emulation                */
-#define IRQ_RST                 1       /* Reset                    */
-#define IRQ_NMI                 2       /* Non Maskable Interrupt   */
-#define IRQ_EVX                 3       /* Exception                */
-#define IRQ_UNUSED              4       /* Reserved interrupt       */
-#define IRQ_HWERR               5       /* Hardware Error           */
-#define IRQ_CORETMR             6       /* Core timer               */
-
-#define IVG_BASE                7
-/* IVG 7  */
-#define IRQ_PLL_WAKEUP          (IVG_BASE + 0)  /* PLL Wakeup Interrupt     */
-#define IRQ_DMA1_ERROR          (IVG_BASE + 1)  /* DMA1   Error (general)   */
-#define IRQ_DMA_ERROR           IRQ_DMA1_ERROR  /* DMA1   Error (general)   */
-#define IRQ_DMA2_ERROR          (IVG_BASE + 2)  /* DMA2   Error (general)   */
-#define IRQ_IMDMA_ERROR         (IVG_BASE + 3)  /* IMDMA  Error Interrupt   */
-#define IRQ_PPI1_ERROR          (IVG_BASE + 4)  /* PPI1   Error Interrupt   */
-#define IRQ_PPI_ERROR           IRQ_PPI1_ERROR  /* PPI1   Error Interrupt   */
-#define IRQ_PPI2_ERROR          (IVG_BASE + 5)  /* PPI2   Error Interrupt   */
-#define IRQ_SPORT0_ERROR        (IVG_BASE + 6)  /* SPORT0 Error Interrupt   */
-#define IRQ_SPORT1_ERROR        (IVG_BASE + 7)  /* SPORT1 Error Interrupt   */
-#define IRQ_SPI_ERROR           (IVG_BASE + 8)  /* SPI    Error Interrupt   */
-#define IRQ_UART_ERROR          (IVG_BASE + 9)  /* UART   Error Interrupt   */
-#define IRQ_RESERVED_ERROR      (IVG_BASE + 10) /* Reversed     Interrupt   */
-/* IVG 8  */
-#define IRQ_DMA1_0              (IVG_BASE + 11) /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_PPI                 IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_PPI0                IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
-#define IRQ_DMA1_1              (IVG_BASE + 12) /* DMA1 1  Interrupt(PPI2)  */
-#define IRQ_PPI1                IRQ_DMA1_1      /* DMA1 1  Interrupt(PPI2)  */
-#define IRQ_DMA1_2              (IVG_BASE + 13) /* DMA1 2  Interrupt        */
-#define IRQ_DMA1_3              (IVG_BASE + 14) /* DMA1 3  Interrupt        */
-#define IRQ_DMA1_4              (IVG_BASE + 15) /* DMA1 4  Interrupt        */
-#define IRQ_DMA1_5              (IVG_BASE + 16) /* DMA1 5  Interrupt        */
-#define IRQ_DMA1_6              (IVG_BASE + 17) /* DMA1 6  Interrupt        */
-#define IRQ_DMA1_7              (IVG_BASE + 18) /* DMA1 7  Interrupt        */
-#define IRQ_DMA1_8              (IVG_BASE + 19) /* DMA1 8  Interrupt        */
-#define IRQ_DMA1_9              (IVG_BASE + 20) /* DMA1 9  Interrupt        */
-#define IRQ_DMA1_10             (IVG_BASE + 21) /* DMA1 10 Interrupt        */
-#define IRQ_DMA1_11             (IVG_BASE + 22) /* DMA1 11 Interrupt        */
-/* IVG 9  */
-#define IRQ_DMA2_0              (IVG_BASE + 23) /* DMA2 0  (SPORT0 RX)      */
-#define IRQ_SPORT0_RX           IRQ_DMA2_0      /* DMA2 0  (SPORT0 RX)      */
-#define IRQ_DMA2_1              (IVG_BASE + 24) /* DMA2 1  (SPORT0 TX)      */
-#define IRQ_SPORT0_TX           IRQ_DMA2_1      /* DMA2 1  (SPORT0 TX)      */
-#define IRQ_DMA2_2              (IVG_BASE + 25) /* DMA2 2  (SPORT1 RX)      */
-#define IRQ_SPORT1_RX           IRQ_DMA2_2      /* DMA2 2  (SPORT1 RX)      */
-#define IRQ_DMA2_3              (IVG_BASE + 26) /* DMA2 3  (SPORT2 TX)      */
-#define IRQ_SPORT1_TX           IRQ_DMA2_3      /* DMA2 3  (SPORT2 TX)      */
-#define IRQ_DMA2_4              (IVG_BASE + 27) /* DMA2 4  (SPI)            */
-#define IRQ_SPI                 IRQ_DMA2_4      /* DMA2 4  (SPI)            */
-#define IRQ_DMA2_5              (IVG_BASE + 28) /* DMA2 5  (UART RX)        */
-#define IRQ_UART_RX             IRQ_DMA2_5      /* DMA2 5  (UART RX)        */
-#define IRQ_DMA2_6              (IVG_BASE + 29) /* DMA2 6  (UART TX)        */
-#define IRQ_UART_TX             IRQ_DMA2_6      /* DMA2 6  (UART TX)        */
-#define IRQ_DMA2_7              (IVG_BASE + 30) /* DMA2 7  Interrupt        */
-#define IRQ_DMA2_8              (IVG_BASE + 31) /* DMA2 8  Interrupt        */
-#define IRQ_DMA2_9              (IVG_BASE + 32) /* DMA2 9  Interrupt        */
-#define IRQ_DMA2_10             (IVG_BASE + 33) /* DMA2 10 Interrupt        */
-#define IRQ_DMA2_11             (IVG_BASE + 34) /* DMA2 11 Interrupt        */
-/* IVG 10 */
-#define IRQ_TIMER0              (IVG_BASE + 35) /* TIMER 0  Interrupt       */
-#define IRQ_TIMER1              (IVG_BASE + 36) /* TIMER 1  Interrupt       */
-#define IRQ_TIMER2              (IVG_BASE + 37) /* TIMER 2  Interrupt       */
-#define IRQ_TIMER3              (IVG_BASE + 38) /* TIMER 3  Interrupt       */
-#define IRQ_TIMER4              (IVG_BASE + 39) /* TIMER 4  Interrupt       */
-#define IRQ_TIMER5              (IVG_BASE + 40) /* TIMER 5  Interrupt       */
-#define IRQ_TIMER6              (IVG_BASE + 41) /* TIMER 6  Interrupt       */
-#define IRQ_TIMER7              (IVG_BASE + 42) /* TIMER 7  Interrupt       */
-#define IRQ_TIMER8              (IVG_BASE + 43) /* TIMER 8  Interrupt       */
-#define IRQ_TIMER9              (IVG_BASE + 44) /* TIMER 9  Interrupt       */
-#define IRQ_TIMER10             (IVG_BASE + 45) /* TIMER 10 Interrupt       */
-#define IRQ_TIMER11             (IVG_BASE + 46) /* TIMER 11 Interrupt       */
-/* IVG 11 */
-#define IRQ_PROG0_INTA          (IVG_BASE + 47) /* Programmable Flags0 A (8) */
-#define IRQ_PROG_INTA           IRQ_PROG0_INTA  /* Programmable Flags0 A (8) */
-#define IRQ_PROG0_INTB          (IVG_BASE + 48) /* Programmable Flags0 B (8) */
-#define IRQ_PROG_INTB           IRQ_PROG0_INTB  /* Programmable Flags0 B (8) */
-#define IRQ_PROG1_INTA          (IVG_BASE + 49) /* Programmable Flags1 A (8) */
-#define IRQ_PROG1_INTB          (IVG_BASE + 50) /* Programmable Flags1 B (8) */
-#define IRQ_PROG2_INTA          (IVG_BASE + 51) /* Programmable Flags2 A (8) */
-#define IRQ_PROG2_INTB          (IVG_BASE + 52) /* Programmable Flags2 B (8) */
-/* IVG 8  */
-#define IRQ_DMA1_WRRD0          (IVG_BASE + 53) /* MDMA1 0 write/read INT   */
-#define IRQ_DMA_WRRD0           IRQ_DMA1_WRRD0  /* MDMA1 0 write/read INT   */
-#define IRQ_MEM_DMA0            IRQ_DMA1_WRRD0
-#define IRQ_DMA1_WRRD1          (IVG_BASE + 54) /* MDMA1 1 write/read INT   */
-#define IRQ_DMA_WRRD1           IRQ_DMA1_WRRD1  /* MDMA1 1 write/read INT   */
-#define IRQ_MEM_DMA1            IRQ_DMA1_WRRD1
-/* IVG 9  */
-#define IRQ_DMA2_WRRD0          (IVG_BASE + 55) /* MDMA2 0 write/read INT   */
-#define IRQ_MEM_DMA2            IRQ_DMA2_WRRD0
-#define IRQ_DMA2_WRRD1          (IVG_BASE + 56) /* MDMA2 1 write/read INT   */
-#define IRQ_MEM_DMA3            IRQ_DMA2_WRRD1
-/* IVG 12 */
-#define IRQ_IMDMA_WRRD0         (IVG_BASE + 57) /* IMDMA 0 write/read INT   */
-#define IRQ_IMEM_DMA0           IRQ_IMDMA_WRRD0
-#define IRQ_IMDMA_WRRD1         (IVG_BASE + 58) /* IMDMA 1 write/read INT   */
-#define IRQ_IMEM_DMA1           IRQ_IMDMA_WRRD1
-/* IVG 13 */
-#define IRQ_WATCH               (IVG_BASE + 59) /* Watch Dog Timer          */
-/* IVG 7  */
-#define IRQ_RESERVED_1          (IVG_BASE + 60) /* Reserved interrupt       */
-#define IRQ_RESERVED_2          (IVG_BASE + 61) /* Reserved interrupt       */
-#define IRQ_SUPPLE_0            (IVG_BASE + 62) /* Supplemental interrupt 0 */
-#define IRQ_SUPPLE_1            (IVG_BASE + 63) /* supplemental interrupt 1 */
-
-#define IRQ_PF0                 73
-#define IRQ_PF1                 74
-#define IRQ_PF2                 75
-#define IRQ_PF3                 76
-#define IRQ_PF4                 77
-#define IRQ_PF5                 78
-#define IRQ_PF6                 79
-#define IRQ_PF7                 80
-#define IRQ_PF8                 81
-#define IRQ_PF9                 82
-#define IRQ_PF10                83
-#define IRQ_PF11                84
-#define IRQ_PF12                85
-#define IRQ_PF13                86
-#define IRQ_PF14                87
-#define IRQ_PF15                88
-#define IRQ_PF16                89
-#define IRQ_PF17                90
-#define IRQ_PF18                91
-#define IRQ_PF19                92
-#define IRQ_PF20                93
-#define IRQ_PF21                94
-#define IRQ_PF22                95
-#define IRQ_PF23                96
-#define IRQ_PF24                97
-#define IRQ_PF25                98
-#define IRQ_PF26                99
-#define IRQ_PF27                100
-#define IRQ_PF28                101
-#define IRQ_PF29                102
-#define IRQ_PF30                103
-#define IRQ_PF31                104
-#define IRQ_PF32                105
-#define IRQ_PF33                106
-#define IRQ_PF34                107
-#define IRQ_PF35                108
-#define IRQ_PF36                109
-#define IRQ_PF37                110
-#define IRQ_PF38                111
-#define IRQ_PF39                112
-#define IRQ_PF40                113
-#define IRQ_PF41                114
-#define IRQ_PF42                115
-#define IRQ_PF43                116
-#define IRQ_PF44                117
-#define IRQ_PF45                118
-#define IRQ_PF46                119
-#define IRQ_PF47                120
-
-#define GPIO_IRQ_BASE           IRQ_PF0
-
-#define NR_IRQS                 (IRQ_PF47 + 1)
-
-#define IVG7                    7
-#define IVG8                    8
-#define IVG9                    9
-#define IVG10                   10
-#define IVG11                   11
-#define IVG12                   12
-#define IVG13                   13
-#define IVG14                   14
-#define IVG15                   15
-
-/*
- * DEFAULT PRIORITIES:
- */
-
-#define CONFIG_DEF_PLL_WAKEUP           7
-#define CONFIG_DEF_DMA1_ERROR           7
-#define CONFIG_DEF_DMA2_ERROR           7
-#define CONFIG_DEF_IMDMA_ERROR          7
-#define CONFIG_DEF_PPI1_ERROR           7
-#define CONFIG_DEF_PPI2_ERROR           7
-#define CONFIG_DEF_SPORT0_ERROR         7
-#define CONFIG_DEF_SPORT1_ERROR         7
-#define CONFIG_DEF_SPI_ERROR            7
-#define CONFIG_DEF_UART_ERROR           7
-#define CONFIG_DEF_RESERVED_ERROR       7
-#define CONFIG_DEF_DMA1_0               8
-#define CONFIG_DEF_DMA1_1               8
-#define CONFIG_DEF_DMA1_2               8
-#define CONFIG_DEF_DMA1_3               8
-#define CONFIG_DEF_DMA1_4               8
-#define CONFIG_DEF_DMA1_5               8
-#define CONFIG_DEF_DMA1_6               8
-#define CONFIG_DEF_DMA1_7               8
-#define CONFIG_DEF_DMA1_8               8
-#define CONFIG_DEF_DMA1_9               8
-#define CONFIG_DEF_DMA1_10              8
-#define CONFIG_DEF_DMA1_11              8
-#define CONFIG_DEF_DMA2_0               9
-#define CONFIG_DEF_DMA2_1               9
-#define CONFIG_DEF_DMA2_2               9
-#define CONFIG_DEF_DMA2_3               9
-#define CONFIG_DEF_DMA2_4               9
-#define CONFIG_DEF_DMA2_5               9
-#define CONFIG_DEF_DMA2_6               9
-#define CONFIG_DEF_DMA2_7               9
-#define CONFIG_DEF_DMA2_8               9
-#define CONFIG_DEF_DMA2_9               9
-#define CONFIG_DEF_DMA2_10              9
-#define CONFIG_DEF_DMA2_11              9
-#define CONFIG_DEF_TIMER0               10
-#define CONFIG_DEF_TIMER1               10
-#define CONFIG_DEF_TIMER2               10
-#define CONFIG_DEF_TIMER3               10
-#define CONFIG_DEF_TIMER4               10
-#define CONFIG_DEF_TIMER5               10
-#define CONFIG_DEF_TIMER6               10
-#define CONFIG_DEF_TIMER7               10
-#define CONFIG_DEF_TIMER8               10
-#define CONFIG_DEF_TIMER9               10
-#define CONFIG_DEF_TIMER10              10
-#define CONFIG_DEF_TIMER11              10
-#define CONFIG_DEF_PROG0_INTA           11
-#define CONFIG_DEF_PROG0_INTB           11
-#define CONFIG_DEF_PROG1_INTA           11
-#define CONFIG_DEF_PROG1_INTB           11
-#define CONFIG_DEF_PROG2_INTA           11
-#define CONFIG_DEF_PROG2_INTB           11
-#define CONFIG_DEF_DMA1_WRRD0           8
-#define CONFIG_DEF_DMA1_WRRD1           8
-#define CONFIG_DEF_DMA2_WRRD0           9
-#define CONFIG_DEF_DMA2_WRRD1           9
-#define CONFIG_DEF_IMDMA_WRRD0          12
-#define CONFIG_DEF_IMDMA_WRRD1          12
-#define CONFIG_DEF_WATCH                13
-#define CONFIG_DEF_RESERVED_1           7
-#define CONFIG_DEF_RESERVED_2           7
-#define CONFIG_DEF_SUPPLE_0             7
-#define CONFIG_DEF_SUPPLE_1             7
-
-/* IAR0 BIT FIELDS */
-#define IRQ_PLL_WAKEUP_POS                      0
-#define IRQ_DMA1_ERROR_POS                      4
-#define IRQ_DMA2_ERROR_POS                      8
-#define IRQ_IMDMA_ERROR_POS                     12
-#define IRQ_PPI0_ERROR_POS                      16
-#define IRQ_PPI1_ERROR_POS                      20
-#define IRQ_SPORT0_ERROR_POS            24
-#define IRQ_SPORT1_ERROR_POS            28
-/* IAR1 BIT FIELDS */
-#define IRQ_SPI_ERROR_POS                       0
-#define IRQ_UART_ERROR_POS                      4
-#define IRQ_RESERVED_ERROR_POS          8
-#define IRQ_DMA1_0_POS                  12
-#define IRQ_DMA1_1_POS                  16
-#define IRQ_DMA1_2_POS                  20
-#define IRQ_DMA1_3_POS                  24
-#define IRQ_DMA1_4_POS                  28
-/* IAR2 BIT FIELDS */
-#define IRQ_DMA1_5_POS                  0
-#define IRQ_DMA1_6_POS                  4
-#define IRQ_DMA1_7_POS                  8
-#define IRQ_DMA1_8_POS                  12
-#define IRQ_DMA1_9_POS                  16
-#define IRQ_DMA1_10_POS                 20
-#define IRQ_DMA1_11_POS                 24
-#define IRQ_DMA2_0_POS                  28
-/* IAR3 BIT FIELDS */
-#define IRQ_DMA2_1_POS                  0
-#define IRQ_DMA2_2_POS                  4
-#define IRQ_DMA2_3_POS                  8
-#define IRQ_DMA2_4_POS                  12
-#define IRQ_DMA2_5_POS                  16
-#define IRQ_DMA2_6_POS                  20
-#define IRQ_DMA2_7_POS                  24
-#define IRQ_DMA2_8_POS                  28
-/* IAR4 BIT FIELDS */
-#define IRQ_DMA2_9_POS                  0
-#define IRQ_DMA2_10_POS                 4
-#define IRQ_DMA2_11_POS                 8
-#define IRQ_TIMER0_POS                  12
-#define IRQ_TIMER1_POS                  16
-#define IRQ_TIMER2_POS                  20
-#define IRQ_TIMER3_POS                  24
-#define IRQ_TIMER4_POS                  28
-/* IAR5 BIT FIELDS */
-#define IRQ_TIMER5_POS                  0
-#define IRQ_TIMER6_POS                  4
-#define IRQ_TIMER7_POS                  8
-#define IRQ_TIMER8_POS                  12
-#define IRQ_TIMER9_POS                  16
-#define IRQ_TIMER10_POS                 20
-#define IRQ_TIMER11_POS                 24
-#define IRQ_PROG0_INTA_POS                      28
-/* IAR6 BIT FIELDS */
-#define IRQ_PROG0_INTB_POS                      0
-#define IRQ_PROG1_INTA_POS                      4
-#define IRQ_PROG1_INTB_POS                      8
-#define IRQ_PROG2_INTA_POS                      12
-#define IRQ_PROG2_INTB_POS                      16
-#define IRQ_DMA1_WRRD0_POS                      20
-#define IRQ_DMA1_WRRD1_POS                      24
-#define IRQ_DMA2_WRRD0_POS                      28
-/* IAR7 BIT FIELDS */
-#define IRQ_DMA2_WRRD1_POS                      0
-#define IRQ_IMDMA_WRRD0_POS                     4
-#define IRQ_IMDMA_WRRD1_POS                     8
-#define IRQ_WDTIMER_POS                 12
-#define IRQ_RESERVED_1_POS                      16
-#define IRQ_RESERVED_2_POS                      20
-#define IRQ_SUPPLE_0_POS                        24
-#define IRQ_SUPPLE_1_POS                        28
-
-#endif                          /* _BF561_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf561/mem_init.h b/include/asm-blackfin/mach-bf561/mem_init.h
deleted file mode 100644
index e163260bca18..000000000000
--- a/include/asm-blackfin/mach-bf561/mem_init.h
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-bf561/mem_init.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Rev:
- *
- * Modified:
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
-#if (CONFIG_SCLK_HZ > 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_7
-#define SDRAM_tRAS_num  7
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_6
-#define SDRAM_tRAS_num  6
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_5
-#define SDRAM_tRAS_num  5
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  4
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
-#define SDRAM_tRP       TRP_2
-#define SDRAM_tRP_num   2
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_2
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_4
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_3
-#define SDRAM_tRAS_num  3
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_2
-#define SDRAM_tRAS_num  2
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#if (CONFIG_SCLK_HZ <= 29850746)
-#define SDRAM_tRP       TRP_1
-#define SDRAM_tRP_num   1
-#define SDRAM_tRAS      TRAS_1
-#define SDRAM_tRAS_num  1
-#define SDRAM_tRCD      TRCD_1
-#define SDRAM_tWR       TWR_2
-#endif
-#endif
-
-#if (CONFIG_MEM_MT48LC16M16A2TG_75)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_MT48LC8M32B2B5_7)
-  /*SDRAM INFORMATION: */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-#if (CONFIG_MEM_GENERIC_BOARD)
-  /*SDRAM INFORMATION: Modify this for your board */
-#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
-#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
-#define SDRAM_CL    CL_3
-#endif
-
-/* Equation from section 17 (p17-46) of BF533 HRM */
-#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
-
-/* Enable SCLK Out */
-#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
-
-#if defined CONFIG_CLKIN_HALF
-#define CLKIN_HALF       1
-#else
-#define CLKIN_HALF       0
-#endif
-
-#if defined CONFIG_PLL_BYPASS
-#define PLL_BYPASS      1
-#else
-#define PLL_BYPASS       0
-#endif
-
-/***************************************Currently Not Being Used *********************************/
-#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
-#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
-
-#if (flash_EBIU_AMBCTL_TT > 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_4
-#endif
-#if (flash_EBIU_AMBCTL_TT == 3)
-#define flash_EBIU_AMBCTL0_TT   B0TT_3
-#endif
-#if (flash_EBIU_AMBCTL_TT == 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_2
-#endif
-#if (flash_EBIU_AMBCTL_TT < 2)
-#define flash_EBIU_AMBCTL0_TT   B0TT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_ST > 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_4
-#endif
-#if (flash_EBIU_AMBCTL_ST == 3)
-#define flash_EBIU_AMBCTL0_ST   B0ST_3
-#endif
-#if (flash_EBIU_AMBCTL_ST == 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_2
-#endif
-#if (flash_EBIU_AMBCTL_ST < 2)
-#define flash_EBIU_AMBCTL0_ST   B0ST_1
-#endif
-
-#if (flash_EBIU_AMBCTL_HT > 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_3
-#endif
-#if (flash_EBIU_AMBCTL_HT == 2)
-#define flash_EBIU_AMBCTL0_HT   B0HT_2
-#endif
-#if (flash_EBIU_AMBCTL_HT == 1)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_0
-#endif
-#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
-#define flash_EBIU_AMBCTL0_HT   B0HT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_WAT > 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 14)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 13)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 12)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 11)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 10)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 9)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 8)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 7)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 6)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 5)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 4)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 3)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 2)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
-#endif
-#if (flash_EBIU_AMBCTL_WAT == 1)
-#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
-#endif
-
-#if (flash_EBIU_AMBCTL_RAT > 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 14)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 13)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 12)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 11)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 10)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 9)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 8)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 7)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 6)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 5)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 4)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 3)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 2)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
-#endif
-#if (flash_EBIU_AMBCTL_RAT == 1)
-#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
-#endif
-
-#define flash_EBIU_AMBCTL0  \
-        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
-         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
deleted file mode 100644
index c26d8486cc4b..000000000000
--- a/include/asm-blackfin/mach-bf561/mem_map.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * Memory MAP
- * Common header file for blackfin BF561 of processors.
- */
-
-#ifndef _MEM_MAP_561_H_
-#define _MEM_MAP_561_H_
-
-#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
-#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
-
-/* Async Memory Banks */
-#define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
-#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
-#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
-#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
-#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
-#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
-
-/* Boot ROM Memory */
-
-#define BOOT_ROM_START          0xEF000000
-#define BOOT_ROM_LENGTH         0x800
-
-/* Level 1 Memory */
-
-#ifdef CONFIG_BFIN_ICACHE
-#define BFIN_ICACHESIZE (16*1024)
-#else
-#define BFIN_ICACHESIZE (0*1024)
-#endif
-
-/* Memory Map for ADSP-BF561 processors */
-
-#ifdef CONFIG_BF561
-#define L1_CODE_START     0xFFA00000
-#define L1_DATA_A_START     0xFF800000
-#define L1_DATA_B_START     0xFF900000
-
-#define L1_CODE_LENGTH      0x4000
-
-#ifdef CONFIG_BFIN_DCACHE
-
-#ifdef CONFIG_BFIN_DCACHE_BANKA
-#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (16*1024)
-#define BFIN_DSUPBANKS  1
-#else
-#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
-#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
-#define BFIN_DCACHESIZE (32*1024)
-#define BFIN_DSUPBANKS  2
-#endif
-
-#else
-#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
-#define L1_DATA_A_LENGTH      0x8000
-#define L1_DATA_B_LENGTH      0x8000
-#define BFIN_DCACHESIZE (0*1024)
-#define BFIN_DSUPBANKS  0
-#endif /*CONFIG_BFIN_DCACHE*/
-#endif
-
-/* Level 2 Memory */
-#define L2_START                0xFEB00000
-#define L2_LENGTH               0x20000
-
-/* Scratch Pad Memory */
-
-#define L1_SCRATCH_START        0xFFB00000
-#define L1_SCRATCH_LENGTH       0x1000
-
-#endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf561/portmux.h b/include/asm-blackfin/mach-bf561/portmux.h
deleted file mode 100644
index a6ee8206efb6..000000000000
--- a/include/asm-blackfin/mach-bf561/portmux.h
+++ /dev/null
@@ -1,89 +0,0 @@
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES   MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK      (P_DONTCARE)
-#define P_PPI0_FS1      (P_DONTCARE)
-#define P_PPI0_FS2      (P_DONTCARE)
-#define P_PPI0_FS3      (P_DONTCARE)
-#define P_PPI0_D15      (P_DEFINED | P_IDENT(GPIO_PF47))
-#define P_PPI0_D14      (P_DEFINED | P_IDENT(GPIO_PF46))
-#define P_PPI0_D13      (P_DEFINED | P_IDENT(GPIO_PF45))
-#define P_PPI0_D12      (P_DEFINED | P_IDENT(GPIO_PF44))
-#define P_PPI0_D11      (P_DEFINED | P_IDENT(GPIO_PF43))
-#define P_PPI0_D10      (P_DEFINED | P_IDENT(GPIO_PF42))
-#define P_PPI0_D9       (P_DEFINED | P_IDENT(GPIO_PF41))
-#define P_PPI0_D8       (P_DEFINED | P_IDENT(GPIO_PF40))
-#define P_PPI0_D0       (P_DONTCARE)
-#define P_PPI0_D1       (P_DONTCARE)
-#define P_PPI0_D2       (P_DONTCARE)
-#define P_PPI0_D3       (P_DONTCARE)
-#define P_PPI0_D4       (P_DONTCARE)
-#define P_PPI0_D5       (P_DONTCARE)
-#define P_PPI0_D6       (P_DONTCARE)
-#define P_PPI0_D7       (P_DONTCARE)
-#define P_PPI1_CLK      (P_DONTCARE)
-#define P_PPI1_FS1      (P_DONTCARE)
-#define P_PPI1_FS2      (P_DONTCARE)
-#define P_PPI1_FS3      (P_DONTCARE)
-#define P_PPI1_D15      (P_DEFINED | P_IDENT(GPIO_PF39))
-#define P_PPI1_D14      (P_DEFINED | P_IDENT(GPIO_PF38))
-#define P_PPI1_D13      (P_DEFINED | P_IDENT(GPIO_PF37))
-#define P_PPI1_D12      (P_DEFINED | P_IDENT(GPIO_PF36))
-#define P_PPI1_D11      (P_DEFINED | P_IDENT(GPIO_PF35))
-#define P_PPI1_D10      (P_DEFINED | P_IDENT(GPIO_PF34))
-#define P_PPI1_D9       (P_DEFINED | P_IDENT(GPIO_PF33))
-#define P_PPI1_D8       (P_DEFINED | P_IDENT(GPIO_PF32))
-#define P_PPI1_D0       (P_DONTCARE)
-#define P_PPI1_D1       (P_DONTCARE)
-#define P_PPI1_D2       (P_DONTCARE)
-#define P_PPI1_D3       (P_DONTCARE)
-#define P_PPI1_D4       (P_DONTCARE)
-#define P_PPI1_D5       (P_DONTCARE)
-#define P_PPI1_D6       (P_DONTCARE)
-#define P_PPI1_D7       (P_DONTCARE)
-#define P_SPORT1_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF31))
-#define P_SPORT1_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF30))
-#define P_SPORT0_TSCLK  (P_DEFINED | P_IDENT(GPIO_PF29))
-#define P_SPORT0_RSCLK  (P_DEFINED | P_IDENT(GPIO_PF28))
-#define P_UART0_RX      (P_DEFINED | P_IDENT(GPIO_PF27))
-#define P_UART0_TX      (P_DEFINED | P_IDENT(GPIO_PF26))
-#define P_SPORT1_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF25))
-#define P_SPORT1_RFS    (P_DEFINED | P_IDENT(GPIO_PF24))
-#define P_SPORT1_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF23))
-#define P_SPORT1_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF22))
-#define P_SPORT1_TFS    (P_DEFINED | P_IDENT(GPIO_PF21))
-#define P_SPORT1_DRPRI  (P_DONTCARE)
-#define P_SPORT0_DRSEC  (P_DEFINED | P_IDENT(GPIO_PF20))
-#define P_SPORT0_RFS    (P_DEFINED | P_IDENT(GPIO_PF19))
-#define P_SPORT0_DTPRI  (P_DEFINED | P_IDENT(GPIO_PF18))
-#define P_SPORT0_DTSEC  (P_DEFINED | P_IDENT(GPIO_PF17))
-#define P_SPORT0_TFS    (P_DEFINED | P_IDENT(GPIO_PF16))
-#define P_SPORT0_DRPRI  (P_DONTCARE)
-#define P_TMRCLK        (P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_SPI0_SSEL7    (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6    (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5    (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4    (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3    (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2    (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1    (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS       (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_TMR11         (P_DONTCARE)
-#define P_TMR10         (P_DONTCARE)
-#define P_TMR9          (P_DONTCARE)
-#define P_TMR8          (P_DONTCARE)
-#define P_TMR7          (P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_TMR6          (P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_TMR5          (P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_TMR4          (P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_TMR3          (P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_TMR2          (P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_TMR1          (P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_TMR0          (P_DEFINED | P_IDENT(GPIO_PF0))
-#define P_SPI0_MOSI     (P_DONTCARE)
-#define P_SPI0_MISO     (P_DONTCARE)
-#define P_SPI0_SCK      (P_DONTCARE)
-
-#endif /* _MACH_PORTMUX_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
deleted file mode 100644
index d39c396f850d..000000000000
--- a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+++ /dev/null
@@ -1,328 +0,0 @@
- /*
-  * File:        include/asm-blackfin/mach-common/cdef_LPBlackfin.h
-  * Based on:
-  * Author:      unknown
-  *              COPYRIGHT 2005 Analog Devices
-  * Created:     ?
-  * Description:
-  *
-  * Modified:
-  *
-  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2, or (at your option)
-  * any later version.
-  *
-  * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
-  *
-  * You should have received a copy of the GNU General Public License
-  * along with this program; see the file COPYING.
-  * If not, write to the Free Software Foundation,
-  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-  */
-
-#ifndef _CDEF_LPBLACKFIN_H
-#define _CDEF_LPBLACKFIN_H
-
-/*#if !defined(__ADSPLPBLACKFIN__)
-#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
-#endif
-*/
-#include <asm/mach-common/def_LPBlackfin.h>
-
-/*Cache & SRAM Memory*/
-#define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
-#define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
-#define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
-#define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
-#define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
-#define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
-#define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
-#define bfin_write_DCPLB_FAULT_ADDR(val)     bfin_write32(DCPLB_FAULT_ADDR,val)
-/*
-#define MMR_TIMEOUT            0xFFE00010
-*/
-#define bfin_read_DCPLB_ADDR0()              bfin_read32(DCPLB_ADDR0)
-#define bfin_write_DCPLB_ADDR0(val)          bfin_write32(DCPLB_ADDR0,val)
-#define bfin_read_DCPLB_ADDR1()              bfin_read32(DCPLB_ADDR1)
-#define bfin_write_DCPLB_ADDR1(val)          bfin_write32(DCPLB_ADDR1,val)
-#define bfin_read_DCPLB_ADDR2()              bfin_read32(DCPLB_ADDR2)
-#define bfin_write_DCPLB_ADDR2(val)          bfin_write32(DCPLB_ADDR2,val)
-#define bfin_read_DCPLB_ADDR3()              bfin_read32(DCPLB_ADDR3)
-#define bfin_write_DCPLB_ADDR3(val)          bfin_write32(DCPLB_ADDR3,val)
-#define bfin_read_DCPLB_ADDR4()              bfin_read32(DCPLB_ADDR4)
-#define bfin_write_DCPLB_ADDR4(val)          bfin_write32(DCPLB_ADDR4,val)
-#define bfin_read_DCPLB_ADDR5()              bfin_read32(DCPLB_ADDR5)
-#define bfin_write_DCPLB_ADDR5(val)          bfin_write32(DCPLB_ADDR5,val)
-#define bfin_read_DCPLB_ADDR6()              bfin_read32(DCPLB_ADDR6)
-#define bfin_write_DCPLB_ADDR6(val)          bfin_write32(DCPLB_ADDR6,val)
-#define bfin_read_DCPLB_ADDR7()              bfin_read32(DCPLB_ADDR7)
-#define bfin_write_DCPLB_ADDR7(val)          bfin_write32(DCPLB_ADDR7,val)
-#define bfin_read_DCPLB_ADDR8()              bfin_read32(DCPLB_ADDR8)
-#define bfin_write_DCPLB_ADDR8(val)          bfin_write32(DCPLB_ADDR8,val)
-#define bfin_read_DCPLB_ADDR9()              bfin_read32(DCPLB_ADDR9)
-#define bfin_write_DCPLB_ADDR9(val)          bfin_write32(DCPLB_ADDR9,val)
-#define bfin_read_DCPLB_ADDR10()             bfin_read32(DCPLB_ADDR10)
-#define bfin_write_DCPLB_ADDR10(val)         bfin_write32(DCPLB_ADDR10,val)
-#define bfin_read_DCPLB_ADDR11()             bfin_read32(DCPLB_ADDR11)
-#define bfin_write_DCPLB_ADDR11(val)         bfin_write32(DCPLB_ADDR11,val)
-#define bfin_read_DCPLB_ADDR12()             bfin_read32(DCPLB_ADDR12)
-#define bfin_write_DCPLB_ADDR12(val)         bfin_write32(DCPLB_ADDR12,val)
-#define bfin_read_DCPLB_ADDR13()             bfin_read32(DCPLB_ADDR13)
-#define bfin_write_DCPLB_ADDR13(val)         bfin_write32(DCPLB_ADDR13,val)
-#define bfin_read_DCPLB_ADDR14()             bfin_read32(DCPLB_ADDR14)
-#define bfin_write_DCPLB_ADDR14(val)         bfin_write32(DCPLB_ADDR14,val)
-#define bfin_read_DCPLB_ADDR15()             bfin_read32(DCPLB_ADDR15)
-#define bfin_write_DCPLB_ADDR15(val)         bfin_write32(DCPLB_ADDR15,val)
-#define bfin_read_DCPLB_DATA0()              bfin_read32(DCPLB_DATA0)
-#define bfin_write_DCPLB_DATA0(val)          bfin_write32(DCPLB_DATA0,val)
-#define bfin_read_DCPLB_DATA1()              bfin_read32(DCPLB_DATA1)
-#define bfin_write_DCPLB_DATA1(val)          bfin_write32(DCPLB_DATA1,val)
-#define bfin_read_DCPLB_DATA2()              bfin_read32(DCPLB_DATA2)
-#define bfin_write_DCPLB_DATA2(val)          bfin_write32(DCPLB_DATA2,val)
-#define bfin_read_DCPLB_DATA3()              bfin_read32(DCPLB_DATA3)
-#define bfin_write_DCPLB_DATA3(val)          bfin_write32(DCPLB_DATA3,val)
-#define bfin_read_DCPLB_DATA4()              bfin_read32(DCPLB_DATA4)
-#define bfin_write_DCPLB_DATA4(val)          bfin_write32(DCPLB_DATA4,val)
-#define bfin_read_DCPLB_DATA5()              bfin_read32(DCPLB_DATA5)
-#define bfin_write_DCPLB_DATA5(val)          bfin_write32(DCPLB_DATA5,val)
-#define bfin_read_DCPLB_DATA6()              bfin_read32(DCPLB_DATA6)
-#define bfin_write_DCPLB_DATA6(val)          bfin_write32(DCPLB_DATA6,val)
-#define bfin_read_DCPLB_DATA7()              bfin_read32(DCPLB_DATA7)
-#define bfin_write_DCPLB_DATA7(val)          bfin_write32(DCPLB_DATA7,val)
-#define bfin_read_DCPLB_DATA8()              bfin_read32(DCPLB_DATA8)
-#define bfin_write_DCPLB_DATA8(val)          bfin_write32(DCPLB_DATA8,val)
-#define bfin_read_DCPLB_DATA9()              bfin_read32(DCPLB_DATA9)
-#define bfin_write_DCPLB_DATA9(val)          bfin_write32(DCPLB_DATA9,val)
-#define bfin_read_DCPLB_DATA10()             bfin_read32(DCPLB_DATA10)
-#define bfin_write_DCPLB_DATA10(val)         bfin_write32(DCPLB_DATA10,val)
-#define bfin_read_DCPLB_DATA11()             bfin_read32(DCPLB_DATA11)
-#define bfin_write_DCPLB_DATA11(val)         bfin_write32(DCPLB_DATA11,val)
-#define bfin_read_DCPLB_DATA12()             bfin_read32(DCPLB_DATA12)
-#define bfin_write_DCPLB_DATA12(val)         bfin_write32(DCPLB_DATA12,val)
-#define bfin_read_DCPLB_DATA13()             bfin_read32(DCPLB_DATA13)
-#define bfin_write_DCPLB_DATA13(val)         bfin_write32(DCPLB_DATA13,val)
-#define bfin_read_DCPLB_DATA14()             bfin_read32(DCPLB_DATA14)
-#define bfin_write_DCPLB_DATA14(val)         bfin_write32(DCPLB_DATA14,val)
-#define bfin_read_DCPLB_DATA15()             bfin_read32(DCPLB_DATA15)
-#define bfin_write_DCPLB_DATA15(val)         bfin_write32(DCPLB_DATA15,val)
-#define bfin_read_DTEST_COMMAND()            bfin_read32(DTEST_COMMAND)
-#define bfin_write_DTEST_COMMAND(val)        bfin_write32(DTEST_COMMAND,val)
-/*
-#define DTEST_INDEX            0xFFE00304
-*/
-#define bfin_read_DTEST_DATA0()              bfin_read32(DTEST_DATA0)
-#define bfin_write_DTEST_DATA0(val)          bfin_write32(DTEST_DATA0,val)
-#define bfin_read_DTEST_DATA1()              bfin_read32(DTEST_DATA1)
-#define bfin_write_DTEST_DATA1(val)          bfin_write32(DTEST_DATA1,val)
-/*
-#define DTEST_DATA2            0xFFE00408
-#define DTEST_DATA3            0xFFE0040C
-*/
-#define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
-#define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
-#define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
-#define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
-#define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)
-#define bfin_write_ICPLB_FAULT_ADDR(val)     bfin_write32(ICPLB_FAULT_ADDR,val)
-#define bfin_read_ICPLB_ADDR0()              bfin_read32(ICPLB_ADDR0)
-#define bfin_write_ICPLB_ADDR0(val)          bfin_write32(ICPLB_ADDR0,val)
-#define bfin_read_ICPLB_ADDR1()              bfin_read32(ICPLB_ADDR1)
-#define bfin_write_ICPLB_ADDR1(val)          bfin_write32(ICPLB_ADDR1,val)
-#define bfin_read_ICPLB_ADDR2()              bfin_read32(ICPLB_ADDR2)
-#define bfin_write_ICPLB_ADDR2(val)          bfin_write32(ICPLB_ADDR2,val)
-#define bfin_read_ICPLB_ADDR3()              bfin_read32(ICPLB_ADDR3)
-#define bfin_write_ICPLB_ADDR3(val)          bfin_write32(ICPLB_ADDR3,val)
-#define bfin_read_ICPLB_ADDR4()              bfin_read32(ICPLB_ADDR4)
-#define bfin_write_ICPLB_ADDR4(val)          bfin_write32(ICPLB_ADDR4,val)
-#define bfin_read_ICPLB_ADDR5()              bfin_read32(ICPLB_ADDR5)
-#define bfin_write_ICPLB_ADDR5(val)          bfin_write32(ICPLB_ADDR5,val)
-#define bfin_read_ICPLB_ADDR6()              bfin_read32(ICPLB_ADDR6)
-#define bfin_write_ICPLB_ADDR6(val)          bfin_write32(ICPLB_ADDR6,val)
-#define bfin_read_ICPLB_ADDR7()              bfin_read32(ICPLB_ADDR7)
-#define bfin_write_ICPLB_ADDR7(val)          bfin_write32(ICPLB_ADDR7,val)
-#define bfin_read_ICPLB_ADDR8()              bfin_read32(ICPLB_ADDR8)
-#define bfin_write_ICPLB_ADDR8(val)          bfin_write32(ICPLB_ADDR8,val)
-#define bfin_read_ICPLB_ADDR9()              bfin_read32(ICPLB_ADDR9)
-#define bfin_write_ICPLB_ADDR9(val)          bfin_write32(ICPLB_ADDR9,val)
-#define bfin_read_ICPLB_ADDR10()             bfin_read32(ICPLB_ADDR10)
-#define bfin_write_ICPLB_ADDR10(val)         bfin_write32(ICPLB_ADDR10,val)
-#define bfin_read_ICPLB_ADDR11()             bfin_read32(ICPLB_ADDR11)
-#define bfin_write_ICPLB_ADDR11(val)         bfin_write32(ICPLB_ADDR11,val)
-#define bfin_read_ICPLB_ADDR12()             bfin_read32(ICPLB_ADDR12)
-#define bfin_write_ICPLB_ADDR12(val)         bfin_write32(ICPLB_ADDR12,val)
-#define bfin_read_ICPLB_ADDR13()             bfin_read32(ICPLB_ADDR13)
-#define bfin_write_ICPLB_ADDR13(val)         bfin_write32(ICPLB_ADDR13,val)
-#define bfin_read_ICPLB_ADDR14()             bfin_read32(ICPLB_ADDR14)
-#define bfin_write_ICPLB_ADDR14(val)         bfin_write32(ICPLB_ADDR14,val)
-#define bfin_read_ICPLB_ADDR15()             bfin_read32(ICPLB_ADDR15)
-#define bfin_write_ICPLB_ADDR15(val)         bfin_write32(ICPLB_ADDR15,val)
-#define bfin_read_ICPLB_DATA0()              bfin_read32(ICPLB_DATA0)
-#define bfin_write_ICPLB_DATA0(val)          bfin_write32(ICPLB_DATA0,val)
-#define bfin_read_ICPLB_DATA1()              bfin_read32(ICPLB_DATA1)
-#define bfin_write_ICPLB_DATA1(val)          bfin_write32(ICPLB_DATA1,val)
-#define bfin_read_ICPLB_DATA2()              bfin_read32(ICPLB_DATA2)
-#define bfin_write_ICPLB_DATA2(val)          bfin_write32(ICPLB_DATA2,val)
-#define bfin_read_ICPLB_DATA3()              bfin_read32(ICPLB_DATA3)
-#define bfin_write_ICPLB_DATA3(val)          bfin_write32(ICPLB_DATA3,val)
-#define bfin_read_ICPLB_DATA4()              bfin_read32(ICPLB_DATA4)
-#define bfin_write_ICPLB_DATA4(val)          bfin_write32(ICPLB_DATA4,val)
-#define bfin_read_ICPLB_DATA5()              bfin_read32(ICPLB_DATA5)
-#define bfin_write_ICPLB_DATA5(val)          bfin_write32(ICPLB_DATA5,val)
-#define bfin_read_ICPLB_DATA6()              bfin_read32(ICPLB_DATA6)
-#define bfin_write_ICPLB_DATA6(val)          bfin_write32(ICPLB_DATA6,val)
-#define bfin_read_ICPLB_DATA7()              bfin_read32(ICPLB_DATA7)
-#define bfin_write_ICPLB_DATA7(val)          bfin_write32(ICPLB_DATA7,val)
-#define bfin_read_ICPLB_DATA8()              bfin_read32(ICPLB_DATA8)
-#define bfin_write_ICPLB_DATA8(val)          bfin_write32(ICPLB_DATA8,val)
-#define bfin_read_ICPLB_DATA9()              bfin_read32(ICPLB_DATA9)
-#define bfin_write_ICPLB_DATA9(val)          bfin_write32(ICPLB_DATA9,val)
-#define bfin_read_ICPLB_DATA10()             bfin_read32(ICPLB_DATA10)
-#define bfin_write_ICPLB_DATA10(val)         bfin_write32(ICPLB_DATA10,val)
-#define bfin_read_ICPLB_DATA11()             bfin_read32(ICPLB_DATA11)
-#define bfin_write_ICPLB_DATA11(val)         bfin_write32(ICPLB_DATA11,val)
-#define bfin_read_ICPLB_DATA12()             bfin_read32(ICPLB_DATA12)
-#define bfin_write_ICPLB_DATA12(val)         bfin_write32(ICPLB_DATA12,val)
-#define bfin_read_ICPLB_DATA13()             bfin_read32(ICPLB_DATA13)
-#define bfin_write_ICPLB_DATA13(val)         bfin_write32(ICPLB_DATA13,val)
-#define bfin_read_ICPLB_DATA14()             bfin_read32(ICPLB_DATA14)
-#define bfin_write_ICPLB_DATA14(val)         bfin_write32(ICPLB_DATA14,val)
-#define bfin_read_ICPLB_DATA15()             bfin_read32(ICPLB_DATA15)
-#define bfin_write_ICPLB_DATA15(val)         bfin_write32(ICPLB_DATA15,val)
-#define bfin_read_ITEST_COMMAND()            bfin_read32(ITEST_COMMAND)
-#define bfin_write_ITEST_COMMAND(val)        bfin_write32(ITEST_COMMAND,val)
-#if 0
-#define ITEST_INDEX            0xFFE01304   /* Instruction Test Index Register */
-#endif
-#define bfin_read_ITEST_DATA0()              bfin_read32(ITEST_DATA0)
-#define bfin_write_ITEST_DATA0(val)          bfin_write32(ITEST_DATA0,val)
-#define bfin_read_ITEST_DATA1()              bfin_read32(ITEST_DATA1)
-#define bfin_write_ITEST_DATA1(val)          bfin_write32(ITEST_DATA1,val)
-
-/* Event/Interrupt Registers*/
-
-#define bfin_read_EVT0()                     bfin_read32(EVT0)
-#define bfin_write_EVT0(val)                 bfin_write32(EVT0,val)
-#define bfin_read_EVT1()                     bfin_read32(EVT1)
-#define bfin_write_EVT1(val)                 bfin_write32(EVT1,val)
-#define bfin_read_EVT2()                     bfin_read32(EVT2)
-#define bfin_write_EVT2(val)                 bfin_write32(EVT2,val)
-#define bfin_read_EVT3()                     bfin_read32(EVT3)
-#define bfin_write_EVT3(val)                 bfin_write32(EVT3,val)
-#define bfin_read_EVT4()                     bfin_read32(EVT4)
-#define bfin_write_EVT4(val)                 bfin_write32(EVT4,val)
-#define bfin_read_EVT5()                     bfin_read32(EVT5)
-#define bfin_write_EVT5(val)                 bfin_write32(EVT5,val)
-#define bfin_read_EVT6()                     bfin_read32(EVT6)
-#define bfin_write_EVT6(val)                 bfin_write32(EVT6,val)
-#define bfin_read_EVT7()                     bfin_read32(EVT7)
-#define bfin_write_EVT7(val)                 bfin_write32(EVT7,val)
-#define bfin_read_EVT8()                     bfin_read32(EVT8)
-#define bfin_write_EVT8(val)                 bfin_write32(EVT8,val)
-#define bfin_read_EVT9()                     bfin_read32(EVT9)
-#define bfin_write_EVT9(val)                 bfin_write32(EVT9,val)
-#define bfin_read_EVT10()                    bfin_read32(EVT10)
-#define bfin_write_EVT10(val)                bfin_write32(EVT10,val)
-#define bfin_read_EVT11()                    bfin_read32(EVT11)
-#define bfin_write_EVT11(val)                bfin_write32(EVT11,val)
-#define bfin_read_EVT12()                    bfin_read32(EVT12)
-#define bfin_write_EVT12(val)                bfin_write32(EVT12,val)
-#define bfin_read_EVT13()                    bfin_read32(EVT13)
-#define bfin_write_EVT13(val)                bfin_write32(EVT13,val)
-#define bfin_read_EVT14()                    bfin_read32(EVT14)
-#define bfin_write_EVT14(val)                bfin_write32(EVT14,val)
-#define bfin_read_EVT15()                    bfin_read32(EVT15)
-#define bfin_write_EVT15(val)                bfin_write32(EVT15,val)
-#define bfin_read_IMASK()                    bfin_read32(IMASK)
-#define bfin_write_IMASK(val)                bfin_write32(IMASK,val)
-#define bfin_read_IPEND()                    bfin_read32(IPEND)
-#define bfin_write_IPEND(val)                bfin_write32(IPEND,val)
-#define bfin_read_ILAT()                     bfin_read32(ILAT)
-#define bfin_write_ILAT(val)                 bfin_write32(ILAT,val)
-
-/*Core Timer Registers*/
-#define bfin_read_TCNTL()                    bfin_read32(TCNTL)
-#define bfin_write_TCNTL(val)                bfin_write32(TCNTL,val)
-#define bfin_read_TPERIOD()                  bfin_read32(TPERIOD)
-#define bfin_write_TPERIOD(val)              bfin_write32(TPERIOD,val)
-#define bfin_read_TSCALE()                   bfin_read32(TSCALE)
-#define bfin_write_TSCALE(val)               bfin_write32(TSCALE,val)
-#define bfin_read_TCOUNT()                   bfin_read32(TCOUNT)
-#define bfin_write_TCOUNT(val)               bfin_write32(TCOUNT,val)
-
-/*Debug/MP/Emulation Registers*/
-#define bfin_read_DSPID()                    bfin_read32(DSPID)
-#define bfin_write_DSPID(val)                bfin_write32(DSPID,val)
-#define bfin_read_DBGCTL()                   bfin_read32(DBGCTL)
-#define bfin_write_DBGCTL(val)               bfin_write32(DBGCTL,val)
-#define bfin_read_DBGSTAT()                  bfin_read32(DBGSTAT)
-#define bfin_write_DBGSTAT(val)              bfin_write32(DBGSTAT,val)
-#define bfin_read_EMUDAT()                   bfin_read32(EMUDAT)
-#define bfin_write_EMUDAT(val)               bfin_write32(EMUDAT,val)
-
-/*Trace Buffer Registers*/
-#define bfin_read_TBUFCTL()                  bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)              bfin_write32(TBUFCTL,val)
-#define bfin_read_TBUFSTAT()                 bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)             bfin_write32(TBUFSTAT,val)
-#define bfin_read_TBUF()                     bfin_read32(TBUF)
-#define bfin_write_TBUF(val)                 bfin_write32(TBUF,val)
-
-/*Watch Point Control Registers*/
-#define bfin_read_WPIACTL()                  bfin_read32(WPIACTL)
-#define bfin_write_WPIACTL(val)              bfin_write32(WPIACTL,val)
-#define bfin_read_WPIA0()                    bfin_read32(WPIA0)
-#define bfin_write_WPIA0(val)                bfin_write32(WPIA0,val)
-#define bfin_read_WPIA1()                    bfin_read32(WPIA1)
-#define bfin_write_WPIA1(val)                bfin_write32(WPIA1,val)
-#define bfin_read_WPIA2()                    bfin_read32(WPIA2)
-#define bfin_write_WPIA2(val)                bfin_write32(WPIA2,val)
-#define bfin_read_WPIA3()                    bfin_read32(WPIA3)
-#define bfin_write_WPIA3(val)                bfin_write32(WPIA3,val)
-#define bfin_read_WPIA4()                    bfin_read32(WPIA4)
-#define bfin_write_WPIA4(val)                bfin_write32(WPIA4,val)
-#define bfin_read_WPIA5()                    bfin_read32(WPIA5)
-#define bfin_write_WPIA5(val)                bfin_write32(WPIA5,val)
-#define bfin_read_WPIACNT0()                 bfin_read32(WPIACNT0)
-#define bfin_write_WPIACNT0(val)             bfin_write32(WPIACNT0,val)
-#define bfin_read_WPIACNT1()                 bfin_read32(WPIACNT1)
-#define bfin_write_WPIACNT1(val)             bfin_write32(WPIACNT1,val)
-#define bfin_read_WPIACNT2()                 bfin_read32(WPIACNT2)
-#define bfin_write_WPIACNT2(val)             bfin_write32(WPIACNT2,val)
-#define bfin_read_WPIACNT3()                 bfin_read32(WPIACNT3)
-#define bfin_write_WPIACNT3(val)             bfin_write32(WPIACNT3,val)
-#define bfin_read_WPIACNT4()                 bfin_read32(WPIACNT4)
-#define bfin_write_WPIACNT4(val)             bfin_write32(WPIACNT4,val)
-#define bfin_read_WPIACNT5()                 bfin_read32(WPIACNT5)
-#define bfin_write_WPIACNT5(val)             bfin_write32(WPIACNT5,val)
-#define bfin_read_WPDACTL()                  bfin_read32(WPDACTL)
-#define bfin_write_WPDACTL(val)              bfin_write32(WPDACTL,val)
-#define bfin_read_WPDA0()                    bfin_read32(WPDA0)
-#define bfin_write_WPDA0(val)                bfin_write32(WPDA0,val)
-#define bfin_read_WPDA1()                    bfin_read32(WPDA1)
-#define bfin_write_WPDA1(val)                bfin_write32(WPDA1,val)
-#define bfin_read_WPDACNT0()                 bfin_read32(WPDACNT0)
-#define bfin_write_WPDACNT0(val)             bfin_write32(WPDACNT0,val)
-#define bfin_read_WPDACNT1()                 bfin_read32(WPDACNT1)
-#define bfin_write_WPDACNT1(val)             bfin_write32(WPDACNT1,val)
-#define bfin_read_WPSTAT()                   bfin_read32(WPSTAT)
-#define bfin_write_WPSTAT(val)               bfin_write32(WPSTAT,val)
-
-/*Performance Monitor Registers*/
-#define bfin_read_PFCTL()                    bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)                bfin_write32(PFCTL,val)
-#define bfin_read_PFCNTR0()                  bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)              bfin_write32(PFCNTR0,val)
-#define bfin_read_PFCNTR1()                  bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)              bfin_write32(PFCNTR1,val)
-
-/*
-#define IPRIO                  0xFFE02110
-*/
-
-#endif                          /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mach-common/clocks.h b/include/asm-blackfin/mach-common/clocks.h
deleted file mode 100644
index 033bba92d61c..000000000000
--- a/include/asm-blackfin/mach-common/clocks.h
+++ /dev/null
@@ -1,70 +0,0 @@
-/*
- * File:         include/asm-blackfin/mach-common/clocks.h
- * Based on:     include/asm-blackfin/mach-bf537/bf537.h
- * Author:       Robin Getz <rgetz@blackfin.uclinux.org>
- *
- * Created:      25Jul07
- * Description:  Common Clock definitions for various kernel files
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef _BFIN_CLOCKS_H
-#define _BFIN_CLOCKS_H
-
-#ifdef CONFIG_CCLK_DIV_1
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
-# define CONFIG_CCLK_DIV 1
-#endif
-
-#ifdef CONFIG_CCLK_DIV_2
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
-# define CONFIG_CCLK_DIV 2
-#endif
-
-#ifdef CONFIG_CCLK_DIV_4
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
-# define CONFIG_CCLK_DIV 4
-#endif
-
-#ifdef CONFIG_CCLK_DIV_8
-# define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
-# define CONFIG_CCLK_DIV 8
-#endif
-
-#ifndef CONFIG_PLL_BYPASS
-# ifndef CONFIG_CLKIN_HALF
-#  define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-#  define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
-# endif
-
-# define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
-# define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
-
-#else
-# define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ)
-# define CONFIG_CCLK_HZ  (CONFIG_CLKIN_HZ)
-# define CONFIG_SCLK_HZ  (CONFIG_CLKIN_HZ)
-# define CONFIG_VCO_MULT 0
-#endif
-
-#endif
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
deleted file mode 100644
index c0e630edfb9a..000000000000
--- a/include/asm-blackfin/mach-common/context.S
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * File:         arch/blackfin/kernel/context.S
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2007 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-/*
- * NOTE!  The single-stepping code assumes that all interrupt handlers
- * start by saving SYSCFG on the stack with their first instruction.
- */
-
-/*
- * Code to save processor context.
- *  We even save the register which are preserved by a function call
- *       - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
-        [--sp] = SYSCFG;
-
-        [--sp] = P0;    /*orig_p0*/
-        [--sp] = R0;    /*orig_r0*/
-
-        [--sp] = ( R7:0, P5:0 );
-        [--sp] = fp;
-        [--sp] = usp;
-
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-
-        [--sp] = ASTAT;
-
-        [--sp] = r0;    /* Skip reserved */
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
-        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
-        [--sp] = SEQSTAT;
-        [--sp] = r0;    /* Skip IPEND as well. */
-        /* Switch to other method of keeping interrupts disabled.  */
-#ifdef CONFIG_DEBUG_HWERR
-        r0 = 0x3f;
-        sti r0;
-#else
-        cli r0;
-#endif
-        [--sp] = RETI;  /*orig_pc*/
-        /* Clear all L registers.  */
-        r0 = 0 (x);
-        l0 = r0;
-        l1 = r0;
-        l2 = r0;
-        l3 = r0;
-.endm
-
-.macro save_context_syscall
-        [--sp] = SYSCFG;
-
-        [--sp] = P0;    /*orig_p0*/
-        [--sp] = R0;    /*orig_r0*/
-        [--sp] = ( R7:0, P5:0 );
-        [--sp] = fp;
-        [--sp] = usp;
-
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-
-        [--sp] = ASTAT;
-
-        [--sp] = r0;    /* Skip reserved */
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
-        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
-        [--sp] = SEQSTAT;
-        [--sp] = r0;    /* Skip IPEND as well. */
-        [--sp] = RETI;  /*orig_pc*/
-        /* Clear all L registers.  */
-        r0 = 0 (x);
-        l0 = r0;
-        l1 = r0;
-        l2 = r0;
-        l3 = r0;
-.endm
-
-.macro save_context_no_interrupts
-        [--sp] = SYSCFG;
-        [--sp] = P0;    /* orig_p0 */
-        [--sp] = R0;    /* orig_r0 */
-        [--sp] = ( R7:0, P5:0 );
-        [--sp] = fp;
-        [--sp] = usp;
-
-        [--sp] = i0;
-        [--sp] = i1;
-        [--sp] = i2;
-        [--sp] = i3;
-
-        [--sp] = m0;
-        [--sp] = m1;
-        [--sp] = m2;
-        [--sp] = m3;
-
-        [--sp] = l0;
-        [--sp] = l1;
-        [--sp] = l2;
-        [--sp] = l3;
-
-        [--sp] = b0;
-        [--sp] = b1;
-        [--sp] = b2;
-        [--sp] = b3;
-        [--sp] = a0.x;
-        [--sp] = a0.w;
-        [--sp] = a1.x;
-        [--sp] = a1.w;
-
-        [--sp] = LC0;
-        [--sp] = LC1;
-        [--sp] = LT0;
-        [--sp] = LT1;
-        [--sp] = LB0;
-        [--sp] = LB1;
-
-        [--sp] = ASTAT;
-
-#ifdef CONFIG_KGDB
-        fp     = 0(Z);
-        r1     = sp;
-        r1    += 60;
-        r1    += 60;
-        r1    += 60;
-        [--sp] = r1;
-#else
-        [--sp] = r0;    /* Skip reserved */
-#endif
-        [--sp] = RETS;
-        r0 = RETI;
-        [--sp] = r0;
-        [--sp] = RETX;
-        [--sp] = RETN;
-        [--sp] = RETE;
-        [--sp] = SEQSTAT;
-#ifdef CONFIG_KGDB
-        r1.l = lo(IPEND);
-        r1.h = hi(IPEND);
-        [--sp] = r1;
-#else
-        [--sp] = r0;    /* Skip IPEND as well. */
-#endif
-        [--sp] = r0;  /*orig_pc*/
-        /* Clear all L registers.  */
-        r0 = 0 (x);
-        l0 = r0;
-        l1 = r0;
-        l2 = r0;
-        l3 = r0;
-.endm
-
-.macro restore_context_no_interrupts
-        sp += 4;        /* Skip orig_pc */
-        sp += 4;        /* Skip IPEND */
-        SEQSTAT = [sp++];
-        RETE = [sp++];
-        RETN = [sp++];
-        RETX = [sp++];
-        r0 = [sp++];
-        RETI = r0;      /* Restore RETI indirectly when in exception */
-        RETS = [sp++];
-
-        sp += 4;        /* Skip Reserved */
-
-        ASTAT = [sp++];
-
-        LB1 = [sp++];
-        LB0 = [sp++];
-        LT1 = [sp++];
-        LT0 = [sp++];
-        LC1 = [sp++];
-        LC0 = [sp++];
-
-        a1.w = [sp++];
-        a1.x = [sp++];
-        a0.w = [sp++];
-        a0.x = [sp++];
-        b3 = [sp++];
-        b2 = [sp++];
-        b1 = [sp++];
-        b0 = [sp++];
-
-        l3 = [sp++];
-        l2 = [sp++];
-        l1 = [sp++];
-        l0 = [sp++];
-
-        m3 = [sp++];
-        m2 = [sp++];
-        m1 = [sp++];
-        m0 = [sp++];
-
-        i3 = [sp++];
-        i2 = [sp++];
-        i1 = [sp++];
-        i0 = [sp++];
-
-        sp += 4;
-        fp = [sp++];
-
-        ( R7 : 0, P5 : 0) = [ SP ++ ];
-        sp += 8;        /* Skip orig_r0/orig_p0 */
-        SYSCFG = [sp++];
-.endm
-
-.macro restore_context_with_interrupts
-        sp += 4;        /* Skip orig_pc */
-        sp += 4;        /* Skip IPEND */
-        SEQSTAT = [sp++];
-        RETE = [sp++];
-        RETN = [sp++];
-        RETX = [sp++];
-        RETI = [sp++];
-        RETS = [sp++];
-
-        p0.h = _irq_flags;
-        p0.l = _irq_flags;
-        r0 = [p0];
-        sti r0;
-
-        sp += 4;        /* Skip Reserved */
-
-        ASTAT = [sp++];
-
-        LB1 = [sp++];
-        LB0 = [sp++];
-        LT1 = [sp++];
-        LT0 = [sp++];
-        LC1 = [sp++];
-        LC0 = [sp++];
-
-        a1.w = [sp++];
-        a1.x = [sp++];
-        a0.w = [sp++];
-        a0.x = [sp++];
-        b3 = [sp++];
-        b2 = [sp++];
-        b1 = [sp++];
-        b0 = [sp++];
-
-        l3 = [sp++];
-        l2 = [sp++];
-        l1 = [sp++];
-        l0 = [sp++];
-
-        m3 = [sp++];
-        m2 = [sp++];
-        m1 = [sp++];
-        m0 = [sp++];
-
-        i3 = [sp++];
-        i2 = [sp++];
-        i1 = [sp++];
-        i0 = [sp++];
-
-        sp += 4;
-        fp = [sp++];
-
-        ( R7 : 0, P5 : 0) = [ SP ++ ];
-        sp += 8;        /* Skip orig_r0/orig_p0 */
-        csync;
-        SYSCFG = [sp++];
-        csync;
-.endm
-
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
deleted file mode 100644
index e8967f6124f7..000000000000
--- a/include/asm-blackfin/mach-common/def_LPBlackfin.h
+++ /dev/null
@@ -1,712 +0,0 @@
- /*
-  * File:        include/asm-blackfin/mach-common/def_LPBlackfin.h
-  * Based on:
-  * Author:      unknown
-  *              COPYRIGHT 2005 Analog Devices
-  * Created:     ?
-  * Description:
-  *
-  * Modified:
-  *
-  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
-  *
-  * This program is free software; you can redistribute it and/or modify
-  * it under the terms of the GNU General Public License as published by
-  * the Free Software Foundation; either version 2, or (at your option)
-  * any later version.
-  *
-  * This program is distributed in the hope that it will be useful,
-  * but WITHOUT ANY WARRANTY; without even the implied warranty of
-  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-  * GNU General Public License for more details.
-  *
-  * You should have received a copy of the GNU General Public License
-  * along with this program; see the file COPYING.
-  * If not, write to the Free Software Foundation,
-  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
-  */
-
-/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
-
-#ifndef _DEF_LPBLACKFIN_H
-#define _DEF_LPBLACKFIN_H
-
-#include <asm/mach/anomaly.h>
-
-#define MK_BMSK_(x) (1<<x)
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define bfin_read8(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = b[%1] (z);" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_read16(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = w[%1] (z);" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_read32(addr) ({ \
-        uint32_t __v; \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "%0 = [%1];" \
-                : "=d" (__v) \
-                : "a" (addr) \
-        ); \
-        __v; })
-
-#define bfin_write8(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "b[%0] = %1;" \
-                : \
-                : "a" (addr), "d" ((uint8_t)(val)) \
-                : "memory" \
-        )
-
-#define bfin_write16(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "w[%0] = %1;" \
-                : \
-                : "a" (addr), "d" ((uint16_t)(val)) \
-                : "memory" \
-        )
-
-#define bfin_write32(addr, val) \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000198 \
-                "[%0] = %1;" \
-                : \
-                : "a" (addr), "d" (val) \
-                : "memory" \
-        )
-
-#endif /* __ASSEMBLY__ */
-
-/**************************************************
- * System Register Bits
- **************************************************/
-
-/**************************************************
- * ASTAT register
- **************************************************/
-
-/* definitions of ASTAT bit positions*/
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ_P         0x00000000
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN_P         0x00000001
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC_P         0x00000005
-/*Quotient Bit*/
-#define ASTAT_AQ_P         0x00000006
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD_P    0x00000008
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_P        0x0000000C
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY_P   0x00000002
-/*Result of last ALU1 operation generated a carry*/
-#define ASTAT_AC1_P        0x0000000D
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0_P        0x00000010
-/*Sticky version of ASTAT_AV0 */
-#define ASTAT_AV0S_P       0x00000011
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1_P        0x00000012
-/*Sticky version of ASTAT_AV1 */
-#define ASTAT_AV1S_P       0x00000013
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_P          0x00000018
-/*Result of last ALU0 or MAC0 operation overflowed*/
-#define ASTAT_V_COPY_P     0x00000003
-/*Sticky version of ASTAT_V*/
-#define ASTAT_VS_P         0x00000019
-
-/* Masks */
-
-/*Result of last ALU0 or shifter operation is zero*/
-#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)
-/*Result of last ALU0 or shifter operation is negative*/
-#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)
-/*Result of last ALU0 operation generated a carry*/
-#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)
-/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
-#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)
-/*Result of last MAC1 operation overflowed, sticky for MAC*/
-#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)
-/*Condition Code, used for holding comparison results*/
-#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)
-/*Quotient Bit*/
-#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)
-/*Rounding mode, set for biased, clear for unbiased*/
-#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)
-/*Overflow Bit*/
-#define ASTAT_V            MK_BMSK_(ASTAT_V_P)
-/*Overflow Bit*/
-#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)
-
-/**************************************************
- *   SEQSTAT register
- **************************************************/
-
-/* Bit Positions  */
-#define SEQSTAT_EXCAUSE0_P      0x00000000      /* Last exception cause bit 0 */
-#define SEQSTAT_EXCAUSE1_P      0x00000001      /* Last exception cause bit 1 */
-#define SEQSTAT_EXCAUSE2_P      0x00000002      /* Last exception cause bit 2 */
-#define SEQSTAT_EXCAUSE3_P      0x00000003      /* Last exception cause bit 3 */
-#define SEQSTAT_EXCAUSE4_P      0x00000004      /* Last exception cause bit 4 */
-#define SEQSTAT_EXCAUSE5_P      0x00000005      /* Last exception cause bit 5 */
-#define SEQSTAT_IDLE_REQ_P      0x0000000C      /* Pending idle mode request,
-                                                 * set by IDLE instruction.
-                                                 */
-#define SEQSTAT_SFTRESET_P      0x0000000D      /* Indicates whether the last
-                                                 * reset was a software reset
-                                                 * (=1)
-                                                 */
-#define SEQSTAT_HWERRCAUSE0_P   0x0000000E      /* Last hw error cause bit 0 */
-#define SEQSTAT_HWERRCAUSE1_P   0x0000000F      /* Last hw error cause bit 1 */
-#define SEQSTAT_HWERRCAUSE2_P   0x00000010      /* Last hw error cause bit 2 */
-#define SEQSTAT_HWERRCAUSE3_P   0x00000011      /* Last hw error cause bit 3 */
-#define SEQSTAT_HWERRCAUSE4_P   0x00000012      /* Last hw error cause bit 4 */
-/* Masks */
-/* Exception cause */
-#define SEQSTAT_EXCAUSE        (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
-                                MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
-                                0)
-
-/* Indicates whether the last reset was a software reset (=1) */
-#define SEQSTAT_SFTRESET       (MK_BMSK_(SEQSTAT_SFTRESET_P))
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE     (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
-                                MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
-                                0)
-
-/* Translate bits to something useful */
-
-/* Last hw error cause */
-#define SEQSTAT_HWERRCAUSE_SHIFT         (14)
-#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR    (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR   (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_PERF_FLOW     (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
-#define SEQSTAT_HWERRCAUSE_RAISE_5       (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
-
-/**************************************************
- *   SYSCFG register
- **************************************************/
-
-/* Bit Positions */
-#define SYSCFG_SSSTEP_P     0x00000000  /* Supervisor single step, when
-                                         * set it forces an exception
-                                         * for each instruction executed
-                                         */
-#define SYSCFG_CCEN_P       0x00000001  /* Enable cycle counter (=1) */
-#define SYSCFG_SNEN_P       0x00000002  /* Self nesting Interrupt Enable */
-
-/* Masks */
-
-/* Supervisor single step, when set it forces an exception for each
- *instruction executed
- */
-#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )
-/* Enable cycle counter (=1) */
-#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )
-/* Self Nesting Interrupt Enable */
-#define SYSCFG_SNEN            MK_BMSK_(SYSCFG_SNEN_P)
-/* Backward-compatibility for typos in prior releases */
-#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
-#define SYSCFG_CCCEN           SYSCFG_CCEN
-
-/****************************************************
- * Core MMR Register Map
- ****************************************************/
-
-/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
-
-#define SRAM_BASE_ADDRESS  0xFFE00000   /* SRAM Base Address Register */
-#define DMEM_CONTROL       0xFFE00004   /* Data memory control */
-#define DCPLB_STATUS       0xFFE00008   /* Data Cache Programmable Look-Aside
-                                         * Buffer Status
-                                         */
-#define DCPLB_FAULT_STATUS 0xFFE00008   /* "" (older define) */
-#define DCPLB_FAULT_ADDR   0xFFE0000C   /* Data Cache Programmable Look-Aside
-                                         * Buffer Fault Address
-                                         */
-#define DCPLB_ADDR0        0xFFE00100   /* Data Cache Protection Lookaside
-                                         * Buffer 0
-                                         */
-#define DCPLB_ADDR1        0xFFE00104   /* Data Cache Protection Lookaside
-                                         * Buffer 1
-                                         */
-#define DCPLB_ADDR2        0xFFE00108   /* Data Cache Protection Lookaside
-                                         * Buffer 2
-                                         */
-#define DCPLB_ADDR3        0xFFE0010C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 3
-                                         */
-#define DCPLB_ADDR4        0xFFE00110   /* Data Cacheability Protection
-                                         * Lookaside Buffer 4
-                                         */
-#define DCPLB_ADDR5        0xFFE00114   /* Data Cacheability Protection
-                                         * Lookaside Buffer 5
-                                         */
-#define DCPLB_ADDR6        0xFFE00118   /* Data Cacheability Protection
-                                         * Lookaside Buffer 6
-                                         */
-#define DCPLB_ADDR7        0xFFE0011C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 7
-                                         */
-#define DCPLB_ADDR8        0xFFE00120   /* Data Cacheability Protection
-                                         * Lookaside Buffer 8
-                                         */
-#define DCPLB_ADDR9        0xFFE00124   /* Data Cacheability Protection
-                                         * Lookaside Buffer 9
-                                         */
-#define DCPLB_ADDR10       0xFFE00128   /* Data Cacheability Protection
-                                         * Lookaside Buffer 10
-                                         */
-#define DCPLB_ADDR11       0xFFE0012C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 11
-                                         */
-#define DCPLB_ADDR12       0xFFE00130   /* Data Cacheability Protection
-                                         * Lookaside Buffer 12
-                                         */
-#define DCPLB_ADDR13       0xFFE00134   /* Data Cacheability Protection
-                                         * Lookaside Buffer 13
-                                         */
-#define DCPLB_ADDR14       0xFFE00138   /* Data Cacheability Protection
-                                         * Lookaside Buffer 14
-                                         */
-#define DCPLB_ADDR15       0xFFE0013C   /* Data Cacheability Protection
-                                         * Lookaside Buffer 15
-                                         */
-#define DCPLB_DATA0        0xFFE00200   /* Data Cache 0 Status */
-#define DCPLB_DATA1        0xFFE00204   /* Data Cache 1 Status */
-#define DCPLB_DATA2        0xFFE00208   /* Data Cache 2 Status */
-#define DCPLB_DATA3        0xFFE0020C   /* Data Cache 3 Status */
-#define DCPLB_DATA4        0xFFE00210   /* Data Cache 4 Status */
-#define DCPLB_DATA5        0xFFE00214   /* Data Cache 5 Status */
-#define DCPLB_DATA6        0xFFE00218   /* Data Cache 6 Status */
-#define DCPLB_DATA7        0xFFE0021C   /* Data Cache 7 Status */
-#define DCPLB_DATA8        0xFFE00220   /* Data Cache 8 Status */
-#define DCPLB_DATA9        0xFFE00224   /* Data Cache 9 Status */
-#define DCPLB_DATA10       0xFFE00228   /* Data Cache 10 Status */
-#define DCPLB_DATA11       0xFFE0022C   /* Data Cache 11 Status */
-#define DCPLB_DATA12       0xFFE00230   /* Data Cache 12 Status */
-#define DCPLB_DATA13       0xFFE00234   /* Data Cache 13 Status */
-#define DCPLB_DATA14       0xFFE00238   /* Data Cache 14 Status */
-#define DCPLB_DATA15       0xFFE0023C   /* Data Cache 15 Status */
-#define DCPLB_DATA16       0xFFE00240   /* Extra Dummy entry */
-
-#define DTEST_COMMAND      0xFFE00300   /* Data Test Command Register */
-#define DTEST_DATA0        0xFFE00400   /* Data Test Data Register */
-#define DTEST_DATA1        0xFFE00404   /* Data Test Data Register */
-
-/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
-
-#define IMEM_CONTROL       0xFFE01004   /* Instruction Memory Control */
-#define ICPLB_STATUS       0xFFE01008   /* Instruction Cache miss status */
-#define CODE_FAULT_STATUS  0xFFE01008   /* "" (older define) */
-#define ICPLB_FAULT_ADDR   0xFFE0100C   /* Instruction Cache miss address */
-#define CODE_FAULT_ADDR    0xFFE0100C   /* "" (older define) */
-#define ICPLB_ADDR0        0xFFE01100   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 0
-                                         */
-#define ICPLB_ADDR1        0xFFE01104   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 1
-                                         */
-#define ICPLB_ADDR2        0xFFE01108   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 2
-                                         */
-#define ICPLB_ADDR3        0xFFE0110C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 3
-                                         */
-#define ICPLB_ADDR4        0xFFE01110   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 4
-                                         */
-#define ICPLB_ADDR5        0xFFE01114   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 5
-                                         */
-#define ICPLB_ADDR6        0xFFE01118   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 6
-                                         */
-#define ICPLB_ADDR7        0xFFE0111C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 7
-                                         */
-#define ICPLB_ADDR8        0xFFE01120   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 8
-                                         */
-#define ICPLB_ADDR9        0xFFE01124   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 9
-                                         */
-#define ICPLB_ADDR10       0xFFE01128   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 10
-                                         */
-#define ICPLB_ADDR11       0xFFE0112C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 11
-                                         */
-#define ICPLB_ADDR12       0xFFE01130   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 12
-                                         */
-#define ICPLB_ADDR13       0xFFE01134   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 13
-                                         */
-#define ICPLB_ADDR14       0xFFE01138   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 14
-                                         */
-#define ICPLB_ADDR15       0xFFE0113C   /* Instruction Cacheability
-                                         * Protection Lookaside Buffer 15
-                                         */
-#define ICPLB_DATA0        0xFFE01200   /* Instruction Cache 0 Status */
-#define ICPLB_DATA1        0xFFE01204   /* Instruction Cache 1 Status */
-#define ICPLB_DATA2        0xFFE01208   /* Instruction Cache 2 Status */
-#define ICPLB_DATA3        0xFFE0120C   /* Instruction Cache 3 Status */
-#define ICPLB_DATA4        0xFFE01210   /* Instruction Cache 4 Status */
-#define ICPLB_DATA5        0xFFE01214   /* Instruction Cache 5 Status */
-#define ICPLB_DATA6        0xFFE01218   /* Instruction Cache 6 Status */
-#define ICPLB_DATA7        0xFFE0121C   /* Instruction Cache 7 Status */
-#define ICPLB_DATA8        0xFFE01220   /* Instruction Cache 8 Status */
-#define ICPLB_DATA9        0xFFE01224   /* Instruction Cache 9 Status */
-#define ICPLB_DATA10       0xFFE01228   /* Instruction Cache 10 Status */
-#define ICPLB_DATA11       0xFFE0122C   /* Instruction Cache 11 Status */
-#define ICPLB_DATA12       0xFFE01230   /* Instruction Cache 12 Status */
-#define ICPLB_DATA13       0xFFE01234   /* Instruction Cache 13 Status */
-#define ICPLB_DATA14       0xFFE01238   /* Instruction Cache 14 Status */
-#define ICPLB_DATA15       0xFFE0123C   /* Instruction Cache 15 Status */
-#define ITEST_COMMAND      0xFFE01300   /* Instruction Test Command Register */
-#define ITEST_DATA0        0xFFE01400   /* Instruction Test Data Register */
-#define ITEST_DATA1        0xFFE01404   /* Instruction Test Data Register */
-
-/* Event/Interrupt Controller Registers   (0xFFE02000 - 0xFFE02110) */
-
-#define EVT0               0xFFE02000   /* Event Vector 0 ESR Address */
-#define EVT1               0xFFE02004   /* Event Vector 1 ESR Address */
-#define EVT2               0xFFE02008   /* Event Vector 2 ESR Address */
-#define EVT3               0xFFE0200C   /* Event Vector 3 ESR Address */
-#define EVT4               0xFFE02010   /* Event Vector 4 ESR Address */
-#define EVT5               0xFFE02014   /* Event Vector 5 ESR Address */
-#define EVT6               0xFFE02018   /* Event Vector 6 ESR Address */
-#define EVT7               0xFFE0201C   /* Event Vector 7 ESR Address */
-#define EVT8               0xFFE02020   /* Event Vector 8 ESR Address */
-#define EVT9               0xFFE02024   /* Event Vector 9 ESR Address */
-#define EVT10              0xFFE02028   /* Event Vector 10 ESR Address */
-#define EVT11              0xFFE0202C   /* Event Vector 11 ESR Address */
-#define EVT12              0xFFE02030   /* Event Vector 12 ESR Address */
-#define EVT13              0xFFE02034   /* Event Vector 13 ESR Address */
-#define EVT14              0xFFE02038   /* Event Vector 14 ESR Address */
-#define EVT15              0xFFE0203C   /* Event Vector 15 ESR Address */
-#define IMASK              0xFFE02104   /* Interrupt Mask Register */
-#define IPEND              0xFFE02108   /* Interrupt Pending Register */
-#define ILAT               0xFFE0210C   /* Interrupt Latch Register */
-#define IPRIO              0xFFE02110   /* Core Interrupt Priority Register */
-
-/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
-
-#define TCNTL              0xFFE03000   /* Core Timer Control Register */
-#define TPERIOD            0xFFE03004   /* Core Timer Period Register */
-#define TSCALE             0xFFE03008   /* Core Timer Scale Register */
-#define TCOUNT             0xFFE0300C   /* Core Timer Count Register */
-
-/* Debug/MP/Emulation Registers     (0xFFE05000 - 0xFFE05008) */
-#define DSPID              0xFFE05000   /* DSP Processor ID Register for
-                                         * MP implementations
-                                         */
-
-#define DBGSTAT            0xFFE05008   /* Debug Status Register */
-
-/* Trace Buffer Registers     (0xFFE06000 - 0xFFE06100) */
-
-#define TBUFCTL            0xFFE06000   /* Trace Buffer Control Register */
-#define TBUFSTAT           0xFFE06004   /* Trace Buffer Status Register */
-#define TBUF               0xFFE06100   /* Trace Buffer */
-
-/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
-
-/* Watchpoint Instruction Address Control Register */
-#define WPIACTL            0xFFE07000
-/* Watchpoint Instruction Address Register 0 */
-#define WPIA0              0xFFE07040
-/* Watchpoint Instruction Address Register 1 */
-#define WPIA1              0xFFE07044
-/* Watchpoint Instruction Address Register 2 */
-#define WPIA2              0xFFE07048
-/* Watchpoint Instruction Address Register 3 */
-#define WPIA3              0xFFE0704C
-/* Watchpoint Instruction Address Register 4 */
-#define WPIA4              0xFFE07050
-/* Watchpoint Instruction Address Register 5 */
-#define WPIA5              0xFFE07054
-/* Watchpoint Instruction Address Count Register 0 */
-#define WPIACNT0           0xFFE07080
-/* Watchpoint Instruction Address Count Register 1 */
-#define WPIACNT1           0xFFE07084
-/* Watchpoint Instruction Address Count Register 2 */
-#define WPIACNT2           0xFFE07088
-/* Watchpoint Instruction Address Count Register 3 */
-#define WPIACNT3           0xFFE0708C
-/* Watchpoint Instruction Address Count Register 4 */
-#define WPIACNT4           0xFFE07090
-/* Watchpoint Instruction Address Count Register 5 */
-#define WPIACNT5           0xFFE07094
-/* Watchpoint Data Address Control Register */
-#define WPDACTL            0xFFE07100
-/* Watchpoint Data Address Register 0 */
-#define WPDA0              0xFFE07140
-/* Watchpoint Data Address Register 1 */
-#define WPDA1              0xFFE07144
-/* Watchpoint Data Address Count Value Register 0 */
-#define WPDACNT0           0xFFE07180
-/* Watchpoint Data Address Count Value Register 1 */
-#define WPDACNT1           0xFFE07184
-/* Watchpoint Status Register */
-#define WPSTAT             0xFFE07200
-
-/* Performance Monitor Registers    (0xFFE08000 - 0xFFE08104) */
-
-/* Performance Monitor Control Register */
-#define PFCTL              0xFFE08000
-/* Performance Monitor Counter Register 0 */
-#define PFCNTR0            0xFFE08100
-/* Performance Monitor Counter Register 1 */
-#define PFCNTR1            0xFFE08104
-
-/****************************************************
- * Core MMR Register Bits
- ****************************************************/
-
-/**************************************************
- * EVT registers (ILAT, IMASK, and IPEND).
- **************************************************/
-
-/* Bit Positions */
-#define EVT_EMU_P        0x00000000     /* Emulator interrupt bit position */
-#define EVT_RST_P        0x00000001     /* Reset interrupt bit position */
-#define EVT_NMI_P        0x00000002     /* Non Maskable interrupt bit position */
-#define EVT_EVX_P        0x00000003     /* Exception bit position */
-#define EVT_IRPTEN_P     0x00000004     /* Global interrupt enable bit position */
-#define EVT_IVHW_P       0x00000005     /* Hardware Error interrupt bit position */
-#define EVT_IVTMR_P      0x00000006     /* Timer interrupt bit position */
-#define EVT_IVG7_P       0x00000007     /* IVG7 interrupt bit position */
-#define EVT_IVG8_P       0x00000008     /* IVG8 interrupt bit position */
-#define EVT_IVG9_P       0x00000009     /* IVG9 interrupt bit position */
-#define EVT_IVG10_P      0x0000000a     /* IVG10 interrupt bit position */
-#define EVT_IVG11_P      0x0000000b     /* IVG11 interrupt bit position */
-#define EVT_IVG12_P      0x0000000c     /* IVG12 interrupt bit position */
-#define EVT_IVG13_P      0x0000000d     /* IVG13 interrupt bit position */
-#define EVT_IVG14_P      0x0000000e     /* IVG14 interrupt bit position */
-#define EVT_IVG15_P      0x0000000f     /* IVG15 interrupt bit position */
-
-/* Masks */
-#define EVT_EMU       MK_BMSK_(EVT_EMU_P   )    /* Emulator interrupt mask */
-#define EVT_RST       MK_BMSK_(EVT_RST_P   )    /* Reset interrupt mask */
-#define EVT_NMI       MK_BMSK_(EVT_NMI_P   )    /* Non Maskable interrupt mask */
-#define EVT_EVX       MK_BMSK_(EVT_EVX_P   )    /* Exception mask */
-#define EVT_IRPTEN    MK_BMSK_(EVT_IRPTEN_P)    /* Global interrupt enable mask */
-#define EVT_IVHW      MK_BMSK_(EVT_IVHW_P  )    /* Hardware Error interrupt mask */
-#define EVT_IVTMR     MK_BMSK_(EVT_IVTMR_P )    /* Timer interrupt mask */
-#define EVT_IVG7      MK_BMSK_(EVT_IVG7_P  )    /* IVG7 interrupt mask */
-#define EVT_IVG8      MK_BMSK_(EVT_IVG8_P  )    /* IVG8 interrupt mask */
-#define EVT_IVG9      MK_BMSK_(EVT_IVG9_P  )    /* IVG9 interrupt mask */
-#define EVT_IVG10     MK_BMSK_(EVT_IVG10_P )    /* IVG10 interrupt mask */
-#define EVT_IVG11     MK_BMSK_(EVT_IVG11_P )    /* IVG11 interrupt mask */
-#define EVT_IVG12     MK_BMSK_(EVT_IVG12_P )    /* IVG12 interrupt mask */
-#define EVT_IVG13     MK_BMSK_(EVT_IVG13_P )    /* IVG13 interrupt mask */
-#define EVT_IVG14     MK_BMSK_(EVT_IVG14_P )    /* IVG14 interrupt mask */
-#define EVT_IVG15     MK_BMSK_(EVT_IVG15_P )    /* IVG15 interrupt mask */
-
-/**************************************************
- *  DMEM_CONTROL Register
- **************************************************/
-/* Bit Positions */
-#define ENDM_P                  0x00    /* (doesn't really exist) Enable
-                                         *Data Memory L1
-                                         */
-#define DMCTL_ENDM_P            ENDM_P  /* "" (older define) */
-
-#define ENDCPLB_P               0x01    /* Enable DCPLBS */
-#define DMCTL_ENDCPLB_P         ENDCPLB_P       /* "" (older define) */
-#define DMC0_P                  0x02    /* L1 Data Memory Configure bit 0 */
-#define DMCTL_DMC0_P            DMC0_P  /* "" (older define) */
-#define DMC1_P                  0x03    /* L1 Data Memory Configure bit 1 */
-#define DMCTL_DMC1_P            DMC1_P  /* "" (older define) */
-#define DCBS_P                  0x04    /* L1 Data Cache Bank Select */
-#define PORT_PREF0_P            0x12    /* DAG0 Port Preference */
-#define PORT_PREF1_P            0x13    /* DAG1 Port Preference */
-
-/* Masks */
-#define ENDM               0x00000001   /* (doesn't really exist) Enable
-                                         * Data Memory L1
-                                         */
-#define ENDCPLB            0x00000002   /* Enable DCPLB */
-#define ASRAM_BSRAM        0x00000000
-#define ACACHE_BSRAM       0x00000008
-#define ACACHE_BCACHE      0x0000000C
-#define DCBS               0x00000010   /*  L1 Data Cache Bank Select */
-#define PORT_PREF0         0x00001000   /* DAG0 Port Preference */
-#define PORT_PREF1         0x00002000   /* DAG1 Port Preference */
-
-/* IMEM_CONTROL Register */
-/* Bit Positions */
-#define ENIM_P                  0x00    /* Enable L1 Code Memory  */
-#define IMCTL_ENIM_P            0x00    /* "" (older define) */
-#define ENICPLB_P               0x01    /* Enable ICPLB */
-#define IMCTL_ENICPLB_P         0x01    /* "" (older define) */
-#define IMC_P                   0x02    /* Enable  */
-#define IMCTL_IMC_P             0x02    /* Configure L1 code memory as
-                                         * cache (0=SRAM)
-                                         */
-#define ILOC0_P                 0x03    /* Lock Way 0 */
-#define ILOC1_P                 0x04    /* Lock Way 1 */
-#define ILOC2_P                 0x05    /* Lock Way 2 */
-#define ILOC3_P                 0x06    /* Lock Way 3 */
-#define LRUPRIORST_P            0x0D    /* Least Recently Used Replacement
-                                         * Priority
-                                         */
-/* Masks */
-#define ENIM               0x00000001   /* Enable L1 Code Memory */
-#define ENICPLB            0x00000002   /* Enable ICPLB */
-#define IMC                0x00000004   /* Configure L1 code memory as
-                                         * cache (0=SRAM)
-                                         */
-#define ILOC0              0x00000008   /* Lock Way 0 */
-#define ILOC1              0x00000010   /* Lock Way 1 */
-#define ILOC2              0x00000020   /* Lock Way 2 */
-#define ILOC3              0x00000040   /* Lock Way 3 */
-#define LRUPRIORST         0x00002000   /* Least Recently Used Replacement
-                                         * Priority
-                                         */
-
-/* TCNTL Masks */
-#define TMPWR              0x00000001   /* Timer Low Power Control,
-                                         * 0=low power mode, 1=active state
-                                         */
-#define TMREN              0x00000002   /* Timer enable, 0=disable, 1=enable */
-#define TAUTORLD           0x00000004   /* Timer auto reload */
-#define TINT               0x00000008   /* Timer generated interrupt 0=no
-                                         * interrupt has been generated,
-                                         * 1=interrupt has been generated
-                                         * (sticky)
-                                         */
-
-/* DCPLB_DATA and ICPLB_DATA Registers */
-/* Bit Positions */
-#define CPLB_VALID_P       0x00000000   /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK_P        0x00000001   /* 0=entry may be replaced, 1=entry
-                                         * locked
-                                         */
-#define CPLB_USER_RD_P     0x00000002   /* 0=no read access, 1=read access
-                                         * allowed (user mode)
-                                         */
-/* Masks */
-#define CPLB_VALID         0x00000001   /* 0=invalid entry, 1=valid entry */
-#define CPLB_LOCK          0x00000002   /* 0=entry may be replaced, 1=entry
-                                         * locked
-                                         */
-#define CPLB_USER_RD       0x00000004   /* 0=no read access, 1=read access
-                                         * allowed (user mode)
-                                         */
-
-#define PAGE_SIZE_1KB      0x00000000   /* 1 KB page size */
-#define PAGE_SIZE_4KB      0x00010000   /* 4 KB page size */
-#define PAGE_SIZE_1MB      0x00020000   /* 1 MB page size */
-#define PAGE_SIZE_4MB      0x00030000   /* 4 MB page size */
-#define CPLB_L1SRAM        0x00000020   /* 0=SRAM mapped in L1, 0=SRAM not
-                                         * mapped to L1
-                                         */
-#define CPLB_PORTPRIO      0x00000200   /* 0=low priority port, 1= high
-                                         * priority port
-                                         */
-#define CPLB_L1_CHBL       0x00001000   /* 0=non-cacheable in L1, 1=cacheable
-                                         * in L1
-                                         */
-/* ICPLB_DATA only */
-#define CPLB_LRUPRIO       0x00000100   /* 0=can be replaced by any line,
-                                         * 1=priority for non-replacement
-                                         */
-/* DCPLB_DATA only */
-#define CPLB_USER_WR       0x00000008   /* 0=no write access, 0=write
-                                         * access allowed (user mode)
-                                         */
-#define CPLB_SUPV_WR       0x00000010   /* 0=no write access, 0=write
-                                         * access allowed (supervisor mode)
-                                         */
-#define CPLB_DIRTY         0x00000080   /* 1=dirty, 0=clean */
-#define CPLB_L1_AOW        0x00008000   /* 0=do not allocate cache lines on
-                                         * write-through writes,
-                                         * 1= allocate cache lines on
-                                         * write-through writes.
-                                         */
-#define CPLB_WT            0x00004000   /* 0=write-back, 1=write-through */
-
-#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-/* TBUFCTL Masks */
-#define TBUFPWR            0x0001
-#define TBUFEN             0x0002
-#define TBUFOVF            0x0004
-#define TBUFCMPLP_SINGLE   0x0008
-#define TBUFCMPLP_DOUBLE   0x0010
-#define TBUFCMPLP          (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
-
-/* TBUFSTAT Masks */
-#define TBUFCNT            0x001F
-
-/* ITEST_COMMAND and DTEST_COMMAND Registers */
-/* Masks */
-#define TEST_READ          0x00000000   /* Read Access */
-#define TEST_WRITE         0x00000002   /* Write Access */
-#define TEST_TAG           0x00000000   /* Access TAG */
-#define TEST_DATA          0x00000004   /* Access DATA */
-#define TEST_DW0           0x00000000   /* Select Double Word 0 */
-#define TEST_DW1           0x00000008   /* Select Double Word 1 */
-#define TEST_DW2           0x00000010   /* Select Double Word 2 */
-#define TEST_DW3           0x00000018   /* Select Double Word 3 */
-#define TEST_MB0           0x00000000   /* Select Mini-Bank 0 */
-#define TEST_MB1           0x00010000   /* Select Mini-Bank 1 */
-#define TEST_MB2           0x00020000   /* Select Mini-Bank 2 */
-#define TEST_MB3           0x00030000   /* Select Mini-Bank 3 */
-#define TEST_SET(x)        ((x << 5) & 0x03E0)  /* Set Index 0->31 */
-#define TEST_WAY0          0x00000000   /* Access Way0 */
-#define TEST_WAY1          0x04000000   /* Access Way1 */
-/* ITEST_COMMAND only */
-#define TEST_WAY2          0x08000000   /* Access Way2 */
-#define TEST_WAY3          0x0C000000   /* Access Way3 */
-/* DTEST_COMMAND only */
-#define TEST_BNKSELA       0x00000000   /* Access SuperBank A */
-#define TEST_BNKSELB       0x00800000   /* Access SuperBank B */
-
-#endif                          /* _DEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h
deleted file mode 100644
index 42d1f37f6d9c..000000000000
--- a/include/asm-blackfin/mem_map.h
+++ /dev/null
@@ -1,12 +0,0 @@
-/*
- * mem_map.h
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _MEM_MAP_H_
-#define _MEM_MAP_H_
-
-#include <asm/mach/mem_map.h>
-
-#endif                          /* _MEM_MAP_H_ */
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
deleted file mode 100644
index b58f5ad3f024..000000000000
--- a/include/asm-blackfin/mman.h
+++ /dev/null
@@ -1,43 +0,0 @@
-#ifndef __BFIN_MMAN_H__
-#define __BFIN_MMAN_H__
-
-#define PROT_READ       0x1     /* page can be read */
-#define PROT_WRITE      0x2     /* page can be written */
-#define PROT_EXEC       0x4     /* page can be executed */
-#define PROT_SEM        0x8     /* page may be used for atomic ops */
-#define PROT_NONE       0x0     /* page can not be accessed */
-#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
-#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
-
-#define MAP_SHARED      0x01    /* Share changes */
-#define MAP_PRIVATE     0x02    /* Changes are private */
-#define MAP_TYPE        0x0f    /* Mask for type of mapping */
-#define MAP_FIXED       0x10    /* Interpret addr exactly */
-#define MAP_ANONYMOUS   0x20    /* don't use a file */
-
-#define MAP_GROWSDOWN   0x0100  /* stack-like segment */
-#define MAP_DENYWRITE   0x0800  /* ETXTBSY */
-#define MAP_EXECUTABLE  0x1000  /* mark it as an executable */
-#define MAP_LOCKED      0x2000  /* pages are locked */
-#define MAP_NORESERVE   0x4000  /* don't check for reservations */
-#define MAP_POPULATE    0x8000  /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x10000 /* do not block on IO */
-
-#define MS_ASYNC        1       /* sync memory asynchronously */
-#define MS_INVALIDATE   2       /* invalidate the caches */
-#define MS_SYNC         4       /* synchronous memory sync */
-
-#define MCL_CURRENT     1       /* lock all current mappings */
-#define MCL_FUTURE      2       /* lock all future mappings */
-
-#define MADV_NORMAL     0x0     /* default page-in behavior */
-#define MADV_RANDOM     0x1     /* page-in minimum required */
-#define MADV_SEQUENTIAL 0x2     /* read-ahead aggressively */
-#define MADV_WILLNEED   0x3     /* pre-fault pages */
-#define MADV_DONTNEED   0x4     /* discard these pages */
-
-/* compatibility flags */
-#define MAP_ANON        MAP_ANONYMOUS
-#define MAP_FILE        0
-
-#endif                          /* __BFIN_MMAN_H__ */
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
deleted file mode 100644
index 757e43906ed4..000000000000
--- a/include/asm-blackfin/mmu.h
+++ /dev/null
@@ -1,32 +0,0 @@
-#ifndef __MMU_H
-#define __MMU_H
-
-/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
-
-struct sram_list_struct {
-        struct sram_list_struct *next;
-        void *addr;
-        size_t length;
-};
-
-typedef struct {
-        struct vm_list_struct *vmlist;
-        unsigned long end_brk;
-        unsigned long stack_start;
-
-        /* Points to the location in SDRAM where the L1 stack is normally
-           saved, or NULL if the stack is always in SDRAM.  */
-        void *l1_stack_save;
-
-        struct sram_list_struct *sram_list;
-
-#ifdef CONFIG_BINFMT_ELF_FDPIC
-        unsigned long   exec_fdpic_loadmap;
-        unsigned long   interp_fdpic_loadmap;
-#endif
-#ifdef CONFIG_MPU
-        unsigned long *page_rwx_mask;
-#endif
-} mm_context_t;
-
-#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
deleted file mode 100644
index f55ec3c23a92..000000000000
--- a/include/asm-blackfin/mmu_context.h
+++ /dev/null
@@ -1,181 +0,0 @@
-/*
- * File:         include/asm-blackfin/mmu_context.h
- * Based on:
- * Author:
- *
- * Created:
- * Description:
- *
- * Modified:
- *               Copyright 2004-2006 Analog Devices Inc.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, see the file COPYING, or write
- * to the Free Software Foundation, Inc.,
- * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
- */
-
-#ifndef __BLACKFIN_MMU_CONTEXT_H__
-#define __BLACKFIN_MMU_CONTEXT_H__
-
-#include <linux/gfp.h>
-#include <linux/sched.h>
-#include <asm/setup.h>
-#include <asm/page.h>
-#include <asm/pgalloc.h>
-#include <asm/cplbinit.h>
-
-extern void *current_l1_stack_save;
-extern int nr_l1stack_tasks;
-extern void *l1_stack_base;
-extern unsigned long l1_stack_len;
-
-extern int l1sram_free(const void*);
-extern void *l1sram_alloc_max(void*);
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/* Called when creating a new context during fork() or execve().  */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-#ifdef CONFIG_MPU
-        unsigned long p = __get_free_pages(GFP_KERNEL, page_mask_order);
-        mm->context.page_rwx_mask = (unsigned long *)p;
-        memset(mm->context.page_rwx_mask, 0,
-               page_mask_nelts * 3 * sizeof(long));
-#endif
-        return 0;
-}
-
-static inline void free_l1stack(void)
-{
-        nr_l1stack_tasks--;
-        if (nr_l1stack_tasks == 0)
-                l1sram_free(l1_stack_base);
-}
-static inline void destroy_context(struct mm_struct *mm)
-{
-        struct sram_list_struct *tmp;
-
-        if (current_l1_stack_save == mm->context.l1_stack_save)
-                current_l1_stack_save = NULL;
-        if (mm->context.l1_stack_save)
-                free_l1stack();
-
-        while ((tmp = mm->context.sram_list)) {
-                mm->context.sram_list = tmp->next;
-                sram_free(tmp->addr);
-                kfree(tmp);
-        }
-#ifdef CONFIG_MPU
-        if (current_rwx_mask == mm->context.page_rwx_mask)
-                current_rwx_mask = NULL;
-        free_pages((unsigned long)mm->context.page_rwx_mask, page_mask_order);
-#endif
-}
-
-static inline unsigned long
-alloc_l1stack(unsigned long length, unsigned long *stack_base)
-{
-        if (nr_l1stack_tasks == 0) {
-                l1_stack_base = l1sram_alloc_max(&l1_stack_len);
-                if (!l1_stack_base)
-                        return 0;
-        }
-
-        if (l1_stack_len < length) {
-                if (nr_l1stack_tasks == 0)
-                        l1sram_free(l1_stack_base);
-                return 0;
-        }
-        *stack_base = (unsigned long)l1_stack_base;
-        nr_l1stack_tasks++;
-        return l1_stack_len;
-}
-
-static inline int
-activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
-{
-        if (current_l1_stack_save)
-                memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
-        mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
-        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-        return 1;
-}
-
-#define deactivate_mm(tsk,mm)   do { } while (0)
-
-#define activate_mm(prev, next) switch_mm(prev, next, NULL)
-
-static inline void switch_mm(struct mm_struct *prev_mm, struct mm_struct *next_mm,
-                             struct task_struct *tsk)
-{
-        if (prev_mm == next_mm)
-                return;
-#ifdef CONFIG_MPU
-        if (prev_mm->context.page_rwx_mask == current_rwx_mask) {
-                flush_switched_cplbs();
-                set_mask_dcplbs(next_mm->context.page_rwx_mask);
-        }
-#endif
-
-        /* L1 stack switching.  */
-        if (!next_mm->context.l1_stack_save)
-                return;
-        if (next_mm->context.l1_stack_save == current_l1_stack_save)
-                return;
-        if (current_l1_stack_save) {
-                memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
-        }
-        current_l1_stack_save = next_mm->context.l1_stack_save;
-        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
-}
-
-#ifdef CONFIG_MPU
-static inline void protect_page(struct mm_struct *mm, unsigned long addr,
-                                unsigned long flags)
-{
-        unsigned long *mask = mm->context.page_rwx_mask;
-        unsigned long page = addr >> 12;
-        unsigned long idx = page >> 5;
-        unsigned long bit = 1 << (page & 31);
-
-        if (flags & VM_MAYREAD)
-                mask[idx] |= bit;
-        else
-                mask[idx] &= ~bit;
-        mask += page_mask_nelts;
-        if (flags & VM_MAYWRITE)
-                mask[idx] |= bit;
-        else
-                mask[idx] &= ~bit;
-        mask += page_mask_nelts;
-        if (flags & VM_MAYEXEC)
-                mask[idx] |= bit;
-        else
-                mask[idx] &= ~bit;
-}
-
-static inline void update_protections(struct mm_struct *mm)
-{
-        flush_switched_cplbs();
-        set_mask_dcplbs(mm->context.page_rwx_mask);
-}
-#endif
-
-#endif
diff --git a/include/asm-blackfin/module.h b/include/asm-blackfin/module.h
deleted file mode 100644
index e3128df139d6..000000000000
--- a/include/asm-blackfin/module.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_BFIN_MODULE_H
-#define _ASM_BFIN_MODULE_H
-
-#define MODULE_SYMBOL_PREFIX "_"
-
-#define Elf_Shdr        Elf32_Shdr
-#define Elf_Sym         Elf32_Sym
-#define Elf_Ehdr        Elf32_Ehdr
-
-struct mod_arch_specific {
-        Elf_Shdr        *text_l1;
-        Elf_Shdr        *data_a_l1;
-        Elf_Shdr        *bss_a_l1;
-        Elf_Shdr        *data_b_l1;
-        Elf_Shdr        *bss_b_l1;
-        Elf_Shdr        *text_l2;
-        Elf_Shdr        *data_l2;
-        Elf_Shdr        *bss_l2;
-};
-#endif                          /* _ASM_BFIN_MODULE_H */
diff --git a/include/asm-blackfin/msgbuf.h b/include/asm-blackfin/msgbuf.h
deleted file mode 100644
index 6fcbe8cd801d..000000000000
--- a/include/asm-blackfin/msgbuf.h
+++ /dev/null
@@ -1,31 +0,0 @@
-#ifndef _BFIN_MSGBUF_H
-#define _BFIN_MSGBUF_H
-
-/*
- * The msqid64_ds structure for bfin architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-        unsigned long __unused1;
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-        unsigned long __unused2;
-        __kernel_time_t msg_ctime;      /* last change time */
-        unsigned long __unused3;
-        unsigned long msg_cbytes;       /* current number of bytes on queue */
-        unsigned long msg_qnum; /* number of messages in queue */
-        unsigned long msg_qbytes;       /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long __unused4;
-        unsigned long __unused5;
-};
-
-#endif                          /* _BFIN_MSGBUF_H */
diff --git a/include/asm-blackfin/mutex.h b/include/asm-blackfin/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-blackfin/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-blackfin/nand.h b/include/asm-blackfin/nand.h
deleted file mode 100644
index afbaafa793f1..000000000000
--- a/include/asm-blackfin/nand.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/* linux/include/asm-blackfin/nand.h
- *
- * Copyright (c) 2007 Analog Devices, Inc.
- *      Bryan Wu <bryan.wu@analog.com>
- *
- * BF5XX - NAND flash controller platfrom_device info
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 as
- * published by the Free Software Foundation.
- */
-
-/* struct bf5xx_nand_platform
- *
- * define a interface between platfrom board specific code and
- * bf54x NFC driver.
- *
- * nr_partitions = number of partitions pointed to be partitoons (or zero)
- * partitions    = mtd partition list
- */
-
-#define NFC_PG_SIZE_256         0
-#define NFC_PG_SIZE_512         1
-#define NFC_PG_SIZE_OFFSET      9
-
-#define NFC_NWIDTH_8            0
-#define NFC_NWIDTH_16           1
-#define NFC_NWIDTH_OFFSET       8
-
-#define NFC_RDDLY_OFFSET        4
-#define NFC_WRDLY_OFFSET        0
-
-#define NFC_STAT_NBUSY          1
-
-struct bf5xx_nand_platform {
-        /* NAND chip information */
-        unsigned short          page_size;
-        unsigned short          data_width;
-
-        /* RD/WR strobe delay timing information, all times in SCLK cycles */
-        unsigned short          rd_dly;
-        unsigned short          wr_dly;
-
-        /* NAND MTD partition information */
-        int                     nr_partitions;
-        struct mtd_partition    *partitions;
-};
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
deleted file mode 100644
index 344f6a8c1f22..000000000000
--- a/include/asm-blackfin/page.h
+++ /dev/null
@@ -1,88 +0,0 @@
-#ifndef _BLACKFIN_PAGE_H
-#define _BLACKFIN_PAGE_H
-
-/* PAGE_SHIFT determines the page size */
-
-#define PAGE_SHIFT      12
-#ifdef __ASSEMBLY__
-#define PAGE_SIZE       (1 << PAGE_SHIFT)
-#else
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#endif
-#define PAGE_MASK       (~(PAGE_SIZE-1))
-
-#include <asm/setup.h>
-
-#ifndef __ASSEMBLY__
-
-#define get_user_page(vaddr)            __get_free_page(GFP_KERNEL)
-#define free_user_page(page, addr)      free_page(addr)
-
-#define clear_page(page)        memset((page), 0, PAGE_SIZE)
-#define copy_page(to,from)      memcpy((to), (from), PAGE_SIZE)
-
-#define clear_user_page(page, vaddr,pg) clear_page(page)
-#define copy_user_page(to, from, vaddr,pg)      copy_page(to, from)
-
-/*
- * These are used to make use of C type-checking..
- */
-typedef struct {
-        unsigned long pte;
-} pte_t;
-typedef struct {
-        unsigned long pmd[16];
-} pmd_t;
-typedef struct {
-        unsigned long pgd;
-} pgd_t;
-typedef struct {
-        unsigned long pgprot;
-} pgprot_t;
-typedef struct page *pgtable_t;
-
-#define pte_val(x)      ((x).pte)
-#define pmd_val(x)      ((&x)->pmd[0])
-#define pgd_val(x)      ((x).pgd)
-#define pgprot_val(x)   ((x).pgprot)
-
-#define __pte(x)        ((pte_t) { (x) } )
-#define __pmd(x)        ((pmd_t) { (x) } )
-#define __pgd(x)        ((pgd_t) { (x) } )
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-extern unsigned long memory_start;
-extern unsigned long memory_end;
-
-#endif                          /* !__ASSEMBLY__ */
-
-#include <asm/page_offset.h>
-#include <asm/io.h>
-
-#define PAGE_OFFSET             (PAGE_OFFSET_RAW)
-
-#ifndef __ASSEMBLY__
-
-#define __pa(vaddr)             virt_to_phys((void *)(vaddr))
-#define __va(paddr)             phys_to_virt((unsigned long)(paddr))
-
-#define MAP_NR(addr)            (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
-
-#define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
-#define virt_to_page(addr)      (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
-#define page_to_virt(page)      ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
-#define VALID_PAGE(page)        ((page - mem_map) < max_mapnr)
-
-#define pfn_to_page(pfn)        virt_to_page(pfn_to_virt(pfn))
-#define page_to_pfn(page)       virt_to_pfn(page_to_virt(page))
-#define pfn_valid(pfn)          ((pfn) < max_mapnr)
-
-#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
-                                ((void *)(kaddr) < (void *)memory_end))
-
-#include <asm-generic/page.h>
-
-#endif                          /* __ASSEMBLY__ */
-
-#endif                          /* _BLACKFIN_PAGE_H */
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
deleted file mode 100644
index cbaff24b4b25..000000000000
--- a/include/asm-blackfin/page_offset.h
+++ /dev/null
@@ -1,6 +0,0 @@
-
-/* This handles the memory map.. */
-
-#ifdef CONFIG_BLACKFIN
-#define PAGE_OFFSET_RAW         0x00000000
-#endif
diff --git a/include/asm-blackfin/param.h b/include/asm-blackfin/param.h
deleted file mode 100644
index 41564a6347f8..000000000000
--- a/include/asm-blackfin/param.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _BLACKFIN_PARAM_H
-#define _BLACKFIN_PARAM_H
-
-#ifdef __KERNEL__
-#define HZ              CONFIG_HZ
-#define USER_HZ         100
-#define CLOCKS_PER_SEC  (USER_HZ)
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE   4096
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#endif                          /* _BLACKFIN_PARAM_H */
diff --git a/include/asm-blackfin/pci.h b/include/asm-blackfin/pci.h
deleted file mode 100644
index 61277358c865..000000000000
--- a/include/asm-blackfin/pci.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/* Changed from asm-m68k version, Lineo Inc.    May 2001        */
-
-#ifndef _ASM_BFIN_PCI_H
-#define _ASM_BFIN_PCI_H
-
-#include <asm/scatterlist.h>
-
-/*
- *
- * Written by Wout Klaren.
- */
-
-/* Added by Chang Junxiao */
-#define PCIBIOS_MIN_IO 0x00001000
-#define PCIBIOS_MIN_MEM 0x10000000
-
-#define PCI_DMA_BUS_IS_PHYS       (1)
-struct pci_ops;
-
-/*
- * Structure with hardware dependent information and functions of the
- * PCI bus.
- */
-struct pci_bus_info {
-
-        /*
-         * Resources of the PCI bus.
-         */
-        struct resource mem_space;
-        struct resource io_space;
-
-        /*
-         * System dependent functions.
-         */
-        struct pci_ops *bfin_pci_ops;
-        void (*fixup) (int pci_modify);
-        void (*conf_device) (unsigned char bus, unsigned char device_fn);
-};
-
-#define pcibios_assign_all_busses()     0
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
-
-        /* No special bus mastering setup handling */
-}
-static inline void pcibios_penalize_isa_irq(int irq)
-{
-
-        /* We don't do dynamic PCI IRQ allocation */
-}
-static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
-                                        size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-         /* return virt_to_bus(ptr); */
-        return (dma_addr_t) ptr;
-}
-
-/* Unmap a single streaming mode DMA translation.  The dma_addr and size
- * must match what was provided for in a previous pci_map_single call.  All
- * other usages are undefined.
- *
- * After this call, reads by the cpu to the buffer are guarenteed to see
- * whatever the device wrote there.
- */
-static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
-                                    size_t size, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Map a set of buffers described by scatterlist in streaming
- * mode for DMA.  This is the scather-gather version of the
- * above pci_map_single interface.  Here the scatter gather list
- * elements are each tagged with the appropriate dma address
- * and length.  They are obtained via sg_dma_{address,length}(SG).
- *
- * NOTE: An implementation may be able to use a smaller number of
- *       DMA address/length pairs than there are SG table elements.
- *       (for example via virtual mapping capabilities)
- *       The routine returns the number of addr/length pairs actually
- *       used, at most nents.
- *
- * Device ownership issues as mentioned above for pci_map_single are
- * the same here.
- */
-static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                             int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-        return nents;
-}
-
-/* Unmap a set of streaming mode DMA translations.
- * Again, cpu read rules concerning calls here are the same as for
- * pci_unmap_single() above.
- */
-static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
-                                int nents, int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a single
- * streaming mode DMA translation after a transfer.
- *
- * If you perform a pci_map_single() but wish to interrogate the
- * buffer using the cpu, yet do not wish to teardown the PCI dma
- * mapping, you must call this function before doing so.  At the
- * next point you give the PCI dma address back to the card, the
- * device again owns the buffer.
- */
-static inline void pci_dma_sync_single(struct pci_dev *hwdev,
-                                       dma_addr_t dma_handle, size_t size,
-                                       int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-/* Make physical memory consistent for a set of streaming
- * mode DMA translations after a transfer.
- *
- * The same as pci_dma_sync_single but for a scatter-gather list,
- * same rules and usage.
- */
-static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
-                                   struct scatterlist *sg, int nelems,
-                                   int direction)
-{
-        if (direction == PCI_DMA_NONE)
-                BUG();
-
-        /* Nothing to do */
-}
-
-#endif                          /* _ASM_BFIN_PCI_H */
diff --git a/include/asm-blackfin/percpu.h b/include/asm-blackfin/percpu.h
deleted file mode 100644
index 78dd61f6b39f..000000000000
--- a/include/asm-blackfin/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ARCH_BLACKFIN_PERCPU__
-#define __ARCH_BLACKFIN_PERCPU__
-
-#include <asm-generic/percpu.h>
-
-#endif                          /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/include/asm-blackfin/pgalloc.h b/include/asm-blackfin/pgalloc.h
deleted file mode 100644
index c686e0542fd0..000000000000
--- a/include/asm-blackfin/pgalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef _BLACKFIN_PGALLOC_H
-#define _BLACKFIN_PGALLOC_H
-
-#include <asm/setup.h>
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif                          /* _BLACKFIN_PGALLOC_H */
diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h
deleted file mode 100644
index b11b114689c0..000000000000
--- a/include/asm-blackfin/pgtable.h
+++ /dev/null
@@ -1,96 +0,0 @@
-#ifndef _BLACKFIN_PGTABLE_H
-#define _BLACKFIN_PGTABLE_H
-
-#include <asm-generic/4level-fixup.h>
-
-#include <asm/page.h>
-#include <asm/mach-common/def_LPBlackfin.h>
-
-typedef pte_t *pte_addr_t;
-/*
-* Trivial page table functions.
-*/
-#define pgd_present(pgd)        (1)
-#define pgd_none(pgd)           (0)
-#define pgd_bad(pgd)            (0)
-#define pgd_clear(pgdp)
-#define kern_addr_valid(addr)   (1)
-
-#define pmd_offset(a, b)        ((void *)0)
-#define pmd_none(x)             (!pmd_val(x))
-#define pmd_present(x)          (pmd_val(x))
-#define pmd_clear(xp)           do { set_pmd(xp, __pmd(0)); } while (0)
-#define pmd_bad(x)              (pmd_val(x) & ~PAGE_MASK)
-
-#define kern_addr_valid(addr) (1)
-
-#define PAGE_NONE               __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_SHARED             __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_COPY               __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_READONLY           __pgprot(0)     /* these mean nothing to NO_MM */
-#define PAGE_KERNEL             __pgprot(0)     /* these mean nothing to NO_MM */
-
-extern void paging_init(void);
-
-#define __swp_type(x)           (0)
-#define __swp_offset(x)         (0)
-#define __swp_entry(typ,off)    ((swp_entry_t) { ((typ) | ((off) << 7)) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-
-static inline int pte_file(pte_t pte)
-{
-        return 0;
-}
-
-#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-/*
- * Page assess control based on Blackfin CPLB management
- */
-#define _PAGE_RD        (CPLB_USER_RD)
-#define _PAGE_WR        (CPLB_USER_WR)
-#define _PAGE_USER      (CPLB_USER_RD | CPLB_USER_WR)
-#define _PAGE_ACCESSED  CPLB_ALL_ACCESS
-#define _PAGE_DIRTY     (CPLB_DIRTY)
-
-#define PTE_BIT_FUNC(fn, op) \
-        static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
-
-PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
-PTE_BIT_FUNC(mkread, |= _PAGE_RD);
-PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
-PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
-PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
-PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
-PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
-PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
-PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
-PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-#define ZERO_PAGE(vaddr)        (virt_to_page(0))
-
-extern unsigned int kobjsize(const void *objp);
-
-#define swapper_pg_dir ((pgd_t *) 0)
-/*
- * No page table caches to initialise.
- */
-#define pgtable_cache_init()    do { } while (0)
-#define io_remap_pfn_range      remap_pfn_range
-
-/*
- * All 32bit addresses are effectively valid for vmalloc...
- * Sort of meaningless for non-VM targets.
- */
-#define VMALLOC_START   0
-#define VMALLOC_END     0xffffffff
-
-#include <asm-generic/pgtable.h>
-
-#endif                          /* _BLACKFIN_PGTABLE_H */
diff --git a/include/asm-blackfin/poll.h b/include/asm-blackfin/poll.h
deleted file mode 100644
index 94cc2636e0e2..000000000000
--- a/include/asm-blackfin/poll.h
+++ /dev/null
@@ -1,24 +0,0 @@
-#ifndef __BFIN_POLL_H
-#define __BFIN_POLL_H
-
-#define POLLIN            1
-#define POLLPRI           2
-#define POLLOUT           4
-#define POLLERR           8
-#define POLLHUP          16
-#define POLLNVAL         32
-#define POLLRDNORM       64
-#define POLLWRNORM      POLLOUT
-#define POLLRDBAND      128
-#define POLLWRBAND      256
-#define POLLMSG         0x0400
-#define POLLREMOVE      0x1000
-#define POLLRDHUP       0x2000
-
-struct pollfd {
-        int fd;
-        short events;
-        short revents;
-};
-
-#endif                          /* __BFIN_POLL_H */
diff --git a/include/asm-blackfin/portmux.h b/include/asm-blackfin/portmux.h
deleted file mode 100644
index 0807b286cd9e..000000000000
--- a/include/asm-blackfin/portmux.h
+++ /dev/null
@@ -1,1188 +0,0 @@
-/*
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _PORTMUX_H_
-#define _PORTMUX_H_
-
-#define P_IDENT(x)      ((x) & 0x1FF)
-#define P_FUNCT(x)      (((x) & 0x3) << 9)
-#define P_FUNCT2MUX(x)  (((x) >> 9) & 0x3)
-#define P_DEFINED       0x8000
-#define P_UNDEF         0x4000
-#define P_MAYSHARE      0x2000
-#define P_DONTCARE      0x1000
-
-
-int peripheral_request(unsigned short per, const char *label);
-void peripheral_free(unsigned short per);
-int peripheral_request_list(const unsigned short per[], const char *label);
-void peripheral_free_list(const unsigned short per[]);
-
-#include <asm/gpio.h>
-#include <asm/mach/portmux.h>
-
-#ifndef P_SPORT2_TFS
-#define P_SPORT2_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTSEC
-#define P_SPORT2_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DTPRI
-#define P_SPORT2_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_TSCLK
-#define P_SPORT2_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RFS
-#define P_SPORT2_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRSEC
-#define P_SPORT2_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT2_DRPRI
-#define P_SPORT2_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT2_RSCLK
-#define P_SPORT2_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TFS
-#define P_SPORT3_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTSEC
-#define P_SPORT3_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DTPRI
-#define P_SPORT3_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_TSCLK
-#define P_SPORT3_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RFS
-#define P_SPORT3_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRSEC
-#define P_SPORT3_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT3_DRPRI
-#define P_SPORT3_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT3_RSCLK
-#define P_SPORT3_RSCLK P_UNDEF
-#endif
-
-#ifndef P_TMR4
-#define P_TMR4 P_UNDEF
-#endif
-
-#ifndef P_TMR5
-#define P_TMR5 P_UNDEF
-#endif
-
-#ifndef P_TMR6
-#define P_TMR6 P_UNDEF
-#endif
-
-#ifndef P_TMR7
-#define P_TMR7 P_UNDEF
-#endif
-
-#ifndef P_TWI1_SCL
-#define P_TWI1_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI1_SDA
-#define P_TWI1_SDA P_UNDEF
-#endif
-
-#ifndef P_UART3_RTS
-#define P_UART3_RTS P_UNDEF
-#endif
-
-#ifndef P_UART3_CTS
-#define P_UART3_CTS P_UNDEF
-#endif
-
-#ifndef P_UART2_TX
-#define P_UART2_TX P_UNDEF
-#endif
-
-#ifndef P_UART2_RX
-#define P_UART2_RX P_UNDEF
-#endif
-
-#ifndef P_UART3_TX
-#define P_UART3_TX P_UNDEF
-#endif
-
-#ifndef P_UART3_RX
-#define P_UART3_RX P_UNDEF
-#endif
-
-#ifndef P_SPI2_SS
-#define P_SPI2_SS P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL1
-#define P_SPI2_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL2
-#define P_SPI2_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL3
-#define P_SPI2_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL4
-#define P_SPI2_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL5
-#define P_SPI2_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL6
-#define P_SPI2_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SSEL7
-#define P_SPI2_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI2_SCK
-#define P_SPI2_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI2_MOSI
-#define P_SPI2_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI2_MISO
-#define P_SPI2_MISO P_UNDEF
-#endif
-
-#ifndef P_TMR0
-#define P_TMR0 P_UNDEF
-#endif
-
-#ifndef P_TMR1
-#define P_TMR1 P_UNDEF
-#endif
-
-#ifndef P_TMR2
-#define P_TMR2 P_UNDEF
-#endif
-
-#ifndef P_TMR3
-#define P_TMR3 P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TFS
-#define P_SPORT0_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTSEC
-#define P_SPORT0_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DTPRI
-#define P_SPORT0_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_TSCLK
-#define P_SPORT0_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RFS
-#define P_SPORT0_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRSEC
-#define P_SPORT0_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT0_DRPRI
-#define P_SPORT0_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT0_RSCLK
-#define P_SPORT0_RSCLK P_UNDEF
-#endif
-
-#ifndef P_SD_D0
-#define P_SD_D0 P_UNDEF
-#endif
-
-#ifndef P_SD_D1
-#define P_SD_D1 P_UNDEF
-#endif
-
-#ifndef P_SD_D2
-#define P_SD_D2 P_UNDEF
-#endif
-
-#ifndef P_SD_D3
-#define P_SD_D3 P_UNDEF
-#endif
-
-#ifndef P_SD_CLK
-#define P_SD_CLK P_UNDEF
-#endif
-
-#ifndef P_SD_CMD
-#define P_SD_CMD P_UNDEF
-#endif
-
-#ifndef P_MMCLK
-#define P_MMCLK P_UNDEF
-#endif
-
-#ifndef P_MBCLK
-#define P_MBCLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_D0
-#define P_PPI1_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D1
-#define P_PPI1_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D2
-#define P_PPI1_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D3
-#define P_PPI1_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D4
-#define P_PPI1_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D5
-#define P_PPI1_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D6
-#define P_PPI1_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D7
-#define P_PPI1_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D8
-#define P_PPI1_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D9
-#define P_PPI1_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D10
-#define P_PPI1_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D11
-#define P_PPI1_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D12
-#define P_PPI1_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D13
-#define P_PPI1_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D14
-#define P_PPI1_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI1_D15
-#define P_PPI1_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D8
-#define P_HOST_D8 P_UNDEF
-#endif
-
-#ifndef P_HOST_D9
-#define P_HOST_D9 P_UNDEF
-#endif
-
-#ifndef P_HOST_D10
-#define P_HOST_D10 P_UNDEF
-#endif
-
-#ifndef P_HOST_D11
-#define P_HOST_D11 P_UNDEF
-#endif
-
-#ifndef P_HOST_D12
-#define P_HOST_D12 P_UNDEF
-#endif
-
-#ifndef P_HOST_D13
-#define P_HOST_D13 P_UNDEF
-#endif
-
-#ifndef P_HOST_D14
-#define P_HOST_D14 P_UNDEF
-#endif
-
-#ifndef P_HOST_D15
-#define P_HOST_D15 P_UNDEF
-#endif
-
-#ifndef P_HOST_D0
-#define P_HOST_D0 P_UNDEF
-#endif
-
-#ifndef P_HOST_D1
-#define P_HOST_D1 P_UNDEF
-#endif
-
-#ifndef P_HOST_D2
-#define P_HOST_D2 P_UNDEF
-#endif
-
-#ifndef P_HOST_D3
-#define P_HOST_D3 P_UNDEF
-#endif
-
-#ifndef P_HOST_D4
-#define P_HOST_D4 P_UNDEF
-#endif
-
-#ifndef P_HOST_D5
-#define P_HOST_D5 P_UNDEF
-#endif
-
-#ifndef P_HOST_D6
-#define P_HOST_D6 P_UNDEF
-#endif
-
-#ifndef P_HOST_D7
-#define P_HOST_D7 P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TFS
-#define P_SPORT1_TFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTSEC
-#define P_SPORT1_DTSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DTPRI
-#define P_SPORT1_DTPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_TSCLK
-#define P_SPORT1_TSCLK P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RFS
-#define P_SPORT1_RFS P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRSEC
-#define P_SPORT1_DRSEC P_UNDEF
-#endif
-
-#ifndef P_SPORT1_DRPRI
-#define P_SPORT1_DRPRI P_UNDEF
-#endif
-
-#ifndef P_SPORT1_RSCLK
-#define P_SPORT1_RSCLK P_UNDEF
-#endif
-
-#ifndef P_PPI2_D0
-#define P_PPI2_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D1
-#define P_PPI2_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D2
-#define P_PPI2_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D3
-#define P_PPI2_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D4
-#define P_PPI2_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D5
-#define P_PPI2_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D6
-#define P_PPI2_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI2_D7
-#define P_PPI2_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D18
-#define P_PPI0_D18 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D19
-#define P_PPI0_D19 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D20
-#define P_PPI0_D20 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D21
-#define P_PPI0_D21 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D22
-#define P_PPI0_D22 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D23
-#define P_PPI0_D23 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW0
-#define P_KEY_ROW0 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW1
-#define P_KEY_ROW1 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW2
-#define P_KEY_ROW2 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW3
-#define P_KEY_ROW3 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL0
-#define P_KEY_COL0 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL1
-#define P_KEY_COL1 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL2
-#define P_KEY_COL2 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL3
-#define P_KEY_COL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SCK
-#define P_SPI0_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI0_MISO
-#define P_SPI0_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI0_MOSI
-#define P_SPI0_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI0_SS
-#define P_SPI0_SS P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL1
-#define P_SPI0_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL2
-#define P_SPI0_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL3
-#define P_SPI0_SSEL3 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL4
-#define P_SPI0_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL5
-#define P_SPI0_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL6
-#define P_SPI0_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI0_SSEL7
-#define P_SPI0_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_UART0_TX
-#define P_UART0_TX P_UNDEF
-#endif
-
-#ifndef P_UART0_RX
-#define P_UART0_RX P_UNDEF
-#endif
-
-#ifndef P_UART1_RTS
-#define P_UART1_RTS P_UNDEF
-#endif
-
-#ifndef P_UART1_CTS
-#define P_UART1_CTS P_UNDEF
-#endif
-
-#ifndef P_PPI1_CLK
-#define P_PPI1_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS1
-#define P_PPI1_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS2
-#define P_PPI1_FS2 P_UNDEF
-#endif
-
-#ifndef P_TWI0_SCL
-#define P_TWI0_SCL P_UNDEF
-#endif
-
-#ifndef P_TWI0_SDA
-#define P_TWI0_SDA P_UNDEF
-#endif
-
-#ifndef P_KEY_COL7
-#define P_KEY_COL7 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW6
-#define P_KEY_ROW6 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL6
-#define P_KEY_COL6 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW5
-#define P_KEY_ROW5 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL5
-#define P_KEY_COL5 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW4
-#define P_KEY_ROW4 P_UNDEF
-#endif
-
-#ifndef P_KEY_COL4
-#define P_KEY_COL4 P_UNDEF
-#endif
-
-#ifndef P_KEY_ROW7
-#define P_KEY_ROW7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D0
-#define P_PPI0_D0 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D1
-#define P_PPI0_D1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D2
-#define P_PPI0_D2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D3
-#define P_PPI0_D3 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D4
-#define P_PPI0_D4 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D5
-#define P_PPI0_D5 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D6
-#define P_PPI0_D6 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D7
-#define P_PPI0_D7 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D8
-#define P_PPI0_D8 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D9
-#define P_PPI0_D9 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D10
-#define P_PPI0_D10 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D11
-#define P_PPI0_D11 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D12
-#define P_PPI0_D12 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D13
-#define P_PPI0_D13 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D14
-#define P_PPI0_D14 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D15
-#define P_PPI0_D15 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D0A
-#define P_ATAPI_D0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D1A
-#define P_ATAPI_D1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D2A
-#define P_ATAPI_D2A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D3A
-#define P_ATAPI_D3A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D4A
-#define P_ATAPI_D4A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D5A
-#define P_ATAPI_D5A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D6A
-#define P_ATAPI_D6A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D7A
-#define P_ATAPI_D7A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D8A
-#define P_ATAPI_D8A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D9A
-#define P_ATAPI_D9A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D10A
-#define P_ATAPI_D10A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D11A
-#define P_ATAPI_D11A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D12A
-#define P_ATAPI_D12A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D13A
-#define P_ATAPI_D13A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D14A
-#define P_ATAPI_D14A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_D15A
-#define P_ATAPI_D15A P_UNDEF
-#endif
-
-#ifndef P_PPI0_CLK
-#define P_PPI0_CLK P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS1
-#define P_PPI0_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS2
-#define P_PPI0_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D16
-#define P_PPI0_D16 P_UNDEF
-#endif
-
-#ifndef P_PPI0_D17
-#define P_PPI0_D17 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL1
-#define P_SPI1_SSEL1 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL2
-#define P_SPI1_SSEL2 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL3
-#define P_SPI1_SSEL3 P_UNDEF
-#endif
-
-
-#ifndef P_SPI1_SSEL4
-#define P_SPI1_SSEL4 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL5
-#define P_SPI1_SSEL5 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL6
-#define P_SPI1_SSEL6 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SSEL7
-#define P_SPI1_SSEL7 P_UNDEF
-#endif
-
-#ifndef P_SPI1_SCK
-#define P_SPI1_SCK P_UNDEF
-#endif
-
-#ifndef P_SPI1_MISO
-#define P_SPI1_MISO P_UNDEF
-#endif
-
-#ifndef P_SPI1_MOSI
-#define P_SPI1_MOSI P_UNDEF
-#endif
-
-#ifndef P_SPI1_SS
-#define P_SPI1_SS P_UNDEF
-#endif
-
-#ifndef P_CAN0_TX
-#define P_CAN0_TX P_UNDEF
-#endif
-
-#ifndef P_CAN0_RX
-#define P_CAN0_RX P_UNDEF
-#endif
-
-#ifndef P_CAN1_TX
-#define P_CAN1_TX P_UNDEF
-#endif
-
-#ifndef P_CAN1_RX
-#define P_CAN1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A0A
-#define P_ATAPI_A0A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A1A
-#define P_ATAPI_A1A P_UNDEF
-#endif
-
-#ifndef P_ATAPI_A2A
-#define P_ATAPI_A2A P_UNDEF
-#endif
-
-#ifndef P_HOST_CE
-#define P_HOST_CE P_UNDEF
-#endif
-
-#ifndef P_HOST_RD
-#define P_HOST_RD P_UNDEF
-#endif
-
-#ifndef P_HOST_WR
-#define P_HOST_WR P_UNDEF
-#endif
-
-#ifndef P_MTXONB
-#define P_MTXONB P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS2
-#define P_PPI2_FS2 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS1
-#define P_PPI2_FS1 P_UNDEF
-#endif
-
-#ifndef P_PPI2_CLK
-#define P_PPI2_CLK P_UNDEF
-#endif
-
-#ifndef P_CNT_CZM
-#define P_CNT_CZM P_UNDEF
-#endif
-
-#ifndef P_UART1_TX
-#define P_UART1_TX P_UNDEF
-#endif
-
-#ifndef P_UART1_RX
-#define P_UART1_RX P_UNDEF
-#endif
-
-#ifndef P_ATAPI_RESET
-#define P_ATAPI_RESET P_UNDEF
-#endif
-
-#ifndef P_HOST_ADDR
-#define P_HOST_ADDR P_UNDEF
-#endif
-
-#ifndef P_HOST_ACK
-#define P_HOST_ACK P_UNDEF
-#endif
-
-#ifndef P_MTX
-#define P_MTX P_UNDEF
-#endif
-
-#ifndef P_MRX
-#define P_MRX P_UNDEF
-#endif
-
-#ifndef P_MRXONB
-#define P_MRXONB P_UNDEF
-#endif
-
-#ifndef P_A4
-#define P_A4 P_UNDEF
-#endif
-
-#ifndef P_A5
-#define P_A5 P_UNDEF
-#endif
-
-#ifndef P_A6
-#define P_A6 P_UNDEF
-#endif
-
-#ifndef P_A7
-#define P_A7 P_UNDEF
-#endif
-
-#ifndef P_A8
-#define P_A8 P_UNDEF
-#endif
-
-#ifndef P_A9
-#define P_A9 P_UNDEF
-#endif
-
-#ifndef P_PPI1_FS3
-#define P_PPI1_FS3 P_UNDEF
-#endif
-
-#ifndef P_PPI2_FS3
-#define P_PPI2_FS3 P_UNDEF
-#endif
-
-#ifndef P_TMR8
-#define P_TMR8 P_UNDEF
-#endif
-
-#ifndef P_TMR9
-#define P_TMR9 P_UNDEF
-#endif
-
-#ifndef P_TMR10
-#define P_TMR10 P_UNDEF
-#endif
-#ifndef P_TMR11
-#define P_TMR11 P_UNDEF
-#endif
-
-#ifndef P_DMAR0
-#define P_DMAR0 P_UNDEF
-#endif
-
-#ifndef P_DMAR1
-#define P_DMAR1 P_UNDEF
-#endif
-
-#ifndef P_PPI0_FS3
-#define P_PPI0_FS3 P_UNDEF
-#endif
-
-#ifndef P_CNT_CDG
-#define P_CNT_CDG P_UNDEF
-#endif
-
-#ifndef P_CNT_CUD
-#define P_CNT_CUD P_UNDEF
-#endif
-
-#ifndef P_A10
-#define P_A10 P_UNDEF
-#endif
-
-#ifndef P_A11
-#define P_A11 P_UNDEF
-#endif
-
-#ifndef P_A12
-#define P_A12 P_UNDEF
-#endif
-
-#ifndef P_A13
-#define P_A13 P_UNDEF
-#endif
-
-#ifndef P_A14
-#define P_A14 P_UNDEF
-#endif
-
-#ifndef P_A15
-#define P_A15 P_UNDEF
-#endif
-
-#ifndef P_A16
-#define P_A16 P_UNDEF
-#endif
-
-#ifndef P_A17
-#define P_A17 P_UNDEF
-#endif
-
-#ifndef P_A18
-#define P_A18 P_UNDEF
-#endif
-
-#ifndef P_A19
-#define P_A19 P_UNDEF
-#endif
-
-#ifndef P_A20
-#define P_A20 P_UNDEF
-#endif
-
-#ifndef P_A21
-#define P_A21 P_UNDEF
-#endif
-
-#ifndef P_A22
-#define P_A22 P_UNDEF
-#endif
-
-#ifndef P_A23
-#define P_A23 P_UNDEF
-#endif
-
-#ifndef P_A24
-#define P_A24 P_UNDEF
-#endif
-
-#ifndef P_A25
-#define P_A25 P_UNDEF
-#endif
-
-#ifndef P_NOR_CLK
-#define P_NOR_CLK P_UNDEF
-#endif
-
-#ifndef  P_TMRCLK
-#define  P_TMRCLK P_UNDEF
-#endif
-
-#ifndef P_AMC_ARDY_NOR_WAIT
-#define P_AMC_ARDY_NOR_WAIT P_UNDEF
-#endif
-
-#ifndef P_NAND_CE
-#define P_NAND_CE P_UNDEF
-#endif
-
-#ifndef P_NAND_RB
-#define P_NAND_RB P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOR
-#define P_ATAPI_DIOR P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DIOW
-#define P_ATAPI_DIOW P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS0
-#define P_ATAPI_CS0 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_CS1
-#define P_ATAPI_CS1 P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMACK
-#define P_ATAPI_DMACK P_UNDEF
-#endif
-
-#ifndef P_ATAPI_DMARQ
-#define P_ATAPI_DMARQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_INTRQ
-#define P_ATAPI_INTRQ P_UNDEF
-#endif
-
-#ifndef P_ATAPI_IORDY
-#define P_ATAPI_IORDY P_UNDEF
-#endif
-
-#ifndef P_AMC_BR
-#define P_AMC_BR P_UNDEF
-#endif
-
-#ifndef P_AMC_BG
-#define P_AMC_BG P_UNDEF
-#endif
-
-#ifndef P_AMC_BGH
-#define P_AMC_BGH P_UNDEF
-#endif
-
-/* EMAC */
-
-#ifndef P_MII0_ETxD0
-#define P_MII0_ETxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD1
-#define P_MII0_ETxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD2
-#define P_MII0_ETxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxD3
-#define P_MII0_ETxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ETxEN
-#define P_MII0_ETxEN P_UNDEF
-#endif
-
-#ifndef P_MII0_TxCLK
-#define P_MII0_TxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_PHYINT
-#define P_MII0_PHYINT P_UNDEF
-#endif
-
-#ifndef P_MII0_COL
-#define P_MII0_COL P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD0
-#define P_MII0_ERxD0 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD1
-#define P_MII0_ERxD1 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD2
-#define P_MII0_ERxD2 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxD3
-#define P_MII0_ERxD3 P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxDV
-#define P_MII0_ERxDV P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxCLK
-#define P_MII0_ERxCLK P_UNDEF
-#endif
-
-#ifndef P_MII0_ERxER
-#define P_MII0_ERxER P_UNDEF
-#endif
-
-#ifndef P_MII0_CRS
-#define P_MII0_CRS P_UNDEF
-#endif
-
-#ifndef P_RMII0_REF_CLK
-#define P_RMII0_REF_CLK P_UNDEF
-#endif
-
-#ifndef P_RMII0_MDINT
-#define P_RMII0_MDINT P_UNDEF
-#endif
-
-#ifndef P_RMII0_CRS_DV
-#define P_RMII0_CRS_DV P_UNDEF
-#endif
-
-#ifndef P_MDC
-#define P_MDC P_UNDEF
-#endif
-
-#ifndef P_MDIO
-#define P_MDIO P_UNDEF
-#endif
-
-#endif                          /* _PORTMUX_H_ */
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
deleted file mode 100644
index 23aa1f8c1bd1..000000000000
--- a/include/asm-blackfin/posix_types.h
+++ /dev/null
@@ -1,61 +0,0 @@
-#ifndef __ARCH_BFIN_POSIX_TYPES_H
-#define __ARCH_BFIN_POSIX_TYPES_H
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long __kernel_ino_t;
-typedef unsigned short __kernel_mode_t;
-typedef unsigned short __kernel_nlink_t;
-typedef long __kernel_off_t;
-typedef int __kernel_pid_t;
-typedef unsigned int __kernel_ipc_pid_t;
-typedef unsigned int __kernel_uid_t;
-typedef unsigned int __kernel_gid_t;
-typedef unsigned long __kernel_size_t;
-typedef long __kernel_ssize_t;
-typedef int __kernel_ptrdiff_t;
-typedef long __kernel_time_t;
-typedef long __kernel_suseconds_t;
-typedef long __kernel_clock_t;
-typedef int __kernel_timer_t;
-typedef int __kernel_clockid_t;
-typedef int __kernel_daddr_t;
-typedef char *__kernel_caddr_t;
-typedef unsigned short __kernel_uid16_t;
-typedef unsigned short __kernel_gid16_t;
-typedef unsigned int __kernel_uid32_t;
-typedef unsigned int __kernel_gid32_t;
-
-typedef unsigned short __kernel_old_uid_t;
-typedef unsigned short __kernel_old_gid_t;
-typedef unsigned short __kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long __kernel_loff_t;
-#endif
-
-typedef struct {
-        int val[2];
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef  __FD_SET
-#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
-
-#undef  __FD_CLR
-#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
-
-#undef  __FD_ISSET
-#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
-
-#undef  __FD_ZERO
-#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
-
-#endif                          /* defined(__KERNEL__) */
-
-#endif
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
deleted file mode 100644
index 6f3995b119d8..000000000000
--- a/include/asm-blackfin/processor.h
+++ /dev/null
@@ -1,158 +0,0 @@
-#ifndef __ASM_BFIN_PROCESSOR_H
-#define __ASM_BFIN_PROCESSOR_H
-
-/*
- * Default implementation of macro that returns current
- * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-#include <asm/blackfin.h>
-#include <asm/segment.h>
-#include <linux/compiler.h>
-
-static inline unsigned long rdusp(void)
-{
-        unsigned long usp;
-
-        __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
-        return usp;
-}
-
-static inline void wrusp(unsigned long usp)
-{
-        __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
-}
-
-/*
- * User space process size: 1st byte beyond user address space.
- * Fairly meaningless on nommu.  Parts of user programs can be scattered
- * in a lot of places, so just disable this by setting it to 0xFFFFFFFF.
- */
-#define TASK_SIZE       0xFFFFFFFF
-
-#ifdef __KERNEL__
-#define STACK_TOP       TASK_SIZE
-#endif
-
-#define TASK_UNMAPPED_BASE      0
-
-struct thread_struct {
-        unsigned long ksp;      /* kernel stack pointer */
-        unsigned long usp;      /* user stack pointer */
-        unsigned short seqstat; /* saved status register */
-        unsigned long esp0;     /* points to SR of stack frame pt_regs */
-        unsigned long pc;       /* instruction pointer */
-        void *        debuggerinfo;
-};
-
-#define INIT_THREAD  {                                          \
-        sizeof(init_stack) + (unsigned long) init_stack, 0,     \
-        PS_S, 0, 0                                              \
-}
-
-/*
- * Do necessary setup to start up a newly executed thread.
- *
- * pass the data segment into user programs if it exists,
- * it can't hurt anything as far as I can tell
- */
-#define start_thread(_regs, _pc, _usp)                                  \
-do {                                                                    \
-        set_fs(USER_DS);                                                \
-        (_regs)->pc = (_pc);                                            \
-        if (current->mm)                                                \
-                (_regs)->p5 = current->mm->start_data;                  \
-        task_thread_info(current)->l1_task_info.stack_start             \
-                = (void *)current->mm->context.stack_start;             \
-        task_thread_info(current)->l1_task_info.lowest_sp = (void *)(_usp); \
-        memcpy(L1_SCRATCH_TASK_INFO, &task_thread_info(current)->l1_task_info, \
-                sizeof(*L1_SCRATCH_TASK_INFO));                         \
-        wrusp(_usp);                                                    \
-} while(0)
-
-/* Forward declaration, a strange C thing */
-struct task_struct;
-
-/* Free all resources held by a thread. */
-static inline void release_thread(struct task_struct *dead_task)
-{
-}
-
-#define prepare_to_copy(tsk)    do { } while (0)
-
-extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
-
-/*
- * Free current thread data structures etc..
- */
-static inline void exit_thread(void)
-{
-}
-
-/*
- * Return saved PC of a blocked thread.
- */
-#define thread_saved_pc(tsk)    (tsk->thread.pc)
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define KSTK_EIP(tsk)                                                   \
-    ({                                                                  \
-        unsigned long eip = 0;                                          \
-        if ((tsk)->thread.esp0 > PAGE_SIZE &&                           \
-            MAP_NR((tsk)->thread.esp0) < max_mapnr)                     \
-              eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc;        \
-        eip; })
-#define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
-
-#define cpu_relax()     barrier()
-
-/* Get the Silicon Revision of the chip */
-static inline uint32_t __pure bfin_revid(void)
-{
-        /* stored in the upper 4 bits */
-        uint32_t revid = bfin_read_CHIPID() >> 28;
-
-#ifdef CONFIG_BF52x
-        /* ANOMALY_05000357
-         * Incorrect Revision Number in DSPID Register
-         */
-        if (revid == 0)
-                switch (bfin_read16(_BOOTROM_GET_DXE_ADDRESS_TWI)) {
-                case 0x0010:
-                        revid = 0;
-                        break;
-                case 0x2796:
-                        revid = 1;
-                        break;
-                default:
-                        revid = 0xFFFF;
-                        break;
-                }
-#endif
-        return revid;
-}
-
-static inline uint32_t __pure bfin_compiled_revid(void)
-{
-#if defined(CONFIG_BF_REV_0_0)
-        return 0;
-#elif defined(CONFIG_BF_REV_0_1)
-        return 1;
-#elif defined(CONFIG_BF_REV_0_2)
-        return 2;
-#elif defined(CONFIG_BF_REV_0_3)
-        return 3;
-#elif defined(CONFIG_BF_REV_0_4)
-        return 4;
-#elif defined(CONFIG_BF_REV_0_5)
-        return 5;
-#elif defined(CONFIG_BF_REV_ANY)
-        return 0xffff;
-#else
-        return -1;
-#endif
-}
-
-#endif
diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
deleted file mode 100644
index a45a80e54adc..000000000000
--- a/include/asm-blackfin/ptrace.h
+++ /dev/null
@@ -1,168 +0,0 @@
-#ifndef _BFIN_PTRACE_H
-#define _BFIN_PTRACE_H
-
-/*
- * GCC defines register number like this:
- * -----------------------------
- *       0 - 7 are data registers R0-R7
- *       8 - 15 are address registers P0-P7
- *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
- *      32 - 33 A registers A0 & A1
- *      34 -    status register
- * -----------------------------
- *
- * We follows above, except:
- *      32-33 --- Low 32-bit of A0&1
- *      34-35 --- High 8-bit of A0&1
- */
-
-#ifndef __ASSEMBLY__
-
-/* this struct defines the way the registers are stored on the
-   stack during a system call. */
-
-struct pt_regs {
-        long orig_pc;
-        long ipend;
-        long seqstat;
-        long rete;
-        long retn;
-        long retx;
-        long pc;                /* PC == RETI */
-        long rets;
-        long reserved;          /* Used as scratch during system calls */
-        long astat;
-        long lb1;
-        long lb0;
-        long lt1;
-        long lt0;
-        long lc1;
-        long lc0;
-        long a1w;
-        long a1x;
-        long a0w;
-        long a0x;
-        long b3;
-        long b2;
-        long b1;
-        long b0;
-        long l3;
-        long l2;
-        long l1;
-        long l0;
-        long m3;
-        long m2;
-        long m1;
-        long m0;
-        long i3;
-        long i2;
-        long i1;
-        long i0;
-        long usp;
-        long fp;
-        long p5;
-        long p4;
-        long p3;
-        long p2;
-        long p1;
-        long p0;
-        long r7;
-        long r6;
-        long r5;
-        long r4;
-        long r3;
-        long r2;
-        long r1;
-        long r0;
-        long orig_r0;
-        long orig_p0;
-        long syscfg;
-};
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS            12
-#define PTRACE_SETREGS            13    /* ptrace signal  */
-
-#define PTRACE_GETFDPIC           31
-#define PTRACE_GETFDPIC_EXEC      0
-#define PTRACE_GETFDPIC_INTERP    1
-
-#define PS_S  (0x0002)
-
-#ifdef __KERNEL__
-
-/* user_mode returns true if only one bit is set in IPEND, other than the
-   master interrupt enable.  */
-#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
-#define instruction_pointer(regs) ((regs)->pc)
-#define profile_pc(regs) instruction_pointer(regs)
-extern void show_regs(struct pt_regs *);
-
-#endif  /*  __KERNEL__  */
-
-#endif                          /* __ASSEMBLY__ */
-
-/*
- * Offsets used by 'ptrace' system call interface.
- */
-
-#define PT_R0 204
-#define PT_R1 200
-#define PT_R2 196
-#define PT_R3 192
-#define PT_R4 188
-#define PT_R5 184
-#define PT_R6 180
-#define PT_R7 176
-#define PT_P0 172
-#define PT_P1 168
-#define PT_P2 164
-#define PT_P3 160
-#define PT_P4 156
-#define PT_P5 152
-#define PT_FP 148
-#define PT_USP 144
-#define PT_I0 140
-#define PT_I1 136
-#define PT_I2 132
-#define PT_I3 128
-#define PT_M0 124
-#define PT_M1 120
-#define PT_M2 116
-#define PT_M3 112
-#define PT_L0 108
-#define PT_L1 104
-#define PT_L2 100
-#define PT_L3 96
-#define PT_B0 92
-#define PT_B1 88
-#define PT_B2 84
-#define PT_B3 80
-#define PT_A0X 76
-#define PT_A0W 72
-#define PT_A1X 68
-#define PT_A1W 64
-#define PT_LC0 60
-#define PT_LC1 56
-#define PT_LT0 52
-#define PT_LT1 48
-#define PT_LB0 44
-#define PT_LB1 40
-#define PT_ASTAT 36
-#define PT_RESERVED 32
-#define PT_RETS 28
-#define PT_PC 24
-#define PT_RETX 20
-#define PT_RETN 16
-#define PT_RETE 12
-#define PT_SEQSTAT 8
-#define PT_IPEND 4
-
-#define PT_SYSCFG 216
-#define PT_TEXT_ADDR 220
-#define PT_TEXT_END_ADDR 224
-#define PT_DATA_ADDR 228
-#define PT_FDPIC_EXEC 232
-#define PT_FDPIC_INTERP 236
-
-#endif                          /* _BFIN_PTRACE_H */
diff --git a/include/asm-blackfin/reboot.h b/include/asm-blackfin/reboot.h
deleted file mode 100644
index 6d448b5f5985..000000000000
--- a/include/asm-blackfin/reboot.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * include/asm-blackfin/reboot.h - shutdown/reboot header
- *
- * Copyright 2004-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_REBOOT_H__
-#define __ASM_REBOOT_H__
-
-/* optional board specific hooks */
-extern void native_machine_restart(char *cmd);
-extern void native_machine_halt(void);
-extern void native_machine_power_off(void);
-
-/* common reboot workarounds */
-extern void bfin_gpio_reset_spi0_ssel1(void);
-
-#endif
diff --git a/include/asm-blackfin/resource.h b/include/asm-blackfin/resource.h
deleted file mode 100644
index 091355ab3495..000000000000
--- a/include/asm-blackfin/resource.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_RESOURCE_H
-#define _BFIN_RESOURCE_H
-
-#include <asm-generic/resource.h>
-
-#endif                          /* _BFIN_RESOURCE_H */
diff --git a/include/asm-blackfin/scatterlist.h b/include/asm-blackfin/scatterlist.h
deleted file mode 100644
index 04f448711cd0..000000000000
--- a/include/asm-blackfin/scatterlist.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _BLACKFIN_SCATTERLIST_H
-#define _BLACKFIN_SCATTERLIST_H
-
-#include <linux/mm.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long sg_magic;
-#endif
-        unsigned long page_link;
-        unsigned int offset;
-        dma_addr_t dma_address;
-        unsigned int length;
-};
-
-/*
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns, or alternatively stop on the first sg_dma_len(sg) which
- * is 0.
- */
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->length)
-
-#define ISA_DMA_THRESHOLD       (0xffffffff)
-
-#endif                          /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/include/asm-blackfin/sections.h b/include/asm-blackfin/sections.h
deleted file mode 100644
index 1443c3353a8c..000000000000
--- a/include/asm-blackfin/sections.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _BLACKFIN_SECTIONS_H
-#define _BLACKFIN_SECTIONS_H
-
-/* nothing to see, move along */
-#include <asm-generic/sections.h>
-
-#endif
diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
deleted file mode 100644
index 02cfd09b5a99..000000000000
--- a/include/asm-blackfin/segment.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef _BFIN_SEGMENT_H
-#define _BFIN_SEGMENT_H
-
-#define KERNEL_DS   (0x5)
-#define USER_DS     (0x1)
-
-#endif                          /* _BFIN_SEGMENT_H */
diff --git a/include/asm-blackfin/sembuf.h b/include/asm-blackfin/sembuf.h
deleted file mode 100644
index 18deb5c7fa5d..000000000000
--- a/include/asm-blackfin/sembuf.h
+++ /dev/null
@@ -1,25 +0,0 @@
-#ifndef _BFIN_SEMBUF_H
-#define _BFIN_SEMBUF_H
-
-/*
- * The semid64_ds structure for bfin architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;      /* last semop time */
-        unsigned long __unused1;
-        __kernel_time_t sem_ctime;      /* last change time */
-        unsigned long __unused2;
-        unsigned long sem_nsems;        /* no. of semaphores in array */
-        unsigned long __unused3;
-        unsigned long __unused4;
-};
-
-#endif                          /* _BFIN_SEMBUF_H */
diff --git a/include/asm-blackfin/serial.h b/include/asm-blackfin/serial.h
deleted file mode 100644
index 994dd869558c..000000000000
--- a/include/asm-blackfin/serial.h
+++ /dev/null
@@ -1,5 +0,0 @@
-/*
- * include/asm-blackfin/serial.h
- */
-
-#define SERIAL_EXTRA_IRQ_FLAGS IRQF_TRIGGER_HIGH
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
deleted file mode 100644
index 01c8c6cbe6fc..000000000000
--- a/include/asm-blackfin/setup.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
-** asm/setup.h -- Definition of the Linux/bfin setup information
-**
-** This file is subject to the terms and conditions of the GNU General Public
-** License.  See the file COPYING in the main directory of this archive
-** for more details.
-**
-** Copyright Lineo, Inc 2001          Tony Kou
-**
-*/
-
-#ifndef _BFIN_SETUP_H
-#define _BFIN_SETUP_H
-
-#define COMMAND_LINE_SIZE       512
-
-#endif                          /* _BFIN_SETUP_H */
diff --git a/include/asm-blackfin/shmbuf.h b/include/asm-blackfin/shmbuf.h
deleted file mode 100644
index 612436303e89..000000000000
--- a/include/asm-blackfin/shmbuf.h
+++ /dev/null
@@ -1,42 +0,0 @@
-#ifndef _BFIN_SHMBUF_H
-#define _BFIN_SHMBUF_H
-
-/*
- * The shmid64_ds structure for bfin architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 64-bit time_t to solve y2038 problem
- * - 2 miscellaneous 32-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm shm_perm;     /* operation perms */
-        size_t shm_segsz;       /* size of segment (bytes) */
-        __kernel_time_t shm_atime;      /* last attach time */
-        unsigned long __unused1;
-        __kernel_time_t shm_dtime;      /* last detach time */
-        unsigned long __unused2;
-        __kernel_time_t shm_ctime;      /* last change time */
-        unsigned long __unused3;
-        __kernel_pid_t shm_cpid;        /* pid of creator */
-        __kernel_pid_t shm_lpid;        /* pid of last operator */
-        unsigned long shm_nattch;       /* no. of current attaches */
-        unsigned long __unused4;
-        unsigned long __unused5;
-};
-
-struct shminfo64 {
-        unsigned long shmmax;
-        unsigned long shmmin;
-        unsigned long shmmni;
-        unsigned long shmseg;
-        unsigned long shmall;
-        unsigned long __unused1;
-        unsigned long __unused2;
-        unsigned long __unused3;
-        unsigned long __unused4;
-};
-
-#endif                          /* _BFIN_SHMBUF_H */
diff --git a/include/asm-blackfin/shmparam.h b/include/asm-blackfin/shmparam.h
deleted file mode 100644
index 3c03906b7664..000000000000
--- a/include/asm-blackfin/shmparam.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_SHMPARAM_H
-#define _BFIN_SHMPARAM_H
-
-#define SHMLBA PAGE_SIZE        /* attach addr a multiple of this */
-
-#endif                          /* _BFIN_SHMPARAM_H */
diff --git a/include/asm-blackfin/sigcontext.h b/include/asm-blackfin/sigcontext.h
deleted file mode 100644
index ce00b03c2775..000000000000
--- a/include/asm-blackfin/sigcontext.h
+++ /dev/null
@@ -1,55 +0,0 @@
-#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
-#define _ASM_BLACKFIN_SIGCONTEXT_H
-
-/* Add new entries at the end of the structure only.  */
-struct sigcontext {
-        unsigned long sc_r0;
-        unsigned long sc_r1;
-        unsigned long sc_r2;
-        unsigned long sc_r3;
-        unsigned long sc_r4;
-        unsigned long sc_r5;
-        unsigned long sc_r6;
-        unsigned long sc_r7;
-        unsigned long sc_p0;
-        unsigned long sc_p1;
-        unsigned long sc_p2;
-        unsigned long sc_p3;
-        unsigned long sc_p4;
-        unsigned long sc_p5;
-        unsigned long sc_usp;
-        unsigned long sc_a0w;
-        unsigned long sc_a1w;
-        unsigned long sc_a0x;
-        unsigned long sc_a1x;
-        unsigned long sc_astat;
-        unsigned long sc_rets;
-        unsigned long sc_pc;
-        unsigned long sc_retx;
-        unsigned long sc_fp;
-        unsigned long sc_i0;
-        unsigned long sc_i1;
-        unsigned long sc_i2;
-        unsigned long sc_i3;
-        unsigned long sc_m0;
-        unsigned long sc_m1;
-        unsigned long sc_m2;
-        unsigned long sc_m3;
-        unsigned long sc_l0;
-        unsigned long sc_l1;
-        unsigned long sc_l2;
-        unsigned long sc_l3;
-        unsigned long sc_b0;
-        unsigned long sc_b1;
-        unsigned long sc_b2;
-        unsigned long sc_b3;
-        unsigned long sc_lc0;
-        unsigned long sc_lc1;
-        unsigned long sc_lt0;
-        unsigned long sc_lt1;
-        unsigned long sc_lb0;
-        unsigned long sc_lb1;
-        unsigned long sc_seqstat;
-};
-
-#endif
diff --git a/include/asm-blackfin/siginfo.h b/include/asm-blackfin/siginfo.h
deleted file mode 100644
index eca4565cea37..000000000000
--- a/include/asm-blackfin/siginfo.h
+++ /dev/null
@@ -1,35 +0,0 @@
-#ifndef _BFIN_SIGINFO_H
-#define _BFIN_SIGINFO_H
-
-#include <linux/types.h>
-#include <asm-generic/siginfo.h>
-
-#define UID16_SIGINFO_COMPAT_NEEDED
-
-#define si_uid16        _sifields._kill._uid
-
-#define ILL_ILLPARAOP   (__SI_FAULT|2)  /* illegal opcode combine ********** */
-#define ILL_ILLEXCPT    (__SI_FAULT|4)  /* unrecoverable exception ********** */
-#define ILL_CPLB_VI     (__SI_FAULT|9)  /* D/I CPLB protect violation ******** */
-#define ILL_CPLB_MISS   (__SI_FAULT|10) /* D/I CPLB miss ******** */
-#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */
-
-/*
- * SIGBUS si_codes
- */
-#define BUS_OPFETCH     (__SI_FAULT|4)  /* error from instruction fetch ******** */
-
-/*
- * SIGTRAP si_codes
- */
-#define TRAP_STEP       (__SI_FAULT|1)  /* single-step breakpoint************* */
-#define TRAP_TRACEFLOW  (__SI_FAULT|2)  /* trace buffer overflow ************* */
-#define TRAP_WATCHPT    (__SI_FAULT|3)  /* watchpoint match      ************* */
-#define TRAP_ILLTRAP    (__SI_FAULT|4)  /* illegal trap          ************* */
-
-/*
- * SIGSEGV si_codes
- */
-#define SEGV_STACKFLOW  (__SI_FAULT|3)  /* stack overflow */
-
-#endif
diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h
deleted file mode 100644
index 87951d251458..000000000000
--- a/include/asm-blackfin/signal.h
+++ /dev/null
@@ -1,160 +0,0 @@
-#ifndef _BLACKFIN_SIGNAL_H
-#define _BLACKFIN_SIGNAL_H
-
-#include <linux/types.h>
-
-/* Avoid too many header ordering problems.  */
-struct siginfo;
-
-#ifdef __KERNEL__
-/* Most things should be clean enough to redefine this at will, if care
-   is taken to make libc match.  */
-
-#define _NSIG           64
-#define _NSIG_BPW       32
-#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
-
-typedef unsigned long old_sigset_t;     /* at least 32 bits */
-
-typedef struct {
-        unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-#define NSIG            32
-typedef unsigned long sigset_t;
-
-#endif                          /* __KERNEL__ */
-
-#define SIGHUP           1
-#define SIGINT           2
-#define SIGQUIT          3
-#define SIGILL           4
-#define SIGTRAP          5
-#define SIGABRT          6
-#define SIGIOT           6
-#define SIGBUS           7
-#define SIGFPE           8
-#define SIGKILL          9
-#define SIGUSR1         10
-#define SIGSEGV         11
-#define SIGUSR2         12
-#define SIGPIPE         13
-#define SIGALRM         14
-#define SIGTERM         15
-#define SIGSTKFLT       16
-#define SIGCHLD         17
-#define SIGCONT         18
-#define SIGSTOP         19
-#define SIGTSTP         20
-#define SIGTTIN         21
-#define SIGTTOU         22
-#define SIGURG          23
-#define SIGXCPU         24
-#define SIGXFSZ         25
-#define SIGVTALRM       26
-#define SIGPROF         27
-#define SIGWINCH        28
-#define SIGIO           29
-#define SIGPOLL         SIGIO
-/*
-#define SIGLOST         29
-*/
-#define SIGPWR          30
-#define SIGSYS          31
-#define SIGUNUSED       31
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_NOCLDSTOP    0x00000001
-#define SA_NOCLDWAIT    0x00000002      /* not supported yet */
-#define SA_SIGINFO      0x00000004
-#define SA_ONSTACK      0x08000000
-#define SA_RESTART      0x10000000
-#define SA_NODEFER      0x40000000
-#define SA_RESETHAND    0x80000000
-
-#define SA_NOMASK       SA_NODEFER
-#define SA_ONESHOT      SA_RESETHAND
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK      1
-#define SS_DISABLE      2
-
-#define MINSIGSTKSZ     2048
-#define SIGSTKSZ        8192
-
-#include <asm-generic/signal.h>
-
-#ifdef __KERNEL__
-struct old_sigaction {
-        __sighandler_t sa_handler;
-        old_sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer) (void);
-};
-
-struct sigaction {
-        __sighandler_t sa_handler;
-        unsigned long sa_flags;
-        void (*sa_restorer) (void);
-        sigset_t sa_mask;       /* mask last for extensibility */
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-};
-#else
-/* Here we must cater to libcs that poke about in kernel headers.  */
-
-struct sigaction {
-        union {
-                __sighandler_t _sa_handler;
-                void (*_sa_sigaction) (int, struct siginfo *, void *);
-        } _u;
-        sigset_t sa_mask;
-        unsigned long sa_flags;
-        void (*sa_restorer) (void);
-};
-
-#define sa_handler      _u._sa_handler
-#define sa_sigaction    _u._sa_sigaction
-
-#endif                          /* __KERNEL__ */
-
-typedef struct sigaltstack {
-        void __user *ss_sp;
-        int ss_flags;
-        size_t ss_size;
-} stack_t;
-
-#ifdef __KERNEL__
-
-#include <asm/sigcontext.h>
-#undef __HAVE_ARCH_SIG_BITOPS
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BLACKFIN_SIGNAL_H */
diff --git a/include/asm-blackfin/socket.h b/include/asm-blackfin/socket.h
deleted file mode 100644
index 2ca702e44d47..000000000000
--- a/include/asm-blackfin/socket.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/* For setsockoptions(2) */
-#define SOL_SOCKET      1
-
-#define SO_DEBUG        1
-#define SO_REUSEADDR    2
-#define SO_TYPE         3
-#define SO_ERROR        4
-#define SO_DONTROUTE    5
-#define SO_BROADCAST    6
-#define SO_SNDBUF       7
-#define SO_RCVBUF       8
-#define SO_SNDBUFFORCE  32
-#define SO_RCVBUFFORCE  33
-#define SO_KEEPALIVE    9
-#define SO_OOBINLINE    10
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_LINGER       13
-#define SO_BSDCOMPAT    14
-/* To add :#define SO_REUSEPORT 15 */
-#define SO_PASSCRED     16
-#define SO_PEERCRED     17
-#define SO_RCVLOWAT     18
-#define SO_SNDLOWAT     19
-#define SO_RCVTIMEO     20
-#define SO_SNDTIMEO     21
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-
-#define SO_BINDTODEVICE 25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_ACCEPTCONN           30
-#define SO_PEERSEC              31
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-#define SO_MARK                 36
-
-#endif                          /* _ASM_SOCKET_H */
diff --git a/include/asm-blackfin/sockios.h b/include/asm-blackfin/sockios.h
deleted file mode 100644
index 426b89bfaa8b..000000000000
--- a/include/asm-blackfin/sockios.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ARCH_BFIN_SOCKIOS__
-#define __ARCH_BFIN_SOCKIOS__
-
-/* Socket-level I/O control calls. */
-#define FIOSETOWN       0x8901
-#define SIOCSPGRP       0x8902
-#define FIOGETOWN       0x8903
-#define SIOCGPGRP       0x8904
-#define SIOCATMARK      0x8905
-#define SIOCGSTAMP      0x8906  /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907  /* Get stamp (timespec) */
-
-#endif                          /* __ARCH_BFIN_SOCKIOS__ */
diff --git a/include/asm-blackfin/spinlock.h b/include/asm-blackfin/spinlock.h
deleted file mode 100644
index 64e908a50646..000000000000
--- a/include/asm-blackfin/spinlock.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __BFIN_SPINLOCK_H
-#define __BFIN_SPINLOCK_H
-
-#error blackfin architecture does not support SMP spin lock yet
-
-#endif
diff --git a/include/asm-blackfin/stat.h b/include/asm-blackfin/stat.h
deleted file mode 100644
index d2b6f11ec231..000000000000
--- a/include/asm-blackfin/stat.h
+++ /dev/null
@@ -1,63 +0,0 @@
-#ifndef _BFIN_STAT_H
-#define _BFIN_STAT_H
-
-struct stat {
-        unsigned short st_dev;
-        unsigned short __pad1;
-        unsigned long st_ino;
-        unsigned short st_mode;
-        unsigned short st_nlink;
-        unsigned short st_uid;
-        unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned short __pad2;
-        unsigned long st_size;
-        unsigned long st_blksize;
-        unsigned long st_blocks;
-        unsigned long st_atime;
-        unsigned long __unused1;
-        unsigned long st_mtime;
-        unsigned long __unused2;
-        unsigned long st_ctime;
-        unsigned long __unused3;
-        unsigned long __unused4;
-        unsigned long __unused5;
-};
-
-/* This matches struct stat64 in glibc2.1, hence the absolutely
- * insane amounts of padding around dev_t's.
- */
-struct stat64 {
-        unsigned long long st_dev;
-        unsigned char __pad1[4];
-
-#define STAT64_HAS_BROKEN_ST_INO        1
-        unsigned long __st_ino;
-
-        unsigned int st_mode;
-        unsigned int st_nlink;
-
-        unsigned long st_uid;
-        unsigned long st_gid;
-
-        unsigned long long st_rdev;
-        unsigned char __pad2[4];
-
-        long long st_size;
-        unsigned long st_blksize;
-
-        long long st_blocks;    /* Number 512-byte blocks allocated. */
-
-        unsigned long st_atime;
-        unsigned long st_atime_nsec;
-
-        unsigned long st_mtime;
-        unsigned long st_mtime_nsec;
-
-        unsigned long st_ctime;
-        unsigned long st_ctime_nsec;
-
-        unsigned long long st_ino;
-};
-
-#endif                          /* _BFIN_STAT_H */
diff --git a/include/asm-blackfin/statfs.h b/include/asm-blackfin/statfs.h
deleted file mode 100644
index 350672091ba3..000000000000
--- a/include/asm-blackfin/statfs.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _BFIN_STATFS_H
-#define _BFIN_STATFS_H
-
-#include <asm-generic/statfs.h>
-
-#endif                          /* _BFIN_STATFS_H */
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
deleted file mode 100644
index 321f4d96e4ae..000000000000
--- a/include/asm-blackfin/string.h
+++ /dev/null
@@ -1,137 +0,0 @@
-#ifndef _BLACKFIN_STRING_H_
-#define _BLACKFIN_STRING_H_
-
-#include <linux/types.h>
-
-#ifdef __KERNEL__               /* only set these up for kernel code */
-
-#define __HAVE_ARCH_STRCPY
-extern inline char *strcpy(char *dest, const char *src)
-{
-        char *xdest = dest;
-        char temp = 0;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%2 = B [%1++] (Z);"
-                "B [%0++] = %2;"
-                "CC = %2;"
-                "if cc jump 1b (bp);"
-                : "+&a" (dest), "+&a" (src), "=&d" (temp)
-                :
-                : "memory", "CC");
-
-        return xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-extern inline char *strncpy(char *dest, const char *src, size_t n)
-{
-        char *xdest = dest;
-        char temp = 0;
-
-        if (n == 0)
-                return xdest;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%3 = B [%1++] (Z);"
-                "B [%0++] = %3;"
-                "CC = %3;"
-                "if ! cc jump 2f;"
-                "%2 += -1;"
-                "CC = %2 == 0;"
-                "if ! cc jump 1b (bp);"
-                "jump 4f;"
-                "2:"
-                /* if src is shorter than n, we need to null pad bytes now */
-                "%3 = 0;"
-                "3:"
-                "%2 += -1;"
-                "CC = %2 == 0;"
-                "if cc jump 4f;"
-                "B [%0++] = %3;"
-                "jump 3b;"
-                "4:"
-                : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
-                :
-                : "memory", "CC");
-
-        return xdest;
-}
-
-#define __HAVE_ARCH_STRCMP
-extern inline int strcmp(const char *cs, const char *ct)
-{
-        /* need to use int's here so the char's in the assembly don't get
-         * sign extended incorrectly when we don't want them to be
-         */
-        int __res1, __res2;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%2 = B[%0++] (Z);"      /* get *cs */
-                "%3 = B[%1++] (Z);"      /* get *ct */
-                "CC = %2 == %3;"         /* compare a byte */
-                "if ! cc jump 2f;"       /* not equal, break out */
-                "CC = %2;"               /* at end of cs? */
-                "if cc jump 1b (bp);"    /* no, keep going */
-                "jump.s 3f;"             /* strings are equal */
-                "2:"
-                "%2 = %2 - %3;"          /* *cs - *ct */
-                "3:"
-                : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
-                :
-                : "memory", "CC");
-
-        return __res1;
-}
-
-#define __HAVE_ARCH_STRNCMP
-extern inline int strncmp(const char *cs, const char *ct, size_t count)
-{
-        /* need to use int's here so the char's in the assembly don't get
-         * sign extended incorrectly when we don't want them to be
-         */
-        int __res1, __res2;
-
-        if (!count)
-                return 0;
-
-        __asm__ __volatile__ (
-                "1:"
-                "%3 = B[%0++] (Z);"      /* get *cs */
-                "%4 = B[%1++] (Z);"      /* get *ct */
-                "CC = %3 == %4;"         /* compare a byte */
-                "if ! cc jump 3f;"       /* not equal, break out */
-                "CC = %3;"               /* at end of cs? */
-                "if ! cc jump 4f;"       /* yes, all done */
-                "%2 += -1;"              /* no, adjust count */
-                "CC = %2 == 0;"
-                "if ! cc jump 1b;"       /* more to do, keep going */
-                "2:"
-                "%3 = 0;"                /* strings are equal */
-                "jump.s 4f;"
-                "3:"
-                "%3 = %3 - %4;"          /* *cs - *ct */
-                "4:"
-                : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
-                :
-                : "memory", "CC");
-
-        return __res1;
-}
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *s, int c, size_t count);
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *d, const void *s, size_t count);
-#define __HAVE_ARCH_MEMCMP
-extern int memcmp(const void *, const void *, __kernel_size_t);
-#define __HAVE_ARCH_MEMCHR
-extern void *memchr(const void *s, int c, size_t n);
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *dest, const void *src, size_t count);
-
-#endif /*__KERNEL__*/
-#endif                          /* _BLACKFIN_STRING_H_ */
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
deleted file mode 100644
index 51494ef5bb41..000000000000
--- a/include/asm-blackfin/system.h
+++ /dev/null
@@ -1,221 +0,0 @@
-/*
- * File:        include/asm/system.h
- * Based on:
- * Author:      Tony Kou (tonyko@lineo.ca)
- *              Copyright (c) 2002 Arcturus Networks Inc.
- *                    (www.arcturusnetworks.com)
- *              Copyright (c) 2003 Metrowerks (www.metrowerks.com)
- *              Copyright (c) 2004 Analog Device Inc.
- * Created:     25Jan2001 - Tony Kou
- * Description: system.h include file
- *
- * Modified:     22Sep2006 - Robin Getz
- *                - move include blackfin.h down, so I can get access to
- *                   irq functions in other include files.
- *
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _BLACKFIN_SYSTEM_H
-#define _BLACKFIN_SYSTEM_H
-
-#include <linux/linkage.h>
-#include <linux/compiler.h>
-#include <asm/mach/anomaly.h>
-
-/*
- * Interrupt configuring macros.
- */
-
-extern unsigned long irq_flags;
-
-#define local_irq_enable() \
-        __asm__ __volatile__( \
-                "sti %0;" \
-                : \
-                : "d" (irq_flags) \
-        )
-
-#define local_irq_disable() \
-        do { \
-                int __tmp_dummy; \
-                __asm__ __volatile__( \
-                        "cli %0;" \
-                        : "=d" (__tmp_dummy) \
-                ); \
-        } while (0)
-
-#if ANOMALY_05000244 && defined(CONFIG_BFIN_ICACHE)
-# define NOP_PAD_ANOMALY_05000244 "nop; nop;"
-#else
-# define NOP_PAD_ANOMALY_05000244
-#endif
-
-#define idle_with_irq_disabled() \
-        __asm__ __volatile__( \
-                NOP_PAD_ANOMALY_05000244 \
-                ".align 8;" \
-                "sti %0;" \
-                "idle;" \
-                : \
-                : "d" (irq_flags) \
-        )
-
-#ifdef CONFIG_DEBUG_HWERR
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %1;" \
-                : "=&d" (x) \
-                : "d" (0x3F) \
-        )
-#else
-# define __save_and_cli(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                : "=&d" (x) \
-        )
-#endif
-
-#define local_save_flags(x) \
-        __asm__ __volatile__( \
-                "cli %0;" \
-                "sti %0;" \
-                : "=d" (x) \
-        )
-
-#ifdef CONFIG_DEBUG_HWERR
-#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
-#else
-#define irqs_enabled_from_flags(x) ((x) != 0x1f)
-#endif
-
-#define local_irq_restore(x) \
-        do { \
-                if (irqs_enabled_from_flags(x)) \
-                        local_irq_enable(); \
-        } while (0)
-
-/* For spinlocks etc */
-#define local_irq_save(x) __save_and_cli(x)
-
-#define irqs_disabled()                         \
-({                                              \
-        unsigned long flags;                    \
-        local_save_flags(flags);                \
-        !irqs_enabled_from_flags(flags);        \
-})
-
-/*
- * Force strict CPU ordering.
- */
-#define nop()  asm volatile ("nop;\n\t"::)
-#define mb()   asm volatile (""   : : :"memory")
-#define rmb()  asm volatile (""   : : :"memory")
-#define wmb()  asm volatile (""   : : :"memory")
-#define set_mb(var, value) do { (void) xchg(&var, value); } while (0)
-
-#define read_barrier_depends()          do { } while(0)
-
-#ifdef CONFIG_SMP
-#define smp_mb()        mb()
-#define smp_rmb()       rmb()
-#define smp_wmb()       wmb()
-#define smp_read_barrier_depends()      read_barrier_depends()
-#else
-#define smp_mb()        barrier()
-#define smp_rmb()       barrier()
-#define smp_wmb()       barrier()
-#define smp_read_barrier_depends()      do { } while(0)
-#endif
-
-#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-
-struct __xchg_dummy {
-        unsigned long a[100];
-};
-#define __xg(x) ((volatile struct __xchg_dummy *)(x))
-
-static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
-                                   int size)
-{
-        unsigned long tmp = 0;
-        unsigned long flags = 0;
-
-        local_irq_save(flags);
-
-        switch (size) {
-        case 1:
-                __asm__ __volatile__
-                        ("%0 = b%2 (z);\n\t"
-                         "b%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        case 2:
-                __asm__ __volatile__
-                        ("%0 = w%2 (z);\n\t"
-                         "w%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        case 4:
-                __asm__ __volatile__
-                        ("%0 = %2;\n\t"
-                         "%2 = %1;\n\t"
-                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
-                break;
-        }
-        local_irq_restore(flags);
-        return tmp;
-}
-
-#include <asm-generic/cmpxchg-local.h>
-
-/*
- * cmpxchg_local and cmpxchg64_local are atomic wrt current CPU. Always make
- * them available.
- */
-#define cmpxchg_local(ptr, o, n)                                               \
-        ((__typeof__(*(ptr)))__cmpxchg_local_generic((ptr), (unsigned long)(o),\
-                        (unsigned long)(n), sizeof(*(ptr))))
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-
-#ifndef CONFIG_SMP
-#include <asm-generic/cmpxchg.h>
-#endif
-
-#define prepare_to_switch()     do { } while(0)
-
-/*
- * switch_to(n) should switch tasks to task ptr, first checking that
- * ptr isn't the current task, in which case it does nothing.
- */
-
-#include <asm/blackfin.h>
-
-asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
-
-#define switch_to(prev,next,last) \
-do {    \
-        memcpy (&task_thread_info(prev)->l1_task_info, L1_SCRATCH_TASK_INFO, \
-                sizeof *L1_SCRATCH_TASK_INFO); \
-        memcpy (L1_SCRATCH_TASK_INFO, &task_thread_info(next)->l1_task_info, \
-                sizeof *L1_SCRATCH_TASK_INFO); \
-        (last) = resume (prev, next);   \
-} while (0)
-
-#endif                          /* _BLACKFIN_SYSTEM_H */
diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h
deleted file mode 100644
index f37feb7cf895..000000000000
--- a/include/asm-blackfin/termbits.h
+++ /dev/null
@@ -1,198 +0,0 @@
-#ifndef __ARCH_BFIN_TERMBITS_H__
-#define __ARCH_BFIN_TERMBITS_H__
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-#define NCCS 19
-struct termios {
-        tcflag_t c_iflag;       /* input mode flags */
-        tcflag_t c_oflag;       /* output mode flags */
-        tcflag_t c_cflag;       /* control mode flags */
-        tcflag_t c_lflag;       /* local mode flags */
-        cc_t c_line;            /* line discipline */
-        cc_t c_cc[NCCS];        /* control characters */
-};
-
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR 0
-#define VQUIT 1
-#define VERASE 2
-#define VKILL 3
-#define VEOF 4
-#define VTIME 5
-#define VMIN 6
-#define VSWTC 7
-#define VSTART 8
-#define VSTOP 9
-#define VSUSP 10
-#define VEOL 11
-#define VREPRINT 12
-#define VDISCARD 13
-#define VWERASE 14
-#define VLNEXT 15
-#define VEOL2 16
-
-/* c_iflag bits */
-#define IGNBRK  0000001
-#define BRKINT  0000002
-#define IGNPAR  0000004
-#define PARMRK  0000010
-#define INPCK   0000020
-#define ISTRIP  0000040
-#define INLCR   0000100
-#define IGNCR   0000200
-#define ICRNL   0000400
-#define IUCLC   0001000
-#define IXON    0002000
-#define IXANY   0004000
-#define IXOFF   0010000
-#define IMAXBEL 0020000
-#define IUTF8   0040000
-
-/* c_oflag bits */
-#define OPOST   0000001
-#define OLCUC   0000002
-#define ONLCR   0000004
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060
-#define   CS5   0000000
-#define   CS6   0000020
-#define   CS7   0000040
-#define   CS8   0000060
-#define CSTOPB  0000100
-#define CREAD   0000200
-#define PARENB  0000400
-#define PARODD  0001000
-#define HUPCL   0002000
-#define CLOCAL  0004000
-#define CBAUDEX 0010000
-#define BOTHER  0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate */
-#define CMSPAR    010000000000  /* mark or space (stick) parity */
-#define CRTSCTS   020000000000  /* flow control */
-
-#define IBSHIFT 16      /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG    0000001
-#define ICANON  0000002
-#define XCASE   0000004
-#define ECHO    0000010
-#define ECHOE   0000020
-#define ECHOK   0000040
-#define ECHONL  0000100
-#define NOFLSH  0000200
-#define TOSTOP  0000400
-#define ECHOCTL 0001000
-#define ECHOPRT 0002000
-#define ECHOKE  0004000
-#define FLUSHO  0010000
-#define PENDIN  0040000
-#define IEXTEN  0100000
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0
-#define TCOON           1
-#define TCIOFF          2
-#define TCION           3
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0
-#define TCOFLUSH        1
-#define TCIOFLUSH       2
-
-/* tcsetattr uses these */
-#define TCSANOW         0
-#define TCSADRAIN       1
-#define TCSAFLUSH       2
-
-#endif                          /* __ARCH_BFIN_TERMBITS_H__ */
diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h
deleted file mode 100644
index d50d063c605a..000000000000
--- a/include/asm-blackfin/termios.h
+++ /dev/null
@@ -1,94 +0,0 @@
-#ifndef __BFIN_TERMIOS_H__
-#define __BFIN_TERMIOS_H__
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC 8
-struct termio {
-        unsigned short c_iflag; /* input mode flags */
-        unsigned short c_oflag; /* output mode flags */
-        unsigned short c_cflag; /* control mode flags */
-        unsigned short c_lflag; /* local mode flags */
-        unsigned char c_line;   /* line discipline */
-        unsigned char c_cc[NCC];        /* control characters */
-};
-
-/* modem lines */
-#define TIOCM_LE        0x001
-#define TIOCM_DTR       0x002
-#define TIOCM_RTS       0x004
-#define TIOCM_ST        0x008
-#define TIOCM_SR        0x010
-#define TIOCM_CTS       0x020
-#define TIOCM_CAR       0x040
-#define TIOCM_RNG       0x080
-#define TIOCM_DSR       0x100
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-
-#ifdef __KERNEL__
-
-/*      intr=^C         quit=^\         erase=del       kill=^U
-        eof=^D          vtime=\0        vmin=\1         sxtc=\0
-        start=^Q        stop=^S         susp=^Z         eol=\0
-        reprint=^R      discard=^U      werase=^W       lnext=^V
-        eol2=\0
-*/
-#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
-        unsigned short __tmp; \
-        get_user(__tmp,&(termio)->x); \
-        *(unsigned short *) &(termios)->x = __tmp; \
-}
-
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
-        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line,  &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) \
-        copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) \
-        copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) \
-        copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) \
-        copy_to_user(u, k, sizeof(struct termios))
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* __BFIN_TERMIOS_H__ */
diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h
deleted file mode 100644
index 642769329d12..000000000000
--- a/include/asm-blackfin/thread_info.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * File:         include/asm-blackfin/thread_info.h
- * Based on:     include/asm-m68knommu/thread_info.h
- * Author:       LG Soft India
- *               Copyright (C) 2004-2005 Analog Devices Inc.
- * Created:      Tue Sep 21 2004
- * Description:  Blackfin low-level thread information
- * Modified:
- * Bugs:         Enter bugs at http://blackfin.uclinux.org/
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2, or (at your option)
- * any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; see the file COPYING.
- * If not, write to the Free Software Foundation,
- * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#include <asm/page.h>
-#include <asm/entry.h>
-#include <asm/l1layout.h>
-#include <linux/compiler.h>
-
-#ifdef __KERNEL__
-
-/* Thread Align Mask to reach to the top of the stack
- * for any process
- */
-#define ALIGN_PAGE_MASK         0xffffe000
-
-/*
- * Size of kernel stack for each process. This must be a power of 2...
- */
-#define THREAD_SIZE_ORDER       1
-#define THREAD_SIZE             8192    /* 2 pages */
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned long mm_segment_t;
-
-/*
- * low level task data.
- * If you change this, change the TI_* offsets below to match.
- */
-
-struct thread_info {
-        struct task_struct *task;       /* main task structure */
-        struct exec_domain *exec_domain;        /* execution domain */
-        unsigned long flags;    /* low level flags */
-        int cpu;                /* cpu we're on */
-        int preempt_count;      /* 0 => preemptable, <0 => BUG */
-        mm_segment_t addr_limit;        /* address limit */
-        struct restart_block restart_block;
-        struct l1_scratch_task_info l1_task_info;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- */
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task           = &tsk,                 \
-        .exec_domain    = &default_exec_domain, \
-        .flags          = 0,                    \
-        .cpu            = 0,                    \
-        .preempt_count  = 1,                    \
-        .restart_block  = {                     \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-/* Given a task stack pointer, you can find its corresponding
- * thread_info structure just by masking it to the THREAD_SIZE
- * boundary (currently 8K as you can see above).
- */
-__attribute_const__
-static inline struct thread_info *current_thread_info(void)
-{
-        struct thread_info *ti;
-      __asm__("%0 = sp;": "=&d"(ti):
-        );
-        return (struct thread_info *)((long)ti & ~((long)THREAD_SIZE-1));
-}
-
-#endif                          /* __ASSEMBLY__ */
-
-/*
- * Offsets in thread_info structure, used in assembly code
- */
-#define TI_TASK         0
-#define TI_EXECDOMAIN   4
-#define TI_FLAGS        8
-#define TI_CPU          12
-#define TI_PREEMPT      16
-
-#define PREEMPT_ACTIVE  0x4000000
-
-/*
- * thread information flag bit numbers
- */
-#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
-#define TIF_SIGPENDING          1       /* signal pending */
-#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
-#define TIF_POLLING_NRFLAG      3       /* true if poll_idle() is polling
-                                           TIF_NEED_RESCHED */
-#define TIF_MEMDIE              4
-#define TIF_RESTORE_SIGMASK     5       /* restore signal mask in do_signal() */
-#define TIF_FREEZE              6       /* is freezing for suspend */
-
-/* as above, but as bit values */
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
-
-#define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-blackfin/time.h b/include/asm-blackfin/time.h
deleted file mode 100644
index ddc43ce38533..000000000000
--- a/include/asm-blackfin/time.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * asm-blackfin/time.h:
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIME_H
-#define _ASM_BLACKFIN_TIME_H
-
-/*
- * The way that the Blackfin core timer works is:
- *  - CCLK is divided by a programmable 8-bit pre-scaler (TSCALE)
- *  - Every time TSCALE ticks, a 32bit is counted down (TCOUNT)
- *
- * If you take the fastest clock (1ns, or 1GHz to make the math work easier)
- *    10ms is 10,000,000 clock ticks, which fits easy into a 32-bit counter
- *    (32 bit counter is 4,294,967,296ns or 4.2 seconds) so, we don't need
- *    to use TSCALE, and program it to zero (which is pass CCLK through).
- *    If you feel like using it, try to keep HZ * TIMESCALE to some
- *    value that divides easy (like power of 2).
- */
-
-#ifndef CONFIG_CPU_FREQ
-#define TIME_SCALE 1
-#define __bfin_cycles_off (0)
-#define __bfin_cycles_mod (0)
-#else
-/*
- * Blackfin CPU frequency scaling supports max Core Clock 1, 1/2 and 1/4 .
- * Whenever we change the Core Clock frequency changes we immediately
- * adjust the Core Timer Presale Register. This way we don't lose time.
- */
-#define TIME_SCALE 4
-extern unsigned long long __bfin_cycles_off;
-extern unsigned int __bfin_cycles_mod;
-#endif
-
-#endif
diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h
deleted file mode 100644
index 22b0806161bb..000000000000
--- a/include/asm-blackfin/timex.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * asm-blackfin/timex.h: cpu cycles!
- *
- * Copyright 2004-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _ASM_BLACKFIN_TIMEX_H
-#define _ASM_BLACKFIN_TIMEX_H
-
-#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
-
-typedef unsigned long long cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
-        unsigned long tmp, tmp2;
-        __asm__("%0 = cycles; %1 = cycles2;" : "=d"(tmp), "=d"(tmp2));
-        return tmp | ((cycles_t)tmp2 << 32);
-}
-
-#endif
diff --git a/include/asm-blackfin/tlb.h b/include/asm-blackfin/tlb.h
deleted file mode 100644
index 89a12ee916d8..000000000000
--- a/include/asm-blackfin/tlb.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef _BLACKFIN_TLB_H
-#define _BLACKFIN_TLB_H
-
-#define tlb_start_vma(tlb, vma) do { } while (0)
-#define tlb_end_vma(tlb, vma)   do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address)      do { } while (0)
-
-/*
- * .. because we flush the whole mm when it
- * fills up.
- */
-#define tlb_flush(tlb)          flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif                          /* _BLACKFIN_TLB_H */
diff --git a/include/asm-blackfin/tlbflush.h b/include/asm-blackfin/tlbflush.h
deleted file mode 100644
index 277b400924b8..000000000000
--- a/include/asm-blackfin/tlbflush.h
+++ /dev/null
@@ -1,56 +0,0 @@
-#ifndef _BLACKFIN_TLBFLUSH_H
-#define _BLACKFIN_TLBFLUSH_H
-
-/*
- * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
- * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
- */
-
-#include <asm/setup.h>
-
-/*
- * flush all user-space atc entries.
- */
-static inline void __flush_tlb(void)
-{
-        BUG();
-}
-
-static inline void __flush_tlb_one(unsigned long addr)
-{
-        BUG();
-}
-
-#define flush_tlb() __flush_tlb()
-
-/*
- * flush all atc entries (both kernel and user-space entries).
- */
-static inline void flush_tlb_all(void)
-{
-        BUG();
-}
-
-static inline void flush_tlb_mm(struct mm_struct *mm)
-{
-        BUG();
-}
-
-static inline void flush_tlb_page(struct vm_area_struct *vma,
-                                  unsigned long addr)
-{
-        BUG();
-}
-
-static inline void flush_tlb_range(struct mm_struct *mm,
-                                   unsigned long start, unsigned long end)
-{
-        BUG();
-}
-
-static inline void flush_tlb_kernel_page(unsigned long addr)
-{
-        BUG();
-}
-
-#endif
diff --git a/include/asm-blackfin/topology.h b/include/asm-blackfin/topology.h
deleted file mode 100644
index acee23987897..000000000000
--- a/include/asm-blackfin/topology.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_BLACKFIN_TOPOLOGY_H
-#define _ASM_BLACKFIN_TOPOLOGY_H
-
-#include <asm-generic/topology.h>
-
-#endif                          /* _ASM_BLACKFIN_TOPOLOGY_H */
diff --git a/include/asm-blackfin/trace.h b/include/asm-blackfin/trace.h
deleted file mode 100644
index 312b596b9731..000000000000
--- a/include/asm-blackfin/trace.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Common header file for blackfin family of processors.
- *
- */
-
-#ifndef _BLACKFIN_TRACE_
-#define _BLACKFIN_TRACE_
-
-/* Normally, we use ON, but you can't turn on software expansion until
- * interrupts subsystem is ready
- */
-
-#define BFIN_TRACE_INIT ((CONFIG_DEBUG_BFIN_HWTRACE_COMPRESSION << 4) | 0x03)
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_EXPAND
-#define BFIN_TRACE_ON   (BFIN_TRACE_INIT | (CONFIG_DEBUG_BFIN_HWTRACE_EXPAND << 2))
-#else
-#define BFIN_TRACE_ON   (BFIN_TRACE_INIT)
-#endif
-
-#ifndef __ASSEMBLY__
-extern unsigned long trace_buff_offset;
-extern unsigned long software_trace_buff[];
-
-/* Trace Macros for C files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_save(x) \
-        do { \
-                (x) = bfin_read_TBUFCTL(); \
-                bfin_write_TBUFCTL((x) & ~TBUFEN); \
-        } while (0)
-
-#define trace_buffer_restore(x) \
-        do { \
-                bfin_write_TBUFCTL((x));        \
-        } while (0)
-#else /* DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_save(x)
-#define trace_buffer_restore(x)
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#else
-/* Trace Macros for Assembly files */
-
-#ifdef CONFIG_DEBUG_BFIN_HWTRACE_ON
-
-#define trace_buffer_stop(preg, dreg)   \
-        preg.L = LO(TBUFCTL);           \
-        preg.H = HI(TBUFCTL);           \
-        dreg = 0x1;                     \
-        [preg] = dreg;
-
-#define trace_buffer_init(preg, dreg) \
-        preg.L = LO(TBUFCTL);         \
-        preg.H = HI(TBUFCTL);         \
-        dreg = BFIN_TRACE_INIT;       \
-        [preg] = dreg;
-
-#define trace_buffer_save(preg, dreg) \
-        preg.L = LO(TBUFCTL); \
-        preg.H = HI(TBUFCTL); \
-        dreg = [preg]; \
-        [--sp] = dreg; \
-        dreg = 0x1; \
-        [preg] = dreg;
-
-#define trace_buffer_restore(preg, dreg) \
-        preg.L = LO(TBUFCTL); \
-        preg.H = HI(TBUFCTL); \
-        dreg = [sp++]; \
-        [preg] = dreg;
-
-#else /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#define trace_buffer_stop(preg, dreg)
-#define trace_buffer_init(preg, dreg)
-#define trace_buffer_save(preg, dreg)
-#define trace_buffer_restore(preg, dreg)
-
-#endif /* CONFIG_DEBUG_BFIN_HWTRACE_ON */
-
-#ifdef CONFIG_DEBUG_BFIN_NO_KERN_HWTRACE
-# define DEBUG_HWTRACE_SAVE(preg, dreg)    trace_buffer_save(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg) trace_buffer_restore(preg, dreg)
-#else
-# define DEBUG_HWTRACE_SAVE(preg, dreg)
-# define DEBUG_HWTRACE_RESTORE(preg, dreg)
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif                          /* _BLACKFIN_TRACE_ */
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
deleted file mode 100644
index f0e5f940d9ca..000000000000
--- a/include/asm-blackfin/traps.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- *  linux/include/asm/traps.h
- *
- *  Copyright (C) 1993        Hamish Macdonald
- *
- *  Lineo, Inc    Jul 2001    Tony Kou
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- */
-
-#ifndef _BFIN_TRAPS_H
-#define _BFIN_TRAPS_H
-
-#define VEC_SYS         (0)
-#define VEC_EXCPT01     (1)
-#define VEC_EXCPT02     (2)
-#define VEC_EXCPT03     (3)
-#define VEC_EXCPT04     (4)
-#define VEC_EXCPT05     (5)
-#define VEC_EXCPT06     (6)
-#define VEC_EXCPT07     (7)
-#define VEC_EXCPT08     (8)
-#define VEC_EXCPT09     (9)
-#define VEC_EXCPT10     (10)
-#define VEC_EXCPT11     (11)
-#define VEC_EXCPT12     (12)
-#define VEC_EXCPT13     (13)
-#define VEC_EXCPT14     (14)
-#define VEC_EXCPT15     (15)
-#define VEC_STEP        (16)
-#define VEC_OVFLOW      (17)
-#define VEC_UNDEF_I     (33)
-#define VEC_ILGAL_I     (34)
-#define VEC_CPLB_VL     (35)
-#define VEC_MISALI_D    (36)
-#define VEC_UNCOV       (37)
-#define VEC_CPLB_M      (38)
-#define VEC_CPLB_MHIT   (39)
-#define VEC_WATCH       (40)
-#define VEC_ISTRU_VL    (41)    /*ADSP-BF535 only (MH) */
-#define VEC_MISALI_I    (42)
-#define VEC_CPLB_I_VL   (43)
-#define VEC_CPLB_I_M    (44)
-#define VEC_CPLB_I_MHIT (45)
-#define VEC_ILL_RES     (46)    /* including unvalid supervisor mode insn */
-/* The hardware reserves (63) for future use - we use it to tell our
- * normal exception handling code we have a hardware error
- */
-#define VEC_HWERR       (63)
-
-#ifndef __ASSEMBLY__
-
-#define HWC_x2(level) \
-        "System MMR Error\n" \
-        level " - An error occurred due to an invalid access to an System MMR location\n" \
-        level "   Possible reason: a 32-bit register is accessed with a 16-bit instruction\n" \
-        level "   or a 16-bit register is accessed with a 32-bit instruction.\n"
-#define HWC_x3(level) \
-        "External Memory Addressing Error\n"
-#define HWC_x12(level) \
-        "Performance Monitor Overflow\n"
-#define HWC_x18(level) \
-        "RAISE 5 instruction\n" \
-        level "    Software issued a RAISE 5 instruction to invoke the Hardware\n"
-#define HWC_default(level) \
-         "Reserved\n"
-#define EXC_0x03(level) \
-        "Application stack overflow\n" \
-        level " - Please increase the stack size of the application using elf2flt -s option,\n" \
-        level "   and/or reduce the stack use of the application.\n"
-#define EXC_0x10(level) \
-        "Single step\n" \
-        level " - When the processor is in single step mode, every instruction\n" \
-        level "   generates an exception. Primarily used for debugging.\n"
-#define EXC_0x11(level) \
-        "Exception caused by a trace buffer full condition\n" \
-        level " - The processor takes this exception when the trace\n" \
-        level "   buffer overflows (only when enabled by the Trace Unit Control register).\n"
-#define EXC_0x21(level) \
-        "Undefined instruction\n" \
-        level " - May be used to emulate instructions that are not defined for\n" \
-        level "   a particular processor implementation.\n"
-#define EXC_0x22(level) \
-        "Illegal instruction combination\n" \
-        level " - See section for multi-issue rules in the ADSP-BF53x Blackfin\n" \
-        level "   Processor Instruction Set Reference.\n"
-#define EXC_0x23(level) \
-        "Data access CPLB protection violation\n" \
-        level " - Attempted read or write to Supervisor resource,\n" \
-        level "   or illegal data memory access. \n"
-#define EXC_0x24(level) \
-        "Data access misaligned address violation\n" \
-        level " - Attempted misaligned data memory or data cache access.\n"
-#define EXC_0x25(level) \
-        "Unrecoverable event\n" \
-        level " - For example, an exception generated while processing a previous exception.\n"
-#define EXC_0x26(level) \
-        "Data access CPLB miss\n" \
-        level " - Used by the MMU to signal a CPLB miss on a data access.\n"
-#define EXC_0x27(level) \
-        "Data access multiple CPLB hits\n" \
-        level " - More than one CPLB entry matches data fetch address.\n"
-#define EXC_0x28(level) \
-        "Program Sequencer Exception caused by an emulation watchpoint match\n" \
-        level " - There is a watchpoint match, and one of the EMUSW\n" \
-        level "   bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
-#define EXC_0x2A(level) \
-        "Instruction fetch misaligned address violation\n" \
-        level " - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch\n" \
-        level "   exception, the return address provided in RETX is the destination address which is\n" \
-        level "   misaligned, rather than the address of the offending instruction.\n"
-#define EXC_0x2B(level) \
-        "CPLB protection violation\n" \
-        level " - Illegal instruction fetch access (memory protection violation).\n"
-#define EXC_0x2C(level) \
-        "Instruction fetch CPLB miss\n" \
-        level " - CPLB miss on an instruction fetch.\n"
-#define EXC_0x2D(level) \
-        "Instruction fetch multiple CPLB hits\n" \
-        level " - More than one CPLB entry matches instruction fetch address.\n"
-#define EXC_0x2E(level) \
-        "Illegal use of supervisor resource\n" \
-        level " - Attempted to use a Supervisor register or instruction from User mode.\n" \
-        level "   Supervisor resources are registers and instructions that are reserved\n" \
-        level "   for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n" \
-        level "   only instructions.\n"
-
-#endif                          /* __ASSEMBLY__ */
-#endif                          /* _BFIN_TRAPS_H */
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
deleted file mode 100644
index 8441cbc2bf9e..000000000000
--- a/include/asm-blackfin/types.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _BFIN_TYPES_H
-#define _BFIN_TYPES_H
-
-/*
- * This file is never included by application software unless
- * explicitly requested (e.g., via linux/types.h) in which case the
- * application is Linux specific so (user-) name space pollution is
- * not a major issue.  However, for interoperability, libraries still
- * need to be careful to avoid a name clashes.
- */
-#include <asm-generic/int-ll64.h>
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif                          /* __ASSEMBLY__ */
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG 32
-
-#ifndef __ASSEMBLY__
-
-/* Dma addresses are 32-bits wide.  */
-
-typedef u32 dma_addr_t;
-typedef u64 dma64_addr_t;
-
-#endif                          /* __ASSEMBLY__ */
-
-#endif                          /* __KERNEL__ */
-
-#endif                          /* _BFIN_TYPES_H */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
deleted file mode 100644
index d928b8099056..000000000000
--- a/include/asm-blackfin/uaccess.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/* Changes made by Lineo Inc.    May 2001
- *
- * Based on: include/asm-m68knommu/uaccess.h
- */
-
-#ifndef __BLACKFIN_UACCESS_H
-#define __BLACKFIN_UACCESS_H
-
-/*
- * User space memory access functions
- */
-#include <linux/sched.h>
-#include <linux/mm.h>
-#include <linux/string.h>
-
-#include <asm/segment.h>
-#ifdef CONFIG_ACCESS_CHECK
-# include <asm/bfin-global.h>
-#endif
-
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current_thread_info()->addr_limit)
-
-static inline void set_fs(mm_segment_t fs)
-{
-        current_thread_info()->addr_limit = fs;
-}
-
-#define segment_eq(a,b) ((a) == (b))
-
-#define VERIFY_READ     0
-#define VERIFY_WRITE    1
-
-#define access_ok(type, addr, size) _access_ok((unsigned long)(addr), (size))
-
-static inline int is_in_rom(unsigned long addr)
-{
-        /*
-         * What we are really trying to do is determine if addr is
-         * in an allocated kernel memory region. If not then assume
-         * we cannot free it or otherwise de-allocate it. Ideally
-         * we could restrict this to really being in a ROM or flash,
-         * but that would need to be done on a board by board basis,
-         * not globally.
-         */
-        if ((addr < _ramstart) || (addr >= _ramend))
-                return (1);
-
-        /* Default case, not in ROM */
-        return (0);
-}
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- */
-
-#ifndef CONFIG_ACCESS_CHECK
-static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
-#else
-#ifdef CONFIG_ACCESS_OK_L1
-extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
-#else
-extern int _access_ok(unsigned long addr, unsigned long size);
-#endif
-#endif
-
-/*
- * The exception table consists of pairs of addresses: the first is the
- * address of an instruction that is allowed to fault, and the second is
- * the address at which the program should continue.  No registers are
- * modified, so it is entirely up to the continuation code to figure out
- * what to do.
- *
- * All the routines below use bits of fixup code that are out of line
- * with the main instruction path.  This means when everything is well,
- * we don't even have to jump over them.  Further, they do not intrude
- * on our cache or tlb entries.
- */
-
-struct exception_table_entry {
-        unsigned long insn, fixup;
-};
-
-/* Returns 0 if exception not found and fixup otherwise.  */
-extern unsigned long search_exception_table(unsigned long);
-
-/*
- * These are the main single-value transfer routines.  They automatically
- * use the right size if we just have the right pointer type.
- */
-
-#define put_user(x,p)                                           \
-        ({                                                      \
-                int _err = 0;                                   \
-                typeof(*(p)) _x = (x);                          \
-                typeof(*(p)) *_p = (p);                         \
-                if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
-                        _err = -EFAULT;                         \
-                }                                               \
-                else {                                          \
-                switch (sizeof (*(_p))) {                       \
-                case 1:                                         \
-                        __put_user_asm(_x, _p, B);              \
-                        break;                                  \
-                case 2:                                         \
-                        __put_user_asm(_x, _p, W);              \
-                        break;                                  \
-                case 4:                                         \
-                        __put_user_asm(_x, _p,  );              \
-                        break;                                  \
-                case 8: {                                       \
-                        long _xl, _xh;                          \
-                        _xl = ((long *)&_x)[0];                 \
-                        _xh = ((long *)&_x)[1];                 \
-                        __put_user_asm(_xl, ((long *)_p)+0, );  \
-                        __put_user_asm(_xh, ((long *)_p)+1, );  \
-                } break;                                        \
-                default:                                        \
-                        _err = __put_user_bad();                \
-                        break;                                  \
-                }                                               \
-                }                                               \
-                _err;                                           \
-        })
-
-#define __put_user(x,p) put_user(x,p)
-static inline int bad_user_access_length(void)
-{
-        panic("bad_user_access_length");
-        return -1;
-}
-
-#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
-                           __FILE__, __LINE__, __func__),\
-                           bad_user_access_length(), (-EFAULT))
-
-/*
- * Tell gcc we read from memory instead of writing: this is because
- * we do not write to any memory gcc knows about, so there are no
- * aliasing issues.
- */
-
-#define __ptr(x) ((unsigned long *)(x))
-
-#define __put_user_asm(x,p,bhw)                         \
-        __asm__ (#bhw"[%1] = %0;\n\t"                   \
-                 : /* no outputs */                     \
-                 :"d" (x),"a" (__ptr(p)) : "memory")
-
-#define get_user(x,p)                                                   \
-        ({                                                              \
-                int _err = 0;                                           \
-                typeof(*(p)) *_p = (p);                                 \
-                if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) {       \
-                        _err = -EFAULT;                                 \
-                }                                                       \
-                else {                                                  \
-                switch (sizeof(*(_p))) {                                \
-                case 1:                                                 \
-                        __get_user_asm(x, _p, B,(Z));                   \
-                        break;                                          \
-                case 2:                                                 \
-                        __get_user_asm(x, _p, W,(Z));                   \
-                        break;                                          \
-                case 4:                                                 \
-                        __get_user_asm(x, _p,  , );                     \
-                        break;                                          \
-                case 8: {                                               \
-                        unsigned long _xl, _xh;                         \
-                        __get_user_asm(_xl, ((unsigned long *)_p)+0,  , ); \
-                        __get_user_asm(_xh, ((unsigned long *)_p)+1,  , ); \
-                        ((unsigned long *)&x)[0] = _xl;                 \
-                        ((unsigned long *)&x)[1] = _xh;                 \
-                } break;                                                \
-                default:                                                \
-                        x = 0;                                          \
-                        printk(KERN_INFO "get_user_bad: %s:%d %s\n",    \
-                               __FILE__, __LINE__, __func__);   \
-                        _err = __get_user_bad();                        \
-                        break;                                          \
-                }                                                       \
-                }                                                       \
-                _err;                                                   \
-        })
-
-#define __get_user(x,p) get_user(x,p)
-
-#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
-
-#define __get_user_asm(x,p,bhw,option)                          \
-        {                                                       \
-                unsigned long _tmp;                             \
-                __asm__ ("%0 =" #bhw "[%1]"#option";\n\t"       \
-                         : "=d" (_tmp)                          \
-                         : "a" (__ptr(p)));                     \
-                (x) = (__typeof__(*(p))) _tmp;                  \
-        }
-
-#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
-#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
-#define __copy_to_user_inatomic __copy_to_user
-#define __copy_from_user_inatomic __copy_from_user
-
-#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n))\
-                                                 return retval; })
-
-#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
-                                                   return retval; })
-
-static inline long copy_from_user(void *to,
-                                  const void __user * from, unsigned long n)
-{
-        if (access_ok(VERIFY_READ, from, n))
-                memcpy(to, from, n);
-        else
-                return n;
-        return 0;
-}
-
-static inline long copy_to_user(void *to,
-                                const void __user * from, unsigned long n)
-{
-        if (access_ok(VERIFY_WRITE, to, n))
-                memcpy(to, from, n);
-        else
-                return n;
-        return 0;
-}
-
-/*
- * Copy a null terminated string from userspace.
- */
-
-static inline long strncpy_from_user(char *dst,
-                                     const char *src, long count)
-{
-        char *tmp;
-        if (!access_ok(VERIFY_READ, src, 1))
-                return -EFAULT;
-        strncpy(dst, src, count);
-        for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
-        return (tmp - dst);
-}
-
-/*
- * Return the size of a string (including the ending 0)
- *
- * Return 0 on exception, a value greater than N if too long
- */
-static inline long strnlen_user(const char *src, long n)
-{
-        return (strlen(src) + 1);
-}
-
-#define strlen_user(str) strnlen_user(str, 32767)
-
-/*
- * Zero Userspace
- */
-
-static inline unsigned long __clear_user(void *to, unsigned long n)
-{
-        memset(to, 0, n);
-        return 0;
-}
-
-#define clear_user(to, n) __clear_user(to, n)
-
-#endif                          /* _BLACKFIN_UACCESS_H */
diff --git a/include/asm-blackfin/ucontext.h b/include/asm-blackfin/ucontext.h
deleted file mode 100644
index 4a4e3856beba..000000000000
--- a/include/asm-blackfin/ucontext.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/** Changes made by Tony Kou   Lineo Inc.    May 2001
- *
- *  Based on: include/m68knommu/ucontext.h
- */
-
-#ifndef _BLACKFIN_UCONTEXT_H
-#define _BLACKFIN_UCONTEXT_H
-
-struct ucontext {
-        unsigned long uc_flags; /* the others are necessary */
-        struct ucontext *uc_link;
-        stack_t uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t uc_sigmask;    /* mask last for extensibility */
-};
-
-#endif                          /* _BLACKFIN_UCONTEXT_H */
diff --git a/include/asm-blackfin/unaligned.h b/include/asm-blackfin/unaligned.h
deleted file mode 100644
index fd8a1d634945..000000000000
--- a/include/asm-blackfin/unaligned.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef _ASM_BLACKFIN_UNALIGNED_H
-#define _ASM_BLACKFIN_UNALIGNED_H
-
-#include <linux/unaligned/le_struct.h>
-#include <linux/unaligned/be_byteshift.h>
-#include <linux/unaligned/generic.h>
-
-#define get_unaligned   __get_unaligned_le
-#define put_unaligned   __put_unaligned_le
-
-#endif /* _ASM_BLACKFIN_UNALIGNED_H */
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
deleted file mode 100644
index 1e57b636e0bc..000000000000
--- a/include/asm-blackfin/unistd.h
+++ /dev/null
@@ -1,438 +0,0 @@
-#ifndef __ASM_BFIN_UNISTD_H
-#define __ASM_BFIN_UNISTD_H
-/*
- * This file contains the system call numbers.
- */
-#define __NR_restart_syscall      0
-#define __NR_exit                 1
-#define __NR_fork                 2
-#define __NR_read                 3
-#define __NR_write                4
-#define __NR_open                 5
-#define __NR_close                6
-                                /* 7 __NR_waitpid obsolete */
-#define __NR_creat                8
-#define __NR_link                 9
-#define __NR_unlink              10
-#define __NR_execve              11
-#define __NR_chdir               12
-#define __NR_time                13
-#define __NR_mknod               14
-#define __NR_chmod               15
-#define __NR_chown               16
-                                /* 17 __NR_break obsolete */
-                                /* 18 __NR_oldstat obsolete */
-#define __NR_lseek               19
-#define __NR_getpid              20
-#define __NR_mount               21
-                                /* 22 __NR_umount obsolete */
-#define __NR_setuid              23
-#define __NR_getuid              24
-#define __NR_stime               25
-#define __NR_ptrace              26
-#define __NR_alarm               27
-                                /* 28 __NR_oldfstat obsolete */
-#define __NR_pause               29
-                                /* 30 __NR_utime obsolete */
-                                /* 31 __NR_stty obsolete */
-                                /* 32 __NR_gtty obsolete */
-#define __NR_access              33
-#define __NR_nice                34
-                                /* 35 __NR_ftime obsolete */
-#define __NR_sync                36
-#define __NR_kill                37
-#define __NR_rename              38
-#define __NR_mkdir               39
-#define __NR_rmdir               40
-#define __NR_dup                 41
-#define __NR_pipe                42
-#define __NR_times               43
-                                /* 44 __NR_prof obsolete */
-#define __NR_brk                 45
-#define __NR_setgid              46
-#define __NR_getgid              47
-                                /* 48 __NR_signal obsolete */
-#define __NR_geteuid             49
-#define __NR_getegid             50
-#define __NR_acct                51
-#define __NR_umount2             52
-                                /* 53 __NR_lock obsolete */
-#define __NR_ioctl               54
-#define __NR_fcntl               55
-                                /* 56 __NR_mpx obsolete */
-#define __NR_setpgid             57
-                                /* 58 __NR_ulimit obsolete */
-                                /* 59 __NR_oldolduname obsolete */
-#define __NR_umask               60
-#define __NR_chroot              61
-#define __NR_ustat               62
-#define __NR_dup2                63
-#define __NR_getppid             64
-#define __NR_getpgrp             65
-#define __NR_setsid              66
-                                /* 67 __NR_sigaction obsolete */
-#define __NR_sgetmask            68
-#define __NR_ssetmask            69
-#define __NR_setreuid            70
-#define __NR_setregid            71
-                                /* 72 __NR_sigsuspend obsolete */
-                                /* 73 __NR_sigpending obsolete */
-#define __NR_sethostname         74
-#define __NR_setrlimit           75
-                                /* 76 __NR_old_getrlimit obsolete */
-#define __NR_getrusage           77
-#define __NR_gettimeofday        78
-#define __NR_settimeofday        79
-#define __NR_getgroups           80
-#define __NR_setgroups           81
-                                /* 82 __NR_select obsolete */
-#define __NR_symlink             83
-                                /* 84 __NR_oldlstat obsolete */
-#define __NR_readlink            85
-                                /* 86 __NR_uselib obsolete */
-                                /* 87 __NR_swapon obsolete */
-#define __NR_reboot              88
-                                /* 89 __NR_readdir obsolete */
-                                /* 90 __NR_mmap obsolete */
-#define __NR_munmap              91
-#define __NR_truncate            92
-#define __NR_ftruncate           93
-#define __NR_fchmod              94
-#define __NR_fchown              95
-#define __NR_getpriority         96
-#define __NR_setpriority         97
-                                /* 98 __NR_profil obsolete */
-#define __NR_statfs              99
-#define __NR_fstatfs            100
-                                /* 101 __NR_ioperm */
-                                /* 102 __NR_socketcall obsolete */
-#define __NR_syslog             103
-#define __NR_setitimer          104
-#define __NR_getitimer          105
-#define __NR_stat               106
-#define __NR_lstat              107
-#define __NR_fstat              108
-                                /* 109 __NR_olduname obsolete */
-                                /* 110 __NR_iopl obsolete */
-#define __NR_vhangup            111
-                                /* 112 __NR_idle obsolete */
-                                /* 113 __NR_vm86old */
-#define __NR_wait4              114
-                                /* 115 __NR_swapoff obsolete */
-#define __NR_sysinfo            116
-                                /* 117 __NR_ipc oboslete */
-#define __NR_fsync              118
-                                /* 119 __NR_sigreturn obsolete */
-#define __NR_clone              120
-#define __NR_setdomainname      121
-#define __NR_uname              122
-                                /* 123 __NR_modify_ldt obsolete */
-#define __NR_adjtimex           124
-#define __NR_mprotect           125
-                                /* 126 __NR_sigprocmask obsolete */
-                                /* 127 __NR_create_module obsolete */
-#define __NR_init_module        128
-#define __NR_delete_module      129
-                                /* 130 __NR_get_kernel_syms obsolete */
-#define __NR_quotactl           131
-#define __NR_getpgid            132
-#define __NR_fchdir             133
-#define __NR_bdflush            134
-                                /* 135 was sysfs */
-#define __NR_personality        136
-                                /* 137 __NR_afs_syscall */
-#define __NR_setfsuid           138
-#define __NR_setfsgid           139
-#define __NR__llseek            140
-#define __NR_getdents           141
-                                /* 142 __NR__newselect obsolete */
-#define __NR_flock              143
-                                /* 144 __NR_msync obsolete */
-#define __NR_readv              145
-#define __NR_writev             146
-#define __NR_getsid             147
-#define __NR_fdatasync          148
-#define __NR__sysctl            149
-                                /* 150 __NR_mlock */
-                                /* 151 __NR_munlock */
-                                /* 152 __NR_mlockall */
-                                /* 153 __NR_munlockall */
-#define __NR_sched_setparam             154
-#define __NR_sched_getparam             155
-#define __NR_sched_setscheduler         156
-#define __NR_sched_getscheduler         157
-#define __NR_sched_yield                158
-#define __NR_sched_get_priority_max     159
-#define __NR_sched_get_priority_min     160
-#define __NR_sched_rr_get_interval      161
-#define __NR_nanosleep          162
-#define __NR_mremap             163
-#define __NR_setresuid          164
-#define __NR_getresuid          165
-                                /* 166 __NR_vm86 */
-                                /* 167 __NR_query_module */
-                                /* 168 __NR_poll */
-#define __NR_nfsservctl         169
-#define __NR_setresgid          170
-#define __NR_getresgid          171
-#define __NR_prctl              172
-#define __NR_rt_sigreturn       173
-#define __NR_rt_sigaction       174
-#define __NR_rt_sigprocmask     175
-#define __NR_rt_sigpending      176
-#define __NR_rt_sigtimedwait    177
-#define __NR_rt_sigqueueinfo    178
-#define __NR_rt_sigsuspend      179
-#define __NR_pread              180
-#define __NR_pwrite             181
-#define __NR_lchown             182
-#define __NR_getcwd             183
-#define __NR_capget             184
-#define __NR_capset             185
-#define __NR_sigaltstack        186
-#define __NR_sendfile           187
-                                /* 188 __NR_getpmsg */
-                                /* 189 __NR_putpmsg */
-#define __NR_vfork              190
-#define __NR_getrlimit          191
-#define __NR_mmap2              192
-#define __NR_truncate64         193
-#define __NR_ftruncate64        194
-#define __NR_stat64             195
-#define __NR_lstat64            196
-#define __NR_fstat64            197
-#define __NR_chown32            198
-#define __NR_getuid32           199
-#define __NR_getgid32           200
-#define __NR_geteuid32          201
-#define __NR_getegid32          202
-#define __NR_setreuid32         203
-#define __NR_setregid32         204
-#define __NR_getgroups32        205
-#define __NR_setgroups32        206
-#define __NR_fchown32           207
-#define __NR_setresuid32        208
-#define __NR_getresuid32        209
-#define __NR_setresgid32        210
-#define __NR_getresgid32        211
-#define __NR_lchown32           212
-#define __NR_setuid32           213
-#define __NR_setgid32           214
-#define __NR_setfsuid32         215
-#define __NR_setfsgid32         216
-#define __NR_pivot_root         217
-                                /* 218 __NR_mincore */
-                                /* 219 __NR_madvise */
-#define __NR_getdents64         220
-#define __NR_fcntl64            221
-                                /* 222 reserved for TUX */
-                                /* 223 reserved for TUX */
-#define __NR_gettid             224
-#define __NR_readahead          225
-#define __NR_setxattr           226
-#define __NR_lsetxattr          227
-#define __NR_fsetxattr          228
-#define __NR_getxattr           229
-#define __NR_lgetxattr          230
-#define __NR_fgetxattr          231
-#define __NR_listxattr          232
-#define __NR_llistxattr         233
-#define __NR_flistxattr         234
-#define __NR_removexattr        235
-#define __NR_lremovexattr       236
-#define __NR_fremovexattr       237
-#define __NR_tkill              238
-#define __NR_sendfile64         239
-#define __NR_futex              240
-#define __NR_sched_setaffinity  241
-#define __NR_sched_getaffinity  242
-                                /* 243 __NR_set_thread_area */
-                                /* 244 __NR_get_thread_area */
-#define __NR_io_setup           245
-#define __NR_io_destroy         246
-#define __NR_io_getevents       247
-#define __NR_io_submit          248
-#define __NR_io_cancel          249
-                                /* 250 __NR_alloc_hugepages */
-                                /* 251 __NR_free_hugepages */
-#define __NR_exit_group         252
-#define __NR_lookup_dcookie     253
-#define __NR_bfin_spinlock      254
-
-#define __NR_epoll_create       255
-#define __NR_epoll_ctl          256
-#define __NR_epoll_wait         257
-                                /* 258 __NR_remap_file_pages */
-#define __NR_set_tid_address    259
-#define __NR_timer_create       260
-#define __NR_timer_settime      261
-#define __NR_timer_gettime      262
-#define __NR_timer_getoverrun   263
-#define __NR_timer_delete       264
-#define __NR_clock_settime      265
-#define __NR_clock_gettime      266
-#define __NR_clock_getres       267
-#define __NR_clock_nanosleep    268
-#define __NR_statfs64           269
-#define __NR_fstatfs64          270
-#define __NR_tgkill             271
-#define __NR_utimes             272
-#define __NR_fadvise64_64       273
-                                /* 274 __NR_vserver */
-                                /* 275 __NR_mbind */
-                                /* 276 __NR_get_mempolicy */
-                                /* 277 __NR_set_mempolicy */
-#define __NR_mq_open            278
-#define __NR_mq_unlink          279
-#define __NR_mq_timedsend       280
-#define __NR_mq_timedreceive    281
-#define __NR_mq_notify          282
-#define __NR_mq_getsetattr      283
-#define __NR_kexec_load         284
-#define __NR_waitid             285
-#define __NR_add_key            286
-#define __NR_request_key        287
-#define __NR_keyctl             288
-#define __NR_ioprio_set         289
-#define __NR_ioprio_get         290
-#define __NR_inotify_init       291
-#define __NR_inotify_add_watch  292
-#define __NR_inotify_rm_watch   293
-                                /* 294 __NR_migrate_pages */
-#define __NR_openat             295
-#define __NR_mkdirat            296
-#define __NR_mknodat            297
-#define __NR_fchownat           298
-#define __NR_futimesat          299
-#define __NR_fstatat64          300
-#define __NR_unlinkat           301
-#define __NR_renameat           302
-#define __NR_linkat             303
-#define __NR_symlinkat          304
-#define __NR_readlinkat         305
-#define __NR_fchmodat           306
-#define __NR_faccessat          307
-#define __NR_pselect6           308
-#define __NR_ppoll              309
-#define __NR_unshare            310
-
-/* Blackfin private syscalls */
-#define __NR_sram_alloc         311
-#define __NR_sram_free          312
-#define __NR_dma_memcpy         313
-
-/* socket syscalls */
-#define __NR_accept             314
-#define __NR_bind               315
-#define __NR_connect            316
-#define __NR_getpeername        317
-#define __NR_getsockname        318
-#define __NR_getsockopt         319
-#define __NR_listen             320
-#define __NR_recv               321
-#define __NR_recvfrom           322
-#define __NR_recvmsg            323
-#define __NR_send               324
-#define __NR_sendmsg            325
-#define __NR_sendto             326
-#define __NR_setsockopt         327
-#define __NR_shutdown           328
-#define __NR_socket             329
-#define __NR_socketpair         330
-
-/* sysv ipc syscalls */
-#define __NR_semctl             331
-#define __NR_semget             332
-#define __NR_semop              333
-#define __NR_msgctl             334
-#define __NR_msgget             335
-#define __NR_msgrcv             336
-#define __NR_msgsnd             337
-#define __NR_shmat              338
-#define __NR_shmctl             339
-#define __NR_shmdt              340
-#define __NR_shmget             341
-
-#define __NR_splice             342
-#define __NR_sync_file_range    343
-#define __NR_tee                344
-#define __NR_vmsplice           345
-
-#define __NR_epoll_pwait        346
-#define __NR_utimensat          347
-#define __NR_signalfd           348
-#define __NR_timerfd_create     349
-#define __NR_eventfd            350
-#define __NR_pread64            351
-#define __NR_pwrite64           352
-#define __NR_fadvise64          353
-#define __NR_set_robust_list    354
-#define __NR_get_robust_list    355
-#define __NR_fallocate          356
-#define __NR_semtimedop         357
-#define __NR_timerfd_settime    358
-#define __NR_timerfd_gettime    359
-#define __NR_signalfd4          360
-#define __NR_eventfd2           361
-#define __NR_epoll_create1      362
-#define __NR_dup3               363
-#define __NR_pipe2              364
-#define __NR_inotify_init1      365
-
-#define __NR_syscall            366
-#define NR_syscalls             __NR_syscall
-
-/* Old optional stuff no one actually uses */
-#define __IGNORE_sysfs
-#define __IGNORE_uselib
-
-/* Implement the newer interfaces */
-#define __IGNORE_mmap
-#define __IGNORE_poll
-#define __IGNORE_select
-#define __IGNORE_utime
-
-/* Not relevant on no-mmu */
-#define __IGNORE_swapon
-#define __IGNORE_swapoff
-#define __IGNORE_msync
-#define __IGNORE_mlock
-#define __IGNORE_munlock
-#define __IGNORE_mlockall
-#define __IGNORE_munlockall
-#define __IGNORE_mincore
-#define __IGNORE_madvise
-#define __IGNORE_remap_file_pages
-#define __IGNORE_mbind
-#define __IGNORE_get_mempolicy
-#define __IGNORE_set_mempolicy
-#define __IGNORE_migrate_pages
-#define __IGNORE_move_pages
-#define __IGNORE_getcpu
-
-#ifdef __KERNEL__
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_STAT64
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_TIME
-#define __ARCH_WANT_SYS_FADVISE64
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_RT_SIGACTION
-#define __ARCH_WANT_SYS_RT_SIGSUSPEND
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
-
-#endif  /* __KERNEL__ */
-
-#endif                          /* __ASM_BFIN_UNISTD_H */
diff --git a/include/asm-blackfin/user.h b/include/asm-blackfin/user.h
deleted file mode 100644
index afe6a0e1f7ce..000000000000
--- a/include/asm-blackfin/user.h
+++ /dev/null
@@ -1,89 +0,0 @@
-#ifndef _BFIN_USER_H
-#define _BFIN_USER_H
-
-/* Changes by Tony Kou   Lineo, Inc.  July, 2001
- *
- * Based include/asm-m68knommu/user.h
- *
- */
-
-/* Core file format: The core file is written in such a way that gdb
-   can understand it and provide useful information to the user (under
-   linux we use the 'trad-core' bfd).  There are quite a number of
-   obstacles to being able to view the contents of the floating point
-   registers, and until these are solved you will not be able to view the
-   contents of them.  Actually, you can read in the core file and look at
-   the contents of the user struct to find out what the floating point
-   registers contain.
-   The actual file contents are as follows:
-   UPAGE: 1 page consisting of a user struct that tells gdb what is present
-   in the file.  Directly after this is a copy of the task_struct, which
-   is currently not used by gdb, but it may come in useful at some point.
-   All of the registers are stored as part of the upage.  The upage should
-   always be only one page.
-   DATA: The data area is stored.  We use current->end_text to
-   current->brk to pick up all of the user variables, plus any memory
-   that may have been malloced.  No attempt is made to determine if a page
-   is demand-zero or if a page is totally unused, we just cover the entire
-   range.  All of the addresses are rounded in such a way that an integral
-   number of pages is written.
-   STACK: We need the stack information in order to get a meaningful
-   backtrace.  We need to write the data from (esp) to
-   current->start_stack, so we round each of these off in order to be able
-   to write an integer number of pages.
-   The minimum core file size is 3 pages, or 12288 bytes.
-*/
-struct user_bfinfp_struct {
-};
-
-/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
-   is still the layout used by user (the new pt_regs doesn't have
-   all registers). */
-struct user_regs_struct {
-        long r0, r1, r2, r3, r4, r5, r6, r7;
-        long p0, p1, p2, p3, p4, p5, usp, fp;
-        long i0, i1, i2, i3;
-        long l0, l1, l2, l3;
-        long b0, b1, b2, b3;
-        long m0, m1, m2, m3;
-        long a0w, a1w;
-        long a0x, a1x;
-        unsigned long rets;
-        unsigned long astat;
-        unsigned long pc;
-        unsigned long orig_p0;
-};
-
-/* When the kernel dumps core, it starts by dumping the user struct -
-   this will be used by gdb to figure out where the data and stack segments
-   are within the file, and what virtual addresses to use. */
-
-struct user {
-/* We start with the registers, to mimic the way that "memory" is returned
-   from the ptrace(3,...) function.  */
-
-        struct user_regs_struct regs;   /* Where the registers are actually stored */
-
-/* The rest of this junk is to help gdb figure out what goes where */
-        unsigned long int u_tsize;      /* Text segment size (pages). */
-        unsigned long int u_dsize;      /* Data segment size (pages). */
-        unsigned long int u_ssize;      /* Stack segment size (pages). */
-        unsigned long start_code;       /* Starting virtual address of text. */
-        unsigned long start_stack;      /* Starting virtual address of stack area.
-                                           This is actually the bottom of the stack,
-                                           the top of the stack is always found in the
-                                           esp register.  */
-        long int signal;        /* Signal that caused the core dump. */
-        int reserved;           /* No longer used */
-        unsigned long u_ar0;
-        /* Used by gdb to help find the values for */
-        /* the registers. */
-        unsigned long magic;    /* To uniquely identify a core file */
-        char u_comm[32];        /* User command that was responsible */
-};
-#define NBPG PAGE_SIZE
-#define UPAGES 1
-#define HOST_TEXT_START_ADDR (u.start_code)
-#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
-
-#endif
diff --git a/include/asm-cris/a.out.h b/include/asm-cris/a.out.h
deleted file mode 100644
index c82e9f9b75f6..000000000000
--- a/include/asm-cris/a.out.h
+++ /dev/null
@@ -1,26 +0,0 @@
-#ifndef __CRIS_A_OUT_H__
-#define __CRIS_A_OUT_H__
-
-/* we don't support a.out binaries on Linux/CRIS anyway, so this is
- * not really used but still needed because binfmt_elf.c for some reason
- * wants to know about a.out even if there is no interpreter available...
- */
-
-struct exec
-{
-  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif
diff --git a/include/asm-cris/elf.h b/include/asm-cris/elf.h
index 001f64ad11e8..f0d17fbc81ba 100644
--- a/include/asm-cris/elf.h
+++ b/include/asm-cris/elf.h
@@ -88,6 +88,6 @@ typedef unsigned long elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif
diff --git a/include/asm-frv/elf.h b/include/asm-frv/elf.h
index 9fb946bb7dc9..7279ec07d62e 100644
--- a/include/asm-frv/elf.h
+++ b/include/asm-frv/elf.h
@@ -137,6 +137,6 @@ do {											\
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif
diff --git a/include/asm-frv/unaligned.h b/include/asm-frv/unaligned.h
index 839a2fbffa0f..6c61c05b2e0c 100644
--- a/include/asm-frv/unaligned.h
+++ b/include/asm-frv/unaligned.h
@@ -13,7 +13,7 @@
 #define _ASM_UNALIGNED_H
 
 #include <linux/unaligned/le_byteshift.h>
-#include <linux/unaligned/be_byteshift.h>
+#include <linux/unaligned/be_struct.h>
 #include <linux/unaligned/generic.h>
 
 #define get_unaligned   __get_unaligned_be
diff --git a/include/asm-generic/Kbuild.asm b/include/asm-generic/Kbuild.asm
index 1170dc60e638..1870d5e05f1c 100644
--- a/include/asm-generic/Kbuild.asm
+++ b/include/asm-generic/Kbuild.asm
@@ -1,8 +1,10 @@
-ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/kvm.h),)
+ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/kvm.h \
+                  $(srctree)/include/asm-$(SRCARCH)/kvm.h),)
 header-y  += kvm.h
 endif
 
-ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/a.out.h),)
+ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/a.out.h \
+                  $(srctree)/include/asm-$(SRCARCH)/a.out.h),)
 unifdef-y += a.out.h
 endif
 unifdef-y += auxvec.h
diff --git a/include/asm-generic/bug.h b/include/asm-generic/bug.h
index a3f738cffdb6..0f6dabd4b517 100644
--- a/include/asm-generic/bug.h
+++ b/include/asm-generic/bug.h
@@ -22,7 +22,7 @@ struct bug_entry {
 
 #ifndef HAVE_ARCH_BUG
 #define BUG() do { \
-        printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __FUNCTION__); \
+        printk("BUG: failure at %s:%d/%s()!\n", __FILE__, __LINE__, __func__); \
         panic("BUG!"); \
 } while (0)
 #endif
@@ -97,6 +97,16 @@ extern void warn_slowpath(const char *file, const int line,
         unlikely(__ret_warn_once);                              \
 })
 
+#define WARN_ONCE(condition, format...) ({                      \
+        static int __warned;                                    \
+        int __ret_warn_once = !!(condition);                    \
+                                                                \
+        if (unlikely(__ret_warn_once))                          \
+                if (WARN(!__warned, format))                    \
+                        __warned = 1;                           \
+        unlikely(__ret_warn_once);                              \
+})
+
 #define WARN_ON_RATELIMIT(condition, state)                     \
                 WARN_ON((condition) && __ratelimit(state))
 
diff --git a/include/asm-generic/gpio.h b/include/asm-generic/gpio.h
index 0f99ad38b012..81797ec9ab29 100644
--- a/include/asm-generic/gpio.h
+++ b/include/asm-generic/gpio.h
@@ -35,11 +35,17 @@ struct module;
  * @label: for diagnostics
  * @dev: optional device providing the GPIOs
  * @owner: helps prevent removal of modules exporting active GPIOs
+ * @request: optional hook for chip-specific activation, such as
+ *      enabling module power and clock; may sleep
+ * @free: optional hook for chip-specific deactivation, such as
+ *      disabling module power and clock; may sleep
  * @direction_input: configures signal "offset" as input, or returns error
  * @get: returns value for signal "offset"; for output signals this
  *      returns either the value actually sensed, or zero
  * @direction_output: configures signal "offset" as output, or returns error
  * @set: assigns output value for signal "offset"
+ * @to_irq: optional hook supporting non-static gpio_to_irq() mappings;
+ *      implementation may not sleep
  * @dbg_show: optional routine to show contents in debugfs; default code
  *      will be used when this is omitted, but custom code can show extra
  *      state (such as pullup/pulldown configuration).
@@ -61,10 +67,15 @@ struct module;
  * is calculated by subtracting @base from the gpio number.
  */
 struct gpio_chip {
-        char                    *label;
+        const char              *label;
         struct device           *dev;
         struct module           *owner;
 
+        int                     (*request)(struct gpio_chip *chip,
+                                                unsigned offset);
+        void                    (*free)(struct gpio_chip *chip,
+                                                unsigned offset);
+
         int                     (*direction_input)(struct gpio_chip *chip,
                                                 unsigned offset);
         int                     (*get)(struct gpio_chip *chip,
@@ -73,6 +84,10 @@ struct gpio_chip {
                                                 unsigned offset, int value);
         void                    (*set)(struct gpio_chip *chip,
                                                 unsigned offset, int value);
+
+        int                     (*to_irq)(struct gpio_chip *chip,
+                                                unsigned offset);
+
         void                    (*dbg_show)(struct seq_file *s,
                                                 struct gpio_chip *chip);
         int                     base;
@@ -112,6 +127,7 @@ extern void __gpio_set_value(unsigned gpio, int value);
 
 extern int __gpio_cansleep(unsigned gpio);
 
+extern int __gpio_to_irq(unsigned gpio);
 
 #ifdef CONFIG_GPIO_SYSFS
 
diff --git a/include/asm-generic/rtc.h b/include/asm-generic/rtc.h
index be4af0029ac0..71ef3f0b9685 100644
--- a/include/asm-generic/rtc.h
+++ b/include/asm-generic/rtc.h
@@ -15,6 +15,7 @@
 #include <linux/mc146818rtc.h>
 #include <linux/rtc.h>
 #include <linux/bcd.h>
+#include <linux/delay.h>
 
 #define RTC_PIE 0x40            /* periodic interrupt enable */
 #define RTC_AIE 0x20            /* alarm interrupt enable */
@@ -43,7 +44,6 @@ static inline unsigned char rtc_is_updating(void)
 
 static inline unsigned int get_rtc_time(struct rtc_time *time)
 {
-        unsigned long uip_watchdog = jiffies;
         unsigned char ctrl;
         unsigned long flags;
 
@@ -53,19 +53,15 @@ static inline unsigned int get_rtc_time(struct rtc_time *time)
 
         /*
          * read RTC once any update in progress is done. The update
-         * can take just over 2ms. We wait 10 to 20ms. There is no need to
+         * can take just over 2ms. We wait 20ms. There is no need to
          * to poll-wait (up to 1s - eeccch) for the falling edge of RTC_UIP.
          * If you need to know *exactly* when a second has started, enable
          * periodic update complete interrupts, (via ioctl) and then 
          * immediately read /dev/rtc which will block until you get the IRQ.
          * Once the read clears, read the RTC time (again via ioctl). Easy.
          */
-
-        if (rtc_is_updating() != 0)
-                while (jiffies - uip_watchdog < 2*HZ/100) {
-                        barrier();
-                        cpu_relax();
-                }
+        if (rtc_is_updating())
+                mdelay(20);
 
         /*
          * Only the values that we read from the RTC are set. We leave
diff --git a/include/asm-generic/sections.h b/include/asm-generic/sections.h
index 8feeae1f2369..79a7ff925bf8 100644
--- a/include/asm-generic/sections.h
+++ b/include/asm-generic/sections.h
@@ -14,4 +14,10 @@ extern char __kprobes_text_start[], __kprobes_text_end[];
 extern char __initdata_begin[], __initdata_end[];
 extern char __start_rodata[], __end_rodata[];
 
+/* function descriptor handling (if any).  Override
+ * in asm/sections.h */
+#ifndef dereference_function_descriptor
+#define dereference_function_descriptor(p) (p)
+#endif
+
 #endif /* _ASM_GENERIC_SECTIONS_H_ */
diff --git a/include/asm-generic/siginfo.h b/include/asm-generic/siginfo.h
index 8786e01e0db8..969570167e9e 100644
--- a/include/asm-generic/siginfo.h
+++ b/include/asm-generic/siginfo.h
@@ -199,6 +199,8 @@ typedef struct siginfo {
  */
 #define TRAP_BRKPT      (__SI_FAULT|1)  /* process breakpoint */
 #define TRAP_TRACE      (__SI_FAULT|2)  /* process trace trap */
+#define TRAP_BRANCH     (__SI_FAULT|3)  /* process taken branch trap */
+#define TRAP_HWBKPT     (__SI_FAULT|4)  /* hardware breakpoint/watchpoint */
 #define NSIGTRAP        2
 
 /*
diff --git a/include/asm-generic/statfs.h b/include/asm-generic/statfs.h
index 1d01043e797d..6129d6802149 100644
--- a/include/asm-generic/statfs.h
+++ b/include/asm-generic/statfs.h
@@ -6,33 +6,64 @@
 typedef __kernel_fsid_t fsid_t;
 #endif
 
+/*
+ * Most 64-bit platforms use 'long', while most 32-bit platforms use '__u32'.
+ * Yes, they differ in signedness as well as size.
+ * Special cases can override it for themselves -- except for S390x, which
+ * is just a little too special for us. And MIPS, which I'm not touching
+ * with a 10' pole.
+ */
+#ifndef __statfs_word
+#if BITS_PER_LONG == 64
+#define __statfs_word long
+#else
+#define __statfs_word __u32
+#endif
+#endif
+
 struct statfs {
-        __u32 f_type;
-        __u32 f_bsize;
-        __u32 f_blocks;
-        __u32 f_bfree;
-        __u32 f_bavail;
-        __u32 f_files;
-        __u32 f_ffree;
+        __statfs_word f_type;
+        __statfs_word f_bsize;
+        __statfs_word f_blocks;
+        __statfs_word f_bfree;
+        __statfs_word f_bavail;
+        __statfs_word f_files;
+        __statfs_word f_ffree;
         __kernel_fsid_t f_fsid;
-        __u32 f_namelen;
-        __u32 f_frsize;
-        __u32 f_spare[5];
+        __statfs_word f_namelen;
+        __statfs_word f_frsize;
+        __statfs_word f_spare[5];
 };
 
+/*
+ * ARM needs to avoid the 32-bit padding at the end, for consistency
+ * between EABI and OABI 
+ */
+#ifndef ARCH_PACK_STATFS64
+#define ARCH_PACK_STATFS64
+#endif
+
 struct statfs64 {
-        __u32 f_type;
-        __u32 f_bsize;
+        __statfs_word f_type;
+        __statfs_word f_bsize;
         __u64 f_blocks;
         __u64 f_bfree;
         __u64 f_bavail;
         __u64 f_files;
         __u64 f_ffree;
         __kernel_fsid_t f_fsid;
-        __u32 f_namelen;
-        __u32 f_frsize;
-        __u32 f_spare[5];
-};
+        __statfs_word f_namelen;
+        __statfs_word f_frsize;
+        __statfs_word f_spare[5];
+} ARCH_PACK_STATFS64;
+
+/* 
+ * IA64 and x86_64 need to avoid the 32-bit padding at the end,
+ * to be compatible with the i386 ABI
+ */
+#ifndef ARCH_PACK_COMPAT_STATFS64
+#define ARCH_PACK_COMPAT_STATFS64
+#endif
 
 struct compat_statfs64 {
         __u32 f_type;
@@ -46,6 +77,6 @@ struct compat_statfs64 {
         __u32 f_namelen;
         __u32 f_frsize;
         __u32 f_spare[5];
-};
+} ARCH_PACK_COMPAT_STATFS64;
 
 #endif
diff --git a/include/asm-generic/syscall.h b/include/asm-generic/syscall.h
index abcf34c2fdc7..ea8087b55ffc 100644
--- a/include/asm-generic/syscall.h
+++ b/include/asm-generic/syscall.h
@@ -126,7 +126,7 @@ void syscall_get_arguments(struct task_struct *task, struct pt_regs *regs,
  * @args:       array of argument values to store
  *
  * Changes @n arguments to the system call starting with the @i'th argument.
- * @n'th argument to @val.  Argument @i gets value @args[0], and so on.
+ * Argument @i gets value @args[0], and so on.
  * An arch inline version is probably optimal when @i and @n are constants.
  *
  * It's only valid to call this when @task is stopped for tracing on
diff --git a/include/asm-generic/vmlinux.lds.h b/include/asm-generic/vmlinux.lds.h
index cb752ba72466..74c5faf26c05 100644
--- a/include/asm-generic/vmlinux.lds.h
+++ b/include/asm-generic/vmlinux.lds.h
@@ -268,7 +268,15 @@
         CPU_DISCARD(init.data)                                          \
         CPU_DISCARD(init.rodata)                                        \
         MEM_DISCARD(init.data)                                          \
-        MEM_DISCARD(init.rodata)
+        MEM_DISCARD(init.rodata)                                        \
+        /* implement dynamic printk debug */                            \
+        VMLINUX_SYMBOL(__start___verbose_strings) = .;                  \
+        *(__verbose_strings)                                            \
+        VMLINUX_SYMBOL(__stop___verbose_strings) = .;                   \
+        . = ALIGN(8);                                                   \
+        VMLINUX_SYMBOL(__start___verbose) = .;                          \
+        *(__verbose)                                                    \
+        VMLINUX_SYMBOL(__stop___verbose) = .;
 
 #define INIT_TEXT                                                       \
         *(.init.text)                                                   \
@@ -385,6 +393,7 @@
         . = ALIGN(align);                                               \
         VMLINUX_SYMBOL(__per_cpu_start) = .;                            \
         .data.percpu  : AT(ADDR(.data.percpu) - LOAD_OFFSET) {          \
+                *(.data.percpu.page_aligned)                            \
                 *(.data.percpu)                                         \
                 *(.data.percpu.shared_aligned)                          \
         }                                                               \
diff --git a/include/asm-h8300/timer.h b/include/asm-h8300/timer.h
new file mode 100644
index 000000000000..def80464d38f
--- /dev/null
+++ b/include/asm-h8300/timer.h
@@ -0,0 +1,25 @@
+#ifndef __H8300_TIMER_H
+#define __H8300_TIMER_H
+
+void h8300_timer_tick(void);
+void h8300_timer_setup(void);
+void h8300_gettod(unsigned int *year, unsigned int *mon, unsigned int *day,
+                   unsigned int *hour, unsigned int *min, unsigned int *sec);
+
+#define TIMER_FREQ (CONFIG_CPU_CLOCK*10000) /* Timer input freq. */
+
+#define calc_param(cnt, div, rate, limit)                       \
+do {                                                            \
+        cnt = TIMER_FREQ / HZ;                                  \
+        for (div = 0; div < ARRAY_SIZE(divide_rate); div++) {   \
+                if (rate[div] == 0)                             \
+                        continue;                               \
+                if ((cnt / rate[div]) > limit)                  \
+                        break;                                  \
+        }                                                       \
+        if (div == ARRAY_SIZE(divide_rate))                     \
+                panic("Timer counter overflow");                \
+        cnt /= divide_rate[div];                                \
+} while(0)
+
+#endif
diff --git a/include/asm-m32r/a.out.h b/include/asm-m32r/a.out.h
deleted file mode 100644
index ab150f5c1666..000000000000
--- a/include/asm-m32r/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_M32R_A_OUT_H
-#define _ASM_M32R_A_OUT_H
-
-struct exec
-{
-  unsigned long a_info;         /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif /* _ASM_M32R_A_OUT_H */
diff --git a/include/asm-m32r/elf.h b/include/asm-m32r/elf.h
index 67bcd77494a5..0cc34c94bf2b 100644
--- a/include/asm-m32r/elf.h
+++ b/include/asm-m32r/elf.h
@@ -129,6 +129,6 @@ typedef elf_fpreg_t elf_fpregset_t;
    intent than poking at uname or /proc/cpuinfo.  */
 #define ELF_PLATFORM    (NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif  /* _ASM_M32R__ELF_H */
diff --git a/include/asm-m68k/atarihw.h b/include/asm-m68k/atarihw.h
index ecf007df7743..1412b4ab202f 100644
--- a/include/asm-m68k/atarihw.h
+++ b/include/asm-m68k/atarihw.h
@@ -39,7 +39,6 @@ extern int atari_dont_touch_floppy_select;
 #define MACH_IS_TT      ((atari_mch_cookie >> 16) == ATARI_MCH_TT)
 #define MACH_IS_FALCON  ((atari_mch_cookie >> 16) == ATARI_MCH_FALCON)
 #define MACH_IS_MEDUSA  (atari_mch_type == ATARI_MACH_MEDUSA)
-#define MACH_IS_HADES   (atari_mch_type == ATARI_MACH_HADES)
 #define MACH_IS_AB40    (atari_mch_type == ATARI_MACH_AB40)
 
 /* values for atari_switches */
diff --git a/include/asm-m68k/dma-mapping.h b/include/asm-m68k/dma-mapping.h
index 91f7944333d4..26f505488c11 100644
--- a/include/asm-m68k/dma-mapping.h
+++ b/include/asm-m68k/dma-mapping.h
@@ -74,6 +74,14 @@ extern void dma_sync_single_for_device(struct device *, dma_addr_t, size_t,
 extern void dma_sync_sg_for_device(struct device *, struct scatterlist *, int,
                                    enum dma_data_direction);
 
+static inline void dma_sync_single_range_for_device(struct device *dev,
+                dma_addr_t dma_handle, unsigned long offset, size_t size,
+                enum dma_data_direction direction)
+{
+        /* just sync everything for now */
+        dma_sync_single_for_device(dev, dma_handle, offset + size, direction);
+}
+
 static inline void dma_sync_single_for_cpu(struct device *dev, dma_addr_t handle,
                                            size_t size, enum dma_data_direction dir)
 {
@@ -84,6 +92,14 @@ static inline void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *s
 {
 }
 
+static inline void dma_sync_single_range_for_cpu(struct device *dev,
+                dma_addr_t dma_handle, unsigned long offset, size_t size,
+                enum dma_data_direction direction)
+{
+        /* just sync everything for now */
+        dma_sync_single_for_cpu(dev, dma_handle, offset + size, direction);
+}
+
 static inline int dma_mapping_error(struct device *dev, dma_addr_t handle)
 {
         return 0;
diff --git a/include/asm-m68k/dma.h b/include/asm-m68k/dma.h
index d0c9e61e57b4..4240fbc946f8 100644
--- a/include/asm-m68k/dma.h
+++ b/include/asm-m68k/dma.h
@@ -11,10 +11,6 @@
 extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
 extern void free_dma(unsigned int dmanr);       /* release it again */
 
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
 #define isa_dma_bridge_buggy    (0)
-#endif
 
 #endif /* _M68K_DMA_H */
diff --git a/include/asm-m68k/elf.h b/include/asm-m68k/elf.h
index 14ea42152b97..0b0f49eb876b 100644
--- a/include/asm-m68k/elf.h
+++ b/include/asm-m68k/elf.h
@@ -114,6 +114,6 @@ typedef struct user_m68kfp_struct elf_fpregset_t;
 
 #define ELF_PLATFORM  (NULL)
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 
 #endif
diff --git a/include/asm-m68k/entry.h b/include/asm-m68k/entry.h
index f8f6b185d793..5202f5a5b420 100644
--- a/include/asm-m68k/entry.h
+++ b/include/asm-m68k/entry.h
@@ -31,7 +31,7 @@
  */
 
 /* the following macro is used when enabling interrupts */
-#if defined(MACH_ATARI_ONLY) && !defined(CONFIG_HADES)
+#if defined(MACH_ATARI_ONLY)
         /* block out HSYNC on the atari */
 #define ALLOWINT        (~0x400)
 #define MAX_NOINT_IPL   3
diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h
index 657187f0c7c2..9e673e3bd434 100644
--- a/include/asm-m68k/io.h
+++ b/include/asm-m68k/io.h
@@ -7,15 +7,12 @@
  *            - added skeleton for GG-II and Amiga PCMCIA
  * 2/3/01 RZ: - moved a few more defs into raw_io.h
  *
- * inX/outX/readX/writeX should not be used by any driver unless it does
- * ISA or PCI access. Other drivers should use function defined in raw_io.h
+ * inX/outX should not be used by any driver unless it does
+ * ISA access. Other drivers should use function defined in raw_io.h
  * or define its own macros on top of these.
  *
- *    inX(),outX()              are for PCI and ISA I/O
- *    readX(),writeX()          are for PCI memory
+ *    inX(),outX()              are for ISA I/O
  *    isa_readX(),isa_writeX()  are for ISA memory
- *
- * moved mem{cpy,set}_*io inside CONFIG_PCI
  */
 
 #ifndef _IO_H
@@ -256,10 +253,7 @@ static inline void isa_delay(void)
        (ISA_SEX ? raw_outsl(isa_itl(port), (u32 *)(buf), (nr)) :  \
                   raw_outsw_swapw(isa_itw(port), (u16 *)(buf), (nr)<<1))
 
-#endif  /* CONFIG_ISA */
-
 
-#if defined(CONFIG_ISA) && !defined(CONFIG_PCI)
 #define inb     isa_inb
 #define inb_p   isa_inb_p
 #define outb    isa_outb
@@ -282,55 +276,9 @@ static inline void isa_delay(void)
 #define readw   isa_readw
 #define writeb  isa_writeb
 #define writew  isa_writew
-#endif /* CONFIG_ISA */
-
-#if defined(CONFIG_PCI)
-
-#define readl(addr)      in_le32(addr)
-#define writel(val,addr) out_le32((addr),(val))
-
-/* those can be defined for both ISA and PCI - it won't work though */
-#define readb(addr)       in_8(addr)
-#define readw(addr)       in_le16(addr)
-#define writeb(val,addr)  out_8((addr),(val))
-#define writew(val,addr)  out_le16((addr),(val))
 
-#define readb_relaxed(addr) readb(addr)
-#define readw_relaxed(addr) readw(addr)
-#define readl_relaxed(addr) readl(addr)
+#else  /* CONFIG_ISA */
 
-#ifndef CONFIG_ISA
-#define inb(port)      in_8(port)
-#define outb(val,port) out_8((port),(val))
-#define inw(port)      in_le16(port)
-#define outw(val,port) out_le16((port),(val))
-#define inl(port)      in_le32(port)
-#define outl(val,port) out_le32((port),(val))
-
-#else
-/*
- * kernel with both ISA and PCI compiled in, those have
- * conflicting defs for in/out. Simply consider port < 1024
- * ISA and everything else PCI. read,write not defined
- * in this case
- */
-#define inb(port) ((port)<1024 ? isa_inb(port) : in_8(port))
-#define inb_p(port) ((port)<1024 ? isa_inb_p(port) : in_8(port))
-#define inw(port) ((port)<1024 ? isa_inw(port) : in_le16(port))
-#define inw_p(port) ((port)<1024 ? isa_inw_p(port) : in_le16(port))
-#define inl(port) ((port)<1024 ? isa_inl(port) : in_le32(port))
-#define inl_p(port) ((port)<1024 ? isa_inl_p(port) : in_le32(port))
-
-#define outb(val,port) ((port)<1024 ? isa_outb((val),(port)) : out_8((port),(val)))
-#define outb_p(val,port) ((port)<1024 ? isa_outb_p((val),(port)) : out_8((port),(val)))
-#define outw(val,port) ((port)<1024 ? isa_outw((val),(port)) : out_le16((port),(val)))
-#define outw_p(val,port) ((port)<1024 ? isa_outw_p((val),(port)) : out_le16((port),(val)))
-#define outl(val,port) ((port)<1024 ? isa_outl((val),(port)) : out_le32((port),(val)))
-#define outl_p(val,port) ((port)<1024 ? isa_outl_p((val),(port)) : out_le32((port),(val)))
-#endif
-#endif /* CONFIG_PCI */
-
-#if !defined(CONFIG_ISA) && !defined(CONFIG_PCI)
 /*
  * We need to define dummy functions for GENERIC_IOMAP support.
  */
@@ -357,11 +305,11 @@ static inline void isa_delay(void)
 #define writeb(val,addr) out_8((addr),(val))
 #define readw(addr)      in_le16(addr)
 #define writew(val,addr) out_le16((addr),(val))
-#endif
-#if !defined(CONFIG_PCI)
+
+#endif /* CONFIG_ISA */
+
 #define readl(addr)      in_le32(addr)
 #define writel(val,addr) out_le32((addr),(val))
-#endif
 
 #define mmiowb()
 
diff --git a/include/asm-m68k/pci.h b/include/asm-m68k/pci.h
index 678cb0b52314..4ad0aea48ab4 100644
--- a/include/asm-m68k/pci.h
+++ b/include/asm-m68k/pci.h
@@ -1,52 +1,7 @@
 #ifndef _ASM_M68K_PCI_H
 #define _ASM_M68K_PCI_H
 
-/*
- * asm-m68k/pci_m68k.h - m68k specific PCI declarations.
- *
- * Written by Wout Klaren.
- */
-
-#include <asm/scatterlist.h>
-
-struct pci_ops;
-
-/*
- * Structure with hardware dependent information and functions of the
- * PCI bus.
- */
-
-struct pci_bus_info
-{
-        /*
-         * Resources of the PCI bus.
-         */
-
-        struct resource mem_space;
-        struct resource io_space;
-
-        /*
-         * System dependent functions.
-         */
-
-        struct pci_ops *m68k_pci_ops;
-
-        void (*fixup)(int pci_modify);
-        void (*conf_device)(struct pci_dev *dev);
-};
-
-#define pcibios_assign_all_busses()     0
-#define pcibios_scan_all_fns(a, b)      0
-
-static inline void pcibios_set_master(struct pci_dev *dev)
-{
-        /* No special bus mastering setup handling */
-}
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-        /* We don't do dynamic PCI IRQ allocation */
-}
+#include <asm-generic/pci-dma-compat.h>
 
 /* The PCI address space does equal the physical memory
  * address space.  The networking and block device layers use
diff --git a/include/asm-m68k/virtconvert.h b/include/asm-m68k/virtconvert.h
index dea32fbc7e51..22ab05c9c52b 100644
--- a/include/asm-m68k/virtconvert.h
+++ b/include/asm-m68k/virtconvert.h
@@ -40,15 +40,9 @@ static inline void *phys_to_virt(unsigned long address)
 
 /*
  * IO bus memory addresses are 1:1 with the physical address,
- * except on the PCI bus of the Hades.
  */
-#ifdef CONFIG_HADES
-#define virt_to_bus(a) (virt_to_phys(a) + (MACH_IS_HADES ? 0x80000000 : 0))
-#define bus_to_virt(a) (phys_to_virt((a) - (MACH_IS_HADES ? 0x80000000 : 0)))
-#else
 #define virt_to_bus virt_to_phys
 #define bus_to_virt phys_to_virt
-#endif
 
 #endif
 #endif
diff --git a/include/asm-mips/Kbuild b/include/asm-mips/Kbuild
deleted file mode 100644
index 7897f05e3165..000000000000
--- a/include/asm-mips/Kbuild
+++ /dev/null
@@ -1,3 +0,0 @@
-include include/asm-generic/Kbuild.asm
-
-header-y += cachectl.h sgidefs.h sysmips.h
diff --git a/include/asm-mips/a.out.h b/include/asm-mips/a.out.h
deleted file mode 100644
index cad8371422ab..000000000000
--- a/include/asm-mips/a.out.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2003 by Ralf Baechle
- */
-#ifndef _ASM_A_OUT_H
-#define _ASM_A_OUT_H
-
-#ifdef __KERNEL__
-
-
-#endif
-
-struct exec
-{
-        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
-        unsigned a_text;        /* length of text, in bytes */
-        unsigned a_data;        /* length of data, in bytes */
-        unsigned a_bss;         /* length of uninitialized data area for
-                                    file, in bytes */
-        unsigned a_syms;        /* length of symbol table data in file,
-                                   in bytes */
-        unsigned a_entry;       /* start address */
-        unsigned a_trsize;      /* length of relocation info for text, in
-                                    bytes */
-        unsigned a_drsize;      /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif /* _ASM_A_OUT_H */
diff --git a/include/asm-mips/abi.h b/include/asm-mips/abi.h
deleted file mode 100644
index 1dd74fbdc09b..000000000000
--- a/include/asm-mips/abi.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005, 06 by Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 2005 MIPS Technologies, Inc.
- */
-#ifndef _ASM_ABI_H
-#define _ASM_ABI_H
-
-#include <asm/signal.h>
-#include <asm/siginfo.h>
-
-struct mips_abi {
-        int (* const setup_frame)(struct k_sigaction * ka,
-                                  struct pt_regs *regs, int signr,
-                                  sigset_t *set);
-        int (* const setup_rt_frame)(struct k_sigaction * ka,
-                               struct pt_regs *regs, int signr,
-                               sigset_t *set, siginfo_t *info);
-        const unsigned long     restart;
-};
-
-#endif /* _ASM_ABI_H */
diff --git a/include/asm-mips/addrspace.h b/include/asm-mips/addrspace.h
deleted file mode 100644
index 569f80aacbd2..000000000000
--- a/include/asm-mips/addrspace.h
+++ /dev/null
@@ -1,154 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99 Ralf Baechle
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
- */
-#ifndef _ASM_ADDRSPACE_H
-#define _ASM_ADDRSPACE_H
-
-#include <spaces.h>
-
-/*
- *  Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ATYPE_
-#define _ATYPE32_
-#define _ATYPE64_
-#define _CONST64_(x)    x
-#else
-#define _ATYPE_         __PTRDIFF_TYPE__
-#define _ATYPE32_       int
-#define _ATYPE64_       __s64
-#ifdef CONFIG_64BIT
-#define _CONST64_(x)    x ## L
-#else
-#define _CONST64_(x)    x ## LL
-#endif
-#endif
-
-/*
- *  32-bit MIPS address spaces
- */
-#ifdef __ASSEMBLY__
-#define _ACAST32_
-#define _ACAST64_
-#else
-#define _ACAST32_               (_ATYPE_)(_ATYPE32_)    /* widen if necessary */
-#define _ACAST64_               (_ATYPE64_)             /* do _not_ narrow */
-#endif
-
-/*
- * Returns the kernel segment base of a given address
- */
-#define KSEGX(a)                ((_ACAST32_ (a)) & 0xe0000000)
-
-/*
- * Returns the physical address of a CKSEGx / XKPHYS address
- */
-#define CPHYSADDR(a)            ((_ACAST32_(a)) & 0x1fffffff)
-#define XPHYSADDR(a)            ((_ACAST64_(a)) &                       \
-                                 _CONST64_(0x000000ffffffffff))
-
-#ifdef CONFIG_64BIT
-
-/*
- * Memory segments (64bit kernel mode addresses)
- * The compatibility segments use the full 64-bit sign extended value.  Note
- * the R8000 doesn't have them so don't reference these in generic MIPS code.
- */
-#define XKUSEG                  _CONST64_(0x0000000000000000)
-#define XKSSEG                  _CONST64_(0x4000000000000000)
-#define XKPHYS                  _CONST64_(0x8000000000000000)
-#define XKSEG                   _CONST64_(0xc000000000000000)
-#define CKSEG0                  _CONST64_(0xffffffff80000000)
-#define CKSEG1                  _CONST64_(0xffffffffa0000000)
-#define CKSSEG                  _CONST64_(0xffffffffc0000000)
-#define CKSEG3                  _CONST64_(0xffffffffe0000000)
-
-#define CKSEG0ADDR(a)           (CPHYSADDR(a) | CKSEG0)
-#define CKSEG1ADDR(a)           (CPHYSADDR(a) | CKSEG1)
-#define CKSEG2ADDR(a)           (CPHYSADDR(a) | CKSEG2)
-#define CKSEG3ADDR(a)           (CPHYSADDR(a) | CKSEG3)
-
-#else
-
-#define CKSEG0ADDR(a)           (CPHYSADDR(a) | KSEG0)
-#define CKSEG1ADDR(a)           (CPHYSADDR(a) | KSEG1)
-#define CKSEG2ADDR(a)           (CPHYSADDR(a) | KSEG2)
-#define CKSEG3ADDR(a)           (CPHYSADDR(a) | KSEG3)
-
-/*
- * Map an address to a certain kernel segment
- */
-#define KSEG0ADDR(a)            (CPHYSADDR(a) | KSEG0)
-#define KSEG1ADDR(a)            (CPHYSADDR(a) | KSEG1)
-#define KSEG2ADDR(a)            (CPHYSADDR(a) | KSEG2)
-#define KSEG3ADDR(a)            (CPHYSADDR(a) | KSEG3)
-
-/*
- * Memory segments (32bit kernel mode addresses)
- * These are the traditional names used in the 32-bit universe.
- */
-#define KUSEG                   0x00000000
-#define KSEG0                   0x80000000
-#define KSEG1                   0xa0000000
-#define KSEG2                   0xc0000000
-#define KSEG3                   0xe0000000
-
-#define CKUSEG                  0x00000000
-#define CKSEG0                  0x80000000
-#define CKSEG1                  0xa0000000
-#define CKSEG2                  0xc0000000
-#define CKSEG3                  0xe0000000
-
-#endif
-
-/*
- * Cache modes for XKPHYS address conversion macros
- */
-#define K_CALG_COH_EXCL1_NOL2   0
-#define K_CALG_COH_SHRL1_NOL2   1
-#define K_CALG_UNCACHED         2
-#define K_CALG_NONCOHERENT      3
-#define K_CALG_COH_EXCL         4
-#define K_CALG_COH_SHAREABLE    5
-#define K_CALG_NOTUSED          6
-#define K_CALG_UNCACHED_ACCEL   7
-
-/*
- * 64-bit address conversions
- */
-#define PHYS_TO_XKSEG_UNCACHED(p)       PHYS_TO_XKPHYS(K_CALG_UNCACHED, (p))
-#define PHYS_TO_XKSEG_CACHED(p)         PHYS_TO_XKPHYS(K_CALG_COH_SHAREABLE, (p))
-#define XKPHYS_TO_PHYS(p)               ((p) & TO_PHYS_MASK)
-#define PHYS_TO_XKPHYS(cm, a)           (_CONST64_(0x8000000000000000) | \
-                                         (_CONST64_(cm) << 59) | (a))
-
-/*
- * The ultimate limited of the 64-bit MIPS architecture:  2 bits for selecting
- * the region, 3 bits for the CCA mode.  This leaves 59 bits of which the
- * R8000 implements most with its 48-bit physical address space.
- */
-#define TO_PHYS_MASK    _CONST64_(0x07ffffffffffffff)   /* 2^^59 - 1 */
-
-#ifndef CONFIG_CPU_R8000
-
-/*
- * The R8000 doesn't have the 32-bit compat spaces so we don't define them
- * in order to catch bugs in the source code.
- */
-
-#define COMPAT_K1BASE32         _CONST64_(0xffffffffa0000000)
-#define PHYS_TO_COMPATK1(x)     ((x) | COMPAT_K1BASE32) /* 32-bit compat k1 */
-
-#endif
-
-#define KDM_TO_PHYS(x)          (_ACAST64_ (x) & TO_PHYS_MASK)
-#define PHYS_TO_K0(x)           (_ACAST64_ (x) | CAC_BASE)
-
-#endif /* _ASM_ADDRSPACE_H */
diff --git a/include/asm-mips/asm.h b/include/asm-mips/asm.h
deleted file mode 100644
index 608cfcfbb3ea..000000000000
--- a/include/asm-mips/asm.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 1997, 1999, 2001 by Ralf Baechle
- * Copyright (C) 1999 by Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- * Copyright (C) 2002  Maciej W. Rozycki
- *
- * Some useful macros for MIPS assembler code
- *
- * Some of the routines below contain useless nops that will be optimized
- * away by gas in -O mode. These nops are however required to fill delay
- * slots in noreorder mode.
- */
-#ifndef __ASM_ASM_H
-#define __ASM_ASM_H
-
-#include <asm/sgidefs.h>
-
-#ifndef CAT
-#ifdef __STDC__
-#define __CAT(str1, str2) str1##str2
-#else
-#define __CAT(str1, str2) str1/**/str2
-#endif
-#define CAT(str1, str2) __CAT(str1, str2)
-#endif
-
-/*
- * PIC specific declarations
- * Not used for the kernel but here seems to be the right place.
- */
-#ifdef __PIC__
-#define CPRESTORE(register)                             \
-                .cprestore register
-#define CPADD(register)                                 \
-                .cpadd  register
-#define CPLOAD(register)                                \
-                .cpload register
-#else
-#define CPRESTORE(register)
-#define CPADD(register)
-#define CPLOAD(register)
-#endif
-
-/*
- * LEAF - declare leaf routine
- */
-#define LEAF(symbol)                                    \
-                .globl  symbol;                         \
-                .align  2;                              \
-                .type   symbol, @function;              \
-                .ent    symbol, 0;                      \
-symbol:         .frame  sp, 0, ra
-
-/*
- * NESTED - declare nested routine entry point
- */
-#define NESTED(symbol, framesize, rpc)                  \
-                .globl  symbol;                         \
-                .align  2;                              \
-                .type   symbol, @function;              \
-                .ent    symbol, 0;                       \
-symbol:         .frame  sp, framesize, rpc
-
-/*
- * END - mark end of function
- */
-#define END(function)                                   \
-                .end    function;                       \
-                .size   function, .-function
-
-/*
- * EXPORT - export definition of symbol
- */
-#define EXPORT(symbol)                                  \
-                .globl  symbol;                         \
-symbol:
-
-/*
- * FEXPORT - export definition of a function symbol
- */
-#define FEXPORT(symbol)                                 \
-                .globl  symbol;                         \
-                .type   symbol, @function;              \
-symbol:
-
-/*
- * ABS - export absolute symbol
- */
-#define ABS(symbol,value)                               \
-                .globl  symbol;                         \
-symbol          =       value
-
-#define PANIC(msg)                                      \
-                .set    push;                           \
-                .set    reorder;                        \
-                PTR_LA  a0, 8f;                          \
-                jal     panic;                          \
-9:              b       9b;                             \
-                .set    pop;                            \
-                TEXT(msg)
-
-/*
- * Print formatted string
- */
-#ifdef CONFIG_PRINTK
-#define PRINT(string)                                   \
-                .set    push;                           \
-                .set    reorder;                        \
-                PTR_LA  a0, 8f;                          \
-                jal     printk;                         \
-                .set    pop;                            \
-                TEXT(string)
-#else
-#define PRINT(string)
-#endif
-
-#define TEXT(msg)                                       \
-                .pushsection .data;                     \
-8:              .asciiz msg;                            \
-                .popsection;
-
-/*
- * Build text tables
- */
-#define TTABLE(string)                                  \
-                .pushsection .text;                     \
-                .word   1f;                             \
-                .popsection                             \
-                .pushsection .data;                     \
-1:              .asciiz string;                         \
-                .popsection
-
-/*
- * MIPS IV pref instruction.
- * Use with .set noreorder only!
- *
- * MIPS IV implementations are free to treat this as a nop.  The R5000
- * is one of them.  So we should have an option not to use this instruction.
- */
-#ifdef CONFIG_CPU_HAS_PREFETCH
-
-#define PREF(hint,addr)                                 \
-                .set    push;                           \
-                .set    mips4;                          \
-                pref    hint, addr;                     \
-                .set    pop
-
-#define PREFX(hint,addr)                                \
-                .set    push;                           \
-                .set    mips4;                          \
-                prefx   hint, addr;                     \
-                .set    pop
-
-#else /* !CONFIG_CPU_HAS_PREFETCH */
-
-#define PREF(hint, addr)
-#define PREFX(hint, addr)
-
-#endif /* !CONFIG_CPU_HAS_PREFETCH */
-
-/*
- * MIPS ISA IV/V movn/movz instructions and equivalents for older CPUs.
- */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS1)
-#define MOVN(rd, rs, rt)                                \
-                .set    push;                           \
-                .set    reorder;                        \
-                beqz    rt, 9f;                         \
-                move    rd, rs;                         \
-                .set    pop;                            \
-9:
-#define MOVZ(rd, rs, rt)                                \
-                .set    push;                           \
-                .set    reorder;                        \
-                bnez    rt, 9f;                         \
-                move    rd, rs;                         \
-                .set    pop;                            \
-9:
-#endif /* _MIPS_ISA == _MIPS_ISA_MIPS1 */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3)
-#define MOVN(rd, rs, rt)                                \
-                .set    push;                           \
-                .set    noreorder;                      \
-                bnezl   rt, 9f;                         \
-                 move   rd, rs;                         \
-                .set    pop;                            \
-9:
-#define MOVZ(rd, rs, rt)                                \
-                .set    push;                           \
-                .set    noreorder;                      \
-                beqzl   rt, 9f;                         \
-                 move   rd, rs;                         \
-                .set    pop;                            \
-9:
-#endif /* (_MIPS_ISA == _MIPS_ISA_MIPS2) || (_MIPS_ISA == _MIPS_ISA_MIPS3) */
-#if (_MIPS_ISA == _MIPS_ISA_MIPS4 ) || (_MIPS_ISA == _MIPS_ISA_MIPS5) || \
-    (_MIPS_ISA == _MIPS_ISA_MIPS32) || (_MIPS_ISA == _MIPS_ISA_MIPS64)
-#define MOVN(rd, rs, rt)                                \
-                movn    rd, rs, rt
-#define MOVZ(rd, rs, rt)                                \
-                movz    rd, rs, rt
-#endif /* MIPS IV, MIPS V, MIPS32 or MIPS64 */
-
-/*
- * Stack alignment
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define ALSZ    7
-#define ALMASK  ~7
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define ALSZ    15
-#define ALMASK  ~15
-#endif
-
-/*
- * Macros to handle different pointer/register sizes for 32/64-bit code
- */
-
-/*
- * Size of a register
- */
-#ifdef __mips64
-#define SZREG   8
-#else
-#define SZREG   4
-#endif
-
-/*
- * Use the following macros in assemblercode to load/store registers,
- * pointers etc.
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define REG_S           sw
-#define REG_L           lw
-#define REG_SUBU        subu
-#define REG_ADDU        addu
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define REG_S           sd
-#define REG_L           ld
-#define REG_SUBU        dsubu
-#define REG_ADDU        daddu
-#endif
-
-/*
- * How to add/sub/load/store/shift C int variables.
- */
-#if (_MIPS_SZINT == 32)
-#define INT_ADD         add
-#define INT_ADDU        addu
-#define INT_ADDI        addi
-#define INT_ADDIU       addiu
-#define INT_SUB         sub
-#define INT_SUBU        subu
-#define INT_L           lw
-#define INT_S           sw
-#define INT_SLL         sll
-#define INT_SLLV        sllv
-#define INT_SRL         srl
-#define INT_SRLV        srlv
-#define INT_SRA         sra
-#define INT_SRAV        srav
-#endif
-
-#if (_MIPS_SZINT == 64)
-#define INT_ADD         dadd
-#define INT_ADDU        daddu
-#define INT_ADDI        daddi
-#define INT_ADDIU       daddiu
-#define INT_SUB         dsub
-#define INT_SUBU        dsubu
-#define INT_L           ld
-#define INT_S           sd
-#define INT_SLL         dsll
-#define INT_SLLV        dsllv
-#define INT_SRL         dsrl
-#define INT_SRLV        dsrlv
-#define INT_SRA         dsra
-#define INT_SRAV        dsrav
-#endif
-
-/*
- * How to add/sub/load/store/shift C long variables.
- */
-#if (_MIPS_SZLONG == 32)
-#define LONG_ADD        add
-#define LONG_ADDU       addu
-#define LONG_ADDI       addi
-#define LONG_ADDIU      addiu
-#define LONG_SUB        sub
-#define LONG_SUBU       subu
-#define LONG_L          lw
-#define LONG_S          sw
-#define LONG_SLL        sll
-#define LONG_SLLV       sllv
-#define LONG_SRL        srl
-#define LONG_SRLV       srlv
-#define LONG_SRA        sra
-#define LONG_SRAV       srav
-
-#define LONG            .word
-#define LONGSIZE        4
-#define LONGMASK        3
-#define LONGLOG         2
-#endif
-
-#if (_MIPS_SZLONG == 64)
-#define LONG_ADD        dadd
-#define LONG_ADDU       daddu
-#define LONG_ADDI       daddi
-#define LONG_ADDIU      daddiu
-#define LONG_SUB        dsub
-#define LONG_SUBU       dsubu
-#define LONG_L          ld
-#define LONG_S          sd
-#define LONG_SLL        dsll
-#define LONG_SLLV       dsllv
-#define LONG_SRL        dsrl
-#define LONG_SRLV       dsrlv
-#define LONG_SRA        dsra
-#define LONG_SRAV       dsrav
-
-#define LONG            .dword
-#define LONGSIZE        8
-#define LONGMASK        7
-#define LONGLOG         3
-#endif
-
-/*
- * How to add/sub/load/store/shift pointers.
- */
-#if (_MIPS_SZPTR == 32)
-#define PTR_ADD         add
-#define PTR_ADDU        addu
-#define PTR_ADDI        addi
-#define PTR_ADDIU       addiu
-#define PTR_SUB         sub
-#define PTR_SUBU        subu
-#define PTR_L           lw
-#define PTR_S           sw
-#define PTR_LA          la
-#define PTR_LI          li
-#define PTR_SLL         sll
-#define PTR_SLLV        sllv
-#define PTR_SRL         srl
-#define PTR_SRLV        srlv
-#define PTR_SRA         sra
-#define PTR_SRAV        srav
-
-#define PTR_SCALESHIFT  2
-
-#define PTR             .word
-#define PTRSIZE         4
-#define PTRLOG          2
-#endif
-
-#if (_MIPS_SZPTR == 64)
-#define PTR_ADD         dadd
-#define PTR_ADDU        daddu
-#define PTR_ADDI        daddi
-#define PTR_ADDIU       daddiu
-#define PTR_SUB         dsub
-#define PTR_SUBU        dsubu
-#define PTR_L           ld
-#define PTR_S           sd
-#define PTR_LA          dla
-#define PTR_LI          dli
-#define PTR_SLL         dsll
-#define PTR_SLLV        dsllv
-#define PTR_SRL         dsrl
-#define PTR_SRLV        dsrlv
-#define PTR_SRA         dsra
-#define PTR_SRAV        dsrav
-
-#define PTR_SCALESHIFT  3
-
-#define PTR             .dword
-#define PTRSIZE         8
-#define PTRLOG          3
-#endif
-
-/*
- * Some cp0 registers were extended to 64bit for MIPS III.
- */
-#if (_MIPS_SIM == _MIPS_SIM_ABI32)
-#define MFC0            mfc0
-#define MTC0            mtc0
-#endif
-#if (_MIPS_SIM == _MIPS_SIM_NABI32) || (_MIPS_SIM == _MIPS_SIM_ABI64)
-#define MFC0            dmfc0
-#define MTC0            dmtc0
-#endif
-
-#define SSNOP           sll zero, zero, 1
-
-#ifdef CONFIG_SGI_IP28
-/* Inhibit speculative stores to volatile (e.g.DMA) or invalid addresses. */
-#include <asm/cacheops.h>
-#define R10KCBARRIER(addr)  cache   Cache_Barrier, addr;
-#else
-#define R10KCBARRIER(addr)
-#endif
-
-#endif /* __ASM_ASM_H */
diff --git a/include/asm-mips/asmmacro-32.h b/include/asm-mips/asmmacro-32.h
deleted file mode 100644
index 5de3963f511e..000000000000
--- a/include/asm-mips/asmmacro-32.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * asmmacro.h: Assembler macros to make things easier to read.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1998, 1999, 2003 Ralf Baechle
- */
-#ifndef _ASM_ASMMACRO_32_H
-#define _ASM_ASMMACRO_32_H
-
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-
-        .macro  fpu_save_double thread status tmp1=t0
-        cfc1    \tmp1,  fcr31
-        sdc1    $f0,  THREAD_FPR0(\thread)
-        sdc1    $f2,  THREAD_FPR2(\thread)
-        sdc1    $f4,  THREAD_FPR4(\thread)
-        sdc1    $f6,  THREAD_FPR6(\thread)
-        sdc1    $f8,  THREAD_FPR8(\thread)
-        sdc1    $f10, THREAD_FPR10(\thread)
-        sdc1    $f12, THREAD_FPR12(\thread)
-        sdc1    $f14, THREAD_FPR14(\thread)
-        sdc1    $f16, THREAD_FPR16(\thread)
-        sdc1    $f18, THREAD_FPR18(\thread)
-        sdc1    $f20, THREAD_FPR20(\thread)
-        sdc1    $f22, THREAD_FPR22(\thread)
-        sdc1    $f24, THREAD_FPR24(\thread)
-        sdc1    $f26, THREAD_FPR26(\thread)
-        sdc1    $f28, THREAD_FPR28(\thread)
-        sdc1    $f30, THREAD_FPR30(\thread)
-        sw      \tmp1, THREAD_FCR31(\thread)
-        .endm
-
-        .macro  fpu_save_single thread tmp=t0
-        cfc1    \tmp,  fcr31
-        swc1    $f0,  THREAD_FPR0(\thread)
-        swc1    $f1,  THREAD_FPR1(\thread)
-        swc1    $f2,  THREAD_FPR2(\thread)
-        swc1    $f3,  THREAD_FPR3(\thread)
-        swc1    $f4,  THREAD_FPR4(\thread)
-        swc1    $f5,  THREAD_FPR5(\thread)
-        swc1    $f6,  THREAD_FPR6(\thread)
-        swc1    $f7,  THREAD_FPR7(\thread)
-        swc1    $f8,  THREAD_FPR8(\thread)
-        swc1    $f9,  THREAD_FPR9(\thread)
-        swc1    $f10, THREAD_FPR10(\thread)
-        swc1    $f11, THREAD_FPR11(\thread)
-        swc1    $f12, THREAD_FPR12(\thread)
-        swc1    $f13, THREAD_FPR13(\thread)
-        swc1    $f14, THREAD_FPR14(\thread)
-        swc1    $f15, THREAD_FPR15(\thread)
-        swc1    $f16, THREAD_FPR16(\thread)
-        swc1    $f17, THREAD_FPR17(\thread)
-        swc1    $f18, THREAD_FPR18(\thread)
-        swc1    $f19, THREAD_FPR19(\thread)
-        swc1    $f20, THREAD_FPR20(\thread)
-        swc1    $f21, THREAD_FPR21(\thread)
-        swc1    $f22, THREAD_FPR22(\thread)
-        swc1    $f23, THREAD_FPR23(\thread)
-        swc1    $f24, THREAD_FPR24(\thread)
-        swc1    $f25, THREAD_FPR25(\thread)
-        swc1    $f26, THREAD_FPR26(\thread)
-        swc1    $f27, THREAD_FPR27(\thread)
-        swc1    $f28, THREAD_FPR28(\thread)
-        swc1    $f29, THREAD_FPR29(\thread)
-        swc1    $f30, THREAD_FPR30(\thread)
-        swc1    $f31, THREAD_FPR31(\thread)
-        sw      \tmp, THREAD_FCR31(\thread)
-        .endm
-
-        .macro  fpu_restore_double thread status tmp=t0
-        lw      \tmp, THREAD_FCR31(\thread)
-        ldc1    $f0,  THREAD_FPR0(\thread)
-        ldc1    $f2,  THREAD_FPR2(\thread)
-        ldc1    $f4,  THREAD_FPR4(\thread)
-        ldc1    $f6,  THREAD_FPR6(\thread)
-        ldc1    $f8,  THREAD_FPR8(\thread)
-        ldc1    $f10, THREAD_FPR10(\thread)
-        ldc1    $f12, THREAD_FPR12(\thread)
-        ldc1    $f14, THREAD_FPR14(\thread)
-        ldc1    $f16, THREAD_FPR16(\thread)
-        ldc1    $f18, THREAD_FPR18(\thread)
-        ldc1    $f20, THREAD_FPR20(\thread)
-        ldc1    $f22, THREAD_FPR22(\thread)
-        ldc1    $f24, THREAD_FPR24(\thread)
-        ldc1    $f26, THREAD_FPR26(\thread)
-        ldc1    $f28, THREAD_FPR28(\thread)
-        ldc1    $f30, THREAD_FPR30(\thread)
-        ctc1    \tmp, fcr31
-        .endm
-
-        .macro  fpu_restore_single thread tmp=t0
-        lw      \tmp, THREAD_FCR31(\thread)
-        lwc1    $f0,  THREAD_FPR0(\thread)
-        lwc1    $f1,  THREAD_FPR1(\thread)
-        lwc1    $f2,  THREAD_FPR2(\thread)
-        lwc1    $f3,  THREAD_FPR3(\thread)
-        lwc1    $f4,  THREAD_FPR4(\thread)
-        lwc1    $f5,  THREAD_FPR5(\thread)
-        lwc1    $f6,  THREAD_FPR6(\thread)
-        lwc1    $f7,  THREAD_FPR7(\thread)
-        lwc1    $f8,  THREAD_FPR8(\thread)
-        lwc1    $f9,  THREAD_FPR9(\thread)
-        lwc1    $f10, THREAD_FPR10(\thread)
-        lwc1    $f11, THREAD_FPR11(\thread)
-        lwc1    $f12, THREAD_FPR12(\thread)
-        lwc1    $f13, THREAD_FPR13(\thread)
-        lwc1    $f14, THREAD_FPR14(\thread)
-        lwc1    $f15, THREAD_FPR15(\thread)
-        lwc1    $f16, THREAD_FPR16(\thread)
-        lwc1    $f17, THREAD_FPR17(\thread)
-        lwc1    $f18, THREAD_FPR18(\thread)
-        lwc1    $f19, THREAD_FPR19(\thread)
-        lwc1    $f20, THREAD_FPR20(\thread)
-        lwc1    $f21, THREAD_FPR21(\thread)
-        lwc1    $f22, THREAD_FPR22(\thread)
-        lwc1    $f23, THREAD_FPR23(\thread)
-        lwc1    $f24, THREAD_FPR24(\thread)
-        lwc1    $f25, THREAD_FPR25(\thread)
-        lwc1    $f26, THREAD_FPR26(\thread)
-        lwc1    $f27, THREAD_FPR27(\thread)
-        lwc1    $f28, THREAD_FPR28(\thread)
-        lwc1    $f29, THREAD_FPR29(\thread)
-        lwc1    $f30, THREAD_FPR30(\thread)
-        lwc1    $f31, THREAD_FPR31(\thread)
-        ctc1    \tmp, fcr31
-        .endm
-
-        .macro  cpu_save_nonscratch thread
-        LONG_S  s0, THREAD_REG16(\thread)
-        LONG_S  s1, THREAD_REG17(\thread)
-        LONG_S  s2, THREAD_REG18(\thread)
-        LONG_S  s3, THREAD_REG19(\thread)
-        LONG_S  s4, THREAD_REG20(\thread)
-        LONG_S  s5, THREAD_REG21(\thread)
-        LONG_S  s6, THREAD_REG22(\thread)
-        LONG_S  s7, THREAD_REG23(\thread)
-        LONG_S  sp, THREAD_REG29(\thread)
-        LONG_S  fp, THREAD_REG30(\thread)
-        .endm
-
-        .macro  cpu_restore_nonscratch thread
-        LONG_L  s0, THREAD_REG16(\thread)
-        LONG_L  s1, THREAD_REG17(\thread)
-        LONG_L  s2, THREAD_REG18(\thread)
-        LONG_L  s3, THREAD_REG19(\thread)
-        LONG_L  s4, THREAD_REG20(\thread)
-        LONG_L  s5, THREAD_REG21(\thread)
-        LONG_L  s6, THREAD_REG22(\thread)
-        LONG_L  s7, THREAD_REG23(\thread)
-        LONG_L  sp, THREAD_REG29(\thread)
-        LONG_L  fp, THREAD_REG30(\thread)
-        LONG_L  ra, THREAD_REG31(\thread)
-        .endm
-
-#endif /* _ASM_ASMMACRO_32_H */
diff --git a/include/asm-mips/asmmacro-64.h b/include/asm-mips/asmmacro-64.h
deleted file mode 100644
index 225feefcb25d..000000000000
--- a/include/asm-mips/asmmacro-64.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * asmmacro.h: Assembler macros to make things easier to read.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1998, 1999 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_ASMMACRO_64_H
-#define _ASM_ASMMACRO_64_H
-
-#include <asm/asm-offsets.h>
-#include <asm/regdef.h>
-#include <asm/fpregdef.h>
-#include <asm/mipsregs.h>
-
-        .macro  fpu_save_16even thread tmp=t0
-        cfc1    \tmp, fcr31
-        sdc1    $f0,  THREAD_FPR0(\thread)
-        sdc1    $f2,  THREAD_FPR2(\thread)
-        sdc1    $f4,  THREAD_FPR4(\thread)
-        sdc1    $f6,  THREAD_FPR6(\thread)
-        sdc1    $f8,  THREAD_FPR8(\thread)
-        sdc1    $f10, THREAD_FPR10(\thread)
-        sdc1    $f12, THREAD_FPR12(\thread)
-        sdc1    $f14, THREAD_FPR14(\thread)
-        sdc1    $f16, THREAD_FPR16(\thread)
-        sdc1    $f18, THREAD_FPR18(\thread)
-        sdc1    $f20, THREAD_FPR20(\thread)
-        sdc1    $f22, THREAD_FPR22(\thread)
-        sdc1    $f24, THREAD_FPR24(\thread)
-        sdc1    $f26, THREAD_FPR26(\thread)
-        sdc1    $f28, THREAD_FPR28(\thread)
-        sdc1    $f30, THREAD_FPR30(\thread)
-        sw      \tmp, THREAD_FCR31(\thread)
-        .endm
-
-        .macro  fpu_save_16odd thread
-        sdc1    $f1,  THREAD_FPR1(\thread)
-        sdc1    $f3,  THREAD_FPR3(\thread)
-        sdc1    $f5,  THREAD_FPR5(\thread)
-        sdc1    $f7,  THREAD_FPR7(\thread)
-        sdc1    $f9,  THREAD_FPR9(\thread)
-        sdc1    $f11, THREAD_FPR11(\thread)
-        sdc1    $f13, THREAD_FPR13(\thread)
-        sdc1    $f15, THREAD_FPR15(\thread)
-        sdc1    $f17, THREAD_FPR17(\thread)
-        sdc1    $f19, THREAD_FPR19(\thread)
-        sdc1    $f21, THREAD_FPR21(\thread)
-        sdc1    $f23, THREAD_FPR23(\thread)
-        sdc1    $f25, THREAD_FPR25(\thread)
-        sdc1    $f27, THREAD_FPR27(\thread)
-        sdc1    $f29, THREAD_FPR29(\thread)
-        sdc1    $f31, THREAD_FPR31(\thread)
-        .endm
-
-        .macro  fpu_save_double thread status tmp
-        sll     \tmp, \status, 5
-        bgez    \tmp, 2f
-        fpu_save_16odd \thread
-2:
-        fpu_save_16even \thread \tmp
-        .endm
-
-        .macro  fpu_restore_16even thread tmp=t0
-        lw      \tmp, THREAD_FCR31(\thread)
-        ldc1    $f0,  THREAD_FPR0(\thread)
-        ldc1    $f2,  THREAD_FPR2(\thread)
-        ldc1    $f4,  THREAD_FPR4(\thread)
-        ldc1    $f6,  THREAD_FPR6(\thread)
-        ldc1    $f8,  THREAD_FPR8(\thread)
-        ldc1    $f10, THREAD_FPR10(\thread)
-        ldc1    $f12, THREAD_FPR12(\thread)
-        ldc1    $f14, THREAD_FPR14(\thread)
-        ldc1    $f16, THREAD_FPR16(\thread)
-        ldc1    $f18, THREAD_FPR18(\thread)
-        ldc1    $f20, THREAD_FPR20(\thread)
-        ldc1    $f22, THREAD_FPR22(\thread)
-        ldc1    $f24, THREAD_FPR24(\thread)
-        ldc1    $f26, THREAD_FPR26(\thread)
-        ldc1    $f28, THREAD_FPR28(\thread)
-        ldc1    $f30, THREAD_FPR30(\thread)
-        ctc1    \tmp, fcr31
-        .endm
-
-        .macro  fpu_restore_16odd thread
-        ldc1    $f1,  THREAD_FPR1(\thread)
-        ldc1    $f3,  THREAD_FPR3(\thread)
-        ldc1    $f5,  THREAD_FPR5(\thread)
-        ldc1    $f7,  THREAD_FPR7(\thread)
-        ldc1    $f9,  THREAD_FPR9(\thread)
-        ldc1    $f11, THREAD_FPR11(\thread)
-        ldc1    $f13, THREAD_FPR13(\thread)
-        ldc1    $f15, THREAD_FPR15(\thread)
-        ldc1    $f17, THREAD_FPR17(\thread)
-        ldc1    $f19, THREAD_FPR19(\thread)
-        ldc1    $f21, THREAD_FPR21(\thread)
-        ldc1    $f23, THREAD_FPR23(\thread)
-        ldc1    $f25, THREAD_FPR25(\thread)
-        ldc1    $f27, THREAD_FPR27(\thread)
-        ldc1    $f29, THREAD_FPR29(\thread)
-        ldc1    $f31, THREAD_FPR31(\thread)
-        .endm
-
-        .macro  fpu_restore_double thread status tmp
-        sll     \tmp, \status, 5
-        bgez    \tmp, 1f                                # 16 register mode?
-
-        fpu_restore_16odd \thread
-1:      fpu_restore_16even \thread \tmp
-        .endm
-
-        .macro  cpu_save_nonscratch thread
-        LONG_S  s0, THREAD_REG16(\thread)
-        LONG_S  s1, THREAD_REG17(\thread)
-        LONG_S  s2, THREAD_REG18(\thread)
-        LONG_S  s3, THREAD_REG19(\thread)
-        LONG_S  s4, THREAD_REG20(\thread)
-        LONG_S  s5, THREAD_REG21(\thread)
-        LONG_S  s6, THREAD_REG22(\thread)
-        LONG_S  s7, THREAD_REG23(\thread)
-        LONG_S  sp, THREAD_REG29(\thread)
-        LONG_S  fp, THREAD_REG30(\thread)
-        .endm
-
-        .macro  cpu_restore_nonscratch thread
-        LONG_L  s0, THREAD_REG16(\thread)
-        LONG_L  s1, THREAD_REG17(\thread)
-        LONG_L  s2, THREAD_REG18(\thread)
-        LONG_L  s3, THREAD_REG19(\thread)
-        LONG_L  s4, THREAD_REG20(\thread)
-        LONG_L  s5, THREAD_REG21(\thread)
-        LONG_L  s6, THREAD_REG22(\thread)
-        LONG_L  s7, THREAD_REG23(\thread)
-        LONG_L  sp, THREAD_REG29(\thread)
-        LONG_L  fp, THREAD_REG30(\thread)
-        LONG_L  ra, THREAD_REG31(\thread)
-        .endm
-
-#endif /* _ASM_ASMMACRO_64_H */
diff --git a/include/asm-mips/asmmacro.h b/include/asm-mips/asmmacro.h
deleted file mode 100644
index 7a881755800f..000000000000
--- a/include/asm-mips/asmmacro.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Ralf Baechle
- */
-#ifndef _ASM_ASMMACRO_H
-#define _ASM_ASMMACRO_H
-
-#include <asm/hazards.h>
-
-#ifdef CONFIG_32BIT
-#include <asm/asmmacro-32.h>
-#endif
-#ifdef CONFIG_64BIT
-#include <asm/asmmacro-64.h>
-#endif
-#ifdef CONFIG_MIPS_MT_SMTC
-#include <asm/mipsmtregs.h>
-#endif
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        .macro  local_irq_enable reg=t0
-        mfc0    \reg, CP0_TCSTATUS
-        ori     \reg, \reg, TCSTATUS_IXMT
-        xori    \reg, \reg, TCSTATUS_IXMT
-        mtc0    \reg, CP0_TCSTATUS
-        _ehb
-        .endm
-
-        .macro  local_irq_disable reg=t0
-        mfc0    \reg, CP0_TCSTATUS
-        ori     \reg, \reg, TCSTATUS_IXMT
-        mtc0    \reg, CP0_TCSTATUS
-        _ehb
-        .endm
-#else
-        .macro  local_irq_enable reg=t0
-        mfc0    \reg, CP0_STATUS
-        ori     \reg, \reg, 1
-        mtc0    \reg, CP0_STATUS
-        irq_enable_hazard
-        .endm
-
-        .macro  local_irq_disable reg=t0
-        mfc0    \reg, CP0_STATUS
-        ori     \reg, \reg, 1
-        xori    \reg, \reg, 1
-        mtc0    \reg, CP0_STATUS
-        irq_disable_hazard
-        .endm
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-/*
- * Temporary until all gas have MT ASE support
- */
-        .macro  DMT     reg=0
-        .word   0x41600bc1 | (\reg << 16)
-        .endm
-
-        .macro  EMT     reg=0
-        .word   0x41600be1 | (\reg << 16)
-        .endm
-
-        .macro  DVPE    reg=0
-        .word   0x41600001 | (\reg << 16)
-        .endm
-
-        .macro  EVPE    reg=0
-        .word   0x41600021 | (\reg << 16)
-        .endm
-
-        .macro  MFTR    rt=0, rd=0, u=0, sel=0
-         .word  0x41000000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
-        .endm
-
-        .macro  MTTR    rt=0, rd=0, u=0, sel=0
-         .word  0x41800000 | (\rt << 16) | (\rd << 11) | (\u << 5) | (\sel)
-        .endm
-
-#endif /* _ASM_ASMMACRO_H */
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
deleted file mode 100644
index 1232be3885b0..000000000000
--- a/include/asm-mips/atomic.h
+++ /dev/null
@@ -1,801 +0,0 @@
-/*
- * Atomic operations that C can't guarantee us.  Useful for
- * resource counting etc..
- *
- * But use these as seldom as possible since they are much more slower
- * than regular operations.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 97, 99, 2000, 03, 04, 06 by Ralf Baechle
- */
-#ifndef _ASM_ATOMIC_H
-#define _ASM_ATOMIC_H
-
-#include <linux/irqflags.h>
-#include <asm/barrier.h>
-#include <asm/cpu-features.h>
-#include <asm/war.h>
-#include <asm/system.h>
-
-typedef struct { volatile int counter; } atomic_t;
-
-#define ATOMIC_INIT(i)    { (i) }
-
-/*
- * atomic_read - read atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically reads the value of @v.
- */
-#define atomic_read(v)          ((v)->counter)
-
-/*
- * atomic_set - set atomic variable
- * @v: pointer of type atomic_t
- * @i: required value
- *
- * Atomically sets the value of @v to @i.
- */
-#define atomic_set(v, i)                ((v)->counter = (i))
-
-/*
- * atomic_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic_t
- *
- * Atomically adds @i to @v.
- */
-static __inline__ void atomic_add(int i, atomic_t * v)
-{
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_add            \n"
-                "       addu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_add            \n"
-                "       addu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                v->counter += i;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * atomic_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v.
- */
-static __inline__ void atomic_sub(int i, atomic_t * v)
-{
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_sub            \n"
-                "       subu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %1          # atomic_sub            \n"
-                "       subu    %0, %2                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                v->counter -= i;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * Same as above, but return the result value
- */
-static __inline__ int atomic_add_return(int i, atomic_t * v)
-{
-        unsigned long result;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_add_return     \n"
-                "       addu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_add_return     \n"
-                "       addu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                result = v->counter;
-                result += i;
-                v->counter = result;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return result;
-}
-
-static __inline__ int atomic_sub_return(int i, atomic_t * v)
-{
-        unsigned long result;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_sub_return     \n"
-                "       subu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_sub_return     \n"
-                "       subu    %0, %1, %3                              \n"
-                "       sc      %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                result = v->counter;
-                result -= i;
-                v->counter = result;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return result;
-}
-
-/*
- * atomic_sub_if_positive - conditionally subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically test @v and subtract @i if @v is greater or equal than @i.
- * The function returns the old value of @v minus @i.
- */
-static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
-{
-        unsigned long result;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
-                "       subu    %0, %1, %3                              \n"
-                "       bltz    %0, 1f                                  \n"
-                "       sc      %0, %2                                  \n"
-                "       .set    noreorder                               \n"
-                "       beqzl   %0, 1b                                  \n"
-                "        subu   %0, %1, %3                              \n"
-                "       .set    reorder                                 \n"
-                "1:                                                     \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %1, %2          # atomic_sub_if_positive\n"
-                "       subu    %0, %1, %3                              \n"
-                "       bltz    %0, 1f                                  \n"
-                "       sc      %0, %2                                  \n"
-                "       .set    noreorder                               \n"
-                "       beqz    %0, 2f                                  \n"
-                "        subu   %0, %1, %3                              \n"
-                "       .set    reorder                                 \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "1:                                                     \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                result = v->counter;
-                result -= i;
-                if (result >= 0)
-                        v->counter = result;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return result;
-}
-
-#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
-
-/**
- * atomic_add_unless - add unless the number is a given value
- * @v: pointer of type atomic_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
-{
-        int c, old;
-        c = atomic_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
-
-#define atomic_dec_return(v) atomic_sub_return(1, (v))
-#define atomic_inc_return(v) atomic_add_return(1, (v))
-
-/*
- * atomic_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_sub_and_test(i, v) (atomic_sub_return((i), (v)) == 0)
-
-/*
- * atomic_inc_and_test - increment and test
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
-
-/*
- * atomic_dec_and_test - decrement by 1 and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
-
-/*
- * atomic_dec_if_positive - decrement by 1 if old value positive
- * @v: pointer of type atomic_t
- */
-#define atomic_dec_if_positive(v)       atomic_sub_if_positive(1, v)
-
-/*
- * atomic_inc - increment atomic variable
- * @v: pointer of type atomic_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic_inc(v) atomic_add(1, (v))
-
-/*
- * atomic_dec - decrement and test
- * @v: pointer of type atomic_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic_dec(v) atomic_sub(1, (v))
-
-/*
- * atomic_add_negative - add and test if negative
- * @v: pointer of type atomic_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define atomic_add_negative(i, v) (atomic_add_return(i, (v)) < 0)
-
-#ifdef CONFIG_64BIT
-
-typedef struct { volatile long counter; } atomic64_t;
-
-#define ATOMIC64_INIT(i)    { (i) }
-
-/*
- * atomic64_read - read atomic variable
- * @v: pointer of type atomic64_t
- *
- */
-#define atomic64_read(v)        ((v)->counter)
-
-/*
- * atomic64_set - set atomic variable
- * @v: pointer of type atomic64_t
- * @i: required value
- */
-#define atomic64_set(v, i)      ((v)->counter = (i))
-
-/*
- * atomic64_add - add integer to atomic variable
- * @i: integer value to add
- * @v: pointer of type atomic64_t
- *
- * Atomically adds @i to @v.
- */
-static __inline__ void atomic64_add(long i, atomic64_t * v)
-{
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_add          \n"
-                "       addu    %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_add          \n"
-                "       addu    %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                v->counter += i;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * atomic64_sub - subtract the atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically subtracts @i from @v.
- */
-static __inline__ void atomic64_sub(long i, atomic64_t * v)
-{
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_sub          \n"
-                "       subu    %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %1          # atomic64_sub          \n"
-                "       subu    %0, %2                                  \n"
-                "       scd     %0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter));
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                v->counter -= i;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * Same as above, but return the result value
- */
-static __inline__ long atomic64_add_return(long i, atomic64_t * v)
-{
-        unsigned long result;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_add_return   \n"
-                "       addu    %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_add_return   \n"
-                "       addu    %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                result = v->counter;
-                result += i;
-                v->counter = result;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return result;
-}
-
-static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
-{
-        unsigned long result;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_sub_return   \n"
-                "       subu    %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_sub_return   \n"
-                "       subu    %0, %1, %3                              \n"
-                "       scd     %0, %2                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                result = v->counter;
-                result -= i;
-                v->counter = result;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return result;
-}
-
-/*
- * atomic64_sub_if_positive - conditionally subtract integer from atomic variable
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically test @v and subtract @i if @v is greater or equal than @i.
- * The function returns the old value of @v minus @i.
- */
-static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
-{
-        unsigned long result;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
-                "       dsubu   %0, %1, %3                              \n"
-                "       bltz    %0, 1f                                  \n"
-                "       scd     %0, %2                                  \n"
-                "       .set    noreorder                               \n"
-                "       beqzl   %0, 1b                                  \n"
-                "        dsubu  %0, %1, %3                              \n"
-                "       .set    reorder                                 \n"
-                "1:                                                     \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %1, %2          # atomic64_sub_if_positive\n"
-                "       dsubu   %0, %1, %3                              \n"
-                "       bltz    %0, 1f                                  \n"
-                "       scd     %0, %2                                  \n"
-                "       .set    noreorder                               \n"
-                "       beqz    %0, 2f                                  \n"
-                "        dsubu  %0, %1, %3                              \n"
-                "       .set    reorder                                 \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "1:                                                     \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (v->counter)
-                : "Ir" (i), "m" (v->counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                result = v->counter;
-                result -= i;
-                if (result >= 0)
-                        v->counter = result;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return result;
-}
-
-#define atomic64_cmpxchg(v, o, n) \
-        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
-#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
-
-/**
- * atomic64_add_unless - add unless the number is a given value
- * @v: pointer of type atomic64_t
- * @a: the amount to add to v...
- * @u: ...unless v is equal to u.
- *
- * Atomically adds @a to @v, so long as it was not @u.
- * Returns non-zero if @v was not @u, and zero otherwise.
- */
-static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
-{
-        long c, old;
-        c = atomic64_read(v);
-        for (;;) {
-                if (unlikely(c == (u)))
-                        break;
-                old = atomic64_cmpxchg((v), c, c + (a));
-                if (likely(old == c))
-                        break;
-                c = old;
-        }
-        return c != (u);
-}
-
-#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
-
-#define atomic64_dec_return(v) atomic64_sub_return(1, (v))
-#define atomic64_inc_return(v) atomic64_add_return(1, (v))
-
-/*
- * atomic64_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @v: pointer of type atomic64_t
- *
- * Atomically subtracts @i from @v and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define atomic64_sub_and_test(i, v) (atomic64_sub_return((i), (v)) == 0)
-
-/*
- * atomic64_inc_and_test - increment and test
- * @v: pointer of type atomic64_t
- *
- * Atomically increments @v by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define atomic64_inc_and_test(v) (atomic64_inc_return(v) == 0)
-
-/*
- * atomic64_dec_and_test - decrement by 1 and test
- * @v: pointer of type atomic64_t
- *
- * Atomically decrements @v by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-#define atomic64_dec_and_test(v) (atomic64_sub_return(1, (v)) == 0)
-
-/*
- * atomic64_dec_if_positive - decrement by 1 if old value positive
- * @v: pointer of type atomic64_t
- */
-#define atomic64_dec_if_positive(v)     atomic64_sub_if_positive(1, v)
-
-/*
- * atomic64_inc - increment atomic variable
- * @v: pointer of type atomic64_t
- *
- * Atomically increments @v by 1.
- */
-#define atomic64_inc(v) atomic64_add(1, (v))
-
-/*
- * atomic64_dec - decrement and test
- * @v: pointer of type atomic64_t
- *
- * Atomically decrements @v by 1.
- */
-#define atomic64_dec(v) atomic64_sub(1, (v))
-
-/*
- * atomic64_add_negative - add and test if negative
- * @v: pointer of type atomic64_t
- * @i: integer value to add
- *
- * Atomically adds @i to @v and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define atomic64_add_negative(i, v) (atomic64_add_return(i, (v)) < 0)
-
-#endif /* CONFIG_64BIT */
-
-/*
- * atomic*_return operations are serializing but not the non-*_return
- * versions.
- */
-#define smp_mb__before_atomic_dec()     smp_llsc_mb()
-#define smp_mb__after_atomic_dec()      smp_llsc_mb()
-#define smp_mb__before_atomic_inc()     smp_llsc_mb()
-#define smp_mb__after_atomic_inc()      smp_llsc_mb()
-
-#include <asm-generic/atomic.h>
-
-#endif /* _ASM_ATOMIC_H */
diff --git a/include/asm-mips/auxvec.h b/include/asm-mips/auxvec.h
deleted file mode 100644
index 7cf7f2d21943..000000000000
--- a/include/asm-mips/auxvec.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef _ASM_AUXVEC_H
-#define _ASM_AUXVEC_H
-
-#endif /* _ASM_AUXVEC_H */
diff --git a/include/asm-mips/barrier.h b/include/asm-mips/barrier.h
deleted file mode 100644
index 8e9ac313ca3b..000000000000
--- a/include/asm-mips/barrier.h
+++ /dev/null
@@ -1,155 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006 by Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_BARRIER_H
-#define __ASM_BARRIER_H
-
-/*
- * read_barrier_depends - Flush all pending reads that subsequents reads
- * depend on.
- *
- * No data-dependent reads from memory-like regions are ever reordered
- * over this barrier.  All reads preceding this primitive are guaranteed
- * to access memory (but not necessarily other CPUs' caches) before any
- * reads following this primitive that depend on the data return by
- * any of the preceding reads.  This primitive is much lighter weight than
- * rmb() on most CPUs, and is never heavier weight than is
- * rmb().
- *
- * These ordering constraints are respected by both the local CPU
- * and the compiler.
- *
- * Ordering is not guaranteed by anything other than these primitives,
- * not even by data dependencies.  See the documentation for
- * memory_barrier() for examples and URLs to more information.
- *
- * For example, the following code would force ordering (the initial
- * value of "a" is zero, "b" is one, and "p" is "&a"):
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      b = 2;
- *      memory_barrier();
- *      p = &b;                         q = p;
- *                                      read_barrier_depends();
- *                                      d = *q;
- * </programlisting>
- *
- * because the read of "*q" depends on the read of "p" and these
- * two reads are separated by a read_barrier_depends().  However,
- * the following code, with the same initial values for "a" and "b":
- *
- * <programlisting>
- *      CPU 0                           CPU 1
- *
- *      a = 2;
- *      memory_barrier();
- *      b = 3;                          y = b;
- *                                      read_barrier_depends();
- *                                      x = a;
- * </programlisting>
- *
- * does not enforce ordering, since there is no data dependency between
- * the read of "a" and the read of "b".  Therefore, on some CPUs, such
- * as Alpha, "y" could be set to 3 and "x" to 0.  Use rmb()
- * in cases like this where there are no data dependencies.
- */
-
-#define read_barrier_depends()          do { } while(0)
-#define smp_read_barrier_depends()      do { } while(0)
-
-#ifdef CONFIG_CPU_HAS_SYNC
-#define __sync()                                \
-        __asm__ __volatile__(                   \
-                ".set   push\n\t"               \
-                ".set   noreorder\n\t"          \
-                ".set   mips2\n\t"              \
-                "sync\n\t"                      \
-                ".set   pop"                    \
-                : /* no output */               \
-                : /* no input */                \
-                : "memory")
-#else
-#define __sync()        do { } while(0)
-#endif
-
-#define __fast_iob()                            \
-        __asm__ __volatile__(                   \
-                ".set   push\n\t"               \
-                ".set   noreorder\n\t"          \
-                "lw     $0,%0\n\t"              \
-                "nop\n\t"                       \
-                ".set   pop"                    \
-                : /* no output */               \
-                : "m" (*(int *)CKSEG1)          \
-                : "memory")
-
-#define fast_wmb()      __sync()
-#define fast_rmb()      __sync()
-#define fast_mb()       __sync()
-#ifdef CONFIG_SGI_IP28
-#define fast_iob()                              \
-        __asm__ __volatile__(                   \
-                ".set   push\n\t"               \
-                ".set   noreorder\n\t"          \
-                "lw     $0,%0\n\t"              \
-                "sync\n\t"                      \
-                "lw     $0,%0\n\t"              \
-                ".set   pop"                    \
-                : /* no output */               \
-                : "m" (*(int *)CKSEG1ADDR(0x1fa00004)) \
-                : "memory")
-#else
-#define fast_iob()                              \
-        do {                                    \
-                __sync();                       \
-                __fast_iob();                   \
-        } while (0)
-#endif
-
-#ifdef CONFIG_CPU_HAS_WB
-
-#include <asm/wbflush.h>
-
-#define wmb()           fast_wmb()
-#define rmb()           fast_rmb()
-#define mb()            wbflush()
-#define iob()           wbflush()
-
-#else /* !CONFIG_CPU_HAS_WB */
-
-#define wmb()           fast_wmb()
-#define rmb()           fast_rmb()
-#define mb()            fast_mb()
-#define iob()           fast_iob()
-
-#endif /* !CONFIG_CPU_HAS_WB */
-
-#if defined(CONFIG_WEAK_ORDERING) && defined(CONFIG_SMP)
-#define __WEAK_ORDERING_MB      "       sync    \n"
-#else
-#define __WEAK_ORDERING_MB      "               \n"
-#endif
-#if defined(CONFIG_WEAK_REORDERING_BEYOND_LLSC) && defined(CONFIG_SMP)
-#define __WEAK_LLSC_MB          "       sync    \n"
-#else
-#define __WEAK_LLSC_MB          "               \n"
-#endif
-
-#define smp_mb()        __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-#define smp_rmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-#define smp_wmb()       __asm__ __volatile__(__WEAK_ORDERING_MB : : :"memory")
-
-#define set_mb(var, value) \
-        do { var = value; smp_mb(); } while (0)
-
-#define smp_llsc_mb()   __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define smp_llsc_rmb()  __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-#define smp_llsc_wmb()  __asm__ __volatile__(__WEAK_LLSC_MB : : :"memory")
-
-#endif /* __ASM_BARRIER_H */
diff --git a/include/asm-mips/bcache.h b/include/asm-mips/bcache.h
deleted file mode 100644
index 0ba9d6ef76a7..000000000000
--- a/include/asm-mips/bcache.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1997, 1999 by Ralf Baechle
- * Copyright (c) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_BCACHE_H
-#define _ASM_BCACHE_H
-
-
-/* Some R4000 / R4400 / R4600 / R5000 machines may have a non-dma-coherent,
-   chipset implemented caches.  On machines with other CPUs the CPU does the
-   cache thing itself. */
-struct bcache_ops {
-        void (*bc_enable)(void);
-        void (*bc_disable)(void);
-        void (*bc_wback_inv)(unsigned long page, unsigned long size);
-        void (*bc_inv)(unsigned long page, unsigned long size);
-};
-
-extern void indy_sc_init(void);
-
-#ifdef CONFIG_BOARD_SCACHE
-
-extern struct bcache_ops *bcops;
-
-static inline void bc_enable(void)
-{
-        bcops->bc_enable();
-}
-
-static inline void bc_disable(void)
-{
-        bcops->bc_disable();
-}
-
-static inline void bc_wback_inv(unsigned long page, unsigned long size)
-{
-        bcops->bc_wback_inv(page, size);
-}
-
-static inline void bc_inv(unsigned long page, unsigned long size)
-{
-        bcops->bc_inv(page, size);
-}
-
-#else /* !defined(CONFIG_BOARD_SCACHE) */
-
-/* Not R4000 / R4400 / R4600 / R5000.  */
-
-#define bc_enable() do { } while (0)
-#define bc_disable() do { } while (0)
-#define bc_wback_inv(page, size) do { } while (0)
-#define bc_inv(page, size) do { } while (0)
-
-#endif /* !defined(CONFIG_BOARD_SCACHE) */
-
-#endif /* _ASM_BCACHE_H */
diff --git a/include/asm-mips/bitops.h b/include/asm-mips/bitops.h
deleted file mode 100644
index 49df8c4c9d25..000000000000
--- a/include/asm-mips/bitops.h
+++ /dev/null
@@ -1,672 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1994 - 1997, 99, 2000, 06, 07  Ralf Baechle (ralf@linux-mips.org)
- * Copyright (c) 1999, 2000  Silicon Graphics, Inc.
- */
-#ifndef _ASM_BITOPS_H
-#define _ASM_BITOPS_H
-
-#ifndef _LINUX_BITOPS_H
-#error only <linux/bitops.h> can be included directly
-#endif
-
-#include <linux/compiler.h>
-#include <linux/irqflags.h>
-#include <linux/types.h>
-#include <asm/barrier.h>
-#include <asm/bug.h>
-#include <asm/byteorder.h>              /* sigh ... */
-#include <asm/cpu-features.h>
-#include <asm/sgidefs.h>
-#include <asm/war.h>
-
-#if _MIPS_SZLONG == 32
-#define SZLONG_LOG 5
-#define SZLONG_MASK 31UL
-#define __LL            "ll     "
-#define __SC            "sc     "
-#define __INS           "ins    "
-#define __EXT           "ext    "
-#elif _MIPS_SZLONG == 64
-#define SZLONG_LOG 6
-#define SZLONG_MASK 63UL
-#define __LL            "lld    "
-#define __SC            "scd    "
-#define __INS           "dins    "
-#define __EXT           "dext    "
-#endif
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()      smp_llsc_mb()
-#define smp_mb__after_clear_bit()       smp_llsc_mb()
-
-/*
- * set_bit - Atomically set a bit in memory
- * @nr: the bit to set
- * @addr: the address to start counting from
- *
- * This function is atomic and may not be reordered.  See __set_bit()
- * if you do not require the atomic guarantees.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void set_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-        unsigned short bit = nr & SZLONG_MASK;
-        unsigned long temp;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       or      %0, %2                                  \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
-#ifdef CONFIG_CPU_MIPSR2
-        } else if (__builtin_constant_p(bit)) {
-                __asm__ __volatile__(
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       " __INS "%0, %4, %2, 1                          \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m), "r" (~0));
-#endif /* CONFIG_CPU_MIPSR2 */
-        } else if (cpu_has_llsc) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # set_bit       \n"
-                "       or      %0, %2                                  \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                *a |= mask;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * clear_bit - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and may not be reordered.  However, it does
- * not contain a memory barrier, so if it is used for locking purposes,
- * you should call smp_mb__before_clear_bit() and/or smp_mb__after_clear_bit()
- * in order to ensure changes are visible on other processors.
- */
-static inline void clear_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-        unsigned short bit = nr & SZLONG_MASK;
-        unsigned long temp;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       and     %0, %2                                  \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << bit)), "m" (*m));
-#ifdef CONFIG_CPU_MIPSR2
-        } else if (__builtin_constant_p(bit)) {
-                __asm__ __volatile__(
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       " __INS "%0, $0, %2, 1                          \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (bit), "m" (*m));
-#endif /* CONFIG_CPU_MIPSR2 */
-        } else if (cpu_has_llsc) {
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1                  # clear_bit     \n"
-                "       and     %0, %2                                  \n"
-                "       " __SC "%0, %1                                  \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (~(1UL << bit)), "m" (*m));
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                *a &= ~mask;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * clear_bit_unlock - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * clear_bit() is atomic and implies release semantics before the memory
- * operation. It can be used for an unlock.
- */
-static inline void clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
-{
-        smp_mb__before_clear_bit();
-        clear_bit(nr, addr);
-}
-
-/*
- * change_bit - Toggle a bit in memory
- * @nr: Bit to change
- * @addr: Address to start counting from
- *
- * change_bit() is atomic and may not be reordered.
- * Note that @nr may be almost arbitrarily large; this function is not
- * restricted to acting on a single-word quantity.
- */
-static inline void change_bit(unsigned long nr, volatile unsigned long *addr)
-{
-        unsigned short bit = nr & SZLONG_MASK;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                           \n"
-                "1:     " __LL "%0, %1          # change_bit    \n"
-                "       xor     %0, %2                          \n"
-                "       " __SC  "%0, %1                         \n"
-                "       beqzl   %0, 1b                          \n"
-                "       .set    mips0                           \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
-        } else if (cpu_has_llsc) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                           \n"
-                "1:     " __LL "%0, %1          # change_bit    \n"
-                "       xor     %0, %2                          \n"
-                "       " __SC  "%0, %1                         \n"
-                "       beqz    %0, 2f                          \n"
-                "       .subsection 2                           \n"
-                "2:     b       1b                              \n"
-                "       .previous                               \n"
-                "       .set    mips0                           \n"
-                : "=&r" (temp), "=m" (*m)
-                : "ir" (1UL << bit), "m" (*m));
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                *a ^= mask;
-                raw_local_irq_restore(flags);
-        }
-}
-
-/*
- * test_and_set_bit - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_set_bit(unsigned long nr,
-        volatile unsigned long *addr)
-{
-        unsigned short bit = nr & SZLONG_MASK;
-        unsigned long res;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       and     %2, %0, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a |= mask;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return res != 0;
-}
-
-/*
- * test_and_set_bit_lock - Set a bit and return its old value
- * @nr: Bit to set
- * @addr: Address to count from
- *
- * This operation is atomic and implies acquire ordering semantics
- * after the memory operation.
- */
-static inline int test_and_set_bit_lock(unsigned long nr,
-        volatile unsigned long *addr)
-{
-        unsigned short bit = nr & SZLONG_MASK;
-        unsigned long res;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       and     %2, %0, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL "%0, %1          # test_and_set_bit      \n"
-                "       or      %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a |= mask;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return res != 0;
-}
-/*
- * test_and_clear_bit - Clear a bit and return its old value
- * @nr: Bit to clear
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_clear_bit(unsigned long nr,
-        volatile unsigned long *addr)
-{
-        unsigned short bit = nr & SZLONG_MASK;
-        unsigned long res;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       or      %2, %0, %3                              \n"
-                "       xor     %2, %3                                  \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       and     %2, %0, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-#ifdef CONFIG_CPU_MIPSR2
-        } else if (__builtin_constant_p(nr)) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       " __EXT "%2, %0, %3, 1                          \n"
-                "       " __INS "%0, $0, %3, 1                          \n"
-                "       " __SC  "%0, %1                                 \n"
-                "       beqz    %0, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "ir" (bit), "m" (*m)
-                : "memory");
-#endif
-        } else if (cpu_has_llsc) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_clear_bit    \n"
-                "       or      %2, %0, %3                              \n"
-                "       xor     %2, %3                                  \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a &= ~mask;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return res != 0;
-}
-
-/*
- * test_and_change_bit - Change a bit and return its old value
- * @nr: Bit to change
- * @addr: Address to count from
- *
- * This operation is atomic and cannot be reordered.
- * It also implies a memory barrier.
- */
-static inline int test_and_change_bit(unsigned long nr,
-        volatile unsigned long *addr)
-{
-        unsigned short bit = nr & SZLONG_MASK;
-        unsigned long res;
-
-        smp_llsc_mb();
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
-                "       xor     %2, %0, %3                              \n"
-                "       " __SC  "%2, %1                                 \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       and     %2, %0, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long *m = ((unsigned long *) addr) + (nr >> SZLONG_LOG);
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    push                                    \n"
-                "       .set    noreorder                               \n"
-                "       .set    mips3                                   \n"
-                "1:     " __LL  "%0, %1         # test_and_change_bit   \n"
-                "       xor     %2, %0, %3                              \n"
-                "       " __SC  "\t%2, %1                               \n"
-                "       beqz    %2, 2f                                  \n"
-                "        and    %2, %0, %3                              \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    pop                                     \n"
-                : "=&r" (temp), "=m" (*m), "=&r" (res)
-                : "r" (1UL << bit), "m" (*m)
-                : "memory");
-        } else {
-                volatile unsigned long *a = addr;
-                unsigned long mask;
-                unsigned long flags;
-
-                a += nr >> SZLONG_LOG;
-                mask = 1UL << bit;
-                raw_local_irq_save(flags);
-                res = (mask & *a);
-                *a ^= mask;
-                raw_local_irq_restore(flags);
-        }
-
-        smp_llsc_mb();
-
-        return res != 0;
-}
-
-#include <asm-generic/bitops/non-atomic.h>
-
-/*
- * __clear_bit_unlock - Clears a bit in memory
- * @nr: Bit to clear
- * @addr: Address to start counting from
- *
- * __clear_bit() is non-atomic and implies release semantics before the memory
- * operation. It can be used for an unlock if no other CPUs can concurrently
- * modify other bits in the word.
- */
-static inline void __clear_bit_unlock(unsigned long nr, volatile unsigned long *addr)
-{
-        smp_mb();
-        __clear_bit(nr, addr);
-}
-
-#if defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64)
-
-/*
- * Return the bit position (0..63) of the most significant 1 bit in a word
- * Returns -1 if no 1 bit exists
- */
-static inline unsigned long __fls(unsigned long x)
-{
-        int lz;
-
-        if (sizeof(x) == 4) {
-                __asm__(
-                "       .set    push                                    \n"
-                "       .set    mips32                                  \n"
-                "       clz     %0, %1                                  \n"
-                "       .set    pop                                     \n"
-                : "=r" (lz)
-                : "r" (x));
-
-                return 31 - lz;
-        }
-
-        BUG_ON(sizeof(x) != 8);
-
-        __asm__(
-        "       .set    push                                            \n"
-        "       .set    mips64                                          \n"
-        "       dclz    %0, %1                                          \n"
-        "       .set    pop                                             \n"
-        : "=r" (lz)
-        : "r" (x));
-
-        return 63 - lz;
-}
-
-/*
- * __ffs - find first bit in word.
- * @word: The word to search
- *
- * Returns 0..SZLONG-1
- * Undefined if no bit exists, so code should check against 0 first.
- */
-static inline unsigned long __ffs(unsigned long word)
-{
-        return __fls(word & -word);
-}
-
-/*
- * fls - find last bit set.
- * @word: The word to search
- *
- * This is defined the same way as ffs.
- * Note fls(0) = 0, fls(1) = 1, fls(0x80000000) = 32.
- */
-static inline int fls(int word)
-{
-        __asm__("clz %0, %1" : "=r" (word) : "r" (word));
-
-        return 32 - word;
-}
-
-#if defined(CONFIG_64BIT) && defined(CONFIG_CPU_MIPS64)
-static inline int fls64(__u64 word)
-{
-        __asm__("dclz %0, %1" : "=r" (word) : "r" (word));
-
-        return 64 - word;
-}
-#else
-#include <asm-generic/bitops/fls64.h>
-#endif
-
-/*
- * ffs - find first bit set.
- * @word: The word to search
- *
- * This is defined the same way as
- * the libc and compiler builtin ffs routines, therefore
- * differs in spirit from the above ffz (man ffs).
- */
-static inline int ffs(int word)
-{
-        if (!word)
-                return 0;
-
-        return fls(word & -word);
-}
-
-#else
-
-#include <asm-generic/bitops/__ffs.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/ffs.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/fls64.h>
-
-#endif /*defined(CONFIG_CPU_MIPS32) || defined(CONFIG_CPU_MIPS64) */
-
-#include <asm-generic/bitops/ffz.h>
-#include <asm-generic/bitops/find.h>
-
-#ifdef __KERNEL__
-
-#include <asm-generic/bitops/sched.h>
-#include <asm-generic/bitops/hweight.h>
-#include <asm-generic/bitops/ext2-non-atomic.h>
-#include <asm-generic/bitops/ext2-atomic.h>
-#include <asm-generic/bitops/minix.h>
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_BITOPS_H */
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
deleted file mode 100644
index 610fe3af7a03..000000000000
--- a/include/asm-mips/bootinfo.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file COPYING in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 2003 by Ralf Baechle
- * Copyright (C) 1995, 1996 Andreas Busse
- * Copyright (C) 1995, 1996 Stoned Elipot
- * Copyright (C) 1995, 1996 Paul M. Antoine.
- */
-#ifndef _ASM_BOOTINFO_H
-#define _ASM_BOOTINFO_H
-
-#include <linux/types.h>
-#include <asm/setup.h>
-
-/*
- * The MACH_ IDs are sort of equivalent to PCI product IDs.  As such the
- * numbers do not necessarily reflect technical relations or similarities
- * between systems.
- */
-
-/*
- * Valid machtype values for group unknown
- */
-#define  MACH_UNKNOWN           0       /* whatever...                  */
-
-/*
- * Valid machtype for group DEC
- */
-#define  MACH_DSUNKNOWN         0
-#define  MACH_DS23100           1       /* DECstation 2100 or 3100      */
-#define  MACH_DS5100            2       /* DECsystem 5100               */
-#define  MACH_DS5000_200        3       /* DECstation 5000/200          */
-#define  MACH_DS5000_1XX        4       /* DECstation 5000/120, 125, 133, 150 */
-#define  MACH_DS5000_XX         5       /* DECstation 5000/20, 25, 33, 50 */
-#define  MACH_DS5000_2X0        6       /* DECstation 5000/240, 260     */
-#define  MACH_DS5400            7       /* DECsystem 5400               */
-#define  MACH_DS5500            8       /* DECsystem 5500               */
-#define  MACH_DS5800            9       /* DECsystem 5800               */
-#define  MACH_DS5900            10      /* DECsystem 5900               */
-
-/*
- * Valid machtype for group PMC-MSP
- */
-#define MACH_MSP4200_EVAL       0       /* PMC-Sierra MSP4200 Evaluation */
-#define MACH_MSP4200_GW         1       /* PMC-Sierra MSP4200 Gateway demo */
-#define MACH_MSP4200_FPGA       2       /* PMC-Sierra MSP4200 Emulation */
-#define MACH_MSP7120_EVAL       3       /* PMC-Sierra MSP7120 Evaluation */
-#define MACH_MSP7120_GW         4       /* PMC-Sierra MSP7120 Residential GW */
-#define MACH_MSP7120_FPGA       5       /* PMC-Sierra MSP7120 Emulation */
-#define MACH_MSP_OTHER        255       /* PMC-Sierra unknown board type */
-
-/*
- * Valid machtype for group Mikrotik
- */
-#define MACH_MIKROTIK_RB532     0       /* Mikrotik RouterBoard 532     */
-#define MACH_MIKROTIK_RB532A    1       /* Mikrotik RouterBoard 532A    */
-
-#define CL_SIZE                 COMMAND_LINE_SIZE
-
-extern char *system_type;
-const char *get_system_type(void);
-
-extern unsigned long mips_machtype;
-
-#define BOOT_MEM_MAP_MAX        32
-#define BOOT_MEM_RAM            1
-#define BOOT_MEM_ROM_DATA       2
-#define BOOT_MEM_RESERVED       3
-
-/*
- * A memory map that's built upon what was determined
- * or specified on the command line.
- */
-struct boot_mem_map {
-        int nr_map;
-        struct boot_mem_map_entry {
-                phys_t addr;    /* start of memory segment */
-                phys_t size;    /* size of memory segment */
-                long type;              /* type of memory segment */
-        } map[BOOT_MEM_MAP_MAX];
-};
-
-extern struct boot_mem_map boot_mem_map;
-
-extern void add_memory_region(phys_t start, phys_t size, long type);
-
-extern void prom_init(void);
-extern void prom_free_prom_memory(void);
-
-extern void free_init_pages(const char *what,
-                            unsigned long begin, unsigned long end);
-
-/*
- * Initial kernel command line, usually setup by prom_init()
- */
-extern char arcs_cmdline[CL_SIZE];
-
-/*
- * Registers a0, a1, a3 and a4 as passed to the kernel entry by firmware
- */
-extern unsigned long fw_arg0, fw_arg1, fw_arg2, fw_arg3;
-
-/*
- * Platform memory detection hook called by setup_arch
- */
-extern void plat_mem_setup(void);
-
-#endif /* _ASM_BOOTINFO_H */
diff --git a/include/asm-mips/branch.h b/include/asm-mips/branch.h
deleted file mode 100644
index 37c6857c8d4a..000000000000
--- a/include/asm-mips/branch.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 2001 by Ralf Baechle
- */
-#ifndef _ASM_BRANCH_H
-#define _ASM_BRANCH_H
-
-#include <asm/ptrace.h>
-
-static inline int delay_slot(struct pt_regs *regs)
-{
-        return regs->cp0_cause & CAUSEF_BD;
-}
-
-static inline unsigned long exception_epc(struct pt_regs *regs)
-{
-        if (!delay_slot(regs))
-                return regs->cp0_epc;
-
-        return regs->cp0_epc + 4;
-}
-
-extern int __compute_return_epc(struct pt_regs *regs);
-
-static inline int compute_return_epc(struct pt_regs *regs)
-{
-        if (!delay_slot(regs)) {
-                regs->cp0_epc += 4;
-                return 0;
-        }
-
-        return __compute_return_epc(regs);
-}
-
-#endif /* _ASM_BRANCH_H */
diff --git a/include/asm-mips/break.h b/include/asm-mips/break.h
deleted file mode 100644
index 25b980c91e7e..000000000000
--- a/include/asm-mips/break.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 2003 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef __ASM_BREAK_H
-#define __ASM_BREAK_H
-
-/*
- * The following break codes are or were in use for specific purposes in
- * other MIPS operating systems.  Linux/MIPS doesn't use all of them.  The
- * unused ones are here as placeholders; we might encounter them in
- * non-Linux/MIPS object files or make use of them in the future.
- */
-#define BRK_USERBP      0       /* User bp (used by debuggers) */
-#define BRK_KERNELBP    1       /* Break in the kernel */
-#define BRK_ABORT       2       /* Sometimes used by abort(3) to SIGIOT */
-#define BRK_BD_TAKEN    3       /* For bd slot emulation - not implemented */
-#define BRK_BD_NOTTAKEN 4       /* For bd slot emulation - not implemented */
-#define BRK_SSTEPBP     5       /* User bp (used by debuggers) */
-#define BRK_OVERFLOW    6       /* Overflow check */
-#define BRK_DIVZERO     7       /* Divide by zero check */
-#define BRK_RANGE       8       /* Range error check */
-#define BRK_STACKOVERFLOW 9     /* For Ada stackchecking */
-#define BRK_NORLD       10      /* No rld found - not used by Linux/MIPS */
-#define _BRK_THREADBP   11      /* For threads, user bp (used by debuggers) */
-#define BRK_BUG         512     /* Used by BUG() */
-#define BRK_KDB         513     /* Used in KDB_ENTER() */
-#define BRK_MULOVF      1023    /* Multiply overflow */
-
-#endif /* __ASM_BREAK_H */
diff --git a/include/asm-mips/bug.h b/include/asm-mips/bug.h
deleted file mode 100644
index 7eb63de808bc..000000000000
--- a/include/asm-mips/bug.h
+++ /dev/null
@@ -1,33 +0,0 @@
-#ifndef __ASM_BUG_H
-#define __ASM_BUG_H
-
-#include <asm/sgidefs.h>
-
-#ifdef CONFIG_BUG
-
-#include <asm/break.h>
-
-#define BUG()                                                           \
-do {                                                                    \
-        __asm__ __volatile__("break %0" : : "i" (BRK_BUG));             \
-} while (0)
-
-#define HAVE_ARCH_BUG
-
-#if (_MIPS_ISA > _MIPS_ISA_MIPS1)
-
-#define BUG_ON(condition)                                               \
-do {                                                                    \
-        __asm__ __volatile__("tne $0, %0, %1"                           \
-                             : : "r" (condition), "i" (BRK_BUG));       \
-} while (0)
-
-#define HAVE_ARCH_BUG_ON
-
-#endif /* _MIPS_ISA > _MIPS_ISA_MIPS1 */
-
-#endif
-
-#include <asm-generic/bug.h>
-
-#endif /* __ASM_BUG_H */
diff --git a/include/asm-mips/bugs.h b/include/asm-mips/bugs.h
deleted file mode 100644
index 9dc10df32078..000000000000
--- a/include/asm-mips/bugs.h
+++ /dev/null
@@ -1,53 +0,0 @@
-/*
- * This is included by init/main.c to check for architecture-dependent bugs.
- *
- * Copyright (C) 2007  Maciej W. Rozycki
- *
- * Needs:
- *      void check_bugs(void);
- */
-#ifndef _ASM_BUGS_H
-#define _ASM_BUGS_H
-
-#include <linux/bug.h>
-#include <linux/delay.h>
-
-#include <asm/cpu.h>
-#include <asm/cpu-info.h>
-
-extern int daddiu_bug;
-
-extern void check_bugs64_early(void);
-
-extern void check_bugs32(void);
-extern void check_bugs64(void);
-
-static inline void check_bugs_early(void)
-{
-#ifdef CONFIG_64BIT
-        check_bugs64_early();
-#endif
-}
-
-static inline void check_bugs(void)
-{
-        unsigned int cpu = smp_processor_id();
-
-        cpu_data[cpu].udelay_val = loops_per_jiffy;
-        check_bugs32();
-#ifdef CONFIG_64BIT
-        check_bugs64();
-#endif
-}
-
-static inline int r4k_daddiu_bug(void)
-{
-#ifdef CONFIG_64BIT
-        WARN_ON(daddiu_bug < 0);
-        return daddiu_bug != 0;
-#else
-        return 0;
-#endif
-}
-
-#endif /* _ASM_BUGS_H */
diff --git a/include/asm-mips/byteorder.h b/include/asm-mips/byteorder.h
deleted file mode 100644
index fe7dc2d59b69..000000000000
--- a/include/asm-mips/byteorder.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99, 2003 by Ralf Baechle
- */
-#ifndef _ASM_BYTEORDER_H
-#define _ASM_BYTEORDER_H
-
-#include <linux/compiler.h>
-#include <asm/types.h>
-
-#ifdef __GNUC__
-
-#ifdef CONFIG_CPU_MIPSR2
-
-static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 x)
-{
-        __asm__(
-        "       wsbh    %0, %1                  \n"
-        : "=r" (x)
-        : "r" (x));
-
-        return x;
-}
-#define __arch__swab16(x)       ___arch__swab16(x)
-
-static __inline__ __attribute_const__ __u32 ___arch__swab32(__u32 x)
-{
-        __asm__(
-        "       wsbh    %0, %1                  \n"
-        "       rotr    %0, %0, 16              \n"
-        : "=r" (x)
-        : "r" (x));
-
-        return x;
-}
-#define __arch__swab32(x)       ___arch__swab32(x)
-
-#ifdef CONFIG_CPU_MIPS64_R2
-
-static __inline__ __attribute_const__ __u64 ___arch__swab64(__u64 x)
-{
-        __asm__(
-        "       dsbh    %0, %1                  \n"
-        "       dshd    %0, %0                  \n"
-        "       drotr   %0, %0, 32              \n"
-        : "=r" (x)
-        : "r" (x));
-
-        return x;
-}
-
-#define __arch__swab64(x)       ___arch__swab64(x)
-
-#endif /* CONFIG_CPU_MIPS64_R2 */
-
-#endif /* CONFIG_CPU_MIPSR2 */
-
-#if !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#endif /* __GNUC__ */
-
-#if defined(__MIPSEB__)
-#  include <linux/byteorder/big_endian.h>
-#elif defined(__MIPSEL__)
-#  include <linux/byteorder/little_endian.h>
-#else
-#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#endif /* _ASM_BYTEORDER_H */
diff --git a/include/asm-mips/cache.h b/include/asm-mips/cache.h
deleted file mode 100644
index 37f175c42bb5..000000000000
--- a/include/asm-mips/cache.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 98, 99, 2000, 2003 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CACHE_H
-#define _ASM_CACHE_H
-
-#include <kmalloc.h>
-
-#define L1_CACHE_SHIFT          CONFIG_MIPS_L1_CACHE_SHIFT
-#define L1_CACHE_BYTES          (1 << L1_CACHE_SHIFT)
-
-#define SMP_CACHE_SHIFT         L1_CACHE_SHIFT
-#define SMP_CACHE_BYTES         L1_CACHE_BYTES
-
-#endif /* _ASM_CACHE_H */
diff --git a/include/asm-mips/cachectl.h b/include/asm-mips/cachectl.h
deleted file mode 100644
index f3ce721861d3..000000000000
--- a/include/asm-mips/cachectl.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996 by Ralf Baechle
- */
-#ifndef _ASM_CACHECTL
-#define _ASM_CACHECTL
-
-/*
- * Options for cacheflush system call
- */
-#define ICACHE  (1<<0)          /* flush instruction cache        */
-#define DCACHE  (1<<1)          /* writeback and flush data cache */
-#define BCACHE  (ICACHE|DCACHE) /* flush both caches              */
-
-/*
- * Caching modes for the cachectl(2) call
- *
- * cachectl(2) is currently not supported and returns ENOSYS.
- */
-#define CACHEABLE       0       /* make pages cacheable */
-#define UNCACHEABLE     1       /* make pages uncacheable */
-
-#endif  /* _ASM_CACHECTL */
diff --git a/include/asm-mips/cacheflush.h b/include/asm-mips/cacheflush.h
deleted file mode 100644
index d5c0f2fda51b..000000000000
--- a/include/asm-mips/cacheflush.h
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
- * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CACHEFLUSH_H
-#define _ASM_CACHEFLUSH_H
-
-/* Keep includes the same across arches.  */
-#include <linux/mm.h>
-#include <asm/cpu-features.h>
-
-/* Cache flushing:
- *
- *  - flush_cache_all() flushes entire cache
- *  - flush_cache_mm(mm) flushes the specified mm context's cache lines
- *  - flush_cache_dup mm(mm) handles cache flushing when forking
- *  - flush_cache_page(mm, vmaddr, pfn) flushes a single page
- *  - flush_cache_range(vma, start, end) flushes a range of pages
- *  - flush_icache_range(start, end) flush a range of instructions
- *  - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache
- *
- * MIPS specific flush operations:
- *
- *  - flush_cache_sigtramp() flush signal trampoline
- *  - flush_icache_all() flush the entire instruction cache
- *  - flush_data_cache_page() flushes a page from the data cache
- */
-extern void (*flush_cache_all)(void);
-extern void (*__flush_cache_all)(void);
-extern void (*flush_cache_mm)(struct mm_struct *mm);
-#define flush_cache_dup_mm(mm)  do { (void) (mm); } while (0)
-extern void (*flush_cache_range)(struct vm_area_struct *vma,
-        unsigned long start, unsigned long end);
-extern void (*flush_cache_page)(struct vm_area_struct *vma, unsigned long page, unsigned long pfn);
-extern void __flush_dcache_page(struct page *page);
-
-static inline void flush_dcache_page(struct page *page)
-{
-        if (cpu_has_dc_aliases || !cpu_has_ic_fills_f_dc)
-                __flush_dcache_page(page);
-
-}
-
-#define flush_dcache_mmap_lock(mapping)         do { } while (0)
-#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
-
-#define ARCH_HAS_FLUSH_ANON_PAGE
-extern void __flush_anon_page(struct page *, unsigned long);
-static inline void flush_anon_page(struct vm_area_struct *vma,
-        struct page *page, unsigned long vmaddr)
-{
-        if (cpu_has_dc_aliases && PageAnon(page))
-                __flush_anon_page(page, vmaddr);
-}
-
-static inline void flush_icache_page(struct vm_area_struct *vma,
-        struct page *page)
-{
-}
-
-extern void (*flush_icache_range)(unsigned long start, unsigned long end);
-
-extern void (*__flush_cache_vmap)(void);
-
-static inline void flush_cache_vmap(unsigned long start, unsigned long end)
-{
-        if (cpu_has_dc_aliases)
-                __flush_cache_vmap();
-}
-
-extern void (*__flush_cache_vunmap)(void);
-
-static inline void flush_cache_vunmap(unsigned long start, unsigned long end)
-{
-        if (cpu_has_dc_aliases)
-                __flush_cache_vunmap();
-}
-
-extern void copy_to_user_page(struct vm_area_struct *vma,
-        struct page *page, unsigned long vaddr, void *dst, const void *src,
-        unsigned long len);
-
-extern void copy_from_user_page(struct vm_area_struct *vma,
-        struct page *page, unsigned long vaddr, void *dst, const void *src,
-        unsigned long len);
-
-extern void (*flush_cache_sigtramp)(unsigned long addr);
-extern void (*flush_icache_all)(void);
-extern void (*local_flush_data_cache_page)(void * addr);
-extern void (*flush_data_cache_page)(unsigned long addr);
-
-/*
- * This flag is used to indicate that the page pointed to by a pte
- * is dirty and requires cleaning before returning it to the user.
- */
-#define PG_dcache_dirty                 PG_arch_1
-
-#define Page_dcache_dirty(page)         \
-        test_bit(PG_dcache_dirty, &(page)->flags)
-#define SetPageDcacheDirty(page)        \
-        set_bit(PG_dcache_dirty, &(page)->flags)
-#define ClearPageDcacheDirty(page)      \
-        clear_bit(PG_dcache_dirty, &(page)->flags)
-
-/* Run kernel code uncached, useful for cache probing functions. */
-unsigned long run_uncached(void *func);
-
-extern void *kmap_coherent(struct page *page, unsigned long addr);
-extern void kunmap_coherent(void);
-
-#endif /* _ASM_CACHEFLUSH_H */
diff --git a/include/asm-mips/cacheops.h b/include/asm-mips/cacheops.h
deleted file mode 100644
index 256ad2cc6eb8..000000000000
--- a/include/asm-mips/cacheops.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Cache operations for the cache instruction.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * (C) Copyright 1996, 97, 99, 2002, 03 Ralf Baechle
- * (C) Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef __ASM_CACHEOPS_H
-#define __ASM_CACHEOPS_H
-
-/*
- * Cache Operations available on all MIPS processors with R4000-style caches
- */
-#define Index_Invalidate_I      0x00
-#define Index_Writeback_Inv_D   0x01
-#define Index_Load_Tag_I        0x04
-#define Index_Load_Tag_D        0x05
-#define Index_Store_Tag_I       0x08
-#define Index_Store_Tag_D       0x09
-#if defined(CONFIG_CPU_LOONGSON2)
-#define Hit_Invalidate_I        0x00
-#else
-#define Hit_Invalidate_I        0x10
-#endif
-#define Hit_Invalidate_D        0x11
-#define Hit_Writeback_Inv_D     0x15
-
-/*
- * R4000-specific cacheops
- */
-#define Create_Dirty_Excl_D     0x0d
-#define Fill                    0x14
-#define Hit_Writeback_I         0x18
-#define Hit_Writeback_D         0x19
-
-/*
- * R4000SC and R4400SC-specific cacheops
- */
-#define Index_Invalidate_SI     0x02
-#define Index_Writeback_Inv_SD  0x03
-#define Index_Load_Tag_SI       0x06
-#define Index_Load_Tag_SD       0x07
-#define Index_Store_Tag_SI      0x0A
-#define Index_Store_Tag_SD      0x0B
-#define Create_Dirty_Excl_SD    0x0f
-#define Hit_Invalidate_SI       0x12
-#define Hit_Invalidate_SD       0x13
-#define Hit_Writeback_Inv_SD    0x17
-#define Hit_Writeback_SD        0x1b
-#define Hit_Set_Virtual_SI      0x1e
-#define Hit_Set_Virtual_SD      0x1f
-
-/*
- * R5000-specific cacheops
- */
-#define R5K_Page_Invalidate_S   0x17
-
-/*
- * RM7000-specific cacheops
- */
-#define Page_Invalidate_T       0x16
-
-/*
- * R10000-specific cacheops
- *
- * Cacheops 0x02, 0x06, 0x0a, 0x0c-0x0e, 0x16, 0x1a and 0x1e are unused.
- * Most of the _S cacheops are identical to the R4000SC _SD cacheops.
- */
-#define Index_Writeback_Inv_S   0x03
-#define Index_Load_Tag_S        0x07
-#define Index_Store_Tag_S       0x0B
-#define Hit_Invalidate_S        0x13
-#define Cache_Barrier           0x14
-#define Hit_Writeback_Inv_S     0x17
-#define Index_Load_Data_I       0x18
-#define Index_Load_Data_D       0x19
-#define Index_Load_Data_S       0x1b
-#define Index_Store_Data_I      0x1c
-#define Index_Store_Data_D      0x1d
-#define Index_Store_Data_S      0x1f
-
-#endif  /* __ASM_CACHEOPS_H */
diff --git a/include/asm-mips/checksum.h b/include/asm-mips/checksum.h
deleted file mode 100644
index 290485ac5407..000000000000
--- a/include/asm-mips/checksum.h
+++ /dev/null
@@ -1,260 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 97, 98, 99, 2001 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2001 Thiemo Seufer.
- * Copyright (C) 2002 Maciej W. Rozycki
- */
-#ifndef _ASM_CHECKSUM_H
-#define _ASM_CHECKSUM_H
-
-#include <linux/in6.h>
-
-#include <asm/uaccess.h>
-
-/*
- * computes the checksum of a memory block at buff, length len,
- * and adds in "sum" (32-bit)
- *
- * returns a 32-bit number suitable for feeding into itself
- * or csum_tcpudp_magic
- *
- * this function must be called with even lengths, except
- * for the last fragment, which may be odd
- *
- * it's best to have buff aligned on a 32-bit boundary
- */
-__wsum csum_partial(const void *buff, int len, __wsum sum);
-
-__wsum __csum_partial_copy_user(const void *src, void *dst,
-                                int len, __wsum sum, int *err_ptr);
-
-/*
- * this is a new version of the above that records errors it finds in *errp,
- * but continues and zeros the rest of the buffer.
- */
-static inline
-__wsum csum_partial_copy_from_user(const void __user *src, void *dst, int len,
-                                   __wsum sum, int *err_ptr)
-{
-        might_sleep();
-        return __csum_partial_copy_user((__force void *)src, dst,
-                                        len, sum, err_ptr);
-}
-
-/*
- * Copy and checksum to user
- */
-#define HAVE_CSUM_COPY_USER
-static inline
-__wsum csum_and_copy_to_user(const void *src, void __user *dst, int len,
-                             __wsum sum, int *err_ptr)
-{
-        might_sleep();
-        if (access_ok(VERIFY_WRITE, dst, len))
-                return __csum_partial_copy_user(src, (__force void *)dst,
-                                                len, sum, err_ptr);
-        if (len)
-                *err_ptr = -EFAULT;
-
-        return (__force __wsum)-1; /* invalid checksum */
-}
-
-/*
- * the same as csum_partial, but copies from user space (but on MIPS
- * we have just one address space, so this is identical to the above)
- */
-__wsum csum_partial_copy_nocheck(const void *src, void *dst,
-                                       int len, __wsum sum);
-
-/*
- *      Fold a partial checksum without adding pseudo headers
- */
-static inline __sum16 csum_fold(__wsum sum)
-{
-        __asm__(
-        "       .set    push            # csum_fold\n"
-        "       .set    noat            \n"
-        "       sll     $1, %0, 16      \n"
-        "       addu    %0, $1          \n"
-        "       sltu    $1, %0, $1      \n"
-        "       srl     %0, %0, 16      \n"
-        "       addu    %0, $1          \n"
-        "       xori    %0, 0xffff      \n"
-        "       .set    pop"
-        : "=r" (sum)
-        : "0" (sum));
-
-        return (__force __sum16)sum;
-}
-
-/*
- *      This is a version of ip_compute_csum() optimized for IP headers,
- *      which always checksum on 4 octet boundaries.
- *
- *      By Jorge Cwik <jorge@laser.satlink.net>, adapted for linux by
- *      Arnt Gulbrandsen.
- */
-static inline __sum16 ip_fast_csum(const void *iph, unsigned int ihl)
-{
-        const unsigned int *word = iph;
-        const unsigned int *stop = word + ihl;
-        unsigned int csum;
-        int carry;
-
-        csum = word[0];
-        csum += word[1];
-        carry = (csum < word[1]);
-        csum += carry;
-
-        csum += word[2];
-        carry = (csum < word[2]);
-        csum += carry;
-
-        csum += word[3];
-        carry = (csum < word[3]);
-        csum += carry;
-
-        word += 4;
-        do {
-                csum += *word;
-                carry = (csum < *word);
-                csum += carry;
-                word++;
-        } while (word != stop);
-
-        return csum_fold(csum);
-}
-
-static inline __wsum csum_tcpudp_nofold(__be32 saddr,
-        __be32 daddr, unsigned short len, unsigned short proto,
-        __wsum sum)
-{
-        __asm__(
-        "       .set    push            # csum_tcpudp_nofold\n"
-        "       .set    noat            \n"
-#ifdef CONFIG_32BIT
-        "       addu    %0, %2          \n"
-        "       sltu    $1, %0, %2      \n"
-        "       addu    %0, $1          \n"
-
-        "       addu    %0, %3          \n"
-        "       sltu    $1, %0, %3      \n"
-        "       addu    %0, $1          \n"
-
-        "       addu    %0, %4          \n"
-        "       sltu    $1, %0, %4      \n"
-        "       addu    %0, $1          \n"
-#endif
-#ifdef CONFIG_64BIT
-        "       daddu   %0, %2          \n"
-        "       daddu   %0, %3          \n"
-        "       daddu   %0, %4          \n"
-        "       dsll32  $1, %0, 0       \n"
-        "       daddu   %0, $1          \n"
-        "       dsra32  %0, %0, 0       \n"
-#endif
-        "       .set    pop"
-        : "=r" (sum)
-        : "0" ((__force unsigned long)daddr),
-          "r" ((__force unsigned long)saddr),
-#ifdef __MIPSEL__
-          "r" ((proto + len) << 8),
-#else
-          "r" (proto + len),
-#endif
-          "r" ((__force unsigned long)sum));
-
-        return sum;
-}
-
-/*
- * computes the checksum of the TCP/UDP pseudo-header
- * returns a 16-bit checksum, already complemented
- */
-static inline __sum16 csum_tcpudp_magic(__be32 saddr, __be32 daddr,
-                                                   unsigned short len,
-                                                   unsigned short proto,
-                                                   __wsum sum)
-{
-        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
-}
-
-/*
- * this routine is used for miscellaneous IP-like checksums, mainly
- * in icmp.c
- */
-static inline __sum16 ip_compute_csum(const void *buff, int len)
-{
-        return csum_fold(csum_partial(buff, len, 0));
-}
-
-#define _HAVE_ARCH_IPV6_CSUM
-static __inline__ __sum16 csum_ipv6_magic(const struct in6_addr *saddr,
-                                          const struct in6_addr *daddr,
-                                          __u32 len, unsigned short proto,
-                                          __wsum sum)
-{
-        __asm__(
-        "       .set    push            # csum_ipv6_magic\n"
-        "       .set    noreorder       \n"
-        "       .set    noat            \n"
-        "       addu    %0, %5          # proto (long in network byte order)\n"
-        "       sltu    $1, %0, %5      \n"
-        "       addu    %0, $1          \n"
-
-        "       addu    %0, %6          # csum\n"
-        "       sltu    $1, %0, %6      \n"
-        "       lw      %1, 0(%2)       # four words source address\n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 4(%2)       \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 8(%2)       \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 12(%2)      \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 0(%3)       \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 4(%3)       \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 8(%3)       \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       lw      %1, 12(%3)      \n"
-        "       addu    %0, $1          \n"
-        "       addu    %0, %1          \n"
-        "       sltu    $1, %0, %1      \n"
-
-        "       addu    %0, $1          # Add final carry\n"
-        "       .set    pop"
-        : "=r" (sum), "=r" (proto)
-        : "r" (saddr), "r" (daddr),
-          "0" (htonl(len)), "1" (htonl(proto)), "r" (sum));
-
-        return csum_fold(sum);
-}
-
-#endif /* _ASM_CHECKSUM_H */
diff --git a/include/asm-mips/cmp.h b/include/asm-mips/cmp.h
deleted file mode 100644
index 89a73fb93ae6..000000000000
--- a/include/asm-mips/cmp.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#ifndef _ASM_CMP_H
-#define _ASM_CMP_H
-
-/*
- * Definitions for CMP multitasking on MIPS cores
- */
-struct task_struct;
-
-extern void cmp_smp_setup(void);
-extern void cmp_smp_finish(void);
-extern void cmp_boot_secondary(int cpu, struct task_struct *t);
-extern void cmp_init_secondary(void);
-extern void cmp_cpus_done(void);
-extern void cmp_prepare_cpus(unsigned int max_cpus);
-
-/* This is platform specific */
-extern void cmp_send_ipi(int cpu, unsigned int action);
-#endif /*  _ASM_CMP_H */
diff --git a/include/asm-mips/cmpxchg.h b/include/asm-mips/cmpxchg.h
deleted file mode 100644
index 4a812c3ceb90..000000000000
--- a/include/asm-mips/cmpxchg.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 06, 07 by Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_CMPXCHG_H
-#define __ASM_CMPXCHG_H
-
-#include <linux/irqflags.h>
-
-#define __HAVE_ARCH_CMPXCHG 1
-
-#define __cmpxchg_asm(ld, st, m, old, new)                              \
-({                                                                      \
-        __typeof(*(m)) __ret;                                           \
-                                                                        \
-        if (cpu_has_llsc && R10000_LLSC_WAR) {                          \
-                __asm__ __volatile__(                                   \
-                "       .set    push                            \n"     \
-                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
-                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
-                "       bne     %0, %z3, 2f                     \n"     \
-                "       .set    mips0                           \n"     \
-                "       move    $1, %z4                         \n"     \
-                "       .set    mips3                           \n"     \
-                "       " st "  $1, %1                          \n"     \
-                "       beqzl   $1, 1b                          \n"     \
-                "2:                                             \n"     \
-                "       .set    pop                             \n"     \
-                : "=&r" (__ret), "=R" (*m)                              \
-                : "R" (*m), "Jr" (old), "Jr" (new)                      \
-                : "memory");                                            \
-        } else if (cpu_has_llsc) {                                      \
-                __asm__ __volatile__(                                   \
-                "       .set    push                            \n"     \
-                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
-                "1:     " ld "  %0, %2          # __cmpxchg_asm \n"     \
-                "       bne     %0, %z3, 2f                     \n"     \
-                "       .set    mips0                           \n"     \
-                "       move    $1, %z4                         \n"     \
-                "       .set    mips3                           \n"     \
-                "       " st "  $1, %1                          \n"     \
-                "       beqz    $1, 3f                          \n"     \
-                "2:                                             \n"     \
-                "       .subsection 2                           \n"     \
-                "3:     b       1b                              \n"     \
-                "       .previous                               \n"     \
-                "       .set    pop                             \n"     \
-                : "=&r" (__ret), "=R" (*m)                              \
-                : "R" (*m), "Jr" (old), "Jr" (new)                      \
-                : "memory");                                            \
-        } else {                                                        \
-                unsigned long __flags;                                  \
-                                                                        \
-                raw_local_irq_save(__flags);                            \
-                __ret = *m;                                             \
-                if (__ret == old)                                       \
-                        *m = new;                                       \
-                raw_local_irq_restore(__flags);                         \
-        }                                                               \
-                                                                        \
-        __ret;                                                          \
-})
-
-/*
- * This function doesn't exist, so you'll get a linker error
- * if something tries to do an invalid cmpxchg().
- */
-extern void __cmpxchg_called_with_bad_pointer(void);
-
-#define __cmpxchg(ptr, old, new, barrier)                               \
-({                                                                      \
-        __typeof__(ptr) __ptr = (ptr);                                  \
-        __typeof__(*(ptr)) __old = (old);                               \
-        __typeof__(*(ptr)) __new = (new);                               \
-        __typeof__(*(ptr)) __res = 0;                                   \
-                                                                        \
-        barrier;                                                        \
-                                                                        \
-        switch (sizeof(*(__ptr))) {                                     \
-        case 4:                                                         \
-                __res = __cmpxchg_asm("ll", "sc", __ptr, __old, __new); \
-                break;                                                  \
-        case 8:                                                         \
-                if (sizeof(long) == 8) {                                \
-                        __res = __cmpxchg_asm("lld", "scd", __ptr,      \
-                                           __old, __new);               \
-                        break;                                          \
-                }                                                       \
-        default:                                                        \
-                __cmpxchg_called_with_bad_pointer();                    \
-                break;                                                  \
-        }                                                               \
-                                                                        \
-        barrier;                                                        \
-                                                                        \
-        __res;                                                          \
-})
-
-#define cmpxchg(ptr, old, new)          __cmpxchg(ptr, old, new, smp_llsc_mb())
-#define cmpxchg_local(ptr, old, new)    __cmpxchg(ptr, old, new, )
-
-#define cmpxchg64(ptr, o, n)                                            \
-  ({                                                                    \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
-        cmpxchg((ptr), (o), (n));                                       \
-  })
-
-#ifdef CONFIG_64BIT
-#define cmpxchg64_local(ptr, o, n)                                      \
-  ({                                                                    \
-        BUILD_BUG_ON(sizeof(*(ptr)) != 8);                              \
-        cmpxchg_local((ptr), (o), (n));                                 \
-  })
-#else
-#include <asm-generic/cmpxchg-local.h>
-#define cmpxchg64_local(ptr, o, n) __cmpxchg64_local_generic((ptr), (o), (n))
-#endif
-
-#endif /* __ASM_CMPXCHG_H */
diff --git a/include/asm-mips/compat-signal.h b/include/asm-mips/compat-signal.h
deleted file mode 100644
index 368a99e5c3e1..000000000000
--- a/include/asm-mips/compat-signal.h
+++ /dev/null
@@ -1,119 +0,0 @@
-#ifndef __ASM_COMPAT_SIGNAL_H
-#define __ASM_COMPAT_SIGNAL_H
-
-#include <linux/bug.h>
-#include <linux/compat.h>
-#include <linux/compiler.h>
-
-#include <asm/signal.h>
-#include <asm/siginfo.h>
-
-#include <asm/uaccess.h>
-
-#define SI_PAD_SIZE32   ((SI_MAX_SIZE/sizeof(int)) - 3)
-
-typedef struct compat_siginfo {
-        int si_signo;
-        int si_code;
-        int si_errno;
-
-        union {
-                int _pad[SI_PAD_SIZE32];
-
-                /* kill() */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        compat_uid_t _uid;      /* sender's uid */
-                } _kill;
-
-                /* SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        compat_uid_t _uid;      /* sender's uid */
-                        int _status;            /* exit code */
-                        compat_clock_t _utime;
-                        compat_clock_t _stime;
-                } _sigchld;
-
-                /* IRIX SIGCHLD */
-                struct {
-                        compat_pid_t _pid;      /* which child */
-                        compat_clock_t _utime;
-                        int _status;            /* exit code */
-                        compat_clock_t _stime;
-                } _irix_sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        s32 _addr; /* faulting insn/memory ref. */
-                } _sigfault;
-
-                /* SIGPOLL, SIGXFSZ (To do ...)  */
-                struct {
-                        int _band;      /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-
-                /* POSIX.1b timers */
-                struct {
-                        timer_t _tid;           /* timer id */
-                        int _overrun;           /* overrun count */
-                        compat_sigval_t _sigval;/* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        compat_pid_t _pid;      /* sender's pid */
-                        compat_uid_t _uid;      /* sender's uid */
-                        compat_sigval_t _sigval;
-                } _rt;
-
-        } _sifields;
-} compat_siginfo_t;
-
-static inline int __copy_conv_sigset_to_user(compat_sigset_t __user *d,
-        const sigset_t *s)
-{
-        int err;
-
-        BUG_ON(sizeof(*d) != sizeof(*s));
-        BUG_ON(_NSIG_WORDS != 2);
-
-        err  = __put_user(s->sig[0],       &d->sig[0]);
-        err |= __put_user(s->sig[0] >> 32, &d->sig[1]);
-        err |= __put_user(s->sig[1],       &d->sig[2]);
-        err |= __put_user(s->sig[1] >> 32, &d->sig[3]);
-
-        return err;
-}
-
-static inline int __copy_conv_sigset_from_user(sigset_t *d,
-        const compat_sigset_t __user *s)
-{
-        int err;
-        union sigset_u {
-                sigset_t        s;
-                compat_sigset_t c;
-        } *u = (union sigset_u *) d;
-
-        BUG_ON(sizeof(*d) != sizeof(*s));
-        BUG_ON(_NSIG_WORDS != 2);
-
-#ifdef CONFIG_CPU_BIG_ENDIAN
-        err  = __get_user(u->c.sig[1], &s->sig[0]);
-        err |= __get_user(u->c.sig[0], &s->sig[1]);
-        err |= __get_user(u->c.sig[3], &s->sig[2]);
-        err |= __get_user(u->c.sig[2], &s->sig[3]);
-#endif
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-        err  = __get_user(u->c.sig[0], &s->sig[0]);
-        err |= __get_user(u->c.sig[1], &s->sig[1]);
-        err |= __get_user(u->c.sig[2], &s->sig[2]);
-        err |= __get_user(u->c.sig[3], &s->sig[3]);
-#endif
-
-        return err;
-}
-
-#endif /* __ASM_COMPAT_SIGNAL_H */
diff --git a/include/asm-mips/compat.h b/include/asm-mips/compat.h
deleted file mode 100644
index ac5d541368e9..000000000000
--- a/include/asm-mips/compat.h
+++ /dev/null
@@ -1,221 +0,0 @@
-#ifndef _ASM_COMPAT_H
-#define _ASM_COMPAT_H
-/*
- * Architecture specific compatibility types
- */
-#include <linux/types.h>
-#include <asm/page.h>
-#include <asm/ptrace.h>
-
-#define COMPAT_USER_HZ  100
-
-typedef u32             compat_size_t;
-typedef s32             compat_ssize_t;
-typedef s32             compat_time_t;
-typedef s32             compat_clock_t;
-typedef s32             compat_suseconds_t;
-
-typedef s32             compat_pid_t;
-typedef s32             __compat_uid_t;
-typedef s32             __compat_gid_t;
-typedef __compat_uid_t  __compat_uid32_t;
-typedef __compat_gid_t  __compat_gid32_t;
-typedef u32             compat_mode_t;
-typedef u32             compat_ino_t;
-typedef u32             compat_dev_t;
-typedef s32             compat_off_t;
-typedef s64             compat_loff_t;
-typedef u32             compat_nlink_t;
-typedef s32             compat_ipc_pid_t;
-typedef s32             compat_daddr_t;
-typedef s32             compat_caddr_t;
-typedef struct {
-        s32     val[2];
-} compat_fsid_t;
-typedef s32             compat_timer_t;
-typedef s32             compat_key_t;
-
-typedef s32             compat_int_t;
-typedef s32             compat_long_t;
-typedef s64             compat_s64;
-typedef u32             compat_uint_t;
-typedef u32             compat_ulong_t;
-typedef u64             compat_u64;
-
-struct compat_timespec {
-        compat_time_t   tv_sec;
-        s32             tv_nsec;
-};
-
-struct compat_timeval {
-        compat_time_t   tv_sec;
-        s32             tv_usec;
-};
-
-struct compat_stat {
-        compat_dev_t    st_dev;
-        s32             st_pad1[3];
-        compat_ino_t    st_ino;
-        compat_mode_t   st_mode;
-        compat_nlink_t  st_nlink;
-        __compat_uid_t  st_uid;
-        __compat_gid_t  st_gid;
-        compat_dev_t    st_rdev;
-        s32             st_pad2[2];
-        compat_off_t    st_size;
-        s32             st_pad3;
-        compat_time_t   st_atime;
-        s32             st_atime_nsec;
-        compat_time_t   st_mtime;
-        s32             st_mtime_nsec;
-        compat_time_t   st_ctime;
-        s32             st_ctime_nsec;
-        s32             st_blksize;
-        s32             st_blocks;
-        s32             st_pad4[14];
-};
-
-struct compat_flock {
-        short           l_type;
-        short           l_whence;
-        compat_off_t    l_start;
-        compat_off_t    l_len;
-        s32             l_sysid;
-        compat_pid_t    l_pid;
-        short           __unused;
-        s32             pad[4];
-};
-
-#define F_GETLK64       33
-#define F_SETLK64       34
-#define F_SETLKW64      35
-
-struct compat_flock64 {
-        short           l_type;
-        short           l_whence;
-        compat_loff_t   l_start;
-        compat_loff_t   l_len;
-        compat_pid_t    l_pid;
-};
-
-struct compat_statfs {
-        int             f_type;
-        int             f_bsize;
-        int             f_frsize;
-        int             f_blocks;
-        int             f_bfree;
-        int             f_files;
-        int             f_ffree;
-        int             f_bavail;
-        compat_fsid_t   f_fsid;
-        int             f_namelen;
-        int             f_spare[6];
-};
-
-#define COMPAT_RLIM_INFINITY    0x7fffffffUL
-
-typedef u32             compat_old_sigset_t;    /* at least 32 bits */
-
-#define _COMPAT_NSIG            128             /* Don't ask !$@#% ...  */
-#define _COMPAT_NSIG_BPW        32
-
-typedef u32             compat_sigset_word;
-
-#define COMPAT_OFF_T_MAX        0x7fffffff
-#define COMPAT_LOFF_T_MAX       0x7fffffffffffffffL
-
-/*
- * A pointer passed in from user mode. This should not
- * be used for syscall parameters, just declare them
- * as pointers because the syscall entry code will have
- * appropriately converted them already.
- */
-typedef u32             compat_uptr_t;
-
-static inline void __user *compat_ptr(compat_uptr_t uptr)
-{
-        /* cast to a __user pointer via "unsigned long" makes sparse happy */
-        return (void __user *)(unsigned long)(long)uptr;
-}
-
-static inline compat_uptr_t ptr_to_compat(void __user *uptr)
-{
-        return (u32)(unsigned long)uptr;
-}
-
-static inline void __user *compat_alloc_user_space(long len)
-{
-        struct pt_regs *regs = (struct pt_regs *)
-                ((unsigned long) current_thread_info() + THREAD_SIZE - 32) - 1;
-
-        return (void __user *) (regs->regs[29] - len);
-}
-
-struct compat_ipc64_perm {
-        compat_key_t key;
-        __compat_uid32_t uid;
-        __compat_gid32_t gid;
-        __compat_uid32_t cuid;
-        __compat_gid32_t cgid;
-        compat_mode_t mode;
-        unsigned short seq;
-        unsigned short __pad2;
-        compat_ulong_t __unused1;
-        compat_ulong_t __unused2;
-};
-
-struct compat_semid64_ds {
-        struct compat_ipc64_perm sem_perm;
-        compat_time_t   sem_otime;
-        compat_time_t   sem_ctime;
-        compat_ulong_t  sem_nsems;
-        compat_ulong_t  __unused1;
-        compat_ulong_t  __unused2;
-};
-
-struct compat_msqid64_ds {
-        struct compat_ipc64_perm msg_perm;
-#ifndef CONFIG_CPU_LITTLE_ENDIAN
-        compat_ulong_t  __unused1;
-#endif
-        compat_time_t   msg_stime;
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-        compat_ulong_t  __unused1;
-#endif
-#ifndef CONFIG_CPU_LITTLE_ENDIAN
-        compat_ulong_t  __unused2;
-#endif
-        compat_time_t   msg_rtime;
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-        compat_ulong_t  __unused2;
-#endif
-#ifndef CONFIG_CPU_LITTLE_ENDIAN
-        compat_ulong_t  __unused3;
-#endif
-        compat_time_t   msg_ctime;
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-        compat_ulong_t  __unused3;
-#endif
-        compat_ulong_t  msg_cbytes;
-        compat_ulong_t  msg_qnum;
-        compat_ulong_t  msg_qbytes;
-        compat_pid_t    msg_lspid;
-        compat_pid_t    msg_lrpid;
-        compat_ulong_t  __unused4;
-        compat_ulong_t  __unused5;
-};
-
-struct compat_shmid64_ds {
-        struct compat_ipc64_perm shm_perm;
-        compat_size_t   shm_segsz;
-        compat_time_t   shm_atime;
-        compat_time_t   shm_dtime;
-        compat_time_t   shm_ctime;
-        compat_pid_t    shm_cpid;
-        compat_pid_t    shm_lpid;
-        compat_ulong_t  shm_nattch;
-        compat_ulong_t  __unused1;
-        compat_ulong_t  __unused2;
-};
-
-#endif /* _ASM_COMPAT_H */
diff --git a/include/asm-mips/compiler.h b/include/asm-mips/compiler.h
deleted file mode 100644
index 71f5c5cfc58a..000000000000
--- a/include/asm-mips/compiler.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Copyright (C) 2004, 2007  Maciej W. Rozycki
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _ASM_COMPILER_H
-#define _ASM_COMPILER_H
-
-#if __GNUC__ > 3 || (__GNUC__ == 3 && __GNUC_MINOR__ >= 4)
-#define GCC_IMM_ASM() "n"
-#define GCC_REG_ACCUM "$0"
-#else
-#define GCC_IMM_ASM() "rn"
-#define GCC_REG_ACCUM "accum"
-#endif
-
-#endif /* _ASM_COMPILER_H */
diff --git a/include/asm-mips/cpu-features.h b/include/asm-mips/cpu-features.h
deleted file mode 100644
index 5ea701fc3425..000000000000
--- a/include/asm-mips/cpu-features.h
+++ /dev/null
@@ -1,219 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle
- * Copyright (C) 2004  Maciej W. Rozycki
- */
-#ifndef __ASM_CPU_FEATURES_H
-#define __ASM_CPU_FEATURES_H
-
-#include <asm/cpu.h>
-#include <asm/cpu-info.h>
-#include <cpu-feature-overrides.h>
-
-#ifndef current_cpu_type
-#define current_cpu_type()      current_cpu_data.cputype
-#endif
-
-/*
- * SMP assumption: Options of CPU 0 are a superset of all processors.
- * This is true for all known MIPS systems.
- */
-#ifndef cpu_has_tlb
-#define cpu_has_tlb             (cpu_data[0].options & MIPS_CPU_TLB)
-#endif
-#ifndef cpu_has_4kex
-#define cpu_has_4kex            (cpu_data[0].options & MIPS_CPU_4KEX)
-#endif
-#ifndef cpu_has_3k_cache
-#define cpu_has_3k_cache        (cpu_data[0].options & MIPS_CPU_3K_CACHE)
-#endif
-#define cpu_has_6k_cache        0
-#define cpu_has_8k_cache        0
-#ifndef cpu_has_4k_cache
-#define cpu_has_4k_cache        (cpu_data[0].options & MIPS_CPU_4K_CACHE)
-#endif
-#ifndef cpu_has_tx39_cache
-#define cpu_has_tx39_cache      (cpu_data[0].options & MIPS_CPU_TX39_CACHE)
-#endif
-#ifndef cpu_has_fpu
-#define cpu_has_fpu             (current_cpu_data.options & MIPS_CPU_FPU)
-#define raw_cpu_has_fpu         (raw_current_cpu_data.options & MIPS_CPU_FPU)
-#else
-#define raw_cpu_has_fpu         cpu_has_fpu
-#endif
-#ifndef cpu_has_32fpr
-#define cpu_has_32fpr           (cpu_data[0].options & MIPS_CPU_32FPR)
-#endif
-#ifndef cpu_has_counter
-#define cpu_has_counter         (cpu_data[0].options & MIPS_CPU_COUNTER)
-#endif
-#ifndef cpu_has_watch
-#define cpu_has_watch           (cpu_data[0].options & MIPS_CPU_WATCH)
-#endif
-#ifndef cpu_has_divec
-#define cpu_has_divec           (cpu_data[0].options & MIPS_CPU_DIVEC)
-#endif
-#ifndef cpu_has_vce
-#define cpu_has_vce             (cpu_data[0].options & MIPS_CPU_VCE)
-#endif
-#ifndef cpu_has_cache_cdex_p
-#define cpu_has_cache_cdex_p    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_P)
-#endif
-#ifndef cpu_has_cache_cdex_s
-#define cpu_has_cache_cdex_s    (cpu_data[0].options & MIPS_CPU_CACHE_CDEX_S)
-#endif
-#ifndef cpu_has_prefetch
-#define cpu_has_prefetch        (cpu_data[0].options & MIPS_CPU_PREFETCH)
-#endif
-#ifndef cpu_has_mcheck
-#define cpu_has_mcheck          (cpu_data[0].options & MIPS_CPU_MCHECK)
-#endif
-#ifndef cpu_has_ejtag
-#define cpu_has_ejtag           (cpu_data[0].options & MIPS_CPU_EJTAG)
-#endif
-#ifndef cpu_has_llsc
-#define cpu_has_llsc            (cpu_data[0].options & MIPS_CPU_LLSC)
-#endif
-#ifndef cpu_has_mips16
-#define cpu_has_mips16          (cpu_data[0].ases & MIPS_ASE_MIPS16)
-#endif
-#ifndef cpu_has_mdmx
-#define cpu_has_mdmx           (cpu_data[0].ases & MIPS_ASE_MDMX)
-#endif
-#ifndef cpu_has_mips3d
-#define cpu_has_mips3d         (cpu_data[0].ases & MIPS_ASE_MIPS3D)
-#endif
-#ifndef cpu_has_smartmips
-#define cpu_has_smartmips      (cpu_data[0].ases & MIPS_ASE_SMARTMIPS)
-#endif
-#ifndef cpu_has_vtag_icache
-#define cpu_has_vtag_icache     (cpu_data[0].icache.flags & MIPS_CACHE_VTAG)
-#endif
-#ifndef cpu_has_dc_aliases
-#define cpu_has_dc_aliases      (cpu_data[0].dcache.flags & MIPS_CACHE_ALIASES)
-#endif
-#ifndef cpu_has_ic_fills_f_dc
-#define cpu_has_ic_fills_f_dc   (cpu_data[0].icache.flags & MIPS_CACHE_IC_F_DC)
-#endif
-#ifndef cpu_has_pindexed_dcache
-#define cpu_has_pindexed_dcache (cpu_data[0].dcache.flags & MIPS_CACHE_PINDEX)
-#endif
-
-/*
- * I-Cache snoops remote store.  This only matters on SMP.  Some multiprocessors
- * such as the R10000 have I-Caches that snoop local stores; the embedded ones
- * don't.  For maintaining I-cache coherency this means we need to flush the
- * D-cache all the way back to whever the I-cache does refills from, so the
- * I-cache has a chance to see the new data at all.  Then we have to flush the
- * I-cache also.
- * Note we may have been rescheduled and may no longer be running on the CPU
- * that did the store so we can't optimize this into only doing the flush on
- * the local CPU.
- */
-#ifndef cpu_icache_snoops_remote_store
-#ifdef CONFIG_SMP
-#define cpu_icache_snoops_remote_store  (cpu_data[0].icache.flags & MIPS_IC_SNOOPS_REMOTE)
-#else
-#define cpu_icache_snoops_remote_store  1
-#endif
-#endif
-
-# ifndef cpu_has_mips32r1
-# define cpu_has_mips32r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R1)
-# endif
-# ifndef cpu_has_mips32r2
-# define cpu_has_mips32r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M32R2)
-# endif
-# ifndef cpu_has_mips64r1
-# define cpu_has_mips64r1       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R1)
-# endif
-# ifndef cpu_has_mips64r2
-# define cpu_has_mips64r2       (cpu_data[0].isa_level & MIPS_CPU_ISA_M64R2)
-# endif
-
-/*
- * Shortcuts ...
- */
-#define cpu_has_mips32  (cpu_has_mips32r1 | cpu_has_mips32r2)
-#define cpu_has_mips64  (cpu_has_mips64r1 | cpu_has_mips64r2)
-#define cpu_has_mips_r1 (cpu_has_mips32r1 | cpu_has_mips64r1)
-#define cpu_has_mips_r2 (cpu_has_mips32r2 | cpu_has_mips64r2)
-
-#ifndef cpu_has_dsp
-#define cpu_has_dsp             (cpu_data[0].ases & MIPS_ASE_DSP)
-#endif
-
-#ifndef cpu_has_mipsmt
-#define cpu_has_mipsmt          (cpu_data[0].ases & MIPS_ASE_MIPSMT)
-#endif
-
-#ifndef cpu_has_userlocal
-#define cpu_has_userlocal       (cpu_data[0].options & MIPS_CPU_ULRI)
-#endif
-
-#ifdef CONFIG_32BIT
-# ifndef cpu_has_nofpuex
-# define cpu_has_nofpuex        (cpu_data[0].options & MIPS_CPU_NOFPUEX)
-# endif
-# ifndef cpu_has_64bits
-# define cpu_has_64bits         (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
-# endif
-# ifndef cpu_has_64bit_zero_reg
-# define cpu_has_64bit_zero_reg (cpu_data[0].isa_level & MIPS_CPU_ISA_64BIT)
-# endif
-# ifndef cpu_has_64bit_gp_regs
-# define cpu_has_64bit_gp_regs          0
-# endif
-# ifndef cpu_has_64bit_addresses
-# define cpu_has_64bit_addresses        0
-# endif
-#endif
-
-#ifdef CONFIG_64BIT
-# ifndef cpu_has_nofpuex
-# define cpu_has_nofpuex                0
-# endif
-# ifndef cpu_has_64bits
-# define cpu_has_64bits                 1
-# endif
-# ifndef cpu_has_64bit_zero_reg
-# define cpu_has_64bit_zero_reg         1
-# endif
-# ifndef cpu_has_64bit_gp_regs
-# define cpu_has_64bit_gp_regs          1
-# endif
-# ifndef cpu_has_64bit_addresses
-# define cpu_has_64bit_addresses        1
-# endif
-#endif
-
-#if defined(CONFIG_CPU_MIPSR2_IRQ_VI) && !defined(cpu_has_vint)
-# define cpu_has_vint           (cpu_data[0].options & MIPS_CPU_VINT)
-#elif !defined(cpu_has_vint)
-# define cpu_has_vint                   0
-#endif
-
-#if defined(CONFIG_CPU_MIPSR2_IRQ_EI) && !defined(cpu_has_veic)
-# define cpu_has_veic           (cpu_data[0].options & MIPS_CPU_VEIC)
-#elif !defined(cpu_has_veic)
-# define cpu_has_veic                   0
-#endif
-
-#ifndef cpu_has_inclusive_pcaches
-#define cpu_has_inclusive_pcaches       (cpu_data[0].options & MIPS_CPU_INCLUSIVE_CACHES)
-#endif
-
-#ifndef cpu_dcache_line_size
-#define cpu_dcache_line_size()  cpu_data[0].dcache.linesz
-#endif
-#ifndef cpu_icache_line_size
-#define cpu_icache_line_size()  cpu_data[0].icache.linesz
-#endif
-#ifndef cpu_scache_line_size
-#define cpu_scache_line_size()  cpu_data[0].scache.linesz
-#endif
-
-#endif /* __ASM_CPU_FEATURES_H */
diff --git a/include/asm-mips/cpu-info.h b/include/asm-mips/cpu-info.h
deleted file mode 100644
index 2de73dbb2e9e..000000000000
--- a/include/asm-mips/cpu-info.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 Waldorf GMBH
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
- * Copyright (C) 1996 Paul M. Antoine
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2004  Maciej W. Rozycki
- */
-#ifndef __ASM_CPU_INFO_H
-#define __ASM_CPU_INFO_H
-
-#include <asm/cache.h>
-
-/*
- * Descriptor for a cache
- */
-struct cache_desc {
-        unsigned int waysize;   /* Bytes per way */
-        unsigned short sets;    /* Number of lines per set */
-        unsigned char ways;     /* Number of ways */
-        unsigned char linesz;   /* Size of line in bytes */
-        unsigned char waybit;   /* Bits to select in a cache set */
-        unsigned char flags;    /* Flags describing cache properties */
-};
-
-/*
- * Flag definitions
- */
-#define MIPS_CACHE_NOT_PRESENT  0x00000001
-#define MIPS_CACHE_VTAG         0x00000002      /* Virtually tagged cache */
-#define MIPS_CACHE_ALIASES      0x00000004      /* Cache could have aliases */
-#define MIPS_CACHE_IC_F_DC      0x00000008      /* Ic can refill from D-cache */
-#define MIPS_IC_SNOOPS_REMOTE   0x00000010      /* Ic snoops remote stores */
-#define MIPS_CACHE_PINDEX       0x00000020      /* Physically indexed cache */
-
-struct cpuinfo_mips {
-        unsigned long           udelay_val;
-        unsigned long           asid_cache;
-
-        /*
-         * Capability and feature descriptor structure for MIPS CPU
-         */
-        unsigned long           options;
-        unsigned long           ases;
-        unsigned int            processor_id;
-        unsigned int            fpu_id;
-        unsigned int            cputype;
-        int                     isa_level;
-        int                     tlbsize;
-        struct cache_desc       icache; /* Primary I-cache */
-        struct cache_desc       dcache; /* Primary D or combined I/D cache */
-        struct cache_desc       scache; /* Secondary cache */
-        struct cache_desc       tcache; /* Tertiary/split secondary cache */
-        int                     srsets; /* Shadow register sets */
-        int                     core;   /* physical core number */
-#if defined(CONFIG_MIPS_MT_SMP) || defined(CONFIG_MIPS_MT_SMTC)
-        /*
-         * In the MIPS MT "SMTC" model, each TC is considered
-         * to be a "CPU" for the purposes of scheduling, but
-         * exception resources, ASID spaces, etc, are common
-         * to all TCs within the same VPE.
-         */
-        int                     vpe_id;  /* Virtual Processor number */
-#endif
-#ifdef CONFIG_MIPS_MT_SMTC
-        int                     tc_id;   /* Thread Context number */
-#endif
-        void                    *data;  /* Additional data */
-} __attribute__((aligned(SMP_CACHE_BYTES)));
-
-extern struct cpuinfo_mips cpu_data[];
-#define current_cpu_data cpu_data[smp_processor_id()]
-#define raw_current_cpu_data cpu_data[raw_smp_processor_id()]
-
-extern void cpu_probe(void);
-extern void cpu_report(void);
-
-extern const char *__cpu_name[];
-#define cpu_name_string()       __cpu_name[smp_processor_id()]
-
-#endif /* __ASM_CPU_INFO_H */
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
deleted file mode 100644
index 229a786101d9..000000000000
--- a/include/asm-mips/cpu.h
+++ /dev/null
@@ -1,267 +0,0 @@
-/*
- * cpu.h: Values of the PRId register used to match up
- *        various MIPS cpu types.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 2004  Maciej W. Rozycki
- */
-#ifndef _ASM_CPU_H
-#define _ASM_CPU_H
-
-/* Assigned Company values for bits 23:16 of the PRId Register
-   (CP0 register 15, select 0).  As of the MIPS32 and MIPS64 specs from
-   MTI, the PRId register is defined in this (backwards compatible)
-   way:
-
-  +----------------+----------------+----------------+----------------+
-  | Company Options| Company ID     | Processor ID   | Revision       |
-  +----------------+----------------+----------------+----------------+
-   31            24 23            16 15             8 7
-
-   I don't have docs for all the previous processors, but my impression is
-   that bits 16-23 have been 0 for all MIPS processors before the MIPS32/64
-   spec.
-*/
-
-#define PRID_COMP_LEGACY        0x000000
-#define PRID_COMP_MIPS          0x010000
-#define PRID_COMP_BROADCOM      0x020000
-#define PRID_COMP_ALCHEMY       0x030000
-#define PRID_COMP_SIBYTE        0x040000
-#define PRID_COMP_SANDCRAFT     0x050000
-#define PRID_COMP_NXP           0x060000
-#define PRID_COMP_TOSHIBA       0x070000
-#define PRID_COMP_LSI           0x080000
-#define PRID_COMP_LEXRA         0x0b0000
-
-
-/*
- * Assigned values for the product ID register.  In order to detect a
- * certain CPU type exactly eventually additional registers may need to
- * be examined.  These are valid when 23:16 == PRID_COMP_LEGACY
- */
-#define PRID_IMP_R2000          0x0100
-#define PRID_IMP_AU1_REV1       0x0100
-#define PRID_IMP_AU1_REV2       0x0200
-#define PRID_IMP_R3000          0x0200          /* Same as R2000A  */
-#define PRID_IMP_R6000          0x0300          /* Same as R3000A  */
-#define PRID_IMP_R4000          0x0400
-#define PRID_IMP_R6000A         0x0600
-#define PRID_IMP_R10000         0x0900
-#define PRID_IMP_R4300          0x0b00
-#define PRID_IMP_VR41XX         0x0c00
-#define PRID_IMP_R12000         0x0e00
-#define PRID_IMP_R14000         0x0f00
-#define PRID_IMP_R8000          0x1000
-#define PRID_IMP_PR4450         0x1200
-#define PRID_IMP_R4600          0x2000
-#define PRID_IMP_R4700          0x2100
-#define PRID_IMP_TX39           0x2200
-#define PRID_IMP_R4640          0x2200
-#define PRID_IMP_R4650          0x2200          /* Same as R4640 */
-#define PRID_IMP_R5000          0x2300
-#define PRID_IMP_TX49           0x2d00
-#define PRID_IMP_SONIC          0x2400
-#define PRID_IMP_MAGIC          0x2500
-#define PRID_IMP_RM7000         0x2700
-#define PRID_IMP_NEVADA         0x2800          /* RM5260 ??? */
-#define PRID_IMP_RM9000         0x3400
-#define PRID_IMP_LOONGSON1      0x4200
-#define PRID_IMP_R5432          0x5400
-#define PRID_IMP_R5500          0x5500
-#define PRID_IMP_LOONGSON2      0x6300
-
-#define PRID_IMP_UNKNOWN        0xff00
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_MIPS
- */
-
-#define PRID_IMP_4KC            0x8000
-#define PRID_IMP_5KC            0x8100
-#define PRID_IMP_20KC           0x8200
-#define PRID_IMP_4KEC           0x8400
-#define PRID_IMP_4KSC           0x8600
-#define PRID_IMP_25KF           0x8800
-#define PRID_IMP_5KE            0x8900
-#define PRID_IMP_4KECR2         0x9000
-#define PRID_IMP_4KEMPR2        0x9100
-#define PRID_IMP_4KSD           0x9200
-#define PRID_IMP_24K            0x9300
-#define PRID_IMP_34K            0x9500
-#define PRID_IMP_24KE           0x9600
-#define PRID_IMP_74K            0x9700
-#define PRID_IMP_1004K          0x9900
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_SIBYTE
- */
-
-#define PRID_IMP_SB1            0x0100
-#define PRID_IMP_SB1A           0x1100
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_SANDCRAFT
- */
-
-#define PRID_IMP_SR71000        0x0400
-
-/*
- * These are the PRID's for when 23:16 == PRID_COMP_BROADCOM
- */
-
-#define PRID_IMP_BCM4710        0x4000
-#define PRID_IMP_BCM3302        0x9000
-
-/*
- * Definitions for 7:0 on legacy processors
- */
-
-#define PRID_REV_MASK           0x00ff
-
-#define PRID_REV_TX4927         0x0022
-#define PRID_REV_TX4937         0x0030
-#define PRID_REV_R4400          0x0040
-#define PRID_REV_R3000A         0x0030
-#define PRID_REV_R3000          0x0020
-#define PRID_REV_R2000A         0x0010
-#define PRID_REV_TX3912         0x0010
-#define PRID_REV_TX3922         0x0030
-#define PRID_REV_TX3927         0x0040
-#define PRID_REV_VR4111         0x0050
-#define PRID_REV_VR4181         0x0050  /* Same as VR4111 */
-#define PRID_REV_VR4121         0x0060
-#define PRID_REV_VR4122         0x0070
-#define PRID_REV_VR4181A        0x0070  /* Same as VR4122 */
-#define PRID_REV_VR4130         0x0080
-#define PRID_REV_34K_V1_0_2     0x0022
-
-/*
- * Older processors used to encode processor version and revision in two
- * 4-bit bitfields, the 4K seems to simply count up and even newer MTI cores
- * have switched to use the 8-bits as 3:3:2 bitfield with the last field as
- * the patch number.  *ARGH*
- */
-#define PRID_REV_ENCODE_44(ver, rev)                                    \
-        ((ver) << 4 | (rev))
-#define PRID_REV_ENCODE_332(ver, rev, patch)                            \
-        ((ver) << 5 | (rev) << 2 | (patch))
-
-/*
- * FPU implementation/revision register (CP1 control register 0).
- *
- * +---------------------------------+----------------+----------------+
- * | 0                               | Implementation | Revision       |
- * +---------------------------------+----------------+----------------+
- *  31                             16 15             8 7              0
- */
-
-#define FPIR_IMP_NONE           0x0000
-
-enum cpu_type_enum {
-        CPU_UNKNOWN,
-
-        /*
-         * R2000 class processors
-         */
-        CPU_R2000, CPU_R3000, CPU_R3000A, CPU_R3041, CPU_R3051, CPU_R3052,
-        CPU_R3081, CPU_R3081E,
-
-        /*
-         * R6000 class processors
-         */
-        CPU_R6000, CPU_R6000A,
-
-        /*
-         * R4000 class processors
-         */
-        CPU_R4000PC, CPU_R4000SC, CPU_R4000MC, CPU_R4200, CPU_R4300, CPU_R4310,
-        CPU_R4400PC, CPU_R4400SC, CPU_R4400MC, CPU_R4600, CPU_R4640, CPU_R4650,
-        CPU_R4700, CPU_R5000, CPU_R5000A, CPU_R5500, CPU_NEVADA, CPU_R5432,
-        CPU_R10000, CPU_R12000, CPU_R14000, CPU_VR41XX, CPU_VR4111, CPU_VR4121,
-        CPU_VR4122, CPU_VR4131, CPU_VR4133, CPU_VR4181, CPU_VR4181A, CPU_RM7000,
-        CPU_SR71000, CPU_RM9000, CPU_TX49XX,
-
-        /*
-         * R8000 class processors
-         */
-        CPU_R8000,
-
-        /*
-         * TX3900 class processors
-         */
-        CPU_TX3912, CPU_TX3922, CPU_TX3927,
-
-        /*
-         * MIPS32 class processors
-         */
-        CPU_4KC, CPU_4KEC, CPU_4KSC, CPU_24K, CPU_34K, CPU_1004K, CPU_74K,
-        CPU_AU1000, CPU_AU1100, CPU_AU1200, CPU_AU1210, CPU_AU1250, CPU_AU1500,
-        CPU_AU1550, CPU_PR4450, CPU_BCM3302, CPU_BCM4710,
-
-        /*
-         * MIPS64 class processors
-         */
-        CPU_5KC, CPU_20KC, CPU_25KF, CPU_SB1, CPU_SB1A, CPU_LOONGSON2,
-
-        CPU_LAST
-};
-
-
-/*
- * ISA Level encodings
- *
- */
-#define MIPS_CPU_ISA_I          0x00000001
-#define MIPS_CPU_ISA_II         0x00000002
-#define MIPS_CPU_ISA_III        0x00000004
-#define MIPS_CPU_ISA_IV         0x00000008
-#define MIPS_CPU_ISA_V          0x00000010
-#define MIPS_CPU_ISA_M32R1      0x00000020
-#define MIPS_CPU_ISA_M32R2      0x00000040
-#define MIPS_CPU_ISA_M64R1      0x00000080
-#define MIPS_CPU_ISA_M64R2      0x00000100
-
-#define MIPS_CPU_ISA_32BIT (MIPS_CPU_ISA_I | MIPS_CPU_ISA_II | \
-        MIPS_CPU_ISA_M32R1 | MIPS_CPU_ISA_M32R2 )
-#define MIPS_CPU_ISA_64BIT (MIPS_CPU_ISA_III | MIPS_CPU_ISA_IV | \
-        MIPS_CPU_ISA_V | MIPS_CPU_ISA_M64R1 | MIPS_CPU_ISA_M64R2)
-
-/*
- * CPU Option encodings
- */
-#define MIPS_CPU_TLB            0x00000001 /* CPU has TLB */
-#define MIPS_CPU_4KEX           0x00000002 /* "R4K" exception model */
-#define MIPS_CPU_3K_CACHE       0x00000004 /* R3000-style caches */
-#define MIPS_CPU_4K_CACHE       0x00000008 /* R4000-style caches */
-#define MIPS_CPU_TX39_CACHE     0x00000010 /* TX3900-style caches */
-#define MIPS_CPU_FPU            0x00000020 /* CPU has FPU */
-#define MIPS_CPU_32FPR          0x00000040 /* 32 dbl. prec. FP registers */
-#define MIPS_CPU_COUNTER        0x00000080 /* Cycle count/compare */
-#define MIPS_CPU_WATCH          0x00000100 /* watchpoint registers */
-#define MIPS_CPU_DIVEC          0x00000200 /* dedicated interrupt vector */
-#define MIPS_CPU_VCE            0x00000400 /* virt. coherence conflict possible */
-#define MIPS_CPU_CACHE_CDEX_P   0x00000800 /* Create_Dirty_Exclusive CACHE op */
-#define MIPS_CPU_CACHE_CDEX_S   0x00001000 /* ... same for seconary cache ... */
-#define MIPS_CPU_MCHECK         0x00002000 /* Machine check exception */
-#define MIPS_CPU_EJTAG          0x00004000 /* EJTAG exception */
-#define MIPS_CPU_NOFPUEX        0x00008000 /* no FPU exception */
-#define MIPS_CPU_LLSC           0x00010000 /* CPU has ll/sc instructions */
-#define MIPS_CPU_INCLUSIVE_CACHES       0x00020000 /* P-cache subset enforced */
-#define MIPS_CPU_PREFETCH       0x00040000 /* CPU has usable prefetch */
-#define MIPS_CPU_VINT           0x00080000 /* CPU supports MIPSR2 vectored interrupts */
-#define MIPS_CPU_VEIC           0x00100000 /* CPU supports MIPSR2 external interrupt controller mode */
-#define MIPS_CPU_ULRI           0x00200000 /* CPU has ULRI feature */
-
-/*
- * CPU ASE encodings
- */
-#define MIPS_ASE_MIPS16         0x00000001 /* code compression */
-#define MIPS_ASE_MDMX           0x00000002 /* MIPS digital media extension */
-#define MIPS_ASE_MIPS3D         0x00000004 /* MIPS-3D */
-#define MIPS_ASE_SMARTMIPS      0x00000008 /* SmartMIPS */
-#define MIPS_ASE_DSP            0x00000010 /* Signal Processing ASE */
-#define MIPS_ASE_MIPSMT         0x00000020 /* CPU supports MIPS MT */
-
-
-#endif /* _ASM_CPU_H */
diff --git a/include/asm-mips/cputime.h b/include/asm-mips/cputime.h
deleted file mode 100644
index c00eacbdd979..000000000000
--- a/include/asm-mips/cputime.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __MIPS_CPUTIME_H
-#define __MIPS_CPUTIME_H
-
-#include <asm-generic/cputime.h>
-
-#endif /* __MIPS_CPUTIME_H */
diff --git a/include/asm-mips/current.h b/include/asm-mips/current.h
deleted file mode 100644
index 559db66b9790..000000000000
--- a/include/asm-mips/current.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2002 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_CURRENT_H
-#define _ASM_CURRENT_H
-
-#include <linux/thread_info.h>
-
-struct task_struct;
-
-static inline struct task_struct * get_current(void)
-{
-        return current_thread_info()->task;
-}
-
-#define current         get_current()
-
-#endif /* _ASM_CURRENT_H */
diff --git a/include/asm-mips/debug.h b/include/asm-mips/debug.h
deleted file mode 100644
index 1fd5a2b39445..000000000000
--- a/include/asm-mips/debug.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Debug macros for run-time debugging.
- * Turned on/off with CONFIG_RUNTIME_DEBUG option.
- *
- * Copyright (C) 2001 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- *
- */
-
-#ifndef _ASM_DEBUG_H
-#define _ASM_DEBUG_H
-
-
-/*
- * run-time macros for catching spurious errors.  Eable CONFIG_RUNTIME_DEBUG in
- * kernel hacking config menu to use them.
- *
- * Use them as run-time debugging aid.  NEVER USE THEM AS ERROR HANDLING CODE!!!
- */
-
-#ifdef CONFIG_RUNTIME_DEBUG
-
-#include <linux/kernel.h>
-
-#define db_assert(x)  if (!(x)) { \
-        panic("assertion failed at %s:%d: %s", __FILE__, __LINE__, #x); }
-#define db_warn(x)  if (!(x)) { \
-        printk(KERN_WARNING "warning at %s:%d: %s", __FILE__, __LINE__, #x); }
-#define db_verify(x, y) db_assert(x y)
-#define db_verify_warn(x, y) db_warn(x y)
-#define db_run(x)  do { x; } while (0)
-
-#else
-
-#define db_assert(x)
-#define db_warn(x)
-#define db_verify(x, y) x
-#define db_verify_warn(x, y) x
-#define db_run(x)
-
-#endif
-
-#endif /* _ASM_DEBUG_H */
diff --git a/include/asm-mips/dec/ecc.h b/include/asm-mips/dec/ecc.h
deleted file mode 100644
index 707ffdbc9add..000000000000
--- a/include/asm-mips/dec/ecc.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- *      include/asm-mips/dec/ecc.h
- *
- *      ECC handling logic definitions common to DECstation/DECsystem
- *      5000/200 (KN02), 5000/240 (KN03), 5000/260 (KN05) and
- *      DECsystem 5900 (KN03), 5900/260 (KN05) systems.
- *
- *      Copyright (C) 2003  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_ECC_H
-#define __ASM_MIPS_DEC_ECC_H
-
-/*
- * Error Address Register bits.
- * The register is r/wc -- any write clears it.
- */
-#define KN0X_EAR_VALID          (1<<31)         /* error data valid, bus IRQ */
-#define KN0X_EAR_CPU            (1<<30)         /* CPU/DMA transaction */
-#define KN0X_EAR_WRITE          (1<<29)         /* write/read transaction */
-#define KN0X_EAR_ECCERR         (1<<28)         /* ECC/timeout or overrun */
-#define KN0X_EAR_RES_27         (1<<27)         /* unused */
-#define KN0X_EAR_ADDRESS        (0x7ffffff<<0)  /* address involved */
-
-/*
- * Error Syndrome Register bits.
- * The register is frozen when EAR.VALID is set, otherwise it records bits
- * from the last memory read.  The register is r/wc -- any write clears it.
- */
-#define KN0X_ESR_VLDHI          (1<<31)         /* error data valid hi word */
-#define KN0X_ESR_CHKHI          (0x7f<<24)      /* check bits read from mem */
-#define KN0X_ESR_SNGHI          (1<<23)         /* single/double bit error */
-#define KN0X_ESR_SYNHI          (0x7f<<16)      /* syndrome from ECC logic */
-#define KN0X_ESR_VLDLO          (1<<15)         /* error data valid lo word */
-#define KN0X_ESR_CHKLO          (0x7f<<8)       /* check bits read from mem */
-#define KN0X_ESR_SNGLO          (1<<7)          /* single/double bit error */
-#define KN0X_ESR_SYNLO          (0x7f<<0)       /* syndrome from ECC logic */
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-
-struct pt_regs;
-
-extern void dec_ecc_be_init(void);
-extern int dec_ecc_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_ecc_be_interrupt(int irq, void *dev_id);
-#endif
-
-#endif /* __ASM_MIPS_DEC_ECC_H */
diff --git a/include/asm-mips/dec/interrupts.h b/include/asm-mips/dec/interrupts.h
deleted file mode 100644
index e10d341067c8..000000000000
--- a/include/asm-mips/dec/interrupts.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Miscellaneous definitions used to initialise the interrupt vector table
- * with the machine-specific interrupt routines.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997 by Paul M. Antoine.
- * reworked 1998 by Harald Koerfgen.
- * Copyright (C) 2001, 2002, 2003  Maciej W. Rozycki
- */
-
-#ifndef __ASM_DEC_INTERRUPTS_H
-#define __ASM_DEC_INTERRUPTS_H
-
-#include <irq.h>
-#include <asm/mipsregs.h>
-
-
-/*
- * The list of possible system devices which provide an
- * interrupt.  Not all devices exist on a given system.
- */
-#define DEC_IRQ_CASCADE         0       /* cascade from CSR or I/O ASIC */
-
-/* Ordinary interrupts */
-#define DEC_IRQ_AB_RECV         1       /* ACCESS.bus receive */
-#define DEC_IRQ_AB_XMIT         2       /* ACCESS.bus transmit */
-#define DEC_IRQ_DZ11            3       /* DZ11 (DC7085) serial */
-#define DEC_IRQ_ASC             4       /* ASC (NCR53C94) SCSI */
-#define DEC_IRQ_FLOPPY          5       /* 82077 FDC */
-#define DEC_IRQ_FPU             6       /* R3k FPU */
-#define DEC_IRQ_HALT            7       /* HALT button or from ACCESS.Bus */
-#define DEC_IRQ_ISDN            8       /* Am79C30A ISDN */
-#define DEC_IRQ_LANCE           9       /* LANCE (Am7990) Ethernet */
-#define DEC_IRQ_BUS             10      /* memory, I/O bus read/write errors */
-#define DEC_IRQ_PSU             11      /* power supply unit warning */
-#define DEC_IRQ_RTC             12      /* DS1287 RTC */
-#define DEC_IRQ_SCC0            13      /* SCC (Z85C30) serial #0 */
-#define DEC_IRQ_SCC1            14      /* SCC (Z85C30) serial #1 */
-#define DEC_IRQ_SII             15      /* SII (DC7061) SCSI */
-#define DEC_IRQ_TC0             16      /* TURBOchannel slot #0 */
-#define DEC_IRQ_TC1             17      /* TURBOchannel slot #1 */
-#define DEC_IRQ_TC2             18      /* TURBOchannel slot #2 */
-#define DEC_IRQ_TIMER           19      /* ARC periodic timer */
-#define DEC_IRQ_VIDEO           20      /* framebuffer */
-
-/* I/O ASIC DMA interrupts */
-#define DEC_IRQ_ASC_MERR        21      /* ASC memory read error */
-#define DEC_IRQ_ASC_ERR         22      /* ASC page overrun */
-#define DEC_IRQ_ASC_DMA         23      /* ASC buffer pointer loaded */
-#define DEC_IRQ_FLOPPY_ERR      24      /* FDC error */
-#define DEC_IRQ_ISDN_ERR        25      /* ISDN memory read/overrun error */
-#define DEC_IRQ_ISDN_RXDMA      26      /* ISDN recv buffer pointer loaded */
-#define DEC_IRQ_ISDN_TXDMA      27      /* ISDN xmit buffer pointer loaded */
-#define DEC_IRQ_LANCE_MERR      28      /* LANCE memory read error */
-#define DEC_IRQ_SCC0A_RXERR     29      /* SCC0A (printer) receive overrun */
-#define DEC_IRQ_SCC0A_RXDMA     30      /* SCC0A receive half page */
-#define DEC_IRQ_SCC0A_TXERR     31      /* SCC0A xmit memory read/overrun */
-#define DEC_IRQ_SCC0A_TXDMA     32      /* SCC0A transmit page end */
-#define DEC_IRQ_AB_RXERR        33      /* ACCESS.bus receive overrun */
-#define DEC_IRQ_AB_RXDMA        34      /* ACCESS.bus receive half page */
-#define DEC_IRQ_AB_TXERR        35      /* ACCESS.bus xmit memory read/ovrn */
-#define DEC_IRQ_AB_TXDMA        36      /* ACCESS.bus transmit page end */
-#define DEC_IRQ_SCC1A_RXERR     37      /* SCC1A (modem) receive overrun */
-#define DEC_IRQ_SCC1A_RXDMA     38      /* SCC1A receive half page */
-#define DEC_IRQ_SCC1A_TXERR     39      /* SCC1A xmit memory read/overrun */
-#define DEC_IRQ_SCC1A_TXDMA     40      /* SCC1A transmit page end */
-
-/* TC5 & TC6 are virtual slots for KN02's onboard devices */
-#define DEC_IRQ_TC5             DEC_IRQ_ASC     /* virtual PMAZ-AA */
-#define DEC_IRQ_TC6             DEC_IRQ_LANCE   /* virtual PMAD-AA */
-
-#define DEC_NR_INTS             41
-
-
-/* Largest of cpu mask_nr tables. */
-#define DEC_MAX_CPU_INTS        6
-/* Largest of asic mask_nr tables. */
-#define DEC_MAX_ASIC_INTS       9
-
-
-/*
- * CPU interrupt bits common to all systems.
- */
-#define DEC_CPU_INR_FPU         7       /* R3k FPU */
-#define DEC_CPU_INR_SW1         1       /* software #1 */
-#define DEC_CPU_INR_SW0         0       /* software #0 */
-
-#define DEC_CPU_IRQ_BASE        MIPS_CPU_IRQ_BASE       /* first IRQ assigned to CPU */
-
-#define DEC_CPU_IRQ_NR(n)       ((n) + DEC_CPU_IRQ_BASE)
-#define DEC_CPU_IRQ_MASK(n)     (1 << ((n) + CAUSEB_IP))
-#define DEC_CPU_IRQ_ALL         (0xff << CAUSEB_IP)
-
-
-#ifndef __ASSEMBLY__
-
-/*
- * Interrupt table structures to hide differences between systems.
- */
-typedef union { int i; void *p; } int_ptr;
-extern int dec_interrupt[DEC_NR_INTS];
-extern int_ptr cpu_mask_nr_tbl[DEC_MAX_CPU_INTS][2];
-extern int_ptr asic_mask_nr_tbl[DEC_MAX_ASIC_INTS][2];
-extern int cpu_fpu_mask;
-
-
-/*
- * Common interrupt routine prototypes for all DECStations
- */
-extern void kn02_io_int(void);
-extern void kn02xa_io_int(void);
-extern void kn03_io_int(void);
-extern void asic_dma_int(void);
-extern void asic_all_int(void);
-extern void kn02_all_int(void);
-extern void cpu_all_int(void);
-
-extern void dec_intr_unimplemented(void);
-extern void asic_intr_unimplemented(void);
-
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-mips/dec/ioasic.h b/include/asm-mips/dec/ioasic.h
deleted file mode 100644
index 98badd6bf22d..000000000000
--- a/include/asm-mips/dec/ioasic.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *      include/asm-mips/dec/ioasic.h
- *
- *      DEC I/O ASIC access operations.
- *
- *      Copyright (C) 2000, 2002, 2003  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-
-#ifndef __ASM_DEC_IOASIC_H
-#define __ASM_DEC_IOASIC_H
-
-#include <linux/spinlock.h>
-#include <linux/types.h>
-
-extern spinlock_t ioasic_ssr_lock;
-
-extern volatile u32 *ioasic_base;
-
-static inline void ioasic_write(unsigned int reg, u32 v)
-{
-        ioasic_base[reg / 4] = v;
-}
-
-static inline u32 ioasic_read(unsigned int reg)
-{
-        return ioasic_base[reg / 4];
-}
-
-extern void init_ioasic_irqs(int base);
-
-extern void dec_ioasic_clocksource_init(void);
-
-#endif /* __ASM_DEC_IOASIC_H */
diff --git a/include/asm-mips/dec/ioasic_addrs.h b/include/asm-mips/dec/ioasic_addrs.h
deleted file mode 100644
index 4cbc1f8a1129..000000000000
--- a/include/asm-mips/dec/ioasic_addrs.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Definitions for the address map in the JUNKIO Asic
- *
- * Created with Information from:
- *
- * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
- *
- * and the Mach Sources
- *
- * Copyright (C) 199x  the Anonymous
- * Copyright (C) 2002, 2003  Maciej W. Rozycki
- */
-
-#ifndef __ASM_MIPS_DEC_IOASIC_ADDRS_H
-#define __ASM_MIPS_DEC_IOASIC_ADDRS_H
-
-#define IOASIC_SLOT_SIZE 0x00040000
-
-/*
- * Address ranges decoded by the I/O ASIC for onboard devices.
- */
-#define IOASIC_SYS_ROM  (0*IOASIC_SLOT_SIZE)    /* system board ROM */
-#define IOASIC_IOCTL    (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
-#define IOASIC_ESAR     (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
-#define IOASIC_LANCE    (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
-#define IOASIC_SCC0     (4*IOASIC_SLOT_SIZE)    /* SCC #0 */
-#define IOASIC_VDAC_HI  (5*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
-#define IOASIC_SCC1     (6*IOASIC_SLOT_SIZE)    /* SCC #1 (3min, 3max+) */
-#define IOASIC_VDAC_LO  (7*IOASIC_SLOT_SIZE)    /* VDAC (maxine) */
-#define IOASIC_TOY      (8*IOASIC_SLOT_SIZE)    /* RTC */
-#define IOASIC_ISDN     (9*IOASIC_SLOT_SIZE)    /* ISDN (maxine) */
-#define IOASIC_ERRADDR  (9*IOASIC_SLOT_SIZE)    /* bus error address (3max+) */
-#define IOASIC_CHKSYN   (10*IOASIC_SLOT_SIZE)   /* ECC syndrome (3max+) */
-#define IOASIC_ACC_BUS  (10*IOASIC_SLOT_SIZE)   /* ACCESS.bus (maxine) */
-#define IOASIC_MCR      (11*IOASIC_SLOT_SIZE)   /* memory control (3max+) */
-#define IOASIC_FLOPPY   (11*IOASIC_SLOT_SIZE)   /* FDC (maxine) */
-#define IOASIC_SCSI     (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
-#define IOASIC_FDC_DMA  (13*IOASIC_SLOT_SIZE)   /* FDC DMA (maxine) */
-#define IOASIC_SCSI_DMA (14*IOASIC_SLOT_SIZE)   /* ??? */
-#define IOASIC_RES_15   (15*IOASIC_SLOT_SIZE)   /* unused? */
-
-
-/*
- * Offsets for I/O ASIC registers
- * (relative to (dec_kn_slot_base + IOASIC_IOCTL)).
- */
-                                        /* all systems */
-#define IO_REG_SCSI_DMA_P       0x00    /* SCSI DMA Pointer */
-#define IO_REG_SCSI_DMA_BP      0x10    /* SCSI DMA Buffer Pointer */
-#define IO_REG_LANCE_DMA_P      0x20    /* LANCE DMA Pointer */
-#define IO_REG_SCC0A_T_DMA_P    0x30    /* SCC0A Transmit DMA Pointer */
-#define IO_REG_SCC0A_R_DMA_P    0x40    /* SCC0A Receive DMA Pointer */
-
-                                        /* except Maxine */
-#define IO_REG_SCC1A_T_DMA_P    0x50    /* SCC1A Transmit DMA Pointer */
-#define IO_REG_SCC1A_R_DMA_P    0x60    /* SCC1A Receive DMA Pointer */
-
-                                        /* Maxine */
-#define IO_REG_AB_T_DMA_P       0x50    /* ACCESS.bus Transmit DMA Pointer */
-#define IO_REG_AB_R_DMA_P       0x60    /* ACCESS.bus Receive DMA Pointer */
-#define IO_REG_FLOPPY_DMA_P     0x70    /* Floppy DMA Pointer */
-#define IO_REG_ISDN_T_DMA_P     0x80    /* ISDN Transmit DMA Pointer */
-#define IO_REG_ISDN_T_DMA_BP    0x90    /* ISDN Transmit DMA Buffer Pointer */
-#define IO_REG_ISDN_R_DMA_P     0xa0    /* ISDN Receive DMA Pointer */
-#define IO_REG_ISDN_R_DMA_BP    0xb0    /* ISDN Receive DMA Buffer Pointer */
-
-                                        /* all systems */
-#define IO_REG_DATA_0           0xc0    /* System Data Buffer 0 */
-#define IO_REG_DATA_1           0xd0    /* System Data Buffer 1 */
-#define IO_REG_DATA_2           0xe0    /* System Data Buffer 2 */
-#define IO_REG_DATA_3           0xf0    /* System Data Buffer 3 */
-
-                                        /* all systems */
-#define IO_REG_SSR              0x100   /* System Support Register */
-#define IO_REG_SIR              0x110   /* System Interrupt Register */
-#define IO_REG_SIMR             0x120   /* System Interrupt Mask Reg. */
-#define IO_REG_SAR              0x130   /* System Address Register */
-
-                                        /* Maxine */
-#define IO_REG_ISDN_T_DATA      0x140   /* ISDN Xmit Data Register */
-#define IO_REG_ISDN_R_DATA      0x150   /* ISDN Receive Data Register */
-
-                                        /* all systems */
-#define IO_REG_LANCE_SLOT       0x160   /* LANCE I/O Slot Register */
-#define IO_REG_SCSI_SLOT        0x170   /* SCSI Slot Register */
-#define IO_REG_SCC0A_SLOT       0x180   /* SCC0A DMA Slot Register */
-
-                                        /* except Maxine */
-#define IO_REG_SCC1A_SLOT       0x190   /* SCC1A DMA Slot Register */
-
-                                        /* Maxine */
-#define IO_REG_AB_SLOT          0x190   /* ACCESS.bus DMA Slot Register */
-#define IO_REG_FLOPPY_SLOT      0x1a0   /* Floppy Slot Register */
-
-                                        /* all systems */
-#define IO_REG_SCSI_SCR         0x1b0   /* SCSI Partial-Word DMA Control */
-#define IO_REG_SCSI_SDR0        0x1c0   /* SCSI DMA Partial Word 0 */
-#define IO_REG_SCSI_SDR1        0x1d0   /* SCSI DMA Partial Word 1 */
-#define IO_REG_FCTR             0x1e0   /* Free-Running Counter */
-#define IO_REG_RES_31           0x1f0   /* unused */
-
-
-/*
- * The upper 16 bits of the System Support Register are a part of the
- * I/O ASIC's internal DMA engine and thus are common to all I/O ASIC
- * machines.  The exception is the Maxine, which makes use of the
- * FLOPPY and ISDN bits (otherwise unused) and has a different SCC
- * wiring.
- */
-                                                /* all systems */
-#define IO_SSR_SCC0A_TX_DMA_EN  (1<<31)         /* SCC0A transmit DMA enable */
-#define IO_SSR_SCC0A_RX_DMA_EN  (1<<30)         /* SCC0A receive DMA enable */
-#define IO_SSR_RES_27           (1<<27)         /* unused */
-#define IO_SSR_RES_26           (1<<26)         /* unused */
-#define IO_SSR_RES_25           (1<<25)         /* unused */
-#define IO_SSR_RES_24           (1<<24)         /* unused */
-#define IO_SSR_RES_23           (1<<23)         /* unused */
-#define IO_SSR_SCSI_DMA_DIR     (1<<18)         /* SCSI DMA direction */
-#define IO_SSR_SCSI_DMA_EN      (1<<17)         /* SCSI DMA enable */
-#define IO_SSR_LANCE_DMA_EN     (1<<16)         /* LANCE DMA enable */
-
-                                                /* except Maxine */
-#define IO_SSR_SCC1A_TX_DMA_EN  (1<<29)         /* SCC1A transmit DMA enable */
-#define IO_SSR_SCC1A_RX_DMA_EN  (1<<28)         /* SCC1A receive DMA enable */
-#define IO_SSR_RES_22           (1<<22)         /* unused */
-#define IO_SSR_RES_21           (1<<21)         /* unused */
-#define IO_SSR_RES_20           (1<<20)         /* unused */
-#define IO_SSR_RES_19           (1<<19)         /* unused */
-
-                                                /* Maxine */
-#define IO_SSR_AB_TX_DMA_EN     (1<<29)         /* ACCESS.bus xmit DMA enable */
-#define IO_SSR_AB_RX_DMA_EN     (1<<28)         /* ACCESS.bus recv DMA enable */
-#define IO_SSR_FLOPPY_DMA_DIR   (1<<22)         /* Floppy DMA direction */
-#define IO_SSR_FLOPPY_DMA_EN    (1<<21)         /* Floppy DMA enable */
-#define IO_SSR_ISDN_TX_DMA_EN   (1<<20)         /* ISDN transmit DMA enable */
-#define IO_SSR_ISDN_RX_DMA_EN   (1<<19)         /* ISDN receive DMA enable */
-
-/*
- * The lower 16 bits are system-specific.  Bits 15,11:8 are common and
- * defined here.  The rest is defined in system-specific headers.
- */
-#define KN0X_IO_SSR_DIAGDN      (1<<15)         /* diagnostic jumper */
-#define KN0X_IO_SSR_SCC_RST     (1<<11)         /* ~SCC0,1 (Z85C30) reset */
-#define KN0X_IO_SSR_RTC_RST     (1<<10)         /* ~RTC (DS1287) reset */
-#define KN0X_IO_SSR_ASC_RST     (1<<9)          /* ~ASC (NCR53C94) reset */
-#define KN0X_IO_SSR_LANCE_RST   (1<<8)          /* ~LANCE (Am7990) reset */
-
-#endif /* __ASM_MIPS_DEC_IOASIC_ADDRS_H */
diff --git a/include/asm-mips/dec/ioasic_ints.h b/include/asm-mips/dec/ioasic_ints.h
deleted file mode 100644
index 9aaa9869615f..000000000000
--- a/include/asm-mips/dec/ioasic_ints.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Definitions for the interrupt related bits in the I/O ASIC
- * interrupt status register (and the interrupt mask register, of course)
- *
- * Created with Information from:
- *
- * "DEC 3000 300/400/500/600/700/800/900 AXP Models System Programmer's Manual"
- *
- * and the Mach Sources
- *
- * Copyright (C) 199x  the Anonymous
- * Copyright (C) 2002  Maciej W. Rozycki
- */
-
-#ifndef __ASM_DEC_IOASIC_INTS_H
-#define __ASM_DEC_IOASIC_INTS_H
-
-/*
- * The upper 16 bits are a part of the I/O ASIC's internal DMA engine
- * and thus are common to all I/O ASIC machines.  The exception is
- * the Maxine, which makes use of the FLOPPY and ISDN bits (otherwise
- * unused) and has a different SCC wiring.
- */
-                                        /* all systems */
-#define IO_INR_SCC0A_TXDMA      31      /* SCC0A transmit page end */
-#define IO_INR_SCC0A_TXERR      30      /* SCC0A transmit memory read error */
-#define IO_INR_SCC0A_RXDMA      29      /* SCC0A receive half page */
-#define IO_INR_SCC0A_RXERR      28      /* SCC0A receive overrun */
-#define IO_INR_ASC_DMA          19      /* ASC buffer pointer loaded */
-#define IO_INR_ASC_ERR          18      /* ASC page overrun */
-#define IO_INR_ASC_MERR         17      /* ASC memory read error */
-#define IO_INR_LANCE_MERR       16      /* LANCE memory read error */
-
-                                        /* except Maxine */
-#define IO_INR_SCC1A_TXDMA      27      /* SCC1A transmit page end */
-#define IO_INR_SCC1A_TXERR      26      /* SCC1A transmit memory read error */
-#define IO_INR_SCC1A_RXDMA      25      /* SCC1A receive half page */
-#define IO_INR_SCC1A_RXERR      24      /* SCC1A receive overrun */
-#define IO_INR_RES_23           23      /* unused */
-#define IO_INR_RES_22           22      /* unused */
-#define IO_INR_RES_21           21      /* unused */
-#define IO_INR_RES_20           20      /* unused */
-
-                                        /* Maxine */
-#define IO_INR_AB_TXDMA         27      /* ACCESS.bus transmit page end */
-#define IO_INR_AB_TXERR         26      /* ACCESS.bus xmit memory read error */
-#define IO_INR_AB_RXDMA         25      /* ACCESS.bus receive half page */
-#define IO_INR_AB_RXERR         24      /* ACCESS.bus receive overrun */
-#define IO_INR_FLOPPY_ERR       23      /* FDC error */
-#define IO_INR_ISDN_TXDMA       22      /* ISDN xmit buffer pointer loaded */
-#define IO_INR_ISDN_RXDMA       21      /* ISDN recv buffer pointer loaded */
-#define IO_INR_ISDN_ERR         20      /* ISDN memory read/overrun error */
-
-#define IO_INR_DMA              16      /* first DMA IRQ */
-
-/*
- * The lower 16 bits are system-specific and thus defined in
- * system-specific headers.
- */
-
-
-#define IO_IRQ_BASE             8       /* first IRQ assigned to I/O ASIC */
-#define IO_IRQ_LINES            32      /* number of I/O ASIC interrupts */
-
-#define IO_IRQ_NR(n)            ((n) + IO_IRQ_BASE)
-#define IO_IRQ_MASK(n)          (1 << (n))
-#define IO_IRQ_ALL              0x0000ffff
-#define IO_IRQ_DMA              0xffff0000
-
-#endif /* __ASM_DEC_IOASIC_INTS_H */
diff --git a/include/asm-mips/dec/kn01.h b/include/asm-mips/dec/kn01.h
deleted file mode 100644
index 28fa717ac423..000000000000
--- a/include/asm-mips/dec/kn01.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- * Hardware info about DECstation DS2100/3100 systems (otherwise known as
- * pmin/pmax or KN01).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
- */
-#ifndef __ASM_MIPS_DEC_KN01_H
-#define __ASM_MIPS_DEC_KN01_H
-
-#define KN01_SLOT_BASE  0x10000000
-#define KN01_SLOT_SIZE  0x01000000
-
-/*
- * Address ranges for devices.
- */
-#define KN01_PMASK      (0*KN01_SLOT_SIZE)      /* color plane mask */
-#define KN01_PCC        (1*KN01_SLOT_SIZE)      /* PCC (DC503) cursor */
-#define KN01_VDAC       (2*KN01_SLOT_SIZE)      /* color map */
-#define KN01_RES_3      (3*KN01_SLOT_SIZE)      /* unused */
-#define KN01_RES_4      (4*KN01_SLOT_SIZE)      /* unused */
-#define KN01_RES_5      (5*KN01_SLOT_SIZE)      /* unused */
-#define KN01_RES_6      (6*KN01_SLOT_SIZE)      /* unused */
-#define KN01_ERRADDR    (7*KN01_SLOT_SIZE)      /* write error address */
-#define KN01_LANCE      (8*KN01_SLOT_SIZE)      /* LANCE (Am7990) Ethernet */
-#define KN01_LANCE_MEM  (9*KN01_SLOT_SIZE)      /* LANCE buffer memory */
-#define KN01_SII        (10*KN01_SLOT_SIZE)     /* SII (DC7061) SCSI */
-#define KN01_SII_MEM    (11*KN01_SLOT_SIZE)     /* SII buffer memory */
-#define KN01_DZ11       (12*KN01_SLOT_SIZE)     /* DZ11 (DC7085) serial */
-#define KN01_RTC        (13*KN01_SLOT_SIZE)     /* DS1287 RTC (bytes #0) */
-#define KN01_ESAR       (13*KN01_SLOT_SIZE)     /* MAC address (bytes #1) */
-#define KN01_CSR        (14*KN01_SLOT_SIZE)     /* system ctrl & status reg */
-#define KN01_SYS_ROM    (15*KN01_SLOT_SIZE)     /* system board ROM */
-
-
-/*
- * Frame buffer memory address.
- */
-#define KN01_VFB_MEM    0x0fc00000
-
-/*
- * CPU interrupt bits.
- */
-#define KN01_CPU_INR_BUS        6       /* memory, I/O bus read/write errors */
-#define KN01_CPU_INR_VIDEO      6       /* PCC area detect #2 */
-#define KN01_CPU_INR_RTC        5       /* DS1287 RTC */
-#define KN01_CPU_INR_DZ11       4       /* DZ11 (DC7085) serial */
-#define KN01_CPU_INR_LANCE      3       /* LANCE (Am7990) Ethernet */
-#define KN01_CPU_INR_SII        2       /* SII (DC7061) SCSI */
-
-
-/*
- * System Control & Status Register bits.
- */
-#define KN01_CSR_MNFMOD         (1<<15) /* MNFMOD manufacturing jumper */
-#define KN01_CSR_STATUS         (1<<14) /* self-test result status output */
-#define KN01_CSR_PARDIS         (1<<13) /* parity error disable */
-#define KN01_CSR_CRSRTST        (1<<12) /* PCC test output */
-#define KN01_CSR_MONO           (1<<11) /* mono/color fb SIMM installed */
-#define KN01_CSR_MEMERR         (1<<10) /* write timeout error status & ack*/
-#define KN01_CSR_VINT           (1<<9)  /* PCC area detect #2 status & ack */
-#define KN01_CSR_TXDIS          (1<<8)  /* DZ11 transmit disable */
-#define KN01_CSR_VBGTRG         (1<<2)  /* blue DAC voltage over green (r/o) */
-#define KN01_CSR_VRGTRG         (1<<1)  /* red DAC voltage over green (r/o) */
-#define KN01_CSR_VRGTRB         (1<<0)  /* red DAC voltage over blue (r/o) */
-#define KN01_CSR_LEDS           (0xff<<0) /* ~diagnostic LEDs (w/o) */
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-#include <linux/spinlock.h>
-#include <linux/types.h>
-
-struct pt_regs;
-
-extern u16 cached_kn01_csr;
-extern spinlock_t kn01_lock;
-
-extern void dec_kn01_be_init(void);
-extern int dec_kn01_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_kn01_be_interrupt(int irq, void *dev_id);
-#endif
-
-#endif /* __ASM_MIPS_DEC_KN01_H */
diff --git a/include/asm-mips/dec/kn02.h b/include/asm-mips/dec/kn02.h
deleted file mode 100644
index 93430b5f4724..000000000000
--- a/include/asm-mips/dec/kn02.h
+++ /dev/null
@@ -1,91 +0,0 @@
-/*
- * Hardware info about DECstation 5000/200 systems (otherwise known as
- * 3max or KN02).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2002, 2003, 2005  Maciej W. Rozycki
- */
-#ifndef __ASM_MIPS_DEC_KN02_H
-#define __ASM_MIPS_DEC_KN02_H
-
-#define KN02_SLOT_BASE  0x1fc00000
-#define KN02_SLOT_SIZE  0x00080000
-
-/*
- * Address ranges decoded by the "system slot" logic for onboard devices.
- */
-#define KN02_SYS_ROM    (0*KN02_SLOT_SIZE)      /* system board ROM */
-#define KN02_RES_1      (1*KN02_SLOT_SIZE)      /* unused */
-#define KN02_CHKSYN     (2*KN02_SLOT_SIZE)      /* ECC syndrome */
-#define KN02_ERRADDR    (3*KN02_SLOT_SIZE)      /* bus error address */
-#define KN02_DZ11       (4*KN02_SLOT_SIZE)      /* DZ11 (DC7085) serial */
-#define KN02_RTC        (5*KN02_SLOT_SIZE)      /* DS1287 RTC */
-#define KN02_CSR        (6*KN02_SLOT_SIZE)      /* system ctrl & status reg */
-#define KN02_SYS_ROM_7  (7*KN02_SLOT_SIZE)      /* system board ROM (alias) */
-
-
-/*
- * System Control & Status Register bits.
- */
-#define KN02_CSR_RES_28         (0xf<<28)       /* unused */
-#define KN02_CSR_PSU            (1<<27)         /* power supply unit warning */
-#define KN02_CSR_NVRAM          (1<<26)         /* ~NVRAM clear jumper */
-#define KN02_CSR_REFEVEN        (1<<25)         /* mem refresh bank toggle */
-#define KN02_CSR_NRMOD          (1<<24)         /* ~NRMOD manufact. jumper */
-#define KN02_CSR_IOINTEN        (0xff<<16)      /* IRQ mask bits */
-#define KN02_CSR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
-#define KN02_CSR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
-#define KN02_CSR_CORRECT        (1<<13)         /* ECC correct/check */
-#define KN02_CSR_LEDIAG         (1<<12)         /* ECC diagn. latch strobe */
-#define KN02_CSR_TXDIS          (1<<11)         /* DZ11 transmit disable */
-#define KN02_CSR_BNK32M         (1<<10)         /* 32M/8M stride */
-#define KN02_CSR_DIAGDN         (1<<9)          /* DIAGDN manufact. jumper */
-#define KN02_CSR_BAUD38         (1<<8)          /* DZ11 38/19kbps ext. rate */
-#define KN02_CSR_IOINT          (0xff<<0)       /* IRQ status bits (r/o) */
-#define KN02_CSR_LEDS           (0xff<<0)       /* ~diagnostic LEDs (w/o) */
-
-
-/*
- * CPU interrupt bits.
- */
-#define KN02_CPU_INR_RES_6      6       /* unused */
-#define KN02_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
-#define KN02_CPU_INR_RES_4      4       /* unused */
-#define KN02_CPU_INR_RTC        3       /* DS1287 RTC */
-#define KN02_CPU_INR_CASCADE    2       /* CSR cascade */
-
-/*
- * CSR interrupt bits.
- */
-#define KN02_CSR_INR_DZ11       7       /* DZ11 (DC7085) serial */
-#define KN02_CSR_INR_LANCE      6       /* LANCE (Am7990) Ethernet */
-#define KN02_CSR_INR_ASC        5       /* ASC (NCR53C94) SCSI */
-#define KN02_CSR_INR_RES_4      4       /* unused */
-#define KN02_CSR_INR_RES_3      3       /* unused */
-#define KN02_CSR_INR_TC2        2       /* TURBOchannel slot #2 */
-#define KN02_CSR_INR_TC1        1       /* TURBOchannel slot #1 */
-#define KN02_CSR_INR_TC0        0       /* TURBOchannel slot #0 */
-
-
-#define KN02_IRQ_BASE           8       /* first IRQ assigned to CSR */
-#define KN02_IRQ_LINES          8       /* number of CSR interrupts */
-
-#define KN02_IRQ_NR(n)          ((n) + KN02_IRQ_BASE)
-#define KN02_IRQ_MASK(n)        (1 << (n))
-#define KN02_IRQ_ALL            0xff
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/types.h>
-
-extern u32 cached_kn02_csr;
-extern void init_kn02_irqs(int base);
-#endif
-
-#endif /* __ASM_MIPS_DEC_KN02_H */
diff --git a/include/asm-mips/dec/kn02ba.h b/include/asm-mips/dec/kn02ba.h
deleted file mode 100644
index c957a4f1b32d..000000000000
--- a/include/asm-mips/dec/kn02ba.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- *      include/asm-mips/dec/kn02ba.h
- *
- *      DECstation 5000/1xx (3min or KN02-BA) definitions.
- *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_KN02BA_H
-#define __ASM_MIPS_DEC_KN02BA_H
-
-#include <asm/dec/kn02xa.h>             /* For common definitions. */
-
-/*
- * CPU interrupt bits.
- */
-#define KN02BA_CPU_INR_HALT     6       /* HALT button */
-#define KN02BA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
-#define KN02BA_CPU_INR_TC2      4       /* TURBOchannel slot #2 */
-#define KN02BA_CPU_INR_TC1      3       /* TURBOchannel slot #1 */
-#define KN02BA_CPU_INR_TC0      2       /* TURBOchannel slot #0 */
-
-/*
- * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
- */
-#define KN02BA_IO_INR_RES_15    15      /* unused */
-#define KN02BA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
-#define KN02BA_IO_INR_RES_13    13      /* unused */
-#define KN02BA_IO_INR_BUS       12      /* memory, I/O bus read/write errors */
-#define KN02BA_IO_INR_RES_11    11      /* unused */
-#define KN02BA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
-#define KN02BA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
-#define KN02BA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
-#define KN02BA_IO_INR_SCC1      7       /* SCC (Z85C30) serial #1 */
-#define KN02BA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
-#define KN02BA_IO_INR_RTC       5       /* DS1287 RTC */
-#define KN02BA_IO_INR_PSU       4       /* power supply unit warning */
-#define KN02BA_IO_INR_RES_3     3       /* unused */
-#define KN02BA_IO_INR_ASC_DATA  2       /* SCSI data ready (for PIO) */
-#define KN02BA_IO_INR_PBNC      1       /* ~HALT button debouncer */
-#define KN02BA_IO_INR_PBNO      0       /* HALT button debouncer */
-
-
-/*
- * Memory Error Register bits.
- */
-#define KN02BA_MER_RES_27       (1<<27)         /* unused */
-
-/*
- * Memory Size Register bits.
- */
-#define KN02BA_MSR_RES_17       (0x3ff<<17)     /* unused */
-
-/*
- * I/O ASIC System Support Register bits.
- */
-#define KN02BA_IO_SSR_TXDIS1    (1<<14)         /* SCC1 transmit disable */
-#define KN02BA_IO_SSR_TXDIS0    (1<<13)         /* SCC0 transmit disable */
-#define KN02BA_IO_SSR_RES_12    (1<<12)         /* unused */
-
-#define KN02BA_IO_SSR_LEDS      (0xff<<0)       /* ~diagnostic LEDs */
-
-#endif /* __ASM_MIPS_DEC_KN02BA_H */
diff --git a/include/asm-mips/dec/kn02ca.h b/include/asm-mips/dec/kn02ca.h
deleted file mode 100644
index 92c0fe256099..000000000000
--- a/include/asm-mips/dec/kn02ca.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- *      include/asm-mips/dec/kn02ca.h
- *
- *      Personal DECstation 5000/xx (Maxine or KN02-CA) definitions.
- *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_KN02CA_H
-#define __ASM_MIPS_DEC_KN02CA_H
-
-#include <asm/dec/kn02xa.h>             /* For common definitions. */
-
-/*
- * CPU interrupt bits.
- */
-#define KN02CA_CPU_INR_HALT     6       /* HALT from ACCESS.Bus */
-#define KN02CA_CPU_INR_CASCADE  5       /* I/O ASIC cascade */
-#define KN02CA_CPU_INR_BUS      4       /* memory, I/O bus read/write errors */
-#define KN02CA_CPU_INR_RTC      3       /* DS1287 RTC */
-#define KN02CA_CPU_INR_TIMER    2       /* ARC periodic timer */
-
-/*
- * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
- */
-#define KN02CA_IO_INR_FLOPPY    15      /* 82077 FDC */
-#define KN02CA_IO_INR_NVRAM     14      /* (*) NVRAM clear jumper */
-#define KN02CA_IO_INR_POWERON   13      /* (*) ACCESS.Bus/power-on reset */
-#define KN02CA_IO_INR_TC0       12      /* TURBOchannel slot #0 */
-#define KN02CA_IO_INR_TIMER     12      /* ARC periodic timer (?) */
-#define KN02CA_IO_INR_ISDN      11      /* Am79C30A ISDN */
-#define KN02CA_IO_INR_NRMOD     10      /* (*) NRMOD manufacturing jumper */
-#define KN02CA_IO_INR_ASC       9       /* ASC (NCR53C94) SCSI */
-#define KN02CA_IO_INR_LANCE     8       /* LANCE (Am7990) Ethernet */
-#define KN02CA_IO_INR_HDFLOPPY  7       /* (*) HD (1.44MB) floppy status */
-#define KN02CA_IO_INR_SCC0      6       /* SCC (Z85C30) serial #0 */
-#define KN02CA_IO_INR_TC1       5       /* TURBOchannel slot #1 */
-#define KN02CA_IO_INR_XDFLOPPY  4       /* (*) XD (2.88MB) floppy status */
-#define KN02CA_IO_INR_VIDEO     3       /* framebuffer */
-#define KN02CA_IO_INR_XVIDEO    2       /* ~framebuffer */
-#define KN02CA_IO_INR_AB_XMIT   1       /* ACCESS.bus transmit */
-#define KN02CA_IO_INR_AB_RECV   0       /* ACCESS.bus receive */
-
-
-/*
- * Memory Error Register bits.
- */
-#define KN02CA_MER_INTR         (1<<27)         /* ARC IRQ status & ack */
-
-/*
- * Memory Size Register bits.
- */
-#define KN02CA_MSR_INTREN       (1<<26)         /* ARC periodic IRQ enable */
-#define KN02CA_MSR_MS10EN       (1<<25)         /* 10/1ms IRQ period select */
-#define KN02CA_MSR_PFORCE       (0xf<<21)       /* byte lane error force */
-#define KN02CA_MSR_MABEN        (1<<20)         /* A side VFB address enable */
-#define KN02CA_MSR_LASTBANK     (0x7<<17)       /* onboard RAM bank # */
-
-/*
- * I/O ASIC System Support Register bits.
- */
-#define KN03CA_IO_SSR_RES_14    (1<<14)         /* unused */
-#define KN03CA_IO_SSR_RES_13    (1<<13)         /* unused */
-#define KN03CA_IO_SSR_ISDN_RST  (1<<12)         /* ~ISDN (Am79C30A) reset */
-
-#define KN03CA_IO_SSR_FLOPPY_RST (1<<7)         /* ~FDC (82077) reset */
-#define KN03CA_IO_SSR_VIDEO_RST (1<<6)          /* ~framebuffer reset */
-#define KN03CA_IO_SSR_AB_RST    (1<<5)          /* ACCESS.bus reset */
-#define KN03CA_IO_SSR_RES_4     (1<<4)          /* unused */
-#define KN03CA_IO_SSR_RES_3     (1<<4)          /* unused */
-#define KN03CA_IO_SSR_RES_2     (1<<2)          /* unused */
-#define KN03CA_IO_SSR_RES_1     (1<<1)          /* unused */
-#define KN03CA_IO_SSR_LED       (1<<0)          /* power LED */
-
-#endif /* __ASM_MIPS_DEC_KN02CA_H */
diff --git a/include/asm-mips/dec/kn02xa.h b/include/asm-mips/dec/kn02xa.h
deleted file mode 100644
index b56b4577f6ef..000000000000
--- a/include/asm-mips/dec/kn02xa.h
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Hardware info common to DECstation 5000/1xx systems (otherwise
- * known as 3min or kn02ba) and Personal DECstations 5000/xx ones
- * (otherwise known as maxine or kn02ca).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
- *
- * These are addresses which have to be known early in the boot process.
- * For other addresses refer to tc.h, ioasic_addrs.h and friends.
- */
-#ifndef __ASM_MIPS_DEC_KN02XA_H
-#define __ASM_MIPS_DEC_KN02XA_H
-
-#include <asm/dec/ioasic_addrs.h>
-
-#define KN02XA_SLOT_BASE        0x1c000000
-
-/*
- * Memory control ASIC registers.
- */
-#define KN02XA_MER              0x0c400000      /* memory error register */
-#define KN02XA_MSR              0x0c800000      /* memory size register */
-
-/*
- * CPU control ASIC registers.
- */
-#define KN02XA_MEM_CONF         0x0e000000      /* write timeout config */
-#define KN02XA_EAR              0x0e000004      /* error address register */
-#define KN02XA_BOOT0            0x0e000008      /* boot 0 register */
-#define KN02XA_MEM_INTR         0x0e00000c      /* write err IRQ stat & ack */
-
-/*
- * Memory Error Register bits, common definitions.
- * The rest is defined in system-specific headers.
- */
-#define KN02XA_MER_RES_28       (0xf<<28)       /* unused */
-#define KN02XA_MER_RES_17       (0x3ff<<17)     /* unused */
-#define KN02XA_MER_PAGERR       (1<<16)         /* 2k page boundary error */
-#define KN02XA_MER_TRANSERR     (1<<15)         /* transfer length error */
-#define KN02XA_MER_PARDIS       (1<<14)         /* parity error disable */
-#define KN02XA_MER_SIZE         (1<<13)         /* r/o mirror of MSR_SIZE */
-#define KN02XA_MER_RES_12       (1<<12)         /* unused */
-#define KN02XA_MER_BYTERR       (0xf<<8)        /* byte lane error bitmask: */
-#define KN02XA_MER_BYTERR_3     (0x8<<8)        /* byte lane #3 */
-#define KN02XA_MER_BYTERR_2     (0x4<<8)        /* byte lane #2 */
-#define KN02XA_MER_BYTERR_1     (0x2<<8)        /* byte lane #1 */
-#define KN02XA_MER_BYTERR_0     (0x1<<8)        /* byte lane #0 */
-#define KN02XA_MER_RES_0        (0xff<<0)       /* unused */
-
-/*
- * Memory Size Register bits, common definitions.
- * The rest is defined in system-specific headers.
- */
-#define KN02XA_MSR_RES_27       (0x1f<<27)      /* unused */
-#define KN02XA_MSR_RES_14       (0x7<<14)       /* unused */
-#define KN02XA_MSR_SIZE         (1<<13)         /* 16M/4M stride */
-#define KN02XA_MSR_RES_0        (0x1fff<<0)     /* unused */
-
-/*
- * Error Address Register bits.
- */
-#define KN02XA_EAR_RES_29       (0x7<<29)       /* unused */
-#define KN02XA_EAR_ADDRESS      (0x7ffffff<<2)  /* address involved */
-#define KN02XA_EAR_RES_0        (0x3<<0)        /* unused */
-
-
-#ifndef __ASSEMBLY__
-
-#include <linux/interrupt.h>
-
-struct pt_regs;
-
-extern void dec_kn02xa_be_init(void);
-extern int dec_kn02xa_be_handler(struct pt_regs *regs, int is_fixup);
-extern irqreturn_t dec_kn02xa_be_interrupt(int irq, void *dev_id);
-#endif
-
-#endif /* __ASM_MIPS_DEC_KN02XA_H */
diff --git a/include/asm-mips/dec/kn03.h b/include/asm-mips/dec/kn03.h
deleted file mode 100644
index edede923ffb8..000000000000
--- a/include/asm-mips/dec/kn03.h
+++ /dev/null
@@ -1,74 +0,0 @@
-/*
- * Hardware info about DECstation 5000/2x0 systems (otherwise known as
- * 3max+) and DECsystem 5900 systems (otherwise known as bigmax) which
- * differ mechanically but are otherwise identical (both are known as
- * KN03).
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995,1996 by Paul M. Antoine, some code and definitions
- * are by courtesy of Chris Fraser.
- * Copyright (C) 2000, 2002, 2003, 2005  Maciej W. Rozycki
- */
-#ifndef __ASM_MIPS_DEC_KN03_H
-#define __ASM_MIPS_DEC_KN03_H
-
-#include <asm/dec/ecc.h>
-#include <asm/dec/ioasic_addrs.h>
-
-#define KN03_SLOT_BASE          0x1f800000
-
-/*
- * CPU interrupt bits.
- */
-#define KN03_CPU_INR_HALT       6       /* HALT button */
-#define KN03_CPU_INR_BUS        5       /* memory, I/O bus read/write errors */
-#define KN03_CPU_INR_RES_4      4       /* unused */
-#define KN03_CPU_INR_RTC        3       /* DS1287 RTC */
-#define KN03_CPU_INR_CASCADE    2       /* I/O ASIC cascade */
-
-/*
- * I/O ASIC interrupt bits.  Star marks denote non-IRQ status bits.
- */
-#define KN03_IO_INR_3MAXP       15      /* (*) 3max+/bigmax ID */
-#define KN03_IO_INR_NVRAM       14      /* (*) NVRAM clear jumper */
-#define KN03_IO_INR_TC2         13      /* TURBOchannel slot #2 */
-#define KN03_IO_INR_TC1         12      /* TURBOchannel slot #1 */
-#define KN03_IO_INR_TC0         11      /* TURBOchannel slot #0 */
-#define KN03_IO_INR_NRMOD       10      /* (*) NRMOD manufacturing jumper */
-#define KN03_IO_INR_ASC         9       /* ASC (NCR53C94) SCSI */
-#define KN03_IO_INR_LANCE       8       /* LANCE (Am7990) Ethernet */
-#define KN03_IO_INR_SCC1        7       /* SCC (Z85C30) serial #1 */
-#define KN03_IO_INR_SCC0        6       /* SCC (Z85C30) serial #0 */
-#define KN03_IO_INR_RTC         5       /* DS1287 RTC */
-#define KN03_IO_INR_PSU         4       /* power supply unit warning */
-#define KN03_IO_INR_RES_3       3       /* unused */
-#define KN03_IO_INR_ASC_DATA    2       /* SCSI data ready (for PIO) */
-#define KN03_IO_INR_PBNC        1       /* ~HALT button debouncer */
-#define KN03_IO_INR_PBNO        0       /* HALT button debouncer */
-
-
-/*
- * Memory Control Register bits.
- */
-#define KN03_MCR_RES_16         (0xffff<<16)    /* unused */
-#define KN03_MCR_DIAGCHK        (1<<15)         /* diagn/norml ECC reads */
-#define KN03_MCR_DIAGGEN        (1<<14)         /* diagn/norml ECC writes */
-#define KN03_MCR_CORRECT        (1<<13)         /* ECC correct/check */
-#define KN03_MCR_RES_11         (0x3<<12)       /* unused */
-#define KN03_MCR_BNK32M         (1<<10)         /* 32M/8M stride */
-#define KN03_MCR_RES_7          (0x7<<7)        /* unused */
-#define KN03_MCR_CHECK          (0x7f<<0)       /* diagnostic check bits */
-
-/*
- * I/O ASIC System Support Register bits.
- */
-#define KN03_IO_SSR_TXDIS1      (1<<14)         /* SCC1 transmit disable */
-#define KN03_IO_SSR_TXDIS0      (1<<13)         /* SCC0 transmit disable */
-#define KN03_IO_SSR_RES_12      (1<<12)         /* unused */
-
-#define KN03_IO_SSR_LEDS        (0xff<<0)       /* ~diagnostic LEDs */
-
-#endif /* __ASM_MIPS_DEC_KN03_H */
diff --git a/include/asm-mips/dec/kn05.h b/include/asm-mips/dec/kn05.h
deleted file mode 100644
index 56d22dc8803a..000000000000
--- a/include/asm-mips/dec/kn05.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- *      include/asm-mips/dec/kn05.h
- *
- *      DECstation/DECsystem 5000/260 (4max+ or KN05), 5000/150 (4min
- *      or KN04-BA), Personal DECstation/DECsystem 5000/50 (4maxine or
- *      KN04-CA) and DECsystem 5900/260 (KN05) R4k CPU card MB ASIC
- *      definitions.
- *
- *      Copyright (C) 2002, 2003, 2005, 2008  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- *
- *      WARNING!  All this information is pure guesswork based on the
- *      ROM.  It is provided here in hope it will give someone some
- *      food for thought.  No documentation for the KN05 nor the KN04
- *      module has been located so far.
- */
-#ifndef __ASM_MIPS_DEC_KN05_H
-#define __ASM_MIPS_DEC_KN05_H
-
-#include <asm/dec/ioasic_addrs.h>
-
-/*
- * The oncard MB (Memory Buffer) ASIC provides an additional address
- * decoder.  Certain address ranges within the "high" 16 slots are
- * passed to the I/O ASIC's decoder like with the KN03 or KN02-BA/CA.
- * Others are handled locally.  "Low" slots are always passed.
- */
-#define KN4K_SLOT_BASE  0x1fc00000
-
-#define KN4K_MB_ROM     (0*IOASIC_SLOT_SIZE)    /* KN05/KN04 card ROM */
-#define KN4K_IOCTL      (1*IOASIC_SLOT_SIZE)    /* I/O ASIC */
-#define KN4K_ESAR       (2*IOASIC_SLOT_SIZE)    /* LANCE MAC address chip */
-#define KN4K_LANCE      (3*IOASIC_SLOT_SIZE)    /* LANCE Ethernet */
-#define KN4K_MB_INT     (4*IOASIC_SLOT_SIZE)    /* MB interrupt register */
-#define KN4K_MB_EA      (5*IOASIC_SLOT_SIZE)    /* MB error address? */
-#define KN4K_MB_EC      (6*IOASIC_SLOT_SIZE)    /* MB error ??? */
-#define KN4K_MB_CSR     (7*IOASIC_SLOT_SIZE)    /* MB control & status */
-#define KN4K_RES_08     (8*IOASIC_SLOT_SIZE)    /* unused? */
-#define KN4K_RES_09     (9*IOASIC_SLOT_SIZE)    /* unused? */
-#define KN4K_RES_10     (10*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN4K_RES_11     (11*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN4K_SCSI       (12*IOASIC_SLOT_SIZE)   /* ASC SCSI */
-#define KN4K_RES_13     (13*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN4K_RES_14     (14*IOASIC_SLOT_SIZE)   /* unused? */
-#define KN4K_RES_15     (15*IOASIC_SLOT_SIZE)   /* unused? */
-
-/*
- * Bits for the MB interrupt register.
- * The register appears read-only.
- */
-#define KN4K_MB_INT_TC          (1<<0)          /* TURBOchannel? */
-#define KN4K_MB_INT_RTC         (1<<1)          /* RTC? */
-#define KN4K_MB_INT_MT          (1<<3)          /* I/O ASIC cascade */
-
-/*
- * Bits for the MB control & status register.
- * Set to 0x00bf8001 for KN05 and to 0x003f8000 for KN04 by the firmware.
- */
-#define KN4K_MB_CSR_PF          (1<<0)          /* PreFetching enable? */
-#define KN4K_MB_CSR_F           (1<<1)          /* ??? */
-#define KN4K_MB_CSR_ECC         (0xff<<2)       /* ??? */
-#define KN4K_MB_CSR_OD          (1<<10)         /* ??? */
-#define KN4K_MB_CSR_CP          (1<<11)         /* ??? */
-#define KN4K_MB_CSR_UNC         (1<<12)         /* ??? */
-#define KN4K_MB_CSR_IM          (1<<13)         /* ??? */
-#define KN4K_MB_CSR_NC          (1<<14)         /* ??? */
-#define KN4K_MB_CSR_EE          (1<<15)         /* (bus) Exception Enable? */
-#define KN4K_MB_CSR_MSK         (0x1f<<16)      /* CPU Int[4:0] mask */
-#define KN4K_MB_CSR_FW          (1<<21)         /* ??? */
-#define KN4K_MB_CSR_W           (1<<31)         /* ??? */
-
-#endif /* __ASM_MIPS_DEC_KN05_H */
diff --git a/include/asm-mips/dec/kn230.h b/include/asm-mips/dec/kn230.h
deleted file mode 100644
index ff1bf17de8d8..000000000000
--- a/include/asm-mips/dec/kn230.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- *      include/asm-mips/dec/kn230.h
- *
- *      DECsystem 5100 (MIPSmate or KN230) definitions.
- *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_KN230_H
-#define __ASM_MIPS_DEC_KN230_H
-
-/*
- * CPU interrupt bits.
- */
-#define KN230_CPU_INR_HALT      6       /* HALT button */
-#define KN230_CPU_INR_BUS       5       /* memory, I/O bus read/write errors */
-#define KN230_CPU_INR_RTC       4       /* DS1287 RTC */
-#define KN230_CPU_INR_SII       3       /* SII (DC7061) SCSI */
-#define KN230_CPU_INR_LANCE     3       /* LANCE (Am7990) Ethernet */
-#define KN230_CPU_INR_DZ11      2       /* DZ11 (DC7085) serial */
-
-#endif /* __ASM_MIPS_DEC_KN230_H */
diff --git a/include/asm-mips/dec/machtype.h b/include/asm-mips/dec/machtype.h
deleted file mode 100644
index a6ecdebc430a..000000000000
--- a/include/asm-mips/dec/machtype.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * Various machine type macros
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1998, 2000 Harald Koerfgen
- */
-
-#ifndef __ASM_DEC_MACHTYPE_H
-#define __ASM_DEC_MACHTYPE_H
-
-#include <asm/bootinfo.h>
-
-#define TURBOCHANNEL    (mips_machtype == MACH_DS5000_200 || \
-                         mips_machtype == MACH_DS5000_1XX || \
-                         mips_machtype == MACH_DS5000_XX  || \
-                         mips_machtype == MACH_DS5000_2X0 || \
-                         mips_machtype == MACH_DS5900)
-
-#define IOASIC          (mips_machtype == MACH_DS5000_1XX || \
-                         mips_machtype == MACH_DS5000_XX  || \
-                         mips_machtype == MACH_DS5000_2X0 || \
-                         mips_machtype == MACH_DS5900)
-
-#endif
diff --git a/include/asm-mips/dec/prom.h b/include/asm-mips/dec/prom.h
deleted file mode 100644
index b9c8203688d5..000000000000
--- a/include/asm-mips/dec/prom.h
+++ /dev/null
@@ -1,174 +0,0 @@
-/*
- *      include/asm-mips/dec/prom.h
- *
- *      DECstation PROM interface.
- *
- *      Copyright (C) 2002  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- *
- *      Based on arch/mips/dec/prom/prom.h by the Anonymous.
- */
-#ifndef _ASM_DEC_PROM_H
-#define _ASM_DEC_PROM_H
-
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-
-/*
- * PMAX/3MAX PROM entry points for DS2100/3100's and DS5000/2xx's.
- * Many of these will work for MIPSen as well!
- */
-#define VEC_RESET               (u64 *)CKSEG1ADDR(0x1fc00000)
-                                                        /* Prom base address */
-
-#define PMAX_PROM_ENTRY(x)      (VEC_RESET + (x))       /* Prom jump table */
-
-#define PMAX_PROM_HALT          PMAX_PROM_ENTRY(2)      /* valid on MIPSen */
-#define PMAX_PROM_AUTOBOOT      PMAX_PROM_ENTRY(5)      /* valid on MIPSen */
-#define PMAX_PROM_OPEN          PMAX_PROM_ENTRY(6)
-#define PMAX_PROM_READ          PMAX_PROM_ENTRY(7)
-#define PMAX_PROM_CLOSE         PMAX_PROM_ENTRY(10)
-#define PMAX_PROM_LSEEK         PMAX_PROM_ENTRY(11)
-#define PMAX_PROM_GETCHAR       PMAX_PROM_ENTRY(12)
-#define PMAX_PROM_PUTCHAR       PMAX_PROM_ENTRY(13)     /* 12 on MIPSen */
-#define PMAX_PROM_GETS          PMAX_PROM_ENTRY(15)
-#define PMAX_PROM_PRINTF        PMAX_PROM_ENTRY(17)
-#define PMAX_PROM_GETENV        PMAX_PROM_ENTRY(33)     /* valid on MIPSen */
-
-
-/*
- * Magic number indicating REX PROM available on DECstation.  Found in
- * register a2 on transfer of control to program from PROM.
- */
-#define REX_PROM_MAGIC          0x30464354
-
-#ifdef CONFIG_64BIT
-
-#define prom_is_rex(magic)      1       /* KN04 and KN05 are REX PROMs.  */
-
-#else /* !CONFIG_64BIT */
-
-#define prom_is_rex(magic)      ((magic) == REX_PROM_MAGIC)
-
-#endif /* !CONFIG_64BIT */
-
-
-/*
- * 3MIN/MAXINE PROM entry points for DS5000/1xx's, DS5000/xx's and
- * DS5000/2x0.
- */
-#define REX_PROM_GETBITMAP      0x84/4  /* get mem bitmap */
-#define REX_PROM_GETCHAR        0x24/4  /* getch() */
-#define REX_PROM_GETENV         0x64/4  /* get env. variable */
-#define REX_PROM_GETSYSID       0x80/4  /* get system id */
-#define REX_PROM_GETTCINFO      0xa4/4
-#define REX_PROM_PRINTF         0x30/4  /* printf() */
-#define REX_PROM_SLOTADDR       0x6c/4  /* slotaddr */
-#define REX_PROM_BOOTINIT       0x54/4  /* open() */
-#define REX_PROM_BOOTREAD       0x58/4  /* read() */
-#define REX_PROM_CLEARCACHE     0x7c/4
-
-
-/*
- * Used by rex_getbitmap().
- */
-typedef struct {
-        int pagesize;
-        unsigned char bitmap[0];
-} memmap;
-
-
-/*
- * Function pointers as read from a PROM's callback vector.
- */
-extern int (*__rex_bootinit)(void);
-extern int (*__rex_bootread)(void);
-extern int (*__rex_getbitmap)(memmap *);
-extern unsigned long *(*__rex_slot_address)(int);
-extern void *(*__rex_gettcinfo)(void);
-extern int (*__rex_getsysid)(void);
-extern void (*__rex_clear_cache)(void);
-
-extern int (*__prom_getchar)(void);
-extern char *(*__prom_getenv)(char *);
-extern int (*__prom_printf)(char *, ...);
-
-extern int (*__pmax_open)(char*, int);
-extern int (*__pmax_lseek)(int, long, int);
-extern int (*__pmax_read)(int, void *, int);
-extern int (*__pmax_close)(int);
-
-
-#ifdef CONFIG_64BIT
-
-/*
- * On MIPS64 we have to call PROM functions via a helper
- * dispatcher to accomodate ABI incompatibilities.
- */
-#define __DEC_PROM_O32(fun, arg) fun arg __asm__(#fun); \
-                                 __asm__(#fun " = call_o32")
-
-int __DEC_PROM_O32(_rex_bootinit, (int (*)(void)));
-int __DEC_PROM_O32(_rex_bootread, (int (*)(void)));
-int __DEC_PROM_O32(_rex_getbitmap, (int (*)(memmap *), memmap *));
-unsigned long *__DEC_PROM_O32(_rex_slot_address,
-                             (unsigned long *(*)(int), int));
-void *__DEC_PROM_O32(_rex_gettcinfo, (void *(*)(void)));
-int __DEC_PROM_O32(_rex_getsysid, (int (*)(void)));
-void __DEC_PROM_O32(_rex_clear_cache, (void (*)(void)));
-
-int __DEC_PROM_O32(_prom_getchar, (int (*)(void)));
-char *__DEC_PROM_O32(_prom_getenv, (char *(*)(char *), char *));
-int __DEC_PROM_O32(_prom_printf, (int (*)(char *, ...), char *, ...));
-
-
-#define rex_bootinit()          _rex_bootinit(__rex_bootinit)
-#define rex_bootread()          _rex_bootread(__rex_bootread)
-#define rex_getbitmap(x)        _rex_getbitmap(__rex_getbitmap, x)
-#define rex_slot_address(x)     _rex_slot_address(__rex_slot_address, x)
-#define rex_gettcinfo()         _rex_gettcinfo(__rex_gettcinfo)
-#define rex_getsysid()          _rex_getsysid(__rex_getsysid)
-#define rex_clear_cache()       _rex_clear_cache(__rex_clear_cache)
-
-#define prom_getchar()          _prom_getchar(__prom_getchar)
-#define prom_getenv(x)          _prom_getenv(__prom_getenv, x)
-#define prom_printf(x...)       _prom_printf(__prom_printf, x)
-
-#else /* !CONFIG_64BIT */
-
-/*
- * On plain MIPS we just call PROM functions directly.
- */
-#define rex_bootinit            __rex_bootinit
-#define rex_bootread            __rex_bootread
-#define rex_getbitmap           __rex_getbitmap
-#define rex_slot_address        __rex_slot_address
-#define rex_gettcinfo           __rex_gettcinfo
-#define rex_getsysid            __rex_getsysid
-#define rex_clear_cache         __rex_clear_cache
-
-#define prom_getchar            __prom_getchar
-#define prom_getenv             __prom_getenv
-#define prom_printf             __prom_printf
-
-#define pmax_open               __pmax_open
-#define pmax_lseek              __pmax_lseek
-#define pmax_read               __pmax_read
-#define pmax_close              __pmax_close
-
-#endif /* !CONFIG_64BIT */
-
-
-extern void prom_meminit(u32);
-extern void prom_identify_arch(u32);
-extern void prom_init_cmdline(s32, s32 *, u32);
-
-extern void register_prom_console(void);
-extern void unregister_prom_console(void);
-
-#endif /* _ASM_DEC_PROM_H */
diff --git a/include/asm-mips/dec/system.h b/include/asm-mips/dec/system.h
deleted file mode 100644
index b2afaccd6831..000000000000
--- a/include/asm-mips/dec/system.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *      include/asm-mips/dec/system.h
- *
- *      Generic DECstation/DECsystem bits.
- *
- *      Copyright (C) 2005, 2006  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_DEC_SYSTEM_H
-#define __ASM_DEC_SYSTEM_H
-
-extern unsigned long dec_kn_slot_base, dec_kn_slot_size;
-extern int dec_tc_bus;
-
-#endif /* __ASM_DEC_SYSTEM_H */
diff --git a/include/asm-mips/delay.h b/include/asm-mips/delay.h
deleted file mode 100644
index b0bccd2c4ed5..000000000000
--- a/include/asm-mips/delay.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 by Waldorf Electronics
- * Copyright (C) 1995 - 2000, 01, 03 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2007  Maciej W. Rozycki
- */
-#ifndef _ASM_DELAY_H
-#define _ASM_DELAY_H
-
-#include <linux/param.h>
-#include <linux/smp.h>
-
-#include <asm/compiler.h>
-#include <asm/war.h>
-
-static inline void __delay(unsigned long loops)
-{
-        if (sizeof(long) == 4)
-                __asm__ __volatile__ (
-                "       .set    noreorder                               \n"
-                "       .align  3                                       \n"
-                "1:     bnez    %0, 1b                                  \n"
-                "       subu    %0, 1                                   \n"
-                "       .set    reorder                                 \n"
-                : "=r" (loops)
-                : "0" (loops));
-        else if (sizeof(long) == 8 && !DADDI_WAR)
-                __asm__ __volatile__ (
-                "       .set    noreorder                               \n"
-                "       .align  3                                       \n"
-                "1:     bnez    %0, 1b                                  \n"
-                "       dsubu   %0, 1                                   \n"
-                "       .set    reorder                                 \n"
-                : "=r" (loops)
-                : "0" (loops));
-        else if (sizeof(long) == 8 && DADDI_WAR)
-                __asm__ __volatile__ (
-                "       .set    noreorder                               \n"
-                "       .align  3                                       \n"
-                "1:     bnez    %0, 1b                                  \n"
-                "       dsubu   %0, %2                                  \n"
-                "       .set    reorder                                 \n"
-                : "=r" (loops)
-                : "0" (loops), "r" (1));
-}
-
-
-/*
- * Division by multiplication: you don't have to worry about
- * loss of precision.
- *
- * Use only for very small delays ( < 1 msec).  Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays.  This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-
-static inline void __udelay(unsigned long usecs, unsigned long lpj)
-{
-        unsigned long hi, lo;
-
-        /*
-         * The rates of 128 is rounded wrongly by the catchall case
-         * for 64-bit.  Excessive precission?  Probably ...
-         */
-#if defined(CONFIG_64BIT) && (HZ == 128)
-        usecs *= 0x0008637bd05af6c7UL;          /* 2**64 / (1000000 / HZ) */
-#elif defined(CONFIG_64BIT)
-        usecs *= (0x8000000000000000UL / (500000 / HZ));
-#else /* 32-bit junk follows here */
-        usecs *= (unsigned long) (((0x8000000000000000ULL / (500000 / HZ)) +
-                                   0x80000000ULL) >> 32);
-#endif
-
-        if (sizeof(long) == 4)
-                __asm__("multu\t%2, %3"
-                : "=h" (usecs), "=l" (lo)
-                : "r" (usecs), "r" (lpj)
-                : GCC_REG_ACCUM);
-        else if (sizeof(long) == 8 && !R4000_WAR)
-                __asm__("dmultu\t%2, %3"
-                : "=h" (usecs), "=l" (lo)
-                : "r" (usecs), "r" (lpj)
-                : GCC_REG_ACCUM);
-        else if (sizeof(long) == 8 && R4000_WAR)
-                __asm__("dmultu\t%3, %4\n\tmfhi\t%0"
-                : "=r" (usecs), "=h" (hi), "=l" (lo)
-                : "r" (usecs), "r" (lpj)
-                : GCC_REG_ACCUM);
-
-        __delay(usecs);
-}
-
-#define __udelay_val cpu_data[raw_smp_processor_id()].udelay_val
-
-#define udelay(usecs) __udelay((usecs), __udelay_val)
-
-/* make sure "usecs *= ..." in udelay do not overflow. */
-#if HZ >= 1000
-#define MAX_UDELAY_MS   1
-#elif HZ <= 200
-#define MAX_UDELAY_MS   5
-#else
-#define MAX_UDELAY_MS   (1000 / HZ)
-#endif
-
-#endif /* _ASM_DELAY_H */
diff --git a/include/asm-mips/device.h b/include/asm-mips/device.h
deleted file mode 100644
index d8f9872b0e2d..000000000000
--- a/include/asm-mips/device.h
+++ /dev/null
@@ -1,7 +0,0 @@
-/*
- * Arch specific extensions to struct device
- *
- * This file is released under the GPLv2
- */
-#include <asm-generic/device.h>
-
diff --git a/include/asm-mips/div64.h b/include/asm-mips/div64.h
deleted file mode 100644
index d1d699105c11..000000000000
--- a/include/asm-mips/div64.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (C) 2000, 2004  Maciej W. Rozycki
- * Copyright (C) 2003, 07 Ralf Baechle (ralf@linux-mips.org)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _ASM_DIV64_H
-#define _ASM_DIV64_H
-
-#include <linux/types.h>
-
-#if (_MIPS_SZLONG == 32)
-
-#include <asm/compiler.h>
-
-/*
- * No traps on overflows for any of these...
- */
-
-#define do_div64_32(res, high, low, base) ({ \
-        unsigned long __quot32, __mod32; \
-        unsigned long __cf, __tmp, __tmp2, __i; \
-        \
-        __asm__(".set   push\n\t" \
-                ".set   noat\n\t" \
-                ".set   noreorder\n\t" \
-                "move   %2, $0\n\t" \
-                "move   %3, $0\n\t" \
-                "b      1f\n\t" \
-                " li    %4, 0x21\n" \
-                "0:\n\t" \
-                "sll    $1, %0, 0x1\n\t" \
-                "srl    %3, %0, 0x1f\n\t" \
-                "or     %0, $1, %5\n\t" \
-                "sll    %1, %1, 0x1\n\t" \
-                "sll    %2, %2, 0x1\n" \
-                "1:\n\t" \
-                "bnez   %3, 2f\n\t" \
-                " sltu  %5, %0, %z6\n\t" \
-                "bnez   %5, 3f\n" \
-                "2:\n\t" \
-                " addiu %4, %4, -1\n\t" \
-                "subu   %0, %0, %z6\n\t" \
-                "addiu  %2, %2, 1\n" \
-                "3:\n\t" \
-                "bnez   %4, 0b\n\t" \
-                " srl   %5, %1, 0x1f\n\t" \
-                ".set   pop" \
-                : "=&r" (__mod32), "=&r" (__tmp), \
-                  "=&r" (__quot32), "=&r" (__cf), \
-                  "=&r" (__i), "=&r" (__tmp2) \
-                : "Jr" (base), "0" (high), "1" (low)); \
-        \
-        (res) = __quot32; \
-        __mod32; })
-
-#define do_div(n, base) ({ \
-        unsigned long long __quot; \
-        unsigned long __mod; \
-        unsigned long long __div; \
-        unsigned long __upper, __low, __high, __base; \
-        \
-        __div = (n); \
-        __base = (base); \
-        \
-        __high = __div >> 32; \
-        __low = __div; \
-        __upper = __high; \
-        \
-        if (__high) \
-                __asm__("divu   $0, %z2, %z3" \
-                        : "=h" (__upper), "=l" (__high) \
-                        : "Jr" (__high), "Jr" (__base) \
-                        : GCC_REG_ACCUM); \
-        \
-        __mod = do_div64_32(__low, __upper, __low, __base); \
-        \
-        __quot = __high; \
-        __quot = __quot << 32 | __low; \
-        (n) = __quot; \
-        __mod; })
-
-#endif /* (_MIPS_SZLONG == 32) */
-
-#if (_MIPS_SZLONG == 64)
-
-/*
- * Hey, we're already 64-bit, no
- * need to play games..
- */
-#define do_div(n, base) ({ \
-        unsigned long __quot; \
-        unsigned int __mod; \
-        unsigned long __div; \
-        unsigned int __base; \
-        \
-        __div = (n); \
-        __base = (base); \
-        \
-        __mod = __div % __base; \
-        __quot = __div / __base; \
-        \
-        (n) = __quot; \
-        __mod; })
-
-#endif /* (_MIPS_SZLONG == 64) */
-
-#endif /* _ASM_DIV64_H */
diff --git a/include/asm-mips/dma-mapping.h b/include/asm-mips/dma-mapping.h
deleted file mode 100644
index c64afb40cd06..000000000000
--- a/include/asm-mips/dma-mapping.h
+++ /dev/null
@@ -1,81 +0,0 @@
-#ifndef _ASM_DMA_MAPPING_H
-#define _ASM_DMA_MAPPING_H
-
-#include <asm/scatterlist.h>
-#include <asm/cache.h>
-
-void *dma_alloc_noncoherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_noncoherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
-
-extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
-        enum dma_data_direction direction);
-extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr,
-        size_t size, enum dma_data_direction direction);
-extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
-        enum dma_data_direction direction);
-extern dma_addr_t dma_map_page(struct device *dev, struct page *page,
-        unsigned long offset, size_t size, enum dma_data_direction direction);
-extern void dma_unmap_page(struct device *dev, dma_addr_t dma_address,
-        size_t size, enum dma_data_direction direction);
-extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
-        int nhwentries, enum dma_data_direction direction);
-extern void dma_sync_single_for_cpu(struct device *dev, dma_addr_t dma_handle,
-        size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_for_device(struct device *dev,
-        dma_addr_t dma_handle, size_t size, enum dma_data_direction direction);
-extern void dma_sync_single_range_for_cpu(struct device *dev,
-        dma_addr_t dma_handle, unsigned long offset, size_t size,
-        enum dma_data_direction direction);
-extern void dma_sync_single_range_for_device(struct device *dev,
-        dma_addr_t dma_handle, unsigned long offset, size_t size,
-        enum dma_data_direction direction);
-extern void dma_sync_sg_for_cpu(struct device *dev, struct scatterlist *sg,
-        int nelems, enum dma_data_direction direction);
-extern void dma_sync_sg_for_device(struct device *dev, struct scatterlist *sg,
-        int nelems, enum dma_data_direction direction);
-extern int dma_mapping_error(struct device *dev, dma_addr_t dma_addr);
-extern int dma_supported(struct device *dev, u64 mask);
-
-static inline int
-dma_set_mask(struct device *dev, u64 mask)
-{
-        if(!dev->dma_mask || !dma_supported(dev, mask))
-                return -EIO;
-
-        *dev->dma_mask = mask;
-
-        return 0;
-}
-
-static inline int
-dma_get_cache_alignment(void)
-{
-        /* XXX Largest on any MIPS */
-        return 128;
-}
-
-extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
-
-extern void dma_cache_sync(struct device *dev, void *vaddr, size_t size,
-               enum dma_data_direction direction);
-
-#if 0
-#define ARCH_HAS_DMA_DECLARE_COHERENT_MEMORY
-
-extern int dma_declare_coherent_memory(struct device *dev, dma_addr_t bus_addr,
-        dma_addr_t device_addr, size_t size, int flags);
-extern void dma_release_declared_memory(struct device *dev);
-extern void * dma_mark_declared_memory_occupied(struct device *dev,
-        dma_addr_t device_addr, size_t size);
-#endif
-
-#endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-mips/dma.h b/include/asm-mips/dma.h
deleted file mode 100644
index 1353c81065d1..000000000000
--- a/include/asm-mips/dma.h
+++ /dev/null
@@ -1,315 +0,0 @@
-/*
- * linux/include/asm/dma.h: Defines for using and allocating dma channels.
- * Written by Hennus Bergman, 1992.
- * High DMA channel support & info by Hannu Savolainen
- * and John Boyd, Nov. 1992.
- *
- * NOTE: all this is true *only* for ISA/EISA expansions on Mips boards
- * and can only be used for expansion cards. Onboard DMA controllers, such
- * as the R4030 on Jazz boards behave totally different!
- */
-
-#ifndef _ASM_DMA_H
-#define _ASM_DMA_H
-
-#include <asm/io.h>                     /* need byte IO */
-#include <linux/spinlock.h>             /* And spinlocks */
-#include <linux/delay.h>
-#include <asm/system.h>
-
-
-#ifdef HAVE_REALLY_SLOW_DMA_CONTROLLER
-#define dma_outb        outb_p
-#else
-#define dma_outb        outb
-#endif
-
-#define dma_inb         inb
-
-/*
- * NOTES about DMA transfers:
- *
- *  controller 1: channels 0-3, byte operations, ports 00-1F
- *  controller 2: channels 4-7, word operations, ports C0-DF
- *
- *  - ALL registers are 8 bits only, regardless of transfer size
- *  - channel 4 is not used - cascades 1 into 2.
- *  - channels 0-3 are byte - addresses/counts are for physical bytes
- *  - channels 5-7 are word - addresses/counts are for physical words
- *  - transfers must not cross physical 64K (0-3) or 128K (5-7) boundaries
- *  - transfer count loaded to registers is 1 less than actual count
- *  - controller 2 offsets are all even (2x offsets for controller 1)
- *  - page registers for 5-7 don't use data bit 0, represent 128K pages
- *  - page registers for 0-3 use bit 0, represent 64K pages
- *
- * DMA transfers are limited to the lower 16MB of _physical_ memory.
- * Note that addresses loaded into registers must be _physical_ addresses,
- * not logical addresses (which may differ if paging is active).
- *
- *  Address mapping for channels 0-3:
- *
- *   A23 ... A16 A15 ... A8  A7 ... A0    (Physical addresses)
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *    |  ...  |   |  ... |   |  ... |
- *   P7  ...  P0  A7 ... A0  A7 ... A0
- * |    Page    | Addr MSB | Addr LSB |   (DMA registers)
- *
- *  Address mapping for channels 5-7:
- *
- *   A23 ... A17 A16 A15 ... A9 A8 A7 ... A1 A0    (Physical addresses)
- *    |  ...  |   \   \   ... \  \  \  ... \  \
- *    |  ...  |    \   \   ... \  \  \  ... \  (not used)
- *    |  ...  |     \   \   ... \  \  \  ... \
- *   P7  ...  P1 (0) A7 A6  ... A0 A7 A6 ... A0
- * |      Page      |  Addr MSB   |  Addr LSB  |   (DMA registers)
- *
- * Again, channels 5-7 transfer _physical_ words (16 bits), so addresses
- * and counts _must_ be word-aligned (the lowest address bit is _ignored_ at
- * the hardware level, so odd-byte transfers aren't possible).
- *
- * Transfer count (_not # bytes_) is limited to 64K, represented as actual
- * count - 1 : 64K => 0xFFFF, 1 => 0x0000.  Thus, count is always 1 or more,
- * and up to 128K bytes may be transferred on channels 5-7 in one operation.
- *
- */
-
-#ifndef CONFIG_GENERIC_ISA_DMA_SUPPORT_BROKEN
-#define MAX_DMA_CHANNELS        8
-#endif
-
-/*
- * The maximum address in KSEG0 that we can perform a DMA transfer to on this
- * platform.  This describes only the PC style part of the DMA logic like on
- * Deskstations or Acer PICA but not the much more versatile DMA logic used
- * for the local devices on Acer PICA or Magnums.
- */
-#if defined(CONFIG_SGI_IP22) || defined(CONFIG_SGI_IP28)
-/* don't care; ISA bus master won't work, ISA slave DMA supports 32bit addr */
-#define MAX_DMA_ADDRESS         PAGE_OFFSET
-#else
-#define MAX_DMA_ADDRESS         (PAGE_OFFSET + 0x01000000)
-#endif
-#define MAX_DMA_PFN             PFN_DOWN(virt_to_phys((void *)MAX_DMA_ADDRESS))
-#define MAX_DMA32_PFN           (1UL << (32 - PAGE_SHIFT))
-
-/* 8237 DMA controllers */
-#define IO_DMA1_BASE    0x00    /* 8 bit slave DMA, channels 0..3 */
-#define IO_DMA2_BASE    0xC0    /* 16 bit master DMA, ch 4(=slave input)..7 */
-
-/* DMA controller registers */
-#define DMA1_CMD_REG            0x08    /* command register (w) */
-#define DMA1_STAT_REG           0x08    /* status register (r) */
-#define DMA1_REQ_REG            0x09    /* request register (w) */
-#define DMA1_MASK_REG           0x0A    /* single-channel mask (w) */
-#define DMA1_MODE_REG           0x0B    /* mode register (w) */
-#define DMA1_CLEAR_FF_REG       0x0C    /* clear pointer flip-flop (w) */
-#define DMA1_TEMP_REG           0x0D    /* Temporary Register (r) */
-#define DMA1_RESET_REG          0x0D    /* Master Clear (w) */
-#define DMA1_CLR_MASK_REG       0x0E    /* Clear Mask */
-#define DMA1_MASK_ALL_REG       0x0F    /* all-channels mask (w) */
-
-#define DMA2_CMD_REG            0xD0    /* command register (w) */
-#define DMA2_STAT_REG           0xD0    /* status register (r) */
-#define DMA2_REQ_REG            0xD2    /* request register (w) */
-#define DMA2_MASK_REG           0xD4    /* single-channel mask (w) */
-#define DMA2_MODE_REG           0xD6    /* mode register (w) */
-#define DMA2_CLEAR_FF_REG       0xD8    /* clear pointer flip-flop (w) */
-#define DMA2_TEMP_REG           0xDA    /* Temporary Register (r) */
-#define DMA2_RESET_REG          0xDA    /* Master Clear (w) */
-#define DMA2_CLR_MASK_REG       0xDC    /* Clear Mask */
-#define DMA2_MASK_ALL_REG       0xDE    /* all-channels mask (w) */
-
-#define DMA_ADDR_0              0x00    /* DMA address registers */
-#define DMA_ADDR_1              0x02
-#define DMA_ADDR_2              0x04
-#define DMA_ADDR_3              0x06
-#define DMA_ADDR_4              0xC0
-#define DMA_ADDR_5              0xC4
-#define DMA_ADDR_6              0xC8
-#define DMA_ADDR_7              0xCC
-
-#define DMA_CNT_0               0x01    /* DMA count registers */
-#define DMA_CNT_1               0x03
-#define DMA_CNT_2               0x05
-#define DMA_CNT_3               0x07
-#define DMA_CNT_4               0xC2
-#define DMA_CNT_5               0xC6
-#define DMA_CNT_6               0xCA
-#define DMA_CNT_7               0xCE
-
-#define DMA_PAGE_0              0x87    /* DMA page registers */
-#define DMA_PAGE_1              0x83
-#define DMA_PAGE_2              0x81
-#define DMA_PAGE_3              0x82
-#define DMA_PAGE_5              0x8B
-#define DMA_PAGE_6              0x89
-#define DMA_PAGE_7              0x8A
-
-#define DMA_MODE_READ   0x44    /* I/O to memory, no autoinit, increment, single mode */
-#define DMA_MODE_WRITE  0x48    /* memory to I/O, no autoinit, increment, single mode */
-#define DMA_MODE_CASCADE 0xC0   /* pass thru DREQ->HRQ, DACK<-HLDA only */
-
-#define DMA_AUTOINIT    0x10
-
-extern spinlock_t  dma_spin_lock;
-
-static __inline__ unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-        spin_lock_irqsave(&dma_spin_lock, flags);
-        return flags;
-}
-
-static __inline__ void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&dma_spin_lock, flags);
-}
-
-/* enable/disable a specific DMA channel */
-static __inline__ void enable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr,  DMA1_MASK_REG);
-        else
-                dma_outb(dmanr & 3,  DMA2_MASK_REG);
-}
-
-static __inline__ void disable_dma(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(dmanr | 4,  DMA1_MASK_REG);
-        else
-                dma_outb((dmanr & 3) | 4,  DMA2_MASK_REG);
-}
-
-/* Clear the 'DMA Pointer Flip Flop'.
- * Write 0 for LSB/MSB, 1 for MSB/LSB access.
- * Use this once to initialize the FF to a known state.
- * After that, keep track of it. :-)
- * --- In order to do that, the DMA routines below should ---
- * --- only be used while holding the DMA lock ! ---
- */
-static __inline__ void clear_dma_ff(unsigned int dmanr)
-{
-        if (dmanr<=3)
-                dma_outb(0,  DMA1_CLEAR_FF_REG);
-        else
-                dma_outb(0,  DMA2_CLEAR_FF_REG);
-}
-
-/* set mode (above) for a specific DMA channel */
-static __inline__ void set_dma_mode(unsigned int dmanr, char mode)
-{
-        if (dmanr<=3)
-                dma_outb(mode | dmanr,  DMA1_MODE_REG);
-        else
-                dma_outb(mode | (dmanr&3),  DMA2_MODE_REG);
-}
-
-/* Set only the page register bits of the transfer address.
- * This is used for successive transfers when we know the contents of
- * the lower 16 bits of the DMA current address register, but a 64k boundary
- * may have been crossed.
- */
-static __inline__ void set_dma_page(unsigned int dmanr, char pagenr)
-{
-        switch(dmanr) {
-                case 0:
-                        dma_outb(pagenr, DMA_PAGE_0);
-                        break;
-                case 1:
-                        dma_outb(pagenr, DMA_PAGE_1);
-                        break;
-                case 2:
-                        dma_outb(pagenr, DMA_PAGE_2);
-                        break;
-                case 3:
-                        dma_outb(pagenr, DMA_PAGE_3);
-                        break;
-                case 5:
-                        dma_outb(pagenr & 0xfe, DMA_PAGE_5);
-                        break;
-                case 6:
-                        dma_outb(pagenr & 0xfe, DMA_PAGE_6);
-                        break;
-                case 7:
-                        dma_outb(pagenr & 0xfe, DMA_PAGE_7);
-                        break;
-        }
-}
-
-
-/* Set transfer address & page bits for specific DMA channel.
- * Assumes dma flipflop is clear.
- */
-static __inline__ void set_dma_addr(unsigned int dmanr, unsigned int a)
-{
-        set_dma_page(dmanr, a>>16);
-        if (dmanr <= 3)  {
-            dma_outb( a & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-            dma_outb( (a>>8) & 0xff, ((dmanr&3)<<1) + IO_DMA1_BASE );
-        }  else  {
-            dma_outb( (a>>1) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-            dma_outb( (a>>9) & 0xff, ((dmanr&3)<<2) + IO_DMA2_BASE );
-        }
-}
-
-
-/* Set transfer size (max 64k for DMA0..3, 128k for DMA5..7) for
- * a specific DMA channel.
- * You must ensure the parameters are valid.
- * NOTE: from a manual: "the number of transfers is one more
- * than the initial word count"! This is taken into account.
- * Assumes dma flip-flop is clear.
- * NOTE 2: "count" represents _bytes_ and must be even for channels 5-7.
- */
-static __inline__ void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        count--;
-        if (dmanr <= 3)  {
-            dma_outb( count & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-            dma_outb( (count>>8) & 0xff, ((dmanr&3)<<1) + 1 + IO_DMA1_BASE );
-        } else {
-            dma_outb( (count>>1) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-            dma_outb( (count>>9) & 0xff, ((dmanr&3)<<2) + 2 + IO_DMA2_BASE );
-        }
-}
-
-
-/* Get DMA residue count. After a DMA transfer, this
- * should return zero. Reading this while a DMA transfer is
- * still in progress will return unpredictable results.
- * If called before the channel has been used, it may return 1.
- * Otherwise, it returns the number of _bytes_ left to transfer.
- *
- * Assumes DMA flip-flop is clear.
- */
-static __inline__ int get_dma_residue(unsigned int dmanr)
-{
-        unsigned int io_port = (dmanr<=3)? ((dmanr&3)<<1) + 1 + IO_DMA1_BASE
-                                         : ((dmanr&3)<<2) + 2 + IO_DMA2_BASE;
-
-        /* using short to get 16-bit wrap around */
-        unsigned short count;
-
-        count = 1 + dma_inb(io_port);
-        count += dma_inb(io_port) << 8;
-
-        return (dmanr<=3)? count : (count<<1);
-}
-
-
-/* These are in kernel/dma.c: */
-extern int request_dma(unsigned int dmanr, const char * device_id);     /* reserve a DMA channel */
-extern void free_dma(unsigned int dmanr);       /* release it again */
-
-/* From PCI */
-
-#ifdef CONFIG_PCI
-extern int isa_dma_bridge_buggy;
-#else
-#define isa_dma_bridge_buggy    (0)
-#endif
-
-#endif /* _ASM_DMA_H */
diff --git a/include/asm-mips/ds1286.h b/include/asm-mips/ds1286.h
deleted file mode 100644
index 6983b6ff0af3..000000000000
--- a/include/asm-mips/ds1286.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Machine dependent access functions for RTC registers.
- *
- * Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_DS1286_H
-#define _ASM_DS1286_H
-
-#include <ds1286.h>
-
-#endif /* _ASM_DS1286_H */
diff --git a/include/asm-mips/ds1287.h b/include/asm-mips/ds1287.h
deleted file mode 100644
index ba1702e86931..000000000000
--- a/include/asm-mips/ds1287.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  DS1287 timer functions.
- *
- *  Copyright (C) 2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA
- */
-#ifndef __ASM_DS1287_H
-#define __ASM_DS1287_H
-
-extern int ds1287_timer_state(void);
-extern void ds1287_set_base_clock(unsigned int clock);
-extern int ds1287_clockevent_init(int irq);
-
-#endif
diff --git a/include/asm-mips/dsp.h b/include/asm-mips/dsp.h
deleted file mode 100644
index e9bfc0813c72..000000000000
--- a/include/asm-mips/dsp.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Copyright (C) 2005 Mips Technologies
- * Author: Chris Dearman, chris@mips.com derived from fpu.h
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_DSP_H
-#define _ASM_DSP_H
-
-#include <asm/cpu.h>
-#include <asm/cpu-features.h>
-#include <asm/hazards.h>
-#include <asm/mipsregs.h>
-
-#define DSP_DEFAULT     0x00000000
-#define DSP_MASK        0x3ff
-
-#define __enable_dsp_hazard()                                           \
-do {                                                                    \
-        asm("_ehb");                                                    \
-} while (0)
-
-static inline void __init_dsp(void)
-{
-        mthi1(0);
-        mtlo1(0);
-        mthi2(0);
-        mtlo2(0);
-        mthi3(0);
-        mtlo3(0);
-        wrdsp(DSP_DEFAULT, DSP_MASK);
-}
-
-static inline void init_dsp(void)
-{
-        if (cpu_has_dsp)
-                __init_dsp();
-}
-
-#define __save_dsp(tsk)                                                 \
-do {                                                                    \
-        tsk->thread.dsp.dspr[0] = mfhi1();                              \
-        tsk->thread.dsp.dspr[1] = mflo1();                              \
-        tsk->thread.dsp.dspr[2] = mfhi2();                              \
-        tsk->thread.dsp.dspr[3] = mflo2();                              \
-        tsk->thread.dsp.dspr[4] = mfhi3();                              \
-        tsk->thread.dsp.dspr[5] = mflo3();                              \
-        tsk->thread.dsp.dspcontrol = rddsp(DSP_MASK);                   \
-} while (0)
-
-#define save_dsp(tsk)                                                   \
-do {                                                                    \
-        if (cpu_has_dsp)                                                \
-                __save_dsp(tsk);                                        \
-} while (0)
-
-#define __restore_dsp(tsk)                                              \
-do {                                                                    \
-        mthi1(tsk->thread.dsp.dspr[0]);                                 \
-        mtlo1(tsk->thread.dsp.dspr[1]);                                 \
-        mthi2(tsk->thread.dsp.dspr[2]);                                 \
-        mtlo2(tsk->thread.dsp.dspr[3]);                                 \
-        mthi3(tsk->thread.dsp.dspr[4]);                                 \
-        mtlo3(tsk->thread.dsp.dspr[5]);                                 \
-        wrdsp(tsk->thread.dsp.dspcontrol, DSP_MASK);                    \
-} while (0)
-
-#define restore_dsp(tsk)                                                \
-do {                                                                    \
-        if (cpu_has_dsp)                                                \
-                __restore_dsp(tsk);                                     \
-} while (0)
-
-#define __get_dsp_regs(tsk)                                             \
-({                                                                      \
-        if (tsk == current)                                             \
-                __save_dsp(current);                                    \
-                                                                        \
-        tsk->thread.dsp.dspr;                                           \
-})
-
-#endif /* _ASM_DSP_H */
diff --git a/include/asm-mips/edac.h b/include/asm-mips/edac.h
deleted file mode 100644
index 4da0c1fe30d9..000000000000
--- a/include/asm-mips/edac.h
+++ /dev/null
@@ -1,34 +0,0 @@
-#ifndef ASM_EDAC_H
-#define ASM_EDAC_H
-
-/* ECC atomic, DMA, SMP and interrupt safe scrub function */
-
-static inline void atomic_scrub(void *va, u32 size)
-{
-        unsigned long *virt_addr = va;
-        unsigned long temp;
-        u32 i;
-
-        for (i = 0; i < size / sizeof(unsigned long); i++) {
-                /*
-                 * Very carefully read and write to memory atomically
-                 * so we are interrupt, DMA and SMP safe.
-                 *
-                 * Intel: asm("lock; addl $0, %0"::"m"(*virt_addr));
-                 */
-
-                __asm__ __volatile__ (
-                "       .set    mips2                                   \n"
-                "1:     ll      %0, %1          # atomic_scrub          \n"
-                "       addu    %0, $0                                  \n"
-                "       sc      %0, %1                                  \n"
-                "       beqz    %0, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (temp), "=m" (*virt_addr)
-                : "m" (*virt_addr));
-
-                virt_addr++;
-        }
-}
-
-#endif
diff --git a/include/asm-mips/elf.h b/include/asm-mips/elf.h
deleted file mode 100644
index f69f7acba637..000000000000
--- a/include/asm-mips/elf.h
+++ /dev/null
@@ -1,371 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Much of this is taken from binutils and GNU libc ...
- */
-#ifndef _ASM_ELF_H
-#define _ASM_ELF_H
-
-
-/* ELF header e_flags defines. */
-/* MIPS architecture level. */
-#define EF_MIPS_ARCH_1          0x00000000      /* -mips1 code.  */
-#define EF_MIPS_ARCH_2          0x10000000      /* -mips2 code.  */
-#define EF_MIPS_ARCH_3          0x20000000      /* -mips3 code.  */
-#define EF_MIPS_ARCH_4          0x30000000      /* -mips4 code.  */
-#define EF_MIPS_ARCH_5          0x40000000      /* -mips5 code.  */
-#define EF_MIPS_ARCH_32         0x50000000      /* MIPS32 code.  */
-#define EF_MIPS_ARCH_64         0x60000000      /* MIPS64 code.  */
-#define EF_MIPS_ARCH_32R2       0x70000000      /* MIPS32 R2 code.  */
-#define EF_MIPS_ARCH_64R2       0x80000000      /* MIPS64 R2 code.  */
-
-/* The ABI of a file. */
-#define EF_MIPS_ABI_O32         0x00001000      /* O32 ABI.  */
-#define EF_MIPS_ABI_O64         0x00002000      /* O32 extended for 64 bit.  */
-
-#define PT_MIPS_REGINFO         0x70000000
-#define PT_MIPS_RTPROC          0x70000001
-#define PT_MIPS_OPTIONS         0x70000002
-
-/* Flags in the e_flags field of the header */
-#define EF_MIPS_NOREORDER       0x00000001
-#define EF_MIPS_PIC             0x00000002
-#define EF_MIPS_CPIC            0x00000004
-#define EF_MIPS_ABI2            0x00000020
-#define EF_MIPS_OPTIONS_FIRST   0x00000080
-#define EF_MIPS_32BITMODE       0x00000100
-#define EF_MIPS_ABI             0x0000f000
-#define EF_MIPS_ARCH            0xf0000000
-
-#define DT_MIPS_RLD_VERSION     0x70000001
-#define DT_MIPS_TIME_STAMP      0x70000002
-#define DT_MIPS_ICHECKSUM       0x70000003
-#define DT_MIPS_IVERSION        0x70000004
-#define DT_MIPS_FLAGS           0x70000005
-        #define RHF_NONE        0x00000000
-        #define RHF_HARDWAY     0x00000001
-        #define RHF_NOTPOT      0x00000002
-        #define RHF_SGI_ONLY    0x00000010
-#define DT_MIPS_BASE_ADDRESS    0x70000006
-#define DT_MIPS_CONFLICT        0x70000008
-#define DT_MIPS_LIBLIST         0x70000009
-#define DT_MIPS_LOCAL_GOTNO     0x7000000a
-#define DT_MIPS_CONFLICTNO      0x7000000b
-#define DT_MIPS_LIBLISTNO       0x70000010
-#define DT_MIPS_SYMTABNO        0x70000011
-#define DT_MIPS_UNREFEXTNO      0x70000012
-#define DT_MIPS_GOTSYM          0x70000013
-#define DT_MIPS_HIPAGENO        0x70000014
-#define DT_MIPS_RLD_MAP         0x70000016
-
-#define R_MIPS_NONE             0
-#define R_MIPS_16               1
-#define R_MIPS_32               2
-#define R_MIPS_REL32            3
-#define R_MIPS_26               4
-#define R_MIPS_HI16             5
-#define R_MIPS_LO16             6
-#define R_MIPS_GPREL16          7
-#define R_MIPS_LITERAL          8
-#define R_MIPS_GOT16            9
-#define R_MIPS_PC16             10
-#define R_MIPS_CALL16           11
-#define R_MIPS_GPREL32          12
-/* The remaining relocs are defined on Irix, although they are not
-   in the MIPS ELF ABI.  */
-#define R_MIPS_UNUSED1          13
-#define R_MIPS_UNUSED2          14
-#define R_MIPS_UNUSED3          15
-#define R_MIPS_SHIFT5           16
-#define R_MIPS_SHIFT6           17
-#define R_MIPS_64               18
-#define R_MIPS_GOT_DISP         19
-#define R_MIPS_GOT_PAGE         20
-#define R_MIPS_GOT_OFST         21
-/*
- * The following two relocation types are specified in the MIPS ABI
- * conformance guide version 1.2 but not yet in the psABI.
- */
-#define R_MIPS_GOTHI16          22
-#define R_MIPS_GOTLO16          23
-#define R_MIPS_SUB              24
-#define R_MIPS_INSERT_A         25
-#define R_MIPS_INSERT_B         26
-#define R_MIPS_DELETE           27
-#define R_MIPS_HIGHER           28
-#define R_MIPS_HIGHEST          29
-/*
- * The following two relocation types are specified in the MIPS ABI
- * conformance guide version 1.2 but not yet in the psABI.
- */
-#define R_MIPS_CALLHI16         30
-#define R_MIPS_CALLLO16         31
-/*
- * This range is reserved for vendor specific relocations.
- */
-#define R_MIPS_LOVENDOR         100
-#define R_MIPS_HIVENDOR         127
-
-#define SHN_MIPS_ACCOMON        0xff00          /* Allocated common symbols */
-#define SHN_MIPS_TEXT           0xff01          /* Allocated test symbols.  */
-#define SHN_MIPS_DATA           0xff02          /* Allocated data symbols.  */
-#define SHN_MIPS_SCOMMON        0xff03          /* Small common symbols */
-#define SHN_MIPS_SUNDEFINED     0xff04          /* Small undefined symbols */
-
-#define SHT_MIPS_LIST           0x70000000
-#define SHT_MIPS_CONFLICT       0x70000002
-#define SHT_MIPS_GPTAB          0x70000003
-#define SHT_MIPS_UCODE          0x70000004
-#define SHT_MIPS_DEBUG          0x70000005
-#define SHT_MIPS_REGINFO        0x70000006
-#define SHT_MIPS_PACKAGE        0x70000007
-#define SHT_MIPS_PACKSYM        0x70000008
-#define SHT_MIPS_RELD           0x70000009
-#define SHT_MIPS_IFACE          0x7000000b
-#define SHT_MIPS_CONTENT        0x7000000c
-#define SHT_MIPS_OPTIONS        0x7000000d
-#define SHT_MIPS_SHDR           0x70000010
-#define SHT_MIPS_FDESC          0x70000011
-#define SHT_MIPS_EXTSYM         0x70000012
-#define SHT_MIPS_DENSE          0x70000013
-#define SHT_MIPS_PDESC          0x70000014
-#define SHT_MIPS_LOCSYM         0x70000015
-#define SHT_MIPS_AUXSYM         0x70000016
-#define SHT_MIPS_OPTSYM         0x70000017
-#define SHT_MIPS_LOCSTR         0x70000018
-#define SHT_MIPS_LINE           0x70000019
-#define SHT_MIPS_RFDESC         0x7000001a
-#define SHT_MIPS_DELTASYM       0x7000001b
-#define SHT_MIPS_DELTAINST      0x7000001c
-#define SHT_MIPS_DELTACLASS     0x7000001d
-#define SHT_MIPS_DWARF          0x7000001e
-#define SHT_MIPS_DELTADECL      0x7000001f
-#define SHT_MIPS_SYMBOL_LIB     0x70000020
-#define SHT_MIPS_EVENTS         0x70000021
-#define SHT_MIPS_TRANSLATE      0x70000022
-#define SHT_MIPS_PIXIE          0x70000023
-#define SHT_MIPS_XLATE          0x70000024
-#define SHT_MIPS_XLATE_DEBUG    0x70000025
-#define SHT_MIPS_WHIRL          0x70000026
-#define SHT_MIPS_EH_REGION      0x70000027
-#define SHT_MIPS_XLATE_OLD      0x70000028
-#define SHT_MIPS_PDR_EXCEPTION  0x70000029
-
-#define SHF_MIPS_GPREL          0x10000000
-#define SHF_MIPS_MERGE          0x20000000
-#define SHF_MIPS_ADDR           0x40000000
-#define SHF_MIPS_STRING         0x80000000
-#define SHF_MIPS_NOSTRIP        0x08000000
-#define SHF_MIPS_LOCAL          0x04000000
-#define SHF_MIPS_NAMES          0x02000000
-#define SHF_MIPS_NODUPES        0x01000000
-
-#ifndef ELF_ARCH
-/* ELF register definitions */
-#define ELF_NGREG       45
-#define ELF_NFPREG      33
-
-typedef unsigned long elf_greg_t;
-typedef elf_greg_t elf_gregset_t[ELF_NGREG];
-
-typedef double elf_fpreg_t;
-typedef elf_fpreg_t elf_fpregset_t[ELF_NFPREG];
-
-#ifdef CONFIG_32BIT
-
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(hdr)                                             \
-({                                                                      \
-        int __res = 1;                                                  \
-        struct elfhdr *__h = (hdr);                                     \
-                                                                        \
-        if (__h->e_machine != EM_MIPS)                                  \
-                __res = 0;                                              \
-        if (__h->e_ident[EI_CLASS] != ELFCLASS32)                       \
-                __res = 0;                                              \
-        if ((__h->e_flags & EF_MIPS_ABI2) != 0)                         \
-                __res = 0;                                              \
-        if (((__h->e_flags & EF_MIPS_ABI) != 0) &&                      \
-            ((__h->e_flags & EF_MIPS_ABI) != EF_MIPS_ABI_O32))          \
-                __res = 0;                                              \
-                                                                        \
-        __res;                                                          \
-})
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS32
-
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-/*
- * This is used to ensure we don't load something for the wrong architecture.
- */
-#define elf_check_arch(hdr)                                             \
-({                                                                      \
-        int __res = 1;                                                  \
-        struct elfhdr *__h = (hdr);                                     \
-                                                                        \
-        if (__h->e_machine != EM_MIPS)                                  \
-                __res = 0;                                              \
-        if (__h->e_ident[EI_CLASS] != ELFCLASS64)                       \
-                __res = 0;                                              \
-                                                                        \
-        __res;                                                          \
-})
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#define ELF_CLASS       ELFCLASS64
-
-#endif /* CONFIG_64BIT */
-
-/*
- * These are used to set parameters in the core dumps.
- */
-#ifdef __MIPSEB__
-#define ELF_DATA        ELFDATA2MSB
-#elif __MIPSEL__
-#define ELF_DATA        ELFDATA2LSB
-#endif
-#define ELF_ARCH        EM_MIPS
-
-#endif /* !defined(ELF_ARCH) */
-
-struct mips_abi;
-
-extern struct mips_abi mips_abi;
-extern struct mips_abi mips_abi_32;
-extern struct mips_abi mips_abi_n32;
-
-#ifdef CONFIG_32BIT
-
-#define SET_PERSONALITY(ex, ibcs2)                                      \
-do {                                                                    \
-        if (ibcs2)                                                      \
-                set_personality(PER_SVR4);                              \
-        set_personality(PER_LINUX);                                     \
-                                                                        \
-        current->thread.abi = &mips_abi;                                \
-} while (0)
-
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-
-#ifdef CONFIG_MIPS32_N32
-#define __SET_PERSONALITY32_N32()                                       \
-        do {                                                            \
-                set_thread_flag(TIF_32BIT_ADDR);                        \
-                current->thread.abi = &mips_abi_n32;                    \
-        } while (0)
-#else
-#define __SET_PERSONALITY32_N32()                                       \
-        do { } while (0)
-#endif
-
-#ifdef CONFIG_MIPS32_O32
-#define __SET_PERSONALITY32_O32()                                       \
-        do {                                                            \
-                set_thread_flag(TIF_32BIT_REGS);                        \
-                set_thread_flag(TIF_32BIT_ADDR);                        \
-                current->thread.abi = &mips_abi_32;                     \
-        } while (0)
-#else
-#define __SET_PERSONALITY32_O32()                                       \
-        do { } while (0)
-#endif
-
-#ifdef CONFIG_MIPS32_COMPAT
-#define __SET_PERSONALITY32(ex)                                         \
-do {                                                                    \
-        if ((((ex).e_flags & EF_MIPS_ABI2) != 0) &&                     \
-             ((ex).e_flags & EF_MIPS_ABI) == 0)                         \
-                __SET_PERSONALITY32_N32();                              \
-        else                                                            \
-                __SET_PERSONALITY32_O32();                              \
-} while (0)
-#else
-#define __SET_PERSONALITY32(ex) do { } while (0)
-#endif
-
-#define SET_PERSONALITY(ex, ibcs2)                                      \
-do {                                                                    \
-        clear_thread_flag(TIF_32BIT_REGS);                              \
-        clear_thread_flag(TIF_32BIT_ADDR);                              \
-                                                                        \
-        if ((ex).e_ident[EI_CLASS] == ELFCLASS32)                       \
-                __SET_PERSONALITY32(ex);                                \
-        else                                                            \
-                current->thread.abi = &mips_abi;                        \
-                                                                        \
-        if (ibcs2)                                                      \
-                set_personality(PER_SVR4);                              \
-        else if (current->personality != PER_LINUX32)                   \
-                set_personality(PER_LINUX);                             \
-} while (0)
-
-#endif /* CONFIG_64BIT */
-
-struct task_struct;
-
-extern void elf_dump_regs(elf_greg_t *, struct pt_regs *regs);
-extern int dump_task_regs(struct task_struct *, elf_gregset_t *);
-extern int dump_task_fpu(struct task_struct *, elf_fpregset_t *);
-
-#define ELF_CORE_COPY_REGS(elf_regs, regs)                      \
-        elf_dump_regs((elf_greg_t *)&(elf_regs), regs);
-#define ELF_CORE_COPY_TASK_REGS(tsk, elf_regs) dump_task_regs(tsk, elf_regs)
-#define ELF_CORE_COPY_FPREGS(tsk, elf_fpregs)                   \
-        dump_task_fpu(tsk, elf_fpregs)
-
-#define USE_ELF_CORE_DUMP
-#define ELF_EXEC_PAGESIZE       PAGE_SIZE
-
-/* This yields a mask that user programs can use to figure out what
-   instruction set this cpu supports.  This could be done in userspace,
-   but it's not easy, and we've already done it here.  */
-
-#define ELF_HWCAP       (0)
-
-/* This yields a string that ld.so will use to load implementation
-   specific libraries for optimization.  This is more specific in
-   intent than poking at uname or /proc/cpuinfo.
-
-   For the moment, we have only optimizations for the Intel generations,
-   but that could change... */
-
-#define ELF_PLATFORM  (NULL)
-
-/*
- * See comments in asm-alpha/elf.h, this is the same thing
- * on the MIPS.
- */
-#define ELF_PLAT_INIT(_r, load_addr)    do { \
-        _r->regs[1] = _r->regs[2] = _r->regs[3] = _r->regs[4] = 0;      \
-        _r->regs[5] = _r->regs[6] = _r->regs[7] = _r->regs[8] = 0;      \
-        _r->regs[9] = _r->regs[10] = _r->regs[11] = _r->regs[12] = 0;   \
-        _r->regs[13] = _r->regs[14] = _r->regs[15] = _r->regs[16] = 0;  \
-        _r->regs[17] = _r->regs[18] = _r->regs[19] = _r->regs[20] = 0;  \
-        _r->regs[21] = _r->regs[22] = _r->regs[23] = _r->regs[24] = 0;  \
-        _r->regs[25] = _r->regs[26] = _r->regs[27] = _r->regs[28] = 0;  \
-        _r->regs[30] = _r->regs[31] = 0;                                \
-} while (0)
-
-/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
-   use of this is to invoke "./ld.so someprog" to test out a new version of
-   the loader.  We need to make sure that it is out of the way of the program
-   that it will "exec", and that there is sufficient room for the brk.  */
-
-#ifndef ELF_ET_DYN_BASE
-#define ELF_ET_DYN_BASE         (TASK_SIZE / 3 * 2)
-#endif
-
-#endif /* _ASM_ELF_H */
diff --git a/include/asm-mips/emergency-restart.h b/include/asm-mips/emergency-restart.h
deleted file mode 100644
index 108d8c48e42e..000000000000
--- a/include/asm-mips/emergency-restart.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
-
-#include <asm-generic/emergency-restart.h>
-
-#endif /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-mips/emma2rh/emma2rh.h b/include/asm-mips/emma2rh/emma2rh.h
deleted file mode 100644
index 6a1af0af51e3..000000000000
--- a/include/asm-mips/emma2rh/emma2rh.h
+++ /dev/null
@@ -1,333 +0,0 @@
-/*
- *  include/asm-mips/emma2rh/emma2rh.h
- *      This file is EMMA2RH common header.
- *
- *  Copyright (C) NEC Electronics Corporation 2005-2006
- *
- *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
- *          Copyright 2001 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ASM_EMMA2RH_EMMA2RH_H
-#define __ASM_EMMA2RH_EMMA2RH_H
-
-#include <irq.h>
-
-/*
- * EMMA2RH registers
- */
-#define REGBASE 0x10000000
-
-#define EMMA2RH_BHIF_STRAP_0    (0x000010+REGBASE)
-#define EMMA2RH_BHIF_INT_ST_0   (0x000030+REGBASE)
-#define EMMA2RH_BHIF_INT_ST_1   (0x000034+REGBASE)
-#define EMMA2RH_BHIF_INT_ST_2   (0x000038+REGBASE)
-#define EMMA2RH_BHIF_INT_EN_0   (0x000040+REGBASE)
-#define EMMA2RH_BHIF_INT_EN_1   (0x000044+REGBASE)
-#define EMMA2RH_BHIF_INT_EN_2   (0x000048+REGBASE)
-#define EMMA2RH_BHIF_INT1_EN_0  (0x000050+REGBASE)
-#define EMMA2RH_BHIF_INT1_EN_1  (0x000054+REGBASE)
-#define EMMA2RH_BHIF_INT1_EN_2  (0x000058+REGBASE)
-#define EMMA2RH_BHIF_SW_INT     (0x000070+REGBASE)
-#define EMMA2RH_BHIF_SW_INT_EN  (0x000080+REGBASE)
-#define EMMA2RH_BHIF_SW_INT_CLR (0x000090+REGBASE)
-#define EMMA2RH_BHIF_MAIN_CTRL  (0x0000b4+REGBASE)
-#define EMMA2RH_BHIF_EXCEPT_VECT_BASE_ADDRESS   (0x0000c0+REGBASE)
-#define EMMA2RH_GPIO_DIR        (0x110d20+REGBASE)
-#define EMMA2RH_GPIO_INT_ST     (0x110d30+REGBASE)
-#define EMMA2RH_GPIO_INT_MASK   (0x110d3c+REGBASE)
-#define EMMA2RH_GPIO_INT_MODE   (0x110d48+REGBASE)
-#define EMMA2RH_GPIO_INT_CND_A  (0x110d54+REGBASE)
-#define EMMA2RH_GPIO_INT_CND_B  (0x110d60+REGBASE)
-#define EMMA2RH_PBRD_INT_EN     (0x100010+REGBASE)
-#define EMMA2RH_PBRD_CLKSEL     (0x100028+REGBASE)
-#define EMMA2RH_PFUR0_BASE      (0x101000+REGBASE)
-#define EMMA2RH_PFUR1_BASE      (0x102000+REGBASE)
-#define EMMA2RH_PFUR2_BASE      (0x103000+REGBASE)
-#define EMMA2RH_PIIC0_BASE      (0x107000+REGBASE)
-#define EMMA2RH_PIIC1_BASE      (0x108000+REGBASE)
-#define EMMA2RH_PIIC2_BASE      (0x109000+REGBASE)
-#define EMMA2RH_PCI_CONTROL     (0x200000+REGBASE)
-#define EMMA2RH_PCI_ARBIT_CTR   (0x200004+REGBASE)
-#define EMMA2RH_PCI_IWIN0_CTR   (0x200010+REGBASE)
-#define EMMA2RH_PCI_IWIN1_CTR   (0x200014+REGBASE)
-#define EMMA2RH_PCI_INIT_ESWP   (0x200018+REGBASE)
-#define EMMA2RH_PCI_INT         (0x200020+REGBASE)
-#define EMMA2RH_PCI_INT_EN      (0x200024+REGBASE)
-#define EMMA2RH_PCI_TWIN_CTR    (0x200030+REGBASE)
-#define EMMA2RH_PCI_TWIN_BADR   (0x200034+REGBASE)
-#define EMMA2RH_PCI_TWIN0_DADR  (0x200038+REGBASE)
-#define EMMA2RH_PCI_TWIN1_DADR  (0x20003c+REGBASE)
-
-/*
- *  Memory map (physical address)
- *
- *  Note most of the following address must be properly aligned by the
- *  corresponding size.  For example, if PCI_IO_SIZE is 16MB, then
- *  PCI_IO_BASE must be aligned along 16MB boundary.
- */
-
-/* the actual ram size is detected at run-time */
-#define EMMA2RH_RAM_BASE        0x00000000
-#define EMMA2RH_RAM_SIZE        0x10000000      /* less than 256MB */
-
-#define EMMA2RH_IO_BASE         0x10000000
-#define EMMA2RH_IO_SIZE         0x01000000      /* 16 MB */
-
-#define EMMA2RH_GENERALIO_BASE  0x11000000
-#define EMMA2RH_GENERALIO_SIZE  0x01000000      /* 16 MB */
-
-#define EMMA2RH_PCI_IO_BASE     0x12000000
-#define EMMA2RH_PCI_IO_SIZE     0x02000000      /* 32 MB */
-
-#define EMMA2RH_PCI_MEM_BASE    0x14000000
-#define EMMA2RH_PCI_MEM_SIZE    0x08000000      /* 128 MB */
-
-#define EMMA2RH_ROM_BASE        0x1c000000
-#define EMMA2RH_ROM_SIZE        0x04000000      /* 64 MB */
-
-#define EMMA2RH_PCI_CONFIG_BASE EMMA2RH_PCI_IO_BASE
-#define EMMA2RH_PCI_CONFIG_SIZE EMMA2RH_PCI_IO_SIZE
-
-#define NUM_CPU_IRQ             8
-#define NUM_EMMA2RH_IRQ         96
-
-#define CPU_EMMA2RH_CASCADE     2
-#define CPU_IRQ_BASE            MIPS_CPU_IRQ_BASE
-#define EMMA2RH_IRQ_BASE        (CPU_IRQ_BASE + NUM_CPU_IRQ)
-
-/*
- * emma2rh irq defs
- */
-
-#define EMMA2RH_IRQ_INT0        (0 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT1        (1 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT2        (2 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT3        (3 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT4        (4 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT5        (5 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT6        (6 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT7        (7 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT8        (8 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT9        (9 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT10       (10 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT11       (11 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT12       (12 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT13       (13 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT14       (14 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT15       (15 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT16       (16 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT17       (17 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT18       (18 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT19       (19 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT20       (20 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT21       (21 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT22       (22 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT23       (23 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT24       (24 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT25       (25 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT26       (26 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT27       (27 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT28       (28 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT29       (29 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT30       (30 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT31       (31 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT32       (32 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT33       (33 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT34       (34 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT35       (35 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT36       (36 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT37       (37 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT38       (38 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT39       (39 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT40       (40 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT41       (41 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT42       (42 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT43       (43 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT44       (44 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT45       (45 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT46       (46 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT47       (47 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT48       (48 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT49       (49 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT50       (50 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT51       (51 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT52       (52 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT53       (53 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT54       (54 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT55       (55 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT56       (56 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT57       (57 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT58       (58 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT59       (59 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT60       (60 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT61       (61 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT62       (62 + EMMA2RH_IRQ_BASE)
-#define EMMA2RH_IRQ_INT63       (63 + EMMA2RH_IRQ_BASE)
-
-#define EMMA2RH_IRQ_PFUR0       EMMA2RH_IRQ_INT49
-#define EMMA2RH_IRQ_PFUR1       EMMA2RH_IRQ_INT50
-#define EMMA2RH_IRQ_PFUR2       EMMA2RH_IRQ_INT51
-#define EMMA2RH_IRQ_PIIC0       EMMA2RH_IRQ_INT56
-#define EMMA2RH_IRQ_PIIC1       EMMA2RH_IRQ_INT57
-#define EMMA2RH_IRQ_PIIC2       EMMA2RH_IRQ_INT58
-
-/*
- *  EMMA2RH Register Access
- */
-
-#define EMMA2RH_BASE (0xa0000000)
-
-static inline void emma2rh_sync(void)
-{
-        volatile u32 *p = (volatile u32 *)0xbfc00000;
-        (void)(*p);
-}
-
-static inline void emma2rh_out32(u32 offset, u32 val)
-{
-        *(volatile u32 *)(EMMA2RH_BASE | offset) = val;
-        emma2rh_sync();
-}
-
-static inline u32 emma2rh_in32(u32 offset)
-{
-        u32 val = *(volatile u32 *)(EMMA2RH_BASE | offset);
-        emma2rh_sync();
-        return val;
-}
-
-static inline void emma2rh_out16(u32 offset, u16 val)
-{
-        *(volatile u16 *)(EMMA2RH_BASE | offset) = val;
-        emma2rh_sync();
-}
-
-static inline u16 emma2rh_in16(u32 offset)
-{
-        u16 val = *(volatile u16 *)(EMMA2RH_BASE | offset);
-        emma2rh_sync();
-        return val;
-}
-
-static inline void emma2rh_out8(u32 offset, u8 val)
-{
-        *(volatile u8 *)(EMMA2RH_BASE | offset) = val;
-        emma2rh_sync();
-}
-
-static inline u8 emma2rh_in8(u32 offset)
-{
-        u8 val = *(volatile u8 *)(EMMA2RH_BASE | offset);
-        emma2rh_sync();
-        return val;
-}
-
-/**
- * IIC registers map
- **/
-
-/*---------------------------------------------------------------------------*/
-/* CNT - Control register (00H R/W)                                          */
-/*---------------------------------------------------------------------------*/
-#define SPT         0x00000001
-#define STT         0x00000002
-#define ACKE        0x00000004
-#define WTIM        0x00000008
-#define SPIE        0x00000010
-#define WREL        0x00000020
-#define LREL        0x00000040
-#define IICE        0x00000080
-#define CNT_RESERVED    0x000000ff      /* reserved bit 0 */
-
-#define I2C_EMMA_START      (IICE | STT)
-#define I2C_EMMA_STOP       (IICE | SPT)
-#define I2C_EMMA_REPSTART   I2C_EMMA_START
-
-/*---------------------------------------------------------------------------*/
-/* STA - Status register (10H Read)                                          */
-/*---------------------------------------------------------------------------*/
-#define MSTS        0x00000080
-#define ALD         0x00000040
-#define EXC         0x00000020
-#define COI         0x00000010
-#define TRC         0x00000008
-#define ACKD        0x00000004
-#define STD         0x00000002
-#define SPD         0x00000001
-
-/*---------------------------------------------------------------------------*/
-/* CSEL - Clock select register (20H R/W)                                    */
-/*---------------------------------------------------------------------------*/
-#define FCL         0x00000080
-#define ND50        0x00000040
-#define CLD         0x00000020
-#define DAD         0x00000010
-#define SMC         0x00000008
-#define DFC         0x00000004
-#define CL          0x00000003
-#define CSEL_RESERVED   0x000000ff      /* reserved bit 0 */
-
-#define FAST397     0x0000008b
-#define FAST297     0x0000008a
-#define FAST347     0x0000000b
-#define FAST260     0x0000000a
-#define FAST130     0x00000008
-#define STANDARD108 0x00000083
-#define STANDARD83  0x00000082
-#define STANDARD95  0x00000003
-#define STANDARD73  0x00000002
-#define STANDARD36  0x00000001
-#define STANDARD71  0x00000000
-
-/*---------------------------------------------------------------------------*/
-/* SVA - Slave address register (30H R/W)                                    */
-/*---------------------------------------------------------------------------*/
-#define SVA         0x000000fe
-
-/*---------------------------------------------------------------------------*/
-/* SHR - Shift register (40H R/W)                                            */
-/*---------------------------------------------------------------------------*/
-#define SR          0x000000ff
-
-/*---------------------------------------------------------------------------*/
-/* INT - Interrupt register (50H R/W)                                        */
-/* INTM - Interrupt mask register (60H R/W)                                  */
-/*---------------------------------------------------------------------------*/
-#define INTE0       0x00000001
-
-/***********************************************************************
- * I2C registers
- ***********************************************************************
- */
-#define I2C_EMMA_CNT            0x00
-#define I2C_EMMA_STA            0x10
-#define I2C_EMMA_CSEL           0x20
-#define I2C_EMMA_SVA            0x30
-#define I2C_EMMA_SHR            0x40
-#define I2C_EMMA_INT            0x50
-#define I2C_EMMA_INTM           0x60
-
-/*
- * include the board dependent part
- */
-#if defined(CONFIG_MARKEINS)
-#include <asm/emma2rh/markeins.h>
-#else
-#error "Unknown EMMA2RH board!"
-#endif
-
-#endif /* __ASM_EMMA2RH_EMMA2RH_H */
diff --git a/include/asm-mips/emma2rh/markeins.h b/include/asm-mips/emma2rh/markeins.h
deleted file mode 100644
index 973b0628490d..000000000000
--- a/include/asm-mips/emma2rh/markeins.h
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- *  include/asm-mips/emma2rh/markeins.h
- *      This file is EMMA2RH board depended header.
- *
- *  Copyright (C) NEC Electronics Corporation 2005-2006
- *
- *  This file based on include/asm-mips/ddb5xxx/ddb5xxx.h
- *          Copyright 2001 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#ifndef MARKEINS_H
-#define MARKEINS_H
-
-#define NUM_EMMA2RH_IRQ_SW      32
-#define NUM_EMMA2RH_IRQ_GPIO    32
-
-#define EMMA2RH_SW_CASCADE      (EMMA2RH_IRQ_INT7 - EMMA2RH_IRQ_INT0)
-#define EMMA2RH_GPIO_CASCADE    (EMMA2RH_IRQ_INT46 - EMMA2RH_IRQ_INT0)
-
-#define EMMA2RH_SW_IRQ_BASE     (EMMA2RH_IRQ_BASE + NUM_EMMA2RH_IRQ)
-#define EMMA2RH_GPIO_IRQ_BASE   (EMMA2RH_SW_IRQ_BASE + NUM_EMMA2RH_IRQ_SW)
-
-#define EMMA2RH_SW_IRQ_INT0     (0+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT1     (1+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT2     (2+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT3     (3+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT4     (4+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT5     (5+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT6     (6+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT7     (7+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT8     (8+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT9     (9+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT10    (10+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT11    (11+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT12    (12+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT13    (13+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT14    (14+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT15    (15+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT16    (16+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT17    (17+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT18    (18+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT19    (19+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT20    (20+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT21    (21+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT22    (22+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT23    (23+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT24    (24+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT25    (25+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT26    (26+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT27    (27+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT28    (28+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT29    (29+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT30    (30+EMMA2RH_SW_IRQ_BASE)
-#define EMMA2RH_SW_IRQ_INT31    (31+EMMA2RH_SW_IRQ_BASE)
-
-#define MARKEINS_PCI_IRQ_INTA   EMMA2RH_GPIO_IRQ_BASE+15
-#define MARKEINS_PCI_IRQ_INTB   EMMA2RH_GPIO_IRQ_BASE+16
-#define MARKEINS_PCI_IRQ_INTC   EMMA2RH_GPIO_IRQ_BASE+17
-#define MARKEINS_PCI_IRQ_INTD   EMMA2RH_GPIO_IRQ_BASE+18
-
-#endif /* CONFIG_MARKEINS */
diff --git a/include/asm-mips/errno.h b/include/asm-mips/errno.h
deleted file mode 100644
index 3c0d840e4577..000000000000
--- a/include/asm-mips/errno.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999, 2001, 2002 by Ralf Baechle
- */
-#ifndef _ASM_ERRNO_H
-#define _ASM_ERRNO_H
-
-/*
- * These error numbers are intended to be MIPS ABI compatible
- */
-
-#include <asm-generic/errno-base.h>
-
-#define ENOMSG          35      /* No message of desired type */
-#define EIDRM           36      /* Identifier removed */
-#define ECHRNG          37      /* Channel number out of range */
-#define EL2NSYNC        38      /* Level 2 not synchronized */
-#define EL3HLT          39      /* Level 3 halted */
-#define EL3RST          40      /* Level 3 reset */
-#define ELNRNG          41      /* Link number out of range */
-#define EUNATCH         42      /* Protocol driver not attached */
-#define ENOCSI          43      /* No CSI structure available */
-#define EL2HLT          44      /* Level 2 halted */
-#define EDEADLK         45      /* Resource deadlock would occur */
-#define ENOLCK          46      /* No record locks available */
-#define EBADE           50      /* Invalid exchange */
-#define EBADR           51      /* Invalid request descriptor */
-#define EXFULL          52      /* Exchange full */
-#define ENOANO          53      /* No anode */
-#define EBADRQC         54      /* Invalid request code */
-#define EBADSLT         55      /* Invalid slot */
-#define EDEADLOCK       56      /* File locking deadlock error */
-#define EBFONT          59      /* Bad font file format */
-#define ENOSTR          60      /* Device not a stream */
-#define ENODATA         61      /* No data available */
-#define ETIME           62      /* Timer expired */
-#define ENOSR           63      /* Out of streams resources */
-#define ENONET          64      /* Machine is not on the network */
-#define ENOPKG          65      /* Package not installed */
-#define EREMOTE         66      /* Object is remote */
-#define ENOLINK         67      /* Link has been severed */
-#define EADV            68      /* Advertise error */
-#define ESRMNT          69      /* Srmount error */
-#define ECOMM           70      /* Communication error on send */
-#define EPROTO          71      /* Protocol error */
-#define EDOTDOT         73      /* RFS specific error */
-#define EMULTIHOP       74      /* Multihop attempted */
-#define EBADMSG         77      /* Not a data message */
-#define ENAMETOOLONG    78      /* File name too long */
-#define EOVERFLOW       79      /* Value too large for defined data type */
-#define ENOTUNIQ        80      /* Name not unique on network */
-#define EBADFD          81      /* File descriptor in bad state */
-#define EREMCHG         82      /* Remote address changed */
-#define ELIBACC         83      /* Can not access a needed shared library */
-#define ELIBBAD         84      /* Accessing a corrupted shared library */
-#define ELIBSCN         85      /* .lib section in a.out corrupted */
-#define ELIBMAX         86      /* Attempting to link in too many shared libraries */
-#define ELIBEXEC        87      /* Cannot exec a shared library directly */
-#define EILSEQ          88      /* Illegal byte sequence */
-#define ENOSYS          89      /* Function not implemented */
-#define ELOOP           90      /* Too many symbolic links encountered */
-#define ERESTART        91      /* Interrupted system call should be restarted */
-#define ESTRPIPE        92      /* Streams pipe error */
-#define ENOTEMPTY       93      /* Directory not empty */
-#define EUSERS          94      /* Too many users */
-#define ENOTSOCK        95      /* Socket operation on non-socket */
-#define EDESTADDRREQ    96      /* Destination address required */
-#define EMSGSIZE        97      /* Message too long */
-#define EPROTOTYPE      98      /* Protocol wrong type for socket */
-#define ENOPROTOOPT     99      /* Protocol not available */
-#define EPROTONOSUPPORT 120     /* Protocol not supported */
-#define ESOCKTNOSUPPORT 121     /* Socket type not supported */
-#define EOPNOTSUPP      122     /* Operation not supported on transport endpoint */
-#define EPFNOSUPPORT    123     /* Protocol family not supported */
-#define EAFNOSUPPORT    124     /* Address family not supported by protocol */
-#define EADDRINUSE      125     /* Address already in use */
-#define EADDRNOTAVAIL   126     /* Cannot assign requested address */
-#define ENETDOWN        127     /* Network is down */
-#define ENETUNREACH     128     /* Network is unreachable */
-#define ENETRESET       129     /* Network dropped connection because of reset */
-#define ECONNABORTED    130     /* Software caused connection abort */
-#define ECONNRESET      131     /* Connection reset by peer */
-#define ENOBUFS         132     /* No buffer space available */
-#define EISCONN         133     /* Transport endpoint is already connected */
-#define ENOTCONN        134     /* Transport endpoint is not connected */
-#define EUCLEAN         135     /* Structure needs cleaning */
-#define ENOTNAM         137     /* Not a XENIX named type file */
-#define ENAVAIL         138     /* No XENIX semaphores available */
-#define EISNAM          139     /* Is a named type file */
-#define EREMOTEIO       140     /* Remote I/O error */
-#define EINIT           141     /* Reserved */
-#define EREMDEV         142     /* Error 142 */
-#define ESHUTDOWN       143     /* Cannot send after transport endpoint shutdown */
-#define ETOOMANYREFS    144     /* Too many references: cannot splice */
-#define ETIMEDOUT       145     /* Connection timed out */
-#define ECONNREFUSED    146     /* Connection refused */
-#define EHOSTDOWN       147     /* Host is down */
-#define EHOSTUNREACH    148     /* No route to host */
-#define EWOULDBLOCK     EAGAIN  /* Operation would block */
-#define EALREADY        149     /* Operation already in progress */
-#define EINPROGRESS     150     /* Operation now in progress */
-#define ESTALE          151     /* Stale NFS file handle */
-#define ECANCELED       158     /* AIO operation canceled */
-
-/*
- * These error are Linux extensions.
- */
-#define ENOMEDIUM       159     /* No medium found */
-#define EMEDIUMTYPE     160     /* Wrong medium type */
-#define ENOKEY          161     /* Required key not available */
-#define EKEYEXPIRED     162     /* Key has expired */
-#define EKEYREVOKED     163     /* Key has been revoked */
-#define EKEYREJECTED    164     /* Key was rejected by service */
-
-/* for robust mutexes */
-#define EOWNERDEAD      165     /* Owner died */
-#define ENOTRECOVERABLE 166     /* State not recoverable */
-
-#define EDQUOT          1133    /* Quota exceeded */
-
-#ifdef __KERNEL__
-
-/* The biggest error number defined here or in <linux/errno.h>. */
-#define EMAXERRNO       1133
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_ERRNO_H */
diff --git a/include/asm-mips/fb.h b/include/asm-mips/fb.h
deleted file mode 100644
index bd3f68c9ddfc..000000000000
--- a/include/asm-mips/fb.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_FB_H_
-#define _ASM_FB_H_
-
-#include <linux/fb.h>
-#include <linux/fs.h>
-#include <asm/page.h>
-
-static inline void fb_pgprotect(struct file *file, struct vm_area_struct *vma,
-                                unsigned long off)
-{
-        vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
-}
-
-static inline int fb_is_primary_device(struct fb_info *info)
-{
-        return 0;
-}
-
-#endif /* _ASM_FB_H_ */
diff --git a/include/asm-mips/fcntl.h b/include/asm-mips/fcntl.h
deleted file mode 100644
index 2a52333a062d..000000000000
--- a/include/asm-mips/fcntl.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 97, 98, 99, 2003, 05 Ralf Baechle
- */
-#ifndef _ASM_FCNTL_H
-#define _ASM_FCNTL_H
-
-
-#define O_APPEND        0x0008
-#define O_SYNC          0x0010
-#define O_NONBLOCK      0x0080
-#define O_CREAT         0x0100  /* not fcntl */
-#define O_TRUNC         0x0200  /* not fcntl */
-#define O_EXCL          0x0400  /* not fcntl */
-#define O_NOCTTY        0x0800  /* not fcntl */
-#define FASYNC          0x1000  /* fcntl, for BSD compatibility */
-#define O_LARGEFILE     0x2000  /* allow large file opens */
-#define O_DIRECT        0x8000  /* direct disk access hint */
-
-#define F_GETLK         14
-#define F_SETLK         6
-#define F_SETLKW        7
-
-#define F_SETOWN        24      /*  for sockets. */
-#define F_GETOWN        23      /*  for sockets. */
-
-#ifndef __mips64
-#define F_GETLK64       33      /*  using 'struct flock64' */
-#define F_SETLK64       34
-#define F_SETLKW64      35
-#endif
-
-/*
- * The flavours of struct flock.  "struct flock" is the ABI compliant
- * variant.  Finally struct flock64 is the LFS variant of struct flock.  As
- * a historic accident and inconsistence with the ABI definition it doesn't
- * contain all the same fields as struct flock.
- */
-
-#ifdef CONFIG_32BIT
-
-struct flock {
-        short   l_type;
-        short   l_whence;
-        off_t   l_start;
-        off_t   l_len;
-        long    l_sysid;
-        __kernel_pid_t l_pid;
-        long    pad[4];
-};
-
-#define HAVE_ARCH_STRUCT_FLOCK
-
-#endif /* CONFIG_32BIT */
-
-#include <asm-generic/fcntl.h>
-
-#endif /* _ASM_FCNTL_H */
diff --git a/include/asm-mips/fixmap.h b/include/asm-mips/fixmap.h
deleted file mode 100644
index 9cc8522a394f..000000000000
--- a/include/asm-mips/fixmap.h
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * fixmap.h: compile-time virtual memory allocation
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998 Ingo Molnar
- *
- * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
- */
-
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
-
-#include <asm/page.h>
-#ifdef CONFIG_HIGHMEM
-#include <linux/threads.h>
-#include <asm/kmap_types.h>
-#endif
-
-/*
- * Here we define all the compile-time 'special' virtual
- * addresses. The point is to have a constant address at
- * compile time, but to set the physical address only
- * in the boot process. We allocate these special  addresses
- * from the end of virtual memory (0xfffff000) backwards.
- * Also this lets us do fail-safe vmalloc(), we
- * can guarantee that these special addresses and
- * vmalloc()-ed addresses never overlap.
- *
- * these 'compile-time allocated' memory buffers are
- * fixed-size 4k pages. (or larger if used with an increment
- * highger than 1) use fixmap_set(idx,phys) to associate
- * physical memory with fixmap indices.
- *
- * TLB entries of such buffers will not be flushed across
- * task switches.
- */
-
-/*
- * on UP currently we will have no trace of the fixmap mechanizm,
- * no page table allocations, etc. This might change in the
- * future, say framebuffers for the console driver(s) could be
- * fix-mapped?
- */
-enum fixed_addresses {
-#define FIX_N_COLOURS 8
-        FIX_CMAP_BEGIN,
-#ifdef CONFIG_MIPS_MT_SMTC
-        FIX_CMAP_END = FIX_CMAP_BEGIN + (FIX_N_COLOURS * NR_CPUS),
-#else
-        FIX_CMAP_END = FIX_CMAP_BEGIN + FIX_N_COLOURS,
-#endif
-#ifdef CONFIG_HIGHMEM
-        /* reserved pte's for temporary kernel mappings */
-        FIX_KMAP_BEGIN = FIX_CMAP_END + 1,
-        FIX_KMAP_END = FIX_KMAP_BEGIN+(KM_TYPE_NR*NR_CPUS)-1,
-#endif
-        __end_of_fixed_addresses
-};
-
-/*
- * used by vmalloc.c.
- *
- * Leave one empty page between vmalloc'ed areas and
- * the start of the fixmap, and leave one page empty
- * at the top of mem..
- */
-#if defined(CONFIG_CPU_TX39XX) || defined(CONFIG_CPU_TX49XX)
-#define FIXADDR_TOP     ((unsigned long)(long)(int)(0xff000000 - 0x20000))
-#else
-#define FIXADDR_TOP     ((unsigned long)(long)(int)0xfffe0000)
-#endif
-#define FIXADDR_SIZE    (__end_of_fixed_addresses << PAGE_SHIFT)
-#define FIXADDR_START   (FIXADDR_TOP - FIXADDR_SIZE)
-
-#define __fix_to_virt(x)        (FIXADDR_TOP - ((x) << PAGE_SHIFT))
-#define __virt_to_fix(x)        ((FIXADDR_TOP - ((x)&PAGE_MASK)) >> PAGE_SHIFT)
-
-extern void __this_fixmap_does_not_exist(void);
-
-/*
- * 'index to address' translation. If anyone tries to use the idx
- * directly without tranlation, we catch the bug with a NULL-deference
- * kernel oops. Illegal ranges of incoming indices are caught too.
- */
-static inline unsigned long fix_to_virt(const unsigned int idx)
-{
-        /*
-         * this branch gets completely eliminated after inlining,
-         * except when someone tries to use fixaddr indices in an
-         * illegal way. (such as mixing up address types or using
-         * out-of-range indices).
-         *
-         * If it doesn't get removed, the linker will complain
-         * loudly with a reasonably clear error message..
-         */
-        if (idx >= __end_of_fixed_addresses)
-                __this_fixmap_does_not_exist();
-
-        return __fix_to_virt(idx);
-}
-
-static inline unsigned long virt_to_fix(const unsigned long vaddr)
-{
-        BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
-        return __virt_to_fix(vaddr);
-}
-
-/*
- * Called from pgtable_init()
- */
-extern void fixrange_init(unsigned long start, unsigned long end,
-        pgd_t *pgd_base);
-
-
-#endif
diff --git a/include/asm-mips/floppy.h b/include/asm-mips/floppy.h
deleted file mode 100644
index 992d232adc83..000000000000
--- a/include/asm-mips/floppy.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * Architecture specific parts of the Floppy driver
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995 - 2000 Ralf Baechle
- */
-#ifndef _ASM_FLOPPY_H
-#define _ASM_FLOPPY_H
-
-#include <linux/dma-mapping.h>
-
-static inline void fd_cacheflush(char * addr, long size)
-{
-        dma_cache_sync(NULL, addr, size, DMA_BIDIRECTIONAL);
-}
-
-#define MAX_BUFFER_SECTORS 24
-
-
-/*
- * And on Mips's the CMOS info fails also ...
- *
- * FIXME: This information should come from the ARC configuration tree
- *        or whereever a particular machine has stored this ...
- */
-#define FLOPPY0_TYPE            fd_drive_type(0)
-#define FLOPPY1_TYPE            fd_drive_type(1)
-
-#define FDC1                    fd_getfdaddr1();
-
-#define N_FDC 1                 /* do you *really* want a second controller? */
-#define N_DRIVE 8
-
-/*
- * The DMA channel used by the floppy controller cannot access data at
- * addresses >= 16MB
- *
- * Went back to the 1MB limit, as some people had problems with the floppy
- * driver otherwise. It doesn't matter much for performance anyway, as most
- * floppy accesses go through the track buffer.
- *
- * On MIPSes using vdma, this actually means that *all* transfers go thru
- * the * track buffer since 0x1000000 is always smaller than KSEG0/1.
- * Actually this needs to be a bit more complicated since the so much different
- * hardware available with MIPS CPUs ...
- */
-#define CROSS_64KB(a, s) ((unsigned long)(a)/K_64 != ((unsigned long)(a) + (s) - 1) / K_64)
-
-#define EXTRA_FLOPPY_PARAMS
-
-#include <floppy.h>
-
-#endif /* _ASM_FLOPPY_H */
diff --git a/include/asm-mips/fpregdef.h b/include/asm-mips/fpregdef.h
deleted file mode 100644
index 2b5fddc8f487..000000000000
--- a/include/asm-mips/fpregdef.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * Definitions for the FPU register names
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999 Ralf Baechle
- * Copyright (C) 1985 MIPS Computer Systems, Inc.
- * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_FPREGDEF_H
-#define _ASM_FPREGDEF_H
-
-#include <asm/sgidefs.h>
-
-#if _MIPS_SIM == _MIPS_SIM_ABI32
-
-/*
- * These definitions only cover the R3000-ish 16/32 register model.
- * But we're trying to be R3000 friendly anyway ...
- */
-#define fv0     $f0      /* return value */
-#define fv0f    $f1
-#define fv1     $f2
-#define fv1f    $f3
-#define fa0     $f12     /* argument registers */
-#define fa0f    $f13
-#define fa1     $f14
-#define fa1f    $f15
-#define ft0     $f4      /* caller saved */
-#define ft0f    $f5
-#define ft1     $f6
-#define ft1f    $f7
-#define ft2     $f8
-#define ft2f    $f9
-#define ft3     $f10
-#define ft3f    $f11
-#define ft4     $f16
-#define ft4f    $f17
-#define ft5     $f18
-#define ft5f    $f19
-#define fs0     $f20     /* callee saved */
-#define fs0f    $f21
-#define fs1     $f22
-#define fs1f    $f23
-#define fs2     $f24
-#define fs2f    $f25
-#define fs3     $f26
-#define fs3f    $f27
-#define fs4     $f28
-#define fs4f    $f29
-#define fs5     $f30
-#define fs5f    $f31
-
-#define fcr31   $31      /* FPU status register */
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
-
-#define fv0     $f0     /* return value */
-#define fv1     $f2
-#define fa0     $f12    /* argument registers */
-#define fa1     $f13
-#define fa2     $f14
-#define fa3     $f15
-#define fa4     $f16
-#define fa5     $f17
-#define fa6     $f18
-#define fa7     $f19
-#define ft0     $f4     /* caller saved */
-#define ft1     $f5
-#define ft2     $f6
-#define ft3     $f7
-#define ft4     $f8
-#define ft5     $f9
-#define ft6     $f10
-#define ft7     $f11
-#define ft8     $f20
-#define ft9     $f21
-#define ft10    $f22
-#define ft11    $f23
-#define ft12    $f1
-#define ft13    $f3
-#define fs0     $f24    /* callee saved */
-#define fs1     $f25
-#define fs2     $f26
-#define fs3     $f27
-#define fs4     $f28
-#define fs5     $f29
-#define fs6     $f30
-#define fs7     $f31
-
-#define fcr31   $31
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
-
-#endif /* _ASM_FPREGDEF_H */
diff --git a/include/asm-mips/fpu.h b/include/asm-mips/fpu.h
deleted file mode 100644
index 8a3ef247659a..000000000000
--- a/include/asm-mips/fpu.h
+++ /dev/null
@@ -1,153 +0,0 @@
-/*
- * Copyright (C) 2002 MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_FPU_H
-#define _ASM_FPU_H
-
-#include <linux/sched.h>
-#include <linux/thread_info.h>
-#include <linux/bitops.h>
-
-#include <asm/mipsregs.h>
-#include <asm/cpu.h>
-#include <asm/cpu-features.h>
-#include <asm/hazards.h>
-#include <asm/processor.h>
-#include <asm/current.h>
-
-#ifdef CONFIG_MIPS_MT_FPAFF
-#include <asm/mips_mt.h>
-#endif
-
-struct sigcontext;
-struct sigcontext32;
-
-extern asmlinkage int (*save_fp_context)(struct sigcontext __user *sc);
-extern asmlinkage int (*restore_fp_context)(struct sigcontext __user *sc);
-
-extern asmlinkage int (*save_fp_context32)(struct sigcontext32 __user *sc);
-extern asmlinkage int (*restore_fp_context32)(struct sigcontext32 __user *sc);
-
-extern void fpu_emulator_init_fpu(void);
-extern int fpu_emulator_save_context(struct sigcontext __user *sc);
-extern int fpu_emulator_restore_context(struct sigcontext __user *sc);
-extern void _init_fpu(void);
-extern void _save_fp(struct task_struct *);
-extern void _restore_fp(struct task_struct *);
-
-#define __enable_fpu()                                                  \
-do {                                                                    \
-        set_c0_status(ST0_CU1);                                         \
-        enable_fpu_hazard();                                            \
-} while (0)
-
-#define __disable_fpu()                                                 \
-do {                                                                    \
-        clear_c0_status(ST0_CU1);                                       \
-        disable_fpu_hazard();                                           \
-} while (0)
-
-#define enable_fpu()                                                    \
-do {                                                                    \
-        if (cpu_has_fpu)                                                \
-                __enable_fpu();                                         \
-} while (0)
-
-#define disable_fpu()                                                   \
-do {                                                                    \
-        if (cpu_has_fpu)                                                \
-                __disable_fpu();                                        \
-} while (0)
-
-
-#define clear_fpu_owner()       clear_thread_flag(TIF_USEDFPU)
-
-static inline int __is_fpu_owner(void)
-{
-        return test_thread_flag(TIF_USEDFPU);
-}
-
-static inline int is_fpu_owner(void)
-{
-        return cpu_has_fpu && __is_fpu_owner();
-}
-
-static inline void __own_fpu(void)
-{
-        __enable_fpu();
-        KSTK_STATUS(current) |= ST0_CU1;
-        set_thread_flag(TIF_USEDFPU);
-}
-
-static inline void own_fpu_inatomic(int restore)
-{
-        if (cpu_has_fpu && !__is_fpu_owner()) {
-                __own_fpu();
-                if (restore)
-                        _restore_fp(current);
-        }
-}
-
-static inline void own_fpu(int restore)
-{
-        preempt_disable();
-        own_fpu_inatomic(restore);
-        preempt_enable();
-}
-
-static inline void lose_fpu(int save)
-{
-        preempt_disable();
-        if (is_fpu_owner()) {
-                if (save)
-                        _save_fp(current);
-                KSTK_STATUS(current) &= ~ST0_CU1;
-                clear_thread_flag(TIF_USEDFPU);
-                __disable_fpu();
-        }
-        preempt_enable();
-}
-
-static inline void init_fpu(void)
-{
-        preempt_disable();
-        if (cpu_has_fpu) {
-                __own_fpu();
-                _init_fpu();
-        } else {
-                fpu_emulator_init_fpu();
-        }
-        preempt_enable();
-}
-
-static inline void save_fp(struct task_struct *tsk)
-{
-        if (cpu_has_fpu)
-                _save_fp(tsk);
-}
-
-static inline void restore_fp(struct task_struct *tsk)
-{
-        if (cpu_has_fpu)
-                _restore_fp(tsk);
-}
-
-static inline fpureg_t *get_fpu_regs(struct task_struct *tsk)
-{
-        if (tsk == current) {
-                preempt_disable();
-                if (is_fpu_owner())
-                        _save_fp(current);
-                preempt_enable();
-        }
-
-        return tsk->thread.fpu.fpr;
-}
-
-#endif /* _ASM_FPU_H */
diff --git a/include/asm-mips/fpu_emulator.h b/include/asm-mips/fpu_emulator.h
deleted file mode 100644
index 2731c38bd7ae..000000000000
--- a/include/asm-mips/fpu_emulator.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Further private data for which no space exists in mips_fpu_struct.
- * This should be subsumed into the mips_fpu_struct structure as
- * defined in processor.h as soon as the absurd wired absolute assembler
- * offsets become dynamic at compile time.
- *
- * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- */
-#ifndef _ASM_FPU_EMULATOR_H
-#define _ASM_FPU_EMULATOR_H
-
-struct mips_fpu_emulator_stats {
-        unsigned int emulated;
-        unsigned int loads;
-        unsigned int stores;
-        unsigned int cp1ops;
-        unsigned int cp1xops;
-        unsigned int errors;
-};
-
-extern struct mips_fpu_emulator_stats fpuemustats;
-
-#endif /* _ASM_FPU_EMULATOR_H */
diff --git a/include/asm-mips/futex.h b/include/asm-mips/futex.h
deleted file mode 100644
index b9cce90346cf..000000000000
--- a/include/asm-mips/futex.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 2006  Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_FUTEX_H
-#define _ASM_FUTEX_H
-
-#ifdef __KERNEL__
-
-#include <linux/futex.h>
-#include <linux/uaccess.h>
-#include <asm/barrier.h>
-#include <asm/errno.h>
-#include <asm/war.h>
-
-#define __futex_atomic_op(insn, ret, oldval, uaddr, oparg)              \
-{                                                                       \
-        if (cpu_has_llsc && R10000_LLSC_WAR) {                          \
-                __asm__ __volatile__(                                   \
-                "       .set    push                            \n"     \
-                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
-                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
-                "       .set    mips0                           \n"     \
-                "       " insn  "                               \n"     \
-                "       .set    mips3                           \n"     \
-                "2:     sc      $1, %2                          \n"     \
-                "       beqzl   $1, 1b                          \n"     \
-                __WEAK_LLSC_MB                                          \
-                "3:                                             \n"     \
-                "       .set    pop                             \n"     \
-                "       .set    mips0                           \n"     \
-                "       .section .fixup,\"ax\"                  \n"     \
-                "4:     li      %0, %6                          \n"     \
-                "       j       3b                              \n"     \
-                "       .previous                               \n"     \
-                "       .section __ex_table,\"a\"               \n"     \
-                "       "__UA_ADDR "\t1b, 4b                    \n"     \
-                "       "__UA_ADDR "\t2b, 4b                    \n"     \
-                "       .previous                               \n"     \
-                : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)             \
-                : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)    \
-                : "memory");                                            \
-        } else if (cpu_has_llsc) {                                      \
-                __asm__ __volatile__(                                   \
-                "       .set    push                            \n"     \
-                "       .set    noat                            \n"     \
-                "       .set    mips3                           \n"     \
-                "1:     ll      %1, %4  # __futex_atomic_op     \n"     \
-                "       .set    mips0                           \n"     \
-                "       " insn  "                               \n"     \
-                "       .set    mips3                           \n"     \
-                "2:     sc      $1, %2                          \n"     \
-                "       beqz    $1, 1b                          \n"     \
-                __WEAK_LLSC_MB                                          \
-                "3:                                             \n"     \
-                "       .set    pop                             \n"     \
-                "       .set    mips0                           \n"     \
-                "       .section .fixup,\"ax\"                  \n"     \
-                "4:     li      %0, %6                          \n"     \
-                "       j       3b                              \n"     \
-                "       .previous                               \n"     \
-                "       .section __ex_table,\"a\"               \n"     \
-                "       "__UA_ADDR "\t1b, 4b                    \n"     \
-                "       "__UA_ADDR "\t2b, 4b                    \n"     \
-                "       .previous                               \n"     \
-                : "=r" (ret), "=&r" (oldval), "=R" (*uaddr)             \
-                : "0" (0), "R" (*uaddr), "Jr" (oparg), "i" (-EFAULT)    \
-                : "memory");                                            \
-        } else                                                          \
-                ret = -ENOSYS;                                          \
-}
-
-static inline int
-futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
-{
-        int op = (encoded_op >> 28) & 7;
-        int cmp = (encoded_op >> 24) & 15;
-        int oparg = (encoded_op << 8) >> 20;
-        int cmparg = (encoded_op << 20) >> 20;
-        int oldval = 0, ret;
-        if (encoded_op & (FUTEX_OP_OPARG_SHIFT << 28))
-                oparg = 1 << oparg;
-
-        if (! access_ok (VERIFY_WRITE, uaddr, sizeof(int)))
-                return -EFAULT;
-
-        pagefault_disable();
-
-        switch (op) {
-        case FUTEX_OP_SET:
-                __futex_atomic_op("move $1, %z5", ret, oldval, uaddr, oparg);
-                break;
-
-        case FUTEX_OP_ADD:
-                __futex_atomic_op("addu $1, %1, %z5",
-                                  ret, oldval, uaddr, oparg);
-                break;
-        case FUTEX_OP_OR:
-                __futex_atomic_op("or   $1, %1, %z5",
-                                  ret, oldval, uaddr, oparg);
-                break;
-        case FUTEX_OP_ANDN:
-                __futex_atomic_op("and  $1, %1, %z5",
-                                  ret, oldval, uaddr, ~oparg);
-                break;
-        case FUTEX_OP_XOR:
-                __futex_atomic_op("xor  $1, %1, %z5",
-                                  ret, oldval, uaddr, oparg);
-                break;
-        default:
-                ret = -ENOSYS;
-        }
-
-        pagefault_enable();
-
-        if (!ret) {
-                switch (cmp) {
-                case FUTEX_OP_CMP_EQ: ret = (oldval == cmparg); break;
-                case FUTEX_OP_CMP_NE: ret = (oldval != cmparg); break;
-                case FUTEX_OP_CMP_LT: ret = (oldval < cmparg); break;
-                case FUTEX_OP_CMP_GE: ret = (oldval >= cmparg); break;
-                case FUTEX_OP_CMP_LE: ret = (oldval <= cmparg); break;
-                case FUTEX_OP_CMP_GT: ret = (oldval > cmparg); break;
-                default: ret = -ENOSYS;
-                }
-        }
-        return ret;
-}
-
-static inline int
-futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval, int newval)
-{
-        int retval;
-
-        if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
-                return -EFAULT;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "# futex_atomic_cmpxchg_inatomic                        \n"
-                "       .set    push                                    \n"
-                "       .set    noat                                    \n"
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %2                                  \n"
-                "       bne     %0, %z3, 3f                             \n"
-                "       .set    mips0                                   \n"
-                "       move    $1, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "2:     sc      $1, %1                                  \n"
-                "       beqzl   $1, 1b                                  \n"
-                __WEAK_LLSC_MB
-                "3:                                                     \n"
-                "       .set    pop                                     \n"
-                "       .section .fixup,\"ax\"                          \n"
-                "4:     li      %0, %5                                  \n"
-                "       j       3b                                      \n"
-                "       .previous                                       \n"
-                "       .section __ex_table,\"a\"                       \n"
-                "       "__UA_ADDR "\t1b, 4b                            \n"
-                "       "__UA_ADDR "\t2b, 4b                            \n"
-                "       .previous                                       \n"
-                : "=&r" (retval), "=R" (*uaddr)
-                : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                __asm__ __volatile__(
-                "# futex_atomic_cmpxchg_inatomic                        \n"
-                "       .set    push                                    \n"
-                "       .set    noat                                    \n"
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %2                                  \n"
-                "       bne     %0, %z3, 3f                             \n"
-                "       .set    mips0                                   \n"
-                "       move    $1, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "2:     sc      $1, %1                                  \n"
-                "       beqz    $1, 1b                                  \n"
-                __WEAK_LLSC_MB
-                "3:                                                     \n"
-                "       .set    pop                                     \n"
-                "       .section .fixup,\"ax\"                          \n"
-                "4:     li      %0, %5                                  \n"
-                "       j       3b                                      \n"
-                "       .previous                                       \n"
-                "       .section __ex_table,\"a\"                       \n"
-                "       "__UA_ADDR "\t1b, 4b                            \n"
-                "       "__UA_ADDR "\t2b, 4b                            \n"
-                "       .previous                                       \n"
-                : "=&r" (retval), "=R" (*uaddr)
-                : "R" (*uaddr), "Jr" (oldval), "Jr" (newval), "i" (-EFAULT)
-                : "memory");
-        } else
-                return -ENOSYS;
-
-        return retval;
-}
-
-#endif
-#endif /* _ASM_FUTEX_H */
diff --git a/include/asm-mips/fw/arc/hinv.h b/include/asm-mips/fw/arc/hinv.h
deleted file mode 100644
index e6ff4add04e2..000000000000
--- a/include/asm-mips/fw/arc/hinv.h
+++ /dev/null
@@ -1,175 +0,0 @@
-/*
- * ARCS hardware/memory inventory/configuration and system ID definitions.
- */
-#ifndef _ASM_ARC_HINV_H
-#define _ASM_ARC_HINV_H
-
-#include <asm/sgidefs.h>
-#include <asm/fw/arc/types.h>
-
-/* configuration query defines */
-typedef enum configclass {
-        SystemClass,
-        ProcessorClass,
-        CacheClass,
-#ifndef _NT_PROM
-        MemoryClass,
-        AdapterClass,
-        ControllerClass,
-        PeripheralClass
-#else   /* _NT_PROM */
-        AdapterClass,
-        ControllerClass,
-        PeripheralClass,
-        MemoryClass
-#endif  /* _NT_PROM */
-} CONFIGCLASS;
-
-typedef enum configtype {
-        ARC,
-        CPU,
-        FPU,
-        PrimaryICache,
-        PrimaryDCache,
-        SecondaryICache,
-        SecondaryDCache,
-        SecondaryCache,
-#ifndef _NT_PROM
-        Memory,
-#endif
-        EISAAdapter,
-        TCAdapter,
-        SCSIAdapter,
-        DTIAdapter,
-        MultiFunctionAdapter,
-        DiskController,
-        TapeController,
-        CDROMController,
-        WORMController,
-        SerialController,
-        NetworkController,
-        DisplayController,
-        ParallelController,
-        PointerController,
-        KeyboardController,
-        AudioController,
-        OtherController,
-        DiskPeripheral,
-        FloppyDiskPeripheral,
-        TapePeripheral,
-        ModemPeripheral,
-        MonitorPeripheral,
-        PrinterPeripheral,
-        PointerPeripheral,
-        KeyboardPeripheral,
-        TerminalPeripheral,
-        LinePeripheral,
-        NetworkPeripheral,
-#ifdef  _NT_PROM
-        Memory,
-#endif
-        OtherPeripheral,
-
-        /* new stuff for IP30 */
-        /* added without moving anything */
-        /* except ANONYMOUS. */
-
-        XTalkAdapter,
-        PCIAdapter,
-        GIOAdapter,
-        TPUAdapter,
-
-        Anonymous
-} CONFIGTYPE;
-
-typedef enum {
-        Failed = 1,
-        ReadOnly = 2,
-        Removable = 4,
-        ConsoleIn = 8,
-        ConsoleOut = 16,
-        Input = 32,
-        Output = 64
-} IDENTIFIERFLAG;
-
-#ifndef NULL                    /* for GetChild(NULL); */
-#define NULL    0
-#endif
-
-union key_u {
-        struct {
-#ifdef  _MIPSEB
-                unsigned char  c_bsize;         /* block size in lines */
-                unsigned char  c_lsize;         /* line size in bytes/tag */
-                unsigned short c_size;          /* cache size in 4K pages */
-#else   /* _MIPSEL */
-                unsigned short c_size;          /* cache size in 4K pages */
-                unsigned char  c_lsize;         /* line size in bytes/tag */
-                unsigned char  c_bsize;         /* block size in lines */
-#endif  /* _MIPSEL */
-        } cache;
-        ULONG FullKey;
-};
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64
-#define SGI_ARCS_VERS   64                      /* sgi 64-bit version */
-#define SGI_ARCS_REV    0                       /* rev .00 */
-#else
-#define SGI_ARCS_VERS   1                       /* first version */
-#define SGI_ARCS_REV    10                      /* rev .10, 3/04/92 */
-#endif
-
-typedef struct component {
-        CONFIGCLASS     Class;
-        CONFIGTYPE      Type;
-        IDENTIFIERFLAG  Flags;
-        USHORT          Version;
-        USHORT          Revision;
-        ULONG           Key;
-        ULONG           AffinityMask;
-        ULONG           ConfigurationDataSize;
-        ULONG           IdentifierLength;
-        char            *Identifier;
-} COMPONENT;
-
-/* internal structure that holds pathname parsing data */
-struct cfgdata {
-        char *name;                     /* full name */
-        int minlen;                     /* minimum length to match */
-        CONFIGTYPE type;                /* type of token */
-};
-
-/* System ID */
-typedef struct systemid {
-        CHAR VendorId[8];
-        CHAR ProductId[8];
-} SYSTEMID;
-
-/* memory query functions */
-typedef enum memorytype {
-        ExceptionBlock,
-        SPBPage,                        /* ARCS == SystemParameterBlock */
-#ifndef _NT_PROM
-        FreeContiguous,
-        FreeMemory,
-        BadMemory,
-        LoadedProgram,
-        FirmwareTemporary,
-        FirmwarePermanent
-#else   /* _NT_PROM */
-        FreeMemory,
-        BadMemory,
-        LoadedProgram,
-        FirmwareTemporary,
-        FirmwarePermanent,
-        FreeContiguous
-#endif  /* _NT_PROM */
-} MEMORYTYPE;
-
-typedef struct memorydescriptor {
-        MEMORYTYPE      Type;
-        LONG            BasePage;
-        LONG            PageCount;
-} MEMORYDESCRIPTOR;
-
-#endif /* _ASM_ARC_HINV_H */
diff --git a/include/asm-mips/fw/arc/types.h b/include/asm-mips/fw/arc/types.h
deleted file mode 100644
index b9adcd6f0860..000000000000
--- a/include/asm-mips/fw/arc/types.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright 1999 Ralf Baechle (ralf@gnu.org)
- * Copyright 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_ARC_TYPES_H
-#define _ASM_ARC_TYPES_H
-
-
-#ifdef CONFIG_ARC32
-
-typedef char            CHAR;
-typedef short           SHORT;
-typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
-typedef long            LONG __attribute__ ((__mode__ (__SI__)));
-typedef unsigned char   UCHAR;
-typedef unsigned short  USHORT;
-typedef unsigned long   ULONG __attribute__ ((__mode__ (__SI__)));
-typedef void            VOID;
-
-/* The pointer types.  Note that we're using a 64-bit compiler but all
-   pointer in the ARC structures are only 32-bit, so we need some disgusting
-   workarounds.  Keep your vomit bag handy.  */
-typedef LONG            _PCHAR;
-typedef LONG            _PSHORT;
-typedef LONG            _PLARGE_INTEGER;
-typedef LONG            _PLONG;
-typedef LONG            _PUCHAR;
-typedef LONG            _PUSHORT;
-typedef LONG            _PULONG;
-typedef LONG            _PVOID;
-
-#endif /* CONFIG_ARC32 */
-
-#ifdef CONFIG_ARC64
-
-typedef char            CHAR;
-typedef short           SHORT;
-typedef long            LARGE_INTEGER __attribute__ ((__mode__ (__DI__)));
-typedef long            LONG __attribute__ ((__mode__ (__DI__)));
-typedef unsigned char   UCHAR;
-typedef unsigned short  USHORT;
-typedef unsigned long   ULONG __attribute__ ((__mode__ (__DI__)));
-typedef void            VOID;
-
-/* The pointer types.  We're 64-bit and the firmware is also 64-bit, so
-   live is sane ...  */
-typedef CHAR            *_PCHAR;
-typedef SHORT           *_PSHORT;
-typedef LARGE_INTEGER   *_PLARGE_INTEGER;
-typedef LONG            *_PLONG;
-typedef UCHAR           *_PUCHAR;
-typedef USHORT          *_PUSHORT;
-typedef ULONG           *_PULONG;
-typedef VOID            *_PVOID;
-
-#endif /* CONFIG_ARC64  */
-
-typedef CHAR            *PCHAR;
-typedef SHORT           *PSHORT;
-typedef LARGE_INTEGER   *PLARGE_INTEGER;
-typedef LONG            *PLONG;
-typedef UCHAR           *PUCHAR;
-typedef USHORT          *PUSHORT;
-typedef ULONG           *PULONG;
-typedef VOID            *PVOID;
-
-/*
- * Return type of ArcGetDisplayStatus()
- */
-typedef struct {
-        USHORT  CursorXPosition;
-        USHORT  CursorYPosition;
-        USHORT  CursorMaxXPosition;
-        USHORT  CursorMaxYPosition;
-        USHORT  ForegroundColor;
-        USHORT  BackgroundColor;
-        UCHAR   HighIntensity;
-        UCHAR   Underscored;
-        UCHAR   ReverseVideo;
-} DISPLAY_STATUS;
-
-#endif /* _ASM_ARC_TYPES_H */
diff --git a/include/asm-mips/fw/cfe/cfe_api.h b/include/asm-mips/fw/cfe/cfe_api.h
deleted file mode 100644
index 0995575db320..000000000000
--- a/include/asm-mips/fw/cfe/cfe_api.h
+++ /dev/null
@@ -1,122 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-/*
- * Broadcom Common Firmware Environment (CFE)
- *
- * This file contains declarations for doing callbacks to
- * cfe from an application.  It should be the only header
- * needed by the application to use this library
- *
- * Authors:  Mitch Lichtenberg, Chris Demetriou
- */
-#ifndef CFE_API_H
-#define CFE_API_H
-
-#include <linux/types.h>
-#include <linux/string.h>
-
-typedef long intptr_t;
-
-
-/*
- * Constants
- */
-
-/* Seal indicating CFE's presence, passed to user program. */
-#define CFE_EPTSEAL 0x43464531
-
-#define CFE_MI_RESERVED 0       /* memory is reserved, do not use */
-#define CFE_MI_AVAILABLE 1      /* memory is available */
-
-#define CFE_FLG_WARMSTART     0x00000001
-#define CFE_FLG_FULL_ARENA    0x00000001
-#define CFE_FLG_ENV_PERMANENT 0x00000001
-
-#define CFE_CPU_CMD_START 1
-#define CFE_CPU_CMD_STOP 0
-
-#define CFE_STDHANDLE_CONSOLE   0
-
-#define CFE_DEV_NETWORK         1
-#define CFE_DEV_DISK            2
-#define CFE_DEV_FLASH           3
-#define CFE_DEV_SERIAL          4
-#define CFE_DEV_CPU             5
-#define CFE_DEV_NVRAM           6
-#define CFE_DEV_CLOCK           7
-#define CFE_DEV_OTHER           8
-#define CFE_DEV_MASK            0x0F
-
-#define CFE_CACHE_FLUSH_D       1
-#define CFE_CACHE_INVAL_I       2
-#define CFE_CACHE_INVAL_D       4
-#define CFE_CACHE_INVAL_L2      8
-
-#define CFE_FWI_64BIT           0x00000001
-#define CFE_FWI_32BIT           0x00000002
-#define CFE_FWI_RELOC           0x00000004
-#define CFE_FWI_UNCACHED        0x00000008
-#define CFE_FWI_MULTICPU        0x00000010
-#define CFE_FWI_FUNCSIM         0x00000020
-#define CFE_FWI_RTLSIM          0x00000040
-
-typedef struct {
-        int64_t fwi_version;            /* major, minor, eco version */
-        int64_t fwi_totalmem;           /* total installed mem */
-        int64_t fwi_flags;              /* various flags */
-        int64_t fwi_boardid;            /* board ID */
-        int64_t fwi_bootarea_va;        /* VA of boot area */
-        int64_t fwi_bootarea_pa;        /* PA of boot area */
-        int64_t fwi_bootarea_size;      /* size of boot area */
-} cfe_fwinfo_t;
-
-
-/*
- * Defines and prototypes for functions which take no arguments.
- */
-int64_t cfe_getticks(void);
-
-/*
- * Defines and prototypes for the rest of the functions.
- */
-int cfe_close(int handle);
-int cfe_cpu_start(int cpu, void (*fn) (void), long sp, long gp, long a1);
-int cfe_cpu_stop(int cpu);
-int cfe_enumenv(int idx, char *name, int namelen, char *val, int vallen);
-int cfe_enummem(int idx, int flags, uint64_t * start, uint64_t * length,
-                uint64_t * type);
-int cfe_exit(int warm, int status);
-int cfe_flushcache(int flg);
-int cfe_getdevinfo(char *name);
-int cfe_getenv(char *name, char *dest, int destlen);
-int cfe_getfwinfo(cfe_fwinfo_t * info);
-int cfe_getstdhandle(int flg);
-int cfe_init(uint64_t handle, uint64_t ept);
-int cfe_inpstat(int handle);
-int cfe_ioctl(int handle, unsigned int ioctlnum, unsigned char *buffer,
-              int length, int *retlen, uint64_t offset);
-int cfe_open(char *name);
-int cfe_read(int handle, unsigned char *buffer, int length);
-int cfe_readblk(int handle, int64_t offset, unsigned char *buffer,
-                int length);
-int cfe_setenv(char *name, char *val);
-int cfe_write(int handle, unsigned char *buffer, int length);
-int cfe_writeblk(int handle, int64_t offset, unsigned char *buffer,
-                 int length);
-
-#endif                          /* CFE_API_H */
diff --git a/include/asm-mips/fw/cfe/cfe_error.h b/include/asm-mips/fw/cfe/cfe_error.h
deleted file mode 100644
index b80374636279..000000000000
--- a/include/asm-mips/fw/cfe/cfe_error.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-/*
- * Broadcom Common Firmware Environment (CFE)
- *
- * CFE's global error code list is here.
- *
- * Author:  Mitch Lichtenberg
- */
-
-#define CFE_OK                   0
-#define CFE_ERR                 -1      /* generic error */
-#define CFE_ERR_INV_COMMAND     -2
-#define CFE_ERR_EOF             -3
-#define CFE_ERR_IOERR           -4
-#define CFE_ERR_NOMEM           -5
-#define CFE_ERR_DEVNOTFOUND     -6
-#define CFE_ERR_DEVOPEN         -7
-#define CFE_ERR_INV_PARAM       -8
-#define CFE_ERR_ENVNOTFOUND     -9
-#define CFE_ERR_ENVREADONLY     -10
-
-#define CFE_ERR_NOTELF          -11
-#define CFE_ERR_NOT32BIT        -12
-#define CFE_ERR_WRONGENDIAN     -13
-#define CFE_ERR_BADELFVERS      -14
-#define CFE_ERR_NOTMIPS         -15
-#define CFE_ERR_BADELFFMT       -16
-#define CFE_ERR_BADADDR         -17
-
-#define CFE_ERR_FILENOTFOUND    -18
-#define CFE_ERR_UNSUPPORTED     -19
-
-#define CFE_ERR_HOSTUNKNOWN     -20
-
-#define CFE_ERR_TIMEOUT         -21
-
-#define CFE_ERR_PROTOCOLERR     -22
-
-#define CFE_ERR_NETDOWN         -23
-#define CFE_ERR_NONAMESERVER    -24
-
-#define CFE_ERR_NOHANDLES       -25
-#define CFE_ERR_ALREADYBOUND    -26
-
-#define CFE_ERR_CANNOTSET       -27
-#define CFE_ERR_NOMORE          -28
-#define CFE_ERR_BADFILESYS      -29
-#define CFE_ERR_FSNOTAVAIL      -30
-
-#define CFE_ERR_INVBOOTBLOCK    -31
-#define CFE_ERR_WRONGDEVTYPE    -32
-#define CFE_ERR_BBCHECKSUM      -33
-#define CFE_ERR_BOOTPROGCHKSUM  -34
-
-#define CFE_ERR_LDRNOTAVAIL     -35
-
-#define CFE_ERR_NOTREADY        -36
-
-#define CFE_ERR_GETMEM          -37
-#define CFE_ERR_SETMEM          -38
-
-#define CFE_ERR_NOTCONN         -39
-#define CFE_ERR_ADDRINUSE       -40
diff --git a/include/asm-mips/gcmpregs.h b/include/asm-mips/gcmpregs.h
deleted file mode 100644
index d74a8a4ca861..000000000000
--- a/include/asm-mips/gcmpregs.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- *
- * Multiprocessor Subsystem Register Definitions
- *
- */
-#ifndef _ASM_GCMPREGS_H
-#define _ASM_GCMPREGS_H
-
-
-/* Offsets to major blocks within GCMP from GCMP base */
-#define GCMP_GCB_OFS            0x0000 /* Global Control Block */
-#define GCMP_CLCB_OFS           0x2000 /* Core Local Control Block */
-#define GCMP_COCB_OFS           0x4000 /* Core Other Control Block */
-#define GCMP_GDB_OFS            0x8000 /* Global Debug Block */
-
-/* Offsets to individual GCMP registers from GCMP base */
-#define GCMPOFS(block, tag, reg)        (GCMP_##block##_OFS + GCMP_##tag##_##reg##_OFS)
-
-#define GCMPGCBOFS(reg)         GCMPOFS(GCB, GCB, reg)
-#define GCMPCLCBOFS(reg)        GCMPOFS(CLCB, CCB, reg)
-#define GCMPCOCBOFS(reg)        GCMPOFS(COCB, CCB, reg)
-#define GCMPGDBOFS(reg)         GCMPOFS(GDB, GDB, reg)
-
-/* GCMP register access */
-#define GCMPGCB(reg)                    REGP(_gcmp_base, GCMPGCBOFS(reg))
-#define GCMPCLCB(reg)                   REGP(_gcmp_base, GCMPCLCBOFS(reg))
-#define GCMPCOCB(reg)                   REGP(_gcmp_base, GCMPCOCBOFS(reg))
-#define GCMPGDB(reg)                    REGP(_gcmp_base, GCMPGDBOFS(reg))
-
-/* Mask generation */
-#define GCMPMSK(block, reg, bits)       (MSK(bits)<<GCMP_##block##_##reg##_SHF)
-#define GCMPGCBMSK(reg, bits)           GCMPMSK(GCB, reg, bits)
-#define GCMPCCBMSK(reg, bits)           GCMPMSK(CCB, reg, bits)
-#define GCMPGDBMSK(reg, bits)           GCMPMSK(GDB, reg, bits)
-
-/* GCB registers */
-#define GCMP_GCB_GC_OFS                 0x0000  /* Global Config Register */
-#define  GCMP_GCB_GC_NUMIOCU_SHF        8
-#define  GCMP_GCB_GC_NUMIOCU_MSK        GCMPGCBMSK(GC_NUMIOCU, 4)
-#define  GCMP_GCB_GC_NUMCORES_SHF       0
-#define  GCMP_GCB_GC_NUMCORES_MSK       GCMPGCBMSK(GC_NUMCORES, 8)
-#define GCMP_GCB_GCMPB_OFS              0x0008          /* Global GCMP Base */
-#define  GCMP_GCB_GCMPB_GCMPBASE_SHF    15
-#define  GCMP_GCB_GCMPB_GCMPBASE_MSK    GCMPGCBMSK(GCMPB_GCMPBASE, 17)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_SHF    0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MSK    GCMPGCBMSK(GCMPB_CMDEFTGT, 2)
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM    0
-#define  GCMP_GCB_GCMPB_CMDEFTGT_MEM1   1
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU1 2
-#define  GCMP_GCB_GCMPB_CMDEFTGT_IOCU2 3
-#define GCMP_GCB_CCMC_OFS               0x0010  /* Global CM Control */
-#define GCMP_GCB_GCSRAP_OFS             0x0020  /* Global CSR Access Privilege */
-#define  GCMP_GCB_GCSRAP_CMACCESS_SHF   0
-#define  GCMP_GCB_GCSRAP_CMACCESS_MSK   GCMPGCBMSK(GCSRAP_CMACCESS, 8)
-#define GCMP_GCB_GCMPREV_OFS            0x0030  /* GCMP Revision Register */
-#define GCMP_GCB_GCMEM_OFS              0x0040  /* Global CM Error Mask */
-#define GCMP_GCB_GCMEC_OFS              0x0048  /* Global CM Error Cause */
-#define  GCMP_GCB_GMEC_ERROR_TYPE_SHF   27
-#define  GCMP_GCB_GMEC_ERROR_TYPE_MSK   GCMPGCBMSK(GMEC_ERROR_TYPE, 5)
-#define  GCMP_GCB_GMEC_ERROR_INFO_SHF   0
-#define  GCMP_GCB_GMEC_ERROR_INFO_MSK   GCMPGCBMSK(GMEC_ERROR_INFO, 27)
-#define GCMP_GCB_GCMEA_OFS              0x0050  /* Global CM Error Address */
-#define GCMP_GCB_GCMEO_OFS              0x0058  /* Global CM Error Multiple */
-#define  GCMP_GCB_GMEO_ERROR_2ND_SHF    0
-#define  GCMP_GCB_GMEO_ERROR_2ND_MSK    GCMPGCBMSK(GMEO_ERROR_2ND, 5)
-#define GCMP_GCB_GICBA_OFS              0x0080  /* Global Interrupt Controller Base Address */
-#define  GCMP_GCB_GICBA_BASE_SHF        17
-#define  GCMP_GCB_GICBA_BASE_MSK        GCMPGCBMSK(GICBA_BASE, 15)
-#define  GCMP_GCB_GICBA_EN_SHF          0
-#define  GCMP_GCB_GICBA_EN_MSK          GCMPGCBMSK(GICBA_EN, 1)
-
-/* GCB Regions */
-#define GCMP_GCB_CMxBASE_OFS(n)         (0x0090+16*(n))         /* Global Region[0-3] Base Address */
-#define  GCMP_GCB_CMxBASE_BASE_SHF      16
-#define  GCMP_GCB_CMxBASE_BASE_MSK      GCMPGCBMSK(CMxBASE_BASE, 16)
-#define GCMP_GCB_CMxMASK_OFS(n)         (0x0098+16*(n))         /* Global Region[0-3] Address Mask */
-#define  GCMP_GCB_CMxMASK_MASK_SHF      16
-#define  GCMP_GCB_CMxMASK_MASK_MSK      GCMPGCBMSK(CMxMASK_MASK, 16)
-#define  GCMP_GCB_CMxMASK_CMREGTGT_SHF  0
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MSK  GCMPGCBMSK(CMxMASK_CMREGTGT, 2)
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM   0
-#define  GCMP_GCB_CMxMASK_CMREGTGT_MEM1  1
-#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU1 2
-#define  GCMP_GCB_CMxMASK_CMREGTGT_IOCU2 3
-
-
-/* Core local/Core other control block registers */
-#define GCMP_CCB_RESETR_OFS             0x0000                  /* Reset Release */
-#define  GCMP_CCB_RESETR_INRESET_SHF    0
-#define  GCMP_CCB_RESETR_INRESET_MSK    GCMPCCBMSK(RESETR_INRESET, 16)
-#define GCMP_CCB_COHCTL_OFS             0x0008                  /* Coherence Control */
-#define  GCMP_CCB_COHCTL_DOMAIN_SHF     0
-#define  GCMP_CCB_COHCTL_DOMAIN_MSK     GCMPCCBMSK(COHCTL_DOMAIN, 8)
-#define GCMP_CCB_CFG_OFS                0x0010                  /* Config */
-#define  GCMP_CCB_CFG_IOCUTYPE_SHF      10
-#define  GCMP_CCB_CFG_IOCUTYPE_MSK      GCMPCCBMSK(CFG_IOCUTYPE, 2)
-#define   GCMP_CCB_CFG_IOCUTYPE_CPU     0
-#define   GCMP_CCB_CFG_IOCUTYPE_NCIOCU  1
-#define   GCMP_CCB_CFG_IOCUTYPE_CIOCU   2
-#define  GCMP_CCB_CFG_NUMVPE_SHF        0
-#define  GCMP_CCB_CFG_NUMVPE_MSK        GCMPCCBMSK(CFG_NUMVPE, 10)
-#define GCMP_CCB_OTHER_OFS              0x0018          /* Other Address */
-#define  GCMP_CCB_OTHER_CORENUM_SHF     16
-#define  GCMP_CCB_OTHER_CORENUM_MSK     GCMPCCBMSK(OTHER_CORENUM, 16)
-#define GCMP_CCB_RESETBASE_OFS          0x0020          /* Reset Exception Base */
-#define  GCMP_CCB_RESETBASE_BEV_SHF     12
-#define  GCMP_CCB_RESETBASE_BEV_MSK     GCMPCCBMSK(RESETBASE_BEV, 20)
-#define GCMP_CCB_ID_OFS                 0x0028          /* Identification */
-#define GCMP_CCB_DINTGROUP_OFS          0x0030          /* DINT Group Participate */
-#define GCMP_CCB_DBGGROUP_OFS           0x0100          /* DebugBreak Group */
-
-#endif /* _ASM_GCMPREGS_H */
diff --git a/include/asm-mips/gic.h b/include/asm-mips/gic.h
deleted file mode 100644
index 954807d9d66a..000000000000
--- a/include/asm-mips/gic.h
+++ /dev/null
@@ -1,487 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- *
- * GIC Register Definitions
- *
- */
-#ifndef _ASM_GICREGS_H
-#define _ASM_GICREGS_H
-
-#undef  GICISBYTELITTLEENDIAN
-#define GICISWORDLITTLEENDIAN
-
-/* Constants */
-#define GIC_POL_POS                     1
-#define GIC_POL_NEG                     0
-#define GIC_TRIG_EDGE                   1
-#define GIC_TRIG_LEVEL                  0
-
-#define GIC_NUM_INTRS                   32
-
-#define MSK(n) ((1 << (n)) - 1)
-#define REG32(addr)             (*(volatile unsigned int *) (addr))
-#define REG(base, offs)         REG32((unsigned long)(base) + offs##_##OFS)
-#define REGP(base, phys)        REG32((unsigned long)(base) + (phys))
-
-/* Accessors */
-#define GIC_REG(segment, offset) \
-        REG32(_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
-#define GIC_REG_ADDR(segment, offset) \
-        REG32(_gic_base + segment##_##SECTION_OFS + offset)
-
-#define GIC_ABS_REG(segment, offset) \
-       (_gic_base + segment##_##SECTION_OFS + offset##_##OFS)
-#define GIC_REG_ABS_ADDR(segment, offset) \
-       (_gic_base + segment##_##SECTION_OFS + offset)
-
-#ifdef GICISBYTELITTLEENDIAN
-#define GICREAD(reg, data)      (data) = (reg), (data) = le32_to_cpu(data)
-#define GICWRITE(reg, data)     (reg) = cpu_to_le32(data)
-#define GICBIS(reg, bits)                       \
-        ({unsigned int data;                    \
-                GICREAD(reg, data);             \
-                data |= bits;                   \
-                GICWRITE(reg, data);            \
-        })
-
-#else
-#define GICREAD(reg, data)      (data) = (reg)
-#define GICWRITE(reg, data)     (reg) = (data)
-#define GICBIS(reg, bits)       (reg) |= (bits)
-#endif
-
-
-/* GIC Address Space */
-#define SHARED_SECTION_OFS              0x0000
-#define SHARED_SECTION_SIZE             0x8000
-#define VPE_LOCAL_SECTION_OFS           0x8000
-#define VPE_LOCAL_SECTION_SIZE          0x4000
-#define VPE_OTHER_SECTION_OFS           0xc000
-#define VPE_OTHER_SECTION_SIZE          0x4000
-#define USM_VISIBLE_SECTION_OFS         0x10000
-#define USM_VISIBLE_SECTION_SIZE        0x10000
-
-/* Register Map for Shared Section */
-#if defined(CONFIG_CPU_LITTLE_ENDIAN) || defined(GICISWORDLITTLEENDIAN)
-
-#define GIC_SH_CONFIG_OFS               0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTER_31_00_OFS        0x0010
-#define GIC_SH_COUNTER_63_32_OFS        0x0014
-
-/* Interrupt Polarity */
-#define GIC_SH_POL_31_0_OFS             0x0100
-#define GIC_SH_POL_63_32_OFS            0x0104
-#define GIC_SH_POL_95_64_OFS            0x0108
-#define GIC_SH_POL_127_96_OFS           0x010c
-#define GIC_SH_POL_159_128_OFS          0x0110
-#define GIC_SH_POL_191_160_OFS          0x0114
-#define GIC_SH_POL_223_192_OFS          0x0118
-#define GIC_SH_POL_255_224_OFS          0x011c
-
-/* Edge/Level Triggering */
-#define GIC_SH_TRIG_31_0_OFS            0x0180
-#define GIC_SH_TRIG_63_32_OFS           0x0184
-#define GIC_SH_TRIG_95_64_OFS           0x0188
-#define GIC_SH_TRIG_127_96_OFS          0x018c
-#define GIC_SH_TRIG_159_128_OFS         0x0190
-#define GIC_SH_TRIG_191_160_OFS         0x0194
-#define GIC_SH_TRIG_223_192_OFS         0x0198
-#define GIC_SH_TRIG_255_224_OFS         0x019c
-
-/* Dual Edge Triggering */
-#define GIC_SH_DUAL_31_0_OFS            0x0200
-#define GIC_SH_DUAL_63_32_OFS           0x0204
-#define GIC_SH_DUAL_95_64_OFS           0x0208
-#define GIC_SH_DUAL_127_96_OFS          0x020c
-#define GIC_SH_DUAL_159_128_OFS         0x0210
-#define GIC_SH_DUAL_191_160_OFS         0x0214
-#define GIC_SH_DUAL_223_192_OFS         0x0218
-#define GIC_SH_DUAL_255_224_OFS         0x021c
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS                0x0280
-
-/* Reset Mask - Disables Interrupt */
-#define GIC_SH_RMASK_31_0_OFS           0x0300
-#define GIC_SH_RMASK_63_32_OFS          0x0304
-#define GIC_SH_RMASK_95_64_OFS          0x0308
-#define GIC_SH_RMASK_127_96_OFS         0x030c
-#define GIC_SH_RMASK_159_128_OFS        0x0310
-#define GIC_SH_RMASK_191_160_OFS        0x0314
-#define GIC_SH_RMASK_223_192_OFS        0x0318
-#define GIC_SH_RMASK_255_224_OFS        0x031c
-
-/* Set Mask (WO) - Enables Interrupt */
-#define GIC_SH_SMASK_31_0_OFS           0x0380
-#define GIC_SH_SMASK_63_32_OFS          0x0384
-#define GIC_SH_SMASK_95_64_OFS          0x0388
-#define GIC_SH_SMASK_127_96_OFS         0x038c
-#define GIC_SH_SMASK_159_128_OFS        0x0390
-#define GIC_SH_SMASK_191_160_OFS        0x0394
-#define GIC_SH_SMASK_223_192_OFS        0x0398
-#define GIC_SH_SMASK_255_224_OFS        0x039c
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_31_0_OFS            0x0400
-#define GIC_SH_MASK_63_32_OFS           0x0404
-#define GIC_SH_MASK_95_64_OFS           0x0408
-#define GIC_SH_MASK_127_96_OFS          0x040c
-#define GIC_SH_MASK_159_128_OFS         0x0410
-#define GIC_SH_MASK_191_160_OFS         0x0414
-#define GIC_SH_MASK_223_192_OFS         0x0418
-#define GIC_SH_MASK_255_224_OFS         0x041c
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_31_0_OFS            0x0480
-#define GIC_SH_PEND_63_32_OFS           0x0484
-#define GIC_SH_PEND_95_64_OFS           0x0488
-#define GIC_SH_PEND_127_96_OFS          0x048c
-#define GIC_SH_PEND_159_128_OFS         0x0490
-#define GIC_SH_PEND_191_160_OFS         0x0494
-#define GIC_SH_PEND_223_192_OFS         0x0498
-#define GIC_SH_PEND_255_224_OFS         0x049c
-
-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
-
-/* Maps Interrupt X to a Pin */
-#define GIC_SH_MAP_TO_PIN(intr) \
-        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
-
-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2000
-
-/* Maps Interrupt X to a VPE */
-#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
-        (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + (((vpe) / 32) * 4))
-#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
-
-/* Polarity : Reset Value is always 0 */
-#define GIC_SH_SET_POLARITY_OFS         0x0100
-#define GIC_SET_POLARITY(intr, pol) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + (((intr) / 32) * 4)), (pol) << ((intr) % 32))
-
-/* Triggering : Reset Value is always 0 */
-#define GIC_SH_SET_TRIGGER_OFS          0x0180
-#define GIC_SET_TRIGGER(intr, trig) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + (((intr) / 32) * 4)), (trig) << ((intr) % 32))
-
-/* Mask manipulation */
-#define GIC_SH_SMASK_OFS                0x0380
-#define GIC_SET_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
-
-#define GIC_SH_RMASK_OFS                0x0300
-#define GIC_CLR_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + (((intr) / 32) * 4)), ((val) << ((intr) % 32)))
-
-/* Register Map for Local Section */
-#define GIC_VPE_CTL_OFS                 0x0000
-#define GIC_VPE_PEND_OFS                0x0004
-#define GIC_VPE_MASK_OFS                0x0008
-#define GIC_VPE_RMASK_OFS               0x000c
-#define GIC_VPE_SMASK_OFS               0x0010
-#define GIC_VPE_WD_MAP_OFS              0x0040
-#define GIC_VPE_COMPARE_MAP_OFS         0x0044
-#define GIC_VPE_TIMER_MAP_OFS           0x0048
-#define GIC_VPE_PERFCTR_MAP_OFS         0x0050
-#define GIC_VPE_SWINT0_MAP_OFS          0x0054
-#define GIC_VPE_SWINT1_MAP_OFS          0x0058
-#define GIC_VPE_OTHER_ADDR_OFS          0x0080
-#define GIC_VPE_WD_CONFIG0_OFS          0x0090
-#define GIC_VPE_WD_COUNT0_OFS           0x0094
-#define GIC_VPE_WD_INITIAL0_OFS         0x0098
-#define GIC_VPE_COMPARE_LO_OFS          0x00a0
-#define GIC_VPE_COMPARE_HI              0x00a4
-
-#define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
-#define GIC_VPE_EIC_SS(intr) \
-        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
-
-#define GIC_VPE_EIC_VEC_BASE            0x0800
-#define GIC_VPE_EIC_VEC(intr) \
-        (GIC_VPE_EIC_VEC_BASE + (4 * intr))
-
-#define GIC_VPE_TENABLE_NMI_OFS         0x1000
-#define GIC_VPE_TENABLE_YQ_OFS          0x1004
-#define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
-#define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
-
-/* User Mode Visible Section Register Map */
-#define GIC_UMV_SH_COUNTER_31_00_OFS    0x0000
-#define GIC_UMV_SH_COUNTER_63_32_OFS    0x0004
-
-#else /* CONFIG_CPU_BIG_ENDIAN */
-
-#define GIC_SH_CONFIG_OFS               0x0000
-
-/* Shared Global Counter */
-#define GIC_SH_COUNTER_31_00_OFS        0x0014
-#define GIC_SH_COUNTER_63_32_OFS        0x0010
-
-/* Interrupt Polarity */
-#define GIC_SH_POL_31_0_OFS             0x0104
-#define GIC_SH_POL_63_32_OFS            0x0100
-#define GIC_SH_POL_95_64_OFS            0x010c
-#define GIC_SH_POL_127_96_OFS           0x0108
-#define GIC_SH_POL_159_128_OFS          0x0114
-#define GIC_SH_POL_191_160_OFS          0x0110
-#define GIC_SH_POL_223_192_OFS          0x011c
-#define GIC_SH_POL_255_224_OFS          0x0118
-
-/* Edge/Level Triggering */
-#define GIC_SH_TRIG_31_0_OFS            0x0184
-#define GIC_SH_TRIG_63_32_OFS           0x0180
-#define GIC_SH_TRIG_95_64_OFS           0x018c
-#define GIC_SH_TRIG_127_96_OFS          0x0188
-#define GIC_SH_TRIG_159_128_OFS         0x0194
-#define GIC_SH_TRIG_191_160_OFS         0x0190
-#define GIC_SH_TRIG_223_192_OFS         0x019c
-#define GIC_SH_TRIG_255_224_OFS         0x0198
-
-/* Dual Edge Triggering */
-#define GIC_SH_DUAL_31_0_OFS            0x0204
-#define GIC_SH_DUAL_63_32_OFS           0x0200
-#define GIC_SH_DUAL_95_64_OFS           0x020c
-#define GIC_SH_DUAL_127_96_OFS          0x0208
-#define GIC_SH_DUAL_159_128_OFS         0x0214
-#define GIC_SH_DUAL_191_160_OFS         0x0210
-#define GIC_SH_DUAL_223_192_OFS         0x021c
-#define GIC_SH_DUAL_255_224_OFS         0x0218
-
-/* Set/Clear corresponding bit in Edge Detect Register */
-#define GIC_SH_WEDGE_OFS                0x0280
-
-/* Reset Mask - Disables Interrupt */
-#define GIC_SH_RMASK_31_0_OFS           0x0304
-#define GIC_SH_RMASK_63_32_OFS          0x0300
-#define GIC_SH_RMASK_95_64_OFS          0x030c
-#define GIC_SH_RMASK_127_96_OFS         0x0308
-#define GIC_SH_RMASK_159_128_OFS        0x0314
-#define GIC_SH_RMASK_191_160_OFS        0x0310
-#define GIC_SH_RMASK_223_192_OFS        0x031c
-#define GIC_SH_RMASK_255_224_OFS        0x0318
-
-/* Set Mask (WO) - Enables Interrupt */
-#define GIC_SH_SMASK_31_0_OFS           0x0384
-#define GIC_SH_SMASK_63_32_OFS          0x0380
-#define GIC_SH_SMASK_95_64_OFS          0x038c
-#define GIC_SH_SMASK_127_96_OFS         0x0388
-#define GIC_SH_SMASK_159_128_OFS        0x0394
-#define GIC_SH_SMASK_191_160_OFS        0x0390
-#define GIC_SH_SMASK_223_192_OFS        0x039c
-#define GIC_SH_SMASK_255_224_OFS        0x0398
-
-/* Global Interrupt Mask Register (RO) - Bit Set == Interrupt enabled */
-#define GIC_SH_MASK_31_0_OFS            0x0404
-#define GIC_SH_MASK_63_32_OFS           0x0400
-#define GIC_SH_MASK_95_64_OFS           0x040c
-#define GIC_SH_MASK_127_96_OFS          0x0408
-#define GIC_SH_MASK_159_128_OFS         0x0414
-#define GIC_SH_MASK_191_160_OFS         0x0410
-#define GIC_SH_MASK_223_192_OFS         0x041c
-#define GIC_SH_MASK_255_224_OFS         0x0418
-
-/* Pending Global Interrupts (RO) */
-#define GIC_SH_PEND_31_0_OFS            0x0484
-#define GIC_SH_PEND_63_32_OFS           0x0480
-#define GIC_SH_PEND_95_64_OFS           0x048c
-#define GIC_SH_PEND_127_96_OFS          0x0488
-#define GIC_SH_PEND_159_128_OFS         0x0494
-#define GIC_SH_PEND_191_160_OFS         0x0490
-#define GIC_SH_PEND_223_192_OFS         0x049c
-#define GIC_SH_PEND_255_224_OFS         0x0498
-
-#define GIC_SH_INTR_MAP_TO_PIN_BASE_OFS 0x0500
-
-/* Maps Interrupt X to a Pin */
-#define GIC_SH_MAP_TO_PIN(intr) \
-        (GIC_SH_INTR_MAP_TO_PIN_BASE_OFS + (4 * intr))
-
-#define GIC_SH_INTR_MAP_TO_VPE_BASE_OFS 0x2004
-
-/*
- * Maps Interrupt X to a VPE.  This is more complex than the LE case, as
- * odd and even registers need to be transposed.  It does work - trust me!
- */
-#define GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe) \
-        (GIC_SH_INTR_MAP_TO_VPE_BASE_OFS + (32 * (intr)) + \
-        (((((vpe) / 32) ^ 1) - 1) * 4))
-#define GIC_SH_MAP_TO_VPE_REG_BIT(vpe)  (1 << ((vpe) % 32))
-
-/* Polarity */
-#define GIC_SH_SET_POLARITY_OFS         0x0100
-#define GIC_SET_POLARITY(intr, pol) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_POLARITY_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (pol) << ((intr) % 32))
-
-/* Triggering */
-#define GIC_SH_SET_TRIGGER_OFS          0x0180
-#define GIC_SET_TRIGGER(intr, trig) \
-        GICBIS(GIC_REG_ADDR(SHARED, GIC_SH_SET_TRIGGER_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), (trig) << ((intr) % 32))
-
-/* Mask manipulation */
-#define GIC_SH_SMASK_OFS                0x0380
-#define GIC_SET_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_SMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
-
-#define GIC_SH_RMASK_OFS                0x0300
-#define GIC_CLR_INTR_MASK(intr, val) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_RMASK_OFS + 4 + (((((intr) / 32) ^ 1) - 1) * 4)), ((val) << ((intr) % 32)))
-
-/* Register Map for Local Section */
-#define GIC_VPE_CTL_OFS                 0x0000
-#define GIC_VPE_PEND_OFS                0x0004
-#define GIC_VPE_MASK_OFS                0x0008
-#define GIC_VPE_RMASK_OFS               0x000c
-#define GIC_VPE_SMASK_OFS               0x0010
-#define GIC_VPE_WD_MAP_OFS              0x0040
-#define GIC_VPE_COMPARE_MAP_OFS         0x0044
-#define GIC_VPE_TIMER_MAP_OFS           0x0048
-#define GIC_VPE_PERFCTR_MAP_OFS         0x0050
-#define GIC_VPE_SWINT0_MAP_OFS          0x0054
-#define GIC_VPE_SWINT1_MAP_OFS          0x0058
-#define GIC_VPE_OTHER_ADDR_OFS          0x0080
-#define GIC_VPE_WD_CONFIG0_OFS          0x0090
-#define GIC_VPE_WD_COUNT0_OFS           0x0094
-#define GIC_VPE_WD_INITIAL0_OFS         0x0098
-#define GIC_VPE_COMPARE_LO_OFS          0x00a4
-#define GIC_VPE_COMPARE_HI_OFS          0x00a0
-
-#define GIC_VPE_EIC_SHADOW_SET_BASE     0x0100
-#define GIC_VPE_EIC_SS(intr) \
-        (GIC_EIC_SHADOW_SET_BASE + (4 * intr))
-
-#define GIC_VPE_EIC_VEC_BASE            0x0800
-#define GIC_VPE_EIC_VEC(intr) \
-        (GIC_VPE_EIC_VEC_BASE + (4 * intr))
-
-#define GIC_VPE_TENABLE_NMI_OFS         0x1000
-#define GIC_VPE_TENABLE_YQ_OFS          0x1004
-#define GIC_VPE_TENABLE_INT_31_0_OFS    0x1080
-#define GIC_VPE_TENABLE_INT_63_32_OFS   0x1084
-
-/* User Mode Visible Section Register Map */
-#define GIC_UMV_SH_COUNTER_31_00_OFS    0x0004
-#define GIC_UMV_SH_COUNTER_63_32_OFS    0x0000
-
-#endif /* !LE */
-
-/* Masks */
-#define GIC_SH_CONFIG_COUNTSTOP_SHF     28
-#define GIC_SH_CONFIG_COUNTSTOP_MSK     (MSK(1) << GIC_SH_CONFIG_COUNTSTOP_SHF)
-
-#define GIC_SH_CONFIG_COUNTBITS_SHF     24
-#define GIC_SH_CONFIG_COUNTBITS_MSK     (MSK(4) << GIC_SH_CONFIG_COUNTBITS_SHF)
-
-#define GIC_SH_CONFIG_NUMINTRS_SHF      16
-#define GIC_SH_CONFIG_NUMINTRS_MSK      (MSK(8) << GIC_SH_CONFIG_NUMINTRS_SHF)
-
-#define GIC_SH_CONFIG_NUMVPES_SHF       0
-#define GIC_SH_CONFIG_NUMVPES_MSK       (MSK(8) << GIC_SH_CONFIG_NUMVPES_SHF)
-
-#define GIC_SH_WEDGE_SET(intr)          (intr | (0x1 << 31))
-#define GIC_SH_WEDGE_CLR(intr)          (intr & ~(0x1 << 31))
-
-#define GIC_MAP_TO_PIN_SHF              31
-#define GIC_MAP_TO_PIN_MSK              (MSK(1) << GIC_MAP_TO_PIN_SHF)
-#define GIC_MAP_TO_NMI_SHF              30
-#define GIC_MAP_TO_NMI_MSK              (MSK(1) << GIC_MAP_TO_NMI_SHF)
-#define GIC_MAP_TO_YQ_SHF               29
-#define GIC_MAP_TO_YQ_MSK               (MSK(1) << GIC_MAP_TO_YQ_SHF)
-#define GIC_MAP_SHF                     0
-#define GIC_MAP_MSK                     (MSK(6) << GIC_MAP_SHF)
-
-/* GIC_VPE_CTL Masks */
-#define GIC_VPE_CTL_PERFCNT_RTBL_SHF    2
-#define GIC_VPE_CTL_PERFCNT_RTBL_MSK    (MSK(1) << GIC_VPE_CTL_PERFCNT_RTBL_SHF)
-#define GIC_VPE_CTL_TIMER_RTBL_SHF      1
-#define GIC_VPE_CTL_TIMER_RTBL_MSK      (MSK(1) << GIC_VPE_CTL_TIMER_RTBL_SHF)
-#define GIC_VPE_CTL_EIC_MODE_SHF        0
-#define GIC_VPE_CTL_EIC_MODE_MSK        (MSK(1) << GIC_VPE_CTL_EIC_MODE_SHF)
-
-/* GIC_VPE_PEND Masks */
-#define GIC_VPE_PEND_WD_SHF             0
-#define GIC_VPE_PEND_WD_MSK             (MSK(1) << GIC_VPE_PEND_WD_SHF)
-#define GIC_VPE_PEND_CMP_SHF            1
-#define GIC_VPE_PEND_CMP_MSK            (MSK(1) << GIC_VPE_PEND_CMP_SHF)
-#define GIC_VPE_PEND_TIMER_SHF          2
-#define GIC_VPE_PEND_TIMER_MSK          (MSK(1) << GIC_VPE_PEND_TIMER_SHF)
-#define GIC_VPE_PEND_PERFCOUNT_SHF      3
-#define GIC_VPE_PEND_PERFCOUNT_MSK      (MSK(1) << GIC_VPE_PEND_PERFCOUNT_SHF)
-#define GIC_VPE_PEND_SWINT0_SHF         4
-#define GIC_VPE_PEND_SWINT0_MSK         (MSK(1) << GIC_VPE_PEND_SWINT0_SHF)
-#define GIC_VPE_PEND_SWINT1_SHF         5
-#define GIC_VPE_PEND_SWINT1_MSK         (MSK(1) << GIC_VPE_PEND_SWINT1_SHF)
-
-/* GIC_VPE_RMASK Masks */
-#define GIC_VPE_RMASK_WD_SHF            0
-#define GIC_VPE_RMASK_WD_MSK            (MSK(1) << GIC_VPE_RMASK_WD_SHF)
-#define GIC_VPE_RMASK_CMP_SHF           1
-#define GIC_VPE_RMASK_CMP_MSK           (MSK(1) << GIC_VPE_RMASK_CMP_SHF)
-#define GIC_VPE_RMASK_TIMER_SHF         2
-#define GIC_VPE_RMASK_TIMER_MSK         (MSK(1) << GIC_VPE_RMASK_TIMER_SHF)
-#define GIC_VPE_RMASK_PERFCNT_SHF       3
-#define GIC_VPE_RMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_RMASK_PERFCNT_SHF)
-#define GIC_VPE_RMASK_SWINT0_SHF        4
-#define GIC_VPE_RMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT0_SHF)
-#define GIC_VPE_RMASK_SWINT1_SHF        5
-#define GIC_VPE_RMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_RMASK_SWINT1_SHF)
-
-/* GIC_VPE_SMASK Masks */
-#define GIC_VPE_SMASK_WD_SHF            0
-#define GIC_VPE_SMASK_WD_MSK            (MSK(1) << GIC_VPE_SMASK_WD_SHF)
-#define GIC_VPE_SMASK_CMP_SHF           1
-#define GIC_VPE_SMASK_CMP_MSK           (MSK(1) << GIC_VPE_SMASK_CMP_SHF)
-#define GIC_VPE_SMASK_TIMER_SHF         2
-#define GIC_VPE_SMASK_TIMER_MSK         (MSK(1) << GIC_VPE_SMASK_TIMER_SHF)
-#define GIC_VPE_SMASK_PERFCNT_SHF       3
-#define GIC_VPE_SMASK_PERFCNT_MSK       (MSK(1) << GIC_VPE_SMASK_PERFCNT_SHF)
-#define GIC_VPE_SMASK_SWINT0_SHF        4
-#define GIC_VPE_SMASK_SWINT0_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT0_SHF)
-#define GIC_VPE_SMASK_SWINT1_SHF        5
-#define GIC_VPE_SMASK_SWINT1_MSK        (MSK(1) << GIC_VPE_SMASK_SWINT1_SHF)
-
-/*
- * Set the Mapping of Interrupt X to a VPE.
- */
-#define GIC_SH_MAP_TO_VPE_SMASK(intr, vpe) \
-        GICWRITE(GIC_REG_ADDR(SHARED, GIC_SH_MAP_TO_VPE_REG_OFF(intr, vpe)), \
-                 GIC_SH_MAP_TO_VPE_REG_BIT(vpe))
-
-struct gic_pcpu_mask {
-       DECLARE_BITMAP(pcpu_mask, GIC_NUM_INTRS);
-};
-
-struct gic_pending_regs {
-       DECLARE_BITMAP(pending, GIC_NUM_INTRS);
-};
-
-struct gic_intrmask_regs {
-       DECLARE_BITMAP(intrmask, GIC_NUM_INTRS);
-};
-
-/*
- * Interrupt Meta-data specification. The ipiflag helps
- * in building ipi_map.
- */
-struct gic_intr_map {
-        unsigned int intrnum;   /* Ext Intr Num         */
-        unsigned int cpunum;    /* Directed to this CPU */
-        unsigned int pin;       /* Directed to this Pin */
-        unsigned int polarity;  /* Polarity : +/-       */
-        unsigned int trigtype;  /* Trigger  : Edge/Levl */
-        unsigned int ipiflag;   /* Is used for IPI ?    */
-};
-
-extern void gic_init(unsigned long gic_base_addr,
-        unsigned long gic_addrspace_size, struct gic_intr_map *intrmap,
-        unsigned int intrmap_size, unsigned int irqbase);
-
-extern unsigned int gic_get_int(void);
-extern void gic_send_ipi(unsigned int intr);
-
-#endif /* _ASM_GICREGS_H */
diff --git a/include/asm-mips/gpio.h b/include/asm-mips/gpio.h
deleted file mode 100644
index 06e46faf862d..000000000000
--- a/include/asm-mips/gpio.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_MIPS_GPIO_H
-#define __ASM_MIPS_GPIO_H
-
-#include <gpio.h>
-
-#endif /* __ASM_MIPS_GPIO_H */
diff --git a/include/asm-mips/gt64120.h b/include/asm-mips/gt64120.h
deleted file mode 100644
index e64b41093c49..000000000000
--- a/include/asm-mips/gt64120.h
+++ /dev/null
@@ -1,580 +0,0 @@
-/*
- * Copyright (C) 2000, 2004, 2005  MIPS Technologies, Inc.
- *      All rights reserved.
- *      Authors: Carsten Langgaard <carstenl@mips.com>
- *               Maciej W. Rozycki <macro@mips.com>
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef _ASM_GT64120_H
-#define _ASM_GT64120_H
-
-#include <linux/clocksource.h>
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-
-#define MSK(n)                  ((1 << (n)) - 1)
-
-/*
- *  Register offset addresses
- */
-/* CPU Configuration.  */
-#define GT_CPU_OFS              0x000
-
-#define GT_MULTI_OFS            0x120
-
-/* CPU Address Decode.  */
-#define GT_SCS10LD_OFS          0x008
-#define GT_SCS10HD_OFS          0x010
-#define GT_SCS32LD_OFS          0x018
-#define GT_SCS32HD_OFS          0x020
-#define GT_CS20LD_OFS           0x028
-#define GT_CS20HD_OFS           0x030
-#define GT_CS3BOOTLD_OFS        0x038
-#define GT_CS3BOOTHD_OFS        0x040
-#define GT_PCI0IOLD_OFS         0x048
-#define GT_PCI0IOHD_OFS         0x050
-#define GT_PCI0M0LD_OFS         0x058
-#define GT_PCI0M0HD_OFS         0x060
-#define GT_ISD_OFS              0x068
-
-#define GT_PCI0M1LD_OFS         0x080
-#define GT_PCI0M1HD_OFS         0x088
-#define GT_PCI1IOLD_OFS         0x090
-#define GT_PCI1IOHD_OFS         0x098
-#define GT_PCI1M0LD_OFS         0x0a0
-#define GT_PCI1M0HD_OFS         0x0a8
-#define GT_PCI1M1LD_OFS         0x0b0
-#define GT_PCI1M1HD_OFS         0x0b8
-#define GT_PCI1M1LD_OFS         0x0b0
-#define GT_PCI1M1HD_OFS         0x0b8
-
-#define GT_SCS10AR_OFS          0x0d0
-#define GT_SCS32AR_OFS          0x0d8
-#define GT_CS20R_OFS            0x0e0
-#define GT_CS3BOOTR_OFS         0x0e8
-
-#define GT_PCI0IOREMAP_OFS      0x0f0
-#define GT_PCI0M0REMAP_OFS      0x0f8
-#define GT_PCI0M1REMAP_OFS      0x100
-#define GT_PCI1IOREMAP_OFS      0x108
-#define GT_PCI1M0REMAP_OFS      0x110
-#define GT_PCI1M1REMAP_OFS      0x118
-
-/* CPU Error Report.  */
-#define GT_CPUERR_ADDRLO_OFS    0x070
-#define GT_CPUERR_ADDRHI_OFS    0x078
-
-#define GT_CPUERR_DATALO_OFS    0x128                   /* GT-64120A only  */
-#define GT_CPUERR_DATAHI_OFS    0x130                   /* GT-64120A only  */
-#define GT_CPUERR_PARITY_OFS    0x138                   /* GT-64120A only  */
-
-/* CPU Sync Barrier.  */
-#define GT_PCI0SYNC_OFS         0x0c0
-#define GT_PCI1SYNC_OFS         0x0c8
-
-/* SDRAM and Device Address Decode.  */
-#define GT_SCS0LD_OFS           0x400
-#define GT_SCS0HD_OFS           0x404
-#define GT_SCS1LD_OFS           0x408
-#define GT_SCS1HD_OFS           0x40c
-#define GT_SCS2LD_OFS           0x410
-#define GT_SCS2HD_OFS           0x414
-#define GT_SCS3LD_OFS           0x418
-#define GT_SCS3HD_OFS           0x41c
-#define GT_CS0LD_OFS            0x420
-#define GT_CS0HD_OFS            0x424
-#define GT_CS1LD_OFS            0x428
-#define GT_CS1HD_OFS            0x42c
-#define GT_CS2LD_OFS            0x430
-#define GT_CS2HD_OFS            0x434
-#define GT_CS3LD_OFS            0x438
-#define GT_CS3HD_OFS            0x43c
-#define GT_BOOTLD_OFS           0x440
-#define GT_BOOTHD_OFS           0x444
-
-#define GT_ADERR_OFS            0x470
-
-/* SDRAM Configuration.  */
-#define GT_SDRAM_CFG_OFS        0x448
-
-#define GT_SDRAM_OPMODE_OFS     0x474
-#define GT_SDRAM_BM_OFS         0x478
-#define GT_SDRAM_ADDRDECODE_OFS 0x47c
-
-/* SDRAM Parameters.  */
-#define GT_SDRAM_B0_OFS         0x44c
-#define GT_SDRAM_B1_OFS         0x450
-#define GT_SDRAM_B2_OFS         0x454
-#define GT_SDRAM_B3_OFS         0x458
-
-/* Device Parameters.  */
-#define GT_DEV_B0_OFS           0x45c
-#define GT_DEV_B1_OFS           0x460
-#define GT_DEV_B2_OFS           0x464
-#define GT_DEV_B3_OFS           0x468
-#define GT_DEV_BOOT_OFS         0x46c
-
-/* ECC.  */
-#define GT_ECC_ERRDATALO        0x480                   /* GT-64120A only  */
-#define GT_ECC_ERRDATAHI        0x484                   /* GT-64120A only  */
-#define GT_ECC_MEM              0x488                   /* GT-64120A only  */
-#define GT_ECC_CALC             0x48c                   /* GT-64120A only  */
-#define GT_ECC_ERRADDR          0x490                   /* GT-64120A only  */
-
-/* DMA Record.  */
-#define GT_DMA0_CNT_OFS         0x800
-#define GT_DMA1_CNT_OFS         0x804
-#define GT_DMA2_CNT_OFS         0x808
-#define GT_DMA3_CNT_OFS         0x80c
-#define GT_DMA0_SA_OFS          0x810
-#define GT_DMA1_SA_OFS          0x814
-#define GT_DMA2_SA_OFS          0x818
-#define GT_DMA3_SA_OFS          0x81c
-#define GT_DMA0_DA_OFS          0x820
-#define GT_DMA1_DA_OFS          0x824
-#define GT_DMA2_DA_OFS          0x828
-#define GT_DMA3_DA_OFS          0x82c
-#define GT_DMA0_NEXT_OFS        0x830
-#define GT_DMA1_NEXT_OFS        0x834
-#define GT_DMA2_NEXT_OFS        0x838
-#define GT_DMA3_NEXT_OFS        0x83c
-
-#define GT_DMA0_CUR_OFS         0x870
-#define GT_DMA1_CUR_OFS         0x874
-#define GT_DMA2_CUR_OFS         0x878
-#define GT_DMA3_CUR_OFS         0x87c
-
-/* DMA Channel Control.  */
-#define GT_DMA0_CTRL_OFS        0x840
-#define GT_DMA1_CTRL_OFS        0x844
-#define GT_DMA2_CTRL_OFS        0x848
-#define GT_DMA3_CTRL_OFS        0x84c
-
-/* DMA Arbiter.  */
-#define GT_DMA_ARB_OFS          0x860
-
-/* Timer/Counter.  */
-#define GT_TC0_OFS              0x850
-#define GT_TC1_OFS              0x854
-#define GT_TC2_OFS              0x858
-#define GT_TC3_OFS              0x85c
-
-#define GT_TC_CONTROL_OFS       0x864
-
-/* PCI Internal.  */
-#define GT_PCI0_CMD_OFS         0xc00
-#define GT_PCI0_TOR_OFS         0xc04
-#define GT_PCI0_BS_SCS10_OFS    0xc08
-#define GT_PCI0_BS_SCS32_OFS    0xc0c
-#define GT_PCI0_BS_CS20_OFS     0xc10
-#define GT_PCI0_BS_CS3BT_OFS    0xc14
-
-#define GT_PCI1_IACK_OFS        0xc30
-#define GT_PCI0_IACK_OFS        0xc34
-
-#define GT_PCI0_BARE_OFS        0xc3c
-#define GT_PCI0_PREFMBR_OFS     0xc40
-
-#define GT_PCI0_SCS10_BAR_OFS   0xc48
-#define GT_PCI0_SCS32_BAR_OFS   0xc4c
-#define GT_PCI0_CS20_BAR_OFS    0xc50
-#define GT_PCI0_CS3BT_BAR_OFS   0xc54
-#define GT_PCI0_SSCS10_BAR_OFS  0xc58
-#define GT_PCI0_SSCS32_BAR_OFS  0xc5c
-
-#define GT_PCI0_SCS3BT_BAR_OFS  0xc64
-
-#define GT_PCI1_CMD_OFS         0xc80
-#define GT_PCI1_TOR_OFS         0xc84
-#define GT_PCI1_BS_SCS10_OFS    0xc88
-#define GT_PCI1_BS_SCS32_OFS    0xc8c
-#define GT_PCI1_BS_CS20_OFS     0xc90
-#define GT_PCI1_BS_CS3BT_OFS    0xc94
-
-#define GT_PCI1_BARE_OFS        0xcbc
-#define GT_PCI1_PREFMBR_OFS     0xcc0
-
-#define GT_PCI1_SCS10_BAR_OFS   0xcc8
-#define GT_PCI1_SCS32_BAR_OFS   0xccc
-#define GT_PCI1_CS20_BAR_OFS    0xcd0
-#define GT_PCI1_CS3BT_BAR_OFS   0xcd4
-#define GT_PCI1_SSCS10_BAR_OFS  0xcd8
-#define GT_PCI1_SSCS32_BAR_OFS  0xcdc
-
-#define GT_PCI1_SCS3BT_BAR_OFS  0xce4
-
-#define GT_PCI1_CFGADDR_OFS     0xcf0
-#define GT_PCI1_CFGDATA_OFS     0xcf4
-#define GT_PCI0_CFGADDR_OFS     0xcf8
-#define GT_PCI0_CFGDATA_OFS     0xcfc
-
-/* Interrupts.  */
-#define GT_INTRCAUSE_OFS        0xc18
-#define GT_INTRMASK_OFS         0xc1c
-
-#define GT_PCI0_ICMASK_OFS      0xc24
-#define GT_PCI0_SERR0MASK_OFS   0xc28
-
-#define GT_CPU_INTSEL_OFS       0xc70
-#define GT_PCI0_INTSEL_OFS      0xc74
-
-#define GT_HINTRCAUSE_OFS       0xc98
-#define GT_HINTRMASK_OFS        0xc9c
-
-#define GT_PCI0_HICMASK_OFS     0xca4
-#define GT_PCI1_SERR1MASK_OFS   0xca8
-
-
-/*
- * I2O Support Registers
- */
-#define INBOUND_MESSAGE_REGISTER0_PCI_SIDE              0x010
-#define INBOUND_MESSAGE_REGISTER1_PCI_SIDE              0x014
-#define OUTBOUND_MESSAGE_REGISTER0_PCI_SIDE             0x018
-#define OUTBOUND_MESSAGE_REGISTER1_PCI_SIDE             0x01c
-#define INBOUND_DOORBELL_REGISTER_PCI_SIDE              0x020
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE       0x024
-#define INBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE        0x028
-#define OUTBOUND_DOORBELL_REGISTER_PCI_SIDE             0x02c
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_PCI_SIDE      0x030
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_PCI_SIDE       0x034
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE    0x040
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_PCI_SIDE   0x044
-#define QUEUE_CONTROL_REGISTER_PCI_SIDE                 0x050
-#define QUEUE_BASE_ADDRESS_REGISTER_PCI_SIDE            0x054
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE     0x060
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE     0x064
-#define INBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE     0x068
-#define INBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE     0x06c
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_PCI_SIDE    0x070
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_PCI_SIDE    0x074
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_PCI_SIDE    0x078
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_PCI_SIDE    0x07c
-
-#define INBOUND_MESSAGE_REGISTER0_CPU_SIDE              0x1c10
-#define INBOUND_MESSAGE_REGISTER1_CPU_SIDE              0x1c14
-#define OUTBOUND_MESSAGE_REGISTER0_CPU_SIDE             0x1c18
-#define OUTBOUND_MESSAGE_REGISTER1_CPU_SIDE             0x1c1c
-#define INBOUND_DOORBELL_REGISTER_CPU_SIDE              0x1c20
-#define INBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE       0x1c24
-#define INBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE        0x1c28
-#define OUTBOUND_DOORBELL_REGISTER_CPU_SIDE             0x1c2c
-#define OUTBOUND_INTERRUPT_CAUSE_REGISTER_CPU_SIDE      0x1c30
-#define OUTBOUND_INTERRUPT_MASK_REGISTER_CPU_SIDE       0x1c34
-#define INBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE    0x1c40
-#define OUTBOUND_QUEUE_PORT_VIRTUAL_REGISTER_CPU_SIDE   0x1c44
-#define QUEUE_CONTROL_REGISTER_CPU_SIDE                 0x1c50
-#define QUEUE_BASE_ADDRESS_REGISTER_CPU_SIDE            0x1c54
-#define INBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c60
-#define INBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c64
-#define INBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE     0x1c68
-#define INBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE     0x1c6c
-#define OUTBOUND_FREE_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c70
-#define OUTBOUND_FREE_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c74
-#define OUTBOUND_POST_HEAD_POINTER_REGISTER_CPU_SIDE    0x1c78
-#define OUTBOUND_POST_TAIL_POINTER_REGISTER_CPU_SIDE    0x1c7c
-
-/*
- *  Register encodings
- */
-#define GT_CPU_ENDIAN_SHF       12
-#define GT_CPU_ENDIAN_MSK       (MSK(1) << GT_CPU_ENDIAN_SHF)
-#define GT_CPU_ENDIAN_BIT       GT_CPU_ENDIAN_MSK
-#define GT_CPU_WR_SHF           16
-#define GT_CPU_WR_MSK           (MSK(1) << GT_CPU_WR_SHF)
-#define GT_CPU_WR_BIT           GT_CPU_WR_MSK
-#define GT_CPU_WR_DXDXDXDX      0
-#define GT_CPU_WR_DDDD          1
-
-
-#define GT_PCI_DCRM_SHF         21
-#define GT_PCI_LD_SHF           0
-#define GT_PCI_LD_MSK           (MSK(15) << GT_PCI_LD_SHF)
-#define GT_PCI_HD_SHF           0
-#define GT_PCI_HD_MSK           (MSK(7) << GT_PCI_HD_SHF)
-#define GT_PCI_REMAP_SHF        0
-#define GT_PCI_REMAP_MSK        (MSK(11) << GT_PCI_REMAP_SHF)
-
-
-#define GT_CFGADDR_CFGEN_SHF    31
-#define GT_CFGADDR_CFGEN_MSK    (MSK(1) << GT_CFGADDR_CFGEN_SHF)
-#define GT_CFGADDR_CFGEN_BIT    GT_CFGADDR_CFGEN_MSK
-
-#define GT_CFGADDR_BUSNUM_SHF   16
-#define GT_CFGADDR_BUSNUM_MSK   (MSK(8) << GT_CFGADDR_BUSNUM_SHF)
-
-#define GT_CFGADDR_DEVNUM_SHF   11
-#define GT_CFGADDR_DEVNUM_MSK   (MSK(5) << GT_CFGADDR_DEVNUM_SHF)
-
-#define GT_CFGADDR_FUNCNUM_SHF  8
-#define GT_CFGADDR_FUNCNUM_MSK  (MSK(3) << GT_CFGADDR_FUNCNUM_SHF)
-
-#define GT_CFGADDR_REGNUM_SHF   2
-#define GT_CFGADDR_REGNUM_MSK   (MSK(6) << GT_CFGADDR_REGNUM_SHF)
-
-
-#define GT_SDRAM_BM_ORDER_SHF   2
-#define GT_SDRAM_BM_ORDER_MSK   (MSK(1) << GT_SDRAM_BM_ORDER_SHF)
-#define GT_SDRAM_BM_ORDER_BIT   GT_SDRAM_BM_ORDER_MSK
-#define GT_SDRAM_BM_ORDER_SUB   1
-#define GT_SDRAM_BM_ORDER_LIN   0
-
-#define GT_SDRAM_BM_RSVD_ALL1   0xffb
-
-
-#define GT_SDRAM_ADDRDECODE_ADDR_SHF    0
-#define GT_SDRAM_ADDRDECODE_ADDR_MSK    (MSK(3) << GT_SDRAM_ADDRDECODE_ADDR_SHF)
-#define GT_SDRAM_ADDRDECODE_ADDR_0      0
-#define GT_SDRAM_ADDRDECODE_ADDR_1      1
-#define GT_SDRAM_ADDRDECODE_ADDR_2      2
-#define GT_SDRAM_ADDRDECODE_ADDR_3      3
-#define GT_SDRAM_ADDRDECODE_ADDR_4      4
-#define GT_SDRAM_ADDRDECODE_ADDR_5      5
-#define GT_SDRAM_ADDRDECODE_ADDR_6      6
-#define GT_SDRAM_ADDRDECODE_ADDR_7      7
-
-
-#define GT_SDRAM_B0_CASLAT_SHF          0
-#define GT_SDRAM_B0_CASLAT_MSK          (MSK(2) << GT_SDRAM_B0__SHF)
-#define GT_SDRAM_B0_CASLAT_2            1
-#define GT_SDRAM_B0_CASLAT_3            2
-
-#define GT_SDRAM_B0_FTDIS_SHF           2
-#define GT_SDRAM_B0_FTDIS_MSK           (MSK(1) << GT_SDRAM_B0_FTDIS_SHF)
-#define GT_SDRAM_B0_FTDIS_BIT           GT_SDRAM_B0_FTDIS_MSK
-
-#define GT_SDRAM_B0_SRASPRCHG_SHF       3
-#define GT_SDRAM_B0_SRASPRCHG_MSK       (MSK(1) << GT_SDRAM_B0_SRASPRCHG_SHF)
-#define GT_SDRAM_B0_SRASPRCHG_BIT       GT_SDRAM_B0_SRASPRCHG_MSK
-#define GT_SDRAM_B0_SRASPRCHG_2         0
-#define GT_SDRAM_B0_SRASPRCHG_3         1
-
-#define GT_SDRAM_B0_B0COMPAB_SHF        4
-#define GT_SDRAM_B0_B0COMPAB_MSK        (MSK(1) << GT_SDRAM_B0_B0COMPAB_SHF)
-#define GT_SDRAM_B0_B0COMPAB_BIT        GT_SDRAM_B0_B0COMPAB_MSK
-
-#define GT_SDRAM_B0_64BITINT_SHF        5
-#define GT_SDRAM_B0_64BITINT_MSK        (MSK(1) << GT_SDRAM_B0_64BITINT_SHF)
-#define GT_SDRAM_B0_64BITINT_BIT        GT_SDRAM_B0_64BITINT_MSK
-#define GT_SDRAM_B0_64BITINT_2          0
-#define GT_SDRAM_B0_64BITINT_4          1
-
-#define GT_SDRAM_B0_BW_SHF              6
-#define GT_SDRAM_B0_BW_MSK              (MSK(1) << GT_SDRAM_B0_BW_SHF)
-#define GT_SDRAM_B0_BW_BIT              GT_SDRAM_B0_BW_MSK
-#define GT_SDRAM_B0_BW_32               0
-#define GT_SDRAM_B0_BW_64               1
-
-#define GT_SDRAM_B0_BLODD_SHF           7
-#define GT_SDRAM_B0_BLODD_MSK           (MSK(1) << GT_SDRAM_B0_BLODD_SHF)
-#define GT_SDRAM_B0_BLODD_BIT           GT_SDRAM_B0_BLODD_MSK
-
-#define GT_SDRAM_B0_PAR_SHF             8
-#define GT_SDRAM_B0_PAR_MSK             (MSK(1) << GT_SDRAM_B0_PAR_SHF)
-#define GT_SDRAM_B0_PAR_BIT             GT_SDRAM_B0_PAR_MSK
-
-#define GT_SDRAM_B0_BYPASS_SHF          9
-#define GT_SDRAM_B0_BYPASS_MSK          (MSK(1) << GT_SDRAM_B0_BYPASS_SHF)
-#define GT_SDRAM_B0_BYPASS_BIT          GT_SDRAM_B0_BYPASS_MSK
-
-#define GT_SDRAM_B0_SRAS2SCAS_SHF       10
-#define GT_SDRAM_B0_SRAS2SCAS_MSK       (MSK(1) << GT_SDRAM_B0_SRAS2SCAS_SHF)
-#define GT_SDRAM_B0_SRAS2SCAS_BIT       GT_SDRAM_B0_SRAS2SCAS_MSK
-#define GT_SDRAM_B0_SRAS2SCAS_2         0
-#define GT_SDRAM_B0_SRAS2SCAS_3         1
-
-#define GT_SDRAM_B0_SIZE_SHF            11
-#define GT_SDRAM_B0_SIZE_MSK            (MSK(1) << GT_SDRAM_B0_SIZE_SHF)
-#define GT_SDRAM_B0_SIZE_BIT            GT_SDRAM_B0_SIZE_MSK
-#define GT_SDRAM_B0_SIZE_16M            0
-#define GT_SDRAM_B0_SIZE_64M            1
-
-#define GT_SDRAM_B0_EXTPAR_SHF          12
-#define GT_SDRAM_B0_EXTPAR_MSK          (MSK(1) << GT_SDRAM_B0_EXTPAR_SHF)
-#define GT_SDRAM_B0_EXTPAR_BIT          GT_SDRAM_B0_EXTPAR_MSK
-
-#define GT_SDRAM_B0_BLEN_SHF            13
-#define GT_SDRAM_B0_BLEN_MSK            (MSK(1) << GT_SDRAM_B0_BLEN_SHF)
-#define GT_SDRAM_B0_BLEN_BIT            GT_SDRAM_B0_BLEN_MSK
-#define GT_SDRAM_B0_BLEN_8              0
-#define GT_SDRAM_B0_BLEN_4              1
-
-
-#define GT_SDRAM_CFG_REFINT_SHF         0
-#define GT_SDRAM_CFG_REFINT_MSK         (MSK(14) << GT_SDRAM_CFG_REFINT_SHF)
-
-#define GT_SDRAM_CFG_NINTERLEAVE_SHF    14
-#define GT_SDRAM_CFG_NINTERLEAVE_MSK    (MSK(1) << GT_SDRAM_CFG_NINTERLEAVE_SHF)
-#define GT_SDRAM_CFG_NINTERLEAVE_BIT    GT_SDRAM_CFG_NINTERLEAVE_MSK
-
-#define GT_SDRAM_CFG_RMW_SHF            15
-#define GT_SDRAM_CFG_RMW_MSK            (MSK(1) << GT_SDRAM_CFG_RMW_SHF)
-#define GT_SDRAM_CFG_RMW_BIT            GT_SDRAM_CFG_RMW_MSK
-
-#define GT_SDRAM_CFG_NONSTAGREF_SHF     16
-#define GT_SDRAM_CFG_NONSTAGREF_MSK     (MSK(1) << GT_SDRAM_CFG_NONSTAGREF_SHF)
-#define GT_SDRAM_CFG_NONSTAGREF_BIT     GT_SDRAM_CFG_NONSTAGREF_MSK
-
-#define GT_SDRAM_CFG_DUPCNTL_SHF        19
-#define GT_SDRAM_CFG_DUPCNTL_MSK        (MSK(1) << GT_SDRAM_CFG_DUPCNTL_SHF)
-#define GT_SDRAM_CFG_DUPCNTL_BIT        GT_SDRAM_CFG_DUPCNTL_MSK
-
-#define GT_SDRAM_CFG_DUPBA_SHF          20
-#define GT_SDRAM_CFG_DUPBA_MSK          (MSK(1) << GT_SDRAM_CFG_DUPBA_SHF)
-#define GT_SDRAM_CFG_DUPBA_BIT          GT_SDRAM_CFG_DUPBA_MSK
-
-#define GT_SDRAM_CFG_DUPEOT0_SHF        21
-#define GT_SDRAM_CFG_DUPEOT0_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT0_SHF)
-#define GT_SDRAM_CFG_DUPEOT0_BIT        GT_SDRAM_CFG_DUPEOT0_MSK
-
-#define GT_SDRAM_CFG_DUPEOT1_SHF        22
-#define GT_SDRAM_CFG_DUPEOT1_MSK        (MSK(1) << GT_SDRAM_CFG_DUPEOT1_SHF)
-#define GT_SDRAM_CFG_DUPEOT1_BIT        GT_SDRAM_CFG_DUPEOT1_MSK
-
-#define GT_SDRAM_OPMODE_OP_SHF          0
-#define GT_SDRAM_OPMODE_OP_MSK          (MSK(3) << GT_SDRAM_OPMODE_OP_SHF)
-#define GT_SDRAM_OPMODE_OP_NORMAL       0
-#define GT_SDRAM_OPMODE_OP_NOP          1
-#define GT_SDRAM_OPMODE_OP_PRCHG        2
-#define GT_SDRAM_OPMODE_OP_MODE         3
-#define GT_SDRAM_OPMODE_OP_CBR          4
-
-#define GT_TC_CONTROL_ENTC0_SHF         0
-#define GT_TC_CONTROL_ENTC0_MSK         (MSK(1) << GT_TC_CONTROL_ENTC0_SHF)
-#define GT_TC_CONTROL_ENTC0_BIT         GT_TC_CONTROL_ENTC0_MSK
-#define GT_TC_CONTROL_SELTC0_SHF        1
-#define GT_TC_CONTROL_SELTC0_MSK        (MSK(1) << GT_TC_CONTROL_SELTC0_SHF)
-#define GT_TC_CONTROL_SELTC0_BIT        GT_TC_CONTROL_SELTC0_MSK
-
-
-#define GT_PCI0_BARE_SWSCS3BOOTDIS_SHF  0
-#define GT_PCI0_BARE_SWSCS3BOOTDIS_MSK  (MSK(1) << GT_PCI0_BARE_SWSCS3BOOTDIS_SHF)
-#define GT_PCI0_BARE_SWSCS3BOOTDIS_BIT  GT_PCI0_BARE_SWSCS3BOOTDIS_MSK
-
-#define GT_PCI0_BARE_SWSCS32DIS_SHF     1
-#define GT_PCI0_BARE_SWSCS32DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS32DIS_SHF)
-#define GT_PCI0_BARE_SWSCS32DIS_BIT     GT_PCI0_BARE_SWSCS32DIS_MSK
-
-#define GT_PCI0_BARE_SWSCS10DIS_SHF     2
-#define GT_PCI0_BARE_SWSCS10DIS_MSK     (MSK(1) << GT_PCI0_BARE_SWSCS10DIS_SHF)
-#define GT_PCI0_BARE_SWSCS10DIS_BIT     GT_PCI0_BARE_SWSCS10DIS_MSK
-
-#define GT_PCI0_BARE_INTIODIS_SHF       3
-#define GT_PCI0_BARE_INTIODIS_MSK       (MSK(1) << GT_PCI0_BARE_INTIODIS_SHF)
-#define GT_PCI0_BARE_INTIODIS_BIT       GT_PCI0_BARE_INTIODIS_MSK
-
-#define GT_PCI0_BARE_INTMEMDIS_SHF      4
-#define GT_PCI0_BARE_INTMEMDIS_MSK      (MSK(1) << GT_PCI0_BARE_INTMEMDIS_SHF)
-#define GT_PCI0_BARE_INTMEMDIS_BIT      GT_PCI0_BARE_INTMEMDIS_MSK
-
-#define GT_PCI0_BARE_CS3BOOTDIS_SHF     5
-#define GT_PCI0_BARE_CS3BOOTDIS_MSK     (MSK(1) << GT_PCI0_BARE_CS3BOOTDIS_SHF)
-#define GT_PCI0_BARE_CS3BOOTDIS_BIT     GT_PCI0_BARE_CS3BOOTDIS_MSK
-
-#define GT_PCI0_BARE_CS20DIS_SHF        6
-#define GT_PCI0_BARE_CS20DIS_MSK        (MSK(1) << GT_PCI0_BARE_CS20DIS_SHF)
-#define GT_PCI0_BARE_CS20DIS_BIT        GT_PCI0_BARE_CS20DIS_MSK
-
-#define GT_PCI0_BARE_SCS32DIS_SHF       7
-#define GT_PCI0_BARE_SCS32DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS32DIS_SHF)
-#define GT_PCI0_BARE_SCS32DIS_BIT       GT_PCI0_BARE_SCS32DIS_MSK
-
-#define GT_PCI0_BARE_SCS10DIS_SHF       8
-#define GT_PCI0_BARE_SCS10DIS_MSK       (MSK(1) << GT_PCI0_BARE_SCS10DIS_SHF)
-#define GT_PCI0_BARE_SCS10DIS_BIT       GT_PCI0_BARE_SCS10DIS_MSK
-
-
-#define GT_INTRCAUSE_MASABORT0_SHF      18
-#define GT_INTRCAUSE_MASABORT0_MSK      (MSK(1) << GT_INTRCAUSE_MASABORT0_SHF)
-#define GT_INTRCAUSE_MASABORT0_BIT      GT_INTRCAUSE_MASABORT0_MSK
-
-#define GT_INTRCAUSE_TARABORT0_SHF      19
-#define GT_INTRCAUSE_TARABORT0_MSK      (MSK(1) << GT_INTRCAUSE_TARABORT0_SHF)
-#define GT_INTRCAUSE_TARABORT0_BIT      GT_INTRCAUSE_TARABORT0_MSK
-
-
-#define GT_PCI0_CFGADDR_REGNUM_SHF      2
-#define GT_PCI0_CFGADDR_REGNUM_MSK      (MSK(6) << GT_PCI0_CFGADDR_REGNUM_SHF)
-#define GT_PCI0_CFGADDR_FUNCTNUM_SHF    8
-#define GT_PCI0_CFGADDR_FUNCTNUM_MSK    (MSK(3) << GT_PCI0_CFGADDR_FUNCTNUM_SHF)
-#define GT_PCI0_CFGADDR_DEVNUM_SHF      11
-#define GT_PCI0_CFGADDR_DEVNUM_MSK      (MSK(5) << GT_PCI0_CFGADDR_DEVNUM_SHF)
-#define GT_PCI0_CFGADDR_BUSNUM_SHF      16
-#define GT_PCI0_CFGADDR_BUSNUM_MSK      (MSK(8) << GT_PCI0_CFGADDR_BUSNUM_SHF)
-#define GT_PCI0_CFGADDR_CONFIGEN_SHF    31
-#define GT_PCI0_CFGADDR_CONFIGEN_MSK    (MSK(1) << GT_PCI0_CFGADDR_CONFIGEN_SHF)
-#define GT_PCI0_CFGADDR_CONFIGEN_BIT    GT_PCI0_CFGADDR_CONFIGEN_MSK
-
-#define GT_PCI0_CMD_MBYTESWAP_SHF       0
-#define GT_PCI0_CMD_MBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_MBYTESWAP_SHF)
-#define GT_PCI0_CMD_MBYTESWAP_BIT       GT_PCI0_CMD_MBYTESWAP_MSK
-#define GT_PCI0_CMD_MWORDSWAP_SHF       10
-#define GT_PCI0_CMD_MWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_MWORDSWAP_SHF)
-#define GT_PCI0_CMD_MWORDSWAP_BIT       GT_PCI0_CMD_MWORDSWAP_MSK
-#define GT_PCI0_CMD_SBYTESWAP_SHF       16
-#define GT_PCI0_CMD_SBYTESWAP_MSK       (MSK(1) << GT_PCI0_CMD_SBYTESWAP_SHF)
-#define GT_PCI0_CMD_SBYTESWAP_BIT       GT_PCI0_CMD_SBYTESWAP_MSK
-#define GT_PCI0_CMD_SWORDSWAP_SHF       11
-#define GT_PCI0_CMD_SWORDSWAP_MSK       (MSK(1) << GT_PCI0_CMD_SWORDSWAP_SHF)
-#define GT_PCI0_CMD_SWORDSWAP_BIT       GT_PCI0_CMD_SWORDSWAP_MSK
-
-#define GT_INTR_T0EXP_SHF               8
-#define GT_INTR_T0EXP_MSK               (MSK(1) << GT_INTR_T0EXP_SHF)
-#define GT_INTR_T0EXP_BIT               GT_INTR_T0EXP_MSK
-#define GT_INTR_RETRYCTR0_SHF           20
-#define GT_INTR_RETRYCTR0_MSK           (MSK(1) << GT_INTR_RETRYCTR0_SHF)
-#define GT_INTR_RETRYCTR0_BIT           GT_INTR_RETRYCTR0_MSK
-
-/*
- *  Misc
- */
-#define GT_DEF_PCI0_IO_BASE     0x10000000UL
-#define GT_DEF_PCI0_IO_SIZE     0x02000000UL
-#define GT_DEF_PCI0_MEM0_BASE   0x12000000UL
-#define GT_DEF_PCI0_MEM0_SIZE   0x02000000UL
-#define GT_DEF_BASE             0x14000000UL
-
-#define GT_MAX_BANKSIZE         (256 * 1024 * 1024)     /* Max 256MB bank  */
-#define GT_LATTIM_MIN           6                       /* Minimum lat  */
-
-/*
- * The gt64120_dep.h file must define the following macros
- *
- *   GT_READ(ofs, data_pointer)
- *   GT_WRITE(ofs, data)           - read/write GT64120 registers in 32bit
- *
- *   TIMER      - gt64120 timer irq, temporary solution until
- *                full gt64120 cascade interrupt support is in place
- */
-
-#include <mach-gt64120.h>
-
-/*
- * Because of an error/peculiarity in the Galileo chip, we need to swap the
- * bytes when running bigendian.  We also provide non-swapping versions.
- */
-#define __GT_READ(ofs)                                                  \
-        (*(volatile u32 *)(GT64120_BASE+(ofs)))
-#define __GT_WRITE(ofs, data)                                           \
-        do { *(volatile u32 *)(GT64120_BASE+(ofs)) = (data); } while (0)
-#define GT_READ(ofs)            le32_to_cpu(__GT_READ(ofs))
-#define GT_WRITE(ofs, data)     __GT_WRITE(ofs, cpu_to_le32(data))
-
-extern void gt641xx_set_base_clock(unsigned int clock);
-extern int gt641xx_timer0_state(void);
-
-#endif /* _ASM_GT64120_H */
diff --git a/include/asm-mips/hardirq.h b/include/asm-mips/hardirq.h
deleted file mode 100644
index 90bf399e6dd9..000000000000
--- a/include/asm-mips/hardirq.h
+++ /dev/null
@@ -1,24 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 98, 99, 2000, 01, 05 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef _ASM_HARDIRQ_H
-#define _ASM_HARDIRQ_H
-
-#include <linux/threads.h>
-#include <linux/irq.h>
-
-typedef struct {
-        unsigned int __softirq_pending;
-} ____cacheline_aligned irq_cpustat_t;
-
-#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
-
-extern void ack_bad_irq(unsigned int irq);
-
-#endif /* _ASM_HARDIRQ_H */
diff --git a/include/asm-mips/hazards.h b/include/asm-mips/hazards.h
deleted file mode 100644
index 2de638f84c86..000000000000
--- a/include/asm-mips/hazards.h
+++ /dev/null
@@ -1,271 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 04, 07 Ralf Baechle <ralf@linux-mips.org>
- * Copyright (C) MIPS Technologies, Inc.
- *   written by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef _ASM_HAZARDS_H
-#define _ASM_HAZARDS_H
-
-#ifdef __ASSEMBLY__
-#define ASMMACRO(name, code...) .macro name; code; .endm
-#else
-
-#include <asm/cpu-features.h>
-
-#define ASMMACRO(name, code...)                                         \
-__asm__(".macro " #name "; " #code "; .endm");                          \
-                                                                        \
-static inline void name(void)                                           \
-{                                                                       \
-        __asm__ __volatile__ (#name);                                   \
-}
-
-/*
- * MIPS R2 instruction hazard barrier.   Needs to be called as a subroutine.
- */
-extern void mips_ihb(void);
-
-#endif
-
-ASMMACRO(_ssnop,
-         sll    $0, $0, 1
-        )
-
-ASMMACRO(_ehb,
-         sll    $0, $0, 3
-        )
-
-/*
- * TLB hazards
- */
-#if defined(CONFIG_CPU_MIPSR2)
-
-/*
- * MIPSR2 defines ehb for hazard avoidance
- */
-
-ASMMACRO(mtc0_tlbw_hazard,
-         _ehb
-        )
-ASMMACRO(tlbw_use_hazard,
-         _ehb
-        )
-ASMMACRO(tlb_probe_hazard,
-         _ehb
-        )
-ASMMACRO(irq_enable_hazard,
-         _ehb
-        )
-ASMMACRO(irq_disable_hazard,
-        _ehb
-        )
-ASMMACRO(back_to_back_c0_hazard,
-         _ehb
-        )
-/*
- * gcc has a tradition of misscompiling the previous construct using the
- * address of a label as argument to inline assembler.  Gas otoh has the
- * annoying difference between la and dla which are only usable for 32-bit
- * rsp. 64-bit code, so can't be used without conditional compilation.
- * The alterantive is switching the assembler to 64-bit code which happens
- * to work right even for 32-bit code ...
- */
-#define instruction_hazard()                                            \
-do {                                                                    \
-        unsigned long tmp;                                              \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    mips64r2                                \n"     \
-        "       dla     %0, 1f                                  \n"     \
-        "       jr.hb   %0                                      \n"     \
-        "       .set    mips0                                   \n"     \
-        "1:                                                     \n"     \
-        : "=r" (tmp));                                                  \
-} while (0)
-
-#elif defined(CONFIG_CPU_MIPSR1)
-
-/*
- * These are slightly complicated by the fact that we guarantee R1 kernels to
- * run fine on R2 processors.
- */
-ASMMACRO(mtc0_tlbw_hazard,
-        _ssnop; _ssnop; _ehb
-        )
-ASMMACRO(tlbw_use_hazard,
-        _ssnop; _ssnop; _ssnop; _ehb
-        )
-ASMMACRO(tlb_probe_hazard,
-         _ssnop; _ssnop; _ssnop; _ehb
-        )
-ASMMACRO(irq_enable_hazard,
-         _ssnop; _ssnop; _ssnop; _ehb
-        )
-ASMMACRO(irq_disable_hazard,
-        _ssnop; _ssnop; _ssnop; _ehb
-        )
-ASMMACRO(back_to_back_c0_hazard,
-         _ssnop; _ssnop; _ssnop; _ehb
-        )
-/*
- * gcc has a tradition of misscompiling the previous construct using the
- * address of a label as argument to inline assembler.  Gas otoh has the
- * annoying difference between la and dla which are only usable for 32-bit
- * rsp. 64-bit code, so can't be used without conditional compilation.
- * The alterantive is switching the assembler to 64-bit code which happens
- * to work right even for 32-bit code ...
- */
-#define __instruction_hazard()                                          \
-do {                                                                    \
-        unsigned long tmp;                                              \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    mips64r2                                \n"     \
-        "       dla     %0, 1f                                  \n"     \
-        "       jr.hb   %0                                      \n"     \
-        "       .set    mips0                                   \n"     \
-        "1:                                                     \n"     \
-        : "=r" (tmp));                                                  \
-} while (0)
-
-#define instruction_hazard()                                            \
-do {                                                                    \
-        if (cpu_has_mips_r2)                                            \
-                __instruction_hazard();                                 \
-} while (0)
-
-#elif defined(CONFIG_CPU_R10000)
-
-/*
- * R10000 rocks - all hazards handled in hardware, so this becomes a nobrainer.
- */
-
-ASMMACRO(mtc0_tlbw_hazard,
-        )
-ASMMACRO(tlbw_use_hazard,
-        )
-ASMMACRO(tlb_probe_hazard,
-        )
-ASMMACRO(irq_enable_hazard,
-        )
-ASMMACRO(irq_disable_hazard,
-        )
-ASMMACRO(back_to_back_c0_hazard,
-        )
-#define instruction_hazard() do { } while (0)
-
-#elif defined(CONFIG_CPU_RM9000)
-
-/*
- * RM9000 hazards.  When the JTLB is updated by tlbwi or tlbwr, a subsequent
- * use of the JTLB for instructions should not occur for 4 cpu cycles and use
- * for data translations should not occur for 3 cpu cycles.
- */
-
-ASMMACRO(mtc0_tlbw_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(tlbw_use_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(tlb_probe_hazard,
-         _ssnop; _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(irq_enable_hazard,
-        )
-ASMMACRO(irq_disable_hazard,
-        )
-ASMMACRO(back_to_back_c0_hazard,
-        )
-#define instruction_hazard() do { } while (0)
-
-#elif defined(CONFIG_CPU_SB1)
-
-/*
- * Mostly like R4000 for historic reasons
- */
-ASMMACRO(mtc0_tlbw_hazard,
-        )
-ASMMACRO(tlbw_use_hazard,
-        )
-ASMMACRO(tlb_probe_hazard,
-        )
-ASMMACRO(irq_enable_hazard,
-        )
-ASMMACRO(irq_disable_hazard,
-         _ssnop; _ssnop; _ssnop
-        )
-ASMMACRO(back_to_back_c0_hazard,
-        )
-#define instruction_hazard() do { } while (0)
-
-#else
-
-/*
- * Finally the catchall case for all other processors including R4000, R4400,
- * R4600, R4700, R5000, RM7000, NEC VR41xx etc.
- *
- * The taken branch will result in a two cycle penalty for the two killed
- * instructions on R4000 / R4400.  Other processors only have a single cycle
- * hazard so this is nice trick to have an optimal code for a range of
- * processors.
- */
-ASMMACRO(mtc0_tlbw_hazard,
-        nop; nop
-        )
-ASMMACRO(tlbw_use_hazard,
-        nop; nop; nop
-        )
-ASMMACRO(tlb_probe_hazard,
-         nop; nop; nop
-        )
-ASMMACRO(irq_enable_hazard,
-         _ssnop; _ssnop; _ssnop;
-        )
-ASMMACRO(irq_disable_hazard,
-        nop; nop; nop
-        )
-ASMMACRO(back_to_back_c0_hazard,
-         _ssnop; _ssnop; _ssnop;
-        )
-#define instruction_hazard() do { } while (0)
-
-#endif
-
-
-/* FPU hazards */
-
-#if defined(CONFIG_CPU_SB1)
-ASMMACRO(enable_fpu_hazard,
-         .set   push;
-         .set   mips64;
-         .set   noreorder;
-         _ssnop;
-         bnezl  $0, .+4;
-         _ssnop;
-         .set   pop
-)
-ASMMACRO(disable_fpu_hazard,
-)
-
-#elif defined(CONFIG_CPU_MIPSR2)
-ASMMACRO(enable_fpu_hazard,
-         _ehb
-)
-ASMMACRO(disable_fpu_hazard,
-         _ehb
-)
-#else
-ASMMACRO(enable_fpu_hazard,
-         nop; nop; nop; nop
-)
-ASMMACRO(disable_fpu_hazard,
-         _ehb
-)
-#endif
-
-#endif /* _ASM_HAZARDS_H */
diff --git a/include/asm-mips/highmem.h b/include/asm-mips/highmem.h
deleted file mode 100644
index 4374ab2adc75..000000000000
--- a/include/asm-mips/highmem.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * highmem.h: virtual kernel memory mappings for high memory
- *
- * Used in CONFIG_HIGHMEM systems for memory pages which
- * are not addressable by direct kernel virtual addresses.
- *
- * Copyright (C) 1999 Gerhard Wichert, Siemens AG
- *                    Gerhard.Wichert@pdb.siemens.de
- *
- *
- * Redesigned the x86 32-bit VM architecture to deal with
- * up to 16 Terabyte physical memory. With current x86 CPUs
- * we now support up to 64 Gigabytes physical RAM.
- *
- * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
- */
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
-
-#ifdef __KERNEL__
-
-#include <linux/init.h>
-#include <linux/interrupt.h>
-#include <linux/uaccess.h>
-#include <asm/kmap_types.h>
-
-/* undef for production */
-#define HIGHMEM_DEBUG 1
-
-/* declarations for highmem.c */
-extern unsigned long highstart_pfn, highend_pfn;
-
-extern pte_t *kmap_pte;
-extern pgprot_t kmap_prot;
-extern pte_t *pkmap_page_table;
-
-/*
- * Right now we initialize only a single pte table. It can be extended
- * easily, subsequent pte tables have to be allocated in one physical
- * chunk of RAM.
- */
-#define LAST_PKMAP 1024
-#define LAST_PKMAP_MASK (LAST_PKMAP-1)
-#define PKMAP_NR(virt)  ((virt-PKMAP_BASE) >> PAGE_SHIFT)
-#define PKMAP_ADDR(nr)  (PKMAP_BASE + ((nr) << PAGE_SHIFT))
-
-extern void * kmap_high(struct page *page);
-extern void kunmap_high(struct page *page);
-
-extern void *__kmap(struct page *page);
-extern void __kunmap(struct page *page);
-extern void *__kmap_atomic(struct page *page, enum km_type type);
-extern void __kunmap_atomic(void *kvaddr, enum km_type type);
-extern void *kmap_atomic_pfn(unsigned long pfn, enum km_type type);
-extern struct page *__kmap_atomic_to_page(void *ptr);
-
-#define kmap                    __kmap
-#define kunmap                  __kunmap
-#define kmap_atomic             __kmap_atomic
-#define kunmap_atomic           __kunmap_atomic
-#define kmap_atomic_to_page     __kmap_atomic_to_page
-
-#define flush_cache_kmaps()     flush_cache_all()
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_HIGHMEM_H */
diff --git a/include/asm-mips/hw_irq.h b/include/asm-mips/hw_irq.h
deleted file mode 100644
index aca05a43a97b..000000000000
--- a/include/asm-mips/hw_irq.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 2001, 2002 by Ralf Baechle
- */
-#ifndef __ASM_HW_IRQ_H
-#define __ASM_HW_IRQ_H
-
-#include <asm/atomic.h>
-
-extern atomic_t irq_err_count;
-
-/*
- * interrupt-retrigger: NOP for now. This may not be apropriate for all
- * machines, we'll see ...
- */
-
-#endif /* __ASM_HW_IRQ_H */
diff --git a/include/asm-mips/i8253.h b/include/asm-mips/i8253.h
deleted file mode 100644
index 5dabc870b322..000000000000
--- a/include/asm-mips/i8253.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- *  Machine specific IO port address definition for generic.
- *  Written by Osamu Tomita <tomita@cinet.co.jp>
- */
-#ifndef __ASM_I8253_H
-#define __ASM_I8253_H
-
-#include <linux/spinlock.h>
-
-/* i8253A PIT registers */
-#define PIT_MODE                0x43
-#define PIT_CH0                 0x40
-#define PIT_CH2                 0x42
-
-#define PIT_TICK_RATE           1193182UL
-
-extern spinlock_t i8253_lock;
-
-extern void setup_pit_timer(void);
-
-#endif /* __ASM_I8253_H */
diff --git a/include/asm-mips/i8259.h b/include/asm-mips/i8259.h
deleted file mode 100644
index 8572a2d90484..000000000000
--- a/include/asm-mips/i8259.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *      include/asm-mips/i8259.h
- *
- *      i8259A interrupt definitions.
- *
- *      Copyright (C) 2003  Maciej W. Rozycki
- *      Copyright (C) 2003  Ralf Baechle <ralf@linux-mips.org>
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_I8259_H
-#define _ASM_I8259_H
-
-#include <linux/compiler.h>
-#include <linux/spinlock.h>
-
-#include <asm/io.h>
-#include <irq.h>
-
-/* i8259A PIC registers */
-#define PIC_MASTER_CMD          0x20
-#define PIC_MASTER_IMR          0x21
-#define PIC_MASTER_ISR          PIC_MASTER_CMD
-#define PIC_MASTER_POLL         PIC_MASTER_ISR
-#define PIC_MASTER_OCW3         PIC_MASTER_ISR
-#define PIC_SLAVE_CMD           0xa0
-#define PIC_SLAVE_IMR           0xa1
-
-/* i8259A PIC related value */
-#define PIC_CASCADE_IR          2
-#define MASTER_ICW4_DEFAULT     0x01
-#define SLAVE_ICW4_DEFAULT      0x01
-#define PIC_ICW4_AEOI           2
-
-extern spinlock_t i8259A_lock;
-
-extern int i8259A_irq_pending(unsigned int irq);
-extern void make_8259A_irq(unsigned int irq);
-
-extern void init_i8259_irqs(void);
-
-/*
- * Do the traditional i8259 interrupt polling thing.  This is for the few
- * cases where no better interrupt acknowledge method is available and we
- * absolutely must touch the i8259.
- */
-static inline int i8259_irq(void)
-{
-        int irq;
-
-        spin_lock(&i8259A_lock);
-
-        /* Perform an interrupt acknowledge cycle on controller 1. */
-        outb(0x0C, PIC_MASTER_CMD);             /* prepare for poll */
-        irq = inb(PIC_MASTER_CMD) & 7;
-        if (irq == PIC_CASCADE_IR) {
-                /*
-                 * Interrupt is cascaded so perform interrupt
-                 * acknowledge on controller 2.
-                 */
-                outb(0x0C, PIC_SLAVE_CMD);              /* prepare for poll */
-                irq = (inb(PIC_SLAVE_CMD) & 7) + 8;
-        }
-
-        if (unlikely(irq == 7)) {
-                /*
-                 * This may be a spurious interrupt.
-                 *
-                 * Read the interrupt status register (ISR). If the most
-                 * significant bit is not set then there is no valid
-                 * interrupt.
-                 */
-                outb(0x0B, PIC_MASTER_ISR);             /* ISR register */
-                if(~inb(PIC_MASTER_ISR) & 0x80)
-                        irq = -1;
-        }
-
-        spin_unlock(&i8259A_lock);
-
-        return likely(irq >= 0) ? irq + I8259A_IRQ_BASE : irq;
-}
-
-#endif /* _ASM_I8259_H */
diff --git a/include/asm-mips/ide.h b/include/asm-mips/ide.h
deleted file mode 100644
index bb674c3b0303..000000000000
--- a/include/asm-mips/ide.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * This file contains the MIPS architecture specific IDE code.
- */
-#ifndef __ASM_IDE_H
-#define __ASM_IDE_H
-
-#include <ide.h>
-
-#endif /* __ASM_IDE_H */
diff --git a/include/asm-mips/inst.h b/include/asm-mips/inst.h
deleted file mode 100644
index 6489f00731ca..000000000000
--- a/include/asm-mips/inst.h
+++ /dev/null
@@ -1,394 +0,0 @@
-/*
- * Format of an instruction in memory.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 2000 by Ralf Baechle
- * Copyright (C) 2006 by Thiemo Seufer
- */
-#ifndef _ASM_INST_H
-#define _ASM_INST_H
-
-/*
- * Major opcodes; before MIPS IV cop1x was called cop3.
- */
-enum major_op {
-        spec_op, bcond_op, j_op, jal_op,
-        beq_op, bne_op, blez_op, bgtz_op,
-        addi_op, addiu_op, slti_op, sltiu_op,
-        andi_op, ori_op, xori_op, lui_op,
-        cop0_op, cop1_op, cop2_op, cop1x_op,
-        beql_op, bnel_op, blezl_op, bgtzl_op,
-        daddi_op, daddiu_op, ldl_op, ldr_op,
-        spec2_op, jalx_op, mdmx_op, spec3_op,
-        lb_op, lh_op, lwl_op, lw_op,
-        lbu_op, lhu_op, lwr_op, lwu_op,
-        sb_op, sh_op, swl_op, sw_op,
-        sdl_op, sdr_op, swr_op, cache_op,
-        ll_op, lwc1_op, lwc2_op, pref_op,
-        lld_op, ldc1_op, ldc2_op, ld_op,
-        sc_op, swc1_op, swc2_op, major_3b_op,
-        scd_op, sdc1_op, sdc2_op, sd_op
-};
-
-/*
- * func field of spec opcode.
- */
-enum spec_op {
-        sll_op, movc_op, srl_op, sra_op,
-        sllv_op, pmon_op, srlv_op, srav_op,
-        jr_op, jalr_op, movz_op, movn_op,
-        syscall_op, break_op, spim_op, sync_op,
-        mfhi_op, mthi_op, mflo_op, mtlo_op,
-        dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
-        mult_op, multu_op, div_op, divu_op,
-        dmult_op, dmultu_op, ddiv_op, ddivu_op,
-        add_op, addu_op, sub_op, subu_op,
-        and_op, or_op, xor_op, nor_op,
-        spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
-        dadd_op, daddu_op, dsub_op, dsubu_op,
-        tge_op, tgeu_op, tlt_op, tltu_op,
-        teq_op, spec5_unused_op, tne_op, spec6_unused_op,
-        dsll_op, spec7_unused_op, dsrl_op, dsra_op,
-        dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
-};
-
-/*
- * func field of spec2 opcode.
- */
-enum spec2_op {
-        madd_op, maddu_op, mul_op, spec2_3_unused_op,
-        msub_op, msubu_op, /* more unused ops */
-        clz_op = 0x20, clo_op,
-        dclz_op = 0x24, dclo_op,
-        sdbpp_op = 0x3f
-};
-
-/*
- * func field of spec3 opcode.
- */
-enum spec3_op {
-        ext_op, dextm_op, dextu_op, dext_op,
-        ins_op, dinsm_op, dinsu_op, dins_op,
-        bshfl_op = 0x20,
-        dbshfl_op = 0x24,
-        rdhwr_op = 0x3b
-};
-
-/*
- * rt field of bcond opcodes.
- */
-enum rt_op {
-        bltz_op, bgez_op, bltzl_op, bgezl_op,
-        spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
-        tgei_op, tgeiu_op, tlti_op, tltiu_op,
-        teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
-        bltzal_op, bgezal_op, bltzall_op, bgezall_op,
-        rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
-        rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
-        bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
-};
-
-/*
- * rs field of cop opcodes.
- */
-enum cop_op {
-        mfc_op        = 0x00, dmfc_op       = 0x01,
-        cfc_op        = 0x02, mtc_op        = 0x04,
-        dmtc_op       = 0x05, ctc_op        = 0x06,
-        bc_op         = 0x08, cop_op        = 0x10,
-        copm_op       = 0x18
-};
-
-/*
- * rt field of cop.bc_op opcodes
- */
-enum bcop_op {
-        bcf_op, bct_op, bcfl_op, bctl_op
-};
-
-/*
- * func field of cop0 coi opcodes.
- */
-enum cop0_coi_func {
-        tlbr_op       = 0x01, tlbwi_op      = 0x02,
-        tlbwr_op      = 0x06, tlbp_op       = 0x08,
-        rfe_op        = 0x10, eret_op       = 0x18
-};
-
-/*
- * func field of cop0 com opcodes.
- */
-enum cop0_com_func {
-        tlbr1_op      = 0x01, tlbw_op       = 0x02,
-        tlbp1_op      = 0x08, dctr_op       = 0x09,
-        dctw_op       = 0x0a
-};
-
-/*
- * fmt field of cop1 opcodes.
- */
-enum cop1_fmt {
-        s_fmt, d_fmt, e_fmt, q_fmt,
-        w_fmt, l_fmt
-};
-
-/*
- * func field of cop1 instructions using d, s or w format.
- */
-enum cop1_sdw_func {
-        fadd_op      =  0x00, fsub_op      =  0x01,
-        fmul_op      =  0x02, fdiv_op      =  0x03,
-        fsqrt_op     =  0x04, fabs_op      =  0x05,
-        fmov_op      =  0x06, fneg_op      =  0x07,
-        froundl_op   =  0x08, ftruncl_op   =  0x09,
-        fceill_op    =  0x0a, ffloorl_op   =  0x0b,
-        fround_op    =  0x0c, ftrunc_op    =  0x0d,
-        fceil_op     =  0x0e, ffloor_op    =  0x0f,
-        fmovc_op     =  0x11, fmovz_op     =  0x12,
-        fmovn_op     =  0x13, frecip_op    =  0x15,
-        frsqrt_op    =  0x16, fcvts_op     =  0x20,
-        fcvtd_op     =  0x21, fcvte_op     =  0x22,
-        fcvtw_op     =  0x24, fcvtl_op     =  0x25,
-        fcmp_op      =  0x30
-};
-
-/*
- * func field of cop1x opcodes (MIPS IV).
- */
-enum cop1x_func {
-        lwxc1_op     =  0x00, ldxc1_op     =  0x01,
-        pfetch_op    =  0x07, swxc1_op     =  0x08,
-        sdxc1_op     =  0x09, madd_s_op    =  0x20,
-        madd_d_op    =  0x21, madd_e_op    =  0x22,
-        msub_s_op    =  0x28, msub_d_op    =  0x29,
-        msub_e_op    =  0x2a, nmadd_s_op   =  0x30,
-        nmadd_d_op   =  0x31, nmadd_e_op   =  0x32,
-        nmsub_s_op   =  0x38, nmsub_d_op   =  0x39,
-        nmsub_e_op   =  0x3a
-};
-
-/*
- * func field for mad opcodes (MIPS IV).
- */
-enum mad_func {
-        madd_fp_op      = 0x08, msub_fp_op      = 0x0a,
-        nmadd_fp_op     = 0x0c, nmsub_fp_op     = 0x0e
-};
-
-/*
- * Damn ...  bitfields depend from byteorder :-(
- */
-#ifdef __MIPSEB__
-struct j_format {       /* Jump format */
-        unsigned int opcode : 6;
-        unsigned int target : 26;
-};
-
-struct i_format {       /* Immediate format (addi, lw, ...) */
-        unsigned int opcode : 6;
-        unsigned int rs : 5;
-        unsigned int rt : 5;
-        signed int simmediate : 16;
-};
-
-struct u_format {       /* Unsigned immediate format (ori, xori, ...) */
-        unsigned int opcode : 6;
-        unsigned int rs : 5;
-        unsigned int rt : 5;
-        unsigned int uimmediate : 16;
-};
-
-struct c_format {       /* Cache (>= R6000) format */
-        unsigned int opcode : 6;
-        unsigned int rs : 5;
-        unsigned int c_op : 3;
-        unsigned int cache : 2;
-        unsigned int simmediate : 16;
-};
-
-struct r_format {       /* Register format */
-        unsigned int opcode : 6;
-        unsigned int rs : 5;
-        unsigned int rt : 5;
-        unsigned int rd : 5;
-        unsigned int re : 5;
-        unsigned int func : 6;
-};
-
-struct p_format {       /* Performance counter format (R10000) */
-        unsigned int opcode : 6;
-        unsigned int rs : 5;
-        unsigned int rt : 5;
-        unsigned int rd : 5;
-        unsigned int re : 5;
-        unsigned int func : 6;
-};
-
-struct f_format {       /* FPU register format */
-        unsigned int opcode : 6;
-        unsigned int : 1;
-        unsigned int fmt : 4;
-        unsigned int rt : 5;
-        unsigned int rd : 5;
-        unsigned int re : 5;
-        unsigned int func : 6;
-};
-
-struct ma_format {      /* FPU multipy and add format (MIPS IV) */
-        unsigned int opcode : 6;
-        unsigned int fr : 5;
-        unsigned int ft : 5;
-        unsigned int fs : 5;
-        unsigned int fd : 5;
-        unsigned int func : 4;
-        unsigned int fmt : 2;
-};
-
-#elif defined(__MIPSEL__)
-
-struct j_format {       /* Jump format */
-        unsigned int target : 26;
-        unsigned int opcode : 6;
-};
-
-struct i_format {       /* Immediate format */
-        signed int simmediate : 16;
-        unsigned int rt : 5;
-        unsigned int rs : 5;
-        unsigned int opcode : 6;
-};
-
-struct u_format {       /* Unsigned immediate format */
-        unsigned int uimmediate : 16;
-        unsigned int rt : 5;
-        unsigned int rs : 5;
-        unsigned int opcode : 6;
-};
-
-struct c_format {       /* Cache (>= R6000) format */
-        unsigned int simmediate : 16;
-        unsigned int cache : 2;
-        unsigned int c_op : 3;
-        unsigned int rs : 5;
-        unsigned int opcode : 6;
-};
-
-struct r_format {       /* Register format */
-        unsigned int func : 6;
-        unsigned int re : 5;
-        unsigned int rd : 5;
-        unsigned int rt : 5;
-        unsigned int rs : 5;
-        unsigned int opcode : 6;
-};
-
-struct p_format {       /* Performance counter format (R10000) */
-        unsigned int func : 6;
-        unsigned int re : 5;
-        unsigned int rd : 5;
-        unsigned int rt : 5;
-        unsigned int rs : 5;
-        unsigned int opcode : 6;
-};
-
-struct f_format {       /* FPU register format */
-        unsigned int func : 6;
-        unsigned int re : 5;
-        unsigned int rd : 5;
-        unsigned int rt : 5;
-        unsigned int fmt : 4;
-        unsigned int : 1;
-        unsigned int opcode : 6;
-};
-
-struct ma_format {      /* FPU multipy and add format (MIPS IV) */
-        unsigned int fmt : 2;
-        unsigned int func : 4;
-        unsigned int fd : 5;
-        unsigned int fs : 5;
-        unsigned int ft : 5;
-        unsigned int fr : 5;
-        unsigned int opcode : 6;
-};
-
-#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
-#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
-#endif
-
-union mips_instruction {
-        unsigned int word;
-        unsigned short halfword[2];
-        unsigned char byte[4];
-        struct j_format j_format;
-        struct i_format i_format;
-        struct u_format u_format;
-        struct c_format c_format;
-        struct r_format r_format;
-        struct f_format f_format;
-        struct ma_format ma_format;
-};
-
-/* HACHACHAHCAHC ...  */
-
-/* In case some other massaging is needed, keep MIPSInst as wrapper */
-
-#define MIPSInst(x) x
-
-#define I_OPCODE_SFT    26
-#define MIPSInst_OPCODE(x) (MIPSInst(x) >> I_OPCODE_SFT)
-
-#define I_JTARGET_SFT   0
-#define MIPSInst_JTARGET(x) (MIPSInst(x) & 0x03ffffff)
-
-#define I_RS_SFT        21
-#define MIPSInst_RS(x) ((MIPSInst(x) & 0x03e00000) >> I_RS_SFT)
-
-#define I_RT_SFT        16
-#define MIPSInst_RT(x) ((MIPSInst(x) & 0x001f0000) >> I_RT_SFT)
-
-#define I_IMM_SFT       0
-#define MIPSInst_SIMM(x) ((int)((short)(MIPSInst(x) & 0xffff)))
-#define MIPSInst_UIMM(x) (MIPSInst(x) & 0xffff)
-
-#define I_CACHEOP_SFT   18
-#define MIPSInst_CACHEOP(x) ((MIPSInst(x) & 0x001c0000) >> I_CACHEOP_SFT)
-
-#define I_CACHESEL_SFT  16
-#define MIPSInst_CACHESEL(x) ((MIPSInst(x) & 0x00030000) >> I_CACHESEL_SFT)
-
-#define I_RD_SFT        11
-#define MIPSInst_RD(x) ((MIPSInst(x) & 0x0000f800) >> I_RD_SFT)
-
-#define I_RE_SFT        6
-#define MIPSInst_RE(x) ((MIPSInst(x) & 0x000007c0) >> I_RE_SFT)
-
-#define I_FUNC_SFT      0
-#define MIPSInst_FUNC(x) (MIPSInst(x) & 0x0000003f)
-
-#define I_FFMT_SFT      21
-#define MIPSInst_FFMT(x) ((MIPSInst(x) & 0x01e00000) >> I_FFMT_SFT)
-
-#define I_FT_SFT        16
-#define MIPSInst_FT(x) ((MIPSInst(x) & 0x001f0000) >> I_FT_SFT)
-
-#define I_FS_SFT        11
-#define MIPSInst_FS(x) ((MIPSInst(x) & 0x0000f800) >> I_FS_SFT)
-
-#define I_FD_SFT        6
-#define MIPSInst_FD(x) ((MIPSInst(x) & 0x000007c0) >> I_FD_SFT)
-
-#define I_FR_SFT        21
-#define MIPSInst_FR(x) ((MIPSInst(x) & 0x03e00000) >> I_FR_SFT)
-
-#define I_FMA_FUNC_SFT  2
-#define MIPSInst_FMA_FUNC(x) ((MIPSInst(x) & 0x0000003c) >> I_FMA_FUNC_SFT)
-
-#define I_FMA_FFMT_SFT  0
-#define MIPSInst_FMA_FFMT(x) (MIPSInst(x) & 0x00000003)
-
-typedef unsigned int mips_instruction;
-
-#endif /* _ASM_INST_H */
diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h
deleted file mode 100644
index 501a40b9f18d..000000000000
--- a/include/asm-mips/io.h
+++ /dev/null
@@ -1,589 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995 Waldorf GmbH
- * Copyright (C) 1994 - 2000, 06 Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2004, 2005  MIPS Technologies, Inc.  All rights reserved.
- *      Author: Maciej W. Rozycki <macro@mips.com>
- */
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
-
-#include <linux/compiler.h>
-#include <linux/kernel.h>
-#include <linux/types.h>
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-#include <asm/cpu.h>
-#include <asm/cpu-features.h>
-#include <asm-generic/iomap.h>
-#include <asm/page.h>
-#include <asm/pgtable-bits.h>
-#include <asm/processor.h>
-#include <asm/string.h>
-
-#include <ioremap.h>
-#include <mangle-port.h>
-
-/*
- * Slowdown I/O port space accesses for antique hardware.
- */
-#undef CONF_SLOWDOWN_IO
-
-/*
- * Raw operations are never swapped in software.  OTOH values that raw
- * operations are working on may or may not have been swapped by the bus
- * hardware.  An example use would be for flash memory that's used for
- * execute in place.
- */
-# define __raw_ioswabb(a, x)    (x)
-# define __raw_ioswabw(a, x)    (x)
-# define __raw_ioswabl(a, x)    (x)
-# define __raw_ioswabq(a, x)    (x)
-# define ____raw_ioswabq(a, x)  (x)
-
-/* ioswab[bwlq], __mem_ioswab[bwlq] are defined in mangle-port.h */
-
-#define IO_SPACE_LIMIT 0xffff
-
-/*
- * On MIPS I/O ports are memory mapped, so we access them using normal
- * load/store instructions. mips_io_port_base is the virtual address to
- * which all ports are being mapped.  For sake of efficiency some code
- * assumes that this is an address that can be loaded with a single lui
- * instruction, so the lower 16 bits must be zero.  Should be true on
- * on any sane architecture; generic code does not use this assumption.
- */
-extern const unsigned long mips_io_port_base;
-
-/*
- * Gcc will generate code to load the value of mips_io_port_base after each
- * function call which may be fairly wasteful in some cases.  So we don't
- * play quite by the book.  We tell gcc mips_io_port_base is a long variable
- * which solves the code generation issue.  Now we need to violate the
- * aliasing rules a little to make initialization possible and finally we
- * will need the barrier() to fight side effects of the aliasing chat.
- * This trickery will eventually collapse under gcc's optimizer.  Oh well.
- */
-static inline void set_io_port_base(unsigned long base)
-{
-        * (unsigned long *) &mips_io_port_base = base;
-        barrier();
-}
-
-/*
- * Thanks to James van Artsdalen for a better timing-fix than
- * the two short jumps: using outb's to a nonexistent port seems
- * to guarantee better timings even on fast machines.
- *
- * On the other hand, I'd like to be sure of a non-existent port:
- * I feel a bit unsafe about using 0x80 (should be safe, though)
- *
- *              Linus
- *
- */
-
-#define __SLOW_DOWN_IO \
-        __asm__ __volatile__( \
-                "sb\t$0,0x80(%0)" \
-                : : "r" (mips_io_port_base));
-
-#ifdef CONF_SLOWDOWN_IO
-#ifdef REALLY_SLOW_IO
-#define SLOW_DOWN_IO { __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; __SLOW_DOWN_IO; }
-#else
-#define SLOW_DOWN_IO __SLOW_DOWN_IO
-#endif
-#else
-#define SLOW_DOWN_IO
-#endif
-
-/*
- *     virt_to_phys    -       map virtual addresses to physical
- *     @address: address to remap
- *
- *     The returned physical address is the physical (CPU) mapping for
- *     the memory address given. It is only valid to use this function on
- *     addresses directly mapped or allocated via kmalloc.
- *
- *     This function does not give bus mappings for DMA transfers. In
- *     almost all conceivable cases a device driver should not be using
- *     this function
- */
-static inline unsigned long virt_to_phys(volatile const void *address)
-{
-        return (unsigned long)address - PAGE_OFFSET + PHYS_OFFSET;
-}
-
-/*
- *     phys_to_virt    -       map physical address to virtual
- *     @address: address to remap
- *
- *     The returned virtual address is a current CPU mapping for
- *     the memory address given. It is only valid to use this function on
- *     addresses that have a kernel mapping
- *
- *     This function does not handle bus mappings for DMA transfers. In
- *     almost all conceivable cases a device driver should not be using
- *     this function
- */
-static inline void * phys_to_virt(unsigned long address)
-{
-        return (void *)(address + PAGE_OFFSET - PHYS_OFFSET);
-}
-
-/*
- * ISA I/O bus memory addresses are 1:1 with the physical address.
- */
-static inline unsigned long isa_virt_to_bus(volatile void * address)
-{
-        return (unsigned long)address - PAGE_OFFSET;
-}
-
-static inline void * isa_bus_to_virt(unsigned long address)
-{
-        return (void *)(address + PAGE_OFFSET);
-}
-
-#define isa_page_to_bus page_to_phys
-
-/*
- * However PCI ones are not necessarily 1:1 and therefore these interfaces
- * are forbidden in portable PCI drivers.
- *
- * Allow them for x86 for legacy drivers, though.
- */
-#define virt_to_bus virt_to_phys
-#define bus_to_virt phys_to_virt
-
-/*
- * Change "struct page" to physical address.
- */
-#define page_to_phys(page)      ((dma_addr_t)page_to_pfn(page) << PAGE_SHIFT)
-
-extern void __iomem * __ioremap(phys_t offset, phys_t size, unsigned long flags);
-extern void __iounmap(const volatile void __iomem *addr);
-
-static inline void __iomem * __ioremap_mode(phys_t offset, unsigned long size,
-        unsigned long flags)
-{
-        void __iomem *addr = plat_ioremap(offset, size, flags);
-
-        if (addr)
-                return addr;
-
-#define __IS_LOW512(addr) (!((phys_t)(addr) & (phys_t) ~0x1fffffffULL))
-
-        if (cpu_has_64bit_addresses) {
-                u64 base = UNCAC_BASE;
-
-                /*
-                 * R10000 supports a 2 bit uncached attribute therefore
-                 * UNCAC_BASE may not equal IO_BASE.
-                 */
-                if (flags == _CACHE_UNCACHED)
-                        base = (u64) IO_BASE;
-                return (void __iomem *) (unsigned long) (base + offset);
-        } else if (__builtin_constant_p(offset) &&
-                   __builtin_constant_p(size) && __builtin_constant_p(flags)) {
-                phys_t phys_addr, last_addr;
-
-                phys_addr = fixup_bigphys_addr(offset, size);
-
-                /* Don't allow wraparound or zero size. */
-                last_addr = phys_addr + size - 1;
-                if (!size || last_addr < phys_addr)
-                        return NULL;
-
-                /*
-                 * Map uncached objects in the low 512MB of address
-                 * space using KSEG1.
-                 */
-                if (__IS_LOW512(phys_addr) && __IS_LOW512(last_addr) &&
-                    flags == _CACHE_UNCACHED)
-                        return (void __iomem *)
-                                (unsigned long)CKSEG1ADDR(phys_addr);
-        }
-
-        return __ioremap(offset, size, flags);
-
-#undef __IS_LOW512
-}
-
-/*
- * ioremap     -   map bus memory into CPU space
- * @offset:    bus address of the memory
- * @size:      size of the resource to map
- *
- * ioremap performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- */
-#define ioremap(offset, size)                                           \
-        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
-
-/*
- * ioremap_nocache     -   map bus memory into CPU space
- * @offset:    bus address of the memory
- * @size:      size of the resource to map
- *
- * ioremap_nocache performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- *
- * This version of ioremap ensures that the memory is marked uncachable
- * on the CPU as well as honouring existing caching rules from things like
- * the PCI bus. Note that there are other caches and buffers on many
- * busses. In paticular driver authors should read up on PCI writes
- *
- * It's useful if some control registers are in such an area and
- * write combining or read caching is not desirable:
- */
-#define ioremap_nocache(offset, size)                                   \
-        __ioremap_mode((offset), (size), _CACHE_UNCACHED)
-
-/*
- * ioremap_cachable -   map bus memory into CPU space
- * @offset:         bus address of the memory
- * @size:           size of the resource to map
- *
- * ioremap_nocache performs a platform specific sequence of operations to
- * make bus memory CPU accessible via the readb/readw/readl/writeb/
- * writew/writel functions and the other mmio helpers. The returned
- * address is not guaranteed to be usable directly as a virtual
- * address.
- *
- * This version of ioremap ensures that the memory is marked cachable by
- * the CPU.  Also enables full write-combining.  Useful for some
- * memory-like regions on I/O busses.
- */
-#define ioremap_cachable(offset, size)                                  \
-        __ioremap_mode((offset), (size), _page_cachable_default)
-
-/*
- * These two are MIPS specific ioremap variant.  ioremap_cacheable_cow
- * requests a cachable mapping, ioremap_uncached_accelerated requests a
- * mapping using the uncached accelerated mode which isn't supported on
- * all processors.
- */
-#define ioremap_cacheable_cow(offset, size)                             \
-        __ioremap_mode((offset), (size), _CACHE_CACHABLE_COW)
-#define ioremap_uncached_accelerated(offset, size)                      \
-        __ioremap_mode((offset), (size), _CACHE_UNCACHED_ACCELERATED)
-
-static inline void iounmap(const volatile void __iomem *addr)
-{
-        if (plat_iounmap(addr))
-                return;
-
-#define __IS_KSEG1(addr) (((unsigned long)(addr) & ~0x1fffffffUL) == CKSEG1)
-
-        if (cpu_has_64bit_addresses ||
-            (__builtin_constant_p(addr) && __IS_KSEG1(addr)))
-                return;
-
-        __iounmap(addr);
-
-#undef __IS_KSEG1
-}
-
-#define __BUILD_MEMORY_SINGLE(pfx, bwlq, type, irq)                     \
-                                                                        \
-static inline void pfx##write##bwlq(type val,                           \
-                                    volatile void __iomem *mem)         \
-{                                                                       \
-        volatile type *__mem;                                           \
-        type __val;                                                     \
-                                                                        \
-        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
-                                                                        \
-        __val = pfx##ioswab##bwlq(__mem, val);                          \
-                                                                        \
-        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
-                *__mem = __val;                                         \
-        else if (cpu_has_64bits) {                                      \
-                unsigned long __flags;                                  \
-                type __tmp;                                             \
-                                                                        \
-                if (irq)                                                \
-                        local_irq_save(__flags);                        \
-                __asm__ __volatile__(                                   \
-                        ".set   mips3"          "\t\t# __writeq""\n\t"  \
-                        "dsll32 %L0, %L0, 0"                    "\n\t"  \
-                        "dsrl32 %L0, %L0, 0"                    "\n\t"  \
-                        "dsll32 %M0, %M0, 0"                    "\n\t"  \
-                        "or     %L0, %L0, %M0"                  "\n\t"  \
-                        "sd     %L0, %2"                        "\n\t"  \
-                        ".set   mips0"                          "\n"    \
-                        : "=r" (__tmp)                                  \
-                        : "0" (__val), "m" (*__mem));                   \
-                if (irq)                                                \
-                        local_irq_restore(__flags);                     \
-        } else                                                          \
-                BUG();                                                  \
-}                                                                       \
-                                                                        \
-static inline type pfx##read##bwlq(const volatile void __iomem *mem)    \
-{                                                                       \
-        volatile type *__mem;                                           \
-        type __val;                                                     \
-                                                                        \
-        __mem = (void *)__swizzle_addr_##bwlq((unsigned long)(mem));    \
-                                                                        \
-        if (sizeof(type) != sizeof(u64) || sizeof(u64) == sizeof(long)) \
-                __val = *__mem;                                         \
-        else if (cpu_has_64bits) {                                      \
-                unsigned long __flags;                                  \
-                                                                        \
-                if (irq)                                                \
-                        local_irq_save(__flags);                        \
-                __asm__ __volatile__(                                   \
-                        ".set   mips3"          "\t\t# __readq" "\n\t"  \
-                        "ld     %L0, %1"                        "\n\t"  \
-                        "dsra32 %M0, %L0, 0"                    "\n\t"  \
-                        "sll    %L0, %L0, 0"                    "\n\t"  \
-                        ".set   mips0"                          "\n"    \
-                        : "=r" (__val)                                  \
-                        : "m" (*__mem));                                \
-                if (irq)                                                \
-                        local_irq_restore(__flags);                     \
-        } else {                                                        \
-                __val = 0;                                              \
-                BUG();                                                  \
-        }                                                               \
-                                                                        \
-        return pfx##ioswab##bwlq(__mem, __val);                         \
-}
-
-#define __BUILD_IOPORT_SINGLE(pfx, bwlq, type, p, slow)                 \
-                                                                        \
-static inline void pfx##out##bwlq##p(type val, unsigned long port)      \
-{                                                                       \
-        volatile type *__addr;                                          \
-        type __val;                                                     \
-                                                                        \
-        __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
-                                                                        \
-        __val = pfx##ioswab##bwlq(__addr, val);                         \
-                                                                        \
-        /* Really, we want this to be atomic */                         \
-        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
-                                                                        \
-        *__addr = __val;                                                \
-        slow;                                                           \
-}                                                                       \
-                                                                        \
-static inline type pfx##in##bwlq##p(unsigned long port)                 \
-{                                                                       \
-        volatile type *__addr;                                          \
-        type __val;                                                     \
-                                                                        \
-        __addr = (void *)__swizzle_addr_##bwlq(mips_io_port_base + port); \
-                                                                        \
-        BUILD_BUG_ON(sizeof(type) > sizeof(unsigned long));             \
-                                                                        \
-        __val = *__addr;                                                \
-        slow;                                                           \
-                                                                        \
-        return pfx##ioswab##bwlq(__addr, __val);                        \
-}
-
-#define __BUILD_MEMORY_PFX(bus, bwlq, type)                             \
-                                                                        \
-__BUILD_MEMORY_SINGLE(bus, bwlq, type, 1)
-
-#define BUILDIO_MEM(bwlq, type)                                         \
-                                                                        \
-__BUILD_MEMORY_PFX(__raw_, bwlq, type)                                  \
-__BUILD_MEMORY_PFX(, bwlq, type)                                        \
-__BUILD_MEMORY_PFX(__mem_, bwlq, type)                                  \
-
-BUILDIO_MEM(b, u8)
-BUILDIO_MEM(w, u16)
-BUILDIO_MEM(l, u32)
-BUILDIO_MEM(q, u64)
-
-#define __BUILD_IOPORT_PFX(bus, bwlq, type)                             \
-        __BUILD_IOPORT_SINGLE(bus, bwlq, type, ,)                       \
-        __BUILD_IOPORT_SINGLE(bus, bwlq, type, _p, SLOW_DOWN_IO)
-
-#define BUILDIO_IOPORT(bwlq, type)                                      \
-        __BUILD_IOPORT_PFX(, bwlq, type)                                \
-        __BUILD_IOPORT_PFX(__mem_, bwlq, type)
-
-BUILDIO_IOPORT(b, u8)
-BUILDIO_IOPORT(w, u16)
-BUILDIO_IOPORT(l, u32)
-#ifdef CONFIG_64BIT
-BUILDIO_IOPORT(q, u64)
-#endif
-
-#define __BUILDIO(bwlq, type)                                           \
-                                                                        \
-__BUILD_MEMORY_SINGLE(____raw_, bwlq, type, 0)
-
-__BUILDIO(q, u64)
-
-#define readb_relaxed                   readb
-#define readw_relaxed                   readw
-#define readl_relaxed                   readl
-#define readq_relaxed                   readq
-
-/*
- * Some code tests for these symbols
- */
-#define readq                           readq
-#define writeq                          writeq
-
-#define __BUILD_MEMORY_STRING(bwlq, type)                               \
-                                                                        \
-static inline void writes##bwlq(volatile void __iomem *mem,             \
-                                const void *addr, unsigned int count)   \
-{                                                                       \
-        const volatile type *__addr = addr;                             \
-                                                                        \
-        while (count--) {                                               \
-                __mem_write##bwlq(*__addr, mem);                        \
-                __addr++;                                               \
-        }                                                               \
-}                                                                       \
-                                                                        \
-static inline void reads##bwlq(volatile void __iomem *mem, void *addr,  \
-                               unsigned int count)                      \
-{                                                                       \
-        volatile type *__addr = addr;                                   \
-                                                                        \
-        while (count--) {                                               \
-                *__addr = __mem_read##bwlq(mem);                        \
-                __addr++;                                               \
-        }                                                               \
-}
-
-#define __BUILD_IOPORT_STRING(bwlq, type)                               \
-                                                                        \
-static inline void outs##bwlq(unsigned long port, const void *addr,     \
-                              unsigned int count)                       \
-{                                                                       \
-        const volatile type *__addr = addr;                             \
-                                                                        \
-        while (count--) {                                               \
-                __mem_out##bwlq(*__addr, port);                         \
-                __addr++;                                               \
-        }                                                               \
-}                                                                       \
-                                                                        \
-static inline void ins##bwlq(unsigned long port, void *addr,            \
-                             unsigned int count)                        \
-{                                                                       \
-        volatile type *__addr = addr;                                   \
-                                                                        \
-        while (count--) {                                               \
-                *__addr = __mem_in##bwlq(port);                         \
-                __addr++;                                               \
-        }                                                               \
-}
-
-#define BUILDSTRING(bwlq, type)                                         \
-                                                                        \
-__BUILD_MEMORY_STRING(bwlq, type)                                       \
-__BUILD_IOPORT_STRING(bwlq, type)
-
-BUILDSTRING(b, u8)
-BUILDSTRING(w, u16)
-BUILDSTRING(l, u32)
-#ifdef CONFIG_64BIT
-BUILDSTRING(q, u64)
-#endif
-
-
-/* Depends on MIPS II instruction set */
-#define mmiowb() asm volatile ("sync" ::: "memory")
-
-static inline void memset_io(volatile void __iomem *addr, unsigned char val, int count)
-{
-        memset((void __force *) addr, val, count);
-}
-static inline void memcpy_fromio(void *dst, const volatile void __iomem *src, int count)
-{
-        memcpy(dst, (void __force *) src, count);
-}
-static inline void memcpy_toio(volatile void __iomem *dst, const void *src, int count)
-{
-        memcpy((void __force *) dst, src, count);
-}
-
-/*
- * The caches on some architectures aren't dma-coherent and have need to
- * handle this in software.  There are three types of operations that
- * can be applied to dma buffers.
- *
- *  - dma_cache_wback_inv(start, size) makes caches and coherent by
- *    writing the content of the caches back to memory, if necessary.
- *    The function also invalidates the affected part of the caches as
- *    necessary before DMA transfers from outside to memory.
- *  - dma_cache_wback(start, size) makes caches and coherent by
- *    writing the content of the caches back to memory, if necessary.
- *    The function also invalidates the affected part of the caches as
- *    necessary before DMA transfers from outside to memory.
- *  - dma_cache_inv(start, size) invalidates the affected parts of the
- *    caches.  Dirty lines of the caches may be written back or simply
- *    be discarded.  This operation is necessary before dma operations
- *    to the memory.
- *
- * This API used to be exported; it now is for arch code internal use only.
- */
-#ifdef CONFIG_DMA_NONCOHERENT
-
-extern void (*_dma_cache_wback_inv)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_wback)(unsigned long start, unsigned long size);
-extern void (*_dma_cache_inv)(unsigned long start, unsigned long size);
-
-#define dma_cache_wback_inv(start, size)        _dma_cache_wback_inv(start, size)
-#define dma_cache_wback(start, size)            _dma_cache_wback(start, size)
-#define dma_cache_inv(start, size)              _dma_cache_inv(start, size)
-
-#else /* Sane hardware */
-
-#define dma_cache_wback_inv(start,size) \
-        do { (void) (start); (void) (size); } while (0)
-#define dma_cache_wback(start,size)     \
-        do { (void) (start); (void) (size); } while (0)
-#define dma_cache_inv(start,size)       \
-        do { (void) (start); (void) (size); } while (0)
-
-#endif /* CONFIG_DMA_NONCOHERENT */
-
-/*
- * Read a 32-bit register that requires a 64-bit read cycle on the bus.
- * Avoid interrupt mucking, just adjust the address for 4-byte access.
- * Assume the addresses are 8-byte aligned.
- */
-#ifdef __MIPSEB__
-#define __CSR_32_ADJUST 4
-#else
-#define __CSR_32_ADJUST 0
-#endif
-
-#define csr_out32(v, a) (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST) = (v))
-#define csr_in32(a)    (*(volatile u32 *)((unsigned long)(a) + __CSR_32_ADJUST))
-
-/*
- * Convert a physical pointer to a virtual kernel pointer for /dev/mem
- * access
- */
-#define xlate_dev_mem_ptr(p)    __va(p)
-
-/*
- * Convert a virtual cached pointer to an uncached pointer
- */
-#define xlate_dev_kmem_ptr(p)   p
-
-#endif /* _ASM_IO_H */
diff --git a/include/asm-mips/ioctl.h b/include/asm-mips/ioctl.h
deleted file mode 100644
index 85067e248a83..000000000000
--- a/include/asm-mips/ioctl.h
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 99, 2001 Ralf Baechle
- */
-#ifndef _ASM_IOCTL_H
-#define _ASM_IOCTL_H
-
-/*
- * The original linux ioctl numbering scheme was just a general
- * "anything goes" setup, where more or less random numbers were
- * assigned.  Sorry, I was clueless when I started out on this.
- *
- * On the alpha, we'll try to clean it up a bit, using a more sane
- * ioctl numbering, and also trying to be compatible with OSF/1 in
- * the process. I'd like to clean it up for the i386 as well, but
- * it's so painful recognizing both the new and the old numbers..
- *
- * The same applies for for the MIPS ABI; in fact even the macros
- * from Linux/Alpha fit almost perfectly.
- */
-
-#define _IOC_NRBITS     8
-#define _IOC_TYPEBITS   8
-#define _IOC_SIZEBITS   13
-#define _IOC_DIRBITS    3
-
-#define _IOC_NRMASK     ((1 << _IOC_NRBITS)-1)
-#define _IOC_TYPEMASK   ((1 << _IOC_TYPEBITS)-1)
-#define _IOC_SIZEMASK   ((1 << _IOC_SIZEBITS)-1)
-#define _IOC_DIRMASK    ((1 << _IOC_DIRBITS)-1)
-
-#define _IOC_NRSHIFT    0
-#define _IOC_TYPESHIFT  (_IOC_NRSHIFT+_IOC_NRBITS)
-#define _IOC_SIZESHIFT  (_IOC_TYPESHIFT+_IOC_TYPEBITS)
-#define _IOC_DIRSHIFT   (_IOC_SIZESHIFT+_IOC_SIZEBITS)
-
-/*
- * Direction bits _IOC_NONE could be 0, but OSF/1 gives it a bit.
- * And this turns out useful to catch old ioctl numbers in header
- * files for us.
- */
-#define _IOC_NONE       1U
-#define _IOC_READ       2U
-#define _IOC_WRITE      4U
-
-/*
- * The following are included for compatibility
- */
-#define _IOC_VOID       0x20000000
-#define _IOC_OUT        0x40000000
-#define _IOC_IN         0x80000000
-#define _IOC_INOUT      (IOC_IN|IOC_OUT)
-
-#define _IOC(dir, type, nr, size) \
-        (((dir)  << _IOC_DIRSHIFT) | \
-         ((type) << _IOC_TYPESHIFT) | \
-         ((nr)   << _IOC_NRSHIFT) | \
-         ((size) << _IOC_SIZESHIFT))
-
-/* provoke compile error for invalid uses of size argument */
-extern unsigned int __invalid_size_argument_for_IOC;
-#define _IOC_TYPECHECK(t) \
-        ((sizeof(t) == sizeof(t[1]) && \
-          sizeof(t) < (1 << _IOC_SIZEBITS)) ? \
-          sizeof(t) : __invalid_size_argument_for_IOC)
-
-/* used to create numbers */
-#define _IO(type, nr)           _IOC(_IOC_NONE, (type), (nr), 0)
-#define _IOR(type, nr, size)    _IOC(_IOC_READ, (type), (nr), (_IOC_TYPECHECK(size)))
-#define _IOW(type, nr, size)    _IOC(_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
-#define _IOWR(type, nr, size)   _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), (_IOC_TYPECHECK(size)))
-#define _IOR_BAD(type, nr, size)        _IOC(_IOC_READ, (type), (nr), sizeof(size))
-#define _IOW_BAD(type, nr, size)        _IOC(_IOC_WRITE, (type), (nr), sizeof(size))
-#define _IOWR_BAD(type, nr, size)       _IOC(_IOC_READ|_IOC_WRITE, (type), (nr), sizeof(size))
-
-
-/* used to decode them.. */
-#define _IOC_DIR(nr)            (((nr) >> _IOC_DIRSHIFT) & _IOC_DIRMASK)
-#define _IOC_TYPE(nr)           (((nr) >> _IOC_TYPESHIFT) & _IOC_TYPEMASK)
-#define _IOC_NR(nr)             (((nr) >> _IOC_NRSHIFT) & _IOC_NRMASK)
-#define _IOC_SIZE(nr)           (((nr) >> _IOC_SIZESHIFT) & _IOC_SIZEMASK)
-
-/* ...and for the drivers/sound files... */
-
-#define IOC_IN          (_IOC_WRITE << _IOC_DIRSHIFT)
-#define IOC_OUT         (_IOC_READ << _IOC_DIRSHIFT)
-#define IOC_INOUT       ((_IOC_WRITE|_IOC_READ) << _IOC_DIRSHIFT)
-#define IOCSIZE_MASK    (_IOC_SIZEMASK << _IOC_SIZESHIFT)
-#define IOCSIZE_SHIFT   (_IOC_SIZESHIFT)
-
-#endif /* _ASM_IOCTL_H */
diff --git a/include/asm-mips/ioctls.h b/include/asm-mips/ioctls.h
deleted file mode 100644
index 3f04a995ec54..000000000000
--- a/include/asm-mips/ioctls.h
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 2001 Ralf Baechle
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef __ASM_IOCTLS_H
-#define __ASM_IOCTLS_H
-
-#include <asm/ioctl.h>
-
-#define TCGETA          0x5401
-#define TCSETA          0x5402  /* Clashes with SNDCTL_TMR_START sound ioctl */
-#define TCSETAW         0x5403
-#define TCSETAF         0x5404
-
-#define TCSBRK          0x5405
-#define TCXONC          0x5406
-#define TCFLSH          0x5407
-
-#define TCGETS          0x540d
-#define TCSETS          0x540e
-#define TCSETSW         0x540f
-#define TCSETSF         0x5410
-
-#define TIOCEXCL        0x740d          /* set exclusive use of tty */
-#define TIOCNXCL        0x740e          /* reset exclusive use of tty */
-#define TIOCOUTQ        0x7472          /* output queue size */
-#define TIOCSTI         0x5472          /* simulate terminal input */
-#define TIOCMGET        0x741d          /* get all modem bits */
-#define TIOCMBIS        0x741b          /* bis modem bits */
-#define TIOCMBIC        0x741c          /* bic modem bits */
-#define TIOCMSET        0x741a          /* set all modem bits */
-#define TIOCPKT         0x5470          /* pty: set/clear packet mode */
-#define  TIOCPKT_DATA           0x00    /* data packet */
-#define  TIOCPKT_FLUSHREAD      0x01    /* flush packet */
-#define  TIOCPKT_FLUSHWRITE     0x02    /* flush packet */
-#define  TIOCPKT_STOP           0x04    /* stop output */
-#define  TIOCPKT_START          0x08    /* start output */
-#define  TIOCPKT_NOSTOP         0x10    /* no more ^S, ^Q */
-#define  TIOCPKT_DOSTOP         0x20    /* now do ^S ^Q */
-/* #define  TIOCPKT_IOCTL               0x40    state change of pty driver */
-#define TIOCSWINSZ      _IOW('t', 103, struct winsize)  /* set window size */
-#define TIOCGWINSZ      _IOR('t', 104, struct winsize)  /* get window size */
-#define TIOCNOTTY       0x5471          /* void tty association */
-#define TIOCSETD        0x7401
-#define TIOCGETD        0x7400
-
-#define FIOCLEX         0x6601
-#define FIONCLEX        0x6602
-#define FIOASYNC        0x667d
-#define FIONBIO         0x667e
-#define FIOQSIZE        0x667f
-
-#define TIOCGLTC        0x7474                  /* get special local chars */
-#define TIOCSLTC        0x7475                  /* set special local chars */
-#define TIOCSPGRP       _IOW('t', 118, int)     /* set pgrp of tty */
-#define TIOCGPGRP       _IOR('t', 119, int)     /* get pgrp of tty */
-#define TIOCCONS        _IOW('t', 120, int)     /* become virtual console */
-
-#define FIONREAD        0x467f
-#define TIOCINQ         FIONREAD
-
-#define TIOCGETP        0x7408
-#define TIOCSETP        0x7409
-#define TIOCSETN        0x740a                  /* TIOCSETP wo flush */
-
-/* #define TIOCSETA     _IOW('t', 20, struct termios) set termios struct */
-/* #define TIOCSETAW    _IOW('t', 21, struct termios) drain output, set */
-/* #define TIOCSETAF    _IOW('t', 22, struct termios) drn out, fls in, set */
-/* #define TIOCGETD     _IOR('t', 26, int)      get line discipline */
-/* #define TIOCSETD     _IOW('t', 27, int)      set line discipline */
-                                                /* 127-124 compat */
-
-#define TIOCSBRK        0x5427  /* BSD compatibility */
-#define TIOCCBRK        0x5428  /* BSD compatibility */
-#define TIOCGSID        0x7416  /* Return the session ID of FD */
-#define TCGETS2         _IOR('T', 0x2A, struct termios2)
-#define TCSETS2         _IOW('T', 0x2B, struct termios2)
-#define TCSETSW2        _IOW('T', 0x2C, struct termios2)
-#define TCSETSF2        _IOW('T', 0x2D, struct termios2)
-#define TIOCGPTN        _IOR('T', 0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
-#define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
-
-/* I hope the range from 0x5480 on is free ... */
-#define TIOCSCTTY       0x5480          /* become controlling tty */
-#define TIOCGSOFTCAR    0x5481
-#define TIOCSSOFTCAR    0x5482
-#define TIOCLINUX       0x5483
-#define TIOCGSERIAL     0x5484
-#define TIOCSSERIAL     0x5485
-#define TCSBRKP         0x5486  /* Needed for POSIX tcsendbreak() */
-#define TIOCSERCONFIG   0x5488
-#define TIOCSERGWILD    0x5489
-#define TIOCSERSWILD    0x548a
-#define TIOCGLCKTRMIOS  0x548b
-#define TIOCSLCKTRMIOS  0x548c
-#define TIOCSERGSTRUCT  0x548d /* For debugging only */
-#define TIOCSERGETLSR   0x548e /* Get line status register */
-#define TIOCSERGETMULTI 0x548f /* Get multiport config  */
-#define TIOCSERSETMULTI 0x5490 /* Set multiport config */
-#define TIOCMIWAIT      0x5491 /* wait for a change on serial input line(s) */
-#define TIOCGICOUNT     0x5492 /* read serial port inline interrupt counts */
-#define TIOCGHAYESESP   0x5493 /* Get Hayes ESP configuration */
-#define TIOCSHAYESESP   0x5494 /* Set Hayes ESP configuration */
-
-#endif /* __ASM_IOCTLS_H */
diff --git a/include/asm-mips/ip32/crime.h b/include/asm-mips/ip32/crime.h
deleted file mode 100644
index 7c36b0e5b1c6..000000000000
--- a/include/asm-mips/ip32/crime.h
+++ /dev/null
@@ -1,158 +0,0 @@
-/*
- * Definitions for the SGI CRIME (CPU, Rendering, Interconnect and Memory
- * Engine)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Harald Koerfgen
- */
-
-#ifndef __ASM_CRIME_H__
-#define __ASM_CRIME_H__
-
-/*
- * Address map
- */
-#define CRIME_BASE      0x14000000      /* physical */
-
-struct sgi_crime {
-        volatile unsigned long id;
-#define CRIME_ID_MASK                   0xff
-#define CRIME_ID_IDBITS                 0xf0
-#define CRIME_ID_IDVALUE                0xa0
-#define CRIME_ID_REV                    0x0f
-#define CRIME_REV_PETTY                 0x00
-#define CRIME_REV_11                    0x11
-#define CRIME_REV_13                    0x13
-#define CRIME_REV_14                    0x14
-
-        volatile unsigned long control;
-#define CRIME_CONTROL_MASK              0x3fff
-#define CRIME_CONTROL_TRITON_SYSADC     0x2000
-#define CRIME_CONTROL_CRIME_SYSADC      0x1000
-#define CRIME_CONTROL_HARD_RESET        0x0800
-#define CRIME_CONTROL_SOFT_RESET        0x0400
-#define CRIME_CONTROL_DOG_ENA           0x0200
-#define CRIME_CONTROL_ENDIANESS         0x0100
-#define CRIME_CONTROL_ENDIAN_BIG        0x0100
-#define CRIME_CONTROL_ENDIAN_LITTLE     0x0000
-#define CRIME_CONTROL_CQUEUE_HWM        0x000f
-#define CRIME_CONTROL_CQUEUE_SHFT       0
-#define CRIME_CONTROL_WBUF_HWM          0x00f0
-#define CRIME_CONTROL_WBUF_SHFT         8
-
-        volatile unsigned long istat;
-        volatile unsigned long imask;
-        volatile unsigned long soft_int;
-        volatile unsigned long hard_int;
-#define MACE_VID_IN1_INT                BIT(0)
-#define MACE_VID_IN2_INT                BIT(1)
-#define MACE_VID_OUT_INT                BIT(2)
-#define MACE_ETHERNET_INT               BIT(3)
-#define MACE_SUPERIO_INT                BIT(4)
-#define MACE_MISC_INT                   BIT(5)
-#define MACE_AUDIO_INT                  BIT(6)
-#define MACE_PCI_BRIDGE_INT             BIT(7)
-#define MACEPCI_SCSI0_INT               BIT(8)
-#define MACEPCI_SCSI1_INT               BIT(9)
-#define MACEPCI_SLOT0_INT               BIT(10)
-#define MACEPCI_SLOT1_INT               BIT(11)
-#define MACEPCI_SLOT2_INT               BIT(12)
-#define MACEPCI_SHARED0_INT             BIT(13)
-#define MACEPCI_SHARED1_INT             BIT(14)
-#define MACEPCI_SHARED2_INT             BIT(15)
-#define CRIME_GBE0_INT                  BIT(16)
-#define CRIME_GBE1_INT                  BIT(17)
-#define CRIME_GBE2_INT                  BIT(18)
-#define CRIME_GBE3_INT                  BIT(19)
-#define CRIME_CPUERR_INT                BIT(20)
-#define CRIME_MEMERR_INT                BIT(21)
-#define CRIME_RE_EMPTY_E_INT            BIT(22)
-#define CRIME_RE_FULL_E_INT             BIT(23)
-#define CRIME_RE_IDLE_E_INT             BIT(24)
-#define CRIME_RE_EMPTY_L_INT            BIT(25)
-#define CRIME_RE_FULL_L_INT             BIT(26)
-#define CRIME_RE_IDLE_L_INT             BIT(27)
-#define CRIME_SOFT0_INT                 BIT(28)
-#define CRIME_SOFT1_INT                 BIT(29)
-#define CRIME_SOFT2_INT                 BIT(30)
-#define CRIME_SYSCORERR_INT             CRIME_SOFT2_INT
-#define CRIME_VICE_INT                  BIT(31)
-/* Masks for deciding who handles the interrupt */
-#define CRIME_MACE_INT_MASK             0x8f
-#define CRIME_MACEISA_INT_MASK          0x70
-#define CRIME_MACEPCI_INT_MASK          0xff00
-#define CRIME_CRIME_INT_MASK            0xffff0000
-
-        volatile unsigned long watchdog;
-#define CRIME_DOG_POWER_ON_RESET        0x00010000
-#define CRIME_DOG_WARM_RESET            0x00080000
-#define CRIME_DOG_TIMEOUT               (CRIME_DOG_POWER_ON_RESET|CRIME_DOG_WARM_RESET)
-#define CRIME_DOG_VALUE                 0x00007fff
-
-        volatile unsigned long timer;
-#define CRIME_MASTER_FREQ               66666500        /* Crime upcounter frequency */
-#define CRIME_NS_PER_TICK               15              /* for delay_calibrate */
-
-        volatile unsigned long cpu_error_addr;
-#define CRIME_CPU_ERROR_ADDR_MASK       0x3ffffffff
-
-        volatile unsigned long cpu_error_stat;
-#define CRIME_CPU_ERROR_MASK            0x7             /* cpu error stat is 3 bits */
-#define CRIME_CPU_ERROR_CPU_ILL_ADDR    0x4
-#define CRIME_CPU_ERROR_VICE_WRT_PRTY   0x2
-#define CRIME_CPU_ERROR_CPU_WRT_PRTY    0x1
-
-        unsigned long _pad0[54];
-
-        volatile unsigned long mc_ctrl;
-        volatile unsigned long bank_ctrl[8];
-#define CRIME_MEM_BANK_CONTROL_MASK             0x11f   /* 9 bits 7:5 reserved */
-#define CRIME_MEM_BANK_CONTROL_ADDR             0x01f
-#define CRIME_MEM_BANK_CONTROL_SDRAM_SIZE       0x100
-#define CRIME_MAXBANKS                          8
-
-        volatile unsigned long mem_ref_counter;
-#define CRIME_MEM_REF_COUNTER_MASK      0x3ff           /* 10bit */
-
-        volatile unsigned long mem_error_stat;
-#define CRIME_MEM_ERROR_STAT_MASK       0x0ff7ffff      /* 28-bit register */
-#define CRIME_MEM_ERROR_MACE_ID         0x0000007f
-#define CRIME_MEM_ERROR_MACE_ACCESS     0x00000080
-#define CRIME_MEM_ERROR_RE_ID           0x00007f00
-#define CRIME_MEM_ERROR_RE_ACCESS       0x00008000
-#define CRIME_MEM_ERROR_GBE_ACCESS      0x00010000
-#define CRIME_MEM_ERROR_VICE_ACCESS     0x00020000
-#define CRIME_MEM_ERROR_CPU_ACCESS      0x00040000
-#define CRIME_MEM_ERROR_RESERVED        0x00080000
-#define CRIME_MEM_ERROR_SOFT_ERR        0x00100000
-#define CRIME_MEM_ERROR_HARD_ERR        0x00200000
-#define CRIME_MEM_ERROR_MULTIPLE        0x00400000
-#define CRIME_MEM_ERROR_ECC             0x01800000
-#define CRIME_MEM_ERROR_MEM_ECC_RD      0x00800000
-#define CRIME_MEM_ERROR_MEM_ECC_RMW     0x01000000
-#define CRIME_MEM_ERROR_INV             0x0e000000
-#define CRIME_MEM_ERROR_INV_MEM_ADDR_RD 0x02000000
-#define CRIME_MEM_ERROR_INV_MEM_ADDR_WR 0x04000000
-#define CRIME_MEM_ERROR_INV_MEM_ADDR_RMW 0x08000000
-
-        volatile unsigned long mem_error_addr;
-#define CRIME_MEM_ERROR_ADDR_MASK       0x3fffffff
-
-        volatile unsigned long mem_ecc_syn;
-#define CRIME_MEM_ERROR_ECC_SYN_MASK    0xffffffff
-
-        volatile unsigned long mem_ecc_chk;
-#define CRIME_MEM_ERROR_ECC_CHK_MASK    0xffffffff
-
-        volatile unsigned long mem_ecc_repl;
-#define CRIME_MEM_ERROR_ECC_REPL_MASK   0xffffffff
-};
-
-extern struct sgi_crime __iomem *crime;
-
-#define CRIME_HI_MEM_BASE       0x40000000      /* this is where whole 1G of RAM is mapped */
-
-#endif /* __ASM_CRIME_H__ */
diff --git a/include/asm-mips/ip32/ip32_ints.h b/include/asm-mips/ip32/ip32_ints.h
deleted file mode 100644
index 85bc5302bce0..000000000000
--- a/include/asm-mips/ip32/ip32_ints.h
+++ /dev/null
@@ -1,114 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Harald Koerfgen
- */
-
-#ifndef __ASM_IP32_INTS_H
-#define __ASM_IP32_INTS_H
-
-#include <asm/irq.h>
-
-/*
- * This list reflects the assignment of interrupt numbers to
- * interrupting events.  Order is fairly irrelevant to handling
- * priority.  This differs from irix.
- */
-
-enum ip32_irq_no {
-        /*
-         * CPU interrupts are 0 ... 7
-         */
-
-        CRIME_IRQ_BASE                  = MIPS_CPU_IRQ_BASE + 8,
-
-        /*
-         * MACE
-         */
-        MACE_VID_IN1_IRQ                = CRIME_IRQ_BASE,
-        MACE_VID_IN2_IRQ,
-        MACE_VID_OUT_IRQ,
-        MACE_ETHERNET_IRQ,
-        /* SUPERIO, MISC, and AUDIO are MACEISA */
-        __MACE_SUPERIO,
-        __MACE_MISC,
-        __MACE_AUDIO,
-        MACE_PCI_BRIDGE_IRQ,
-
-        /*
-         * MACEPCI
-         */
-        MACEPCI_SCSI0_IRQ,
-        MACEPCI_SCSI1_IRQ,
-        MACEPCI_SLOT0_IRQ,
-        MACEPCI_SLOT1_IRQ,
-        MACEPCI_SLOT2_IRQ,
-        MACEPCI_SHARED0_IRQ,
-        MACEPCI_SHARED1_IRQ,
-        MACEPCI_SHARED2_IRQ,
-
-        /*
-         * CRIME
-         */
-        CRIME_GBE0_IRQ,
-        CRIME_GBE1_IRQ,
-        CRIME_GBE2_IRQ,
-        CRIME_GBE3_IRQ,
-        CRIME_CPUERR_IRQ,
-        CRIME_MEMERR_IRQ,
-        CRIME_RE_EMPTY_E_IRQ,
-        CRIME_RE_FULL_E_IRQ,
-        CRIME_RE_IDLE_E_IRQ,
-        CRIME_RE_EMPTY_L_IRQ,
-        CRIME_RE_FULL_L_IRQ,
-        CRIME_RE_IDLE_L_IRQ,
-        CRIME_SOFT0_IRQ,
-        CRIME_SOFT1_IRQ,
-        CRIME_SOFT2_IRQ,
-        CRIME_SYSCORERR_IRQ             = CRIME_SOFT2_IRQ,
-        CRIME_VICE_IRQ,
-
-        /*
-         * MACEISA
-         */
-        MACEISA_AUDIO_SW_IRQ,
-        MACEISA_AUDIO_SC_IRQ,
-        MACEISA_AUDIO1_DMAT_IRQ,
-        MACEISA_AUDIO1_OF_IRQ,
-        MACEISA_AUDIO2_DMAT_IRQ,
-        MACEISA_AUDIO2_MERR_IRQ,
-        MACEISA_AUDIO3_DMAT_IRQ,
-        MACEISA_AUDIO3_MERR_IRQ,
-        MACEISA_RTC_IRQ,
-        MACEISA_KEYB_IRQ,
-        /* MACEISA_KEYB_POLL is not an IRQ */
-        __MACEISA_KEYB_POLL,
-        MACEISA_MOUSE_IRQ,
-        /* MACEISA_MOUSE_POLL is not an IRQ */
-        __MACEISA_MOUSE_POLL,
-        MACEISA_TIMER0_IRQ,
-        MACEISA_TIMER1_IRQ,
-        MACEISA_TIMER2_IRQ,
-        MACEISA_PARALLEL_IRQ,
-        MACEISA_PAR_CTXA_IRQ,
-        MACEISA_PAR_CTXB_IRQ,
-        MACEISA_PAR_MERR_IRQ,
-        MACEISA_SERIAL1_IRQ,
-        MACEISA_SERIAL1_TDMAT_IRQ,
-        MACEISA_SERIAL1_TDMAPR_IRQ,
-        MACEISA_SERIAL1_TDMAME_IRQ,
-        MACEISA_SERIAL1_RDMAT_IRQ,
-        MACEISA_SERIAL1_RDMAOR_IRQ,
-        MACEISA_SERIAL2_IRQ,
-        MACEISA_SERIAL2_TDMAT_IRQ,
-        MACEISA_SERIAL2_TDMAPR_IRQ,
-        MACEISA_SERIAL2_TDMAME_IRQ,
-        MACEISA_SERIAL2_RDMAT_IRQ,
-        MACEISA_SERIAL2_RDMAOR_IRQ,
-
-        IP32_IRQ_MAX                    = MACEISA_SERIAL2_RDMAOR_IRQ
-};
-
-#endif /* __ASM_IP32_INTS_H */
diff --git a/include/asm-mips/ip32/mace.h b/include/asm-mips/ip32/mace.h
deleted file mode 100644
index d08d7c672139..000000000000
--- a/include/asm-mips/ip32/mace.h
+++ /dev/null
@@ -1,365 +0,0 @@
-/*
- * Definitions for the SGI MACE (Multimedia, Audio and Communications Engine)
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Harald Koerfgen
- * Copyright (C) 2004 Ladislav Michl
- */
-
-#ifndef __ASM_MACE_H__
-#define __ASM_MACE_H__
-
-/*
- * Address map
- */
-#define MACE_BASE       0x1f000000      /* physical */
-
-/*
- * PCI interface
- */
-struct mace_pci {
-        volatile unsigned int error_addr;
-        volatile unsigned int error;
-#define MACEPCI_ERROR_MASTER_ABORT              BIT(31)
-#define MACEPCI_ERROR_TARGET_ABORT              BIT(30)
-#define MACEPCI_ERROR_DATA_PARITY_ERR           BIT(29)
-#define MACEPCI_ERROR_RETRY_ERR                 BIT(28)
-#define MACEPCI_ERROR_ILLEGAL_CMD               BIT(27)
-#define MACEPCI_ERROR_SYSTEM_ERR                BIT(26)
-#define MACEPCI_ERROR_INTERRUPT_TEST            BIT(25)
-#define MACEPCI_ERROR_PARITY_ERR                BIT(24)
-#define MACEPCI_ERROR_OVERRUN                   BIT(23)
-#define MACEPCI_ERROR_RSVD                      BIT(22)
-#define MACEPCI_ERROR_MEMORY_ADDR               BIT(21)
-#define MACEPCI_ERROR_CONFIG_ADDR               BIT(20)
-#define MACEPCI_ERROR_MASTER_ABORT_ADDR_VALID   BIT(19)
-#define MACEPCI_ERROR_TARGET_ABORT_ADDR_VALID   BIT(18)
-#define MACEPCI_ERROR_DATA_PARITY_ADDR_VALID    BIT(17)
-#define MACEPCI_ERROR_RETRY_ADDR_VALID          BIT(16)
-#define MACEPCI_ERROR_SIG_TABORT                BIT(4)
-#define MACEPCI_ERROR_DEVSEL_MASK               0xc0
-#define MACEPCI_ERROR_DEVSEL_FAST               0
-#define MACEPCI_ERROR_DEVSEL_MED                0x40
-#define MACEPCI_ERROR_DEVSEL_SLOW               0x80
-#define MACEPCI_ERROR_FBB                       BIT(1)
-#define MACEPCI_ERROR_66MHZ                     BIT(0)
-        volatile unsigned int control;
-#define MACEPCI_CONTROL_INT(x)                  BIT(x)
-#define MACEPCI_CONTROL_INT_MASK                0xff
-#define MACEPCI_CONTROL_SERR_ENA                BIT(8)
-#define MACEPCI_CONTROL_ARB_N6                  BIT(9)
-#define MACEPCI_CONTROL_PARITY_ERR              BIT(10)
-#define MACEPCI_CONTROL_MRMRA_ENA               BIT(11)
-#define MACEPCI_CONTROL_ARB_N3                  BIT(12)
-#define MACEPCI_CONTROL_ARB_N4                  BIT(13)
-#define MACEPCI_CONTROL_ARB_N5                  BIT(14)
-#define MACEPCI_CONTROL_PARK_LIU                BIT(15)
-#define MACEPCI_CONTROL_INV_INT(x)              BIT(16+x)
-#define MACEPCI_CONTROL_INV_INT_MASK            0x00ff0000
-#define MACEPCI_CONTROL_OVERRUN_INT             BIT(24)
-#define MACEPCI_CONTROL_PARITY_INT              BIT(25)
-#define MACEPCI_CONTROL_SERR_INT                BIT(26)
-#define MACEPCI_CONTROL_IT_INT                  BIT(27)
-#define MACEPCI_CONTROL_RE_INT                  BIT(28)
-#define MACEPCI_CONTROL_DPED_INT                BIT(29)
-#define MACEPCI_CONTROL_TAR_INT                 BIT(30)
-#define MACEPCI_CONTROL_MAR_INT                 BIT(31)
-        volatile unsigned int rev;
-        unsigned int _pad[0xcf8/4 - 4];
-        volatile unsigned int config_addr;
-        union {
-                volatile unsigned char b[4];
-                volatile unsigned short w[2];
-                volatile unsigned int l;
-        } config_data;
-};
-#define MACEPCI_LOW_MEMORY              0x1a000000
-#define MACEPCI_LOW_IO                  0x18000000
-#define MACEPCI_SWAPPED_VIEW            0
-#define MACEPCI_NATIVE_VIEW             0x40000000
-#define MACEPCI_IO                      0x80000000
-#define MACEPCI_HI_MEMORY               0x280000000
-#define MACEPCI_HI_IO                   0x100000000
-
-/*
- * Video interface
- */
-struct mace_video {
-        unsigned long xxx;      /* later... */
-};
-
-/*
- * Ethernet interface
- */
-struct mace_ethernet {
-        volatile unsigned long mac_ctrl;
-        volatile unsigned long int_stat;
-        volatile unsigned long dma_ctrl;
-        volatile unsigned long timer;
-        volatile unsigned long tx_int_al;
-        volatile unsigned long rx_int_al;
-        volatile unsigned long tx_info;
-        volatile unsigned long tx_info_al;
-        volatile unsigned long rx_buff;
-        volatile unsigned long rx_buff_al1;
-        volatile unsigned long rx_buff_al2;
-        volatile unsigned long diag;
-        volatile unsigned long phy_data;
-        volatile unsigned long phy_regs;
-        volatile unsigned long phy_trans_go;
-        volatile unsigned long backoff_seed;
-        /*===================================*/
-        volatile unsigned long imq_reserved[4];
-        volatile unsigned long mac_addr;
-        volatile unsigned long mac_addr2;
-        volatile unsigned long mcast_filter;
-        volatile unsigned long tx_ring_base;
-        /* Following are read-only registers for debugging */
-        volatile unsigned long tx_pkt1_hdr;
-        volatile unsigned long tx_pkt1_ptr[3];
-        volatile unsigned long tx_pkt2_hdr;
-        volatile unsigned long tx_pkt2_ptr[3];
-        /*===================================*/
-        volatile unsigned long rx_fifo;
-};
-
-/*
- * Peripherals
- */
-
-/* Audio registers */
-struct mace_audio {
-        volatile unsigned long control;
-        volatile unsigned long codec_control;           /* codec status control */
-        volatile unsigned long codec_mask;              /* codec status input mask */
-        volatile unsigned long codec_read;              /* codec status read data */
-        struct {
-                volatile unsigned long control;         /* channel control */
-                volatile unsigned long read_ptr;        /* channel read pointer */
-                volatile unsigned long write_ptr;       /* channel write pointer */
-                volatile unsigned long depth;           /* channel depth */
-        } chan[3];
-};
-
-
-/* register definitions for parallel port DMA */
-struct mace_parport {
-        /* 0 - do nothing,
-         * 1 - pulse terminal count to the device after buffer is drained */
-#define MACEPAR_CONTEXT_LASTFLAG        BIT(63)
-        /* Should not cross 4K page boundary */
-#define MACEPAR_CONTEXT_DATA_BOUND      0x0000000000001000UL
-#define MACEPAR_CONTEXT_DATALEN_MASK    0x00000fff00000000UL
-#define MACEPAR_CONTEXT_DATALEN_SHIFT   32
-        /* Can be arbitrarily aligned on any byte boundary on output,
-         * 64 byte aligned on input */
-#define MACEPAR_CONTEXT_BASEADDR_MASK   0x00000000ffffffffUL
-        volatile u64 context_a;
-        volatile u64 context_b;
-        /* 0 - mem->device, 1 - device->mem */
-#define MACEPAR_CTLSTAT_DIRECTION       BIT(0)
-        /* 0 - channel frozen, 1 - channel enabled */
-#define MACEPAR_CTLSTAT_ENABLE          BIT(1)
-        /* 0 - channel active, 1 - complete channel reset */
-#define MACEPAR_CTLSTAT_RESET           BIT(2)
-#define MACEPAR_CTLSTAT_CTXB_VALID      BIT(3)
-#define MACEPAR_CTLSTAT_CTXA_VALID      BIT(4)
-        volatile u64 cntlstat;          /* Control/Status register */
-#define MACEPAR_DIAG_CTXINUSE           BIT(0)
-        /* 1 - Dma engine is enabled and processing something */
-#define MACEPAR_DIAG_DMACTIVE           BIT(1)
-        /* Counter of bytes left */
-#define MACEPAR_DIAG_CTRMASK            0x0000000000003ffcUL
-#define MACEPAR_DIAG_CTRSHIFT           2
-        volatile u64 diagnostic;        /* RO: diagnostic register */
-};
-
-/* ISA Control and DMA registers */
-struct mace_isactrl {
-        volatile unsigned long ringbase;
-#define MACEISA_RINGBUFFERS_SIZE        (8 * 4096)
-
-        volatile unsigned long misc;
-#define MACEISA_FLASH_WE                BIT(0)  /* 1=> Enable FLASH writes */
-#define MACEISA_PWD_CLEAR               BIT(1)  /* 1=> PWD CLEAR jumper detected */
-#define MACEISA_NIC_DEASSERT            BIT(2)
-#define MACEISA_NIC_DATA                BIT(3)
-#define MACEISA_LED_RED                 BIT(4)  /* 0=> Illuminate red LED */
-#define MACEISA_LED_GREEN               BIT(5)  /* 0=> Illuminate green LED */
-#define MACEISA_DP_RAM_ENABLE           BIT(6)
-
-        volatile unsigned long istat;
-        volatile unsigned long imask;
-#define MACEISA_AUDIO_SW_INT            BIT(0)
-#define MACEISA_AUDIO_SC_INT            BIT(1)
-#define MACEISA_AUDIO1_DMAT_INT         BIT(2)
-#define MACEISA_AUDIO1_OF_INT           BIT(3)
-#define MACEISA_AUDIO2_DMAT_INT         BIT(4)
-#define MACEISA_AUDIO2_MERR_INT         BIT(5)
-#define MACEISA_AUDIO3_DMAT_INT         BIT(6)
-#define MACEISA_AUDIO3_MERR_INT         BIT(7)
-#define MACEISA_RTC_INT                 BIT(8)
-#define MACEISA_KEYB_INT                BIT(9)
-#define MACEISA_KEYB_POLL_INT           BIT(10)
-#define MACEISA_MOUSE_INT               BIT(11)
-#define MACEISA_MOUSE_POLL_INT          BIT(12)
-#define MACEISA_TIMER0_INT              BIT(13)
-#define MACEISA_TIMER1_INT              BIT(14)
-#define MACEISA_TIMER2_INT              BIT(15)
-#define MACEISA_PARALLEL_INT            BIT(16)
-#define MACEISA_PAR_CTXA_INT            BIT(17)
-#define MACEISA_PAR_CTXB_INT            BIT(18)
-#define MACEISA_PAR_MERR_INT            BIT(19)
-#define MACEISA_SERIAL1_INT             BIT(20)
-#define MACEISA_SERIAL1_TDMAT_INT       BIT(21)
-#define MACEISA_SERIAL1_TDMAPR_INT      BIT(22)
-#define MACEISA_SERIAL1_TDMAME_INT      BIT(23)
-#define MACEISA_SERIAL1_RDMAT_INT       BIT(24)
-#define MACEISA_SERIAL1_RDMAOR_INT      BIT(25)
-#define MACEISA_SERIAL2_INT             BIT(26)
-#define MACEISA_SERIAL2_TDMAT_INT       BIT(27)
-#define MACEISA_SERIAL2_TDMAPR_INT      BIT(28)
-#define MACEISA_SERIAL2_TDMAME_INT      BIT(29)
-#define MACEISA_SERIAL2_RDMAT_INT       BIT(30)
-#define MACEISA_SERIAL2_RDMAOR_INT      BIT(31)
-
-        volatile unsigned long _pad[0x2000/8 - 4];
-
-        volatile unsigned long dp_ram[0x400];
-        struct mace_parport parport;
-};
-
-/* Keyboard & Mouse registers
- * -> drivers/input/serio/maceps2.c */
-struct mace_ps2port {
-        volatile unsigned long tx;
-        volatile unsigned long rx;
-        volatile unsigned long control;
-        volatile unsigned long status;
-};
-
-struct mace_ps2 {
-        struct mace_ps2port keyb;
-        struct mace_ps2port mouse;
-};
-
-/* I2C registers
- * -> drivers/i2c/algos/i2c-algo-sgi.c */
-struct mace_i2c {
-        volatile unsigned long config;
-#define MACEI2C_RESET           BIT(0)
-#define MACEI2C_FAST            BIT(1)
-#define MACEI2C_DATA_OVERRIDE   BIT(2)
-#define MACEI2C_CLOCK_OVERRIDE  BIT(3)
-#define MACEI2C_DATA_STATUS     BIT(4)
-#define MACEI2C_CLOCK_STATUS    BIT(5)
-        volatile unsigned long control;
-        volatile unsigned long data;
-};
-
-/* Timer registers */
-typedef union {
-        volatile unsigned long ust_msc;
-        struct reg {
-                volatile unsigned int ust;
-                volatile unsigned int msc;
-        } reg;
-} timer_reg;
-
-struct mace_timers {
-        volatile unsigned long ust;
-#define MACE_UST_PERIOD_NS      960
-
-        volatile unsigned long compare1;
-        volatile unsigned long compare2;
-        volatile unsigned long compare3;
-
-        timer_reg audio_in;
-        timer_reg audio_out1;
-        timer_reg audio_out2;
-        timer_reg video_in1;
-        timer_reg video_in2;
-        timer_reg video_out;
-};
-
-struct mace_perif {
-        struct mace_audio audio;
-        char _pad0[0x10000 - sizeof(struct mace_audio)];
-
-        struct mace_isactrl ctrl;
-        char _pad1[0x10000 - sizeof(struct mace_isactrl)];
-
-        struct mace_ps2 ps2;
-        char _pad2[0x10000 - sizeof(struct mace_ps2)];
-
-        struct mace_i2c i2c;
-        char _pad3[0x10000 - sizeof(struct mace_i2c)];
-
-        struct mace_timers timers;
-        char _pad4[0x10000 - sizeof(struct mace_timers)];
-};
-
-
-/*
- * ISA peripherals
- */
-
-/* Parallel port */
-struct mace_parallel {
-};
-
-struct mace_ecp1284 {   /* later... */
-};
-
-/* Serial port */
-struct mace_serial {
-        volatile unsigned long xxx;     /* later... */
-};
-
-struct mace_isa {
-        struct mace_parallel parallel;
-        char _pad1[0x8000 - sizeof(struct mace_parallel)];
-
-        struct mace_ecp1284 ecp1284;
-        char _pad2[0x8000 - sizeof(struct mace_ecp1284)];
-
-        struct mace_serial serial1;
-        char _pad3[0x8000 - sizeof(struct mace_serial)];
-
-        struct mace_serial serial2;
-        char _pad4[0x8000 - sizeof(struct mace_serial)];
-
-        volatile unsigned char rtc[0x10000];
-};
-
-struct sgi_mace {
-        char _reserved[0x80000];
-
-        struct mace_pci pci;
-        char _pad0[0x80000 - sizeof(struct mace_pci)];
-
-        struct mace_video video_in1;
-        char _pad1[0x80000 - sizeof(struct mace_video)];
-
-        struct mace_video video_in2;
-        char _pad2[0x80000 - sizeof(struct mace_video)];
-
-        struct mace_video video_out;
-        char _pad3[0x80000 - sizeof(struct mace_video)];
-
-        struct mace_ethernet eth;
-        char _pad4[0x80000 - sizeof(struct mace_ethernet)];
-
-        struct mace_perif perif;
-        char _pad5[0x80000 - sizeof(struct mace_perif)];
-
-        struct mace_isa isa;
-        char _pad6[0x80000 - sizeof(struct mace_isa)];
-};
-
-extern struct sgi_mace __iomem *mace;
-
-#endif /* __ASM_MACE_H__ */
diff --git a/include/asm-mips/ipcbuf.h b/include/asm-mips/ipcbuf.h
deleted file mode 100644
index d47d08f264e7..000000000000
--- a/include/asm-mips/ipcbuf.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef _ASM_IPCBUF_H
-#define _ASM_IPCBUF_H
-
-/*
- * The ipc64_perm structure for alpha architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 32-bit seq
- * - 2 miscellaneous 64-bit values
- */
-
-struct ipc64_perm
-{
-        __kernel_key_t  key;
-        __kernel_uid_t  uid;
-        __kernel_gid_t  gid;
-        __kernel_uid_t  cuid;
-        __kernel_gid_t  cgid;
-        __kernel_mode_t mode;
-        unsigned short  seq;
-        unsigned short  __pad1;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-};
-
-#endif /* _ASM_IPCBUF_H */
diff --git a/include/asm-mips/irq.h b/include/asm-mips/irq.h
deleted file mode 100644
index a58f0eecc68f..000000000000
--- a/include/asm-mips/irq.h
+++ /dev/null
@@ -1,163 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
- * Copyright (C) 1995, 96, 97, 98, 99, 2000, 01, 02, 03 by Ralf Baechle
- */
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
-
-#include <linux/linkage.h>
-
-#include <asm/mipsmtregs.h>
-
-#include <irq.h>
-
-#ifdef CONFIG_I8259
-static inline int irq_canonicalize(int irq)
-{
-        return ((irq == I8259A_IRQ_BASE + 2) ? I8259A_IRQ_BASE + 9 : irq);
-}
-#else
-#define irq_canonicalize(irq) (irq)     /* Sane hardware, sane code ... */
-#endif
-
-#ifdef CONFIG_MIPS_MT_SMTC
-
-struct irqaction;
-
-extern unsigned long irq_hwmask[];
-extern int setup_irq_smtc(unsigned int irq, struct irqaction * new,
-                          unsigned long hwmask);
-
-static inline void smtc_im_ack_irq(unsigned int irq)
-{
-        if (irq_hwmask[irq] & ST0_IM)
-                set_c0_status(irq_hwmask[irq] & ST0_IM);
-}
-
-#else
-
-static inline void smtc_im_ack_irq(unsigned int irq)
-{
-}
-
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
-#include <linux/cpumask.h>
-
-extern void plat_set_irq_affinity(unsigned int irq, cpumask_t affinity);
-extern void smtc_forward_irq(unsigned int irq);
-
-/*
- * IRQ affinity hook invoked at the beginning of interrupt dispatch
- * if option is enabled.
- *
- * Up through Linux 2.6.22 (at least) cpumask operations are very
- * inefficient on MIPS.  Initial prototypes of SMTC IRQ affinity
- * used a "fast path" per-IRQ-descriptor cache of affinity information
- * to reduce latency.  As there is a project afoot to optimize the
- * cpumask implementations, this version is optimistically assuming
- * that cpumask.h macro overhead is reasonable during interrupt dispatch.
- */
-#define IRQ_AFFINITY_HOOK(irq)                                          \
-do {                                                                    \
-    if (!cpu_isset(smp_processor_id(), irq_desc[irq].affinity)) {       \
-        smtc_forward_irq(irq);                                          \
-        irq_exit();                                                     \
-        return;                                                         \
-    }                                                                   \
-} while (0)
-
-#else /* Not doing SMTC affinity */
-
-#define IRQ_AFFINITY_HOOK(irq) do { } while (0)
-
-#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
-
-#ifdef CONFIG_MIPS_MT_SMTC_IM_BACKSTOP
-
-/*
- * Clear interrupt mask handling "backstop" if irq_hwmask
- * entry so indicates. This implies that the ack() or end()
- * functions will take over re-enabling the low-level mask.
- * Otherwise it will be done on return from exception.
- */
-#define __DO_IRQ_SMTC_HOOK(irq)                                         \
-do {                                                                    \
-        IRQ_AFFINITY_HOOK(irq);                                         \
-        if (irq_hwmask[irq] & 0x0000ff00)                               \
-                write_c0_tccontext(read_c0_tccontext() &                \
-                                   ~(irq_hwmask[irq] & 0x0000ff00));    \
-} while (0)
-
-#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq)                                \
-do {                                                                    \
-        if (irq_hwmask[irq] & 0x0000ff00)                               \
-                write_c0_tccontext(read_c0_tccontext() &                \
-                                   ~(irq_hwmask[irq] & 0x0000ff00));    \
-} while (0)
-
-#else
-
-#define __DO_IRQ_SMTC_HOOK(irq)                                         \
-do {                                                                    \
-        IRQ_AFFINITY_HOOK(irq);                                         \
-} while (0)
-#define __NO_AFFINITY_IRQ_SMTC_HOOK(irq) do { } while (0)
-
-#endif
-
-/*
- * do_IRQ handles all normal device IRQ's (the special
- * SMP cross-CPU interrupts have their own specific
- * handlers).
- *
- * Ideally there should be away to get this into kernel/irq/handle.c to
- * avoid the overhead of a call for just a tiny function ...
- */
-#define do_IRQ(irq)                                                     \
-do {                                                                    \
-        irq_enter();                                                    \
-        __DO_IRQ_SMTC_HOOK(irq);                                        \
-        generic_handle_irq(irq);                                        \
-        irq_exit();                                                     \
-} while (0)
-
-#ifdef CONFIG_MIPS_MT_SMTC_IRQAFF
-/*
- * To avoid inefficient and in some cases pathological re-checking of
- * IRQ affinity, we have this variant that skips the affinity check.
- */
-
-
-#define do_IRQ_no_affinity(irq)                                         \
-do {                                                                    \
-        irq_enter();                                                    \
-        __NO_AFFINITY_IRQ_SMTC_HOOK(irq);                               \
-        generic_handle_irq(irq);                                        \
-        irq_exit();                                                     \
-} while (0)
-
-#endif /* CONFIG_MIPS_MT_SMTC_IRQAFF */
-
-extern void arch_init_irq(void);
-extern void spurious_interrupt(void);
-
-extern int allocate_irqno(void);
-extern void alloc_legacy_irqno(void);
-extern void free_irqno(unsigned int irq);
-
-/*
- * Before R2 the timer and performance counter interrupts were both fixed to
- * IE7.  Since R2 their number has to be read from the c0_intctl register.
- */
-#define CP0_LEGACY_COMPARE_IRQ 7
-
-extern int cp0_compare_irq;
-extern int cp0_perfcount_irq;
-
-#endif /* _ASM_IRQ_H */
diff --git a/include/asm-mips/irq_cpu.h b/include/asm-mips/irq_cpu.h
deleted file mode 100644
index ef6a07cddb23..000000000000
--- a/include/asm-mips/irq_cpu.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- *      include/asm-mips/irq_cpu.h
- *
- *      MIPS CPU interrupt definitions.
- *
- *      Copyright (C) 2002  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_IRQ_CPU_H
-#define _ASM_IRQ_CPU_H
-
-extern void mips_cpu_irq_init(void);
-extern void rm7k_cpu_irq_init(void);
-extern void rm9k_cpu_irq_init(void);
-
-#endif /* _ASM_IRQ_CPU_H */
diff --git a/include/asm-mips/irq_gt641xx.h b/include/asm-mips/irq_gt641xx.h
deleted file mode 100644
index f9a7c3ac2e66..000000000000
--- a/include/asm-mips/irq_gt641xx.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- *  Galileo/Marvell GT641xx IRQ definitions.
- *
- *  Copyright (C) 2007  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#ifndef _ASM_IRQ_GT641XX_H
-#define _ASM_IRQ_GT641XX_H
-
-#ifndef GT641XX_IRQ_BASE
-#define GT641XX_IRQ_BASE                8
-#endif
-
-#define GT641XX_MEMORY_OUT_OF_RANGE_IRQ         (GT641XX_IRQ_BASE + 1)
-#define GT641XX_DMA_OUT_OF_RANGE_IRQ            (GT641XX_IRQ_BASE + 2)
-#define GT641XX_CPU_ACCESS_OUT_OF_RANGE_IRQ     (GT641XX_IRQ_BASE + 3)
-#define GT641XX_DMA0_IRQ                        (GT641XX_IRQ_BASE + 4)
-#define GT641XX_DMA1_IRQ                        (GT641XX_IRQ_BASE + 5)
-#define GT641XX_DMA2_IRQ                        (GT641XX_IRQ_BASE + 6)
-#define GT641XX_DMA3_IRQ                        (GT641XX_IRQ_BASE + 7)
-#define GT641XX_TIMER0_IRQ                      (GT641XX_IRQ_BASE + 8)
-#define GT641XX_TIMER1_IRQ                      (GT641XX_IRQ_BASE + 9)
-#define GT641XX_TIMER2_IRQ                      (GT641XX_IRQ_BASE + 10)
-#define GT641XX_TIMER3_IRQ                      (GT641XX_IRQ_BASE + 11)
-#define GT641XX_PCI_0_MASTER_READ_ERROR_IRQ     (GT641XX_IRQ_BASE + 12)
-#define GT641XX_PCI_0_SLAVE_WRITE_ERROR_IRQ     (GT641XX_IRQ_BASE + 13)
-#define GT641XX_PCI_0_MASTER_WRITE_ERROR_IRQ    (GT641XX_IRQ_BASE + 14)
-#define GT641XX_PCI_0_SLAVE_READ_ERROR_IRQ      (GT641XX_IRQ_BASE + 15)
-#define GT641XX_PCI_0_ADDRESS_ERROR_IRQ         (GT641XX_IRQ_BASE + 16)
-#define GT641XX_MEMORY_ERROR_IRQ                (GT641XX_IRQ_BASE + 17)
-#define GT641XX_PCI_0_MASTER_ABORT_IRQ          (GT641XX_IRQ_BASE + 18)
-#define GT641XX_PCI_0_TARGET_ABORT_IRQ          (GT641XX_IRQ_BASE + 19)
-#define GT641XX_PCI_0_RETRY_TIMEOUT_IRQ         (GT641XX_IRQ_BASE + 20)
-#define GT641XX_CPU_INT0_IRQ                    (GT641XX_IRQ_BASE + 21)
-#define GT641XX_CPU_INT1_IRQ                    (GT641XX_IRQ_BASE + 22)
-#define GT641XX_CPU_INT2_IRQ                    (GT641XX_IRQ_BASE + 23)
-#define GT641XX_CPU_INT3_IRQ                    (GT641XX_IRQ_BASE + 24)
-#define GT641XX_CPU_INT4_IRQ                    (GT641XX_IRQ_BASE + 25)
-#define GT641XX_PCI_INT0_IRQ                    (GT641XX_IRQ_BASE + 26)
-#define GT641XX_PCI_INT1_IRQ                    (GT641XX_IRQ_BASE + 27)
-#define GT641XX_PCI_INT2_IRQ                    (GT641XX_IRQ_BASE + 28)
-#define GT641XX_PCI_INT3_IRQ                    (GT641XX_IRQ_BASE + 29)
-
-extern void gt641xx_irq_dispatch(void);
-extern void gt641xx_irq_init(void);
-
-#endif /* _ASM_IRQ_GT641XX_H */
diff --git a/include/asm-mips/irq_regs.h b/include/asm-mips/irq_regs.h
deleted file mode 100644
index 33bd2a06de57..000000000000
--- a/include/asm-mips/irq_regs.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- *
- * Copyright (C) 2006 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_IRQ_REGS_H
-#define __ASM_IRQ_REGS_H
-
-#define ARCH_HAS_OWN_IRQ_REGS
-
-#include <linux/thread_info.h>
-
-static inline struct pt_regs *get_irq_regs(void)
-{
-        return current_thread_info()->regs;
-}
-
-#endif /* __ASM_IRQ_REGS_H */
diff --git a/include/asm-mips/irqflags.h b/include/asm-mips/irqflags.h
deleted file mode 100644
index 881e8866501d..000000000000
--- a/include/asm-mips/irqflags.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003 by Ralf Baechle
- * Copyright (C) 1996 by Paul M. Antoine
- * Copyright (C) 1999 Silicon Graphics
- * Copyright (C) 2000 MIPS Technologies, Inc.
- */
-#ifndef _ASM_IRQFLAGS_H
-#define _ASM_IRQFLAGS_H
-
-#ifndef __ASSEMBLY__
-
-#include <linux/compiler.h>
-#include <asm/hazards.h>
-
-__asm__(
-        "       .macro  raw_local_irq_enable                            \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-        "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    $1, $2, 1       # SMTC - clear TCStatus.IXMT    \n"
-        "       ori     $1, 0x400                                       \n"
-        "       xori    $1, 0x400                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
-        "       ei                                                      \n"
-#else
-        "       mfc0    $1,$12                                          \n"
-        "       ori     $1,0x1f                                         \n"
-        "       xori    $1,0x1e                                         \n"
-        "       mtc0    $1,$12                                          \n"
-#endif
-        "       irq_enable_hazard                                       \n"
-        "       .set    pop                                             \n"
-        "       .endm");
-
-static inline void raw_local_irq_enable(void)
-{
-        __asm__ __volatile__(
-                "raw_local_irq_enable"
-                : /* no outputs */
-                : /* no inputs */
-                : "memory");
-}
-
-/*
- * For cli() we have to insert nops to make sure that the new value
- * has actually arrived in the status register before the end of this
- * macro.
- * R4000/R4400 need three nops, the R4600 two nops and the R10000 needs
- * no nops at all.
- */
-/*
- * For TX49, operating only IE bit is not enough.
- *
- * If mfc0 $12 follows store and the mfc0 is last instruction of a
- * page and fetching the next instruction causes TLB miss, the result
- * of the mfc0 might wrongly contain EXL bit.
- *
- * ERT-TX49H2-027, ERT-TX49H3-012, ERT-TX49HL3-006, ERT-TX49H4-008
- *
- * Workaround: mask EXL bit of the result or place a nop before mfc0.
- */
-__asm__(
-        "       .macro  raw_local_irq_disable\n"
-        "       .set    push                                            \n"
-        "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    $1, $2, 1                                       \n"
-        "       ori     $1, 0x400                                       \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
-        "       di                                                      \n"
-#else
-        "       mfc0    $1,$12                                          \n"
-        "       ori     $1,0x1f                                         \n"
-        "       xori    $1,0x1f                                         \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1,$12                                          \n"
-#endif
-        "       irq_disable_hazard                                      \n"
-        "       .set    pop                                             \n"
-        "       .endm                                                   \n");
-
-static inline void raw_local_irq_disable(void)
-{
-        __asm__ __volatile__(
-                "raw_local_irq_disable"
-                : /* no outputs */
-                : /* no inputs */
-                : "memory");
-}
-
-__asm__(
-        "       .macro  raw_local_save_flags flags                      \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    \\flags, $2, 1                                  \n"
-#else
-        "       mfc0    \\flags, $12                                    \n"
-#endif
-        "       .set    pop                                             \n"
-        "       .endm                                                   \n");
-
-#define raw_local_save_flags(x)                                         \
-__asm__ __volatile__(                                                   \
-        "raw_local_save_flags %0"                                       \
-        : "=r" (x))
-
-__asm__(
-        "       .macro  raw_local_irq_save result                       \n"
-        "       .set    push                                            \n"
-        "       .set    reorder                                         \n"
-        "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "       mfc0    \\result, $2, 1                                 \n"
-        "       ori     $1, \\result, 0x400                             \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1, $2, 1                                       \n"
-        "       andi    \\result, \\result, 0x400                       \n"
-#elif defined(CONFIG_CPU_MIPSR2)
-        "       di      \\result                                        \n"
-        "       andi    \\result, 1                                     \n"
-#else
-        "       mfc0    \\result, $12                                   \n"
-        "       ori     $1, \\result, 0x1f                              \n"
-        "       xori    $1, 0x1f                                        \n"
-        "       .set    noreorder                                       \n"
-        "       mtc0    $1, $12                                         \n"
-#endif
-        "       irq_disable_hazard                                      \n"
-        "       .set    pop                                             \n"
-        "       .endm                                                   \n");
-
-#define raw_local_irq_save(x)                                           \
-__asm__ __volatile__(                                                   \
-        "raw_local_irq_save\t%0"                                        \
-        : "=r" (x)                                                      \
-        : /* no inputs */                                               \
-        : "memory")
-
-__asm__(
-        "       .macro  raw_local_irq_restore flags                     \n"
-        "       .set    push                                            \n"
-        "       .set    noreorder                                       \n"
-        "       .set    noat                                            \n"
-#ifdef CONFIG_MIPS_MT_SMTC
-        "mfc0   $1, $2, 1                                               \n"
-        "andi   \\flags, 0x400                                          \n"
-        "ori    $1, 0x400                                               \n"
-        "xori   $1, 0x400                                               \n"
-        "or     \\flags, $1                                             \n"
-        "mtc0   \\flags, $2, 1                                          \n"
-#elif defined(CONFIG_CPU_MIPSR2) && defined(CONFIG_IRQ_CPU)
-        /*
-         * Slow, but doesn't suffer from a relativly unlikely race
-         * condition we're having since days 1.
-         */
-        "       beqz    \\flags, 1f                                     \n"
-        "        di                                                     \n"
-        "       ei                                                      \n"
-        "1:                                                             \n"
-#elif defined(CONFIG_CPU_MIPSR2)
-        /*
-         * Fast, dangerous.  Life is fun, life is good.
-         */
-        "       mfc0    $1, $12                                         \n"
-        "       ins     $1, \\flags, 0, 1                               \n"
-        "       mtc0    $1, $12                                         \n"
-#else
-        "       mfc0    $1, $12                                         \n"
-        "       andi    \\flags, 1                                      \n"
-        "       ori     $1, 0x1f                                        \n"
-        "       xori    $1, 0x1f                                        \n"
-        "       or      \\flags, $1                                     \n"
-        "       mtc0    \\flags, $12                                    \n"
-#endif
-        "       irq_disable_hazard                                      \n"
-        "       .set    pop                                             \n"
-        "       .endm                                                   \n");
-
-extern void smtc_ipi_replay(void);
-
-static inline void raw_local_irq_restore(unsigned long flags)
-{
-        unsigned long __tmp1;
-
-#ifdef CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY
-        /*
-         * CONFIG_MIPS_MT_SMTC_INSTANT_REPLAY does prompt replay of deferred
-         * IPIs, at the cost of branch and call overhead on each
-         * local_irq_restore()
-         */
-        if (unlikely(!(flags & 0x0400)))
-                smtc_ipi_replay();
-#endif
-
-        __asm__ __volatile__(
-                "raw_local_irq_restore\t%0"
-                : "=r" (__tmp1)
-                : "0" (flags)
-                : "memory");
-}
-
-static inline int raw_irqs_disabled_flags(unsigned long flags)
-{
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         * SMTC model uses TCStatus.IXMT to disable interrupts for a thread/CPU
-         */
-        return flags & 0x400;
-#else
-        return !(flags & 1);
-#endif
-}
-
-#endif
-
-/*
- * Do the CPU's IRQ-state tracing from assembly code.
- */
-#ifdef CONFIG_TRACE_IRQFLAGS
-/* Reload some registers clobbered by trace_hardirqs_on */
-#ifdef CONFIG_64BIT
-# define TRACE_IRQS_RELOAD_REGS                                         \
-        LONG_L  $11, PT_R11(sp);                                        \
-        LONG_L  $10, PT_R10(sp);                                        \
-        LONG_L  $9, PT_R9(sp);                                          \
-        LONG_L  $8, PT_R8(sp);                                          \
-        LONG_L  $7, PT_R7(sp);                                          \
-        LONG_L  $6, PT_R6(sp);                                          \
-        LONG_L  $5, PT_R5(sp);                                          \
-        LONG_L  $4, PT_R4(sp);                                          \
-        LONG_L  $2, PT_R2(sp)
-#else
-# define TRACE_IRQS_RELOAD_REGS                                         \
-        LONG_L  $7, PT_R7(sp);                                          \
-        LONG_L  $6, PT_R6(sp);                                          \
-        LONG_L  $5, PT_R5(sp);                                          \
-        LONG_L  $4, PT_R4(sp);                                          \
-        LONG_L  $2, PT_R2(sp)
-#endif
-# define TRACE_IRQS_ON                                                  \
-        CLI;    /* make sure trace_hardirqs_on() is called in kernel level */ \
-        jal     trace_hardirqs_on
-# define TRACE_IRQS_ON_RELOAD                                           \
-        TRACE_IRQS_ON;                                                  \
-        TRACE_IRQS_RELOAD_REGS
-# define TRACE_IRQS_OFF                                                 \
-        jal     trace_hardirqs_off
-#else
-# define TRACE_IRQS_ON
-# define TRACE_IRQS_ON_RELOAD
-# define TRACE_IRQS_OFF
-#endif
-
-#endif /* _ASM_IRQFLAGS_H */
diff --git a/include/asm-mips/isadep.h b/include/asm-mips/isadep.h
deleted file mode 100644
index 24c6cda79377..000000000000
--- a/include/asm-mips/isadep.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Various ISA level dependent constants.
- * Most of the following constants reflect the different layout
- * of Coprocessor 0 registers.
- *
- * Copyright (c) 1998 Harald Koerfgen
- */
-
-#ifndef __ASM_ISADEP_H
-#define __ASM_ISADEP_H
-
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-/*
- * R2000 or R3000
- */
-
-/*
- * kernel or user mode? (CP0_STATUS)
- */
-#define KU_MASK 0x08
-#define KU_USER 0x08
-#define KU_KERN 0x00
-
-#else
-/*
- * kernel or user mode?
- */
-#define KU_MASK 0x18
-#define KU_USER 0x10
-#define KU_KERN 0x00
-
-#endif
-
-#endif /* __ASM_ISADEP_H */
diff --git a/include/asm-mips/jazz.h b/include/asm-mips/jazz.h
deleted file mode 100644
index 83f449dec95e..000000000000
--- a/include/asm-mips/jazz.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995 - 1998 by Andreas Busse and Ralf Baechle
- */
-#ifndef __ASM_JAZZ_H
-#define __ASM_JAZZ_H
-
-/*
- * The addresses below are virtual address. The mappings are
- * created on startup via wired entries in the tlb. The Mips
- * Magnum R3000 and R4000 machines are similar in many aspects,
- * but many hardware register are accessible at 0xb9000000 in
- * instead of 0xe0000000.
- */
-
-#define JAZZ_LOCAL_IO_SPACE     0xe0000000
-
-/*
- * Revision numbers in PICA_ASIC_REVISION
- *
- * 0xf0000000 - Rev1
- * 0xf0000001 - Rev2
- * 0xf0000002 - Rev3
- */
-#define PICA_ASIC_REVISION      0xe0000008
-
-/*
- * The segments of the seven segment LED are mapped
- * to the control bits as follows:
- *
- *         (7)
- *      ---------
- *      |       |
- *  (2) |       | (6)
- *      |  (1)  |
- *      ---------
- *      |       |
- *  (3) |       | (5)
- *      |  (4)  |
- *      --------- . (0)
- */
-#define PICA_LED                0xe000f000
-
-/*
- * Some characters for the LED control registers
- * The original Mips machines seem to have a LED display
- * with integrated decoder while the Acer machines can
- * control each of the seven segments and the dot independently.
- * It's only a toy, anyway...
- */
-#define LED_DOT                 0x01
-#define LED_SPACE               0x00
-#define LED_0                   0xfc
-#define LED_1                   0x60
-#define LED_2                   0xda
-#define LED_3                   0xf2
-#define LED_4                   0x66
-#define LED_5                   0xb6
-#define LED_6                   0xbe
-#define LED_7                   0xe0
-#define LED_8                   0xfe
-#define LED_9                   0xf6
-#define LED_A                   0xee
-#define LED_b                   0x3e
-#define LED_C                   0x9c
-#define LED_d                   0x7a
-#define LED_E                   0x9e
-#define LED_F                   0x8e
-
-#ifndef __ASSEMBLY__
-
-static __inline__ void pica_set_led(unsigned int bits)
-{
-        volatile unsigned int *led_register = (unsigned int *) PICA_LED;
-
-        *led_register = bits;
-}
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Base address of the Sonic Ethernet adapter in Jazz machines.
- */
-#define JAZZ_ETHERNET_BASE  0xe0001000
-
-/*
- * Base address of the 53C94 SCSI hostadapter in Jazz machines.
- */
-#define JAZZ_SCSI_BASE          0xe0002000
-
-/*
- * i8042 keyboard controller for JAZZ and PICA chipsets.
- * This address is just a guess and seems to differ from
- * other mips machines such as RC3xxx...
- */
-#define JAZZ_KEYBOARD_ADDRESS   0xe0005000
-#define JAZZ_KEYBOARD_DATA      0xe0005000
-#define JAZZ_KEYBOARD_COMMAND   0xe0005001
-
-#ifndef __ASSEMBLY__
-
-typedef struct {
-        unsigned char data;
-        unsigned char command;
-} jazz_keyboard_hardware;
-
-#define jazz_kh ((keyboard_hardware *) JAZZ_KEYBOARD_ADDRESS)
-
-typedef struct {
-        unsigned char pad0[3];
-        unsigned char data;
-        unsigned char pad1[3];
-        unsigned char command;
-} mips_keyboard_hardware;
-
-/*
- * For now. Needs to be changed for RC3xxx support. See below.
- */
-#define keyboard_hardware       jazz_keyboard_hardware
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * i8042 keyboard controller for most other Mips machines.
- */
-#define MIPS_KEYBOARD_ADDRESS   0xb9005000
-#define MIPS_KEYBOARD_DATA      0xb9005003
-#define MIPS_KEYBOARD_COMMAND   0xb9005007
-
-/*
- * Serial and parallel ports (WD 16C552) on the Mips JAZZ
- */
-#define JAZZ_SERIAL1_BASE       (unsigned int)0xe0006000
-#define JAZZ_SERIAL2_BASE       (unsigned int)0xe0007000
-#define JAZZ_PARALLEL_BASE      (unsigned int)0xe0008000
-
-/*
- * Dummy Device Address. Used in jazzdma.c
- */
-#define JAZZ_DUMMY_DEVICE       0xe000d000
-
-/*
- * JAZZ timer registers and interrupt no.
- * Note that the hardware timer interrupt is actually on
- * cpu level 6, but to keep compatibility with PC stuff
- * it is remapped to vector 0. See arch/mips/kernel/entry.S.
- */
-#define JAZZ_TIMER_INTERVAL     0xe0000228
-#define JAZZ_TIMER_REGISTER     0xe0000230
-
-/*
- * DRAM configuration register
- */
-#ifndef __ASSEMBLY__
-#ifdef __MIPSEL__
-typedef struct {
-        unsigned int bank2 : 3;
-        unsigned int bank1 : 3;
-        unsigned int mem_bus_width : 1;
-        unsigned int reserved2 : 1;
-        unsigned int page_mode : 1;
-        unsigned int reserved1 : 23;
-} dram_configuration;
-#else /* defined (__MIPSEB__) */
-typedef struct {
-        unsigned int reserved1 : 23;
-        unsigned int page_mode : 1;
-        unsigned int reserved2 : 1;
-        unsigned int mem_bus_width : 1;
-        unsigned int bank1 : 3;
-        unsigned int bank2 : 3;
-} dram_configuration;
-#endif
-#endif /* !__ASSEMBLY__ */
-
-#define PICA_DRAM_CONFIG        0xe00fffe0
-
-/*
- * JAZZ interrupt control registers
- */
-#define JAZZ_IO_IRQ_SOURCE      0xe0010000
-#define JAZZ_IO_IRQ_ENABLE      0xe0010002
-
-/*
- * JAZZ Interrupt Level definitions
- *
- * This is somewhat broken.  For reasons which nobody can remember anymore
- * we remap the Jazz interrupts to the usual ISA style interrupt numbers.
- */
-#define JAZZ_IRQ_START          24
-#define JAZZ_IRQ_END            (24 + 9)
-#define JAZZ_PARALLEL_IRQ       (JAZZ_IRQ_START + 0)
-#define JAZZ_FLOPPY_IRQ         (JAZZ_IRQ_START + 1)
-#define JAZZ_SOUND_IRQ          (JAZZ_IRQ_START + 2)
-#define JAZZ_VIDEO_IRQ          (JAZZ_IRQ_START + 3)
-#define JAZZ_ETHERNET_IRQ       (JAZZ_IRQ_START + 4)
-#define JAZZ_SCSI_IRQ           (JAZZ_IRQ_START + 5)
-#define JAZZ_KEYBOARD_IRQ       (JAZZ_IRQ_START + 6)
-#define JAZZ_MOUSE_IRQ          (JAZZ_IRQ_START + 7)
-#define JAZZ_SERIAL1_IRQ        (JAZZ_IRQ_START + 8)
-#define JAZZ_SERIAL2_IRQ        (JAZZ_IRQ_START + 9)
-
-#define JAZZ_TIMER_IRQ          (MIPS_CPU_IRQ_BASE+6)
-
-
-/*
- * JAZZ DMA Channels
- * Note: Channels 4...7 are not used with respect to the Acer PICA-61
- * chipset which does not provide these DMA channels.
- */
-#define JAZZ_SCSI_DMA           0              /* SCSI */
-#define JAZZ_FLOPPY_DMA         1              /* FLOPPY */
-#define JAZZ_AUDIOL_DMA         2              /* AUDIO L */
-#define JAZZ_AUDIOR_DMA         3              /* AUDIO R */
-
-/*
- * JAZZ R4030 MCT_ADR chip (DMA controller)
- * Note: Virtual Addresses !
- */
-#define JAZZ_R4030_CONFIG       0xE0000000      /* R4030 config register */
-#define JAZZ_R4030_REVISION     0xE0000008      /* same as PICA_ASIC_REVISION */
-#define JAZZ_R4030_INV_ADDR     0xE0000010      /* Invalid Address register */
-
-#define JAZZ_R4030_TRSTBL_BASE  0xE0000018      /* Translation Table Base */
-#define JAZZ_R4030_TRSTBL_LIM   0xE0000020      /* Translation Table Limit */
-#define JAZZ_R4030_TRSTBL_INV   0xE0000028      /* Translation Table Invalidate */
-
-#define JAZZ_R4030_CACHE_MTNC   0xE0000030      /* Cache Maintenance */
-#define JAZZ_R4030_R_FAIL_ADDR  0xE0000038      /* Remote Failed Address */
-#define JAZZ_R4030_M_FAIL_ADDR  0xE0000040      /* Memory Failed Address */
-
-#define JAZZ_R4030_CACHE_PTAG   0xE0000048      /* I/O Cache Physical Tag */
-#define JAZZ_R4030_CACHE_LTAG   0xE0000050      /* I/O Cache Logical Tag */
-#define JAZZ_R4030_CACHE_BMASK  0xE0000058      /* I/O Cache Byte Mask */
-#define JAZZ_R4030_CACHE_BWIN   0xE0000060      /* I/O Cache Buffer Window */
-
-/*
- * Remote Speed Registers.
- *
- *  0: free,      1: Ethernet,  2: SCSI,      3: Floppy,
- *  4: RTC,       5: Kb./Mouse  6: serial 1,  7: serial 2,
- *  8: parallel,  9: NVRAM,    10: CPU,      11: PROM,
- * 12: reserved, 13: free,     14: 7seg LED, 15: ???
- */
-#define JAZZ_R4030_REM_SPEED    0xE0000070      /* 16 Remote Speed Registers */
-                                                /* 0xE0000070,78,80... 0xE00000E8 */
-#define JAZZ_R4030_IRQ_ENABLE   0xE00000E8      /* Internal Interrupt Enable */
-#define JAZZ_R4030_INVAL_ADDR   0xE0000010      /* Invalid address Register */
-#define JAZZ_R4030_IRQ_SOURCE   0xE0000200      /* Interrupt Source Register */
-#define JAZZ_R4030_I386_ERROR   0xE0000208      /* i386/EISA Bus Error */
-
-/*
- * Virtual (E)ISA controller address
- */
-#define JAZZ_EISA_IRQ_ACK       0xE0000238      /* EISA interrupt acknowledge */
-
-/*
- * Access the R4030 DMA and I/O Controller
- */
-#ifndef __ASSEMBLY__
-
-static inline void r4030_delay(void)
-{
-__asm__ __volatile__(
-        ".set\tnoreorder\n\t"
-        "nop\n\t"
-        "nop\n\t"
-        "nop\n\t"
-        "nop\n\t"
-        ".set\treorder");
-}
-
-static inline unsigned short r4030_read_reg16(unsigned long addr)
-{
-        unsigned short ret = *((volatile unsigned short *)addr);
-        r4030_delay();
-        return ret;
-}
-
-static inline unsigned int r4030_read_reg32(unsigned long addr)
-{
-        unsigned int ret = *((volatile unsigned int *)addr);
-        r4030_delay();
-        return ret;
-}
-
-static inline void r4030_write_reg16(unsigned long addr, unsigned val)
-{
-        *((volatile unsigned short *)addr) = val;
-        r4030_delay();
-}
-
-static inline void r4030_write_reg32(unsigned long addr, unsigned val)
-{
-        *((volatile unsigned int *)addr) = val;
-        r4030_delay();
-}
-
-#endif /* !__ASSEMBLY__ */
-
-#define JAZZ_FDC_BASE   0xe0003000
-#define JAZZ_RTC_BASE   0xe0004000
-#define JAZZ_PORT_BASE  0xe2000000
-
-#define JAZZ_EISA_BASE  0xe3000000
-
-#endif /* __ASM_JAZZ_H */
diff --git a/include/asm-mips/jazzdma.h b/include/asm-mips/jazzdma.h
deleted file mode 100644
index 8bb37bba68f0..000000000000
--- a/include/asm-mips/jazzdma.h
+++ /dev/null
@@ -1,95 +0,0 @@
-/*
- * Helpfile for jazzdma.c -- Mips Jazz R4030 DMA controller support
- */
-#ifndef _ASM_JAZZDMA_H
-#define _ASM_JAZZDMA_H
-
-/*
- * Prototypes and macros
- */
-extern unsigned long vdma_alloc(unsigned long paddr, unsigned long size);
-extern int vdma_free(unsigned long laddr);
-extern int vdma_remap(unsigned long laddr, unsigned long paddr,
-                      unsigned long size);
-extern unsigned long vdma_phys2log(unsigned long paddr);
-extern unsigned long vdma_log2phys(unsigned long laddr);
-extern void vdma_stats(void);           /* for debugging only */
-
-extern void vdma_enable(int channel);
-extern void vdma_disable(int channel);
-extern void vdma_set_mode(int channel, int mode);
-extern void vdma_set_addr(int channel, long addr);
-extern void vdma_set_count(int channel, int count);
-extern int vdma_get_residue(int channel);
-extern int vdma_get_enable(int channel);
-
-/*
- * some definitions used by the driver functions
- */
-#define VDMA_PAGESIZE           4096
-#define VDMA_PGTBL_ENTRIES      4096
-#define VDMA_PGTBL_SIZE         (sizeof(VDMA_PGTBL_ENTRY) * VDMA_PGTBL_ENTRIES)
-#define VDMA_PAGE_EMPTY         0xff000000
-
-/*
- * Macros to get page no. and offset of a given address
- * Note that VDMA_PAGE() works for physical addresses only
- */
-#define VDMA_PAGE(a)            ((unsigned int)(a) >> 12)
-#define VDMA_OFFSET(a)          ((unsigned int)(a) & (VDMA_PAGESIZE-1))
-
-/*
- * error code returned by vdma_alloc()
- * (See also arch/mips/kernel/jazzdma.c)
- */
-#define VDMA_ERROR              0xffffffff
-
-/*
- * VDMA pagetable entry description
- */
-typedef volatile struct VDMA_PGTBL_ENTRY {
-        unsigned int frame;             /* physical frame no. */
-        unsigned int owner;             /* owner of this entry (0=free) */
-} VDMA_PGTBL_ENTRY;
-
-
-/*
- * DMA channel control registers
- * in the R4030 MCT_ADR chip
- */
-#define JAZZ_R4030_CHNL_MODE    0xE0000100      /* 8 DMA Channel Mode Registers, */
-                                                /* 0xE0000100,120,140... */
-#define JAZZ_R4030_CHNL_ENABLE  0xE0000108      /* 8 DMA Channel Enable Regs, */
-                                                /* 0xE0000108,128,148... */
-#define JAZZ_R4030_CHNL_COUNT   0xE0000110      /* 8 DMA Channel Byte Cnt Regs, */
-                                                /* 0xE0000110,130,150... */
-#define JAZZ_R4030_CHNL_ADDR    0xE0000118      /* 8 DMA Channel Address Regs, */
-                                                /* 0xE0000118,138,158... */
-
-/* channel enable register bits */
-
-#define R4030_CHNL_ENABLE        (1<<0)
-#define R4030_CHNL_WRITE         (1<<1)
-#define R4030_TC_INTR            (1<<8)
-#define R4030_MEM_INTR           (1<<9)
-#define R4030_ADDR_INTR          (1<<10)
-
-/*
- * Channel mode register bits
- */
-#define R4030_MODE_ATIME_40      (0) /* device access time on remote bus */
-#define R4030_MODE_ATIME_80      (1)
-#define R4030_MODE_ATIME_120     (2)
-#define R4030_MODE_ATIME_160     (3)
-#define R4030_MODE_ATIME_200     (4)
-#define R4030_MODE_ATIME_240     (5)
-#define R4030_MODE_ATIME_280     (6)
-#define R4030_MODE_ATIME_320     (7)
-#define R4030_MODE_WIDTH_8       (1<<3) /* device data bus width */
-#define R4030_MODE_WIDTH_16      (2<<3)
-#define R4030_MODE_WIDTH_32      (3<<3)
-#define R4030_MODE_INTR_EN       (1<<5)
-#define R4030_MODE_BURST         (1<<6) /* Rev. 2 only */
-#define R4030_MODE_FAST_ACK      (1<<7) /* Rev. 2 only */
-
-#endif /* _ASM_JAZZDMA_H */
diff --git a/include/asm-mips/kdebug.h b/include/asm-mips/kdebug.h
deleted file mode 100644
index 5bf62aafc890..000000000000
--- a/include/asm-mips/kdebug.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_MIPS_KDEBUG_H
-#define _ASM_MIPS_KDEBUG_H
-
-#include <linux/notifier.h>
-
-enum die_val {
-        DIE_OOPS = 1,
-        DIE_FP,
-        DIE_TRAP,
-        DIE_RI,
-};
-
-#endif /* _ASM_MIPS_KDEBUG_H */
diff --git a/include/asm-mips/kexec.h b/include/asm-mips/kexec.h
deleted file mode 100644
index 4314892aaebb..000000000000
--- a/include/asm-mips/kexec.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * kexec.h for kexec
- * Created by <nschichan@corp.free.fr> on Thu Oct 12 14:59:34 2006
- *
- * This source code is licensed under the GNU General Public License,
- * Version 2.  See the file COPYING for more details.
- */
-
-#ifndef _MIPS_KEXEC
-# define _MIPS_KEXEC
-
-/* Maximum physical address we can use pages from */
-#define KEXEC_SOURCE_MEMORY_LIMIT (0x20000000)
-/* Maximum address we can reach in physical address mode */
-#define KEXEC_DESTINATION_MEMORY_LIMIT (0x20000000)
- /* Maximum address we can use for the control code buffer */
-#define KEXEC_CONTROL_MEMORY_LIMIT (0x20000000)
-
-#define KEXEC_CONTROL_PAGE_SIZE 4096
-
-/* The native architecture */
-#define KEXEC_ARCH KEXEC_ARCH_MIPS
-
-static inline void crash_setup_regs(struct pt_regs *newregs,
-                                    struct pt_regs *oldregs)
-{
-        /* Dummy implementation for now */
-}
-
-#endif /* !_MIPS_KEXEC */
diff --git a/include/asm-mips/kgdb.h b/include/asm-mips/kgdb.h
deleted file mode 100644
index 48223b09396c..000000000000
--- a/include/asm-mips/kgdb.h
+++ /dev/null
@@ -1,44 +0,0 @@
-#ifndef __ASM_KGDB_H_
-#define __ASM_KGDB_H_
-
-#ifdef __KERNEL__
-
-#include <asm/sgidefs.h>
-
-#if (_MIPS_ISA == _MIPS_ISA_MIPS1) || (_MIPS_ISA == _MIPS_ISA_MIPS2) || \
-        (_MIPS_ISA == _MIPS_ISA_MIPS32)
-
-#define KGDB_GDB_REG_SIZE 32
-
-#elif (_MIPS_ISA == _MIPS_ISA_MIPS3) || (_MIPS_ISA == _MIPS_ISA_MIPS4) || \
-        (_MIPS_ISA == _MIPS_ISA_MIPS64)
-
-#ifdef CONFIG_32BIT
-#define KGDB_GDB_REG_SIZE 32
-#else /* CONFIG_CPU_32BIT */
-#define KGDB_GDB_REG_SIZE 64
-#endif
-#else
-#error "Need to set KGDB_GDB_REG_SIZE for MIPS ISA"
-#endif /* _MIPS_ISA */
-
-#define BUFMAX                  2048
-#if (KGDB_GDB_REG_SIZE == 32)
-#define NUMREGBYTES             (90*sizeof(u32))
-#define NUMCRITREGBYTES         (12*sizeof(u32))
-#else
-#define NUMREGBYTES             (90*sizeof(u64))
-#define NUMCRITREGBYTES         (12*sizeof(u64))
-#endif
-#define BREAK_INSTR_SIZE        4
-#define CACHE_FLUSH_IS_SAFE     0
-
-extern void arch_kgdb_breakpoint(void);
-extern int kgdb_early_setup;
-extern void *saved_vectors[32];
-extern void handle_exception(struct pt_regs *regs);
-extern void breakinst(void);
-
-#endif                          /* __KERNEL__ */
-
-#endif /* __ASM_KGDB_H_ */
diff --git a/include/asm-mips/kmap_types.h b/include/asm-mips/kmap_types.h
deleted file mode 100644
index 806aae3c5338..000000000000
--- a/include/asm-mips/kmap_types.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef _ASM_KMAP_TYPES_H
-#define _ASM_KMAP_TYPES_H
-
-
-#ifdef CONFIG_DEBUG_HIGHMEM
-# define D(n) __KM_FENCE_##n ,
-#else
-# define D(n)
-#endif
-
-enum km_type {
-D(0)    KM_BOUNCE_READ,
-D(1)    KM_SKB_SUNRPC_DATA,
-D(2)    KM_SKB_DATA_SOFTIRQ,
-D(3)    KM_USER0,
-D(4)    KM_USER1,
-D(5)    KM_BIO_SRC_IRQ,
-D(6)    KM_BIO_DST_IRQ,
-D(7)    KM_PTE0,
-D(8)    KM_PTE1,
-D(9)    KM_IRQ0,
-D(10)   KM_IRQ1,
-D(11)   KM_SOFTIRQ0,
-D(12)   KM_SOFTIRQ1,
-D(13)   KM_TYPE_NR
-};
-
-#undef D
-
-#endif
diff --git a/include/asm-mips/kspd.h b/include/asm-mips/kspd.h
deleted file mode 100644
index 4e9e724c8935..000000000000
--- a/include/asm-mips/kspd.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _ASM_KSPD_H
-#define _ASM_KSPD_H
-
-struct kspd_notifications {
-        void (*kspd_sp_exit)(int sp_id);
-
-        struct list_head list;
-};
-
-#ifdef CONFIG_MIPS_APSP_KSPD
-extern void kspd_notify(struct kspd_notifications *notify);
-#else
-static inline void kspd_notify(struct kspd_notifications *notify)
-{
-}
-#endif
-
-#endif
diff --git a/include/asm-mips/lasat/ds1603.h b/include/asm-mips/lasat/ds1603.h
deleted file mode 100644
index edcd7544b358..000000000000
--- a/include/asm-mips/lasat/ds1603.h
+++ /dev/null
@@ -1,18 +0,0 @@
-#include <asm/addrspace.h>
-
-/* Lasat 100    */
-#define DS1603_REG_100          (KSEG1ADDR(0x1c810000))
-#define DS1603_RST_100          (1 << 2)
-#define DS1603_CLK_100          (1 << 0)
-#define DS1603_DATA_SHIFT_100   1
-#define DS1603_DATA_100         (1 << DS1603_DATA_SHIFT_100)
-
-/* Lasat 200    */
-#define DS1603_REG_200          (KSEG1ADDR(0x11000000))
-#define DS1603_RST_200          (1 << 3)
-#define DS1603_CLK_200          (1 << 4)
-#define DS1603_DATA_200         (1 << 5)
-
-#define DS1603_DATA_REG_200             (DS1603_REG_200 + 0x10000)
-#define DS1603_DATA_READ_SHIFT_200      9
-#define DS1603_DATA_READ_200    (1 << DS1603_DATA_READ_SHIFT_200)
diff --git a/include/asm-mips/lasat/eeprom.h b/include/asm-mips/lasat/eeprom.h
deleted file mode 100644
index 3dac203697fa..000000000000
--- a/include/asm-mips/lasat/eeprom.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#include <asm/addrspace.h>
-
-/* lasat 100 */
-#define AT93C_REG_100               KSEG1ADDR(0x1c810000)
-#define AT93C_RDATA_REG_100         AT93C_REG_100
-#define AT93C_RDATA_SHIFT_100       4
-#define AT93C_WDATA_SHIFT_100       4
-#define AT93C_CS_M_100              (1 << 5)
-#define AT93C_CLK_M_100             (1 << 3)
-
-/* lasat 200 */
-#define AT93C_REG_200           KSEG1ADDR(0x11000000)
-#define AT93C_RDATA_REG_200     (AT93C_REG_200+0x10000)
-#define AT93C_RDATA_SHIFT_200   8
-#define AT93C_WDATA_SHIFT_200   2
-#define AT93C_CS_M_200          (1 << 0)
-#define AT93C_CLK_M_200         (1 << 1)
diff --git a/include/asm-mips/lasat/head.h b/include/asm-mips/lasat/head.h
deleted file mode 100644
index f5589f31a197..000000000000
--- a/include/asm-mips/lasat/head.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * Image header stuff
- */
-#ifndef _HEAD_H
-#define _HEAD_H
-
-#define LASAT_K_MAGIC0_VAL      0xfedeabba
-#define LASAT_K_MAGIC1_VAL      0x00bedead
-
-#ifndef _LANGUAGE_ASSEMBLY
-#include <linux/types.h>
-struct bootloader_header {
-        u32 magic[2];
-        u32 version;
-        u32 image_start;
-        u32 image_size;
-        u32 kernel_start;
-        u32 kernel_entry;
-};
-#endif
-
-#endif /* _HEAD_H */
diff --git a/include/asm-mips/lasat/lasat.h b/include/asm-mips/lasat/lasat.h
deleted file mode 100644
index caeba1e302a2..000000000000
--- a/include/asm-mips/lasat/lasat.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * lasat.h
- *
- * Thomas Horsten <thh@lasat.com>
- * Copyright (C) 2000 LASAT Networks A/S.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Configuration for LASAT boards, loads the appropriate include files.
- */
-#ifndef _LASAT_H
-#define _LASAT_H
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-extern struct lasat_misc {
-        volatile u32 *reset_reg;
-        volatile u32 *flash_wp_reg;
-        u32 flash_wp_bit;
-} *lasat_misc;
-
-enum lasat_mtdparts {
-        LASAT_MTD_BOOTLOADER,
-        LASAT_MTD_SERVICE,
-        LASAT_MTD_NORMAL,
-        LASAT_MTD_CONFIG,
-        LASAT_MTD_FS,
-        LASAT_MTD_LAST
-};
-
-/*
- * The format of the data record in the EEPROM.
- * See Documentation/LASAT/eeprom.txt for a detailed description
- * of the fields in this struct, and the LASAT Hardware Configuration
- * field specification for a detailed description of the config
- * field.
- */
-#include <linux/types.h>
-
-#define LASAT_EEPROM_VERSION 7
-struct lasat_eeprom_struct {
-        unsigned int  version;
-        unsigned int  cfg[3];
-        unsigned char hwaddr[6];
-        unsigned char print_partno[12];
-        unsigned char term0;
-        unsigned char print_serial[14];
-        unsigned char term1;
-        unsigned char prod_partno[12];
-        unsigned char term2;
-        unsigned char prod_serial[14];
-        unsigned char term3;
-        unsigned char passwd_hash[16];
-        unsigned char pwdnull;
-        unsigned char vendid;
-        unsigned char ts_ref;
-        unsigned char ts_signoff;
-        unsigned char reserved[11];
-        unsigned char debugaccess;
-        unsigned short prid;
-        unsigned int  serviceflag;
-        unsigned int  ipaddr;
-        unsigned int  netmask;
-        unsigned int  crc32;
-};
-
-struct lasat_eeprom_struct_pre7 {
-        unsigned int  version;
-        unsigned int  flags[3];
-        unsigned char hwaddr0[6];
-        unsigned char hwaddr1[6];
-        unsigned char print_partno[9];
-        unsigned char term0;
-        unsigned char print_serial[14];
-        unsigned char term1;
-        unsigned char prod_partno[9];
-        unsigned char term2;
-        unsigned char prod_serial[14];
-        unsigned char term3;
-        unsigned char passwd_hash[24];
-        unsigned char pwdnull;
-        unsigned char vendor;
-        unsigned char ts_ref;
-        unsigned char ts_signoff;
-        unsigned char reserved[6];
-        unsigned int  writecount;
-        unsigned int  ipaddr;
-        unsigned int  netmask;
-        unsigned int  crc32;
-};
-
-/* Configuration descriptor encoding - see the doc for details */
-
-#define LASAT_W0_DSCTYPE(v)             (((v))         & 0xf)
-#define LASAT_W0_BMID(v)                (((v) >> 0x04) & 0xf)
-#define LASAT_W0_CPUTYPE(v)             (((v) >> 0x08) & 0xf)
-#define LASAT_W0_BUSSPEED(v)            (((v) >> 0x0c) & 0xf)
-#define LASAT_W0_CPUCLK(v)              (((v) >> 0x10) & 0xf)
-#define LASAT_W0_SDRAMBANKSZ(v)         (((v) >> 0x14) & 0xf)
-#define LASAT_W0_SDRAMBANKS(v)          (((v) >> 0x18) & 0xf)
-#define LASAT_W0_L2CACHE(v)             (((v) >> 0x1c) & 0xf)
-
-#define LASAT_W1_EDHAC(v)               (((v))         & 0xf)
-#define LASAT_W1_HIFN(v)                (((v) >> 0x04) & 0x1)
-#define LASAT_W1_ISDN(v)                (((v) >> 0x05) & 0x1)
-#define LASAT_W1_IDE(v)                 (((v) >> 0x06) & 0x1)
-#define LASAT_W1_HDLC(v)                (((v) >> 0x07) & 0x1)
-#define LASAT_W1_USVERSION(v)           (((v) >> 0x08) & 0x1)
-#define LASAT_W1_4MACS(v)               (((v) >> 0x09) & 0x1)
-#define LASAT_W1_EXTSERIAL(v)           (((v) >> 0x0a) & 0x1)
-#define LASAT_W1_FLASHSIZE(v)           (((v) >> 0x0c) & 0xf)
-#define LASAT_W1_PCISLOTS(v)            (((v) >> 0x10) & 0xf)
-#define LASAT_W1_PCI1OPT(v)             (((v) >> 0x14) & 0xf)
-#define LASAT_W1_PCI2OPT(v)             (((v) >> 0x18) & 0xf)
-#define LASAT_W1_PCI3OPT(v)             (((v) >> 0x1c) & 0xf)
-
-/* Routines specific to LASAT boards */
-
-#define LASAT_BMID_MASQUERADE2          0
-#define LASAT_BMID_MASQUERADEPRO        1
-#define LASAT_BMID_SAFEPIPE25           2
-#define LASAT_BMID_SAFEPIPE50           3
-#define LASAT_BMID_SAFEPIPE100          4
-#define LASAT_BMID_SAFEPIPE5000         5
-#define LASAT_BMID_SAFEPIPE7000         6
-#define LASAT_BMID_SAFEPIPE1000         7
-#if 0
-#define LASAT_BMID_SAFEPIPE30           7
-#define LASAT_BMID_SAFEPIPE5100         8
-#define LASAT_BMID_SAFEPIPE7100         9
-#endif
-#define LASAT_BMID_UNKNOWN              0xf
-#define LASAT_MAX_BMID_NAMES            9   /* no larger than 15! */
-
-#define LASAT_HAS_EDHAC                 (1 << 0)
-#define LASAT_EDHAC_FAST                (1 << 1)
-#define LASAT_HAS_EADI                  (1 << 2)
-#define LASAT_HAS_HIFN                  (1 << 3)
-#define LASAT_HAS_ISDN                  (1 << 4)
-#define LASAT_HAS_LEASEDLINE_IF         (1 << 5)
-#define LASAT_HAS_HDC                   (1 << 6)
-
-#define LASAT_PRID_MASQUERADE2          0
-#define LASAT_PRID_MASQUERADEPRO        1
-#define LASAT_PRID_SAFEPIPE25           2
-#define LASAT_PRID_SAFEPIPE50           3
-#define LASAT_PRID_SAFEPIPE100          4
-#define LASAT_PRID_SAFEPIPE5000         5
-#define LASAT_PRID_SAFEPIPE7000         6
-#define LASAT_PRID_SAFEPIPE30           7
-#define LASAT_PRID_SAFEPIPE5100         8
-#define LASAT_PRID_SAFEPIPE7100         9
-
-#define LASAT_PRID_SAFEPIPE1110         10
-#define LASAT_PRID_SAFEPIPE3020         11
-#define LASAT_PRID_SAFEPIPE3030         12
-#define LASAT_PRID_SAFEPIPE5020         13
-#define LASAT_PRID_SAFEPIPE5030         14
-#define LASAT_PRID_SAFEPIPE1120         15
-#define LASAT_PRID_SAFEPIPE1130         16
-#define LASAT_PRID_SAFEPIPE6010         17
-#define LASAT_PRID_SAFEPIPE6110         18
-#define LASAT_PRID_SAFEPIPE6210         19
-#define LASAT_PRID_SAFEPIPE1020         20
-#define LASAT_PRID_SAFEPIPE1040         21
-#define LASAT_PRID_SAFEPIPE1060         22
-
-struct lasat_info {
-        unsigned int  li_cpu_hz;
-        unsigned int  li_bus_hz;
-        unsigned int  li_bmid;
-        unsigned int  li_memsize;
-        unsigned int  li_flash_size;
-        unsigned int  li_prid;
-        unsigned char li_bmstr[16];
-        unsigned char li_namestr[32];
-        unsigned char li_typestr[16];
-        /* Info on the Flash layout */
-        unsigned int  li_flash_base;
-        unsigned long li_flashpart_base[LASAT_MTD_LAST];
-        unsigned long li_flashpart_size[LASAT_MTD_LAST];
-        struct lasat_eeprom_struct li_eeprom_info;
-        unsigned int  li_eeprom_upgrade_version;
-        unsigned int  li_debugaccess;
-};
-
-extern struct lasat_info lasat_board_info;
-
-static inline unsigned long lasat_flash_partition_start(int partno)
-{
-        if (partno < 0 || partno >= LASAT_MTD_LAST)
-                return 0;
-
-        return lasat_board_info.li_flashpart_base[partno];
-}
-
-static inline unsigned long lasat_flash_partition_size(int partno)
-{
-        if (partno < 0 || partno >= LASAT_MTD_LAST)
-                return 0;
-
-        return lasat_board_info.li_flashpart_size[partno];
-}
-
-/* Called from setup() to initialize the global board_info struct */
-extern int lasat_init_board_info(void);
-
-/* Write the modified EEPROM info struct */
-extern void lasat_write_eeprom_info(void);
-
-#define N_MACHTYPES             2
-/* for calibration of delays */
-
-/* the lasat_ndelay function is necessary because it is used at an
- * early stage of the boot process where ndelay is not calibrated.
- * It is used for the bit-banging rtc and eeprom drivers */
-
-#include <linux/delay.h>
-
-/* calculating with the slowest board with 100 MHz clock */
-#define LASAT_100_DIVIDER 20
-/* All 200's run at 250 MHz clock */
-#define LASAT_200_DIVIDER 8
-
-extern unsigned int lasat_ndelay_divider;
-
-static inline void lasat_ndelay(unsigned int ns)
-{
-        __delay(ns / lasat_ndelay_divider);
-}
-
-#define IS_LASAT_200()     (current_cpu_data.cputype == CPU_R5000)
-
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
-#define LASAT_SERVICEMODE_MAGIC_1     0xdeadbeef
-#define LASAT_SERVICEMODE_MAGIC_2     0xfedeabba
-
-/* Lasat 100 boards */
-#define LASAT_GT_BASE           (KSEG1ADDR(0x14000000))
-
-/* Lasat 200 boards */
-#define Vrc5074_PHYS_BASE       0x1fa00000
-#define Vrc5074_BASE            (KSEG1ADDR(Vrc5074_PHYS_BASE))
-#define PCI_WINDOW1             0x1a000000
-
-#endif /* _LASAT_H */
diff --git a/include/asm-mips/lasat/lasatint.h b/include/asm-mips/lasat/lasatint.h
deleted file mode 100644
index e0d2458b43d0..000000000000
--- a/include/asm-mips/lasat/lasatint.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef __ASM_LASAT_LASATINT_H
-#define __ASM_LASAT_LASATINT_H
-
-/* lasat 100 */
-#define LASAT_INT_STATUS_REG_100        (KSEG1ADDR(0x1c880000))
-#define LASAT_INT_MASK_REG_100          (KSEG1ADDR(0x1c890000))
-#define LASATINT_MASK_SHIFT_100         0
-
-/* lasat 200 */
-#define LASAT_INT_STATUS_REG_200        (KSEG1ADDR(0x1104003c))
-#define LASAT_INT_MASK_REG_200          (KSEG1ADDR(0x1104003c))
-#define LASATINT_MASK_SHIFT_200         16
-
-#endif /* __ASM_LASAT_LASATINT_H */
diff --git a/include/asm-mips/lasat/picvue.h b/include/asm-mips/lasat/picvue.h
deleted file mode 100644
index 42a492edc40e..000000000000
--- a/include/asm-mips/lasat/picvue.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/* Lasat 100 */
-#define PVC_REG_100             KSEG1ADDR(0x1c820000)
-#define PVC_DATA_SHIFT_100      0
-#define PVC_DATA_M_100          0xFF
-#define PVC_E_100               (1 << 8)
-#define PVC_RW_100              (1 << 9)
-#define PVC_RS_100              (1 << 10)
-
-/* Lasat 200 */
-#define PVC_REG_200             KSEG1ADDR(0x11000000)
-#define PVC_DATA_SHIFT_200      24
-#define PVC_DATA_M_200          (0xFF << PVC_DATA_SHIFT_200)
-#define PVC_E_200               (1 << 16)
-#define PVC_RW_200              (1 << 17)
-#define PVC_RS_200              (1 << 18)
diff --git a/include/asm-mips/lasat/serial.h b/include/asm-mips/lasat/serial.h
deleted file mode 100644
index 1c37d70579b8..000000000000
--- a/include/asm-mips/lasat/serial.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#include <asm/lasat/lasat.h>
-
-/* Lasat 100 boards serial configuration */
-#define LASAT_BASE_BAUD_100             (7372800 / 16)
-#define LASAT_UART_REGS_BASE_100        0x1c8b0000
-#define LASAT_UART_REGS_SHIFT_100       2
-#define LASATINT_UART_100               16
-
-/* * LASAT 200 boards serial configuration */
-#define LASAT_BASE_BAUD_200             (100000000 / 16 / 12)
-#define LASAT_UART_REGS_BASE_200        (Vrc5074_PHYS_BASE + 0x0300)
-#define LASAT_UART_REGS_SHIFT_200       3
-#define LASATINT_UART_200               21
diff --git a/include/asm-mips/linkage.h b/include/asm-mips/linkage.h
deleted file mode 100644
index e9a940d1b0c6..000000000000
--- a/include/asm-mips/linkage.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#ifdef __ASSEMBLY__
-#include <asm/asm.h>
-#endif
-
-#define __weak __attribute__((weak))
-
-#endif
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
deleted file mode 100644
index f96fd59e0845..000000000000
--- a/include/asm-mips/local.h
+++ /dev/null
@@ -1,221 +0,0 @@
-#ifndef _ARCH_MIPS_LOCAL_H
-#define _ARCH_MIPS_LOCAL_H
-
-#include <linux/percpu.h>
-#include <linux/bitops.h>
-#include <asm/atomic.h>
-#include <asm/cmpxchg.h>
-#include <asm/war.h>
-
-typedef struct
-{
-        atomic_long_t a;
-} local_t;
-
-#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
-
-#define local_read(l)   atomic_long_read(&(l)->a)
-#define local_set(l, i) atomic_long_set(&(l)->a, (i))
-
-#define local_add(i, l) atomic_long_add((i), (&(l)->a))
-#define local_sub(i, l) atomic_long_sub((i), (&(l)->a))
-#define local_inc(l)    atomic_long_inc(&(l)->a)
-#define local_dec(l)    atomic_long_dec(&(l)->a)
-
-/*
- * Same as above, but return the result value
- */
-static __inline__ long local_add_return(long i, local_t * l)
-{
-        unsigned long result;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:"    __LL    "%1, %2         # local_add_return      \n"
-                "       addu    %0, %1, %3                              \n"
-                        __SC    "%0, %2                                 \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
-                : "Ir" (i), "m" (l->a.counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:"    __LL    "%1, %2         # local_add_return      \n"
-                "       addu    %0, %1, %3                              \n"
-                        __SC    "%0, %2                                 \n"
-                "       beqz    %0, 1b                                  \n"
-                "       addu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
-                : "Ir" (i), "m" (l->a.counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                local_irq_save(flags);
-                result = l->a.counter;
-                result += i;
-                l->a.counter = result;
-                local_irq_restore(flags);
-        }
-
-        return result;
-}
-
-static __inline__ long local_sub_return(long i, local_t * l)
-{
-        unsigned long result;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:"    __LL    "%1, %2         # local_sub_return      \n"
-                "       subu    %0, %1, %3                              \n"
-                        __SC    "%0, %2                                 \n"
-                "       beqzl   %0, 1b                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
-                : "Ir" (i), "m" (l->a.counter)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long temp;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:"    __LL    "%1, %2         # local_sub_return      \n"
-                "       subu    %0, %1, %3                              \n"
-                        __SC    "%0, %2                                 \n"
-                "       beqz    %0, 1b                                  \n"
-                "       subu    %0, %1, %3                              \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
-                : "Ir" (i), "m" (l->a.counter)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                local_irq_save(flags);
-                result = l->a.counter;
-                result -= i;
-                l->a.counter = result;
-                local_irq_restore(flags);
-        }
-
-        return result;
-}
-
-#define local_cmpxchg(l, o, n) \
-        ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
-#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
-
-/**
- * local_add_unless - add unless the number is a given value
- * @l: pointer of type local_t
- * @a: the amount to add to l...
- * @u: ...unless l is equal to u.
- *
- * Atomically adds @a to @l, so long as it was not @u.
- * Returns non-zero if @l was not @u, and zero otherwise.
- */
-#define local_add_unless(l, a, u)                               \
-({                                                              \
-        long c, old;                                            \
-        c = local_read(l);                                      \
-        while (c != (u) && (old = local_cmpxchg((l), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
-#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
-
-#define local_dec_return(l) local_sub_return(1, (l))
-#define local_inc_return(l) local_add_return(1, (l))
-
-/*
- * local_sub_and_test - subtract value from variable and test result
- * @i: integer value to subtract
- * @l: pointer of type local_t
- *
- * Atomically subtracts @i from @l and returns
- * true if the result is zero, or false for all
- * other cases.
- */
-#define local_sub_and_test(i, l) (local_sub_return((i), (l)) == 0)
-
-/*
- * local_inc_and_test - increment and test
- * @l: pointer of type local_t
- *
- * Atomically increments @l by 1
- * and returns true if the result is zero, or false for all
- * other cases.
- */
-#define local_inc_and_test(l) (local_inc_return(l) == 0)
-
-/*
- * local_dec_and_test - decrement by 1 and test
- * @l: pointer of type local_t
- *
- * Atomically decrements @l by 1 and
- * returns true if the result is 0, or false for all other
- * cases.
- */
-#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
-
-/*
- * local_add_negative - add and test if negative
- * @l: pointer of type local_t
- * @i: integer value to add
- *
- * Atomically adds @i to @l and returns true
- * if the result is negative, or false when
- * result is greater than or equal to zero.
- */
-#define local_add_negative(i, l) (local_add_return(i, (l)) < 0)
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations.  Note they take
- * a variable, not an address.
- */
-
-#define __local_inc(l)          ((l)->a.counter++)
-#define __local_dec(l)          ((l)->a.counter++)
-#define __local_add(i, l)       ((l)->a.counter+=(i))
-#define __local_sub(i, l)       ((l)->a.counter-=(i))
-
-/* Need to disable preemption for the cpu local counters otherwise we could
-   still access a variable of a previous CPU in a non atomic way. */
-#define cpu_local_wrap_v(l)             \
-        ({ local_t res__;               \
-           preempt_disable();           \
-           res__ = (l);                 \
-           preempt_enable();            \
-           res__; })
-#define cpu_local_wrap(l)               \
-        ({ preempt_disable();           \
-           l;                           \
-           preempt_enable(); })         \
-
-#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
-#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
-#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
-#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
-#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
-#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
-
-#define __cpu_local_inc(l)      cpu_local_inc(l)
-#define __cpu_local_dec(l)      cpu_local_dec(l)
-#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
-#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
-
-#endif /* _ARCH_MIPS_LOCAL_H */
diff --git a/include/asm-mips/m48t35.h b/include/asm-mips/m48t35.h
deleted file mode 100644
index f44852e9a96d..000000000000
--- a/include/asm-mips/m48t35.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  Registers for the SGS-Thomson M48T35 Timekeeper RAM chip
- */
-#ifndef _ASM_M48T35_H
-#define _ASM_M48T35_H
-
-#include <linux/spinlock.h>
-
-extern spinlock_t rtc_lock;
-
-struct m48t35_rtc {
-        volatile u8     pad[0x7ff8];    /* starts at 0x7ff8 */
-        volatile u8     control;
-        volatile u8     sec;
-        volatile u8     min;
-        volatile u8     hour;
-        volatile u8     day;
-        volatile u8     date;
-        volatile u8     month;
-        volatile u8     year;
-};
-
-#define M48T35_RTC_SET          0x80
-#define M48T35_RTC_STOPPED      0x80
-#define M48T35_RTC_READ         0x40
-
-#endif /* _ASM_M48T35_H */
diff --git a/include/asm-mips/m48t37.h b/include/asm-mips/m48t37.h
deleted file mode 100644
index cabf86264f36..000000000000
--- a/include/asm-mips/m48t37.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *  Registers for the SGS-Thomson M48T37 Timekeeper RAM chip
- */
-#ifndef _ASM_M48T37_H
-#define _ASM_M48T37_H
-
-#include <linux/spinlock.h>
-
-extern spinlock_t rtc_lock;
-
-struct m48t37_rtc {
-        volatile u8     pad[0x7ff0];    /* NVRAM */
-        volatile u8     flags;
-        volatile u8     century;
-        volatile u8     alarm_sec;
-        volatile u8     alarm_min;
-        volatile u8     alarm_hour;
-        volatile u8     alarm_data;
-        volatile u8     interrupts;
-        volatile u8     watchdog;
-        volatile u8     control;
-        volatile u8     sec;
-        volatile u8     min;
-        volatile u8     hour;
-        volatile u8     day;
-        volatile u8     date;
-        volatile u8     month;
-        volatile u8     year;
-};
-
-#define M48T37_RTC_SET          0x80
-#define M48T37_RTC_STOPPED      0x80
-#define M48T37_RTC_READ         0x40
-
-#endif /* _ASM_M48T37_H */
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
deleted file mode 100644
index 0d302bad4492..000000000000
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ /dev/null
@@ -1,1772 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2000-2001, 2006-2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
- /*
-  * some definitions add by takuzo@sm.sony.co.jp and sato@sm.sony.co.jp
-  */
-
-#ifndef _AU1000_H_
-#define _AU1000_H_
-
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-#include <linux/delay.h>
-#include <linux/types.h>
-
-#include <linux/io.h>
-#include <linux/irq.h>
-
-/* cpu pipeline flush */
-void static inline au_sync(void)
-{
-        __asm__ volatile ("sync");
-}
-
-void static inline au_sync_udelay(int us)
-{
-        __asm__ volatile ("sync");
-        udelay(us);
-}
-
-void static inline au_sync_delay(int ms)
-{
-        __asm__ volatile ("sync");
-        mdelay(ms);
-}
-
-void static inline au_writeb(u8 val, unsigned long reg)
-{
-        *(volatile u8 *)reg = val;
-}
-
-void static inline au_writew(u16 val, unsigned long reg)
-{
-        *(volatile u16 *)reg = val;
-}
-
-void static inline au_writel(u32 val, unsigned long reg)
-{
-        *(volatile u32 *)reg = val;
-}
-
-static inline u8 au_readb(unsigned long reg)
-{
-        return *(volatile u8 *)reg;
-}
-
-static inline u16 au_readw(unsigned long reg)
-{
-        return *(volatile u16 *)reg;
-}
-
-static inline u32 au_readl(unsigned long reg)
-{
-        return *(volatile u32 *)reg;
-}
-
-
-/* arch/mips/au1000/common/clocks.c */
-extern void set_au1x00_speed(unsigned int new_freq);
-extern unsigned int get_au1x00_speed(void);
-extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
-extern unsigned long get_au1x00_uart_baud_base(void);
-extern void set_au1x00_lcd_clock(void);
-extern unsigned int get_au1x00_lcd_clock(void);
-
-/*
- * Every board describes its IRQ mapping with this table.
- */
-struct au1xxx_irqmap {
-        int     im_irq;
-        int     im_type;
-        int     im_request;
-};
-
-/*
- * init_IRQ looks for a table with this name.
- */
-extern struct au1xxx_irqmap au1xxx_irq_map[];
-
-#endif /* !defined (_LANGUAGE_ASSEMBLY) */
-
-/*
- * SDRAM register offsets
- */
-#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || \
-    defined(CONFIG_SOC_AU1100)
-#define MEM_SDMODE0             0x0000
-#define MEM_SDMODE1             0x0004
-#define MEM_SDMODE2             0x0008
-#define MEM_SDADDR0             0x000C
-#define MEM_SDADDR1             0x0010
-#define MEM_SDADDR2             0x0014
-#define MEM_SDREFCFG            0x0018
-#define MEM_SDPRECMD            0x001C
-#define MEM_SDAUTOREF           0x0020
-#define MEM_SDWRMD0             0x0024
-#define MEM_SDWRMD1             0x0028
-#define MEM_SDWRMD2             0x002C
-#define MEM_SDSLEEP             0x0030
-#define MEM_SDSMCKE             0x0034
-
-/*
- * MEM_SDMODE register content definitions
- */
-#define MEM_SDMODE_F            (1 << 22)
-#define MEM_SDMODE_SR           (1 << 21)
-#define MEM_SDMODE_BS           (1 << 20)
-#define MEM_SDMODE_RS           (3 << 18)
-#define MEM_SDMODE_CS           (7 << 15)
-#define MEM_SDMODE_TRAS         (15 << 11)
-#define MEM_SDMODE_TMRD         (3 << 9)
-#define MEM_SDMODE_TWR          (3 << 7)
-#define MEM_SDMODE_TRP          (3 << 5)
-#define MEM_SDMODE_TRCD         (3 << 3)
-#define MEM_SDMODE_TCL          (7 << 0)
-
-#define MEM_SDMODE_BS_2Bank     (0 << 20)
-#define MEM_SDMODE_BS_4Bank     (1 << 20)
-#define MEM_SDMODE_RS_11Row     (0 << 18)
-#define MEM_SDMODE_RS_12Row     (1 << 18)
-#define MEM_SDMODE_RS_13Row     (2 << 18)
-#define MEM_SDMODE_RS_N(N)      ((N) << 18)
-#define MEM_SDMODE_CS_7Col      (0 << 15)
-#define MEM_SDMODE_CS_8Col      (1 << 15)
-#define MEM_SDMODE_CS_9Col      (2 << 15)
-#define MEM_SDMODE_CS_10Col     (3 << 15)
-#define MEM_SDMODE_CS_11Col     (4 << 15)
-#define MEM_SDMODE_CS_N(N)      ((N) << 15)
-#define MEM_SDMODE_TRAS_N(N)    ((N) << 11)
-#define MEM_SDMODE_TMRD_N(N)    ((N) << 9)
-#define MEM_SDMODE_TWR_N(N)     ((N) << 7)
-#define MEM_SDMODE_TRP_N(N)     ((N) << 5)
-#define MEM_SDMODE_TRCD_N(N)    ((N) << 3)
-#define MEM_SDMODE_TCL_N(N)     ((N) << 0)
-
-/*
- * MEM_SDADDR register contents definitions
- */
-#define MEM_SDADDR_E            (1 << 20)
-#define MEM_SDADDR_CSBA         (0x03FF << 10)
-#define MEM_SDADDR_CSMASK       (0x03FF << 0)
-#define MEM_SDADDR_CSBA_N(N)    ((N) & (0x03FF << 22) >> 12)
-#define MEM_SDADDR_CSMASK_N(N)  ((N)&(0x03FF << 22) >> 22)
-
-/*
- * MEM_SDREFCFG register content definitions
- */
-#define MEM_SDREFCFG_TRC        (15 << 28)
-#define MEM_SDREFCFG_TRPM       (3 << 26)
-#define MEM_SDREFCFG_E          (1 << 25)
-#define MEM_SDREFCFG_RE         (0x1ffffff << 0)
-#define MEM_SDREFCFG_TRC_N(N)   ((N) << MEM_SDREFCFG_TRC)
-#define MEM_SDREFCFG_TRPM_N(N)  ((N) << MEM_SDREFCFG_TRPM)
-#define MEM_SDREFCFG_REF_N(N)   (N)
-#endif
-
-/***********************************************************************/
-
-/*
- * Au1550 SDRAM Register Offsets
- */
-
-/***********************************************************************/
-
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_SDMODE0             0x0800
-#define MEM_SDMODE1             0x0808
-#define MEM_SDMODE2             0x0810
-#define MEM_SDADDR0             0x0820
-#define MEM_SDADDR1             0x0828
-#define MEM_SDADDR2             0x0830
-#define MEM_SDCONFIGA           0x0840
-#define MEM_SDCONFIGB           0x0848
-#define MEM_SDSTAT              0x0850
-#define MEM_SDERRADDR           0x0858
-#define MEM_SDSTRIDE0           0x0860
-#define MEM_SDSTRIDE1           0x0868
-#define MEM_SDSTRIDE2           0x0870
-#define MEM_SDWRMD0             0x0880
-#define MEM_SDWRMD1             0x0888
-#define MEM_SDWRMD2             0x0890
-#define MEM_SDPRECMD            0x08C0
-#define MEM_SDAUTOREF           0x08C8
-#define MEM_SDSREF              0x08D0
-#define MEM_SDSLEEP             MEM_SDSREF
-
-#endif
-
-/*
- * Physical base addresses for integrated peripherals
- */
-
-#ifdef CONFIG_SOC_AU1000
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
-#define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
-#define IRDA_PHYS_ADDR          0x10300000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MAC1_PHYS_ADDR          0x10510000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART2_PHYS_ADDR         0x11300000
-#define UART3_PHYS_ADDR         0x11400000
-#define SSI0_PHYS_ADDR          0x11600000
-#define SSI1_PHYS_ADDR          0x11680000
-#define SYS_PHYS_ADDR           0x11900000
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1500
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
-#define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
-#define PCI_PHYS_ADDR           0x14005000
-#define MAC0_PHYS_ADDR          0x11500000
-#define MAC1_PHYS_ADDR          0x11510000
-#define MACEN_PHYS_ADDR         0x11520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART3_PHYS_ADDR         0x11400000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define PCI_MEM_PHYS_ADDR       0x400000000ULL
-#define PCI_IO_PHYS_ADDR        0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/********************************************************************/
-
-#ifdef CONFIG_SOC_AU1100
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define DMA0_PHYS_ADDR          0x14002000
-#define DMA1_PHYS_ADDR          0x14002100
-#define DMA2_PHYS_ADDR          0x14002200
-#define DMA3_PHYS_ADDR          0x14002300
-#define DMA4_PHYS_ADDR          0x14002400
-#define DMA5_PHYS_ADDR          0x14002500
-#define DMA6_PHYS_ADDR          0x14002600
-#define DMA7_PHYS_ADDR          0x14002700
-#define IC0_PHYS_ADDR           0x10400000
-#define SD0_PHYS_ADDR           0x10600000
-#define SD1_PHYS_ADDR           0x10680000
-#define IC1_PHYS_ADDR           0x11800000
-#define AC97_PHYS_ADDR          0x10000000
-#define USBH_PHYS_ADDR          0x10100000
-#define USBD_PHYS_ADDR          0x10200000
-#define IRDA_PHYS_ADDR          0x10300000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define I2S_PHYS_ADDR           0x11000000
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART3_PHYS_ADDR         0x11400000
-#define SSI0_PHYS_ADDR          0x11600000
-#define SSI1_PHYS_ADDR          0x11680000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define LCD_PHYS_ADDR           0x15000000
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1550
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define USBH_PHYS_ADDR          0x14020000
-#define USBD_PHYS_ADDR          0x10200000
-#define PCI_PHYS_ADDR           0x14005000
-#define MAC0_PHYS_ADDR          0x10500000
-#define MAC1_PHYS_ADDR          0x10510000
-#define MACEN_PHYS_ADDR         0x10520000
-#define MACDMA0_PHYS_ADDR       0x14004000
-#define MACDMA1_PHYS_ADDR       0x14004200
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define UART3_PHYS_ADDR         0x11400000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define DDMA_PHYS_ADDR          0x14002000
-#define PE_PHYS_ADDR            0x14008000
-#define PSC0_PHYS_ADDR          0x11A00000
-#define PSC1_PHYS_ADDR          0x11B00000
-#define PSC2_PHYS_ADDR          0x10A00000
-#define PSC3_PHYS_ADDR          0x10B00000
-#define PCI_MEM_PHYS_ADDR       0x400000000ULL
-#define PCI_IO_PHYS_ADDR        0x500000000ULL
-#define PCI_CONFIG0_PHYS_ADDR   0x600000000ULL
-#define PCI_CONFIG1_PHYS_ADDR   0x680000000ULL
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/***********************************************************************/
-
-#ifdef CONFIG_SOC_AU1200
-#define MEM_PHYS_ADDR           0x14000000
-#define STATIC_MEM_PHYS_ADDR    0x14001000
-#define AES_PHYS_ADDR           0x10300000
-#define CIM_PHYS_ADDR           0x14004000
-#define IC0_PHYS_ADDR           0x10400000
-#define IC1_PHYS_ADDR           0x11800000
-#define USBM_PHYS_ADDR          0x14020000
-#define USBH_PHYS_ADDR          0x14020100
-#define UART0_PHYS_ADDR         0x11100000
-#define UART1_PHYS_ADDR         0x11200000
-#define GPIO2_PHYS_ADDR         0x11700000
-#define SYS_PHYS_ADDR           0x11900000
-#define DDMA_PHYS_ADDR          0x14002000
-#define PSC0_PHYS_ADDR          0x11A00000
-#define PSC1_PHYS_ADDR          0x11B00000
-#define SD0_PHYS_ADDR           0x10600000
-#define SD1_PHYS_ADDR           0x10680000
-#define LCD_PHYS_ADDR           0x15000000
-#define SWCNT_PHYS_ADDR         0x1110010C
-#define MAEFE_PHYS_ADDR         0x14012000
-#define MAEBE_PHYS_ADDR         0x14010000
-#define PCMCIA_IO_PHYS_ADDR     0xF00000000ULL
-#define PCMCIA_ATTR_PHYS_ADDR   0xF40000000ULL
-#define PCMCIA_MEM_PHYS_ADDR    0xF80000000ULL
-#endif
-
-/* Static Bus Controller */
-#define MEM_STCFG0              0xB4001000
-#define MEM_STTIME0             0xB4001004
-#define MEM_STADDR0             0xB4001008
-
-#define MEM_STCFG1              0xB4001010
-#define MEM_STTIME1             0xB4001014
-#define MEM_STADDR1             0xB4001018
-
-#define MEM_STCFG2              0xB4001020
-#define MEM_STTIME2             0xB4001024
-#define MEM_STADDR2             0xB4001028
-
-#define MEM_STCFG3              0xB4001030
-#define MEM_STTIME3             0xB4001034
-#define MEM_STADDR3             0xB4001038
-
-#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
-#define MEM_STNDCTL             0xB4001100
-#define MEM_STSTAT              0xB4001104
-
-#define MEM_STNAND_CMD          0x0
-#define MEM_STNAND_ADDR         0x4
-#define MEM_STNAND_DATA         0x20
-#endif
-
-/* Interrupt Controller 0 */
-#define IC0_CFG0RD              0xB0400040
-#define IC0_CFG0SET             0xB0400040
-#define IC0_CFG0CLR             0xB0400044
-
-#define IC0_CFG1RD              0xB0400048
-#define IC0_CFG1SET             0xB0400048
-#define IC0_CFG1CLR             0xB040004C
-
-#define IC0_CFG2RD              0xB0400050
-#define IC0_CFG2SET             0xB0400050
-#define IC0_CFG2CLR             0xB0400054
-
-#define IC0_REQ0INT             0xB0400054
-#define IC0_SRCRD               0xB0400058
-#define IC0_SRCSET              0xB0400058
-#define IC0_SRCCLR              0xB040005C
-#define IC0_REQ1INT             0xB040005C
-
-#define IC0_ASSIGNRD            0xB0400060
-#define IC0_ASSIGNSET           0xB0400060
-#define IC0_ASSIGNCLR           0xB0400064
-
-#define IC0_WAKERD              0xB0400068
-#define IC0_WAKESET             0xB0400068
-#define IC0_WAKECLR             0xB040006C
-
-#define IC0_MASKRD              0xB0400070
-#define IC0_MASKSET             0xB0400070
-#define IC0_MASKCLR             0xB0400074
-
-#define IC0_RISINGRD            0xB0400078
-#define IC0_RISINGCLR           0xB0400078
-#define IC0_FALLINGRD           0xB040007C
-#define IC0_FALLINGCLR          0xB040007C
-
-#define IC0_TESTBIT             0xB0400080
-
-/* Interrupt Controller 1 */
-#define IC1_CFG0RD              0xB1800040
-#define IC1_CFG0SET             0xB1800040
-#define IC1_CFG0CLR             0xB1800044
-
-#define IC1_CFG1RD              0xB1800048
-#define IC1_CFG1SET             0xB1800048
-#define IC1_CFG1CLR             0xB180004C
-
-#define IC1_CFG2RD              0xB1800050
-#define IC1_CFG2SET             0xB1800050
-#define IC1_CFG2CLR             0xB1800054
-
-#define IC1_REQ0INT             0xB1800054
-#define IC1_SRCRD               0xB1800058
-#define IC1_SRCSET              0xB1800058
-#define IC1_SRCCLR              0xB180005C
-#define IC1_REQ1INT             0xB180005C
-
-#define IC1_ASSIGNRD            0xB1800060
-#define IC1_ASSIGNSET           0xB1800060
-#define IC1_ASSIGNCLR           0xB1800064
-
-#define IC1_WAKERD              0xB1800068
-#define IC1_WAKESET             0xB1800068
-#define IC1_WAKECLR             0xB180006C
-
-#define IC1_MASKRD              0xB1800070
-#define IC1_MASKSET             0xB1800070
-#define IC1_MASKCLR             0xB1800074
-
-#define IC1_RISINGRD            0xB1800078
-#define IC1_RISINGCLR           0xB1800078
-#define IC1_FALLINGRD           0xB180007C
-#define IC1_FALLINGCLR          0xB180007C
-
-#define IC1_TESTBIT             0xB1800080
-
-/* Interrupt Configuration Modes */
-#define INTC_INT_DISABLED               0x0
-#define INTC_INT_RISE_EDGE              0x1
-#define INTC_INT_FALL_EDGE              0x2
-#define INTC_INT_RISE_AND_FALL_EDGE     0x3
-#define INTC_INT_HIGH_LEVEL             0x5
-#define INTC_INT_LOW_LEVEL              0x6
-#define INTC_INT_HIGH_AND_LOW_LEVEL     0x7
-
-/* Interrupt Numbers */
-/* Au1000 */
-#ifdef CONFIG_SOC_AU1000
-enum soc_au1000_ints {
-        AU1000_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1000_UART0_INT        = AU1000_FIRST_INT,
-        AU1000_UART1_INT,                               /* au1000 */
-        AU1000_UART2_INT,                               /* au1000 */
-        AU1000_UART3_INT,
-        AU1000_SSI0_INT,                                /* au1000 */
-        AU1000_SSI1_INT,                                /* au1000 */
-        AU1000_DMA_INT_BASE,
-
-        AU1000_TOY_INT          = AU1000_FIRST_INT + 14,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1000_IRDA_TX_INT,                             /* au1000 */
-        AU1000_IRDA_RX_INT,                             /* au1000 */
-        AU1000_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_SUS_INT,
-        AU1000_USB_HOST_INT,
-        AU1000_ACSYNC_INT,
-        AU1000_MAC0_DMA_INT,
-        AU1000_MAC1_DMA_INT,
-        AU1000_I2S_UO_INT,                              /* au1000 */
-        AU1000_AC97C_INT,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1000_GPIO_16,
-        AU1000_GPIO_17,
-        AU1000_GPIO_18,
-        AU1000_GPIO_19,
-        AU1000_GPIO_20,
-        AU1000_GPIO_21,
-        AU1000_GPIO_22,
-        AU1000_GPIO_23,
-        AU1000_GPIO_24,
-        AU1000_GPIO_25,
-        AU1000_GPIO_26,
-        AU1000_GPIO_27,
-        AU1000_GPIO_28,
-        AU1000_GPIO_29,
-        AU1000_GPIO_30,
-        AU1000_GPIO_31,
-};
-
-#define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
-#define UART2_ADDR              0xB1300000
-#define UART3_ADDR              0xB1400000
-
-#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
-#define USB_HOST_CONFIG         0xB017FFFC
-
-#define AU1000_ETH0_BASE        0xB0500000
-#define AU1000_ETH1_BASE        0xB0510000
-#define AU1000_MAC0_ENABLE      0xB0520000
-#define AU1000_MAC1_ENABLE      0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif /* CONFIG_SOC_AU1000 */
-
-/* Au1500 */
-#ifdef CONFIG_SOC_AU1500
-enum soc_au1500_ints {
-        AU1500_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1500_UART0_INT        = AU1500_FIRST_INT,
-        AU1000_PCI_INTA,                                /* au1500 */
-        AU1000_PCI_INTB,                                /* au1500 */
-        AU1500_UART3_INT,
-        AU1000_PCI_INTC,                                /* au1500 */
-        AU1000_PCI_INTD,                                /* au1500 */
-        AU1000_DMA_INT_BASE,
-
-        AU1000_TOY_INT          = AU1500_FIRST_INT + 14,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1500_PCI_ERR_INT,
-        AU1500_RESERVED_INT,
-        AU1000_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_SUS_INT,
-        AU1000_USB_HOST_INT,
-        AU1000_ACSYNC_INT,
-        AU1500_MAC0_DMA_INT,
-        AU1500_MAC1_DMA_INT,
-        AU1000_AC97C_INT        = AU1500_FIRST_INT + 31,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1500_GPIO_200,
-        AU1500_GPIO_201,
-        AU1500_GPIO_202,
-        AU1500_GPIO_203,
-        AU1500_GPIO_20,
-        AU1500_GPIO_204,
-        AU1500_GPIO_205,
-        AU1500_GPIO_23,
-        AU1500_GPIO_24,
-        AU1500_GPIO_25,
-        AU1500_GPIO_26,
-        AU1500_GPIO_27,
-        AU1500_GPIO_28,
-        AU1500_GPIO_206,
-        AU1500_GPIO_207,
-        AU1500_GPIO_208_215,
-};
-
-/* shortcuts */
-#define INTA AU1000_PCI_INTA
-#define INTB AU1000_PCI_INTB
-#define INTC AU1000_PCI_INTC
-#define INTD AU1000_PCI_INTD
-
-#define UART0_ADDR              0xB1100000
-#define UART3_ADDR              0xB1400000
-
-#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
-#define USB_HOST_CONFIG         0xB017fffc
-
-#define AU1500_ETH0_BASE        0xB1500000
-#define AU1500_ETH1_BASE        0xB1510000
-#define AU1500_MAC0_ENABLE      0xB1520000
-#define AU1500_MAC1_ENABLE      0xB1520004
-#define NUM_ETH_INTERFACES 2
-#endif /* CONFIG_SOC_AU1500 */
-
-/* Au1100 */
-#ifdef CONFIG_SOC_AU1100
-enum soc_au1100_ints {
-        AU1100_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1100_UART0_INT,
-        AU1100_UART1_INT,
-        AU1100_SD_INT,
-        AU1100_UART3_INT,
-        AU1000_SSI0_INT,
-        AU1000_SSI1_INT,
-        AU1000_DMA_INT_BASE,
-
-        AU1000_TOY_INT          = AU1100_FIRST_INT + 14,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-        AU1000_IRDA_TX_INT,
-        AU1000_IRDA_RX_INT,
-        AU1000_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_SUS_INT,
-        AU1000_USB_HOST_INT,
-        AU1000_ACSYNC_INT,
-        AU1100_MAC0_DMA_INT,
-        AU1100_GPIO_208_215,
-        AU1100_LCD_INT,
-        AU1000_AC97C_INT,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1000_GPIO_16,
-        AU1000_GPIO_17,
-        AU1000_GPIO_18,
-        AU1000_GPIO_19,
-        AU1000_GPIO_20,
-        AU1000_GPIO_21,
-        AU1000_GPIO_22,
-        AU1000_GPIO_23,
-        AU1000_GPIO_24,
-        AU1000_GPIO_25,
-        AU1000_GPIO_26,
-        AU1000_GPIO_27,
-        AU1000_GPIO_28,
-        AU1000_GPIO_29,
-        AU1000_GPIO_30,
-        AU1000_GPIO_31,
-};
-
-#define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
-#define UART3_ADDR              0xB1400000
-
-#define USB_OHCI_BASE           0x10100000      /* phys addr for ioremap */
-#define USB_HOST_CONFIG         0xB017FFFC
-
-#define AU1100_ETH0_BASE        0xB0500000
-#define AU1100_MAC0_ENABLE      0xB0520000
-#define NUM_ETH_INTERFACES 1
-#endif /* CONFIG_SOC_AU1100 */
-
-#ifdef CONFIG_SOC_AU1550
-enum soc_au1550_ints {
-        AU1550_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1550_UART0_INT        = AU1550_FIRST_INT,
-        AU1550_PCI_INTA,
-        AU1550_PCI_INTB,
-        AU1550_DDMA_INT,
-        AU1550_CRYPTO_INT,
-        AU1550_PCI_INTC,
-        AU1550_PCI_INTD,
-        AU1550_PCI_RST_INT,
-        AU1550_UART1_INT,
-        AU1550_UART3_INT,
-        AU1550_PSC0_INT,
-        AU1550_PSC1_INT,
-        AU1550_PSC2_INT,
-        AU1550_PSC3_INT,
-        AU1000_TOY_INT,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-
-        AU1550_NAND_INT                 = AU1550_FIRST_INT + 23,
-        AU1550_USB_DEV_REQ_INT,
-        AU1000_USB_DEV_REQ_INT          = AU1550_USB_DEV_REQ_INT,
-        AU1550_USB_DEV_SUS_INT,
-        AU1000_USB_DEV_SUS_INT          = AU1550_USB_DEV_SUS_INT,
-        AU1550_USB_HOST_INT,
-        AU1000_USB_HOST_INT             = AU1550_USB_HOST_INT,
-        AU1550_MAC0_DMA_INT,
-        AU1550_MAC1_DMA_INT,
-        AU1000_GPIO_0                   = AU1550_FIRST_INT + 32,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1550_GPIO_200,
-        AU1500_GPIO_201_205,                    /* Logical or of GPIO201:205 */
-        AU1500_GPIO_16,
-        AU1500_GPIO_17,
-        AU1500_GPIO_20,
-        AU1500_GPIO_21,
-        AU1500_GPIO_22,
-        AU1500_GPIO_23,
-        AU1500_GPIO_24,
-        AU1500_GPIO_25,
-        AU1500_GPIO_26,
-        AU1500_GPIO_27,
-        AU1500_GPIO_28,
-        AU1500_GPIO_206,
-        AU1500_GPIO_207,
-        AU1500_GPIO_208_218,                    /* Logical or of GPIO208:218 */
-};
-
-/* shortcuts */
-#define INTA AU1550_PCI_INTA
-#define INTB AU1550_PCI_INTB
-#define INTC AU1550_PCI_INTC
-#define INTD AU1550_PCI_INTD
-
-#define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
-#define UART3_ADDR              0xB1400000
-
-#define USB_OHCI_BASE           0x14020000      /* phys addr for ioremap */
-#define USB_OHCI_LEN            0x00060000
-#define USB_HOST_CONFIG         0xB4027ffc
-
-#define AU1550_ETH0_BASE        0xB0500000
-#define AU1550_ETH1_BASE        0xB0510000
-#define AU1550_MAC0_ENABLE      0xB0520000
-#define AU1550_MAC1_ENABLE      0xB0520004
-#define NUM_ETH_INTERFACES 2
-#endif /* CONFIG_SOC_AU1550 */
-
-#ifdef CONFIG_SOC_AU1200
-enum soc_au1200_ints {
-        AU1200_FIRST_INT        = MIPS_CPU_IRQ_BASE + 8,
-        AU1200_UART0_INT        = AU1200_FIRST_INT,
-        AU1200_SWT_INT,
-        AU1200_SD_INT,
-        AU1200_DDMA_INT,
-        AU1200_MAE_BE_INT,
-        AU1200_GPIO_200,
-        AU1200_GPIO_201,
-        AU1200_GPIO_202,
-        AU1200_UART1_INT,
-        AU1200_MAE_FE_INT,
-        AU1200_PSC0_INT,
-        AU1200_PSC1_INT,
-        AU1200_AES_INT,
-        AU1200_CAMERA_INT,
-        AU1000_TOY_INT,
-        AU1000_TOY_MATCH0_INT,
-        AU1000_TOY_MATCH1_INT,
-        AU1000_TOY_MATCH2_INT,
-        AU1000_RTC_INT,
-        AU1000_RTC_MATCH0_INT,
-        AU1000_RTC_MATCH1_INT,
-        AU1000_RTC_MATCH2_INT,
-
-        AU1200_NAND_INT         = AU1200_FIRST_INT + 23,
-        AU1200_GPIO_204,
-        AU1200_GPIO_205,
-        AU1200_GPIO_206,
-        AU1200_GPIO_207,
-        AU1200_GPIO_208_215,                    /* Logical OR of 208:215 */
-        AU1200_USB_INT,
-        AU1000_USB_HOST_INT     = AU1200_USB_INT,
-        AU1200_LCD_INT,
-        AU1200_MAE_BOTH_INT,
-        AU1000_GPIO_0,
-        AU1000_GPIO_1,
-        AU1000_GPIO_2,
-        AU1000_GPIO_3,
-        AU1000_GPIO_4,
-        AU1000_GPIO_5,
-        AU1000_GPIO_6,
-        AU1000_GPIO_7,
-        AU1000_GPIO_8,
-        AU1000_GPIO_9,
-        AU1000_GPIO_10,
-        AU1000_GPIO_11,
-        AU1000_GPIO_12,
-        AU1000_GPIO_13,
-        AU1000_GPIO_14,
-        AU1000_GPIO_15,
-        AU1000_GPIO_16,
-        AU1000_GPIO_17,
-        AU1000_GPIO_18,
-        AU1000_GPIO_19,
-        AU1000_GPIO_20,
-        AU1000_GPIO_21,
-        AU1000_GPIO_22,
-        AU1000_GPIO_23,
-        AU1000_GPIO_24,
-        AU1000_GPIO_25,
-        AU1000_GPIO_26,
-        AU1000_GPIO_27,
-        AU1000_GPIO_28,
-        AU1000_GPIO_29,
-        AU1000_GPIO_30,
-        AU1000_GPIO_31,
-};
-
-#define UART0_ADDR              0xB1100000
-#define UART1_ADDR              0xB1200000
-
-#define USB_UOC_BASE            0x14020020
-#define USB_UOC_LEN             0x20
-#define USB_OHCI_BASE           0x14020100
-#define USB_OHCI_LEN            0x100
-#define USB_EHCI_BASE           0x14020200
-#define USB_EHCI_LEN            0x100
-#define USB_UDC_BASE            0x14022000
-#define USB_UDC_LEN             0x2000
-#define USB_MSR_BASE            0xB4020000
-#define USB_MSR_MCFG            4
-#define USBMSRMCFG_OMEMEN       0
-#define USBMSRMCFG_OBMEN        1
-#define USBMSRMCFG_EMEMEN       2
-#define USBMSRMCFG_EBMEN        3
-#define USBMSRMCFG_DMEMEN       4
-#define USBMSRMCFG_DBMEN        5
-#define USBMSRMCFG_GMEMEN       6
-#define USBMSRMCFG_OHCCLKEN     16
-#define USBMSRMCFG_EHCCLKEN     17
-#define USBMSRMCFG_UDCCLKEN     18
-#define USBMSRMCFG_PHYPLLEN     19
-#define USBMSRMCFG_RDCOMB       30
-#define USBMSRMCFG_PFEN         31
-
-#endif /* CONFIG_SOC_AU1200 */
-
-#define AU1000_INTC0_INT_BASE   (MIPS_CPU_IRQ_BASE + 8)
-#define AU1000_INTC0_INT_LAST   (AU1000_INTC0_INT_BASE + 31)
-#define AU1000_INTC1_INT_BASE   (AU1000_INTC0_INT_BASE + 32)
-#define AU1000_INTC1_INT_LAST   (AU1000_INTC1_INT_BASE + 31)
-
-#define AU1000_MAX_INTR         AU1000_INTC1_INT_LAST
-#define INTX                    0xFF                    /* not valid */
-
-/* Programmable Counters 0 and 1 */
-#define SYS_BASE                0xB1900000
-#define SYS_COUNTER_CNTRL       (SYS_BASE + 0x14)
-#  define SYS_CNTRL_E1S         (1 << 23)
-#  define SYS_CNTRL_T1S         (1 << 20)
-#  define SYS_CNTRL_M21         (1 << 19)
-#  define SYS_CNTRL_M11         (1 << 18)
-#  define SYS_CNTRL_M01         (1 << 17)
-#  define SYS_CNTRL_C1S         (1 << 16)
-#  define SYS_CNTRL_BP          (1 << 14)
-#  define SYS_CNTRL_EN1         (1 << 13)
-#  define SYS_CNTRL_BT1         (1 << 12)
-#  define SYS_CNTRL_EN0         (1 << 11)
-#  define SYS_CNTRL_BT0         (1 << 10)
-#  define SYS_CNTRL_E0          (1 << 8)
-#  define SYS_CNTRL_E0S         (1 << 7)
-#  define SYS_CNTRL_32S         (1 << 5)
-#  define SYS_CNTRL_T0S         (1 << 4)
-#  define SYS_CNTRL_M20         (1 << 3)
-#  define SYS_CNTRL_M10         (1 << 2)
-#  define SYS_CNTRL_M00         (1 << 1)
-#  define SYS_CNTRL_C0S         (1 << 0)
-
-/* Programmable Counter 0 Registers */
-#define SYS_TOYTRIM             (SYS_BASE + 0)
-#define SYS_TOYWRITE            (SYS_BASE + 4)
-#define SYS_TOYMATCH0           (SYS_BASE + 8)
-#define SYS_TOYMATCH1           (SYS_BASE + 0xC)
-#define SYS_TOYMATCH2           (SYS_BASE + 0x10)
-#define SYS_TOYREAD             (SYS_BASE + 0x40)
-
-/* Programmable Counter 1 Registers */
-#define SYS_RTCTRIM             (SYS_BASE + 0x44)
-#define SYS_RTCWRITE            (SYS_BASE + 0x48)
-#define SYS_RTCMATCH0           (SYS_BASE + 0x4C)
-#define SYS_RTCMATCH1           (SYS_BASE + 0x50)
-#define SYS_RTCMATCH2           (SYS_BASE + 0x54)
-#define SYS_RTCREAD             (SYS_BASE + 0x58)
-
-/* I2S Controller */
-#define I2S_DATA                0xB1000000
-#  define I2S_DATA_MASK         0xffffff
-#define I2S_CONFIG              0xB1000004
-#  define I2S_CONFIG_XU         (1 << 25)
-#  define I2S_CONFIG_XO         (1 << 24)
-#  define I2S_CONFIG_RU         (1 << 23)
-#  define I2S_CONFIG_RO         (1 << 22)
-#  define I2S_CONFIG_TR         (1 << 21)
-#  define I2S_CONFIG_TE         (1 << 20)
-#  define I2S_CONFIG_TF         (1 << 19)
-#  define I2S_CONFIG_RR         (1 << 18)
-#  define I2S_CONFIG_RE         (1 << 17)
-#  define I2S_CONFIG_RF         (1 << 16)
-#  define I2S_CONFIG_PD         (1 << 11)
-#  define I2S_CONFIG_LB         (1 << 10)
-#  define I2S_CONFIG_IC         (1 << 9)
-#  define I2S_CONFIG_FM_BIT     7
-#  define I2S_CONFIG_FM_MASK    (0x3 << I2S_CONFIG_FM_BIT)
-#    define I2S_CONFIG_FM_I2S   (0x0 << I2S_CONFIG_FM_BIT)
-#    define I2S_CONFIG_FM_LJ    (0x1 << I2S_CONFIG_FM_BIT)
-#    define I2S_CONFIG_FM_RJ    (0x2 << I2S_CONFIG_FM_BIT)
-#  define I2S_CONFIG_TN         (1 << 6)
-#  define I2S_CONFIG_RN         (1 << 5)
-#  define I2S_CONFIG_SZ_BIT     0
-#  define I2S_CONFIG_SZ_MASK    (0x1F << I2S_CONFIG_SZ_BIT)
-
-#define I2S_CONTROL             0xB1000008
-#  define I2S_CONTROL_D         (1 << 1)
-#  define I2S_CONTROL_CE        (1 << 0)
-
-/* USB Host Controller */
-#ifndef USB_OHCI_LEN
-#define USB_OHCI_LEN            0x00100000
-#endif
-
-#ifndef CONFIG_SOC_AU1200
-
-/* USB Device Controller */
-#define USBD_EP0RD              0xB0200000
-#define USBD_EP0WR              0xB0200004
-#define USBD_EP2WR              0xB0200008
-#define USBD_EP3WR              0xB020000C
-#define USBD_EP4RD              0xB0200010
-#define USBD_EP5RD              0xB0200014
-#define USBD_INTEN              0xB0200018
-#define USBD_INTSTAT            0xB020001C
-#  define USBDEV_INT_SOF        (1 << 12)
-#  define USBDEV_INT_HF_BIT     6
-#  define USBDEV_INT_HF_MASK    (0x3f << USBDEV_INT_HF_BIT)
-#  define USBDEV_INT_CMPLT_BIT  0
-#  define USBDEV_INT_CMPLT_MASK (0x3f << USBDEV_INT_CMPLT_BIT)
-#define USBD_CONFIG             0xB0200020
-#define USBD_EP0CS              0xB0200024
-#define USBD_EP2CS              0xB0200028
-#define USBD_EP3CS              0xB020002C
-#define USBD_EP4CS              0xB0200030
-#define USBD_EP5CS              0xB0200034
-#  define USBDEV_CS_SU          (1 << 14)
-#  define USBDEV_CS_NAK         (1 << 13)
-#  define USBDEV_CS_ACK         (1 << 12)
-#  define USBDEV_CS_BUSY        (1 << 11)
-#  define USBDEV_CS_TSIZE_BIT   1
-#  define USBDEV_CS_TSIZE_MASK  (0x3ff << USBDEV_CS_TSIZE_BIT)
-#  define USBDEV_CS_STALL       (1 << 0)
-#define USBD_EP0RDSTAT          0xB0200040
-#define USBD_EP0WRSTAT          0xB0200044
-#define USBD_EP2WRSTAT          0xB0200048
-#define USBD_EP3WRSTAT          0xB020004C
-#define USBD_EP4RDSTAT          0xB0200050
-#define USBD_EP5RDSTAT          0xB0200054
-#  define USBDEV_FSTAT_FLUSH    (1 << 6)
-#  define USBDEV_FSTAT_UF       (1 << 5)
-#  define USBDEV_FSTAT_OF       (1 << 4)
-#  define USBDEV_FSTAT_FCNT_BIT 0
-#  define USBDEV_FSTAT_FCNT_MASK (0x0f << USBDEV_FSTAT_FCNT_BIT)
-#define USBD_ENABLE             0xB0200058
-#  define USBDEV_ENABLE         (1 << 1)
-#  define USBDEV_CE             (1 << 0)
-
-#endif /* !CONFIG_SOC_AU1200 */
-
-/* Ethernet Controllers  */
-
-/* 4 byte offsets from AU1000_ETH_BASE */
-#define MAC_CONTROL             0x0
-#  define MAC_RX_ENABLE         (1 << 2)
-#  define MAC_TX_ENABLE         (1 << 3)
-#  define MAC_DEF_CHECK         (1 << 5)
-#  define MAC_SET_BL(X)         (((X) & 0x3) << 6)
-#  define MAC_AUTO_PAD          (1 << 8)
-#  define MAC_DISABLE_RETRY     (1 << 10)
-#  define MAC_DISABLE_BCAST     (1 << 11)
-#  define MAC_LATE_COL          (1 << 12)
-#  define MAC_HASH_MODE         (1 << 13)
-#  define MAC_HASH_ONLY         (1 << 15)
-#  define MAC_PASS_ALL          (1 << 16)
-#  define MAC_INVERSE_FILTER    (1 << 17)
-#  define MAC_PROMISCUOUS       (1 << 18)
-#  define MAC_PASS_ALL_MULTI    (1 << 19)
-#  define MAC_FULL_DUPLEX       (1 << 20)
-#  define MAC_NORMAL_MODE       0
-#  define MAC_INT_LOOPBACK      (1 << 21)
-#  define MAC_EXT_LOOPBACK      (1 << 22)
-#  define MAC_DISABLE_RX_OWN    (1 << 23)
-#  define MAC_BIG_ENDIAN        (1 << 30)
-#  define MAC_RX_ALL            (1 << 31)
-#define MAC_ADDRESS_HIGH        0x4
-#define MAC_ADDRESS_LOW         0x8
-#define MAC_MCAST_HIGH          0xC
-#define MAC_MCAST_LOW           0x10
-#define MAC_MII_CNTRL           0x14
-#  define MAC_MII_BUSY          (1 << 0)
-#  define MAC_MII_READ          0
-#  define MAC_MII_WRITE         (1 << 1)
-#  define MAC_SET_MII_SELECT_REG(X) (((X) & 0x1f) << 6)
-#  define MAC_SET_MII_SELECT_PHY(X) (((X) & 0x1f) << 11)
-#define MAC_MII_DATA            0x18
-#define MAC_FLOW_CNTRL          0x1C
-#  define MAC_FLOW_CNTRL_BUSY   (1 << 0)
-#  define MAC_FLOW_CNTRL_ENABLE (1 << 1)
-#  define MAC_PASS_CONTROL      (1 << 2)
-#  define MAC_SET_PAUSE(X)      (((X) & 0xffff) << 16)
-#define MAC_VLAN1_TAG           0x20
-#define MAC_VLAN2_TAG           0x24
-
-/* Ethernet Controller Enable */
-
-#  define MAC_EN_CLOCK_ENABLE   (1 << 0)
-#  define MAC_EN_RESET0         (1 << 1)
-#  define MAC_EN_TOSS           (0 << 2)
-#  define MAC_EN_CACHEABLE      (1 << 3)
-#  define MAC_EN_RESET1         (1 << 4)
-#  define MAC_EN_RESET2         (1 << 5)
-#  define MAC_DMA_RESET         (1 << 6)
-
-/* Ethernet Controller DMA Channels */
-
-#define MAC0_TX_DMA_ADDR        0xB4004000
-#define MAC1_TX_DMA_ADDR        0xB4004200
-/* offsets from MAC_TX_RING_ADDR address */
-#define MAC_TX_BUFF0_STATUS     0x0
-#  define TX_FRAME_ABORTED      (1 << 0)
-#  define TX_JAB_TIMEOUT        (1 << 1)
-#  define TX_NO_CARRIER         (1 << 2)
-#  define TX_LOSS_CARRIER       (1 << 3)
-#  define TX_EXC_DEF            (1 << 4)
-#  define TX_LATE_COLL_ABORT    (1 << 5)
-#  define TX_EXC_COLL           (1 << 6)
-#  define TX_UNDERRUN           (1 << 7)
-#  define TX_DEFERRED           (1 << 8)
-#  define TX_LATE_COLL          (1 << 9)
-#  define TX_COLL_CNT_MASK      (0xF << 10)
-#  define TX_PKT_RETRY          (1 << 31)
-#define MAC_TX_BUFF0_ADDR       0x4
-#  define TX_DMA_ENABLE         (1 << 0)
-#  define TX_T_DONE             (1 << 1)
-#  define TX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
-#define MAC_TX_BUFF0_LEN        0x8
-#define MAC_TX_BUFF1_STATUS     0x10
-#define MAC_TX_BUFF1_ADDR       0x14
-#define MAC_TX_BUFF1_LEN        0x18
-#define MAC_TX_BUFF2_STATUS     0x20
-#define MAC_TX_BUFF2_ADDR       0x24
-#define MAC_TX_BUFF2_LEN        0x28
-#define MAC_TX_BUFF3_STATUS     0x30
-#define MAC_TX_BUFF3_ADDR       0x34
-#define MAC_TX_BUFF3_LEN        0x38
-
-#define MAC0_RX_DMA_ADDR        0xB4004100
-#define MAC1_RX_DMA_ADDR        0xB4004300
-/* offsets from MAC_RX_RING_ADDR */
-#define MAC_RX_BUFF0_STATUS     0x0
-#  define RX_FRAME_LEN_MASK     0x3fff
-#  define RX_WDOG_TIMER         (1 << 14)
-#  define RX_RUNT               (1 << 15)
-#  define RX_OVERLEN            (1 << 16)
-#  define RX_COLL               (1 << 17)
-#  define RX_ETHER              (1 << 18)
-#  define RX_MII_ERROR          (1 << 19)
-#  define RX_DRIBBLING          (1 << 20)
-#  define RX_CRC_ERROR          (1 << 21)
-#  define RX_VLAN1              (1 << 22)
-#  define RX_VLAN2              (1 << 23)
-#  define RX_LEN_ERROR          (1 << 24)
-#  define RX_CNTRL_FRAME        (1 << 25)
-#  define RX_U_CNTRL_FRAME      (1 << 26)
-#  define RX_MCAST_FRAME        (1 << 27)
-#  define RX_BCAST_FRAME        (1 << 28)
-#  define RX_FILTER_FAIL        (1 << 29)
-#  define RX_PACKET_FILTER      (1 << 30)
-#  define RX_MISSED_FRAME       (1 << 31)
-
-#  define RX_ERROR (RX_WDOG_TIMER | RX_RUNT | RX_OVERLEN |  \
-                    RX_COLL | RX_MII_ERROR | RX_CRC_ERROR | \
-                    RX_LEN_ERROR | RX_U_CNTRL_FRAME | RX_MISSED_FRAME)
-#define MAC_RX_BUFF0_ADDR       0x4
-#  define RX_DMA_ENABLE         (1 << 0)
-#  define RX_T_DONE             (1 << 1)
-#  define RX_GET_DMA_BUFFER(X)  (((X) >> 2) & 0x3)
-#  define RX_SET_BUFF_ADDR(X)   ((X) & 0xffffffc0)
-#define MAC_RX_BUFF1_STATUS     0x10
-#define MAC_RX_BUFF1_ADDR       0x14
-#define MAC_RX_BUFF2_STATUS     0x20
-#define MAC_RX_BUFF2_ADDR       0x24
-#define MAC_RX_BUFF3_STATUS     0x30
-#define MAC_RX_BUFF3_ADDR       0x34
-
-/* UARTS 0-3 */
-#define UART_BASE               UART0_ADDR
-#ifdef  CONFIG_SOC_AU1200
-#define UART_DEBUG_BASE         UART1_ADDR
-#else
-#define UART_DEBUG_BASE         UART3_ADDR
-#endif
-
-#define UART_RX         0       /* Receive buffer */
-#define UART_TX         4       /* Transmit buffer */
-#define UART_IER        8       /* Interrupt Enable Register */
-#define UART_IIR        0xC     /* Interrupt ID Register */
-#define UART_FCR        0x10    /* FIFO Control Register */
-#define UART_LCR        0x14    /* Line Control Register */
-#define UART_MCR        0x18    /* Modem Control Register */
-#define UART_LSR        0x1C    /* Line Status Register */
-#define UART_MSR        0x20    /* Modem Status Register */
-#define UART_CLK        0x28    /* Baud Rate Clock Divider */
-#define UART_MOD_CNTRL  0x100   /* Module Control */
-
-#define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
-#define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
-#define UART_FCR_CLEAR_XMIT     0x04 /* Clear the XMIT FIFO */
-#define UART_FCR_DMA_SELECT     0x08 /* For DMA applications */
-#define UART_FCR_TRIGGER_MASK   0xF0 /* Mask for the FIFO trigger range */
-#define UART_FCR_R_TRIGGER_1    0x00 /* Mask for receive trigger set at 1 */
-#define UART_FCR_R_TRIGGER_4    0x40 /* Mask for receive trigger set at 4 */
-#define UART_FCR_R_TRIGGER_8    0x80 /* Mask for receive trigger set at 8 */
-#define UART_FCR_R_TRIGGER_14   0xA0 /* Mask for receive trigger set at 14 */
-#define UART_FCR_T_TRIGGER_0    0x00 /* Mask for transmit trigger set at 0 */
-#define UART_FCR_T_TRIGGER_4    0x10 /* Mask for transmit trigger set at 4 */
-#define UART_FCR_T_TRIGGER_8    0x20 /* Mask for transmit trigger set at 8 */
-#define UART_FCR_T_TRIGGER_12   0x30 /* Mask for transmit trigger set at 12 */
-
-/*
- * These are the definitions for the Line Control Register
- */
-#define UART_LCR_SBC    0x40    /* Set break control */
-#define UART_LCR_SPAR   0x20    /* Stick parity (?) */
-#define UART_LCR_EPAR   0x10    /* Even parity select */
-#define UART_LCR_PARITY 0x08    /* Parity Enable */
-#define UART_LCR_STOP   0x04    /* Stop bits: 0=1 stop bit, 1= 2 stop bits */
-#define UART_LCR_WLEN5  0x00    /* Wordlength: 5 bits */
-#define UART_LCR_WLEN6  0x01    /* Wordlength: 6 bits */
-#define UART_LCR_WLEN7  0x02    /* Wordlength: 7 bits */
-#define UART_LCR_WLEN8  0x03    /* Wordlength: 8 bits */
-
-/*
- * These are the definitions for the Line Status Register
- */
-#define UART_LSR_TEMT   0x40    /* Transmitter empty */
-#define UART_LSR_THRE   0x20    /* Transmit-hold-register empty */
-#define UART_LSR_BI     0x10    /* Break interrupt indicator */
-#define UART_LSR_FE     0x08    /* Frame error indicator */
-#define UART_LSR_PE     0x04    /* Parity error indicator */
-#define UART_LSR_OE     0x02    /* Overrun error indicator */
-#define UART_LSR_DR     0x01    /* Receiver data ready */
-
-/*
- * These are the definitions for the Interrupt Identification Register
- */
-#define UART_IIR_NO_INT 0x01    /* No interrupts pending */
-#define UART_IIR_ID     0x06    /* Mask for the interrupt ID */
-#define UART_IIR_MSI    0x00    /* Modem status interrupt */
-#define UART_IIR_THRI   0x02    /* Transmitter holding register empty */
-#define UART_IIR_RDI    0x04    /* Receiver data interrupt */
-#define UART_IIR_RLSI   0x06    /* Receiver line status interrupt */
-
-/*
- * These are the definitions for the Interrupt Enable Register
- */
-#define UART_IER_MSI    0x08    /* Enable Modem status interrupt */
-#define UART_IER_RLSI   0x04    /* Enable receiver line status interrupt */
-#define UART_IER_THRI   0x02    /* Enable Transmitter holding register int. */
-#define UART_IER_RDI    0x01    /* Enable receiver data interrupt */
-
-/*
- * These are the definitions for the Modem Control Register
- */
-#define UART_MCR_LOOP   0x10    /* Enable loopback test mode */
-#define UART_MCR_OUT2   0x08    /* Out2 complement */
-#define UART_MCR_OUT1   0x04    /* Out1 complement */
-#define UART_MCR_RTS    0x02    /* RTS complement */
-#define UART_MCR_DTR    0x01    /* DTR complement */
-
-/*
- * These are the definitions for the Modem Status Register
- */
-#define UART_MSR_DCD    0x80    /* Data Carrier Detect */
-#define UART_MSR_RI     0x40    /* Ring Indicator */
-#define UART_MSR_DSR    0x20    /* Data Set Ready */
-#define UART_MSR_CTS    0x10    /* Clear to Send */
-#define UART_MSR_DDCD   0x08    /* Delta DCD */
-#define UART_MSR_TERI   0x04    /* Trailing edge ring indicator */
-#define UART_MSR_DDSR   0x02    /* Delta DSR */
-#define UART_MSR_DCTS   0x01    /* Delta CTS */
-#define UART_MSR_ANY_DELTA 0x0F /* Any of the delta bits! */
-
-/* SSIO */
-#define SSI0_STATUS             0xB1600000
-#  define SSI_STATUS_BF         (1 << 4)
-#  define SSI_STATUS_OF         (1 << 3)
-#  define SSI_STATUS_UF         (1 << 2)
-#  define SSI_STATUS_D          (1 << 1)
-#  define SSI_STATUS_B          (1 << 0)
-#define SSI0_INT                0xB1600004
-#  define SSI_INT_OI            (1 << 3)
-#  define SSI_INT_UI            (1 << 2)
-#  define SSI_INT_DI            (1 << 1)
-#define SSI0_INT_ENABLE         0xB1600008
-#  define SSI_INTE_OIE          (1 << 3)
-#  define SSI_INTE_UIE          (1 << 2)
-#  define SSI_INTE_DIE          (1 << 1)
-#define SSI0_CONFIG             0xB1600020
-#  define SSI_CONFIG_AO         (1 << 24)
-#  define SSI_CONFIG_DO         (1 << 23)
-#  define SSI_CONFIG_ALEN_BIT   20
-#  define SSI_CONFIG_ALEN_MASK  (0x7 << 20)
-#  define SSI_CONFIG_DLEN_BIT   16
-#  define SSI_CONFIG_DLEN_MASK  (0x7 << 16)
-#  define SSI_CONFIG_DD         (1 << 11)
-#  define SSI_CONFIG_AD         (1 << 10)
-#  define SSI_CONFIG_BM_BIT     8
-#  define SSI_CONFIG_BM_MASK    (0x3 << 8)
-#  define SSI_CONFIG_CE         (1 << 7)
-#  define SSI_CONFIG_DP         (1 << 6)
-#  define SSI_CONFIG_DL         (1 << 5)
-#  define SSI_CONFIG_EP         (1 << 4)
-#define SSI0_ADATA              0xB1600024
-#  define SSI_AD_D              (1 << 24)
-#  define SSI_AD_ADDR_BIT       16
-#  define SSI_AD_ADDR_MASK      (0xff << 16)
-#  define SSI_AD_DATA_BIT       0
-#  define SSI_AD_DATA_MASK      (0xfff << 0)
-#define SSI0_CLKDIV             0xB1600028
-#define SSI0_CONTROL            0xB1600100
-#  define SSI_CONTROL_CD        (1 << 1)
-#  define SSI_CONTROL_E         (1 << 0)
-
-/* SSI1 */
-#define SSI1_STATUS             0xB1680000
-#define SSI1_INT                0xB1680004
-#define SSI1_INT_ENABLE         0xB1680008
-#define SSI1_CONFIG             0xB1680020
-#define SSI1_ADATA              0xB1680024
-#define SSI1_CLKDIV             0xB1680028
-#define SSI1_ENABLE             0xB1680100
-
-/*
- * Register content definitions
- */
-#define SSI_STATUS_BF           (1 << 4)
-#define SSI_STATUS_OF           (1 << 3)
-#define SSI_STATUS_UF           (1 << 2)
-#define SSI_STATUS_D            (1 << 1)
-#define SSI_STATUS_B            (1 << 0)
-
-/* SSI_INT */
-#define SSI_INT_OI              (1 << 3)
-#define SSI_INT_UI              (1 << 2)
-#define SSI_INT_DI              (1 << 1)
-
-/* SSI_INTEN */
-#define SSI_INTEN_OIE           (1 << 3)
-#define SSI_INTEN_UIE           (1 << 2)
-#define SSI_INTEN_DIE           (1 << 1)
-
-#define SSI_CONFIG_AO           (1 << 24)
-#define SSI_CONFIG_DO           (1 << 23)
-#define SSI_CONFIG_ALEN         (7 << 20)
-#define SSI_CONFIG_DLEN         (15 << 16)
-#define SSI_CONFIG_DD           (1 << 11)
-#define SSI_CONFIG_AD           (1 << 10)
-#define SSI_CONFIG_BM           (3 << 8)
-#define SSI_CONFIG_CE           (1 << 7)
-#define SSI_CONFIG_DP           (1 << 6)
-#define SSI_CONFIG_DL           (1 << 5)
-#define SSI_CONFIG_EP           (1 << 4)
-#define SSI_CONFIG_ALEN_N(N)    ((N-1) << 20)
-#define SSI_CONFIG_DLEN_N(N)    ((N-1) << 16)
-#define SSI_CONFIG_BM_HI        (0 << 8)
-#define SSI_CONFIG_BM_LO        (1 << 8)
-#define SSI_CONFIG_BM_CY        (2 << 8)
-
-#define SSI_ADATA_D             (1 << 24)
-#define SSI_ADATA_ADDR          (0xFF << 16)
-#define SSI_ADATA_DATA          0x0FFF
-#define SSI_ADATA_ADDR_N(N)     (N << 16)
-
-#define SSI_ENABLE_CD           (1 << 1)
-#define SSI_ENABLE_E            (1 << 0)
-
-/* IrDA Controller */
-#define IRDA_BASE               0xB0300000
-#define IR_RING_PTR_STATUS      (IRDA_BASE + 0x00)
-#define IR_RING_BASE_ADDR_H     (IRDA_BASE + 0x04)
-#define IR_RING_BASE_ADDR_L     (IRDA_BASE + 0x08)
-#define IR_RING_SIZE            (IRDA_BASE + 0x0C)
-#define IR_RING_PROMPT          (IRDA_BASE + 0x10)
-#define IR_RING_ADDR_CMPR       (IRDA_BASE + 0x14)
-#define IR_INT_CLEAR            (IRDA_BASE + 0x18)
-#define IR_CONFIG_1             (IRDA_BASE + 0x20)
-#  define IR_RX_INVERT_LED      (1 << 0)
-#  define IR_TX_INVERT_LED      (1 << 1)
-#  define IR_ST                 (1 << 2)
-#  define IR_SF                 (1 << 3)
-#  define IR_SIR                (1 << 4)
-#  define IR_MIR                (1 << 5)
-#  define IR_FIR                (1 << 6)
-#  define IR_16CRC              (1 << 7)
-#  define IR_TD                 (1 << 8)
-#  define IR_RX_ALL             (1 << 9)
-#  define IR_DMA_ENABLE         (1 << 10)
-#  define IR_RX_ENABLE          (1 << 11)
-#  define IR_TX_ENABLE          (1 << 12)
-#  define IR_LOOPBACK           (1 << 14)
-#  define IR_SIR_MODE           (IR_SIR | IR_DMA_ENABLE | \
-                                 IR_RX_ALL | IR_RX_ENABLE | IR_SF | IR_16CRC)
-#define IR_SIR_FLAGS            (IRDA_BASE + 0x24)
-#define IR_ENABLE               (IRDA_BASE + 0x28)
-#  define IR_RX_STATUS          (1 << 9)
-#  define IR_TX_STATUS          (1 << 10)
-#define IR_READ_PHY_CONFIG      (IRDA_BASE + 0x2C)
-#define IR_WRITE_PHY_CONFIG     (IRDA_BASE + 0x30)
-#define IR_MAX_PKT_LEN          (IRDA_BASE + 0x34)
-#define IR_RX_BYTE_CNT          (IRDA_BASE + 0x38)
-#define IR_CONFIG_2             (IRDA_BASE + 0x3C)
-#  define IR_MODE_INV           (1 << 0)
-#  define IR_ONE_PIN            (1 << 1)
-#define IR_INTERFACE_CONFIG     (IRDA_BASE + 0x40)
-
-/* GPIO */
-#define SYS_PINFUNC             0xB190002C
-#  define SYS_PF_USB            (1 << 15)       /* 2nd USB device/host */
-#  define SYS_PF_U3             (1 << 14)       /* GPIO23/U3TXD */
-#  define SYS_PF_U2             (1 << 13)       /* GPIO22/U2TXD */
-#  define SYS_PF_U1             (1 << 12)       /* GPIO21/U1TXD */
-#  define SYS_PF_SRC            (1 << 11)       /* GPIO6/SROMCKE */
-#  define SYS_PF_CK5            (1 << 10)       /* GPIO3/CLK5 */
-#  define SYS_PF_CK4            (1 << 9)        /* GPIO2/CLK4 */
-#  define SYS_PF_IRF            (1 << 8)        /* GPIO15/IRFIRSEL */
-#  define SYS_PF_UR3            (1 << 7)        /* GPIO[14:9]/UART3 */
-#  define SYS_PF_I2D            (1 << 6)        /* GPIO8/I2SDI */
-#  define SYS_PF_I2S            (1 << 5)        /* I2S/GPIO[29:31] */
-#  define SYS_PF_NI2            (1 << 4)        /* NI2/GPIO[24:28] */
-#  define SYS_PF_U0             (1 << 3)        /* U0TXD/GPIO20 */
-#  define SYS_PF_RD             (1 << 2)        /* IRTXD/GPIO19 */
-#  define SYS_PF_A97            (1 << 1)        /* AC97/SSL1 */
-#  define SYS_PF_S0             (1 << 0)        /* SSI_0/GPIO[16:18] */
-
-/* Au1100 only */
-#  define SYS_PF_PC             (1 << 18)       /* PCMCIA/GPIO[207:204] */
-#  define SYS_PF_LCD            (1 << 17)       /* extern lcd/GPIO[203:200] */
-#  define SYS_PF_CS             (1 << 16)       /* EXTCLK0/32KHz to gpio2 */
-#  define SYS_PF_EX0            (1 << 9)        /* GPIO2/clock */
-
-/* Au1550 only.  Redefines lots of pins */
-#  define SYS_PF_PSC2_MASK      (7 << 17)
-#  define SYS_PF_PSC2_AC97      0
-#  define SYS_PF_PSC2_SPI       0
-#  define SYS_PF_PSC2_I2S       (1 << 17)
-#  define SYS_PF_PSC2_SMBUS     (3 << 17)
-#  define SYS_PF_PSC2_GPIO      (7 << 17)
-#  define SYS_PF_PSC3_MASK      (7 << 20)
-#  define SYS_PF_PSC3_AC97      0
-#  define SYS_PF_PSC3_SPI       0
-#  define SYS_PF_PSC3_I2S       (1 << 20)
-#  define SYS_PF_PSC3_SMBUS     (3 << 20)
-#  define SYS_PF_PSC3_GPIO      (7 << 20)
-#  define SYS_PF_PSC1_S1        (1 << 1)
-#  define SYS_PF_MUST_BE_SET    ((1 << 5) | (1 << 2))
-
-/* Au1200 only */
-#ifdef CONFIG_SOC_AU1200
-#define SYS_PINFUNC_DMA         (1 << 31)
-#define SYS_PINFUNC_S0A         (1 << 30)
-#define SYS_PINFUNC_S1A         (1 << 29)
-#define SYS_PINFUNC_LP0         (1 << 28)
-#define SYS_PINFUNC_LP1         (1 << 27)
-#define SYS_PINFUNC_LD16        (1 << 26)
-#define SYS_PINFUNC_LD8         (1 << 25)
-#define SYS_PINFUNC_LD1         (1 << 24)
-#define SYS_PINFUNC_LD0         (1 << 23)
-#define SYS_PINFUNC_P1A         (3 << 21)
-#define SYS_PINFUNC_P1B         (1 << 20)
-#define SYS_PINFUNC_FS3         (1 << 19)
-#define SYS_PINFUNC_P0A         (3 << 17)
-#define SYS_PINFUNC_CS          (1 << 16)
-#define SYS_PINFUNC_CIM         (1 << 15)
-#define SYS_PINFUNC_P1C         (1 << 14)
-#define SYS_PINFUNC_U1T         (1 << 12)
-#define SYS_PINFUNC_U1R         (1 << 11)
-#define SYS_PINFUNC_EX1         (1 << 10)
-#define SYS_PINFUNC_EX0         (1 << 9)
-#define SYS_PINFUNC_U0R         (1 << 8)
-#define SYS_PINFUNC_MC          (1 << 7)
-#define SYS_PINFUNC_S0B         (1 << 6)
-#define SYS_PINFUNC_S0C         (1 << 5)
-#define SYS_PINFUNC_P0B         (1 << 4)
-#define SYS_PINFUNC_U0T         (1 << 3)
-#define SYS_PINFUNC_S1B         (1 << 2)
-#endif
-
-#define SYS_TRIOUTRD            0xB1900100
-#define SYS_TRIOUTCLR           0xB1900100
-#define SYS_OUTPUTRD            0xB1900108
-#define SYS_OUTPUTSET           0xB1900108
-#define SYS_OUTPUTCLR           0xB190010C
-#define SYS_PINSTATERD          0xB1900110
-#define SYS_PININPUTEN          0xB1900110
-
-/* GPIO2, Au1500, Au1550 only */
-#define GPIO2_BASE              0xB1700000
-#define GPIO2_DIR               (GPIO2_BASE + 0)
-#define GPIO2_OUTPUT            (GPIO2_BASE + 8)
-#define GPIO2_PINSTATE          (GPIO2_BASE + 0xC)
-#define GPIO2_INTENABLE         (GPIO2_BASE + 0x10)
-#define GPIO2_ENABLE            (GPIO2_BASE + 0x14)
-
-/* Power Management */
-#define SYS_SCRATCH0            0xB1900018
-#define SYS_SCRATCH1            0xB190001C
-#define SYS_WAKEMSK             0xB1900034
-#define SYS_ENDIAN              0xB1900038
-#define SYS_POWERCTRL           0xB190003C
-#define SYS_WAKESRC             0xB190005C
-#define SYS_SLPPWR              0xB1900078
-#define SYS_SLEEP               0xB190007C
-
-/* Clock Controller */
-#define SYS_FREQCTRL0           0xB1900020
-#  define SYS_FC_FRDIV2_BIT     22
-#  define SYS_FC_FRDIV2_MASK    (0xff << SYS_FC_FRDIV2_BIT)
-#  define SYS_FC_FE2            (1 << 21)
-#  define SYS_FC_FS2            (1 << 20)
-#  define SYS_FC_FRDIV1_BIT     12
-#  define SYS_FC_FRDIV1_MASK    (0xff << SYS_FC_FRDIV1_BIT)
-#  define SYS_FC_FE1            (1 << 11)
-#  define SYS_FC_FS1            (1 << 10)
-#  define SYS_FC_FRDIV0_BIT     2
-#  define SYS_FC_FRDIV0_MASK    (0xff << SYS_FC_FRDIV0_BIT)
-#  define SYS_FC_FE0            (1 << 1)
-#  define SYS_FC_FS0            (1 << 0)
-#define SYS_FREQCTRL1           0xB1900024
-#  define SYS_FC_FRDIV5_BIT     22
-#  define SYS_FC_FRDIV5_MASK    (0xff << SYS_FC_FRDIV5_BIT)
-#  define SYS_FC_FE5            (1 << 21)
-#  define SYS_FC_FS5            (1 << 20)
-#  define SYS_FC_FRDIV4_BIT     12
-#  define SYS_FC_FRDIV4_MASK    (0xff << SYS_FC_FRDIV4_BIT)
-#  define SYS_FC_FE4            (1 << 11)
-#  define SYS_FC_FS4            (1 << 10)
-#  define SYS_FC_FRDIV3_BIT     2
-#  define SYS_FC_FRDIV3_MASK    (0xff << SYS_FC_FRDIV3_BIT)
-#  define SYS_FC_FE3            (1 << 1)
-#  define SYS_FC_FS3            (1 << 0)
-#define SYS_CLKSRC              0xB1900028
-#  define SYS_CS_ME1_BIT        27
-#  define SYS_CS_ME1_MASK       (0x7 << SYS_CS_ME1_BIT)
-#  define SYS_CS_DE1            (1 << 26)
-#  define SYS_CS_CE1            (1 << 25)
-#  define SYS_CS_ME0_BIT        22
-#  define SYS_CS_ME0_MASK       (0x7 << SYS_CS_ME0_BIT)
-#  define SYS_CS_DE0            (1 << 21)
-#  define SYS_CS_CE0            (1 << 20)
-#  define SYS_CS_MI2_BIT        17
-#  define SYS_CS_MI2_MASK       (0x7 << SYS_CS_MI2_BIT)
-#  define SYS_CS_DI2            (1 << 16)
-#  define SYS_CS_CI2            (1 << 15)
-#ifdef CONFIG_SOC_AU1100
-#  define SYS_CS_ML_BIT         7
-#  define SYS_CS_ML_MASK        (0x7 << SYS_CS_ML_BIT)
-#  define SYS_CS_DL             (1 << 6)
-#  define SYS_CS_CL             (1 << 5)
-#else
-#  define SYS_CS_MUH_BIT        12
-#  define SYS_CS_MUH_MASK       (0x7 << SYS_CS_MUH_BIT)
-#  define SYS_CS_DUH            (1 << 11)
-#  define SYS_CS_CUH            (1 << 10)
-#  define SYS_CS_MUD_BIT        7
-#  define SYS_CS_MUD_MASK       (0x7 << SYS_CS_MUD_BIT)
-#  define SYS_CS_DUD            (1 << 6)
-#  define SYS_CS_CUD            (1 << 5)
-#endif
-#  define SYS_CS_MIR_BIT        2
-#  define SYS_CS_MIR_MASK       (0x7 << SYS_CS_MIR_BIT)
-#  define SYS_CS_DIR            (1 << 1)
-#  define SYS_CS_CIR            (1 << 0)
-
-#  define SYS_CS_MUX_AUX        0x1
-#  define SYS_CS_MUX_FQ0        0x2
-#  define SYS_CS_MUX_FQ1        0x3
-#  define SYS_CS_MUX_FQ2        0x4
-#  define SYS_CS_MUX_FQ3        0x5
-#  define SYS_CS_MUX_FQ4        0x6
-#  define SYS_CS_MUX_FQ5        0x7
-#define SYS_CPUPLL              0xB1900060
-#define SYS_AUXPLL              0xB1900064
-
-/* AC97 Controller */
-#define AC97C_CONFIG            0xB0000000
-#  define AC97C_RECV_SLOTS_BIT  13
-#  define AC97C_RECV_SLOTS_MASK (0x3ff << AC97C_RECV_SLOTS_BIT)
-#  define AC97C_XMIT_SLOTS_BIT  3
-#  define AC97C_XMIT_SLOTS_MASK (0x3ff << AC97C_XMIT_SLOTS_BIT)
-#  define AC97C_SG              (1 << 2)
-#  define AC97C_SYNC            (1 << 1)
-#  define AC97C_RESET           (1 << 0)
-#define AC97C_STATUS            0xB0000004
-#  define AC97C_XU              (1 << 11)
-#  define AC97C_XO              (1 << 10)
-#  define AC97C_RU              (1 << 9)
-#  define AC97C_RO              (1 << 8)
-#  define AC97C_READY           (1 << 7)
-#  define AC97C_CP              (1 << 6)
-#  define AC97C_TR              (1 << 5)
-#  define AC97C_TE              (1 << 4)
-#  define AC97C_TF              (1 << 3)
-#  define AC97C_RR              (1 << 2)
-#  define AC97C_RE              (1 << 1)
-#  define AC97C_RF              (1 << 0)
-#define AC97C_DATA              0xB0000008
-#define AC97C_CMD               0xB000000C
-#  define AC97C_WD_BIT          16
-#  define AC97C_READ            (1 << 7)
-#  define AC97C_INDEX_MASK      0x7f
-#define AC97C_CNTRL             0xB0000010
-#  define AC97C_RS              (1 << 1)
-#  define AC97C_CE              (1 << 0)
-
-/* Secure Digital (SD) Controller */
-#define SD0_XMIT_FIFO   0xB0600000
-#define SD0_RECV_FIFO   0xB0600004
-#define SD1_XMIT_FIFO   0xB0680000
-#define SD1_RECV_FIFO   0xB0680004
-
-#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
-/* Au1500 PCI Controller */
-#define Au1500_CFG_BASE         0xB4005000      /* virtual, KSEG1 addr */
-#define Au1500_PCI_CMEM         (Au1500_CFG_BASE + 0)
-#define Au1500_PCI_CFG          (Au1500_CFG_BASE + 4)
-#  define PCI_ERROR             ((1 << 22) | (1 << 23) | (1 << 24) | \
-                                 (1 << 25) | (1 << 26) | (1 << 27))
-#define Au1500_PCI_B2BMASK_CCH  (Au1500_CFG_BASE + 8)
-#define Au1500_PCI_B2B0_VID     (Au1500_CFG_BASE + 0xC)
-#define Au1500_PCI_B2B1_ID      (Au1500_CFG_BASE + 0x10)
-#define Au1500_PCI_MWMASK_DEV   (Au1500_CFG_BASE + 0x14)
-#define Au1500_PCI_MWBASE_REV_CCL (Au1500_CFG_BASE + 0x18)
-#define Au1500_PCI_ERR_ADDR     (Au1500_CFG_BASE + 0x1C)
-#define Au1500_PCI_SPEC_INTACK  (Au1500_CFG_BASE + 0x20)
-#define Au1500_PCI_ID           (Au1500_CFG_BASE + 0x100)
-#define Au1500_PCI_STATCMD      (Au1500_CFG_BASE + 0x104)
-#define Au1500_PCI_CLASSREV     (Au1500_CFG_BASE + 0x108)
-#define Au1500_PCI_HDRTYPE      (Au1500_CFG_BASE + 0x10C)
-#define Au1500_PCI_MBAR         (Au1500_CFG_BASE + 0x110)
-
-#define Au1500_PCI_HDR          0xB4005100      /* virtual, KSEG1 addr */
-
-/*
- * All of our structures, like PCI resource, have 32-bit members.
- * Drivers are expected to do an ioremap on the PCI MEM resource, but it's
- * hard to store 0x4 0000 0000 in a 32-bit type.  We require a small patch
- * to __ioremap to check for addresses between (u32)Au1500_PCI_MEM_START and
- * (u32)Au1500_PCI_MEM_END and change those to the full 36-bit PCI MEM
- * addresses.  For PCI I/O, it's simpler because we get to do the ioremap
- * ourselves and then adjust the device's resources.
- */
-#define Au1500_EXT_CFG          0x600000000ULL
-#define Au1500_EXT_CFG_TYPE1    0x680000000ULL
-#define Au1500_PCI_IO_START     0x500000000ULL
-#define Au1500_PCI_IO_END       0x5000FFFFFULL
-#define Au1500_PCI_MEM_START    0x440000000ULL
-#define Au1500_PCI_MEM_END      0x44FFFFFFFULL
-
-#define PCI_IO_START    0x00001000
-#define PCI_IO_END      0x000FFFFF
-#define PCI_MEM_START   0x40000000
-#define PCI_MEM_END     0x4FFFFFFF
-
-#define PCI_FIRST_DEVFN (0 << 3)
-#define PCI_LAST_DEVFN  (19 << 3)
-
-#define IOPORT_RESOURCE_START   0x00001000      /* skip legacy probing */
-#define IOPORT_RESOURCE_END     0xffffffff
-#define IOMEM_RESOURCE_START    0x10000000
-#define IOMEM_RESOURCE_END      0xffffffff
-
-#else /* Au1000 and Au1100 and Au1200 */
-
-/* Don't allow any legacy ports probing */
-#define IOPORT_RESOURCE_START   0x10000000
-#define IOPORT_RESOURCE_END     0xffffffff
-#define IOMEM_RESOURCE_START    0x10000000
-#define IOMEM_RESOURCE_END      0xffffffff
-
-#define PCI_IO_START    0
-#define PCI_IO_END      0
-#define PCI_MEM_START   0
-#define PCI_MEM_END     0
-#define PCI_FIRST_DEVFN 0
-#define PCI_LAST_DEVFN  0
-
-#endif
-
-#ifndef _LANGUAGE_ASSEMBLY
-typedef volatile struct {
-        /* 0x0000 */ u32 toytrim;
-        /* 0x0004 */ u32 toywrite;
-        /* 0x0008 */ u32 toymatch0;
-        /* 0x000C */ u32 toymatch1;
-        /* 0x0010 */ u32 toymatch2;
-        /* 0x0014 */ u32 cntrctrl;
-        /* 0x0018 */ u32 scratch0;
-        /* 0x001C */ u32 scratch1;
-        /* 0x0020 */ u32 freqctrl0;
-        /* 0x0024 */ u32 freqctrl1;
-        /* 0x0028 */ u32 clksrc;
-        /* 0x002C */ u32 pinfunc;
-        /* 0x0030 */ u32 reserved0;
-        /* 0x0034 */ u32 wakemsk;
-        /* 0x0038 */ u32 endian;
-        /* 0x003C */ u32 powerctrl;
-        /* 0x0040 */ u32 toyread;
-        /* 0x0044 */ u32 rtctrim;
-        /* 0x0048 */ u32 rtcwrite;
-        /* 0x004C */ u32 rtcmatch0;
-        /* 0x0050 */ u32 rtcmatch1;
-        /* 0x0054 */ u32 rtcmatch2;
-        /* 0x0058 */ u32 rtcread;
-        /* 0x005C */ u32 wakesrc;
-        /* 0x0060 */ u32 cpupll;
-        /* 0x0064 */ u32 auxpll;
-        /* 0x0068 */ u32 reserved1;
-        /* 0x006C */ u32 reserved2;
-        /* 0x0070 */ u32 reserved3;
-        /* 0x0074 */ u32 reserved4;
-        /* 0x0078 */ u32 slppwr;
-        /* 0x007C */ u32 sleep;
-        /* 0x0080 */ u32 reserved5[32];
-        /* 0x0100 */ u32 trioutrd;
-#define trioutclr trioutrd
-        /* 0x0104 */ u32 reserved6;
-        /* 0x0108 */ u32 outputrd;
-#define outputset outputrd
-        /* 0x010C */ u32 outputclr;
-        /* 0x0110 */ u32 pinstaterd;
-#define pininputen pinstaterd
-} AU1X00_SYS;
-
-static AU1X00_SYS * const sys = (AU1X00_SYS *)SYS_BASE;
-
-#endif
-
-/*
- * Processor information based on PRID.
- * Copied from PowerPC.
- */
-#ifndef _LANGUAGE_ASSEMBLY
-struct cpu_spec {
-        /* CPU is matched via (PRID & prid_mask) == prid_value */
-        unsigned int    prid_mask;
-        unsigned int    prid_value;
-
-        char            *cpu_name;
-        unsigned char   cpu_od;         /* Set Config[OD] */
-        unsigned char   cpu_bclk;       /* Enable BCLK switching */
-        unsigned char   cpu_pll_wo;     /* sys_cpupll reg. write-only */
-};
-
-extern struct cpu_spec  cpu_specs[];
-extern struct cpu_spec  *cur_cpu_spec[];
-#endif
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/au1000_dma.h b/include/asm-mips/mach-au1x00/au1000_dma.h
deleted file mode 100644
index c333b4e1cd44..000000000000
--- a/include/asm-mips/mach-au1x00/au1000_dma.h
+++ /dev/null
@@ -1,458 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Defines for using and allocating DMA channels on the Alchemy
- *      Au1x00 MIPS processors.
- *
- * Copyright 2000, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-#ifndef __ASM_AU1000_DMA_H
-#define __ASM_AU1000_DMA_H
-
-#include <linux/io.h>           /* need byte IO */
-#include <linux/spinlock.h>     /* And spinlocks */
-#include <linux/delay.h>
-#include <asm/system.h>
-
-#define NUM_AU1000_DMA_CHANNELS 8
-
-/* DMA Channel Base Addresses */
-#define DMA_CHANNEL_BASE        0xB4002000
-#define DMA_CHANNEL_LEN         0x00000100
-
-/* DMA Channel Register Offsets */
-#define DMA_MODE_SET            0x00000000
-#define DMA_MODE_READ           DMA_MODE_SET
-#define DMA_MODE_CLEAR          0x00000004
-/* DMA Mode register bits follow */
-#define DMA_DAH_MASK            (0x0f << 20)
-#define DMA_DID_BIT             16
-#define DMA_DID_MASK            (0x0f << DMA_DID_BIT)
-#define DMA_DS                  (1 << 15)
-#define DMA_BE                  (1 << 13)
-#define DMA_DR                  (1 << 12)
-#define DMA_TS8                 (1 << 11)
-#define DMA_DW_BIT              9
-#define DMA_DW_MASK             (0x03 << DMA_DW_BIT)
-#define DMA_DW8                 (0 << DMA_DW_BIT)
-#define DMA_DW16                (1 << DMA_DW_BIT)
-#define DMA_DW32                (2 << DMA_DW_BIT)
-#define DMA_NC                  (1 << 8)
-#define DMA_IE                  (1 << 7)
-#define DMA_HALT                (1 << 6)
-#define DMA_GO                  (1 << 5)
-#define DMA_AB                  (1 << 4)
-#define DMA_D1                  (1 << 3)
-#define DMA_BE1                 (1 << 2)
-#define DMA_D0                  (1 << 1)
-#define DMA_BE0                 (1 << 0)
-
-#define DMA_PERIPHERAL_ADDR     0x00000008
-#define DMA_BUFFER0_START       0x0000000C
-#define DMA_BUFFER1_START       0x00000014
-#define DMA_BUFFER0_COUNT       0x00000010
-#define DMA_BUFFER1_COUNT       0x00000018
-#define DMA_BAH_BIT     16
-#define DMA_BAH_MASK    (0x0f << DMA_BAH_BIT)
-#define DMA_COUNT_BIT   0
-#define DMA_COUNT_MASK  (0xffff << DMA_COUNT_BIT)
-
-/* DMA Device IDs follow */
-enum {
-        DMA_ID_UART0_TX = 0,
-        DMA_ID_UART0_RX,
-        DMA_ID_GP04,
-        DMA_ID_GP05,
-        DMA_ID_AC97C_TX,
-        DMA_ID_AC97C_RX,
-        DMA_ID_UART3_TX,
-        DMA_ID_UART3_RX,
-        DMA_ID_USBDEV_EP0_RX,
-        DMA_ID_USBDEV_EP0_TX,
-        DMA_ID_USBDEV_EP2_TX,
-        DMA_ID_USBDEV_EP3_TX,
-        DMA_ID_USBDEV_EP4_RX,
-        DMA_ID_USBDEV_EP5_RX,
-        DMA_ID_I2S_TX,
-        DMA_ID_I2S_RX,
-        DMA_NUM_DEV
-};
-
-/* DMA Device ID's for 2nd bank (AU1100) follow */
-enum {
-        DMA_ID_SD0_TX = 0,
-        DMA_ID_SD0_RX,
-        DMA_ID_SD1_TX,
-        DMA_ID_SD1_RX,
-        DMA_NUM_DEV_BANK2
-};
-
-struct dma_chan {
-        int dev_id;             /* this channel is allocated if >= 0, */
-                                /* free otherwise */
-        unsigned int io;
-        const char *dev_str;
-        int irq;
-        void *irq_dev;
-        unsigned int fifo_addr;
-        unsigned int mode;
-};
-
-/* These are in arch/mips/au1000/common/dma.c */
-extern struct dma_chan au1000_dma_table[];
-extern int request_au1000_dma(int dev_id,
-                              const char *dev_str,
-                              irq_handler_t irqhandler,
-                              unsigned long irqflags,
-                              void *irq_dev_id);
-extern void free_au1000_dma(unsigned int dmanr);
-extern int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
-                                int length, int *eof, void *data);
-extern void dump_au1000_dma_channel(unsigned int dmanr);
-extern spinlock_t au1000_dma_spin_lock;
-
-static inline struct dma_chan *get_dma_chan(unsigned int dmanr)
-{
-        if (dmanr >= NUM_AU1000_DMA_CHANNELS ||
-            au1000_dma_table[dmanr].dev_id < 0)
-                return NULL;
-        return &au1000_dma_table[dmanr];
-}
-
-static inline unsigned long claim_dma_lock(void)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&au1000_dma_spin_lock, flags);
-        return flags;
-}
-
-static inline void release_dma_lock(unsigned long flags)
-{
-        spin_unlock_irqrestore(&au1000_dma_spin_lock, flags);
-}
-
-/*
- * Set the DMA buffer enable bits in the mode register.
- */
-static inline void enable_dma_buffer0(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(DMA_BE0, chan->io + DMA_MODE_SET);
-}
-
-static inline void enable_dma_buffer1(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(DMA_BE1, chan->io + DMA_MODE_SET);
-}
-static inline void enable_dma_buffers(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(DMA_BE0 | DMA_BE1, chan->io + DMA_MODE_SET);
-}
-
-static inline void start_dma(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(DMA_GO, chan->io + DMA_MODE_SET);
-}
-
-#define DMA_HALT_POLL 0x5000
-
-static inline void halt_dma(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-        int i;
-
-        if (!chan)
-                return;
-        au_writel(DMA_GO, chan->io + DMA_MODE_CLEAR);
-
-        /* Poll the halt bit */
-        for (i = 0; i < DMA_HALT_POLL; i++)
-                if (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT)
-                        break;
-        if (i == DMA_HALT_POLL)
-                printk(KERN_INFO "halt_dma: HALT poll expired!\n");
-}
-
-static inline void disable_dma(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-
-        halt_dma(dmanr);
-
-        /* Now we can disable the buffers */
-        au_writel(~DMA_GO, chan->io + DMA_MODE_CLEAR);
-}
-
-static inline int dma_halted(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return 1;
-        return (au_readl(chan->io + DMA_MODE_READ) & DMA_HALT) ? 1 : 0;
-}
-
-/* Initialize a DMA channel. */
-static inline void init_dma(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-        u32 mode;
-
-        if (!chan)
-                return;
-
-        disable_dma(dmanr);
-
-        /* Set device FIFO address */
-        au_writel(CPHYSADDR(chan->fifo_addr), chan->io + DMA_PERIPHERAL_ADDR);
-
-        mode = chan->mode | (chan->dev_id << DMA_DID_BIT);
-        if (chan->irq)
-                mode |= DMA_IE;
-
-        au_writel(~mode, chan->io + DMA_MODE_CLEAR);
-        au_writel(mode,  chan->io + DMA_MODE_SET);
-}
-
-/*
- * Set mode for a specific DMA channel
- */
-static inline void set_dma_mode(unsigned int dmanr, unsigned int mode)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        /*
-         * set_dma_mode is only allowed to change endianess, direction,
-         * transfer size, device FIFO width, and coherency settings.
-         * Make sure anything else is masked off.
-         */
-        mode &= (DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
-        chan->mode &= ~(DMA_BE | DMA_DR | DMA_TS8 | DMA_DW_MASK | DMA_NC);
-        chan->mode |= mode;
-}
-
-static inline unsigned int get_dma_mode(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return 0;
-        return chan->mode;
-}
-
-static inline int get_dma_active_buffer(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return -1;
-        return (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ? 1 : 0;
-}
-
-/*
- * Set the device FIFO address for a specific DMA channel - only
- * applicable to GPO4 and GPO5. All the other devices have fixed
- * FIFO addresses.
- */
-static inline void set_dma_fifo_addr(unsigned int dmanr, unsigned int a)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-
-        if (chan->mode & DMA_DS)        /* second bank of device IDs */
-                return;
-
-        if (chan->dev_id != DMA_ID_GP04 && chan->dev_id != DMA_ID_GP05)
-                return;
-
-        au_writel(CPHYSADDR(a), chan->io + DMA_PERIPHERAL_ADDR);
-}
-
-/*
- * Clear the DMA buffer done bits in the mode register.
- */
-static inline void clear_dma_done0(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(DMA_D0, chan->io + DMA_MODE_CLEAR);
-}
-
-static inline void clear_dma_done1(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(DMA_D1, chan->io + DMA_MODE_CLEAR);
-}
-
-/*
- * This does nothing - not applicable to Au1000 DMA.
- */
-static inline void set_dma_page(unsigned int dmanr, char pagenr)
-{
-}
-
-/*
- * Set Buffer 0 transfer address for specific DMA channel.
- */
-static inline void set_dma_addr0(unsigned int dmanr, unsigned int a)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(a, chan->io + DMA_BUFFER0_START);
-}
-
-/*
- * Set Buffer 1 transfer address for specific DMA channel.
- */
-static inline void set_dma_addr1(unsigned int dmanr, unsigned int a)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        au_writel(a, chan->io + DMA_BUFFER1_START);
-}
-
-
-/*
- * Set Buffer 0 transfer size (max 64k) for a specific DMA channel.
- */
-static inline void set_dma_count0(unsigned int dmanr, unsigned int count)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        count &= DMA_COUNT_MASK;
-        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
-}
-
-/*
- * Set Buffer 1 transfer size (max 64k) for a specific DMA channel.
- */
-static inline void set_dma_count1(unsigned int dmanr, unsigned int count)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        count &= DMA_COUNT_MASK;
-        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
-}
-
-/*
- * Set both buffer transfer sizes (max 64k) for a specific DMA channel.
- */
-static inline void set_dma_count(unsigned int dmanr, unsigned int count)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return;
-        count &= DMA_COUNT_MASK;
-        au_writel(count, chan->io + DMA_BUFFER0_COUNT);
-        au_writel(count, chan->io + DMA_BUFFER1_COUNT);
-}
-
-/*
- * Returns which buffer has its done bit set in the mode register.
- * Returns -1 if neither or both done bits set.
- */
-static inline unsigned int get_dma_buffer_done(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return 0;
-        return au_readl(chan->io + DMA_MODE_READ) & (DMA_D0 | DMA_D1);
-}
-
-
-/*
- * Returns the DMA channel's Buffer Done IRQ number.
- */
-static inline int get_dma_done_irq(unsigned int dmanr)
-{
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return -1;
-        return chan->irq;
-}
-
-/*
- * Get DMA residue count. Returns the number of _bytes_ left to transfer.
- */
-static inline int get_dma_residue(unsigned int dmanr)
-{
-        int curBufCntReg, count;
-        struct dma_chan *chan = get_dma_chan(dmanr);
-
-        if (!chan)
-                return 0;
-
-        curBufCntReg = (au_readl(chan->io + DMA_MODE_READ) & DMA_AB) ?
-            DMA_BUFFER1_COUNT : DMA_BUFFER0_COUNT;
-
-        count = au_readl(chan->io + curBufCntReg) & DMA_COUNT_MASK;
-
-        if ((chan->mode & DMA_DW_MASK) == DMA_DW16)
-                count <<= 1;
-        else if ((chan->mode & DMA_DW_MASK) == DMA_DW32)
-                count <<= 2;
-
-        return count;
-}
-
-#endif /* __ASM_AU1000_DMA_H */
diff --git a/include/asm-mips/mach-au1x00/au1000_gpio.h b/include/asm-mips/mach-au1x00/au1000_gpio.h
deleted file mode 100644
index d8c96fda5549..000000000000
--- a/include/asm-mips/mach-au1x00/au1000_gpio.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * FILE NAME au1000_gpio.h
- *
- * BRIEF MODULE DESCRIPTION
- *      API to Alchemy Au1xx0 GPIO device.
- *
- *  Author: MontaVista Software, Inc.  <source@mvista.com>
- *          Steve Longerbeam
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __AU1000_GPIO_H
-#define __AU1000_GPIO_H
-
-#include <linux/ioctl.h>
-
-#define AU1000GPIO_IOC_MAGIC 'A'
-
-#define AU1000GPIO_IN           _IOR(AU1000GPIO_IOC_MAGIC, 0, int)
-#define AU1000GPIO_SET          _IOW(AU1000GPIO_IOC_MAGIC, 1, int)
-#define AU1000GPIO_CLEAR        _IOW(AU1000GPIO_IOC_MAGIC, 2, int)
-#define AU1000GPIO_OUT          _IOW(AU1000GPIO_IOC_MAGIC, 3, int)
-#define AU1000GPIO_TRISTATE     _IOW(AU1000GPIO_IOC_MAGIC, 4, int)
-#define AU1000GPIO_AVAIL_MASK   _IOR(AU1000GPIO_IOC_MAGIC, 5, int)
-
-#ifdef __KERNEL__
-extern u32 get_au1000_avail_gpio_mask(void);
-extern int au1000gpio_tristate(u32 data);
-extern int au1000gpio_in(u32 *data);
-extern int au1000gpio_set(u32 data);
-extern int au1000gpio_clear(u32 data);
-extern int au1000gpio_out(u32 data);
-#endif
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/au1100_mmc.h b/include/asm-mips/mach-au1x00/au1100_mmc.h
deleted file mode 100644
index c35e20918490..000000000000
--- a/include/asm-mips/mach-au1x00/au1100_mmc.h
+++ /dev/null
@@ -1,208 +0,0 @@
-/*
- * BRIEF MODULE DESCRIPTION
- *      Defines for using the MMC/SD controllers on the
- *      Alchemy Au1100 mips processor.
- *
- * Copyright (c) 2003 Embedded Edge, LLC.
- * Author: Embedded Edge, LLC.
- *              dan@embeddededge.com or tim@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-/*
- * AU1100 MMC/SD definitions.
- *
- * From "AMD Alchemy Solutions Au1100 Processor Data Book - Preliminary"
- *    June, 2003
- */
-
-#ifndef __ASM_AU1100_MMC_H
-#define __ASM_AU1100_MMC_H
-
-#include <linux/leds.h>
-
-struct au1xmmc_platform_data {
-        int(*cd_setup)(void *mmc_host, int on);
-        int(*card_inserted)(void *mmc_host);
-        int(*card_readonly)(void *mmc_host);
-        void(*set_power)(void *mmc_host, int state);
-        struct led_classdev *led;
-};
-
-#define SD0_BASE        0xB0600000
-#define SD1_BASE        0xB0680000
-
-
-/*
- *  Register offsets.
- */
-#define SD_TXPORT       (0x0000)
-#define SD_RXPORT       (0x0004)
-#define SD_CONFIG       (0x0008)
-#define SD_ENABLE       (0x000C)
-#define SD_CONFIG2      (0x0010)
-#define SD_BLKSIZE      (0x0014)
-#define SD_STATUS       (0x0018)
-#define SD_DEBUG        (0x001C)
-#define SD_CMD          (0x0020)
-#define SD_CMDARG       (0x0024)
-#define SD_RESP3        (0x0028)
-#define SD_RESP2        (0x002C)
-#define SD_RESP1        (0x0030)
-#define SD_RESP0        (0x0034)
-#define SD_TIMEOUT      (0x0038)
-
-
-/*
- *  SD_TXPORT bit definitions.
- */
-#define SD_TXPORT_TXD   (0x000000ff)
-
-
-/*
- *  SD_RXPORT bit definitions.
- */
-#define SD_RXPORT_RXD   (0x000000ff)
-
-
-/*
- *  SD_CONFIG bit definitions.
- */
-#define SD_CONFIG_DIV   (0x000001ff)
-#define SD_CONFIG_DE    (0x00000200)
-#define SD_CONFIG_NE    (0x00000400)
-#define SD_CONFIG_TU    (0x00000800)
-#define SD_CONFIG_TO    (0x00001000)
-#define SD_CONFIG_RU    (0x00002000)
-#define SD_CONFIG_RO    (0x00004000)
-#define SD_CONFIG_I     (0x00008000)
-#define SD_CONFIG_CR    (0x00010000)
-#define SD_CONFIG_RAT   (0x00020000)
-#define SD_CONFIG_DD    (0x00040000)
-#define SD_CONFIG_DT    (0x00080000)
-#define SD_CONFIG_SC    (0x00100000)
-#define SD_CONFIG_RC    (0x00200000)
-#define SD_CONFIG_WC    (0x00400000)
-#define SD_CONFIG_xxx   (0x00800000)
-#define SD_CONFIG_TH    (0x01000000)
-#define SD_CONFIG_TE    (0x02000000)
-#define SD_CONFIG_TA    (0x04000000)
-#define SD_CONFIG_RH    (0x08000000)
-#define SD_CONFIG_RA    (0x10000000)
-#define SD_CONFIG_RF    (0x20000000)
-#define SD_CONFIG_CD    (0x40000000)
-#define SD_CONFIG_SI    (0x80000000)
-
-
-/*
- *  SD_ENABLE bit definitions.
- */
-#define SD_ENABLE_CE    (0x00000001)
-#define SD_ENABLE_R     (0x00000002)
-
-
-/*
- *  SD_CONFIG2 bit definitions.
- */
-#define SD_CONFIG2_EN   (0x00000001)
-#define SD_CONFIG2_FF   (0x00000002)
-#define SD_CONFIG2_xx1  (0x00000004)
-#define SD_CONFIG2_DF   (0x00000008)
-#define SD_CONFIG2_DC   (0x00000010)
-#define SD_CONFIG2_xx2  (0x000000e0)
-#define SD_CONFIG2_WB   (0x00000100)
-#define SD_CONFIG2_RW   (0x00000200)
-
-
-/*
- *  SD_BLKSIZE bit definitions.
- */
-#define SD_BLKSIZE_BS   (0x000007ff)
-#define SD_BLKSIZE_BS_SHIFT      (0)
-#define SD_BLKSIZE_BC   (0x01ff0000)
-#define SD_BLKSIZE_BC_SHIFT     (16)
-
-
-/*
- *  SD_STATUS bit definitions.
- */
-#define SD_STATUS_DCRCW (0x00000007)
-#define SD_STATUS_xx1   (0x00000008)
-#define SD_STATUS_CB    (0x00000010)
-#define SD_STATUS_DB    (0x00000020)
-#define SD_STATUS_CF    (0x00000040)
-#define SD_STATUS_D3    (0x00000080)
-#define SD_STATUS_xx2   (0x00000300)
-#define SD_STATUS_NE    (0x00000400)
-#define SD_STATUS_TU    (0x00000800)
-#define SD_STATUS_TO    (0x00001000)
-#define SD_STATUS_RU    (0x00002000)
-#define SD_STATUS_RO    (0x00004000)
-#define SD_STATUS_I     (0x00008000)
-#define SD_STATUS_CR    (0x00010000)
-#define SD_STATUS_RAT   (0x00020000)
-#define SD_STATUS_DD    (0x00040000)
-#define SD_STATUS_DT    (0x00080000)
-#define SD_STATUS_SC    (0x00100000)
-#define SD_STATUS_RC    (0x00200000)
-#define SD_STATUS_WC    (0x00400000)
-#define SD_STATUS_xx3   (0x00800000)
-#define SD_STATUS_TH    (0x01000000)
-#define SD_STATUS_TE    (0x02000000)
-#define SD_STATUS_TA    (0x04000000)
-#define SD_STATUS_RH    (0x08000000)
-#define SD_STATUS_RA    (0x10000000)
-#define SD_STATUS_RF    (0x20000000)
-#define SD_STATUS_CD    (0x40000000)
-#define SD_STATUS_SI    (0x80000000)
-
-
-/*
- *  SD_CMD bit definitions.
- */
-#define SD_CMD_GO       (0x00000001)
-#define SD_CMD_RY       (0x00000002)
-#define SD_CMD_xx1      (0x0000000c)
-#define SD_CMD_CT_MASK  (0x000000f0)
-#define SD_CMD_CT_0     (0x00000000)
-#define SD_CMD_CT_1     (0x00000010)
-#define SD_CMD_CT_2     (0x00000020)
-#define SD_CMD_CT_3     (0x00000030)
-#define SD_CMD_CT_4     (0x00000040)
-#define SD_CMD_CT_5     (0x00000050)
-#define SD_CMD_CT_6     (0x00000060)
-#define SD_CMD_CT_7     (0x00000070)
-#define SD_CMD_CI       (0x0000ff00)
-#define SD_CMD_CI_SHIFT         (8)
-#define SD_CMD_RT_MASK  (0x00ff0000)
-#define SD_CMD_RT_0     (0x00000000)
-#define SD_CMD_RT_1     (0x00010000)
-#define SD_CMD_RT_2     (0x00020000)
-#define SD_CMD_RT_3     (0x00030000)
-#define SD_CMD_RT_4     (0x00040000)
-#define SD_CMD_RT_5     (0x00050000)
-#define SD_CMD_RT_6     (0x00060000)
-#define SD_CMD_RT_1B    (0x00810000)
-
-
-#endif /* __ASM_AU1100_MMC_H */
-
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
deleted file mode 100644
index 08e1958e9410..000000000000
--- a/include/asm-mips/mach-au1x00/au1550_spi.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * au1550_spi.h - Au1550 PSC SPI controller driver - platform data structure
- */
-
-#ifndef _AU1550_SPI_H_
-#define _AU1550_SPI_H_
-
-struct au1550_spi_info {
-        u32 mainclk_hz;         /* main input clock frequency of PSC */
-        u16 num_chipselect;     /* number of chipselects supported */
-        void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
-        void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
-};
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/au1xxx.h b/include/asm-mips/mach-au1x00/au1xxx.h
deleted file mode 100644
index 1b3655090ed3..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef _AU1XXX_H_
-#define _AU1XXX_H_
-
-#include <asm/mach-au1x00/au1000.h>
-
-#if defined(CONFIG_MIPS_DB1000) || defined(CONFIG_MIPS_DB1100) || \
-    defined(CONFIG_MIPS_DB1500) || defined(CONFIG_MIPS_DB1550)
-#include <asm/mach-db1x00/db1x00.h>
-
-#elif defined(CONFIG_MIPS_PB1550)
-#include <asm/mach-pb1x00/pb1550.h>
-
-#elif defined(CONFIG_MIPS_PB1200)
-#include <asm/mach-pb1x00/pb1200.h>
-
-#elif defined(CONFIG_MIPS_DB1200)
-#include <asm/mach-db1x00/db1200.h>
-
-#endif
-
-#endif /* _AU1XXX_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
deleted file mode 100644
index 44a67bf05dc1..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ /dev/null
@@ -1,386 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Include file for Alchemy Semiconductor's Au1550 Descriptor
- *      Based DMA Controller.
- *
- * Copyright 2004 Embedded Edge, LLC
- *      dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/*
- * Specifics for the Au1xxx Descriptor-Based DMA Controller,
- * first seen in the AU1550 part.
- */
-#ifndef _AU1000_DBDMA_H_
-#define _AU1000_DBDMA_H_
-
-#ifndef _LANGUAGE_ASSEMBLY
-
-/*
- * The DMA base addresses.
- * The channels are every 256 bytes (0x0100) from the channel 0 base.
- * Interrupt status/enable is bits 15:0 for channels 15 to zero.
- */
-#define DDMA_GLOBAL_BASE        0xb4003000
-#define DDMA_CHANNEL_BASE       0xb4002000
-
-typedef volatile struct dbdma_global {
-        u32     ddma_config;
-        u32     ddma_intstat;
-        u32     ddma_throttle;
-        u32     ddma_inten;
-} dbdma_global_t;
-
-/* General Configuration. */
-#define DDMA_CONFIG_AF          (1 << 2)
-#define DDMA_CONFIG_AH          (1 << 1)
-#define DDMA_CONFIG_AL          (1 << 0)
-
-#define DDMA_THROTTLE_EN        (1 << 31)
-
-/* The structure of a DMA Channel. */
-typedef volatile struct au1xxx_dma_channel {
-        u32     ddma_cfg;       /* See below */
-        u32     ddma_desptr;    /* 32-byte aligned pointer to descriptor */
-        u32     ddma_statptr;   /* word aligned pointer to status word */
-        u32     ddma_dbell;     /* A write activates channel operation */
-        u32     ddma_irq;       /* If bit 0 set, interrupt pending */
-        u32     ddma_stat;      /* See below */
-        u32     ddma_bytecnt;   /* Byte count, valid only when chan idle */
-        /* Remainder, up to the 256 byte boundary, is reserved. */
-} au1x_dma_chan_t;
-
-#define DDMA_CFG_SED    (1 << 9)        /* source DMA level/edge detect */
-#define DDMA_CFG_SP     (1 << 8)        /* source DMA polarity */
-#define DDMA_CFG_DED    (1 << 7)        /* destination DMA level/edge detect */
-#define DDMA_CFG_DP     (1 << 6)        /* destination DMA polarity */
-#define DDMA_CFG_SYNC   (1 << 5)        /* Sync static bus controller */
-#define DDMA_CFG_PPR    (1 << 4)        /* PCI posted read/write control */
-#define DDMA_CFG_DFN    (1 << 3)        /* Descriptor fetch non-coherent */
-#define DDMA_CFG_SBE    (1 << 2)        /* Source big endian */
-#define DDMA_CFG_DBE    (1 << 1)        /* Destination big endian */
-#define DDMA_CFG_EN     (1 << 0)        /* Channel enable */
-
-/*
- * Always set when descriptor processing done, regardless of
- * interrupt enable state.  Reflected in global intstat, don't
- * clear this until global intstat is read/used.
- */
-#define DDMA_IRQ_IN     (1 << 0)
-
-#define DDMA_STAT_DB    (1 << 2)        /* Doorbell pushed */
-#define DDMA_STAT_V     (1 << 1)        /* Descriptor valid */
-#define DDMA_STAT_H     (1 << 0)        /* Channel Halted */
-
-/*
- * "Standard" DDMA Descriptor.
- * Must be 32-byte aligned.
- */
-typedef volatile struct au1xxx_ddma_desc {
-        u32     dscr_cmd0;              /* See below */
-        u32     dscr_cmd1;              /* See below */
-        u32     dscr_source0;           /* source phys address */
-        u32     dscr_source1;           /* See below */
-        u32     dscr_dest0;             /* Destination address */
-        u32     dscr_dest1;             /* See below */
-        u32     dscr_stat;              /* completion status */
-        u32     dscr_nxtptr;            /* Next descriptor pointer (mostly) */
-        /*
-         * First 32 bytes are HW specific!!!
-         * Lets have some SW data following -- make sure it's 32 bytes.
-         */
-        u32     sw_status;
-        u32     sw_context;
-        u32     sw_reserved[6];
-} au1x_ddma_desc_t;
-
-#define DSCR_CMD0_V             (1 << 31)       /* Descriptor valid */
-#define DSCR_CMD0_MEM           (1 << 30)       /* mem-mem transfer */
-#define DSCR_CMD0_SID_MASK      (0x1f << 25)    /* Source ID */
-#define DSCR_CMD0_DID_MASK      (0x1f << 20)    /* Destination ID */
-#define DSCR_CMD0_SW_MASK       (0x3 << 18)     /* Source Width */
-#define DSCR_CMD0_DW_MASK       (0x3 << 16)     /* Destination Width */
-#define DSCR_CMD0_ARB           (0x1 << 15)     /* Set for Hi Pri */
-#define DSCR_CMD0_DT_MASK       (0x3 << 13)     /* Descriptor Type */
-#define DSCR_CMD0_SN            (0x1 << 12)     /* Source non-coherent */
-#define DSCR_CMD0_DN            (0x1 << 11)     /* Destination non-coherent */
-#define DSCR_CMD0_SM            (0x1 << 10)     /* Stride mode */
-#define DSCR_CMD0_IE            (0x1 << 8)      /* Interrupt Enable */
-#define DSCR_CMD0_SP            (0x1 << 4)      /* Status pointer select */
-#define DSCR_CMD0_CV            (0x1 << 2)      /* Clear Valid when done */
-#define DSCR_CMD0_ST_MASK       (0x3 << 0)      /* Status instruction */
-
-#define SW_STATUS_INUSE         (1 << 0)
-
-/* Command 0 device IDs. */
-#ifdef CONFIG_SOC_AU1550
-#define DSCR_CMD0_UART0_TX      0
-#define DSCR_CMD0_UART0_RX      1
-#define DSCR_CMD0_UART3_TX      2
-#define DSCR_CMD0_UART3_RX      3
-#define DSCR_CMD0_DMA_REQ0      4
-#define DSCR_CMD0_DMA_REQ1      5
-#define DSCR_CMD0_DMA_REQ2      6
-#define DSCR_CMD0_DMA_REQ3      7
-#define DSCR_CMD0_USBDEV_RX0    8
-#define DSCR_CMD0_USBDEV_TX0    9
-#define DSCR_CMD0_USBDEV_TX1    10
-#define DSCR_CMD0_USBDEV_TX2    11
-#define DSCR_CMD0_USBDEV_RX3    12
-#define DSCR_CMD0_USBDEV_RX4    13
-#define DSCR_CMD0_PSC0_TX       14
-#define DSCR_CMD0_PSC0_RX       15
-#define DSCR_CMD0_PSC1_TX       16
-#define DSCR_CMD0_PSC1_RX       17
-#define DSCR_CMD0_PSC2_TX       18
-#define DSCR_CMD0_PSC2_RX       19
-#define DSCR_CMD0_PSC3_TX       20
-#define DSCR_CMD0_PSC3_RX       21
-#define DSCR_CMD0_PCI_WRITE     22
-#define DSCR_CMD0_NAND_FLASH    23
-#define DSCR_CMD0_MAC0_RX       24
-#define DSCR_CMD0_MAC0_TX       25
-#define DSCR_CMD0_MAC1_RX       26
-#define DSCR_CMD0_MAC1_TX       27
-#endif /* CONFIG_SOC_AU1550 */
-
-#ifdef CONFIG_SOC_AU1200
-#define DSCR_CMD0_UART0_TX      0
-#define DSCR_CMD0_UART0_RX      1
-#define DSCR_CMD0_UART1_TX      2
-#define DSCR_CMD0_UART1_RX      3
-#define DSCR_CMD0_DMA_REQ0      4
-#define DSCR_CMD0_DMA_REQ1      5
-#define DSCR_CMD0_MAE_BE        6
-#define DSCR_CMD0_MAE_FE        7
-#define DSCR_CMD0_SDMS_TX0      8
-#define DSCR_CMD0_SDMS_RX0      9
-#define DSCR_CMD0_SDMS_TX1      10
-#define DSCR_CMD0_SDMS_RX1      11
-#define DSCR_CMD0_AES_TX        13
-#define DSCR_CMD0_AES_RX        12
-#define DSCR_CMD0_PSC0_TX       14
-#define DSCR_CMD0_PSC0_RX       15
-#define DSCR_CMD0_PSC1_TX       16
-#define DSCR_CMD0_PSC1_RX       17
-#define DSCR_CMD0_CIM_RXA       18
-#define DSCR_CMD0_CIM_RXB       19
-#define DSCR_CMD0_CIM_RXC       20
-#define DSCR_CMD0_MAE_BOTH      21
-#define DSCR_CMD0_LCD           22
-#define DSCR_CMD0_NAND_FLASH    23
-#define DSCR_CMD0_PSC0_SYNC     24
-#define DSCR_CMD0_PSC1_SYNC     25
-#define DSCR_CMD0_CIM_SYNC      26
-#endif /* CONFIG_SOC_AU1200 */
-
-#define DSCR_CMD0_THROTTLE      30
-#define DSCR_CMD0_ALWAYS        31
-#define DSCR_NDEV_IDS           32
-/* This macro is used to find/create custom device types */
-#define DSCR_DEV2CUSTOM_ID(x, d) (((((x) & 0xFFFF) << 8) | 0x32000000) | \
-                                  ((d) & 0xFF))
-#define DSCR_CUSTOM2DEV_ID(x)   ((x) & 0xFF)
-
-#define DSCR_CMD0_SID(x)        (((x) & 0x1f) << 25)
-#define DSCR_CMD0_DID(x)        (((x) & 0x1f) << 20)
-
-/* Source/Destination transfer width. */
-#define DSCR_CMD0_BYTE          0
-#define DSCR_CMD0_HALFWORD      1
-#define DSCR_CMD0_WORD          2
-
-#define DSCR_CMD0_SW(x)         (((x) & 0x3) << 18)
-#define DSCR_CMD0_DW(x)         (((x) & 0x3) << 16)
-
-/* DDMA Descriptor Type. */
-#define DSCR_CMD0_STANDARD      0
-#define DSCR_CMD0_LITERAL       1
-#define DSCR_CMD0_CMP_BRANCH    2
-
-#define DSCR_CMD0_DT(x)         (((x) & 0x3) << 13)
-
-/* Status Instruction. */
-#define DSCR_CMD0_ST_NOCHANGE   0       /* Don't change */
-#define DSCR_CMD0_ST_CURRENT    1       /* Write current status */
-#define DSCR_CMD0_ST_CMD0       2       /* Write cmd0 with V cleared */
-#define DSCR_CMD0_ST_BYTECNT    3       /* Write remaining byte count */
-
-#define DSCR_CMD0_ST(x)         (((x) & 0x3) << 0)
-
-/* Descriptor Command 1. */
-#define DSCR_CMD1_SUPTR_MASK    (0xf << 28)     /* upper 4 bits of src addr */
-#define DSCR_CMD1_DUPTR_MASK    (0xf << 24)     /* upper 4 bits of dest addr */
-#define DSCR_CMD1_FL_MASK       (0x3 << 22)     /* Flag bits */
-#define DSCR_CMD1_BC_MASK       (0x3fffff)      /* Byte count */
-
-/* Flag description. */
-#define DSCR_CMD1_FL_MEM_STRIDE0        0
-#define DSCR_CMD1_FL_MEM_STRIDE1        1
-#define DSCR_CMD1_FL_MEM_STRIDE2        2
-
-#define DSCR_CMD1_FL(x)         (((x) & 0x3) << 22)
-
-/* Source1, 1-dimensional stride. */
-#define DSCR_SRC1_STS_MASK      (3 << 30)       /* Src xfer size */
-#define DSCR_SRC1_SAM_MASK      (3 << 28)       /* Src xfer movement */
-#define DSCR_SRC1_SB_MASK       (0x3fff << 14)  /* Block size */
-#define DSCR_SRC1_SB(x)         (((x) & 0x3fff) << 14)
-#define DSCR_SRC1_SS_MASK       (0x3fff << 0)   /* Stride */
-#define DSCR_SRC1_SS(x)         (((x) & 0x3fff) << 0)
-
-/* Dest1, 1-dimensional stride. */
-#define DSCR_DEST1_DTS_MASK     (3 << 30)       /* Dest xfer size */
-#define DSCR_DEST1_DAM_MASK     (3 << 28)       /* Dest xfer movement */
-#define DSCR_DEST1_DB_MASK      (0x3fff << 14)  /* Block size */
-#define DSCR_DEST1_DB(x)        (((x) & 0x3fff) << 14)
-#define DSCR_DEST1_DS_MASK      (0x3fff << 0)   /* Stride */
-#define DSCR_DEST1_DS(x)        (((x) & 0x3fff) << 0)
-
-#define DSCR_xTS_SIZE1          0
-#define DSCR_xTS_SIZE2          1
-#define DSCR_xTS_SIZE4          2
-#define DSCR_xTS_SIZE8          3
-#define DSCR_SRC1_STS(x)        (((x) & 3) << 30)
-#define DSCR_DEST1_DTS(x)       (((x) & 3) << 30)
-
-#define DSCR_xAM_INCREMENT      0
-#define DSCR_xAM_DECREMENT      1
-#define DSCR_xAM_STATIC         2
-#define DSCR_xAM_BURST          3
-#define DSCR_SRC1_SAM(x)        (((x) & 3) << 28)
-#define DSCR_DEST1_DAM(x)       (((x) & 3) << 28)
-
-/* The next descriptor pointer. */
-#define DSCR_NXTPTR_MASK        (0x07ffffff)
-#define DSCR_NXTPTR(x)          ((x) >> 5)
-#define DSCR_GET_NXTPTR(x)      ((x) << 5)
-#define DSCR_NXTPTR_MS          (1 << 27)
-
-/* The number of DBDMA channels. */
-#define NUM_DBDMA_CHANS 16
-
-/*
- * DDMA API definitions
- * FIXME: may not fit to this header file
- */
-typedef struct dbdma_device_table {
-        u32     dev_id;
-        u32     dev_flags;
-        u32     dev_tsize;
-        u32     dev_devwidth;
-        u32     dev_physaddr;           /* If FIFO */
-        u32     dev_intlevel;
-        u32     dev_intpolarity;
-} dbdev_tab_t;
-
-
-typedef struct dbdma_chan_config {
-        spinlock_t      lock;
-
-        u32                     chan_flags;
-        u32                     chan_index;
-        dbdev_tab_t             *chan_src;
-        dbdev_tab_t             *chan_dest;
-        au1x_dma_chan_t         *chan_ptr;
-        au1x_ddma_desc_t        *chan_desc_base;
-        au1x_ddma_desc_t        *get_ptr, *put_ptr, *cur_ptr;
-        void                    *chan_callparam;
-        void                    (*chan_callback)(int, void *);
-} chan_tab_t;
-
-#define DEV_FLAGS_INUSE         (1 << 0)
-#define DEV_FLAGS_ANYUSE        (1 << 1)
-#define DEV_FLAGS_OUT           (1 << 2)
-#define DEV_FLAGS_IN            (1 << 3)
-#define DEV_FLAGS_BURSTABLE     (1 << 4)
-#define DEV_FLAGS_SYNC          (1 << 5)
-/* end DDMA API definitions */
-
-/*
- * External functions for drivers to use.
- * Use this to allocate a DBDMA channel.  The device IDs are one of
- * the DSCR_CMD0 devices IDs, which is usually redefined to a more
- * meaningful name.  The 'callback' is called during DMA completion
- * interrupt.
- */
-extern u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
-                                   void (*callback)(int, void *),
-                                   void *callparam);
-
-#define DBDMA_MEM_CHAN  DSCR_CMD0_ALWAYS
-
-/* Set the device width of an in/out FIFO. */
-u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
-
-/* Allocate a ring of descriptors for DBDMA. */
-u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
-
-/* Put buffers on source/destination descriptors. */
-u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
-u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
-
-/* Get a buffer from the destination descriptor. */
-u32 au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes);
-
-void au1xxx_dbdma_stop(u32 chanid);
-void au1xxx_dbdma_start(u32 chanid);
-void au1xxx_dbdma_reset(u32 chanid);
-u32 au1xxx_get_dma_residue(u32 chanid);
-
-void au1xxx_dbdma_chan_free(u32 chanid);
-void au1xxx_dbdma_dump(u32 chanid);
-
-u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr);
-
-u32 au1xxx_ddma_add_device(dbdev_tab_t *dev);
-extern void au1xxx_ddma_del_device(u32 devid);
-void *au1xxx_ddma_get_nextptr_virt(au1x_ddma_desc_t *dp);
-
-/*
- * Some compatibilty macros -- needed to make changes to API
- * without breaking existing drivers.
- */
-#define au1xxx_dbdma_put_source(chanid, buf, nbytes)                    \
-        _au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)       \
-        _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
-#define put_source_flags(chanid, buf, nbytes, flags)                    \
-        au1xxx_dbdma_put_source_flags(chanid, buf, nbytes, flags)
-
-#define au1xxx_dbdma_put_dest(chanid, buf, nbytes)                      \
-        _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
-#define au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)         \
-        _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
-#define put_dest_flags(chanid, buf, nbytes, flags)                      \
-        au1xxx_dbdma_put_dest_flags(chanid, buf, nbytes, flags)
-
-/*
- *      Flags for the put_source/put_dest functions.
- */
-#define DDMA_FLAGS_IE   (1 << 0)
-#define DDMA_FLAGS_NOIE (1 << 1)
-
-#endif /* _LANGUAGE_ASSEMBLY */
-#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-au1x00/au1xxx_ide.h b/include/asm-mips/mach-au1x00/au1xxx_ide.h
deleted file mode 100644
index 60638b8969ba..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_ide.h
+++ /dev/null
@@ -1,194 +0,0 @@
-/*
- * include/asm-mips/mach-au1x00/au1xxx_ide.h  version 01.30.00   Aug. 02 2005
- *
- * BRIEF MODULE DESCRIPTION
- * AMD Alchemy Au1xxx IDE interface routines over the Static Bus
- *
- * Copyright (c) 2003-2005 AMD, Personal Connectivity Solutions
- *
- * This program is free software; you can redistribute it and/or modify it under
- * the terms of the GNU General Public License as published by the Free Software
- * Foundation; either version 2 of the License, or (at your option) any later
- * version.
- *
- * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES,
- * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND
- * FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR
- * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
- * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
- * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
- * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
- * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- * You should have received a copy of the GNU General Public License along with
- * this program; if not, write to the Free Software Foundation, Inc.,
- * 675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Note: for more information, please refer "AMD Alchemy Au1200/Au1550 IDE
- *       Interface and Linux Device Driver" Application Note.
- */
-
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-#define DMA_WAIT_TIMEOUT        100
-#define NUM_DESCRIPTORS         PRD_ENTRIES
-#else /* CONFIG_BLK_DEV_IDE_AU1XXX_PIO_DBDMA */
-#define NUM_DESCRIPTORS         2
-#endif
-
-#ifndef AU1XXX_ATA_RQSIZE
-#define AU1XXX_ATA_RQSIZE       128
-#endif
-
-/* Disable Burstable-Support for DBDMA */
-#ifndef CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON
-#define CONFIG_BLK_DEV_IDE_AU1XXX_BURSTABLE_ON  0
-#endif
-
-#ifdef CONFIG_PM
-/*
- * This will enable the device to be powered up when write() or read()
- * is called. If this is not defined, the driver will return -EBUSY.
- */
-#define WAKE_ON_ACCESS 1
-
-typedef struct {
-        spinlock_t              lock;   /* Used to block on state transitions */
-        au1xxx_power_dev_t      *dev;   /* Power Managers device structure */
-        unsigned                stopped; /* Used to signal device is stopped */
-} pm_state;
-#endif
-
-typedef struct {
-        u32                     tx_dev_id, rx_dev_id, target_dev_id;
-        u32                     tx_chan, rx_chan;
-        void                    *tx_desc_head, *rx_desc_head;
-        ide_hwif_t              *hwif;
-#ifdef CONFIG_BLK_DEV_IDE_AU1XXX_MDMA2_DBDMA
-        ide_drive_t             *drive;
-        struct dbdma_cmd        *dma_table_cpu;
-        dma_addr_t              dma_table_dma;
-#endif
-        int                     irq;
-        u32                     regbase;
-#ifdef CONFIG_PM
-        pm_state                pm;
-#endif
-} _auide_hwif;
-
-/******************************************************************************/
-/* PIO Mode timing calculation :                                              */
-/*                                                                            */
-/* Static Bus Spec   ATA Spec                                                 */
-/*      Tcsoe      =    t1                                                    */
-/*      Toecs      =    t9                                                    */
-/*      Twcs       =    t9                                                    */
-/*      Tcsh       =    t2i | t2                                              */
-/*      Tcsoff     =    t2i | t2                                              */
-/*      Twp        =    t2                                                    */
-/*      Tcsw       =    t1                                                    */
-/*      Tpm        =    0                                                     */
-/*      Ta         =    t1+t2                                                 */
-/******************************************************************************/
-
-#define TCSOE_MASK              (0x07 << 29)
-#define TOECS_MASK              (0x07 << 26)
-#define TWCS_MASK               (0x07 << 28)
-#define TCSH_MASK               (0x0F << 24)
-#define TCSOFF_MASK             (0x07 << 20)
-#define TWP_MASK                (0x3F << 14)
-#define TCSW_MASK               (0x0F << 10)
-#define TPM_MASK                (0x0F << 6)
-#define TA_MASK                 (0x3F << 0)
-#define TS_MASK                 (1 << 8)
-
-/* Timing parameters PIO mode 0 */
-#define SBC_IDE_PIO0_TCSOE      (0x04 << 29)
-#define SBC_IDE_PIO0_TOECS      (0x01 << 26)
-#define SBC_IDE_PIO0_TWCS       (0x02 << 28)
-#define SBC_IDE_PIO0_TCSH       (0x08 << 24)
-#define SBC_IDE_PIO0_TCSOFF     (0x07 << 20)
-#define SBC_IDE_PIO0_TWP        (0x10 << 14)
-#define SBC_IDE_PIO0_TCSW       (0x04 << 10)
-#define SBC_IDE_PIO0_TPM        (0x00 << 6)
-#define SBC_IDE_PIO0_TA         (0x15 << 0)
-/* Timing parameters PIO mode 1 */
-#define SBC_IDE_PIO1_TCSOE      (0x03 << 29)
-#define SBC_IDE_PIO1_TOECS      (0x01 << 26)
-#define SBC_IDE_PIO1_TWCS       (0x01 << 28)
-#define SBC_IDE_PIO1_TCSH       (0x06 << 24)
-#define SBC_IDE_PIO1_TCSOFF     (0x06 << 20)
-#define SBC_IDE_PIO1_TWP        (0x08 << 14)
-#define SBC_IDE_PIO1_TCSW       (0x03 << 10)
-#define SBC_IDE_PIO1_TPM        (0x00 << 6)
-#define SBC_IDE_PIO1_TA         (0x0B << 0)
-/* Timing parameters PIO mode 2 */
-#define SBC_IDE_PIO2_TCSOE      (0x05 << 29)
-#define SBC_IDE_PIO2_TOECS      (0x01 << 26)
-#define SBC_IDE_PIO2_TWCS       (0x01 << 28)
-#define SBC_IDE_PIO2_TCSH       (0x07 << 24)
-#define SBC_IDE_PIO2_TCSOFF     (0x07 << 20)
-#define SBC_IDE_PIO2_TWP        (0x1F << 14)
-#define SBC_IDE_PIO2_TCSW       (0x05 << 10)
-#define SBC_IDE_PIO2_TPM        (0x00 << 6)
-#define SBC_IDE_PIO2_TA         (0x22 << 0)
-/* Timing parameters PIO mode 3 */
-#define SBC_IDE_PIO3_TCSOE      (0x05 << 29)
-#define SBC_IDE_PIO3_TOECS      (0x01 << 26)
-#define SBC_IDE_PIO3_TWCS       (0x01 << 28)
-#define SBC_IDE_PIO3_TCSH       (0x0D << 24)
-#define SBC_IDE_PIO3_TCSOFF     (0x0D << 20)
-#define SBC_IDE_PIO3_TWP        (0x15 << 14)
-#define SBC_IDE_PIO3_TCSW       (0x05 << 10)
-#define SBC_IDE_PIO3_TPM        (0x00 << 6)
-#define SBC_IDE_PIO3_TA         (0x1A << 0)
-/* Timing parameters PIO mode 4 */
-#define SBC_IDE_PIO4_TCSOE      (0x04 << 29)
-#define SBC_IDE_PIO4_TOECS      (0x01 << 26)
-#define SBC_IDE_PIO4_TWCS       (0x01 << 28)
-#define SBC_IDE_PIO4_TCSH       (0x04 << 24)
-#define SBC_IDE_PIO4_TCSOFF     (0x04 << 20)
-#define SBC_IDE_PIO4_TWP        (0x0D << 14)
-#define SBC_IDE_PIO4_TCSW       (0x03 << 10)
-#define SBC_IDE_PIO4_TPM        (0x00 << 6)
-#define SBC_IDE_PIO4_TA         (0x12 << 0)
-/* Timing parameters MDMA mode 0 */
-#define SBC_IDE_MDMA0_TCSOE     (0x03 << 29)
-#define SBC_IDE_MDMA0_TOECS     (0x01 << 26)
-#define SBC_IDE_MDMA0_TWCS      (0x01 << 28)
-#define SBC_IDE_MDMA0_TCSH      (0x07 << 24)
-#define SBC_IDE_MDMA0_TCSOFF    (0x07 << 20)
-#define SBC_IDE_MDMA0_TWP       (0x0C << 14)
-#define SBC_IDE_MDMA0_TCSW      (0x03 << 10)
-#define SBC_IDE_MDMA0_TPM       (0x00 << 6)
-#define SBC_IDE_MDMA0_TA        (0x0F << 0)
-/* Timing parameters MDMA mode 1 */
-#define SBC_IDE_MDMA1_TCSOE     (0x05 << 29)
-#define SBC_IDE_MDMA1_TOECS     (0x01 << 26)
-#define SBC_IDE_MDMA1_TWCS      (0x01 << 28)
-#define SBC_IDE_MDMA1_TCSH      (0x05 << 24)
-#define SBC_IDE_MDMA1_TCSOFF    (0x05 << 20)
-#define SBC_IDE_MDMA1_TWP       (0x0F << 14)
-#define SBC_IDE_MDMA1_TCSW      (0x05 << 10)
-#define SBC_IDE_MDMA1_TPM       (0x00 << 6)
-#define SBC_IDE_MDMA1_TA        (0x15 << 0)
-/* Timing parameters MDMA mode 2 */
-#define SBC_IDE_MDMA2_TCSOE     (0x04 << 29)
-#define SBC_IDE_MDMA2_TOECS     (0x01 << 26)
-#define SBC_IDE_MDMA2_TWCS      (0x01 << 28)
-#define SBC_IDE_MDMA2_TCSH      (0x04 << 24)
-#define SBC_IDE_MDMA2_TCSOFF    (0x04 << 20)
-#define SBC_IDE_MDMA2_TWP       (0x0D << 14)
-#define SBC_IDE_MDMA2_TCSW      (0x04 << 10)
-#define SBC_IDE_MDMA2_TPM       (0x00 << 6)
-#define SBC_IDE_MDMA2_TA        (0x12 << 0)
-
-#define SBC_IDE_TIMING(mode) \
-        (SBC_IDE_##mode##_TWCS | \
-         SBC_IDE_##mode##_TCSH | \
-         SBC_IDE_##mode##_TCSOFF | \
-         SBC_IDE_##mode##_TWP | \
-         SBC_IDE_##mode##_TCSW | \
-         SBC_IDE_##mode##_TPM | \
-         SBC_IDE_##mode##_TA)
diff --git a/include/asm-mips/mach-au1x00/au1xxx_psc.h b/include/asm-mips/mach-au1x00/au1xxx_psc.h
deleted file mode 100644
index 892b7f168eb4..000000000000
--- a/include/asm-mips/mach-au1x00/au1xxx_psc.h
+++ /dev/null
@@ -1,505 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *      Include file for Alchemy Semiconductor's Au1k CPU.
- *
- * Copyright 2004 Embedded Edge, LLC
- *      dan@embeddededge.com
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-/* Specifics for the Au1xxx Programmable Serial Controllers, first
- * seen in the AU1550 part.
- */
-#ifndef _AU1000_PSC_H_
-#define _AU1000_PSC_H_
-
-/* The PSC base addresses.  */
-#ifdef CONFIG_SOC_AU1550
-#define PSC0_BASE_ADDR          0xb1a00000
-#define PSC1_BASE_ADDR          0xb1b00000
-#define PSC2_BASE_ADDR          0xb0a00000
-#define PSC3_BASE_ADDR          0xb0b00000
-#endif
-
-#ifdef CONFIG_SOC_AU1200
-#define PSC0_BASE_ADDR          0xb1a00000
-#define PSC1_BASE_ADDR          0xb1b00000
-#endif
-
-/*
- * The PSC select and control registers are common to all protocols.
- */
-#define PSC_SEL_OFFSET          0x00000000
-#define PSC_CTRL_OFFSET         0x00000004
-
-#define PSC_SEL_CLK_MASK        (3 << 4)
-#define PSC_SEL_CLK_INTCLK      (0 << 4)
-#define PSC_SEL_CLK_EXTCLK      (1 << 4)
-#define PSC_SEL_CLK_SERCLK      (2 << 4)
-
-#define PSC_SEL_PS_MASK         0x00000007
-#define PSC_SEL_PS_DISABLED     0
-#define PSC_SEL_PS_SPIMODE      2
-#define PSC_SEL_PS_I2SMODE      3
-#define PSC_SEL_PS_AC97MODE     4
-#define PSC_SEL_PS_SMBUSMODE    5
-
-#define PSC_CTRL_DISABLE        0
-#define PSC_CTRL_SUSPEND        2
-#define PSC_CTRL_ENABLE         3
-
-/* AC97 Registers. */
-#define PSC_AC97CFG_OFFSET      0x00000008
-#define PSC_AC97MSK_OFFSET      0x0000000c
-#define PSC_AC97PCR_OFFSET      0x00000010
-#define PSC_AC97STAT_OFFSET     0x00000014
-#define PSC_AC97EVNT_OFFSET     0x00000018
-#define PSC_AC97TXRX_OFFSET     0x0000001c
-#define PSC_AC97CDC_OFFSET      0x00000020
-#define PSC_AC97RST_OFFSET      0x00000024
-#define PSC_AC97GPO_OFFSET      0x00000028
-#define PSC_AC97GPI_OFFSET      0x0000002c
-
-#define AC97_PSC_SEL            (AC97_PSC_BASE + PSC_SEL_OFFSET)
-#define AC97_PSC_CTRL           (AC97_PSC_BASE + PSC_CTRL_OFFSET)
-#define PSC_AC97CFG             (AC97_PSC_BASE + PSC_AC97CFG_OFFSET)
-#define PSC_AC97MSK             (AC97_PSC_BASE + PSC_AC97MSK_OFFSET)
-#define PSC_AC97PCR             (AC97_PSC_BASE + PSC_AC97PCR_OFFSET)
-#define PSC_AC97STAT            (AC97_PSC_BASE + PSC_AC97STAT_OFFSET)
-#define PSC_AC97EVNT            (AC97_PSC_BASE + PSC_AC97EVNT_OFFSET)
-#define PSC_AC97TXRX            (AC97_PSC_BASE + PSC_AC97TXRX_OFFSET)
-#define PSC_AC97CDC             (AC97_PSC_BASE + PSC_AC97CDC_OFFSET)
-#define PSC_AC97RST             (AC97_PSC_BASE + PSC_AC97RST_OFFSET)
-#define PSC_AC97GPO             (AC97_PSC_BASE + PSC_AC97GPO_OFFSET)
-#define PSC_AC97GPI             (AC97_PSC_BASE + PSC_AC97GPI_OFFSET)
-
-/* AC97 Config Register. */
-#define PSC_AC97CFG_RT_MASK     (3 << 30)
-#define PSC_AC97CFG_RT_FIFO1    (0 << 30)
-#define PSC_AC97CFG_RT_FIFO2    (1 << 30)
-#define PSC_AC97CFG_RT_FIFO4    (2 << 30)
-#define PSC_AC97CFG_RT_FIFO8    (3 << 30)
-
-#define PSC_AC97CFG_TT_MASK     (3 << 28)
-#define PSC_AC97CFG_TT_FIFO1    (0 << 28)
-#define PSC_AC97CFG_TT_FIFO2    (1 << 28)
-#define PSC_AC97CFG_TT_FIFO4    (2 << 28)
-#define PSC_AC97CFG_TT_FIFO8    (3 << 28)
-
-#define PSC_AC97CFG_DD_DISABLE  (1 << 27)
-#define PSC_AC97CFG_DE_ENABLE   (1 << 26)
-#define PSC_AC97CFG_SE_ENABLE   (1 << 25)
-
-#define PSC_AC97CFG_LEN_MASK    (0xf << 21)
-#define PSC_AC97CFG_TXSLOT_MASK (0x3ff << 11)
-#define PSC_AC97CFG_RXSLOT_MASK (0x3ff << 1)
-#define PSC_AC97CFG_GE_ENABLE   (1)
-
-/* Enable slots 3-12. */
-#define PSC_AC97CFG_TXSLOT_ENA(x)       (1 << (((x) - 3) + 11))
-#define PSC_AC97CFG_RXSLOT_ENA(x)       (1 << (((x) - 3) + 1))
-
-/*
- * The word length equation is ((x) * 2) + 2, so choose 'x' appropriately.
- * The only sensible numbers are 7, 9, or possibly 11.  Nah, just do the
- * arithmetic in the macro.
- */
-#define PSC_AC97CFG_SET_LEN(x)  (((((x) - 2) / 2) & 0xf) << 21)
-#define PSC_AC97CFG_GET_LEN(x)  (((((x) >> 21) & 0xf) * 2) + 2)
-
-/* AC97 Mask Register. */
-#define PSC_AC97MSK_GR          (1 << 25)
-#define PSC_AC97MSK_CD          (1 << 24)
-#define PSC_AC97MSK_RR          (1 << 13)
-#define PSC_AC97MSK_RO          (1 << 12)
-#define PSC_AC97MSK_RU          (1 << 11)
-#define PSC_AC97MSK_TR          (1 << 10)
-#define PSC_AC97MSK_TO          (1 << 9)
-#define PSC_AC97MSK_TU          (1 << 8)
-#define PSC_AC97MSK_RD          (1 << 5)
-#define PSC_AC97MSK_TD          (1 << 4)
-#define PSC_AC97MSK_ALLMASK     (PSC_AC97MSK_GR | PSC_AC97MSK_CD | \
-                                 PSC_AC97MSK_RR | PSC_AC97MSK_RO | \
-                                 PSC_AC97MSK_RU | PSC_AC97MSK_TR | \
-                                 PSC_AC97MSK_TO | PSC_AC97MSK_TU | \
-                                 PSC_AC97MSK_RD | PSC_AC97MSK_TD)
-
-/* AC97 Protocol Control Register. */
-#define PSC_AC97PCR_RC          (1 << 6)
-#define PSC_AC97PCR_RP          (1 << 5)
-#define PSC_AC97PCR_RS          (1 << 4)
-#define PSC_AC97PCR_TC          (1 << 2)
-#define PSC_AC97PCR_TP          (1 << 1)
-#define PSC_AC97PCR_TS          (1 << 0)
-
-/* AC97 Status register (read only). */
-#define PSC_AC97STAT_CB         (1 << 26)
-#define PSC_AC97STAT_CP         (1 << 25)
-#define PSC_AC97STAT_CR         (1 << 24)
-#define PSC_AC97STAT_RF         (1 << 13)
-#define PSC_AC97STAT_RE         (1 << 12)
-#define PSC_AC97STAT_RR         (1 << 11)
-#define PSC_AC97STAT_TF         (1 << 10)
-#define PSC_AC97STAT_TE         (1 << 9)
-#define PSC_AC97STAT_TR         (1 << 8)
-#define PSC_AC97STAT_RB         (1 << 5)
-#define PSC_AC97STAT_TB         (1 << 4)
-#define PSC_AC97STAT_DI         (1 << 2)
-#define PSC_AC97STAT_DR         (1 << 1)
-#define PSC_AC97STAT_SR         (1 << 0)
-
-/* AC97 Event Register. */
-#define PSC_AC97EVNT_GR         (1 << 25)
-#define PSC_AC97EVNT_CD         (1 << 24)
-#define PSC_AC97EVNT_RR         (1 << 13)
-#define PSC_AC97EVNT_RO         (1 << 12)
-#define PSC_AC97EVNT_RU         (1 << 11)
-#define PSC_AC97EVNT_TR         (1 << 10)
-#define PSC_AC97EVNT_TO         (1 << 9)
-#define PSC_AC97EVNT_TU         (1 << 8)
-#define PSC_AC97EVNT_RD         (1 << 5)
-#define PSC_AC97EVNT_TD         (1 << 4)
-
-/* CODEC Command Register. */
-#define PSC_AC97CDC_RD          (1 << 25)
-#define PSC_AC97CDC_ID_MASK     (3 << 23)
-#define PSC_AC97CDC_INDX_MASK   (0x7f << 16)
-#define PSC_AC97CDC_ID(x)       (((x) & 0x03) << 23)
-#define PSC_AC97CDC_INDX(x)     (((x) & 0x7f) << 16)
-
-/* AC97 Reset Control Register. */
-#define PSC_AC97RST_RST         (1 << 1)
-#define PSC_AC97RST_SNC         (1 << 0)
-
-/* PSC in I2S Mode. */
-typedef struct  psc_i2s {
-        u32     psc_sel;
-        u32     psc_ctrl;
-        u32     psc_i2scfg;
-        u32     psc_i2smsk;
-        u32     psc_i2spcr;
-        u32     psc_i2sstat;
-        u32     psc_i2sevent;
-        u32     psc_i2stxrx;
-        u32     psc_i2sudf;
-} psc_i2s_t;
-
-#define PSC_I2SCFG_OFFSET       0x08
-#define PSC_I2SMASK_OFFSET      0x0C
-#define PSC_I2SPCR_OFFSET       0x10
-#define PSC_I2SSTAT_OFFSET      0x14
-#define PSC_I2SEVENT_OFFSET     0x18
-#define PSC_I2SRXTX_OFFSET      0x1C
-#define PSC_I2SUDF_OFFSET       0x20
-
-/* I2S Config Register. */
-#define PSC_I2SCFG_RT_MASK      (3 << 30)
-#define PSC_I2SCFG_RT_FIFO1     (0 << 30)
-#define PSC_I2SCFG_RT_FIFO2     (1 << 30)
-#define PSC_I2SCFG_RT_FIFO4     (2 << 30)
-#define PSC_I2SCFG_RT_FIFO8     (3 << 30)
-
-#define PSC_I2SCFG_TT_MASK      (3 << 28)
-#define PSC_I2SCFG_TT_FIFO1     (0 << 28)
-#define PSC_I2SCFG_TT_FIFO2     (1 << 28)
-#define PSC_I2SCFG_TT_FIFO4     (2 << 28)
-#define PSC_I2SCFG_TT_FIFO8     (3 << 28)
-
-#define PSC_I2SCFG_DD_DISABLE   (1 << 27)
-#define PSC_I2SCFG_DE_ENABLE    (1 << 26)
-#define PSC_I2SCFG_SET_WS(x)    (((((x) / 2) - 1) & 0x7f) << 16)
-#define PSC_I2SCFG_WS(n)        ((n & 0xFF) << 16)
-#define PSC_I2SCFG_WS_MASK      (PSC_I2SCFG_WS(0x3F))
-#define PSC_I2SCFG_WI           (1 << 15)
-
-#define PSC_I2SCFG_DIV_MASK     (3 << 13)
-#define PSC_I2SCFG_DIV2         (0 << 13)
-#define PSC_I2SCFG_DIV4         (1 << 13)
-#define PSC_I2SCFG_DIV8         (2 << 13)
-#define PSC_I2SCFG_DIV16        (3 << 13)
-
-#define PSC_I2SCFG_BI           (1 << 12)
-#define PSC_I2SCFG_BUF          (1 << 11)
-#define PSC_I2SCFG_MLJ          (1 << 10)
-#define PSC_I2SCFG_XM           (1 << 9)
-
-/* The word length equation is simply LEN+1. */
-#define PSC_I2SCFG_SET_LEN(x)   ((((x) - 1) & 0x1f) << 4)
-#define PSC_I2SCFG_GET_LEN(x)   ((((x) >> 4) & 0x1f) + 1)
-
-#define PSC_I2SCFG_LB           (1 << 2)
-#define PSC_I2SCFG_MLF          (1 << 1)
-#define PSC_I2SCFG_MS           (1 << 0)
-
-/* I2S Mask Register. */
-#define PSC_I2SMSK_RR           (1 << 13)
-#define PSC_I2SMSK_RO           (1 << 12)
-#define PSC_I2SMSK_RU           (1 << 11)
-#define PSC_I2SMSK_TR           (1 << 10)
-#define PSC_I2SMSK_TO           (1 << 9)
-#define PSC_I2SMSK_TU           (1 << 8)
-#define PSC_I2SMSK_RD           (1 << 5)
-#define PSC_I2SMSK_TD           (1 << 4)
-#define PSC_I2SMSK_ALLMASK      (PSC_I2SMSK_RR | PSC_I2SMSK_RO | \
-                                 PSC_I2SMSK_RU | PSC_I2SMSK_TR | \
-                                 PSC_I2SMSK_TO | PSC_I2SMSK_TU | \
-                                 PSC_I2SMSK_RD | PSC_I2SMSK_TD)
-
-/* I2S Protocol Control Register. */
-#define PSC_I2SPCR_RC           (1 << 6)
-#define PSC_I2SPCR_RP           (1 << 5)
-#define PSC_I2SPCR_RS           (1 << 4)
-#define PSC_I2SPCR_TC           (1 << 2)
-#define PSC_I2SPCR_TP           (1 << 1)
-#define PSC_I2SPCR_TS           (1 << 0)
-
-/* I2S Status register (read only). */
-#define PSC_I2SSTAT_RF          (1 << 13)
-#define PSC_I2SSTAT_RE          (1 << 12)
-#define PSC_I2SSTAT_RR          (1 << 11)
-#define PSC_I2SSTAT_TF          (1 << 10)
-#define PSC_I2SSTAT_TE          (1 << 9)
-#define PSC_I2SSTAT_TR          (1 << 8)
-#define PSC_I2SSTAT_RB          (1 << 5)
-#define PSC_I2SSTAT_TB          (1 << 4)
-#define PSC_I2SSTAT_DI          (1 << 2)
-#define PSC_I2SSTAT_DR          (1 << 1)
-#define PSC_I2SSTAT_SR          (1 << 0)
-
-/* I2S Event Register. */
-#define PSC_I2SEVNT_RR          (1 << 13)
-#define PSC_I2SEVNT_RO          (1 << 12)
-#define PSC_I2SEVNT_RU          (1 << 11)
-#define PSC_I2SEVNT_TR          (1 << 10)
-#define PSC_I2SEVNT_TO          (1 << 9)
-#define PSC_I2SEVNT_TU          (1 << 8)
-#define PSC_I2SEVNT_RD          (1 << 5)
-#define PSC_I2SEVNT_TD          (1 << 4)
-
-/* PSC in SPI Mode. */
-typedef struct  psc_spi {
-        u32     psc_sel;
-        u32     psc_ctrl;
-        u32     psc_spicfg;
-        u32     psc_spimsk;
-        u32     psc_spipcr;
-        u32     psc_spistat;
-        u32     psc_spievent;
-        u32     psc_spitxrx;
-} psc_spi_t;
-
-/* SPI Config Register. */
-#define PSC_SPICFG_RT_MASK      (3 << 30)
-#define PSC_SPICFG_RT_FIFO1     (0 << 30)
-#define PSC_SPICFG_RT_FIFO2     (1 << 30)
-#define PSC_SPICFG_RT_FIFO4     (2 << 30)
-#define PSC_SPICFG_RT_FIFO8     (3 << 30)
-
-#define PSC_SPICFG_TT_MASK      (3 << 28)
-#define PSC_SPICFG_TT_FIFO1     (0 << 28)
-#define PSC_SPICFG_TT_FIFO2     (1 << 28)
-#define PSC_SPICFG_TT_FIFO4     (2 << 28)
-#define PSC_SPICFG_TT_FIFO8     (3 << 28)
-
-#define PSC_SPICFG_DD_DISABLE   (1 << 27)
-#define PSC_SPICFG_DE_ENABLE    (1 << 26)
-#define PSC_SPICFG_CLR_BAUD(x)  ((x) & ~((0x3f) << 15))
-#define PSC_SPICFG_SET_BAUD(x)  (((x) & 0x3f) << 15)
-
-#define PSC_SPICFG_SET_DIV(x)   (((x) & 0x03) << 13)
-#define PSC_SPICFG_DIV2         0
-#define PSC_SPICFG_DIV4         1
-#define PSC_SPICFG_DIV8         2
-#define PSC_SPICFG_DIV16        3
-
-#define PSC_SPICFG_BI           (1 << 12)
-#define PSC_SPICFG_PSE          (1 << 11)
-#define PSC_SPICFG_CGE          (1 << 10)
-#define PSC_SPICFG_CDE          (1 << 9)
-
-#define PSC_SPICFG_CLR_LEN(x)   ((x) & ~((0x1f) << 4))
-#define PSC_SPICFG_SET_LEN(x)   (((x-1) & 0x1f) << 4)
-
-#define PSC_SPICFG_LB           (1 << 3)
-#define PSC_SPICFG_MLF          (1 << 1)
-#define PSC_SPICFG_MO           (1 << 0)
-
-/* SPI Mask Register. */
-#define PSC_SPIMSK_MM           (1 << 16)
-#define PSC_SPIMSK_RR           (1 << 13)
-#define PSC_SPIMSK_RO           (1 << 12)
-#define PSC_SPIMSK_RU           (1 << 11)
-#define PSC_SPIMSK_TR           (1 << 10)
-#define PSC_SPIMSK_TO           (1 << 9)
-#define PSC_SPIMSK_TU           (1 << 8)
-#define PSC_SPIMSK_SD           (1 << 5)
-#define PSC_SPIMSK_MD           (1 << 4)
-#define PSC_SPIMSK_ALLMASK      (PSC_SPIMSK_MM | PSC_SPIMSK_RR | \
-                                 PSC_SPIMSK_RO | PSC_SPIMSK_TO | \
-                                 PSC_SPIMSK_TU | PSC_SPIMSK_SD | \
-                                 PSC_SPIMSK_MD)
-
-/* SPI Protocol Control Register. */
-#define PSC_SPIPCR_RC           (1 << 6)
-#define PSC_SPIPCR_SP           (1 << 5)
-#define PSC_SPIPCR_SS           (1 << 4)
-#define PSC_SPIPCR_TC           (1 << 2)
-#define PSC_SPIPCR_MS           (1 << 0)
-
-/* SPI Status register (read only). */
-#define PSC_SPISTAT_RF          (1 << 13)
-#define PSC_SPISTAT_RE          (1 << 12)
-#define PSC_SPISTAT_RR          (1 << 11)
-#define PSC_SPISTAT_TF          (1 << 10)
-#define PSC_SPISTAT_TE          (1 << 9)
-#define PSC_SPISTAT_TR          (1 << 8)
-#define PSC_SPISTAT_SB          (1 << 5)
-#define PSC_SPISTAT_MB          (1 << 4)
-#define PSC_SPISTAT_DI          (1 << 2)
-#define PSC_SPISTAT_DR          (1 << 1)
-#define PSC_SPISTAT_SR          (1 << 0)
-
-/* SPI Event Register. */
-#define PSC_SPIEVNT_MM          (1 << 16)
-#define PSC_SPIEVNT_RR          (1 << 13)
-#define PSC_SPIEVNT_RO          (1 << 12)
-#define PSC_SPIEVNT_RU          (1 << 11)
-#define PSC_SPIEVNT_TR          (1 << 10)
-#define PSC_SPIEVNT_TO          (1 << 9)
-#define PSC_SPIEVNT_TU          (1 << 8)
-#define PSC_SPIEVNT_SD          (1 << 5)
-#define PSC_SPIEVNT_MD          (1 << 4)
-
-/* Transmit register control. */
-#define PSC_SPITXRX_LC          (1 << 29)
-#define PSC_SPITXRX_SR          (1 << 28)
-
-/* PSC in SMBus (I2C) Mode. */
-typedef struct  psc_smb {
-        u32     psc_sel;
-        u32     psc_ctrl;
-        u32     psc_smbcfg;
-        u32     psc_smbmsk;
-        u32     psc_smbpcr;
-        u32     psc_smbstat;
-        u32     psc_smbevnt;
-        u32     psc_smbtxrx;
-        u32     psc_smbtmr;
-} psc_smb_t;
-
-/* SMBus Config Register. */
-#define PSC_SMBCFG_RT_MASK      (3 << 30)
-#define PSC_SMBCFG_RT_FIFO1     (0 << 30)
-#define PSC_SMBCFG_RT_FIFO2     (1 << 30)
-#define PSC_SMBCFG_RT_FIFO4     (2 << 30)
-#define PSC_SMBCFG_RT_FIFO8     (3 << 30)
-
-#define PSC_SMBCFG_TT_MASK      (3 << 28)
-#define PSC_SMBCFG_TT_FIFO1     (0 << 28)
-#define PSC_SMBCFG_TT_FIFO2     (1 << 28)
-#define PSC_SMBCFG_TT_FIFO4     (2 << 28)
-#define PSC_SMBCFG_TT_FIFO8     (3 << 28)
-
-#define PSC_SMBCFG_DD_DISABLE   (1 << 27)
-#define PSC_SMBCFG_DE_ENABLE    (1 << 26)
-
-#define PSC_SMBCFG_SET_DIV(x)   (((x) & 0x03) << 13)
-#define PSC_SMBCFG_DIV2         0
-#define PSC_SMBCFG_DIV4         1
-#define PSC_SMBCFG_DIV8         2
-#define PSC_SMBCFG_DIV16        3
-
-#define PSC_SMBCFG_GCE          (1 << 9)
-#define PSC_SMBCFG_SFM          (1 << 8)
-
-#define PSC_SMBCFG_SET_SLV(x)   (((x) & 0x7f) << 1)
-
-/* SMBus Mask Register. */
-#define PSC_SMBMSK_DN           (1 << 30)
-#define PSC_SMBMSK_AN           (1 << 29)
-#define PSC_SMBMSK_AL           (1 << 28)
-#define PSC_SMBMSK_RR           (1 << 13)
-#define PSC_SMBMSK_RO           (1 << 12)
-#define PSC_SMBMSK_RU           (1 << 11)
-#define PSC_SMBMSK_TR           (1 << 10)
-#define PSC_SMBMSK_TO           (1 << 9)
-#define PSC_SMBMSK_TU           (1 << 8)
-#define PSC_SMBMSK_SD           (1 << 5)
-#define PSC_SMBMSK_MD           (1 << 4)
-#define PSC_SMBMSK_ALLMASK      (PSC_SMBMSK_DN | PSC_SMBMSK_AN | \
-                                 PSC_SMBMSK_AL | PSC_SMBMSK_RR | \
-                                 PSC_SMBMSK_RO | PSC_SMBMSK_TO | \
-                                 PSC_SMBMSK_TU | PSC_SMBMSK_SD | \
-                                 PSC_SMBMSK_MD)
-
-/* SMBus Protocol Control Register. */
-#define PSC_SMBPCR_DC           (1 << 2)
-#define PSC_SMBPCR_MS           (1 << 0)
-
-/* SMBus Status register (read only). */
-#define PSC_SMBSTAT_BB          (1 << 28)
-#define PSC_SMBSTAT_RF          (1 << 13)
-#define PSC_SMBSTAT_RE          (1 << 12)
-#define PSC_SMBSTAT_RR          (1 << 11)
-#define PSC_SMBSTAT_TF          (1 << 10)
-#define PSC_SMBSTAT_TE          (1 << 9)
-#define PSC_SMBSTAT_TR          (1 << 8)
-#define PSC_SMBSTAT_SB          (1 << 5)
-#define PSC_SMBSTAT_MB          (1 << 4)
-#define PSC_SMBSTAT_DI          (1 << 2)
-#define PSC_SMBSTAT_DR          (1 << 1)
-#define PSC_SMBSTAT_SR          (1 << 0)
-
-/* SMBus Event Register. */
-#define PSC_SMBEVNT_DN          (1 << 30)
-#define PSC_SMBEVNT_AN          (1 << 29)
-#define PSC_SMBEVNT_AL          (1 << 28)
-#define PSC_SMBEVNT_RR          (1 << 13)
-#define PSC_SMBEVNT_RO          (1 << 12)
-#define PSC_SMBEVNT_RU          (1 << 11)
-#define PSC_SMBEVNT_TR          (1 << 10)
-#define PSC_SMBEVNT_TO          (1 << 9)
-#define PSC_SMBEVNT_TU          (1 << 8)
-#define PSC_SMBEVNT_SD          (1 << 5)
-#define PSC_SMBEVNT_MD          (1 << 4)
-#define PSC_SMBEVNT_ALLCLR      (PSC_SMBEVNT_DN | PSC_SMBEVNT_AN | \
-                                 PSC_SMBEVNT_AL | PSC_SMBEVNT_RR | \
-                                 PSC_SMBEVNT_RO | PSC_SMBEVNT_TO | \
-                                 PSC_SMBEVNT_TU | PSC_SMBEVNT_SD | \
-                                 PSC_SMBEVNT_MD)
-
-/* Transmit register control. */
-#define PSC_SMBTXRX_RSR         (1 << 28)
-#define PSC_SMBTXRX_STP         (1 << 29)
-#define PSC_SMBTXRX_DATAMASK    0xff
-
-/* SMBus protocol timers register. */
-#define PSC_SMBTMR_SET_TH(x)    (((x) & 0x03) << 30)
-#define PSC_SMBTMR_SET_PS(x)    (((x) & 0x1f) << 25)
-#define PSC_SMBTMR_SET_PU(x)    (((x) & 0x1f) << 20)
-#define PSC_SMBTMR_SET_SH(x)    (((x) & 0x1f) << 15)
-#define PSC_SMBTMR_SET_SU(x)    (((x) & 0x1f) << 10)
-#define PSC_SMBTMR_SET_CL(x)    (((x) & 0x1f) << 5)
-#define PSC_SMBTMR_SET_CH(x)    (((x) & 0x1f) << 0)
-
-#endif /* _AU1000_PSC_H_ */
diff --git a/include/asm-mips/mach-au1x00/gpio.h b/include/asm-mips/mach-au1x00/gpio.h
deleted file mode 100644
index 2dc61e009a08..000000000000
--- a/include/asm-mips/mach-au1x00/gpio.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _AU1XXX_GPIO_H_
-#define _AU1XXX_GPIO_H_
-
-#include <linux/types.h>
-
-#define AU1XXX_GPIO_BASE        200
-
-struct au1x00_gpio2 {
-        u32     dir;
-        u32     reserved;
-        u32     output;
-        u32     pinstate;
-        u32     inten;
-        u32     enable;
-};
-
-extern int au1xxx_gpio_get_value(unsigned gpio);
-extern void au1xxx_gpio_set_value(unsigned gpio, int value);
-extern int au1xxx_gpio_direction_input(unsigned gpio);
-extern int au1xxx_gpio_direction_output(unsigned gpio, int value);
-
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        /* Not yet implemented */
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        /* Not yet implemented */
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        return au1xxx_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        return au1xxx_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return au1xxx_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        au1xxx_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return irq;
-}
-
-/* For cansleep */
-#include <asm-generic/gpio.h>
-
-#endif /* _AU1XXX_GPIO_H_ */
diff --git a/include/asm-mips/mach-au1x00/ioremap.h b/include/asm-mips/mach-au1x00/ioremap.h
deleted file mode 100644
index 364cea2dc71f..000000000000
--- a/include/asm-mips/mach-au1x00/ioremap.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *      include/asm-mips/mach-au1x00/ioremap.h
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MACH_AU1X00_IOREMAP_H
-#define __ASM_MACH_AU1X00_IOREMAP_H
-
-#include <linux/types.h>
-
-#ifdef CONFIG_64BIT_PHYS_ADDR
-extern phys_t __fixup_bigphys_addr(phys_t, phys_t);
-#else
-static inline phys_t __fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-        return phys_addr;
-}
-#endif
-
-/*
- * Allow physical addresses to be fixed up to help 36-bit peripherals.
- */
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-        return __fixup_bigphys_addr(phys_addr, size);
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-        unsigned long flags)
-{
-        return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-        return 0;
-}
-
-#endif /* __ASM_MACH_AU1X00_IOREMAP_H */
diff --git a/include/asm-mips/mach-au1x00/prom.h b/include/asm-mips/mach-au1x00/prom.h
deleted file mode 100644
index e38715577c51..000000000000
--- a/include/asm-mips/mach-au1x00/prom.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __AU1X00_PROM_H
-#define __AU1X00_PROM_H
-
-extern int prom_argc;
-extern char **prom_argv;
-extern char **prom_envp;
-
-extern void prom_init_cmdline(void);
-extern char *prom_getcmdline(void);
-extern char *prom_getenv(char *envname);
-extern int prom_get_ethernet_addr(char *ethernet_addr);
-
-#endif
diff --git a/include/asm-mips/mach-au1x00/war.h b/include/asm-mips/mach-au1x00/war.h
deleted file mode 100644
index dd57d03d68ba..000000000000
--- a/include/asm-mips/mach-au1x00/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_AU1X00_WAR_H
-#define __ASM_MIPS_MACH_AU1X00_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_AU1X00_WAR_H */
diff --git a/include/asm-mips/mach-bcm47xx/bcm47xx.h b/include/asm-mips/mach-bcm47xx/bcm47xx.h
deleted file mode 100644
index d008f47a28bd..000000000000
--- a/include/asm-mips/mach-bcm47xx/bcm47xx.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef __ASM_BCM47XX_H
-#define __ASM_BCM47XX_H
-
-/* SSB bus */
-extern struct ssb_bus ssb_bcm47xx;
-
-#endif /* __ASM_BCM47XX_H */
diff --git a/include/asm-mips/mach-bcm47xx/gpio.h b/include/asm-mips/mach-bcm47xx/gpio.h
deleted file mode 100644
index cfc8f4d618ce..000000000000
--- a/include/asm-mips/mach-bcm47xx/gpio.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Aurelien Jarno <aurelien@aurel32.net>
- */
-
-#ifndef __BCM47XX_GPIO_H
-#define __BCM47XX_GPIO_H
-
-#define BCM47XX_EXTIF_GPIO_LINES        5
-#define BCM47XX_CHIPCO_GPIO_LINES       16
-
-extern int bcm47xx_gpio_to_irq(unsigned gpio);
-extern int bcm47xx_gpio_get_value(unsigned gpio);
-extern void bcm47xx_gpio_set_value(unsigned gpio, int value);
-extern int bcm47xx_gpio_direction_input(unsigned gpio);
-extern int bcm47xx_gpio_direction_output(unsigned gpio, int value);
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-       return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return bcm47xx_gpio_to_irq(gpio);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return bcm47xx_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        bcm47xx_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        return bcm47xx_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        return bcm47xx_gpio_direction_output(gpio, value);
-}
-
-
-/* cansleep wrappers */
-#include <asm-generic/gpio.h>
-
-#endif /* __BCM47XX_GPIO_H */
diff --git a/include/asm-mips/mach-bcm47xx/war.h b/include/asm-mips/mach-bcm47xx/war.h
deleted file mode 100644
index 4a2b7986b582..000000000000
--- a/include/asm-mips/mach-bcm47xx/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_BCM947XX_WAR_H
-#define __ASM_MIPS_MACH_BCM947XX_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_BCM947XX_WAR_H */
diff --git a/include/asm-mips/mach-cobalt/cobalt.h b/include/asm-mips/mach-cobalt/cobalt.h
deleted file mode 100644
index 5b9fce73f11d..000000000000
--- a/include/asm-mips/mach-cobalt/cobalt.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * The Cobalt board ID information.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997 Cobalt Microserver
- * Copyright (C) 1997, 2003 Ralf Baechle
- * Copyright (C) 2001, 2002, 2003 Liam Davies (ldavies@agile.tv)
- */
-#ifndef __ASM_COBALT_H
-#define __ASM_COBALT_H
-
-extern int cobalt_board_id;
-
-#define COBALT_BRD_ID_QUBE1    0x3
-#define COBALT_BRD_ID_RAQ1     0x4
-#define COBALT_BRD_ID_QUBE2    0x5
-#define COBALT_BRD_ID_RAQ2     0x6
-
-#endif /* __ASM_COBALT_H */
diff --git a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h b/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
deleted file mode 100644
index b3314cf53194..000000000000
--- a/include/asm-mips/mach-cobalt/cpu-feature-overrides.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006, 07 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
-#define __ASM_COBALT_CPU_FEATURE_OVERRIDES_H
-
-
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_3k_cache        0
-#define cpu_has_4k_cache        1
-#define cpu_has_tx39_cache      0
-#define cpu_has_fpu             1
-#define cpu_has_32fpr           1
-#define cpu_has_counter         1
-#define cpu_has_watch           0
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        0
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_inclusive_pcaches       0
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  0
-
-#ifdef CONFIG_64BIT
-#define cpu_has_llsc            0
-#else
-#define cpu_has_llsc            1
-#endif
-
-#define cpu_has_mips16          0
-#define cpu_has_mdmx            0
-#define cpu_has_mips3d          0
-#define cpu_has_smartmips       0
-#define cpu_has_vtag_icache     0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_icache_snoops_remote_store  0
-#define cpu_has_dsp             0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_COBALT_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-cobalt/irq.h b/include/asm-mips/mach-cobalt/irq.h
deleted file mode 100644
index 57c8c9ac5851..000000000000
--- a/include/asm-mips/mach-cobalt/irq.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * Cobalt IRQ definitions.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997 Cobalt Microserver
- * Copyright (C) 1997, 2003 Ralf Baechle
- * Copyright (C) 2001-2003 Liam Davies (ldavies@agile.tv)
- * Copyright (C) 2007 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- */
-#ifndef _ASM_COBALT_IRQ_H
-#define _ASM_COBALT_IRQ_H
-
-/*
- * i8259 interrupts used on Cobalt:
- *
- *      8  - RTC
- *      9  - PCI slot
- *      14 - IDE0
- *      15 - IDE1(no connector on board)
- */
-#define I8259A_IRQ_BASE                 0
-
-#define PCISLOT_IRQ                     (I8259A_IRQ_BASE + 9)
-
-/*
- * CPU interrupts used on Cobalt:
- *
- *      0 - Software interrupt 0 (unused)
- *      1 - Software interrupt 0 (unused)
- *      2 - cascade GT64111
- *      3 - ethernet or SCSI host controller
- *      4 - ethernet
- *      5 - 16550 UART
- *      6 - cascade i8259
- *      7 - CP0 counter
- */
-#define MIPS_CPU_IRQ_BASE               16
-
-#define GT641XX_CASCADE_IRQ             (MIPS_CPU_IRQ_BASE + 2)
-#define RAQ2_SCSI_IRQ                   (MIPS_CPU_IRQ_BASE + 3)
-#define ETH0_IRQ                        (MIPS_CPU_IRQ_BASE + 3)
-#define QUBE1_ETH0_IRQ                  (MIPS_CPU_IRQ_BASE + 4)
-#define ETH1_IRQ                        (MIPS_CPU_IRQ_BASE + 4)
-#define SERIAL_IRQ                      (MIPS_CPU_IRQ_BASE + 5)
-#define SCSI_IRQ                        (MIPS_CPU_IRQ_BASE + 5)
-#define I8259_CASCADE_IRQ               (MIPS_CPU_IRQ_BASE + 6)
-
-#define GT641XX_IRQ_BASE                24
-
-#include <asm/irq_gt641xx.h>
-
-#define NR_IRQS                                 (GT641XX_PCI_INT3_IRQ + 1)
-
-#endif /* _ASM_COBALT_IRQ_H */
diff --git a/include/asm-mips/mach-cobalt/mach-gt64120.h b/include/asm-mips/mach-cobalt/mach-gt64120.h
deleted file mode 100644
index ae9c5523c7ef..000000000000
--- a/include/asm-mips/mach-cobalt/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  Copyright (C) 2006  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301  USA
- */
-#ifndef _COBALT_MACH_GT64120_H
-#define _COBALT_MACH_GT64120_H
-
-/*
- * Cobalt uses GT64111. GT64111 is almost the same as GT64120.
- */
-
-#define GT64120_BASE    CKSEG1ADDR(GT_DEF_BASE)
-
-#endif /* _COBALT_MACH_GT64120_H */
diff --git a/include/asm-mips/mach-cobalt/war.h b/include/asm-mips/mach-cobalt/war.h
deleted file mode 100644
index 97884fd18ac0..000000000000
--- a/include/asm-mips/mach-cobalt/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_COBALT_WAR_H
-#define __ASM_MIPS_MACH_COBALT_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_COBALT_WAR_H */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
deleted file mode 100644
index 27f26102b1bb..000000000000
--- a/include/asm-mips/mach-db1x00/db1200.h
+++ /dev/null
@@ -1,230 +0,0 @@
-/*
- * AMD Alchemy DBAu1200 Reference Board
- * Board register defines.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1200_H
-#define __ASM_DB1200_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
-
-/*
- * SPI and SMB are muxed on the DBAu1200 board.
- * Refer to board documentation.
- */
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
-/*
- * AC'97 and I2S are muxed on the DBAu1200 board.
- * Refer to board documentation.
- */
-#define AC97_PSC_BASE           PSC1_BASE_ADDR
-#define I2S_PSC_BASE            PSC1_BASE_ADDR
-
-#define BCSR_KSEG1_ADDR         0xB9800000
-
-typedef volatile struct
-{
-        /*00*/  u16 whoami;
-                u16 reserved0;
-        /*04*/  u16 status;
-                u16 reserved1;
-        /*08*/  u16 switches;
-                u16 reserved2;
-        /*0C*/  u16 resets;
-                u16 reserved3;
-
-        /*10*/  u16 pcmcia;
-                u16 reserved4;
-        /*14*/  u16 board;
-                u16 reserved5;
-        /*18*/  u16 disk_leds;
-                u16 reserved6;
-        /*1C*/  u16 system;
-                u16 reserved7;
-
-        /*20*/  u16 intclr;
-                u16 reserved8;
-        /*24*/  u16 intset;
-                u16 reserved9;
-        /*28*/  u16 intclr_mask;
-                u16 reserved10;
-        /*2C*/  u16 intset_mask;
-                u16 reserved11;
-
-        /*30*/  u16 sig_status;
-                u16 reserved12;
-        /*34*/  u16 int_status;
-                u16 reserved13;
-        /*38*/  u16 reserved14;
-                u16 reserved15;
-        /*3C*/  u16 reserved16;
-                u16 reserved17;
-
-} BCSR;
-
-static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-
-/*
- * Register bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID        0x000F
-#define BCSR_WHOAMI_CPLD        0x00F0
-#define BCSR_WHOAMI_BOARD       0x0F00
-
-#define BCSR_STATUS_PCMCIA0VS   0x0003
-#define BCSR_STATUS_PCMCIA1VS   0x000C
-#define BCSR_STATUS_SWAPBOOT    0x0040
-#define BCSR_STATUS_FLASHBUSY   0x0100
-#define BCSR_STATUS_IDECBLID    0x0200
-#define BCSR_STATUS_SD0WP       0x0400
-#define BCSR_STATUS_U0RXD       0x1000
-#define BCSR_STATUS_U1RXD       0x2000
-
-#define BCSR_SWITCHES_OCTAL     0x00FF
-#define BCSR_SWITCHES_DIP_1     0x0080
-#define BCSR_SWITCHES_DIP_2     0x0040
-#define BCSR_SWITCHES_DIP_3     0x0020
-#define BCSR_SWITCHES_DIP_4     0x0010
-#define BCSR_SWITCHES_DIP_5     0x0008
-#define BCSR_SWITCHES_DIP_6     0x0004
-#define BCSR_SWITCHES_DIP_7     0x0002
-#define BCSR_SWITCHES_DIP_8     0x0001
-#define BCSR_SWITCHES_ROTARY    0x0F00
-
-#define BCSR_RESETS_ETH         0x0001
-#define BCSR_RESETS_CAMERA      0x0002
-#define BCSR_RESETS_DC          0x0004
-#define BCSR_RESETS_IDE         0x0008
-#define BCSR_RESETS_TV          0x0010
-/* Not resets but in the same register */
-#define BCSR_RESETS_PWMR1MUX    0x0800
-#define BCSR_RESETS_PCS0MUX     0x1000
-#define BCSR_RESETS_PCS1MUX     0x2000
-#define BCSR_RESETS_SPISEL      0x4000
-
-#define BCSR_PCMCIA_PC0VPP      0x0003
-#define BCSR_PCMCIA_PC0VCC      0x000C
-#define BCSR_PCMCIA_PC0DRVEN    0x0010
-#define BCSR_PCMCIA_PC0RST      0x0080
-#define BCSR_PCMCIA_PC1VPP      0x0300
-#define BCSR_PCMCIA_PC1VCC      0x0C00
-#define BCSR_PCMCIA_PC1DRVEN    0x1000
-#define BCSR_PCMCIA_PC1RST      0x8000
-
-#define BCSR_BOARD_LCDVEE       0x0001
-#define BCSR_BOARD_LCDVDD       0x0002
-#define BCSR_BOARD_LCDBL        0x0004
-#define BCSR_BOARD_CAMSNAP      0x0010
-#define BCSR_BOARD_CAMPWR       0x0020
-#define BCSR_BOARD_SD0PWR       0x0040
-
-#define BCSR_LEDS_DECIMALS      0x0003
-#define BCSR_LEDS_LED0          0x0100
-#define BCSR_LEDS_LED1          0x0200
-#define BCSR_LEDS_LED2          0x0400
-#define BCSR_LEDS_LED3          0x0800
-
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
-/* Bit positions for the different interrupt sources */
-#define BCSR_INT_IDE            0x0001
-#define BCSR_INT_ETH            0x0002
-#define BCSR_INT_PC0            0x0004
-#define BCSR_INT_PC0STSCHG      0x0008
-#define BCSR_INT_PC1            0x0010
-#define BCSR_INT_PC1STSCHG      0x0020
-#define BCSR_INT_DC             0x0040
-#define BCSR_INT_FLASHBUSY      0x0080
-#define BCSR_INT_PC0INSERT      0x0100
-#define BCSR_INT_PC0EJECT       0x0200
-#define BCSR_INT_PC1INSERT      0x0400
-#define BCSR_INT_PC1EJECT       0x0800
-#define BCSR_INT_SD0INSERT      0x1000
-#define BCSR_INT_SD0EJECT       0x2000
-
-#define SMC91C111_PHYS_ADDR     0x19000300
-#define SMC91C111_INT           DB1200_ETH_INT
-
-#define IDE_PHYS_ADDR           0x18800000
-#define IDE_REG_SHIFT           5
-#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
-#define IDE_INT                 DB1200_IDE_INT
-#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
-#define IDE_RQSIZE              128
-
-#define NAND_PHYS_ADDR          0x20000000
-
-/*
- * External Interrupts for DBAu1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the DB1200_INT_BEGIN value.
- *
- *   Example: IDE bis pos is  = 64 - 64
- *            ETH bit pos is  = 65 - 64
- */
-enum external_pb1200_ints {
-        DB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
-
-        DB1200_IDE_INT          = DB1200_INT_BEGIN,
-        DB1200_ETH_INT,
-        DB1200_PC0_INT,
-        DB1200_PC0_STSCHG_INT,
-        DB1200_PC1_INT,
-        DB1200_PC1_STSCHG_INT,
-        DB1200_DC_INT,
-        DB1200_FLASHBUSY_INT,
-        DB1200_PC0_INSERT_INT,
-        DB1200_PC0_EJECT_INT,
-        DB1200_PC1_INSERT_INT,
-        DB1200_PC1_EJECT_INT,
-        DB1200_SD0_INSERT_INT,
-        DB1200_SD0_EJECT_INT,
-
-        DB1200_INT_END          = DB1200_INT_BEGIN + 15,
-};
-
-
-/*
- * DBAu1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
- */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-#define BOARD_PC0_INT   DB1200_PC0_INT
-#define BOARD_PC1_INT   DB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
-
-/* NAND chip select */
-#define NAND_CS 1
-
-#endif /* __ASM_DB1200_H */
diff --git a/include/asm-mips/mach-db1x00/db1x00.h b/include/asm-mips/mach-db1x00/db1x00.h
deleted file mode 100644
index 1a515b8c870f..000000000000
--- a/include/asm-mips/mach-db1x00/db1x00.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * AMD Alchemy DBAu1x00 Reference Boards
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_DB1X00_H
-#define __ASM_DB1X00_H
-
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#ifdef CONFIG_MIPS_DB1550
-
-#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define AC97_PSC_BASE           PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
-#define I2S_PSC_BASE            PSC3_BASE_ADDR
-
-#define BCSR_KSEG1_ADDR         0xAF000000
-#define NAND_PHYS_ADDR          0x20000000
-
-#else
-#define BCSR_KSEG1_ADDR 0xAE000000
-#endif
-
-/*
- * Overlay data structure of the DBAu1x00 board registers.
- * Registers are located at physical 0E0000xx, KSEG1 0xAE0000xx.
- */
-typedef volatile struct
-{
-        /*00*/  unsigned short whoami;
-        unsigned short reserved0;
-        /*04*/  unsigned short status;
-        unsigned short reserved1;
-        /*08*/  unsigned short switches;
-        unsigned short reserved2;
-        /*0C*/  unsigned short resets;
-        unsigned short reserved3;
-        /*10*/  unsigned short pcmcia;
-        unsigned short reserved4;
-        /*14*/  unsigned short specific;
-        unsigned short reserved5;
-        /*18*/  unsigned short leds;
-        unsigned short reserved6;
-        /*1C*/  unsigned short swreset;
-        unsigned short reserved7;
-
-} BCSR;
-
-
-/*
- * Register/mask bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID                0x000F
-#define BCSR_WHOAMI_CPLD                0x00F0
-#define BCSR_WHOAMI_BOARD               0x0F00
-
-#define BCSR_STATUS_PC0VS               0x0003
-#define BCSR_STATUS_PC1VS               0x000C
-#define BCSR_STATUS_PC0FI               0x0010
-#define BCSR_STATUS_PC1FI               0x0020
-#define BCSR_STATUS_FLASHBUSY           0x0100
-#define BCSR_STATUS_ROMBUSY             0x0400
-#define BCSR_STATUS_SWAPBOOT            0x2000
-#define BCSR_STATUS_FLASHDEN            0xC000
-
-#define BCSR_SWITCHES_DIP               0x00FF
-#define BCSR_SWITCHES_DIP_1             0x0080
-#define BCSR_SWITCHES_DIP_2             0x0040
-#define BCSR_SWITCHES_DIP_3             0x0020
-#define BCSR_SWITCHES_DIP_4             0x0010
-#define BCSR_SWITCHES_DIP_5             0x0008
-#define BCSR_SWITCHES_DIP_6             0x0004
-#define BCSR_SWITCHES_DIP_7             0x0002
-#define BCSR_SWITCHES_DIP_8             0x0001
-#define BCSR_SWITCHES_ROTARY            0x0F00
-
-#define BCSR_RESETS_PHY0                0x0001
-#define BCSR_RESETS_PHY1                0x0002
-#define BCSR_RESETS_DC                  0x0004
-#define BCSR_RESETS_FIR_SEL             0x2000
-#define BCSR_RESETS_IRDA_MODE_MASK      0xC000
-#define BCSR_RESETS_IRDA_MODE_FULL      0x0000
-#define BCSR_RESETS_IRDA_MODE_OFF       0x4000
-#define BCSR_RESETS_IRDA_MODE_2_3       0x8000
-#define BCSR_RESETS_IRDA_MODE_1_3       0xC000
-
-#define BCSR_PCMCIA_PC0VPP              0x0003
-#define BCSR_PCMCIA_PC0VCC              0x000C
-#define BCSR_PCMCIA_PC0DRVEN            0x0010
-#define BCSR_PCMCIA_PC0RST              0x0080
-#define BCSR_PCMCIA_PC1VPP              0x0300
-#define BCSR_PCMCIA_PC1VCC              0x0C00
-#define BCSR_PCMCIA_PC1DRVEN            0x1000
-#define BCSR_PCMCIA_PC1RST              0x8000
-
-#define BCSR_BOARD_PCIM66EN             0x0001
-#define BCSR_BOARD_SD0_PWR              0x0040
-#define BCSR_BOARD_SD1_PWR              0x0080
-#define BCSR_BOARD_PCIM33               0x0100
-#define BCSR_BOARD_GPIO200RST           0x0400
-#define BCSR_BOARD_PCICFG               0x1000
-#define BCSR_BOARD_SD0_WP               0x4000
-#define BCSR_BOARD_SD1_WP               0x8000
-
-#define BCSR_LEDS_DECIMALS              0x0003
-#define BCSR_LEDS_LED0                  0x0100
-#define BCSR_LEDS_LED1                  0x0200
-#define BCSR_LEDS_LED2                  0x0400
-#define BCSR_LEDS_LED3                  0x0800
-
-#define BCSR_SWRESET_RESET              0x0080
-
-/* PCMCIA DBAu1x00 specific defines */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT)\
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-/*
- * NAND defines
- *
- * Timing values as described in databook, * ns value stripped of the
- * lower 2 bits.
- * These defines are here rather than an Au1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-#define NAND_CS         1
-
-/* Should be done by YAMON */
-#define NAND_STCFG      0x00400005 /* 8-bit NAND */
-#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_DB1X00_H */
diff --git a/include/asm-mips/mach-dec/mc146818rtc.h b/include/asm-mips/mach-dec/mc146818rtc.h
deleted file mode 100644
index 6724e99e43e1..000000000000
--- a/include/asm-mips/mach-dec/mc146818rtc.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * RTC definitions for DECstation style attached Dallas DS1287 chip.
- *
- * Copyright (C) 1998, 2001 by Ralf Baechle
- * Copyright (C) 1998 by Harald Koerfgen
- * Copyright (C) 2002, 2005  Maciej W. Rozycki
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MIPS_DEC_RTC_DEC_H
-#define __ASM_MIPS_DEC_RTC_DEC_H
-
-#include <linux/types.h>
-#include <asm/addrspace.h>
-#include <asm/dec/system.h>
-
-extern volatile u8 *dec_rtc_base;
-
-#define ARCH_RTC_LOCATION
-
-#define RTC_PORT(x)     CPHYSADDR((long)dec_rtc_base)
-#define RTC_IO_EXTENT   dec_kn_slot_size
-#define RTC_IOMAPPED    0
-#undef RTC_IRQ
-
-#define RTC_DEC_YEAR    0x3f    /* Where we store the real year on DECs.  */
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        return dec_rtc_base[addr * 4];
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        dec_rtc_base[addr * 4] = data;
-}
-
-#define RTC_ALWAYS_BCD  0
-
-#endif /* __ASM_MIPS_DEC_RTC_DEC_H */
diff --git a/include/asm-mips/mach-dec/war.h b/include/asm-mips/mach-dec/war.h
deleted file mode 100644
index ca5e2ef909ad..000000000000
--- a/include/asm-mips/mach-dec/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_DEC_WAR_H
-#define __ASM_MIPS_MACH_DEC_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_DEC_WAR_H */
diff --git a/include/asm-mips/mach-emma2rh/irq.h b/include/asm-mips/mach-emma2rh/irq.h
deleted file mode 100644
index 5439eb856461..000000000000
--- a/include/asm-mips/mach-emma2rh/irq.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-#ifndef __ASM_MACH_EMMA2RH_IRQ_H
-#define __ASM_MACH_EMMA2RH_IRQ_H
-
-#define NR_IRQS 256
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_EMMA2RH_IRQ_H */
diff --git a/include/asm-mips/mach-emma2rh/war.h b/include/asm-mips/mach-emma2rh/war.h
deleted file mode 100644
index b660a4c30e6a..000000000000
--- a/include/asm-mips/mach-emma2rh/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_EMMA2RH_WAR_H
-#define __ASM_MIPS_MACH_EMMA2RH_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_EMMA2RH_WAR_H */
diff --git a/include/asm-mips/mach-excite/cpu-feature-overrides.h b/include/asm-mips/mach-excite/cpu-feature-overrides.h
deleted file mode 100644
index 107104c3cd12..000000000000
--- a/include/asm-mips/mach-excite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 Thomas Koeller <thomas.koeller@baslerweb.com>
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Basler eXcite has an RM9122 processor.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-
-#endif /* __ASM_MACH_EXCITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-excite/excite.h b/include/asm-mips/mach-excite/excite.h
deleted file mode 100644
index 4c29ba44992c..000000000000
--- a/include/asm-mips/mach-excite/excite.h
+++ /dev/null
@@ -1,154 +0,0 @@
-#ifndef __EXCITE_H__
-#define __EXCITE_H__
-
-#include <linux/init.h>
-#include <asm/addrspace.h>
-#include <asm/types.h>
-
-#define EXCITE_CPU_EXT_CLOCK 100000000
-
-#if !defined(__ASSEMBLY__)
-void __init excite_kgdb_init(void);
-void excite_procfs_init(void);
-extern unsigned long memsize;
-extern char modetty[];
-extern u32 unit_id;
-#endif
-
-/* Base name for XICAP devices */
-#define XICAP_NAME      "xicap_gpi"
-
-/* OCD register offsets */
-#define LKB0            0x0038
-#define LKB5            0x0128
-#define LKM5            0x012C
-#define LKB7            0x0138
-#define LKM7            0x013c
-#define LKB8            0x0140
-#define LKM8            0x0144
-#define LKB9            0x0148
-#define LKM9            0x014c
-#define LKB10           0x0150
-#define LKM10           0x0154
-#define LKB11           0x0158
-#define LKM11           0x015c
-#define LKB12           0x0160
-#define LKM12           0x0164
-#define LKB13           0x0168
-#define LKM13           0x016c
-#define LDP0            0x0200
-#define LDP1            0x0210
-#define LDP2            0x0220
-#define LDP3            0x0230
-#define INTPIN0         0x0A40
-#define INTPIN1         0x0A44
-#define INTPIN2         0x0A48
-#define INTPIN3         0x0A4C
-#define INTPIN4         0x0A50
-#define INTPIN5         0x0A54
-#define INTPIN6         0x0A58
-#define INTPIN7         0x0A5C
-
-
-
-
-/* TITAN register offsets */
-#define CPRR            0x0004
-#define CPDSR           0x0008
-#define CPTC0R          0x000c
-#define CPTC1R          0x0010
-#define CPCFG0          0x0020
-#define CPCFG1          0x0024
-#define CPDST0A         0x0028
-#define CPDST0B         0x002c
-#define CPDST1A         0x0030
-#define CPDST1B         0x0034
-#define CPXDSTA         0x0038
-#define CPXDSTB         0x003c
-#define CPXCISRA        0x0048
-#define CPXCISRB        0x004c
-#define CPGIG0ER        0x0050
-#define CPGIG1ER        0x0054
-#define CPGRWL          0x0068
-#define CPURSLMT        0x00f8
-#define UACFG           0x0200
-#define UAINTS          0x0204
-#define SDRXFCIE        0x4828
-#define SDTXFCIE        0x4928
-#define INTP0Status0    0x1B00
-#define INTP0Mask0      0x1B04
-#define INTP0Set0       0x1B08
-#define INTP0Clear0     0x1B0C
-#define GXCFG           0x5000
-#define GXDMADRPFX      0x5018
-#define GXDMA_DESCADR   0x501c
-#define GXCH0TDESSTRT   0x5054
-
-/* IRQ definitions */
-#define NMICONFIG               0xac0
-#define TITAN_MSGINT    0xc4
-#define TITAN_IRQ       ((TITAN_MSGINT / 0x20) + 2)
-#define FPGA0_MSGINT    0x5a
-#define FPGA0_IRQ       ((FPGA0_MSGINT / 0x20) + 2)
-#define FPGA1_MSGINT    0x7b
-#define FPGA1_IRQ       ((FPGA1_MSGINT / 0x20) + 2)
-#define PHY_MSGINT      0x9c
-#define PHY_IRQ         ((PHY_MSGINT   / 0x20) + 2)
-
-#if defined(CONFIG_BASLER_EXCITE_PROTOTYPE)
-/* Pre-release units used interrupt pin #9 */
-#define USB_IRQ         11
-#else
-/* Re-designed units use interrupt pin #1 */
-#define USB_MSGINT      0x39
-#define USB_IRQ         ((USB_MSGINT / 0x20) + 2)
-#endif
-#define TIMER_IRQ       12
-
-
-/* Device address ranges */
-#define EXCITE_OFFS_OCD         0x1fffc000
-#define EXCITE_SIZE_OCD         (16 * 1024)
-#define EXCITE_PHYS_OCD         CPHYSADDR(EXCITE_OFFS_OCD)
-#define EXCITE_ADDR_OCD         CKSEG1ADDR(EXCITE_OFFS_OCD)
-
-#define EXCITE_OFFS_SCRAM       0x1fffa000
-#define EXCITE_SIZE_SCRAM       (8 << 10)
-#define EXCITE_PHYS_SCRAM       CPHYSADDR(EXCITE_OFFS_SCRAM)
-#define EXCITE_ADDR_SCRAM       CKSEG1ADDR(EXCITE_OFFS_SCRAM)
-
-#define EXCITE_OFFS_PCI_IO      0x1fff8000
-#define EXCITE_SIZE_PCI_IO      (8 << 10)
-#define EXCITE_PHYS_PCI_IO      CPHYSADDR(EXCITE_OFFS_PCI_IO)
-#define EXCITE_ADDR_PCI_IO      CKSEG1ADDR(EXCITE_OFFS_PCI_IO)
-
-#define EXCITE_OFFS_TITAN       0x1fff0000
-#define EXCITE_SIZE_TITAN       (32 << 10)
-#define EXCITE_PHYS_TITAN       CPHYSADDR(EXCITE_OFFS_TITAN)
-#define EXCITE_ADDR_TITAN       CKSEG1ADDR(EXCITE_OFFS_TITAN)
-
-#define EXCITE_OFFS_PCI_MEM     0x1ffe0000
-#define EXCITE_SIZE_PCI_MEM     (64 << 10)
-#define EXCITE_PHYS_PCI_MEM     CPHYSADDR(EXCITE_OFFS_PCI_MEM)
-#define EXCITE_ADDR_PCI_MEM     CKSEG1ADDR(EXCITE_OFFS_PCI_MEM)
-
-#define EXCITE_OFFS_FPGA        0x1ffdc000
-#define EXCITE_SIZE_FPGA        (16 << 10)
-#define EXCITE_PHYS_FPGA        CPHYSADDR(EXCITE_OFFS_FPGA)
-#define EXCITE_ADDR_FPGA        CKSEG1ADDR(EXCITE_OFFS_FPGA)
-
-#define EXCITE_OFFS_NAND        0x1ffd8000
-#define EXCITE_SIZE_NAND        (16 << 10)
-#define EXCITE_PHYS_NAND        CPHYSADDR(EXCITE_OFFS_NAND)
-#define EXCITE_ADDR_NAND        CKSEG1ADDR(EXCITE_OFFS_NAND)
-
-#define EXCITE_OFFS_BOOTROM     0x1f000000
-#define EXCITE_SIZE_BOOTROM     (8 << 20)
-#define EXCITE_PHYS_BOOTROM     CPHYSADDR(EXCITE_OFFS_BOOTROM)
-#define EXCITE_ADDR_BOOTROM     CKSEG1ADDR(EXCITE_OFFS_BOOTROM)
-
-/* FPGA address offsets */
-#define EXCITE_FPGA_DPR         0x0104  /* dual-ported ram */
-#define EXCITE_FPGA_SYSCTL      0x0200  /* system control register block */
-
-#endif /* __EXCITE_H__ */
diff --git a/include/asm-mips/mach-excite/excite_fpga.h b/include/asm-mips/mach-excite/excite_fpga.h
deleted file mode 100644
index 0a1ef69bece7..000000000000
--- a/include/asm-mips/mach-excite/excite_fpga.h
+++ /dev/null
@@ -1,80 +0,0 @@
-#ifndef EXCITE_FPGA_H_INCLUDED
-#define EXCITE_FPGA_H_INCLUDED
-
-
-/**
- * Address alignment of the individual FPGA bytes.
- * The address arrangement of the individual bytes of the FPGA is two
- * byte aligned at the embedded MK2 platform.
- */
-#ifdef EXCITE_CCI_FPGA_MK2
-typedef unsigned char excite_cci_fpga_align_t __attribute__ ((aligned(2)));
-#else
-typedef unsigned char excite_cci_fpga_align_t;
-#endif
-
-
-/**
- * Size of Dual Ported RAM.
- */
-#define EXCITE_DPR_SIZE 263
-
-
-/**
- * Size of Reserved Status Fields in Dual Ported RAM.
- */
-#define EXCITE_DPR_STATUS_SIZE 7
-
-
-
-/**
- * FPGA.
- * Hardware register layout of the FPGA interface. The FPGA must accessed
- * byte wise solely.
- * @see EXCITE_CCI_DPR_MK2
- */
-typedef struct excite_fpga {
-
-        /**
-         * Dual Ported RAM.
-         */
-        excite_cci_fpga_align_t dpr[EXCITE_DPR_SIZE];
-
-        /**
-         * Status.
-         */
-        excite_cci_fpga_align_t status[EXCITE_DPR_STATUS_SIZE];
-
-#ifdef EXCITE_CCI_FPGA_MK2
-        /**
-         * RM9000 Interrupt.
-         * Write access initiates interrupt at the RM9000 (MIPS) processor of the eXcite.
-         */
-        excite_cci_fpga_align_t rm9k_int;
-#else
-        /**
-         * MK2 Interrupt.
-         * Write access initiates interrupt at the ARM processor of the MK2.
-         */
-        excite_cci_fpga_align_t mk2_int;
-
-        excite_cci_fpga_align_t gap[0x1000-0x10f];
-
-        /**
-         * IRQ Source/Acknowledge.
-         */
-        excite_cci_fpga_align_t rm9k_irq_src;
-
-        /**
-         * IRQ Mask.
-         * Set bits enable the related interrupt.
-         */
-        excite_cci_fpga_align_t rm9k_irq_mask;
-#endif
-
-
-} excite_fpga;
-
-
-
-#endif  /* ndef EXCITE_FPGA_H_INCLUDED */
diff --git a/include/asm-mips/mach-excite/excite_nandflash.h b/include/asm-mips/mach-excite/excite_nandflash.h
deleted file mode 100644
index c4cf6140622e..000000000000
--- a/include/asm-mips/mach-excite/excite_nandflash.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __EXCITE_NANDFLASH_H__
-#define __EXCITE_NANDFLASH_H__
-
-/* Resource names */
-#define EXCITE_NANDFLASH_RESOURCE_REGS  "excite_nandflash_regs"
-
-#endif /* __EXCITE_NANDFLASH_H__ */
diff --git a/include/asm-mips/mach-excite/rm9k_eth.h b/include/asm-mips/mach-excite/rm9k_eth.h
deleted file mode 100644
index 94705a46f72e..000000000000
--- a/include/asm-mips/mach-excite/rm9k_eth.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#if !defined(__RM9K_ETH_H__)
-#define __RM9K_ETH_H__
-
-#define RM9K_GE_NAME                    "rm9k_ge"
-
-/* Resource names */
-#define RM9K_GE_RESOURCE_MAC            "rm9k_ge_mac"
-#define RM9K_GE_RESOURCE_MSTAT          "rm9k_ge_mstat"
-#define RM9K_GE_RESOURCE_PKTPROC        "rm9k_ge_pktproc"
-#define RM9K_GE_RESOURCE_XDMA           "rm9k_ge_xdma"
-#define RM9K_GE_RESOURCE_FIFO_RX        "rm9k_ge_fifo_rx"
-#define RM9K_GE_RESOURCE_FIFO_TX        "rm9k_ge_fifo_tx"
-#define RM9K_GE_RESOURCE_FIFOMEM_RX     "rm9k_ge_fifo_memory_rx"
-#define RM9K_GE_RESOURCE_FIFOMEM_TX     "rm9k_ge_fifo_memory_tx"
-#define RM9K_GE_RESOURCE_PHY            "rm9k_ge_phy"
-#define RM9K_GE_RESOURCE_DMADESC_RX     "rm9k_ge_dmadesc_rx"
-#define RM9K_GE_RESOURCE_DMADESC_TX     "rm9k_ge_dmadesc_tx"
-#define RM9K_GE_RESOURCE_IRQ_MAIN       "rm9k_ge_irq_main"
-#define RM9K_GE_RESOURCE_IRQ_PHY        "rm9k_ge_irq_phy"
-#define RM9K_GE_RESOURCE_GPI_SLICE      "rm9k_ge_gpi_slice"
-#define RM9K_GE_RESOURCE_MDIO_CHANNEL   "rm9k_ge_mdio_channel"
-
-#endif /* !defined(__RM9K_ETH_H__) */
diff --git a/include/asm-mips/mach-excite/rm9k_wdt.h b/include/asm-mips/mach-excite/rm9k_wdt.h
deleted file mode 100644
index 3fa3c08d2da7..000000000000
--- a/include/asm-mips/mach-excite/rm9k_wdt.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef __RM9K_WDT_H__
-#define __RM9K_WDT_H__
-
-/* Device name */
-#define WDT_NAME                "wdt_gpi"
-
-/* Resource names */
-#define WDT_RESOURCE_REGS       "excite_watchdog_regs"
-#define WDT_RESOURCE_IRQ        "excite_watchdog_irq"
-#define WDT_RESOURCE_COUNTER    "excite_watchdog_counter"
-
-#endif /* __RM9K_WDT_H__ */
diff --git a/include/asm-mips/mach-excite/rm9k_xicap.h b/include/asm-mips/mach-excite/rm9k_xicap.h
deleted file mode 100644
index 009577734a8d..000000000000
--- a/include/asm-mips/mach-excite/rm9k_xicap.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __EXCITE_XICAP_H__
-#define __EXCITE_XICAP_H__
-
-
-/* Resource names */
-#define XICAP_RESOURCE_FIFO_RX          "xicap_fifo_rx"
-#define XICAP_RESOURCE_FIFO_TX          "xicap_fifo_tx"
-#define XICAP_RESOURCE_XDMA             "xicap_xdma"
-#define XICAP_RESOURCE_DMADESC          "xicap_dmadesc"
-#define XICAP_RESOURCE_PKTPROC          "xicap_pktproc"
-#define XICAP_RESOURCE_IRQ              "xicap_irq"
-#define XICAP_RESOURCE_GPI_SLICE        "xicap_gpi_slice"
-#define XICAP_RESOURCE_FIFO_BLK         "xicap_fifo_blocks"
-#define XICAP_RESOURCE_PKT_STREAM       "xicap_pkt_stream"
-
-#endif /* __EXCITE_XICAP_H__ */
diff --git a/include/asm-mips/mach-excite/war.h b/include/asm-mips/mach-excite/war.h
deleted file mode 100644
index 1f82180c1598..000000000000
--- a/include/asm-mips/mach-excite/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_EXCITE_WAR_H
-#define __ASM_MIPS_MACH_EXCITE_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             1
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR 0
-
-#endif /* __ASM_MIPS_MACH_EXCITE_WAR_H */
diff --git a/include/asm-mips/mach-generic/cpu-feature-overrides.h b/include/asm-mips/mach-generic/cpu-feature-overrides.h
deleted file mode 100644
index 7c185bb06f13..000000000000
--- a/include/asm-mips/mach-generic/cpu-feature-overrides.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Ralf Baechle
- */
-#ifndef __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H
-
-/* Intentionally empty file ...  */
-
-#endif /* __ASM_MACH_GENERIC_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-generic/dma-coherence.h b/include/asm-mips/mach-generic/dma-coherence.h
deleted file mode 100644
index 76e04e7feb84..000000000000
--- a/include/asm-mips/mach-generic/dma-coherence.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
- *
- */
-#ifndef __ASM_MACH_GENERIC_DMA_COHERENCE_H
-#define __ASM_MACH_GENERIC_DMA_COHERENCE_H
-
-struct device;
-
-static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
-        size_t size)
-{
-        return virt_to_phys(addr);
-}
-
-static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
-        struct page *page)
-{
-        return page_to_phys(page);
-}
-
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
-{
-        return dma_addr;
-}
-
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
-{
-}
-
-static inline int plat_device_is_coherent(struct device *dev)
-{
-#ifdef CONFIG_DMA_COHERENT
-        return 1;
-#endif
-#ifdef CONFIG_DMA_NONCOHERENT
-        return 0;
-#endif
-}
-
-#endif /* __ASM_MACH_GENERIC_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-generic/floppy.h b/include/asm-mips/mach-generic/floppy.h
deleted file mode 100644
index 001a8ce17c17..000000000000
--- a/include/asm-mips/mach-generic/floppy.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 2003 by Ralf Baechle
- */
-#ifndef __ASM_MACH_GENERIC_FLOPPY_H
-#define __ASM_MACH_GENERIC_FLOPPY_H
-
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/ioport.h>
-#include <linux/sched.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-
-#include <asm/bootinfo.h>
-#include <asm/cachectl.h>
-#include <asm/dma.h>
-#include <asm/floppy.h>
-#include <asm/io.h>
-#include <asm/irq.h>
-#include <asm/pgtable.h>
-
-/*
- * How to access the FDC's registers.
- */
-static inline unsigned char fd_inb(unsigned int port)
-{
-        return inb_p(port);
-}
-
-static inline void fd_outb(unsigned char value, unsigned int port)
-{
-        outb_p(value, port);
-}
-
-/*
- * How to access the floppy DMA functions.
- */
-static inline void fd_enable_dma(void)
-{
-        enable_dma(FLOPPY_DMA);
-}
-
-static inline void fd_disable_dma(void)
-{
-        disable_dma(FLOPPY_DMA);
-}
-
-static inline int fd_request_dma(void)
-{
-        return request_dma(FLOPPY_DMA, "floppy");
-}
-
-static inline void fd_free_dma(void)
-{
-        free_dma(FLOPPY_DMA);
-}
-
-static inline void fd_clear_dma_ff(void)
-{
-        clear_dma_ff(FLOPPY_DMA);
-}
-
-static inline void fd_set_dma_mode(char mode)
-{
-        set_dma_mode(FLOPPY_DMA, mode);
-}
-
-static inline void fd_set_dma_addr(char *addr)
-{
-        set_dma_addr(FLOPPY_DMA, (unsigned long) addr);
-}
-
-static inline void fd_set_dma_count(unsigned int count)
-{
-        set_dma_count(FLOPPY_DMA, count);
-}
-
-static inline int fd_get_dma_residue(void)
-{
-        return get_dma_residue(FLOPPY_DMA);
-}
-
-static inline void fd_enable_irq(void)
-{
-        enable_irq(FLOPPY_IRQ);
-}
-
-static inline void fd_disable_irq(void)
-{
-        disable_irq(FLOPPY_IRQ);
-}
-
-static inline int fd_request_irq(void)
-{
-        return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                           IRQF_DISABLED, "floppy", NULL);
-}
-
-static inline void fd_free_irq(void)
-{
-        free_irq(FLOPPY_IRQ, NULL);
-}
-
-#define fd_free_irq()           free_irq(FLOPPY_IRQ, NULL);
-
-
-static inline unsigned long fd_getfdaddr1(void)
-{
-        return 0x3f0;
-}
-
-static inline unsigned long fd_dma_mem_alloc(unsigned long size)
-{
-        unsigned long mem;
-
-        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
-
-        return mem;
-}
-
-static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
-{
-        free_pages(addr, get_order(size));
-}
-
-static inline unsigned long fd_drive_type(unsigned long n)
-{
-        if (n == 0)
-                return 4;       /* 3,5", 1.44mb */
-
-        return 0;
-}
-
-#endif /* __ASM_MACH_GENERIC_FLOPPY_H */
diff --git a/include/asm-mips/mach-generic/gpio.h b/include/asm-mips/mach-generic/gpio.h
deleted file mode 100644
index b4e70208da64..000000000000
--- a/include/asm-mips/mach-generic/gpio.h
+++ /dev/null
@@ -1,21 +0,0 @@
-#ifndef __ASM_MACH_GENERIC_GPIO_H
-#define __ASM_MACH_GENERIC_GPIO_H
-
-#ifdef CONFIG_GPIOLIB
-#define gpio_get_value  __gpio_get_value
-#define gpio_set_value  __gpio_set_value
-#define gpio_cansleep   __gpio_cansleep
-#else
-int gpio_request(unsigned gpio, const char *label);
-void gpio_free(unsigned gpio);
-int gpio_direction_input(unsigned gpio);
-int gpio_direction_output(unsigned gpio, int value);
-int gpio_get_value(unsigned gpio);
-void gpio_set_value(unsigned gpio, int value);
-#endif
-int gpio_to_irq(unsigned gpio);
-int irq_to_gpio(unsigned irq);
-
-#include <asm-generic/gpio.h>           /* cansleep wrappers */
-
-#endif /* __ASM_MACH_GENERIC_GPIO_H */
diff --git a/include/asm-mips/mach-generic/ide.h b/include/asm-mips/mach-generic/ide.h
deleted file mode 100644
index 73008f7bdc93..000000000000
--- a/include/asm-mips/mach-generic/ide.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994-1996  Linus Torvalds & authors
- *
- * Copied from i386; many of the especially older MIPS or ISA-based platforms
- * are basically identical.  Using this file probably implies i8259 PIC
- * support in a system but the very least interrupt numbers 0 - 15 need to
- * be put aside for legacy devices.
- */
-#ifndef __ASM_MACH_GENERIC_IDE_H
-#define __ASM_MACH_GENERIC_IDE_H
-
-#ifdef __KERNEL__
-
-#include <linux/pci.h>
-#include <linux/stddef.h>
-#include <asm/processor.h>
-
-static __inline__ int ide_probe_legacy(void)
-{
-#ifdef CONFIG_PCI
-        struct pci_dev *dev;
-        /*
-         * This can be called on the ide_setup() path, super-early in
-         * boot.  But the down_read() will enable local interrupts,
-         * which can cause some machines to crash.  So here we detect
-         * and flag that situation and bail out early.
-         */
-        if (no_pci_devices())
-                return 0;
-        dev = pci_get_class(PCI_CLASS_BRIDGE_EISA << 8, NULL);
-        if (dev)
-                goto found;
-        dev = pci_get_class(PCI_CLASS_BRIDGE_ISA << 8, NULL);
-        if (dev)
-                goto found;
-        return 0;
-found:
-        pci_dev_put(dev);
-        return 1;
-#elif defined(CONFIG_EISA) || defined(CONFIG_ISA)
-        return 1;
-#else
-        return 0;
-#endif
-}
-
-/* MIPS port and memory-mapped I/O string operations.  */
-static inline void __ide_flush_prologue(void)
-{
-#ifdef CONFIG_SMP
-        if (cpu_has_dc_aliases)
-                preempt_disable();
-#endif
-}
-
-static inline void __ide_flush_epilogue(void)
-{
-#ifdef CONFIG_SMP
-        if (cpu_has_dc_aliases)
-                preempt_enable();
-#endif
-}
-
-static inline void __ide_flush_dcache_range(unsigned long addr, unsigned long size)
-{
-        if (cpu_has_dc_aliases) {
-                unsigned long end = addr + size;
-
-                while (addr < end) {
-                        local_flush_data_cache_page((void *)addr);
-                        addr += PAGE_SIZE;
-                }
-        }
-}
-
-/*
- * insw() and gang might be called with interrupts disabled, so we can't
- * send IPIs for flushing due to the potencial of deadlocks, see the comment
- * above smp_call_function() in arch/mips/kernel/smp.c.  We work around the
- * problem by disabling preemption so we know we actually perform the flush
- * on the processor that actually has the lines to be flushed which hopefully
- * is even better for performance anyway.
- */
-static inline void __ide_insw(unsigned long port, void *addr,
-        unsigned int count)
-{
-        __ide_flush_prologue();
-        insw(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 2);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_insl(unsigned long port, void *addr, unsigned int count)
-{
-        __ide_flush_prologue();
-        insl(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 4);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_outsw(unsigned long port, const void *addr,
-        unsigned long count)
-{
-        __ide_flush_prologue();
-        outsw(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 2);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_outsl(unsigned long port, const void *addr,
-        unsigned long count)
-{
-        __ide_flush_prologue();
-        outsl(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 4);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_mm_insw(void __iomem *port, void *addr, u32 count)
-{
-        __ide_flush_prologue();
-        readsw(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 2);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_mm_insl(void __iomem *port, void *addr, u32 count)
-{
-        __ide_flush_prologue();
-        readsl(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 4);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_mm_outsw(void __iomem *port, void *addr, u32 count)
-{
-        __ide_flush_prologue();
-        writesw(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 2);
-        __ide_flush_epilogue();
-}
-
-static inline void __ide_mm_outsl(void __iomem * port, void *addr, u32 count)
-{
-        __ide_flush_prologue();
-        writesl(port, addr, count);
-        __ide_flush_dcache_range((unsigned long)addr, count * 4);
-        __ide_flush_epilogue();
-}
-
-/* ide_insw calls insw, not __ide_insw.  Why? */
-#undef insw
-#undef insl
-#undef outsw
-#undef outsl
-#define insw(port, addr, count) __ide_insw(port, addr, count)
-#define insl(port, addr, count) __ide_insl(port, addr, count)
-#define outsw(port, addr, count) __ide_outsw(port, addr, count)
-#define outsl(port, addr, count) __ide_outsl(port, addr, count)
-
-#endif /* __KERNEL__ */
-
-#endif /* __ASM_MACH_GENERIC_IDE_H */
diff --git a/include/asm-mips/mach-generic/ioremap.h b/include/asm-mips/mach-generic/ioremap.h
deleted file mode 100644
index b379938d47f0..000000000000
--- a/include/asm-mips/mach-generic/ioremap.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- *      include/asm-mips/mach-generic/ioremap.h
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MACH_GENERIC_IOREMAP_H
-#define __ASM_MACH_GENERIC_IOREMAP_H
-
-#include <linux/types.h>
-
-/*
- * Allow physical addresses to be fixed up to help peripherals located
- * outside the low 32-bit range -- generic pass-through version.
- */
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-        return phys_addr;
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-        unsigned long flags)
-{
-        return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-        return 0;
-}
-
-#endif /* __ASM_MACH_GENERIC_IOREMAP_H */
diff --git a/include/asm-mips/mach-generic/irq.h b/include/asm-mips/mach-generic/irq.h
deleted file mode 100644
index 70d9a25132c5..000000000000
--- a/include/asm-mips/mach-generic/irq.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-#ifndef __ASM_MACH_GENERIC_IRQ_H
-#define __ASM_MACH_GENERIC_IRQ_H
-
-#ifndef NR_IRQS
-#define NR_IRQS 128
-#endif
-
-#ifdef CONFIG_I8259
-#ifndef I8259A_IRQ_BASE
-#define I8259A_IRQ_BASE 0
-#endif
-#endif
-
-#ifdef CONFIG_IRQ_CPU
-
-#ifndef MIPS_CPU_IRQ_BASE
-#ifdef CONFIG_I8259
-#define MIPS_CPU_IRQ_BASE 16
-#else
-#define MIPS_CPU_IRQ_BASE 0
-#endif /* CONFIG_I8259 */
-#endif
-
-#ifdef CONFIG_IRQ_CPU_RM7K
-#ifndef RM7K_CPU_IRQ_BASE
-#define RM7K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+8)
-#endif
-#endif
-
-#ifdef CONFIG_IRQ_CPU_RM9K
-#ifndef RM9K_CPU_IRQ_BASE
-#define RM9K_CPU_IRQ_BASE (MIPS_CPU_IRQ_BASE+12)
-#endif
-#endif
-
-#endif /* CONFIG_IRQ_CPU */
-
-#endif /* __ASM_MACH_GENERIC_IRQ_H */
diff --git a/include/asm-mips/mach-generic/kernel-entry-init.h b/include/asm-mips/mach-generic/kernel-entry-init.h
deleted file mode 100644
index 7e66505fa574..000000000000
--- a/include/asm-mips/mach-generic/kernel-entry-init.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Embedded Alley Solutions, Inc
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_GENERIC_KERNEL_ENTRY_H
-#define __ASM_MACH_GENERIC_KERNEL_ENTRY_H
-
-/* Intentionally empty macro, used in head.S. Override in
- * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
- */
-.macro  kernel_entry_setup
-.endm
-
-/*
- * Do SMP slave processor setup necessary before we can savely execute C code.
- */
-        .macro  smp_slave_setup
-        .endm
-
-
-#endif /* __ASM_MACH_GENERIC_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-generic/kmalloc.h b/include/asm-mips/mach-generic/kmalloc.h
deleted file mode 100644
index b8e6deba352f..000000000000
--- a/include/asm-mips/mach-generic/kmalloc.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_MACH_GENERIC_KMALLOC_H
-#define __ASM_MACH_GENERIC_KMALLOC_H
-
-
-#ifndef CONFIG_DMA_COHERENT
-/*
- * Total overkill for most systems but need as a safe default.
- * Set this one if any device in the system might do non-coherent DMA.
- */
-#define ARCH_KMALLOC_MINALIGN   128
-#endif
-
-#endif /* __ASM_MACH_GENERIC_KMALLOC_H */
diff --git a/include/asm-mips/mach-generic/mangle-port.h b/include/asm-mips/mach-generic/mangle-port.h
deleted file mode 100644
index f49dc990214b..000000000000
--- a/include/asm-mips/mach-generic/mangle-port.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle
- */
-#ifndef __ASM_MACH_GENERIC_MANGLE_PORT_H
-#define __ASM_MACH_GENERIC_MANGLE_PORT_H
-
-#define __swizzle_addr_b(port)  (port)
-#define __swizzle_addr_w(port)  (port)
-#define __swizzle_addr_l(port)  (port)
-#define __swizzle_addr_q(port)  (port)
-
-/*
- * Sane hardware offers swapping of PCI/ISA I/O space accesses in hardware;
- * less sane hardware forces software to fiddle with this...
- *
- * Regardless, if the host bus endianness mismatches that of PCI/ISA, then
- * you can't have the numerical value of data and byte addresses within
- * multibyte quantities both preserved at the same time.  Hence two
- * variations of functions: non-prefixed ones that preserve the value
- * and prefixed ones that preserve byte addresses.  The latters are
- * typically used for moving raw data between a peripheral and memory (cf.
- * string I/O functions), hence the "__mem_" prefix.
- */
-#if defined(CONFIG_SWAP_IO_SPACE)
-
-# define ioswabb(a, x)          (x)
-# define __mem_ioswabb(a, x)    (x)
-# define ioswabw(a, x)          le16_to_cpu(x)
-# define __mem_ioswabw(a, x)    (x)
-# define ioswabl(a, x)          le32_to_cpu(x)
-# define __mem_ioswabl(a, x)    (x)
-# define ioswabq(a, x)          le64_to_cpu(x)
-# define __mem_ioswabq(a, x)    (x)
-
-#else
-
-# define ioswabb(a, x)          (x)
-# define __mem_ioswabb(a, x)    (x)
-# define ioswabw(a, x)          (x)
-# define __mem_ioswabw(a, x)    cpu_to_le16(x)
-# define ioswabl(a, x)          (x)
-# define __mem_ioswabl(a, x)    cpu_to_le32(x)
-# define ioswabq(a, x)          (x)
-# define __mem_ioswabq(a, x)    cpu_to_le32(x)
-
-#endif
-
-#endif /* __ASM_MACH_GENERIC_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-generic/mc146818rtc.h b/include/asm-mips/mach-generic/mc146818rtc.h
deleted file mode 100644
index 0b9a942f079d..000000000000
--- a/include/asm-mips/mach-generic/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_GENERIC_MC146818RTC_H
-#define __ASM_MACH_GENERIC_MC146818RTC_H
-
-#include <asm/io.h>
-
-#define RTC_PORT(x)     (0x70 + (x))
-#define RTC_IRQ         8
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        outb_p(addr, RTC_PORT(0));
-        return inb_p(RTC_PORT(1));
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        outb_p(addr, RTC_PORT(0));
-        outb_p(data, RTC_PORT(1));
-}
-
-#define RTC_ALWAYS_BCD  1
-
-#ifndef mc146818_decode_year
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
-#endif
-
-#endif /* __ASM_MACH_GENERIC_MC146818RTC_H */
diff --git a/include/asm-mips/mach-generic/spaces.h b/include/asm-mips/mach-generic/spaces.h
deleted file mode 100644
index c9fa4b14968d..000000000000
--- a/include/asm-mips/mach-generic/spaces.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_MACH_GENERIC_SPACES_H
-#define _ASM_MACH_GENERIC_SPACES_H
-
-#include <linux/const.h>
-
-/*
- * This gives the physical RAM offset.
- */
-#ifndef PHYS_OFFSET
-#define PHYS_OFFSET             _AC(0, UL)
-#endif
-
-#ifdef CONFIG_32BIT
-
-#define CAC_BASE                _AC(0x80000000, UL)
-#define IO_BASE                 _AC(0xa0000000, UL)
-#define UNCAC_BASE              _AC(0xa0000000, UL)
-
-#ifndef MAP_BASE
-#define MAP_BASE                _AC(0xc0000000, UL)
-#endif
-
-/*
- * Memory above this physical address will be considered highmem.
- */
-#ifndef HIGHMEM_START
-#define HIGHMEM_START           _AC(0x20000000, UL)
-#endif
-
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-
-#ifndef CAC_BASE
-#ifdef CONFIG_DMA_NONCOHERENT
-#define CAC_BASE                _AC(0x9800000000000000, UL)
-#else
-#define CAC_BASE                _AC(0xa800000000000000, UL)
-#endif
-#endif
-
-#ifndef IO_BASE
-#define IO_BASE                 _AC(0x9000000000000000, UL)
-#endif
-
-#ifndef UNCAC_BASE
-#define UNCAC_BASE              _AC(0x9000000000000000, UL)
-#endif
-
-#ifndef MAP_BASE
-#define MAP_BASE                _AC(0xc000000000000000, UL)
-#endif
-
-/*
- * Memory above this physical address will be considered highmem.
- * Fixme: 59 bits is a fictive number and makes assumptions about processors
- * in the distant future.  Nobody will care for a few years :-)
- */
-#ifndef HIGHMEM_START
-#define HIGHMEM_START           (_AC(1, UL) << _AC(59, UL))
-#endif
-
-#define TO_PHYS(x)              (             ((x) & TO_PHYS_MASK))
-#define TO_CAC(x)               (CAC_BASE   | ((x) & TO_PHYS_MASK))
-#define TO_UNCAC(x)             (UNCAC_BASE | ((x) & TO_PHYS_MASK))
-
-#endif /* CONFIG_64BIT */
-
-/*
- * This handles the memory map.
- */
-#ifndef PAGE_OFFSET
-#define PAGE_OFFSET             (CAC_BASE + PHYS_OFFSET)
-#endif
-
-#endif /* __ASM_MACH_GENERIC_SPACES_H */
diff --git a/include/asm-mips/mach-generic/topology.h b/include/asm-mips/mach-generic/topology.h
deleted file mode 100644
index 5428f333a02c..000000000000
--- a/include/asm-mips/mach-generic/topology.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/topology.h>
diff --git a/include/asm-mips/mach-ip22/cpu-feature-overrides.h b/include/asm-mips/mach-ip22/cpu-feature-overrides.h
deleted file mode 100644
index 9c8735158da1..000000000000
--- a/include/asm-mips/mach-ip22/cpu-feature-overrides.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 07 Ralf Baechle
- */
-#ifndef __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H
-
-/*
- * IP22 with a variety of processors so we can't use defaults for everything.
- */
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-#define cpu_has_fpu             1
-#define cpu_has_32fpr           1
-#define cpu_has_counter         1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_cache_cdex_p    1
-#define cpu_has_prefetch        0
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0               /* Needs to change for R8000 */
-#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
-#define cpu_has_ic_fills_f_dc   0
-
-#define cpu_has_dsp             0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_IP22_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip22/ds1286.h b/include/asm-mips/mach-ip22/ds1286.h
deleted file mode 100644
index f19f1eafbc71..000000000000
--- a/include/asm-mips/mach-ip22/ds1286.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_IP22_DS1286_H
-#define __ASM_MACH_IP22_DS1286_H
-
-#include <asm/sgi/hpc3.h>
-
-#define rtc_read(reg)           (hpc3c0->rtcregs[(reg)] & 0xff)
-#define rtc_write(data, reg)    do { hpc3c0->rtcregs[(reg)] = (data); } while(0)
-
-#endif /* __ASM_MACH_IP22_DS1286_H */
diff --git a/include/asm-mips/mach-ip22/spaces.h b/include/asm-mips/mach-ip22/spaces.h
deleted file mode 100644
index 7f9fa6f66059..000000000000
--- a/include/asm-mips/mach-ip22/spaces.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_MACH_IP22_SPACES_H
-#define _ASM_MACH_IP22_SPACES_H
-
-
-#ifdef CONFIG_64BIT
-
-#define PAGE_OFFSET             0xffffffff80000000UL
-
-#define CAC_BASE                0xffffffff80000000
-#define IO_BASE                 0xffffffffa0000000
-#define UNCAC_BASE              0xffffffffa0000000
-#define MAP_BASE                0xc000000000000000
-
-#endif /* CONFIG_64BIT */
-
-#include <asm/mach-generic/spaces.h>
-
-#endif /* __ASM_MACH_IP22_SPACES_H */
diff --git a/include/asm-mips/mach-ip22/war.h b/include/asm-mips/mach-ip22/war.h
deleted file mode 100644
index a44fa9656a82..000000000000
--- a/include/asm-mips/mach-ip22/war.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP22_WAR_H
-#define __ASM_MIPS_MACH_IP22_WAR_H
-
-/*
- * R4600 CPU modules for the Indy come with both V1.7 and V2.0 processors.
- */
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     1
-#define R4600_V1_HIT_CACHEOP_WAR        1
-#define R4600_V2_HIT_CACHEOP_WAR        1
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_IP22_WAR_H */
diff --git a/include/asm-mips/mach-ip27/cpu-feature-overrides.h b/include/asm-mips/mach-ip27/cpu-feature-overrides.h
deleted file mode 100644
index 7d3112b148d9..000000000000
--- a/include/asm-mips/mach-ip27/cpu-feature-overrides.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 07 Ralf Baechle
- */
-#ifndef __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H
-
-/*
- * IP27 only comes with R10000 family processors all using the same config
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  1
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_4kex            1
-#define cpu_has_3k_cache        0
-#define cpu_has_6k_cache        0
-#define cpu_has_4k_cache        1
-#define cpu_has_8k_cache        0
-#define cpu_has_tx39_cache      0
-
-#define cpu_has_inclusive_pcaches       1
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  64
-#define cpu_scache_line_size()  128
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_IP27_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip27/dma-coherence.h b/include/asm-mips/mach-ip27/dma-coherence.h
deleted file mode 100644
index ed7e6222dc15..000000000000
--- a/include/asm-mips/mach-ip27/dma-coherence.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
- *
- */
-#ifndef __ASM_MACH_IP27_DMA_COHERENCE_H
-#define __ASM_MACH_IP27_DMA_COHERENCE_H
-
-#include <asm/pci/bridge.h>
-
-#define pdev_to_baddr(pdev, addr) \
-        (BRIDGE_CONTROLLER(pdev->bus)->baddr + (addr))
-#define dev_to_baddr(dev, addr) \
-        pdev_to_baddr(to_pci_dev(dev), (addr))
-
-struct device;
-
-static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
-        size_t size)
-{
-        dma_addr_t pa = dev_to_baddr(dev, virt_to_phys(addr));
-
-        return pa;
-}
-
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
-{
-        dma_addr_t pa = dev_to_baddr(dev, page_to_phys(page));
-
-        return pa;
-}
-
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
-{
-        return dma_addr & ~(0xffUL << 56);
-}
-
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
-{
-}
-
-static inline int plat_device_is_coherent(struct device *dev)
-{
-        return 1;               /* IP27 non-cohernet mode is unsupported */
-}
-
-#endif /* __ASM_MACH_IP27_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-ip27/irq.h b/include/asm-mips/mach-ip27/irq.h
deleted file mode 100644
index cf4384bfa846..000000000000
--- a/include/asm-mips/mach-ip27/irq.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999, 2000, 01, 02, 03 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2001 Kanoj Sarcar
- */
-#ifndef __ASM_MACH_IP27_IRQ_H
-#define __ASM_MACH_IP27_IRQ_H
-
-/*
- * A hardwired interrupt number is completly stupid for this system - a
- * large configuration might have thousands if not tenthousands of
- * interrupts.
- */
-#define NR_IRQS 256
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_IP27_IRQ_H */
diff --git a/include/asm-mips/mach-ip27/kernel-entry-init.h b/include/asm-mips/mach-ip27/kernel-entry-init.h
deleted file mode 100644
index 624d66c7f290..000000000000
--- a/include/asm-mips/mach-ip27/kernel-entry-init.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Copyright (C) 2005 Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_IP27_KERNEL_ENTRY_H
-#define __ASM_MACH_IP27_KERNEL_ENTRY_H
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/sn0/hubni.h>
-#include <asm/sn/klkernvars.h>
-
-/*
- * Returns the local nasid into res.
- */
-        .macro GET_NASID_ASM res
-        dli     \res, LOCAL_HUB_ADDR(NI_STATUS_REV_ID)
-        ld      \res, (\res)
-        and     \res, NSRI_NODEID_MASK
-        dsrl    \res, NSRI_NODEID_SHFT
-        .endm
-
-/*
- * Intentionally empty macro, used in head.S. Override in
- * arch/mips/mach-xxx/kernel-entry-init.h when necessary.
- */
-        .macro  kernel_entry_setup
-        GET_NASID_ASM   t1
-        move            t2, t1                  # text and data are here
-        MAPPED_KERNEL_SETUP_TLB
-        .endm
-
-/*
- * Do SMP slave processor setup necessary before we can savely execute C code.
- */
-        .macro  smp_slave_setup
-        GET_NASID_ASM   t1
-        dli     t0, KLDIR_OFFSET + (KLI_KERN_VARS * KLDIR_ENT_SIZE) + \
-                    KLDIR_OFF_POINTER + CAC_BASE
-        dsll    t1, NASID_SHFT
-        or      t0, t0, t1
-        ld      t0, 0(t0)                       # t0 points to kern_vars struct
-        lh      t1, KV_RO_NASID_OFFSET(t0)
-        lh      t2, KV_RW_NASID_OFFSET(t0)
-        MAPPED_KERNEL_SETUP_TLB
-
-        /*
-         * We might not get launched at the address the kernel is linked to,
-         * so we jump there.
-         */
-        PTR_LA  t0, 0f
-        jr      t0
-0:
-        .endm
-
-#endif /* __ASM_MACH_IP27_KERNEL_ENTRY_H */
diff --git a/include/asm-mips/mach-ip27/kmalloc.h b/include/asm-mips/mach-ip27/kmalloc.h
deleted file mode 100644
index 426bd049b2d7..000000000000
--- a/include/asm-mips/mach-ip27/kmalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_MACH_IP27_KMALLOC_H
-#define __ASM_MACH_IP27_KMALLOC_H
-
-/*
- * All happy, no need to define ARCH_KMALLOC_MINALIGN
- */
-
-#endif /* __ASM_MACH_IP27_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip27/mangle-port.h b/include/asm-mips/mach-ip27/mangle-port.h
deleted file mode 100644
index f6e4912ea062..000000000000
--- a/include/asm-mips/mach-ip27/mangle-port.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Ralf Baechle
- */
-#ifndef __ASM_MACH_IP27_MANGLE_PORT_H
-#define __ASM_MACH_IP27_MANGLE_PORT_H
-
-#define __swizzle_addr_b(port)  (port)
-#define __swizzle_addr_w(port)  ((port) ^ 2)
-#define __swizzle_addr_l(port)  (port)
-#define __swizzle_addr_q(port)  (port)
-
-# define ioswabb(a, x)          (x)
-# define __mem_ioswabb(a, x)    (x)
-# define ioswabw(a, x)          (x)
-# define __mem_ioswabw(a, x)    cpu_to_le16(x)
-# define ioswabl(a, x)          (x)
-# define __mem_ioswabl(a, x)    cpu_to_le32(x)
-# define ioswabq(a, x)          (x)
-# define __mem_ioswabq(a, x)    cpu_to_le32(x)
-
-#endif /* __ASM_MACH_IP27_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip27/mmzone.h b/include/asm-mips/mach-ip27/mmzone.h
deleted file mode 100644
index 986a3b9b59a7..000000000000
--- a/include/asm-mips/mach-ip27/mmzone.h
+++ /dev/null
@@ -1,36 +0,0 @@
-#ifndef _ASM_MACH_MMZONE_H
-#define _ASM_MACH_MMZONE_H
-
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-#include <asm/sn/hub.h>
-
-#define pa_to_nid(addr)         NASID_TO_COMPACT_NODEID(NASID_GET(addr))
-
-#define LEVELS_PER_SLICE        128
-
-struct slice_data {
-        unsigned long irq_enable_mask[2];
-        int level_to_irq[LEVELS_PER_SLICE];
-};
-
-struct hub_data {
-        kern_vars_t     kern_vars;
-        DECLARE_BITMAP(h_bigwin_used, HUB_NUM_BIG_WINDOW);
-        cpumask_t       h_cpus;
-        unsigned long slice_map;
-        unsigned long irq_alloc_mask[2];
-        struct slice_data slice[2];
-};
-
-struct node_data {
-        struct pglist_data pglist;
-        struct hub_data hub;
-};
-
-extern struct node_data *__node_data[];
-
-#define NODE_DATA(n)            (&__node_data[(n)]->pglist)
-#define hub_data(n)             (&__node_data[(n)]->hub)
-
-#endif /* _ASM_MACH_MMZONE_H */
diff --git a/include/asm-mips/mach-ip27/spaces.h b/include/asm-mips/mach-ip27/spaces.h
deleted file mode 100644
index b18802a0b17e..000000000000
--- a/include/asm-mips/mach-ip27/spaces.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 99 Ralf Baechle
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999 by Silicon Graphics, Inc.
- */
-#ifndef _ASM_MACH_IP27_SPACES_H
-#define _ASM_MACH_IP27_SPACES_H
-
-/*
- * IP27 uses the R10000's uncached attribute feature.  Attribute 3 selects
- * uncached memory addressing.
- */
-
-#define HSPEC_BASE              0x9000000000000000
-#define IO_BASE                 0x9200000000000000
-#define MSPEC_BASE              0x9400000000000000
-#define UNCAC_BASE              0x9600000000000000
-
-#define TO_MSPEC(x)             (MSPEC_BASE | ((x) & TO_PHYS_MASK))
-#define TO_HSPEC(x)             (HSPEC_BASE | ((x) & TO_PHYS_MASK))
-
-#define HIGHMEM_START           (~0UL)
-
-#include <asm/mach-generic/spaces.h>
-
-#endif /* _ASM_MACH_IP27_SPACES_H */
diff --git a/include/asm-mips/mach-ip27/topology.h b/include/asm-mips/mach-ip27/topology.h
deleted file mode 100644
index 7785bec732f2..000000000000
--- a/include/asm-mips/mach-ip27/topology.h
+++ /dev/null
@@ -1,59 +0,0 @@
-#ifndef _ASM_MACH_TOPOLOGY_H
-#define _ASM_MACH_TOPOLOGY_H    1
-
-#include <asm/sn/hub.h>
-#include <asm/sn/types.h>
-#include <asm/mmzone.h>
-
-struct cpuinfo_ip27 {
-//      cpuid_t         p_cpuid;        /* PROM assigned cpuid */
-        cnodeid_t       p_nodeid;       /* my node ID in compact-id-space */
-        nasid_t         p_nasid;        /* my node ID in numa-as-id-space */
-        unsigned char   p_slice;        /* Physical position on node board */
-#if 0
-        unsigned long           loops_per_sec;
-        unsigned long           ipi_count;
-        unsigned long           irq_attempt[NR_IRQS];
-        unsigned long           smp_local_irq_count;
-        unsigned long           prof_multiplier;
-        unsigned long           prof_counter;
-#endif
-};
-
-extern struct cpuinfo_ip27 sn_cpu_info[NR_CPUS];
-
-#define cpu_to_node(cpu)        (sn_cpu_info[(cpu)].p_nodeid)
-#define parent_node(node)       (node)
-#define node_to_cpumask(node)   (hub_data(node)->h_cpus)
-#define node_to_first_cpu(node) (first_cpu(node_to_cpumask(node)))
-struct pci_bus;
-extern int pcibus_to_node(struct pci_bus *);
-
-#define pcibus_to_cpumask(bus)  (cpu_online_map)
-
-extern unsigned char __node_distances[MAX_COMPACT_NODES][MAX_COMPACT_NODES];
-
-#define node_distance(from, to) (__node_distances[(from)][(to)])
-
-/* sched_domains SD_NODE_INIT for SGI IP27 machines */
-#define SD_NODE_INIT (struct sched_domain) {            \
-        .span                   = CPU_MASK_NONE,        \
-        .parent                 = NULL,                 \
-        .child                  = NULL,                 \
-        .groups                 = NULL,                 \
-        .min_interval           = 8,                    \
-        .max_interval           = 32,                   \
-        .busy_factor            = 32,                   \
-        .imbalance_pct          = 125,                  \
-        .cache_nice_tries       = 1,                    \
-        .flags                  = SD_LOAD_BALANCE       \
-                                | SD_BALANCE_EXEC       \
-                                | SD_WAKE_BALANCE,      \
-        .last_balance           = jiffies,              \
-        .balance_interval       = 1,                    \
-        .nr_balance_failed      = 0,                    \
-}
-
-#include <asm-generic/topology.h>
-
-#endif /* _ASM_MACH_TOPOLOGY_H */
diff --git a/include/asm-mips/mach-ip27/war.h b/include/asm-mips/mach-ip27/war.h
deleted file mode 100644
index e2ddcc9b1fff..000000000000
--- a/include/asm-mips/mach-ip27/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP27_WAR_H
-#define __ASM_MIPS_MACH_IP27_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 1
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_IP27_WAR_H */
diff --git a/include/asm-mips/mach-ip28/cpu-feature-overrides.h b/include/asm-mips/mach-ip28/cpu-feature-overrides.h
deleted file mode 100644
index 9a53b326f848..000000000000
--- a/include/asm-mips/mach-ip28/cpu-feature-overrides.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Ralf Baechle
- * 6/2004       pf
- */
-#ifndef __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H
-
-/*
- * IP28 only comes with R10000 family processors all using the same config
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0 /* see probe_pcache() */
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_icache_snoops_remote_store  1
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-
-#define cpu_has_inclusive_pcaches       1
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  64
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_IP28_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip28/ds1286.h b/include/asm-mips/mach-ip28/ds1286.h
deleted file mode 100644
index 471bb9a33e0f..000000000000
--- a/include/asm-mips/mach-ip28/ds1286.h
+++ /dev/null
@@ -1,4 +0,0 @@
-#ifndef __ASM_MACH_IP28_DS1286_H
-#define __ASM_MACH_IP28_DS1286_H
-#include <asm/mach-ip22/ds1286.h>
-#endif /* __ASM_MACH_IP28_DS1286_H */
diff --git a/include/asm-mips/mach-ip28/spaces.h b/include/asm-mips/mach-ip28/spaces.h
deleted file mode 100644
index 05aabb27e5e7..000000000000
--- a/include/asm-mips/mach-ip28/spaces.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2000, 03, 04 Ralf Baechle
- * Copyright (C) 2000, 2002  Maciej W. Rozycki
- * Copyright (C) 1990, 1999, 2000 Silicon Graphics, Inc.
- * 2004 pf
- */
-#ifndef _ASM_MACH_IP28_SPACES_H
-#define _ASM_MACH_IP28_SPACES_H
-
-#define CAC_BASE                0xa800000000000000
-
-#define HIGHMEM_START           (~0UL)
-
-#define PHYS_OFFSET             _AC(0x20000000, UL)
-
-#include <asm/mach-generic/spaces.h>
-
-#endif /* _ASM_MACH_IP28_SPACES_H */
diff --git a/include/asm-mips/mach-ip28/war.h b/include/asm-mips/mach-ip28/war.h
deleted file mode 100644
index a1baafab486a..000000000000
--- a/include/asm-mips/mach-ip28/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP28_WAR_H
-#define __ASM_MIPS_MACH_IP28_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 1
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_IP28_WAR_H */
diff --git a/include/asm-mips/mach-ip32/cpu-feature-overrides.h b/include/asm-mips/mach-ip32/cpu-feature-overrides.h
deleted file mode 100644
index 6782fccebe8d..000000000000
--- a/include/asm-mips/mach-ip32/cpu-feature-overrides.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Ilya A. Volynets-Evenbakh
- * Copyright (C) 2005, 07 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H
-
-
-/*
- * R5000 has an interesting "restriction":  ll(d)/sc(d)
- * instructions to XKPHYS region simply do uncached bus
- * requests. This breaks all the atomic bitops functions.
- * so, for 64bit IP32 kernel we just don't use ll/sc.
- * This does not affect luserland.
- */
-#if (defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_NEVADA)) && defined(CONFIG_64BIT)
-#define cpu_has_llsc            0
-#else
-#define cpu_has_llsc            1
-#endif
-
-/* Settings which are common for all ip32 CPUs */
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_fpu             1
-#define cpu_has_32fpr           1
-#define cpu_has_counter         1
-#define cpu_has_mips16          0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-#define cpu_has_vtag_icache     0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_has_4k_cache        1
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_IP32_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-ip32/dma-coherence.h b/include/asm-mips/mach-ip32/dma-coherence.h
deleted file mode 100644
index a5511ebb2d53..000000000000
--- a/include/asm-mips/mach-ip32/dma-coherence.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
- *
- */
-#ifndef __ASM_MACH_IP32_DMA_COHERENCE_H
-#define __ASM_MACH_IP32_DMA_COHERENCE_H
-
-#include <asm/ip32/crime.h>
-
-struct device;
-
-/*
- * Few notes.
- * 1. CPU sees memory as two chunks: 0-256M@0x0, and the rest @0x40000000+256M
- * 2. PCI sees memory as one big chunk @0x0 (or we could use 0x40000000 for
- *    native-endian)
- * 3. All other devices see memory as one big chunk at 0x40000000
- * 4. Non-PCI devices will pass NULL as struct device*
- *
- * Thus we translate differently, depending on device.
- */
-
-#define RAM_OFFSET_MASK 0x3fffffffUL
-
-static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
-        size_t size)
-{
-        dma_addr_t pa = virt_to_phys(addr) & RAM_OFFSET_MASK;
-
-        if (dev == NULL)
-                pa += CRIME_HI_MEM_BASE;
-
-        return pa;
-}
-
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
-{
-        dma_addr_t pa;
-
-        pa = page_to_phys(page) & RAM_OFFSET_MASK;
-
-        if (dev == NULL)
-                pa += CRIME_HI_MEM_BASE;
-
-        return pa;
-}
-
-/* This is almost certainly wrong but it's what dma-ip32.c used to use  */
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
-{
-        unsigned long addr = dma_addr & RAM_OFFSET_MASK;
-
-        if (dma_addr >= 256*1024*1024)
-                addr += CRIME_HI_MEM_BASE;
-
-        return addr;
-}
-
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
-{
-}
-
-static inline int plat_device_is_coherent(struct device *dev)
-{
-        return 0;               /* IP32 is non-cohernet */
-}
-
-#endif /* __ASM_MACH_IP32_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-ip32/kmalloc.h b/include/asm-mips/mach-ip32/kmalloc.h
deleted file mode 100644
index b1e0be60f720..000000000000
--- a/include/asm-mips/mach-ip32/kmalloc.h
+++ /dev/null
@@ -1,11 +0,0 @@
-#ifndef __ASM_MACH_IP32_KMALLOC_H
-#define __ASM_MACH_IP32_KMALLOC_H
-
-
-#if defined(CONFIG_CPU_R5000) || defined(CONFIG_CPU_RM7000)
-#define ARCH_KMALLOC_MINALIGN   32
-#else
-#define ARCH_KMALLOC_MINALIGN   128
-#endif
-
-#endif /* __ASM_MACH_IP32_KMALLOC_H */
diff --git a/include/asm-mips/mach-ip32/mangle-port.h b/include/asm-mips/mach-ip32/mangle-port.h
deleted file mode 100644
index f1d0f1756a9f..000000000000
--- a/include/asm-mips/mach-ip32/mangle-port.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Ladislav Michl
- * Copyright (C) 2004 Ralf Baechle
- */
-#ifndef __ASM_MACH_IP32_MANGLE_PORT_H
-#define __ASM_MACH_IP32_MANGLE_PORT_H
-
-#define __swizzle_addr_b(port)  ((port) ^ 3)
-#define __swizzle_addr_w(port)  ((port) ^ 2)
-#define __swizzle_addr_l(port)  (port)
-#define __swizzle_addr_q(port)  (port)
-
-# define ioswabb(a, x)          (x)
-# define __mem_ioswabb(a, x)    (x)
-# define ioswabw(a, x)          (x)
-# define __mem_ioswabw(a, x)    cpu_to_le16(x)
-# define ioswabl(a, x)          (x)
-# define __mem_ioswabl(a, x)    cpu_to_le32(x)
-# define ioswabq(a, x)          (x)
-# define __mem_ioswabq(a, x)    cpu_to_le32(x)
-
-#endif /* __ASM_MACH_IP32_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-ip32/mc146818rtc.h b/include/asm-mips/mach-ip32/mc146818rtc.h
deleted file mode 100644
index c28ba8d84076..000000000000
--- a/include/asm-mips/mach-ip32/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- * Copyright (C) 2000 Harald Koerfgen
- *
- * RTC routines for IP32 style attached Dallas chip.
- */
-#ifndef __ASM_MACH_IP32_MC146818RTC_H
-#define __ASM_MACH_IP32_MC146818RTC_H
-
-#include <asm/ip32/mace.h>
-
-#define RTC_PORT(x)     (0x70 + (x))
-
-static unsigned char CMOS_READ(unsigned long addr)
-{
-        return mace->isa.rtc[addr << 8];
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        mace->isa.rtc[addr << 8] = data;
-}
-
-/*
- * FIXME: Do it right. For now just assume that noone lives in 20th century
- * and no O2 user in 22th century ;-)
- */
-#define mc146818_decode_year(year) ((year) + 2000)
-
-#define RTC_ALWAYS_BCD  0
-
-#endif /* __ASM_MACH_IP32_MC146818RTC_H */
diff --git a/include/asm-mips/mach-ip32/war.h b/include/asm-mips/mach-ip32/war.h
deleted file mode 100644
index d194056dcd7a..000000000000
--- a/include/asm-mips/mach-ip32/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_IP32_WAR_H
-#define __ASM_MIPS_MACH_IP32_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_IP32_WAR_H */
diff --git a/include/asm-mips/mach-jazz/dma-coherence.h b/include/asm-mips/mach-jazz/dma-coherence.h
deleted file mode 100644
index d66979a124a8..000000000000
--- a/include/asm-mips/mach-jazz/dma-coherence.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006  Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MACH_JAZZ_DMA_COHERENCE_H
-#define __ASM_MACH_JAZZ_DMA_COHERENCE_H
-
-#include <asm/jazzdma.h>
-
-struct device;
-
-static dma_addr_t plat_map_dma_mem(struct device *dev, void *addr, size_t size)
-{
-        return vdma_alloc(virt_to_phys(addr), size);
-}
-
-static dma_addr_t plat_map_dma_mem_page(struct device *dev, struct page *page)
-{
-        return vdma_alloc(page_to_phys(page), PAGE_SIZE);
-}
-
-static unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
-{
-        return vdma_log2phys(dma_addr);
-}
-
-static void plat_unmap_dma_mem(dma_addr_t dma_addr)
-{
-        vdma_free(dma_addr);
-}
-
-static inline int plat_device_is_coherent(struct device *dev)
-{
-        return 0;
-}
-
-#endif /* __ASM_MACH_JAZZ_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-jazz/floppy.h b/include/asm-mips/mach-jazz/floppy.h
deleted file mode 100644
index 56e9ca6ae426..000000000000
--- a/include/asm-mips/mach-jazz/floppy.h
+++ /dev/null
@@ -1,135 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2003 by Ralf Baechle
- */
-#ifndef __ASM_MACH_JAZZ_FLOPPY_H
-#define __ASM_MACH_JAZZ_FLOPPY_H
-
-#include <linux/delay.h>
-#include <linux/init.h>
-#include <linux/linkage.h>
-#include <linux/types.h>
-#include <linux/mm.h>
-#include <asm/addrspace.h>
-#include <asm/jazz.h>
-#include <asm/jazzdma.h>
-#include <asm/pgtable.h>
-
-static inline unsigned char fd_inb(unsigned int port)
-{
-        unsigned char c;
-
-        c = *(volatile unsigned char *) port;
-        udelay(1);
-
-        return c;
-}
-
-static inline void fd_outb(unsigned char value, unsigned int port)
-{
-        *(volatile unsigned char *) port = value;
-}
-
-/*
- * How to access the floppy DMA functions.
- */
-static inline void fd_enable_dma(void)
-{
-        vdma_enable(JAZZ_FLOPPY_DMA);
-}
-
-static inline void fd_disable_dma(void)
-{
-        vdma_disable(JAZZ_FLOPPY_DMA);
-}
-
-static inline int fd_request_dma(void)
-{
-        return 0;
-}
-
-static inline void fd_free_dma(void)
-{
-}
-
-static inline void fd_clear_dma_ff(void)
-{
-}
-
-static inline void fd_set_dma_mode(char mode)
-{
-        vdma_set_mode(JAZZ_FLOPPY_DMA, mode);
-}
-
-static inline void fd_set_dma_addr(char *a)
-{
-        vdma_set_addr(JAZZ_FLOPPY_DMA, vdma_phys2log(CPHYSADDR((unsigned long)a)));
-}
-
-static inline void fd_set_dma_count(unsigned int count)
-{
-        vdma_set_count(JAZZ_FLOPPY_DMA, count);
-}
-
-static inline int fd_get_dma_residue(void)
-{
-        return vdma_get_residue(JAZZ_FLOPPY_DMA);
-}
-
-static inline void fd_enable_irq(void)
-{
-}
-
-static inline void fd_disable_irq(void)
-{
-}
-
-static inline int fd_request_irq(void)
-{
-        return request_irq(FLOPPY_IRQ, floppy_interrupt,
-                           IRQF_DISABLED, "floppy", NULL);
-}
-
-static inline void fd_free_irq(void)
-{
-        free_irq(FLOPPY_IRQ, NULL);
-}
-
-static inline unsigned long fd_getfdaddr1(void)
-{
-        return JAZZ_FDC_BASE;
-}
-
-static inline unsigned long fd_dma_mem_alloc(unsigned long size)
-{
-        unsigned long mem;
-
-        mem = __get_dma_pages(GFP_KERNEL, get_order(size));
-        if(!mem)
-                return 0;
-        vdma_alloc(CPHYSADDR(mem), size);       /* XXX error checking */
-
-        return mem;
-}
-
-static inline void fd_dma_mem_free(unsigned long addr, unsigned long size)
-{
-        vdma_free(vdma_phys2log(CPHYSADDR(addr)));
-        free_pages(addr, get_order(size));
-}
-
-static inline unsigned long fd_drive_type(unsigned long n)
-{
-        /* XXX This is wrong for machines with ED 2.88mb disk drives like the
-           Olivetti M700.  Anyway, we should suck this from the ARC
-           firmware.  */
-        if (n == 0)
-                return 4;       /* 3,5", 1.44mb */
-
-        return 0;
-}
-
-#endif /* __ASM_MACH_JAZZ_FLOPPY_H */
diff --git a/include/asm-mips/mach-jazz/mc146818rtc.h b/include/asm-mips/mach-jazz/mc146818rtc.h
deleted file mode 100644
index 987f727afe25..000000000000
--- a/include/asm-mips/mach-jazz/mc146818rtc.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- * Copyright (C) 2007 Thomas Bogendoerfer
- *
- * RTC routines for Jazz style attached Dallas chip.
- */
-#ifndef __ASM_MACH_JAZZ_MC146818RTC_H
-#define __ASM_MACH_JAZZ_MC146818RTC_H
-
-#include <linux/delay.h>
-
-#include <asm/io.h>
-#include <asm/jazz.h>
-
-#define RTC_PORT(x)     (0x70 + (x))
-#define RTC_IRQ         8
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        outb_p(addr, RTC_PORT(0));
-        return *(volatile char *)JAZZ_RTC_BASE;
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        outb_p(addr, RTC_PORT(0));
-        *(volatile char *)JAZZ_RTC_BASE = data;
-}
-
-#define RTC_ALWAYS_BCD  0
-
-#define mc146818_decode_year(year) ((year) + 1980)
-
-#endif /* __ASM_MACH_JAZZ_MC146818RTC_H */
diff --git a/include/asm-mips/mach-jazz/war.h b/include/asm-mips/mach-jazz/war.h
deleted file mode 100644
index 6158ee861bfd..000000000000
--- a/include/asm-mips/mach-jazz/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_JAZZ_WAR_H
-#define __ASM_MIPS_MACH_JAZZ_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_JAZZ_WAR_H */
diff --git a/include/asm-mips/mach-lasat/irq.h b/include/asm-mips/mach-lasat/irq.h
deleted file mode 100644
index 3a282419d5f9..000000000000
--- a/include/asm-mips/mach-lasat/irq.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _ASM_MACH_LASAT_IRQ_H
-#define _ASM_MACH_LASAT_IRQ_H
-
-#define LASAT_CASCADE_IRQ       (MIPS_CPU_IRQ_BASE + 2)
-
-#define LASAT_IRQ_BASE          8
-#define LASAT_IRQ_END           23
-
-#define NR_IRQS                 24
-
-#include_next <irq.h>
-
-#endif /* _ASM_MACH_LASAT_IRQ_H */
diff --git a/include/asm-mips/mach-lasat/mach-gt64120.h b/include/asm-mips/mach-lasat/mach-gt64120.h
deleted file mode 100644
index 1a9ad45cc135..000000000000
--- a/include/asm-mips/mach-lasat/mach-gt64120.h
+++ /dev/null
@@ -1,27 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef _ASM_GT64120_LASAT_GT64120_DEP_H
-#define _ASM_GT64120_LASAT_GT64120_DEP_H
-
-/*
- *   GT64120 config space base address on Lasat 100
- */
-#define GT64120_BASE    (KSEG1ADDR(0x14000000))
-
-/*
- *   PCI Bus allocation
- *
- *   (Guessing ...)
- */
-#define GT_PCI_MEM_BASE 0x12000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x10000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-#define GT_ISA_IO_BASE  PCI_IO_BASE
-
-#endif /* _ASM_GT64120_LASAT_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-lasat/war.h b/include/asm-mips/mach-lasat/war.h
deleted file mode 100644
index bb1e0325c9be..000000000000
--- a/include/asm-mips/mach-lasat/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_LASAT_WAR_H
-#define __ASM_MIPS_MACH_LASAT_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_LASAT_WAR_H */
diff --git a/include/asm-mips/mach-lemote/dma-coherence.h b/include/asm-mips/mach-lemote/dma-coherence.h
deleted file mode 100644
index 7e914777ebc4..000000000000
--- a/include/asm-mips/mach-lemote/dma-coherence.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2006, 07  Ralf Baechle <ralf@linux-mips.org>
- * Copyright (C) 2007 Lemote, Inc. & Institute of Computing Technology
- * Author: Fuxin Zhang, zhangfx@lemote.com
- *
- */
-#ifndef __ASM_MACH_LEMOTE_DMA_COHERENCE_H
-#define __ASM_MACH_LEMOTE_DMA_COHERENCE_H
-
-struct device;
-
-static inline dma_addr_t plat_map_dma_mem(struct device *dev, void *addr,
-                                          size_t size)
-{
-        return virt_to_phys(addr) | 0x80000000;
-}
-
-static inline dma_addr_t plat_map_dma_mem_page(struct device *dev,
-                                               struct page *page)
-{
-        return page_to_phys(page) | 0x80000000;
-}
-
-static inline unsigned long plat_dma_addr_to_phys(dma_addr_t dma_addr)
-{
-        return dma_addr & 0x7fffffff;
-}
-
-static inline void plat_unmap_dma_mem(dma_addr_t dma_addr)
-{
-}
-
-static inline int plat_device_is_coherent(struct device *dev)
-{
-        return 0;
-}
-
-#endif /* __ASM_MACH_LEMOTE_DMA_COHERENCE_H */
diff --git a/include/asm-mips/mach-lemote/mc146818rtc.h b/include/asm-mips/mach-lemote/mc146818rtc.h
deleted file mode 100644
index ed5147e11085..000000000000
--- a/include/asm-mips/mach-lemote/mc146818rtc.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03, 07 by Ralf Baechle (ralf@linux-mips.org)
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_LEMOTE_MC146818RTC_H
-#define __ASM_MACH_LEMOTE_MC146818RTC_H
-
-#include <linux/io.h>
-
-#define RTC_PORT(x)     (0x70 + (x))
-#define RTC_IRQ         8
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        outb_p(addr, RTC_PORT(0));
-        return inb_p(RTC_PORT(1));
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        outb_p(addr, RTC_PORT(0));
-        outb_p(data, RTC_PORT(1));
-}
-
-#define RTC_ALWAYS_BCD  0
-
-#ifndef mc146818_decode_year
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1970)
-#endif
-
-#endif /* __ASM_MACH_LEMOTE_MC146818RTC_H */
diff --git a/include/asm-mips/mach-lemote/war.h b/include/asm-mips/mach-lemote/war.h
deleted file mode 100644
index 05f89e0f2a11..000000000000
--- a/include/asm-mips/mach-lemote/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_LEMOTE_WAR_H
-#define __ASM_MIPS_MACH_LEMOTE_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_LEMOTE_WAR_H */
diff --git a/include/asm-mips/mach-malta/cpu-feature-overrides.h b/include/asm-mips/mach-malta/cpu-feature-overrides.h
deleted file mode 100644
index 7f3e3f9bd23a..000000000000
--- a/include/asm-mips/mach-malta/cpu-feature-overrides.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Chris Dearman
- * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H
-
-
-/*
- * CPU feature overrides for MIPS boards
- */
-#ifdef CONFIG_CPU_MIPS32
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-/* #define cpu_has_fpu          ? */
-/* #define cpu_has_32fpr        ? */
-#define cpu_has_counter         1
-/* #define cpu_has_watch        ? */
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch     ? */
-#define cpu_has_mcheck          1
-/* #define cpu_has_ejtag        ? */
-#ifdef CONFIG_CPU_HAS_LLSC
-#define cpu_has_llsc            1
-#else
-#define cpu_has_llsc            0
-#endif
-/* #define cpu_has_vtag_icache  ? */
-/* #define cpu_has_dc_aliases   ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex         0
-/* #define cpu_has_64bits       ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#define cpu_icache_snoops_remote_store 1
-#endif
-
-#ifdef CONFIG_CPU_MIPS64
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-/* #define cpu_has_fpu          ? */
-/* #define cpu_has_32fpr        ? */
-#define cpu_has_counter         1
-/* #define cpu_has_watch        ? */
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch     ? */
-#define cpu_has_mcheck          1
-/* #define cpu_has_ejtag        ? */
-#define cpu_has_llsc            1
-/* #define cpu_has_vtag_icache  ? */
-/* #define cpu_has_dc_aliases   ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex         0
-/* #define cpu_has_64bits       ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#define cpu_icache_snoops_remote_store 1
-#endif
-
-#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-malta/irq.h b/include/asm-mips/mach-malta/irq.h
deleted file mode 100644
index 9b9da26683c2..000000000000
--- a/include/asm-mips/mach-malta/irq.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_MACH_MIPS_IRQ_H
-#define __ASM_MACH_MIPS_IRQ_H
-
-
-#define NR_IRQS 256
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_MIPS_IRQ_H */
diff --git a/include/asm-mips/mach-malta/kernel-entry-init.h b/include/asm-mips/mach-malta/kernel-entry-init.h
deleted file mode 100644
index 0b793e7bf67e..000000000000
--- a/include/asm-mips/mach-malta/kernel-entry-init.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Chris Dearman (chris@mips.com)
- * Copyright (C) 2007 Mips Technologies, Inc.
- */
-#ifndef __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
-#define __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H
-
-        .macro  kernel_entry_setup
-#ifdef CONFIG_MIPS_MT_SMTC
-        mfc0    t0, CP0_CONFIG
-        bgez    t0, 9f
-        mfc0    t0, CP0_CONFIG, 1
-        bgez    t0, 9f
-        mfc0    t0, CP0_CONFIG, 2
-        bgez    t0, 9f
-        mfc0    t0, CP0_CONFIG, 3
-        and     t0, 1<<2
-        bnez    t0, 0f
-9:
-        /* Assume we came from YAMON... */
-        PTR_LA  v0, 0x9fc00534  /* YAMON print */
-        lw      v0, (v0)
-        move    a0, zero
-        PTR_LA  a1, nonmt_processor
-        jal     v0
-
-        PTR_LA  v0, 0x9fc00520  /* YAMON exit */
-        lw      v0, (v0)
-        li      a0, 1
-        jal     v0
-
-1:      b       1b
-
-        __INITDATA
-nonmt_processor:
-        .asciz  "SMTC kernel requires the MT ASE to run\n"
-        __FINIT
-0:
-#endif
-        .endm
-
-/*
- * Do SMP slave processor setup necessary before we can safely execute C code.
- */
-        .macro  smp_slave_setup
-        .endm
-
-#endif /* __ASM_MACH_MIPS_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-malta/mach-gt64120.h b/include/asm-mips/mach-malta/mach-gt64120.h
deleted file mode 100644
index 0f863148f3b6..000000000000
--- a/include/asm-mips/mach-malta/mach-gt64120.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- *  This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- *  The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef _ASM_MACH_MIPS_MACH_GT64120_DEP_H
-#define _ASM_MACH_MIPS_MACH_GT64120_DEP_H
-
-#define MIPS_GT_BASE    0x1be00000
-
-extern unsigned long _pcictrl_gt64120;
-/*
- *   GT64120 config space base address
- */
-#define GT64120_BASE    _pcictrl_gt64120
-
-#endif /* _ASM_MACH_MIPS_MACH_GT64120_DEP_H */
diff --git a/include/asm-mips/mach-malta/mc146818rtc.h b/include/asm-mips/mach-malta/mc146818rtc.h
deleted file mode 100644
index ea612f37f614..000000000000
--- a/include/asm-mips/mach-malta/mc146818rtc.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 1999,2000 MIPS Technologies, Inc.  All rights reserved.
- * Copyright (C) 2003 by Ralf Baechle
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * RTC routines for Malta style attached PIIX4 device, which contains a
- * Motorola MC146818A-compatible Real Time Clock.
- */
-#ifndef __ASM_MACH_MALTA_MC146818RTC_H
-#define __ASM_MACH_MALTA_MC146818RTC_H
-
-#include <asm/io.h>
-#include <asm/mips-boards/generic.h>
-#include <asm/mips-boards/malta.h>
-
-#define RTC_PORT(x)     (0x70 + (x))
-#define RTC_IRQ         8
-
-static inline unsigned char CMOS_READ(unsigned long addr)
-{
-        outb(addr, MALTA_RTC_ADR_REG);
-        return inb(MALTA_RTC_DAT_REG);
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long addr)
-{
-        outb(addr, MALTA_RTC_ADR_REG);
-        outb(data, MALTA_RTC_DAT_REG);
-}
-
-#define RTC_ALWAYS_BCD  0
-
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
-
-#endif /* __ASM_MACH_MALTA_MC146818RTC_H */
diff --git a/include/asm-mips/mach-malta/war.h b/include/asm-mips/mach-malta/war.h
deleted file mode 100644
index 7c6931d5f45f..000000000000
--- a/include/asm-mips/mach-malta/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        1
-#define MIPS_CACHE_SYNC_WAR             1
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h b/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
deleted file mode 100644
index 779b02205737..000000000000
--- a/include/asm-mips/mach-mipssim/cpu-feature-overrides.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 2004 Chris Dearman
- */
-#ifndef __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_SIM_CPU_FEATURE_OVERRIDES_H
-
-
-/*
- * CPU feature overrides for MIPS boards
- */
-#ifdef CONFIG_CPU_MIPS32
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-#define cpu_has_fpu             0
-/* #define cpu_has_32fpr        ? */
-#define cpu_has_counter         1
-/* #define cpu_has_watch        ? */
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch     ? */
-#define cpu_has_mcheck          1
-/* #define cpu_has_ejtag        ? */
-#define cpu_has_llsc            1
-/* #define cpu_has_vtag_icache  ? */
-/* #define cpu_has_dc_aliases   ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex         0
-/* #define cpu_has_64bits       ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#endif
-
-#ifdef CONFIG_CPU_MIPS64
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-/* #define cpu_has_fpu          ? */
-/* #define cpu_has_32fpr        ? */
-#define cpu_has_counter         1
-/* #define cpu_has_watch        ? */
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-/* #define cpu_has_cache_cdex_p ? */
-/* #define cpu_has_cache_cdex_s ? */
-/* #define cpu_has_prefetch     ? */
-#define cpu_has_mcheck          1
-/* #define cpu_has_ejtag        ? */
-#define cpu_has_llsc            1
-/* #define cpu_has_vtag_icache  ? */
-/* #define cpu_has_dc_aliases   ? */
-/* #define cpu_has_ic_fills_f_dc ? */
-#define cpu_has_nofpuex         0
-/* #define cpu_has_64bits       ? */
-/* #define cpu_has_64bit_zero_reg ? */
-/* #define cpu_has_inclusive_pcaches ? */
-#endif
-
-#endif /* __ASM_MACH_MIPS_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-mipssim/war.h b/include/asm-mips/mach-mipssim/war.h
deleted file mode 100644
index c8a74a3515e0..000000000000
--- a/include/asm-mips/mach-mipssim/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPSSIM_WAR_H
-#define __ASM_MIPS_MACH_MIPSSIM_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_MIPSSIM_WAR_H */
diff --git a/include/asm-mips/mach-pb1x00/mc146818rtc.h b/include/asm-mips/mach-pb1x00/mc146818rtc.h
deleted file mode 100644
index 622c58710e5b..000000000000
--- a/include/asm-mips/mach-pb1x00/mc146818rtc.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 2001, 03 by Ralf Baechle
- *
- * RTC routines for PC style attached Dallas chip.
- */
-#ifndef __ASM_MACH_AU1XX_MC146818RTC_H
-#define __ASM_MACH_AU1XX_MC146818RTC_H
-
-#include <asm/io.h>
-#include <asm/mach-au1x00/au1000.h>
-
-#define RTC_PORT(x)     (0x0c000000 + (x))
-#define RTC_IRQ         8
-#define PB1500_RTC_ADDR 0x0c000000
-
-static inline unsigned char CMOS_READ(unsigned long offset)
-{
-        offset <<= 2;
-        return (u8)(au_readl(offset + PB1500_RTC_ADDR) & 0xff);
-}
-
-static inline void CMOS_WRITE(unsigned char data, unsigned long offset)
-{
-        offset <<= 2;
-        au_writel(data, offset + PB1500_RTC_ADDR);
-}
-
-#define RTC_ALWAYS_BCD  1
-
-#endif /* __ASM_MACH_AU1XX_MC146818RTC_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1000.h b/include/asm-mips/mach-pb1x00/pb1000.h
deleted file mode 100644
index 6d1ff9060e44..000000000000
--- a/include/asm-mips/mach-pb1x00/pb1000.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Alchemy Semi Pb1000 Referrence Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1000_H
-#define __ASM_PB1000_H
-
-/* PCMCIA PB1000 specific defines */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-#define PB1000_PCR              0xBE000000
-#  define PCR_SLOT_0_VPP0       (1 << 0)
-#  define PCR_SLOT_0_VPP1       (1 << 1)
-#  define PCR_SLOT_0_VCC0       (1 << 2)
-#  define PCR_SLOT_0_VCC1       (1 << 3)
-#  define PCR_SLOT_0_RST        (1 << 4)
-#  define PCR_SLOT_1_VPP0       (1 << 8)
-#  define PCR_SLOT_1_VPP1       (1 << 9)
-#  define PCR_SLOT_1_VCC0       (1 << 10)
-#  define PCR_SLOT_1_VCC1       (1 << 11)
-#  define PCR_SLOT_1_RST        (1 << 12)
-
-#define PB1000_MDR              0xBE000004
-#  define MDR_PI                (1 << 5)        /* PCMCIA int latch  */
-#  define MDR_EPI               (1 << 14)       /* enable PCMCIA int */
-#  define MDR_CPI               (1 << 15)       /* clear  PCMCIA int  */
-
-#define PB1000_ACR1             0xBE000008
-#  define ACR1_SLOT_0_CD1       (1 << 0)        /* card detect 1        */
-#  define ACR1_SLOT_0_CD2       (1 << 1)        /* card detect 2        */
-#  define ACR1_SLOT_0_READY     (1 << 2)        /* ready                */
-#  define ACR1_SLOT_0_STATUS    (1 << 3)        /* status change        */
-#  define ACR1_SLOT_0_VS1       (1 << 4)        /* voltage sense 1      */
-#  define ACR1_SLOT_0_VS2       (1 << 5)        /* voltage sense 2      */
-#  define ACR1_SLOT_0_INPACK    (1 << 6)        /* inpack pin status    */
-#  define ACR1_SLOT_1_CD1       (1 << 8)        /* card detect 1        */
-#  define ACR1_SLOT_1_CD2       (1 << 9)        /* card detect 2        */
-#  define ACR1_SLOT_1_READY     (1 << 10)       /* ready                */
-#  define ACR1_SLOT_1_STATUS    (1 << 11)       /* status change        */
-#  define ACR1_SLOT_1_VS1       (1 << 12)       /* voltage sense 1      */
-#  define ACR1_SLOT_1_VS2       (1 << 13)       /* voltage sense 2      */
-#  define ACR1_SLOT_1_INPACK    (1 << 14)       /* inpack pin status    */
-
-#define CPLD_AUX0               0xBE00000C
-#define CPLD_AUX1               0xBE000010
-#define CPLD_AUX2               0xBE000014
-
-/* Voltage levels */
-
-/* VPPEN1 - VPPEN0 */
-#define VPP_GND ((0 << 1) | (0 << 0))
-#define VPP_5V  ((1 << 1) | (0 << 0))
-#define VPP_3V  ((0 << 1) | (1 << 0))
-#define VPP_12V ((0 << 1) | (1 << 0))
-#define VPP_HIZ ((1 << 1) | (1 << 0))
-
-/* VCCEN1 - VCCEN0 */
-#define VCC_3V  ((0 << 1) | (1 << 0))
-#define VCC_5V  ((1 << 1) | (0 << 0))
-#define VCC_HIZ ((0 << 1) | (0 << 0))
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-#endif /* __ASM_PB1000_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1100.h b/include/asm-mips/mach-pb1x00/pb1100.h
deleted file mode 100644
index b1a60f1cbd02..000000000000
--- a/include/asm-mips/mach-pb1x00/pb1100.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * Alchemy Semi Pb1100 Referrence Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1100_H
-#define __ASM_PB1100_H
-
-#define PB1100_IDENT            0xAE000000
-#define BOARD_STATUS_REG        0xAE000004
-#  define PB1100_ROM_SEL        (1 << 15)
-#  define PB1100_ROM_SIZ        (1 << 14)
-#  define PB1100_SWAP_BOOT      (1 << 13)
-#  define PB1100_FLASH_WP       (1 << 12)
-#  define PB1100_ROM_H_STS      (1 << 11)
-#  define PB1100_ROM_L_STS      (1 << 10)
-#  define PB1100_FLASH_H_STS    (1 << 9)
-#  define PB1100_FLASH_L_STS    (1 << 8)
-#  define PB1100_SRAM_SIZ       (1 << 7)
-#  define PB1100_TSC_BUSY       (1 << 6)
-#  define PB1100_PCMCIA_VS_MASK (3 << 4)
-#  define PB1100_RS232_CD       (1 << 3)
-#  define PB1100_RS232_CTS      (1 << 2)
-#  define PB1100_RS232_DSR      (1 << 1)
-#  define PB1100_RS232_RI       (1 << 0)
-
-#define PB1100_IRDA_RS232       0xAE00000C
-#  define PB1100_IRDA_FULL      (0 << 14)       /* full power           */
-#  define PB1100_IRDA_SHUTDOWN  (1 << 14)
-#  define PB1100_IRDA_TT        (2 << 14)       /* 2/3 power            */
-#  define PB1100_IRDA_OT        (3 << 14)       /* 1/3 power            */
-#  define PB1100_IRDA_FIR       (1 << 13)
-
-#define PCMCIA_BOARD_REG        0xAE000010
-#  define PB1100_SD_WP1_RO      (1 << 15)       /* read only            */
-#  define PB1100_SD_WP0_RO      (1 << 14)       /* read only            */
-#  define PB1100_SD_PWR1        (1 << 11)       /* applies power to SD1 */
-#  define PB1100_SD_PWR0        (1 << 10)       /* applies power to SD0 */
-#  define PB1100_SEL_SD_CONN1   (1 << 9)
-#  define PB1100_SEL_SD_CONN0   (1 << 8)
-#  define PC_DEASSERT_RST       (1 << 7)
-#  define PC_DRV_EN             (1 << 4)
-
-#define PB1100_G_CONTROL        0xAE000014      /* graphics control     */
-
-#define PB1100_RST_VDDI         0xAE00001C
-#  define PB1100_SOFT_RESET     (1 << 15)       /* clear to reset the board */
-#  define PB1100_VDDI_MASK      0x1F
-
-#define PB1100_LEDS             0xAE000018
-
-/*
- * 11:8 is 4 discreet LEDs. Clearing a bit illuminates the LED.
- * 7:0  is the LED Display's decimal points.
- */
-#define PB1100_HEX_LED          0xAE000018
-
-/* PCMCIA Pb1100 specific defines */
-#define PCMCIA_MAX_SOCK  0
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
-
-#endif /* __ASM_PB1100_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
deleted file mode 100644
index c8618df88cb5..000000000000
--- a/include/asm-mips/mach-pb1x00/pb1200.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*
- * AMD Alchemy Pb1200 Referrence Board
- * Board Registers defines.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1200_H
-#define __ASM_PB1200_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC1_TX
-#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC1_RX
-
-/*
- * SPI and SMB are muxed on the Pb1200 board.
- * Refer to board documentation.
- */
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC0_BASE_ADDR
-/*
- * AC97 and I2S are muxed on the Pb1200 board.
- * Refer to board documentation.
- */
-#define AC97_PSC_BASE       PSC1_BASE_ADDR
-#define I2S_PSC_BASE            PSC1_BASE_ADDR
-
-#define BCSR_KSEG1_ADDR 0xAD800000
-
-typedef volatile struct
-{
-        /*00*/  u16 whoami;
-                u16 reserved0;
-        /*04*/  u16 status;
-                u16 reserved1;
-        /*08*/  u16 switches;
-                u16 reserved2;
-        /*0C*/  u16 resets;
-                u16 reserved3;
-
-        /*10*/  u16 pcmcia;
-                u16 reserved4;
-        /*14*/  u16 board;
-                u16 reserved5;
-        /*18*/  u16 disk_leds;
-                u16 reserved6;
-        /*1C*/  u16 system;
-                u16 reserved7;
-
-        /*20*/  u16 intclr;
-                u16 reserved8;
-        /*24*/  u16 intset;
-                u16 reserved9;
-        /*28*/  u16 intclr_mask;
-                u16 reserved10;
-        /*2C*/  u16 intset_mask;
-                u16 reserved11;
-
-        /*30*/  u16 sig_status;
-                u16 reserved12;
-        /*34*/  u16 int_status;
-                u16 reserved13;
-        /*38*/  u16 reserved14;
-                u16 reserved15;
-        /*3C*/  u16 reserved16;
-                u16 reserved17;
-
-} BCSR;
-
-static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
-
-/*
- * Register bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID        0x000F
-#define BCSR_WHOAMI_CPLD        0x00F0
-#define BCSR_WHOAMI_BOARD       0x0F00
-
-#define BCSR_STATUS_PCMCIA0VS   0x0003
-#define BCSR_STATUS_PCMCIA1VS   0x000C
-#define BCSR_STATUS_SWAPBOOT    0x0040
-#define BCSR_STATUS_FLASHBUSY   0x0100
-#define BCSR_STATUS_IDECBLID    0x0200
-#define BCSR_STATUS_SD0WP       0x0400
-#define BCSR_STATUS_SD1WP       0x0800
-#define BCSR_STATUS_U0RXD       0x1000
-#define BCSR_STATUS_U1RXD       0x2000
-
-#define BCSR_SWITCHES_OCTAL     0x00FF
-#define BCSR_SWITCHES_DIP_1     0x0080
-#define BCSR_SWITCHES_DIP_2     0x0040
-#define BCSR_SWITCHES_DIP_3     0x0020
-#define BCSR_SWITCHES_DIP_4     0x0010
-#define BCSR_SWITCHES_DIP_5     0x0008
-#define BCSR_SWITCHES_DIP_6     0x0004
-#define BCSR_SWITCHES_DIP_7     0x0002
-#define BCSR_SWITCHES_DIP_8     0x0001
-#define BCSR_SWITCHES_ROTARY    0x0F00
-
-#define BCSR_RESETS_ETH         0x0001
-#define BCSR_RESETS_CAMERA      0x0002
-#define BCSR_RESETS_DC          0x0004
-#define BCSR_RESETS_IDE         0x0008
-/* not resets but in the same register */
-#define BCSR_RESETS_WSCFSM      0x0800
-#define BCSR_RESETS_PCS0MUX     0x1000
-#define BCSR_RESETS_PCS1MUX     0x2000
-#define BCSR_RESETS_SPISEL      0x4000
-#define BCSR_RESETS_SD1MUX      0x8000
-
-#define BCSR_PCMCIA_PC0VPP      0x0003
-#define BCSR_PCMCIA_PC0VCC      0x000C
-#define BCSR_PCMCIA_PC0DRVEN    0x0010
-#define BCSR_PCMCIA_PC0RST      0x0080
-#define BCSR_PCMCIA_PC1VPP      0x0300
-#define BCSR_PCMCIA_PC1VCC      0x0C00
-#define BCSR_PCMCIA_PC1DRVEN    0x1000
-#define BCSR_PCMCIA_PC1RST      0x8000
-
-#define BCSR_BOARD_LCDVEE       0x0001
-#define BCSR_BOARD_LCDVDD       0x0002
-#define BCSR_BOARD_LCDBL        0x0004
-#define BCSR_BOARD_CAMSNAP      0x0010
-#define BCSR_BOARD_CAMPWR       0x0020
-#define BCSR_BOARD_SD0PWR       0x0040
-#define BCSR_BOARD_SD1PWR       0x0080
-
-#define BCSR_LEDS_DECIMALS      0x00FF
-#define BCSR_LEDS_LED0          0x0100
-#define BCSR_LEDS_LED1          0x0200
-#define BCSR_LEDS_LED2          0x0400
-#define BCSR_LEDS_LED3          0x0800
-
-#define BCSR_SYSTEM_VDDI        0x001F
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
-/* Bit positions for the different interrupt sources */
-#define BCSR_INT_IDE            0x0001
-#define BCSR_INT_ETH            0x0002
-#define BCSR_INT_PC0            0x0004
-#define BCSR_INT_PC0STSCHG      0x0008
-#define BCSR_INT_PC1            0x0010
-#define BCSR_INT_PC1STSCHG      0x0020
-#define BCSR_INT_DC             0x0040
-#define BCSR_INT_FLASHBUSY      0x0080
-#define BCSR_INT_PC0INSERT      0x0100
-#define BCSR_INT_PC0EJECT       0x0200
-#define BCSR_INT_PC1INSERT      0x0400
-#define BCSR_INT_PC1EJECT       0x0800
-#define BCSR_INT_SD0INSERT      0x1000
-#define BCSR_INT_SD0EJECT       0x2000
-#define BCSR_INT_SD1INSERT      0x4000
-#define BCSR_INT_SD1EJECT       0x8000
-
-#define SMC91C111_PHYS_ADDR     0x0D000300
-#define SMC91C111_INT           PB1200_ETH_INT
-
-#define IDE_PHYS_ADDR           0x0C800000
-#define IDE_REG_SHIFT           5
-#define IDE_PHYS_LEN            (16 << IDE_REG_SHIFT)
-#define IDE_INT                 PB1200_IDE_INT
-#define IDE_DDMA_REQ            DSCR_CMD0_DMA_REQ1
-#define IDE_RQSIZE              128
-
-#define NAND_PHYS_ADDR  0x1C000000
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an Au1200 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-/*
- * External Interrupts for Pb1200 as of 8/6/2004.
- * Bit positions in the CPLD registers can be calculated by taking
- * the interrupt define and subtracting the PB1200_INT_BEGIN value.
- *
- *   Example: IDE bis pos is  = 64 - 64
- *            ETH bit pos is  = 65 - 64
- */
-enum external_pb1200_ints {
-        PB1200_INT_BEGIN        = AU1000_MAX_INTR + 1,
-
-        PB1200_IDE_INT          = PB1200_INT_BEGIN,
-        PB1200_ETH_INT,
-        PB1200_PC0_INT,
-        PB1200_PC0_STSCHG_INT,
-        PB1200_PC1_INT,
-        PB1200_PC1_STSCHG_INT,
-        PB1200_DC_INT,
-        PB1200_FLASHBUSY_INT,
-        PB1200_PC0_INSERT_INT,
-        PB1200_PC0_EJECT_INT,
-        PB1200_PC1_INSERT_INT,
-        PB1200_PC1_EJECT_INT,
-        PB1200_SD0_INSERT_INT,
-        PB1200_SD0_EJECT_INT,
-        PB1200_SD1_INSERT_INT,
-        PB1200_SD1_EJECT_INT,
-
-        PB1200_INT_END          = PB1200_INT_BEGIN + 15
-};
-
-/*
- * Pb1200 specific PCMCIA defines for drivers/pcmcia/au1000_db1x00.c
- */
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-#define BOARD_PC0_INT   PB1200_PC0_INT
-#define BOARD_PC1_INT   PB1200_PC1_INT
-#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1 << (8 + (2 * SOCKET)))
-
-/* NAND chip select */
-#define NAND_CS 1
-
-#endif /* __ASM_PB1200_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1500.h b/include/asm-mips/mach-pb1x00/pb1500.h
deleted file mode 100644
index da51a2eb7b82..000000000000
--- a/include/asm-mips/mach-pb1x00/pb1500.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Alchemy Semi Pb1500 Referrence Board
- *
- * Copyright 2001, 2008 MontaVista Software Inc.
- * Author: MontaVista Software, Inc. <source@mvista.com>
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1500_H
-#define __ASM_PB1500_H
-
-#define IDENT_BOARD_REG         0xAE000000
-#define BOARD_STATUS_REG        0xAE000004
-#define PCI_BOARD_REG           0xAE000010
-#define PCMCIA_BOARD_REG        0xAE000010
-#  define PC_DEASSERT_RST             0x80
-#  define PC_DRV_EN                   0x10
-#define PB1500_G_CONTROL        0xAE000014
-#define PB1500_RST_VDDI         0xAE00001C
-#define PB1500_LEDS             0xAE000018
-
-#define PB1500_HEX_LED          0xAF000004
-#define PB1500_HEX_LED_BLANK    0xAF000008
-
-/* PCMCIA Pb1500 specific defines */
-#define PCMCIA_MAX_SOCK  0
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP) (((VCC) << 2) | ((VPP) << 0))
-
-#endif /* __ASM_PB1500_H */
diff --git a/include/asm-mips/mach-pb1x00/pb1550.h b/include/asm-mips/mach-pb1x00/pb1550.h
deleted file mode 100644
index 6704a11497db..000000000000
--- a/include/asm-mips/mach-pb1x00/pb1550.h
+++ /dev/null
@@ -1,177 +0,0 @@
-/*
- * AMD Alchemy Semi PB1550 Referrence Board
- * Board Registers defines.
- *
- * Copyright 2004 Embedded Edge LLC.
- * Copyright 2005 Ralf Baechle (ralf@linux-mips.org)
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- *
- */
-#ifndef __ASM_PB1550_H
-#define __ASM_PB1550_H
-
-#include <linux/types.h>
-#include <asm/mach-au1x00/au1xxx_psc.h>
-
-#define DBDMA_AC97_TX_CHAN      DSCR_CMD0_PSC1_TX
-#define DBDMA_AC97_RX_CHAN      DSCR_CMD0_PSC1_RX
-#define DBDMA_I2S_TX_CHAN       DSCR_CMD0_PSC3_TX
-#define DBDMA_I2S_RX_CHAN       DSCR_CMD0_PSC3_RX
-
-#define SPI_PSC_BASE            PSC0_BASE_ADDR
-#define AC97_PSC_BASE           PSC1_BASE_ADDR
-#define SMBUS_PSC_BASE          PSC2_BASE_ADDR
-#define I2S_PSC_BASE            PSC3_BASE_ADDR
-
-#define BCSR_PHYS_ADDR 0xAF000000
-
-typedef volatile struct
-{
-        /*00*/  u16 whoami;
-                u16 reserved0;
-        /*04*/  u16 status;
-                u16 reserved1;
-        /*08*/  u16 switches;
-                u16 reserved2;
-        /*0C*/  u16 resets;
-                u16 reserved3;
-        /*10*/  u16 pcmcia;
-                u16 reserved4;
-        /*14*/  u16 pci;
-                u16 reserved5;
-        /*18*/  u16 leds;
-                u16 reserved6;
-        /*1C*/  u16 system;
-                u16 reserved7;
-
-} BCSR;
-
-static BCSR * const bcsr = (BCSR *)BCSR_PHYS_ADDR;
-
-/*
- * Register bit definitions for the BCSRs
- */
-#define BCSR_WHOAMI_DCID        0x000F
-#define BCSR_WHOAMI_CPLD        0x00F0
-#define BCSR_WHOAMI_BOARD       0x0F00
-
-#define BCSR_STATUS_PCMCIA0VS   0x0003
-#define BCSR_STATUS_PCMCIA1VS   0x000C
-#define BCSR_STATUS_PCMCIA0FI   0x0010
-#define BCSR_STATUS_PCMCIA1FI   0x0020
-#define BCSR_STATUS_SWAPBOOT    0x0040
-#define BCSR_STATUS_SRAMWIDTH   0x0080
-#define BCSR_STATUS_FLASHBUSY   0x0100
-#define BCSR_STATUS_ROMBUSY     0x0200
-#define BCSR_STATUS_USBOTGID    0x0800
-#define BCSR_STATUS_U0RXD       0x1000
-#define BCSR_STATUS_U1RXD       0x2000
-#define BCSR_STATUS_U3RXD       0x8000
-
-#define BCSR_SWITCHES_OCTAL     0x00FF
-#define BCSR_SWITCHES_DIP_1     0x0080
-#define BCSR_SWITCHES_DIP_2     0x0040
-#define BCSR_SWITCHES_DIP_3     0x0020
-#define BCSR_SWITCHES_DIP_4     0x0010
-#define BCSR_SWITCHES_DIP_5     0x0008
-#define BCSR_SWITCHES_DIP_6     0x0004
-#define BCSR_SWITCHES_DIP_7     0x0002
-#define BCSR_SWITCHES_DIP_8     0x0001
-#define BCSR_SWITCHES_ROTARY    0x0F00
-
-#define BCSR_RESETS_PHY0        0x0001
-#define BCSR_RESETS_PHY1        0x0002
-#define BCSR_RESETS_DC          0x0004
-#define BCSR_RESETS_WSC         0x2000
-#define BCSR_RESETS_SPISEL      0x4000
-#define BCSR_RESETS_DMAREQ      0x8000
-
-#define BCSR_PCMCIA_PC0VPP      0x0003
-#define BCSR_PCMCIA_PC0VCC      0x000C
-#define BCSR_PCMCIA_PC0DRVEN    0x0010
-#define BCSR_PCMCIA_PC0RST      0x0080
-#define BCSR_PCMCIA_PC1VPP      0x0300
-#define BCSR_PCMCIA_PC1VCC      0x0C00
-#define BCSR_PCMCIA_PC1DRVEN    0x1000
-#define BCSR_PCMCIA_PC1RST      0x8000
-
-#define BCSR_PCI_M66EN          0x0001
-#define BCSR_PCI_M33            0x0100
-#define BCSR_PCI_EXTERNARB      0x0200
-#define BCSR_PCI_GPIO200RST     0x0400
-#define BCSR_PCI_CLKOUT         0x0800
-#define BCSR_PCI_CFGHOST        0x1000
-
-#define BCSR_LEDS_DECIMALS      0x00FF
-#define BCSR_LEDS_LED0          0x0100
-#define BCSR_LEDS_LED1          0x0200
-#define BCSR_LEDS_LED2          0x0400
-#define BCSR_LEDS_LED3          0x0800
-
-#define BCSR_SYSTEM_VDDI        0x001F
-#define BCSR_SYSTEM_POWEROFF    0x4000
-#define BCSR_SYSTEM_RESET       0x8000
-
-#define PCMCIA_MAX_SOCK  1
-#define PCMCIA_NUM_SOCKS (PCMCIA_MAX_SOCK + 1)
-
-/* VPP/VCC */
-#define SET_VCC_VPP(VCC, VPP, SLOT) \
-        ((((VCC) << 2) | ((VPP) << 0)) << ((SLOT) * 8))
-
-#if defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOTH_BANKS
-#elif defined(CONFIG_MTD_PB1550_BOOT) && !defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_BOOT_ONLY
-#elif !defined(CONFIG_MTD_PB1550_BOOT) && defined(CONFIG_MTD_PB1550_USER)
-#define PB1550_USER_ONLY
-#endif
-
-/*
- * Timing values as described in databook, * ns value stripped of
- * lower 2 bits.
- * These defines are here rather than an SOC1550 generic file because
- * the parts chosen on another board may be different and may require
- * different timings.
- */
-#define NAND_T_H                (18 >> 2)
-#define NAND_T_PUL              (30 >> 2)
-#define NAND_T_SU               (30 >> 2)
-#define NAND_T_WH               (30 >> 2)
-
-/* Bitfield shift amounts */
-#define NAND_T_H_SHIFT          0
-#define NAND_T_PUL_SHIFT        4
-#define NAND_T_SU_SHIFT         8
-#define NAND_T_WH_SHIFT         12
-
-#define NAND_TIMING     (((NAND_T_H   & 0xF) << NAND_T_H_SHIFT)   | \
-                         ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
-                         ((NAND_T_SU  & 0xF) << NAND_T_SU_SHIFT)  | \
-                         ((NAND_T_WH  & 0xF) << NAND_T_WH_SHIFT))
-
-#define NAND_CS 1
-
-/* Should be done by YAMON */
-#define NAND_STCFG      0x00400005 /* 8-bit NAND */
-#define NAND_STTIME     0x00007774 /* valid for 396 MHz SD=2 only */
-#define NAND_STADDR     0x12000FFF /* physical address 0x20000000 */
-
-#endif /* __ASM_PB1550_H */
diff --git a/include/asm-mips/mach-pnx8550/cm.h b/include/asm-mips/mach-pnx8550/cm.h
deleted file mode 100644
index bb0a56c7d011..000000000000
--- a/include/asm-mips/mach-pnx8550/cm.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   Clock module specific definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_CM_H
-#define __PNX8550_CM_H
-
-#define PNX8550_CM_BASE 0xBBE47000
-
-#define PNX8550_CM_PLL0_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x000)
-#define PNX8550_CM_PLL1_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x004)
-#define PNX8550_CM_PLL2_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x008)
-#define PNX8550_CM_PLL3_CTL    *(volatile unsigned long *)(PNX8550_CM_BASE + 0x00C)
-
-// Table not complete.....
-
-#define PNX8550_CM_PLL_BLOCKED_MASK     0x80000000
-#define PNX8550_CM_PLL_LOCK_MASK        0x40000000
-#define PNX8550_CM_PLL_CURRENT_ADJ_MASK 0x3c000000
-#define PNX8550_CM_PLL_N_MASK           0x01ff0000
-#define PNX8550_CM_PLL_M_MASK           0x00003f00
-#define PNX8550_CM_PLL_P_MASK           0x0000000c
-#define PNX8550_CM_PLL_PD_MASK          0x00000002
-
-
-#endif
diff --git a/include/asm-mips/mach-pnx8550/glb.h b/include/asm-mips/mach-pnx8550/glb.h
deleted file mode 100644
index 07aa85e609bc..000000000000
--- a/include/asm-mips/mach-pnx8550/glb.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   PNX8550 global definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_GLB_H
-#define __PNX8550_GLB_H
-
-#define PNX8550_GLB1_BASE       0xBBE63000
-#define PNX8550_GLB2_BASE       0xBBE4d000
-#define PNX8550_RESET_BASE      0xBBE60000
-
-/* PCI Inta Output Enable Registers */
-#define PNX8550_GLB2_ENAB_INTA_O        *(volatile unsigned long *)(PNX8550_GLB2_BASE + 0x050)
-
-/* Bit 1:Enable DAC Powerdown
-     0:DACs are enabled and are working normally
-     1:DACs are powerdown
-*/
-#define PNX8550_GLB_DAC_PD      0x2
-/*   Bit 0:Enable of PCI inta output
-     0 = Disable PCI inta output
-     1 = Enable PCI inta output
-*/
-#define PNX8550_GLB_ENABLE_INTA_O 0x1
-
-/* PCI Direct Mappings */
-#define PNX8550_PCIMEM          0x12000000
-#define PNX8550_PCIMEM_SIZE     0x08000000
-#define PNX8550_PCIIO           0x1c000000
-#define PNX8550_PCIIO_SIZE      0x02000000      /* 32M */
-
-#define PNX8550_PORT_BASE       KSEG1
-
-// GPIO def
-#define PNX8550_GPIO_BASE       0x1Be00000
-
-#define PNX8550_GPIO_DIRQ0       (PNX8550_GPIO_BASE + 0x104500)
-#define PNX8550_GPIO_MC1         (PNX8550_GPIO_BASE + 0x104004)
-#define PNX8550_GPIO_MC_31_BIT   30
-#define PNX8550_GPIO_MC_30_BIT   28
-#define PNX8550_GPIO_MC_29_BIT   26
-#define PNX8550_GPIO_MC_28_BIT   24
-#define PNX8550_GPIO_MC_27_BIT   22
-#define PNX8550_GPIO_MC_26_BIT   20
-#define PNX8550_GPIO_MC_25_BIT   18
-#define PNX8550_GPIO_MC_24_BIT   16
-#define PNX8550_GPIO_MC_23_BIT   14
-#define PNX8550_GPIO_MC_22_BIT   12
-#define PNX8550_GPIO_MC_21_BIT   10
-#define PNX8550_GPIO_MC_20_BIT   8
-#define PNX8550_GPIO_MC_19_BIT   6
-#define PNX8550_GPIO_MC_18_BIT   4
-#define PNX8550_GPIO_MC_17_BIT   2
-#define PNX8550_GPIO_MC_16_BIT   0
-
-#define PNX8550_GPIO_MODE_PRIMOP    0x1
-#define PNX8550_GPIO_MODE_NO_OPENDR 0x2
-#define PNX8550_GPIO_MODE_OPENDR    0x3
-
-// RESET module
-#define PNX8550_RST_CTL             *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x0)
-#define PNX8550_RST_CAUSE           *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x4)
-#define PNX8550_RST_EN_WATCHDOG     *(volatile unsigned long *)(PNX8550_RESET_BASE + 0x8)
-
-#define PNX8550_RST_REL_MIPS_RST_N     0x8
-#define PNX8550_RST_DO_SW_RST          0x4
-#define PNX8550_RST_REL_SYS_RST_OUT    0x2
-#define PNX8550_RST_ASSERT_SYS_RST_OUT 0x1
-#endif
diff --git a/include/asm-mips/mach-pnx8550/int.h b/include/asm-mips/mach-pnx8550/int.h
deleted file mode 100644
index 0e0668b524f4..000000000000
--- a/include/asm-mips/mach-pnx8550/int.h
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *   Interrupt specific definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_INT_H
-#define __PNX8550_INT_H
-
-#define PNX8550_GIC_BASE        0xBBE3E000
-
-#define PNX8550_GIC_PRIMASK_0   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x000)
-#define PNX8550_GIC_PRIMASK_1   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x004)
-#define PNX8550_GIC_VECTOR_0    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x100)
-#define PNX8550_GIC_VECTOR_1    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x104)
-#define PNX8550_GIC_PEND_1_31   *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x200)
-#define PNX8550_GIC_PEND_32_63  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x204)
-#define PNX8550_GIC_PEND_64_70  *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x208)
-#define PNX8550_GIC_FEATURES    *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x300)
-#define PNX8550_GIC_REQ(x)      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0x400 + (x)*4)
-#define PNX8550_GIC_MOD_ID      *(volatile unsigned long *)(PNX8550_GIC_BASE + 0xFFC)
-
-// cp0 is two software + six hw exceptions
-#define PNX8550_INT_CP0_TOTINT  8
-#define PNX8550_INT_CP0_MIN     0
-#define PNX8550_INT_CP0_MAX     (PNX8550_INT_CP0_MIN + PNX8550_INT_CP0_TOTINT - 1)
-
-#define MIPS_CPU_GIC_IRQ        2
-#define MIPS_CPU_TIMER_IRQ      7
-
-// GIC are 71 exceptions connected to cp0's first hardware exception
-#define PNX8550_INT_GIC_TOTINT  71
-#define PNX8550_INT_GIC_MIN     (PNX8550_INT_CP0_MAX+1)
-#define PNX8550_INT_GIC_MAX     (PNX8550_INT_GIC_MIN + PNX8550_INT_GIC_TOTINT - 1)
-
-#define PNX8550_INT_UNDEF              (PNX8550_INT_GIC_MIN+0)
-#define PNX8550_INT_IPC_TARGET0_MIPS   (PNX8550_INT_GIC_MIN+1)
-#define PNX8550_INT_IPC_TARGET1_TM32_1 (PNX8550_INT_GIC_MIN+2)
-#define PNX8550_INT_IPC_TARGET1_TM32_2 (PNX8550_INT_GIC_MIN+3)
-#define PNX8550_INT_RESERVED_4         (PNX8550_INT_GIC_MIN+4)
-#define PNX8550_INT_USB                (PNX8550_INT_GIC_MIN+5)
-#define PNX8550_INT_GPIO_EQ1           (PNX8550_INT_GIC_MIN+6)
-#define PNX8550_INT_GPIO_EQ2           (PNX8550_INT_GIC_MIN+7)
-#define PNX8550_INT_GPIO_EQ3           (PNX8550_INT_GIC_MIN+8)
-#define PNX8550_INT_GPIO_EQ4           (PNX8550_INT_GIC_MIN+9)
-
-#define PNX8550_INT_GPIO_EQ5           (PNX8550_INT_GIC_MIN+10)
-#define PNX8550_INT_GPIO_EQ6           (PNX8550_INT_GIC_MIN+11)
-#define PNX8550_INT_RESERVED_12        (PNX8550_INT_GIC_MIN+12)
-#define PNX8550_INT_QVCP1              (PNX8550_INT_GIC_MIN+13)
-#define PNX8550_INT_QVCP2              (PNX8550_INT_GIC_MIN+14)
-#define PNX8550_INT_I2C1               (PNX8550_INT_GIC_MIN+15)
-#define PNX8550_INT_I2C2               (PNX8550_INT_GIC_MIN+16)
-#define PNX8550_INT_ISO_UART1          (PNX8550_INT_GIC_MIN+17)
-#define PNX8550_INT_ISO_UART2          (PNX8550_INT_GIC_MIN+18)
-#define PNX8550_INT_UART1              (PNX8550_INT_GIC_MIN+19)
-
-#define PNX8550_INT_UART2              (PNX8550_INT_GIC_MIN+20)
-#define PNX8550_INT_QNTR               (PNX8550_INT_GIC_MIN+21)
-#define PNX8550_INT_RESERVED22         (PNX8550_INT_GIC_MIN+22)
-#define PNX8550_INT_T_DSC              (PNX8550_INT_GIC_MIN+23)
-#define PNX8550_INT_M_DSC              (PNX8550_INT_GIC_MIN+24)
-#define PNX8550_INT_RESERVED25         (PNX8550_INT_GIC_MIN+25)
-#define PNX8550_INT_2D_DRAW_ENG        (PNX8550_INT_GIC_MIN+26)
-#define PNX8550_INT_MEM_BASED_SCALAR1  (PNX8550_INT_GIC_MIN+27)
-#define PNX8550_INT_VIDEO_MPEG         (PNX8550_INT_GIC_MIN+28)
-#define PNX8550_INT_VIDEO_INPUT_P1     (PNX8550_INT_GIC_MIN+29)
-
-#define PNX8550_INT_VIDEO_INPUT_P2     (PNX8550_INT_GIC_MIN+30)
-#define PNX8550_INT_SPDI1              (PNX8550_INT_GIC_MIN+31)
-#define PNX8550_INT_SPDO               (PNX8550_INT_GIC_MIN+32)
-#define PNX8550_INT_AUDIO_INPUT1       (PNX8550_INT_GIC_MIN+33)
-#define PNX8550_INT_AUDIO_OUTPUT1      (PNX8550_INT_GIC_MIN+34)
-#define PNX8550_INT_AUDIO_INPUT2       (PNX8550_INT_GIC_MIN+35)
-#define PNX8550_INT_AUDIO_OUTPUT2      (PNX8550_INT_GIC_MIN+36)
-#define PNX8550_INT_MEMBASED_SCALAR2   (PNX8550_INT_GIC_MIN+37)
-#define PNX8550_INT_VPK                (PNX8550_INT_GIC_MIN+38)
-#define PNX8550_INT_MPEG1_MIPS         (PNX8550_INT_GIC_MIN+39)
-
-#define PNX8550_INT_MPEG1_TM           (PNX8550_INT_GIC_MIN+40)
-#define PNX8550_INT_MPEG2_MIPS         (PNX8550_INT_GIC_MIN+41)
-#define PNX8550_INT_MPEG2_TM           (PNX8550_INT_GIC_MIN+42)
-#define PNX8550_INT_TS_DMA             (PNX8550_INT_GIC_MIN+43)
-#define PNX8550_INT_EDMA               (PNX8550_INT_GIC_MIN+44)
-#define PNX8550_INT_TM_DEBUG1          (PNX8550_INT_GIC_MIN+45)
-#define PNX8550_INT_TM_DEBUG2          (PNX8550_INT_GIC_MIN+46)
-#define PNX8550_INT_PCI_INTA           (PNX8550_INT_GIC_MIN+47)
-#define PNX8550_INT_CLOCK_MODULE       (PNX8550_INT_GIC_MIN+48)
-#define PNX8550_INT_PCI_XIO_INTA_PCI   (PNX8550_INT_GIC_MIN+49)
-
-#define PNX8550_INT_PCI_XIO_INTB_DMA   (PNX8550_INT_GIC_MIN+50)
-#define PNX8550_INT_PCI_XIO_INTC_GPPM  (PNX8550_INT_GIC_MIN+51)
-#define PNX8550_INT_PCI_XIO_INTD_GPXIO (PNX8550_INT_GIC_MIN+52)
-#define PNX8550_INT_DVD_CSS            (PNX8550_INT_GIC_MIN+53)
-#define PNX8550_INT_VLD                (PNX8550_INT_GIC_MIN+54)
-#define PNX8550_INT_GPIO_TSU_7_0       (PNX8550_INT_GIC_MIN+55)
-#define PNX8550_INT_GPIO_TSU_15_8      (PNX8550_INT_GIC_MIN+56)
-#define PNX8550_INT_GPIO_CTU_IR        (PNX8550_INT_GIC_MIN+57)
-#define PNX8550_INT_GPIO0              (PNX8550_INT_GIC_MIN+58)
-#define PNX8550_INT_GPIO1              (PNX8550_INT_GIC_MIN+59)
-
-#define PNX8550_INT_GPIO2              (PNX8550_INT_GIC_MIN+60)
-#define PNX8550_INT_GPIO3              (PNX8550_INT_GIC_MIN+61)
-#define PNX8550_INT_GPIO4              (PNX8550_INT_GIC_MIN+62)
-#define PNX8550_INT_GPIO5              (PNX8550_INT_GIC_MIN+63)
-#define PNX8550_INT_GPIO6              (PNX8550_INT_GIC_MIN+64)
-#define PNX8550_INT_GPIO7              (PNX8550_INT_GIC_MIN+65)
-#define PNX8550_INT_PMAN_SECURITY      (PNX8550_INT_GIC_MIN+66)
-#define PNX8550_INT_I2C3               (PNX8550_INT_GIC_MIN+67)
-#define PNX8550_INT_RESERVED_68        (PNX8550_INT_GIC_MIN+68)
-#define PNX8550_INT_SPDI2              (PNX8550_INT_GIC_MIN+69)
-
-#define PNX8550_INT_I2C4               (PNX8550_INT_GIC_MIN+70)
-
-// Timer are 3 exceptions connected to cp0's 7th hardware exception
-#define PNX8550_INT_TIMER_TOTINT       3
-#define PNX8550_INT_TIMER_MIN          (PNX8550_INT_GIC_MAX+1)
-#define PNX8550_INT_TIMER_MAX          (PNX8550_INT_TIMER_MIN + PNX8550_INT_TIMER_TOTINT - 1)
-
-#define PNX8550_INT_TIMER1             (PNX8550_INT_TIMER_MIN+0)
-#define PNX8550_INT_TIMER2             (PNX8550_INT_TIMER_MIN+1)
-#define PNX8550_INT_TIMER3             (PNX8550_INT_TIMER_MIN+2)
-#define PNX8550_INT_WATCHDOG           PNX8550_INT_TIMER3
-
-#endif
diff --git a/include/asm-mips/mach-pnx8550/kernel-entry-init.h b/include/asm-mips/mach-pnx8550/kernel-entry-init.h
deleted file mode 100644
index bdde00c9199b..000000000000
--- a/include/asm-mips/mach-pnx8550/kernel-entry-init.h
+++ /dev/null
@@ -1,262 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2005 Embedded Alley Solutions, Inc
- */
-#ifndef __ASM_MACH_KERNEL_ENTRY_INIT_H
-#define __ASM_MACH_KERNEL_ENTRY_INIT_H
-
-#include <asm/cacheops.h>
-#include <asm/addrspace.h>
-
-#define CO_CONFIGPR_VALID  0x3F1F41FF    /* valid bits to write to ConfigPR */
-#define HAZARD_CP0 nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop; nop;
-#define CACHE_OPC      0xBC000000  /* MIPS cache instruction opcode */
-#define ICACHE_LINE_SIZE        32      /* Instruction cache line size bytes */
-#define DCACHE_LINE_SIZE        32      /* Data cache line size in bytes */
-
-#define ICACHE_SET_COUNT        256     /* Instruction cache set count */
-#define DCACHE_SET_COUNT        128     /* Data cache set count */
-
-#define ICACHE_SET_SIZE         (ICACHE_SET_COUNT * ICACHE_LINE_SIZE)
-#define DCACHE_SET_SIZE         (DCACHE_SET_COUNT * DCACHE_LINE_SIZE)
-
-        .macro  kernel_entry_setup
-        .set    push
-        .set    noreorder
-        /*
-         * PNX8550 entry point, when running a non compressed
-         * kernel. When loading a zImage, the head.S code in
-         * arch/mips/zboot/pnx8550 will init the caches and,
-         * decompress the kernel, and branch to kernel_entry.
-                 */
-cache_begin:    li      t0, (1<<28)
-        mtc0    t0, CP0_STATUS /* cp0 usable */
-        HAZARD_CP0
-
-        mtc0    zero, CP0_CAUSE
-        HAZARD_CP0
-
-
-        /* Set static virtual to phys address translation and TLB disabled */
-        mfc0    t0, CP0_CONFIG, 7
-        HAZARD_CP0
-
-        and     t0, ~((1<<19) | (1<<20))     /* TLB/MAP cleared */
-        mtc0    t0, CP0_CONFIG, 7
-        HAZARD_CP0
-
-        /* CPU boots with kseg0 cache algo set to 0x2 -- uncached */
-
-        init_icache
-        nop
-        init_dcache
-        nop
-
-        cachePr4450ICReset
-        nop
-
-        cachePr4450DCReset
-        nop
-
-        /* read ConfigPR into t0 */
-        mfc0    t0, CP0_CONFIG, 7
-        HAZARD_CP0
-
-        /*  enable the TLB */
-        or      t0, (1<<19)
-
-        /* disable the ICACHE: at least 10x slower */
-        /* or      t0, (1<<26) */
-
-        /* disable the DCACHE; CONFIG_CPU_HAS_LLSC should not be set  */
-        /* or      t0, (1<<27) */
-
-        and     t0, CO_CONFIGPR_VALID
-
-        /* enable TLB. */
-        mtc0    t0, CP0_CONFIG, 7
-        HAZARD_CP0
-cache_end:
-        /* Setup CMEM_0 to MMIO address space, 2MB */
-        lui    t0, 0x1BE0
-        addi   t0, t0, 0x3
-        mtc0   $8, $22, 4
-        nop
-
-        /* Setup CMEM_1, 128MB */
-        lui    t0, 0x1000
-        addi   t0, t0, 0xf
-        mtc0   $8, $22, 5
-        nop
-
-
-        /* Setup CMEM_2, 32MB */
-        lui    t0, 0x1C00
-        addi   t0, t0, 0xb
-        mtc0   $8, $22, 6
-        nop
-
-        /* Setup CMEM_3, 0MB */
-        lui    t0, 0x0
-        addi   t0, t0, 0x0
-        mtc0   $8, $22, 7
-        nop
-
-        /* Enable cache */
-        mfc0    t0, CP0_CONFIG
-        HAZARD_CP0
-        and     t0, t0, 0xFFFFFFF8
-        or      t0, t0, 3
-        mtc0    t0, CP0_CONFIG
-        HAZARD_CP0
-        .set    pop
-        .endm
-
-        .macro  init_icache
-        .set    push
-        .set    noreorder
-
-        /* Get Cache Configuration */
-        mfc0    t3, CP0_CONFIG, 1
-        HAZARD_CP0
-
-        /* get cache Line size */
-
-        srl   t1, t3, 19   /* C0_CONFIGPR_IL_SHIFT */
-        andi  t1, t1, 0x7  /* C0_CONFIGPR_IL_MASK */
-        beq   t1, zero, pr4450_instr_cache_invalidated /* if zero instruction cache is absent */
-        nop
-        addiu t0, t1, 1
-        ori   t1, zero, 1
-        sllv  t1, t1, t0
-
-        /* get max cache Index */
-        srl   t2, t3, 22  /* C0_CONFIGPR_IS_SHIFT */
-        andi  t2, t2, 0x7 /* C0_CONFIGPR_IS_MASK */
-        addiu t0, t2, 6
-        ori   t2, zero, 1
-        sllv  t2, t2, t0
-
-        /* get max cache way */
-        srl   t3, t3, 16  /* C0_CONFIGPR_IA_SHIFT */
-        andi  t3, t3, 0x7 /* C0_CONFIGPR_IA_MASK */
-        addiu t3, t3, 1
-
-        /* total no of cache lines */
-        multu t2, t3             /* max index * max way */
-        mflo  t2
-        addiu t2, t2, -1
-
-        move  t0, zero
-pr4450_next_instruction_cache_set:
-        cache  Index_Invalidate_I, 0(t0)
-        addu  t0, t0, t1         /* add bytes in a line */
-        bne   t2, zero, pr4450_next_instruction_cache_set
-        addiu t2, t2, -1   /* reduce no of lines to invalidate by one */
-pr4450_instr_cache_invalidated:
-        .set    pop
-        .endm
-
-        .macro  init_dcache
-        .set    push
-        .set    noreorder
-        move t1, zero
-
-        /* Store Tag Information */
-        mtc0    zero, CP0_TAGLO, 0
-        HAZARD_CP0
-
-        mtc0    zero, CP0_TAGHI, 0
-        HAZARD_CP0
-
-        /* Cache size is 16384 = 512 lines x 32 bytes per line */
-        or       t2, zero, (128*4)-1  /* 512 lines  */
-        /* Invalidate all lines */
-2:
-        cache Index_Store_Tag_D, 0(t1)
-        addiu    t2, t2, -1
-        bne      t2, zero, 2b
-        addiu    t1, t1, 32        /* 32 bytes in a line */
-        .set pop
-        .endm
-
-        .macro  cachePr4450ICReset
-        .set    push
-        .set    noreorder
-
-        /* Save CP0 status reg on entry; */
-        /* disable interrupts during cache reset */
-        mfc0    t0, CP0_STATUS      /* T0 = interrupt status on entry */
-        HAZARD_CP0
-
-        mtc0    zero, CP0_STATUS   /* disable CPU interrupts */
-        HAZARD_CP0
-
-        or      t1, zero, zero              /* T1 = starting cache index (0) */
-        ori     t2, zero, (256 - 1) /* T2 = inst cache set cnt - 1 */
-
-        icache_invd_loop:
-        /* 9 == register t1 */
-        .word   CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
-                (0 * ICACHE_SET_SIZE)  /* invalidate inst cache WAY0 */
-        .word   CACHE_OPC | (9 << 21) | (Index_Invalidate_I << 16) | \
-                (1 * ICACHE_SET_SIZE)  /* invalidate inst cache WAY1 */
-
-        addiu   t1, t1, ICACHE_LINE_SIZE    /* T1 = next cache line index */
-        bne     t2, zero, icache_invd_loop /* T2 = 0 if all sets invalidated */
-        addiu   t2, t2, -1        /* decrement T2 set cnt (delay slot) */
-
-        /* Initialize the latches in the instruction cache tag */
-        /* that drive the way selection tri-state bus drivers, by doing a */
-        /* dummy load while the instruction cache is still disabled. */
-        /* TODO: Is this needed ? */
-        la      t1, KSEG0            /* T1 = cached memory base address */
-        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
-
-        mtc0    t0, CP0_STATUS        /* restore interrupt status on entry */
-        HAZARD_CP0
-        .set    pop
-        .endm
-
-        .macro  cachePr4450DCReset
-        .set    push
-        .set    noreorder
-        mfc0    t0, CP0_STATUS           /* T0 = interrupt status on entry */
-        HAZARD_CP0
-        mtc0    zero, CP0_STATUS         /* disable CPU interrupts */
-        HAZARD_CP0
-
-        /* Writeback/invalidate entire data cache sets/ways/lines */
-        or      t1, zero, zero              /* T1 = starting cache index (0) */
-        ori     t2, zero, (DCACHE_SET_COUNT - 1) /* T2 = data cache set cnt - 1 */
-
-        dcache_wbinvd_loop:
-        /* 9 == register t1 */
-        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-                (0 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY0 */
-        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-                (1 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY1 */
-        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-                (2 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY2 */
-        .word   CACHE_OPC | (9 << 21) | (Index_Writeback_Inv_D << 16) | \
-                (3 * DCACHE_SET_SIZE)  /* writeback/invalidate WAY3 */
-
-        addiu   t1, t1, DCACHE_LINE_SIZE  /* T1 = next data cache line index */
-        bne     t2, zero, dcache_wbinvd_loop /* T2 = 0 when wbinvd entire cache */
-        addiu   t2, t2, -1          /* decrement T2 set cnt (delay slot) */
-
-        /* Initialize the latches in the data cache tag that drive the way
-        selection tri-state bus drivers, by doing a dummy load while the
-        data cache is still in the disabled mode.  TODO: Is this needed ? */
-        la      t1, KSEG0            /* T1 = cached memory base address */
-        lw      zero, 0x0000(t1)      /* (dummy read of first memory word) */
-
-        mtc0    t0, CP0_STATUS       /* restore interrupt status on entry */
-        HAZARD_CP0
-        .set    pop
-        .endm
-
-#endif /* __ASM_MACH_KERNEL_ENTRY_INIT_H */
diff --git a/include/asm-mips/mach-pnx8550/nand.h b/include/asm-mips/mach-pnx8550/nand.h
deleted file mode 100644
index aefbc514ab09..000000000000
--- a/include/asm-mips/mach-pnx8550/nand.h
+++ /dev/null
@@ -1,121 +0,0 @@
-#ifndef __PNX8550_NAND_H
-#define __PNX8550_NAND_H
-
-#define PNX8550_NAND_BASE_ADDR   0x10000000
-#define PNX8550_PCIXIO_BASE      0xBBE40000
-
-#define PNX8550_DMA_EXT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x800)
-#define PNX8550_DMA_INT_ADDR     *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x804)
-#define PNX8550_DMA_TRANS_SIZE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x808)
-#define PNX8550_DMA_CTRL         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x80c)
-#define PNX8550_XIO_SEL0         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x814)
-#define PNX8550_GPXIO_ADDR       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x820)
-#define PNX8550_GPXIO_WR         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x824)
-#define PNX8550_GPXIO_RD         *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x828)
-#define PNX8550_GPXIO_CTRL       *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x82C)
-#define PNX8550_XIO_FLASH_CTRL   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0x830)
-#define PNX8550_GPXIO_INT_STATUS *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb0)
-#define PNX8550_GPXIO_INT_ENABLE *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb4)
-#define PNX8550_GPXIO_INT_CLEAR  *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfb8)
-#define PNX8550_DMA_INT_STATUS   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd0)
-#define PNX8550_DMA_INT_ENABLE   *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd4)
-#define PNX8550_DMA_INT_CLEAR    *(volatile unsigned long *)(PNX8550_PCIXIO_BASE + 0xfd8)
-
-#define PNX8550_XIO_SEL0_EN_16BIT    0x00800000
-#define PNX8550_XIO_SEL0_USE_ACK     0x00400000
-#define PNX8550_XIO_SEL0_REN_HIGH    0x00100000
-#define PNX8550_XIO_SEL0_REN_LOW     0x00040000
-#define PNX8550_XIO_SEL0_WEN_HIGH    0x00010000
-#define PNX8550_XIO_SEL0_WEN_LOW     0x00004000
-#define PNX8550_XIO_SEL0_WAIT        0x00000200
-#define PNX8550_XIO_SEL0_OFFSET      0x00000020
-#define PNX8550_XIO_SEL0_TYPE_68360  0x00000000
-#define PNX8550_XIO_SEL0_TYPE_NOR    0x00000008
-#define PNX8550_XIO_SEL0_TYPE_NAND   0x00000010
-#define PNX8550_XIO_SEL0_TYPE_IDE    0x00000018
-#define PNX8550_XIO_SEL0_SIZE_8MB    0x00000000
-#define PNX8550_XIO_SEL0_SIZE_16MB   0x00000002
-#define PNX8550_XIO_SEL0_SIZE_32MB   0x00000004
-#define PNX8550_XIO_SEL0_SIZE_64MB   0x00000006
-#define PNX8550_XIO_SEL0_ENAB        0x00000001
-
-#define PNX8550_SEL0_DEFAULT ((PNX8550_XIO_SEL0_EN_16BIT)  | \
-                              (PNX8550_XIO_SEL0_REN_HIGH*0)| \
-                              (PNX8550_XIO_SEL0_REN_LOW*2) | \
-                              (PNX8550_XIO_SEL0_WEN_HIGH*0)| \
-                              (PNX8550_XIO_SEL0_WEN_LOW*2) | \
-                              (PNX8550_XIO_SEL0_WAIT*4)    | \
-                              (PNX8550_XIO_SEL0_OFFSET*0)  | \
-                              (PNX8550_XIO_SEL0_TYPE_NAND) | \
-                              (PNX8550_XIO_SEL0_SIZE_32MB) | \
-                              (PNX8550_XIO_SEL0_ENAB))
-
-#define PNX8550_GPXIO_PENDING        0x00000200
-#define PNX8550_GPXIO_DONE           0x00000100
-#define PNX8550_GPXIO_CLR_DONE       0x00000080
-#define PNX8550_GPXIO_INIT           0x00000040
-#define PNX8550_GPXIO_READ_CMD       0x00000010
-#define PNX8550_GPXIO_BEN            0x0000000F
-
-#define PNX8550_XIO_FLASH_64MB       0x00200000
-#define PNX8550_XIO_FLASH_INC_DATA   0x00100000
-#define PNX8550_XIO_FLASH_CMD_PH     0x000C0000
-#define PNX8550_XIO_FLASH_CMD_PH2    0x00080000
-#define PNX8550_XIO_FLASH_CMD_PH1    0x00040000
-#define PNX8550_XIO_FLASH_CMD_PH0    0x00000000
-#define PNX8550_XIO_FLASH_ADR_PH     0x00030000
-#define PNX8550_XIO_FLASH_ADR_PH3    0x00030000
-#define PNX8550_XIO_FLASH_ADR_PH2    0x00020000
-#define PNX8550_XIO_FLASH_ADR_PH1    0x00010000
-#define PNX8550_XIO_FLASH_ADR_PH0    0x00000000
-#define PNX8550_XIO_FLASH_CMD_B(x)   ((x<<8) & 0x0000FF00)
-#define PNX8550_XIO_FLASH_CMD_A(x)   (x & 0x000000FF)
-
-#define PNX8550_XIO_INT_ACK          0x00004000
-#define PNX8550_XIO_INT_COMPL        0x00002000
-#define PNX8550_XIO_INT_NONSUP       0x00000200
-#define PNX8550_XIO_INT_ABORT        0x00000004
-
-#define PNX8550_DMA_CTRL_SINGLE_DATA 0x00000400
-#define PNX8550_DMA_CTRL_SND2XIO     0x00000200
-#define PNX8550_DMA_CTRL_FIX_ADDR    0x00000100
-#define PNX8550_DMA_CTRL_BURST_8     0x00000000
-#define PNX8550_DMA_CTRL_BURST_16    0x00000020
-#define PNX8550_DMA_CTRL_BURST_32    0x00000040
-#define PNX8550_DMA_CTRL_BURST_64    0x00000060
-#define PNX8550_DMA_CTRL_BURST_128   0x00000080
-#define PNX8550_DMA_CTRL_BURST_256   0x000000A0
-#define PNX8550_DMA_CTRL_BURST_512   0x000000C0
-#define PNX8550_DMA_CTRL_BURST_NORES 0x000000E0
-#define PNX8550_DMA_CTRL_INIT_DMA    0x00000010
-#define PNX8550_DMA_CTRL_CMD_TYPE    0x0000000F
-
-/* see PCI system arch, page 100 for the full list: */
-#define PNX8550_DMA_CTRL_PCI_CMD_READ    0x00000006
-#define PNX8550_DMA_CTRL_PCI_CMD_WRITE   0x00000007
-
-#define PNX8550_DMA_INT_STAT_ACK_DONE   (1<<14)
-#define PNX8550_DMA_INT_STAT_DMA_DONE   (1<<12)
-#define PNX8550_DMA_INT_STAT_DMA_ERR    (1<<9)
-#define PNX8550_DMA_INT_STAT_PERR5      (1<<5)
-#define PNX8550_DMA_INT_STAT_PERR4      (1<<4)
-#define PNX8550_DMA_INT_STAT_M_ABORT    (1<<2)
-#define PNX8550_DMA_INT_STAT_T_ABORT    (1<<1)
-
-#define PNX8550_DMA_INT_EN_ACK_DONE     (1<<14)
-#define PNX8550_DMA_INT_EN_DMA_DONE     (1<<12)
-#define PNX8550_DMA_INT_EN_DMA_ERR      (1<<9)
-#define PNX8550_DMA_INT_EN_PERR5        (1<<5)
-#define PNX8550_DMA_INT_EN_PERR4        (1<<4)
-#define PNX8550_DMA_INT_EN_M_ABORT      (1<<2)
-#define PNX8550_DMA_INT_EN_T_ABORT      (1<<1)
-
-#define PNX8550_DMA_INT_CLR_ACK_DONE    (1<<14)
-#define PNX8550_DMA_INT_CLR_DMA_DONE    (1<<12)
-#define PNX8550_DMA_INT_CLR_DMA_ERR     (1<<9)
-#define PNX8550_DMA_INT_CLR_PERR5       (1<<5)
-#define PNX8550_DMA_INT_CLR_PERR4       (1<<4)
-#define PNX8550_DMA_INT_CLR_M_ABORT     (1<<2)
-#define PNX8550_DMA_INT_CLR_T_ABORT     (1<<1)
-
-#endif
diff --git a/include/asm-mips/mach-pnx8550/pci.h b/include/asm-mips/mach-pnx8550/pci.h
deleted file mode 100644
index b921508d701b..000000000000
--- a/include/asm-mips/mach-pnx8550/pci.h
+++ /dev/null
@@ -1,185 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- * PCI specific definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_PCI_H
-#define __PNX8550_PCI_H
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <linux/kernel.h>
-#include <linux/init.h>
-
-#define PCI_ACCESS_READ  0
-#define PCI_ACCESS_WRITE 1
-
-#define PCI_CMD_IOR                     0x20
-#define PCI_CMD_IOW                     0x30
-#define PCI_CMD_CONFIG_READ             0xa0
-#define PCI_CMD_CONFIG_WRITE            0xb0
-
-#define PCI_IO_TIMEOUT                  1000
-#define PCI_IO_RETRY                    5
-/* Timeout for IO and CFG accesses.
-   This is in 1/1024 th of a jiffie(=10ms)
-   i.e. approx 10us */
-#define PCI_IO_JIFFIES_TIMEOUT          40
-#define PCI_IO_JIFFIES_SHIFT            10
-
-#define PCI_BYTE_ENABLE_MASK            0x0000000f
-#define PCI_CFG_BUS_SHIFT               16
-#define PCI_CFG_FUNC_SHIFT              8
-#define PCI_CFG_REG_SHIFT               2
-
-#define PCI_BASE                  0x1be00000
-#define PCI_SETUP                 0x00040010
-#define PCI_DIS_REQGNT           (1<<30)
-#define PCI_DIS_REQGNTA          (1<<29)
-#define PCI_DIS_REQGNTB          (1<<28)
-#define PCI_D2_SUPPORT           (1<<27)
-#define PCI_D1_SUPPORT           (1<<26)
-#define PCI_EN_TA                (1<<24)
-#define PCI_EN_PCI2MMI           (1<<23)
-#define PCI_EN_XIO               (1<<22)
-#define PCI_BASE18_PREF          (1<<21)
-#define SIZE_16M                 0x3
-#define SIZE_32M                 0x4
-#define SIZE_64M                 0x5
-#define SIZE_128M                0x6
-#define PCI_SETUP_BASE18_SIZE(X) (X<<18)
-#define PCI_SETUP_BASE18_EN      (1<<17)
-#define PCI_SETUP_BASE14_PREF    (1<<16)
-#define PCI_SETUP_BASE14_SIZE(X) (X<<12)
-#define PCI_SETUP_BASE14_EN      (1<<11)
-#define PCI_SETUP_BASE10_PREF    (1<<10)
-#define PCI_SETUP_BASE10_SIZE(X) (X<<7)
-#define PCI_SETUP_CFGMANAGE_EN   (1<<1)
-#define PCI_SETUP_PCIARB_EN      (1<<0)
-
-#define PCI_CTRL                  0x040014
-#define PCI_SWPB_DCS_PCI         (1<<16)
-#define PCI_SWPB_PCI_PCI         (1<<15)
-#define PCI_SWPB_PCI_DCS         (1<<14)
-#define PCI_REG_WR_POST          (1<<13)
-#define PCI_XIO_WR_POST          (1<<12)
-#define PCI_PCI2_WR_POST         (1<<13)
-#define PCI_PCI1_WR_POST         (1<<12)
-#define PCI_SERR_SEEN            (1<<11)
-#define PCI_B10_SPEC_RD          (1<<6)
-#define PCI_B14_SPEC_RD          (1<<5)
-#define PCI_B18_SPEC_RD          (1<<4)
-#define PCI_B10_NOSUBWORD        (1<<3)
-#define PCI_B14_NOSUBWORD        (1<<2)
-#define PCI_B18_NOSUBWORD        (1<<1)
-#define PCI_RETRY_TMREN          (1<<0)
-
-#define PCI_BASE1_LO              0x040018
-#define PCI_BASE1_HI              0x04001C
-#define PCI_BASE2_LO              0x040020
-#define PCI_BASE2_HI              0x040024
-#define PCI_RDLIFETIM             0x040028
-#define PCI_GPPM_ADDR             0x04002C
-#define PCI_GPPM_WDAT             0x040030
-#define PCI_GPPM_RDAT             0x040034
-#define PCI_GPPM_CTRL             0x040038
-#define GPPM_DONE                (1<<10)
-#define INIT_PCI_CYCLE           (1<<9)
-#define GPPM_CMD(X)              (((X)&0xf)<<4)
-#define GPPM_BYTEEN(X)           ((X)&0xf)
-#define PCI_UNLOCKREG             0x04003C
-#define UNLOCK_SSID(X)           (((X)&0xff)<<8)
-#define UNLOCK_SETUP(X)          (((X)&0xff)<<0)
-#define UNLOCK_MAGIC             0xCA
-#define PCI_DEV_VEND_ID           0x040040
-#define DEVICE_ID(X)             (((X)>>16)&0xffff)
-#define VENDOR_ID(X)             (((X)&0xffff))
-#define PCI_CFG_CMDSTAT           0x040044
-#define PCI_CFG_STATUS(X)            (((X)>>16)&0xffff)
-#define PCI_CFG_COMMAND(X)           ((X)&0xffff)
-#define PCI_CLASS_REV             0x040048
-#define PCI_CLASSCODE(X)         (((X)>>8)&0xffffff)
-#define PCI_REVID(X)             ((X)&0xff)
-#define PCI_LAT_TMR     0x04004c
-#define PCI_BASE10      0x040050
-#define PCI_BASE14      0x040054
-#define PCI_BASE18      0x040058
-#define PCI_SUBSYS_ID   0x04006c
-#define PCI_CAP_PTR     0x040074
-#define PCI_CFG_MISC    0x04007c
-#define PCI_PMC         0x040080
-#define PCI_PWR_STATE   0x040084
-#define PCI_IO          0x040088
-#define PCI_SLVTUNING   0x04008C
-#define PCI_DMATUNING   0x040090
-#define PCI_DMAEADDR    0x040800
-#define PCI_DMAIADDR    0x040804
-#define PCI_DMALEN      0x040808
-#define PCI_DMACTRL     0x04080C
-#define PCI_XIOCTRL     0x040810
-#define PCI_SEL0PROF    0x040814
-#define PCI_SEL1PROF    0x040818
-#define PCI_SEL2PROF    0x04081C
-#define PCI_GPXIOADDR   0x040820
-#define PCI_NANDCTRLS   0x400830
-#define PCI_SEL3PROF    0x040834
-#define PCI_SEL4PROF    0x040838
-#define PCI_GPXIO_STAT  0x040FB0
-#define PCI_GPXIO_IMASK 0x040FB4
-#define PCI_GPXIO_ICLR  0x040FB8
-#define PCI_GPXIO_ISET  0x040FBC
-#define PCI_GPPM_STATUS 0x040FC0
-#define GPPM_DONE      (1<<10)
-#define GPPM_ERR       (1<<9)
-#define GPPM_MPAR_ERR  (1<<8)
-#define GPPM_PAR_ERR   (1<<7)
-#define GPPM_R_MABORT  (1<<2)
-#define GPPM_R_TABORT  (1<<1)
-#define PCI_GPPM_IMASK  0x040FC4
-#define PCI_GPPM_ICLR   0x040FC8
-#define PCI_GPPM_ISET   0x040FCC
-#define PCI_DMA_STATUS  0x040FD0
-#define PCI_DMA_IMASK   0x040FD4
-#define PCI_DMA_ICLR    0x040FD8
-#define PCI_DMA_ISET    0x040FDC
-#define PCI_ISTATUS     0x040FE0
-#define PCI_IMASK       0x040FE4
-#define PCI_ICLR        0x040FE8
-#define PCI_ISET        0x040FEC
-#define PCI_MOD_ID      0x040FFC
-
-/*
- *  PCI configuration cycle AD bus definition
- */
-/* Type 0 */
-#define PCI_CFG_TYPE0_REG_SHF           0
-#define PCI_CFG_TYPE0_FUNC_SHF          8
-
-/* Type 1 */
-#define PCI_CFG_TYPE1_REG_SHF           0
-#define PCI_CFG_TYPE1_FUNC_SHF          8
-#define PCI_CFG_TYPE1_DEV_SHF           11
-#define PCI_CFG_TYPE1_BUS_SHF           16
-
-/*
- *  Ethernet device DP83816 definition
- */
-#define DP83816_IRQ_ETHER               66
-
-#endif
diff --git a/include/asm-mips/mach-pnx8550/uart.h b/include/asm-mips/mach-pnx8550/uart.h
deleted file mode 100644
index ad7608d44874..000000000000
--- a/include/asm-mips/mach-pnx8550/uart.h
+++ /dev/null
@@ -1,30 +0,0 @@
-#ifndef __IP3106_UART_H
-#define __IP3106_UART_H
-
-#include <int.h>
-
-/* early macros for kgdb use. fixme: clean this up */
-
-#define UART_BASE               0xbbe4a000      /* PNX8550 */
-
-#define PNX8550_UART_PORT0      (UART_BASE)
-#define PNX8550_UART_PORT1      (UART_BASE + 0x1000)
-
-#define PNX8550_UART_INT(x)             (PNX8550_INT_GIC_MIN+19+x)
-#define IRQ_TO_UART(x)                  (x-PNX8550_INT_GIC_MIN-19)
-
-/* early macros needed for prom/kgdb */
-
-#define ip3106_lcr(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0x000)
-#define ip3106_mcr(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x004)
-#define ip3106_baud(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x008)
-#define ip3106_cfg(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0x00C)
-#define ip3106_fifo(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0x028)
-#define ip3106_istat(base, port) *(volatile u32 *)(base+(port*0x1000) + 0xFE0)
-#define ip3106_ien(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFE4)
-#define ip3106_iclr(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFE8)
-#define ip3106_iset(base, port)  *(volatile u32 *)(base+(port*0x1000) + 0xFEC)
-#define ip3106_pd(base, port)    *(volatile u32 *)(base+(port*0x1000) + 0xFF4)
-#define ip3106_mid(base, port)   *(volatile u32 *)(base+(port*0x1000) + 0xFFC)
-
-#endif
diff --git a/include/asm-mips/mach-pnx8550/usb.h b/include/asm-mips/mach-pnx8550/usb.h
deleted file mode 100644
index 483b7fc65d41..000000000000
--- a/include/asm-mips/mach-pnx8550/usb.h
+++ /dev/null
@@ -1,32 +0,0 @@
-/*
- *
- * BRIEF MODULE DESCRIPTION
- *  USB specific definitions
- *
- * Author: source@mvista.com
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-
-#ifndef __PNX8550_USB_H
-#define __PNX8550_USB_H
-
-/*
- * USB Host controller
- */
-
-#define PNX8550_USB_OHCI_OP_BASE        0x1be48000
-#define PNX8550_USB_OHCI_OP_LEN         0x1000
-
-#endif
diff --git a/include/asm-mips/mach-pnx8550/war.h b/include/asm-mips/mach-pnx8550/war.h
deleted file mode 100644
index d0458dd082f9..000000000000
--- a/include/asm-mips/mach-pnx8550/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_PNX8550_WAR_H
-#define __ASM_MIPS_MACH_PNX8550_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_PNX8550_WAR_H */
diff --git a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h b/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
deleted file mode 100644
index f3bc7efa2608..000000000000
--- a/include/asm-mips/mach-rc32434/cpu-feature-overrides.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  IDT RC32434 specific CPU feature overrides
- *
- *  Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This file was derived from: include/asm-mips/cpu-features.h
- *      Copyright (C) 2003, 2004 Ralf Baechle
- *      Copyright (C) 2004 Maciej W. Rozycki
- *
- *  This program is free software; you can redistribute it and/or
- *  modify it under the terms of the GNU General Public License
- *  as published by the Free Software Foundation; either version 2
- *  of the License, or (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the
- *  Free Software Foundation, Inc., 51 Franklin Street, Fifth Floor,
- *  Boston, MA  02110-1301, USA.
- */
-#ifndef __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H
-
-/*
- * The IDT RC32434 SOC has a built-in MIPS 4Kc core.
- */
-#define cpu_has_tlb                     1
-#define cpu_has_4kex                    1
-#define cpu_has_3k_cache                0
-#define cpu_has_4k_cache                1
-#define cpu_has_tx39_cache              0
-#define cpu_has_sb1_cache               0
-#define cpu_has_fpu                     0
-#define cpu_has_32fpr                   0
-#define cpu_has_counter                 1
-#define cpu_has_watch                   1
-#define cpu_has_divec                   1
-#define cpu_has_vce                     0
-#define cpu_has_cache_cdex_p            0
-#define cpu_has_cache_cdex_s            0
-#define cpu_has_prefetch                1
-#define cpu_has_mcheck                  1
-#define cpu_has_ejtag                   1
-#define cpu_has_llsc                    1
-
-#define cpu_has_mips16                  0
-#define cpu_has_mdmx                    0
-#define cpu_has_mips3d                  0
-#define cpu_has_smartmips               0
-
-#define cpu_has_vtag_icache             0
-/* #define cpu_has_dc_aliases           ? */
-/* #define cpu_has_ic_fills_f_dc        ? */
-/* #define cpu_has_pindexed_dcache      ? */
-
-/* #define cpu_icache_snoops_remote_store       ? */
-
-#define cpu_has_mips32r1                1
-#define cpu_has_mips32r2                0
-#define cpu_has_mips64r1                0
-#define cpu_has_mips64r2                0
-
-#define cpu_has_dsp                     0
-#define cpu_has_mipsmt                  0
-
-/* #define cpu_has_nofpuex              ? */
-#define cpu_has_64bits                  0
-#define cpu_has_64bit_zero_reg          0
-#define cpu_has_64bit_gp_regs           0
-#define cpu_has_64bit_addresses         0
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()          16
-#define cpu_icache_line_size()          16
-
-#endif /* __ASM_MACH_RC32434_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rc32434/ddr.h b/include/asm-mips/mach-rc32434/ddr.h
deleted file mode 100644
index 291e2cf9dde0..000000000000
--- a/include/asm-mips/mach-rc32434/ddr.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- *  Definitions for the DDR registers
- *
- *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef _ASM_RC32434_DDR_H_
-#define _ASM_RC32434_DDR_H_
-
-#include <asm/mach-rc32434/rb.h>
-
-/* DDR register structure */
-struct ddr_ram {
-        u32 ddrbase;
-        u32 ddrmask;
-        u32 res1;
-        u32 res2;
-        u32 ddrc;
-        u32 ddrabase;
-        u32 ddramask;
-        u32 ddramap;
-        u32 ddrcust;
-        u32 ddrrdc;
-        u32 ddrspare;
-};
-
-#define DDR0_PHYS_ADDR          0x18018000
-
-/* DDR banks masks */
-#define DDR_MASK                0xffff0000
-#define DDR0_BASE_MSK           DDR_MASK
-#define DDR1_BASE_MSK           DDR_MASK
-
-/* DDR bank0 registers */
-#define RC32434_DDR0_ATA_BIT            5
-#define RC32434_DDR0_ATA_MSK            0x000000E0
-#define RC32434_DDR0_DBW_BIT            8
-#define RC32434_DDR0_DBW_MSK            0x00000100
-#define RC32434_DDR0_WR_BIT             9
-#define RC32434_DDR0_WR_MSK             0x00000600
-#define RC32434_DDR0_PS_BIT             11
-#define RC32434_DDR0_PS_MSK             0x00001800
-#define RC32434_DDR0_DTYPE_BIT          13
-#define RC32434_DDR0_DTYPE_MSK          0x0000e000
-#define RC32434_DDR0_RFC_BIT            16
-#define RC32434_DDR0_RFC_MSK            0x000f0000
-#define RC32434_DDR0_RP_BIT             20
-#define RC32434_DDR0_RP_MSK             0x00300000
-#define RC32434_DDR0_AP_BIT             22
-#define RC32434_DDR0_AP_MSK             0x00400000
-#define RC32434_DDR0_RCD_BIT            23
-#define RC32434_DDR0_RCD_MSK            0x01800000
-#define RC32434_DDR0_CL_BIT             25
-#define RC32434_DDR0_CL_MSK             0x06000000
-#define RC32434_DDR0_DBM_BIT            27
-#define RC32434_DDR0_DBM_MSK            0x08000000
-#define RC32434_DDR0_SDS_BIT            28
-#define RC32434_DDR0_SDS_MSK            0x10000000
-#define RC32434_DDR0_ATP_BIT            29
-#define RC32434_DDR0_ATP_MSK            0x60000000
-#define RC32434_DDR0_RE_BIT             31
-#define RC32434_DDR0_RE_MSK             0x80000000
-
-/* DDR bank C registers */
-#define RC32434_DDRC_MSK(x)             BIT_TO_MASK(x)
-#define RC32434_DDRC_CES_BIT            0
-#define RC32434_DDRC_ACE_BIT            1
-
-/* Custom DDR bank registers */
-#define RC32434_DCST_MSK(x)             BIT_TO_MASK(x)
-#define RC32434_DCST_CS_BIT             0
-#define RC32434_DCST_CS_MSK             0x00000003
-#define RC32434_DCST_WE_BIT             2
-#define RC32434_DCST_RAS_BIT            3
-#define RC32434_DCST_CAS_BIT            4
-#define RC32434_DSCT_CKE_BIT            5
-#define RC32434_DSCT_BA_BIT             6
-#define RC32434_DSCT_BA_MSK             0x000000c0
-
-/* DDR QSC registers */
-#define RC32434_QSC_DM_BIT              0
-#define RC32434_QSC_DM_MSK              0x00000003
-#define RC32434_QSC_DQSBS_BIT           2
-#define RC32434_QSC_DQSBS_MSK           0x000000fc
-#define RC32434_QSC_DB_BIT              8
-#define RC32434_QSC_DB_MSK              0x00000100
-#define RC32434_QSC_DBSP_BIT            9
-#define RC32434_QSC_DBSP_MSK            0x01fffe00
-#define RC32434_QSC_BDP_BIT             25
-#define RC32434_QSC_BDP_MSK             0x7e000000
-
-/* DDR LLC registers */
-#define RC32434_LLC_EAO_BIT             0
-#define RC32434_LLC_EAO_MSK             0x00000001
-#define RC32434_LLC_EO_BIT              1
-#define RC32434_LLC_EO_MSK              0x0000003e
-#define RC32434_LLC_FS_BIT              6
-#define RC32434_LLC_FS_MSK              0x000000c0
-#define RC32434_LLC_AS_BIT              8
-#define RC32434_LLC_AS_MSK              0x00000700
-#define RC32434_LLC_SP_BIT              11
-#define RC32434_LLC_SP_MSK              0x001ff800
-
-/* DDR LLFC registers */
-#define RC32434_LLFC_MSK(x)             BIT_TO_MASK(x)
-#define RC32434_LLFC_MEN_BIT            0
-#define RC32434_LLFC_EAN_BIT            1
-#define RC32434_LLFC_FF_BIT             2
-
-/* DDR DLLTA registers */
-#define RC32434_DLLTA_ADDR_BIT          2
-#define RC32434_DLLTA_ADDR_MSK          0xfffffffc
-
-/* DDR DLLED registers */
-#define RC32434_DLLED_MSK(x)            BIT_TO_MASK(x)
-#define RC32434_DLLED_DBE_BIT           0
-#define RC32434_DLLED_DTE_BIT           1
-
-#endif  /* _ASM_RC32434_DDR_H_ */
diff --git a/include/asm-mips/mach-rc32434/dma.h b/include/asm-mips/mach-rc32434/dma.h
deleted file mode 100644
index 5f898b5873f7..000000000000
--- a/include/asm-mips/mach-rc32434/dma.h
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- *              All rights reserved.
- *
- * DMA register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date   : 20011005
- */
-
-#ifndef __ASM_RC32434_DMA_H
-#define __ASM_RC32434_DMA_H
-
-#include <asm/mach-rc32434/rb.h>
-
-#define DMA0_BASE_ADDR                  0x18040000
-
-/*
- * DMA descriptor (in physical memory).
- */
-
-struct dma_desc {
-        u32 control;                    /* Control. use DMAD_* */
-        u32 ca;                         /* Current Address. */
-        u32 devcs;                      /* Device control and status. */
-        u32 link;                       /* Next descriptor in chain. */
-};
-
-#define DMA_DESC_SIZ                    sizeof(struct dma_desc)
-#define DMA_DESC_COUNT_BIT              0
-#define DMA_DESC_COUNT_MSK              0x0003ffff
-#define DMA_DESC_DS_BIT                 20
-#define DMA_DESC_DS_MSK                 0x00300000
-
-#define DMA_DESC_DEV_CMD_BIT            22
-#define DMA_DESC_DEV_CMD_MSK            0x01c00000
-
-/* DMA command sizes */
-#define DMA_DESC_DEV_CMD_BYTE           0
-#define DMA_DESC_DEV_CMD_HLF_WD         1
-#define DMA_DESC_DEV_CMD_WORD           2
-#define DMA_DESC_DEV_CMD_2WORDS         3
-#define DMA_DESC_DEV_CMD_4WORDS         4
-#define DMA_DESC_DEV_CMD_6WORDS         5
-#define DMA_DESC_DEV_CMD_8WORDS         6
-#define DMA_DESC_DEV_CMD_16WORDS        7
-
-/* DMA descriptors interrupts */
-#define DMA_DESC_COF                    (1 << 25) /* Chain on finished */
-#define DMA_DESC_COD                    (1 << 26) /* Chain on done */
-#define DMA_DESC_IOF                    (1 << 27) /* Interrupt on finished */
-#define DMA_DESC_IOD                    (1 << 28) /* Interrupt on done */
-#define DMA_DESC_TERM                   (1 << 29) /* Terminated */
-#define DMA_DESC_DONE                   (1 << 30) /* Done */
-#define DMA_DESC_FINI                   (1 << 31) /* Finished */
-
-/*
- * DMA register (within Internal Register Map).
- */
-
-struct dma_reg {
-        u32 dmac;               /* Control. */
-        u32 dmas;               /* Status. */
-        u32 dmasm;              /* Mask. */
-        u32 dmadptr;            /* Descriptor pointer. */
-        u32 dmandptr;           /* Next descriptor pointer. */
-};
-
-/* DMA channels specific registers */
-#define DMA_CHAN_RUN_BIT                (1 << 0)
-#define DMA_CHAN_DONE_BIT               (1 << 1)
-#define DMA_CHAN_MODE_BIT               (1 << 2)
-#define DMA_CHAN_MODE_MSK               0x0000000c
-#define  DMA_CHAN_MODE_AUTO             0
-#define  DMA_CHAN_MODE_BURST            1
-#define  DMA_CHAN_MODE_XFRT             2
-#define  DMA_CHAN_MODE_RSVD             3
-#define DMA_CHAN_ACT_BIT                (1 << 4)
-
-/* DMA status registers */
-#define DMA_STAT_FINI                   (1 << 0)
-#define DMA_STAT_DONE                   (1 << 1)
-#define DMA_STAT_CHAIN                  (1 << 2)
-#define DMA_STAT_ERR                    (1 << 3)
-#define DMA_STAT_HALT                   (1 << 4)
-
-/*
- * DMA channel definitions
- */
-
-#define DMA_CHAN_ETH_RCV                0
-#define DMA_CHAN_ETH_XMT                1
-#define DMA_CHAN_MEM_TO_FIFO            2
-#define DMA_CHAN_FIFO_TO_MEM            3
-#define DMA_CHAN_PCI_TO_MEM             4
-#define DMA_CHAN_MEM_TO_PCI             5
-#define DMA_CHAN_COUNT                  6
-
-struct dma_channel {
-        struct dma_reg ch[DMA_CHAN_COUNT];
-};
-
-#endif  /* __ASM_RC32434_DMA_H */
diff --git a/include/asm-mips/mach-rc32434/dma_v.h b/include/asm-mips/mach-rc32434/dma_v.h
deleted file mode 100644
index 173a9f9146cd..000000000000
--- a/include/asm-mips/mach-rc32434/dma_v.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- *              All rights reserved.
- *
- * DMA register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date   : 20011005
- */
-
-#ifndef _ASM_RC32434_DMA_V_H_
-#define _ASM_RC32434_DMA_V_H_
-
-#include  <asm/mach-rc32434/dma.h>
-#include  <asm/mach-rc32434/rc32434.h>
-
-#define DMA_CHAN_OFFSET         0x14
-#define IS_DMA_USED(X)          (((X) & \
-                                (DMA_DESC_FINI | DMA_DESC_DONE | DMA_DESC_TERM)) \
-                                != 0)
-#define DMA_COUNT(count)        ((count) & DMA_DESC_COUNT_MSK)
-
-#define DMA_HALT_TIMEOUT        500
-
-static inline int rc32434_halt_dma(struct dma_reg *ch)
-{
-        int timeout = 1;
-        if (__raw_readl(&ch->dmac) & DMA_CHAN_RUN_BIT) {
-                __raw_writel(0, &ch->dmac);
-                for (timeout = DMA_HALT_TIMEOUT; timeout > 0; timeout--) {
-                        if (__raw_readl(&ch->dmas) & DMA_STAT_HALT) {
-                                __raw_writel(0, &ch->dmas);
-                                break;
-                        }
-                }
-        }
-
-        return timeout ? 0 : 1;
-}
-
-static inline void rc32434_start_dma(struct dma_reg *ch, u32 dma_addr)
-{
-        __raw_writel(0, &ch->dmandptr);
-        __raw_writel(dma_addr, &ch->dmadptr);
-}
-
-static inline void rc32434_chain_dma(struct dma_reg *ch, u32 dma_addr)
-{
-        __raw_writel(dma_addr, &ch->dmandptr);
-}
-
-#endif  /* _ASM_RC32434_DMA_V_H_ */
diff --git a/include/asm-mips/mach-rc32434/eth.h b/include/asm-mips/mach-rc32434/eth.h
deleted file mode 100644
index a25cbc56173d..000000000000
--- a/include/asm-mips/mach-rc32434/eth.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- *  Definitions for the Ethernet registers
- *
- *  Copyright 2002 Allend Stichter <allen.stichter@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_RC32434_ETH_H
-#define __ASM_RC32434_ETH_H
-
-
-#define ETH0_BASE_ADDR          0x18060000
-
-struct eth_regs {
-        u32 ethintfc;
-        u32 ethfifott;
-        u32 etharc;
-        u32 ethhash0;
-        u32 ethhash1;
-        u32 ethu0[4];           /* Reserved. */
-        u32 ethpfs;
-        u32 ethmcp;
-        u32 eth_u1[10];         /* Reserved. */
-        u32 ethspare;
-        u32 eth_u2[42];         /* Reserved. */
-        u32 ethsal0;
-        u32 ethsah0;
-        u32 ethsal1;
-        u32 ethsah1;
-        u32 ethsal2;
-        u32 ethsah2;
-        u32 ethsal3;
-        u32 ethsah3;
-        u32 ethrbc;
-        u32 ethrpc;
-        u32 ethrupc;
-        u32 ethrfc;
-        u32 ethtbc;
-        u32 ethgpf;
-        u32 eth_u9[50];         /* Reserved. */
-        u32 ethmac1;
-        u32 ethmac2;
-        u32 ethipgt;
-        u32 ethipgr;
-        u32 ethclrt;
-        u32 ethmaxf;
-        u32 eth_u10;            /* Reserved. */
-        u32 ethmtest;
-        u32 miimcfg;
-        u32 miimcmd;
-        u32 miimaddr;
-        u32 miimwtd;
-        u32 miimrdd;
-        u32 miimind;
-        u32 eth_u11;            /* Reserved. */
-        u32 eth_u12;            /* Reserved. */
-        u32 ethcfsa0;
-        u32 ethcfsa1;
-        u32 ethcfsa2;
-};
-
-/* Ethernet interrupt registers */
-#define ETH_INT_FC_EN           (1 << 0)
-#define ETH_INT_FC_ITS          (1 << 1)
-#define ETH_INT_FC_RIP          (1 << 2)
-#define ETH_INT_FC_JAM          (1 << 3)
-#define ETH_INT_FC_OVR          (1 << 4)
-#define ETH_INT_FC_UND          (1 << 5)
-#define ETH_INT_FC_IOC          0x000000c0
-
-/* Ethernet FIFO registers */
-#define ETH_FIFI_TT_TTH_BIT     0
-#define ETH_FIFO_TT_TTH         0x0000007f
-
-/* Ethernet ARC/multicast registers */
-#define ETH_ARC_PRO             (1 << 0)
-#define ETH_ARC_AM              (1 << 1)
-#define ETH_ARC_AFM             (1 << 2)
-#define ETH_ARC_AB              (1 << 3)
-
-/* Ethernet SAL registers */
-#define ETH_SAL_BYTE_5          0x000000ff
-#define ETH_SAL_BYTE_4          0x0000ff00
-#define ETH_SAL_BYTE_3          0x00ff0000
-#define ETH_SAL_BYTE_2          0xff000000
-
-/* Ethernet SAH registers */
-#define ETH_SAH_BYTE1           0x000000ff
-#define ETH_SAH_BYTE0           0x0000ff00
-
-/* Ethernet GPF register */
-#define ETH_GPF_PTV             0x0000ffff
-
-/* Ethernet PFG register */
-#define ETH_PFS_PFD             (1 << 0)
-
-/* Ethernet CFSA[0-3] registers */
-#define ETH_CFSA0_CFSA4         0x000000ff
-#define ETH_CFSA0_CFSA5         0x0000ff00
-#define ETH_CFSA1_CFSA2         0x000000ff
-#define ETH_CFSA1_CFSA3         0x0000ff00
-#define ETH_CFSA1_CFSA0         0x000000ff
-#define ETH_CFSA1_CFSA1         0x0000ff00
-
-/* Ethernet MAC1 registers */
-#define ETH_MAC1_RE             (1 << 0)
-#define ETH_MAC1_PAF            (1 << 1)
-#define ETH_MAC1_RFC            (1 << 2)
-#define ETH_MAC1_TFC            (1 << 3)
-#define ETH_MAC1_LB             (1 << 4)
-#define ETH_MAC1_MR             (1 << 31)
-
-/* Ethernet MAC2 registers */
-#define ETH_MAC2_FD             (1 << 0)
-#define ETH_MAC2_FLC            (1 << 1)
-#define ETH_MAC2_HFE            (1 << 2)
-#define ETH_MAC2_DC             (1 << 3)
-#define ETH_MAC2_CEN            (1 << 4)
-#define ETH_MAC2_PE             (1 << 5)
-#define ETH_MAC2_VPE            (1 << 6)
-#define ETH_MAC2_APE            (1 << 7)
-#define ETH_MAC2_PPE            (1 << 8)
-#define ETH_MAC2_LPE            (1 << 9)
-#define ETH_MAC2_NB             (1 << 12)
-#define ETH_MAC2_BP             (1 << 13)
-#define ETH_MAC2_ED             (1 << 14)
-
-/* Ethernet IPGT register */
-#define ETH_IPGT                0x0000007f
-
-/* Ethernet IPGR registers */
-#define ETH_IPGR_IPGR2          0x0000007f
-#define ETH_IPGR_IPGR1          0x00007f00
-
-/* Ethernet CLRT registers */
-#define ETH_CLRT_MAX_RET        0x0000000f
-#define ETH_CLRT_COL_WIN        0x00003f00
-
-/* Ethernet MAXF register */
-#define ETH_MAXF                0x0000ffff
-
-/* Ethernet test registers */
-#define ETH_TEST_REG            (1 << 2)
-#define ETH_MCP_DIV             0x000000ff
-
-/* MII registers */
-#define ETH_MII_CFG_RSVD        0x0000000c
-#define ETH_MII_CMD_RD          (1 << 0)
-#define ETH_MII_CMD_SCN         (1 << 1)
-#define ETH_MII_REG_ADDR        0x0000001f
-#define ETH_MII_PHY_ADDR        0x00001f00
-#define ETH_MII_WTD_DATA        0x0000ffff
-#define ETH_MII_RDD_DATA        0x0000ffff
-#define ETH_MII_IND_BSY         (1 << 0)
-#define ETH_MII_IND_SCN         (1 << 1)
-#define ETH_MII_IND_NV          (1 << 2)
-
-/*
- * Values for the DEVCS field of the Ethernet DMA Rx and Tx descriptors.
- */
-
-#define ETH_RX_FD               (1 << 0)
-#define ETH_RX_LD               (1 << 1)
-#define ETH_RX_ROK              (1 << 2)
-#define ETH_RX_FM               (1 << 3)
-#define ETH_RX_MP               (1 << 4)
-#define ETH_RX_BP               (1 << 5)
-#define ETH_RX_VLT              (1 << 6)
-#define ETH_RX_CF               (1 << 7)
-#define ETH_RX_OVR              (1 << 8)
-#define ETH_RX_CRC              (1 << 9)
-#define ETH_RX_CV               (1 << 10)
-#define ETH_RX_DB               (1 << 11)
-#define ETH_RX_LE               (1 << 12)
-#define ETH_RX_LOR              (1 << 13)
-#define ETH_RX_CES              (1 << 14)
-#define ETH_RX_LEN_BIT          16
-#define ETH_RX_LEN              0xffff0000
-
-#define ETH_TX_FD               (1 << 0)
-#define ETH_TX_LD               (1 << 1)
-#define ETH_TX_OEN              (1 << 2)
-#define ETH_TX_PEN              (1 << 3)
-#define ETH_TX_CEN              (1 << 4)
-#define ETH_TX_HEN              (1 << 5)
-#define ETH_TX_TOK              (1 << 6)
-#define ETH_TX_MP               (1 << 7)
-#define ETH_TX_BP               (1 << 8)
-#define ETH_TX_UND              (1 << 9)
-#define ETH_TX_OF               (1 << 10)
-#define ETH_TX_ED               (1 << 11)
-#define ETH_TX_EC               (1 << 12)
-#define ETH_TX_LC               (1 << 13)
-#define ETH_TX_TD               (1 << 14)
-#define ETH_TX_CRC              (1 << 15)
-#define ETH_TX_LE               (1 << 16)
-#define ETH_TX_CC               0x001E0000
-
-#endif  /* __ASM_RC32434_ETH_H */
diff --git a/include/asm-mips/mach-rc32434/gpio.h b/include/asm-mips/mach-rc32434/gpio.h
deleted file mode 100644
index f946f5f45bbb..000000000000
--- a/include/asm-mips/mach-rc32434/gpio.h
+++ /dev/null
@@ -1,126 +0,0 @@
-/*
- * Copyright 2002 Integrated Device Technology, Inc.
- *      All rights reserved.
- *
- * GPIO register definition.
- *
- * Author : ryan.holmQVist@idt.com
- * Date   : 20011005
- * Copyright (C) 2001, 2002 Ryan Holm <ryan.holmQVist@idt.com>
- * Copyright (C) 2008 Florian Fainelli <florian@openwrt.org>
- */
-
-#ifndef _RC32434_GPIO_H_
-#define _RC32434_GPIO_H_
-
-#include <linux/types.h>
-
-struct rb532_gpio_reg {
-        u32   gpiofunc;   /* GPIO Function Register
-                           * gpiofunc[x]==0 bit = gpio
-                           * func[x]==1  bit = altfunc
-                           */
-        u32   gpiocfg;    /* GPIO Configuration Register
-                           * gpiocfg[x]==0 bit = input
-                           * gpiocfg[x]==1 bit = output
-                           */
-        u32   gpiod;      /* GPIO Data Register
-                           * gpiod[x] read/write gpio pinX status
-                           */
-        u32   gpioilevel; /* GPIO Interrupt Status Register
-                           * interrupt level (see gpioistat)
-                           */
-        u32   gpioistat;  /* Gpio Interrupt Status Register
-                           * istat[x] = (gpiod[x] == level[x])
-                           * cleared in ISR (STICKY bits)
-                           */
-        u32   gpionmien;  /* GPIO Non-maskable Interrupt Enable Register */
-};
-
-/* UART GPIO signals */
-#define RC32434_UART0_SOUT      (1 << 0)
-#define RC32434_UART0_SIN       (1 << 1)
-#define RC32434_UART0_RTS       (1 << 2)
-#define RC32434_UART0_CTS       (1 << 3)
-
-/* M & P bus GPIO signals */
-#define RC32434_MP_BIT_22       (1 << 4)
-#define RC32434_MP_BIT_23       (1 << 5)
-#define RC32434_MP_BIT_24       (1 << 6)
-#define RC32434_MP_BIT_25       (1 << 7)
-
-/* CPU GPIO signals */
-#define RC32434_CPU_GPIO        (1 << 8)
-
-/* Reserved GPIO signals */
-#define RC32434_AF_SPARE_6      (1 << 9)
-#define RC32434_AF_SPARE_4      (1 << 10)
-#define RC32434_AF_SPARE_3      (1 << 11)
-#define RC32434_AF_SPARE_2      (1 << 12)
-
-/* PCI messaging unit */
-#define RC32434_PCI_MSU_GPIO    (1 << 13)
-
-
-extern void set_434_reg(unsigned reg_offs, unsigned bit, unsigned len, unsigned val);
-extern unsigned get_434_reg(unsigned reg_offs);
-extern void set_latch_u5(unsigned char or_mask, unsigned char nand_mask);
-extern unsigned char get_latch_u5(void);
-
-extern int rb532_gpio_get_value(unsigned gpio);
-extern void rb532_gpio_set_value(unsigned gpio, int value);
-extern int rb532_gpio_direction_input(unsigned gpio);
-extern int rb532_gpio_direction_output(unsigned gpio, int value);
-extern void rb532_gpio_set_int_level(unsigned gpio, int value);
-extern int rb532_gpio_get_int_level(unsigned gpio);
-extern void rb532_gpio_set_int_status(unsigned gpio, int value);
-extern int rb532_gpio_get_int_status(unsigned gpio);
-
-
-/* Wrappers for the arch-neutral GPIO API */
-
-static inline int gpio_request(unsigned gpio, const char *label)
-{
-        /* Not yet implemented */
-        return 0;
-}
-
-static inline void gpio_free(unsigned gpio)
-{
-        /* Not yet implemented */
-}
-
-static inline int gpio_direction_input(unsigned gpio)
-{
-        return rb532_gpio_direction_input(gpio);
-}
-
-static inline int gpio_direction_output(unsigned gpio, int value)
-{
-        return rb532_gpio_direction_output(gpio, value);
-}
-
-static inline int gpio_get_value(unsigned gpio)
-{
-        return rb532_gpio_get_value(gpio);
-}
-
-static inline void gpio_set_value(unsigned gpio, int value)
-{
-        rb532_gpio_set_value(gpio, value);
-}
-
-static inline int gpio_to_irq(unsigned gpio)
-{
-        return gpio;
-}
-
-static inline int irq_to_gpio(unsigned irq)
-{
-        return irq;
-}
-
-/* For cansleep */
-#include <asm-generic/gpio.h>
-
-#endif /* _RC32434_GPIO_H_ */
diff --git a/include/asm-mips/mach-rc32434/integ.h b/include/asm-mips/mach-rc32434/integ.h
deleted file mode 100644
index fa65bc3d8807..000000000000
--- a/include/asm-mips/mach-rc32434/integ.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- *  Definitions for the Watchdog registers
- *
- *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __RC32434_INTEG_H__
-#define __RC32434_INTEG_H__
-
-#include <asm/mach-rc32434/rb.h>
-
-#define INTEG0_BASE_ADDR        0x18030030
-
-struct integ {
-        u32 errcs;                      /* sticky use ERRCS_ */
-        u32 wtcount;                    /* Watchdog timer count reg. */
-        u32 wtcompare;                  /* Watchdog timer timeout value. */
-        u32 wtc;                        /* Watchdog timer control. use WTC_ */
-};
-
-/* Error counters */
-#define RC32434_ERR_WTO         0
-#define RC32434_ERR_WNE         1
-#define RC32434_ERR_UCW         2
-#define RC32434_ERR_UCR         3
-#define RC32434_ERR_UPW         4
-#define RC32434_ERR_UPR         5
-#define RC32434_ERR_UDW         6
-#define RC32434_ERR_UDR         7
-#define RC32434_ERR_SAE         8
-#define RC32434_ERR_WRE         9
-
-/* Watchdog control bits */
-#define RC32434_WTC_EN          0
-#define RC32434_WTC_TO          1
-
-#endif  /* __RC32434_INTEG_H__ */
diff --git a/include/asm-mips/mach-rc32434/irq.h b/include/asm-mips/mach-rc32434/irq.h
deleted file mode 100644
index cb9e4725f5dc..000000000000
--- a/include/asm-mips/mach-rc32434/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_RC32434_IRQ_H
-#define __ASM_RC32434_IRQ_H
-
-#define NR_IRQS 256
-
-#include <asm/mach-generic/irq.h>
-
-#endif  /* __ASM_RC32434_IRQ_H */
diff --git a/include/asm-mips/mach-rc32434/pci.h b/include/asm-mips/mach-rc32434/pci.h
deleted file mode 100644
index 410638f2af74..000000000000
--- a/include/asm-mips/mach-rc32434/pci.h
+++ /dev/null
@@ -1,481 +0,0 @@
-/*
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- * Copyright 2004 IDT Inc. (rischelp@idt.com)
- *
- * Initial Release
- */
-
-#ifndef _ASM_RC32434_PCI_H_
-#define _ASM_RC32434_PCI_H_
-
-#define epld_mask ((volatile unsigned char *)0xB900000d)
-
-#define PCI0_BASE_ADDR          0x18080000
-#define PCI_LBA_COUNT           4
-
-struct pci_map {
-        u32 address;            /* Address. */
-        u32 control;            /* Control. */
-        u32 mapping;            /* mapping. */
-};
-
-struct pci_reg {
-        u32 pcic;
-        u32 pcis;
-        u32 pcism;
-        u32 pcicfga;
-        u32 pcicfgd;
-        volatile struct pci_map pcilba[PCI_LBA_COUNT];
-        u32 pcidac;
-        u32 pcidas;
-        u32 pcidasm;
-        u32 pcidad;
-        u32 pcidma8c;
-        u32 pcidma9c;
-        u32 pcitc;
-};
-
-#define PCI_MSU_COUNT           2
-
-struct pci_msu {
-        u32 pciim[PCI_MSU_COUNT];
-        u32 pciom[PCI_MSU_COUNT];
-        u32 pciid;
-        u32 pciiic;
-        u32 pciiim;
-        u32 pciiod;
-        u32 pciioic;
-        u32 pciioim;
-};
-
-/*
- * PCI Control Register
- */
-
-#define PCI_CTL_EN              (1 << 0)
-#define PCI_CTL_TNR             (1 << 1)
-#define PCI_CTL_SCE             (1 << 2)
-#define PCI_CTL_IEN             (1 << 3)
-#define PCI_CTL_AAA             (1 << 4)
-#define PCI_CTL_EAP             (1 << 5)
-#define PCI_CTL_PCIM_BIT        6
-#define PCI_CTL_PCIM            0x000001c0
-
-#define PCI_CTL_PCIM_DIS        0
-#define PCI_CTL_PCIM_TNR        1 /* Satellite - target not ready */
-#define PCI_CTL_PCIM_SUS        2 /* Satellite - suspended CPU. */
-#define PCI_CTL_PCIM_EXT        3 /* Host - external arbiter. */
-#define PCI_CTL PCIM_PRIO       4 /* Host - fixed priority arb. */
-#define PCI_CTL_PCIM_RR         5 /* Host - round robin priority. */
-#define PCI_CTL_PCIM_RSVD6      6
-#define PCI_CTL_PCIM_RSVD7      7
-
-#define PCI_CTL_IGM             (1 << 9)
-
-/*
- * PCI Status Register
- */
-
-#define PCI_STAT_EED            (1 << 0)
-#define PCI_STAT_WR             (1 << 1)
-#define PCI_STAT_NMI            (1 << 2)
-#define PCI_STAT_II             (1 << 3)
-#define PCI_STAT_CWE            (1 << 4)
-#define PCI_STAT_CRE            (1 << 5)
-#define PCI_STAT_MDPE           (1 << 6)
-#define PCI_STAT_STA            (1 << 7)
-#define PCI_STAT_RTA            (1 << 8)
-#define PCI_STAT_RMA            (1 << 9)
-#define PCI_STAT_SSE            (1 << 10)
-#define PCI_STAT_OSE            (1 << 11)
-#define PCI_STAT_PE             (1 << 12)
-#define PCI_STAT_TAE            (1 << 13)
-#define PCI_STAT_RLE            (1 << 14)
-#define PCI_STAT_BME            (1 << 15)
-#define PCI_STAT_PRD            (1 << 16)
-#define PCI_STAT_RIP            (1 << 17)
-
-/*
- * PCI Status Mask Register
- */
-
-#define PCI_STATM_EED           PCI_STAT_EED
-#define PCI_STATM_WR            PCI_STAT_WR
-#define PCI_STATM_NMI           PCI_STAT_NMI
-#define PCI_STATM_II            PCI_STAT_II
-#define PCI_STATM_CWE           PCI_STAT_CWE
-#define PCI_STATM_CRE           PCI_STAT_CRE
-#define PCI_STATM_MDPE          PCI_STAT_MDPE
-#define PCI_STATM_STA           PCI_STAT_STA
-#define PCI_STATM_RTA           PCI_STAT_RTA
-#define PCI_STATM_RMA           PCI_STAT_RMA
-#define PCI_STATM_SSE           PCI_STAT_SSE
-#define PCI_STATM_OSE           PCI_STAT_OSE
-#define PCI_STATM_PE            PCI_STAT_PE
-#define PCI_STATM_TAE           PCI_STAT_TAE
-#define PCI_STATM_RLE           PCI_STAT_RLE
-#define PCI_STATM_BME           PCI_STAT_BME
-#define PCI_STATM_PRD           PCI_STAT_PRD
-#define PCI_STATM_RIP           PCI_STAT_RIP
-
-/*
- * PCI Configuration Address Register
- */
-#define PCI_CFGA_REG_BIT        2
-#define PCI_CFGA_REG            0x000000fc
-#define  PCI_CFGA_REG_ID        (0x00 >> 2)     /* use PCFGID */
-#define  PCI_CFGA_REG_04        (0x04 >> 2)     /* use PCFG04_ */
-#define  PCI_CFGA_REG_08        (0x08 >> 2)     /* use PCFG08_ */
-#define  PCI_CFGA_REG_0C        (0x0C >> 2)     /* use PCFG0C_ */
-#define  PCI_CFGA_REG_PBA0      (0x10 >> 2)     /* use PCIPBA_ */
-#define  PCI_CFGA_REG_PBA1      (0x14 >> 2)     /* use PCIPBA_ */
-#define  PCI_CFGA_REG_PBA2      (0x18 >> 2)     /* use PCIPBA_ */
-#define  PCI_CFGA_REG_PBA3      (0x1c >> 2)     /* use PCIPBA_ */
-#define  PCI_CFGA_REG_SUBSYS    (0x2c >> 2)     /* use PCFGSS_ */
-#define  PCI_CFGA_REG_3C        (0x3C >> 2)     /* use PCFG3C_ */
-#define  PCI_CFGA_REG_PBBA0C    (0x44 >> 2)     /* use PCIPBAC_ */
-#define  PCI_CFGA_REG_PBA0M     (0x48 >> 2)
-#define  PCI_CFGA_REG_PBA1C     (0x4c >> 2)     /* use PCIPBAC_ */
-#define  PCI_CFGA_REG_PBA1M     (0x50 >> 2)
-#define  PCI_CFGA_REG_PBA2C     (0x54 >> 2)     /* use PCIPBAC_ */
-#define  PCI_CFGA_REG_PBA2M     (0x58 >> 2)
-#define  PCI_CFGA_REG_PBA3C     (0x5c >> 2)     /* use PCIPBAC_ */
-#define  PCI_CFGA_REG_PBA3M     (0x60 >> 2)
-#define  PCI_CFGA_REG_PMGT      (0x64 >> 2)
-#define PCI_CFGA_FUNC_BIT       8
-#define PCI_CFGA_FUNC           0x00000700
-#define PCI_CFGA_DEV_BIT        11
-#define PCI_CFGA_DEV            0x0000f800
-#define PCI_CFGA_DEV_INTERN     0
-#define PCI_CFGA_BUS_BIT        16
-#define PCI CFGA_BUS            0x00ff0000
-#define PCI_CFGA_BUS_TYPE0      0
-#define PCI_CFGA_EN             (1 << 31)
-
-/* PCI CFG04 commands */
-#define PCI_CFG04_CMD_IO_ENA    (1 << 0)
-#define PCI_CFG04_CMD_MEM_ENA   (1 << 1)
-#define PCI_CFG04_CMD_BM_ENA    (1 << 2)
-#define PCI_CFG04_CMD_MW_INV    (1 << 4)
-#define PCI_CFG04_CMD_PAR_ENA   (1 << 6)
-#define PCI_CFG04_CMD_SER_ENA   (1 << 8)
-#define PCI_CFG04_CMD_FAST_ENA  (1 << 9)
-
-/* PCI CFG04 status fields */
-#define PCI_CFG04_STAT_BIT      16
-#define PCI_CFG04_STAT          0xffff0000
-#define PCI_CFG04_STAT_66_MHZ   (1 << 21)
-#define PCI_CFG04_STAT_FBB      (1 << 23)
-#define PCI_CFG04_STAT_MDPE     (1 << 24)
-#define PCI_CFG04_STAT_DST      (1 << 25)
-#define PCI_CFG04_STAT_STA      (1 << 27)
-#define PCI_CFG04_STAT_RTA      (1 << 28)
-#define PCI_CFG04_STAT_RMA      (1 << 29)
-#define PCI_CFG04_STAT_SSE      (1 << 30)
-#define PCI_CFG04_STAT_PE       (1 << 31)
-
-#define PCI_PBA_MSI             (1 << 0)
-#define PCI_PBA_P               (1 << 2)
-
-/* PCI PBAC registers */
-#define PCI_PBAC_MSI            (1 << 0)
-#define PCI_PBAC_P              (1 << 1)
-#define PCI_PBAC_SIZE_BIT       2
-#define PCI_PBAC_SIZE           0x0000007c
-#define PCI_PBAC_SB             (1 << 7)
-#define PCI_PBAC_PP             (1 << 8)
-#define PCI_PBAC_MR_BIT         9
-#define PCI_PBAC_MR             0x00000600
-#define  PCI_PBAC_MR_RD         0
-#define  PCI_PBAC_MR_RD_LINE    1
-#define  PCI_PBAC_MR_RD_MULT    2
-#define PCI_PBAC_MRL            (1 << 11)
-#define PCI_PBAC_MRM            (1 << 12)
-#define PCI_PBAC_TRP            (1 << 13)
-
-#define PCI_CFG40_TRDY_TIM      0x000000ff
-#define PCI_CFG40_RET_LIM       0x0000ff00
-
-/*
- * PCI Local Base Address [0|1|2|3] Register
- */
-
-#define PCI_LBA_BADDR_BIT       0
-#define PCI_LBA_BADDR           0xffffff00
-
-/*
- * PCI Local Base Address Control Register
- */
-
-#define PCI_LBAC_MSI            (1 << 0)
-#define  PCI_LBAC_MSI_MEM       0
-#define  PCI_LBAC_MSI_IO        1
-#define PCI_LBAC_SIZE_BIT       2
-#define PCI_LBAC_SIZE           0x0000007c
-#define PCI_LBAC_SB             (1 << 7)
-#define PCI_LBAC_RT             (1 << 8)
-#define  PCI_LBAC_RT_NO_PREF    0
-#define  PCI_LBAC_RT_PREF       1
-
-/*
- * PCI Local Base Address [0|1|2|3] Mapping Register
- */
-#define PCI_LBAM_MADDR_BIT      8
-#define PCI_LBAM_MADDR          0xffffff00
-
-/*
- * PCI Decoupled Access Control Register
- */
-#define PCI_DAC_DEN             (1 << 0)
-
-/*
- * PCI Decoupled Access Status Register
- */
-#define PCI_DAS_D               (1 << 0)
-#define PCI_DAS_B               (1 << 1)
-#define PCI_DAS_E               (1 << 2)
-#define PCI_DAS_OFE             (1 << 3)
-#define PCI_DAS_OFF             (1 << 4)
-#define PCI_DAS_IFE             (1 << 5)
-#define PCI_DAS_IFF             (1 << 6)
-
-/*
- * PCI DMA Channel 8 Configuration Register
- */
-#define PCI_DMA8C_MBS_BIT       0
-#define PCI_DMA8C_MBS           0x00000fff /* Maximum Burst Size. */
-#define PCI_DMA8C_OUR           (1 << 12)
-
-/*
- * PCI DMA Channel 9 Configuration Register
- */
-#define PCI_DMA9C_MBS_BIT       0       /* Maximum Burst Size. */
-#define PCI_DMA9C_MBS           0x00000fff
-
-/*
- * PCI to Memory(DMA Channel 8) AND Memory to PCI DMA(DMA Channel 9)Descriptors
- */
-
-#define PCI_DMAD_PT_BIT         22              /* in DEVCMD field (descriptor) */
-#define PCI_DMAD_PT             0x00c00000      /* preferred transaction field */
-/* These are for reads (DMA channel 8) */
-#define PCI_DMAD_DEVCMD_MR      0               /* memory read */
-#define PCI_DMAD_DEVCMD_MRL     1               /* memory read line */
-#define PCI_DMAD_DEVCMD_MRM     2               /* memory read multiple */
-#define PCI_DMAD_DEVCMD_IOR     3               /* I/O read */
-/* These are for writes (DMA channel 9) */
-#define PCI_DMAD_DEVCMD_MW      0               /* memory write */
-#define PCI_DMAD_DEVCMD_MWI     1               /* memory write invalidate */
-#define PCI_DMAD_DEVCMD_IOW     3               /* I/O write */
-
-/* Swap byte field applies to both DMA channel 8 and 9 */
-#define PCI_DMAD_SB             (1 << 24)       /* swap byte field */
-
-
-/*
- * PCI Target Control Register
- */
-
-#define PCI_TC_RTIMER_BIT       0
-#define PCI_TC_RTIMER           0x000000ff
-#define PCI_TC_DTIMER_BIT       8
-#define PCI_TC_DTIMER           0x0000ff00
-#define PCI_TC_RDR              (1 << 18)
-#define PCI_TC_DDT              (1 << 19)
-
-/*
- * PCI messaging unit [applies to both inbound and outbound registers ]
- */
-#define PCI_MSU_M0              (1 << 0)
-#define PCI_MSU_M1              (1 << 1)
-#define PCI_MSU_DB              (1 << 2)
-
-#define PCI_MSG_ADDR            0xB8088010
-#define PCI0_ADDR               0xB8080000
-#define rc32434_pci ((struct pci_reg *) PCI0_ADDR)
-#define rc32434_pci_msg ((struct pci_msu *) PCI_MSG_ADDR)
-
-#define PCIM_SHFT               0x6
-#define PCIM_BIT_LEN            0x7
-#define PCIM_H_EA               0x3
-#define PCIM_H_IA_FIX           0x4
-#define PCIM_H_IA_RR            0x5
-#if 0
-#define PCI_ADDR_START          0x13000000
-#endif
-
-#define PCI_ADDR_START          0x50000000
-
-#define CPUTOPCI_MEM_WIN        0x02000000
-#define CPUTOPCI_IO_WIN         0x00100000
-#define PCILBA_SIZE_SHFT        2
-#define PCILBA_SIZE_MASK        0x1F
-#define SIZE_256MB              0x1C
-#define SIZE_128MB              0x1B
-#define SIZE_64MB               0x1A
-#define SIZE_32MB               0x19
-#define SIZE_16MB               0x18
-#define SIZE_4MB                0x16
-#define SIZE_2MB                0x15
-#define SIZE_1MB                0x14
-#define KORINA_CONFIG0_ADDR     0x80000000
-#define KORINA_CONFIG1_ADDR     0x80000004
-#define KORINA_CONFIG2_ADDR     0x80000008
-#define KORINA_CONFIG3_ADDR     0x8000000C
-#define KORINA_CONFIG4_ADDR     0x80000010
-#define KORINA_CONFIG5_ADDR     0x80000014
-#define KORINA_CONFIG6_ADDR     0x80000018
-#define KORINA_CONFIG7_ADDR     0x8000001C
-#define KORINA_CONFIG8_ADDR     0x80000020
-#define KORINA_CONFIG9_ADDR     0x80000024
-#define KORINA_CONFIG10_ADDR    0x80000028
-#define KORINA_CONFIG11_ADDR    0x8000002C
-#define KORINA_CONFIG12_ADDR    0x80000030
-#define KORINA_CONFIG13_ADDR    0x80000034
-#define KORINA_CONFIG14_ADDR    0x80000038
-#define KORINA_CONFIG15_ADDR    0x8000003C
-#define KORINA_CONFIG16_ADDR    0x80000040
-#define KORINA_CONFIG17_ADDR    0x80000044
-#define KORINA_CONFIG18_ADDR    0x80000048
-#define KORINA_CONFIG19_ADDR    0x8000004C
-#define KORINA_CONFIG20_ADDR    0x80000050
-#define KORINA_CONFIG21_ADDR    0x80000054
-#define KORINA_CONFIG22_ADDR    0x80000058
-#define KORINA_CONFIG23_ADDR    0x8000005C
-#define KORINA_CONFIG24_ADDR    0x80000060
-#define KORINA_CONFIG25_ADDR    0x80000064
-#define KORINA_CMD              (PCI_CFG04_CMD_IO_ENA | \
-                                 PCI_CFG04_CMD_MEM_ENA | \
-                                 PCI_CFG04_CMD_BM_ENA | \
-                                 PCI_CFG04_CMD_MW_INV | \
-                                 PCI_CFG04_CMD_PAR_ENA | \
-                                 PCI_CFG04_CMD_SER_ENA)
-
-#define KORINA_STAT             (PCI_CFG04_STAT_MDPE | \
-                                 PCI_CFG04_STAT_STA | \
-                                 PCI_CFG04_STAT_RTA | \
-                                 PCI_CFG04_STAT_RMA | \
-                                 PCI_CFG04_STAT_SSE | \
-                                 PCI_CFG04_STAT_PE)
-
-#define KORINA_CNFG1            ((KORINA_STAT<<16)|KORINA_CMD)
-
-#define KORINA_REVID            0
-#define KORINA_CLASS_CODE       0
-#define KORINA_CNFG2            ((KORINA_CLASS_CODE<<8) | \
-                                  KORINA_REVID)
-
-#define KORINA_CACHE_LINE_SIZE  4
-#define KORINA_MASTER_LAT       0x3c
-#define KORINA_HEADER_TYPE      0
-#define KORINA_BIST             0
-
-#define KORINA_CNFG3 ((KORINA_BIST << 24) | \
-                      (KORINA_HEADER_TYPE<<16) | \
-                      (KORINA_MASTER_LAT<<8) | \
-                      KORINA_CACHE_LINE_SIZE)
-
-#define KORINA_BAR0     0x00000008      /* 128 MB Memory */
-#define KORINA_BAR1     0x18800001      /* 1 MB IO */
-#define KORINA_BAR2     0x18000001      /* 2 MB IO window for Korina
-                                           internal Registers */
-#define KORINA_BAR3     0x48000008      /* Spare 128 MB Memory */
-
-#define KORINA_CNFG4    KORINA_BAR0
-#define KORINA_CNFG5    KORINA_BAR1
-#define KORINA_CNFG6    KORINA_BAR2
-#define KORINA_CNFG7    KORINA_BAR3
-
-#define KORINA_SUBSYS_VENDOR_ID 0x011d
-#define KORINA_SUBSYSTEM_ID     0x0214
-#define KORINA_CNFG8            0
-#define KORINA_CNFG9            0
-#define KORINA_CNFG10           0
-#define KORINA_CNFG11   ((KORINA_SUBSYS_VENDOR_ID<<16) | \
-                          KORINA_SUBSYSTEM_ID)
-#define KORINA_INT_LINE         1
-#define KORINA_INT_PIN          1
-#define KORINA_MIN_GNT          8
-#define KORINA_MAX_LAT          0x38
-#define KORINA_CNFG12           0
-#define KORINA_CNFG13           0
-#define KORINA_CNFG14           0
-#define KORINA_CNFG15   ((KORINA_MAX_LAT<<24) | \
-                         (KORINA_MIN_GNT<<16) | \
-                         (KORINA_INT_PIN<<8)  | \
-                          KORINA_INT_LINE)
-#define KORINA_RETRY_LIMIT      0x80
-#define KORINA_TRDY_LIMIT       0x80
-#define KORINA_CNFG16 ((KORINA_RETRY_LIMIT<<8) | \
-                        KORINA_TRDY_LIMIT)
-#define PCI_PBAxC_R             0x0
-#define PCI_PBAxC_RL            0x1
-#define PCI_PBAxC_RM            0x2
-#define SIZE_SHFT               2
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA0C    (PCI_PBAC_MRL | PCI_PBAC_SB | \
-                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
-                          PCI_PBAC_PP | \
-                          (SIZE_128MB<<SIZE_SHFT) | \
-                           PCI_PBAC_P)
-#else
-#define KORINA_PBA0C    (PCI_PBAC_MRL | \
-                          ((PCI_PBAxC_RM & 0x3) << PCI_PBAC_MR_BIT) | \
-                          PCI_PBAC_PP | \
-                          (SIZE_128MB<<SIZE_SHFT) | \
-                           PCI_PBAC_P)
-#endif
-#define KORINA_CNFG17   KORINA_PBA0C
-#define KORINA_PBA0M    0x0
-#define KORINA_CNFG18   KORINA_PBA0M
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | PCI_PBAC_SB | \
-                          PCI_PBAC_MSI)
-#else
-#define KORINA_PBA1C    ((SIZE_1MB<<SIZE_SHFT) | \
-                          PCI_PBAC_MSI)
-#endif
-#define KORINA_CNFG19   KORINA_PBA1C
-#define KORINA_PBA1M    0x0
-#define KORINA_CNFG20   KORINA_PBA1M
-
-#if defined(__MIPSEB__)
-#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | PCI_PBAC_SB | \
-                          PCI_PBAC_MSI)
-#else
-#define KORINA_PBA2C    ((SIZE_2MB<<SIZE_SHFT) | \
-                          PCI_PBAC_MSI)
-#endif
-#define KORINA_CNFG21   KORINA_PBA2C
-#define KORINA_PBA2M    0x18000000
-#define KORINA_CNFG22   KORINA_PBA2M
-#define KORINA_PBA3C    0
-#define KORINA_CNFG23   KORINA_PBA3C
-#define KORINA_PBA3M    0
-#define KORINA_CNFG24   KORINA_PBA3M
-
-#define PCITC_DTIMER_VAL        8
-#define PCITC_RTIMER_VAL        0x10
-
-#endif  /* __ASM_RC32434_PCI_H */
diff --git a/include/asm-mips/mach-rc32434/prom.h b/include/asm-mips/mach-rc32434/prom.h
deleted file mode 100644
index 1d66ddcda89a..000000000000
--- a/include/asm-mips/mach-rc32434/prom.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- *  Definitions for the PROM
- *
- *  Copyright 2002 Ryan Holm <ryan.holmQVist@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#define PROM_ENTRY(x)           (0xbfc00000 + ((x) * 8))
-
-#define GPIO_INIT_NOBUTTON      ""
-#define GPIO_INIT_BUTTON        " 2"
-
-#define SR_NMI                  0x00180000
-#define SERIAL_SPEED_ENTRY      0x00000001
-
-#define FREQ_TAG                "HZ="
-#define GPIO_TAG                "gpio="
-#define KMAC_TAG                "kmac="
-#define MEM_TAG                 "mem="
-#define BOARD_TAG               "board="
-
-#define BOARD_RB532             "500"
-#define BOARD_RB532A            "500r5"
diff --git a/include/asm-mips/mach-rc32434/rb.h b/include/asm-mips/mach-rc32434/rb.h
deleted file mode 100644
index e0a76e3ffea8..000000000000
--- a/include/asm-mips/mach-rc32434/rb.h
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- *  GNU General Public License for more details.
- *
- *  Copyright (C) 2004 IDT Inc.
- *  Copyright (C) 2006 Felix Fietkau <nbd@openwrt.org>
- */
-#ifndef __ASM_RC32434_RB_H
-#define __ASM_RC32434_RB_H
-
-#include <linux/genhd.h>
-
-#define IDT434_REG_BASE ((volatile void *) KSEG1ADDR(0x18000000))
-#define DEV0BASE        0x010000
-#define DEV0MASK        0x010004
-#define DEV0C           0x010008
-#define DEV0T           0x01000C
-#define DEV1BASE        0x010010
-#define DEV1MASK        0x010014
-#define DEV1C           0x010018
-#define DEV1TC          0x01001C
-#define DEV2BASE        0x010020
-#define DEV2MASK        0x010024
-#define DEV2C           0x010028
-#define DEV2TC          0x01002C
-#define DEV3BASE        0x010030
-#define DEV3MASK        0x010034
-#define DEV3C           0x010038
-#define DEV3TC          0x01003C
-#define BTCS            0x010040
-#define BTCOMPARE       0x010044
-#define GPIOBASE        0x050000
-#define GPIOCFG         0x050004
-#define GPIOD           0x050008
-#define GPIOILEVEL      0x05000C
-#define GPIOISTAT       0x050010
-#define GPIONMIEN       0x050014
-#define IMASK6          0x038038
-#define LO_WPX          (1 << 0)
-#define LO_ALE          (1 << 1)
-#define LO_CLE          (1 << 2)
-#define LO_CEX          (1 << 3)
-#define LO_FOFF         (1 << 5)
-#define LO_SPICS        (1 << 6)
-#define LO_ULED         (1 << 7)
-
-#define BIT_TO_MASK(x)  (1 << x)
-
-struct dev_reg {
-        u32     base;
-        u32     mask;
-        u32     ctl;
-        u32     timing;
-};
-
-struct korina_device {
-        char *name;
-        unsigned char mac[6];
-        struct net_device *dev;
-};
-
-struct cf_device {
-        int gpio_pin;
-        void *dev;
-        struct gendisk *gd;
-};
-
-struct mpmc_device {
-        unsigned char   state;
-        spinlock_t      lock;
-        void __iomem    *base;
-};
-
-#endif  /* __ASM_RC32434_RB_H */
diff --git a/include/asm-mips/mach-rc32434/rc32434.h b/include/asm-mips/mach-rc32434/rc32434.h
deleted file mode 100644
index c4a02145104e..000000000000
--- a/include/asm-mips/mach-rc32434/rc32434.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Definitions for IDT RC323434 CPU.
- */
-
-#ifndef _ASM_RC32434_RC32434_H_
-#define _ASM_RC32434_RC32434_H_
-
-#include <linux/delay.h>
-#include <linux/io.h>
-
-#define RC32434_REG_BASE        0x18000000
-#define RC32434_RST             (1 << 15)
-
-#define IDT_CLOCK_MULT          2
-#define MIPS_CPU_TIMER_IRQ      7
-
-/* Interrupt Controller */
-#define IC_GROUP0_PEND          (RC32434_REG_BASE + 0x38000)
-#define IC_GROUP0_MASK          (RC32434_REG_BASE + 0x38008)
-#define IC_GROUP_OFFSET         0x0C
-
-#define NUM_INTR_GROUPS         5
-
-/* 16550 UARTs */
-#define GROUP0_IRQ_BASE         8       /* GRP2 IRQ numbers start here */
-                                        /* GRP3 IRQ numbers start here */
-#define GROUP1_IRQ_BASE         (GROUP0_IRQ_BASE + 32)
-                                        /* GRP4 IRQ numbers start here */
-#define GROUP2_IRQ_BASE         (GROUP1_IRQ_BASE + 32)
-                                        /* GRP5 IRQ numbers start here */
-#define GROUP3_IRQ_BASE         (GROUP2_IRQ_BASE + 32)
-#define GROUP4_IRQ_BASE         (GROUP3_IRQ_BASE + 32)
-
-
-#ifdef __MIPSEB__
-#define RC32434_UART0_BASE      (RC32434_REG_BASE + 0x58003)
-#else
-#define RC32434_UART0_BASE      (RC32434_REG_BASE + 0x58000)
-#endif
-
-#define RC32434_UART0_IRQ       (GROUP3_IRQ_BASE + 0)
-
-/* cpu pipeline flush */
-static inline void rc32434_sync(void)
-{
-        __asm__ volatile ("sync");
-}
-
-static inline void rc32434_sync_udelay(int us)
-{
-        __asm__ volatile ("sync");
-        udelay(us);
-}
-
-static inline void rc32434_sync_delay(int ms)
-{
-        __asm__ volatile ("sync");
-        mdelay(ms);
-}
-
-#endif  /* _ASM_RC32434_RC32434_H_ */
diff --git a/include/asm-mips/mach-rc32434/timer.h b/include/asm-mips/mach-rc32434/timer.h
deleted file mode 100644
index e49b1d57a017..000000000000
--- a/include/asm-mips/mach-rc32434/timer.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- *  Definitions for timer registers
- *
- *  Copyright 2004 Philip Rischel <rischelp@idt.com>
- *  Copyright 2008 Florian Fainelli <florian@openwrt.org>
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
- *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
- *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- *
- */
-
-#ifndef __ASM_RC32434_TIMER_H
-#define __ASM_RC32434_TIMER_H
-
-#include <asm/mach-rc32434/rb.h>
-
-#define TIMER0_BASE_ADDR                0x18028000
-#define TIMER_COUNT                     3
-
-struct timer_counter {
-        u32 count;
-        u32 compare;
-        u32 ctc;                /*use CTC_ */
-};
-
-struct timer {
-        struct timer_counter tim[TIMER_COUNT];
-        u32 rcount;     /* use RCOUNT_ */
-        u32 rcompare;   /* use RCOMPARE_ */
-        u32 rtc;        /* use RTC_ */
-};
-
-#define RC32434_CTC_EN_BIT              0
-#define RC32434_CTC_TO_BIT              1
-
-/* Real time clock registers */
-#define RC32434_RTC_MSK(x)              BIT_TO_MASK(x)
-#define RC32434_RTC_CE_BIT              0
-#define RC32434_RTC_TO_BIT              1
-#define RC32434_RTC_RQE_BIT             2
-
-/* Counter registers */
-#define RC32434_RCOUNT_BIT              0
-#define RC32434_RCOUNT_MSK              0x0000ffff
-#define RC32434_RCOMP_BIT               0
-#define RC32434_RCOMP_MSK               0x0000ffff
-
-#endif  /* __ASM_RC32434_TIMER_H */
diff --git a/include/asm-mips/mach-rc32434/war.h b/include/asm-mips/mach-rc32434/war.h
deleted file mode 100644
index 3ddf187e98a6..000000000000
--- a/include/asm-mips/mach-rc32434/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_MIPS_WAR_H
-#define __ASM_MIPS_MACH_MIPS_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        1
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_MIPS_WAR_H */
diff --git a/include/asm-mips/mach-rm/cpu-feature-overrides.h b/include/asm-mips/mach-rm/cpu-feature-overrides.h
deleted file mode 100644
index ccf543363537..000000000000
--- a/include/asm-mips/mach-rm/cpu-feature-overrides.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
- *
- * SNI RM200 C apparently was only shipped with R4600 V2.0 and R5000 processors.
- */
-#ifndef __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H
-
-#include <cpu-feature-overrides.h>
-
-#define cpu_has_tlb             1
-#define cpu_has_4kex            1
-#define cpu_has_4k_cache        1
-#define cpu_has_fpu             1
-#define cpu_has_32fpr           1
-#define cpu_has_counter         1
-#define cpu_has_watch           0
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_cache_cdex_p    1
-#define cpu_has_prefetch        0
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      (PAGE_SIZE < 0x4000)
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_RM200_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-rm/mc146818rtc.h b/include/asm-mips/mach-rm/mc146818rtc.h
deleted file mode 100644
index 145bce096fe9..000000000000
--- a/include/asm-mips/mach-rm/mc146818rtc.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- *
- * RTC routines for PC style attached Dallas chip with ARC epoch.
- */
-#ifndef __ASM_MACH_RM_MC146818RTC_H
-#define __ASM_MACH_RM_MC146818RTC_H
-
-#ifdef CONFIG_CPU_BIG_ENDIAN
-#define mc146818_decode_year(year) ((year) < 70 ? (year) + 2000 : (year) + 1900)
-#else
-#define mc146818_decode_year(year) ((year) + 1980)
-#endif
-
-#include_next <mc146818rtc.h>
-
-#endif /* __ASM_MACH_RM_MC146818RTC_H */
diff --git a/include/asm-mips/mach-rm/war.h b/include/asm-mips/mach-rm/war.h
deleted file mode 100644
index 948d3129a114..000000000000
--- a/include/asm-mips/mach-rm/war.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_RM_WAR_H
-#define __ASM_MIPS_MACH_RM_WAR_H
-
-/*
- * The RM200C seems to have been shipped only with V2.0 R4600s
- */
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        1
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_RM_WAR_H */
diff --git a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h b/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
deleted file mode 100644
index 1c1f92415b9a..000000000000
--- a/include/asm-mips/mach-sibyte/cpu-feature-overrides.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Sibyte are MIPS64 processors wired to a specific configuration
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           1
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          1
-#define cpu_has_ejtag           1
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     1
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-#define cpu_icache_snoops_remote_store  0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_mips32r1        1
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        1
-#define cpu_has_mips64r2        0
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-
-#endif /* __ASM_MACH_SIBYTE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-sibyte/war.h b/include/asm-mips/mach-sibyte/war.h
deleted file mode 100644
index 7950ef4f032c..000000000000
--- a/include/asm-mips/mach-sibyte/war.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_SIBYTE_WAR_H
-#define __ASM_MIPS_MACH_SIBYTE_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-
-#if defined(CONFIG_SB1_PASS_1_WORKAROUNDS) || \
-    defined(CONFIG_SB1_PASS_2_WORKAROUNDS)
-
-#define BCM1250_M3_WAR  1
-#define SIBYTE_1956_WAR 1
-
-#else
-
-#define BCM1250_M3_WAR  0
-#define SIBYTE_1956_WAR 0
-
-#endif
-
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_SIBYTE_WAR_H */
diff --git a/include/asm-mips/mach-tx39xx/ioremap.h b/include/asm-mips/mach-tx39xx/ioremap.h
deleted file mode 100644
index 93c6c04ffda3..000000000000
--- a/include/asm-mips/mach-tx39xx/ioremap.h
+++ /dev/null
@@ -1,38 +0,0 @@
-/*
- *      include/asm-mips/mach-tx39xx/ioremap.h
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MACH_TX39XX_IOREMAP_H
-#define __ASM_MACH_TX39XX_IOREMAP_H
-
-#include <linux/types.h>
-
-/*
- * Allow physical addresses to be fixed up to help peripherals located
- * outside the low 32-bit range -- generic pass-through version.
- */
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-        return phys_addr;
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-        unsigned long flags)
-{
-#define TXX9_DIRECTMAP_BASE     0xff000000ul
-        if (offset >= TXX9_DIRECTMAP_BASE &&
-            offset < TXX9_DIRECTMAP_BASE + 0xff0000)
-                return (void __iomem *)offset;
-        return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >= TXX9_DIRECTMAP_BASE;
-}
-
-#endif /* __ASM_MACH_TX39XX_IOREMAP_H */
diff --git a/include/asm-mips/mach-tx39xx/mangle-port.h b/include/asm-mips/mach-tx39xx/mangle-port.h
deleted file mode 100644
index ef0b502fd8b7..000000000000
--- a/include/asm-mips/mach-tx39xx/mangle-port.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __ASM_MACH_TX39XX_MANGLE_PORT_H
-#define __ASM_MACH_TX39XX_MANGLE_PORT_H
-
-#if defined(CONFIG_TOSHIBA_JMR3927)
-extern unsigned long (*__swizzle_addr_b)(unsigned long port);
-#define NEEDS_TXX9_SWIZZLE_ADDR_B
-#else
-#define __swizzle_addr_b(port)  (port)
-#endif
-#define __swizzle_addr_w(port)  (port)
-#define __swizzle_addr_l(port)  (port)
-#define __swizzle_addr_q(port)  (port)
-
-#define ioswabb(a, x)           (x)
-#define __mem_ioswabb(a, x)     (x)
-#define ioswabw(a, x)           le16_to_cpu(x)
-#define __mem_ioswabw(a, x)     (x)
-#define ioswabl(a, x)           le32_to_cpu(x)
-#define __mem_ioswabl(a, x)     (x)
-#define ioswabq(a, x)           le64_to_cpu(x)
-#define __mem_ioswabq(a, x)     (x)
-
-#endif /* __ASM_MACH_TX39XX_MANGLE_PORT_H */
diff --git a/include/asm-mips/mach-tx39xx/war.h b/include/asm-mips/mach-tx39xx/war.h
deleted file mode 100644
index 433814616359..000000000000
--- a/include/asm-mips/mach-tx39xx/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_TX39XX_WAR_H
-#define __ASM_MIPS_MACH_TX39XX_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_TX39XX_WAR_H */
diff --git a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h b/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h
deleted file mode 100644
index 275eaf92c748..000000000000
--- a/include/asm-mips/mach-tx49xx/cpu-feature-overrides.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H
-
-#define cpu_has_llsc    1
-#define cpu_has_64bits  1
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_has_mips16          0
-#define cpu_has_mdmx            0
-#define cpu_has_mips3d          0
-#define cpu_has_smartmips       0
-#define cpu_has_vtag_icache     0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp     0
-#define cpu_has_mipsmt  0
-#define cpu_has_userlocal       0
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_TX49XX_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-tx49xx/ioremap.h b/include/asm-mips/mach-tx49xx/ioremap.h
deleted file mode 100644
index 1e7beae72229..000000000000
--- a/include/asm-mips/mach-tx49xx/ioremap.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *      include/asm-mips/mach-tx49xx/ioremap.h
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef __ASM_MACH_TX49XX_IOREMAP_H
-#define __ASM_MACH_TX49XX_IOREMAP_H
-
-#include <linux/types.h>
-
-/*
- * Allow physical addresses to be fixed up to help peripherals located
- * outside the low 32-bit range -- generic pass-through version.
- */
-static inline phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
-{
-        return phys_addr;
-}
-
-static inline void __iomem *plat_ioremap(phys_t offset, unsigned long size,
-        unsigned long flags)
-{
-#ifdef CONFIG_64BIT
-#define TXX9_DIRECTMAP_BASE     0xfff000000ul
-#else
-#define TXX9_DIRECTMAP_BASE     0xff000000ul
-#endif
-        if (offset >= TXX9_DIRECTMAP_BASE &&
-            offset < TXX9_DIRECTMAP_BASE + 0x400000)
-                return (void __iomem *)(unsigned long)(int)offset;
-        return NULL;
-}
-
-static inline int plat_iounmap(const volatile void __iomem *addr)
-{
-        return (unsigned long)addr >=
-                (unsigned long)(int)(TXX9_DIRECTMAP_BASE & 0xffffffff);
-}
-
-#endif /* __ASM_MACH_TX49XX_IOREMAP_H */
diff --git a/include/asm-mips/mach-tx49xx/kmalloc.h b/include/asm-mips/mach-tx49xx/kmalloc.h
deleted file mode 100644
index 913ff196259d..000000000000
--- a/include/asm-mips/mach-tx49xx/kmalloc.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_MACH_TX49XX_KMALLOC_H
-#define __ASM_MACH_TX49XX_KMALLOC_H
-
-/*
- * All happy, no need to define ARCH_KMALLOC_MINALIGN
- */
-
-#endif /* __ASM_MACH_TX49XX_KMALLOC_H */
diff --git a/include/asm-mips/mach-tx49xx/war.h b/include/asm-mips/mach-tx49xx/war.h
deleted file mode 100644
index 39b5d1177c57..000000000000
--- a/include/asm-mips/mach-tx49xx/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_TX49XX_WAR_H
-#define __ASM_MIPS_MACH_TX49XX_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     1
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_TX49XX_WAR_H */
diff --git a/include/asm-mips/mach-vr41xx/irq.h b/include/asm-mips/mach-vr41xx/irq.h
deleted file mode 100644
index 862058d3f81b..000000000000
--- a/include/asm-mips/mach-vr41xx/irq.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#ifndef __ASM_MACH_VR41XX_IRQ_H
-#define __ASM_MACH_VR41XX_IRQ_H
-
-#include <asm/vr41xx/irq.h> /* for MIPS_CPU_IRQ_BASE */
-
-#include_next <irq.h>
-
-#endif /* __ASM_MACH_VR41XX_IRQ_H */
diff --git a/include/asm-mips/mach-vr41xx/war.h b/include/asm-mips/mach-vr41xx/war.h
deleted file mode 100644
index 56a38926412a..000000000000
--- a/include/asm-mips/mach-vr41xx/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_VR41XX_WAR_H
-#define __ASM_MIPS_MACH_VR41XX_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_VR41XX_WAR_H */
diff --git a/include/asm-mips/mach-wrppmc/mach-gt64120.h b/include/asm-mips/mach-wrppmc/mach-gt64120.h
deleted file mode 100644
index 83746b84a5ec..000000000000
--- a/include/asm-mips/mach-wrppmc/mach-gt64120.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This is a direct copy of the ev96100.h file, with a global
- * search and replace.  The numbers are the same.
- *
- * The reason I'm duplicating this is so that the 64120/96100
- * defines won't be confusing in the source code.
- */
-#ifndef __ASM_MIPS_GT64120_H
-#define __ASM_MIPS_GT64120_H
-
-/*
- * This is the CPU physical memory map of PPMC Board:
- *
- *    0x00000000-0x03FFFFFF      - 64MB SDRAM (SCS[0]#)
- *    0x1C000000-0x1C000000      - LED (CS0)
- *    0x1C800000-0x1C800007      - UART 16550 port (CS1)
- *    0x1F000000-0x1F000000      - MailBox (CS3)
- *    0x1FC00000-0x20000000      - 4MB Flash (BOOT CS)
- */
-
-#define WRPPMC_SDRAM_SCS0_BASE  0x00000000
-#define WRPPMC_SDRAM_SCS0_SIZE  0x04000000
-
-#define WRPPMC_UART16550_BASE   0x1C800000
-#define WRPPMC_UART16550_CLOCK  3686400 /* 3.68MHZ */
-
-#define WRPPMC_LED_BASE         0x1C000000
-#define WRPPMC_MBOX_BASE        0x1F000000
-
-#define WRPPMC_BOOTROM_BASE     0x1FC00000
-#define WRPPMC_BOOTROM_SIZE     0x00400000 /* 4M Flash */
-
-#define WRPPMC_MIPS_TIMER_IRQ   7 /* MIPS compare/count timer interrupt */
-#define WRPPMC_UART16550_IRQ    6
-#define WRPPMC_PCI_INTA_IRQ     3
-
-/*
- * PCI Bus I/O and Memory resources allocation
- *
- * NOTE: We only have PCI_0 hose interface
- */
-#define GT_PCI_MEM_BASE 0x13000000UL
-#define GT_PCI_MEM_SIZE 0x02000000UL
-#define GT_PCI_IO_BASE  0x11000000UL
-#define GT_PCI_IO_SIZE  0x02000000UL
-
-/*
- * PCI interrupts will come in on either the INTA or INTD interrupt lines,
- * which are mapped to the #2 and #5 interrupt pins of the MIPS.  On our
- * boards, they all either come in on IntD or they all come in on IntA, they
- * aren't mixed. There can be numerous PCI interrupts, so we keep a list of the
- * "requested" interrupt numbers and go through the list whenever we get an
- * IntA/D.
- *
- * Interrupts < 8 are directly wired to the processor; PCI INTA is 8 and
- * INTD is 11.
- */
-#define GT_TIMER        4
-#define GT_INTA         2
-#define GT_INTD         5
-
-#ifndef __ASSEMBLY__
-
-/*
- * GT64120 internal register space base address
- */
-extern unsigned long gt64120_base;
-
-#define GT64120_BASE    (gt64120_base)
-
-/* define WRPPMC_EARLY_DEBUG to enable early output something to UART */
-#undef WRPPMC_EARLY_DEBUG
-
-#ifdef WRPPMC_EARLY_DEBUG
-extern void wrppmc_led_on(int mask);
-extern void wrppmc_led_off(int mask);
-extern void wrppmc_early_printk(const char *fmt, ...);
-#else
-#define wrppmc_early_printk(fmt, ...) do {} while (0)
-#endif /* WRPPMC_EARLY_DEBUG */
-
-#endif /* __ASSEMBLY__ */
-#endif /* __ASM_MIPS_GT64120_H */
diff --git a/include/asm-mips/mach-wrppmc/war.h b/include/asm-mips/mach-wrppmc/war.h
deleted file mode 100644
index ac48629bb1ce..000000000000
--- a/include/asm-mips/mach-wrppmc/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_WRPPMC_WAR_H
-#define __ASM_MIPS_MACH_WRPPMC_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_WRPPMC_WAR_H */
diff --git a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h b/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
deleted file mode 100644
index 470e5e9e10d6..000000000000
--- a/include/asm-mips/mach-yosemite/cpu-feature-overrides.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003, 04, 07 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
-#define __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H
-
-/*
- * Momentum Jaguar ATX always has the RM9000 processor.
- */
-#define cpu_has_watch           1
-#define cpu_has_mips16          0
-#define cpu_has_divec           0
-#define cpu_has_vce             0
-#define cpu_has_cache_cdex_p    0
-#define cpu_has_cache_cdex_s    0
-#define cpu_has_prefetch        1
-#define cpu_has_mcheck          0
-#define cpu_has_ejtag           0
-
-#define cpu_has_llsc            1
-#define cpu_has_vtag_icache     0
-#define cpu_has_dc_aliases      0
-#define cpu_has_ic_fills_f_dc   0
-#define cpu_has_dsp             0
-#define cpu_has_mipsmt          0
-#define cpu_has_userlocal       0
-#define cpu_icache_snoops_remote_store  0
-
-#define cpu_has_nofpuex         0
-#define cpu_has_64bits          1
-
-#define cpu_has_inclusive_pcaches       0
-
-#define cpu_dcache_line_size()  32
-#define cpu_icache_line_size()  32
-#define cpu_scache_line_size()  32
-
-#define cpu_has_mips32r1        0
-#define cpu_has_mips32r2        0
-#define cpu_has_mips64r1        0
-#define cpu_has_mips64r2        0
-
-#endif /* __ASM_MACH_YOSEMITE_CPU_FEATURE_OVERRIDES_H */
diff --git a/include/asm-mips/mach-yosemite/war.h b/include/asm-mips/mach-yosemite/war.h
deleted file mode 100644
index e5c6d53efc86..000000000000
--- a/include/asm-mips/mach-yosemite/war.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_MACH_YOSEMITE_WAR_H
-#define __ASM_MIPS_MACH_YOSEMITE_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             1
-#define ICACHE_REFILLS_WORKAROUND_WAR   1
-#define R10000_LLSC_WAR                 0
-#define MIPS34K_MISSED_ITLB_WAR         0
-
-#endif /* __ASM_MIPS_MACH_YOSEMITE_WAR_H */
diff --git a/include/asm-mips/mc146818-time.h b/include/asm-mips/mc146818-time.h
deleted file mode 100644
index cdc379a0a94e..000000000000
--- a/include/asm-mips/mc146818-time.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Machine dependent access functions for RTC registers.
- */
-#ifndef __ASM_MC146818_TIME_H
-#define __ASM_MC146818_TIME_H
-
-#include <linux/bcd.h>
-#include <linux/mc146818rtc.h>
-#include <linux/time.h>
-
-/*
- * For check timing call set_rtc_mmss() 500ms; used in timer interrupt.
- */
-#define USEC_AFTER      500000
-#define USEC_BEFORE     500000
-
-/*
- * In order to set the CMOS clock precisely, set_rtc_mmss has to be
- * called 500 ms after the second nowtime has started, because when
- * nowtime is written into the registers of the CMOS clock, it will
- * jump to the next second precisely 500 ms later. Check the Motorola
- * MC146818A or Dallas DS12887 data sheet for details.
- *
- * BUG: This routine does not handle hour overflow properly; it just
- *      sets the minutes. Usually you'll only notice that after reboot!
- */
-static inline int mc146818_set_rtc_mmss(unsigned long nowtime)
-{
-        int real_seconds, real_minutes, cmos_minutes;
-        unsigned char save_control, save_freq_select;
-        int retval = 0;
-        unsigned long flags;
-
-        spin_lock_irqsave(&rtc_lock, flags);
-        save_control = CMOS_READ(RTC_CONTROL); /* tell the clock it's being set */
-        CMOS_WRITE((save_control|RTC_SET), RTC_CONTROL);
-
-        save_freq_select = CMOS_READ(RTC_FREQ_SELECT); /* stop and reset prescaler */
-        CMOS_WRITE((save_freq_select|RTC_DIV_RESET2), RTC_FREQ_SELECT);
-
-        cmos_minutes = CMOS_READ(RTC_MINUTES);
-        if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD)
-                BCD_TO_BIN(cmos_minutes);
-
-        /*
-         * since we're only adjusting minutes and seconds,
-         * don't interfere with hour overflow. This avoids
-         * messing with unknown time zones but requires your
-         * RTC not to be off by more than 15 minutes
-         */
-        real_seconds = nowtime % 60;
-        real_minutes = nowtime / 60;
-        if (((abs(real_minutes - cmos_minutes) + 15)/30) & 1)
-                real_minutes += 30;             /* correct for half hour time zone */
-        real_minutes %= 60;
-
-        if (abs(real_minutes - cmos_minutes) < 30) {
-                if (!(save_control & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
-                        BIN_TO_BCD(real_seconds);
-                        BIN_TO_BCD(real_minutes);
-                }
-                CMOS_WRITE(real_seconds, RTC_SECONDS);
-                CMOS_WRITE(real_minutes, RTC_MINUTES);
-        } else {
-                printk(KERN_WARNING
-                       "set_rtc_mmss: can't update from %d to %d\n",
-                       cmos_minutes, real_minutes);
-                retval = -1;
-        }
-
-        /* The following flags have to be released exactly in this order,
-         * otherwise the DS12887 (popular MC146818A clone with integrated
-         * battery and quartz) will not reset the oscillator and will not
-         * update precisely 500 ms later. You won't find this mentioned in
-         * the Dallas Semiconductor data sheets, but who believes data
-         * sheets anyway ...                           -- Markus Kuhn
-         */
-        CMOS_WRITE(save_control, RTC_CONTROL);
-        CMOS_WRITE(save_freq_select, RTC_FREQ_SELECT);
-        spin_unlock_irqrestore(&rtc_lock, flags);
-
-        return retval;
-}
-
-static inline unsigned long mc146818_get_cmos_time(void)
-{
-        unsigned int year, mon, day, hour, min, sec;
-        unsigned long flags;
-
-        spin_lock_irqsave(&rtc_lock, flags);
-
-        do {
-                sec = CMOS_READ(RTC_SECONDS);
-                min = CMOS_READ(RTC_MINUTES);
-                hour = CMOS_READ(RTC_HOURS);
-                day = CMOS_READ(RTC_DAY_OF_MONTH);
-                mon = CMOS_READ(RTC_MONTH);
-                year = CMOS_READ(RTC_YEAR);
-        } while (sec != CMOS_READ(RTC_SECONDS));
-
-        if (!(CMOS_READ(RTC_CONTROL) & RTC_DM_BINARY) || RTC_ALWAYS_BCD) {
-                BCD_TO_BIN(sec);
-                BCD_TO_BIN(min);
-                BCD_TO_BIN(hour);
-                BCD_TO_BIN(day);
-                BCD_TO_BIN(mon);
-                BCD_TO_BIN(year);
-        }
-        spin_unlock_irqrestore(&rtc_lock, flags);
-        year = mc146818_decode_year(year);
-
-        return mktime(year, mon, day, hour, min, sec);
-}
-
-#endif /* __ASM_MC146818_TIME_H */
diff --git a/include/asm-mips/mc146818rtc.h b/include/asm-mips/mc146818rtc.h
deleted file mode 100644
index 68b4da6d520b..000000000000
--- a/include/asm-mips/mc146818rtc.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Machine dependent access functions for RTC registers.
- *
- * Copyright (C) 1996, 1997, 1998, 2000 Ralf Baechle
- * Copyright (C) 2002  Maciej W. Rozycki
- */
-#ifndef _ASM_MC146818RTC_H
-#define _ASM_MC146818RTC_H
-
-#include <mc146818rtc.h>
-
-#endif /* _ASM_MC146818RTC_H */
diff --git a/include/asm-mips/mips-boards/bonito64.h b/include/asm-mips/mips-boards/bonito64.h
deleted file mode 100644
index a0f04bb99c99..000000000000
--- a/include/asm-mips/mips-boards/bonito64.h
+++ /dev/null
@@ -1,436 +0,0 @@
-/*
- * Bonito Register Map
- *
- * This file is the original bonito.h from Algorithmics with minor changes
- * to fit into linux.
- *
- * Copyright (c) 1999 Algorithmics Ltd
- *
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2001 MIPS Technologies, Inc.  All rights reserved.
- *
- * Algorithmics gives permission for anyone to use and modify this file
- * without any obligation or license condition except that you retain
- * this copyright message in any source redistribution in whole or part.
- *
- */
-
-/* Revision 1.48 autogenerated on 08/17/99 15:20:01 */
-/* This bonito64 version editted from bonito.h Revision 1.48 on 11/09/00 */
-
-#ifndef _ASM_MIPS_BOARDS_BONITO64_H
-#define _ASM_MIPS_BOARDS_BONITO64_H
-
-#ifdef __ASSEMBLY__
-
-/* offsets from base register */
-#define BONITO(x)       (x)
-
-#elif defined(CONFIG_LEMOTE_FULONG)
-
-#define BONITO(x) (*(volatile u32 *)((char *)CKSEG1ADDR(BONITO_REG_BASE) + (x)))
-#define BONITO_IRQ_BASE   32
-
-#else
-
-/*
- * Algorithmics Bonito64 system controller register base.
- */
-extern unsigned long _pcictrl_bonito;
-extern unsigned long _pcictrl_bonito_pcicfg;
-
-#define BONITO(x)               *(volatile u32 *)(_pcictrl_bonito + (x))
-
-#endif /* __ASSEMBLY__ */
-
-
-#define BONITO_BOOT_BASE                0x1fc00000
-#define BONITO_BOOT_SIZE                0x00100000
-#define BONITO_BOOT_TOP                 (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1)
-#define BONITO_FLASH_BASE               0x1c000000
-#define BONITO_FLASH_SIZE               0x03000000
-#define BONITO_FLASH_TOP                (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1)
-#define BONITO_SOCKET_BASE              0x1f800000
-#define BONITO_SOCKET_SIZE              0x00400000
-#define BONITO_SOCKET_TOP               (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1)
-#define BONITO_REG_BASE                 0x1fe00000
-#define BONITO_REG_SIZE                 0x00040000
-#define BONITO_REG_TOP                  (BONITO_REG_BASE+BONITO_REG_SIZE-1)
-#define BONITO_DEV_BASE                 0x1ff00000
-#define BONITO_DEV_SIZE                 0x00100000
-#define BONITO_DEV_TOP                  (BONITO_DEV_BASE+BONITO_DEV_SIZE-1)
-#define BONITO_PCILO_BASE               0x10000000
-#define BONITO_PCILO_SIZE               0x0c000000
-#define BONITO_PCILO_TOP                (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1)
-#define BONITO_PCILO0_BASE              0x10000000
-#define BONITO_PCILO1_BASE              0x14000000
-#define BONITO_PCILO2_BASE              0x18000000
-#define BONITO_PCIHI_BASE               0x20000000
-#define BONITO_PCIHI_SIZE               0x20000000
-#define BONITO_PCIHI_TOP                (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1)
-#define BONITO_PCIIO_BASE               0x1fd00000
-#define BONITO_PCIIO_SIZE               0x00100000
-#define BONITO_PCIIO_TOP                (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1)
-#define BONITO_PCICFG_BASE              0x1fe80000
-#define BONITO_PCICFG_SIZE              0x00080000
-#define BONITO_PCICFG_TOP               (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1)
-
-
-/* Bonito Register Bases */
-
-#define BONITO_PCICONFIGBASE            0x00
-#define BONITO_REGBASE                  0x100
-
-
-/* PCI Configuration  Registers */
-
-#define BONITO_PCI_REG(x)               BONITO(BONITO_PCICONFIGBASE + (x))
-#define BONITO_PCIDID                   BONITO_PCI_REG(0x00)
-#define BONITO_PCICMD                   BONITO_PCI_REG(0x04)
-#define BONITO_PCICLASS                 BONITO_PCI_REG(0x08)
-#define BONITO_PCILTIMER                BONITO_PCI_REG(0x0c)
-#define BONITO_PCIBASE0                 BONITO_PCI_REG(0x10)
-#define BONITO_PCIBASE1                 BONITO_PCI_REG(0x14)
-#define BONITO_PCIBASE2                 BONITO_PCI_REG(0x18)
-#define BONITO_PCIEXPRBASE              BONITO_PCI_REG(0x30)
-#define BONITO_PCIINT                   BONITO_PCI_REG(0x3c)
-
-#define BONITO_PCICMD_PERR_CLR          0x80000000
-#define BONITO_PCICMD_SERR_CLR          0x40000000
-#define BONITO_PCICMD_MABORT_CLR        0x20000000
-#define BONITO_PCICMD_MTABORT_CLR       0x10000000
-#define BONITO_PCICMD_TABORT_CLR        0x08000000
-#define BONITO_PCICMD_MPERR_CLR         0x01000000
-#define BONITO_PCICMD_PERRRESPEN        0x00000040
-#define BONITO_PCICMD_ASTEPEN           0x00000080
-#define BONITO_PCICMD_SERREN            0x00000100
-#define BONITO_PCILTIMER_BUSLATENCY     0x0000ff00
-#define BONITO_PCILTIMER_BUSLATENCY_SHIFT       8
-
-
-
-
-/* 1. Bonito h/w Configuration */
-/* Power on register */
-
-#define BONITO_BONPONCFG                BONITO(BONITO_REGBASE + 0x00)
-
-#define BONITO_BONPONCFG_SYSCONTROLLERRD        0x00040000
-#define BONITO_BONPONCFG_ROMCS1SAMP     0x00020000
-#define BONITO_BONPONCFG_ROMCS0SAMP     0x00010000
-#define BONITO_BONPONCFG_CPUBIGEND      0x00004000
-/* Added by RPF 11-9-00 */
-#define BONITO_BONPONCFG_BURSTORDER     0x00001000
-/* --- */
-#define BONITO_BONPONCFG_CPUPARITY      0x00002000
-#define BONITO_BONPONCFG_CPUTYPE        0x00000007
-#define BONITO_BONPONCFG_CPUTYPE_SHIFT  0
-#define BONITO_BONPONCFG_PCIRESET_OUT   0x00000008
-#define BONITO_BONPONCFG_IS_ARBITER     0x00000010
-#define BONITO_BONPONCFG_ROMBOOT        0x000000c0
-#define BONITO_BONPONCFG_ROMBOOT_SHIFT  6
-
-#define BONITO_BONPONCFG_ROMBOOT_FLASH  (0x0<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-#define BONITO_BONPONCFG_ROMBOOT_SOCKET (0x1<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-#define BONITO_BONPONCFG_ROMBOOT_SDRAM  (0x2<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-#define BONITO_BONPONCFG_ROMBOOT_CPURESET       (0x3<<BONITO_BONPONCFG_ROMBOOT_SHIFT)
-
-#define BONITO_BONPONCFG_ROMCS0WIDTH    0x00000100
-#define BONITO_BONPONCFG_ROMCS1WIDTH    0x00000200
-#define BONITO_BONPONCFG_ROMCS0FAST     0x00000400
-#define BONITO_BONPONCFG_ROMCS1FAST     0x00000800
-#define BONITO_BONPONCFG_CONFIG_DIS     0x00000020
-
-
-/* Other Bonito configuration */
-
-#define BONITO_BONGENCFG_OFFSET         0x4
-#define BONITO_BONGENCFG                BONITO(BONITO_REGBASE + BONITO_BONGENCFG_OFFSET)
-
-#define BONITO_BONGENCFG_DEBUGMODE      0x00000001
-#define BONITO_BONGENCFG_SNOOPEN        0x00000002
-#define BONITO_BONGENCFG_CPUSELFRESET   0x00000004
-
-#define BONITO_BONGENCFG_FORCE_IRQA     0x00000008
-#define BONITO_BONGENCFG_IRQA_ISOUT     0x00000010
-#define BONITO_BONGENCFG_IRQA_FROM_INT1 0x00000020
-#define BONITO_BONGENCFG_BYTESWAP       0x00000040
-
-#define BONITO_BONGENCFG_UNCACHED       0x00000080
-#define BONITO_BONGENCFG_PREFETCHEN     0x00000100
-#define BONITO_BONGENCFG_WBEHINDEN      0x00000200
-#define BONITO_BONGENCFG_CACHEALG       0x00000c00
-#define BONITO_BONGENCFG_CACHEALG_SHIFT 10
-#define BONITO_BONGENCFG_PCIQUEUE       0x00001000
-#define BONITO_BONGENCFG_CACHESTOP      0x00002000
-#define BONITO_BONGENCFG_MSTRBYTESWAP   0x00004000
-#define BONITO_BONGENCFG_BUSERREN       0x00008000
-#define BONITO_BONGENCFG_NORETRYTIMEOUT 0x00010000
-#define BONITO_BONGENCFG_SHORTCOPYTIMEOUT       0x00020000
-
-/* 2. IO & IDE configuration */
-
-#define BONITO_IODEVCFG                 BONITO(BONITO_REGBASE + 0x08)
-
-/* 3. IO & IDE configuration */
-
-#define BONITO_SDCFG                    BONITO(BONITO_REGBASE + 0x0c)
-
-/* 4. PCI address map control */
-
-#define BONITO_PCIMAP                   BONITO(BONITO_REGBASE + 0x10)
-#define BONITO_PCIMEMBASECFG            BONITO(BONITO_REGBASE + 0x14)
-#define BONITO_PCIMAP_CFG               BONITO(BONITO_REGBASE + 0x18)
-
-/* 5. ICU & GPIO regs */
-
-/* GPIO Regs - r/w */
-
-#define BONITO_GPIODATA_OFFSET          0x1c
-#define BONITO_GPIODATA                 BONITO(BONITO_REGBASE + BONITO_GPIODATA_OFFSET)
-#define BONITO_GPIOIE                   BONITO(BONITO_REGBASE + 0x20)
-
-/* ICU Configuration Regs - r/w */
-
-#define BONITO_INTEDGE                  BONITO(BONITO_REGBASE + 0x24)
-#define BONITO_INTSTEER                 BONITO(BONITO_REGBASE + 0x28)
-#define BONITO_INTPOL                   BONITO(BONITO_REGBASE + 0x2c)
-
-/* ICU Enable Regs - IntEn & IntISR are r/o. */
-
-#define BONITO_INTENSET                 BONITO(BONITO_REGBASE + 0x30)
-#define BONITO_INTENCLR                 BONITO(BONITO_REGBASE + 0x34)
-#define BONITO_INTEN                    BONITO(BONITO_REGBASE + 0x38)
-#define BONITO_INTISR                   BONITO(BONITO_REGBASE + 0x3c)
-
-/* PCI mail boxes */
-
-#define BONITO_PCIMAIL0_OFFSET          0x40
-#define BONITO_PCIMAIL1_OFFSET          0x44
-#define BONITO_PCIMAIL2_OFFSET          0x48
-#define BONITO_PCIMAIL3_OFFSET          0x4c
-#define BONITO_PCIMAIL0                 BONITO(BONITO_REGBASE + 0x40)
-#define BONITO_PCIMAIL1                 BONITO(BONITO_REGBASE + 0x44)
-#define BONITO_PCIMAIL2                 BONITO(BONITO_REGBASE + 0x48)
-#define BONITO_PCIMAIL3                 BONITO(BONITO_REGBASE + 0x4c)
-
-
-/* 6. PCI cache */
-
-#define BONITO_PCICACHECTRL             BONITO(BONITO_REGBASE + 0x50)
-#define BONITO_PCICACHETAG              BONITO(BONITO_REGBASE + 0x54)
-
-#define BONITO_PCIBADADDR               BONITO(BONITO_REGBASE + 0x58)
-#define BONITO_PCIMSTAT                 BONITO(BONITO_REGBASE + 0x5c)
-
-
-/*
-#define BONITO_PCIRDPOST                BONITO(BONITO_REGBASE + 0x60)
-#define BONITO_PCIDATA                  BONITO(BONITO_REGBASE + 0x64)
-*/
-
-/* 7. IDE DMA & Copier */
-
-#define BONITO_CONFIGBASE               0x000
-#define BONITO_BONITOBASE               0x100
-#define BONITO_LDMABASE                 0x200
-#define BONITO_COPBASE                  0x300
-#define BONITO_REG_BLOCKMASK            0x300
-
-#define BONITO_LDMACTRL                 BONITO(BONITO_LDMABASE + 0x0)
-#define BONITO_LDMASTAT                 BONITO(BONITO_LDMABASE + 0x0)
-#define BONITO_LDMAADDR                 BONITO(BONITO_LDMABASE + 0x4)
-#define BONITO_LDMAGO                   BONITO(BONITO_LDMABASE + 0x8)
-#define BONITO_LDMADATA                 BONITO(BONITO_LDMABASE + 0xc)
-
-#define BONITO_COPCTRL                  BONITO(BONITO_COPBASE + 0x0)
-#define BONITO_COPSTAT                  BONITO(BONITO_COPBASE + 0x0)
-#define BONITO_COPPADDR                 BONITO(BONITO_COPBASE + 0x4)
-#define BONITO_COPDADDR                 BONITO(BONITO_COPBASE + 0x8)
-#define BONITO_COPGO                    BONITO(BONITO_COPBASE + 0xc)
-
-
-/* ###### Bit Definitions for individual Registers #### */
-
-/* Gen DMA. */
-
-#define BONITO_IDECOPDADDR_DMA_DADDR    0x0ffffffc
-#define BONITO_IDECOPDADDR_DMA_DADDR_SHIFT      2
-#define BONITO_IDECOPPADDR_DMA_PADDR    0xfffffffc
-#define BONITO_IDECOPPADDR_DMA_PADDR_SHIFT      2
-#define BONITO_IDECOPGO_DMA_SIZE        0x0000fffe
-#define BONITO_IDECOPGO_DMA_SIZE_SHIFT  0
-#define BONITO_IDECOPGO_DMA_WRITE       0x00010000
-#define BONITO_IDECOPGO_DMAWCOUNT       0x000f0000
-#define BONITO_IDECOPGO_DMAWCOUNT_SHIFT 16
-
-#define BONITO_IDECOPCTRL_DMA_STARTBIT  0x80000000
-#define BONITO_IDECOPCTRL_DMA_RSTBIT    0x40000000
-
-/* DRAM - sdCfg */
-
-#define BONITO_SDCFG_AROWBITS           0x00000003
-#define BONITO_SDCFG_AROWBITS_SHIFT     0
-#define BONITO_SDCFG_ACOLBITS           0x0000000c
-#define BONITO_SDCFG_ACOLBITS_SHIFT     2
-#define BONITO_SDCFG_ABANKBIT           0x00000010
-#define BONITO_SDCFG_ASIDES             0x00000020
-#define BONITO_SDCFG_AABSENT            0x00000040
-#define BONITO_SDCFG_AWIDTH64           0x00000080
-
-#define BONITO_SDCFG_BROWBITS           0x00000300
-#define BONITO_SDCFG_BROWBITS_SHIFT     8
-#define BONITO_SDCFG_BCOLBITS           0x00000c00
-#define BONITO_SDCFG_BCOLBITS_SHIFT     10
-#define BONITO_SDCFG_BBANKBIT           0x00001000
-#define BONITO_SDCFG_BSIDES             0x00002000
-#define BONITO_SDCFG_BABSENT            0x00004000
-#define BONITO_SDCFG_BWIDTH64           0x00008000
-
-#define BONITO_SDCFG_EXTRDDATA          0x00010000
-#define BONITO_SDCFG_EXTRASCAS          0x00020000
-#define BONITO_SDCFG_EXTPRECH           0x00040000
-#define BONITO_SDCFG_EXTRASWIDTH        0x00180000
-#define BONITO_SDCFG_EXTRASWIDTH_SHIFT  19
-/* Changed by RPF 11-9-00 */
-#define BONITO_SDCFG_DRAMMODESET        0x00200000
-/* --- */
-#define BONITO_SDCFG_DRAMEXTREGS        0x00400000
-#define BONITO_SDCFG_DRAMPARITY         0x00800000
-/* Added by RPF 11-9-00 */
-#define BONITO_SDCFG_DRAMBURSTLEN       0x03000000
-#define BONITO_SDCFG_DRAMBURSTLEN_SHIFT 24
-#define BONITO_SDCFG_DRAMMODESET_DONE   0x80000000
-/* --- */
-
-/* PCI Cache - pciCacheCtrl */
-
-#define BONITO_PCICACHECTRL_CACHECMD    0x00000007
-#define BONITO_PCICACHECTRL_CACHECMD_SHIFT      0
-#define BONITO_PCICACHECTRL_CACHECMDLINE        0x00000018
-#define BONITO_PCICACHECTRL_CACHECMDLINE_SHIFT  3
-#define BONITO_PCICACHECTRL_CMDEXEC     0x00000020
-
-#define BONITO_PCICACHECTRL_IOBCCOH_PRES        0x00000100
-#define BONITO_PCICACHECTRL_IOBCCOH_EN  0x00000200
-#define BONITO_PCICACHECTRL_CPUCOH_PRES 0x00000400
-#define BONITO_PCICACHECTRL_CPUCOH_EN   0x00000800
-
-#define BONITO_IODEVCFG_BUFFBIT_CS0     0x00000001
-#define BONITO_IODEVCFG_SPEEDBIT_CS0    0x00000002
-#define BONITO_IODEVCFG_MOREABITS_CS0   0x00000004
-
-#define BONITO_IODEVCFG_BUFFBIT_CS1     0x00000008
-#define BONITO_IODEVCFG_SPEEDBIT_CS1    0x00000010
-#define BONITO_IODEVCFG_MOREABITS_CS1   0x00000020
-
-#define BONITO_IODEVCFG_BUFFBIT_CS2     0x00000040
-#define BONITO_IODEVCFG_SPEEDBIT_CS2    0x00000080
-#define BONITO_IODEVCFG_MOREABITS_CS2   0x00000100
-
-#define BONITO_IODEVCFG_BUFFBIT_CS3     0x00000200
-#define BONITO_IODEVCFG_SPEEDBIT_CS3    0x00000400
-#define BONITO_IODEVCFG_MOREABITS_CS3   0x00000800
-
-#define BONITO_IODEVCFG_BUFFBIT_IDE     0x00001000
-#define BONITO_IODEVCFG_SPEEDBIT_IDE    0x00002000
-#define BONITO_IODEVCFG_WORDSWAPBIT_IDE 0x00004000
-#define BONITO_IODEVCFG_MODEBIT_IDE     0x00008000
-#define BONITO_IODEVCFG_DMAON_IDE       0x001f0000
-#define BONITO_IODEVCFG_DMAON_IDE_SHIFT 16
-#define BONITO_IODEVCFG_DMAOFF_IDE      0x01e00000
-#define BONITO_IODEVCFG_DMAOFF_IDE_SHIFT        21
-#define BONITO_IODEVCFG_EPROMSPLIT      0x02000000
-/* Added by RPF 11-9-00 */
-#define BONITO_IODEVCFG_CPUCLOCKPERIOD  0xfc000000
-#define BONITO_IODEVCFG_CPUCLOCKPERIOD_SHIFT 26
-/* --- */
-
-/* gpio */
-#define BONITO_GPIO_GPIOW               0x000003ff
-#define BONITO_GPIO_GPIOW_SHIFT         0
-#define BONITO_GPIO_GPIOR               0x01ff0000
-#define BONITO_GPIO_GPIOR_SHIFT         16
-#define BONITO_GPIO_GPINR               0xfe000000
-#define BONITO_GPIO_GPINR_SHIFT         25
-#define BONITO_GPIO_IOW(N)              (1<<(BONITO_GPIO_GPIOW_SHIFT+(N)))
-#define BONITO_GPIO_IOR(N)              (1<<(BONITO_GPIO_GPIOR_SHIFT+(N)))
-#define BONITO_GPIO_INR(N)              (1<<(BONITO_GPIO_GPINR_SHIFT+(N)))
-
-/* ICU */
-#define BONITO_ICU_MBOXES               0x0000000f
-#define BONITO_ICU_MBOXES_SHIFT         0
-#define BONITO_ICU_DMARDY               0x00000010
-#define BONITO_ICU_DMAEMPTY             0x00000020
-#define BONITO_ICU_COPYRDY              0x00000040
-#define BONITO_ICU_COPYEMPTY            0x00000080
-#define BONITO_ICU_COPYERR              0x00000100
-#define BONITO_ICU_PCIIRQ               0x00000200
-#define BONITO_ICU_MASTERERR            0x00000400
-#define BONITO_ICU_SYSTEMERR            0x00000800
-#define BONITO_ICU_DRAMPERR             0x00001000
-#define BONITO_ICU_RETRYERR             0x00002000
-#define BONITO_ICU_GPIOS                0x01ff0000
-#define BONITO_ICU_GPIOS_SHIFT          16
-#define BONITO_ICU_GPINS                0x7e000000
-#define BONITO_ICU_GPINS_SHIFT          25
-#define BONITO_ICU_MBOX(N)              (1<<(BONITO_ICU_MBOXES_SHIFT+(N)))
-#define BONITO_ICU_GPIO(N)              (1<<(BONITO_ICU_GPIOS_SHIFT+(N)))
-#define BONITO_ICU_GPIN(N)              (1<<(BONITO_ICU_GPINS_SHIFT+(N)))
-
-/* pcimap */
-
-#define BONITO_PCIMAP_PCIMAP_LO0        0x0000003f
-#define BONITO_PCIMAP_PCIMAP_LO0_SHIFT  0
-#define BONITO_PCIMAP_PCIMAP_LO1        0x00000fc0
-#define BONITO_PCIMAP_PCIMAP_LO1_SHIFT  6
-#define BONITO_PCIMAP_PCIMAP_LO2        0x0003f000
-#define BONITO_PCIMAP_PCIMAP_LO2_SHIFT  12
-#define BONITO_PCIMAP_PCIMAP_2          0x00040000
-#define BONITO_PCIMAP_WIN(WIN, ADDR)    ((((ADDR)>>26) & BONITO_PCIMAP_PCIMAP_LO0) << ((WIN)*6))
-
-#define BONITO_PCIMAP_WINSIZE           (1<<26)
-#define BONITO_PCIMAP_WINOFFSET(ADDR)   ((ADDR) & (BONITO_PCIMAP_WINSIZE - 1))
-#define BONITO_PCIMAP_WINBASE(ADDR)     ((ADDR) << 26)
-
-/* pcimembaseCfg */
-
-#define BONITO_PCIMEMBASECFG_MASK               0xf0000000
-#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK      0x0000001f
-#define BONITO_PCIMEMBASECFG_MEMBASE0_MASK_SHIFT        0
-#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS     0x000003e0
-#define BONITO_PCIMEMBASECFG_MEMBASE0_TRANS_SHIFT       5
-#define BONITO_PCIMEMBASECFG_MEMBASE0_CACHED    0x00000400
-#define BONITO_PCIMEMBASECFG_MEMBASE0_IO        0x00000800
-
-#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK      0x0001f000
-#define BONITO_PCIMEMBASECFG_MEMBASE1_MASK_SHIFT        12
-#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS     0x003e0000
-#define BONITO_PCIMEMBASECFG_MEMBASE1_TRANS_SHIFT       17
-#define BONITO_PCIMEMBASECFG_MEMBASE1_CACHED    0x00400000
-#define BONITO_PCIMEMBASECFG_MEMBASE1_IO        0x00800000
-
-#define BONITO_PCIMEMBASECFG_ASHIFT     23
-#define BONITO_PCIMEMBASECFG_AMASK              0x007fffff
-#define BONITO_PCIMEMBASECFGSIZE(WIN, SIZE)     (((~((SIZE)-1))>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)
-#define BONITO_PCIMEMBASECFGBASE(WIN, BASE)     (((BASE)>>(BONITO_PCIMEMBASECFG_ASHIFT-BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS)
-
-#define BONITO_PCIMEMBASECFG_SIZE(WIN, CFG)  (((((~(CFG)) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK)) << (BONITO_PCIMEMBASECFG_ASHIFT - BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT)) | BONITO_PCIMEMBASECFG_AMASK)
-
-
-#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-#define BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)  ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_MASK_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-#define BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG) ((((CFG) & BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS) >> BONITO_PCIMEMBASECFG_MEMBASE##WIN##_TRANS_SHIFT) << BONITO_PCIMEMBASECFG_ASHIFT)
-
-#define BONITO_PCITOPHYS(WIN, ADDR, CFG)          ( \
-                                                  (((ADDR) & (~(BONITO_PCIMEMBASECFG_MASK))) & (~(BONITO_PCIMEMBASECFG_ADDRMASK(WIN, CFG)))) | \
-                                                  (BONITO_PCIMEMBASECFG_ADDRTRANS(WIN, CFG)) \
-                                                )
-
-/* PCICmd */
-
-#define BONITO_PCICMD_MEMEN             0x00000002
-#define BONITO_PCICMD_MSTREN            0x00000004
-
-
-#endif /* _ASM_MIPS_BOARDS_BONITO64_H */
diff --git a/include/asm-mips/mips-boards/generic.h b/include/asm-mips/mips-boards/generic.h
deleted file mode 100644
index 7f0b034dd9a5..000000000000
--- a/include/asm-mips/mips-boards/generic.h
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * This program is free software; you can distribute it and/or modify it
- * under the terms of the GNU General Public License (Version 2) as
- * published by the Free Software Foundation.
- *
- * This program is distributed in the hope it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- * for more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Defines of the MIPS boards specific address-MAP, registers, etc.
- */
-#ifndef __ASM_MIPS_BOARDS_GENERIC_H
-#define __ASM_MIPS_BOARDS_GENERIC_H
-
-#include <asm/addrspace.h>
-#include <asm/byteorder.h>
-#include <asm/mips-boards/bonito64.h>
-
-/*
- * Display register base.
- */
-#define ASCII_DISPLAY_WORD_BASE    0x1f000410
-#define ASCII_DISPLAY_POS_BASE     0x1f000418
-
-
-/*
- * Yamon Prom print address.
- */
-#define YAMON_PROM_PRINT_ADDR      0x1fc00504
-
-
-/*
- * Reset register.
- */
-#define SOFTRES_REG       0x1f000500
-#define GORESET           0x42
-
-/*
- * Revision register.
- */
-#define MIPS_REVISION_REG                  0x1fc00010
-#define MIPS_REVISION_CORID_QED_RM5261     0
-#define MIPS_REVISION_CORID_CORE_LV        1
-#define MIPS_REVISION_CORID_BONITO64       2
-#define MIPS_REVISION_CORID_CORE_20K       3
-#define MIPS_REVISION_CORID_CORE_FPGA      4
-#define MIPS_REVISION_CORID_CORE_MSC       5
-#define MIPS_REVISION_CORID_CORE_EMUL      6
-#define MIPS_REVISION_CORID_CORE_FPGA2     7
-#define MIPS_REVISION_CORID_CORE_FPGAR2    8
-#define MIPS_REVISION_CORID_CORE_FPGA3     9
-#define MIPS_REVISION_CORID_CORE_24K       10
-#define MIPS_REVISION_CORID_CORE_FPGA4     11
-#define MIPS_REVISION_CORID_CORE_FPGA5     12
-
-/**** Artificial corid defines ****/
-/*
- *  CoreEMUL with   Bonito   System Controller is treated like a Core20K
- *  CoreEMUL with SOC-it 101 System Controller is treated like a CoreMSC
- */
-#define MIPS_REVISION_CORID_CORE_EMUL_BON  -1
-#define MIPS_REVISION_CORID_CORE_EMUL_MSC  -2
-
-#define MIPS_REVISION_CORID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 10) & 0x3f)
-
-extern int mips_revision_corid;
-
-#define MIPS_REVISION_SCON_OTHER           0
-#define MIPS_REVISION_SCON_SOCITSC         1
-#define MIPS_REVISION_SCON_SOCITSCP        2
-
-/* Artificial SCON defines for MIPS_REVISION_SCON_OTHER */
-#define MIPS_REVISION_SCON_UNKNOWN         -1
-#define MIPS_REVISION_SCON_GT64120         -2
-#define MIPS_REVISION_SCON_BONITO          -3
-#define MIPS_REVISION_SCON_BRTL            -4
-#define MIPS_REVISION_SCON_SOCIT           -5
-#define MIPS_REVISION_SCON_ROCIT           -6
-
-#define MIPS_REVISION_SCONID (((*(volatile u32 *)ioremap(MIPS_REVISION_REG, 4)) >> 24) & 0xff)
-
-extern int mips_revision_sconid;
-
-extern void mips_reboot_setup(void);
-
-#ifdef CONFIG_PCI
-extern void mips_pcibios_init(void);
-#else
-#define mips_pcibios_init() do { } while (0)
-#endif
-
-#ifdef CONFIG_KGDB
-extern void kgdb_config(void);
-#endif
-
-#endif  /* __ASM_MIPS_BOARDS_GENERIC_H */
diff --git a/include/asm-mips/mips-boards/launch.h b/include/asm-mips/mips-boards/launch.h
deleted file mode 100644
index d8ae7f95a522..000000000000
--- a/include/asm-mips/mips-boards/launch.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- *
- */
-
-#ifndef _ASSEMBLER_
-
-struct cpulaunch {
-    unsigned long       pc;
-    unsigned long       gp;
-    unsigned long       sp;
-    unsigned long       a0;
-    unsigned long       _pad[3]; /* pad to cache line size to avoid thrashing */
-    unsigned long       flags;
-};
-
-#else
-
-#define LOG2CPULAUNCH   5
-#define LAUNCH_PC       0
-#define LAUNCH_GP       4
-#define LAUNCH_SP       8
-#define LAUNCH_A0       12
-#define LAUNCH_FLAGS    28
-
-#endif
-
-#define LAUNCH_FREADY   1
-#define LAUNCH_FGO      2
-#define LAUNCH_FGONE    4
-
-#define CPULAUNCH       0x00000f00
-#define NCPULAUNCH      8
-
-/* Polling period in count cycles for secondary CPU's */
-#define LAUNCHPERIOD    10000
diff --git a/include/asm-mips/mips-boards/malta.h b/include/asm-mips/mips-boards/malta.h
deleted file mode 100644
index c1891578fa65..000000000000
--- a/include/asm-mips/mips-boards/malta.h
+++ /dev/null
@@ -1,102 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Defines of the Malta board specific address-MAP, registers, etc.
- */
-#ifndef __ASM_MIPS_BOARDS_MALTA_H
-#define __ASM_MIPS_BOARDS_MALTA_H
-
-#include <asm/addrspace.h>
-#include <asm/io.h>
-#include <asm/mips-boards/msc01_pci.h>
-#include <asm/gt64120.h>
-
-/* Mips interrupt controller found in SOCit variations */
-#define MIPS_MSC01_IC_REG_BASE          0x1bc40000
-#define MIPS_SOCITSC_IC_REG_BASE        0x1ffa0000
-
-/*
- * Malta I/O ports base address for the Galileo GT64120 and Algorithmics
- * Bonito system controllers.
- */
-#define MALTA_GT_PORT_BASE      get_gt_port_base(GT_PCI0IOLD_OFS)
-#define MALTA_BONITO_PORT_BASE  ((unsigned long)ioremap (0x1fd00000, 0x10000))
-#define MALTA_MSC_PORT_BASE     get_msc_port_base(MSC01_PCI_SC2PIOBASL)
-
-static inline unsigned long get_gt_port_base(unsigned long reg)
-{
-        unsigned long addr;
-        addr = GT_READ(reg);
-        return (unsigned long) ioremap (((addr & 0xffff) << 21), 0x10000);
-}
-
-static inline unsigned long get_msc_port_base(unsigned long reg)
-{
-        unsigned long addr;
-        MSC_READ(reg, addr);
-        return (unsigned long) ioremap(addr, 0x10000);
-}
-
-/*
- * GCMP Specific definitions
- */
-#define GCMP_BASE_ADDR                  0x1fbf8000
-#define GCMP_ADDRSPACE_SZ               (256 * 1024)
-
-/*
- * GIC Specific definitions
- */
-#define GIC_BASE_ADDR                   0x1bdc0000
-#define GIC_ADDRSPACE_SZ                (128 * 1024)
-
-/*
- * MSC01 BIU Specific definitions
- * FIXME : These should be elsewhere ?
- */
-#define MSC01_BIU_REG_BASE              0x1bc80000
-#define MSC01_BIU_ADDRSPACE_SZ          (256 * 1024)
-#define MSC01_SC_CFG_OFS                0x0110
-#define MSC01_SC_CFG_GICPRES_MSK        0x00000004
-#define MSC01_SC_CFG_GICPRES_SHF        2
-#define MSC01_SC_CFG_GICENA_SHF         3
-
-/*
- * Malta RTC-device indirect register access.
- */
-#define MALTA_RTC_ADR_REG       0x70
-#define MALTA_RTC_DAT_REG       0x71
-
-/*
- * Malta SMSC FDC37M817 Super I/O Controller register.
- */
-#define SMSC_CONFIG_REG         0x3f0
-#define SMSC_DATA_REG           0x3f1
-
-#define SMSC_CONFIG_DEVNUM      0x7
-#define SMSC_CONFIG_ACTIVATE    0x30
-#define SMSC_CONFIG_ENTER       0x55
-#define SMSC_CONFIG_EXIT        0xaa
-
-#define SMSC_CONFIG_DEVNUM_FLOPPY     0
-
-#define SMSC_CONFIG_ACTIVATE_ENABLE   1
-
-#define SMSC_WRITE(x, a)     outb(x, a)
-
-#define MALTA_JMPRS_REG         0x1f000210
-
-#endif /* __ASM_MIPS_BOARDS_MALTA_H */
diff --git a/include/asm-mips/mips-boards/maltaint.h b/include/asm-mips/mips-boards/maltaint.h
deleted file mode 100644
index cea872fc6f5c..000000000000
--- a/include/asm-mips/mips-boards/maltaint.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * Defines for the Malta interrupt controller.
- *
- */
-#ifndef _MIPS_MALTAINT_H
-#define _MIPS_MALTAINT_H
-
-#include <irq.h>
-
-/*
- * Interrupts 0..15 are used for Malta ISA compatible interrupts
- */
-#define MALTA_INT_BASE          0
-
-/* CPU interrupt offsets */
-#define MIPSCPU_INT_SW0         0
-#define MIPSCPU_INT_SW1         1
-#define MIPSCPU_INT_MB0         2
-#define MIPSCPU_INT_I8259A      MIPSCPU_INT_MB0
-#define MIPSCPU_INT_MB1         3
-#define MIPSCPU_INT_SMI         MIPSCPU_INT_MB1
-#define MIPSCPU_INT_IPI0        MIPSCPU_INT_MB1 /* GIC IPI */
-#define MIPSCPU_INT_MB2         4
-#define MIPSCPU_INT_IPI1        MIPSCPU_INT_MB2 /* GIC IPI */
-#define MIPSCPU_INT_MB3         5
-#define MIPSCPU_INT_COREHI      MIPSCPU_INT_MB3
-#define MIPSCPU_INT_MB4         6
-#define MIPSCPU_INT_CORELO      MIPSCPU_INT_MB4
-
-/*
- * Interrupts 64..127 are used for Soc-it Classic interrupts
- */
-#define MSC01C_INT_BASE         64
-
-/* SOC-it Classic interrupt offsets */
-#define MSC01C_INT_TMR          0
-#define MSC01C_INT_PCI          1
-
-/*
- * Interrupts 64..127 are used for Soc-it EIC interrupts
- */
-#define MSC01E_INT_BASE         64
-
-/* SOC-it EIC interrupt offsets */
-#define MSC01E_INT_SW0          1
-#define MSC01E_INT_SW1          2
-#define MSC01E_INT_MB0          3
-#define MSC01E_INT_I8259A       MSC01E_INT_MB0
-#define MSC01E_INT_MB1          4
-#define MSC01E_INT_SMI          MSC01E_INT_MB1
-#define MSC01E_INT_MB2          5
-#define MSC01E_INT_MB3          6
-#define MSC01E_INT_COREHI       MSC01E_INT_MB3
-#define MSC01E_INT_MB4          7
-#define MSC01E_INT_CORELO       MSC01E_INT_MB4
-#define MSC01E_INT_TMR          8
-#define MSC01E_INT_PCI          9
-#define MSC01E_INT_PERFCTR      10
-#define MSC01E_INT_CPUCTR       11
-
-/* GIC's Nomenclature for Core Interrupt Pins on the Malta */
-#define GIC_CPU_INT0            0 /* Core Interrupt 2   */
-#define GIC_CPU_INT1            1 /* .                  */
-#define GIC_CPU_INT2            2 /* .                  */
-#define GIC_CPU_INT3            3 /* .                  */
-#define GIC_CPU_INT4            4 /* .                  */
-#define GIC_CPU_INT5            5 /* Core Interrupt 5   */
-
-#define GIC_EXT_INTR(x)         x
-
-/* Dummy data */
-#define X                       0xdead
-
-/* External Interrupts used for IPI */
-#define GIC_IPI_EXT_INTR_RESCHED_VPE0   16
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE0   17
-#define GIC_IPI_EXT_INTR_RESCHED_VPE1   18
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE1   19
-#define GIC_IPI_EXT_INTR_RESCHED_VPE2   20
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE2   21
-#define GIC_IPI_EXT_INTR_RESCHED_VPE3   22
-#define GIC_IPI_EXT_INTR_CALLFNC_VPE3   23
-
-#define MIPS_GIC_IRQ_BASE       (MIPS_CPU_IRQ_BASE + 8)
-
-#ifndef __ASSEMBLY__
-extern void maltaint_init(void);
-#endif
-
-#endif /* !(_MIPS_MALTAINT_H) */
diff --git a/include/asm-mips/mips-boards/msc01_pci.h b/include/asm-mips/mips-boards/msc01_pci.h
deleted file mode 100644
index e036b7dd6deb..000000000000
--- a/include/asm-mips/mips-boards/msc01_pci.h
+++ /dev/null
@@ -1,258 +0,0 @@
-/*
- * PCI Register definitions for the MIPS System Controller.
- *
- * Copyright (C) 2002, 2005  MIPS Technologies, Inc.  All rights reserved.
- *      Authors: Carsten Langgaard <carstenl@mips.com>
- *               Maciej W. Rozycki <macro@mips.com>
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_MIPS_BOARDS_MSC01_PCI_H
-#define __ASM_MIPS_BOARDS_MSC01_PCI_H
-
-/*
- * Register offset addresses
- */
-
-#define MSC01_PCI_ID_OFS                0x0000
-#define MSC01_PCI_SC2PMBASL_OFS         0x0208
-#define MSC01_PCI_SC2PMMSKL_OFS         0x0218
-#define MSC01_PCI_SC2PMMAPL_OFS         0x0228
-#define MSC01_PCI_SC2PIOBASL_OFS        0x0248
-#define MSC01_PCI_SC2PIOMSKL_OFS        0x0258
-#define MSC01_PCI_SC2PIOMAPL_OFS        0x0268
-#define MSC01_PCI_P2SCMSKL_OFS          0x0308
-#define MSC01_PCI_P2SCMAPL_OFS          0x0318
-#define MSC01_PCI_INTCFG_OFS            0x0600
-#define MSC01_PCI_INTSTAT_OFS           0x0608
-#define MSC01_PCI_CFGADDR_OFS           0x0610
-#define MSC01_PCI_CFGDATA_OFS           0x0618
-#define MSC01_PCI_IACK_OFS              0x0620
-#define MSC01_PCI_HEAD0_OFS             0x2000  /* DevID, VendorID */
-#define MSC01_PCI_HEAD1_OFS             0x2008  /* Status, Command */
-#define MSC01_PCI_HEAD2_OFS             0x2010  /* Class code, RevID */
-#define MSC01_PCI_HEAD3_OFS             0x2018  /* bist, header, latency */
-#define MSC01_PCI_HEAD4_OFS             0x2020  /* BAR 0 */
-#define MSC01_PCI_HEAD5_OFS             0x2028  /* BAR 1 */
-#define MSC01_PCI_HEAD6_OFS             0x2030  /* BAR 2 */
-#define MSC01_PCI_HEAD7_OFS             0x2038  /* BAR 3 */
-#define MSC01_PCI_HEAD8_OFS             0x2040  /* BAR 4 */
-#define MSC01_PCI_HEAD9_OFS             0x2048  /* BAR 5 */
-#define MSC01_PCI_HEAD10_OFS            0x2050  /* CardBus CIS Ptr */
-#define MSC01_PCI_HEAD11_OFS            0x2058  /* SubSystem ID, -VendorID */
-#define MSC01_PCI_HEAD12_OFS            0x2060  /* ROM BAR */
-#define MSC01_PCI_HEAD13_OFS            0x2068  /* Capabilities ptr */
-#define MSC01_PCI_HEAD14_OFS            0x2070  /* reserved */
-#define MSC01_PCI_HEAD15_OFS            0x2078  /* Maxl, ming, intpin, int */
-#define MSC01_PCI_BAR0_OFS              0x2220
-#define MSC01_PCI_CFG_OFS               0x2380
-#define MSC01_PCI_SWAP_OFS              0x2388
-
-
-/*****************************************************************************
- * Register encodings
- ****************************************************************************/
-
-#define MSC01_PCI_ID_ID_SHF             16
-#define MSC01_PCI_ID_ID_MSK             0x00ff0000
-#define MSC01_PCI_ID_ID_HOSTBRIDGE      82
-#define MSC01_PCI_ID_MAR_SHF            8
-#define MSC01_PCI_ID_MAR_MSK            0x0000ff00
-#define MSC01_PCI_ID_MIR_SHF            0
-#define MSC01_PCI_ID_MIR_MSK            0x000000ff
-
-#define MSC01_PCI_SC2PMBASL_BAS_SHF     24
-#define MSC01_PCI_SC2PMBASL_BAS_MSK     0xff000000
-
-#define MSC01_PCI_SC2PMMSKL_MSK_SHF     24
-#define MSC01_PCI_SC2PMMSKL_MSK_MSK     0xff000000
-
-#define MSC01_PCI_SC2PMMAPL_MAP_SHF     24
-#define MSC01_PCI_SC2PMMAPL_MAP_MSK     0xff000000
-
-#define MSC01_PCI_SC2PIOBASL_BAS_SHF    24
-#define MSC01_PCI_SC2PIOBASL_BAS_MSK    0xff000000
-
-#define MSC01_PCI_SC2PIOMSKL_MSK_SHF    24
-#define MSC01_PCI_SC2PIOMSKL_MSK_MSK    0xff000000
-
-#define MSC01_PCI_SC2PIOMAPL_MAP_SHF    24
-#define MSC01_PCI_SC2PIOMAPL_MAP_MSK    0xff000000
-
-#define MSC01_PCI_P2SCMSKL_MSK_SHF      24
-#define MSC01_PCI_P2SCMSKL_MSK_MSK      0xff000000
-
-#define MSC01_PCI_P2SCMAPL_MAP_SHF      24
-#define MSC01_PCI_P2SCMAPL_MAP_MSK      0xff000000
-
-#define MSC01_PCI_INTCFG_RST_SHF        10
-#define MSC01_PCI_INTCFG_RST_MSK        0x00000400
-#define MSC01_PCI_INTCFG_RST_BIT        0x00000400
-#define MSC01_PCI_INTCFG_MWE_SHF        9
-#define MSC01_PCI_INTCFG_MWE_MSK        0x00000200
-#define MSC01_PCI_INTCFG_MWE_BIT        0x00000200
-#define MSC01_PCI_INTCFG_DTO_SHF        8
-#define MSC01_PCI_INTCFG_DTO_MSK        0x00000100
-#define MSC01_PCI_INTCFG_DTO_BIT        0x00000100
-#define MSC01_PCI_INTCFG_MA_SHF         7
-#define MSC01_PCI_INTCFG_MA_MSK         0x00000080
-#define MSC01_PCI_INTCFG_MA_BIT         0x00000080
-#define MSC01_PCI_INTCFG_TA_SHF         6
-#define MSC01_PCI_INTCFG_TA_MSK         0x00000040
-#define MSC01_PCI_INTCFG_TA_BIT         0x00000040
-#define MSC01_PCI_INTCFG_RTY_SHF        5
-#define MSC01_PCI_INTCFG_RTY_MSK        0x00000020
-#define MSC01_PCI_INTCFG_RTY_BIT        0x00000020
-#define MSC01_PCI_INTCFG_MWP_SHF        4
-#define MSC01_PCI_INTCFG_MWP_MSK        0x00000010
-#define MSC01_PCI_INTCFG_MWP_BIT        0x00000010
-#define MSC01_PCI_INTCFG_MRP_SHF        3
-#define MSC01_PCI_INTCFG_MRP_MSK        0x00000008
-#define MSC01_PCI_INTCFG_MRP_BIT        0x00000008
-#define MSC01_PCI_INTCFG_SWP_SHF        2
-#define MSC01_PCI_INTCFG_SWP_MSK        0x00000004
-#define MSC01_PCI_INTCFG_SWP_BIT        0x00000004
-#define MSC01_PCI_INTCFG_SRP_SHF        1
-#define MSC01_PCI_INTCFG_SRP_MSK        0x00000002
-#define MSC01_PCI_INTCFG_SRP_BIT        0x00000002
-#define MSC01_PCI_INTCFG_SE_SHF         0
-#define MSC01_PCI_INTCFG_SE_MSK         0x00000001
-#define MSC01_PCI_INTCFG_SE_BIT         0x00000001
-
-#define MSC01_PCI_INTSTAT_RST_SHF       10
-#define MSC01_PCI_INTSTAT_RST_MSK       0x00000400
-#define MSC01_PCI_INTSTAT_RST_BIT       0x00000400
-#define MSC01_PCI_INTSTAT_MWE_SHF       9
-#define MSC01_PCI_INTSTAT_MWE_MSK       0x00000200
-#define MSC01_PCI_INTSTAT_MWE_BIT       0x00000200
-#define MSC01_PCI_INTSTAT_DTO_SHF       8
-#define MSC01_PCI_INTSTAT_DTO_MSK       0x00000100
-#define MSC01_PCI_INTSTAT_DTO_BIT       0x00000100
-#define MSC01_PCI_INTSTAT_MA_SHF        7
-#define MSC01_PCI_INTSTAT_MA_MSK        0x00000080
-#define MSC01_PCI_INTSTAT_MA_BIT        0x00000080
-#define MSC01_PCI_INTSTAT_TA_SHF        6
-#define MSC01_PCI_INTSTAT_TA_MSK        0x00000040
-#define MSC01_PCI_INTSTAT_TA_BIT        0x00000040
-#define MSC01_PCI_INTSTAT_RTY_SHF       5
-#define MSC01_PCI_INTSTAT_RTY_MSK       0x00000020
-#define MSC01_PCI_INTSTAT_RTY_BIT       0x00000020
-#define MSC01_PCI_INTSTAT_MWP_SHF       4
-#define MSC01_PCI_INTSTAT_MWP_MSK       0x00000010
-#define MSC01_PCI_INTSTAT_MWP_BIT       0x00000010
-#define MSC01_PCI_INTSTAT_MRP_SHF       3
-#define MSC01_PCI_INTSTAT_MRP_MSK       0x00000008
-#define MSC01_PCI_INTSTAT_MRP_BIT       0x00000008
-#define MSC01_PCI_INTSTAT_SWP_SHF       2
-#define MSC01_PCI_INTSTAT_SWP_MSK       0x00000004
-#define MSC01_PCI_INTSTAT_SWP_BIT       0x00000004
-#define MSC01_PCI_INTSTAT_SRP_SHF       1
-#define MSC01_PCI_INTSTAT_SRP_MSK       0x00000002
-#define MSC01_PCI_INTSTAT_SRP_BIT       0x00000002
-#define MSC01_PCI_INTSTAT_SE_SHF        0
-#define MSC01_PCI_INTSTAT_SE_MSK        0x00000001
-#define MSC01_PCI_INTSTAT_SE_BIT        0x00000001
-
-#define MSC01_PCI_CFGADDR_BNUM_SHF      16
-#define MSC01_PCI_CFGADDR_BNUM_MSK      0x00ff0000
-#define MSC01_PCI_CFGADDR_DNUM_SHF      11
-#define MSC01_PCI_CFGADDR_DNUM_MSK      0x0000f800
-#define MSC01_PCI_CFGADDR_FNUM_SHF      8
-#define MSC01_PCI_CFGADDR_FNUM_MSK      0x00000700
-#define MSC01_PCI_CFGADDR_RNUM_SHF      2
-#define MSC01_PCI_CFGADDR_RNUM_MSK      0x000000fc
-
-#define MSC01_PCI_CFGDATA_DATA_SHF      0
-#define MSC01_PCI_CFGDATA_DATA_MSK      0xffffffff
-
-/* The defines below are ONLY valid for a MEM bar! */
-#define MSC01_PCI_BAR0_SIZE_SHF         4
-#define MSC01_PCI_BAR0_SIZE_MSK         0xfffffff0
-#define MSC01_PCI_BAR0_P_SHF            3
-#define MSC01_PCI_BAR0_P_MSK            0x00000008
-#define MSC01_PCI_BAR0_P_BIT            MSC01_PCI_BAR0_P_MSK
-#define MSC01_PCI_BAR0_D_SHF            1
-#define MSC01_PCI_BAR0_D_MSK            0x00000006
-#define MSC01_PCI_BAR0_T_SHF            0
-#define MSC01_PCI_BAR0_T_MSK            0x00000001
-#define MSC01_PCI_BAR0_T_BIT            MSC01_PCI_BAR0_T_MSK
-
-
-#define MSC01_PCI_CFG_RA_SHF            17
-#define MSC01_PCI_CFG_RA_MSK            0x00020000
-#define MSC01_PCI_CFG_RA_BIT            MSC01_PCI_CFG_RA_MSK
-#define MSC01_PCI_CFG_G_SHF             16
-#define MSC01_PCI_CFG_G_MSK             0x00010000
-#define MSC01_PCI_CFG_G_BIT             MSC01_PCI_CFG_G_MSK
-#define MSC01_PCI_CFG_EN_SHF            15
-#define MSC01_PCI_CFG_EN_MSK            0x00008000
-#define MSC01_PCI_CFG_EN_BIT            MSC01_PCI_CFG_EN_MSK
-#define MSC01_PCI_CFG_MAXRTRY_SHF       0
-#define MSC01_PCI_CFG_MAXRTRY_MSK       0x00000fff
-
-#define MSC01_PCI_SWAP_IO_SHF           18
-#define MSC01_PCI_SWAP_IO_MSK           0x000c0000
-#define MSC01_PCI_SWAP_MEM_SHF          16
-#define MSC01_PCI_SWAP_MEM_MSK          0x00030000
-#define MSC01_PCI_SWAP_BAR0_SHF         0
-#define MSC01_PCI_SWAP_BAR0_MSK         0x00000003
-#define MSC01_PCI_SWAP_NOSWAP           0
-#define MSC01_PCI_SWAP_BYTESWAP         1
-
-/*
- * MIPS System controller PCI register base.
- *
- * FIXME - are these macros specific to Malta and co or to the MSC?  If the
- * latter, they should be moved elsewhere.
- */
-#define MIPS_MSC01_PCI_REG_BASE         0x1bd00000
-#define MIPS_SOCITSC_PCI_REG_BASE       0x1ff10000
-
-extern unsigned long _pcictrl_msc;
-
-#define MSC01_PCI_REG_BASE      _pcictrl_msc
-
-#define MSC_WRITE(reg, data)    do { *(volatile u32 *)(reg) = data; } while (0)
-#define MSC_READ(reg, data)     do { data = *(volatile u32 *)(reg); } while (0)
-
-/*
- * Registers absolute addresses
- */
-
-#define MSC01_PCI_ID            (MSC01_PCI_REG_BASE + MSC01_PCI_ID_OFS)
-#define MSC01_PCI_SC2PMBASL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMBASL_OFS)
-#define MSC01_PCI_SC2PMMSKL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMSKL_OFS)
-#define MSC01_PCI_SC2PMMAPL     (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PMMAPL_OFS)
-#define MSC01_PCI_SC2PIOBASL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOBASL_OFS)
-#define MSC01_PCI_SC2PIOMSKL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMSKL_OFS)
-#define MSC01_PCI_SC2PIOMAPL    (MSC01_PCI_REG_BASE + MSC01_PCI_SC2PIOMAPL_OFS)
-#define MSC01_PCI_P2SCMSKL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMSKL_OFS)
-#define MSC01_PCI_P2SCMAPL      (MSC01_PCI_REG_BASE + MSC01_PCI_P2SCMAPL_OFS)
-#define MSC01_PCI_INTCFG        (MSC01_PCI_REG_BASE + MSC01_PCI_INTCFG_OFS)
-#define MSC01_PCI_INTSTAT       (MSC01_PCI_REG_BASE + MSC01_PCI_INTSTAT_OFS)
-#define MSC01_PCI_CFGADDR       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGADDR_OFS)
-#define MSC01_PCI_CFGDATA       (MSC01_PCI_REG_BASE + MSC01_PCI_CFGDATA_OFS)
-#define MSC01_PCI_IACK          (MSC01_PCI_REG_BASE + MSC01_PCI_IACK_OFS)
-#define MSC01_PCI_HEAD0         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD0_OFS)
-#define MSC01_PCI_HEAD1         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD1_OFS)
-#define MSC01_PCI_HEAD2         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD2_OFS)
-#define MSC01_PCI_HEAD3         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD3_OFS)
-#define MSC01_PCI_HEAD4         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD4_OFS)
-#define MSC01_PCI_HEAD5         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD5_OFS)
-#define MSC01_PCI_HEAD6         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD6_OFS)
-#define MSC01_PCI_HEAD7         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD7_OFS)
-#define MSC01_PCI_HEAD8         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD8_OFS)
-#define MSC01_PCI_HEAD9         (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD9_OFS)
-#define MSC01_PCI_HEAD10        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD10_OFS)
-#define MSC01_PCI_HEAD11        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD12        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD13        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD14        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_HEAD15        (MSC01_PCI_REG_BASE + MSC01_PCI_HEAD11_OFS)
-#define MSC01_PCI_BAR0          (MSC01_PCI_REG_BASE + MSC01_PCI_BAR0_OFS)
-#define MSC01_PCI_CFG           (MSC01_PCI_REG_BASE + MSC01_PCI_CFG_OFS)
-#define MSC01_PCI_SWAP          (MSC01_PCI_REG_BASE + MSC01_PCI_SWAP_OFS)
-
-#endif /* __ASM_MIPS_BOARDS_MSC01_PCI_H */
diff --git a/include/asm-mips/mips-boards/piix4.h b/include/asm-mips/mips-boards/piix4.h
deleted file mode 100644
index 2971d60f2e95..000000000000
--- a/include/asm-mips/mips-boards/piix4.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * Register definitions for Intel PIIX4 South Bridge Device.
- */
-#ifndef __ASM_MIPS_BOARDS_PIIX4_H
-#define __ASM_MIPS_BOARDS_PIIX4_H
-
-/************************************************************************
- *  IO register offsets
- ************************************************************************/
-#define PIIX4_ICTLR1_ICW1       0x20
-#define PIIX4_ICTLR1_ICW2       0x21
-#define PIIX4_ICTLR1_ICW3       0x21
-#define PIIX4_ICTLR1_ICW4       0x21
-#define PIIX4_ICTLR2_ICW1       0xa0
-#define PIIX4_ICTLR2_ICW2       0xa1
-#define PIIX4_ICTLR2_ICW3       0xa1
-#define PIIX4_ICTLR2_ICW4       0xa1
-#define PIIX4_ICTLR1_OCW1       0x21
-#define PIIX4_ICTLR1_OCW2       0x20
-#define PIIX4_ICTLR1_OCW3       0x20
-#define PIIX4_ICTLR1_OCW4       0x20
-#define PIIX4_ICTLR2_OCW1       0xa1
-#define PIIX4_ICTLR2_OCW2       0xa0
-#define PIIX4_ICTLR2_OCW3       0xa0
-#define PIIX4_ICTLR2_OCW4       0xa0
-
-
-/************************************************************************
- *  Register encodings.
- ************************************************************************/
-#define PIIX4_OCW2_NSEOI        (0x1 << 5)
-#define PIIX4_OCW2_SEOI         (0x3 << 5)
-#define PIIX4_OCW2_RNSEOI       (0x5 << 5)
-#define PIIX4_OCW2_RAEOIS       (0x4 << 5)
-#define PIIX4_OCW2_RAEOIC       (0x0 << 5)
-#define PIIX4_OCW2_RSEOI        (0x7 << 5)
-#define PIIX4_OCW2_SP           (0x6 << 5)
-#define PIIX4_OCW2_NOP          (0x2 << 5)
-
-#define PIIX4_OCW2_SEL          (0x0 << 3)
-
-#define PIIX4_OCW2_ILS_0        0
-#define PIIX4_OCW2_ILS_1        1
-#define PIIX4_OCW2_ILS_2        2
-#define PIIX4_OCW2_ILS_3        3
-#define PIIX4_OCW2_ILS_4        4
-#define PIIX4_OCW2_ILS_5        5
-#define PIIX4_OCW2_ILS_6        6
-#define PIIX4_OCW2_ILS_7        7
-#define PIIX4_OCW2_ILS_8        0
-#define PIIX4_OCW2_ILS_9        1
-#define PIIX4_OCW2_ILS_10       2
-#define PIIX4_OCW2_ILS_11       3
-#define PIIX4_OCW2_ILS_12       4
-#define PIIX4_OCW2_ILS_13       5
-#define PIIX4_OCW2_ILS_14       6
-#define PIIX4_OCW2_ILS_15       7
-
-#define PIIX4_OCW3_SEL          (0x1 << 3)
-
-#define PIIX4_OCW3_IRR          0x2
-#define PIIX4_OCW3_ISR          0x3
-
-#endif /* __ASM_MIPS_BOARDS_PIIX4_H */
diff --git a/include/asm-mips/mips-boards/prom.h b/include/asm-mips/mips-boards/prom.h
deleted file mode 100644
index a9db576a9768..000000000000
--- a/include/asm-mips/mips-boards/prom.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- *
- * MIPS boards bootprom interface for the Linux kernel.
- *
- */
-
-#ifndef _MIPS_PROM_H
-#define _MIPS_PROM_H
-
-extern char *prom_getcmdline(void);
-extern char *prom_getenv(char *name);
-extern void prom_init_cmdline(void);
-extern void prom_meminit(void);
-extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-extern void mips_display_message(const char *str);
-extern void mips_display_word(unsigned int num);
-extern void mips_scroll_message(void);
-extern int get_ethernet_addr(char *ethernet_addr);
-
-/* Memory descriptor management. */
-#define PROM_MAX_PMEMBLOCKS    32
-struct prom_pmemblock {
-        unsigned long base; /* Within KSEG0. */
-        unsigned int size;  /* In bytes. */
-        unsigned int type;  /* free or prom memory */
-};
-
-#endif /* !(_MIPS_PROM_H) */
diff --git a/include/asm-mips/mips-boards/sim.h b/include/asm-mips/mips-boards/sim.h
deleted file mode 100644
index acb7c2331d98..000000000000
--- a/include/asm-mips/mips-boards/sim.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _ASM_MIPS_BOARDS_SIM_H
-#define _ASM_MIPS_BOARDS_SIM_H
-
-#define STATS_ON        1
-#define STATS_OFF       2
-#define STATS_CLEAR     3
-#define STATS_DUMP      4
-#define TRACE_ON                5
-#define TRACE_OFF       6
-
-
-#define simcfg(code)                                            \
-({                                         \
-        __asm__  __volatile__( \
-        "sltiu $0,$0, %0" \
-                ::"i"(code)                                     \
-                ); \
-})
-
-
-
-#endif
diff --git a/include/asm-mips/mips-boards/simint.h b/include/asm-mips/mips-boards/simint.h
deleted file mode 100644
index 8ef6db76d5c1..000000000000
--- a/include/asm-mips/mips-boards/simint.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- */
-#ifndef _MIPS_SIMINT_H
-#define _MIPS_SIMINT_H
-
-#include <irq.h>
-
-#define SIM_INT_BASE            0
-#define MIPSCPU_INT_MB0         2
-#define MIPS_CPU_TIMER_IRQ      7
-
-
-#define MSC01E_INT_BASE         64
-
-#define MSC01E_INT_CPUCTR       11
-
-#endif
diff --git a/include/asm-mips/mips_mt.h b/include/asm-mips/mips_mt.h
deleted file mode 100644
index ac7935203f89..000000000000
--- a/include/asm-mips/mips_mt.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Definitions and decalrations for MIPS MT support
- * that are common between SMTC, VSMP, and/or AP/SP
- * kernel models.
- */
-#ifndef __ASM_MIPS_MT_H
-#define __ASM_MIPS_MT_H
-
-#include <linux/cpumask.h>
-
-/*
- * How many VPEs and TCs is Linux allowed to use?  0 means no limit.
- */
-extern int tclimit;
-extern int vpelimit;
-
-extern cpumask_t mt_fpu_cpumask;
-extern unsigned long mt_fpemul_threshold;
-
-extern void mips_mt_regdump(unsigned long previous_mvpcontrol_value);
-extern void mips_mt_set_cpuoptions(void);
-
-struct class;
-extern struct class *mt_class;
-
-#endif /* __ASM_MIPS_MT_H */
diff --git a/include/asm-mips/mipsmtregs.h b/include/asm-mips/mipsmtregs.h
deleted file mode 100644
index c9420aa97e32..000000000000
--- a/include/asm-mips/mipsmtregs.h
+++ /dev/null
@@ -1,395 +0,0 @@
-/*
- * MT regs definitions, follows on from mipsregs.h
- * Copyright (C) 2004 - 2005 MIPS Technologies, Inc.  All rights reserved.
- * Elizabeth Clarke et. al.
- *
- */
-#ifndef _ASM_MIPSMTREGS_H
-#define _ASM_MIPSMTREGS_H
-
-#include <asm/mipsregs.h>
-#include <asm/war.h>
-
-#ifndef __ASSEMBLY__
-
-/*
- * C macros
- */
-
-#define read_c0_mvpcontrol()            __read_32bit_c0_register($0, 1)
-#define write_c0_mvpcontrol(val)        __write_32bit_c0_register($0, 1, val)
-
-#define read_c0_mvpconf0()              __read_32bit_c0_register($0, 2)
-#define read_c0_mvpconf1()              __read_32bit_c0_register($0, 3)
-
-#define read_c0_vpecontrol()            __read_32bit_c0_register($1, 1)
-#define write_c0_vpecontrol(val)        __write_32bit_c0_register($1, 1, val)
-
-#define read_c0_vpeconf0()              __read_32bit_c0_register($1, 2)
-#define write_c0_vpeconf0(val)          __write_32bit_c0_register($1, 2, val)
-
-#define read_c0_tcstatus()              __read_32bit_c0_register($2, 1)
-#define write_c0_tcstatus(val)          __write_32bit_c0_register($2, 1, val)
-
-#define read_c0_tcbind()                __read_32bit_c0_register($2, 2)
-
-#define read_c0_tccontext()             __read_32bit_c0_register($2, 5)
-#define write_c0_tccontext(val)         __write_32bit_c0_register($2, 5, val)
-
-#else /* Assembly */
-/*
- * Macros for use in assembly language code
- */
-
-#define CP0_MVPCONTROL          $0, 1
-#define CP0_MVPCONF0            $0, 2
-#define CP0_MVPCONF1            $0, 3
-#define CP0_VPECONTROL          $1, 1
-#define CP0_VPECONF0            $1, 2
-#define CP0_VPECONF1            $1, 3
-#define CP0_YQMASK              $1, 4
-#define CP0_VPESCHEDULE $1, 5
-#define CP0_VPESCHEFBK          $1, 6
-#define CP0_TCSTATUS            $2, 1
-#define CP0_TCBIND              $2, 2
-#define CP0_TCRESTART           $2, 3
-#define CP0_TCHALT              $2, 4
-#define CP0_TCCONTEXT           $2, 5
-#define CP0_TCSCHEDULE          $2, 6
-#define CP0_TCSCHEFBK           $2, 7
-#define CP0_SRSCONF0            $6, 1
-#define CP0_SRSCONF1            $6, 2
-#define CP0_SRSCONF2            $6, 3
-#define CP0_SRSCONF3            $6, 4
-#define CP0_SRSCONF4            $6, 5
-
-#endif
-
-/* MVPControl fields */
-#define MVPCONTROL_EVP          (_ULCAST_(1))
-
-#define MVPCONTROL_VPC_SHIFT    1
-#define MVPCONTROL_VPC          (_ULCAST_(1) << MVPCONTROL_VPC_SHIFT)
-
-#define MVPCONTROL_STLB_SHIFT   2
-#define MVPCONTROL_STLB         (_ULCAST_(1) << MVPCONTROL_STLB_SHIFT)
-
-
-/* MVPConf0 fields */
-#define MVPCONF0_PTC_SHIFT      0
-#define MVPCONF0_PTC            ( _ULCAST_(0xff))
-#define MVPCONF0_PVPE_SHIFT     10
-#define MVPCONF0_PVPE           ( _ULCAST_(0xf) << MVPCONF0_PVPE_SHIFT)
-#define MVPCONF0_TCA_SHIFT      15
-#define MVPCONF0_TCA            ( _ULCAST_(1) << MVPCONF0_TCA_SHIFT)
-#define MVPCONF0_PTLBE_SHIFT    16
-#define MVPCONF0_PTLBE          (_ULCAST_(0x3ff) << MVPCONF0_PTLBE_SHIFT)
-#define MVPCONF0_TLBS_SHIFT     29
-#define MVPCONF0_TLBS           (_ULCAST_(1) << MVPCONF0_TLBS_SHIFT)
-#define MVPCONF0_M_SHIFT        31
-#define MVPCONF0_M              (_ULCAST_(0x1) << MVPCONF0_M_SHIFT)
-
-
-/* config3 fields */
-#define CONFIG3_MT_SHIFT        2
-#define CONFIG3_MT              (_ULCAST_(1) << CONFIG3_MT_SHIFT)
-
-
-/* VPEControl fields (per VPE) */
-#define VPECONTROL_TARGTC       (_ULCAST_(0xff))
-
-#define VPECONTROL_TE_SHIFT     15
-#define VPECONTROL_TE           (_ULCAST_(1) << VPECONTROL_TE_SHIFT)
-#define VPECONTROL_EXCPT_SHIFT  16
-#define VPECONTROL_EXCPT        (_ULCAST_(0x7) << VPECONTROL_EXCPT_SHIFT)
-
-/* Thread Exception Codes for EXCPT field */
-#define THREX_TU                0
-#define THREX_TO                1
-#define THREX_IYQ               2
-#define THREX_GSX               3
-#define THREX_YSCH              4
-#define THREX_GSSCH             5
-
-#define VPECONTROL_GSI_SHIFT    20
-#define VPECONTROL_GSI          (_ULCAST_(1) << VPECONTROL_GSI_SHIFT)
-#define VPECONTROL_YSI_SHIFT    21
-#define VPECONTROL_YSI          (_ULCAST_(1) << VPECONTROL_YSI_SHIFT)
-
-/* VPEConf0 fields (per VPE) */
-#define VPECONF0_VPA_SHIFT      0
-#define VPECONF0_VPA            (_ULCAST_(1) << VPECONF0_VPA_SHIFT)
-#define VPECONF0_MVP_SHIFT      1
-#define VPECONF0_MVP            (_ULCAST_(1) << VPECONF0_MVP_SHIFT)
-#define VPECONF0_XTC_SHIFT      21
-#define VPECONF0_XTC            (_ULCAST_(0xff) << VPECONF0_XTC_SHIFT)
-
-/* TCStatus fields (per TC) */
-#define TCSTATUS_TASID          (_ULCAST_(0xff))
-#define TCSTATUS_IXMT_SHIFT     10
-#define TCSTATUS_IXMT           (_ULCAST_(1) << TCSTATUS_IXMT_SHIFT)
-#define TCSTATUS_TKSU_SHIFT     11
-#define TCSTATUS_TKSU           (_ULCAST_(3) << TCSTATUS_TKSU_SHIFT)
-#define TCSTATUS_A_SHIFT        13
-#define TCSTATUS_A              (_ULCAST_(1) << TCSTATUS_A_SHIFT)
-#define TCSTATUS_DA_SHIFT       15
-#define TCSTATUS_DA             (_ULCAST_(1) << TCSTATUS_DA_SHIFT)
-#define TCSTATUS_DT_SHIFT       20
-#define TCSTATUS_DT             (_ULCAST_(1) << TCSTATUS_DT_SHIFT)
-#define TCSTATUS_TDS_SHIFT      21
-#define TCSTATUS_TDS            (_ULCAST_(1) << TCSTATUS_TDS_SHIFT)
-#define TCSTATUS_TSST_SHIFT     22
-#define TCSTATUS_TSST           (_ULCAST_(1) << TCSTATUS_TSST_SHIFT)
-#define TCSTATUS_RNST_SHIFT     23
-#define TCSTATUS_RNST           (_ULCAST_(3) << TCSTATUS_RNST_SHIFT)
-/* Codes for RNST */
-#define TC_RUNNING              0
-#define TC_WAITING              1
-#define TC_YIELDING             2
-#define TC_GATED                3
-
-#define TCSTATUS_TMX_SHIFT      27
-#define TCSTATUS_TMX            (_ULCAST_(1) << TCSTATUS_TMX_SHIFT)
-/* TCStatus TCU bits can use same definitions/offsets as CU bits in Status */
-
-/* TCBind */
-#define TCBIND_CURVPE_SHIFT     0
-#define TCBIND_CURVPE           (_ULCAST_(0xf))
-
-#define TCBIND_CURTC_SHIFT      21
-
-#define TCBIND_CURTC            (_ULCAST_(0xff) << TCBIND_CURTC_SHIFT)
-
-/* TCHalt */
-#define TCHALT_H                (_ULCAST_(1))
-
-#ifndef __ASSEMBLY__
-
-static inline unsigned int dvpe(void)
-{
-        int res = 0;
-
-        __asm__ __volatile__(
-        "       .set    push                                            \n"
-        "       .set    noreorder                                       \n"
-        "       .set    noat                                            \n"
-        "       .set    mips32r2                                        \n"
-        "       .word   0x41610001              # dvpe $1               \n"
-        "       move    %0, $1                                          \n"
-        "       ehb                                                     \n"
-        "       .set    pop                                             \n"
-        : "=r" (res));
-
-        instruction_hazard();
-
-        return res;
-}
-
-static inline void __raw_evpe(void)
-{
-        __asm__ __volatile__(
-        "       .set    push                                            \n"
-        "       .set    noreorder                                       \n"
-        "       .set    noat                                            \n"
-        "       .set    mips32r2                                        \n"
-        "       .word   0x41600021              # evpe                  \n"
-        "       ehb                                                     \n"
-        "       .set    pop                                             \n");
-}
-
-/* Enable virtual processor execution if previous suggested it should be.
-   EVPE_ENABLE to force */
-
-#define EVPE_ENABLE MVPCONTROL_EVP
-
-static inline void evpe(int previous)
-{
-        if ((previous & MVPCONTROL_EVP))
-                __raw_evpe();
-}
-
-static inline unsigned int dmt(void)
-{
-        int res;
-
-        __asm__ __volatile__(
-        "       .set    push                                            \n"
-        "       .set    mips32r2                                        \n"
-        "       .set    noat                                            \n"
-        "       .word   0x41610BC1                      # dmt $1        \n"
-        "       ehb                                                     \n"
-        "       move    %0, $1                                          \n"
-        "       .set    pop                                             \n"
-        : "=r" (res));
-
-        instruction_hazard();
-
-        return res;
-}
-
-static inline void __raw_emt(void)
-{
-        __asm__ __volatile__(
-        "       .set    noreorder                                       \n"
-        "       .set    mips32r2                                        \n"
-        "       .word   0x41600be1                      # emt           \n"
-        "       ehb                                                     \n"
-        "       .set    mips0                                           \n"
-        "       .set    reorder");
-}
-
-/* enable multi-threaded execution if previous suggested it should be.
-   EMT_ENABLE to force */
-
-#define EMT_ENABLE VPECONTROL_TE
-
-static inline void emt(int previous)
-{
-        if ((previous & EMT_ENABLE))
-                __raw_emt();
-}
-
-static inline void ehb(void)
-{
-        __asm__ __volatile__(
-        "       .set    mips32r2                                \n"
-        "       ehb                                             \n"
-        "       .set    mips0                                   \n");
-}
-
-#define mftc0(rt,sel)                                                   \
-({                                                                      \
-         unsigned long  __res;                                          \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    mips32r2                                \n"     \
-        "       .set    noat                                    \n"     \
-        "       # mftc0 $1, $" #rt ", " #sel "                  \n"     \
-        "       .word   0x41000800 | (" #rt " << 16) | " #sel " \n"     \
-        "       move    %0, $1                                  \n"     \
-        "       .set    pop                                     \n"     \
-        : "=r" (__res));                                                \
-                                                                        \
-        __res;                                                          \
-})
-
-#define mftgpr(rt)                                                      \
-({                                                                      \
-        unsigned long __res;                                            \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       .set    mips32r2                                \n"     \
-        "       # mftgpr $1," #rt "                             \n"     \
-        "       .word   0x41000820 | (" #rt " << 16)            \n"     \
-        "       move    %0, $1                                  \n"     \
-        "       .set    pop                                     \n"     \
-        : "=r" (__res));                                                \
-                                                                        \
-        __res;                                                          \
-})
-
-#define mftr(rt, u, sel)                                                        \
-({                                                                      \
-        unsigned long __res;                                            \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       mftr    %0, " #rt ", " #u ", " #sel "           \n"     \
-        : "=r" (__res));                                                \
-                                                                        \
-        __res;                                                          \
-})
-
-#define mttgpr(rd,v)                                                    \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    mips32r2                                \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mttgpr $1, " #rd "                            \n"     \
-        "       .word   0x41810020 | (" #rd " << 11)            \n"     \
-        "       .set    pop                                     \n"     \
-        : : "r" (v));                                                   \
-} while (0)
-
-#define mttc0(rd, sel, v)                                                       \
-({                                                                      \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    mips32r2                                \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mttc0 %0," #rd ", " #sel "                    \n"     \
-        "       .word   0x41810000 | (" #rd " << 11) | " #sel " \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (v));                                                     \
-})
-
-
-#define mttr(rd, u, sel, v)                                             \
-({                                                                      \
-        __asm__ __volatile__(                                           \
-        "mttr   %0," #rd ", " #u ", " #sel                              \
-        : : "r" (v));                                                   \
-})
-
-
-#define settc(tc)                                                       \
-do {                                                                    \
-        write_c0_vpecontrol((read_c0_vpecontrol()&~VPECONTROL_TARGTC) | (tc)); \
-        ehb();                                                          \
-} while (0)
-
-
-/* you *must* set the target tc (settc) before trying to use these */
-#define read_vpe_c0_vpecontrol()        mftc0(1, 1)
-#define write_vpe_c0_vpecontrol(val)    mttc0(1, 1, val)
-#define read_vpe_c0_vpeconf0()          mftc0(1, 2)
-#define write_vpe_c0_vpeconf0(val)      mttc0(1, 2, val)
-#define read_vpe_c0_count()             mftc0(9, 0)
-#define write_vpe_c0_count(val)         mttc0(9, 0, val)
-#define read_vpe_c0_status()            mftc0(12, 0)
-#define write_vpe_c0_status(val)        mttc0(12, 0, val)
-#define read_vpe_c0_cause()             mftc0(13, 0)
-#define write_vpe_c0_cause(val)         mttc0(13, 0, val)
-#define read_vpe_c0_config()            mftc0(16, 0)
-#define write_vpe_c0_config(val)        mttc0(16, 0, val)
-#define read_vpe_c0_config1()           mftc0(16, 1)
-#define write_vpe_c0_config1(val)       mttc0(16, 1, val)
-#define read_vpe_c0_config7()           mftc0(16, 7)
-#define write_vpe_c0_config7(val)       mttc0(16, 7, val)
-#define read_vpe_c0_ebase()             mftc0(15, 1)
-#define write_vpe_c0_ebase(val)         mttc0(15, 1, val)
-#define write_vpe_c0_compare(val)       mttc0(11, 0, val)
-#define read_vpe_c0_badvaddr()          mftc0(8, 0)
-#define read_vpe_c0_epc()               mftc0(14, 0)
-#define write_vpe_c0_epc(val)           mttc0(14, 0, val)
-
-
-/* TC */
-#define read_tc_c0_tcstatus()           mftc0(2, 1)
-#define write_tc_c0_tcstatus(val)       mttc0(2, 1, val)
-#define read_tc_c0_tcbind()             mftc0(2, 2)
-#define write_tc_c0_tcbind(val)         mttc0(2, 2, val)
-#define read_tc_c0_tcrestart()          mftc0(2, 3)
-#define write_tc_c0_tcrestart(val)      mttc0(2, 3, val)
-#define read_tc_c0_tchalt()             mftc0(2, 4)
-#define write_tc_c0_tchalt(val)         mttc0(2, 4, val)
-#define read_tc_c0_tccontext()          mftc0(2, 5)
-#define write_tc_c0_tccontext(val)      mttc0(2, 5, val)
-
-/* GPR */
-#define read_tc_gpr_sp()                mftgpr(29)
-#define write_tc_gpr_sp(val)            mttgpr(29, val)
-#define read_tc_gpr_gp()                mftgpr(28)
-#define write_tc_gpr_gp(val)            mttgpr(28, val)
-
-__BUILD_SET_C0(mvpcontrol)
-
-#endif /* Not __ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-mips/mipsprom.h b/include/asm-mips/mipsprom.h
deleted file mode 100644
index 146d41b67adc..000000000000
--- a/include/asm-mips/mipsprom.h
+++ /dev/null
@@ -1,76 +0,0 @@
-#ifndef __ASM_MIPS_PROM_H
-#define __ASM_MIPS_PROM_H
-
-#define PROM_RESET              0
-#define PROM_EXEC               1
-#define PROM_RESTART            2
-#define PROM_REINIT             3
-#define PROM_REBOOT             4
-#define PROM_AUTOBOOT           5
-#define PROM_OPEN               6
-#define PROM_READ               7
-#define PROM_WRITE              8
-#define PROM_IOCTL              9
-#define PROM_CLOSE              10
-#define PROM_GETCHAR            11
-#define PROM_PUTCHAR            12
-#define PROM_SHOWCHAR           13      /* XXX */
-#define PROM_GETS               14      /* XXX */
-#define PROM_PUTS               15      /* XXX */
-#define PROM_PRINTF             16      /* XXX */
-
-/* What are these for? */
-#define PROM_INITPROTO          17      /* XXX */
-#define PROM_PROTOENABLE        18      /* XXX */
-#define PROM_PROTODISABLE       19      /* XXX */
-#define PROM_GETPKT             20      /* XXX */
-#define PROM_PUTPKT             21      /* XXX */
-
-/* More PROM shit.  Probably has to do with VME RMW cycles??? */
-#define PROM_ORW_RMW            22      /* XXX */
-#define PROM_ORH_RMW            23      /* XXX */
-#define PROM_ORB_RMW            24      /* XXX */
-#define PROM_ANDW_RMW           25      /* XXX */
-#define PROM_ANDH_RMW           26      /* XXX */
-#define PROM_ANDB_RMW           27      /* XXX */
-
-/* Cache handling stuff */
-#define PROM_FLUSHCACHE         28      /* XXX */
-#define PROM_CLEARCACHE         29      /* XXX */
-
-/* Libc alike stuff */
-#define PROM_SETJMP             30      /* XXX */
-#define PROM_LONGJMP            31      /* XXX */
-#define PROM_BEVUTLB            32      /* XXX */
-#define PROM_GETENV             33      /* XXX */
-#define PROM_SETENV             34      /* XXX */
-#define PROM_ATOB               35      /* XXX */
-#define PROM_STRCMP             36      /* XXX */
-#define PROM_STRLEN             37      /* XXX */
-#define PROM_STRCPY             38      /* XXX */
-#define PROM_STRCAT             39      /* XXX */
-
-/* Misc stuff */
-#define PROM_PARSER             40      /* XXX */
-#define PROM_RANGE              41      /* XXX */
-#define PROM_ARGVIZE            42      /* XXX */
-#define PROM_HELP               43      /* XXX */
-
-/* Entry points for some PROM commands */
-#define PROM_DUMPCMD            44      /* XXX */
-#define PROM_SETENVCMD          45      /* XXX */
-#define PROM_UNSETENVCMD        46      /* XXX */
-#define PROM_PRINTENVCMD        47      /* XXX */
-#define PROM_BEVEXCEPT          48      /* XXX */
-#define PROM_ENABLECMD          49      /* XXX */
-#define PROM_DISABLECMD         50      /* XXX */
-
-#define PROM_CLEARNOFAULT       51      /* XXX */
-#define PROM_NOTIMPLEMENT       52      /* XXX */
-
-#define PROM_NV_GET             53      /* XXX */
-#define PROM_NV_SET             54      /* XXX */
-
-extern char *prom_getenv(char *);
-
-#endif /* __ASM_MIPS_PROM_H */
diff --git a/include/asm-mips/mipsregs.h b/include/asm-mips/mipsregs.h
deleted file mode 100644
index a46f8e258e6b..000000000000
--- a/include/asm-mips/mipsregs.h
+++ /dev/null
@@ -1,1526 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1997, 2000, 2001 by Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- * Modified for further R[236]000 support by Paul M. Antoine, 1996.
- * Kevin D. Kissell, kevink@mips.com and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000, 07 MIPS Technologies, Inc.
- * Copyright (C) 2003, 2004  Maciej W. Rozycki
- */
-#ifndef _ASM_MIPSREGS_H
-#define _ASM_MIPSREGS_H
-
-#include <linux/linkage.h>
-#include <asm/hazards.h>
-#include <asm/war.h>
-
-/*
- * The following macros are especially useful for __asm__
- * inline assembler.
- */
-#ifndef __STR
-#define __STR(x) #x
-#endif
-#ifndef STR
-#define STR(x) __STR(x)
-#endif
-
-/*
- *  Configure language
- */
-#ifdef __ASSEMBLY__
-#define _ULCAST_
-#else
-#define _ULCAST_ (unsigned long)
-#endif
-
-/*
- * Coprocessor 0 register names
- */
-#define CP0_INDEX $0
-#define CP0_RANDOM $1
-#define CP0_ENTRYLO0 $2
-#define CP0_ENTRYLO1 $3
-#define CP0_CONF $3
-#define CP0_CONTEXT $4
-#define CP0_PAGEMASK $5
-#define CP0_WIRED $6
-#define CP0_INFO $7
-#define CP0_BADVADDR $8
-#define CP0_COUNT $9
-#define CP0_ENTRYHI $10
-#define CP0_COMPARE $11
-#define CP0_STATUS $12
-#define CP0_CAUSE $13
-#define CP0_EPC $14
-#define CP0_PRID $15
-#define CP0_CONFIG $16
-#define CP0_LLADDR $17
-#define CP0_WATCHLO $18
-#define CP0_WATCHHI $19
-#define CP0_XCONTEXT $20
-#define CP0_FRAMEMASK $21
-#define CP0_DIAGNOSTIC $22
-#define CP0_DEBUG $23
-#define CP0_DEPC $24
-#define CP0_PERFORMANCE $25
-#define CP0_ECC $26
-#define CP0_CACHEERR $27
-#define CP0_TAGLO $28
-#define CP0_TAGHI $29
-#define CP0_ERROREPC $30
-#define CP0_DESAVE $31
-
-/*
- * R4640/R4650 cp0 register names.  These registers are listed
- * here only for completeness; without MMU these CPUs are not useable
- * by Linux.  A future ELKS port might take make Linux run on them
- * though ...
- */
-#define CP0_IBASE $0
-#define CP0_IBOUND $1
-#define CP0_DBASE $2
-#define CP0_DBOUND $3
-#define CP0_CALG $17
-#define CP0_IWATCH $18
-#define CP0_DWATCH $19
-
-/*
- * Coprocessor 0 Set 1 register names
- */
-#define CP0_S1_DERRADDR0  $26
-#define CP0_S1_DERRADDR1  $27
-#define CP0_S1_INTCONTROL $20
-
-/*
- * Coprocessor 0 Set 2 register names
- */
-#define CP0_S2_SRSCTL     $12   /* MIPSR2 */
-
-/*
- * Coprocessor 0 Set 3 register names
- */
-#define CP0_S3_SRSMAP     $12   /* MIPSR2 */
-
-/*
- *  TX39 Series
- */
-#define CP0_TX39_CACHE  $7
-
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION   $0
-#define CP1_STATUS     $31
-
-/*
- * FPU Status Register Values
- */
-/*
- * Status Register Values
- */
-
-#define FPU_CSR_FLUSH   0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND    0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1   0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2   0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3   0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4   0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5   0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6   0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7   0x80000000      /* $fcc7 */
-
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X   0x0003f000
-#define FPU_CSR_UNI_X   0x00020000
-#define FPU_CSR_INV_X   0x00010000
-#define FPU_CSR_DIV_X   0x00008000
-#define FPU_CSR_OVF_X   0x00004000
-#define FPU_CSR_UDF_X   0x00002000
-#define FPU_CSR_INE_X   0x00001000
-
-#define FPU_CSR_ALL_E   0x00000f80
-#define FPU_CSR_INV_E   0x00000800
-#define FPU_CSR_DIV_E   0x00000400
-#define FPU_CSR_OVF_E   0x00000200
-#define FPU_CSR_UDF_E   0x00000100
-#define FPU_CSR_INE_E   0x00000080
-
-#define FPU_CSR_ALL_S   0x0000007c
-#define FPU_CSR_INV_S   0x00000040
-#define FPU_CSR_DIV_S   0x00000020
-#define FPU_CSR_OVF_S   0x00000010
-#define FPU_CSR_UDF_S   0x00000008
-#define FPU_CSR_INE_S   0x00000004
-
-/* rounding mode */
-#define FPU_CSR_RN      0x0     /* nearest */
-#define FPU_CSR_RZ      0x1     /* towards zero */
-#define FPU_CSR_RU      0x2     /* towards +Infinity */
-#define FPU_CSR_RD      0x3     /* towards -Infinity */
-
-
-/*
- * Values for PageMask register
- */
-#ifdef CONFIG_CPU_VR41XX
-
-/* Why doesn't stupidity hurt ... */
-
-#define PM_1K           0x00000000
-#define PM_4K           0x00001800
-#define PM_16K          0x00007800
-#define PM_64K          0x0001f800
-#define PM_256K         0x0007f800
-
-#else
-
-#define PM_4K           0x00000000
-#define PM_16K          0x00006000
-#define PM_64K          0x0001e000
-#define PM_256K         0x0007e000
-#define PM_1M           0x001fe000
-#define PM_4M           0x007fe000
-#define PM_16M          0x01ffe000
-#define PM_64M          0x07ffe000
-#define PM_256M         0x1fffe000
-
-#endif
-
-/*
- * Default page size for a given kernel configuration
- */
-#ifdef CONFIG_PAGE_SIZE_4KB
-#define PM_DEFAULT_MASK PM_4K
-#elif defined(CONFIG_PAGE_SIZE_16KB)
-#define PM_DEFAULT_MASK PM_16K
-#elif defined(CONFIG_PAGE_SIZE_64KB)
-#define PM_DEFAULT_MASK PM_64K
-#else
-#error Bad page size configuration!
-#endif
-
-
-/*
- * Values used for computation of new tlb entries
- */
-#define PL_4K           12
-#define PL_16K          14
-#define PL_64K          16
-#define PL_256K         18
-#define PL_1M           20
-#define PL_4M           22
-#define PL_16M          24
-#define PL_64M          26
-#define PL_256M         28
-
-/*
- * R4x00 interrupt enable / cause bits
- */
-#define IE_SW0          (_ULCAST_(1) <<  8)
-#define IE_SW1          (_ULCAST_(1) <<  9)
-#define IE_IRQ0         (_ULCAST_(1) << 10)
-#define IE_IRQ1         (_ULCAST_(1) << 11)
-#define IE_IRQ2         (_ULCAST_(1) << 12)
-#define IE_IRQ3         (_ULCAST_(1) << 13)
-#define IE_IRQ4         (_ULCAST_(1) << 14)
-#define IE_IRQ5         (_ULCAST_(1) << 15)
-
-/*
- * R4x00 interrupt cause bits
- */
-#define C_SW0           (_ULCAST_(1) <<  8)
-#define C_SW1           (_ULCAST_(1) <<  9)
-#define C_IRQ0          (_ULCAST_(1) << 10)
-#define C_IRQ1          (_ULCAST_(1) << 11)
-#define C_IRQ2          (_ULCAST_(1) << 12)
-#define C_IRQ3          (_ULCAST_(1) << 13)
-#define C_IRQ4          (_ULCAST_(1) << 14)
-#define C_IRQ5          (_ULCAST_(1) << 15)
-
-/*
- * Bitfields in the R4xx0 cp0 status register
- */
-#define ST0_IE                  0x00000001
-#define ST0_EXL                 0x00000002
-#define ST0_ERL                 0x00000004
-#define ST0_KSU                 0x00000018
-#  define KSU_USER              0x00000010
-#  define KSU_SUPERVISOR        0x00000008
-#  define KSU_KERNEL            0x00000000
-#define ST0_UX                  0x00000020
-#define ST0_SX                  0x00000040
-#define ST0_KX                  0x00000080
-#define ST0_DE                  0x00010000
-#define ST0_CE                  0x00020000
-
-/*
- * Setting c0_status.co enables Hit_Writeback and Hit_Writeback_Invalidate
- * cacheops in userspace.  This bit exists only on RM7000 and RM9000
- * processors.
- */
-#define ST0_CO                  0x08000000
-
-/*
- * Bitfields in the R[23]000 cp0 status register.
- */
-#define ST0_IEC                 0x00000001
-#define ST0_KUC                 0x00000002
-#define ST0_IEP                 0x00000004
-#define ST0_KUP                 0x00000008
-#define ST0_IEO                 0x00000010
-#define ST0_KUO                 0x00000020
-/* bits 6 & 7 are reserved on R[23]000 */
-#define ST0_ISC                 0x00010000
-#define ST0_SWC                 0x00020000
-#define ST0_CM                  0x00080000
-
-/*
- * Bits specific to the R4640/R4650
- */
-#define ST0_UM                  (_ULCAST_(1) <<  4)
-#define ST0_IL                  (_ULCAST_(1) << 23)
-#define ST0_DL                  (_ULCAST_(1) << 24)
-
-/*
- * Enable the MIPS MDMX and DSP ASEs
- */
-#define ST0_MX                  0x01000000
-
-/*
- * Bitfields in the TX39 family CP0 Configuration Register 3
- */
-#define TX39_CONF_ICS_SHIFT     19
-#define TX39_CONF_ICS_MASK      0x00380000
-#define TX39_CONF_ICS_1KB       0x00000000
-#define TX39_CONF_ICS_2KB       0x00080000
-#define TX39_CONF_ICS_4KB       0x00100000
-#define TX39_CONF_ICS_8KB       0x00180000
-#define TX39_CONF_ICS_16KB      0x00200000
-
-#define TX39_CONF_DCS_SHIFT     16
-#define TX39_CONF_DCS_MASK      0x00070000
-#define TX39_CONF_DCS_1KB       0x00000000
-#define TX39_CONF_DCS_2KB       0x00010000
-#define TX39_CONF_DCS_4KB       0x00020000
-#define TX39_CONF_DCS_8KB       0x00030000
-#define TX39_CONF_DCS_16KB      0x00040000
-
-#define TX39_CONF_CWFON         0x00004000
-#define TX39_CONF_WBON          0x00002000
-#define TX39_CONF_RF_SHIFT      10
-#define TX39_CONF_RF_MASK       0x00000c00
-#define TX39_CONF_DOZE          0x00000200
-#define TX39_CONF_HALT          0x00000100
-#define TX39_CONF_LOCK          0x00000080
-#define TX39_CONF_ICE           0x00000020
-#define TX39_CONF_DCE           0x00000010
-#define TX39_CONF_IRSIZE_SHIFT  2
-#define TX39_CONF_IRSIZE_MASK   0x0000000c
-#define TX39_CONF_DRSIZE_SHIFT  0
-#define TX39_CONF_DRSIZE_MASK   0x00000003
-
-/*
- * Status register bits available in all MIPS CPUs.
- */
-#define ST0_IM                  0x0000ff00
-#define  STATUSB_IP0            8
-#define  STATUSF_IP0            (_ULCAST_(1) <<  8)
-#define  STATUSB_IP1            9
-#define  STATUSF_IP1            (_ULCAST_(1) <<  9)
-#define  STATUSB_IP2            10
-#define  STATUSF_IP2            (_ULCAST_(1) << 10)
-#define  STATUSB_IP3            11
-#define  STATUSF_IP3            (_ULCAST_(1) << 11)
-#define  STATUSB_IP4            12
-#define  STATUSF_IP4            (_ULCAST_(1) << 12)
-#define  STATUSB_IP5            13
-#define  STATUSF_IP5            (_ULCAST_(1) << 13)
-#define  STATUSB_IP6            14
-#define  STATUSF_IP6            (_ULCAST_(1) << 14)
-#define  STATUSB_IP7            15
-#define  STATUSF_IP7            (_ULCAST_(1) << 15)
-#define  STATUSB_IP8            0
-#define  STATUSF_IP8            (_ULCAST_(1) <<  0)
-#define  STATUSB_IP9            1
-#define  STATUSF_IP9            (_ULCAST_(1) <<  1)
-#define  STATUSB_IP10           2
-#define  STATUSF_IP10           (_ULCAST_(1) <<  2)
-#define  STATUSB_IP11           3
-#define  STATUSF_IP11           (_ULCAST_(1) <<  3)
-#define  STATUSB_IP12           4
-#define  STATUSF_IP12           (_ULCAST_(1) <<  4)
-#define  STATUSB_IP13           5
-#define  STATUSF_IP13           (_ULCAST_(1) <<  5)
-#define  STATUSB_IP14           6
-#define  STATUSF_IP14           (_ULCAST_(1) <<  6)
-#define  STATUSB_IP15           7
-#define  STATUSF_IP15           (_ULCAST_(1) <<  7)
-#define ST0_CH                  0x00040000
-#define ST0_SR                  0x00100000
-#define ST0_TS                  0x00200000
-#define ST0_BEV                 0x00400000
-#define ST0_RE                  0x02000000
-#define ST0_FR                  0x04000000
-#define ST0_CU                  0xf0000000
-#define ST0_CU0                 0x10000000
-#define ST0_CU1                 0x20000000
-#define ST0_CU2                 0x40000000
-#define ST0_CU3                 0x80000000
-#define ST0_XX                  0x80000000      /* MIPS IV naming */
-
-/*
- * Bitfields and bit numbers in the coprocessor 0 cause register.
- *
- * Refer to your MIPS R4xx0 manual, chapter 5 for explanation.
- */
-#define  CAUSEB_EXCCODE         2
-#define  CAUSEF_EXCCODE         (_ULCAST_(31)  <<  2)
-#define  CAUSEB_IP              8
-#define  CAUSEF_IP              (_ULCAST_(255) <<  8)
-#define  CAUSEB_IP0             8
-#define  CAUSEF_IP0             (_ULCAST_(1)   <<  8)
-#define  CAUSEB_IP1             9
-#define  CAUSEF_IP1             (_ULCAST_(1)   <<  9)
-#define  CAUSEB_IP2             10
-#define  CAUSEF_IP2             (_ULCAST_(1)   << 10)
-#define  CAUSEB_IP3             11
-#define  CAUSEF_IP3             (_ULCAST_(1)   << 11)
-#define  CAUSEB_IP4             12
-#define  CAUSEF_IP4             (_ULCAST_(1)   << 12)
-#define  CAUSEB_IP5             13
-#define  CAUSEF_IP5             (_ULCAST_(1)   << 13)
-#define  CAUSEB_IP6             14
-#define  CAUSEF_IP6             (_ULCAST_(1)   << 14)
-#define  CAUSEB_IP7             15
-#define  CAUSEF_IP7             (_ULCAST_(1)   << 15)
-#define  CAUSEB_IV              23
-#define  CAUSEF_IV              (_ULCAST_(1)   << 23)
-#define  CAUSEB_CE              28
-#define  CAUSEF_CE              (_ULCAST_(3)   << 28)
-#define  CAUSEB_BD              31
-#define  CAUSEF_BD              (_ULCAST_(1)   << 31)
-
-/*
- * Bits in the coprocessor 0 config register.
- */
-/* Generic bits.  */
-#define CONF_CM_CACHABLE_NO_WA          0
-#define CONF_CM_CACHABLE_WA             1
-#define CONF_CM_UNCACHED                2
-#define CONF_CM_CACHABLE_NONCOHERENT    3
-#define CONF_CM_CACHABLE_CE             4
-#define CONF_CM_CACHABLE_COW            5
-#define CONF_CM_CACHABLE_CUW            6
-#define CONF_CM_CACHABLE_ACCELERATED    7
-#define CONF_CM_CMASK                   7
-#define CONF_BE                 (_ULCAST_(1) << 15)
-
-/* Bits common to various processors.  */
-#define CONF_CU                 (_ULCAST_(1) <<  3)
-#define CONF_DB                 (_ULCAST_(1) <<  4)
-#define CONF_IB                 (_ULCAST_(1) <<  5)
-#define CONF_DC                 (_ULCAST_(7) <<  6)
-#define CONF_IC                 (_ULCAST_(7) <<  9)
-#define CONF_EB                 (_ULCAST_(1) << 13)
-#define CONF_EM                 (_ULCAST_(1) << 14)
-#define CONF_SM                 (_ULCAST_(1) << 16)
-#define CONF_SC                 (_ULCAST_(1) << 17)
-#define CONF_EW                 (_ULCAST_(3) << 18)
-#define CONF_EP                 (_ULCAST_(15)<< 24)
-#define CONF_EC                 (_ULCAST_(7) << 28)
-#define CONF_CM                 (_ULCAST_(1) << 31)
-
-/* Bits specific to the R4xx0.  */
-#define R4K_CONF_SW             (_ULCAST_(1) << 20)
-#define R4K_CONF_SS             (_ULCAST_(1) << 21)
-#define R4K_CONF_SB             (_ULCAST_(3) << 22)
-
-/* Bits specific to the R5000.  */
-#define R5K_CONF_SE             (_ULCAST_(1) << 12)
-#define R5K_CONF_SS             (_ULCAST_(3) << 20)
-
-/* Bits specific to the RM7000.  */
-#define RM7K_CONF_SE            (_ULCAST_(1) <<  3)
-#define RM7K_CONF_TE            (_ULCAST_(1) << 12)
-#define RM7K_CONF_CLK           (_ULCAST_(1) << 16)
-#define RM7K_CONF_TC            (_ULCAST_(1) << 17)
-#define RM7K_CONF_SI            (_ULCAST_(3) << 20)
-#define RM7K_CONF_SC            (_ULCAST_(1) << 31)
-
-/* Bits specific to the R10000.  */
-#define R10K_CONF_DN            (_ULCAST_(3) <<  3)
-#define R10K_CONF_CT            (_ULCAST_(1) <<  5)
-#define R10K_CONF_PE            (_ULCAST_(1) <<  6)
-#define R10K_CONF_PM            (_ULCAST_(3) <<  7)
-#define R10K_CONF_EC            (_ULCAST_(15)<<  9)
-#define R10K_CONF_SB            (_ULCAST_(1) << 13)
-#define R10K_CONF_SK            (_ULCAST_(1) << 14)
-#define R10K_CONF_SS            (_ULCAST_(7) << 16)
-#define R10K_CONF_SC            (_ULCAST_(7) << 19)
-#define R10K_CONF_DC            (_ULCAST_(7) << 26)
-#define R10K_CONF_IC            (_ULCAST_(7) << 29)
-
-/* Bits specific to the VR41xx.  */
-#define VR41_CONF_CS            (_ULCAST_(1) << 12)
-#define VR41_CONF_P4K           (_ULCAST_(1) << 13)
-#define VR41_CONF_BP            (_ULCAST_(1) << 16)
-#define VR41_CONF_M16           (_ULCAST_(1) << 20)
-#define VR41_CONF_AD            (_ULCAST_(1) << 23)
-
-/* Bits specific to the R30xx.  */
-#define R30XX_CONF_FDM          (_ULCAST_(1) << 19)
-#define R30XX_CONF_REV          (_ULCAST_(1) << 22)
-#define R30XX_CONF_AC           (_ULCAST_(1) << 23)
-#define R30XX_CONF_RF           (_ULCAST_(1) << 24)
-#define R30XX_CONF_HALT         (_ULCAST_(1) << 25)
-#define R30XX_CONF_FPINT        (_ULCAST_(7) << 26)
-#define R30XX_CONF_DBR          (_ULCAST_(1) << 29)
-#define R30XX_CONF_SB           (_ULCAST_(1) << 30)
-#define R30XX_CONF_LOCK         (_ULCAST_(1) << 31)
-
-/* Bits specific to the TX49.  */
-#define TX49_CONF_DC            (_ULCAST_(1) << 16)
-#define TX49_CONF_IC            (_ULCAST_(1) << 17)  /* conflict with CONF_SC */
-#define TX49_CONF_HALT          (_ULCAST_(1) << 18)
-#define TX49_CONF_CWFON         (_ULCAST_(1) << 27)
-
-/* Bits specific to the MIPS32/64 PRA.  */
-#define MIPS_CONF_MT            (_ULCAST_(7) <<  7)
-#define MIPS_CONF_AR            (_ULCAST_(7) << 10)
-#define MIPS_CONF_AT            (_ULCAST_(3) << 13)
-#define MIPS_CONF_M             (_ULCAST_(1) << 31)
-
-/*
- * Bits in the MIPS32/64 PRA coprocessor 0 config registers 1 and above.
- */
-#define MIPS_CONF1_FP           (_ULCAST_(1) <<  0)
-#define MIPS_CONF1_EP           (_ULCAST_(1) <<  1)
-#define MIPS_CONF1_CA           (_ULCAST_(1) <<  2)
-#define MIPS_CONF1_WR           (_ULCAST_(1) <<  3)
-#define MIPS_CONF1_PC           (_ULCAST_(1) <<  4)
-#define MIPS_CONF1_MD           (_ULCAST_(1) <<  5)
-#define MIPS_CONF1_C2           (_ULCAST_(1) <<  6)
-#define MIPS_CONF1_DA           (_ULCAST_(7) <<  7)
-#define MIPS_CONF1_DL           (_ULCAST_(7) << 10)
-#define MIPS_CONF1_DS           (_ULCAST_(7) << 13)
-#define MIPS_CONF1_IA           (_ULCAST_(7) << 16)
-#define MIPS_CONF1_IL           (_ULCAST_(7) << 19)
-#define MIPS_CONF1_IS           (_ULCAST_(7) << 22)
-#define MIPS_CONF1_TLBS         (_ULCAST_(63)<< 25)
-
-#define MIPS_CONF2_SA           (_ULCAST_(15)<<  0)
-#define MIPS_CONF2_SL           (_ULCAST_(15)<<  4)
-#define MIPS_CONF2_SS           (_ULCAST_(15)<<  8)
-#define MIPS_CONF2_SU           (_ULCAST_(15)<< 12)
-#define MIPS_CONF2_TA           (_ULCAST_(15)<< 16)
-#define MIPS_CONF2_TL           (_ULCAST_(15)<< 20)
-#define MIPS_CONF2_TS           (_ULCAST_(15)<< 24)
-#define MIPS_CONF2_TU           (_ULCAST_(7) << 28)
-
-#define MIPS_CONF3_TL           (_ULCAST_(1) <<  0)
-#define MIPS_CONF3_SM           (_ULCAST_(1) <<  1)
-#define MIPS_CONF3_MT           (_ULCAST_(1) <<  2)
-#define MIPS_CONF3_SP           (_ULCAST_(1) <<  4)
-#define MIPS_CONF3_VINT         (_ULCAST_(1) <<  5)
-#define MIPS_CONF3_VEIC         (_ULCAST_(1) <<  6)
-#define MIPS_CONF3_LPA          (_ULCAST_(1) <<  7)
-#define MIPS_CONF3_DSP          (_ULCAST_(1) << 10)
-#define MIPS_CONF3_ULRI         (_ULCAST_(1) << 13)
-
-#define MIPS_CONF7_WII          (_ULCAST_(1) << 31)
-
-#define MIPS_CONF7_RPS          (_ULCAST_(1) << 2)
-
-
-/*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S             (_ULCAST_(1) << 16)
-#define MIPS_FPIR_D             (_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS            (_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D            (_ULCAST_(1) << 19)
-#define MIPS_FPIR_W             (_ULCAST_(1) << 20)
-#define MIPS_FPIR_L             (_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64           (_ULCAST_(1) << 22)
-
-#ifndef __ASSEMBLY__
-
-/*
- * Functions to access the R10000 performance counters.  These are basically
- * mfc0 and mtc0 instructions from and to coprocessor register with a 5-bit
- * performance counter number encoded into bits 1 ... 5 of the instruction.
- * Only performance counters 0 to 1 actually exist, so for a non-R10000 aware
- * disassembler these will look like an access to sel 0 or 1.
- */
-#define read_r10k_perf_cntr(counter)                            \
-({                                                              \
-        unsigned int __res;                                     \
-        __asm__ __volatile__(                                   \
-        "mfpc\t%0, %1"                                          \
-        : "=r" (__res)                                          \
-        : "i" (counter));                                       \
-                                                                \
-        __res;                                                  \
-})
-
-#define write_r10k_perf_cntr(counter,val)                       \
-do {                                                            \
-        __asm__ __volatile__(                                   \
-        "mtpc\t%0, %1"                                          \
-        :                                                       \
-        : "r" (val), "i" (counter));                            \
-} while (0)
-
-#define read_r10k_perf_event(counter)                           \
-({                                                              \
-        unsigned int __res;                                     \
-        __asm__ __volatile__(                                   \
-        "mfps\t%0, %1"                                          \
-        : "=r" (__res)                                          \
-        : "i" (counter));                                       \
-                                                                \
-        __res;                                                  \
-})
-
-#define write_r10k_perf_cntl(counter,val)                       \
-do {                                                            \
-        __asm__ __volatile__(                                   \
-        "mtps\t%0, %1"                                          \
-        :                                                       \
-        : "r" (val), "i" (counter));                            \
-} while (0)
-
-
-/*
- * Macros to access the system control coprocessor
- */
-
-#define __read_32bit_c0_register(source, sel)                           \
-({ int __res;                                                           \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        "mfc0\t%0, " #source "\n\t"                     \
-                        : "=r" (__res));                                \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips32\n\t"                              \
-                        "mfc0\t%0, " #source ", " #sel "\n\t"           \
-                        ".set\tmips0\n\t"                               \
-                        : "=r" (__res));                                \
-        __res;                                                          \
-})
-
-#define __read_64bit_c0_register(source, sel)                           \
-({ unsigned long long __res;                                            \
-        if (sizeof(unsigned long) == 4)                                 \
-                __res = __read_64bit_c0_split(source, sel);             \
-        else if (sel == 0)                                              \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips3\n\t"                               \
-                        "dmfc0\t%0, " #source "\n\t"                    \
-                        ".set\tmips0"                                   \
-                        : "=r" (__res));                                \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc0\t%0, " #source ", " #sel "\n\t"          \
-                        ".set\tmips0"                                   \
-                        : "=r" (__res));                                \
-        __res;                                                          \
-})
-
-#define __write_32bit_c0_register(register, sel, value)                 \
-do {                                                                    \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        "mtc0\t%z0, " #register "\n\t"                  \
-                        : : "Jr" ((unsigned int)(value)));              \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips32\n\t"                              \
-                        "mtc0\t%z0, " #register ", " #sel "\n\t"        \
-                        ".set\tmips0"                                   \
-                        : : "Jr" ((unsigned int)(value)));              \
-} while (0)
-
-#define __write_64bit_c0_register(register, sel, value)                 \
-do {                                                                    \
-        if (sizeof(unsigned long) == 4)                                 \
-                __write_64bit_c0_split(register, sel, value);           \
-        else if (sel == 0)                                              \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips3\n\t"                               \
-                        "dmtc0\t%z0, " #register "\n\t"                 \
-                        ".set\tmips0"                                   \
-                        : : "Jr" (value));                              \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmtc0\t%z0, " #register ", " #sel "\n\t"       \
-                        ".set\tmips0"                                   \
-                        : : "Jr" (value));                              \
-} while (0)
-
-#define __read_ulong_c0_register(reg, sel)                              \
-        ((sizeof(unsigned long) == 4) ?                                 \
-        (unsigned long) __read_32bit_c0_register(reg, sel) :            \
-        (unsigned long) __read_64bit_c0_register(reg, sel))
-
-#define __write_ulong_c0_register(reg, sel, val)                        \
-do {                                                                    \
-        if (sizeof(unsigned long) == 4)                                 \
-                __write_32bit_c0_register(reg, sel, val);               \
-        else                                                            \
-                __write_64bit_c0_register(reg, sel, val);               \
-} while (0)
-
-/*
- * On RM7000/RM9000 these are uses to access cop0 set 1 registers
- */
-#define __read_32bit_c0_ctrl_register(source)                           \
-({ int __res;                                                           \
-        __asm__ __volatile__(                                           \
-                "cfc0\t%0, " #source "\n\t"                             \
-                : "=r" (__res));                                        \
-        __res;                                                          \
-})
-
-#define __write_32bit_c0_ctrl_register(register, value)                 \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-                "ctc0\t%z0, " #register "\n\t"                          \
-                : : "Jr" ((unsigned int)(value)));                      \
-} while (0)
-
-/*
- * These versions are only needed for systems with more than 38 bits of
- * physical address space running the 32-bit kernel.  That's none atm :-)
- */
-#define __read_64bit_c0_split(source, sel)                              \
-({                                                                      \
-        unsigned long long __val;                                       \
-        unsigned long __flags;                                          \
-                                                                        \
-        local_irq_save(__flags);                                        \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc0\t%M0, " #source "\n\t"                   \
-                        "dsll\t%L0, %M0, 32\n\t"                        \
-                        "dsrl\t%M0, %M0, 32\n\t"                        \
-                        "dsrl\t%L0, %L0, 32\n\t"                        \
-                        ".set\tmips0"                                   \
-                        : "=r" (__val));                                \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dmfc0\t%M0, " #source ", " #sel "\n\t"         \
-                        "dsll\t%L0, %M0, 32\n\t"                        \
-                        "dsrl\t%M0, %M0, 32\n\t"                        \
-                        "dsrl\t%L0, %L0, 32\n\t"                        \
-                        ".set\tmips0"                                   \
-                        : "=r" (__val));                                \
-        local_irq_restore(__flags);                                     \
-                                                                        \
-        __val;                                                          \
-})
-
-#define __write_64bit_c0_split(source, sel, val)                        \
-do {                                                                    \
-        unsigned long __flags;                                          \
-                                                                        \
-        local_irq_save(__flags);                                        \
-        if (sel == 0)                                                   \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dsll\t%L0, %L0, 32\n\t"                        \
-                        "dsrl\t%L0, %L0, 32\n\t"                        \
-                        "dsll\t%M0, %M0, 32\n\t"                        \
-                        "or\t%L0, %L0, %M0\n\t"                         \
-                        "dmtc0\t%L0, " #source "\n\t"                   \
-                        ".set\tmips0"                                   \
-                        : : "r" (val));                                 \
-        else                                                            \
-                __asm__ __volatile__(                                   \
-                        ".set\tmips64\n\t"                              \
-                        "dsll\t%L0, %L0, 32\n\t"                        \
-                        "dsrl\t%L0, %L0, 32\n\t"                        \
-                        "dsll\t%M0, %M0, 32\n\t"                        \
-                        "or\t%L0, %L0, %M0\n\t"                         \
-                        "dmtc0\t%L0, " #source ", " #sel "\n\t"         \
-                        ".set\tmips0"                                   \
-                        : : "r" (val));                                 \
-        local_irq_restore(__flags);                                     \
-} while (0)
-
-#define read_c0_index()         __read_32bit_c0_register($0, 0)
-#define write_c0_index(val)     __write_32bit_c0_register($0, 0, val)
-
-#define read_c0_random()        __read_32bit_c0_register($1, 0)
-#define write_c0_random(val)    __write_32bit_c0_register($1, 0, val)
-
-#define read_c0_entrylo0()      __read_ulong_c0_register($2, 0)
-#define write_c0_entrylo0(val)  __write_ulong_c0_register($2, 0, val)
-
-#define read_c0_entrylo1()      __read_ulong_c0_register($3, 0)
-#define write_c0_entrylo1(val)  __write_ulong_c0_register($3, 0, val)
-
-#define read_c0_conf()          __read_32bit_c0_register($3, 0)
-#define write_c0_conf(val)      __write_32bit_c0_register($3, 0, val)
-
-#define read_c0_context()       __read_ulong_c0_register($4, 0)
-#define write_c0_context(val)   __write_ulong_c0_register($4, 0, val)
-
-#define read_c0_userlocal()     __read_ulong_c0_register($4, 2)
-#define write_c0_userlocal(val) __write_ulong_c0_register($4, 2, val)
-
-#define read_c0_pagemask()      __read_32bit_c0_register($5, 0)
-#define write_c0_pagemask(val)  __write_32bit_c0_register($5, 0, val)
-
-#define read_c0_wired()         __read_32bit_c0_register($6, 0)
-#define write_c0_wired(val)     __write_32bit_c0_register($6, 0, val)
-
-#define read_c0_info()          __read_32bit_c0_register($7, 0)
-
-#define read_c0_cache()         __read_32bit_c0_register($7, 0) /* TX39xx */
-#define write_c0_cache(val)     __write_32bit_c0_register($7, 0, val)
-
-#define read_c0_badvaddr()      __read_ulong_c0_register($8, 0)
-#define write_c0_badvaddr(val)  __write_ulong_c0_register($8, 0, val)
-
-#define read_c0_count()         __read_32bit_c0_register($9, 0)
-#define write_c0_count(val)     __write_32bit_c0_register($9, 0, val)
-
-#define read_c0_count2()        __read_32bit_c0_register($9, 6) /* pnx8550 */
-#define write_c0_count2(val)    __write_32bit_c0_register($9, 6, val)
-
-#define read_c0_count3()        __read_32bit_c0_register($9, 7) /* pnx8550 */
-#define write_c0_count3(val)    __write_32bit_c0_register($9, 7, val)
-
-#define read_c0_entryhi()       __read_ulong_c0_register($10, 0)
-#define write_c0_entryhi(val)   __write_ulong_c0_register($10, 0, val)
-
-#define read_c0_compare()       __read_32bit_c0_register($11, 0)
-#define write_c0_compare(val)   __write_32bit_c0_register($11, 0, val)
-
-#define read_c0_compare2()      __read_32bit_c0_register($11, 6) /* pnx8550 */
-#define write_c0_compare2(val)  __write_32bit_c0_register($11, 6, val)
-
-#define read_c0_compare3()      __read_32bit_c0_register($11, 7) /* pnx8550 */
-#define write_c0_compare3(val)  __write_32bit_c0_register($11, 7, val)
-
-#define read_c0_status()        __read_32bit_c0_register($12, 0)
-#ifdef CONFIG_MIPS_MT_SMTC
-#define write_c0_status(val)                                            \
-do {                                                                    \
-        __write_32bit_c0_register($12, 0, val);                         \
-        __ehb();                                                        \
-} while (0)
-#else
-/*
- * Legacy non-SMTC code, which may be hazardous
- * but which might not support EHB
- */
-#define write_c0_status(val)    __write_32bit_c0_register($12, 0, val)
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-#define read_c0_cause()         __read_32bit_c0_register($13, 0)
-#define write_c0_cause(val)     __write_32bit_c0_register($13, 0, val)
-
-#define read_c0_epc()           __read_ulong_c0_register($14, 0)
-#define write_c0_epc(val)       __write_ulong_c0_register($14, 0, val)
-
-#define read_c0_prid()          __read_32bit_c0_register($15, 0)
-
-#define read_c0_config()        __read_32bit_c0_register($16, 0)
-#define read_c0_config1()       __read_32bit_c0_register($16, 1)
-#define read_c0_config2()       __read_32bit_c0_register($16, 2)
-#define read_c0_config3()       __read_32bit_c0_register($16, 3)
-#define read_c0_config4()       __read_32bit_c0_register($16, 4)
-#define read_c0_config5()       __read_32bit_c0_register($16, 5)
-#define read_c0_config6()       __read_32bit_c0_register($16, 6)
-#define read_c0_config7()       __read_32bit_c0_register($16, 7)
-#define write_c0_config(val)    __write_32bit_c0_register($16, 0, val)
-#define write_c0_config1(val)   __write_32bit_c0_register($16, 1, val)
-#define write_c0_config2(val)   __write_32bit_c0_register($16, 2, val)
-#define write_c0_config3(val)   __write_32bit_c0_register($16, 3, val)
-#define write_c0_config4(val)   __write_32bit_c0_register($16, 4, val)
-#define write_c0_config5(val)   __write_32bit_c0_register($16, 5, val)
-#define write_c0_config6(val)   __write_32bit_c0_register($16, 6, val)
-#define write_c0_config7(val)   __write_32bit_c0_register($16, 7, val)
-
-/*
- * The WatchLo register.  There may be upto 8 of them.
- */
-#define read_c0_watchlo0()      __read_ulong_c0_register($18, 0)
-#define read_c0_watchlo1()      __read_ulong_c0_register($18, 1)
-#define read_c0_watchlo2()      __read_ulong_c0_register($18, 2)
-#define read_c0_watchlo3()      __read_ulong_c0_register($18, 3)
-#define read_c0_watchlo4()      __read_ulong_c0_register($18, 4)
-#define read_c0_watchlo5()      __read_ulong_c0_register($18, 5)
-#define read_c0_watchlo6()      __read_ulong_c0_register($18, 6)
-#define read_c0_watchlo7()      __read_ulong_c0_register($18, 7)
-#define write_c0_watchlo0(val)  __write_ulong_c0_register($18, 0, val)
-#define write_c0_watchlo1(val)  __write_ulong_c0_register($18, 1, val)
-#define write_c0_watchlo2(val)  __write_ulong_c0_register($18, 2, val)
-#define write_c0_watchlo3(val)  __write_ulong_c0_register($18, 3, val)
-#define write_c0_watchlo4(val)  __write_ulong_c0_register($18, 4, val)
-#define write_c0_watchlo5(val)  __write_ulong_c0_register($18, 5, val)
-#define write_c0_watchlo6(val)  __write_ulong_c0_register($18, 6, val)
-#define write_c0_watchlo7(val)  __write_ulong_c0_register($18, 7, val)
-
-/*
- * The WatchHi register.  There may be upto 8 of them.
- */
-#define read_c0_watchhi0()      __read_32bit_c0_register($19, 0)
-#define read_c0_watchhi1()      __read_32bit_c0_register($19, 1)
-#define read_c0_watchhi2()      __read_32bit_c0_register($19, 2)
-#define read_c0_watchhi3()      __read_32bit_c0_register($19, 3)
-#define read_c0_watchhi4()      __read_32bit_c0_register($19, 4)
-#define read_c0_watchhi5()      __read_32bit_c0_register($19, 5)
-#define read_c0_watchhi6()      __read_32bit_c0_register($19, 6)
-#define read_c0_watchhi7()      __read_32bit_c0_register($19, 7)
-
-#define write_c0_watchhi0(val)  __write_32bit_c0_register($19, 0, val)
-#define write_c0_watchhi1(val)  __write_32bit_c0_register($19, 1, val)
-#define write_c0_watchhi2(val)  __write_32bit_c0_register($19, 2, val)
-#define write_c0_watchhi3(val)  __write_32bit_c0_register($19, 3, val)
-#define write_c0_watchhi4(val)  __write_32bit_c0_register($19, 4, val)
-#define write_c0_watchhi5(val)  __write_32bit_c0_register($19, 5, val)
-#define write_c0_watchhi6(val)  __write_32bit_c0_register($19, 6, val)
-#define write_c0_watchhi7(val)  __write_32bit_c0_register($19, 7, val)
-
-#define read_c0_xcontext()      __read_ulong_c0_register($20, 0)
-#define write_c0_xcontext(val)  __write_ulong_c0_register($20, 0, val)
-
-#define read_c0_intcontrol()    __read_32bit_c0_ctrl_register($20)
-#define write_c0_intcontrol(val) __write_32bit_c0_ctrl_register($20, val)
-
-#define read_c0_framemask()     __read_32bit_c0_register($21, 0)
-#define write_c0_framemask(val) __write_32bit_c0_register($21, 0, val)
-
-/* RM9000 PerfControl performance counter control register */
-#define read_c0_perfcontrol()   __read_32bit_c0_register($22, 0)
-#define write_c0_perfcontrol(val) __write_32bit_c0_register($22, 0, val)
-
-#define read_c0_diag()          __read_32bit_c0_register($22, 0)
-#define write_c0_diag(val)      __write_32bit_c0_register($22, 0, val)
-
-#define read_c0_diag1()         __read_32bit_c0_register($22, 1)
-#define write_c0_diag1(val)     __write_32bit_c0_register($22, 1, val)
-
-#define read_c0_diag2()         __read_32bit_c0_register($22, 2)
-#define write_c0_diag2(val)     __write_32bit_c0_register($22, 2, val)
-
-#define read_c0_diag3()         __read_32bit_c0_register($22, 3)
-#define write_c0_diag3(val)     __write_32bit_c0_register($22, 3, val)
-
-#define read_c0_diag4()         __read_32bit_c0_register($22, 4)
-#define write_c0_diag4(val)     __write_32bit_c0_register($22, 4, val)
-
-#define read_c0_diag5()         __read_32bit_c0_register($22, 5)
-#define write_c0_diag5(val)     __write_32bit_c0_register($22, 5, val)
-
-#define read_c0_debug()         __read_32bit_c0_register($23, 0)
-#define write_c0_debug(val)     __write_32bit_c0_register($23, 0, val)
-
-#define read_c0_depc()          __read_ulong_c0_register($24, 0)
-#define write_c0_depc(val)      __write_ulong_c0_register($24, 0, val)
-
-/*
- * MIPS32 / MIPS64 performance counters
- */
-#define read_c0_perfctrl0()     __read_32bit_c0_register($25, 0)
-#define write_c0_perfctrl0(val) __write_32bit_c0_register($25, 0, val)
-#define read_c0_perfcntr0()     __read_32bit_c0_register($25, 1)
-#define write_c0_perfcntr0(val) __write_32bit_c0_register($25, 1, val)
-#define read_c0_perfctrl1()     __read_32bit_c0_register($25, 2)
-#define write_c0_perfctrl1(val) __write_32bit_c0_register($25, 2, val)
-#define read_c0_perfcntr1()     __read_32bit_c0_register($25, 3)
-#define write_c0_perfcntr1(val) __write_32bit_c0_register($25, 3, val)
-#define read_c0_perfctrl2()     __read_32bit_c0_register($25, 4)
-#define write_c0_perfctrl2(val) __write_32bit_c0_register($25, 4, val)
-#define read_c0_perfcntr2()     __read_32bit_c0_register($25, 5)
-#define write_c0_perfcntr2(val) __write_32bit_c0_register($25, 5, val)
-#define read_c0_perfctrl3()     __read_32bit_c0_register($25, 6)
-#define write_c0_perfctrl3(val) __write_32bit_c0_register($25, 6, val)
-#define read_c0_perfcntr3()     __read_32bit_c0_register($25, 7)
-#define write_c0_perfcntr3(val) __write_32bit_c0_register($25, 7, val)
-
-/* RM9000 PerfCount performance counter register */
-#define read_c0_perfcount()     __read_64bit_c0_register($25, 0)
-#define write_c0_perfcount(val) __write_64bit_c0_register($25, 0, val)
-
-#define read_c0_ecc()           __read_32bit_c0_register($26, 0)
-#define write_c0_ecc(val)       __write_32bit_c0_register($26, 0, val)
-
-#define read_c0_derraddr0()     __read_ulong_c0_register($26, 1)
-#define write_c0_derraddr0(val) __write_ulong_c0_register($26, 1, val)
-
-#define read_c0_cacheerr()      __read_32bit_c0_register($27, 0)
-
-#define read_c0_derraddr1()     __read_ulong_c0_register($27, 1)
-#define write_c0_derraddr1(val) __write_ulong_c0_register($27, 1, val)
-
-#define read_c0_taglo()         __read_32bit_c0_register($28, 0)
-#define write_c0_taglo(val)     __write_32bit_c0_register($28, 0, val)
-
-#define read_c0_dtaglo()        __read_32bit_c0_register($28, 2)
-#define write_c0_dtaglo(val)    __write_32bit_c0_register($28, 2, val)
-
-#define read_c0_taghi()         __read_32bit_c0_register($29, 0)
-#define write_c0_taghi(val)     __write_32bit_c0_register($29, 0, val)
-
-#define read_c0_errorepc()      __read_ulong_c0_register($30, 0)
-#define write_c0_errorepc(val)  __write_ulong_c0_register($30, 0, val)
-
-/* MIPSR2 */
-#define read_c0_hwrena()        __read_32bit_c0_register($7, 0)
-#define write_c0_hwrena(val)    __write_32bit_c0_register($7, 0, val)
-
-#define read_c0_intctl()        __read_32bit_c0_register($12, 1)
-#define write_c0_intctl(val)    __write_32bit_c0_register($12, 1, val)
-
-#define read_c0_srsctl()        __read_32bit_c0_register($12, 2)
-#define write_c0_srsctl(val)    __write_32bit_c0_register($12, 2, val)
-
-#define read_c0_srsmap()        __read_32bit_c0_register($12, 3)
-#define write_c0_srsmap(val)    __write_32bit_c0_register($12, 3, val)
-
-#define read_c0_ebase()         __read_32bit_c0_register($15, 1)
-#define write_c0_ebase(val)     __write_32bit_c0_register($15, 1, val)
-
-/*
- * Macros to access the floating point coprocessor control registers
- */
-#define read_32bit_cp1_register(source)                         \
-({ int __res;                                                   \
-        __asm__ __volatile__(                                   \
-        ".set\tpush\n\t"                                        \
-        ".set\treorder\n\t"                                     \
-        "cfc1\t%0,"STR(source)"\n\t"                            \
-        ".set\tpop"                                             \
-        : "=r" (__res));                                        \
-        __res;})
-
-#define rddsp(mask)                                                     \
-({                                                                      \
-        unsigned int __res;                                             \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                            \n"             \
-        "       .set    noat                            \n"             \
-        "       # rddsp $1, %x1                         \n"             \
-        "       .word   0x7c000cb8 | (%x1 << 16)        \n"             \
-        "       move    %0, $1                          \n"             \
-        "       .set    pop                             \n"             \
-        : "=r" (__res)                                                  \
-        : "i" (mask));                                                  \
-        __res;                                                          \
-})
-
-#define wrdsp(val, mask)                                                \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # wrdsp $1, %x1                                 \n"     \
-        "       .word   0x7c2004f8 | (%x1 << 11)                \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (val), "i" (mask));                                       \
-} while (0)
-
-#if 0   /* Need DSP ASE capable assembler ... */
-#define mflo0() ({ long mflo0; __asm__("mflo %0, $ac0" : "=r" (mflo0)); mflo0;})
-#define mflo1() ({ long mflo1; __asm__("mflo %0, $ac1" : "=r" (mflo1)); mflo1;})
-#define mflo2() ({ long mflo2; __asm__("mflo %0, $ac2" : "=r" (mflo2)); mflo2;})
-#define mflo3() ({ long mflo3; __asm__("mflo %0, $ac3" : "=r" (mflo3)); mflo3;})
-
-#define mfhi0() ({ long mfhi0; __asm__("mfhi %0, $ac0" : "=r" (mfhi0)); mfhi0;})
-#define mfhi1() ({ long mfhi1; __asm__("mfhi %0, $ac1" : "=r" (mfhi1)); mfhi1;})
-#define mfhi2() ({ long mfhi2; __asm__("mfhi %0, $ac2" : "=r" (mfhi2)); mfhi2;})
-#define mfhi3() ({ long mfhi3; __asm__("mfhi %0, $ac3" : "=r" (mfhi3)); mfhi3;})
-
-#define mtlo0(x) __asm__("mtlo %0, $ac0" ::"r" (x))
-#define mtlo1(x) __asm__("mtlo %0, $ac1" ::"r" (x))
-#define mtlo2(x) __asm__("mtlo %0, $ac2" ::"r" (x))
-#define mtlo3(x) __asm__("mtlo %0, $ac3" ::"r" (x))
-
-#define mthi0(x) __asm__("mthi %0, $ac0" ::"r" (x))
-#define mthi1(x) __asm__("mthi %0, $ac1" ::"r" (x))
-#define mthi2(x) __asm__("mthi %0, $ac2" ::"r" (x))
-#define mthi3(x) __asm__("mthi %0, $ac3" ::"r" (x))
-
-#else
-
-#define mfhi0()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mfhi  %0, $ac0                \n"                     \
-        "       .word   0x00000810              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mfhi1()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mfhi  %0, $ac1                \n"                     \
-        "       .word   0x00200810              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mfhi2()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mfhi  %0, $ac2                \n"                     \
-        "       .word   0x00400810              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mfhi3()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mfhi  %0, $ac3                \n"                     \
-        "       .word   0x00600810              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mflo0()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mflo  %0, $ac0                \n"                     \
-        "       .word   0x00000812              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mflo1()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mflo  %0, $ac1                \n"                     \
-        "       .word   0x00200812              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mflo2()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mflo  %0, $ac2                \n"                     \
-        "       .word   0x00400812              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mflo3()                                                         \
-({                                                                      \
-        unsigned long __treg;                                           \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "       .set    push                    \n"                     \
-        "       .set    noat                    \n"                     \
-        "       # mflo  %0, $ac3                \n"                     \
-        "       .word   0x00600812              \n"                     \
-        "       move    %0, $1                  \n"                     \
-        "       .set    pop                     \n"                     \
-        : "=r" (__treg));                                               \
-        __treg;                                                         \
-})
-
-#define mthi0(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mthi  $1, $ac0                                \n"     \
-        "       .word   0x00200011                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mthi1(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mthi  $1, $ac1                                \n"     \
-        "       .word   0x00200811                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mthi2(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mthi  $1, $ac2                                \n"     \
-        "       .word   0x00201011                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mthi3(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mthi  $1, $ac3                                \n"     \
-        "       .word   0x00201811                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mtlo0(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mtlo  $1, $ac0                                \n"     \
-        "       .word   0x00200013                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mtlo1(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mtlo  $1, $ac1                                \n"     \
-        "       .word   0x00200813                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mtlo2(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mtlo  $1, $ac2                                \n"     \
-        "       .word   0x00201013                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#define mtlo3(x)                                                        \
-do {                                                                    \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noat                                    \n"     \
-        "       move    $1, %0                                  \n"     \
-        "       # mtlo  $1, $ac3                                \n"     \
-        "       .word   0x00201813                              \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "r" (x));                                                     \
-} while (0)
-
-#endif
-
-/*
- * TLB operations.
- *
- * It is responsibility of the caller to take care of any TLB hazards.
- */
-static inline void tlb_probe(void)
-{
-        __asm__ __volatile__(
-                ".set noreorder\n\t"
-                "tlbp\n\t"
-                ".set reorder");
-}
-
-static inline void tlb_read(void)
-{
-#if MIPS34K_MISSED_ITLB_WAR
-        int res = 0;
-
-        __asm__ __volatile__(
-        "       .set    push                                    \n"
-        "       .set    noreorder                               \n"
-        "       .set    noat                                    \n"
-        "       .set    mips32r2                                \n"
-        "       .word   0x41610001              # dvpe $1       \n"
-        "       move    %0, $1                                  \n"
-        "       ehb                                             \n"
-        "       .set    pop                                     \n"
-        : "=r" (res));
-
-        instruction_hazard();
-#endif
-
-        __asm__ __volatile__(
-                ".set noreorder\n\t"
-                "tlbr\n\t"
-                ".set reorder");
-
-#if MIPS34K_MISSED_ITLB_WAR
-        if ((res & _ULCAST_(1)))
-                __asm__ __volatile__(
-                "       .set    push                            \n"
-                "       .set    noreorder                       \n"
-                "       .set    noat                            \n"
-                "       .set    mips32r2                        \n"
-                "       .word   0x41600021      # evpe          \n"
-                "       ehb                                     \n"
-                "       .set    pop                             \n");
-#endif
-}
-
-static inline void tlb_write_indexed(void)
-{
-        __asm__ __volatile__(
-                ".set noreorder\n\t"
-                "tlbwi\n\t"
-                ".set reorder");
-}
-
-static inline void tlb_write_random(void)
-{
-        __asm__ __volatile__(
-                ".set noreorder\n\t"
-                "tlbwr\n\t"
-                ".set reorder");
-}
-
-/*
- * Manipulate bits in a c0 register.
- */
-#ifndef CONFIG_MIPS_MT_SMTC
-/*
- * SMTC Linux requires shutting-down microthread scheduling
- * during CP0 register read-modify-write sequences.
- */
-#define __BUILD_SET_C0(name)                                    \
-static inline unsigned int                                      \
-set_c0_##name(unsigned int set)                                 \
-{                                                               \
-        unsigned int res;                                       \
-                                                                \
-        res = read_c0_##name();                                 \
-        res |= set;                                             \
-        write_c0_##name(res);                                   \
-                                                                \
-        return res;                                             \
-}                                                               \
-                                                                \
-static inline unsigned int                                      \
-clear_c0_##name(unsigned int clear)                             \
-{                                                               \
-        unsigned int res;                                       \
-                                                                \
-        res = read_c0_##name();                                 \
-        res &= ~clear;                                          \
-        write_c0_##name(res);                                   \
-                                                                \
-        return res;                                             \
-}                                                               \
-                                                                \
-static inline unsigned int                                      \
-change_c0_##name(unsigned int change, unsigned int new)         \
-{                                                               \
-        unsigned int res;                                       \
-                                                                \
-        res = read_c0_##name();                                 \
-        res &= ~change;                                         \
-        res |= (new & change);                                  \
-        write_c0_##name(res);                                   \
-                                                                \
-        return res;                                             \
-}
-
-#else /* SMTC versions that manage MT scheduling */
-
-#include <linux/irqflags.h>
-
-/*
- * This is a duplicate of dmt() in mipsmtregs.h to avoid problems with
- * header file recursion.
- */
-static inline unsigned int __dmt(void)
-{
-        int res;
-
-        __asm__ __volatile__(
-        "       .set    push                                            \n"
-        "       .set    mips32r2                                        \n"
-        "       .set    noat                                            \n"
-        "       .word   0x41610BC1                      # dmt $1        \n"
-        "       ehb                                                     \n"
-        "       move    %0, $1                                          \n"
-        "       .set    pop                                             \n"
-        : "=r" (res));
-
-        instruction_hazard();
-
-        return res;
-}
-
-#define __VPECONTROL_TE_SHIFT   15
-#define __VPECONTROL_TE         (1UL << __VPECONTROL_TE_SHIFT)
-
-#define __EMT_ENABLE            __VPECONTROL_TE
-
-static inline void __emt(unsigned int previous)
-{
-        if ((previous & __EMT_ENABLE))
-                __asm__ __volatile__(
-                "       .set    mips32r2                                \n"
-                "       .word   0x41600be1              # emt           \n"
-                "       ehb                                             \n"
-                "       .set    mips0                                   \n");
-}
-
-static inline void __ehb(void)
-{
-        __asm__ __volatile__(
-        "       .set    mips32r2                                        \n"
-        "       ehb                                                     \n"             "       .set    mips0                                           \n");
-}
-
-/*
- * Note that local_irq_save/restore affect TC-specific IXMT state,
- * not Status.IE as in non-SMTC kernel.
- */
-
-#define __BUILD_SET_C0(name)                                    \
-static inline unsigned int                                      \
-set_c0_##name(unsigned int set)                                 \
-{                                                               \
-        unsigned int res;                                       \
-        unsigned int omt;                                       \
-        unsigned int flags;                                     \
-                                                                \
-        local_irq_save(flags);                                  \
-        omt = __dmt();                                          \
-        res = read_c0_##name();                                 \
-        res |= set;                                             \
-        write_c0_##name(res);                                   \
-        __emt(omt);                                             \
-        local_irq_restore(flags);                               \
-                                                                \
-        return res;                                             \
-}                                                               \
-                                                                \
-static inline unsigned int                                      \
-clear_c0_##name(unsigned int clear)                             \
-{                                                               \
-        unsigned int res;                                       \
-        unsigned int omt;                                       \
-        unsigned int flags;                                     \
-                                                                \
-        local_irq_save(flags);                                  \
-        omt = __dmt();                                          \
-        res = read_c0_##name();                                 \
-        res &= ~clear;                                          \
-        write_c0_##name(res);                                   \
-        __emt(omt);                                             \
-        local_irq_restore(flags);                               \
-                                                                \
-        return res;                                             \
-}                                                               \
-                                                                \
-static inline unsigned int                                      \
-change_c0_##name(unsigned int change, unsigned int new)         \
-{                                                               \
-        unsigned int res;                                       \
-        unsigned int omt;                                       \
-        unsigned int flags;                                     \
-                                                                \
-        local_irq_save(flags);                                  \
-                                                                \
-        omt = __dmt();                                          \
-        res = read_c0_##name();                                 \
-        res &= ~change;                                         \
-        res |= (new & change);                                  \
-        write_c0_##name(res);                                   \
-        __emt(omt);                                             \
-        local_irq_restore(flags);                               \
-                                                                \
-        return res;                                             \
-}
-#endif
-
-__BUILD_SET_C0(status)
-__BUILD_SET_C0(cause)
-__BUILD_SET_C0(config)
-__BUILD_SET_C0(intcontrol)
-__BUILD_SET_C0(intctl)
-__BUILD_SET_C0(srsmap)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_MIPSREGS_H */
diff --git a/include/asm-mips/mman.h b/include/asm-mips/mman.h
deleted file mode 100644
index e4d6f1fb1cf7..000000000000
--- a/include/asm-mips/mman.h
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999, 2002 by Ralf Baechle
- */
-#ifndef _ASM_MMAN_H
-#define _ASM_MMAN_H
-
-/*
- * Protections are chosen from these bits, OR'd together.  The
- * implementation does not necessarily support PROT_EXEC or PROT_WRITE
- * without PROT_READ.  The only guarantees are that no writing will be
- * allowed without PROT_WRITE and no access will be allowed for PROT_NONE.
- */
-#define PROT_NONE       0x00            /* page can not be accessed */
-#define PROT_READ       0x01            /* page can be read */
-#define PROT_WRITE      0x02            /* page can be written */
-#define PROT_EXEC       0x04            /* page can be executed */
-/*                      0x08               reserved for PROT_EXEC_NOFLUSH */
-#define PROT_SEM        0x10            /* page may be used for atomic ops */
-#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
-#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
-
-/*
- * Flags for mmap
- */
-#define MAP_SHARED      0x001           /* Share changes */
-#define MAP_PRIVATE     0x002           /* Changes are private */
-#define MAP_TYPE        0x00f           /* Mask for type of mapping */
-#define MAP_FIXED       0x010           /* Interpret addr exactly */
-
-/* not used by linux, but here to make sure we don't clash with ABI defines */
-#define MAP_RENAME      0x020           /* Assign page to file */
-#define MAP_AUTOGROW    0x040           /* File may grow by writing */
-#define MAP_LOCAL       0x080           /* Copy on fork/sproc */
-#define MAP_AUTORSRV    0x100           /* Logical swap reserved on demand */
-
-/* These are linux-specific */
-#define MAP_NORESERVE   0x0400          /* don't check for reservations */
-#define MAP_ANONYMOUS   0x0800          /* don't use a file */
-#define MAP_GROWSDOWN   0x1000          /* stack-like segment */
-#define MAP_DENYWRITE   0x2000          /* ETXTBSY */
-#define MAP_EXECUTABLE  0x4000          /* mark it as an executable */
-#define MAP_LOCKED      0x8000          /* pages are locked */
-#define MAP_POPULATE    0x10000         /* populate (prefault) pagetables */
-#define MAP_NONBLOCK    0x20000         /* do not block on IO */
-
-/*
- * Flags for msync
- */
-#define MS_ASYNC        0x0001          /* sync memory asynchronously */
-#define MS_INVALIDATE   0x0002          /* invalidate mappings & caches */
-#define MS_SYNC         0x0004          /* synchronous memory sync */
-
-/*
- * Flags for mlockall
- */
-#define MCL_CURRENT     1               /* lock all current mappings */
-#define MCL_FUTURE      2               /* lock all future mappings */
-
-#define MADV_NORMAL     0               /* no further special treatment */
-#define MADV_RANDOM     1               /* expect random page references */
-#define MADV_SEQUENTIAL 2               /* expect sequential page references */
-#define MADV_WILLNEED   3               /* will need these pages */
-#define MADV_DONTNEED   4               /* don't need these pages */
-
-/* common parameters: try to keep these consistent across architectures */
-#define MADV_REMOVE     9               /* remove these pages & resources */
-#define MADV_DONTFORK   10              /* don't inherit across fork */
-#define MADV_DOFORK     11              /* do inherit across fork */
-
-/* compatibility flags */
-#define MAP_FILE        0
-
-#endif /* _ASM_MMAN_H */
diff --git a/include/asm-mips/mmu.h b/include/asm-mips/mmu.h
deleted file mode 100644
index 4063edd79623..000000000000
--- a/include/asm-mips/mmu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_MMU_H
-#define __ASM_MMU_H
-
-typedef unsigned long mm_context_t[NR_CPUS];
-
-#endif /* __ASM_MMU_H */
diff --git a/include/asm-mips/mmu_context.h b/include/asm-mips/mmu_context.h
deleted file mode 100644
index 0c4f245eaeb2..000000000000
--- a/include/asm-mips/mmu_context.h
+++ /dev/null
@@ -1,297 +0,0 @@
-/*
- * Switch a MMU context.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 1999 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_MMU_CONTEXT_H
-#define _ASM_MMU_CONTEXT_H
-
-#include <linux/errno.h>
-#include <linux/sched.h>
-#include <linux/slab.h>
-#include <asm/cacheflush.h>
-#include <asm/tlbflush.h>
-#ifdef CONFIG_MIPS_MT_SMTC
-#include <asm/mipsmtregs.h>
-#include <asm/smtc.h>
-#endif /* SMTC */
-#include <asm-generic/mm_hooks.h>
-
-/*
- * For the fast tlb miss handlers, we keep a per cpu array of pointers
- * to the current pgd for each processor. Also, the proc. id is stuffed
- * into the context register.
- */
-extern unsigned long pgd_current[];
-
-#define TLBMISS_HANDLER_SETUP_PGD(pgd) \
-        pgd_current[smp_processor_id()] = (unsigned long)(pgd)
-
-#ifdef CONFIG_32BIT
-#define TLBMISS_HANDLER_SETUP()                                         \
-        write_c0_context((unsigned long) smp_processor_id() << 25);     \
-        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
-#endif
-#ifdef CONFIG_64BIT
-#define TLBMISS_HANDLER_SETUP()                                         \
-        write_c0_context((unsigned long) smp_processor_id() << 26);     \
-        TLBMISS_HANDLER_SETUP_PGD(swapper_pg_dir)
-#endif
-
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-
-#define ASID_INC        0x40
-#define ASID_MASK       0xfc0
-
-#elif defined(CONFIG_CPU_R8000)
-
-#define ASID_INC        0x10
-#define ASID_MASK       0xff0
-
-#elif defined(CONFIG_CPU_RM9000)
-
-#define ASID_INC        0x1
-#define ASID_MASK       0xfff
-
-/* SMTC/34K debug hack - but maybe we'll keep it */
-#elif defined(CONFIG_MIPS_MT_SMTC)
-
-#define ASID_INC        0x1
-extern unsigned long smtc_asid_mask;
-#define ASID_MASK       (smtc_asid_mask)
-#define HW_ASID_MASK    0xff
-/* End SMTC/34K debug hack */
-#else /* FIXME: not correct for R6000 */
-
-#define ASID_INC        0x1
-#define ASID_MASK       0xff
-
-#endif
-
-#define cpu_context(cpu, mm)    ((mm)->context[cpu])
-#define cpu_asid(cpu, mm)       (cpu_context((cpu), (mm)) & ASID_MASK)
-#define asid_cache(cpu)         (cpu_data[cpu].asid_cache)
-
-static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
-{
-}
-
-/*
- *  All unused by hardware upper bits will be considered
- *  as a software asid extension.
- */
-#define ASID_VERSION_MASK  ((unsigned long)~(ASID_MASK|(ASID_MASK-1)))
-#define ASID_FIRST_VERSION ((unsigned long)(~ASID_VERSION_MASK) + 1)
-
-#ifndef CONFIG_MIPS_MT_SMTC
-/* Normal, classic MIPS get_new_mmu_context */
-static inline void
-get_new_mmu_context(struct mm_struct *mm, unsigned long cpu)
-{
-        unsigned long asid = asid_cache(cpu);
-
-        if (! ((asid += ASID_INC) & ASID_MASK) ) {
-                if (cpu_has_vtag_icache)
-                        flush_icache_all();
-                local_flush_tlb_all();  /* start new asid cycle */
-                if (!asid)              /* fix version if needed */
-                        asid = ASID_FIRST_VERSION;
-        }
-        cpu_context(cpu, mm) = asid_cache(cpu) = asid;
-}
-
-#else /* CONFIG_MIPS_MT_SMTC */
-
-#define get_new_mmu_context(mm, cpu) smtc_get_new_mmu_context((mm), (cpu))
-
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-/*
- * Initialize the context related info for a new mm_struct
- * instance.
- */
-static inline int
-init_new_context(struct task_struct *tsk, struct mm_struct *mm)
-{
-        int i;
-
-        for_each_online_cpu(i)
-                cpu_context(i, mm) = 0;
-
-        return 0;
-}
-
-static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
-                             struct task_struct *tsk)
-{
-        unsigned int cpu = smp_processor_id();
-        unsigned long flags;
-#ifdef CONFIG_MIPS_MT_SMTC
-        unsigned long oldasid;
-        unsigned long mtflags;
-        int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
-        local_irq_save(flags);
-        mtflags = dvpe();
-#else /* Not SMTC */
-        local_irq_save(flags);
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-        /* Check if our ASID is of an older version and thus invalid */
-        if ((cpu_context(cpu, next) ^ asid_cache(cpu)) & ASID_VERSION_MASK)
-                get_new_mmu_context(next, cpu);
-#ifdef CONFIG_MIPS_MT_SMTC
-        /*
-         * If the EntryHi ASID being replaced happens to be
-         * the value flagged at ASID recycling time as having
-         * an extended life, clear the bit showing it being
-         * in use by this "CPU", and if that's the last bit,
-         * free up the ASID value for use and flush any old
-         * instances of it from the TLB.
-         */
-        oldasid = (read_c0_entryhi() & ASID_MASK);
-        if(smtc_live_asid[mytlb][oldasid]) {
-                smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
-                if(smtc_live_asid[mytlb][oldasid] == 0)
-                        smtc_flush_tlb_asid(oldasid);
-        }
-        /*
-         * Tread softly on EntryHi, and so long as we support
-         * having ASID_MASK smaller than the hardware maximum,
-         * make sure no "soft" bits become "hard"...
-         */
-        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
-                        | (cpu_context(cpu, next) & ASID_MASK));
-        ehb(); /* Make sure it propagates to TCStatus */
-        evpe(mtflags);
-#else
-        write_c0_entryhi(cpu_context(cpu, next));
-#endif /* CONFIG_MIPS_MT_SMTC */
-        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
-
-        /*
-         * Mark current->active_mm as not "active" anymore.
-         * We don't want to mislead possible IPI tlb flush routines.
-         */
-        cpu_clear(cpu, prev->cpu_vm_mask);
-        cpu_set(cpu, next->cpu_vm_mask);
-
-        local_irq_restore(flags);
-}
-
-/*
- * Destroy context related info for an mm_struct that is about
- * to be put to rest.
- */
-static inline void destroy_context(struct mm_struct *mm)
-{
-}
-
-#define deactivate_mm(tsk, mm)  do { } while (0)
-
-/*
- * After we have set current->mm to a new value, this activates
- * the context for the new mm so we see the new mappings.
- */
-static inline void
-activate_mm(struct mm_struct *prev, struct mm_struct *next)
-{
-        unsigned long flags;
-        unsigned int cpu = smp_processor_id();
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        unsigned long oldasid;
-        unsigned long mtflags;
-        int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-        local_irq_save(flags);
-
-        /* Unconditionally get a new ASID.  */
-        get_new_mmu_context(next, cpu);
-
-#ifdef CONFIG_MIPS_MT_SMTC
-        /* See comments for similar code above */
-        mtflags = dvpe();
-        oldasid = read_c0_entryhi() & ASID_MASK;
-        if(smtc_live_asid[mytlb][oldasid]) {
-                smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
-                if(smtc_live_asid[mytlb][oldasid] == 0)
-                         smtc_flush_tlb_asid(oldasid);
-        }
-        /* See comments for similar code above */
-        write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK) |
-                         (cpu_context(cpu, next) & ASID_MASK));
-        ehb(); /* Make sure it propagates to TCStatus */
-        evpe(mtflags);
-#else
-        write_c0_entryhi(cpu_context(cpu, next));
-#endif /* CONFIG_MIPS_MT_SMTC */
-        TLBMISS_HANDLER_SETUP_PGD(next->pgd);
-
-        /* mark mmu ownership change */
-        cpu_clear(cpu, prev->cpu_vm_mask);
-        cpu_set(cpu, next->cpu_vm_mask);
-
-        local_irq_restore(flags);
-}
-
-/*
- * If mm is currently active_mm, we can't really drop it.  Instead,
- * we will get a new one for it.
- */
-static inline void
-drop_mmu_context(struct mm_struct *mm, unsigned cpu)
-{
-        unsigned long flags;
-#ifdef CONFIG_MIPS_MT_SMTC
-        unsigned long oldasid;
-        /* Can't use spinlock because called from TLB flush within DVPE */
-        unsigned int prevvpe;
-        int mytlb = (smtc_status & SMTC_TLB_SHARED) ? 0 : cpu_data[cpu].vpe_id;
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-        local_irq_save(flags);
-
-        if (cpu_isset(cpu, mm->cpu_vm_mask))  {
-                get_new_mmu_context(mm, cpu);
-#ifdef CONFIG_MIPS_MT_SMTC
-                /* See comments for similar code above */
-                prevvpe = dvpe();
-                oldasid = (read_c0_entryhi() & ASID_MASK);
-                if (smtc_live_asid[mytlb][oldasid]) {
-                        smtc_live_asid[mytlb][oldasid] &= ~(0x1 << cpu);
-                        if(smtc_live_asid[mytlb][oldasid] == 0)
-                                smtc_flush_tlb_asid(oldasid);
-                }
-                /* See comments for similar code above */
-                write_c0_entryhi((read_c0_entryhi() & ~HW_ASID_MASK)
-                                | cpu_asid(cpu, mm));
-                ehb(); /* Make sure it propagates to TCStatus */
-                evpe(prevvpe);
-#else /* not CONFIG_MIPS_MT_SMTC */
-                write_c0_entryhi(cpu_asid(cpu, mm));
-#endif /* CONFIG_MIPS_MT_SMTC */
-        } else {
-                /* will get a new context next time */
-#ifndef CONFIG_MIPS_MT_SMTC
-                cpu_context(cpu, mm) = 0;
-#else /* SMTC */
-                int i;
-
-                /* SMTC shares the TLB (and ASIDs) across VPEs */
-                for_each_online_cpu(i) {
-                    if((smtc_status & SMTC_TLB_SHARED)
-                    || (cpu_data[i].vpe_id == cpu_data[cpu].vpe_id))
-                        cpu_context(i, mm) = 0;
-                }
-#endif /* CONFIG_MIPS_MT_SMTC */
-        }
-        local_irq_restore(flags);
-}
-
-#endif /* _ASM_MMU_CONTEXT_H */
diff --git a/include/asm-mips/mmzone.h b/include/asm-mips/mmzone.h
deleted file mode 100644
index f53ec54c92ff..000000000000
--- a/include/asm-mips/mmzone.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * Written by Kanoj Sarcar (kanoj@sgi.com) Aug 99
- * Rewritten for Linux 2.6 by Christoph Hellwig (hch@lst.de) Jan 2004
- */
-#ifndef _ASM_MMZONE_H_
-#define _ASM_MMZONE_H_
-
-#include <asm/page.h>
-#include <mmzone.h>
-
-#ifdef CONFIG_DISCONTIGMEM
-
-#define pfn_to_nid(pfn)         pa_to_nid((pfn) << PAGE_SHIFT)
-
-#endif /* CONFIG_DISCONTIGMEM */
-
-#endif /* _ASM_MMZONE_H_ */
diff --git a/include/asm-mips/module.h b/include/asm-mips/module.h
deleted file mode 100644
index de6d09ebbd80..000000000000
--- a/include/asm-mips/module.h
+++ /dev/null
@@ -1,136 +0,0 @@
-#ifndef _ASM_MODULE_H
-#define _ASM_MODULE_H
-
-#include <linux/list.h>
-#include <asm/uaccess.h>
-
-struct mod_arch_specific {
-        /* Data Bus Error exception tables */
-        struct list_head dbe_list;
-        const struct exception_table_entry *dbe_start;
-        const struct exception_table_entry *dbe_end;
-};
-
-typedef uint8_t Elf64_Byte;             /* Type for a 8-bit quantity.  */
-
-typedef struct {
-        Elf64_Addr r_offset;                    /* Address of relocation.  */
-        Elf64_Word r_sym;                       /* Symbol index.  */
-        Elf64_Byte r_ssym;                      /* Special symbol.  */
-        Elf64_Byte r_type3;                     /* Third relocation.  */
-        Elf64_Byte r_type2;                     /* Second relocation.  */
-        Elf64_Byte r_type;                      /* First relocation.  */
-} Elf64_Mips_Rel;
-
-typedef struct {
-        Elf64_Addr r_offset;                    /* Address of relocation.  */
-        Elf64_Word r_sym;                       /* Symbol index.  */
-        Elf64_Byte r_ssym;                      /* Special symbol.  */
-        Elf64_Byte r_type3;                     /* Third relocation.  */
-        Elf64_Byte r_type2;                     /* Second relocation.  */
-        Elf64_Byte r_type;                      /* First relocation.  */
-        Elf64_Sxword r_addend;                  /* Addend.  */
-} Elf64_Mips_Rela;
-
-#ifdef CONFIG_32BIT
-
-#define Elf_Shdr        Elf32_Shdr
-#define Elf_Sym         Elf32_Sym
-#define Elf_Ehdr        Elf32_Ehdr
-#define Elf_Addr        Elf32_Addr
-
-#define Elf_Mips_Rel    Elf32_Rel
-#define Elf_Mips_Rela   Elf32_Rela
-
-#define ELF_MIPS_R_SYM(rel) ELF32_R_SYM(rel.r_info)
-#define ELF_MIPS_R_TYPE(rel) ELF32_R_TYPE(rel.r_info)
-
-#endif
-
-#ifdef CONFIG_64BIT
-
-#define Elf_Shdr        Elf64_Shdr
-#define Elf_Sym         Elf64_Sym
-#define Elf_Ehdr        Elf64_Ehdr
-#define Elf_Addr        Elf64_Addr
-
-#define Elf_Mips_Rel    Elf64_Mips_Rel
-#define Elf_Mips_Rela   Elf64_Mips_Rela
-
-#define ELF_MIPS_R_SYM(rel) (rel.r_sym)
-#define ELF_MIPS_R_TYPE(rel) (rel.r_type)
-
-#endif
-
-#ifdef CONFIG_MODULES
-/* Given an address, look for it in the exception tables. */
-const struct exception_table_entry*search_module_dbetables(unsigned long addr);
-#else
-/* Given an address, look for it in the exception tables. */
-static inline const struct exception_table_entry *
-search_module_dbetables(unsigned long addr)
-{
-        return NULL;
-}
-#endif
-
-#ifdef CONFIG_CPU_MIPS32_R1
-#define MODULE_PROC_FAMILY "MIPS32_R1 "
-#elif defined CONFIG_CPU_MIPS32_R2
-#define MODULE_PROC_FAMILY "MIPS32_R2 "
-#elif defined CONFIG_CPU_MIPS64_R1
-#define MODULE_PROC_FAMILY "MIPS64_R1 "
-#elif defined CONFIG_CPU_MIPS64_R2
-#define MODULE_PROC_FAMILY "MIPS64_R2 "
-#elif defined CONFIG_CPU_R3000
-#define MODULE_PROC_FAMILY "R3000 "
-#elif defined CONFIG_CPU_TX39XX
-#define MODULE_PROC_FAMILY "TX39XX "
-#elif defined CONFIG_CPU_VR41XX
-#define MODULE_PROC_FAMILY "VR41XX "
-#elif defined CONFIG_CPU_R4300
-#define MODULE_PROC_FAMILY "R4300 "
-#elif defined CONFIG_CPU_R4X00
-#define MODULE_PROC_FAMILY "R4X00 "
-#elif defined CONFIG_CPU_TX49XX
-#define MODULE_PROC_FAMILY "TX49XX "
-#elif defined CONFIG_CPU_R5000
-#define MODULE_PROC_FAMILY "R5000 "
-#elif defined CONFIG_CPU_R5432
-#define MODULE_PROC_FAMILY "R5432 "
-#elif defined CONFIG_CPU_R6000
-#define MODULE_PROC_FAMILY "R6000 "
-#elif defined CONFIG_CPU_NEVADA
-#define MODULE_PROC_FAMILY "NEVADA "
-#elif defined CONFIG_CPU_R8000
-#define MODULE_PROC_FAMILY "R8000 "
-#elif defined CONFIG_CPU_R10000
-#define MODULE_PROC_FAMILY "R10000 "
-#elif defined CONFIG_CPU_RM7000
-#define MODULE_PROC_FAMILY "RM7000 "
-#elif defined CONFIG_CPU_RM9000
-#define MODULE_PROC_FAMILY "RM9000 "
-#elif defined CONFIG_CPU_SB1
-#define MODULE_PROC_FAMILY "SB1 "
-#elif defined CONFIG_CPU_LOONGSON2
-#define MODULE_PROC_FAMILY "LOONGSON2 "
-#else
-#error MODULE_PROC_FAMILY undefined for your processor configuration
-#endif
-
-#ifdef CONFIG_32BIT
-#define MODULE_KERNEL_TYPE "32BIT "
-#elif defined CONFIG_64BIT
-#define MODULE_KERNEL_TYPE "64BIT "
-#endif
-
-#ifdef CONFIG_MIPS_MT_SMTC
-#define MODULE_KERNEL_SMTC "MT_SMTC "
-#else
-#define MODULE_KERNEL_SMTC ""
-#endif
-
-#define MODULE_ARCH_VERMAGIC \
-        MODULE_PROC_FAMILY MODULE_KERNEL_TYPE MODULE_KERNEL_SMTC
-
-#endif /* _ASM_MODULE_H */
diff --git a/include/asm-mips/msc01_ic.h b/include/asm-mips/msc01_ic.h
deleted file mode 100644
index 7989b9ffc1d2..000000000000
--- a/include/asm-mips/msc01_ic.h
+++ /dev/null
@@ -1,148 +0,0 @@
-/*
- * PCI Register definitions for the MIPS System Controller.
- *
- * Copyright (C) 2004 MIPS Technologies, Inc.  All rights reserved.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-
-#ifndef __ASM_MIPS_BOARDS_MSC01_IC_H
-#define __ASM_MIPS_BOARDS_MSC01_IC_H
-
-/*****************************************************************************
- * Register offset addresses
- *****************************************************************************/
-
-#define MSC01_IC_RST_OFS     0x00008    /* Software reset              */
-#define MSC01_IC_ENAL_OFS    0x00100    /* Int_in enable mask 31:0     */
-#define MSC01_IC_ENAH_OFS    0x00108    /* Int_in enable mask 63:32    */
-#define MSC01_IC_DISL_OFS    0x00120    /* Int_in disable mask 31:0    */
-#define MSC01_IC_DISH_OFS    0x00128    /* Int_in disable mask 63:32   */
-#define MSC01_IC_ISBL_OFS    0x00140    /* Raw int_in 31:0             */
-#define MSC01_IC_ISBH_OFS    0x00148    /* Raw int_in 63:32            */
-#define MSC01_IC_ISAL_OFS    0x00160    /* Masked int_in 31:0          */
-#define MSC01_IC_ISAH_OFS    0x00168    /* Masked int_in 63:32         */
-#define MSC01_IC_LVL_OFS     0x00180    /* Disable priority int_out    */
-#define MSC01_IC_RAMW_OFS    0x00180    /* Shadow set RAM (EI)         */
-#define MSC01_IC_OSB_OFS     0x00188    /* Raw int_out                 */
-#define MSC01_IC_OSA_OFS     0x00190    /* Masked int_out              */
-#define MSC01_IC_GENA_OFS    0x00198    /* Global HW int enable        */
-#define MSC01_IC_BASE_OFS    0x001a0    /* Base address of IC_VEC      */
-#define MSC01_IC_VEC_OFS     0x001b0    /* Active int's vector address */
-#define MSC01_IC_EOI_OFS     0x001c0    /* Enable lower level ints     */
-#define MSC01_IC_CFG_OFS     0x001c8    /* Configuration register      */
-#define MSC01_IC_TRLD_OFS    0x001d0    /* Interval timer reload val   */
-#define MSC01_IC_TVAL_OFS    0x001e0    /* Interval timer current val  */
-#define MSC01_IC_TCFG_OFS    0x001f0    /* Interval timer config       */
-#define MSC01_IC_SUP_OFS     0x00200    /* Set up int_in line 0        */
-#define MSC01_IC_ENA_OFS     0x00800    /* Int_in enable mask 63:0     */
-#define MSC01_IC_DIS_OFS     0x00820    /* Int_in disable mask 63:0    */
-#define MSC01_IC_ISB_OFS     0x00840    /* Raw int_in 63:0             */
-#define MSC01_IC_ISA_OFS     0x00860    /* Masked int_in 63:0          */
-
-/*****************************************************************************
- * Register field encodings
- *****************************************************************************/
-
-#define MSC01_IC_RST_RST_SHF      0
-#define MSC01_IC_RST_RST_MSK      0x00000001
-#define MSC01_IC_RST_RST_BIT      MSC01_IC_RST_RST_MSK
-#define MSC01_IC_LVL_LVL_SHF      0
-#define MSC01_IC_LVL_LVL_MSK      0x000000ff
-#define MSC01_IC_LVL_SPUR_SHF     16
-#define MSC01_IC_LVL_SPUR_MSK     0x00010000
-#define MSC01_IC_LVL_SPUR_BIT     MSC01_IC_LVL_SPUR_MSK
-#define MSC01_IC_RAMW_RIPL_SHF    0
-#define MSC01_IC_RAMW_RIPL_MSK    0x0000003f
-#define MSC01_IC_RAMW_DATA_SHF    6
-#define MSC01_IC_RAMW_DATA_MSK    0x00000fc0
-#define MSC01_IC_RAMW_ADDR_SHF    25
-#define MSC01_IC_RAMW_ADDR_MSK    0x7e000000
-#define MSC01_IC_RAMW_READ_SHF    31
-#define MSC01_IC_RAMW_READ_MSK    0x80000000
-#define MSC01_IC_RAMW_READ_BIT    MSC01_IC_RAMW_READ_MSK
-#define MSC01_IC_OSB_OSB_SHF      0
-#define MSC01_IC_OSB_OSB_MSK      0x000000ff
-#define MSC01_IC_OSA_OSA_SHF      0
-#define MSC01_IC_OSA_OSA_MSK      0x000000ff
-#define MSC01_IC_GENA_GENA_SHF    0
-#define MSC01_IC_GENA_GENA_MSK    0x00000001
-#define MSC01_IC_GENA_GENA_BIT    MSC01_IC_GENA_GENA_MSK
-#define MSC01_IC_CFG_DIS_SHF      0
-#define MSC01_IC_CFG_DIS_MSK      0x00000001
-#define MSC01_IC_CFG_DIS_BIT      MSC01_IC_CFG_DIS_MSK
-#define MSC01_IC_CFG_SHFT_SHF     8
-#define MSC01_IC_CFG_SHFT_MSK     0x00000f00
-#define MSC01_IC_TCFG_ENA_SHF     0
-#define MSC01_IC_TCFG_ENA_MSK     0x00000001
-#define MSC01_IC_TCFG_ENA_BIT     MSC01_IC_TCFG_ENA_MSK
-#define MSC01_IC_TCFG_INT_SHF     8
-#define MSC01_IC_TCFG_INT_MSK     0x00000100
-#define MSC01_IC_TCFG_INT_BIT     MSC01_IC_TCFG_INT_MSK
-#define MSC01_IC_TCFG_EDGE_SHF    16
-#define MSC01_IC_TCFG_EDGE_MSK    0x00010000
-#define MSC01_IC_TCFG_EDGE_BIT    MSC01_IC_TCFG_EDGE_MSK
-#define MSC01_IC_SUP_PRI_SHF      0
-#define MSC01_IC_SUP_PRI_MSK      0x00000007
-#define MSC01_IC_SUP_EDGE_SHF     8
-#define MSC01_IC_SUP_EDGE_MSK     0x00000100
-#define MSC01_IC_SUP_EDGE_BIT     MSC01_IC_SUP_EDGE_MSK
-#define MSC01_IC_SUP_STEP         8
-
-/*
- * MIPS System controller interrupt register base.
- *
- */
-
-/*****************************************************************************
- * Absolute register addresses
- *****************************************************************************/
-
-#define MSC01_IC_RST     (MSC01_IC_REG_BASE + MSC01_IC_RST_OFS)
-#define MSC01_IC_ENAL    (MSC01_IC_REG_BASE + MSC01_IC_ENAL_OFS)
-#define MSC01_IC_ENAH    (MSC01_IC_REG_BASE + MSC01_IC_ENAH_OFS)
-#define MSC01_IC_DISL    (MSC01_IC_REG_BASE + MSC01_IC_DISL_OFS)
-#define MSC01_IC_DISH    (MSC01_IC_REG_BASE + MSC01_IC_DISH_OFS)
-#define MSC01_IC_ISBL    (MSC01_IC_REG_BASE + MSC01_IC_ISBL_OFS)
-#define MSC01_IC_ISBH    (MSC01_IC_REG_BASE + MSC01_IC_ISBH_OFS)
-#define MSC01_IC_ISAL    (MSC01_IC_REG_BASE + MSC01_IC_ISAL_OFS)
-#define MSC01_IC_ISAH    (MSC01_IC_REG_BASE + MSC01_IC_ISAH_OFS)
-#define MSC01_IC_LVL     (MSC01_IC_REG_BASE + MSC01_IC_LVL_OFS)
-#define MSC01_IC_RAMW    (MSC01_IC_REG_BASE + MSC01_IC_RAMW_OFS)
-#define MSC01_IC_OSB     (MSC01_IC_REG_BASE + MSC01_IC_OSB_OFS)
-#define MSC01_IC_OSA     (MSC01_IC_REG_BASE + MSC01_IC_OSA_OFS)
-#define MSC01_IC_GENA    (MSC01_IC_REG_BASE + MSC01_IC_GENA_OFS)
-#define MSC01_IC_BASE    (MSC01_IC_REG_BASE + MSC01_IC_BASE_OFS)
-#define MSC01_IC_VEC     (MSC01_IC_REG_BASE + MSC01_IC_VEC_OFS)
-#define MSC01_IC_EOI     (MSC01_IC_REG_BASE + MSC01_IC_EOI_OFS)
-#define MSC01_IC_CFG     (MSC01_IC_REG_BASE + MSC01_IC_CFG_OFS)
-#define MSC01_IC_TRLD    (MSC01_IC_REG_BASE + MSC01_IC_TRLD_OFS)
-#define MSC01_IC_TVAL    (MSC01_IC_REG_BASE + MSC01_IC_TVAL_OFS)
-#define MSC01_IC_TCFG    (MSC01_IC_REG_BASE + MSC01_IC_TCFG_OFS)
-#define MSC01_IC_SUP     (MSC01_IC_REG_BASE + MSC01_IC_SUP_OFS)
-#define MSC01_IC_ENA     (MSC01_IC_REG_BASE + MSC01_IC_ENA_OFS)
-#define MSC01_IC_DIS     (MSC01_IC_REG_BASE + MSC01_IC_DIS_OFS)
-#define MSC01_IC_ISB     (MSC01_IC_REG_BASE + MSC01_IC_ISB_OFS)
-#define MSC01_IC_ISA     (MSC01_IC_REG_BASE + MSC01_IC_ISA_OFS)
-
-/*
- * Soc-it interrupts are configurable.
- * Every board describes its IRQ mapping with this table.
- */
-typedef struct msc_irqmap {
-        int     im_irq;
-        int     im_type;
-        int     im_lvl;
-} msc_irqmap_t;
-
-/* im_type */
-#define MSC01_IRQ_LEVEL         0
-#define MSC01_IRQ_EDGE          1
-
-extern void __init init_msc_irqs(unsigned long icubase, unsigned int base, msc_irqmap_t *imp, int nirq);
-extern void ll_msc_irq(void);
-
-#endif /* __ASM_MIPS_BOARDS_MSC01_IC_H */
-
diff --git a/include/asm-mips/msgbuf.h b/include/asm-mips/msgbuf.h
deleted file mode 100644
index 0d6c7f14de31..000000000000
--- a/include/asm-mips/msgbuf.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef _ASM_MSGBUF_H
-#define _ASM_MSGBUF_H
-
-
-/*
- * The msqid64_ds structure for the MIPS architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - extension of time_t to 64-bit on 32-bitsystem to solve the y2038 problem
- * - 2 miscellaneous unsigned long values
- */
-
-struct msqid64_ds {
-        struct ipc64_perm msg_perm;
-#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
-        unsigned long   __unused1;
-#endif
-        __kernel_time_t msg_stime;      /* last msgsnd time */
-#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
-        unsigned long   __unused1;
-#endif
-#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
-        unsigned long   __unused2;
-#endif
-        __kernel_time_t msg_rtime;      /* last msgrcv time */
-#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
-        unsigned long   __unused2;
-#endif
-#if defined(CONFIG_32BIT) && !defined(CONFIG_CPU_LITTLE_ENDIAN)
-        unsigned long   __unused3;
-#endif
-        __kernel_time_t msg_ctime;      /* last change time */
-#if defined(CONFIG_32BIT) && defined(CONFIG_CPU_LITTLE_ENDIAN)
-        unsigned long   __unused3;
-#endif
-        unsigned long  msg_cbytes;      /* current number of bytes on queue */
-        unsigned long  msg_qnum;        /* number of messages in queue */
-        unsigned long  msg_qbytes;      /* max number of bytes on queue */
-        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
-        __kernel_pid_t msg_lrpid;       /* last receive pid */
-        unsigned long  __unused4;
-        unsigned long  __unused5;
-};
-
-#endif /* _ASM_MSGBUF_H */
diff --git a/include/asm-mips/mutex.h b/include/asm-mips/mutex.h
deleted file mode 100644
index 458c1f7fbc18..000000000000
--- a/include/asm-mips/mutex.h
+++ /dev/null
@@ -1,9 +0,0 @@
-/*
- * Pull in the generic implementation for the mutex fastpath.
- *
- * TODO: implement optimized primitives instead, or leave the generic
- * implementation in place, or pick the atomic_xchg() based generic
- * implementation. (see asm-generic/mutex-xchg.h for details)
- */
-
-#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-mips/nile4.h b/include/asm-mips/nile4.h
deleted file mode 100644
index c3ca959aa4d9..000000000000
--- a/include/asm-mips/nile4.h
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- *  asm-mips/nile4.h -- NEC Vrc-5074 Nile 4 definitions
- *
- *  Copyright (C) 2000 Geert Uytterhoeven <geert@sonycom.com>
- *                     Sony Software Development Center Europe (SDCE), Brussels
- *
- *  This file is based on the following documentation:
- *
- *      NEC Vrc 5074 System Controller Data Sheet, June 1998
- */
-
-#ifndef _ASM_NILE4_H
-#define _ASM_NILE4_H
-
-#define NILE4_BASE              0xbfa00000
-#define NILE4_SIZE              0x00200000              /* 2 MB */
-
-
-    /*
-     *  Physical Device Address Registers (PDARs)
-     */
-
-#define NILE4_SDRAM0    0x0000  /* SDRAM Bank 0 [R/W] */
-#define NILE4_SDRAM1    0x0008  /* SDRAM Bank 1 [R/W] */
-#define NILE4_DCS2      0x0010  /* Device Chip-Select 2 [R/W] */
-#define NILE4_DCS3      0x0018  /* Device Chip-Select 3 [R/W] */
-#define NILE4_DCS4      0x0020  /* Device Chip-Select 4 [R/W] */
-#define NILE4_DCS5      0x0028  /* Device Chip-Select 5 [R/W] */
-#define NILE4_DCS6      0x0030  /* Device Chip-Select 6 [R/W] */
-#define NILE4_DCS7      0x0038  /* Device Chip-Select 7 [R/W] */
-#define NILE4_DCS8      0x0040  /* Device Chip-Select 8 [R/W] */
-#define NILE4_PCIW0     0x0060  /* PCI Address Window 0 [R/W] */
-#define NILE4_PCIW1     0x0068  /* PCI Address Window 1 [R/W] */
-#define NILE4_INTCS     0x0070  /* Controller Internal Registers and Devices */
-                                /* [R/W] */
-#define NILE4_BOOTCS    0x0078  /* Boot ROM Chip-Select [R/W] */
-
-
-    /*
-     *  CPU Interface Registers
-     */
-
-#define NILE4_CPUSTAT   0x0080  /* CPU Status [R/W] */
-#define NILE4_INTCTRL   0x0088  /* Interrupt Control [R/W] */
-#define NILE4_INTSTAT0  0x0090  /* Interrupt Status 0 [R] */
-#define NILE4_INTSTAT1  0x0098  /* Interrupt Status 1 and CPU Interrupt */
-                                /* Enable [R/W] */
-#define NILE4_INTCLR    0x00A0  /* Interrupt Clear [R/W] */
-#define NILE4_INTPPES   0x00A8  /* PCI Interrupt Control [R/W] */
-
-
-    /*
-     *  Memory-Interface Registers
-     */
-
-#define NILE4_MEMCTRL   0x00C0  /* Memory Control */
-#define NILE4_ACSTIME   0x00C8  /* Memory Access Timing [R/W] */
-#define NILE4_CHKERR    0x00D0  /* Memory Check Error Status [R] */
-
-
-    /*
-     *  PCI-Bus Registers
-     */
-
-#define NILE4_PCICTRL   0x00E0  /* PCI Control [R/W] */
-#define NILE4_PCIARB    0x00E8  /* PCI Arbiter [R/W] */
-#define NILE4_PCIINIT0  0x00F0  /* PCI Master (Initiator) 0 [R/W] */
-#define NILE4_PCIINIT1  0x00F8  /* PCI Master (Initiator) 1 [R/W] */
-#define NILE4_PCIERR    0x00B8  /* PCI Error [R/W] */
-
-
-    /*
-     *  Local-Bus Registers
-     */
-
-#define NILE4_LCNFG     0x0100  /* Local Bus Configuration [R/W] */
-#define NILE4_LCST2     0x0110  /* Local Bus Chip-Select Timing 2 [R/W] */
-#define NILE4_LCST3     0x0118  /* Local Bus Chip-Select Timing 3 [R/W] */
-#define NILE4_LCST4     0x0120  /* Local Bus Chip-Select Timing 4 [R/W] */
-#define NILE4_LCST5     0x0128  /* Local Bus Chip-Select Timing 5 [R/W] */
-#define NILE4_LCST6     0x0130  /* Local Bus Chip-Select Timing 6 [R/W] */
-#define NILE4_LCST7     0x0138  /* Local Bus Chip-Select Timing 7 [R/W] */
-#define NILE4_LCST8     0x0140  /* Local Bus Chip-Select Timing 8 [R/W] */
-#define NILE4_DCSFN     0x0150  /* Device Chip-Select Muxing and Output */
-                                /* Enables [R/W] */
-#define NILE4_DCSIO     0x0158  /* Device Chip-Selects As I/O Bits [R/W] */
-#define NILE4_BCST      0x0178  /* Local Boot Chip-Select Timing [R/W] */
-
-
-    /*
-     *  DMA Registers
-     */
-
-#define NILE4_DMACTRL0  0x0180  /* DMA Control 0 [R/W] */
-#define NILE4_DMASRCA0  0x0188  /* DMA Source Address 0 [R/W] */
-#define NILE4_DMADESA0  0x0190  /* DMA Destination Address 0 [R/W] */
-#define NILE4_DMACTRL1  0x0198  /* DMA Control 1 [R/W] */
-#define NILE4_DMASRCA1  0x01A0  /* DMA Source Address 1 [R/W] */
-#define NILE4_DMADESA1  0x01A8  /* DMA Destination Address 1 [R/W] */
-
-
-    /*
-     *  Timer Registers
-     */
-
-#define NILE4_T0CTRL    0x01C0  /* SDRAM Refresh Control [R/W] */
-#define NILE4_T0CNTR    0x01C8  /* SDRAM Refresh Counter [R/W] */
-#define NILE4_T1CTRL    0x01D0  /* CPU-Bus Read Time-Out Control [R/W] */
-#define NILE4_T1CNTR    0x01D8  /* CPU-Bus Read Time-Out Counter [R/W] */
-#define NILE4_T2CTRL    0x01E0  /* General-Purpose Timer Control [R/W] */
-#define NILE4_T2CNTR    0x01E8  /* General-Purpose Timer Counter [R/W] */
-#define NILE4_T3CTRL    0x01F0  /* Watchdog Timer Control [R/W] */
-#define NILE4_T3CNTR    0x01F8  /* Watchdog Timer Counter [R/W] */
-
-
-    /*
-     *  PCI Configuration Space Registers
-     */
-
-#define NILE4_PCI_BASE  0x0200
-
-#define NILE4_VID       0x0200  /* PCI Vendor ID [R] */
-#define NILE4_DID       0x0202  /* PCI Device ID [R] */
-#define NILE4_PCICMD    0x0204  /* PCI Command [R/W] */
-#define NILE4_PCISTS    0x0206  /* PCI Status [R/W] */
-#define NILE4_REVID     0x0208  /* PCI Revision ID [R] */
-#define NILE4_CLASS     0x0209  /* PCI Class Code [R] */
-#define NILE4_CLSIZ     0x020C  /* PCI Cache Line Size [R/W] */
-#define NILE4_MLTIM     0x020D  /* PCI Latency Timer [R/W] */
-#define NILE4_HTYPE     0x020E  /* PCI Header Type [R] */
-#define NILE4_BIST      0x020F  /* BIST [R] (unimplemented) */
-#define NILE4_BARC      0x0210  /* PCI Base Address Register Control [R/W] */
-#define NILE4_BAR0      0x0218  /* PCI Base Address Register 0 [R/W] */
-#define NILE4_BAR1      0x0220  /* PCI Base Address Register 1 [R/W] */
-#define NILE4_CIS       0x0228  /* PCI Cardbus CIS Pointer [R] */
-                                /* (unimplemented) */
-#define NILE4_SSVID     0x022C  /* PCI Sub-System Vendor ID [R/W] */
-#define NILE4_SSID      0x022E  /* PCI Sub-System ID [R/W] */
-#define NILE4_ROM       0x0230  /* Expansion ROM Base Address [R] */
-                                /* (unimplemented) */
-#define NILE4_INTLIN    0x023C  /* PCI Interrupt Line [R/W] */
-#define NILE4_INTPIN    0x023D  /* PCI Interrupt Pin [R] */
-#define NILE4_MINGNT    0x023E  /* PCI Min_Gnt [R] (unimplemented) */
-#define NILE4_MAXLAT    0x023F  /* PCI Max_Lat [R] (unimplemented) */
-#define NILE4_BAR2      0x0240  /* PCI Base Address Register 2 [R/W] */
-#define NILE4_BAR3      0x0248  /* PCI Base Address Register 3 [R/W] */
-#define NILE4_BAR4      0x0250  /* PCI Base Address Register 4 [R/W] */
-#define NILE4_BAR5      0x0258  /* PCI Base Address Register 5 [R/W] */
-#define NILE4_BAR6      0x0260  /* PCI Base Address Register 6 [R/W] */
-#define NILE4_BAR7      0x0268  /* PCI Base Address Register 7 [R/W] */
-#define NILE4_BAR8      0x0270  /* PCI Base Address Register 8 [R/W] */
-#define NILE4_BARB      0x0278  /* PCI Base Address Register BOOT [R/W] */
-
-
-    /*
-     *  Serial-Port Registers
-     */
-
-#define NILE4_UART_BASE 0x0300
-
-#define NILE4_UARTRBR   0x0300  /* UART Receiver Data Buffer [R] */
-#define NILE4_UARTTHR   0x0300  /* UART Transmitter Data Holding [W] */
-#define NILE4_UARTIER   0x0308  /* UART Interrupt Enable [R/W] */
-#define NILE4_UARTDLL   0x0300  /* UART Divisor Latch LSB [R/W] */
-#define NILE4_UARTDLM   0x0308  /* UART Divisor Latch MSB [R/W] */
-#define NILE4_UARTIIR   0x0310  /* UART Interrupt ID [R] */
-#define NILE4_UARTFCR   0x0310  /* UART FIFO Control [W] */
-#define NILE4_UARTLCR   0x0318  /* UART Line Control [R/W] */
-#define NILE4_UARTMCR   0x0320  /* UART Modem Control [R/W] */
-#define NILE4_UARTLSR   0x0328  /* UART Line Status [R/W] */
-#define NILE4_UARTMSR   0x0330  /* UART Modem Status [R/W] */
-#define NILE4_UARTSCR   0x0338  /* UART Scratch [R/W] */
-
-#define NILE4_UART_BASE_BAUD    520833  /* 100 MHz / 12 / 16 */
-
-
-    /*
-     *  Interrupt Lines
-     */
-
-#define NILE4_INT_CPCE  0       /* CPU-Interface Parity-Error Interrupt */
-#define NILE4_INT_CNTD  1       /* CPU No-Target Decode Interrupt */
-#define NILE4_INT_MCE   2       /* Memory-Check Error Interrupt */
-#define NILE4_INT_DMA   3       /* DMA Controller Interrupt */
-#define NILE4_INT_UART  4       /* UART Interrupt */
-#define NILE4_INT_WDOG  5       /* Watchdog Timer Interrupt */
-#define NILE4_INT_GPT   6       /* General-Purpose Timer Interrupt */
-#define NILE4_INT_LBRTD 7       /* Local-Bus Ready Timer Interrupt */
-#define NILE4_INT_INTA  8       /* PCI Interrupt Signal INTA# */
-#define NILE4_INT_INTB  9       /* PCI Interrupt Signal INTB# */
-#define NILE4_INT_INTC  10      /* PCI Interrupt Signal INTC# */
-#define NILE4_INT_INTD  11      /* PCI Interrupt Signal INTD# */
-#define NILE4_INT_INTE  12      /* PCI Interrupt Signal INTE# (ISA cascade) */
-#define NILE4_INT_RESV  13      /* Reserved */
-#define NILE4_INT_PCIS  14      /* PCI SERR# Interrupt */
-#define NILE4_INT_PCIE  15      /* PCI Internal Error Interrupt */
-
-
-    /*
-     *  Nile 4 Register Access
-     */
-
-static inline void nile4_sync(void)
-{
-    volatile u32 *p = (volatile u32 *)0xbfc00000;
-    (void)(*p);
-}
-
-static inline void nile4_out32(u32 offset, u32 val)
-{
-    *(volatile u32 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-
-static inline u32 nile4_in32(u32 offset)
-{
-    u32 val = *(volatile u32 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-
-static inline void nile4_out16(u32 offset, u16 val)
-{
-    *(volatile u16 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-
-static inline u16 nile4_in16(u32 offset)
-{
-    u16 val = *(volatile u16 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-
-static inline void nile4_out8(u32 offset, u8 val)
-{
-    *(volatile u8 *)(NILE4_BASE+offset) = val;
-    nile4_sync();
-}
-
-static inline u8 nile4_in8(u32 offset)
-{
-    u8 val = *(volatile u8 *)(NILE4_BASE+offset);
-    nile4_sync();
-    return val;
-}
-
-
-    /*
-     *  Physical Device Address Registers
-     */
-
-extern void nile4_set_pdar(u32 pdar, u32 phys, u32 size, int width,
-                           int on_memory_bus, int visible);
-
-
-    /*
-     *  PCI Master Registers
-     */
-
-#define NILE4_PCICMD_IACK       0       /* PCI Interrupt Acknowledge */
-#define NILE4_PCICMD_IO         1       /* PCI I/O Space */
-#define NILE4_PCICMD_MEM        3       /* PCI Memory Space */
-#define NILE4_PCICMD_CFG        5       /* PCI Configuration Space */
-
-
-    /*
-     *  PCI Address Spaces
-     *
-     *  Note that these are multiplexed using PCIINIT[01]!
-     */
-
-#define NILE4_PCI_IO_BASE       0xa6000000
-#define NILE4_PCI_MEM_BASE      0xa8000000
-#define NILE4_PCI_CFG_BASE      NILE4_PCI_MEM_BASE
-#define NILE4_PCI_IACK_BASE     NILE4_PCI_IO_BASE
-
-
-extern void nile4_set_pmr(u32 pmr, u32 type, u32 addr);
-
-
-    /*
-     *  Interrupt Programming
-     */
-
-#define NUM_I8259_INTERRUPTS    16
-#define NUM_NILE4_INTERRUPTS    16
-
-#define IRQ_I8259_CASCADE       NILE4_INT_INTE
-#define is_i8259_irq(irq)       ((irq) < NUM_I8259_INTERRUPTS)
-#define nile4_to_irq(n)         ((n)+NUM_I8259_INTERRUPTS)
-#define irq_to_nile4(n)         ((n)-NUM_I8259_INTERRUPTS)
-
-extern void nile4_map_irq(int nile4_irq, int cpu_irq);
-extern void nile4_map_irq_all(int cpu_irq);
-extern void nile4_enable_irq(unsigned int nile4_irq);
-extern void nile4_disable_irq(unsigned int nile4_irq);
-extern void nile4_disable_irq_all(void);
-extern u16 nile4_get_irq_stat(int cpu_irq);
-extern void nile4_enable_irq_output(int cpu_irq);
-extern void nile4_disable_irq_output(int cpu_irq);
-extern void nile4_set_pci_irq_polarity(int pci_irq, int high);
-extern void nile4_set_pci_irq_level_or_edge(int pci_irq, int level);
-extern void nile4_clear_irq(int nile4_irq);
-extern void nile4_clear_irq_mask(u32 mask);
-extern u8 nile4_i8259_iack(void);
-extern void nile4_dump_irq_status(void);        /* Debug */
-
-#endif
-
diff --git a/include/asm-mips/paccess.h b/include/asm-mips/paccess.h
deleted file mode 100644
index c2394f8b0fe1..000000000000
--- a/include/asm-mips/paccess.h
+++ /dev/null
@@ -1,112 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 1999, 2000 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- *
- * Protected memory access.  Used for everything that might take revenge
- * by sending a DBE error like accessing possibly non-existant memory or
- * devices.
- */
-#ifndef _ASM_PACCESS_H
-#define _ASM_PACCESS_H
-
-#include <linux/errno.h>
-
-#ifdef CONFIG_32BIT
-#define __PA_ADDR       ".word"
-#endif
-#ifdef CONFIG_64BIT
-#define __PA_ADDR       ".dword"
-#endif
-
-extern asmlinkage void handle_ibe(void);
-extern asmlinkage void handle_dbe(void);
-
-#define put_dbe(x, ptr) __put_dbe((x), (ptr), sizeof(*(ptr)))
-#define get_dbe(x, ptr) __get_dbe((x), (ptr), sizeof(*(ptr)))
-
-struct __large_pstruct { unsigned long buf[100]; };
-#define __mp(x) (*(struct __large_pstruct *)(x))
-
-#define __get_dbe(x, ptr, size)                                         \
-({                                                                      \
-        long __gu_err;                                                  \
-        __typeof__(*(ptr)) __gu_val;                                    \
-        unsigned long __gu_addr;                                        \
-        __asm__("":"=r" (__gu_val));                                    \
-        __gu_addr = (unsigned long) (ptr);                              \
-        __asm__("":"=r" (__gu_err));                                    \
-        switch (size) {                                                 \
-        case 1: __get_dbe_asm("lb"); break;                             \
-        case 2: __get_dbe_asm("lh"); break;                             \
-        case 4: __get_dbe_asm("lw"); break;                             \
-        case 8:  __get_dbe_asm("ld"); break;                            \
-        default: __get_dbe_unknown(); break;                            \
-        }                                                               \
-        x = (__typeof__(*(ptr))) __gu_val;                              \
-        __gu_err;                                                       \
-})
-
-#define __get_dbe_asm(insn)                                             \
-{                                                                       \
-        __asm__ __volatile__(                                           \
-        "1:\t" insn "\t%1,%2\n\t"                                       \
-        "move\t%0,$0\n"                                                 \
-        "2:\n\t"                                                        \
-        ".section\t.fixup,\"ax\"\n"                                     \
-        "3:\tli\t%0,%3\n\t"                                             \
-        "move\t%1,$0\n\t"                                               \
-        "j\t2b\n\t"                                                     \
-        ".previous\n\t"                                                 \
-        ".section\t__dbe_table,\"a\"\n\t"                               \
-        __PA_ADDR "\t1b, 3b\n\t"                                        \
-        ".previous"                                                     \
-        :"=r" (__gu_err), "=r" (__gu_val)                               \
-        :"o" (__mp(__gu_addr)), "i" (-EFAULT));                         \
-}
-
-extern void __get_dbe_unknown(void);
-
-#define __put_dbe(x, ptr, size)                                         \
-({                                                                      \
-        long __pu_err;                                                  \
-        __typeof__(*(ptr)) __pu_val;                                    \
-        long __pu_addr;                                                 \
-        __pu_val = (x);                                                 \
-        __pu_addr = (long) (ptr);                                       \
-        __asm__("":"=r" (__pu_err));                                    \
-        switch (size) {                                                 \
-        case 1: __put_dbe_asm("sb"); break;                             \
-        case 2: __put_dbe_asm("sh"); break;                             \
-        case 4: __put_dbe_asm("sw"); break;                             \
-        case 8: __put_dbe_asm("sd"); break;                             \
-        default: __put_dbe_unknown(); break;                            \
-        }                                                               \
-        __pu_err;                                                       \
-})
-
-#define __put_dbe_asm(insn)                                             \
-{                                                                       \
-        __asm__ __volatile__(                                           \
-        "1:\t" insn "\t%1,%2\n\t"                                       \
-        "move\t%0,$0\n"                                                 \
-        "2:\n\t"                                                        \
-        ".section\t.fixup,\"ax\"\n"                                     \
-        "3:\tli\t%0,%3\n\t"                                             \
-        "j\t2b\n\t"                                                     \
-        ".previous\n\t"                                                 \
-        ".section\t__dbe_table,\"a\"\n\t"                               \
-        __PA_ADDR "\t1b, 3b\n\t"                                        \
-        ".previous"                                                     \
-        : "=r" (__pu_err)                                               \
-        : "r" (__pu_val), "o" (__mp(__pu_addr)), "i" (-EFAULT));        \
-}
-
-extern void __put_dbe_unknown(void);
-
-extern unsigned long search_dbe_table(unsigned long addr);
-
-#endif /* _ASM_PACCESS_H */
diff --git a/include/asm-mips/page.h b/include/asm-mips/page.h
deleted file mode 100644
index fe7a88ea066e..000000000000
--- a/include/asm-mips/page.h
+++ /dev/null
@@ -1,191 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 1999, 2000, 03 Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PAGE_H
-#define _ASM_PAGE_H
-
-#include <spaces.h>
-
-/*
- * PAGE_SHIFT determines the page size
- */
-#ifdef CONFIG_PAGE_SIZE_4KB
-#define PAGE_SHIFT      12
-#endif
-#ifdef CONFIG_PAGE_SIZE_8KB
-#define PAGE_SHIFT      13
-#endif
-#ifdef CONFIG_PAGE_SIZE_16KB
-#define PAGE_SHIFT      14
-#endif
-#ifdef CONFIG_PAGE_SIZE_64KB
-#define PAGE_SHIFT      16
-#endif
-#define PAGE_SIZE       (1UL << PAGE_SHIFT)
-#define PAGE_MASK       (~((1 << PAGE_SHIFT) - 1))
-
-#ifndef __ASSEMBLY__
-
-#include <linux/pfn.h>
-#include <asm/io.h>
-
-extern void build_clear_page(void);
-extern void build_copy_page(void);
-
-/*
- * It's normally defined only for FLATMEM config but it's
- * used in our early mem init code for all memory models.
- * So always define it.
- */
-#define ARCH_PFN_OFFSET         PFN_UP(PHYS_OFFSET)
-
-extern void clear_page(void * page);
-extern void copy_page(void * to, void * from);
-
-extern unsigned long shm_align_mask;
-
-static inline unsigned long pages_do_alias(unsigned long addr1,
-        unsigned long addr2)
-{
-        return (addr1 ^ addr2) & shm_align_mask;
-}
-
-struct page;
-
-static inline void clear_user_page(void *addr, unsigned long vaddr,
-        struct page *page)
-{
-        extern void (*flush_data_cache_page)(unsigned long addr);
-
-        clear_page(addr);
-        if (pages_do_alias((unsigned long) addr, vaddr & PAGE_MASK))
-                flush_data_cache_page((unsigned long)addr);
-}
-
-extern void copy_user_page(void *vto, void *vfrom, unsigned long vaddr,
-        struct page *to);
-struct vm_area_struct;
-extern void copy_user_highpage(struct page *to, struct page *from,
-        unsigned long vaddr, struct vm_area_struct *vma);
-
-#define __HAVE_ARCH_COPY_USER_HIGHPAGE
-
-/*
- * These are used to make use of C type-checking..
- */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-  #ifdef CONFIG_CPU_MIPS32
-    typedef struct { unsigned long pte_low, pte_high; } pte_t;
-    #define pte_val(x)    ((x).pte_low | ((unsigned long long)(x).pte_high << 32))
-    #define __pte(x)      ({ pte_t __pte = {(x), ((unsigned long long)(x)) >> 32}; __pte; })
-  #else
-     typedef struct { unsigned long long pte; } pte_t;
-     #define pte_val(x) ((x).pte)
-     #define __pte(x)   ((pte_t) { (x) } )
-  #endif
-#else
-typedef struct { unsigned long pte; } pte_t;
-#define pte_val(x)      ((x).pte)
-#define __pte(x)        ((pte_t) { (x) } )
-#endif
-typedef struct page *pgtable_t;
-
-/*
- * For 3-level pagetables we defines these ourselves, for 2-level the
- * definitions are supplied by <asm-generic/pgtable-nopmd.h>.
- */
-#ifdef CONFIG_64BIT
-
-typedef struct { unsigned long pmd; } pmd_t;
-#define pmd_val(x)      ((x).pmd)
-#define __pmd(x)        ((pmd_t) { (x) } )
-
-#endif
-
-/*
- * Right now we don't support 4-level pagetables, so all pud-related
- * definitions come from <asm-generic/pgtable-nopud.h>.
- */
-
-/*
- * Finall the top of the hierarchy, the pgd
- */
-typedef struct { unsigned long pgd; } pgd_t;
-#define pgd_val(x)      ((x).pgd)
-#define __pgd(x)        ((pgd_t) { (x) } )
-
-/*
- * Manipulate page protection bits
- */
-typedef struct { unsigned long pgprot; } pgprot_t;
-#define pgprot_val(x)   ((x).pgprot)
-#define __pgprot(x)     ((pgprot_t) { (x) } )
-
-/*
- * On R4000-style MMUs where a TLB entry is mapping a adjacent even / odd
- * pair of pages we only have a single global bit per pair of pages.  When
- * writing to the TLB make sure we always have the bit set for both pages
- * or none.  This macro is used to access the `buddy' of the pte we're just
- * working on.
- */
-#define ptep_buddy(x)   ((pte_t *)((unsigned long)(x) ^ sizeof(pte_t)))
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * __pa()/__va() should be used only during mem init.
- */
-#ifdef CONFIG_64BIT
-#define __pa(x)                                                         \
-({                                                                      \
-    unsigned long __x = (unsigned long)(x);                             \
-    __x < CKSEG0 ? XPHYSADDR(__x) : CPHYSADDR(__x);                     \
-})
-#else
-#define __pa(x)                                                         \
-    ((unsigned long)(x) - PAGE_OFFSET + PHYS_OFFSET)
-#endif
-#define __va(x)         ((void *)((unsigned long)(x) + PAGE_OFFSET - PHYS_OFFSET))
-#define __pa_symbol(x)  __pa(RELOC_HIDE((unsigned long)(x), 0))
-
-#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
-
-#ifdef CONFIG_FLATMEM
-
-#define pfn_valid(pfn)          ((pfn) >= ARCH_PFN_OFFSET && (pfn) < max_mapnr)
-
-#elif defined(CONFIG_SPARSEMEM)
-
-/* pfn_valid is defined in linux/mmzone.h */
-
-#elif defined(CONFIG_NEED_MULTIPLE_NODES)
-
-#define pfn_valid(pfn)                                                  \
-({                                                                      \
-        unsigned long __pfn = (pfn);                                    \
-        int __n = pfn_to_nid(__pfn);                                    \
-        ((__n >= 0) ? (__pfn < NODE_DATA(__n)->node_start_pfn +         \
-                               NODE_DATA(__n)->node_spanned_pages)      \
-                    : 0);                                               \
-})
-
-#endif
-
-#define virt_to_page(kaddr)     pfn_to_page(PFN_DOWN(virt_to_phys(kaddr)))
-#define virt_addr_valid(kaddr)  pfn_valid(PFN_DOWN(virt_to_phys(kaddr)))
-
-#define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
-                                 VM_MAYREAD | VM_MAYWRITE | VM_MAYEXEC)
-
-#define UNCAC_ADDR(addr)        ((addr) - PAGE_OFFSET + UNCAC_BASE)
-#define CAC_ADDR(addr)          ((addr) - UNCAC_BASE + PAGE_OFFSET)
-
-#include <asm-generic/memory_model.h>
-#include <asm-generic/page.h>
-
-#endif /* _ASM_PAGE_H */
diff --git a/include/asm-mips/param.h b/include/asm-mips/param.h
deleted file mode 100644
index 1d9bb8c5ab24..000000000000
--- a/include/asm-mips/param.h
+++ /dev/null
@@ -1,31 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright 1994 - 2000, 2002 Ralf Baechle (ralf@gnu.org)
- * Copyright 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PARAM_H
-#define _ASM_PARAM_H
-
-#ifdef __KERNEL__
-
-# define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
-# define USER_HZ        100             /* .. some user interfaces are in "ticks" */
-# define CLOCKS_PER_SEC (USER_HZ)       /* like times() */
-#endif
-
-#ifndef HZ
-#define HZ 100
-#endif
-
-#define EXEC_PAGESIZE   65536
-
-#ifndef NOGROUP
-#define NOGROUP         (-1)
-#endif
-
-#define MAXHOSTNAMELEN  64      /* max length of hostname */
-
-#endif /* _ASM_PARAM_H */
diff --git a/include/asm-mips/parport.h b/include/asm-mips/parport.h
deleted file mode 100644
index f52656826cce..000000000000
--- a/include/asm-mips/parport.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * Copyright (C) 1999, 2000  Tim Waugh <tim@cyberelk.demon.co.uk>
- *
- * This file should only be included by drivers/parport/parport_pc.c.
- */
-#ifndef _ASM_PARPORT_H
-#define _ASM_PARPORT_H
-
-static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
-static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
-{
-        return parport_pc_find_isa_ports(autoirq, autodma);
-}
-
-#endif /* _ASM_PARPORT_H */
diff --git a/include/asm-mips/pci.h b/include/asm-mips/pci.h
deleted file mode 100644
index 5510c53b7feb..000000000000
--- a/include/asm-mips/pci.h
+++ /dev/null
@@ -1,179 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _ASM_PCI_H
-#define _ASM_PCI_H
-
-#include <linux/mm.h>
-
-#ifdef __KERNEL__
-
-/*
- * This file essentially defines the interface between board
- * specific PCI code and MIPS common PCI code.  Should potentially put
- * into include/asm/pci.h file.
- */
-
-#include <linux/ioport.h>
-
-/*
- * Each pci channel is a top-level PCI bus seem by CPU.  A machine  with
- * multiple PCI channels may have multiple PCI host controllers or a
- * single controller supporting multiple channels.
- */
-struct pci_controller {
-        struct pci_controller *next;
-        struct pci_bus *bus;
-
-        struct pci_ops *pci_ops;
-        struct resource *mem_resource;
-        unsigned long mem_offset;
-        struct resource *io_resource;
-        unsigned long io_offset;
-        unsigned long io_map_base;
-
-        unsigned int index;
-        /* For compatibility with current (as of July 2003) pciutils
-           and XFree86. Eventually will be removed. */
-        unsigned int need_domain_info;
-
-        int iommu;
-
-        /* Optional access methods for reading/writing the bus number
-           of the PCI controller */
-        int (*get_busno)(void);
-        void (*set_busno)(int busno);
-};
-
-/*
- * Used by boards to register their PCI busses before the actual scanning.
- */
-extern struct pci_controller * alloc_pci_controller(void);
-extern void register_pci_controller(struct pci_controller *hose);
-
-/*
- * board supplied pci irq fixup routine
- */
-extern int pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-
-/* Can be used to override the logic in pci_scan_bus for skipping
-   already-configured bus numbers - to be used for buggy BIOSes
-   or architectures with incomplete PCI setup by the loader */
-
-extern unsigned int pcibios_assign_all_busses(void);
-
-#define pcibios_scan_all_fns(a, b)      0
-
-extern unsigned long PCIBIOS_MIN_IO;
-extern unsigned long PCIBIOS_MIN_MEM;
-
-#define PCIBIOS_MIN_CARDBUS_IO  0x4000
-
-extern void pcibios_set_master(struct pci_dev *dev);
-
-static inline void pcibios_penalize_isa_irq(int irq, int active)
-{
-        /* We don't do dynamic PCI IRQ allocation */
-}
-
-/*
- * Dynamic DMA mapping stuff.
- * MIPS has everything mapped statically.
- */
-
-#include <linux/types.h>
-#include <linux/slab.h>
-#include <asm/scatterlist.h>
-#include <linux/string.h>
-#include <asm/io.h>
-
-struct pci_dev;
-
-/*
- * The PCI address space does equal the physical memory address space.  The
- * networking and block device layers use this boolean for bounce buffer
- * decisions.  This is set if any hose does not have an IOMMU.
- */
-extern unsigned int PCI_DMA_BUS_IS_PHYS;
-
-#ifdef CONFIG_DMA_NEED_PCI_MAP_STATE
-
-/* pci_unmap_{single,page} is not a nop, thus... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)       dma_addr_t ADDR_NAME;
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)         __u32 LEN_NAME;
-#define pci_unmap_addr(PTR, ADDR_NAME)          ((PTR)->ADDR_NAME)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) (((PTR)->ADDR_NAME) = (VAL))
-#define pci_unmap_len(PTR, LEN_NAME)            ((PTR)->LEN_NAME)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   (((PTR)->LEN_NAME) = (VAL))
-
-#else /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
-
-/* pci_unmap_{page,single} is a nop so... */
-#define DECLARE_PCI_UNMAP_ADDR(ADDR_NAME)
-#define DECLARE_PCI_UNMAP_LEN(LEN_NAME)
-#define pci_unmap_addr(PTR, ADDR_NAME)          (0)
-#define pci_unmap_addr_set(PTR, ADDR_NAME, VAL) do { } while (0)
-#define pci_unmap_len(PTR, LEN_NAME)            (0)
-#define pci_unmap_len_set(PTR, LEN_NAME, VAL)   do { } while (0)
-
-#endif /* CONFIG_DMA_NEED_PCI_MAP_STATE  */
-
-#ifdef CONFIG_PCI
-static inline void pci_dma_burst_advice(struct pci_dev *pdev,
-                                        enum pci_dma_burst_strategy *strat,
-                                        unsigned long *strategy_parameter)
-{
-        *strat = PCI_DMA_BURST_INFINITY;
-        *strategy_parameter = ~0UL;
-}
-#endif
-
-extern void pcibios_resource_to_bus(struct pci_dev *dev,
-        struct pci_bus_region *region, struct resource *res);
-
-extern void pcibios_bus_to_resource(struct pci_dev *dev, struct resource *res,
-                                    struct pci_bus_region *region);
-
-static inline struct resource *
-pcibios_select_root(struct pci_dev *pdev, struct resource *res)
-{
-        struct resource *root = NULL;
-
-        if (res->flags & IORESOURCE_IO)
-                root = &ioport_resource;
-        if (res->flags & IORESOURCE_MEM)
-                root = &iomem_resource;
-
-        return root;
-}
-
-#define pci_domain_nr(bus) ((struct pci_controller *)(bus)->sysdata)->index
-
-static inline int pci_proc_domain(struct pci_bus *bus)
-{
-        struct pci_controller *hose = bus->sysdata;
-        return hose->need_domain_info;
-}
-
-#endif /* __KERNEL__ */
-
-/* implement the pci_ DMA API in terms of the generic device dma_ one */
-#include <asm-generic/pci-dma-compat.h>
-
-/* Do platform specific device initialization at pci_enable_device() time */
-extern int pcibios_plat_dev_init(struct pci_dev *dev);
-
-/* Chances are this interrupt is wired PC-style ...  */
-static inline int pci_get_legacy_ide_irq(struct pci_dev *dev, int channel)
-{
-        return channel ? 15 : 14;
-}
-
-extern int pci_probe_only;
-
-extern char * (*pcibios_plat_setup)(char *str);
-
-#endif /* _ASM_PCI_H */
diff --git a/include/asm-mips/pci/bridge.h b/include/asm-mips/pci/bridge.h
deleted file mode 100644
index 5f4b9d4e4114..000000000000
--- a/include/asm-mips/pci/bridge.h
+++ /dev/null
@@ -1,854 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * bridge.h - bridge chip header file, derived from IRIX <sys/PCI/bridge.h>,
- * revision 1.76.
- *
- * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_PCI_BRIDGE_H
-#define _ASM_PCI_BRIDGE_H
-
-#include <linux/types.h>
-#include <linux/pci.h>
-#include <asm/xtalk/xwidget.h>          /* generic widget header */
-#include <asm/sn/types.h>
-
-/* I/O page size */
-
-#define IOPFNSHIFT              12      /* 4K per mapped page */
-
-#define IOPGSIZE                (1 << IOPFNSHIFT)
-#define IOPG(x)                 ((x) >> IOPFNSHIFT)
-#define IOPGOFF(x)              ((x) & (IOPGSIZE-1))
-
-/* Bridge RAM sizes */
-
-#define BRIDGE_ATE_RAM_SIZE     0x00000400      /* 1kB ATE RAM */
-
-#define BRIDGE_CONFIG_BASE      0x20000
-#define BRIDGE_CONFIG1_BASE     0x28000
-#define BRIDGE_CONFIG_END       0x30000
-#define BRIDGE_CONFIG_SLOT_SIZE 0x1000
-
-#define BRIDGE_SSRAM_512K       0x00080000      /* 512kB */
-#define BRIDGE_SSRAM_128K       0x00020000      /* 128kB */
-#define BRIDGE_SSRAM_64K        0x00010000      /* 64kB */
-#define BRIDGE_SSRAM_0K         0x00000000      /* 0kB */
-
-/* ========================================================================
- *    Bridge address map
- */
-
-#ifndef __ASSEMBLY__
-
-/*
- * All accesses to bridge hardware registers must be done
- * using 32-bit loads and stores.
- */
-typedef u32     bridgereg_t;
-
-typedef u64     bridge_ate_t;
-
-/* pointers to bridge ATEs
- * are always "pointer to volatile"
- */
-typedef volatile bridge_ate_t  *bridge_ate_p;
-
-/*
- * It is generally preferred that hardware registers on the bridge
- * are located from C code via this structure.
- *
- * Generated from Bridge spec dated 04oct95
- */
-
-typedef volatile struct bridge_s {
-        /* Local Registers                             0x000000-0x00FFFF */
-
-        /* standard widget configuration               0x000000-0x000057 */
-        widget_cfg_t        b_widget;                   /* 0x000000 */
-
-        /* helper fieldnames for accessing bridge widget */
-
-#define b_wid_id                        b_widget.w_id
-#define b_wid_stat                      b_widget.w_status
-#define b_wid_err_upper                 b_widget.w_err_upper_addr
-#define b_wid_err_lower                 b_widget.w_err_lower_addr
-#define b_wid_control                   b_widget.w_control
-#define b_wid_req_timeout               b_widget.w_req_timeout
-#define b_wid_int_upper                 b_widget.w_intdest_upper_addr
-#define b_wid_int_lower                 b_widget.w_intdest_lower_addr
-#define b_wid_err_cmdword               b_widget.w_err_cmd_word
-#define b_wid_llp                       b_widget.w_llp_cfg
-#define b_wid_tflush                    b_widget.w_tflush
-
-        /* bridge-specific widget configuration 0x000058-0x00007F */
-        bridgereg_t         _pad_000058;
-        bridgereg_t         b_wid_aux_err;              /* 0x00005C */
-        bridgereg_t         _pad_000060;
-        bridgereg_t         b_wid_resp_upper;           /* 0x000064 */
-        bridgereg_t         _pad_000068;
-        bridgereg_t         b_wid_resp_lower;           /* 0x00006C */
-        bridgereg_t         _pad_000070;
-        bridgereg_t         b_wid_tst_pin_ctrl;         /* 0x000074 */
-        bridgereg_t     _pad_000078[2];
-
-        /* PMU & Map 0x000080-0x00008F */
-        bridgereg_t     _pad_000080;
-        bridgereg_t     b_dir_map;                      /* 0x000084 */
-        bridgereg_t     _pad_000088[2];
-
-        /* SSRAM 0x000090-0x00009F */
-        bridgereg_t     _pad_000090;
-        bridgereg_t     b_ram_perr;                     /* 0x000094 */
-        bridgereg_t     _pad_000098[2];
-
-        /* Arbitration 0x0000A0-0x0000AF */
-        bridgereg_t     _pad_0000A0;
-        bridgereg_t     b_arb;                          /* 0x0000A4 */
-        bridgereg_t     _pad_0000A8[2];
-
-        /* Number In A Can 0x0000B0-0x0000BF */
-        bridgereg_t     _pad_0000B0;
-        bridgereg_t     b_nic;                          /* 0x0000B4 */
-        bridgereg_t     _pad_0000B8[2];
-
-        /* PCI/GIO 0x0000C0-0x0000FF */
-        bridgereg_t     _pad_0000C0;
-        bridgereg_t     b_bus_timeout;                  /* 0x0000C4 */
-#define b_pci_bus_timeout b_bus_timeout
-
-        bridgereg_t     _pad_0000C8;
-        bridgereg_t     b_pci_cfg;                      /* 0x0000CC */
-        bridgereg_t     _pad_0000D0;
-        bridgereg_t     b_pci_err_upper;                /* 0x0000D4 */
-        bridgereg_t     _pad_0000D8;
-        bridgereg_t     b_pci_err_lower;                /* 0x0000DC */
-        bridgereg_t     _pad_0000E0[8];
-#define b_gio_err_lower b_pci_err_lower
-#define b_gio_err_upper b_pci_err_upper
-
-        /* Interrupt 0x000100-0x0001FF */
-        bridgereg_t     _pad_000100;
-        bridgereg_t     b_int_status;                   /* 0x000104 */
-        bridgereg_t     _pad_000108;
-        bridgereg_t     b_int_enable;                   /* 0x00010C */
-        bridgereg_t     _pad_000110;
-        bridgereg_t     b_int_rst_stat;                 /* 0x000114 */
-        bridgereg_t     _pad_000118;
-        bridgereg_t     b_int_mode;                     /* 0x00011C */
-        bridgereg_t     _pad_000120;
-        bridgereg_t     b_int_device;                   /* 0x000124 */
-        bridgereg_t     _pad_000128;
-        bridgereg_t     b_int_host_err;                 /* 0x00012C */
-
-        struct {
-                bridgereg_t     __pad;                  /* 0x0001{30,,,68} */
-                bridgereg_t     addr;                   /* 0x0001{34,,,6C} */
-        } b_int_addr[8];                                /* 0x000130 */
-
-        bridgereg_t     _pad_000170[36];
-
-        /* Device 0x000200-0x0003FF */
-        struct {
-                bridgereg_t     __pad;                  /* 0x0002{00,,,38} */
-                bridgereg_t     reg;                    /* 0x0002{04,,,3C} */
-        } b_device[8];                                  /* 0x000200 */
-
-        struct {
-                bridgereg_t     __pad;                  /* 0x0002{40,,,78} */
-                bridgereg_t     reg;                    /* 0x0002{44,,,7C} */
-        } b_wr_req_buf[8];                              /* 0x000240 */
-
-        struct {
-                bridgereg_t     __pad;                  /* 0x0002{80,,,88} */
-                bridgereg_t     reg;                    /* 0x0002{84,,,8C} */
-        } b_rrb_map[2];                                 /* 0x000280 */
-#define b_even_resp     b_rrb_map[0].reg                /* 0x000284 */
-#define b_odd_resp      b_rrb_map[1].reg                /* 0x00028C */
-
-        bridgereg_t     _pad_000290;
-        bridgereg_t     b_resp_status;                  /* 0x000294 */
-        bridgereg_t     _pad_000298;
-        bridgereg_t     b_resp_clear;                   /* 0x00029C */
-
-        bridgereg_t     _pad_0002A0[24];
-
-        char            _pad_000300[0x10000 - 0x000300];
-
-        /* Internal Address Translation Entry RAM 0x010000-0x0103FF */
-        union {
-                bridge_ate_t    wr;                     /* write-only */
-                struct {
-                        bridgereg_t     _p_pad;
-                        bridgereg_t     rd;             /* read-only */
-                }                       hi;
-        }                           b_int_ate_ram[128];
-
-        char    _pad_010400[0x11000 - 0x010400];
-
-        /* Internal Address Translation Entry RAM LOW 0x011000-0x0113FF */
-        struct {
-                bridgereg_t     _p_pad;
-                bridgereg_t     rd;             /* read-only */
-        } b_int_ate_ram_lo[128];
-
-        char    _pad_011400[0x20000 - 0x011400];
-
-        /* PCI Device Configuration Spaces 0x020000-0x027FFF */
-        union {                         /* make all access sizes available. */
-                u8      c[0x1000 / 1];
-                u16     s[0x1000 / 2];
-                u32     l[0x1000 / 4];
-                u64     d[0x1000 / 8];
-                union {
-                        u8      c[0x100 / 1];
-                        u16     s[0x100 / 2];
-                        u32     l[0x100 / 4];
-                        u64     d[0x100 / 8];
-                } f[8];
-        } b_type0_cfg_dev[8];                                   /* 0x020000 */
-
-    /* PCI Type 1 Configuration Space 0x028000-0x028FFF */
-        union {                         /* make all access sizes available. */
-                u8      c[0x1000 / 1];
-                u16     s[0x1000 / 2];
-                u32     l[0x1000 / 4];
-                u64     d[0x1000 / 8];
-        } b_type1_cfg;                                  /* 0x028000-0x029000 */
-
-        char    _pad_029000[0x007000];                  /* 0x029000-0x030000 */
-
-        /* PCI Interrupt Acknowledge Cycle 0x030000 */
-        union {
-                u8      c[8 / 1];
-                u16     s[8 / 2];
-                u32     l[8 / 4];
-                u64     d[8 / 8];
-        } b_pci_iack;                                           /* 0x030000 */
-
-        u8      _pad_030007[0x04fff8];                  /* 0x030008-0x07FFFF */
-
-        /* External Address Translation Entry RAM 0x080000-0x0FFFFF */
-        bridge_ate_t    b_ext_ate_ram[0x10000];
-
-        /* Reserved 0x100000-0x1FFFFF */
-        char    _pad_100000[0x200000-0x100000];
-
-        /* PCI/GIO Device Spaces 0x200000-0xBFFFFF */
-        union {                         /* make all access sizes available. */
-                u8      c[0x100000 / 1];
-                u16     s[0x100000 / 2];
-                u32     l[0x100000 / 4];
-                u64     d[0x100000 / 8];
-        } b_devio_raw[10];                              /* 0x200000 */
-
-        /* b_devio macro is a bit strange; it reflects the
-         * fact that the Bridge ASIC provides 2M for the
-         * first two DevIO windows and 1M for the other six.
-         */
-#define b_devio(n)      b_devio_raw[((n)<2)?(n*2):(n+2)]
-
-        /* External Flash Proms 1,0 0xC00000-0xFFFFFF */
-        union {         /* make all access sizes available. */
-                u8      c[0x400000 / 1];        /* read-only */
-                u16     s[0x400000 / 2];        /* read-write */
-                u32     l[0x400000 / 4];        /* read-only */
-                u64     d[0x400000 / 8];        /* read-only */
-        } b_external_flash;                     /* 0xC00000 */
-} bridge_t;
-
-/*
- * Field formats for Error Command Word and Auxillary Error Command Word
- * of bridge.
- */
-typedef struct bridge_err_cmdword_s {
-        union {
-                u32             cmd_word;
-                struct {
-                        u32     didn:4,         /* Destination ID */
-                                sidn:4,         /* Source ID      */
-                                pactyp:4,       /* Packet type    */
-                                tnum:5,         /* Trans Number   */
-                                coh:1,          /* Coh Transacti  */
-                                ds:2,           /* Data size      */
-                                gbr:1,          /* GBR enable     */
-                                vbpm:1,         /* VBPM message   */
-                                error:1,        /* Error occurred  */
-                                barr:1,         /* Barrier op     */
-                                rsvd:8;
-                } berr_st;
-        } berr_un;
-} bridge_err_cmdword_t;
-
-#define berr_field      berr_un.berr_st
-#endif /* !__ASSEMBLY__ */
-
-/*
- * The values of these macros can and should be crosschecked
- * regularly against the offsets of the like-named fields
- * within the "bridge_t" structure above.
- */
-
-/* Byte offset macros for Bridge internal registers */
-
-#define BRIDGE_WID_ID           WIDGET_ID
-#define BRIDGE_WID_STAT         WIDGET_STATUS
-#define BRIDGE_WID_ERR_UPPER    WIDGET_ERR_UPPER_ADDR
-#define BRIDGE_WID_ERR_LOWER    WIDGET_ERR_LOWER_ADDR
-#define BRIDGE_WID_CONTROL      WIDGET_CONTROL
-#define BRIDGE_WID_REQ_TIMEOUT  WIDGET_REQ_TIMEOUT
-#define BRIDGE_WID_INT_UPPER    WIDGET_INTDEST_UPPER_ADDR
-#define BRIDGE_WID_INT_LOWER    WIDGET_INTDEST_LOWER_ADDR
-#define BRIDGE_WID_ERR_CMDWORD  WIDGET_ERR_CMD_WORD
-#define BRIDGE_WID_LLP          WIDGET_LLP_CFG
-#define BRIDGE_WID_TFLUSH       WIDGET_TFLUSH
-
-#define BRIDGE_WID_AUX_ERR      0x00005C        /* Aux Error Command Word */
-#define BRIDGE_WID_RESP_UPPER   0x000064        /* Response Buf Upper Addr */
-#define BRIDGE_WID_RESP_LOWER   0x00006C        /* Response Buf Lower Addr */
-#define BRIDGE_WID_TST_PIN_CTRL 0x000074        /* Test pin control */
-
-#define BRIDGE_DIR_MAP          0x000084        /* Direct Map reg */
-
-#define BRIDGE_RAM_PERR         0x000094        /* SSRAM Parity Error */
-
-#define BRIDGE_ARB              0x0000A4        /* Arbitration Priority reg */
-
-#define BRIDGE_NIC              0x0000B4        /* Number In A Can */
-
-#define BRIDGE_BUS_TIMEOUT      0x0000C4        /* Bus Timeout Register */
-#define BRIDGE_PCI_BUS_TIMEOUT  BRIDGE_BUS_TIMEOUT
-#define BRIDGE_PCI_CFG          0x0000CC        /* PCI Type 1 Config reg */
-#define BRIDGE_PCI_ERR_UPPER    0x0000D4        /* PCI error Upper Addr */
-#define BRIDGE_PCI_ERR_LOWER    0x0000DC        /* PCI error Lower Addr */
-
-#define BRIDGE_INT_STATUS       0x000104        /* Interrupt Status */
-#define BRIDGE_INT_ENABLE       0x00010C        /* Interrupt Enables */
-#define BRIDGE_INT_RST_STAT     0x000114        /* Reset Intr Status */
-#define BRIDGE_INT_MODE         0x00011C        /* Interrupt Mode */
-#define BRIDGE_INT_DEVICE       0x000124        /* Interrupt Device */
-#define BRIDGE_INT_HOST_ERR     0x00012C        /* Host Error Field */
-
-#define BRIDGE_INT_ADDR0        0x000134        /* Host Address Reg */
-#define BRIDGE_INT_ADDR_OFF     0x000008        /* Host Addr offset (1..7) */
-#define BRIDGE_INT_ADDR(x)      (BRIDGE_INT_ADDR0+(x)*BRIDGE_INT_ADDR_OFF)
-
-#define BRIDGE_DEVICE0          0x000204        /* Device 0 */
-#define BRIDGE_DEVICE_OFF       0x000008        /* Device offset (1..7) */
-#define BRIDGE_DEVICE(x)        (BRIDGE_DEVICE0+(x)*BRIDGE_DEVICE_OFF)
-
-#define BRIDGE_WR_REQ_BUF0      0x000244        /* Write Request Buffer 0 */
-#define BRIDGE_WR_REQ_BUF_OFF   0x000008        /* Buffer Offset (1..7) */
-#define BRIDGE_WR_REQ_BUF(x)    (BRIDGE_WR_REQ_BUF0+(x)*BRIDGE_WR_REQ_BUF_OFF)
-
-#define BRIDGE_EVEN_RESP        0x000284        /* Even Device Response Buf */
-#define BRIDGE_ODD_RESP         0x00028C        /* Odd Device Response Buf */
-
-#define BRIDGE_RESP_STATUS      0x000294        /* Read Response Status reg */
-#define BRIDGE_RESP_CLEAR       0x00029C        /* Read Response Clear reg */
-
-/* Byte offset macros for Bridge I/O space */
-
-#define BRIDGE_ATE_RAM          0x00010000      /* Internal Addr Xlat Ram */
-
-#define BRIDGE_TYPE0_CFG_DEV0   0x00020000      /* Type 0 Cfg, Device 0 */
-#define BRIDGE_TYPE0_CFG_SLOT_OFF       0x00001000      /* Type 0 Cfg Slot Offset (1..7) */
-#define BRIDGE_TYPE0_CFG_FUNC_OFF       0x00000100      /* Type 0 Cfg Func Offset (1..7) */
-#define BRIDGE_TYPE0_CFG_DEV(s)         (BRIDGE_TYPE0_CFG_DEV0+\
-                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF)
-#define BRIDGE_TYPE0_CFG_DEVF(s, f)     (BRIDGE_TYPE0_CFG_DEV0+\
-                                         (s)*BRIDGE_TYPE0_CFG_SLOT_OFF+\
-                                         (f)*BRIDGE_TYPE0_CFG_FUNC_OFF)
-
-#define BRIDGE_TYPE1_CFG        0x00028000      /* Type 1 Cfg space */
-
-#define BRIDGE_PCI_IACK         0x00030000      /* PCI Interrupt Ack */
-#define BRIDGE_EXT_SSRAM        0x00080000      /* Extern SSRAM (ATE) */
-
-/* Byte offset macros for Bridge device IO spaces */
-
-#define BRIDGE_DEV_CNT          8       /* Up to 8 devices per bridge */
-#define BRIDGE_DEVIO0           0x00200000      /* Device IO 0 Addr */
-#define BRIDGE_DEVIO1           0x00400000      /* Device IO 1 Addr */
-#define BRIDGE_DEVIO2           0x00600000      /* Device IO 2 Addr */
-#define BRIDGE_DEVIO_OFF        0x00100000      /* Device IO Offset (3..7) */
-
-#define BRIDGE_DEVIO_2MB        0x00200000      /* Device IO Offset (0..1) */
-#define BRIDGE_DEVIO_1MB        0x00100000      /* Device IO Offset (2..7) */
-
-#define BRIDGE_DEVIO(x)         ((x)<=1 ? BRIDGE_DEVIO0+(x)*BRIDGE_DEVIO_2MB : BRIDGE_DEVIO2+((x)-2)*BRIDGE_DEVIO_1MB)
-
-#define BRIDGE_EXTERNAL_FLASH   0x00C00000      /* External Flash PROMS */
-
-/* ========================================================================
- *    Bridge register bit field definitions
- */
-
-/* Widget part number of bridge */
-#define BRIDGE_WIDGET_PART_NUM          0xc002
-#define XBRIDGE_WIDGET_PART_NUM         0xd002
-
-/* Manufacturer of bridge */
-#define BRIDGE_WIDGET_MFGR_NUM          0x036
-#define XBRIDGE_WIDGET_MFGR_NUM         0x024
-
-/* Revision numbers for known Bridge revisions */
-#define BRIDGE_REV_A                    0x1
-#define BRIDGE_REV_B                    0x2
-#define BRIDGE_REV_C                    0x3
-#define BRIDGE_REV_D                    0x4
-
-/* Bridge widget status register bits definition */
-
-#define BRIDGE_STAT_LLP_REC_CNT         (0xFFu << 24)
-#define BRIDGE_STAT_LLP_TX_CNT          (0xFF << 16)
-#define BRIDGE_STAT_FLASH_SELECT        (0x1 << 6)
-#define BRIDGE_STAT_PCI_GIO_N           (0x1 << 5)
-#define BRIDGE_STAT_PENDING             (0x1F << 0)
-
-/* Bridge widget control register bits definition */
-#define BRIDGE_CTRL_FLASH_WR_EN         (0x1ul << 31)
-#define BRIDGE_CTRL_EN_CLK50            (0x1 << 30)
-#define BRIDGE_CTRL_EN_CLK40            (0x1 << 29)
-#define BRIDGE_CTRL_EN_CLK33            (0x1 << 28)
-#define BRIDGE_CTRL_RST(n)              ((n) << 24)
-#define BRIDGE_CTRL_RST_MASK            (BRIDGE_CTRL_RST(0xF))
-#define BRIDGE_CTRL_RST_PIN(x)          (BRIDGE_CTRL_RST(0x1 << (x)))
-#define BRIDGE_CTRL_IO_SWAP             (0x1 << 23)
-#define BRIDGE_CTRL_MEM_SWAP            (0x1 << 22)
-#define BRIDGE_CTRL_PAGE_SIZE           (0x1 << 21)
-#define BRIDGE_CTRL_SS_PAR_BAD          (0x1 << 20)
-#define BRIDGE_CTRL_SS_PAR_EN           (0x1 << 19)
-#define BRIDGE_CTRL_SSRAM_SIZE(n)       ((n) << 17)
-#define BRIDGE_CTRL_SSRAM_SIZE_MASK     (BRIDGE_CTRL_SSRAM_SIZE(0x3))
-#define BRIDGE_CTRL_SSRAM_512K          (BRIDGE_CTRL_SSRAM_SIZE(0x3))
-#define BRIDGE_CTRL_SSRAM_128K          (BRIDGE_CTRL_SSRAM_SIZE(0x2))
-#define BRIDGE_CTRL_SSRAM_64K           (BRIDGE_CTRL_SSRAM_SIZE(0x1))
-#define BRIDGE_CTRL_SSRAM_1K            (BRIDGE_CTRL_SSRAM_SIZE(0x0))
-#define BRIDGE_CTRL_F_BAD_PKT           (0x1 << 16)
-#define BRIDGE_CTRL_LLP_XBAR_CRD(n)     ((n) << 12)
-#define BRIDGE_CTRL_LLP_XBAR_CRD_MASK   (BRIDGE_CTRL_LLP_XBAR_CRD(0xf))
-#define BRIDGE_CTRL_CLR_RLLP_CNT        (0x1 << 11)
-#define BRIDGE_CTRL_CLR_TLLP_CNT        (0x1 << 10)
-#define BRIDGE_CTRL_SYS_END             (0x1 << 9)
-#define BRIDGE_CTRL_MAX_TRANS(n)        ((n) << 4)
-#define BRIDGE_CTRL_MAX_TRANS_MASK      (BRIDGE_CTRL_MAX_TRANS(0x1f))
-#define BRIDGE_CTRL_WIDGET_ID(n)        ((n) << 0)
-#define BRIDGE_CTRL_WIDGET_ID_MASK      (BRIDGE_CTRL_WIDGET_ID(0xf))
-
-/* Bridge Response buffer Error Upper Register bit fields definition */
-#define BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT (20)
-#define BRIDGE_RESP_ERRUPPR_DEVNUM_MASK (0x7 << BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
-#define BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT (16)
-#define BRIDGE_RESP_ERRUPPR_BUFNUM_MASK (0xF << BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
-#define BRIDGE_RESP_ERRRUPPR_BUFMASK    (0xFFFF)
-
-#define BRIDGE_RESP_ERRUPPR_BUFNUM(x)   \
-                        (((x) & BRIDGE_RESP_ERRUPPR_BUFNUM_MASK) >> \
-                                BRIDGE_RESP_ERRUPPR_BUFNUM_SHFT)
-
-#define BRIDGE_RESP_ERRUPPR_DEVICE(x)   \
-                        (((x) &  BRIDGE_RESP_ERRUPPR_DEVNUM_MASK) >> \
-                                 BRIDGE_RESP_ERRUPPR_DEVNUM_SHFT)
-
-/* Bridge direct mapping register bits definition */
-#define BRIDGE_DIRMAP_W_ID_SHFT         20
-#define BRIDGE_DIRMAP_W_ID              (0xf << BRIDGE_DIRMAP_W_ID_SHFT)
-#define BRIDGE_DIRMAP_RMF_64            (0x1 << 18)
-#define BRIDGE_DIRMAP_ADD512            (0x1 << 17)
-#define BRIDGE_DIRMAP_OFF               (0x1ffff << 0)
-#define BRIDGE_DIRMAP_OFF_ADDRSHFT      (31)    /* lsbit of DIRMAP_OFF is xtalk address bit 31 */
-
-/* Bridge Arbitration register bits definition */
-#define BRIDGE_ARB_REQ_WAIT_TICK(x)     ((x) << 16)
-#define BRIDGE_ARB_REQ_WAIT_TICK_MASK   BRIDGE_ARB_REQ_WAIT_TICK(0x3)
-#define BRIDGE_ARB_REQ_WAIT_EN(x)       ((x) << 8)
-#define BRIDGE_ARB_REQ_WAIT_EN_MASK     BRIDGE_ARB_REQ_WAIT_EN(0xff)
-#define BRIDGE_ARB_FREEZE_GNT           (1 << 6)
-#define BRIDGE_ARB_HPRI_RING_B2         (1 << 5)
-#define BRIDGE_ARB_HPRI_RING_B1         (1 << 4)
-#define BRIDGE_ARB_HPRI_RING_B0         (1 << 3)
-#define BRIDGE_ARB_LPRI_RING_B2         (1 << 2)
-#define BRIDGE_ARB_LPRI_RING_B1         (1 << 1)
-#define BRIDGE_ARB_LPRI_RING_B0         (1 << 0)
-
-/* Bridge Bus time-out register bits definition */
-#define BRIDGE_BUS_PCI_RETRY_HLD(x)     ((x) << 16)
-#define BRIDGE_BUS_PCI_RETRY_HLD_MASK   BRIDGE_BUS_PCI_RETRY_HLD(0x1f)
-#define BRIDGE_BUS_GIO_TIMEOUT          (1 << 12)
-#define BRIDGE_BUS_PCI_RETRY_CNT(x)     ((x) << 0)
-#define BRIDGE_BUS_PCI_RETRY_MASK       BRIDGE_BUS_PCI_RETRY_CNT(0x3ff)
-
-/* Bridge interrupt status register bits definition */
-#define BRIDGE_ISR_MULTI_ERR            (0x1u << 31)
-#define BRIDGE_ISR_PMU_ESIZE_FAULT      (0x1 << 30)
-#define BRIDGE_ISR_UNEXP_RESP           (0x1 << 29)
-#define BRIDGE_ISR_BAD_XRESP_PKT        (0x1 << 28)
-#define BRIDGE_ISR_BAD_XREQ_PKT         (0x1 << 27)
-#define BRIDGE_ISR_RESP_XTLK_ERR        (0x1 << 26)
-#define BRIDGE_ISR_REQ_XTLK_ERR         (0x1 << 25)
-#define BRIDGE_ISR_INVLD_ADDR           (0x1 << 24)
-#define BRIDGE_ISR_UNSUPPORTED_XOP      (0x1 << 23)
-#define BRIDGE_ISR_XREQ_FIFO_OFLOW      (0x1 << 22)
-#define BRIDGE_ISR_LLP_REC_SNERR        (0x1 << 21)
-#define BRIDGE_ISR_LLP_REC_CBERR        (0x1 << 20)
-#define BRIDGE_ISR_LLP_RCTY             (0x1 << 19)
-#define BRIDGE_ISR_LLP_TX_RETRY         (0x1 << 18)
-#define BRIDGE_ISR_LLP_TCTY             (0x1 << 17)
-#define BRIDGE_ISR_SSRAM_PERR           (0x1 << 16)
-#define BRIDGE_ISR_PCI_ABORT            (0x1 << 15)
-#define BRIDGE_ISR_PCI_PARITY           (0x1 << 14)
-#define BRIDGE_ISR_PCI_SERR             (0x1 << 13)
-#define BRIDGE_ISR_PCI_PERR             (0x1 << 12)
-#define BRIDGE_ISR_PCI_MST_TIMEOUT      (0x1 << 11)
-#define BRIDGE_ISR_GIO_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
-#define BRIDGE_ISR_PCI_RETRY_CNT        (0x1 << 10)
-#define BRIDGE_ISR_XREAD_REQ_TIMEOUT    (0x1 << 9)
-#define BRIDGE_ISR_GIO_B_ENBL_ERR       (0x1 << 8)
-#define BRIDGE_ISR_INT_MSK              (0xff << 0)
-#define BRIDGE_ISR_INT(x)               (0x1 << (x))
-
-#define BRIDGE_ISR_LINK_ERROR           \
-                (BRIDGE_ISR_LLP_REC_SNERR|BRIDGE_ISR_LLP_REC_CBERR|     \
-                 BRIDGE_ISR_LLP_RCTY|BRIDGE_ISR_LLP_TX_RETRY|           \
-                 BRIDGE_ISR_LLP_TCTY)
-
-#define BRIDGE_ISR_PCIBUS_PIOERR        \
-                (BRIDGE_ISR_PCI_MST_TIMEOUT|BRIDGE_ISR_PCI_ABORT)
-
-#define BRIDGE_ISR_PCIBUS_ERROR         \
-                (BRIDGE_ISR_PCIBUS_PIOERR|BRIDGE_ISR_PCI_PERR|          \
-                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_RETRY_CNT|          \
-                 BRIDGE_ISR_PCI_PARITY)
-
-#define BRIDGE_ISR_XTALK_ERROR          \
-                (BRIDGE_ISR_XREAD_REQ_TIMEOUT|BRIDGE_ISR_XREQ_FIFO_OFLOW|\
-                 BRIDGE_ISR_UNSUPPORTED_XOP|BRIDGE_ISR_INVLD_ADDR|      \
-                 BRIDGE_ISR_REQ_XTLK_ERR|BRIDGE_ISR_RESP_XTLK_ERR|      \
-                 BRIDGE_ISR_BAD_XREQ_PKT|BRIDGE_ISR_BAD_XRESP_PKT|      \
-                 BRIDGE_ISR_UNEXP_RESP)
-
-#define BRIDGE_ISR_ERRORS               \
-                (BRIDGE_ISR_LINK_ERROR|BRIDGE_ISR_PCIBUS_ERROR|         \
-                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR|          \
-                 BRIDGE_ISR_PMU_ESIZE_FAULT)
-
-/*
- * List of Errors which are fatal and kill the system
- */
-#define BRIDGE_ISR_ERROR_FATAL          \
-                ((BRIDGE_ISR_XTALK_ERROR & ~BRIDGE_ISR_XREAD_REQ_TIMEOUT)|\
-                 BRIDGE_ISR_PCI_SERR|BRIDGE_ISR_PCI_PARITY )
-
-#define BRIDGE_ISR_ERROR_DUMP           \
-                (BRIDGE_ISR_PCIBUS_ERROR|BRIDGE_ISR_PMU_ESIZE_FAULT|    \
-                 BRIDGE_ISR_XTALK_ERROR|BRIDGE_ISR_SSRAM_PERR)
-
-/* Bridge interrupt enable register bits definition */
-#define BRIDGE_IMR_UNEXP_RESP           BRIDGE_ISR_UNEXP_RESP
-#define BRIDGE_IMR_PMU_ESIZE_FAULT      BRIDGE_ISR_PMU_ESIZE_FAULT
-#define BRIDGE_IMR_BAD_XRESP_PKT        BRIDGE_ISR_BAD_XRESP_PKT
-#define BRIDGE_IMR_BAD_XREQ_PKT         BRIDGE_ISR_BAD_XREQ_PKT
-#define BRIDGE_IMR_RESP_XTLK_ERR        BRIDGE_ISR_RESP_XTLK_ERR
-#define BRIDGE_IMR_REQ_XTLK_ERR         BRIDGE_ISR_REQ_XTLK_ERR
-#define BRIDGE_IMR_INVLD_ADDR           BRIDGE_ISR_INVLD_ADDR
-#define BRIDGE_IMR_UNSUPPORTED_XOP      BRIDGE_ISR_UNSUPPORTED_XOP
-#define BRIDGE_IMR_XREQ_FIFO_OFLOW      BRIDGE_ISR_XREQ_FIFO_OFLOW
-#define BRIDGE_IMR_LLP_REC_SNERR        BRIDGE_ISR_LLP_REC_SNERR
-#define BRIDGE_IMR_LLP_REC_CBERR        BRIDGE_ISR_LLP_REC_CBERR
-#define BRIDGE_IMR_LLP_RCTY             BRIDGE_ISR_LLP_RCTY
-#define BRIDGE_IMR_LLP_TX_RETRY         BRIDGE_ISR_LLP_TX_RETRY
-#define BRIDGE_IMR_LLP_TCTY             BRIDGE_ISR_LLP_TCTY
-#define BRIDGE_IMR_SSRAM_PERR           BRIDGE_ISR_SSRAM_PERR
-#define BRIDGE_IMR_PCI_ABORT            BRIDGE_ISR_PCI_ABORT
-#define BRIDGE_IMR_PCI_PARITY           BRIDGE_ISR_PCI_PARITY
-#define BRIDGE_IMR_PCI_SERR             BRIDGE_ISR_PCI_SERR
-#define BRIDGE_IMR_PCI_PERR             BRIDGE_ISR_PCI_PERR
-#define BRIDGE_IMR_PCI_MST_TIMEOUT      BRIDGE_ISR_PCI_MST_TIMEOUT
-#define BRIDGE_IMR_GIO_MST_TIMEOUT      BRIDGE_ISR_GIO_MST_TIMEOUT
-#define BRIDGE_IMR_PCI_RETRY_CNT        BRIDGE_ISR_PCI_RETRY_CNT
-#define BRIDGE_IMR_XREAD_REQ_TIMEOUT    BRIDGE_ISR_XREAD_REQ_TIMEOUT
-#define BRIDGE_IMR_GIO_B_ENBL_ERR       BRIDGE_ISR_GIO_B_ENBL_ERR
-#define BRIDGE_IMR_INT_MSK              BRIDGE_ISR_INT_MSK
-#define BRIDGE_IMR_INT(x)               BRIDGE_ISR_INT(x)
-
-/* Bridge interrupt reset register bits definition */
-#define BRIDGE_IRR_MULTI_CLR            (0x1 << 6)
-#define BRIDGE_IRR_CRP_GRP_CLR          (0x1 << 5)
-#define BRIDGE_IRR_RESP_BUF_GRP_CLR     (0x1 << 4)
-#define BRIDGE_IRR_REQ_DSP_GRP_CLR      (0x1 << 3)
-#define BRIDGE_IRR_LLP_GRP_CLR          (0x1 << 2)
-#define BRIDGE_IRR_SSRAM_GRP_CLR        (0x1 << 1)
-#define BRIDGE_IRR_PCI_GRP_CLR          (0x1 << 0)
-#define BRIDGE_IRR_GIO_GRP_CLR          (0x1 << 0)
-#define BRIDGE_IRR_ALL_CLR              0x7f
-
-#define BRIDGE_IRR_CRP_GRP              (BRIDGE_ISR_UNEXP_RESP | \
-                                         BRIDGE_ISR_XREQ_FIFO_OFLOW)
-#define BRIDGE_IRR_RESP_BUF_GRP         (BRIDGE_ISR_BAD_XRESP_PKT | \
-                                         BRIDGE_ISR_RESP_XTLK_ERR | \
-                                         BRIDGE_ISR_XREAD_REQ_TIMEOUT)
-#define BRIDGE_IRR_REQ_DSP_GRP          (BRIDGE_ISR_UNSUPPORTED_XOP | \
-                                         BRIDGE_ISR_BAD_XREQ_PKT | \
-                                         BRIDGE_ISR_REQ_XTLK_ERR | \
-                                         BRIDGE_ISR_INVLD_ADDR)
-#define BRIDGE_IRR_LLP_GRP              (BRIDGE_ISR_LLP_REC_SNERR | \
-                                         BRIDGE_ISR_LLP_REC_CBERR | \
-                                         BRIDGE_ISR_LLP_RCTY | \
-                                         BRIDGE_ISR_LLP_TX_RETRY | \
-                                         BRIDGE_ISR_LLP_TCTY)
-#define BRIDGE_IRR_SSRAM_GRP            (BRIDGE_ISR_SSRAM_PERR | \
-                                         BRIDGE_ISR_PMU_ESIZE_FAULT)
-#define BRIDGE_IRR_PCI_GRP              (BRIDGE_ISR_PCI_ABORT | \
-                                         BRIDGE_ISR_PCI_PARITY | \
-                                         BRIDGE_ISR_PCI_SERR | \
-                                         BRIDGE_ISR_PCI_PERR | \
-                                         BRIDGE_ISR_PCI_MST_TIMEOUT | \
-                                         BRIDGE_ISR_PCI_RETRY_CNT)
-
-#define BRIDGE_IRR_GIO_GRP              (BRIDGE_ISR_GIO_B_ENBL_ERR | \
-                                         BRIDGE_ISR_GIO_MST_TIMEOUT)
-
-/* Bridge INT_DEV register bits definition */
-#define BRIDGE_INT_DEV_SHFT(n)          ((n)*3)
-#define BRIDGE_INT_DEV_MASK(n)          (0x7 << BRIDGE_INT_DEV_SHFT(n))
-#define BRIDGE_INT_DEV_SET(_dev, _line) (_dev << BRIDGE_INT_DEV_SHFT(_line))
-
-/* Bridge interrupt(x) register bits definition */
-#define BRIDGE_INT_ADDR_HOST            0x0003FF00
-#define BRIDGE_INT_ADDR_FLD             0x000000FF
-
-#define BRIDGE_TMO_PCI_RETRY_HLD_MASK   0x1f0000
-#define BRIDGE_TMO_GIO_TIMEOUT_MASK     0x001000
-#define BRIDGE_TMO_PCI_RETRY_CNT_MASK   0x0003ff
-
-#define BRIDGE_TMO_PCI_RETRY_CNT_MAX    0x3ff
-
-/*
- * The NASID should be shifted by this amount and stored into the
- * interrupt(x) register.
- */
-#define BRIDGE_INT_ADDR_NASID_SHFT      8
-
-/*
- * The BRIDGE_INT_ADDR_DEST_IO bit should be set to send an interrupt to
- * memory.
- */
-#define BRIDGE_INT_ADDR_DEST_IO         (1 << 17)
-#define BRIDGE_INT_ADDR_DEST_MEM        0
-#define BRIDGE_INT_ADDR_MASK            (1 << 17)
-
-/* Bridge device(x) register bits definition */
-#define BRIDGE_DEV_ERR_LOCK_EN          0x10000000
-#define BRIDGE_DEV_PAGE_CHK_DIS         0x08000000
-#define BRIDGE_DEV_FORCE_PCI_PAR        0x04000000
-#define BRIDGE_DEV_VIRTUAL_EN           0x02000000
-#define BRIDGE_DEV_PMU_WRGA_EN          0x01000000
-#define BRIDGE_DEV_DIR_WRGA_EN          0x00800000
-#define BRIDGE_DEV_DEV_SIZE             0x00400000
-#define BRIDGE_DEV_RT                   0x00200000
-#define BRIDGE_DEV_SWAP_PMU             0x00100000
-#define BRIDGE_DEV_SWAP_DIR             0x00080000
-#define BRIDGE_DEV_PREF                 0x00040000
-#define BRIDGE_DEV_PRECISE              0x00020000
-#define BRIDGE_DEV_COH                  0x00010000
-#define BRIDGE_DEV_BARRIER              0x00008000
-#define BRIDGE_DEV_GBR                  0x00004000
-#define BRIDGE_DEV_DEV_SWAP             0x00002000
-#define BRIDGE_DEV_DEV_IO_MEM           0x00001000
-#define BRIDGE_DEV_OFF_MASK             0x00000fff
-#define BRIDGE_DEV_OFF_ADDR_SHFT        20
-
-#define BRIDGE_DEV_PMU_BITS             (BRIDGE_DEV_PMU_WRGA_EN         | \
-                                         BRIDGE_DEV_SWAP_PMU)
-#define BRIDGE_DEV_D32_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
-                                         BRIDGE_DEV_SWAP_DIR            | \
-                                         BRIDGE_DEV_PREF                | \
-                                         BRIDGE_DEV_PRECISE             | \
-                                         BRIDGE_DEV_COH                 | \
-                                         BRIDGE_DEV_BARRIER)
-#define BRIDGE_DEV_D64_BITS             (BRIDGE_DEV_DIR_WRGA_EN         | \
-                                         BRIDGE_DEV_SWAP_DIR            | \
-                                         BRIDGE_DEV_COH                 | \
-                                         BRIDGE_DEV_BARRIER)
-
-/* Bridge Error Upper register bit field definition */
-#define BRIDGE_ERRUPPR_DEVMASTER        (0x1 << 20)     /* Device was master */
-#define BRIDGE_ERRUPPR_PCIVDEV          (0x1 << 19)     /* Virtual Req value */
-#define BRIDGE_ERRUPPR_DEVNUM_SHFT      (16)
-#define BRIDGE_ERRUPPR_DEVNUM_MASK      (0x7 << BRIDGE_ERRUPPR_DEVNUM_SHFT)
-#define BRIDGE_ERRUPPR_DEVICE(err)      (((err) >> BRIDGE_ERRUPPR_DEVNUM_SHFT) & 0x7)
-#define BRIDGE_ERRUPPR_ADDRMASK         (0xFFFF)
-
-/* Bridge interrupt mode register bits definition */
-#define BRIDGE_INTMODE_CLR_PKT_EN(x)    (0x1 << (x))
-
-/* this should be written to the xbow's link_control(x) register */
-#define BRIDGE_CREDIT   3
-
-/* RRB assignment register */
-#define BRIDGE_RRB_EN   0x8     /* after shifting down */
-#define BRIDGE_RRB_DEV  0x7     /* after shifting down */
-#define BRIDGE_RRB_VDEV 0x4     /* after shifting down */
-#define BRIDGE_RRB_PDEV 0x3     /* after shifting down */
-
-/* RRB status register */
-#define BRIDGE_RRB_VALID(r)     (0x00010000<<(r))
-#define BRIDGE_RRB_INUSE(r)     (0x00000001<<(r))
-
-/* RRB clear register */
-#define BRIDGE_RRB_CLEAR(r)     (0x00000001<<(r))
-
-/* xbox system controller declarations */
-#define XBOX_BRIDGE_WID         8
-#define FLASH_PROM1_BASE        0xE00000 /* To read the xbox sysctlr status */
-#define XBOX_RPS_EXISTS         1 << 6   /* RPS bit in status register */
-#define XBOX_RPS_FAIL           1 << 4   /* RPS status bit in register */
-
-/* ========================================================================
- */
-/*
- * Macros for Xtalk to Bridge bus (PCI/GIO) PIO
- * refer to section 4.2.1 of Bridge Spec for xtalk to PCI/GIO PIO mappings
- */
-/* XTALK addresses that map into Bridge Bus addr space */
-#define BRIDGE_PIO32_XTALK_ALIAS_BASE   0x000040000000L
-#define BRIDGE_PIO32_XTALK_ALIAS_LIMIT  0x00007FFFFFFFL
-#define BRIDGE_PIO64_XTALK_ALIAS_BASE   0x000080000000L
-#define BRIDGE_PIO64_XTALK_ALIAS_LIMIT  0x0000BFFFFFFFL
-#define BRIDGE_PCIIO_XTALK_ALIAS_BASE   0x000100000000L
-#define BRIDGE_PCIIO_XTALK_ALIAS_LIMIT  0x0001FFFFFFFFL
-
-/* Ranges of PCI bus space that can be accessed via PIO from xtalk */
-#define BRIDGE_MIN_PIO_ADDR_MEM         0x00000000      /* 1G PCI memory space */
-#define BRIDGE_MAX_PIO_ADDR_MEM         0x3fffffff
-#define BRIDGE_MIN_PIO_ADDR_IO          0x00000000      /* 4G PCI IO space */
-#define BRIDGE_MAX_PIO_ADDR_IO          0xffffffff
-
-/* XTALK addresses that map into PCI addresses */
-#define BRIDGE_PCI_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
-#define BRIDGE_PCI_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
-#define BRIDGE_PCI_MEM64_BASE           BRIDGE_PIO64_XTALK_ALIAS_BASE
-#define BRIDGE_PCI_MEM64_LIMIT          BRIDGE_PIO64_XTALK_ALIAS_LIMIT
-#define BRIDGE_PCI_IO_BASE              BRIDGE_PCIIO_XTALK_ALIAS_BASE
-#define BRIDGE_PCI_IO_LIMIT             BRIDGE_PCIIO_XTALK_ALIAS_LIMIT
-
-/*
- * Macros for Bridge bus (PCI/GIO) to Xtalk DMA
- */
-/* Bridge Bus DMA addresses */
-#define BRIDGE_LOCAL_BASE               0
-#define BRIDGE_DMA_MAPPED_BASE          0x40000000
-#define BRIDGE_DMA_MAPPED_SIZE          0x40000000      /* 1G Bytes */
-#define BRIDGE_DMA_DIRECT_BASE          0x80000000
-#define BRIDGE_DMA_DIRECT_SIZE          0x80000000      /* 2G Bytes */
-
-#define PCI32_LOCAL_BASE                BRIDGE_LOCAL_BASE
-
-/* PCI addresses of regions decoded by Bridge for DMA */
-#define PCI32_MAPPED_BASE               BRIDGE_DMA_MAPPED_BASE
-#define PCI32_DIRECT_BASE               BRIDGE_DMA_DIRECT_BASE
-
-#define IS_PCI32_LOCAL(x)       ((ulong_t)(x) < PCI32_MAPPED_BASE)
-#define IS_PCI32_MAPPED(x)      ((ulong_t)(x) < PCI32_DIRECT_BASE && \
-                                        (ulong_t)(x) >= PCI32_MAPPED_BASE)
-#define IS_PCI32_DIRECT(x)      ((ulong_t)(x) >= PCI32_MAPPED_BASE)
-#define IS_PCI64(x)             ((ulong_t)(x) >= PCI64_BASE)
-
-/*
- * The GIO address space.
- */
-/* Xtalk to GIO PIO */
-#define BRIDGE_GIO_MEM32_BASE           BRIDGE_PIO32_XTALK_ALIAS_BASE
-#define BRIDGE_GIO_MEM32_LIMIT          BRIDGE_PIO32_XTALK_ALIAS_LIMIT
-
-#define GIO_LOCAL_BASE                  BRIDGE_LOCAL_BASE
-
-/* GIO addresses of regions decoded by Bridge for DMA */
-#define GIO_MAPPED_BASE                 BRIDGE_DMA_MAPPED_BASE
-#define GIO_DIRECT_BASE                 BRIDGE_DMA_DIRECT_BASE
-
-#define IS_GIO_LOCAL(x)         ((ulong_t)(x) < GIO_MAPPED_BASE)
-#define IS_GIO_MAPPED(x)        ((ulong_t)(x) < GIO_DIRECT_BASE && \
-                                        (ulong_t)(x) >= GIO_MAPPED_BASE)
-#define IS_GIO_DIRECT(x)        ((ulong_t)(x) >= GIO_MAPPED_BASE)
-
-/* PCI to xtalk mapping */
-
-/* given a DIR_OFF value and a pci/gio 32 bits direct address, determine
- * which xtalk address is accessed
- */
-#define BRIDGE_DIRECT_32_SEG_SIZE       BRIDGE_DMA_DIRECT_SIZE
-#define BRIDGE_DIRECT_32_TO_XTALK(dir_off,adr)          \
-        ((dir_off) * BRIDGE_DIRECT_32_SEG_SIZE +        \
-                ((adr) & (BRIDGE_DIRECT_32_SEG_SIZE - 1)) + PHYS_RAMBASE)
-
-/* 64-bit address attribute masks */
-#define PCI64_ATTR_TARG_MASK    0xf000000000000000
-#define PCI64_ATTR_TARG_SHFT    60
-#define PCI64_ATTR_PREF         0x0800000000000000
-#define PCI64_ATTR_PREC         0x0400000000000000
-#define PCI64_ATTR_VIRTUAL      0x0200000000000000
-#define PCI64_ATTR_BAR          0x0100000000000000
-#define PCI64_ATTR_RMF_MASK     0x00ff000000000000
-#define PCI64_ATTR_RMF_SHFT     48
-
-#ifndef __ASSEMBLY__
-/* Address translation entry for mapped pci32 accesses */
-typedef union ate_u {
-        u64     ent;
-        struct ate_s {
-                u64     rmf:16;
-                u64     addr:36;
-                u64     targ:4;
-                u64     reserved:3;
-                u64     barrier:1;
-                u64     prefetch:1;
-                u64     precise:1;
-                u64     coherent:1;
-                u64     valid:1;
-        } field;
-} ate_t;
-#endif /* !__ASSEMBLY__ */
-
-#define ATE_V           0x01
-#define ATE_CO          0x02
-#define ATE_PREC        0x04
-#define ATE_PREF        0x08
-#define ATE_BAR         0x10
-
-#define ATE_PFNSHIFT            12
-#define ATE_TIDSHIFT            8
-#define ATE_RMFSHIFT            48
-
-#define mkate(xaddr, xid, attr) ((xaddr) & 0x0000fffffffff000ULL) | \
-                                ((xid)<<ATE_TIDSHIFT) | \
-                                (attr)
-
-#define BRIDGE_INTERNAL_ATES    128
-
-struct bridge_controller {
-        struct pci_controller   pc;
-        struct resource         mem;
-        struct resource         io;
-        bridge_t                *base;
-        nasid_t                 nasid;
-        unsigned int            widget_id;
-        unsigned int            irq_cpu;
-        dma64_addr_t            baddr;
-        unsigned int            pci_int[8];
-};
-
-#define BRIDGE_CONTROLLER(bus) \
-        ((struct bridge_controller *)((bus)->sysdata))
-
-extern void register_bridge_irq(unsigned int irq);
-extern int request_bridge_irq(struct bridge_controller *bc);
-
-extern struct pci_ops bridge_pci_ops;
-
-#endif /* _ASM_PCI_BRIDGE_H */
diff --git a/include/asm-mips/percpu.h b/include/asm-mips/percpu.h
deleted file mode 100644
index 844e763e9332..000000000000
--- a/include/asm-mips/percpu.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_PERCPU_H
-#define __ASM_PERCPU_H
-
-#include <asm-generic/percpu.h>
-
-#endif /* __ASM_PERCPU_H */
diff --git a/include/asm-mips/pgalloc.h b/include/asm-mips/pgalloc.h
deleted file mode 100644
index 1275831dda29..000000000000
--- a/include/asm-mips/pgalloc.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 2001, 2003 by Ralf Baechle
- * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PGALLOC_H
-#define _ASM_PGALLOC_H
-
-#include <linux/highmem.h>
-#include <linux/mm.h>
-#include <linux/sched.h>
-
-static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
-        pte_t *pte)
-{
-        set_pmd(pmd, __pmd((unsigned long)pte));
-}
-
-static inline void pmd_populate(struct mm_struct *mm, pmd_t *pmd,
-        pgtable_t pte)
-{
-        set_pmd(pmd, __pmd((unsigned long)page_address(pte)));
-}
-#define pmd_pgtable(pmd) pmd_page(pmd)
-
-/*
- * Initialize a new pmd table with invalid pointers.
- */
-extern void pmd_init(unsigned long page, unsigned long pagetable);
-
-#ifdef CONFIG_64BIT
-
-static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
-{
-        set_pud(pud, __pud((unsigned long)pmd));
-}
-#endif
-
-/*
- * Initialize a new pgd / pmd table with invalid pointers.
- */
-extern void pgd_init(unsigned long page);
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
-        pgd_t *ret, *init;
-
-        ret = (pgd_t *) __get_free_pages(GFP_KERNEL, PGD_ORDER);
-        if (ret) {
-                init = pgd_offset(&init_mm, 0UL);
-                pgd_init((unsigned long)ret);
-                memcpy(ret + USER_PTRS_PER_PGD, init + USER_PTRS_PER_PGD,
-                       (PTRS_PER_PGD - USER_PTRS_PER_PGD) * sizeof(pgd_t));
-        }
-
-        return ret;
-}
-
-static inline void pgd_free(struct mm_struct *mm, pgd_t *pgd)
-{
-        free_pages((unsigned long)pgd, PGD_ORDER);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
-        unsigned long address)
-{
-        pte_t *pte;
-
-        pte = (pte_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT|__GFP_ZERO, PTE_ORDER);
-
-        return pte;
-}
-
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
-        unsigned long address)
-{
-        struct page *pte;
-
-        pte = alloc_pages(GFP_KERNEL | __GFP_REPEAT, PTE_ORDER);
-        if (pte) {
-                clear_highpage(pte);
-                pgtable_page_ctor(pte);
-        }
-        return pte;
-}
-
-static inline void pte_free_kernel(struct mm_struct *mm, pte_t *pte)
-{
-        free_pages((unsigned long)pte, PTE_ORDER);
-}
-
-static inline void pte_free(struct mm_struct *mm, pgtable_t pte)
-{
-        pgtable_page_dtor(pte);
-        __free_pages(pte, PTE_ORDER);
-}
-
-#define __pte_free_tlb(tlb,pte)                         \
-do {                                                    \
-        pgtable_page_dtor(pte);                         \
-        tlb_remove_page((tlb), pte);                    \
-} while (0)
-
-#ifdef CONFIG_32BIT
-
-/*
- * allocating and freeing a pmd is trivial: the 1-entry pmd is
- * inside the pgd, so has no extra memory associated with it.
- */
-#define pmd_free(mm, x)                 do { } while (0)
-#define __pmd_free_tlb(tlb, x)          do { } while (0)
-
-#endif
-
-#ifdef CONFIG_64BIT
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long address)
-{
-        pmd_t *pmd;
-
-        pmd = (pmd_t *) __get_free_pages(GFP_KERNEL|__GFP_REPEAT, PMD_ORDER);
-        if (pmd)
-                pmd_init((unsigned long)pmd, (unsigned long)invalid_pte_table);
-        return pmd;
-}
-
-static inline void pmd_free(struct mm_struct *mm, pmd_t *pmd)
-{
-        free_pages((unsigned long)pmd, PMD_ORDER);
-}
-
-#define __pmd_free_tlb(tlb, x)  pmd_free((tlb)->mm, x)
-
-#endif
-
-#define check_pgt_cache()       do { } while (0)
-
-extern void pagetable_init(void);
-
-#endif /* _ASM_PGALLOC_H */
diff --git a/include/asm-mips/pgtable-32.h b/include/asm-mips/pgtable-32.h
deleted file mode 100644
index 4396e9ffd418..000000000000
--- a/include/asm-mips/pgtable-32.h
+++ /dev/null
@@ -1,234 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
- * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PGTABLE_32_H
-#define _ASM_PGTABLE_32_H
-
-#include <asm/addrspace.h>
-#include <asm/page.h>
-
-#include <linux/linkage.h>
-#include <asm/cachectl.h>
-#include <asm/fixmap.h>
-
-#include <asm-generic/pgtable-nopmd.h>
-
-/*
- * - add_wired_entry() add a fixed TLB entry, and move wired register
- */
-extern void add_wired_entry(unsigned long entrylo0, unsigned long entrylo1,
-                               unsigned long entryhi, unsigned long pagemask);
-
-/*
- * - add_temporary_entry() add a temporary TLB entry. We use TLB entries
- *      starting at the top and working down. This is for populating the
- *      TLB before trap_init() puts the TLB miss handler in place. It
- *      should be used only for entries matching the actual page tables,
- *      to prevent inconsistencies.
- */
-extern int add_temporary_entry(unsigned long entrylo0, unsigned long entrylo1,
-                               unsigned long entryhi, unsigned long pagemask);
-
-
-/* Basically we have the same two-level (which is the logical three level
- * Linux page table layout folded) page tables as the i386.  Some day
- * when we have proper page coloring support we can have a 1% quicker
- * tlb refill handling mechanism, but for now it is a bit slower but
- * works even with the cache aliasing problem the R4k and above have.
- */
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (2 * PAGE_SHIFT + PTE_ORDER - PTE_T_LOG2)
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK      (~(PGDIR_SIZE-1))
-
-/*
- * Entries per page directory level: we use two-level, so
- * we don't really have any PUD/PMD directory physically.
- */
-#define __PGD_ORDER     (32 - 3 * PAGE_SHIFT + PGD_T_LOG2 + PTE_T_LOG2)
-#define PGD_ORDER       (__PGD_ORDER >= 0 ? __PGD_ORDER : 0)
-#define PUD_ORDER       aieeee_attempt_to_allocate_pud
-#define PMD_ORDER       1
-#define PTE_ORDER       0
-
-#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
-#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
-
-#define USER_PTRS_PER_PGD       (0x80000000UL/PGDIR_SIZE)
-#define FIRST_USER_ADDRESS      0
-
-#define VMALLOC_START     MAP_BASE
-
-#define PKMAP_BASE              (0xfe000000UL)
-
-#ifdef CONFIG_HIGHMEM
-# define VMALLOC_END    (PKMAP_BASE-2*PAGE_SIZE)
-#else
-# define VMALLOC_END    (FIXADDR_START-2*PAGE_SIZE)
-#endif
-
-#ifdef CONFIG_64BIT_PHYS_ADDR
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %016Lx.\n", __FILE__, __LINE__, pte_val(e))
-#else
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#endif
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-extern void load_pgd(unsigned long pg_dir);
-
-extern pte_t invalid_pte_table[PAGE_SIZE/sizeof(pte_t)];
-
-/*
- * Empty pgd/pmd entries point to the invalid_pte_table.
- */
-static inline int pmd_none(pmd_t pmd)
-{
-        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
-}
-
-#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
-
-static inline int pmd_present(pmd_t pmd)
-{
-        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
-}
-
-static inline void pmd_clear(pmd_t *pmdp)
-{
-        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
-}
-
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define pte_page(x)             pfn_to_page(pte_pfn(x))
-#define pte_pfn(x)              ((unsigned long)((x).pte_high >> 6))
-static inline pte_t
-pfn_pte(unsigned long pfn, pgprot_t prot)
-{
-        pte_t pte;
-        pte.pte_high = (pfn << 6) | (pgprot_val(prot) & 0x3f);
-        pte.pte_low = pgprot_val(prot);
-        return pte;
-}
-
-#else
-
-#define pte_page(x)             pfn_to_page(pte_pfn(x))
-
-#ifdef CONFIG_CPU_VR41XX
-#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
-#else
-#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)      __pte(((unsigned long long)(pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
-
-#define __pgd_offset(address)   pgd_index(address)
-#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
-#define __pmd_offset(address)   (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
-/* to find an entry in a kernel page-table-directory */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-
-/* to find an entry in a page-table-directory */
-#define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
-
-/* Find an entry in the third-level page table.. */
-#define __pte_offset(address)                                           \
-        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset(dir, address)                                        \
-        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_kernel(dir, address)                                 \
-        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-
-#define pte_offset_map(dir, address)                                    \
-        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-#define pte_offset_map_nested(dir, address)                             \
-        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-#define pte_unmap(pte) ((void)(pte))
-#define pte_unmap_nested(pte) ((void)(pte))
-
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-
-/* Swap entries must have VALID bit cleared. */
-#define __swp_type(x)           (((x).val >> 10) & 0x1f)
-#define __swp_offset(x)         ((x).val >> 15)
-#define __swp_entry(type,offset)        \
-        ((swp_entry_t) { ((type) << 10) | ((offset) << 15) })
-
-/*
- * Bits 0, 4, 8, and 9 are taken, split up 28 bits of offset into this range:
- */
-#define PTE_FILE_MAX_BITS       28
-
-#define pte_to_pgoff(_pte)      ((((_pte).pte >> 1 ) & 0x07) | \
-                                 (((_pte).pte >> 2 ) & 0x38) | \
-                                 (((_pte).pte >> 10) <<  6 ))
-
-#define pgoff_to_pte(off)       ((pte_t) { (((off) & 0x07) << 1 ) | \
-                                           (((off) & 0x38) << 2 ) | \
-                                           (((off) >>  6 ) << 10) | \
-                                           _PAGE_FILE })
-
-#else
-
-/* Swap entries must have VALID and GLOBAL bits cleared. */
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define __swp_type(x)           (((x).val >> 2) & 0x1f)
-#define __swp_offset(x)          ((x).val >> 7)
-#define __swp_entry(type,offset)        \
-                ((swp_entry_t)  { ((type) << 2) | ((offset) << 7) })
-#else
-#define __swp_type(x)           (((x).val >> 8) & 0x1f)
-#define __swp_offset(x)          ((x).val >> 13)
-#define __swp_entry(type,offset)        \
-                ((swp_entry_t)  { ((type) << 8) | ((offset) << 13) })
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32) */
-
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-/*
- * Bits 0 and 1 of pte_high are taken, use the rest for the page offset...
- */
-#define PTE_FILE_MAX_BITS       30
-
-#define pte_to_pgoff(_pte)      ((_pte).pte_high >> 2)
-#define pgoff_to_pte(off)       ((pte_t) { _PAGE_FILE, (off) << 2 })
-
-#else
-/*
- * Bits 0, 4, 6, and 7 are taken, split up 28 bits of offset into this range:
- */
-#define PTE_FILE_MAX_BITS       28
-
-#define pte_to_pgoff(_pte)      ((((_pte).pte >> 1) & 0x7) | \
-                                 (((_pte).pte >> 2) & 0x8) | \
-                                 (((_pte).pte >> 8) <<  4))
-
-#define pgoff_to_pte(off)       ((pte_t) { (((off) & 0x7) << 1) | \
-                                           (((off) & 0x8) << 2) | \
-                                           (((off) >>  4) << 8) | \
-                                           _PAGE_FILE })
-#endif
-
-#endif
-
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { (pte).pte_high })
-#define __swp_entry_to_pte(x)   ((pte_t) { 0, (x).val })
-#else
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-#endif
-
-#endif /* _ASM_PGTABLE_32_H */
diff --git a/include/asm-mips/pgtable-64.h b/include/asm-mips/pgtable-64.h
deleted file mode 100644
index 943515f0ef87..000000000000
--- a/include/asm-mips/pgtable-64.h
+++ /dev/null
@@ -1,253 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000, 2003 Ralf Baechle
- * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PGTABLE_64_H
-#define _ASM_PGTABLE_64_H
-
-#include <linux/linkage.h>
-
-#include <asm/addrspace.h>
-#include <asm/page.h>
-#include <asm/cachectl.h>
-#include <asm/fixmap.h>
-
-#include <asm-generic/pgtable-nopud.h>
-
-/*
- * Each address space has 2 4K pages as its page directory, giving 1024
- * (== PTRS_PER_PGD) 8 byte pointers to pmd tables. Each pmd table is a
- * single 4K page, giving 512 (== PTRS_PER_PMD) 8 byte pointers to page
- * tables. Each page table is also a single 4K page, giving 512 (==
- * PTRS_PER_PTE) 8 byte ptes. Each pud entry is initialized to point to
- * invalid_pmd_table, each pmd entry is initialized to point to
- * invalid_pte_table, each pte is initialized to 0. When memory is low,
- * and a pmd table or a page table allocation fails, empty_bad_pmd_table
- * and empty_bad_page_table is returned back to higher layer code, so
- * that the failure is recognized later on. Linux does not seem to
- * handle these failures very well though. The empty_bad_page_table has
- * invalid pte entries in it, to force page faults.
- *
- * Kernel mappings: kernel mappings are held in the swapper_pg_table.
- * The layout is identical to userspace except it's indexed with the
- * fault address - VMALLOC_START.
- */
-
-/* PMD_SHIFT determines the size of the area a second-level page table can map */
-#define PMD_SHIFT       (PAGE_SHIFT + (PAGE_SHIFT + PTE_ORDER - 3))
-#define PMD_SIZE        (1UL << PMD_SHIFT)
-#define PMD_MASK        (~(PMD_SIZE-1))
-
-/* PGDIR_SHIFT determines what a third-level page table entry can map */
-#define PGDIR_SHIFT     (PMD_SHIFT + (PAGE_SHIFT + PMD_ORDER - 3))
-#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
-#define PGDIR_MASK      (~(PGDIR_SIZE-1))
-
-/*
- * For 4kB page size we use a 3 level page tree and an 8kB pud, which
- * permits us mapping 40 bits of virtual address space.
- *
- * We used to implement 41 bits by having an order 1 pmd level but that seemed
- * rather pointless.
- *
- * For 8kB page size we use a 3 level page tree which permits a total of
- * 8TB of address space.  Alternatively a 33-bit / 8GB organization using
- * two levels would be easy to implement.
- *
- * For 16kB page size we use a 2 level page tree which permits a total of
- * 36 bits of virtual address space.  We could add a third level but it seems
- * like at the moment there's no need for this.
- *
- * For 64kB page size we use a 2 level page table tree for a total of 42 bits
- * of virtual address space.
- */
-#ifdef CONFIG_PAGE_SIZE_4KB
-#define PGD_ORDER               1
-#define PUD_ORDER               aieeee_attempt_to_allocate_pud
-#define PMD_ORDER               0
-#define PTE_ORDER               0
-#endif
-#ifdef CONFIG_PAGE_SIZE_8KB
-#define PGD_ORDER               0
-#define PUD_ORDER               aieeee_attempt_to_allocate_pud
-#define PMD_ORDER               0
-#define PTE_ORDER               0
-#endif
-#ifdef CONFIG_PAGE_SIZE_16KB
-#define PGD_ORDER               0
-#define PUD_ORDER               aieeee_attempt_to_allocate_pud
-#define PMD_ORDER               0
-#define PTE_ORDER               0
-#endif
-#ifdef CONFIG_PAGE_SIZE_64KB
-#define PGD_ORDER               0
-#define PUD_ORDER               aieeee_attempt_to_allocate_pud
-#define PMD_ORDER               0
-#define PTE_ORDER               0
-#endif
-
-#define PTRS_PER_PGD    ((PAGE_SIZE << PGD_ORDER) / sizeof(pgd_t))
-#define PTRS_PER_PMD    ((PAGE_SIZE << PMD_ORDER) / sizeof(pmd_t))
-#define PTRS_PER_PTE    ((PAGE_SIZE << PTE_ORDER) / sizeof(pte_t))
-
-#if PGDIR_SIZE >= TASK_SIZE
-#define USER_PTRS_PER_PGD       (1)
-#else
-#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
-#endif
-#define FIRST_USER_ADDRESS      0UL
-
-#define VMALLOC_START           MAP_BASE
-#define VMALLOC_END     \
-        (VMALLOC_START + PTRS_PER_PGD * PTRS_PER_PMD * PTRS_PER_PTE * PAGE_SIZE)
-#if defined(CONFIG_MODULES) && defined(KBUILD_64BIT_SYM32) && \
-        VMALLOC_START != CKSSEG
-/* Load modules into 32bit-compatible segment. */
-#define MODULE_START    CKSSEG
-#define MODULE_END      (FIXADDR_START-2*PAGE_SIZE)
-extern pgd_t module_pg_dir[PTRS_PER_PGD];
-#endif
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %016lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %016lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-extern pte_t invalid_pte_table[PTRS_PER_PTE];
-extern pte_t empty_bad_page_table[PTRS_PER_PTE];
-extern pmd_t invalid_pmd_table[PTRS_PER_PMD];
-extern pmd_t empty_bad_pmd_table[PTRS_PER_PMD];
-
-/*
- * Empty pgd/pmd entries point to the invalid_pte_table.
- */
-static inline int pmd_none(pmd_t pmd)
-{
-        return pmd_val(pmd) == (unsigned long) invalid_pte_table;
-}
-
-#define pmd_bad(pmd)            (pmd_val(pmd) & ~PAGE_MASK)
-
-static inline int pmd_present(pmd_t pmd)
-{
-        return pmd_val(pmd) != (unsigned long) invalid_pte_table;
-}
-
-static inline void pmd_clear(pmd_t *pmdp)
-{
-        pmd_val(*pmdp) = ((unsigned long) invalid_pte_table);
-}
-
-/*
- * Empty pud entries point to the invalid_pmd_table.
- */
-static inline int pud_none(pud_t pud)
-{
-        return pud_val(pud) == (unsigned long) invalid_pmd_table;
-}
-
-static inline int pud_bad(pud_t pud)
-{
-        return pud_val(pud) & ~PAGE_MASK;
-}
-
-static inline int pud_present(pud_t pud)
-{
-        return pud_val(pud) != (unsigned long) invalid_pmd_table;
-}
-
-static inline void pud_clear(pud_t *pudp)
-{
-        pud_val(*pudp) = ((unsigned long) invalid_pmd_table);
-}
-
-#define pte_page(x)             pfn_to_page(pte_pfn(x))
-
-#ifdef CONFIG_CPU_VR41XX
-#define pte_pfn(x)              ((unsigned long)((x).pte >> (PAGE_SHIFT + 2)))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << (PAGE_SHIFT + 2)) | pgprot_val(prot))
-#else
-#define pte_pfn(x)              ((unsigned long)((x).pte >> PAGE_SHIFT))
-#define pfn_pte(pfn, prot)      __pte(((pfn) << PAGE_SHIFT) | pgprot_val(prot))
-#endif
-
-#define __pgd_offset(address)   pgd_index(address)
-#define __pud_offset(address)   (((address) >> PUD_SHIFT) & (PTRS_PER_PUD-1))
-#define __pmd_offset(address)   pmd_index(address)
-
-/* to find an entry in a kernel page-table-directory */
-#ifdef MODULE_START
-#define pgd_offset_k(address) \
-        ((address) >= MODULE_START ? module_pg_dir : pgd_offset(&init_mm, 0UL))
-#else
-#define pgd_offset_k(address) pgd_offset(&init_mm, 0UL)
-#endif
-
-#define pgd_index(address)      (((address) >> PGDIR_SHIFT) & (PTRS_PER_PGD-1))
-#define pmd_index(address)      (((address) >> PMD_SHIFT) & (PTRS_PER_PMD-1))
-
-/* to find an entry in a page-table-directory */
-#define pgd_offset(mm, addr)    ((mm)->pgd + pgd_index(addr))
-
-static inline unsigned long pud_page_vaddr(pud_t pud)
-{
-        return pud_val(pud);
-}
-#define pud_phys(pud)           virt_to_phys((void *)pud_val(pud))
-#define pud_page(pud)           (pfn_to_page(pud_phys(pud) >> PAGE_SHIFT))
-
-/* Find an entry in the second-level page table.. */
-static inline pmd_t *pmd_offset(pud_t * pud, unsigned long address)
-{
-        return (pmd_t *) pud_page_vaddr(*pud) + pmd_index(address);
-}
-
-/* Find an entry in the third-level page table.. */
-#define __pte_offset(address)                                           \
-        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
-#define pte_offset(dir, address)                                        \
-        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_kernel(dir, address)                                 \
-        ((pte_t *) pmd_page_vaddr(*(dir)) + __pte_offset(address))
-#define pte_offset_map(dir, address)                                    \
-        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-#define pte_offset_map_nested(dir, address)                             \
-        ((pte_t *)page_address(pmd_page(*(dir))) + __pte_offset(address))
-#define pte_unmap(pte) ((void)(pte))
-#define pte_unmap_nested(pte) ((void)(pte))
-
-/*
- * Initialize a new pgd / pmd table with invalid pointers.
- */
-extern void pgd_init(unsigned long page);
-extern void pmd_init(unsigned long page, unsigned long pagetable);
-
-/*
- * Non-present pages:  high 24 bits are offset, next 8 bits type,
- * low 32 bits zero.
- */
-static inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
-{ pte_t pte; pte_val(pte) = (type << 32) | (offset << 40); return pte; }
-
-#define __swp_type(x)           (((x).val >> 32) & 0xff)
-#define __swp_offset(x)         ((x).val >> 40)
-#define __swp_entry(type, offset) ((swp_entry_t) { pte_val(mk_swap_pte((type), (offset))) })
-#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
-
-/*
- * Bits 0, 4, 6, and 7 are taken. Let's leave bits 1, 2, 3, and 5 alone to
- * make things easier, and only use the upper 56 bits for the page offset...
- */
-#define PTE_FILE_MAX_BITS       56
-
-#define pte_to_pgoff(_pte)      ((_pte).pte >> 8)
-#define pgoff_to_pte(off)       ((pte_t) { ((off) << 8) | _PAGE_FILE })
-
-#endif /* _ASM_PGTABLE_64_H */
diff --git a/include/asm-mips/pgtable-bits.h b/include/asm-mips/pgtable-bits.h
deleted file mode 100644
index 51b34a48c84a..000000000000
--- a/include/asm-mips/pgtable-bits.h
+++ /dev/null
@@ -1,137 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 - 2002 by Ralf Baechle
- * Copyright (C) 1999, 2000, 2001 Silicon Graphics, Inc.
- * Copyright (C) 2002  Maciej W. Rozycki
- */
-#ifndef _ASM_PGTABLE_BITS_H
-#define _ASM_PGTABLE_BITS_H
-
-
-/*
- * Note that we shift the lower 32bits of each EntryLo[01] entry
- * 6 bits to the left. That way we can convert the PFN into the
- * physical address by a single 'and' operation and gain 6 additional
- * bits for storing information which isn't present in a normal
- * MIPS page table.
- *
- * Similar to the Alpha port, we need to keep track of the ref
- * and mod bits in software.  We have a software "yeah you can read
- * from this page" bit, and a hardware one which actually lets the
- * process read from the page.  On the same token we have a software
- * writable bit and the real hardware one which actually lets the
- * process write to the page, this keeps a mod bit via the hardware
- * dirty bit.
- *
- * Certain revisions of the R4000 and R5000 have a bug where if a
- * certain sequence occurs in the last 3 instructions of an executable
- * page, and the following page is not mapped, the cpu can do
- * unpredictable things.  The code (when it is written) to deal with
- * this problem will be in the update_mmu_cache() code for the r4k.
- */
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-
-#define _PAGE_PRESENT               (1<<6)  /* implemented in software */
-#define _PAGE_READ                  (1<<7)  /* implemented in software */
-#define _PAGE_WRITE                 (1<<8)  /* implemented in software */
-#define _PAGE_ACCESSED              (1<<9)  /* implemented in software */
-#define _PAGE_MODIFIED              (1<<10) /* implemented in software */
-#define _PAGE_FILE                  (1<<10) /* set:pagecache unset:swap */
-
-#define _PAGE_R4KBUG                (1<<0)  /* workaround for r4k bug  */
-#define _PAGE_GLOBAL                (1<<0)
-#define _PAGE_VALID                 (1<<1)
-#define _PAGE_SILENT_READ           (1<<1)  /* synonym                 */
-#define _PAGE_DIRTY                 (1<<2)  /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE          (1<<2)
-#define _CACHE_SHIFT                3
-#define _CACHE_MASK                 (7<<3)
-
-#else
-
-#define _PAGE_PRESENT               (1<<0)  /* implemented in software */
-#define _PAGE_READ                  (1<<1)  /* implemented in software */
-#define _PAGE_WRITE                 (1<<2)  /* implemented in software */
-#define _PAGE_ACCESSED              (1<<3)  /* implemented in software */
-#define _PAGE_MODIFIED              (1<<4)  /* implemented in software */
-#define _PAGE_FILE                  (1<<4)  /* set:pagecache unset:swap */
-
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-
-#define _PAGE_GLOBAL                (1<<8)
-#define _PAGE_VALID                 (1<<9)
-#define _PAGE_SILENT_READ           (1<<9)  /* synonym                 */
-#define _PAGE_DIRTY                 (1<<10) /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE          (1<<10)
-#define _CACHE_UNCACHED             (1<<11)
-#define _CACHE_MASK                 (1<<11)
-
-#else
-
-#define _PAGE_R4KBUG                (1<<5)  /* workaround for r4k bug  */
-#define _PAGE_GLOBAL                (1<<6)
-#define _PAGE_VALID                 (1<<7)
-#define _PAGE_SILENT_READ           (1<<7)  /* synonym                 */
-#define _PAGE_DIRTY                 (1<<8)  /* The MIPS dirty bit      */
-#define _PAGE_SILENT_WRITE          (1<<8)
-#define _CACHE_SHIFT                9
-#define _CACHE_MASK                 (7<<9)
-
-#endif
-#endif /* defined(CONFIG_64BIT_PHYS_ADDR && defined(CONFIG_CPU_MIPS32) */
-
-
-/*
- * Cache attributes
- */
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-
-#define _CACHE_CACHABLE_NONCOHERENT 0
-
-#elif defined(CONFIG_CPU_SB1)
-
-/* No penalty for being coherent on the SB1, so just
-   use it for "noncoherent" spaces, too.  Shouldn't hurt. */
-
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)
-#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)
-#define _CACHE_CACHABLE_NONCOHERENT (5<<_CACHE_SHIFT)
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)
-
-#elif defined(CONFIG_CPU_RM9000)
-
-#define _CACHE_WT                   (0<<_CACHE_SHIFT)
-#define _CACHE_WTWA                 (1<<_CACHE_SHIFT)
-#define _CACHE_UC_B                 (2<<_CACHE_SHIFT)
-#define _CACHE_WB                   (3<<_CACHE_SHIFT)
-#define _CACHE_CWBEA                (4<<_CACHE_SHIFT)
-#define _CACHE_CWB                  (5<<_CACHE_SHIFT)
-#define _CACHE_UCNB                 (6<<_CACHE_SHIFT)
-#define _CACHE_FPC                  (7<<_CACHE_SHIFT)
-
-#define _CACHE_UNCACHED             _CACHE_UC_B
-#define _CACHE_CACHABLE_NONCOHERENT _CACHE_WB
-
-#else
-
-#define _CACHE_CACHABLE_NO_WA       (0<<_CACHE_SHIFT)  /* R4600 only      */
-#define _CACHE_CACHABLE_WA          (1<<_CACHE_SHIFT)  /* R4600 only      */
-#define _CACHE_UNCACHED             (2<<_CACHE_SHIFT)  /* R4[0246]00      */
-#define _CACHE_CACHABLE_NONCOHERENT (3<<_CACHE_SHIFT)  /* R4[0246]00      */
-#define _CACHE_CACHABLE_CE          (4<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COW         (5<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_CACHABLE_COHERENT    (5<<_CACHE_SHIFT)  /* MIPS32R2 CMP    */
-#define _CACHE_CACHABLE_CUW         (6<<_CACHE_SHIFT)  /* R4[04]00MC only */
-#define _CACHE_UNCACHED_ACCELERATED (7<<_CACHE_SHIFT)  /* R10000 only     */
-
-#endif
-
-#define __READABLE      (_PAGE_READ | _PAGE_SILENT_READ | _PAGE_ACCESSED)
-#define __WRITEABLE     (_PAGE_WRITE | _PAGE_SILENT_WRITE | _PAGE_MODIFIED)
-
-#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_MODIFIED | _CACHE_MASK)
-
-#endif /* _ASM_PGTABLE_BITS_H */
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
deleted file mode 100644
index 6a0edf72ffbc..000000000000
--- a/include/asm-mips/pgtable.h
+++ /dev/null
@@ -1,383 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 Ralf Baechle
- */
-#ifndef _ASM_PGTABLE_H
-#define _ASM_PGTABLE_H
-
-#ifdef CONFIG_32BIT
-#include <asm/pgtable-32.h>
-#endif
-#ifdef CONFIG_64BIT
-#include <asm/pgtable-64.h>
-#endif
-
-#include <asm/io.h>
-#include <asm/pgtable-bits.h>
-
-struct mm_struct;
-struct vm_area_struct;
-
-#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _CACHE_CACHABLE_NONCOHERENT)
-#define PAGE_SHARED     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
-                                 _page_cachable_default)
-#define PAGE_COPY       __pgprot(_PAGE_PRESENT | _PAGE_READ | \
-                                 _page_cachable_default)
-#define PAGE_READONLY   __pgprot(_PAGE_PRESENT | _PAGE_READ | \
-                                 _page_cachable_default)
-#define PAGE_KERNEL     __pgprot(_PAGE_PRESENT | __READABLE | __WRITEABLE | \
-                                 _PAGE_GLOBAL | _page_cachable_default)
-#define PAGE_USERIO     __pgprot(_PAGE_PRESENT | _PAGE_READ | _PAGE_WRITE | \
-                                 _page_cachable_default)
-#define PAGE_KERNEL_UNCACHED __pgprot(_PAGE_PRESENT | __READABLE | \
-                        __WRITEABLE | _PAGE_GLOBAL | _CACHE_UNCACHED)
-
-/*
- * MIPS can't do page protection for execute, and considers that the same like
- * read. Also, write permissions imply read permissions. This is the closest
- * we can get by reasonable means..
- */
-
-/*
- * Dummy values to fill the table in mmap.c
- * The real values will be generated at runtime
- */
-#define __P000 __pgprot(0)
-#define __P001 __pgprot(0)
-#define __P010 __pgprot(0)
-#define __P011 __pgprot(0)
-#define __P100 __pgprot(0)
-#define __P101 __pgprot(0)
-#define __P110 __pgprot(0)
-#define __P111 __pgprot(0)
-
-#define __S000 __pgprot(0)
-#define __S001 __pgprot(0)
-#define __S010 __pgprot(0)
-#define __S011 __pgprot(0)
-#define __S100 __pgprot(0)
-#define __S101 __pgprot(0)
-#define __S110 __pgprot(0)
-#define __S111 __pgprot(0)
-
-extern unsigned long _page_cachable_default;
-
-/*
- * ZERO_PAGE is a global shared page that is always zero; used
- * for zero-mapped memory areas etc..
- */
-
-extern unsigned long empty_zero_page;
-extern unsigned long zero_page_mask;
-
-#define ZERO_PAGE(vaddr) \
-        (virt_to_page((void *)(empty_zero_page + (((unsigned long)(vaddr)) & zero_page_mask))))
-
-extern void paging_init(void);
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define pmd_phys(pmd)           virt_to_phys((void *)pmd_val(pmd))
-#define pmd_page(pmd)           (pfn_to_page(pmd_phys(pmd) >> PAGE_SHIFT))
-#define pmd_page_vaddr(pmd)     pmd_val(pmd)
-
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-
-#define pte_none(pte)           (!(((pte).pte_low | (pte).pte_high) & ~_PAGE_GLOBAL))
-#define pte_present(pte)        ((pte).pte_low & _PAGE_PRESENT)
-
-static inline void set_pte(pte_t *ptep, pte_t pte)
-{
-        ptep->pte_high = pte.pte_high;
-        smp_wmb();
-        ptep->pte_low = pte.pte_low;
-        //printk("pte_high %x pte_low %x\n", ptep->pte_high, ptep->pte_low);
-
-        if (pte.pte_low & _PAGE_GLOBAL) {
-                pte_t *buddy = ptep_buddy(ptep);
-                /*
-                 * Make sure the buddy is global too (if it's !none,
-                 * it better already be global)
-                 */
-                if (pte_none(*buddy)) {
-                        buddy->pte_low  |= _PAGE_GLOBAL;
-                        buddy->pte_high |= _PAGE_GLOBAL;
-                }
-        }
-}
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
-        pte_t null = __pte(0);
-
-        /* Preserve global status for the pair */
-        if (ptep_buddy(ptep)->pte_low & _PAGE_GLOBAL)
-                null.pte_low = null.pte_high = _PAGE_GLOBAL;
-
-        set_pte_at(mm, addr, ptep, null);
-}
-#else
-
-#define pte_none(pte)           (!(pte_val(pte) & ~_PAGE_GLOBAL))
-#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
-
-/*
- * Certain architectures need to do special things when pte's
- * within a page table are directly modified.  Thus, the following
- * hook is made available.
- */
-static inline void set_pte(pte_t *ptep, pte_t pteval)
-{
-        *ptep = pteval;
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
-        if (pte_val(pteval) & _PAGE_GLOBAL) {
-                pte_t *buddy = ptep_buddy(ptep);
-                /*
-                 * Make sure the buddy is global too (if it's !none,
-                 * it better already be global)
-                 */
-                if (pte_none(*buddy))
-                        pte_val(*buddy) = pte_val(*buddy) | _PAGE_GLOBAL;
-        }
-#endif
-}
-#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr, pte_t *ptep)
-{
-#if !defined(CONFIG_CPU_R3000) && !defined(CONFIG_CPU_TX39XX)
-        /* Preserve global status for the pair */
-        if (pte_val(*ptep_buddy(ptep)) & _PAGE_GLOBAL)
-                set_pte_at(mm, addr, ptep, __pte(_PAGE_GLOBAL));
-        else
-#endif
-                set_pte_at(mm, addr, ptep, __pte(0));
-}
-#endif
-
-/*
- * (pmds are folded into puds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pmd(pmdptr, pmdval) do { *(pmdptr) = (pmdval); } while(0)
-
-#ifdef CONFIG_64BIT
-/*
- * (puds are folded into pgds so this doesn't get actually called,
- * but the define is needed for a generic inline function.)
- */
-#define set_pud(pudptr, pudval) do { *(pudptr) = (pudval); } while(0)
-#endif
-
-#define PGD_T_LOG2      (__builtin_ffs(sizeof(pgd_t)) - 1)
-#define PMD_T_LOG2      (__builtin_ffs(sizeof(pmd_t)) - 1)
-#define PTE_T_LOG2      (__builtin_ffs(sizeof(pte_t)) - 1)
-
-/*
- * We used to declare this array with size but gcc 3.3 and older are not able
- * to find that this expression is a constant, so the size is dropped.
- */
-extern pgd_t swapper_pg_dir[];
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-static inline int pte_write(pte_t pte)  { return pte.pte_low & _PAGE_WRITE; }
-static inline int pte_dirty(pte_t pte)  { return pte.pte_low & _PAGE_MODIFIED; }
-static inline int pte_young(pte_t pte)  { return pte.pte_low & _PAGE_ACCESSED; }
-static inline int pte_file(pte_t pte)   { return pte.pte_low & _PAGE_FILE; }
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
-        pte.pte_low  &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
-        pte.pte_high &= ~_PAGE_SILENT_WRITE;
-        return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
-        pte.pte_low  &= ~(_PAGE_MODIFIED | _PAGE_SILENT_WRITE);
-        pte.pte_high &= ~_PAGE_SILENT_WRITE;
-        return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
-        pte.pte_low  &= ~(_PAGE_ACCESSED | _PAGE_SILENT_READ);
-        pte.pte_high &= ~_PAGE_SILENT_READ;
-        return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
-        pte.pte_low |= _PAGE_WRITE;
-        if (pte.pte_low & _PAGE_MODIFIED) {
-                pte.pte_low  |= _PAGE_SILENT_WRITE;
-                pte.pte_high |= _PAGE_SILENT_WRITE;
-        }
-        return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
-        pte.pte_low |= _PAGE_MODIFIED;
-        if (pte.pte_low & _PAGE_WRITE) {
-                pte.pte_low  |= _PAGE_SILENT_WRITE;
-                pte.pte_high |= _PAGE_SILENT_WRITE;
-        }
-        return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
-        pte.pte_low |= _PAGE_ACCESSED;
-        if (pte.pte_low & _PAGE_READ) {
-                pte.pte_low  |= _PAGE_SILENT_READ;
-                pte.pte_high |= _PAGE_SILENT_READ;
-        }
-        return pte;
-}
-#else
-static inline int pte_write(pte_t pte)  { return pte_val(pte) & _PAGE_WRITE; }
-static inline int pte_dirty(pte_t pte)  { return pte_val(pte) & _PAGE_MODIFIED; }
-static inline int pte_young(pte_t pte)  { return pte_val(pte) & _PAGE_ACCESSED; }
-static inline int pte_file(pte_t pte)   { return pte_val(pte) & _PAGE_FILE; }
-
-static inline pte_t pte_wrprotect(pte_t pte)
-{
-        pte_val(pte) &= ~(_PAGE_WRITE | _PAGE_SILENT_WRITE);
-        return pte;
-}
-
-static inline pte_t pte_mkclean(pte_t pte)
-{
-        pte_val(pte) &= ~(_PAGE_MODIFIED|_PAGE_SILENT_WRITE);
-        return pte;
-}
-
-static inline pte_t pte_mkold(pte_t pte)
-{
-        pte_val(pte) &= ~(_PAGE_ACCESSED|_PAGE_SILENT_READ);
-        return pte;
-}
-
-static inline pte_t pte_mkwrite(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_WRITE;
-        if (pte_val(pte) & _PAGE_MODIFIED)
-                pte_val(pte) |= _PAGE_SILENT_WRITE;
-        return pte;
-}
-
-static inline pte_t pte_mkdirty(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_MODIFIED;
-        if (pte_val(pte) & _PAGE_WRITE)
-                pte_val(pte) |= _PAGE_SILENT_WRITE;
-        return pte;
-}
-
-static inline pte_t pte_mkyoung(pte_t pte)
-{
-        pte_val(pte) |= _PAGE_ACCESSED;
-        if (pte_val(pte) & _PAGE_READ)
-                pte_val(pte) |= _PAGE_SILENT_READ;
-        return pte;
-}
-#endif
-static inline int pte_special(pte_t pte)        { return 0; }
-static inline pte_t pte_mkspecial(pte_t pte)    { return pte; }
-
-/*
- * Macro to make mark a page protection value as "uncacheable".  Note
- * that "protection" is really a misnomer here as the protection value
- * contains the memory attribute bits, dirty bits, and various other
- * bits as well.
- */
-#define pgprot_noncached pgprot_noncached
-
-static inline pgprot_t pgprot_noncached(pgprot_t _prot)
-{
-        unsigned long prot = pgprot_val(_prot);
-
-        prot = (prot & ~_CACHE_MASK) | _CACHE_UNCACHED;
-
-        return __pgprot(prot);
-}
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- */
-#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
-
-#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32)
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-        pte.pte_low  &= _PAGE_CHG_MASK;
-        pte.pte_high &= ~0x3f;
-        pte.pte_low  |= pgprot_val(newprot);
-        pte.pte_high |= pgprot_val(newprot) & 0x3f;
-        return pte;
-}
-#else
-static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
-{
-        return __pte((pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot));
-}
-#endif
-
-
-extern void __update_tlb(struct vm_area_struct *vma, unsigned long address,
-        pte_t pte);
-extern void __update_cache(struct vm_area_struct *vma, unsigned long address,
-        pte_t pte);
-
-static inline void update_mmu_cache(struct vm_area_struct *vma,
-        unsigned long address, pte_t pte)
-{
-        __update_tlb(vma, address, pte);
-        __update_cache(vma, address, pte);
-}
-
-#define kern_addr_valid(addr)   (1)
-
-#ifdef CONFIG_64BIT_PHYS_ADDR
-extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from, unsigned long pfn, unsigned long size, pgprot_t prot);
-
-static inline int io_remap_pfn_range(struct vm_area_struct *vma,
-                unsigned long vaddr,
-                unsigned long pfn,
-                unsigned long size,
-                pgprot_t prot)
-{
-        phys_t phys_addr_high = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
-        return remap_pfn_range(vma, vaddr, phys_addr_high >> PAGE_SHIFT, size, prot);
-}
-#else
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-#endif
-
-#include <asm-generic/pgtable.h>
-
-/*
- * We provide our own get_unmapped area to cope with the virtual aliasing
- * constraints placed on us by the cache architecture.
- */
-#define HAVE_ARCH_UNMAPPED_AREA
-
-/*
- * No page table caches to initialise
- */
-#define pgtable_cache_init()    do { } while (0)
-
-#endif /* _ASM_PGTABLE_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
deleted file mode 100644
index c84bcf9570b1..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_cic_int.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/*
- * Defines for the MSP interrupt controller.
- *
- * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
- * Author: Carsten Langgaard, carstenl@mips.com
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- */
-
-#ifndef _MSP_CIC_INT_H
-#define _MSP_CIC_INT_H
-
-/*
- * The PMC-Sierra CIC interrupts are all centrally managed by the
- * CIC sub-system.
- * We attempt to keep the interrupt numbers as consistent as possible
- * across all of the MSP devices, but some differences will creep in ...
- * The interrupts which are directly forwarded to the MIPS core interrupts
- * are assigned interrupts in the range 0-7, interrupts cascaded through
- * the CIC are assigned interrupts 8-39.  The cascade occurs on C_IRQ4
- * (MSP_INT_CIC).  Currently we don't really distinguish between VPE1
- * and VPE0 (or thread contexts for that matter).  Will have to fix.
- * The PER interrupts are assigned interrupts in the range 40-71.
-*/
-
-
-/*
- * IRQs directly forwarded to the CPU
- */
-#define MSP_MIPS_INTBASE        0
-#define MSP_INT_SW0             0       /* IRQ for swint0,       C_SW0  */
-#define MSP_INT_SW1             1       /* IRQ for swint1,       C_SW1  */
-#define MSP_INT_MAC0            2       /* IRQ for MAC 0,        C_IRQ0 */
-#define MSP_INT_MAC1            3       /* IRQ for MAC 1,        C_IRQ1 */
-#define MSP_INT_USB             4       /* IRQ for USB,          C_IRQ2 */
-#define MSP_INT_SAR             5       /* IRQ for ADSL2+ SAR,   C_IRQ3 */
-#define MSP_INT_CIC             6       /* IRQ for CIC block,    C_IRQ4 */
-#define MSP_INT_SEC             7       /* IRQ for Sec engine,   C_IRQ5 */
-
-/*
- * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
- * These defines should be tied to the register definitions for the CIC
- * interrupt routine.  For now, just use hard-coded values.
- */
-#define MSP_CIC_INTBASE         (MSP_MIPS_INTBASE + 8)
-#define MSP_INT_EXT0            (MSP_CIC_INTBASE + 0)
-                                        /* External interrupt 0         */
-#define MSP_INT_EXT1            (MSP_CIC_INTBASE + 1)
-                                        /* External interrupt 1         */
-#define MSP_INT_EXT2            (MSP_CIC_INTBASE + 2)
-                                        /* External interrupt 2         */
-#define MSP_INT_EXT3            (MSP_CIC_INTBASE + 3)
-                                        /* External interrupt 3         */
-#define MSP_INT_CPUIF           (MSP_CIC_INTBASE + 4)
-                                        /* CPU interface interrupt      */
-#define MSP_INT_EXT4            (MSP_CIC_INTBASE + 5)
-                                        /* External interrupt 4         */
-#define MSP_INT_CIC_USB         (MSP_CIC_INTBASE + 6)
-                                        /* Cascaded IRQ for USB         */
-#define MSP_INT_MBOX            (MSP_CIC_INTBASE + 7)
-                                        /* Sec engine mailbox IRQ       */
-#define MSP_INT_EXT5            (MSP_CIC_INTBASE + 8)
-                                        /* External interrupt 5         */
-#define MSP_INT_TDM             (MSP_CIC_INTBASE + 9)
-                                        /* TDM interrupt                */
-#define MSP_INT_CIC_MAC0        (MSP_CIC_INTBASE + 10)
-                                        /* Cascaded IRQ for MAC 0       */
-#define MSP_INT_CIC_MAC1        (MSP_CIC_INTBASE + 11)
-                                        /* Cascaded IRQ for MAC 1       */
-#define MSP_INT_CIC_SEC         (MSP_CIC_INTBASE + 12)
-                                        /* Cascaded IRQ for sec engine  */
-#define MSP_INT_PER             (MSP_CIC_INTBASE + 13)
-                                        /* Peripheral interrupt         */
-#define MSP_INT_TIMER0          (MSP_CIC_INTBASE + 14)
-                                        /* SLP timer 0                  */
-#define MSP_INT_TIMER1          (MSP_CIC_INTBASE + 15)
-                                        /* SLP timer 1                  */
-#define MSP_INT_TIMER2          (MSP_CIC_INTBASE + 16)
-                                        /* SLP timer 2                  */
-#define MSP_INT_VPE0_TIMER      (MSP_CIC_INTBASE + 17)
-                                        /* VPE0 MIPS timer              */
-#define MSP_INT_BLKCP           (MSP_CIC_INTBASE + 18)
-                                        /* Block Copy                   */
-#define MSP_INT_UART0           (MSP_CIC_INTBASE + 19)
-                                        /* UART 0                       */
-#define MSP_INT_PCI             (MSP_CIC_INTBASE + 20)
-                                        /* PCI subsystem                */
-#define MSP_INT_EXT6            (MSP_CIC_INTBASE + 21)
-                                        /* External interrupt 5         */
-#define MSP_INT_PCI_MSI         (MSP_CIC_INTBASE + 22)
-                                        /* PCI Message Signal           */
-#define MSP_INT_CIC_SAR         (MSP_CIC_INTBASE + 23)
-                                        /* Cascaded ADSL2+ SAR IRQ      */
-#define MSP_INT_DSL             (MSP_CIC_INTBASE + 24)
-                                        /* ADSL2+ IRQ                   */
-#define MSP_INT_CIC_ERR         (MSP_CIC_INTBASE + 25)
-                                        /* SLP error condition          */
-#define MSP_INT_VPE1_TIMER      (MSP_CIC_INTBASE + 26)
-                                        /* VPE1 MIPS timer              */
-#define MSP_INT_VPE0_PC         (MSP_CIC_INTBASE + 27)
-                                        /* VPE0 Performance counter     */
-#define MSP_INT_VPE1_PC         (MSP_CIC_INTBASE + 28)
-                                        /* VPE1 Performance counter     */
-#define MSP_INT_EXT7            (MSP_CIC_INTBASE + 29)
-                                        /* External interrupt 5         */
-#define MSP_INT_VPE0_SW         (MSP_CIC_INTBASE + 30)
-                                        /* VPE0 Software interrupt      */
-#define MSP_INT_VPE1_SW         (MSP_CIC_INTBASE + 31)
-                                        /* VPE0 Software interrupt      */
-
-/*
- * IRQs cascaded on CIC PER interrupt (MSP_INT_PER)
- */
-#define MSP_PER_INTBASE         (MSP_CIC_INTBASE + 32)
-/* Reserved                                        0-1                  */
-#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
-                                        /* UART 1                       */
-/* Reserved                                        3-5                  */
-#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
-                                        /* 2-wire                       */
-#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
-                                        /* Peripheral timer block out 0 */
-#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
-                                        /* Peripheral timer block out 1 */
-/* Reserved                                        9                    */
-#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
-                                        /* SPI RX complete              */
-#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
-                                        /* SPI TX complete              */
-#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
-                                        /* GPIO                         */
-#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
-                                        /* Peripheral error             */
-/* Reserved                                        14-31                */
-
-#endif /* !_MSP_CIC_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
deleted file mode 100644
index 1d9f05474820..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_int.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Defines for the MSP interrupt handlers.
- *
- * Copyright (C) 2005, PMC-Sierra, Inc.  All rights reserved.
- * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- */
-
-#ifndef _MSP_INT_H
-#define _MSP_INT_H
-
-/*
- * The PMC-Sierra MSP product line has at least two different interrupt
- * controllers, the SLP register based scheme and the CIC interrupt
- * controller block mechanism.  This file distinguishes between them
- * so that devices see a uniform interface.
- */
-
-#if defined(CONFIG_IRQ_MSP_SLP)
-        #include "msp_slp_int.h"
-#elif defined(CONFIG_IRQ_MSP_CIC)
-        #include "msp_cic_int.h"
-#else
-        #error "What sort of interrupt controller does *your* MSP have?"
-#endif
-
-#endif /* !_MSP_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h b/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
deleted file mode 100644
index 415606903617..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_pci.h
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2000-2006 PMC-Sierra INC.
- *
- *     This program is free software; you can redistribute it
- *     and/or modify it under the terms of the GNU General
- *     Public License as published by the Free Software
- *     Foundation; either version 2 of the License, or (at your
- *     option) any later version.
- *
- *     This program is distributed in the hope that it will be
- *     useful, but WITHOUT ANY WARRANTY; without even the implied
- *     warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR
- *     PURPOSE.  See the GNU General Public License for more
- *     details.
- *
- *     You should have received a copy of the GNU General Public
- *     License along with this program; if not, write to the Free
- *     Software Foundation, Inc., 675 Mass Ave, Cambridge, MA
- *     02139, USA.
- *
- * PMC-SIERRA INC. DISCLAIMS ANY LIABILITY OF ANY KIND
- * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS
- * SOFTWARE.
- */
-
-#ifndef _MSP_PCI_H_
-#define _MSP_PCI_H_
-
-#define MSP_HAS_PCI(ID) (((u32)(ID) <= 0x4236) && ((u32)(ID) >= 0x4220))
-
-/*
- * It is convenient to program the OATRAN register so that
- * Athena virtual address space and PCI address space are
- * the same. This is not a requirement, just a convenience.
- *
- * The only hard restrictions on the value of OATRAN is that
- * OATRAN must not be programmed to allow translated memory
- * addresses to fall within the lowest 512MB of
- * PCI address space. This region is hardcoded
- * for use as Athena PCI Host Controller target
- * access memory space to the Athena's SDRAM.
- *
- * Note that OATRAN applies only to memory accesses, not
- * to I/O accesses.
- *
- * To program OATRAN to make Athena virtual address space
- * and PCI address space have the same values, OATRAN
- * is to be programmed to 0xB8000000. The top seven
- * bits of the value mimic the seven bits clipped off
- * by the PCI Host controller.
- *
- * With OATRAN at the said value, when the CPU does
- * an access to its virtual address at, say 0xB900_5000,
- * the address appearing on the PCI bus will be
- * 0xB900_5000.
- *    - Michael Penner
- */
-#define MSP_PCI_OATRAN          0xB8000000UL
-
-#define MSP_PCI_SPACE_BASE      (MSP_PCI_OATRAN + 0x1002000UL)
-#define MSP_PCI_SPACE_SIZE      (0x3000000UL - 0x2000)
-#define MSP_PCI_SPACE_END \
-                (MSP_PCI_SPACE_BASE + MSP_PCI_SPACE_SIZE - 1)
-#define MSP_PCI_IOSPACE_BASE    (MSP_PCI_OATRAN + 0x1001000UL)
-#define MSP_PCI_IOSPACE_SIZE    0x1000
-#define MSP_PCI_IOSPACE_END  \
-                (MSP_PCI_IOSPACE_BASE + MSP_PCI_IOSPACE_SIZE - 1)
-
-/* IRQ for PCI status interrupts */
-#define PCI_STAT_IRQ    20
-
-#define QFLUSH_REG_1    0xB7F40000
-
-typedef volatile unsigned int pcireg;
-typedef void * volatile ppcireg;
-
-struct pci_block_copy
-{
-    pcireg   unused1; /* +0x00 */
-    pcireg   unused2; /* +0x04 */
-    ppcireg  unused3; /* +0x08 */
-    ppcireg  unused4; /* +0x0C */
-    pcireg   unused5; /* +0x10 */
-    pcireg   unused6; /* +0x14 */
-    pcireg   unused7; /* +0x18 */
-    ppcireg  unused8; /* +0x1C */
-    ppcireg  unused9; /* +0x20 */
-    pcireg   unusedA; /* +0x24 */
-    ppcireg  unusedB; /* +0x28 */
-    ppcireg  unusedC; /* +0x2C */
-};
-
-enum
-{
-    config_device_vendor,  /* 0 */
-    config_status_command, /* 1 */
-    config_class_revision, /* 2 */
-    config_BIST_header_latency_cache, /* 3 */
-    config_BAR0,           /* 4 */
-    config_BAR1,           /* 5 */
-    config_BAR2,           /* 6 */
-    config_not_used7,      /* 7 */
-    config_not_used8,      /* 8 */
-    config_not_used9,      /* 9 */
-    config_CIS,            /* 10 */
-    config_subsystem,      /* 11 */
-    config_not_used12,     /* 12 */
-    config_capabilities,   /* 13 */
-    config_not_used14,     /* 14 */
-    config_lat_grant_irq,  /* 15 */
-    config_message_control,/* 16 */
-    config_message_addr,   /* 17 */
-    config_message_data,   /* 18 */
-    config_VPD_addr,       /* 19 */
-    config_VPD_data,       /* 20 */
-    config_maxregs         /* 21 - number of registers */
-};
-
-struct msp_pci_regs
-{
-    pcireg hop_unused_00; /* +0x00 */
-    pcireg hop_unused_04; /* +0x04 */
-    pcireg hop_unused_08; /* +0x08 */
-    pcireg hop_unused_0C; /* +0x0C */
-    pcireg hop_unused_10; /* +0x10 */
-    pcireg hop_unused_14; /* +0x14 */
-    pcireg hop_unused_18; /* +0x18 */
-    pcireg hop_unused_1C; /* +0x1C */
-    pcireg hop_unused_20; /* +0x20 */
-    pcireg hop_unused_24; /* +0x24 */
-    pcireg hop_unused_28; /* +0x28 */
-    pcireg hop_unused_2C; /* +0x2C */
-    pcireg hop_unused_30; /* +0x30 */
-    pcireg hop_unused_34; /* +0x34 */
-    pcireg if_control;    /* +0x38 */
-    pcireg oatran;        /* +0x3C */
-    pcireg reset_ctl;     /* +0x40 */
-    pcireg config_addr;   /* +0x44 */
-    pcireg hop_unused_48; /* +0x48 */
-    pcireg msg_signaled_int_status; /* +0x4C */
-    pcireg msg_signaled_int_mask;   /* +0x50 */
-    pcireg if_status;     /* +0x54 */
-    pcireg if_mask;       /* +0x58 */
-    pcireg hop_unused_5C; /* +0x5C */
-    pcireg hop_unused_60; /* +0x60 */
-    pcireg hop_unused_64; /* +0x64 */
-    pcireg hop_unused_68; /* +0x68 */
-    pcireg hop_unused_6C; /* +0x6C */
-    pcireg hop_unused_70; /* +0x70 */
-
-    struct pci_block_copy pci_bc[2] __attribute__((aligned(64)));
-
-    pcireg error_hdr1; /* +0xE0 */
-    pcireg error_hdr2; /* +0xE4 */
-
-    pcireg config[config_maxregs] __attribute__((aligned(256)));
-
-};
-
-#define BPCI_CFGADDR_BUSNUM_SHF 16
-#define BPCI_CFGADDR_FUNCTNUM_SHF 8
-#define BPCI_CFGADDR_REGNUM_SHF 2
-#define BPCI_CFGADDR_ENABLE (1<<31)
-
-#define BPCI_IFCONTROL_RTO (1<<20) /* Retry timeout */
-#define BPCI_IFCONTROL_HCE (1<<16) /* Host configuration enable */
-#define BPCI_IFCONTROL_CTO_SHF 12  /* Shift count for CTO bits */
-#define BPCI_IFCONTROL_SE  (1<<5)  /* Enable exceptions on errors */
-#define BPCI_IFCONTROL_BIST (1<<4) /* Use BIST in per. mode */
-#define BPCI_IFCONTROL_CAP (1<<3)  /* Enable capabilities */
-#define BPCI_IFCONTROL_MMC_SHF 0   /* Shift count for MMC bits */
-
-#define BPCI_IFSTATUS_MGT  (1<<8)  /* Master Grant timeout */
-#define BPCI_IFSTATUS_MTT  (1<<9)  /* Master TRDY timeout */
-#define BPCI_IFSTATUS_MRT  (1<<10) /* Master retry timeout */
-#define BPCI_IFSTATUS_BC0F (1<<13) /* Block copy 0 fault */
-#define BPCI_IFSTATUS_BC1F (1<<14) /* Block copy 1 fault */
-#define BPCI_IFSTATUS_PCIU (1<<15) /* PCI unable to respond */
-#define BPCI_IFSTATUS_BSIZ (1<<16) /* PCI access with illegal size */
-#define BPCI_IFSTATUS_BADD (1<<17) /* PCI access with illegal addr */
-#define BPCI_IFSTATUS_RTO  (1<<18) /* Retry time out */
-#define BPCI_IFSTATUS_SER  (1<<19) /* System error */
-#define BPCI_IFSTATUS_PER  (1<<20) /* Parity error */
-#define BPCI_IFSTATUS_LCA  (1<<21) /* Local CPU abort */
-#define BPCI_IFSTATUS_MEM  (1<<22) /* Memory prot. violation */
-#define BPCI_IFSTATUS_ARB  (1<<23) /* Arbiter timed out */
-#define BPCI_IFSTATUS_STA  (1<<27) /* Signaled target abort */
-#define BPCI_IFSTATUS_TA   (1<<28) /* Target abort */
-#define BPCI_IFSTATUS_MA   (1<<29) /* Master abort */
-#define BPCI_IFSTATUS_PEI  (1<<30) /* Parity error as initiator */
-#define BPCI_IFSTATUS_PET  (1<<31) /* Parity error as target */
-
-#define BPCI_RESETCTL_PR (1<<0)    /* True if reset asserted */
-#define BPCI_RESETCTL_RT (1<<4)    /* Release time */
-#define BPCI_RESETCTL_CT (1<<8)    /* Config time */
-#define BPCI_RESETCTL_PE (1<<12)   /* PCI enabled */
-#define BPCI_RESETCTL_HM (1<<13)   /* PCI host mode */
-#define BPCI_RESETCTL_RI (1<<14)   /* PCI reset in */
-
-extern struct msp_pci_regs msp_pci_regs
-                        __attribute__((section(".register")));
-extern unsigned long msp_pci_config_space
-                        __attribute__((section(".register")));
-
-#endif /* !_MSP_PCI_H_ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h b/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
deleted file mode 100644
index 14ca7dc382a8..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_prom.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*
- * MIPS boards bootprom interface for the Linux kernel.
- *
- * Copyright (C) 2000 MIPS Technologies, Inc.  All rights reserved.
- * Author: Carsten Langgaard, carstenl@mips.com
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- */
-
-#ifndef _ASM_MSP_PROM_H
-#define _ASM_MSP_PROM_H
-
-#include <linux/types.h>
-
-#define DEVICEID                        "deviceid"
-#define FEATURES                        "features"
-#define PROM_ENV                        "prom_env"
-#define PROM_ENV_FILE                   "/proc/"PROM_ENV
-#define PROM_ENV_SIZE                   256
-
-#define CPU_DEVID_FAMILY                0x0000ff00
-#define CPU_DEVID_REVISION              0x000000ff
-
-#define FPGA_IS_POLO(revision) \
-                (((revision >= 0xb0) && (revision < 0xd0)))
-#define FPGA_IS_5000(revision) \
-                ((revision >= 0x80) && (revision <= 0x90))
-#define FPGA_IS_ZEUS(revision)          ((revision < 0x7f))
-#define FPGA_IS_DUET(revision) \
-                (((revision >= 0xa0) && (revision < 0xb0)))
-#define FPGA_IS_MSP4200(revision)       ((revision >= 0xd0))
-#define FPGA_IS_MSP7100(revision)       ((revision >= 0xd0))
-
-#define MACHINE_TYPE_POLO               "POLO"
-#define MACHINE_TYPE_DUET               "DUET"
-#define MACHINE_TYPE_ZEUS               "ZEUS"
-#define MACHINE_TYPE_MSP2000REVB        "MSP2000REVB"
-#define MACHINE_TYPE_MSP5000            "MSP5000"
-#define MACHINE_TYPE_MSP4200            "MSP4200"
-#define MACHINE_TYPE_MSP7120            "MSP7120"
-#define MACHINE_TYPE_MSP7130            "MSP7130"
-#define MACHINE_TYPE_OTHER              "OTHER"
-
-#define MACHINE_TYPE_POLO_FPGA          "POLO-FPGA"
-#define MACHINE_TYPE_DUET_FPGA          "DUET-FPGA"
-#define MACHINE_TYPE_ZEUS_FPGA          "ZEUS_FPGA"
-#define MACHINE_TYPE_MSP2000REVB_FPGA   "MSP2000REVB-FPGA"
-#define MACHINE_TYPE_MSP5000_FPGA       "MSP5000-FPGA"
-#define MACHINE_TYPE_MSP4200_FPGA       "MSP4200-FPGA"
-#define MACHINE_TYPE_MSP7100_FPGA       "MSP7100-FPGA"
-#define MACHINE_TYPE_OTHER_FPGA         "OTHER-FPGA"
-
-/* Device Family definitions */
-#define FAMILY_FPGA                     0x0000
-#define FAMILY_ZEUS                     0x1000
-#define FAMILY_POLO                     0x2000
-#define FAMILY_DUET                     0x4000
-#define FAMILY_TRIAD                    0x5000
-#define FAMILY_MSP4200                  0x4200
-#define FAMILY_MSP4200_FPGA             0x4f00
-#define FAMILY_MSP7100                  0x7100
-#define FAMILY_MSP7100_FPGA             0x7f00
-
-/* Device Type definitions */
-#define TYPE_MSP7120                    0x7120
-#define TYPE_MSP7130                    0x7130
-
-#define ENET_KEY                'E'
-#define ENETTXD_KEY             'e'
-#define PCI_KEY                 'P'
-#define PCIMUX_KEY              'p'
-#define SEC_KEY                 'S'
-#define SPAD_KEY                'D'
-#define TDM_KEY                 'T'
-#define ZSP_KEY                 'Z'
-
-#define FEATURE_NOEXIST         '-'
-#define FEATURE_EXIST           '+'
-
-#define ENET_MII                'M'
-#define ENET_RMII               'R'
-
-#define ENETTXD_FALLING         'F'
-#define ENETTXD_RISING          'R'
-
-#define PCI_HOST                'H'
-#define PCI_PERIPHERAL          'P'
-
-#define PCIMUX_FULL             'F'
-#define PCIMUX_SINGLE           'S'
-
-#define SEC_DUET                'D'
-#define SEC_POLO                'P'
-#define SEC_SLOW                'S'
-#define SEC_TRIAD               'T'
-
-#define SPAD_POLO               'P'
-
-#define TDM_DUET                'D'     /* DUET TDMs might exist */
-#define TDM_POLO                'P'     /* POLO TDMs might exist */
-#define TDM_TRIAD               'T'     /* TRIAD TDMs might exist */
-
-#define ZSP_DUET                'D'     /* one DUET zsp engine */
-#define ZSP_TRIAD               'T'     /* two TRIAD zsp engines */
-
-extern char *prom_getcmdline(void);
-extern char *prom_getenv(char *name);
-extern void prom_init_cmdline(void);
-extern void prom_meminit(void);
-extern void prom_fixup_mem_map(unsigned long start_mem,
-                               unsigned long end_mem);
-
-#ifdef CONFIG_MTD_PMC_MSP_RAMROOT
-extern bool get_ramroot(void **start, unsigned long *size);
-#endif
-
-extern int get_ethernet_addr(char *ethaddr_name, char *ethernet_addr);
-extern unsigned long get_deviceid(void);
-extern char identify_enet(unsigned long interface_num);
-extern char identify_enetTxD(unsigned long interface_num);
-extern char identify_pci(void);
-extern char identify_sec(void);
-extern char identify_spad(void);
-extern char identify_sec(void);
-extern char identify_tdm(void);
-extern char identify_zsp(void);
-extern unsigned long identify_family(void);
-extern unsigned long identify_revision(void);
-
-/*
- * The following macro calls prom_printf and puts the format string
- * into an init section so it can be reclaimed.
- */
-#define ppfinit(f, x...) \
-        do { \
-                static char _f[] __initdata = KERN_INFO f; \
-                printk(_f, ## x); \
-        } while (0)
-
-/* Memory descriptor management. */
-#define PROM_MAX_PMEMBLOCKS    7        /* 6 used */
-
-enum yamon_memtypes {
-        yamon_dontuse,
-        yamon_prom,
-        yamon_free,
-};
-
-struct prom_pmemblock {
-        unsigned long base; /* Within KSEG0. */
-        unsigned int size;  /* In bytes. */
-        unsigned int type;  /* free or prom memory */
-};
-
-extern int prom_argc;
-extern char **prom_argv;
-extern char **prom_envp;
-extern int *prom_vec;
-extern struct prom_pmemblock *prom_getmdesc(void);
-
-#endif /* !_ASM_MSP_PROM_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
deleted file mode 100644
index 60a5a38dd5b2..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_regops.h
+++ /dev/null
@@ -1,236 +0,0 @@
-/*
- * SMP/VPE-safe functions to access "registers" (see note).
- *
- * NOTES:
-* - These macros use ll/sc instructions, so it is your responsibility to
- * ensure these are available on your platform before including this file.
- * - The MIPS32 spec states that ll/sc results are undefined for uncached
- * accesses. This means they can't be used on HW registers accessed
- * through kseg1. Code which requires these macros for this purpose must
- * front-end the registers with cached memory "registers" and have a single
- * thread update the actual HW registers.
- * - A maximum of 2k of code can be inserted between ll and sc. Every
- * memory accesses between the instructions will increase the chance of
- * sc failing and having to loop.
- * - When using custom_read_reg32/custom_write_reg32 only perform the
- * necessary logical operations on the register value in between these
- * two calls. All other logic should be performed before the first call.
-  * - There is a bug on the R10000 chips which has a workaround. If you
- * are affected by this bug, make sure to define the symbol 'R10000_LLSC_WAR'
- * to be non-zero.  If you are using this header from within linux, you may
- * include <asm/war.h> before including this file to have this defined
- * appropriately for you.
- *
- * Copyright 2005-2007 PMC-Sierra, Inc.
- *
- *  This program is free software; you can redistribute  it and/or modify it
- *  under  the terms of  the GNU General  Public License as published by the
- *  Free Software Foundation;  either version 2 of the  License, or (at your
- *  option) any later version.
- *
- *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
- *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN NO
- *  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- *  LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF USE,
- *  DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- *  THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
- *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
- *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the  GNU General Public License along
- *  with this program; if not, write  to the Free Software Foundation, Inc., 675
- *  Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef __ASM_REGOPS_H__
-#define __ASM_REGOPS_H__
-
-#include <linux/types.h>
-
-#include <asm/war.h>
-
-#ifndef R10000_LLSC_WAR
-#define R10000_LLSC_WAR 0
-#endif
-
-#if R10000_LLSC_WAR == 1
-#define __beqz  "beqzl  "
-#else
-#define __beqz  "beqz   "
-#endif
-
-#ifndef _LINUX_TYPES_H
-typedef unsigned int u32;
-#endif
-
-/*
- * Sets all the masked bits to the corresponding value bits
- */
-static inline void set_value_reg32(volatile u32 *const addr,
-                                        u32 const mask,
-                                        u32 const value)
-{
-        u32 temp;
-
-        __asm__ __volatile__(
-        "       .set    push                            \n"
-        "       .set    mips3                           \n"
-        "1:     ll      %0, %1  # set_value_reg32       \n"
-        "       and     %0, %2                          \n"
-        "       or      %0, %3                          \n"
-        "       sc      %0, %1                          \n"
-        "       "__beqz"%0, 1b                          \n"
-        "       nop                                     \n"
-        "       .set    pop                             \n"
-        : "=&r" (temp), "=m" (*addr)
-        : "ir" (~mask), "ir" (value), "m" (*addr));
-}
-
-/*
- * Sets all the masked bits to '1'
- */
-static inline void set_reg32(volatile u32 *const addr,
-                                u32 const mask)
-{
-        u32 temp;
-
-        __asm__ __volatile__(
-        "       .set    push                            \n"
-        "       .set    mips3                           \n"
-        "1:     ll      %0, %1          # set_reg32     \n"
-        "       or      %0, %2                          \n"
-        "       sc      %0, %1                          \n"
-        "       "__beqz"%0, 1b                          \n"
-        "       nop                                     \n"
-        "       .set    pop                             \n"
-        : "=&r" (temp), "=m" (*addr)
-        : "ir" (mask), "m" (*addr));
-}
-
-/*
- * Sets all the masked bits to '0'
- */
-static inline void clear_reg32(volatile u32 *const addr,
-                                u32 const mask)
-{
-        u32 temp;
-
-        __asm__ __volatile__(
-        "       .set    push                            \n"
-        "       .set    mips3                           \n"
-        "1:     ll      %0, %1          # clear_reg32   \n"
-        "       and     %0, %2                          \n"
-        "       sc      %0, %1                          \n"
-        "       "__beqz"%0, 1b                          \n"
-        "       nop                                     \n"
-        "       .set    pop                             \n"
-        : "=&r" (temp), "=m" (*addr)
-        : "ir" (~mask), "m" (*addr));
-}
-
-/*
- * Toggles all masked bits from '0' to '1' and '1' to '0'
- */
-static inline void toggle_reg32(volatile u32 *const addr,
-                                u32 const mask)
-{
-        u32 temp;
-
-        __asm__ __volatile__(
-        "       .set    push                            \n"
-        "       .set    mips3                           \n"
-        "1:     ll      %0, %1          # toggle_reg32  \n"
-        "       xor     %0, %2                          \n"
-        "       sc      %0, %1                          \n"
-        "       "__beqz"%0, 1b                          \n"
-        "       nop                                     \n"
-        "       .set    pop                             \n"
-        : "=&r" (temp), "=m" (*addr)
-        : "ir" (mask), "m" (*addr));
-}
-
-/*
- * Read all masked bits others are returned as '0'
- */
-static inline u32 read_reg32(volatile u32 *const addr,
-                                u32 const mask)
-{
-        u32 temp;
-
-        __asm__ __volatile__(
-        "       .set    push                            \n"
-        "       .set    noreorder                       \n"
-        "       lw      %0, %1          # read          \n"
-        "       and     %0, %2          # mask          \n"
-        "       .set    pop                             \n"
-        : "=&r" (temp)
-        : "m" (*addr), "ir" (mask));
-
-        return temp;
-}
-
-/*
- * blocking_read_reg32 - Read address with blocking load
- *
- * Uncached writes need to be read back to ensure they reach RAM.
- * The returned value must be 'used' to prevent from becoming a
- * non-blocking load.
- */
-static inline u32 blocking_read_reg32(volatile u32 *const addr)
-{
-        u32 temp;
-
-        __asm__ __volatile__(
-        "       .set    push                            \n"
-        "       .set    noreorder                       \n"
-        "       lw      %0, %1          # read          \n"
-        "       move    %0, %0          # block         \n"
-        "       .set    pop                             \n"
-        : "=&r" (temp)
-        : "m" (*addr));
-
-        return temp;
-}
-
-/*
- * For special strange cases only:
- *
- * If you need custom processing within a ll/sc loop, use the following macros
- * VERY CAREFULLY:
- *
- *   u32 tmp;                           <-- Define a variable to hold the data
- *
- *   custom_read_reg32(address, tmp);   <-- Reads the address and put the value
- *                                              in the 'tmp' variable given
- *
- *      From here on out, you are (basicly) atomic, so don't do anything too
- *      fancy!
- *      Also, this code may loop if the end of this block fails to write
- *      everything back safely due do the other CPU, so do NOT do anything
- *      with side-effects!
- *
- *   custom_write_reg32(address, tmp);  <-- Writes back 'tmp' safely.
- */
-#define custom_read_reg32(address, tmp)                         \
-        __asm__ __volatile__(                                   \
-        "       .set    push                            \n"     \
-        "       .set    mips3                           \n"     \
-        "1:     ll      %0, %1  #custom_read_reg32      \n"     \
-        "       .set    pop                             \n"     \
-        : "=r" (tmp), "=m" (*address)                           \
-        : "m" (*address))
-
-#define custom_write_reg32(address, tmp)                        \
-        __asm__ __volatile__(                                   \
-        "       .set    push                            \n"     \
-        "       .set    mips3                           \n"     \
-        "       sc      %0, %1  #custom_write_reg32     \n"     \
-        "       "__beqz"%0, 1b                          \n"     \
-        "       nop                                     \n"     \
-        "       .set    pop                             \n"     \
-        : "=&r" (tmp), "=m" (*address)                          \
-        : "0" (tmp), "m" (*address))
-
-#endif  /* __ASM_REGOPS_H__ */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h b/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
deleted file mode 100644
index 603eb737b4a8..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_regs.h
+++ /dev/null
@@ -1,663 +0,0 @@
-/*
- * Defines for the address space, registers and register configuration
- * (bit masks, access macros etc) for the PMC-Sierra line of MSP products.
- * This file contains addess maps for all the devices in the line of
- * products but only has register definitions and configuration masks for
- * registers which aren't definitely associated with any device.  Things
- * like clock settings, reset access, the ELB etc.  Individual device
- * drivers will reference the appropriate XXX_BASE value defined here
- * and have individual registers offset from that.
- *
- * Copyright (C) 2005-2007 PMC-Sierra, Inc.  All rights reserved.
- * Author: Andrew Hughes, Andrew_Hughes@pmc-sierra.com
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- */
-
-#include <asm/addrspace.h>
-#include <linux/types.h>
-
-#ifndef _ASM_MSP_REGS_H
-#define _ASM_MSP_REGS_H
-
-/*
- ########################################################################
- #  Address space and device base definitions                           #
- ########################################################################
- */
-
-/*
- ***************************************************************************
- * System Logic and Peripherals (ELB, UART0, etc) device address space     *
- ***************************************************************************
- */
-#define MSP_SLP_BASE            0x1c000000
-                                        /* System Logic and Peripherals */
-#define MSP_RST_BASE            (MSP_SLP_BASE + 0x10)
-                                        /* System reset register base   */
-#define MSP_RST_SIZE            0x0C    /* System reset register space  */
-
-#define MSP_WTIMER_BASE         (MSP_SLP_BASE + 0x04C)
-                                        /* watchdog timer base          */
-#define MSP_ITIMER_BASE         (MSP_SLP_BASE + 0x054)
-                                        /* internal timer base          */
-#define MSP_UART0_BASE          (MSP_SLP_BASE + 0x100)
-                                        /* UART0 controller base        */
-#define MSP_BCPY_CTRL_BASE      (MSP_SLP_BASE + 0x120)
-                                        /* Block Copy controller base   */
-#define MSP_BCPY_DESC_BASE      (MSP_SLP_BASE + 0x160)
-                                        /* Block Copy descriptor base   */
-
-/*
- ***************************************************************************
- * PCI address space                                                       *
- ***************************************************************************
- */
-#define MSP_PCI_BASE            0x19000000
-
-/*
- ***************************************************************************
- * MSbus device address space                                              *
- ***************************************************************************
- */
-#define MSP_MSB_BASE            0x18000000
-                                        /* MSbus address start          */
-#define MSP_PER_BASE            (MSP_MSB_BASE + 0x400000)
-                                        /* Peripheral device registers  */
-#define MSP_MAC0_BASE           (MSP_MSB_BASE + 0x600000)
-                                        /* MAC A device registers       */
-#define MSP_MAC1_BASE           (MSP_MSB_BASE + 0x700000)
-                                        /* MAC B device registers       */
-#define MSP_MAC_SIZE            0xE0    /* MAC register space           */
-
-#define MSP_SEC_BASE            (MSP_MSB_BASE + 0x800000)
-                                        /* Security Engine registers    */
-#define MSP_MAC2_BASE           (MSP_MSB_BASE + 0x900000)
-                                        /* MAC C device registers       */
-#define MSP_ADSL2_BASE          (MSP_MSB_BASE + 0xA80000)
-                                        /* ADSL2 device registers       */
-#define MSP_USB_BASE            (MSP_MSB_BASE + 0xB40000)
-                                        /* USB device registers         */
-#define MSP_USB_BASE_START      (MSP_MSB_BASE + 0xB40100)
-                                        /* USB device registers         */
-#define MSP_USB_BASE_END        (MSP_MSB_BASE + 0xB401FF)
-                                        /* USB device registers         */
-#define MSP_CPUIF_BASE          (MSP_MSB_BASE + 0xC00000)
-                                        /* CPU interface registers      */
-
-/* Devices within the MSbus peripheral block */
-#define MSP_UART1_BASE          (MSP_PER_BASE + 0x030)
-                                        /* UART1 controller base        */
-#define MSP_SPI_BASE            (MSP_PER_BASE + 0x058)
-                                        /* SPI/MPI control registers    */
-#define MSP_TWI_BASE            (MSP_PER_BASE + 0x090)
-                                        /* Two-wire control registers   */
-#define MSP_PTIMER_BASE         (MSP_PER_BASE + 0x0F0)
-                                        /* Programmable timer control   */
-
-/*
- ***************************************************************************
- * Physical Memory configuration address space                             *
- ***************************************************************************
- */
-#define MSP_MEM_CFG_BASE        0x17f00000
-
-#define MSP_MEM_INDIRECT_CTL_10 0x10
-
-/*
- * Notes:
- *  1) The SPI registers are split into two blocks, one offset from the
- *     MSP_SPI_BASE by 0x00 and the other offset from the MSP_SPI_BASE by
- *     0x68.  The SPI driver definitions for the register must be aware
- *     of this.
- *  2) The block copy engine register are divided into two regions, one
- *     for the control/configuration of the engine proper and one for the
- *     values of the descriptors used in the copy process.  These have
- *     different base defines (CTRL_BASE vs DESC_BASE)
- *  3) These constants are for physical addresses which means that they
- *     work correctly with "ioremap" and friends.  This means that device
- *     drivers will need to remap these addresses using ioremap and perhaps
- *     the readw/writew macros.  Or they could use the regptr() macro
- *     defined below, but the readw/writew calls are the correct thing.
- *  4) The UARTs have an additional status register offset from the base
- *     address.  This register isn't used in the standard 8250 driver but
- *     may be used in other software.  Consult the hardware datasheet for
- *     offset details.
- *  5) For some unknown reason the security engine (MSP_SEC_BASE) registers
- *     start at an offset of 0x84 from the base address but the block of
- *     registers before this is reserved for the security engine.  The
- *     driver will have to be aware of this but it makes the register
- *     definitions line up better with the documentation.
- */
-
-/*
- ########################################################################
- #  System register definitions.  Not associated with a specific device #
- ########################################################################
- */
-
-/*
- * This macro maps the physical register number into uncached space
- * and (for C code) casts it into a u32 pointer so it can be dereferenced
- * Normally these would be accessed with ioremap and readX/writeX, but
- * these are convenient for a lot of internal kernel code.
- */
-#ifdef __ASSEMBLER__
-        #define regptr(addr) (KSEG1ADDR(addr))
-#else
-        #define regptr(addr) ((volatile u32 *const)(KSEG1ADDR(addr)))
-#endif
-
-/*
- ***************************************************************************
- * System Logic and Peripherals (RESET, ELB, etc) registers                *
- ***************************************************************************
- */
-
-/* System Control register definitions */
-#define DEV_ID_REG      regptr(MSP_SLP_BASE + 0x00)
-                                        /* Device-ID                 RO */
-#define FWR_ID_REG      regptr(MSP_SLP_BASE + 0x04)
-                                        /* Firmware-ID Register      RW */
-#define SYS_ID_REG0     regptr(MSP_SLP_BASE + 0x08)
-                                        /* System-ID Register-0      RW */
-#define SYS_ID_REG1     regptr(MSP_SLP_BASE + 0x0C)
-                                        /* System-ID Register-1      RW */
-
-/* System Reset register definitions */
-#define RST_STS_REG     regptr(MSP_SLP_BASE + 0x10)
-                                        /* System Reset Status       RO */
-#define RST_SET_REG     regptr(MSP_SLP_BASE + 0x14)
-                                        /* System Set Reset          WO */
-#define RST_CLR_REG     regptr(MSP_SLP_BASE + 0x18)
-                                        /* System Clear Reset        WO */
-
-/* System Clock Registers */
-#define PCI_SLP_REG     regptr(MSP_SLP_BASE + 0x1C)
-                                        /* PCI clock generator       RW */
-#define URT_SLP_REG     regptr(MSP_SLP_BASE + 0x20)
-                                        /* UART clock generator      RW */
-/* reserved                   (MSP_SLP_BASE + 0x24)                     */
-/* reserved                   (MSP_SLP_BASE + 0x28)                     */
-#define PLL1_SLP_REG    regptr(MSP_SLP_BASE + 0x2C)
-                                        /* PLL1 clock generator      RW */
-#define PLL0_SLP_REG    regptr(MSP_SLP_BASE + 0x30)
-                                        /* PLL0 clock generator      RW */
-#define MIPS_SLP_REG    regptr(MSP_SLP_BASE + 0x34)
-                                        /* MIPS clock generator      RW */
-#define VE_SLP_REG      regptr(MSP_SLP_BASE + 0x38)
-                                        /* Voice Eng clock generator RW */
-/* reserved                   (MSP_SLP_BASE + 0x3C)                     */
-#define MSB_SLP_REG     regptr(MSP_SLP_BASE + 0x40)
-                                        /* MS-Bus clock generator    RW */
-#define SMAC_SLP_REG    regptr(MSP_SLP_BASE + 0x44)
-                                        /* Sec & MAC clock generator RW */
-#define PERF_SLP_REG    regptr(MSP_SLP_BASE + 0x48)
-                                        /* Per & TDM clock generator RW */
-
-/* Interrupt Controller Registers */
-#define SLP_INT_STS_REG regptr(MSP_SLP_BASE + 0x70)
-                                        /* Interrupt status register RW */
-#define SLP_INT_MSK_REG regptr(MSP_SLP_BASE + 0x74)
-                                        /* Interrupt enable/mask     RW */
-#define SE_MBOX_REG     regptr(MSP_SLP_BASE + 0x78)
-                                        /* Security Engine mailbox   RW */
-#define VE_MBOX_REG     regptr(MSP_SLP_BASE + 0x7C)
-                                        /* Voice Engine mailbox      RW */
-
-/* ELB Controller Registers */
-#define CS0_CNFG_REG    regptr(MSP_SLP_BASE + 0x80)
-                                        /* ELB CS0 Configuration Reg    */
-#define CS0_ADDR_REG    regptr(MSP_SLP_BASE + 0x84)
-                                        /* ELB CS0 Base Address Reg     */
-#define CS0_MASK_REG    regptr(MSP_SLP_BASE + 0x88)
-                                        /* ELB CS0 Mask Register        */
-#define CS0_ACCESS_REG  regptr(MSP_SLP_BASE + 0x8C)
-                                        /* ELB CS0 access register      */
-
-#define CS1_CNFG_REG    regptr(MSP_SLP_BASE + 0x90)
-                                        /* ELB CS1 Configuration Reg    */
-#define CS1_ADDR_REG    regptr(MSP_SLP_BASE + 0x94)
-                                        /* ELB CS1 Base Address Reg     */
-#define CS1_MASK_REG    regptr(MSP_SLP_BASE + 0x98)
-                                        /* ELB CS1 Mask Register        */
-#define CS1_ACCESS_REG  regptr(MSP_SLP_BASE + 0x9C)
-                                        /* ELB CS1 access register      */
-
-#define CS2_CNFG_REG    regptr(MSP_SLP_BASE + 0xA0)
-                                        /* ELB CS2 Configuration Reg    */
-#define CS2_ADDR_REG    regptr(MSP_SLP_BASE + 0xA4)
-                                        /* ELB CS2 Base Address Reg     */
-#define CS2_MASK_REG    regptr(MSP_SLP_BASE + 0xA8)
-                                        /* ELB CS2 Mask Register        */
-#define CS2_ACCESS_REG  regptr(MSP_SLP_BASE + 0xAC)
-                                        /* ELB CS2 access register      */
-
-#define CS3_CNFG_REG    regptr(MSP_SLP_BASE + 0xB0)
-                                        /* ELB CS3 Configuration Reg    */
-#define CS3_ADDR_REG    regptr(MSP_SLP_BASE + 0xB4)
-                                        /* ELB CS3 Base Address Reg     */
-#define CS3_MASK_REG    regptr(MSP_SLP_BASE + 0xB8)
-                                        /* ELB CS3 Mask Register        */
-#define CS3_ACCESS_REG  regptr(MSP_SLP_BASE + 0xBC)
-                                        /* ELB CS3 access register      */
-
-#define CS4_CNFG_REG    regptr(MSP_SLP_BASE + 0xC0)
-                                        /* ELB CS4 Configuration Reg    */
-#define CS4_ADDR_REG    regptr(MSP_SLP_BASE + 0xC4)
-                                        /* ELB CS4 Base Address Reg     */
-#define CS4_MASK_REG    regptr(MSP_SLP_BASE + 0xC8)
-                                        /* ELB CS4 Mask Register        */
-#define CS4_ACCESS_REG  regptr(MSP_SLP_BASE + 0xCC)
-                                        /* ELB CS4 access register      */
-
-#define CS5_CNFG_REG    regptr(MSP_SLP_BASE + 0xD0)
-                                        /* ELB CS5 Configuration Reg    */
-#define CS5_ADDR_REG    regptr(MSP_SLP_BASE + 0xD4)
-                                        /* ELB CS5 Base Address Reg     */
-#define CS5_MASK_REG    regptr(MSP_SLP_BASE + 0xD8)
-                                        /* ELB CS5 Mask Register        */
-#define CS5_ACCESS_REG  regptr(MSP_SLP_BASE + 0xDC)
-                                        /* ELB CS5 access register      */
-
-/* reserved                            0xE0 - 0xE8                      */
-#define ELB_1PC_EN_REG  regptr(MSP_SLP_BASE + 0xEC)
-                                        /* ELB single PC card detect    */
-
-/* reserved                            0xF0 - 0xF8                      */
-#define ELB_CLK_CFG_REG regptr(MSP_SLP_BASE + 0xFC)
-                                        /* SDRAM read/ELB timing Reg    */
-
-/* Extended UART status registers */
-#define UART0_STATUS_REG        regptr(MSP_UART0_BASE + 0x0c0)
-                                        /* UART Status Register 0       */
-#define UART1_STATUS_REG        regptr(MSP_UART1_BASE + 0x170)
-                                        /* UART Status Register 1       */
-
-/* Performance monitoring registers */
-#define PERF_MON_CTRL_REG       regptr(MSP_SLP_BASE + 0x140)
-                                        /* Performance monitor control  */
-#define PERF_MON_CLR_REG        regptr(MSP_SLP_BASE + 0x144)
-                                        /* Performance monitor clear    */
-#define PERF_MON_CNTH_REG       regptr(MSP_SLP_BASE + 0x148)
-                                        /* Perf monitor counter high    */
-#define PERF_MON_CNTL_REG       regptr(MSP_SLP_BASE + 0x14C)
-                                        /* Perf monitor counter low     */
-
-/* System control registers */
-#define SYS_CTRL_REG            regptr(MSP_SLP_BASE + 0x150)
-                                        /* System control register      */
-#define SYS_ERR1_REG            regptr(MSP_SLP_BASE + 0x154)
-                                        /* System Error status 1        */
-#define SYS_ERR2_REG            regptr(MSP_SLP_BASE + 0x158)
-                                        /* System Error status 2        */
-#define SYS_INT_CFG_REG         regptr(MSP_SLP_BASE + 0x15C)
-                                        /* System Interrupt config      */
-
-/* Voice Engine Memory configuration */
-#define VE_MEM_REG              regptr(MSP_SLP_BASE + 0x17C)
-                                        /* Voice engine memory config   */
-
-/* CPU/SLP Error Status registers */
-#define CPU_ERR1_REG            regptr(MSP_SLP_BASE + 0x180)
-                                        /* CPU/SLP Error status 1       */
-#define CPU_ERR2_REG            regptr(MSP_SLP_BASE + 0x184)
-                                        /* CPU/SLP Error status 1       */
-
-#define EXTENDED_GPIO_REG       regptr(MSP_SLP_BASE + 0x188)
-                                        /* Extended GPIO register       */
-
-/* System Error registers */
-#define SLP_ERR_STS_REG         regptr(MSP_SLP_BASE + 0x190)
-                                        /* Int status for SLP errors    */
-#define SLP_ERR_MSK_REG         regptr(MSP_SLP_BASE + 0x194)
-                                        /* Int mask for SLP errors      */
-#define SLP_ELB_ERST_REG        regptr(MSP_SLP_BASE + 0x198)
-                                        /* External ELB reset           */
-#define SLP_BOOT_STS_REG        regptr(MSP_SLP_BASE + 0x19C)
-                                        /* Boot Status                  */
-
-/* Extended ELB addressing */
-#define CS0_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A0)
-                                        /* CS0 Extended address         */
-#define CS1_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A4)
-                                        /* CS1 Extended address         */
-#define CS2_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1A8)
-                                        /* CS2 Extended address         */
-#define CS3_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1AC)
-                                        /* CS3 Extended address         */
-/* reserved                                           0x1B0             */
-#define CS5_EXT_ADDR_REG        regptr(MSP_SLP_BASE + 0x1B4)
-                                        /* CS5 Extended address         */
-
-/* PLL Adjustment registers */
-#define PLL_LOCK_REG            regptr(MSP_SLP_BASE + 0x200)
-                                        /* PLL0 lock status             */
-#define PLL_ARST_REG            regptr(MSP_SLP_BASE + 0x204)
-                                        /* PLL Analog reset status      */
-#define PLL0_ADJ_REG            regptr(MSP_SLP_BASE + 0x208)
-                                        /* PLL0 Adjustment value        */
-#define PLL1_ADJ_REG            regptr(MSP_SLP_BASE + 0x20C)
-                                        /* PLL1 Adjustment value        */
-
-/*
- ***************************************************************************
- * Peripheral Register definitions                                         *
- ***************************************************************************
- */
-
-/* Peripheral status */
-#define PER_CTRL_REG            regptr(MSP_PER_BASE + 0x50)
-                                        /* Peripheral control register  */
-#define PER_STS_REG             regptr(MSP_PER_BASE + 0x54)
-                                        /* Peripheral status register   */
-
-/* SPI/MPI Registers */
-#define SMPI_TX_SZ_REG          regptr(MSP_PER_BASE + 0x58)
-                                        /* SPI/MPI Tx Size register     */
-#define SMPI_RX_SZ_REG          regptr(MSP_PER_BASE + 0x5C)
-                                        /* SPI/MPI Rx Size register     */
-#define SMPI_CTL_REG            regptr(MSP_PER_BASE + 0x60)
-                                        /* SPI/MPI Control register     */
-#define SMPI_MS_REG             regptr(MSP_PER_BASE + 0x64)
-                                        /* SPI/MPI Chip Select reg      */
-#define SMPI_CORE_DATA_REG      regptr(MSP_PER_BASE + 0xC0)
-                                        /* SPI/MPI Core Data reg        */
-#define SMPI_CORE_CTRL_REG      regptr(MSP_PER_BASE + 0xC4)
-                                        /* SPI/MPI Core Control reg     */
-#define SMPI_CORE_STAT_REG      regptr(MSP_PER_BASE + 0xC8)
-                                        /* SPI/MPI Core Status reg      */
-#define SMPI_CORE_SSEL_REG      regptr(MSP_PER_BASE + 0xCC)
-                                        /* SPI/MPI Core Ssel reg        */
-#define SMPI_FIFO_REG           regptr(MSP_PER_BASE + 0xD0)
-                                        /* SPI/MPI Data FIFO reg        */
-
-/* Peripheral Block Error Registers           */
-#define PER_ERR_STS_REG         regptr(MSP_PER_BASE + 0x70)
-                                        /* Error Bit Status Register    */
-#define PER_ERR_MSK_REG         regptr(MSP_PER_BASE + 0x74)
-                                        /* Error Bit Mask Register      */
-#define PER_HDR1_REG            regptr(MSP_PER_BASE + 0x78)
-                                        /* Error Header 1 Register      */
-#define PER_HDR2_REG            regptr(MSP_PER_BASE + 0x7C)
-                                        /* Error Header 2 Register      */
-
-/* Peripheral Block Interrupt Registers       */
-#define PER_INT_STS_REG         regptr(MSP_PER_BASE + 0x80)
-                                        /* Interrupt status register    */
-#define PER_INT_MSK_REG         regptr(MSP_PER_BASE + 0x84)
-                                        /* Interrupt Mask Register      */
-#define GPIO_INT_STS_REG        regptr(MSP_PER_BASE + 0x88)
-                                        /* GPIO interrupt status reg    */
-#define GPIO_INT_MSK_REG        regptr(MSP_PER_BASE + 0x8C)
-                                        /* GPIO interrupt MASK Reg      */
-
-/* POLO GPIO registers                        */
-#define POLO_GPIO_DAT1_REG      regptr(MSP_PER_BASE + 0x0E0)
-                                        /* Polo GPIO[8:0]  data reg     */
-#define POLO_GPIO_CFG1_REG      regptr(MSP_PER_BASE + 0x0E4)
-                                        /* Polo GPIO[7:0]  config reg   */
-#define POLO_GPIO_CFG2_REG      regptr(MSP_PER_BASE + 0x0E8)
-                                        /* Polo GPIO[15:8] config reg   */
-#define POLO_GPIO_OD1_REG       regptr(MSP_PER_BASE + 0x0EC)
-                                        /* Polo GPIO[31:0] output drive */
-#define POLO_GPIO_CFG3_REG      regptr(MSP_PER_BASE + 0x170)
-                                        /* Polo GPIO[23:16] config reg  */
-#define POLO_GPIO_DAT2_REG      regptr(MSP_PER_BASE + 0x174)
-                                        /* Polo GPIO[15:9]  data reg    */
-#define POLO_GPIO_DAT3_REG      regptr(MSP_PER_BASE + 0x178)
-                                        /* Polo GPIO[23:16]  data reg   */
-#define POLO_GPIO_DAT4_REG      regptr(MSP_PER_BASE + 0x17C)
-                                        /* Polo GPIO[31:24]  data reg   */
-#define POLO_GPIO_DAT5_REG      regptr(MSP_PER_BASE + 0x180)
-                                        /* Polo GPIO[39:32]  data reg   */
-#define POLO_GPIO_DAT6_REG      regptr(MSP_PER_BASE + 0x184)
-                                        /* Polo GPIO[47:40]  data reg   */
-#define POLO_GPIO_DAT7_REG      regptr(MSP_PER_BASE + 0x188)
-                                        /* Polo GPIO[54:48]  data reg   */
-#define POLO_GPIO_CFG4_REG      regptr(MSP_PER_BASE + 0x18C)
-                                        /* Polo GPIO[31:24] config reg  */
-#define POLO_GPIO_CFG5_REG      regptr(MSP_PER_BASE + 0x190)
-                                        /* Polo GPIO[39:32] config reg  */
-#define POLO_GPIO_CFG6_REG      regptr(MSP_PER_BASE + 0x194)
-                                        /* Polo GPIO[47:40] config reg  */
-#define POLO_GPIO_CFG7_REG      regptr(MSP_PER_BASE + 0x198)
-                                        /* Polo GPIO[54:48] config reg  */
-#define POLO_GPIO_OD2_REG       regptr(MSP_PER_BASE + 0x19C)
-                                        /* Polo GPIO[54:32] output drive */
-
-/* Generic GPIO registers                     */
-#define GPIO_DATA1_REG          regptr(MSP_PER_BASE + 0x170)
-                                        /* GPIO[1:0] data register      */
-#define GPIO_DATA2_REG          regptr(MSP_PER_BASE + 0x174)
-                                        /* GPIO[5:2] data register      */
-#define GPIO_DATA3_REG          regptr(MSP_PER_BASE + 0x178)
-                                        /* GPIO[9:6] data register      */
-#define GPIO_DATA4_REG          regptr(MSP_PER_BASE + 0x17C)
-                                        /* GPIO[15:10] data register    */
-#define GPIO_CFG1_REG           regptr(MSP_PER_BASE + 0x180)
-                                        /* GPIO[1:0] config register    */
-#define GPIO_CFG2_REG           regptr(MSP_PER_BASE + 0x184)
-                                        /* GPIO[5:2] config register    */
-#define GPIO_CFG3_REG           regptr(MSP_PER_BASE + 0x188)
-                                        /* GPIO[9:6] config register    */
-#define GPIO_CFG4_REG           regptr(MSP_PER_BASE + 0x18C)
-                                        /* GPIO[15:10] config register  */
-#define GPIO_OD_REG             regptr(MSP_PER_BASE + 0x190)
-                                        /* GPIO[15:0] output drive      */
-
-/*
- ***************************************************************************
- * CPU Interface register definitions                                      *
- ***************************************************************************
- */
-#define PCI_FLUSH_REG           regptr(MSP_CPUIF_BASE + 0x00)
-                                        /* PCI-SDRAM queue flush trigger */
-#define OCP_ERR1_REG            regptr(MSP_CPUIF_BASE + 0x04)
-                                        /* OCP Error Attribute 1        */
-#define OCP_ERR2_REG            regptr(MSP_CPUIF_BASE + 0x08)
-                                        /* OCP Error Attribute 2        */
-#define OCP_STS_REG             regptr(MSP_CPUIF_BASE + 0x0C)
-                                        /* OCP Error Status             */
-#define CPUIF_PM_REG            regptr(MSP_CPUIF_BASE + 0x10)
-                                        /* CPU policy configuration     */
-#define CPUIF_CFG_REG           regptr(MSP_CPUIF_BASE + 0x10)
-                                        /* Misc configuration options   */
-
-/* Central Interrupt Controller Registers */
-#define MSP_CIC_BASE            (MSP_CPUIF_BASE + 0x8000)
-                                        /* Central Interrupt registers  */
-#define CIC_EXT_CFG_REG         regptr(MSP_CIC_BASE + 0x00)
-                                        /* External interrupt config    */
-#define CIC_STS_REG             regptr(MSP_CIC_BASE + 0x04)
-                                        /* CIC Interrupt Status         */
-#define CIC_VPE0_MSK_REG        regptr(MSP_CIC_BASE + 0x08)
-                                        /* VPE0 Interrupt Mask          */
-#define CIC_VPE1_MSK_REG        regptr(MSP_CIC_BASE + 0x0C)
-                                        /* VPE1 Interrupt Mask          */
-#define CIC_TC0_MSK_REG         regptr(MSP_CIC_BASE + 0x10)
-                                        /* Thread Context 0 Int Mask    */
-#define CIC_TC1_MSK_REG         regptr(MSP_CIC_BASE + 0x14)
-                                        /* Thread Context 1 Int Mask    */
-#define CIC_TC2_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
-                                        /* Thread Context 2 Int Mask    */
-#define CIC_TC3_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
-                                        /* Thread Context 3 Int Mask    */
-#define CIC_TC4_MSK_REG         regptr(MSP_CIC_BASE + 0x18)
-                                        /* Thread Context 4 Int Mask    */
-#define CIC_PCIMSI_STS_REG      regptr(MSP_CIC_BASE + 0x18)
-#define CIC_PCIMSI_MSK_REG      regptr(MSP_CIC_BASE + 0x18)
-#define CIC_PCIFLSH_REG         regptr(MSP_CIC_BASE + 0x18)
-#define CIC_VPE0_SWINT_REG      regptr(MSP_CIC_BASE + 0x08)
-
-
-/*
- ***************************************************************************
- * Memory controller registers                                             *
- ***************************************************************************
- */
-#define MEM_CFG1_REG            regptr(MSP_MEM_CFG_BASE + 0x00)
-#define MEM_SS_ADDR             regptr(MSP_MEM_CFG_BASE + 0x00)
-#define MEM_SS_DATA             regptr(MSP_MEM_CFG_BASE + 0x04)
-#define MEM_SS_WRITE            regptr(MSP_MEM_CFG_BASE + 0x08)
-
-/*
- ***************************************************************************
- * PCI controller registers                                                *
- ***************************************************************************
- */
-#define PCI_BASE_REG            regptr(MSP_PCI_BASE + 0x00)
-#define PCI_CONFIG_SPACE_REG    regptr(MSP_PCI_BASE + 0x800)
-#define PCI_JTAG_DEVID_REG      regptr(MSP_SLP_BASE + 0x13c)
-
-/*
- ########################################################################
- #  Register content & macro definitions                                #
- ########################################################################
- */
-
-/*
- ***************************************************************************
- * DEV_ID defines                                                          *
- ***************************************************************************
- */
-#define DEV_ID_PCI_DIS          (1 << 26)       /* Set if PCI disabled */
-#define DEV_ID_PCI_HOST         (1 << 20)       /* Set if PCI host */
-#define DEV_ID_SINGLE_PC        (1 << 19)       /* Set if single PC Card */
-#define DEV_ID_FAMILY           (0xff << 8)     /* family ID code */
-#define POLO_ZEUS_SUB_FAMILY    (0x7  << 16)    /* sub family for Polo/Zeus */
-
-#define MSPFPGA_ID              (0x00  << 8)    /* you are on your own here */
-#define MSP5000_ID              (0x50  << 8)
-#define MSP4F00_ID              (0x4f  << 8)    /* FPGA version of MSP4200 */
-#define MSP4E00_ID              (0x4f  << 8)    /* FPGA version of MSP7120 */
-#define MSP4200_ID              (0x42  << 8)
-#define MSP4000_ID              (0x40  << 8)
-#define MSP2XXX_ID              (0x20  << 8)
-#define MSPZEUS_ID              (0x10  << 8)
-
-#define MSP2004_SUB_ID          (0x0   << 16)
-#define MSP2005_SUB_ID          (0x1   << 16)
-#define MSP2006_SUB_ID          (0x1   << 16)
-#define MSP2007_SUB_ID          (0x2   << 16)
-#define MSP2010_SUB_ID          (0x3   << 16)
-#define MSP2015_SUB_ID          (0x4   << 16)
-#define MSP2020_SUB_ID          (0x5   << 16)
-#define MSP2100_SUB_ID          (0x6   << 16)
-
-/*
- ***************************************************************************
- * RESET defines                                                           *
- ***************************************************************************
- */
-#define MSP_GR_RST              (0x01 << 0)     /* Global reset bit     */
-#define MSP_MR_RST              (0x01 << 1)     /* MIPS reset bit       */
-#define MSP_PD_RST              (0x01 << 2)     /* PVC DMA reset bit    */
-#define MSP_PP_RST              (0x01 << 3)     /* PVC reset bit        */
-/* reserved                                                             */
-#define MSP_EA_RST              (0x01 << 6)     /* Mac A reset bit      */
-#define MSP_EB_RST              (0x01 << 7)     /* Mac B reset bit      */
-#define MSP_SE_RST              (0x01 << 8)     /* Security Eng reset bit */
-#define MSP_PB_RST              (0x01 << 9)     /* Per block reset bit  */
-#define MSP_EC_RST              (0x01 << 10)    /* Mac C reset bit      */
-#define MSP_TW_RST              (0x01 << 11)    /* TWI reset bit        */
-#define MSP_SPI_RST             (0x01 << 12)    /* SPI/MPI reset bit    */
-#define MSP_U1_RST              (0x01 << 13)    /* UART1 reset bit      */
-#define MSP_U0_RST              (0x01 << 14)    /* UART0 reset bit      */
-
-/*
- ***************************************************************************
- * UART defines                                                            *
- ***************************************************************************
- */
-#define MSP_BASE_BAUD           25000000
-#define MSP_UART_REG_LEN        0x20
-
-/*
- ***************************************************************************
- * ELB defines                                                             *
- ***************************************************************************
- */
-#define PCCARD_32               0x02    /* Set if is PCCARD 32 (Cardbus) */
-#define SINGLE_PCCARD           0x01    /* Set to enable single PC card */
-
-/*
- ***************************************************************************
- * CIC defines                                                             *
- ***************************************************************************
- */
-
-/* CIC_EXT_CFG_REG */
-#define EXT_INT_POL(eirq)                       (1 << (eirq + 8))
-#define EXT_INT_EDGE(eirq)                      (1 << eirq)
-
-#define CIC_EXT_SET_TRIGGER_LEVEL(reg, eirq)    (reg &= ~EXT_INT_EDGE(eirq))
-#define CIC_EXT_SET_TRIGGER_EDGE(reg, eirq)     (reg |= EXT_INT_EDGE(eirq))
-#define CIC_EXT_SET_ACTIVE_HI(reg, eirq)        (reg |= EXT_INT_POL(eirq))
-#define CIC_EXT_SET_ACTIVE_LO(reg, eirq)        (reg &= ~EXT_INT_POL(eirq))
-#define CIC_EXT_SET_ACTIVE_RISING               CIC_EXT_SET_ACTIVE_HI
-#define CIC_EXT_SET_ACTIVE_FALLING              CIC_EXT_SET_ACTIVE_LO
-
-#define CIC_EXT_IS_TRIGGER_LEVEL(reg, eirq) \
-                                ((reg & EXT_INT_EDGE(eirq)) == 0)
-#define CIC_EXT_IS_TRIGGER_EDGE(reg, eirq)      (reg & EXT_INT_EDGE(eirq))
-#define CIC_EXT_IS_ACTIVE_HI(reg, eirq)         (reg & EXT_INT_POL(eirq))
-#define CIC_EXT_IS_ACTIVE_LO(reg, eirq) \
-                                ((reg & EXT_INT_POL(eirq)) == 0)
-#define CIC_EXT_IS_ACTIVE_RISING                CIC_EXT_IS_ACTIVE_HI
-#define CIC_EXT_IS_ACTIVE_FALLING               CIC_EXT_IS_ACTIVE_LO
-
-/*
- ***************************************************************************
- * Memory Controller defines                                               *
- ***************************************************************************
- */
-
-/* Indirect memory controller registers */
-#define DDRC_CFG(n)             (n)
-#define DDRC_DEBUG(n)           (0x04 + n)
-#define DDRC_CTL(n)             (0x40 + n)
-
-/* Macro to perform DDRC indirect write */
-#define DDRC_INDIRECT_WRITE(reg, mask, value) \
-({ \
-        *MEM_SS_ADDR = (((mask) & 0xf) << 8) | ((reg) & 0xff); \
-        *MEM_SS_DATA = (value); \
-        *MEM_SS_WRITE = 1; \
-})
-
-/*
- ***************************************************************************
- * SPI/MPI Mode                                                            *
- ***************************************************************************
- */
-#define SPI_MPI_RX_BUSY         0x00008000      /* SPI/MPI Receive Busy */
-#define SPI_MPI_FIFO_EMPTY      0x00004000      /* SPI/MPI Fifo Empty   */
-#define SPI_MPI_TX_BUSY         0x00002000      /* SPI/MPI Transmit Busy */
-#define SPI_MPI_FIFO_FULL       0x00001000      /* SPI/MPU FIFO full    */
-
-/*
- ***************************************************************************
- * SPI/MPI Control Register                                                *
- ***************************************************************************
- */
-#define SPI_MPI_RX_START        0x00000004      /* Start receive command */
-#define SPI_MPI_FLUSH_Q         0x00000002      /* Flush SPI/MPI Queue */
-#define SPI_MPI_TX_START        0x00000001      /* Start Transmit Command */
-
-#endif /* !_ASM_MSP_REGS_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h b/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
deleted file mode 100644
index 96d4c8ce8c83..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/msp_slp_int.h
+++ /dev/null
@@ -1,141 +0,0 @@
-/*
- * Defines for the MSP interrupt controller.
- *
- * Copyright (C) 1999 MIPS Technologies, Inc.  All rights reserved.
- * Author: Carsten Langgaard, carstenl@mips.com
- *
- * ########################################################################
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- * ########################################################################
- */
-
-#ifndef _MSP_SLP_INT_H
-#define _MSP_SLP_INT_H
-
-/*
- * The PMC-Sierra SLP interrupts are arranged in a 3 level cascaded
- * hierarchical system.  The first level are the direct MIPS interrupts
- * and are assigned the interrupt range 0-7.  The second level is the SLM
- * interrupt controller and is assigned the range 8-39.  The third level
- * comprises the Peripherial block, the PCI block, the PCI MSI block and
- * the SLP.  The PCI interrupts and the SLP errors are handled by the
- * relevant subsystems so the core interrupt code needs only concern
- * itself with the Peripheral block.  These are assigned interrupts in
- * the range 40-71.
- */
-
-/*
- * IRQs directly connected to CPU
- */
-#define MSP_MIPS_INTBASE        0
-#define MSP_INT_SW0             0  /* IRQ for swint0,         C_SW0  */
-#define MSP_INT_SW1             1  /* IRQ for swint1,         C_SW1  */
-#define MSP_INT_MAC0            2  /* IRQ for MAC 0,          C_IRQ0 */
-#define MSP_INT_MAC1            3  /* IRQ for MAC 1,          C_IRQ1 */
-#define MSP_INT_C_IRQ2          4  /* Wired off,              C_IRQ2 */
-#define MSP_INT_VE              5  /* IRQ for Voice Engine,   C_IRQ3 */
-#define MSP_INT_SLP             6  /* IRQ for SLM block,      C_IRQ4 */
-#define MSP_INT_TIMER           7  /* IRQ for the MIPS timer, C_IRQ5 */
-
-/*
- * IRQs cascaded on CPU interrupt 4 (CAUSE bit 12, C_IRQ4)
- * These defines should be tied to the register definition for the SLM
- * interrupt routine.  For now, just use hard-coded values.
- */
-#define MSP_SLP_INTBASE         (MSP_MIPS_INTBASE + 8)
-#define MSP_INT_EXT0            (MSP_SLP_INTBASE + 0)
-                                        /* External interrupt 0         */
-#define MSP_INT_EXT1            (MSP_SLP_INTBASE + 1)
-                                        /* External interrupt 1         */
-#define MSP_INT_EXT2            (MSP_SLP_INTBASE + 2)
-                                        /* External interrupt 2         */
-#define MSP_INT_EXT3            (MSP_SLP_INTBASE + 3)
-                                        /* External interrupt 3         */
-/* Reserved                                        4-7                  */
-
-/*
- *************************************************************************
- * DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER/DANGER *
- * Some MSP produces have this interrupt labelled as Voice and some are  *
- * SEC mbox ...                                                          *
- *************************************************************************
- */
-#define MSP_INT_SLP_VE          (MSP_SLP_INTBASE + 8)
-                                        /* Cascaded IRQ for Voice Engine*/
-#define MSP_INT_SLP_TDM         (MSP_SLP_INTBASE + 9)
-                                        /* TDM interrupt                */
-#define MSP_INT_SLP_MAC0        (MSP_SLP_INTBASE + 10)
-                                        /* Cascaded IRQ for MAC 0       */
-#define MSP_INT_SLP_MAC1        (MSP_SLP_INTBASE + 11)
-                                        /* Cascaded IRQ for MAC 1       */
-#define MSP_INT_SEC             (MSP_SLP_INTBASE + 12)
-                                        /* IRQ for security engine      */
-#define MSP_INT_PER             (MSP_SLP_INTBASE + 13)
-                                        /* Peripheral interrupt         */
-#define MSP_INT_TIMER0          (MSP_SLP_INTBASE + 14)
-                                        /* SLP timer 0                  */
-#define MSP_INT_TIMER1          (MSP_SLP_INTBASE + 15)
-                                        /* SLP timer 1                  */
-#define MSP_INT_TIMER2          (MSP_SLP_INTBASE + 16)
-                                        /* SLP timer 2                  */
-#define MSP_INT_SLP_TIMER       (MSP_SLP_INTBASE + 17)
-                                        /* Cascaded MIPS timer          */
-#define MSP_INT_BLKCP           (MSP_SLP_INTBASE + 18)
-                                        /* Block Copy                   */
-#define MSP_INT_UART0           (MSP_SLP_INTBASE + 19)
-                                        /* UART 0                       */
-#define MSP_INT_PCI             (MSP_SLP_INTBASE + 20)
-                                        /* PCI subsystem                */
-#define MSP_INT_PCI_DBELL       (MSP_SLP_INTBASE + 21)
-                                        /* PCI doorbell                 */
-#define MSP_INT_PCI_MSI         (MSP_SLP_INTBASE + 22)
-                                        /* PCI Message Signal           */
-#define MSP_INT_PCI_BC0         (MSP_SLP_INTBASE + 23)
-                                        /* PCI Block Copy 0             */
-#define MSP_INT_PCI_BC1         (MSP_SLP_INTBASE + 24)
-                                        /* PCI Block Copy 1             */
-#define MSP_INT_SLP_ERR         (MSP_SLP_INTBASE + 25)
-                                        /* SLP error condition          */
-#define MSP_INT_MAC2            (MSP_SLP_INTBASE + 26)
-                                        /* IRQ for MAC2                 */
-/* Reserved                                        26-31                */
-
-/*
- * IRQs cascaded on SLP PER interrupt (MSP_INT_PER)
- */
-#define MSP_PER_INTBASE         (MSP_SLP_INTBASE + 32)
-/* Reserved                                        0-1                  */
-#define MSP_INT_UART1           (MSP_PER_INTBASE + 2)
-                                        /* UART 1                       */
-/* Reserved                                        3-5                  */
-#define MSP_INT_2WIRE           (MSP_PER_INTBASE + 6)
-                                        /* 2-wire                       */
-#define MSP_INT_TM0             (MSP_PER_INTBASE + 7)
-                                        /* Peripheral timer block out 0 */
-#define MSP_INT_TM1             (MSP_PER_INTBASE + 8)
-                                        /* Peripheral timer block out 1 */
-/* Reserved                                        9                    */
-#define MSP_INT_SPRX            (MSP_PER_INTBASE + 10)
-                                        /* SPI RX complete              */
-#define MSP_INT_SPTX            (MSP_PER_INTBASE + 11)
-                                        /* SPI TX complete              */
-#define MSP_INT_GPIO            (MSP_PER_INTBASE + 12)
-                                        /* GPIO                         */
-#define MSP_INT_PER_ERR         (MSP_PER_INTBASE + 13)
-                                        /* Peripheral error             */
-/* Reserved                                        14-31                */
-
-#endif /* !_MSP_SLP_INT_H */
diff --git a/include/asm-mips/pmc-sierra/msp71xx/war.h b/include/asm-mips/pmc-sierra/msp71xx/war.h
deleted file mode 100644
index 0bf48fc1892b..000000000000
--- a/include/asm-mips/pmc-sierra/msp71xx/war.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
- */
-#ifndef __ASM_MIPS_PMC_SIERRA_WAR_H
-#define __ASM_MIPS_PMC_SIERRA_WAR_H
-
-#define R4600_V1_INDEX_ICACHEOP_WAR     0
-#define R4600_V1_HIT_CACHEOP_WAR        0
-#define R4600_V2_HIT_CACHEOP_WAR        0
-#define R5432_CP0_INTERRUPT_WAR         0
-#define BCM1250_M3_WAR                  0
-#define SIBYTE_1956_WAR                 0
-#define MIPS4K_ICACHE_REFILL_WAR        0
-#define MIPS_CACHE_SYNC_WAR             0
-#define TX49XX_ICACHE_INDEX_INV_WAR     0
-#define RM9000_CDEX_SMP_WAR             0
-#define ICACHE_REFILLS_WORKAROUND_WAR   0
-#define R10000_LLSC_WAR                 0
-#if defined(CONFIG_PMC_MSP7120_EVAL) || defined(CONFIG_PMC_MSP7120_GW) || \
-        defined(CONFIG_PMC_MSP7120_FPGA)
-#define MIPS34K_MISSED_ITLB_WAR         1
-#endif
-
-#endif /* __ASM_MIPS_PMC_SIERRA_WAR_H */
diff --git a/include/asm-mips/pmon.h b/include/asm-mips/pmon.h
deleted file mode 100644
index 6ad519189ce2..000000000000
--- a/include/asm-mips/pmon.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2004 by Ralf Baechle
- *
- * The cpustart method is a PMC-Sierra's function to start the secondary CPU.
- * Stock PMON 2000 has the smpfork, semlock and semunlock methods instead.
- */
-#ifndef _ASM_PMON_H
-#define _ASM_PMON_H
-
-struct callvectors {
-        int     (*open) (char*, int, int);
-        int     (*close) (int);
-        int     (*read) (int, void*, int);
-        int     (*write) (int, void*, int);
-        off_t   (*lseek) (int, off_t, int);
-        int     (*printf) (const char*, ...);
-        void    (*cacheflush) (void);
-        char*   (*gets) (char*);
-        union {
-                int     (*smpfork) (unsigned long cp, char *sp);
-                int     (*cpustart) (long, void (*)(void), void *, long);
-        } _s;
-        int     (*semlock) (int sem);
-        void    (*semunlock) (int sem);
-};
-
-extern struct callvectors *debug_vectors;
-
-#define pmon_open(name, flags, mode)    debug_vectors->open(name, flage, mode)
-#define pmon_close(fd)                  debug_vectors->close(fd)
-#define pmon_read(fd, buf, count)       debug_vectors->read(fd, buf, count)
-#define pmon_write(fd, buf, count)      debug_vectors->write(fd, buf, count)
-#define pmon_lseek(fd, off, whence)     debug_vectors->lseek(fd, off, whence)
-#define pmon_printf(fmt...)             debug_vectors->printf(fmt)
-#define pmon_cacheflush()               debug_vectors->cacheflush()
-#define pmon_gets(s)                    debug_vectors->gets(s)
-#define pmon_cpustart(n, f, sp, gp)     debug_vectors->_s.cpustart(n, f, sp, gp)
-#define pmon_smpfork(cp, sp)            debug_vectors->_s.smpfork(cp, sp)
-#define pmon_semlock(sem)               debug_vectors->semlock(sem)
-#define pmon_semunlock(sem)             debug_vectors->semunlock(sem)
-
-#endif /* _ASM_PMON_H */
diff --git a/include/asm-mips/poll.h b/include/asm-mips/poll.h
deleted file mode 100644
index 47b952080431..000000000000
--- a/include/asm-mips/poll.h
+++ /dev/null
@@ -1,9 +0,0 @@
-#ifndef __ASM_POLL_H
-#define __ASM_POLL_H
-
-#define POLLWRNORM      POLLOUT
-#define POLLWRBAND      0x0100
-
-#include <asm-generic/poll.h>
-
-#endif /* __ASM_POLL_H */
diff --git a/include/asm-mips/posix_types.h b/include/asm-mips/posix_types.h
deleted file mode 100644
index c200102c8586..000000000000
--- a/include/asm-mips/posix_types.h
+++ /dev/null
@@ -1,144 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 97, 98, 99, 2000 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_POSIX_TYPES_H
-#define _ASM_POSIX_TYPES_H
-
-#include <asm/sgidefs.h>
-
-/*
- * This file is generally used by user-level software, so you need to
- * be a little careful about namespace pollution etc.  Also, we cannot
- * assume GCC is being used.
- */
-
-typedef unsigned long   __kernel_ino_t;
-typedef unsigned int    __kernel_mode_t;
-#if (_MIPS_SZLONG == 32)
-typedef unsigned long   __kernel_nlink_t;
-#endif
-#if (_MIPS_SZLONG == 64)
-typedef unsigned int    __kernel_nlink_t;
-#endif
-typedef long            __kernel_off_t;
-typedef int             __kernel_pid_t;
-typedef int             __kernel_ipc_pid_t;
-typedef unsigned int    __kernel_uid_t;
-typedef unsigned int    __kernel_gid_t;
-#if (_MIPS_SZLONG == 32)
-typedef unsigned int    __kernel_size_t;
-typedef int             __kernel_ssize_t;
-typedef int             __kernel_ptrdiff_t;
-#endif
-#if (_MIPS_SZLONG == 64)
-typedef unsigned long   __kernel_size_t;
-typedef long            __kernel_ssize_t;
-typedef long            __kernel_ptrdiff_t;
-#endif
-typedef long            __kernel_time_t;
-typedef long            __kernel_suseconds_t;
-typedef long            __kernel_clock_t;
-typedef int             __kernel_timer_t;
-typedef int             __kernel_clockid_t;
-typedef long            __kernel_daddr_t;
-typedef char *          __kernel_caddr_t;
-
-typedef unsigned short  __kernel_uid16_t;
-typedef unsigned short  __kernel_gid16_t;
-typedef unsigned int    __kernel_uid32_t;
-typedef unsigned int    __kernel_gid32_t;
-typedef __kernel_uid_t  __kernel_old_uid_t;
-typedef __kernel_gid_t  __kernel_old_gid_t;
-typedef unsigned int    __kernel_old_dev_t;
-
-#ifdef __GNUC__
-typedef long long      __kernel_loff_t;
-#endif
-
-typedef struct {
-#if (_MIPS_SZLONG == 32)
-        long    val[2];
-#endif
-#if (_MIPS_SZLONG == 64)
-        int     val[2];
-#endif
-} __kernel_fsid_t;
-
-#if defined(__KERNEL__)
-
-#undef __FD_SET
-static __inline__ void __FD_SET(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-        unsigned long __tmp = __fd / __NFDBITS;
-        unsigned long __rem = __fd % __NFDBITS;
-        __fdsetp->fds_bits[__tmp] |= (1UL<<__rem);
-}
-
-#undef __FD_CLR
-static __inline__ void __FD_CLR(unsigned long __fd, __kernel_fd_set *__fdsetp)
-{
-        unsigned long __tmp = __fd / __NFDBITS;
-        unsigned long __rem = __fd % __NFDBITS;
-        __fdsetp->fds_bits[__tmp] &= ~(1UL<<__rem);
-}
-
-#undef __FD_ISSET
-static __inline__ int __FD_ISSET(unsigned long __fd, const __kernel_fd_set *__p)
-{
-        unsigned long __tmp = __fd / __NFDBITS;
-        unsigned long __rem = __fd % __NFDBITS;
-        return (__p->fds_bits[__tmp] & (1UL<<__rem)) != 0;
-}
-
-/*
- * This will unroll the loop for the normal constant case (8 ints,
- * for a 256-bit fd_set)
- */
-#undef __FD_ZERO
-static __inline__ void __FD_ZERO(__kernel_fd_set *__p)
-{
-        unsigned long *__tmp = __p->fds_bits;
-        int __i;
-
-        if (__builtin_constant_p(__FDSET_LONGS)) {
-                switch (__FDSET_LONGS) {
-                case 16:
-                        __tmp[ 0] = 0; __tmp[ 1] = 0;
-                        __tmp[ 2] = 0; __tmp[ 3] = 0;
-                        __tmp[ 4] = 0; __tmp[ 5] = 0;
-                        __tmp[ 6] = 0; __tmp[ 7] = 0;
-                        __tmp[ 8] = 0; __tmp[ 9] = 0;
-                        __tmp[10] = 0; __tmp[11] = 0;
-                        __tmp[12] = 0; __tmp[13] = 0;
-                        __tmp[14] = 0; __tmp[15] = 0;
-                        return;
-
-                case 8:
-                        __tmp[ 0] = 0; __tmp[ 1] = 0;
-                        __tmp[ 2] = 0; __tmp[ 3] = 0;
-                        __tmp[ 4] = 0; __tmp[ 5] = 0;
-                        __tmp[ 6] = 0; __tmp[ 7] = 0;
-                        return;
-
-                case 4:
-                        __tmp[ 0] = 0; __tmp[ 1] = 0;
-                        __tmp[ 2] = 0; __tmp[ 3] = 0;
-                        return;
-                }
-        }
-        __i = __FDSET_LONGS;
-        while (__i) {
-                __i--;
-                *__tmp = 0;
-                __tmp++;
-        }
-}
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* _ASM_POSIX_TYPES_H */
diff --git a/include/asm-mips/prefetch.h b/include/asm-mips/prefetch.h
deleted file mode 100644
index 17850834ccb0..000000000000
--- a/include/asm-mips/prefetch.h
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2003 by Ralf Baechle
- */
-#ifndef __ASM_PREFETCH_H
-#define __ASM_PREFETCH_H
-
-
-/*
- * R5000 and RM5200 implements pref and prefx instructions but they're nops, so
- * rather than wasting time we pretend these processors don't support
- * prefetching at all.
- *
- * R5432 implements Load, Store, LoadStreamed, StoreStreamed, LoadRetained,
- * StoreRetained and WriteBackInvalidate but not Pref_PrepareForStore.
- *
- * Hell (and the book on my shelf I can't open ...) know what the R8000 does.
- *
- * RM7000 version 1.0 interprets all hints as Pref_Load; version 2.0 implements
- * Pref_PrepareForStore also.
- *
- * RM9000 is MIPS IV but implements prefetching like MIPS32/MIPS64; it's
- * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in
- * current versions due to erratum G105.
- *
- * VR7701 only implements the Load prefetch.
- *
- * Finally MIPS32 and MIPS64 implement all of the following hints.
- */
-
-#define Pref_Load                       0
-#define Pref_Store                      1
-                                                /* 2 and 3 are reserved */
-#define Pref_LoadStreamed               4
-#define Pref_StoreStreamed              5
-#define Pref_LoadRetained               6
-#define Pref_StoreRetained              7
-                                                /* 8 ... 24 are reserved */
-#define Pref_WriteBackInvalidate        25
-#define Pref_PrepareForStore            30
-
-#ifdef __ASSEMBLY__
-
-        .macro  __pref hint addr
-#ifdef CONFIG_CPU_HAS_PREFETCH
-        pref    \hint, \addr
-#endif
-        .endm
-
-        .macro  pref_load addr
-        __pref  Pref_Load, \addr
-        .endm
-
-        .macro  pref_store addr
-        __pref  Pref_Store, \addr
-        .endm
-
-        .macro  pref_load_streamed addr
-        __pref  Pref_LoadStreamed, \addr
-        .endm
-
-        .macro  pref_store_streamed addr
-        __pref  Pref_StoreStreamed, \addr
-        .endm
-
-        .macro  pref_load_retained addr
-        __pref  Pref_LoadRetained, \addr
-        .endm
-
-        .macro  pref_store_retained addr
-        __pref  Pref_StoreRetained, \addr
-        .endm
-
-        .macro  pref_wback_inv addr
-        __pref  Pref_WriteBackInvalidate, \addr
-        .endm
-
-        .macro  pref_prepare_for_store addr
-        __pref  Pref_PrepareForStore, \addr
-        .endm
-
-#endif
-
-#endif /* __ASM_PREFETCH_H */
diff --git a/include/asm-mips/processor.h b/include/asm-mips/processor.h
deleted file mode 100644
index a1e4453469f9..000000000000
--- a/include/asm-mips/processor.h
+++ /dev/null
@@ -1,263 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994 Waldorf GMBH
- * Copyright (C) 1995, 1996, 1997, 1998, 1999, 2001, 2002, 2003 Ralf Baechle
- * Copyright (C) 1996 Paul M. Antoine
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PROCESSOR_H
-#define _ASM_PROCESSOR_H
-
-#include <linux/cpumask.h>
-#include <linux/threads.h>
-
-#include <asm/cachectl.h>
-#include <asm/cpu.h>
-#include <asm/cpu-info.h>
-#include <asm/mipsregs.h>
-#include <asm/prefetch.h>
-#include <asm/system.h>
-
-/*
- * Return current * instruction pointer ("program counter").
- */
-#define current_text_addr() ({ __label__ _l; _l: &&_l;})
-
-/*
- * System setup and hardware flags..
- */
-extern void (*cpu_wait)(void);
-
-extern unsigned int vced_count, vcei_count;
-
-#ifdef CONFIG_32BIT
-/*
- * User space process size: 2GB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.
- */
-#define TASK_SIZE       0x7fff8000UL
-#define STACK_TOP       TASK_SIZE
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE      ((TASK_SIZE / 3) & ~(PAGE_SIZE))
-#endif
-
-#ifdef CONFIG_64BIT
-/*
- * User space process size: 1TB. This is hardcoded into a few places,
- * so don't change it unless you know what you are doing.  TASK_SIZE
- * is limited to 1TB by the R4000 architecture; R10000 and better can
- * support 16TB; the architectural reserve for future expansion is
- * 8192EB ...
- */
-#define TASK_SIZE32     0x7fff8000UL
-#define TASK_SIZE       0x10000000000UL
-#define STACK_TOP       \
-      (test_thread_flag(TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
-
-/*
- * This decides where the kernel will search for a free chunk of vm
- * space during mmap's.
- */
-#define TASK_UNMAPPED_BASE                                              \
-        (test_thread_flag(TIF_32BIT_ADDR) ?                             \
-                PAGE_ALIGN(TASK_SIZE32 / 3) : PAGE_ALIGN(TASK_SIZE / 3))
-#define TASK_SIZE_OF(tsk)                                               \
-        (test_tsk_thread_flag(tsk, TIF_32BIT_ADDR) ? TASK_SIZE32 : TASK_SIZE)
-#endif
-
-#ifdef __KERNEL__
-#define STACK_TOP_MAX   TASK_SIZE
-#endif
-
-#define NUM_FPU_REGS    32
-
-typedef __u64 fpureg_t;
-
-/*
- * It would be nice to add some more fields for emulator statistics, but there
- * are a number of fixed offsets in offset.h and elsewhere that would have to
- * be recalculated by hand.  So the additional information will be private to
- * the FPU emulator for now.  See asm-mips/fpu_emulator.h.
- */
-
-struct mips_fpu_struct {
-        fpureg_t        fpr[NUM_FPU_REGS];
-        unsigned int    fcr31;
-};
-
-#define NUM_DSP_REGS   6
-
-typedef __u32 dspreg_t;
-
-struct mips_dsp_state {
-        dspreg_t        dspr[NUM_DSP_REGS];
-        unsigned int    dspcontrol;
-};
-
-#define INIT_CPUMASK { \
-        {0,} \
-}
-
-typedef struct {
-        unsigned long seg;
-} mm_segment_t;
-
-#define ARCH_MIN_TASKALIGN      8
-
-struct mips_abi;
-
-/*
- * If you change thread_struct remember to change the #defines below too!
- */
-struct thread_struct {
-        /* Saved main processor registers. */
-        unsigned long reg16;
-        unsigned long reg17, reg18, reg19, reg20, reg21, reg22, reg23;
-        unsigned long reg29, reg30, reg31;
-
-        /* Saved cp0 stuff. */
-        unsigned long cp0_status;
-
-        /* Saved fpu/fpu emulator stuff. */
-        struct mips_fpu_struct fpu;
-#ifdef CONFIG_MIPS_MT_FPAFF
-        /* Emulated instruction count */
-        unsigned long emulated_fp;
-        /* Saved per-thread scheduler affinity mask */
-        cpumask_t user_cpus_allowed;
-#endif /* CONFIG_MIPS_MT_FPAFF */
-
-        /* Saved state of the DSP ASE, if available. */
-        struct mips_dsp_state dsp;
-
-        /* Other stuff associated with the thread. */
-        unsigned long cp0_badvaddr;     /* Last user fault */
-        unsigned long cp0_baduaddr;     /* Last kernel fault accessing USEG */
-        unsigned long error_code;
-        unsigned long trap_no;
-        unsigned long irix_trampoline;  /* Wheee... */
-        unsigned long irix_oldctx;
-        struct mips_abi *abi;
-};
-
-#ifdef CONFIG_MIPS_MT_FPAFF
-#define FPAFF_INIT                                              \
-        .emulated_fp                    = 0,                    \
-        .user_cpus_allowed              = INIT_CPUMASK,
-#else
-#define FPAFF_INIT
-#endif /* CONFIG_MIPS_MT_FPAFF */
-
-#define INIT_THREAD  {                                          \
-        /*                                                      \
-         * Saved main processor registers                       \
-         */                                                     \
-        .reg16                  = 0,                            \
-        .reg17                  = 0,                            \
-        .reg18                  = 0,                            \
-        .reg19                  = 0,                            \
-        .reg20                  = 0,                            \
-        .reg21                  = 0,                            \
-        .reg22                  = 0,                            \
-        .reg23                  = 0,                            \
-        .reg29                  = 0,                            \
-        .reg30                  = 0,                            \
-        .reg31                  = 0,                            \
-        /*                                                      \
-         * Saved cp0 stuff                                      \
-         */                                                     \
-        .cp0_status             = 0,                            \
-        /*                                                      \
-         * Saved FPU/FPU emulator stuff                         \
-         */                                                     \
-        .fpu                    = {                             \
-                .fpr            = {0,},                         \
-                .fcr31          = 0,                            \
-        },                                                      \
-        /*                                                      \
-         * FPU affinity state (null if not FPAFF)               \
-         */                                                     \
-        FPAFF_INIT                                              \
-        /*                                                      \
-         * Saved DSP stuff                                      \
-         */                                                     \
-        .dsp                    = {                             \
-                .dspr           = {0, },                        \
-                .dspcontrol     = 0,                            \
-        },                                                      \
-        /*                                                      \
-         * Other stuff associated with the process              \
-         */                                                     \
-        .cp0_badvaddr           = 0,                            \
-        .cp0_baduaddr           = 0,                            \
-        .error_code             = 0,                            \
-        .trap_no                = 0,                            \
-        .irix_trampoline        = 0,                            \
-        .irix_oldctx            = 0,                            \
-}
-
-struct task_struct;
-
-/* Free all resources held by a thread. */
-#define release_thread(thread) do { } while(0)
-
-/* Prepare to copy thread state - unlazy all lazy status */
-#define prepare_to_copy(tsk)    do { } while (0)
-
-extern long kernel_thread(int (*fn)(void *), void * arg, unsigned long flags);
-
-extern unsigned long thread_saved_pc(struct task_struct *tsk);
-
-/*
- * Do necessary setup to start up a newly executed thread.
- */
-extern void start_thread(struct pt_regs * regs, unsigned long pc, unsigned long sp);
-
-unsigned long get_wchan(struct task_struct *p);
-
-#define __KSTK_TOS(tsk) ((unsigned long)task_stack_page(tsk) + THREAD_SIZE - 32)
-#define task_pt_regs(tsk) ((struct pt_regs *)__KSTK_TOS(tsk) - 1)
-#define KSTK_EIP(tsk) (task_pt_regs(tsk)->cp0_epc)
-#define KSTK_ESP(tsk) (task_pt_regs(tsk)->regs[29])
-#define KSTK_STATUS(tsk) (task_pt_regs(tsk)->cp0_status)
-
-#define cpu_relax()     barrier()
-
-/*
- * Return_address is a replacement for __builtin_return_address(count)
- * which on certain architectures cannot reasonably be implemented in GCC
- * (MIPS, Alpha) or is unuseable with -fomit-frame-pointer (i386).
- * Note that __builtin_return_address(x>=1) is forbidden because GCC
- * aborts compilation on some CPUs.  It's simply not possible to unwind
- * some CPU's stackframes.
- *
- * __builtin_return_address works only for non-leaf functions.  We avoid the
- * overhead of a function call by forcing the compiler to save the return
- * address register on the stack.
- */
-#define return_address() ({__asm__ __volatile__("":::"$31");__builtin_return_address(0);})
-
-#ifdef CONFIG_CPU_HAS_PREFETCH
-
-#define ARCH_HAS_PREFETCH
-
-static inline void prefetch(const void *addr)
-{
-        __asm__ __volatile__(
-        "       .set    mips4           \n"
-        "       pref    %0, (%1)        \n"
-        "       .set    mips0           \n"
-        :
-        : "i" (Pref_Load), "r" (addr));
-}
-
-#endif
-
-#endif /* _ASM_PROCESSOR_H */
diff --git a/include/asm-mips/ptrace.h b/include/asm-mips/ptrace.h
deleted file mode 100644
index 786f7e3c99bc..000000000000
--- a/include/asm-mips/ptrace.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2000 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_PTRACE_H
-#define _ASM_PTRACE_H
-
-
-/* 0 - 31 are integer registers, 32 - 63 are fp registers.  */
-#define FPR_BASE        32
-#define PC              64
-#define CAUSE           65
-#define BADVADDR        66
-#define MMHI            67
-#define MMLO            68
-#define FPC_CSR         69
-#define FPC_EIR         70
-#define DSP_BASE        71              /* 3 more hi / lo register pairs */
-#define DSP_CONTROL     77
-#define ACX             78
-
-/*
- * This struct defines the way the registers are stored on the stack during a
- * system call/exception. As usual the registers k0/k1 aren't being saved.
- */
-struct pt_regs {
-#ifdef CONFIG_32BIT
-        /* Pad bytes for argument save space on the stack. */
-        unsigned long pad0[6];
-#endif
-
-        /* Saved main processor registers. */
-        unsigned long regs[32];
-
-        /* Saved special registers. */
-        unsigned long cp0_status;
-        unsigned long hi;
-        unsigned long lo;
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-        unsigned long acx;
-#endif
-        unsigned long cp0_badvaddr;
-        unsigned long cp0_cause;
-        unsigned long cp0_epc;
-#ifdef CONFIG_MIPS_MT_SMTC
-        unsigned long cp0_tcstatus;
-#endif /* CONFIG_MIPS_MT_SMTC */
-} __attribute__ ((aligned (8)));
-
-/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
-#define PTRACE_GETREGS          12
-#define PTRACE_SETREGS          13
-#define PTRACE_GETFPREGS                14
-#define PTRACE_SETFPREGS                15
-/* #define PTRACE_GETFPXREGS            18 */
-/* #define PTRACE_SETFPXREGS            19 */
-
-#define PTRACE_OLDSETOPTIONS    21
-
-#define PTRACE_GET_THREAD_AREA  25
-#define PTRACE_SET_THREAD_AREA  26
-
-/* Calls to trace a 64bit program from a 32bit program.  */
-#define PTRACE_PEEKTEXT_3264    0xc0
-#define PTRACE_PEEKDATA_3264    0xc1
-#define PTRACE_POKETEXT_3264    0xc2
-#define PTRACE_POKEDATA_3264    0xc3
-#define PTRACE_GET_THREAD_AREA_3264     0xc4
-
-#ifdef __KERNEL__
-
-#include <linux/linkage.h>
-#include <asm/isadep.h>
-
-/*
- * Does the process account for user or for system time?
- */
-#define user_mode(regs) (((regs)->cp0_status & KU_MASK) == KU_USER)
-
-#define instruction_pointer(regs) ((regs)->cp0_epc)
-#define profile_pc(regs) instruction_pointer(regs)
-
-extern asmlinkage void do_syscall_trace(struct pt_regs *regs, int entryexit);
-
-extern NORET_TYPE void die(const char *, const struct pt_regs *) ATTRIB_NORET;
-
-static inline void die_if_kernel(const char *str, const struct pt_regs *regs)
-{
-        if (unlikely(!user_mode(regs)))
-                die(str, regs);
-}
-
-#endif
-
-#endif /* _ASM_PTRACE_H */
diff --git a/include/asm-mips/r4k-timer.h b/include/asm-mips/r4k-timer.h
deleted file mode 100644
index a37d12b3b61c..000000000000
--- a/include/asm-mips/r4k-timer.h
+++ /dev/null
@@ -1,30 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2008 by Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef __ASM_R4K_TYPES_H
-#define __ASM_R4K_TYPES_H
-
-#include <linux/compiler.h>
-
-#ifdef CONFIG_SYNC_R4K
-
-extern void synchronise_count_master(void);
-extern void synchronise_count_slave(void);
-
-#else
-
-static inline void synchronise_count_master(void)
-{
-}
-
-static inline void synchronise_count_slave(void)
-{
-}
-
-#endif
-
-#endif /* __ASM_R4K_TYPES_H */
diff --git a/include/asm-mips/r4kcache.h b/include/asm-mips/r4kcache.h
deleted file mode 100644
index 4c140db36786..000000000000
--- a/include/asm-mips/r4kcache.h
+++ /dev/null
@@ -1,443 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Inline assembly cache operations.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1997 - 2002 Ralf Baechle (ralf@gnu.org)
- * Copyright (C) 2004 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_R4KCACHE_H
-#define _ASM_R4KCACHE_H
-
-#include <asm/asm.h>
-#include <asm/cacheops.h>
-#include <asm/cpu-features.h>
-#include <asm/mipsmtregs.h>
-
-/*
- * This macro return a properly sign-extended address suitable as base address
- * for indexed cache operations.  Two issues here:
- *
- *  - The MIPS32 and MIPS64 specs permit an implementation to directly derive
- *    the index bits from the virtual address.  This breaks with tradition
- *    set by the R4000.  To keep unpleasant surprises from happening we pick
- *    an address in KSEG0 / CKSEG0.
- *  - We need a properly sign extended address for 64-bit code.  To get away
- *    without ifdefs we let the compiler do it by a type cast.
- */
-#define INDEX_BASE      CKSEG0
-
-#define cache_op(op,addr)                                               \
-        __asm__ __volatile__(                                           \
-        "       .set    push                                    \n"     \
-        "       .set    noreorder                               \n"     \
-        "       .set    mips3\n\t                               \n"     \
-        "       cache   %0, %1                                  \n"     \
-        "       .set    pop                                     \n"     \
-        :                                                               \
-        : "i" (op), "R" (*(unsigned char *)(addr)))
-
-#ifdef CONFIG_MIPS_MT
-/*
- * Temporary hacks for SMTC debug. Optionally force single-threaded
- * execution during I-cache flushes.
- */
-
-#define PROTECT_CACHE_FLUSHES 1
-
-#ifdef PROTECT_CACHE_FLUSHES
-
-extern int mt_protiflush;
-extern int mt_protdflush;
-extern void mt_cflush_lockdown(void);
-extern void mt_cflush_release(void);
-
-#define BEGIN_MT_IPROT \
-        unsigned long flags = 0;                        \
-        unsigned long mtflags = 0;                      \
-        if(mt_protiflush) {                             \
-                local_irq_save(flags);                  \
-                ehb();                                  \
-                mtflags = dvpe();                       \
-                mt_cflush_lockdown();                   \
-        }
-
-#define END_MT_IPROT \
-        if(mt_protiflush) {                             \
-                mt_cflush_release();                    \
-                evpe(mtflags);                          \
-                local_irq_restore(flags);               \
-        }
-
-#define BEGIN_MT_DPROT \
-        unsigned long flags = 0;                        \
-        unsigned long mtflags = 0;                      \
-        if(mt_protdflush) {                             \
-                local_irq_save(flags);                  \
-                ehb();                                  \
-                mtflags = dvpe();                       \
-                mt_cflush_lockdown();                   \
-        }
-
-#define END_MT_DPROT \
-        if(mt_protdflush) {                             \
-                mt_cflush_release();                    \
-                evpe(mtflags);                          \
-                local_irq_restore(flags);               \
-        }
-
-#else
-
-#define BEGIN_MT_IPROT
-#define BEGIN_MT_DPROT
-#define END_MT_IPROT
-#define END_MT_DPROT
-
-#endif /* PROTECT_CACHE_FLUSHES */
-
-#define __iflush_prologue                                               \
-        unsigned long redundance;                                       \
-        extern int mt_n_iflushes;                                       \
-        BEGIN_MT_IPROT                                                  \
-        for (redundance = 0; redundance < mt_n_iflushes; redundance++) {
-
-#define __iflush_epilogue                                               \
-        END_MT_IPROT                                                    \
-        }
-
-#define __dflush_prologue                                               \
-        unsigned long redundance;                                       \
-        extern int mt_n_dflushes;                                       \
-        BEGIN_MT_DPROT                                                  \
-        for (redundance = 0; redundance < mt_n_dflushes; redundance++) {
-
-#define __dflush_epilogue \
-        END_MT_DPROT     \
-        }
-
-#define __inv_dflush_prologue __dflush_prologue
-#define __inv_dflush_epilogue __dflush_epilogue
-#define __sflush_prologue {
-#define __sflush_epilogue }
-#define __inv_sflush_prologue __sflush_prologue
-#define __inv_sflush_epilogue __sflush_epilogue
-
-#else /* CONFIG_MIPS_MT */
-
-#define __iflush_prologue {
-#define __iflush_epilogue }
-#define __dflush_prologue {
-#define __dflush_epilogue }
-#define __inv_dflush_prologue {
-#define __inv_dflush_epilogue }
-#define __sflush_prologue {
-#define __sflush_epilogue }
-#define __inv_sflush_prologue {
-#define __inv_sflush_epilogue }
-
-#endif /* CONFIG_MIPS_MT */
-
-static inline void flush_icache_line_indexed(unsigned long addr)
-{
-        __iflush_prologue
-        cache_op(Index_Invalidate_I, addr);
-        __iflush_epilogue
-}
-
-static inline void flush_dcache_line_indexed(unsigned long addr)
-{
-        __dflush_prologue
-        cache_op(Index_Writeback_Inv_D, addr);
-        __dflush_epilogue
-}
-
-static inline void flush_scache_line_indexed(unsigned long addr)
-{
-        cache_op(Index_Writeback_Inv_SD, addr);
-}
-
-static inline void flush_icache_line(unsigned long addr)
-{
-        __iflush_prologue
-        cache_op(Hit_Invalidate_I, addr);
-        __iflush_epilogue
-}
-
-static inline void flush_dcache_line(unsigned long addr)
-{
-        __dflush_prologue
-        cache_op(Hit_Writeback_Inv_D, addr);
-        __dflush_epilogue
-}
-
-static inline void invalidate_dcache_line(unsigned long addr)
-{
-        __dflush_prologue
-        cache_op(Hit_Invalidate_D, addr);
-        __dflush_epilogue
-}
-
-static inline void invalidate_scache_line(unsigned long addr)
-{
-        cache_op(Hit_Invalidate_SD, addr);
-}
-
-static inline void flush_scache_line(unsigned long addr)
-{
-        cache_op(Hit_Writeback_Inv_SD, addr);
-}
-
-#define protected_cache_op(op,addr)                             \
-        __asm__ __volatile__(                                   \
-        "       .set    push                    \n"             \
-        "       .set    noreorder               \n"             \
-        "       .set    mips3                   \n"             \
-        "1:     cache   %0, (%1)                \n"             \
-        "2:     .set    pop                     \n"             \
-        "       .section __ex_table,\"a\"       \n"             \
-        "       "STR(PTR)" 1b, 2b               \n"             \
-        "       .previous"                                      \
-        :                                                       \
-        : "i" (op), "r" (addr))
-
-/*
- * The next two are for badland addresses like signal trampolines.
- */
-static inline void protected_flush_icache_line(unsigned long addr)
-{
-        protected_cache_op(Hit_Invalidate_I, addr);
-}
-
-/*
- * R10000 / R12000 hazard - these processors don't support the Hit_Writeback_D
- * cacheop so we use Hit_Writeback_Inv_D which is supported by all R4000-style
- * caches.  We're talking about one cacheline unnecessarily getting invalidated
- * here so the penalty isn't overly hard.
- */
-static inline void protected_writeback_dcache_line(unsigned long addr)
-{
-        protected_cache_op(Hit_Writeback_Inv_D, addr);
-}
-
-static inline void protected_writeback_scache_line(unsigned long addr)
-{
-        protected_cache_op(Hit_Writeback_Inv_SD, addr);
-}
-
-/*
- * This one is RM7000-specific
- */
-static inline void invalidate_tcache_page(unsigned long addr)
-{
-        cache_op(Page_Invalidate_T, addr);
-}
-
-#define cache16_unroll32(base,op)                                       \
-        __asm__ __volatile__(                                           \
-        "       .set push                                       \n"     \
-        "       .set noreorder                                  \n"     \
-        "       .set mips3                                      \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x010(%0)        \n"     \
-        "       cache %1, 0x020(%0); cache %1, 0x030(%0)        \n"     \
-        "       cache %1, 0x040(%0); cache %1, 0x050(%0)        \n"     \
-        "       cache %1, 0x060(%0); cache %1, 0x070(%0)        \n"     \
-        "       cache %1, 0x080(%0); cache %1, 0x090(%0)        \n"     \
-        "       cache %1, 0x0a0(%0); cache %1, 0x0b0(%0)        \n"     \
-        "       cache %1, 0x0c0(%0); cache %1, 0x0d0(%0)        \n"     \
-        "       cache %1, 0x0e0(%0); cache %1, 0x0f0(%0)        \n"     \
-        "       cache %1, 0x100(%0); cache %1, 0x110(%0)        \n"     \
-        "       cache %1, 0x120(%0); cache %1, 0x130(%0)        \n"     \
-        "       cache %1, 0x140(%0); cache %1, 0x150(%0)        \n"     \
-        "       cache %1, 0x160(%0); cache %1, 0x170(%0)        \n"     \
-        "       cache %1, 0x180(%0); cache %1, 0x190(%0)        \n"     \
-        "       cache %1, 0x1a0(%0); cache %1, 0x1b0(%0)        \n"     \
-        "       cache %1, 0x1c0(%0); cache %1, 0x1d0(%0)        \n"     \
-        "       cache %1, 0x1e0(%0); cache %1, 0x1f0(%0)        \n"     \
-        "       .set pop                                        \n"     \
-                :                                                       \
-                : "r" (base),                                           \
-                  "i" (op));
-
-#define cache32_unroll32(base,op)                                       \
-        __asm__ __volatile__(                                           \
-        "       .set push                                       \n"     \
-        "       .set noreorder                                  \n"     \
-        "       .set mips3                                      \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x020(%0)        \n"     \
-        "       cache %1, 0x040(%0); cache %1, 0x060(%0)        \n"     \
-        "       cache %1, 0x080(%0); cache %1, 0x0a0(%0)        \n"     \
-        "       cache %1, 0x0c0(%0); cache %1, 0x0e0(%0)        \n"     \
-        "       cache %1, 0x100(%0); cache %1, 0x120(%0)        \n"     \
-        "       cache %1, 0x140(%0); cache %1, 0x160(%0)        \n"     \
-        "       cache %1, 0x180(%0); cache %1, 0x1a0(%0)        \n"     \
-        "       cache %1, 0x1c0(%0); cache %1, 0x1e0(%0)        \n"     \
-        "       cache %1, 0x200(%0); cache %1, 0x220(%0)        \n"     \
-        "       cache %1, 0x240(%0); cache %1, 0x260(%0)        \n"     \
-        "       cache %1, 0x280(%0); cache %1, 0x2a0(%0)        \n"     \
-        "       cache %1, 0x2c0(%0); cache %1, 0x2e0(%0)        \n"     \
-        "       cache %1, 0x300(%0); cache %1, 0x320(%0)        \n"     \
-        "       cache %1, 0x340(%0); cache %1, 0x360(%0)        \n"     \
-        "       cache %1, 0x380(%0); cache %1, 0x3a0(%0)        \n"     \
-        "       cache %1, 0x3c0(%0); cache %1, 0x3e0(%0)        \n"     \
-        "       .set pop                                        \n"     \
-                :                                                       \
-                : "r" (base),                                           \
-                  "i" (op));
-
-#define cache64_unroll32(base,op)                                       \
-        __asm__ __volatile__(                                           \
-        "       .set push                                       \n"     \
-        "       .set noreorder                                  \n"     \
-        "       .set mips3                                      \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x040(%0)        \n"     \
-        "       cache %1, 0x080(%0); cache %1, 0x0c0(%0)        \n"     \
-        "       cache %1, 0x100(%0); cache %1, 0x140(%0)        \n"     \
-        "       cache %1, 0x180(%0); cache %1, 0x1c0(%0)        \n"     \
-        "       cache %1, 0x200(%0); cache %1, 0x240(%0)        \n"     \
-        "       cache %1, 0x280(%0); cache %1, 0x2c0(%0)        \n"     \
-        "       cache %1, 0x300(%0); cache %1, 0x340(%0)        \n"     \
-        "       cache %1, 0x380(%0); cache %1, 0x3c0(%0)        \n"     \
-        "       cache %1, 0x400(%0); cache %1, 0x440(%0)        \n"     \
-        "       cache %1, 0x480(%0); cache %1, 0x4c0(%0)        \n"     \
-        "       cache %1, 0x500(%0); cache %1, 0x540(%0)        \n"     \
-        "       cache %1, 0x580(%0); cache %1, 0x5c0(%0)        \n"     \
-        "       cache %1, 0x600(%0); cache %1, 0x640(%0)        \n"     \
-        "       cache %1, 0x680(%0); cache %1, 0x6c0(%0)        \n"     \
-        "       cache %1, 0x700(%0); cache %1, 0x740(%0)        \n"     \
-        "       cache %1, 0x780(%0); cache %1, 0x7c0(%0)        \n"     \
-        "       .set pop                                        \n"     \
-                :                                                       \
-                : "r" (base),                                           \
-                  "i" (op));
-
-#define cache128_unroll32(base,op)                                      \
-        __asm__ __volatile__(                                           \
-        "       .set push                                       \n"     \
-        "       .set noreorder                                  \n"     \
-        "       .set mips3                                      \n"     \
-        "       cache %1, 0x000(%0); cache %1, 0x080(%0)        \n"     \
-        "       cache %1, 0x100(%0); cache %1, 0x180(%0)        \n"     \
-        "       cache %1, 0x200(%0); cache %1, 0x280(%0)        \n"     \
-        "       cache %1, 0x300(%0); cache %1, 0x380(%0)        \n"     \
-        "       cache %1, 0x400(%0); cache %1, 0x480(%0)        \n"     \
-        "       cache %1, 0x500(%0); cache %1, 0x580(%0)        \n"     \
-        "       cache %1, 0x600(%0); cache %1, 0x680(%0)        \n"     \
-        "       cache %1, 0x700(%0); cache %1, 0x780(%0)        \n"     \
-        "       cache %1, 0x800(%0); cache %1, 0x880(%0)        \n"     \
-        "       cache %1, 0x900(%0); cache %1, 0x980(%0)        \n"     \
-        "       cache %1, 0xa00(%0); cache %1, 0xa80(%0)        \n"     \
-        "       cache %1, 0xb00(%0); cache %1, 0xb80(%0)        \n"     \
-        "       cache %1, 0xc00(%0); cache %1, 0xc80(%0)        \n"     \
-        "       cache %1, 0xd00(%0); cache %1, 0xd80(%0)        \n"     \
-        "       cache %1, 0xe00(%0); cache %1, 0xe80(%0)        \n"     \
-        "       cache %1, 0xf00(%0); cache %1, 0xf80(%0)        \n"     \
-        "       .set pop                                        \n"     \
-                :                                                       \
-                : "r" (base),                                           \
-                  "i" (op));
-
-/* build blast_xxx, blast_xxx_page, blast_xxx_page_indexed */
-#define __BUILD_BLAST_CACHE(pfx, desc, indexop, hitop, lsize) \
-static inline void blast_##pfx##cache##lsize(void)                      \
-{                                                                       \
-        unsigned long start = INDEX_BASE;                               \
-        unsigned long end = start + current_cpu_data.desc.waysize;      \
-        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
-        unsigned long ws_end = current_cpu_data.desc.ways <<            \
-                               current_cpu_data.desc.waybit;            \
-        unsigned long ws, addr;                                         \
-                                                                        \
-        __##pfx##flush_prologue                                         \
-                                                                        \
-        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
-                for (addr = start; addr < end; addr += lsize * 32)      \
-                        cache##lsize##_unroll32(addr|ws, indexop);      \
-                                                                        \
-        __##pfx##flush_epilogue                                         \
-}                                                                       \
-                                                                        \
-static inline void blast_##pfx##cache##lsize##_page(unsigned long page) \
-{                                                                       \
-        unsigned long start = page;                                     \
-        unsigned long end = page + PAGE_SIZE;                           \
-                                                                        \
-        __##pfx##flush_prologue                                         \
-                                                                        \
-        do {                                                            \
-                cache##lsize##_unroll32(start, hitop);                  \
-                start += lsize * 32;                                    \
-        } while (start < end);                                          \
-                                                                        \
-        __##pfx##flush_epilogue                                         \
-}                                                                       \
-                                                                        \
-static inline void blast_##pfx##cache##lsize##_page_indexed(unsigned long page) \
-{                                                                       \
-        unsigned long indexmask = current_cpu_data.desc.waysize - 1;    \
-        unsigned long start = INDEX_BASE + (page & indexmask);          \
-        unsigned long end = start + PAGE_SIZE;                          \
-        unsigned long ws_inc = 1UL << current_cpu_data.desc.waybit;     \
-        unsigned long ws_end = current_cpu_data.desc.ways <<            \
-                               current_cpu_data.desc.waybit;            \
-        unsigned long ws, addr;                                         \
-                                                                        \
-        __##pfx##flush_prologue                                         \
-                                                                        \
-        for (ws = 0; ws < ws_end; ws += ws_inc)                         \
-                for (addr = start; addr < end; addr += lsize * 32)      \
-                        cache##lsize##_unroll32(addr|ws, indexop);      \
-                                                                        \
-        __##pfx##flush_epilogue                                         \
-}
-
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 16)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 16)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 16)
-__BUILD_BLAST_CACHE(d, dcache, Index_Writeback_Inv_D, Hit_Writeback_Inv_D, 32)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 32)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 32)
-__BUILD_BLAST_CACHE(i, icache, Index_Invalidate_I, Hit_Invalidate_I, 64)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 64)
-__BUILD_BLAST_CACHE(s, scache, Index_Writeback_Inv_SD, Hit_Writeback_Inv_SD, 128)
-
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 16)
-__BUILD_BLAST_CACHE(inv_d, dcache, Index_Writeback_Inv_D, Hit_Invalidate_D, 32)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 16)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 32)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 64)
-__BUILD_BLAST_CACHE(inv_s, scache, Index_Writeback_Inv_SD, Hit_Invalidate_SD, 128)
-
-/* build blast_xxx_range, protected_blast_xxx_range */
-#define __BUILD_BLAST_CACHE_RANGE(pfx, desc, hitop, prot) \
-static inline void prot##blast_##pfx##cache##_range(unsigned long start, \
-                                                    unsigned long end)  \
-{                                                                       \
-        unsigned long lsize = cpu_##desc##_line_size();                 \
-        unsigned long addr = start & ~(lsize - 1);                      \
-        unsigned long aend = (end - 1) & ~(lsize - 1);                  \
-                                                                        \
-        __##pfx##flush_prologue                                         \
-                                                                        \
-        while (1) {                                                     \
-                prot##cache_op(hitop, addr);                            \
-                if (addr == aend)                                       \
-                        break;                                          \
-                addr += lsize;                                          \
-        }                                                               \
-                                                                        \
-        __##pfx##flush_epilogue                                         \
-}
-
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, protected_)
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, protected_)
-__BUILD_BLAST_CACHE_RANGE(i, icache, Hit_Invalidate_I, protected_)
-__BUILD_BLAST_CACHE_RANGE(d, dcache, Hit_Writeback_Inv_D, )
-__BUILD_BLAST_CACHE_RANGE(s, scache, Hit_Writeback_Inv_SD, )
-/* blast_inv_dcache_range */
-__BUILD_BLAST_CACHE_RANGE(inv_d, dcache, Hit_Invalidate_D, )
-__BUILD_BLAST_CACHE_RANGE(inv_s, scache, Hit_Invalidate_SD, )
-
-#endif /* _ASM_R4KCACHE_H */
diff --git a/include/asm-mips/reboot.h b/include/asm-mips/reboot.h
deleted file mode 100644
index e48c0bfab257..000000000000
--- a/include/asm-mips/reboot.h
+++ /dev/null
@@ -1,15 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 1999, 2001, 06 by Ralf Baechle
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef _ASM_REBOOT_H
-#define _ASM_REBOOT_H
-
-extern void (*_machine_restart)(char *command);
-extern void (*_machine_halt)(void);
-
-#endif /* _ASM_REBOOT_H */
diff --git a/include/asm-mips/reg.h b/include/asm-mips/reg.h
deleted file mode 100644
index 634b55d7e7f6..000000000000
--- a/include/asm-mips/reg.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Various register offset definitions for debuggers, core file
- * examiners and whatnot.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999 Ralf Baechle
- * Copyright (C) 1995, 1999 Silicon Graphics
- */
-#ifndef __ASM_MIPS_REG_H
-#define __ASM_MIPS_REG_H
-
-
-#if defined(CONFIG_32BIT) || defined(WANT_COMPAT_REG_H)
-
-#define EF_R0                   6
-#define EF_R1                   7
-#define EF_R2                   8
-#define EF_R3                   9
-#define EF_R4                   10
-#define EF_R5                   11
-#define EF_R6                   12
-#define EF_R7                   13
-#define EF_R8                   14
-#define EF_R9                   15
-#define EF_R10                  16
-#define EF_R11                  17
-#define EF_R12                  18
-#define EF_R13                  19
-#define EF_R14                  20
-#define EF_R15                  21
-#define EF_R16                  22
-#define EF_R17                  23
-#define EF_R18                  24
-#define EF_R19                  25
-#define EF_R20                  26
-#define EF_R21                  27
-#define EF_R22                  28
-#define EF_R23                  29
-#define EF_R24                  30
-#define EF_R25                  31
-
-/*
- * k0/k1 unsaved
- */
-#define EF_R26                  32
-#define EF_R27                  33
-
-#define EF_R28                  34
-#define EF_R29                  35
-#define EF_R30                  36
-#define EF_R31                  37
-
-/*
- * Saved special registers
- */
-#define EF_LO                   38
-#define EF_HI                   39
-
-#define EF_CP0_EPC              40
-#define EF_CP0_BADVADDR         41
-#define EF_CP0_STATUS           42
-#define EF_CP0_CAUSE            43
-#define EF_UNUSED0              44
-
-#define EF_SIZE                 180
-
-#endif
-
-#ifdef CONFIG_64BIT
-
-#define EF_R0                    0
-#define EF_R1                    1
-#define EF_R2                    2
-#define EF_R3                    3
-#define EF_R4                    4
-#define EF_R5                    5
-#define EF_R6                    6
-#define EF_R7                    7
-#define EF_R8                    8
-#define EF_R9                    9
-#define EF_R10                  10
-#define EF_R11                  11
-#define EF_R12                  12
-#define EF_R13                  13
-#define EF_R14                  14
-#define EF_R15                  15
-#define EF_R16                  16
-#define EF_R17                  17
-#define EF_R18                  18
-#define EF_R19                  19
-#define EF_R20                  20
-#define EF_R21                  21
-#define EF_R22                  22
-#define EF_R23                  23
-#define EF_R24                  24
-#define EF_R25                  25
-
-/*
- * k0/k1 unsaved
- */
-#define EF_R26                  26
-#define EF_R27                  27
-
-
-#define EF_R28                  28
-#define EF_R29                  29
-#define EF_R30                  30
-#define EF_R31                  31
-
-/*
- * Saved special registers
- */
-#define EF_LO                   32
-#define EF_HI                   33
-
-#define EF_CP0_EPC              34
-#define EF_CP0_BADVADDR         35
-#define EF_CP0_STATUS           36
-#define EF_CP0_CAUSE            37
-
-#define EF_SIZE                 304     /* size in bytes */
-
-#endif /* CONFIG_64BIT */
-
-#endif /* __ASM_MIPS_REG_H */
diff --git a/include/asm-mips/regdef.h b/include/asm-mips/regdef.h
deleted file mode 100644
index 7c8ecb6b9c40..000000000000
--- a/include/asm-mips/regdef.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1985 MIPS Computer Systems, Inc.
- * Copyright (C) 1994, 95, 99, 2003 by Ralf Baechle
- * Copyright (C) 1990 - 1992, 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_REGDEF_H
-#define _ASM_REGDEF_H
-
-#include <asm/sgidefs.h>
-
-#if _MIPS_SIM == _MIPS_SIM_ABI32
-
-/*
- * Symbolic register names for 32 bit ABI
- */
-#define zero    $0      /* wired zero */
-#define AT      $1      /* assembler temp  - uppercase because of ".set at" */
-#define v0      $2      /* return value */
-#define v1      $3
-#define a0      $4      /* argument registers */
-#define a1      $5
-#define a2      $6
-#define a3      $7
-#define t0      $8      /* caller saved */
-#define t1      $9
-#define t2      $10
-#define t3      $11
-#define t4      $12
-#define t5      $13
-#define t6      $14
-#define t7      $15
-#define s0      $16     /* callee saved */
-#define s1      $17
-#define s2      $18
-#define s3      $19
-#define s4      $20
-#define s5      $21
-#define s6      $22
-#define s7      $23
-#define t8      $24     /* caller saved */
-#define t9      $25
-#define jp      $25     /* PIC jump register */
-#define k0      $26     /* kernel scratch */
-#define k1      $27
-#define gp      $28     /* global pointer */
-#define sp      $29     /* stack pointer */
-#define fp      $30     /* frame pointer */
-#define s8      $30     /* same like fp! */
-#define ra      $31     /* return address */
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
-
-#define zero    $0      /* wired zero */
-#define AT      $at     /* assembler temp - uppercase because of ".set at" */
-#define v0      $2      /* return value - caller saved */
-#define v1      $3
-#define a0      $4      /* argument registers */
-#define a1      $5
-#define a2      $6
-#define a3      $7
-#define a4      $8      /* arg reg 64 bit; caller saved in 32 bit */
-#define ta0     $8
-#define a5      $9
-#define ta1     $9
-#define a6      $10
-#define ta2     $10
-#define a7      $11
-#define ta3     $11
-#define t0      $12     /* caller saved */
-#define t1      $13
-#define t2      $14
-#define t3      $15
-#define s0      $16     /* callee saved */
-#define s1      $17
-#define s2      $18
-#define s3      $19
-#define s4      $20
-#define s5      $21
-#define s6      $22
-#define s7      $23
-#define t8      $24     /* caller saved */
-#define t9      $25     /* callee address for PIC/temp */
-#define jp      $25     /* PIC jump register */
-#define k0      $26     /* kernel temporary */
-#define k1      $27
-#define gp      $28     /* global pointer - caller saved for PIC */
-#define sp      $29     /* stack pointer */
-#define fp      $30     /* frame pointer */
-#define s8      $30     /* callee saved */
-#define ra      $31     /* return address */
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
-
-#endif /* _ASM_REGDEF_H */
diff --git a/include/asm-mips/resource.h b/include/asm-mips/resource.h
deleted file mode 100644
index 87cb3085269c..000000000000
--- a/include/asm-mips/resource.h
+++ /dev/null
@@ -1,35 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 98, 99, 2000 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_RESOURCE_H
-#define _ASM_RESOURCE_H
-
-
-/*
- * These five resource limit IDs have a MIPS/Linux-specific ordering,
- * the rest comes from the generic header:
- */
-#define RLIMIT_NOFILE           5       /* max number of open files */
-#define RLIMIT_AS               6       /* address space limit */
-#define RLIMIT_RSS              7       /* max resident set size */
-#define RLIMIT_NPROC            8       /* max number of processes */
-#define RLIMIT_MEMLOCK          9       /* max locked-in-memory address space */
-
-/*
- * SuS says limits have to be unsigned.
- * Which makes a ton more sense anyway,
- * but we keep the old value on MIPS32,
- * for compatibility:
- */
-#ifdef CONFIG_32BIT
-# define RLIM_INFINITY          0x7fffffffUL
-#endif
-
-#include <asm-generic/resource.h>
-
-#endif /* _ASM_RESOURCE_H */
diff --git a/include/asm-mips/rm9k-ocd.h b/include/asm-mips/rm9k-ocd.h
deleted file mode 100644
index b0b80d9ecf96..000000000000
--- a/include/asm-mips/rm9k-ocd.h
+++ /dev/null
@@ -1,56 +0,0 @@
-/*
- *  Copyright (C) 2004 by Basler Vision Technologies AG
- *  Author: Thomas Koeller <thomas.koeller@baslerweb.com>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-
-#if !defined(_ASM_RM9K_OCD_H)
-#define _ASM_RM9K_OCD_H
-
-#include <linux/types.h>
-#include <linux/spinlock.h>
-#include <asm/io.h>
-
-extern volatile void __iomem * const ocd_base;
-extern volatile void __iomem * const titan_base;
-
-#define ocd_addr(__x__)         (ocd_base + (__x__))
-#define titan_addr(__x__)       (titan_base + (__x__))
-#define scram_addr(__x__)       (scram_base + (__x__))
-
-/* OCD register access */
-#define ocd_readl(__offs__) __raw_readl(ocd_addr(__offs__))
-#define ocd_readw(__offs__) __raw_readw(ocd_addr(__offs__))
-#define ocd_readb(__offs__) __raw_readb(ocd_addr(__offs__))
-#define ocd_writel(__val__, __offs__) \
-        __raw_writel((__val__), ocd_addr(__offs__))
-#define ocd_writew(__val__, __offs__) \
-        __raw_writew((__val__), ocd_addr(__offs__))
-#define ocd_writeb(__val__, __offs__) \
-        __raw_writeb((__val__), ocd_addr(__offs__))
-
-/* TITAN register access - 32 bit-wide only */
-#define titan_readl(__offs__) __raw_readl(titan_addr(__offs__))
-#define titan_writel(__val__, __offs__) \
-        __raw_writel((__val__), titan_addr(__offs__))
-
-/* Protect access to shared TITAN registers */
-extern spinlock_t titan_lock;
-extern int titan_irqflags;
-#define lock_titan_regs() spin_lock_irqsave(&titan_lock, titan_irqflags)
-#define unlock_titan_regs() spin_unlock_irqrestore(&titan_lock, titan_irqflags)
-
-#endif  /* !defined(_ASM_RM9K_OCD_H) */
diff --git a/include/asm-mips/rtlx.h b/include/asm-mips/rtlx.h
deleted file mode 100644
index 4ca3063ed2ce..000000000000
--- a/include/asm-mips/rtlx.h
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2004, 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- */
-
-#ifndef __ASM_RTLX_H_
-#define __ASM_RTLX_H_
-
-#include <irq.h>
-
-#define LX_NODE_BASE 10
-
-#define MIPS_CPU_RTLX_IRQ 0
-
-#define RTLX_VERSION 2
-#define RTLX_xID 0x12345600
-#define RTLX_ID (RTLX_xID | RTLX_VERSION)
-#define RTLX_CHANNELS 8
-
-#define RTLX_CHANNEL_STDIO      0
-#define RTLX_CHANNEL_DBG        1
-#define RTLX_CHANNEL_SYSIO      2
-
-extern int rtlx_open(int index, int can_sleep);
-extern int rtlx_release(int index);
-extern ssize_t rtlx_read(int index, void __user *buff, size_t count);
-extern ssize_t rtlx_write(int index, const void __user *buffer, size_t count);
-extern unsigned int rtlx_read_poll(int index, int can_sleep);
-extern unsigned int rtlx_write_poll(int index);
-
-enum rtlx_state {
-        RTLX_STATE_UNUSED = 0,
-        RTLX_STATE_INITIALISED,
-        RTLX_STATE_REMOTE_READY,
-        RTLX_STATE_OPENED
-};
-
-#define RTLX_BUFFER_SIZE 2048
-
-/* each channel supports read and write.
-   linux (vpe0) reads lx_buffer  and writes rt_buffer
-   SP (vpe1) reads rt_buffer and writes lx_buffer
-*/
-struct rtlx_channel {
-        enum rtlx_state rt_state;
-        enum rtlx_state lx_state;
-
-        int buffer_size;
-
-        /* read and write indexes per buffer */
-        int rt_write, rt_read;
-        char *rt_buffer;
-
-        int lx_write, lx_read;
-        char *lx_buffer;
-};
-
-struct rtlx_info {
-        unsigned long id;
-        enum rtlx_state state;
-
-        struct rtlx_channel channel[RTLX_CHANNELS];
-};
-
-#endif /* __ASM_RTLX_H_ */
diff --git a/include/asm-mips/scatterlist.h b/include/asm-mips/scatterlist.h
deleted file mode 100644
index 83d69fe17c9f..000000000000
--- a/include/asm-mips/scatterlist.h
+++ /dev/null
@@ -1,28 +0,0 @@
-#ifndef __ASM_SCATTERLIST_H
-#define __ASM_SCATTERLIST_H
-
-#include <asm/types.h>
-
-struct scatterlist {
-#ifdef CONFIG_DEBUG_SG
-        unsigned long   sg_magic;
-#endif
-        unsigned long   page_link;
-        unsigned int    offset;
-        dma_addr_t      dma_address;
-        unsigned int    length;
-};
-
-/*
- * These macros should be used after a pci_map_sg call has been done
- * to get bus addresses of each of the SG entries and their lengths.
- * You should only work with the number of sg entries pci_map_sg
- * returns, or alternatively stop on the first sg_dma_len(sg) which
- * is 0.
- */
-#define sg_dma_address(sg)      ((sg)->dma_address)
-#define sg_dma_len(sg)          ((sg)->length)
-
-#define ISA_DMA_THRESHOLD (0x00ffffffUL)
-
-#endif /* __ASM_SCATTERLIST_H */
diff --git a/include/asm-mips/seccomp.h b/include/asm-mips/seccomp.h
deleted file mode 100644
index 36ed44070256..000000000000
--- a/include/asm-mips/seccomp.h
+++ /dev/null
@@ -1,37 +0,0 @@
-#ifndef __ASM_SECCOMP_H
-
-#include <linux/thread_info.h>
-#include <linux/unistd.h>
-
-#define __NR_seccomp_read __NR_read
-#define __NR_seccomp_write __NR_write
-#define __NR_seccomp_exit __NR_exit
-#define __NR_seccomp_sigreturn __NR_rt_sigreturn
-
-/*
- * Kludge alert:
- *
- * The generic seccomp code currently allows only a single compat ABI.  Until
- * this is fixed we priorize O32 as the compat ABI over N32.
- */
-#ifdef CONFIG_MIPS32_O32
-
-#define TIF_32BIT TIF_32BIT_REGS
-
-#define __NR_seccomp_read_32            4003
-#define __NR_seccomp_write_32           4004
-#define __NR_seccomp_exit_32            4001
-#define __NR_seccomp_sigreturn_32       4193    /* rt_sigreturn */
-
-#elif defined(CONFIG_MIPS32_N32)
-
-#define TIF_32BIT _TIF_32BIT_ADDR
-
-#define __NR_seccomp_read_32            6000
-#define __NR_seccomp_write_32           6001
-#define __NR_seccomp_exit_32            6058
-#define __NR_seccomp_sigreturn_32       6211    /* rt_sigreturn */
-
-#endif /* CONFIG_MIPS32_O32 */
-
-#endif /* __ASM_SECCOMP_H */
diff --git a/include/asm-mips/sections.h b/include/asm-mips/sections.h
deleted file mode 100644
index b7e37262c246..000000000000
--- a/include/asm-mips/sections.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_SECTIONS_H
-#define _ASM_SECTIONS_H
-
-#include <asm-generic/sections.h>
-
-#endif /* _ASM_SECTIONS_H */
diff --git a/include/asm-mips/segment.h b/include/asm-mips/segment.h
deleted file mode 100644
index 92ac001fc483..000000000000
--- a/include/asm-mips/segment.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef _ASM_SEGMENT_H
-#define _ASM_SEGMENT_H
-
-/* Only here because we have some old header files that expect it.. */
-
-#endif /* _ASM_SEGMENT_H */
diff --git a/include/asm-mips/sembuf.h b/include/asm-mips/sembuf.h
deleted file mode 100644
index 7281a4decaa0..000000000000
--- a/include/asm-mips/sembuf.h
+++ /dev/null
@@ -1,22 +0,0 @@
-#ifndef _ASM_SEMBUF_H
-#define _ASM_SEMBUF_H
-
-/*
- * The semid64_ds structure for the MIPS architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 2 miscellaneous 64-bit values
- */
-
-struct semid64_ds {
-        struct ipc64_perm sem_perm;             /* permissions .. see ipc.h */
-        __kernel_time_t sem_otime;              /* last semop time */
-        __kernel_time_t sem_ctime;              /* last change time */
-        unsigned long   sem_nsems;              /* no. of semaphores in array */
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-};
-
-#endif /* _ASM_SEMBUF_H */
diff --git a/include/asm-mips/serial.h b/include/asm-mips/serial.h
deleted file mode 100644
index c07ebd8eb9e7..000000000000
--- a/include/asm-mips/serial.h
+++ /dev/null
@@ -1,22 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SERIAL_H
-#define _ASM_SERIAL_H
-
-
-/*
- * This assumes you have a 1.8432 MHz clock for your UART.
- *
- * It'd be nice if someone built a serial card with a 24.576 MHz
- * clock, since the 16550A is capable of handling a top speed of 1.5
- * megabits/second; but this requires the faster clock.
- */
-#define BASE_BAUD (1843200 / 16)
-
-#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-mips/setup.h b/include/asm-mips/setup.h
deleted file mode 100644
index e600cedda976..000000000000
--- a/include/asm-mips/setup.h
+++ /dev/null
@@ -1,10 +0,0 @@
-#ifndef _MIPS_SETUP_H
-#define _MIPS_SETUP_H
-
-#define COMMAND_LINE_SIZE       256
-
-#ifdef  __KERNEL__
-extern void setup_early_printk(void);
-#endif /* __KERNEL__ */
-
-#endif /* __SETUP_H */
diff --git a/include/asm-mips/sgi/gio.h b/include/asm-mips/sgi/gio.h
deleted file mode 100644
index 889cf028c95d..000000000000
--- a/include/asm-mips/sgi/gio.h
+++ /dev/null
@@ -1,86 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * gio.h: Definitions for SGI GIO bus
- *
- * Copyright (C) 2002 Ladislav Michl
- */
-
-#ifndef _SGI_GIO_H
-#define _SGI_GIO_H
-
-/*
- * GIO bus addresses
- *
- * The Indigo and Indy have two GIO bus connectors. Indigo2 (all models) have
- * three physical connectors, but only two slots, GFX and EXP0.
- *
- * There is 10MB of GIO address space for GIO64 slot devices
- * slot#   slot type address range            size
- * -----   --------- ----------------------- -----
- *   0     GFX       0x1f000000 - 0x1f3fffff   4MB
- *   1     EXP0      0x1f400000 - 0x1f5fffff   2MB
- *   2     EXP1      0x1f600000 - 0x1f9fffff   4MB
- *
- * There are un-slotted devices, HPC, I/O and misc devices, which are grouped
- * into the HPC address space.
- *   -     MISC      0x1fb00000 - 0x1fbfffff   1MB
- *
- * Following space is reserved and unused
- *   -     RESERVED  0x18000000 - 0x1effffff 112MB
- *
- * GIO bus IDs
- *
- * Each GIO bus device identifies itself to the system by answering a
- * read with an "ID" value. IDs are either 8 or 32 bits long. IDs less
- * than 128 are 8 bits long, with the most significant 24 bits read from
- * the slot undefined.
- *
- * 32-bit IDs are divided into
- *      bits 0:6        the product ID; ranges from 0x00 to 0x7F.
- *      bit 7           0=GIO Product ID is 8 bits wide
- *                      1=GIO Product ID is 32 bits wide.
- *      bits 8:15       manufacturer version for the product.
- *      bit 16          0=GIO32 and GIO32-bis, 1=GIO64.
- *      bit 17          0=no ROM present
- *                      1=ROM present on this board AND next three words
- *                      space define the ROM.
- *      bits 18:31      up to manufacturer.
- *
- * IDs above 0x50/0xd0 are of 3rd party boards.
- *
- * 8-bit IDs
- *      0x01            XPI low cost FDDI
- *      0x02            GTR TokenRing
- *      0x04            Synchronous ISDN
- *      0x05            ATM board [*]
- *      0x06            Canon Interface
- *      0x07            16 bit SCSI Card [*]
- *      0x08            JPEG (Double Wide)
- *      0x09            JPEG (Single Wide)
- *      0x0a            XPI mez. FDDI device 0
- *      0x0b            XPI mez. FDDI device 1
- *      0x0c            SMPTE 259M Video [*]
- *      0x0d            Babblefish Compression [*]
- *      0x0e            E-Plex 8-port Ethernet
- *      0x30            Lyon Lamb IVAS
- *      0xb8            GIO 100BaseTX Fast Ethernet (gfe)
- *
- * [*] Device provide 32-bit ID.
- *
- */
-
-#define GIO_ID(x)               (x & 0x7f)
-#define GIO_32BIT_ID            0x80
-#define GIO_REV(x)              ((x >> 8) & 0xff)
-#define GIO_64BIT_IFACE         0x10000
-#define GIO_ROM_PRESENT         0x20000
-#define GIO_VENDOR_CODE(x)      ((x >> 18) & 0x3fff)
-
-#define GIO_SLOT_GFX_BASE       0x1f000000
-#define GIO_SLOT_EXP0_BASE      0x1f400000
-#define GIO_SLOT_EXP1_BASE      0x1f600000
-
-#endif /* _SGI_GIO_H */
diff --git a/include/asm-mips/sgi/hpc3.h b/include/asm-mips/sgi/hpc3.h
deleted file mode 100644
index c4729f531919..000000000000
--- a/include/asm-mips/sgi/hpc3.h
+++ /dev/null
@@ -1,317 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * hpc3.h: Definitions for SGI HPC3 controller
- *
- * Copyright (C) 1996 David S. Miller
- * Copyright (C) 1998 Ralf Baechle
- */
-
-#ifndef _SGI_HPC3_H
-#define _SGI_HPC3_H
-
-#include <linux/types.h>
-#include <asm/page.h>
-
-/* An HPC DMA descriptor. */
-struct hpc_dma_desc {
-        u32 pbuf;       /* physical address of data buffer */
-        u32 cntinfo;    /* counter and info bits */
-#define HPCDMA_EOX      0x80000000 /* last desc in chain for tx */
-#define HPCDMA_EOR      0x80000000 /* last desc in chain for rx */
-#define HPCDMA_EOXP     0x40000000 /* end of packet for tx */
-#define HPCDMA_EORP     0x40000000 /* end of packet for rx */
-#define HPCDMA_XIE      0x20000000 /* irq generated when at end of this desc */
-#define HPCDMA_XIU      0x01000000 /* Tx buffer in use by CPU. */
-#define HPCDMA_EIPC     0x00ff0000 /* SEEQ ethernet special xternal bytecount */
-#define HPCDMA_ETXD     0x00008000 /* set to one by HPC when packet tx'd */
-#define HPCDMA_OWN      0x00004000 /* Denotes ring buffer ownership on rx */
-#define HPCDMA_BCNT     0x00003fff /* size in bytes of this dma buffer */
-
-        u32 pnext;      /* paddr of next hpc_dma_desc if any */
-};
-
-/* The set of regs for each HPC3 PBUS DMA channel. */
-struct hpc3_pbus_dmacregs {
-        volatile u32 pbdma_bptr;        /* pbus dma channel buffer ptr */
-        volatile u32 pbdma_dptr;        /* pbus dma channel desc ptr */
-        u32 _unused0[0x1000/4 - 2];     /* padding */
-        volatile u32 pbdma_ctrl;        /* pbus dma channel control register has
-                                         * copletely different meaning for read
-                                         * compared with write */
-        /* read */
-#define HPC3_PDMACTRL_INT       0x00000001 /* interrupt (cleared after read) */
-#define HPC3_PDMACTRL_ISACT     0x00000002 /* channel active */
-        /* write */
-#define HPC3_PDMACTRL_SEL       0x00000002 /* little endian transfer */
-#define HPC3_PDMACTRL_RCV       0x00000004 /* direction is receive */
-#define HPC3_PDMACTRL_FLSH      0x00000008 /* enable flush for receive DMA */
-#define HPC3_PDMACTRL_ACT       0x00000010 /* start dma transfer */
-#define HPC3_PDMACTRL_LD        0x00000020 /* load enable for ACT */
-#define HPC3_PDMACTRL_RT        0x00000040 /* Use realtime GIO bus servicing */
-#define HPC3_PDMACTRL_HW        0x0000ff00 /* DMA High-water mark */
-#define HPC3_PDMACTRL_FB        0x003f0000 /* Ptr to beginning of fifo */
-#define HPC3_PDMACTRL_FE        0x3f000000 /* Ptr to end of fifo */
-
-        u32 _unused1[0x1000/4 - 1];     /* padding */
-};
-
-/* The HPC3 SCSI registers, this does not include external ones. */
-struct hpc3_scsiregs {
-        volatile u32 cbptr;     /* current dma buffer ptr, diagnostic use only */
-        volatile u32 ndptr;     /* next dma descriptor ptr */
-        u32 _unused0[0x1000/4 - 2];     /* padding */
-        volatile u32 bcd;       /* byte count info */
-#define HPC3_SBCD_BCNTMSK 0x00003fff /* bytes to transfer from/to memory */
-#define HPC3_SBCD_XIE     0x00004000 /* Send IRQ when done with cur buf */
-#define HPC3_SBCD_EOX     0x00008000 /* Indicates this is last buf in chain */
-
-        volatile u32 ctrl;    /* control register */
-#define HPC3_SCTRL_IRQ    0x01 /* IRQ asserted, either dma done or parity */
-#define HPC3_SCTRL_ENDIAN 0x02 /* DMA endian mode, 0=big 1=little */
-#define HPC3_SCTRL_DIR    0x04 /* DMA direction, 1=dev2mem 0=mem2dev */
-#define HPC3_SCTRL_FLUSH  0x08 /* Tells HPC3 to flush scsi fifos */
-#define HPC3_SCTRL_ACTIVE 0x10 /* SCSI DMA channel is active */
-#define HPC3_SCTRL_AMASK  0x20 /* DMA active inhibits PIO */
-#define HPC3_SCTRL_CRESET 0x40 /* Resets dma channel and external controller */
-#define HPC3_SCTRL_PERR   0x80 /* Bad parity on HPC3 iface to scsi controller */
-
-        volatile u32 gfptr;     /* current GIO fifo ptr */
-        volatile u32 dfptr;     /* current device fifo ptr */
-        volatile u32 dconfig;   /* DMA configuration register */
-#define HPC3_SDCFG_HCLK 0x00001 /* Enable DMA half clock mode */
-#define HPC3_SDCFG_D1   0x00006 /* Cycles to spend in D1 state */
-#define HPC3_SDCFG_D2   0x00038 /* Cycles to spend in D2 state */
-#define HPC3_SDCFG_D3   0x001c0 /* Cycles to spend in D3 state */
-#define HPC3_SDCFG_HWAT 0x00e00 /* DMA high water mark */
-#define HPC3_SDCFG_HW   0x01000 /* Enable 16-bit halfword DMA accesses to scsi */
-#define HPC3_SDCFG_SWAP 0x02000 /* Byte swap all DMA accesses */
-#define HPC3_SDCFG_EPAR 0x04000 /* Enable parity checking for DMA */
-#define HPC3_SDCFG_POLL 0x08000 /* hd_dreq polarity control */
-#define HPC3_SDCFG_ERLY 0x30000 /* hd_dreq behavior control bits */
-
-        volatile u32 pconfig;   /* PIO configuration register */
-#define HPC3_SPCFG_P3   0x0003 /* Cycles to spend in P3 state */
-#define HPC3_SPCFG_P2W  0x001c /* Cycles to spend in P2 state for writes */
-#define HPC3_SPCFG_P2R  0x01e0 /* Cycles to spend in P2 state for reads */
-#define HPC3_SPCFG_P1   0x0e00 /* Cycles to spend in P1 state */
-#define HPC3_SPCFG_HW   0x1000 /* Enable 16-bit halfword PIO accesses to scsi */
-#define HPC3_SPCFG_SWAP 0x2000 /* Byte swap all PIO accesses */
-#define HPC3_SPCFG_EPAR 0x4000 /* Enable parity checking for PIO */
-#define HPC3_SPCFG_FUJI 0x8000 /* Fujitsu scsi controller mode for faster dma/pio */
-
-        u32 _unused1[0x1000/4 - 6];     /* padding */
-};
-
-/* SEEQ ethernet HPC3 registers, only one seeq per HPC3. */
-struct hpc3_ethregs {
-        /* Receiver registers. */
-        volatile u32 rx_cbptr;   /* current dma buffer ptr, diagnostic use only */
-        volatile u32 rx_ndptr;   /* next dma descriptor ptr */
-        u32 _unused0[0x1000/4 - 2];     /* padding */
-        volatile u32 rx_bcd;    /* byte count info */
-#define HPC3_ERXBCD_BCNTMSK 0x00003fff /* bytes to be sent to memory */
-#define HPC3_ERXBCD_XIE     0x20000000 /* HPC3 interrupts cpu at end of this buf */
-#define HPC3_ERXBCD_EOX     0x80000000 /* flags this as end of descriptor chain */
-
-        volatile u32 rx_ctrl;   /* control register */
-#define HPC3_ERXCTRL_STAT50 0x0000003f /* Receive status reg bits of Seeq8003 */
-#define HPC3_ERXCTRL_STAT6  0x00000040 /* Rdonly irq status */
-#define HPC3_ERXCTRL_STAT7  0x00000080 /* Rdonlt old/new status bit from Seeq */
-#define HPC3_ERXCTRL_ENDIAN 0x00000100 /* Endian for dma channel, little=1 big=0 */
-#define HPC3_ERXCTRL_ACTIVE 0x00000200 /* Tells if DMA transfer is in progress */
-#define HPC3_ERXCTRL_AMASK  0x00000400 /* Tells if ACTIVE inhibits PIO's to hpc3 */
-#define HPC3_ERXCTRL_RBO    0x00000800 /* Receive buffer overflow if set to 1 */
-
-        volatile u32 rx_gfptr;  /* current GIO fifo ptr */
-        volatile u32 rx_dfptr;  /* current device fifo ptr */
-        u32 _unused1;           /* padding */
-        volatile u32 reset;     /* reset register */
-#define HPC3_ERST_CRESET 0x1    /* Reset dma channel and external controller */
-#define HPC3_ERST_CLRIRQ 0x2    /* Clear channel interrupt */
-#define HPC3_ERST_LBACK  0x4    /* Enable diagnostic loopback mode of Seeq8003 */
-
-        volatile u32 dconfig;    /* DMA configuration register */
-#define HPC3_EDCFG_D1    0x0000f /* Cycles to spend in D1 state for PIO */
-#define HPC3_EDCFG_D2    0x000f0 /* Cycles to spend in D2 state for PIO */
-#define HPC3_EDCFG_D3    0x00f00 /* Cycles to spend in D3 state for PIO */
-#define HPC3_EDCFG_WCTRL 0x01000 /* Enable writes of desc into ex ctrl port */
-#define HPC3_EDCFG_FRXDC 0x02000 /* Clear eop stat bits upon rxdc, hw seeq fix */
-#define HPC3_EDCFG_FEOP  0x04000 /* Bad packet marker timeout enable */
-#define HPC3_EDCFG_FIRQ  0x08000 /* Another bad packet timeout enable */
-#define HPC3_EDCFG_PTO   0x30000 /* Programmed timeout value for above two */
-
-        volatile u32 pconfig;   /* PIO configuration register */
-#define HPC3_EPCFG_P1    0x000f /* Cycles to spend in P1 state for PIO */
-#define HPC3_EPCFG_P2    0x00f0 /* Cycles to spend in P2 state for PIO */
-#define HPC3_EPCFG_P3    0x0f00 /* Cycles to spend in P3 state for PIO */
-#define HPC3_EPCFG_TST   0x1000 /* Diagnistic ram test feature bit */
-
-        u32 _unused2[0x1000/4 - 8];     /* padding */
-
-        /* Transmitter registers. */
-        volatile u32 tx_cbptr;  /* current dma buffer ptr, diagnostic use only */
-        volatile u32 tx_ndptr;  /* next dma descriptor ptr */
-        u32 _unused3[0x1000/4 - 2];     /* padding */
-        volatile u32 tx_bcd;            /* byte count info */
-#define HPC3_ETXBCD_BCNTMSK 0x00003fff  /* bytes to be read from memory */
-#define HPC3_ETXBCD_ESAMP   0x10000000  /* if set, too late to add descriptor */
-#define HPC3_ETXBCD_XIE     0x20000000  /* Interrupt cpu at end of cur desc */
-#define HPC3_ETXBCD_EOP     0x40000000  /* Last byte of cur buf is end of packet */
-#define HPC3_ETXBCD_EOX     0x80000000  /* This buf is the end of desc chain */
-
-        volatile u32 tx_ctrl;           /* control register */
-#define HPC3_ETXCTRL_STAT30 0x0000000f  /* Rdonly copy of seeq tx stat reg */
-#define HPC3_ETXCTRL_STAT4  0x00000010  /* Indicate late collision occurred */
-#define HPC3_ETXCTRL_STAT75 0x000000e0  /* Rdonly irq status from seeq */
-#define HPC3_ETXCTRL_ENDIAN 0x00000100  /* DMA channel endian mode, 1=little 0=big */
-#define HPC3_ETXCTRL_ACTIVE 0x00000200  /* DMA tx channel is active */
-#define HPC3_ETXCTRL_AMASK  0x00000400  /* Indicates ACTIVE inhibits PIO's */
-
-        volatile u32 tx_gfptr;          /* current GIO fifo ptr */
-        volatile u32 tx_dfptr;          /* current device fifo ptr */
-        u32 _unused4[0x1000/4 - 4];     /* padding */
-};
-
-struct hpc3_regs {
-        /* First regs for the PBUS 8 dma channels. */
-        struct hpc3_pbus_dmacregs pbdma[8];
-
-        /* Now the HPC scsi registers, we get two scsi reg sets. */
-        struct hpc3_scsiregs scsi_chan0, scsi_chan1;
-
-        /* The SEEQ hpc3 ethernet dma/control registers. */
-        struct hpc3_ethregs ethregs;
-
-        /* Here are where the hpc3 fifo's can be directly accessed
-         * via PIO accesses.  Under normal operation we never stick
-         * our grubby paws in here so it's just padding. */
-        u32 _unused0[0x18000/4];
-
-        /* HPC3 irq status regs.  Due to a peculiar bug you need to
-         * look at two different register addresses to get at all of
-         * the status bits.  The first reg can only reliably report
-         * bits 4:0 of the status, and the second reg can only
-         * reliably report bits 9:5 of the hpc3 irq status.  I told
-         * you it was a peculiar bug. ;-)
-         */
-        volatile u32 istat0;            /* Irq status, only bits <4:0> reliable. */
-#define HPC3_ISTAT_PBIMASK      0x0ff   /* irq bits for pbus devs 0 --> 7 */
-#define HPC3_ISTAT_SC0MASK      0x100   /* irq bit for scsi channel 0 */
-#define HPC3_ISTAT_SC1MASK      0x200   /* irq bit for scsi channel 1 */
-
-        volatile u32 gio_misc;          /* GIO misc control bits. */
-#define HPC3_GIOMISC_ERTIME     0x1     /* Enable external timer real time. */
-#define HPC3_GIOMISC_DENDIAN    0x2     /* dma descriptor endian, 1=lit 0=big */
-
-        u32 eeprom;                     /* EEPROM data reg. */
-#define HPC3_EEPROM_EPROT       0x01    /* Protect register enable */
-#define HPC3_EEPROM_CSEL        0x02    /* Chip select */
-#define HPC3_EEPROM_ECLK        0x04    /* EEPROM clock */
-#define HPC3_EEPROM_DATO        0x08    /* Data out */
-#define HPC3_EEPROM_DATI        0x10    /* Data in */
-
-        volatile u32 istat1;            /* Irq status, only bits <9:5> reliable. */
-        volatile u32 bestat;            /* Bus error interrupt status reg. */
-#define HPC3_BESTAT_BLMASK      0x000ff /* Bus lane where bad parity occurred */
-#define HPC3_BESTAT_CTYPE       0x00100 /* Bus cycle type, 0=PIO 1=DMA */
-#define HPC3_BESTAT_PIDSHIFT    9
-#define HPC3_BESTAT_PIDMASK     0x3f700 /* DMA channel parity identifier */
-
-        u32 _unused1[0x14000/4 - 5];    /* padding */
-
-        /* Now direct PIO per-HPC3 peripheral access to external regs. */
-        volatile u32 scsi0_ext[256];    /* SCSI channel 0 external regs */
-        u32 _unused2[0x7c00/4];
-        volatile u32 scsi1_ext[256];    /* SCSI channel 1 external regs */
-        u32 _unused3[0x7c00/4];
-        volatile u32 eth_ext[320];      /* Ethernet external registers */
-        u32 _unused4[0x3b00/4];
-
-        /* Per-peripheral device external registers and DMA/PIO control. */
-        volatile u32 pbus_extregs[16][256];
-        volatile u32 pbus_dmacfg[8][128];
-        /* Cycles to spend in D3 for reads */
-#define HPC3_DMACFG_D3R_MASK            0x00000001
-#define HPC3_DMACFG_D3R_SHIFT           0
-        /* Cycles to spend in D4 for reads */
-#define HPC3_DMACFG_D4R_MASK            0x0000001e
-#define HPC3_DMACFG_D4R_SHIFT           1
-        /* Cycles to spend in D5 for reads */
-#define HPC3_DMACFG_D5R_MASK            0x000001e0
-#define HPC3_DMACFG_D5R_SHIFT           5
-        /* Cycles to spend in D3 for writes */
-#define HPC3_DMACFG_D3W_MASK            0x00000200
-#define HPC3_DMACFG_D3W_SHIFT           9
-        /* Cycles to spend in D4 for writes */
-#define HPC3_DMACFG_D4W_MASK            0x00003c00
-#define HPC3_DMACFG_D4W_SHIFT           10
-        /* Cycles to spend in D5 for writes */
-#define HPC3_DMACFG_D5W_MASK            0x0003c000
-#define HPC3_DMACFG_D5W_SHIFT           14
-        /* Enable 16-bit DMA access mode */
-#define HPC3_DMACFG_DS16                0x00040000
-        /* Places halfwords on high 16 bits of bus */
-#define HPC3_DMACFG_EVENHI              0x00080000
-        /* Make this device real time */
-#define HPC3_DMACFG_RTIME               0x00200000
-        /* 5 bit burst count for DMA device */
-#define HPC3_DMACFG_BURST_MASK          0x07c00000
-#define HPC3_DMACFG_BURST_SHIFT 22
-        /* Use live pbus_dreq unsynchronized signal */
-#define HPC3_DMACFG_DRQLIVE             0x08000000
-        volatile u32 pbus_piocfg[16][64];
-        /* Cycles to spend in P2 state for reads */
-#define HPC3_PIOCFG_P2R_MASK            0x00001
-#define HPC3_PIOCFG_P2R_SHIFT           0
-        /* Cycles to spend in P3 state for reads */
-#define HPC3_PIOCFG_P3R_MASK            0x0001e
-#define HPC3_PIOCFG_P3R_SHIFT           1
-        /* Cycles to spend in P4 state for reads */
-#define HPC3_PIOCFG_P4R_MASK            0x001e0
-#define HPC3_PIOCFG_P4R_SHIFT           5
-        /* Cycles to spend in P2 state for writes */
-#define HPC3_PIOCFG_P2W_MASK            0x00200
-#define HPC3_PIOCFG_P2W_SHIFT           9
-        /* Cycles to spend in P3 state for writes */
-#define HPC3_PIOCFG_P3W_MASK            0x03c00
-#define HPC3_PIOCFG_P3W_SHIFT           10
-        /* Cycles to spend in P4 state for writes */
-#define HPC3_PIOCFG_P4W_MASK            0x3c000
-#define HPC3_PIOCFG_P4W_SHIFT           14
-        /* Enable 16-bit PIO accesses */
-#define HPC3_PIOCFG_DS16                0x40000
-        /* Place even address bits in bits <15:8> */
-#define HPC3_PIOCFG_EVENHI              0x80000
-
-        /* PBUS PROM control regs. */
-        volatile u32 pbus_promwe;       /* PROM write enable register */
-#define HPC3_PROM_WENAB 0x1     /* Enable writes to the PROM */
-
-        u32 _unused5[0x0800/4 - 1];
-        volatile u32 pbus_promswap;     /* Chip select swap reg */
-#define HPC3_PROM_SWAP  0x1     /* invert GIO addr bit to select prom0 or prom1 */
-
-        u32 _unused6[0x0800/4 - 1];
-        volatile u32 pbus_gout; /* PROM general purpose output reg */
-#define HPC3_PROM_STAT  0x1     /* General purpose status bit in gout */
-
-        u32 _unused7[0x1000/4 - 1];
-        volatile u32 rtcregs[14];       /* Dallas clock registers */
-        u32 _unused8[50];
-        volatile u32 bbram[8192-50-14]; /* Battery backed ram */
-};
-
-/*
- * It is possible to have two HPC3's within the address space on
- * one machine, though only having one is more likely on an Indy.
- */
-extern struct hpc3_regs *hpc3c0, *hpc3c1;
-#define HPC3_CHIP0_BASE         0x1fb80000      /* physical */
-#define HPC3_CHIP1_BASE         0x1fb00000      /* physical */
-
-extern void sgihpc_init(void);
-
-#endif /* _SGI_HPC3_H */
diff --git a/include/asm-mips/sgi/ioc.h b/include/asm-mips/sgi/ioc.h
deleted file mode 100644
index 343ed15f8dc4..000000000000
--- a/include/asm-mips/sgi/ioc.h
+++ /dev/null
@@ -1,200 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * ioc.h: Definitions for SGI I/O Controller
- *
- * Copyright (C) 1996 David S. Miller
- * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
- * Copyright (C) 2001, 2003 Ladislav Michl
- */
-
-#ifndef _SGI_IOC_H
-#define _SGI_IOC_H
-
-#include <linux/types.h>
-#include <asm/sgi/pi1.h>
-
-/*
- * All registers are 8-bit wide alligned on 32-bit boundary. Bad things
- * happen if you try word access them. You have been warned.
- */
-
-struct sgioc_uart_regs {
-        u8 _ctrl1[3];
-        volatile u8 ctrl1;
-        u8 _data1[3];
-        volatile u8 data1;
-        u8 _ctrl2[3];
-        volatile u8 ctrl2;
-        u8 _data2[3];
-        volatile u8 data2;
-};
-
-struct sgioc_keyb_regs {
-        u8 _data[3];
-        volatile u8 data;
-        u8 _command[3];
-        volatile u8 command;
-};
-
-struct sgint_regs {
-        u8 _istat0[3];
-        volatile u8 istat0;             /* Interrupt status zero */
-#define SGINT_ISTAT0_FFULL      0x01
-#define SGINT_ISTAT0_SCSI0      0x02
-#define SGINT_ISTAT0_SCSI1      0x04
-#define SGINT_ISTAT0_ENET       0x08
-#define SGINT_ISTAT0_GFXDMA     0x10
-#define SGINT_ISTAT0_PPORT      0x20
-#define SGINT_ISTAT0_HPC2       0x40
-#define SGINT_ISTAT0_LIO2       0x80
-        u8 _imask0[3];
-        volatile u8 imask0;             /* Interrupt mask zero */
-        u8 _istat1[3];
-        volatile u8 istat1;             /* Interrupt status one */
-#define SGINT_ISTAT1_ISDNI      0x01
-#define SGINT_ISTAT1_PWR        0x02
-#define SGINT_ISTAT1_ISDNH      0x04
-#define SGINT_ISTAT1_LIO3       0x08
-#define SGINT_ISTAT1_HPC3       0x10
-#define SGINT_ISTAT1_AFAIL      0x20
-#define SGINT_ISTAT1_VIDEO      0x40
-#define SGINT_ISTAT1_GIO2       0x80
-        u8 _imask1[3];
-        volatile u8 imask1;             /* Interrupt mask one */
-        u8 _vmeistat[3];
-        volatile u8 vmeistat;           /* VME interrupt status */
-        u8 _cmeimask0[3];
-        volatile u8 cmeimask0;          /* VME interrupt mask zero */
-        u8 _cmeimask1[3];
-        volatile u8 cmeimask1;          /* VME interrupt mask one */
-        u8 _cmepol[3];
-        volatile u8 cmepol;             /* VME polarity */
-        u8 _tclear[3];
-        volatile u8 tclear;
-        u8 _errstat[3];
-        volatile u8 errstat;    /* Error status reg, reserved on INT2 */
-        u32 _unused0[2];
-        u8 _tcnt0[3];
-        volatile u8 tcnt0;              /* counter 0 */
-        u8 _tcnt1[3];
-        volatile u8 tcnt1;              /* counter 1 */
-        u8 _tcnt2[3];
-        volatile u8 tcnt2;              /* counter 2 */
-        u8 _tcword[3];
-        volatile u8 tcword;             /* control word */
-#define SGINT_TCWORD_BCD        0x01    /* Use BCD mode for counters */
-#define SGINT_TCWORD_MMASK      0x0e    /* Mode bitmask. */
-#define SGINT_TCWORD_MITC       0x00    /* IRQ on terminal count (doesn't work) */
-#define SGINT_TCWORD_MOS        0x02    /* One-shot IRQ mode. */
-#define SGINT_TCWORD_MRGEN      0x04    /* Normal rate generation */
-#define SGINT_TCWORD_MSWGEN     0x06    /* Square wave generator mode */
-#define SGINT_TCWORD_MSWST      0x08    /* Software strobe */
-#define SGINT_TCWORD_MHWST      0x0a    /* Hardware strobe */
-#define SGINT_TCWORD_CMASK      0x30    /* Command mask */
-#define SGINT_TCWORD_CLAT       0x00    /* Latch command */
-#define SGINT_TCWORD_CLSB       0x10    /* LSB read/write */
-#define SGINT_TCWORD_CMSB       0x20    /* MSB read/write */
-#define SGINT_TCWORD_CALL       0x30    /* Full counter read/write */
-#define SGINT_TCWORD_CNT0       0x00    /* Select counter zero */
-#define SGINT_TCWORD_CNT1       0x40    /* Select counter one */
-#define SGINT_TCWORD_CNT2       0x80    /* Select counter two */
-#define SGINT_TCWORD_CRBCK      0xc0    /* Readback command */
-};
-
-/*
- * The timer is the good old 8254.  Unlike in PCs it's clocked at exactly 1MHz
- */
-#define SGINT_TIMER_CLOCK       1000000
-
-/*
- * This is the constant we're using for calibrating the counter.
- */
-#define SGINT_TCSAMP_COUNTER    ((SGINT_TIMER_CLOCK / HZ) + 255)
-
-/* We need software copies of these because they are write only. */
-extern u8 sgi_ioc_reset, sgi_ioc_write;
-
-struct sgioc_regs {
-        struct pi1_regs pport;
-        u32 _unused0[2];
-        struct sgioc_uart_regs uart;
-        struct sgioc_keyb_regs kbdmouse;
-        u8 _gcsel[3];
-        volatile u8 gcsel;
-        u8 _genctrl[3];
-        volatile u8 genctrl;
-        u8 _panel[3];
-        volatile u8 panel;
-#define SGIOC_PANEL_POWERON     0x01
-#define SGIOC_PANEL_POWERINTR   0x02
-#define SGIOC_PANEL_VOLDNINTR   0x10
-#define SGIOC_PANEL_VOLDNHOLD   0x20
-#define SGIOC_PANEL_VOLUPINTR   0x40
-#define SGIOC_PANEL_VOLUPHOLD   0x80
-        u32 _unused1;
-        u8 _sysid[3];
-        volatile u8 sysid;
-#define SGIOC_SYSID_FULLHOUSE   0x01
-#define SGIOC_SYSID_BOARDREV(x) (((x) & 0x1e) >> 1)
-#define SGIOC_SYSID_CHIPREV(x)  (((x) & 0xe0) >> 5)
-        u32 _unused2;
-        u8 _read[3];
-        volatile u8 read;
-        u32 _unused3;
-        u8 _dmasel[3];
-        volatile u8 dmasel;
-#define SGIOC_DMASEL_SCLK10MHZ  0x00    /* use 10MHZ serial clock */
-#define SGIOC_DMASEL_ISDNB      0x01    /* enable isdn B */
-#define SGIOC_DMASEL_ISDNA      0x02    /* enable isdn A */
-#define SGIOC_DMASEL_PPORT      0x04    /* use parallel DMA */
-#define SGIOC_DMASEL_SCLK667MHZ 0x10    /* use 6.67MHZ serial clock */
-#define SGIOC_DMASEL_SCLKEXT    0x20    /* use external serial clock */
-        u32 _unused4;
-        u8 _reset[3];
-        volatile u8 reset;
-#define SGIOC_RESET_PPORT       0x01    /* 0=parport reset, 1=nornal */
-#define SGIOC_RESET_KBDMOUSE    0x02    /* 0=kbdmouse reset, 1=normal */
-#define SGIOC_RESET_EISA        0x04    /* 0=eisa reset, 1=normal */
-#define SGIOC_RESET_ISDN        0x08    /* 0=isdn reset, 1=normal */
-#define SGIOC_RESET_LC0OFF      0x10    /* guiness: turn led off (red, else green) */
-#define SGIOC_RESET_LC1OFF      0x20    /* guiness: turn led off (green, else amber) */
-        u32 _unused5;
-        u8 _write[3];
-        volatile u8 write;
-#define SGIOC_WRITE_NTHRESH     0x01    /* use 4.5db threshhold */
-#define SGIOC_WRITE_TPSPEED     0x02    /* use 100ohm TP speed */
-#define SGIOC_WRITE_EPSEL       0x04    /* force cable mode: 1=AUI 0=TP */
-#define SGIOC_WRITE_EASEL       0x08    /* 1=autoselect 0=manual cable selection */
-#define SGIOC_WRITE_U1AMODE     0x10    /* 1=PC 0=MAC UART mode */
-#define SGIOC_WRITE_U0AMODE     0x20    /* 1=PC 0=MAC UART mode */
-#define SGIOC_WRITE_MLO         0x40    /* 1=4.75V 0=+5V */
-#define SGIOC_WRITE_MHI         0x80    /* 1=5.25V 0=+5V */
-        u32 _unused6;
-        struct sgint_regs int3;
-        u32 _unused7[16];
-        volatile u32 extio;             /* FullHouse only */
-#define EXTIO_S0_IRQ_3          0x8000  /* S0: vid.vsync */
-#define EXTIO_S0_IRQ_2          0x4000  /* S0: gfx.fifofull */
-#define EXTIO_S0_IRQ_1          0x2000  /* S0: gfx.int */
-#define EXTIO_S0_RETRACE        0x1000
-#define EXTIO_SG_IRQ_3          0x0800  /* SG: vid.vsync */
-#define EXTIO_SG_IRQ_2          0x0400  /* SG: gfx.fifofull */
-#define EXTIO_SG_IRQ_1          0x0200  /* SG: gfx.int */
-#define EXTIO_SG_RETRACE        0x0100
-#define EXTIO_GIO_33MHZ         0x0080
-#define EXTIO_EISA_BUSERR       0x0040
-#define EXTIO_MC_BUSERR         0x0020
-#define EXTIO_HPC3_BUSERR       0x0010
-#define EXTIO_S0_STAT_1         0x0008
-#define EXTIO_S0_STAT_0         0x0004
-#define EXTIO_SG_STAT_1         0x0002
-#define EXTIO_SG_STAT_0         0x0001
-};
-
-extern struct sgioc_regs *sgioc;
-extern struct sgint_regs *sgint;
-
-#endif
diff --git a/include/asm-mips/sgi/ip22.h b/include/asm-mips/sgi/ip22.h
deleted file mode 100644
index c0501f91719b..000000000000
--- a/include/asm-mips/sgi/ip22.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * ip22.h: Definitions for SGI IP22 machines
- *
- * Copyright (C) 1996 David S. Miller
- * Copyright (C) 1997, 1998, 1999, 2000 Ralf Baechle
- */
-
-#ifndef _SGI_IP22_H
-#define _SGI_IP22_H
-
-/*
- * These are the virtual IRQ numbers, we divide all IRQ's into
- * 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an SGI machine. HPC DMA and MC DMA interrupts
- * are not supported this way. Driver is supposed to allocate HPC/MC
- * interrupt as shareable and then look to proper status bit (see
- * HAL2 driver). This will prevent many complications, trust me ;-)
- */
-
-#include <irq.h>
-#include <asm/sgi/ioc.h>
-
-#define SGINT_EISA      0       /* 16 EISA irq levels (Indigo2) */
-#define SGINT_CPU       MIPS_CPU_IRQ_BASE       /* MIPS CPU define 8 interrupt sources */
-#define SGINT_LOCAL0    (SGINT_CPU+8)   /* 8 local0 irq levels */
-#define SGINT_LOCAL1    (SGINT_CPU+16)  /* 8 local1 irq levels */
-#define SGINT_LOCAL2    (SGINT_CPU+24)  /* 8 local2 vectored irq levels */
-#define SGINT_LOCAL3    (SGINT_CPU+32)  /* 8 local3 vectored irq levels */
-#define SGINT_END       (SGINT_CPU+40)  /* End of 'spaces' */
-
-/*
- * Individual interrupt definitions for the Indy and Indigo2
- */
-
-#define SGI_SOFT_0_IRQ  SGINT_CPU + 0
-#define SGI_SOFT_1_IRQ  SGINT_CPU + 1
-#define SGI_LOCAL_0_IRQ SGINT_CPU + 2
-#define SGI_LOCAL_1_IRQ SGINT_CPU + 3
-#define SGI_8254_0_IRQ  SGINT_CPU + 4
-#define SGI_8254_1_IRQ  SGINT_CPU + 5
-#define SGI_BUSERR_IRQ  SGINT_CPU + 6
-#define SGI_TIMER_IRQ   SGINT_CPU + 7
-
-#define SGI_FIFO_IRQ    SGINT_LOCAL0 + 0        /* FIFO full */
-#define SGI_GIO_0_IRQ   SGI_FIFO_IRQ            /* GIO-0 */
-#define SGI_WD93_0_IRQ  SGINT_LOCAL0 + 1        /* 1st onboard WD93 */
-#define SGI_WD93_1_IRQ  SGINT_LOCAL0 + 2        /* 2nd onboard WD93 */
-#define SGI_ENET_IRQ    SGINT_LOCAL0 + 3        /* onboard ethernet */
-#define SGI_MCDMA_IRQ   SGINT_LOCAL0 + 4        /* MC DMA done */
-#define SGI_PARPORT_IRQ SGINT_LOCAL0 + 5        /* Parallel port */
-#define SGI_GIO_1_IRQ   SGINT_LOCAL0 + 6        /* GE / GIO-1 / 2nd-HPC */
-#define SGI_MAP_0_IRQ   SGINT_LOCAL0 + 7        /* Mappable interrupt 0 */
-
-#define SGI_GPL0_IRQ    SGINT_LOCAL1 + 0        /* General Purpose LOCAL1_N<0> */
-#define SGI_PANEL_IRQ   SGINT_LOCAL1 + 1        /* front panel */
-#define SGI_GPL2_IRQ    SGINT_LOCAL1 + 2        /* General Purpose LOCAL1_N<2> */
-#define SGI_MAP_1_IRQ   SGINT_LOCAL1 + 3        /* Mappable interrupt 1 */
-#define SGI_HPCDMA_IRQ  SGINT_LOCAL1 + 4        /* HPC DMA done */
-#define SGI_ACFAIL_IRQ  SGINT_LOCAL1 + 5        /* AC fail */
-#define SGI_VINO_IRQ    SGINT_LOCAL1 + 6        /* Indy VINO */
-#define SGI_GIO_2_IRQ   SGINT_LOCAL1 + 7        /* Vert retrace / GIO-2 */
-
-/* Mapped interrupts. These interrupts may be mapped to either 0, or 1 */
-#define SGI_VERT_IRQ    SGINT_LOCAL2 + 0        /* INT3: newport vertical status */
-#define SGI_EISA_IRQ    SGINT_LOCAL2 + 3        /* EISA interrupts */
-#define SGI_KEYBD_IRQ   SGINT_LOCAL2 + 4        /* keyboard */
-#define SGI_SERIAL_IRQ  SGINT_LOCAL2 + 5        /* onboard serial */
-
-#define ip22_is_fullhouse()     (sgioc->sysid & SGIOC_SYSID_FULLHOUSE)
-
-extern unsigned short ip22_eeprom_read(unsigned int *ctrl, int reg);
-extern unsigned short ip22_nvram_read(int reg);
-
-#endif
diff --git a/include/asm-mips/sgi/mc.h b/include/asm-mips/sgi/mc.h
deleted file mode 100644
index 1576c2394de8..000000000000
--- a/include/asm-mips/sgi/mc.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License. See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * mc.h: Definitions for SGI Memory Controller
- *
- * Copyright (C) 1996 David S. Miller
- * Copyright (C) 1999 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-
-#ifndef _SGI_MC_H
-#define _SGI_MC_H
-
-struct sgimc_regs {
-        u32 _unused0;
-        volatile u32 cpuctrl0;  /* CPU control register 0, readwrite */
-#define SGIMC_CCTRL0_REFS       0x0000000f /* REFS mask */
-#define SGIMC_CCTRL0_EREFRESH   0x00000010 /* Memory refresh enable */
-#define SGIMC_CCTRL0_EPERRGIO   0x00000020 /* GIO parity error enable */
-#define SGIMC_CCTRL0_EPERRMEM   0x00000040 /* Main mem parity error enable */
-#define SGIMC_CCTRL0_EPERRCPU   0x00000080 /* CPU bus parity error enable */
-#define SGIMC_CCTRL0_WDOG       0x00000100 /* Watchdog timer enable */
-#define SGIMC_CCTRL0_SYSINIT    0x00000200 /* System init bit */
-#define SGIMC_CCTRL0_GFXRESET   0x00000400 /* Graphics interface reset */
-#define SGIMC_CCTRL0_EISALOCK   0x00000800 /* Lock CPU from memory for EISA */
-#define SGIMC_CCTRL0_EPERRSCMD  0x00001000 /* SysCMD bus parity error enable */
-#define SGIMC_CCTRL0_IENAB      0x00002000 /* Allow interrupts from MC */
-#define SGIMC_CCTRL0_ESNOOP     0x00004000 /* Snooping I/O enable */
-#define SGIMC_CCTRL0_EPROMWR    0x00008000 /* Prom writes from cpu enable */
-#define SGIMC_CCTRL0_WRESETPMEM 0x00010000 /* Perform warm reset, preserves mem */
-#define SGIMC_CCTRL0_LENDIAN    0x00020000 /* Put MC in little-endian mode */
-#define SGIMC_CCTRL0_WRESETDMEM 0x00040000 /* Warm reset, destroys mem contents */
-#define SGIMC_CCTRL0_CMEMBADPAR 0x02000000 /* Generate bad perr from cpu to mem */
-#define SGIMC_CCTRL0_R4KNOCHKPARR 0x04000000 /* Don't chk parity on mem data reads */
-#define SGIMC_CCTRL0_GIOBTOB    0x08000000 /* Allow GIO back to back writes */
-        u32 _unused1;
-        volatile u32 cpuctrl1;  /* CPU control register 1, readwrite */
-#define SGIMC_CCTRL1_EGIOTIMEO  0x00000010 /* GIO bus timeout enable */
-#define SGIMC_CCTRL1_FIXEDEHPC  0x00001000 /* Fixed HPC endianness */
-#define SGIMC_CCTRL1_LITTLEHPC  0x00002000 /* Little endian HPC */
-#define SGIMC_CCTRL1_FIXEDEEXP0 0x00004000 /* Fixed EXP0 endianness */
-#define SGIMC_CCTRL1_LITTLEEXP0 0x00008000 /* Little endian EXP0 */
-#define SGIMC_CCTRL1_FIXEDEEXP1 0x00010000 /* Fixed EXP1 endianness */
-#define SGIMC_CCTRL1_LITTLEEXP1 0x00020000 /* Little endian EXP1 */
-
-        u32 _unused2;
-        volatile u32 watchdogt; /* Watchdog reg rdonly, write clears */
-
-        u32 _unused3;
-        volatile u32 systemid;  /* MC system ID register, readonly */
-#define SGIMC_SYSID_MASKREV     0x0000000f /* Revision of MC controller */
-#define SGIMC_SYSID_EPRESENT    0x00000010 /* Indicates presence of EISA bus */
-
-        u32 _unused4[3];
-        volatile u32 divider;   /* Divider reg for RPSS */
-
-        u32 _unused5;
-        u32 eeprom;             /* EEPROM byte reg for r4k */
-#define SGIMC_EEPROM_PRE        0x00000001 /* eeprom chip PRE pin assertion */
-#define SGIMC_EEPROM_CSEL       0x00000002 /* Active high, eeprom chip select */
-#define SGIMC_EEPROM_SECLOCK    0x00000004 /* EEPROM serial clock */
-#define SGIMC_EEPROM_SDATAO     0x00000008 /* Serial EEPROM data-out */
-#define SGIMC_EEPROM_SDATAI     0x00000010 /* Serial EEPROM data-in */
-
-        u32 _unused6[3];
-        volatile u32 rcntpre;   /* Preload refresh counter */
-
-        u32 _unused7;
-        volatile u32 rcounter;  /* Readonly refresh counter */
-
-        u32 _unused8[13];
-        volatile u32 giopar;    /* Parameter word for GIO64 */
-#define SGIMC_GIOPAR_HPC64      0x00000001 /* HPC talks to GIO using 64-bits */
-#define SGIMC_GIOPAR_GFX64      0x00000002 /* GFX talks to GIO using 64-bits */
-#define SGIMC_GIOPAR_EXP064     0x00000004 /* EXP(slot0) talks using 64-bits */
-#define SGIMC_GIOPAR_EXP164     0x00000008 /* EXP(slot1) talks using 64-bits */
-#define SGIMC_GIOPAR_EISA64     0x00000010 /* EISA bus talks 64-bits to GIO */
-#define SGIMC_GIOPAR_HPC264     0x00000020 /* 2nd HPX talks 64-bits to GIO */
-#define SGIMC_GIOPAR_RTIMEGFX   0x00000040 /* GFX device has realtime attr */
-#define SGIMC_GIOPAR_RTIMEEXP0  0x00000080 /* EXP(slot0) has realtime attr */
-#define SGIMC_GIOPAR_RTIMEEXP1  0x00000100 /* EXP(slot1) has realtime attr */
-#define SGIMC_GIOPAR_MASTEREISA 0x00000200 /* EISA bus can act as bus master */
-#define SGIMC_GIOPAR_ONEBUS     0x00000400 /* Exists one GIO64 pipelined bus */
-#define SGIMC_GIOPAR_MASTERGFX  0x00000800 /* GFX can act as a bus master */
-#define SGIMC_GIOPAR_MASTEREXP0 0x00001000 /* EXP(slot0) can bus master */
-#define SGIMC_GIOPAR_MASTEREXP1 0x00002000 /* EXP(slot1) can bus master */
-#define SGIMC_GIOPAR_PLINEEXP0  0x00004000 /* EXP(slot0) has pipeline attr */
-#define SGIMC_GIOPAR_PLINEEXP1  0x00008000 /* EXP(slot1) has pipeline attr */
-
-        u32 _unused9;
-        volatile u32 cputp;     /* CPU bus arb time period */
-
-        u32 _unused10[3];
-        volatile u32 lbursttp;  /* Time period for long bursts */
-
-        /* MC chip can drive up to 4 bank 4 SIMMs each. All SIMMs in bank must
-         * be the same size. The size encoding for supported SIMMs is bellow */
-        u32 _unused11[9];
-        volatile u32 mconfig0;  /* Memory config register zero */
-        u32 _unused12;
-        volatile u32 mconfig1;  /* Memory config register one */
-#define SGIMC_MCONFIG_BASEADDR  0x000000ff /* Base address of bank*/
-#define SGIMC_MCONFIG_RMASK     0x00001f00 /* Ram config bitmask */
-#define SGIMC_MCONFIG_BVALID    0x00002000 /* Bank is valid */
-#define SGIMC_MCONFIG_SBANKS    0x00004000 /* Number of subbanks */
-
-        u32 _unused13;
-        volatile u32 cmacc;        /* Mem access config for CPU */
-        u32 _unused14;
-        volatile u32 gmacc;        /* Mem access config for GIO */
-
-        /* This define applies to both cmacc and gmacc registers above. */
-#define SGIMC_MACC_ALIASBIG     0x20000000 /* 512MB home for alias */
-
-        /* Error address/status regs from GIO and CPU perspectives. */
-        u32 _unused15;
-        volatile u32 cerr;      /* Error address reg for CPU */
-        u32 _unused16;
-        volatile u32 cstat;     /* Status reg for CPU */
-#define SGIMC_CSTAT_RD          0x00000100 /* read parity error */
-#define SGIMC_CSTAT_PAR         0x00000200 /* CPU parity error */
-#define SGIMC_CSTAT_ADDR        0x00000400 /* memory bus error bad addr */
-#define SGIMC_CSTAT_SYSAD_PAR   0x00000800 /* sysad parity error */
-#define SGIMC_CSTAT_SYSCMD_PAR  0x00001000 /* syscmd parity error */
-#define SGIMC_CSTAT_BAD_DATA    0x00002000 /* bad data identifier */
-#define SGIMC_CSTAT_PAR_MASK    0x00001f00 /* parity error mask */
-#define SGIMC_CSTAT_RD_PAR      (SGIMC_CSTAT_RD | SGIMC_CSTAT_PAR)
-
-        u32 _unused17;
-        volatile u32 gerr;      /* Error address reg for GIO */
-        u32 _unused18;
-        volatile u32 gstat;     /* Status reg for GIO */
-#define SGIMC_GSTAT_RD          0x00000100 /* read parity error */
-#define SGIMC_GSTAT_WR          0x00000200 /* write parity error */
-#define SGIMC_GSTAT_TIME        0x00000400 /* GIO bus timed out */
-#define SGIMC_GSTAT_PROM        0x00000800 /* write to PROM when PROM_EN not set */
-#define SGIMC_GSTAT_ADDR        0x00001000 /* parity error on addr cycle */
-#define SGIMC_GSTAT_BC          0x00002000 /* parity error on byte count cycle */
-#define SGIMC_GSTAT_PIO_RD      0x00004000 /* read data parity on pio */
-#define SGIMC_GSTAT_PIO_WR      0x00008000 /* write data parity on pio */
-
-        /* Special hard bus locking registers. */
-        u32 _unused19;
-        volatile u32 syssembit;         /* Uni-bit system semaphore */
-        u32 _unused20;
-        volatile u32 mlock;             /* Global GIO memory access lock */
-        u32 _unused21;
-        volatile u32 elock;             /* Locks EISA from GIO accesses */
-
-        /* GIO dma control registers. */
-        u32 _unused22[15];
-        volatile u32 gio_dma_trans;     /* DMA mask to translation GIO addrs */
-        u32 _unused23;
-        volatile u32 gio_dma_sbits;     /* DMA GIO addr substitution bits */
-        u32 _unused24;
-        volatile u32 dma_intr_cause;    /* DMA IRQ cause indicator bits */
-        u32 _unused25;
-        volatile u32 dma_ctrl;          /* Main DMA control reg */
-
-        /* DMA TLB entry 0 */
-        u32 _unused26[5];
-        volatile u32 dtlb_hi0;
-        u32 _unused27;
-        volatile u32 dtlb_lo0;
-
-        /* DMA TLB entry 1 */
-        u32 _unused28;
-        volatile u32 dtlb_hi1;
-        u32 _unused29;
-        volatile u32 dtlb_lo1;
-
-        /* DMA TLB entry 2 */
-        u32 _unused30;
-        volatile u32 dtlb_hi2;
-        u32 _unused31;
-        volatile u32 dtlb_lo2;
-
-        /* DMA TLB entry 3 */
-        u32 _unused32;
-        volatile u32 dtlb_hi3;
-        u32 _unused33;
-        volatile u32 dtlb_lo3;
-
-        u32 _unused34[0x0392];
-
-        u32 _unused35;
-        volatile u32 rpsscounter;       /* Chirps at 100ns */
-
-        u32 _unused36[0x1000/4-2*4];
-
-        u32 _unused37;
-        volatile u32 maddronly;         /* Address DMA goes at */
-        u32 _unused38;
-        volatile u32 maddrpdeflts;      /* Same as above, plus set defaults */
-        u32 _unused39;
-        volatile u32 dmasz;             /* DMA count */
-        u32 _unused40;
-        volatile u32 ssize;             /* DMA stride size */
-        u32 _unused41;
-        volatile u32 gmaddronly;        /* Set GIO DMA but don't start trans */
-        u32 _unused42;
-        volatile u32 dmaddnpgo;         /* Set GIO DMA addr + start transfer */
-        u32 _unused43;
-        volatile u32 dmamode;           /* DMA mode config bit settings */
-        u32 _unused44;
-        volatile u32 dmaccount;         /* Zoom and byte count for DMA */
-        u32 _unused45;
-        volatile u32 dmastart;          /* Pedal to the metal. */
-        u32 _unused46;
-        volatile u32 dmarunning;        /* DMA op is in progress */
-        u32 _unused47;
-        volatile u32 maddrdefstart;     /* Set dma addr, defaults, and kick it */
-};
-
-extern struct sgimc_regs *sgimc;
-#define SGIMC_BASE              0x1fa00000      /* physical */
-
-/* Base location of the two ram banks found in IP2[0268] machines. */
-#define SGIMC_SEG0_BADDR        0x08000000
-#define SGIMC_SEG1_BADDR        0x20000000
-
-/* Maximum size of the above banks are per machine. */
-#define SGIMC_SEG0_SIZE_ALL             0x10000000 /* 256MB */
-#define SGIMC_SEG1_SIZE_IP20_IP22       0x08000000 /* 128MB */
-#define SGIMC_SEG1_SIZE_IP26_IP28       0x20000000 /* 512MB */
-
-extern void sgimc_init(void);
-
-#endif /* _SGI_MC_H */
diff --git a/include/asm-mips/sgi/pi1.h b/include/asm-mips/sgi/pi1.h
deleted file mode 100644
index c9506915dc5c..000000000000
--- a/include/asm-mips/sgi/pi1.h
+++ /dev/null
@@ -1,71 +0,0 @@
-/*
- * pi1.h: Definitions for SGI PI1 parallel port
- */
-
-#ifndef _SGI_PI1_H
-#define _SGI_PI1_H
-
-struct pi1_regs {
-        u8 _data[3];
-        volatile u8 data;
-        u8 _ctrl[3];
-        volatile u8 ctrl;
-#define PI1_CTRL_STROBE_N       0x01
-#define PI1_CTRL_AFD_N          0x02
-#define PI1_CTRL_INIT_N         0x04
-#define PI1_CTRL_SLIN_N         0x08
-#define PI1_CTRL_IRQ_ENA        0x10
-#define PI1_CTRL_DIR            0x20
-#define PI1_CTRL_SEL            0x40
-        u8 _status[3];
-        volatile u8 status;
-#define PI1_STAT_DEVID          0x03    /* bits 0-1 */
-#define PI1_STAT_NOINK          0x04    /* SGI MODE only */
-#define PI1_STAT_ERROR          0x08
-#define PI1_STAT_ONLINE         0x10
-#define PI1_STAT_PE             0x20
-#define PI1_STAT_ACK            0x40
-#define PI1_STAT_BUSY           0x80
-        u8 _dmactrl[3];
-        volatile u8 dmactrl;
-#define PI1_DMACTRL_FIFO_EMPTY  0x01    /* fifo empty R/O */
-#define PI1_DMACTRL_ABORT       0x02    /* reset DMA and internal fifo W/O */
-#define PI1_DMACTRL_STDMODE     0x00    /* bits 2-3 */
-#define PI1_DMACTRL_SGIMODE     0x04    /* bits 2-3 */
-#define PI1_DMACTRL_RICOHMODE   0x08    /* bits 2-3 */
-#define PI1_DMACTRL_HPMODE      0x0c    /* bits 2-3 */
-#define PI1_DMACTRL_BLKMODE     0x10    /* block mode */
-#define PI1_DMACTRL_FIFO_CLEAR  0x20    /* clear fifo W/O */
-#define PI1_DMACTRL_READ        0x40    /* read */
-#define PI1_DMACTRL_RUN         0x80    /* pedal to the metal */
-        u8 _intstat[3];
-        volatile u8 intstat;
-#define PI1_INTSTAT_ACK         0x04
-#define PI1_INTSTAT_FEMPTY      0x08
-#define PI1_INTSTAT_NOINK       0x10
-#define PI1_INTSTAT_ONLINE      0x20
-#define PI1_INTSTAT_ERR         0x40
-#define PI1_INTSTAT_PE          0x80
-        u8 _intmask[3];
-        volatile u8 intmask;            /* enabled low, reset high*/
-#define PI1_INTMASK_ACK         0x04
-#define PI1_INTMASK_FIFO_EMPTY  0x08
-#define PI1_INTMASK_NOINK       0x10
-#define PI1_INTMASK_ONLINE      0x20
-#define PI1_INTMASK_ERR         0x40
-#define PI1_INTMASK_PE          0x80
-        u8 _timer1[3];
-        volatile u8 timer1;
-#define PI1_TIME1               0x27
-        u8 _timer2[3];
-        volatile u8 timer2;
-#define PI1_TIME2               0x13
-        u8 _timer3[3];
-        volatile u8 timer3;
-#define PI1_TIME3               0x10
-        u8 _timer4[3];
-        volatile u8 timer4;
-#define PI1_TIME4               0x00
-};
-
-#endif
diff --git a/include/asm-mips/sgi/seeq.h b/include/asm-mips/sgi/seeq.h
deleted file mode 100644
index af0ffd76899d..000000000000
--- a/include/asm-mips/sgi/seeq.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 by Ralf Baechle
- */
-#ifndef __ASM_SGI_SEEQ_H
-#define __ASM_SGI_SEEQ_H
-
-#include <linux/if_ether.h>
-
-#include <asm/sgi/hpc3.h>
-
-struct sgiseeq_platform_data {
-        struct hpc3_regs *hpc;
-        unsigned int irq;
-        unsigned char mac[ETH_ALEN];
-};
-
-#endif /* __ASM_SGI_SEEQ_H */
diff --git a/include/asm-mips/sgi/sgi.h b/include/asm-mips/sgi/sgi.h
deleted file mode 100644
index 645cea7c0f8e..000000000000
--- a/include/asm-mips/sgi/sgi.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * sgi.h: Definitions specific to SGI machines.
- *
- * Copyright (C) 1996 David S. Miller (dm@sgi.com)
- */
-#ifndef _ASM_SGI_SGI_H
-#define _ASM_SGI_SGI_H
-
-/* UP=UniProcessor MP=MultiProcessor(capable) */
-enum sgi_mach {
-        ip4,    /* R2k UP */
-        ip5,    /* R2k MP */
-        ip6,    /* R3k UP */
-        ip7,    /* R3k MP */
-        ip9,    /* R3k UP */
-        ip12,   /* R3kA UP, Indigo */
-        ip15,   /* R3kA MP */
-        ip17,   /* R4K UP */
-        ip19,   /* R4K MP */
-        ip20,   /* R4K UP, Indigo */
-        ip21,   /* TFP MP */
-        ip22,   /* R4x00 UP, Indigo2 */
-        ip25,   /* R10k MP */
-        ip26,   /* TFP UP, Indigo2 */
-        ip27,   /* R10k MP, R12k MP, Origin */
-        ip28,   /* R10k UP, Indigo2 */
-        ip30,   /* Octane */
-        ip32,   /* O2 */
-};
-
-extern enum sgi_mach sgimach;
-extern void sgi_sysinit(void);
-
-/* Many I/O space registers are byte sized and are contained within
- * one byte per word, specifically the MSB, this macro helps out.
- */
-#ifdef __MIPSEL__
-#define SGI_MSB(regaddr)   (regaddr)
-#else
-#define SGI_MSB(regaddr)   ((regaddr) | 0x3)
-#endif
-
-#endif /* _ASM_SGI_SGI_H */
diff --git a/include/asm-mips/sgi/wd.h b/include/asm-mips/sgi/wd.h
deleted file mode 100644
index 0d6c3a4da891..000000000000
--- a/include/asm-mips/sgi/wd.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 by Ralf Baechle
- */
-#ifndef __ASM_SGI_WD_H
-#define __ASM_SGI_WD_H
-
-#include <asm/sgi/hpc3.h>
-
-struct sgiwd93_platform_data {
-        unsigned int unit;
-        unsigned int irq;
-        struct hpc3_scsiregs *hregs;
-        unsigned char *wdregs;
-};
-
-#endif /* __ASM_SGI_WD_H */
diff --git a/include/asm-mips/sgialib.h b/include/asm-mips/sgialib.h
deleted file mode 100644
index bfce5c786f1c..000000000000
--- a/include/asm-mips/sgialib.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI ARCS firmware interface library for the Linux kernel.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 2001, 2002 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_SGIALIB_H
-#define _ASM_SGIALIB_H
-
-#include <asm/sgiarcs.h>
-
-extern struct linux_romvec *romvec;
-extern int prom_argc;
-
-extern LONG *_prom_argv, *_prom_envp;
-
-/* A 32-bit ARC PROM pass arguments and environment as 32-bit pointer.
-   These macros take care of sign extension.  */
-#define prom_argv(index) ((char *) (long) _prom_argv[(index)])
-#define prom_argc(index) ((char *) (long) _prom_argc[(index)])
-
-extern int prom_flags;
-
-#define PROM_FLAG_ARCS                  1
-#define PROM_FLAG_USE_AS_CONSOLE        2
-#define PROM_FLAG_DONT_FREE_TEMP        4
-
-/* Simple char-by-char console I/O. */
-extern void prom_putchar(char c);
-extern char prom_getchar(void);
-
-/* Memory descriptor management. */
-#define PROM_MAX_PMEMBLOCKS    32
-struct prom_pmemblock {
-        LONG    base;           /* Within KSEG0 or XKPHYS. */
-        ULONG   size;           /* In bytes. */
-        ULONG   type;           /* free or prom memory */
-};
-
-/* Get next memory descriptor after CURR, returns first descriptor
- * in chain is CURR is NULL.
- */
-extern struct linux_mdesc *prom_getmdesc(struct linux_mdesc *curr);
-#define PROM_NULL_MDESC   ((struct linux_mdesc *) 0)
-
-/* Called by prom_init to setup the physical memory pmemblock
- * array.
- */
-extern void prom_meminit(void);
-extern void prom_fixup_mem_map(unsigned long start_mem, unsigned long end_mem);
-
-/* PROM device tree library routines. */
-#define PROM_NULL_COMPONENT ((pcomponent *) 0)
-
-/* Get sibling component of THIS. */
-extern pcomponent *ArcGetPeer(pcomponent *this);
-
-/* Get child component of THIS. */
-extern pcomponent *ArcGetChild(pcomponent *this);
-
-/* Get parent component of CHILD. */
-extern pcomponent *prom_getparent(pcomponent *child);
-
-/* Copy component opaque data of component THIS into BUFFER
- * if component THIS has opaque data.  Returns success or
- * failure status.
- */
-extern long prom_getcdata(void *buffer, pcomponent *this);
-
-/* Other misc. component routines. */
-extern pcomponent *prom_childadd(pcomponent *this, pcomponent *tmp, void *data);
-extern long prom_delcomponent(pcomponent *this);
-extern pcomponent *prom_componentbypath(char *path);
-
-/* This is called at prom_init time to identify the
- * ARC architecture we are running on
- */
-extern void prom_identify_arch(void);
-
-/* Environment variable routines. */
-extern PCHAR ArcGetEnvironmentVariable(PCHAR name);
-extern LONG ArcSetEnvironmentVariable(PCHAR name, PCHAR value);
-
-/* ARCS command line acquisition and parsing. */
-extern char *prom_getcmdline(void);
-extern void prom_init_cmdline(void);
-
-/* Acquiring info about the current time, etc. */
-extern struct linux_tinfo *prom_gettinfo(void);
-extern unsigned long prom_getrtime(void);
-
-/* File operations. */
-extern long prom_getvdirent(unsigned long fd, struct linux_vdirent *ent, unsigned long num, unsigned long *cnt);
-extern long prom_open(char *name, enum linux_omode md, unsigned long *fd);
-extern long prom_close(unsigned long fd);
-extern LONG ArcRead(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
-extern long prom_getrstatus(unsigned long fd);
-extern LONG ArcWrite(ULONG fd, PVOID buf, ULONG num, PULONG cnt);
-extern long prom_seek(unsigned long fd, struct linux_bigint *off, enum linux_seekmode sm);
-extern long prom_mount(char *name, enum linux_mountops op);
-extern long prom_getfinfo(unsigned long fd, struct linux_finfo *buf);
-extern long prom_setfinfo(unsigned long fd, unsigned long flags, unsigned long msk);
-
-/* Running stand-along programs. */
-extern long prom_load(char *name, unsigned long end, unsigned long *pc, unsigned long *eaddr);
-extern long prom_invoke(unsigned long pc, unsigned long sp, long argc, char **argv, char **envp);
-extern long prom_exec(char *name, long argc, char **argv, char **envp);
-
-/* Misc. routines. */
-extern VOID prom_halt(VOID) __attribute__((noreturn));
-extern VOID prom_powerdown(VOID) __attribute__((noreturn));
-extern VOID prom_restart(VOID) __attribute__((noreturn));
-extern VOID ArcReboot(VOID) __attribute__((noreturn));
-extern VOID ArcEnterInteractiveMode(VOID) __attribute__((noreturn));
-extern long prom_cfgsave(VOID);
-extern struct linux_sysid *prom_getsysid(VOID);
-extern VOID ArcFlushAllCaches(VOID);
-extern DISPLAY_STATUS *ArcGetDisplayStatus(ULONG FileID);
-
-#endif /* _ASM_SGIALIB_H */
diff --git a/include/asm-mips/sgiarcs.h b/include/asm-mips/sgiarcs.h
deleted file mode 100644
index 721327f88601..000000000000
--- a/include/asm-mips/sgiarcs.h
+++ /dev/null
@@ -1,548 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * ARC firmware interface defines.
- *
- * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
- * Copyright (C) 1999, 2001 Ralf Baechle (ralf@gnu.org)
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SGIARCS_H
-#define _ASM_SGIARCS_H
-
-#include <asm/types.h>
-#include <asm/fw/arc/types.h>
-
-/* Various ARCS error codes. */
-#define PROM_ESUCCESS                   0x00
-#define PROM_E2BIG                      0x01
-#define PROM_EACCESS                    0x02
-#define PROM_EAGAIN                     0x03
-#define PROM_EBADF                      0x04
-#define PROM_EBUSY                      0x05
-#define PROM_EFAULT                     0x06
-#define PROM_EINVAL                     0x07
-#define PROM_EIO                        0x08
-#define PROM_EISDIR                     0x09
-#define PROM_EMFILE                     0x0a
-#define PROM_EMLINK                     0x0b
-#define PROM_ENAMETOOLONG               0x0c
-#define PROM_ENODEV                     0x0d
-#define PROM_ENOENT                     0x0e
-#define PROM_ENOEXEC                    0x0f
-#define PROM_ENOMEM                     0x10
-#define PROM_ENOSPC                     0x11
-#define PROM_ENOTDIR                    0x12
-#define PROM_ENOTTY                     0x13
-#define PROM_ENXIO                      0x14
-#define PROM_EROFS                      0x15
-/* SGI ARCS specific errno's. */
-#define PROM_EADDRNOTAVAIL              0x1f
-#define PROM_ETIMEDOUT                  0x20
-#define PROM_ECONNABORTED               0x21
-#define PROM_ENOCONNECT                 0x22
-
-/* Device classes, types, and identifiers for prom
- * device inventory queries.
- */
-enum linux_devclass {
-        system, processor, cache, adapter, controller, peripheral, memory
-};
-
-enum linux_devtypes {
-        /* Generic stuff. */
-        Arc, Cpu, Fpu,
-
-        /* Primary insn and data caches. */
-        picache, pdcache,
-
-        /* Secondary insn, data, and combined caches. */
-        sicache, sdcache, sccache,
-
-        memdev, eisa_adapter, tc_adapter, scsi_adapter, dti_adapter,
-        multifunc_adapter, dsk_controller, tp_controller, cdrom_controller,
-        worm_controller, serial_controller, net_controller, disp_controller,
-        parallel_controller, ptr_controller, kbd_controller, audio_controller,
-        misc_controller, disk_peripheral, flpy_peripheral, tp_peripheral,
-        modem_peripheral, monitor_peripheral, printer_peripheral,
-        ptr_peripheral, kbd_peripheral, term_peripheral, line_peripheral,
-        net_peripheral, misc_peripheral, anon
-};
-
-enum linux_identifier {
-        bogus, ronly, removable, consin, consout, input, output
-};
-
-/* A prom device tree component. */
-struct linux_component {
-        enum linux_devclass     class;  /* node class */
-        enum linux_devtypes     type;   /* node type */
-        enum linux_identifier   iflags; /* node flags */
-        USHORT                  vers;   /* node version */
-        USHORT                  rev;    /* node revision */
-        ULONG                   key;    /* completely magic */
-        ULONG                   amask;  /* XXX affinity mask??? */
-        ULONG                   cdsize; /* size of configuration data */
-        ULONG                   ilen;   /* length of string identifier */
-        _PULONG                 iname;  /* string identifier */
-};
-typedef struct linux_component pcomponent;
-
-struct linux_sysid {
-        char vend[8], prod[8];
-};
-
-/* ARCS prom memory descriptors. */
-enum arcs_memtypes {
-        arcs_eblock,  /* exception block */
-        arcs_rvpage,  /* ARCS romvec page */
-        arcs_fcontig, /* Contiguous and free */
-        arcs_free,    /* Generic free memory */
-        arcs_bmem,    /* Borken memory, don't use */
-        arcs_prog,    /* A loaded program resides here */
-        arcs_atmp,    /* ARCS temporary storage area, wish Sparc OpenBoot told this */
-        arcs_aperm,   /* ARCS permanent storage... */
-};
-
-/* ARC has slightly different types than ARCS */
-enum arc_memtypes {
-        arc_eblock,  /* exception block */
-        arc_rvpage,  /* romvec page */
-        arc_free,    /* Generic free memory */
-        arc_bmem,    /* Borken memory, don't use */
-        arc_prog,    /* A loaded program resides here */
-        arc_atmp,    /* temporary storage area */
-        arc_aperm,   /* permanent storage */
-        arc_fcontig, /* Contiguous and free */
-};
-
-union linux_memtypes {
-    enum arcs_memtypes arcs;
-    enum arc_memtypes arc;
-};
-
-struct linux_mdesc {
-        union linux_memtypes type;
-        ULONG base;
-        ULONG pages;
-};
-
-/* Time of day descriptor. */
-struct linux_tinfo {
-        unsigned short yr;
-        unsigned short mnth;
-        unsigned short day;
-        unsigned short hr;
-        unsigned short min;
-        unsigned short sec;
-        unsigned short msec;
-};
-
-/* ARCS virtual dirents. */
-struct linux_vdirent {
-        ULONG namelen;
-        unsigned char attr;
-        char fname[32]; /* XXX imperical, should be a define */
-};
-
-/* Other stuff for files. */
-enum linux_omode {
-        rdonly, wronly, rdwr, wronly_creat, rdwr_creat,
-        wronly_ssede, rdwr_ssede, dirent, dirent_creat
-};
-
-enum linux_seekmode {
-        absolute, relative
-};
-
-enum linux_mountops {
-        media_load, media_unload
-};
-
-/* This prom has a bolixed design. */
-struct linux_bigint {
-#ifdef __MIPSEL__
-        u32 lo;
-        s32 hi;
-#else /* !(__MIPSEL__) */
-        s32 hi;
-        u32 lo;
-#endif
-};
-
-struct linux_finfo {
-        struct linux_bigint   begin;
-        struct linux_bigint   end;
-        struct linux_bigint   cur;
-        enum linux_devtypes   dtype;
-        unsigned long         namelen;
-        unsigned char         attr;
-        char                  name[32]; /* XXX imperical, should be define */
-};
-
-/* This describes the vector containing function pointers to the ARC
-   firmware functions.  */
-struct linux_romvec {
-        LONG    load;                   /* Load an executable image. */
-        LONG    invoke;                 /* Invoke a standalong image. */
-        LONG    exec;                   /* Load and begin execution of a
-                                           standalone image. */
-        LONG    halt;                   /* Halt the machine. */
-        LONG    pdown;                  /* Power down the machine. */
-        LONG    restart;                /* XXX soft reset??? */
-        LONG    reboot;                 /* Reboot the machine. */
-        LONG    imode;                  /* Enter PROM interactive mode. */
-        LONG    _unused1;               /* Was ReturnFromMain(). */
-
-        /* PROM device tree interface. */
-        LONG    next_component;
-        LONG    child_component;
-        LONG    parent_component;
-        LONG    component_data;
-        LONG    child_add;
-        LONG    comp_del;
-        LONG    component_by_path;
-
-        /* Misc. stuff. */
-        LONG    cfg_save;
-        LONG    get_sysid;
-
-        /* Probing for memory. */
-        LONG    get_mdesc;
-        LONG    _unused2;               /* was Signal() */
-
-        LONG    get_tinfo;
-        LONG    get_rtime;
-
-        /* File type operations. */
-        LONG    get_vdirent;
-        LONG    open;
-        LONG    close;
-        LONG    read;
-        LONG    get_rstatus;
-        LONG    write;
-        LONG    seek;
-        LONG    mount;
-
-        /* Dealing with firmware environment variables. */
-        LONG    get_evar;
-        LONG    set_evar;
-
-        LONG    get_finfo;
-        LONG    set_finfo;
-
-        /* Miscellaneous. */
-        LONG    cache_flush;
-        LONG    TestUnicodeCharacter;           /* ARC; not sure if ARCS too */
-        LONG    GetDisplayStatus;
-};
-
-/* The SGI ARCS parameter block is in a fixed location for standalone
- * programs to access PROM facilities easily.
- */
-typedef struct _SYSTEM_PARAMETER_BLOCK {
-        ULONG                   magic;          /* magic cookie */
-#define PROMBLOCK_MAGIC      0x53435241
-
-        ULONG                   len;            /* length of parm block */
-        USHORT                  ver;            /* ARCS firmware version */
-        USHORT                  rev;            /* ARCS firmware revision */
-        _PLONG                  rs_block;       /* Restart block. */
-        _PLONG                  dbg_block;      /* Debug block. */
-        _PLONG                  gevect;         /* XXX General vector??? */
-        _PLONG                  utlbvect;       /* XXX UTLB vector??? */
-        ULONG                   rveclen;        /* Size of romvec struct. */
-        _PVOID                  romvec;         /* Function interface. */
-        ULONG                   pveclen;        /* Length of private vector. */
-        _PVOID                  pvector;        /* Private vector. */
-        ULONG                   adap_cnt;       /* Adapter count. */
-        ULONG                   adap_typ0;      /* First adapter type. */
-        ULONG                   adap_vcnt0;     /* Adapter 0 vector count. */
-        _PVOID                  adap_vector;    /* Adapter 0 vector ptr. */
-        ULONG                   adap_typ1;      /* Second adapter type. */
-        ULONG                   adap_vcnt1;     /* Adapter 1 vector count. */
-        _PVOID                  adap_vector1;   /* Adapter 1 vector ptr. */
-        /* More adapter vectors go here... */
-} SYSTEM_PARAMETER_BLOCK, *PSYSTEM_PARAMETER_BLOCK;
-
-#define PROMBLOCK ((PSYSTEM_PARAMETER_BLOCK) (int)0xA0001000)
-#define ROMVECTOR ((struct linux_romvec *) (long)(PROMBLOCK)->romvec)
-
-/* Cache layout parameter block. */
-union linux_cache_key {
-        struct param {
-#ifdef __MIPSEL__
-                unsigned short size;
-                unsigned char lsize;
-                unsigned char bsize;
-#else /* !(__MIPSEL__) */
-                unsigned char bsize;
-                unsigned char lsize;
-                unsigned short size;
-#endif
-        } info;
-        unsigned long allinfo;
-};
-
-/* Configuration data. */
-struct linux_cdata {
-        char *name;
-        int mlen;
-        enum linux_devtypes type;
-};
-
-/* Common SGI ARCS firmware file descriptors. */
-#define SGIPROM_STDIN     0
-#define SGIPROM_STDOUT    1
-
-/* Common SGI ARCS firmware file types. */
-#define SGIPROM_ROFILE    0x01  /* read-only file */
-#define SGIPROM_HFILE     0x02  /* hidden file */
-#define SGIPROM_SFILE     0x04  /* System file */
-#define SGIPROM_AFILE     0x08  /* Archive file */
-#define SGIPROM_DFILE     0x10  /* Directory file */
-#define SGIPROM_DELFILE   0x20  /* Deleted file */
-
-/* SGI ARCS boot record information. */
-struct sgi_partition {
-        unsigned char flag;
-#define SGIPART_UNUSED 0x00
-#define SGIPART_ACTIVE 0x80
-
-        unsigned char shead, ssect, scyl; /* unused */
-        unsigned char systype; /* OS type, Irix or NT */
-        unsigned char ehead, esect, ecyl; /* unused */
-        unsigned char rsect0, rsect1, rsect2, rsect3;
-        unsigned char tsect0, tsect1, tsect2, tsect3;
-};
-
-#define SGIBBLOCK_MAGIC   0xaa55
-#define SGIBBLOCK_MAXPART 0x0004
-
-struct sgi_bootblock {
-        unsigned char _unused[446];
-        struct sgi_partition partitions[SGIBBLOCK_MAXPART];
-        unsigned short magic;
-};
-
-/* BIOS parameter block. */
-struct sgi_bparm_block {
-        unsigned short bytes_sect;    /* bytes per sector */
-        unsigned char  sect_clust;    /* sectors per cluster */
-        unsigned short sect_resv;     /* reserved sectors */
-        unsigned char  nfats;         /* # of allocation tables */
-        unsigned short nroot_dirents; /* # of root directory entries */
-        unsigned short sect_volume;   /* sectors in volume */
-        unsigned char  media_type;    /* media descriptor */
-        unsigned short sect_fat;      /* sectors per allocation table */
-        unsigned short sect_track;    /* sectors per track */
-        unsigned short nheads;        /* # of heads */
-        unsigned short nhsects;       /* # of hidden sectors */
-};
-
-struct sgi_bsector {
-        unsigned char   jmpinfo[3];
-        unsigned char   manuf_name[8];
-        struct sgi_bparm_block info;
-};
-
-/* Debugging block used with SGI symmon symbolic debugger. */
-#define SMB_DEBUG_MAGIC   0xfeeddead
-struct linux_smonblock {
-        unsigned long   magic;
-        void            (*handler)(void);  /* Breakpoint routine. */
-        unsigned long   dtable_base;       /* Base addr of dbg table. */
-        int             (*printf)(const char *fmt, ...);
-        unsigned long   btable_base;       /* Breakpoint table. */
-        unsigned long   mpflushreqs;       /* SMP cache flush request list. */
-        unsigned long   ntab;              /* Name table. */
-        unsigned long   stab;              /* Symbol table. */
-        int             smax;              /* Max # of symbols. */
-};
-
-/*
- * Macros for calling a 32-bit ARC implementation from 64-bit code
- */
-
-#if defined(CONFIG_64BIT) && defined(CONFIG_ARC32)
-
-#define __arc_clobbers                                                  \
-        "$2", "$3" /* ... */, "$8", "$9", "$10", "$11",                         \
-        "$12", "$13", "$14", "$15", "$16", "$24", "$25", "$31"
-
-#define ARC_CALL0(dest)                                                 \
-({      long __res;                                                     \
-        long __vec = (long) romvec->dest;                               \
-        __asm__ __volatile__(                                           \
-        "dsubu\t$29, 32\n\t"                                            \
-        "jalr\t%1\n\t"                                                  \
-        "daddu\t$29, 32\n\t"                                            \
-        "move\t%0, $2"                                                  \
-        : "=r" (__res), "=r" (__vec)                                    \
-        : "1" (__vec)                                                   \
-        : __arc_clobbers, "$4", "$5", "$6", "$7");                      \
-        (unsigned long) __res;                                          \
-})
-
-#define ARC_CALL1(dest, a1)                                             \
-({      long __res;                                                     \
-        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
-        long __vec = (long) romvec->dest;                               \
-        __asm__ __volatile__(                                           \
-        "dsubu\t$29, 32\n\t"                                            \
-        "jalr\t%1\n\t"                                                  \
-        "daddu\t$29, 32\n\t"                                            \
-        "move\t%0, $2"                                                  \
-        : "=r" (__res), "=r" (__vec)                                    \
-        : "1" (__vec), "r" (__a1)                                       \
-        : __arc_clobbers, "$5", "$6", "$7");                            \
-        (unsigned long) __res;                                          \
-})
-
-#define ARC_CALL2(dest, a1, a2)                                         \
-({      long __res;                                                     \
-        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
-        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
-        long __vec = (long) romvec->dest;                               \
-        __asm__ __volatile__(                                           \
-        "dsubu\t$29, 32\n\t"                                            \
-        "jalr\t%1\n\t"                                                  \
-        "daddu\t$29, 32\n\t"                                            \
-        "move\t%0, $2"                                                  \
-        : "=r" (__res), "=r" (__vec)                                    \
-        : "1" (__vec), "r" (__a1), "r" (__a2)                           \
-        : __arc_clobbers, "$6", "$7");                                  \
-        __res;                                                          \
-})
-
-#define ARC_CALL3(dest, a1, a2, a3)                                     \
-({      long __res;                                                     \
-        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
-        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
-        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
-        long __vec = (long) romvec->dest;                               \
-        __asm__ __volatile__(                                           \
-        "dsubu\t$29, 32\n\t"                                            \
-        "jalr\t%1\n\t"                                                  \
-        "daddu\t$29, 32\n\t"                                            \
-        "move\t%0, $2"                                                  \
-        : "=r" (__res), "=r" (__vec)                                    \
-        : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3)               \
-        : __arc_clobbers, "$7");                                        \
-        __res;                                                          \
-})
-
-#define ARC_CALL4(dest, a1, a2, a3, a4)                                 \
-({      long __res;                                                     \
-        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
-        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
-        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
-        register signed int __a4 __asm__("$7") = (int) (long) (a4);     \
-        long __vec = (long) romvec->dest;                               \
-        __asm__ __volatile__(                                           \
-        "dsubu\t$29, 32\n\t"                                            \
-        "jalr\t%1\n\t"                                                  \
-        "daddu\t$29, 32\n\t"                                            \
-        "move\t%0, $2"                                                  \
-        : "=r" (__res), "=r" (__vec)                                    \
-        : "1" (__vec), "r" (__a1), "r" (__a2), "r" (__a3),              \
-          "r" (__a4)                                                    \
-        : __arc_clobbers);                                              \
-        __res;                                                          \
-})
-
-#define ARC_CALL5(dest, a1, a2, a3, a4, a5)                                     \
-({      long __res;                                                     \
-        register signed int __a1 __asm__("$4") = (int) (long) (a1);     \
-        register signed int __a2 __asm__("$5") = (int) (long) (a2);     \
-        register signed int __a3 __asm__("$6") = (int) (long) (a3);     \
-        register signed int __a4 __asm__("$7") = (int) (long) (a4);     \
-        register signed int __a5 = (int) (long) (a5);                   \
-        long __vec = (long) romvec->dest;                               \
-        __asm__ __volatile__(                                           \
-        "dsubu\t$29, 32\n\t"                                            \
-        "sw\t%7, 16($29)\n\t"                                           \
-        "jalr\t%1\n\t"                                                  \
-        "daddu\t$29, 32\n\t"                                            \
-        "move\t%0, $2"                                                  \
-        : "=r" (__res), "=r" (__vec)                                    \
-        : "1" (__vec),                                                  \
-          "r" (__a1), "r" (__a2), "r" (__a3), "r" (__a4),               \
-          "r" (__a5)                                                    \
-        : __arc_clobbers);                                              \
-        __res;                                                          \
-})
-
-#endif /* defined(CONFIG_64BIT) && defined(CONFIG_ARC32) */
-
-#if (defined(CONFIG_32BIT) && defined(CONFIG_ARC32)) ||         \
-    (defined(CONFIG_64BIT) && defined(CONFIG_ARC64))
-
-#define ARC_CALL0(dest)                                                 \
-({      long __res;                                                     \
-        long (*__vec)(void) = (void *) romvec->dest;                    \
-                                                                        \
-        __res = __vec();                                                \
-        __res;                                                          \
-})
-
-#define ARC_CALL1(dest, a1)                                             \
-({      long __res;                                                     \
-        long __a1 = (long) (a1);                                        \
-        long (*__vec)(long) = (void *) romvec->dest;                    \
-                                                                        \
-        __res = __vec(__a1);                                            \
-        __res;                                                          \
-})
-
-#define ARC_CALL2(dest, a1, a2)                                         \
-({      long __res;                                                     \
-        long __a1 = (long) (a1);                                        \
-        long __a2 = (long) (a2);                                        \
-        long (*__vec)(long, long) = (void *) romvec->dest;              \
-                                                                        \
-        __res = __vec(__a1, __a2);                                      \
-        __res;                                                          \
-})
-
-#define ARC_CALL3(dest, a1, a2, a3)                                     \
-({      long __res;                                                     \
-        long __a1 = (long) (a1);                                        \
-        long __a2 = (long) (a2);                                        \
-        long __a3 = (long) (a3);                                        \
-        long (*__vec)(long, long, long) = (void *) romvec->dest;        \
-                                                                        \
-        __res = __vec(__a1, __a2, __a3);                                \
-        __res;                                                          \
-})
-
-#define ARC_CALL4(dest, a1, a2, a3, a4)                                 \
-({      long __res;                                                     \
-        long __a1 = (long) (a1);                                        \
-        long __a2 = (long) (a2);                                        \
-        long __a3 = (long) (a3);                                        \
-        long __a4 = (long) (a4);                                        \
-        long (*__vec)(long, long, long, long) = (void *) romvec->dest;  \
-                                                                        \
-        __res = __vec(__a1, __a2, __a3, __a4);                          \
-        __res;                                                          \
-})
-
-#define ARC_CALL5(dest, a1, a2, a3, a4, a5)                             \
-({      long __res;                                                     \
-        long __a1 = (long) (a1);                                        \
-        long __a2 = (long) (a2);                                        \
-        long __a3 = (long) (a3);                                        \
-        long __a4 = (long) (a4);                                        \
-        long __a5 = (long) (a5);                                        \
-        long (*__vec)(long, long, long, long, long);                    \
-        __vec = (void *) romvec->dest;                                  \
-                                                                        \
-        __res = __vec(__a1, __a2, __a3, __a4, __a5);                    \
-        __res;                                                          \
-})
-#endif /* both kernel and ARC either 32-bit or 64-bit */
-
-#endif /* _ASM_SGIARCS_H */
diff --git a/include/asm-mips/sgidefs.h b/include/asm-mips/sgidefs.h
deleted file mode 100644
index 876442fcfb32..000000000000
--- a/include/asm-mips/sgidefs.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1999, 2001 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef __ASM_SGIDEFS_H
-#define __ASM_SGIDEFS_H
-
-/*
- * Using a Linux compiler for building Linux seems logic but not to
- * everybody.
- */
-#ifndef __linux__
-#error Use a Linux compiler or give up.
-#endif
-
-/*
- * Definitions for the ISA levels
- *
- * With the introduction of MIPS32 / MIPS64 instruction sets definitions
- * MIPS ISAs are no longer subsets of each other.  Therefore comparisons
- * on these symbols except with == may result in unexpected results and
- * are forbidden!
- */
-#define _MIPS_ISA_MIPS1         1
-#define _MIPS_ISA_MIPS2         2
-#define _MIPS_ISA_MIPS3         3
-#define _MIPS_ISA_MIPS4         4
-#define _MIPS_ISA_MIPS5         5
-#define _MIPS_ISA_MIPS32        6
-#define _MIPS_ISA_MIPS64        7
-
-/*
- * Subprogram calling convention
- */
-#define _MIPS_SIM_ABI32         1
-#define _MIPS_SIM_NABI32        2
-#define _MIPS_SIM_ABI64         3
-
-#endif /* __ASM_SGIDEFS_H */
diff --git a/include/asm-mips/shmbuf.h b/include/asm-mips/shmbuf.h
deleted file mode 100644
index f994438277bf..000000000000
--- a/include/asm-mips/shmbuf.h
+++ /dev/null
@@ -1,38 +0,0 @@
-#ifndef _ASM_SHMBUF_H
-#define _ASM_SHMBUF_H
-
-/*
- * The shmid64_ds structure for the MIPS architecture.
- * Note extra padding because this structure is passed back and forth
- * between kernel and user space.
- *
- * Pad space is left for:
- * - 2 miscellaneous 32-bit rsp. 64-bit values
- */
-
-struct shmid64_ds {
-        struct ipc64_perm       shm_perm;       /* operation perms */
-        size_t                  shm_segsz;      /* size of segment (bytes) */
-        __kernel_time_t         shm_atime;      /* last attach time */
-        __kernel_time_t         shm_dtime;      /* last detach time */
-        __kernel_time_t         shm_ctime;      /* last change time */
-        __kernel_pid_t          shm_cpid;       /* pid of creator */
-        __kernel_pid_t          shm_lpid;       /* pid of last operator */
-        unsigned long           shm_nattch;     /* no. of current attaches */
-        unsigned long           __unused1;
-        unsigned long           __unused2;
-};
-
-struct shminfo64 {
-        unsigned long   shmmax;
-        unsigned long   shmmin;
-        unsigned long   shmmni;
-        unsigned long   shmseg;
-        unsigned long   shmall;
-        unsigned long   __unused1;
-        unsigned long   __unused2;
-        unsigned long   __unused3;
-        unsigned long   __unused4;
-};
-
-#endif /* _ASM_SHMBUF_H */
diff --git a/include/asm-mips/shmparam.h b/include/asm-mips/shmparam.h
deleted file mode 100644
index 09290720751c..000000000000
--- a/include/asm-mips/shmparam.h
+++ /dev/null
@@ -1,13 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef _ASM_SHMPARAM_H
-#define _ASM_SHMPARAM_H
-
-#define __ARCH_FORCE_SHMLBA     1
-
-#define SHMLBA 0x40000                  /* attach addr a multiple of this */
-
-#endif /* _ASM_SHMPARAM_H */
diff --git a/include/asm-mips/sibyte/bcm1480_int.h b/include/asm-mips/sibyte/bcm1480_int.h
deleted file mode 100644
index 6109557c14e9..000000000000
--- a/include/asm-mips/sibyte/bcm1480_int.h
+++ /dev/null
@@ -1,312 +0,0 @@
-/*  *********************************************************************
-    *  BCM1280/BCM1480 Board Support Package
-    *
-    *  Interrupt Mapper definitions             File: bcm1480_int.h
-    *
-    *  This module contains constants for manipulating the
-    *  BCM1255/BCM1280/BCM1455/BCM1480's interrupt mapper and
-    *  definitions for the interrupt sources.
-    *
-    *  BCM1480 specification level: 1X55_1X80-UM100-D4 (11/24/03)
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _BCM1480_INT_H
-#define _BCM1480_INT_H
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  Interrupt Mapper Constants
-    ********************************************************************* */
-
-/*
- * The interrupt mapper deals with 128-bit logical registers that are
- * implemented as pairs of 64-bit registers, with the "low" 64 bits in
- * a register that has an address 0x1000 higher(!) than the
- * corresponding "high" register.
- *
- * For appropriate registers, bit 0 of the "high" register is a
- * cascade bit that summarizes (as a bit-OR) the 64 bits of the "low"
- * register.
- */
-
-/*
- * This entire file uses _BCM1480_ in all the symbols because it is
- * entirely BCM1480 specific.
- */
-
-/*
- * Interrupt sources (Table 22)
- */
-
-#define K_BCM1480_INT_SOURCES               128
-
-#define _BCM1480_INT_HIGH(k)   (k)
-#define _BCM1480_INT_LOW(k)    ((k)+64)
-
-#define K_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_HIGH(1)
-#define K_BCM1480_INT_GPIO_0                _BCM1480_INT_HIGH(4)
-#define K_BCM1480_INT_GPIO_1                _BCM1480_INT_HIGH(5)
-#define K_BCM1480_INT_GPIO_2                _BCM1480_INT_HIGH(6)
-#define K_BCM1480_INT_GPIO_3                _BCM1480_INT_HIGH(7)
-#define K_BCM1480_INT_PCI_INTA              _BCM1480_INT_HIGH(8)
-#define K_BCM1480_INT_PCI_INTB              _BCM1480_INT_HIGH(9)
-#define K_BCM1480_INT_PCI_INTC              _BCM1480_INT_HIGH(10)
-#define K_BCM1480_INT_PCI_INTD              _BCM1480_INT_HIGH(11)
-#define K_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_HIGH(12)
-#define K_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_HIGH(13)
-#define K_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_HIGH(14)
-#define K_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_HIGH(15)
-#define K_BCM1480_INT_TIMER_0               _BCM1480_INT_HIGH(20)
-#define K_BCM1480_INT_TIMER_1               _BCM1480_INT_HIGH(21)
-#define K_BCM1480_INT_TIMER_2               _BCM1480_INT_HIGH(22)
-#define K_BCM1480_INT_TIMER_3               _BCM1480_INT_HIGH(23)
-#define K_BCM1480_INT_DM_CH_0               _BCM1480_INT_HIGH(28)
-#define K_BCM1480_INT_DM_CH_1               _BCM1480_INT_HIGH(29)
-#define K_BCM1480_INT_DM_CH_2               _BCM1480_INT_HIGH(30)
-#define K_BCM1480_INT_DM_CH_3               _BCM1480_INT_HIGH(31)
-#define K_BCM1480_INT_MAC_0                 _BCM1480_INT_HIGH(36)
-#define K_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_HIGH(37)
-#define K_BCM1480_INT_MAC_1                 _BCM1480_INT_HIGH(38)
-#define K_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_HIGH(39)
-#define K_BCM1480_INT_MAC_2                 _BCM1480_INT_HIGH(40)
-#define K_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_HIGH(41)
-#define K_BCM1480_INT_MAC_3                 _BCM1480_INT_HIGH(42)
-#define K_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_HIGH(43)
-#define K_BCM1480_INT_PMI_LOW               _BCM1480_INT_HIGH(52)
-#define K_BCM1480_INT_PMI_HIGH              _BCM1480_INT_HIGH(53)
-#define K_BCM1480_INT_PMO_LOW               _BCM1480_INT_HIGH(54)
-#define K_BCM1480_INT_PMO_HIGH              _BCM1480_INT_HIGH(55)
-#define K_BCM1480_INT_MBOX_0_0              _BCM1480_INT_HIGH(56)
-#define K_BCM1480_INT_MBOX_0_1              _BCM1480_INT_HIGH(57)
-#define K_BCM1480_INT_MBOX_0_2              _BCM1480_INT_HIGH(58)
-#define K_BCM1480_INT_MBOX_0_3              _BCM1480_INT_HIGH(59)
-#define K_BCM1480_INT_MBOX_1_0              _BCM1480_INT_HIGH(60)
-#define K_BCM1480_INT_MBOX_1_1              _BCM1480_INT_HIGH(61)
-#define K_BCM1480_INT_MBOX_1_2              _BCM1480_INT_HIGH(62)
-#define K_BCM1480_INT_MBOX_1_3              _BCM1480_INT_HIGH(63)
-
-#define K_BCM1480_INT_BAD_ECC               _BCM1480_INT_LOW(1)
-#define K_BCM1480_INT_COR_ECC               _BCM1480_INT_LOW(2)
-#define K_BCM1480_INT_IO_BUS                _BCM1480_INT_LOW(3)
-#define K_BCM1480_INT_PERF_CNT              _BCM1480_INT_LOW(4)
-#define K_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_LOW(5)
-#define K_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_LOW(6)
-#define K_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_LOW(7)
-#define K_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_LOW(8)
-#define K_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_LOW(9)
-#define K_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_LOW(10)
-#define K_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_LOW(11)
-#define K_BCM1480_INT_PCI_ERROR             _BCM1480_INT_LOW(16)
-#define K_BCM1480_INT_PCI_RESET             _BCM1480_INT_LOW(17)
-#define K_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_LOW(18)
-#define K_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_LOW(19)
-#define K_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_LOW(20)
-#define K_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_LOW(21)
-#define K_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_LOW(22)
-#define K_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_LOW(23)
-#define K_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_LOW(24)
-#define K_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_LOW(25)
-#define K_BCM1480_INT_LDT_SMI               _BCM1480_INT_LOW(32)
-#define K_BCM1480_INT_LDT_NMI               _BCM1480_INT_LOW(33)
-#define K_BCM1480_INT_LDT_INIT              _BCM1480_INT_LOW(34)
-#define K_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_LOW(35)
-#define K_BCM1480_INT_LDT_EXT               _BCM1480_INT_LOW(36)
-#define K_BCM1480_INT_SMB_0                 _BCM1480_INT_LOW(40)
-#define K_BCM1480_INT_SMB_1                 _BCM1480_INT_LOW(41)
-#define K_BCM1480_INT_PCMCIA                _BCM1480_INT_LOW(42)
-#define K_BCM1480_INT_UART_0                _BCM1480_INT_LOW(44)
-#define K_BCM1480_INT_UART_1                _BCM1480_INT_LOW(45)
-#define K_BCM1480_INT_UART_2                _BCM1480_INT_LOW(46)
-#define K_BCM1480_INT_UART_3                _BCM1480_INT_LOW(47)
-#define K_BCM1480_INT_GPIO_4                _BCM1480_INT_LOW(52)
-#define K_BCM1480_INT_GPIO_5                _BCM1480_INT_LOW(53)
-#define K_BCM1480_INT_GPIO_6                _BCM1480_INT_LOW(54)
-#define K_BCM1480_INT_GPIO_7                _BCM1480_INT_LOW(55)
-#define K_BCM1480_INT_GPIO_8                _BCM1480_INT_LOW(56)
-#define K_BCM1480_INT_GPIO_9                _BCM1480_INT_LOW(57)
-#define K_BCM1480_INT_GPIO_10               _BCM1480_INT_LOW(58)
-#define K_BCM1480_INT_GPIO_11               _BCM1480_INT_LOW(59)
-#define K_BCM1480_INT_GPIO_12               _BCM1480_INT_LOW(60)
-#define K_BCM1480_INT_GPIO_13               _BCM1480_INT_LOW(61)
-#define K_BCM1480_INT_GPIO_14               _BCM1480_INT_LOW(62)
-#define K_BCM1480_INT_GPIO_15               _BCM1480_INT_LOW(63)
-
-/*
- * Mask values for each interrupt
- */
-
-#define _BCM1480_INT_MASK(w, n)              _SB_MAKEMASK(w, ((n) & 0x3F))
-#define _BCM1480_INT_MASK1(n)               _SB_MAKEMASK1(((n) & 0x3F))
-#define _BCM1480_INT_OFFSET(n)              (((n) & 0x40) << 6)
-
-#define M_BCM1480_INT_CASCADE               _BCM1480_INT_MASK1(_BCM1480_INT_HIGH(0))
-
-#define M_BCM1480_INT_ADDR_TRAP             _BCM1480_INT_MASK1(K_BCM1480_INT_ADDR_TRAP)
-#define M_BCM1480_INT_GPIO_0                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_0)
-#define M_BCM1480_INT_GPIO_1                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_1)
-#define M_BCM1480_INT_GPIO_2                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_2)
-#define M_BCM1480_INT_GPIO_3                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_3)
-#define M_BCM1480_INT_PCI_INTA              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTA)
-#define M_BCM1480_INT_PCI_INTB              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTB)
-#define M_BCM1480_INT_PCI_INTC              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTC)
-#define M_BCM1480_INT_PCI_INTD              _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_INTD)
-#define M_BCM1480_INT_CYCLE_CP0             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP0)
-#define M_BCM1480_INT_CYCLE_CP1             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP1)
-#define M_BCM1480_INT_CYCLE_CP2             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP2)
-#define M_BCM1480_INT_CYCLE_CP3             _BCM1480_INT_MASK1(K_BCM1480_INT_CYCLE_CP3)
-#define M_BCM1480_INT_TIMER_0               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_0)
-#define M_BCM1480_INT_TIMER_1               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_1)
-#define M_BCM1480_INT_TIMER_2               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_2)
-#define M_BCM1480_INT_TIMER_3               _BCM1480_INT_MASK1(K_BCM1480_INT_TIMER_3)
-#define M_BCM1480_INT_DM_CH_0               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_0)
-#define M_BCM1480_INT_DM_CH_1               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_1)
-#define M_BCM1480_INT_DM_CH_2               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_2)
-#define M_BCM1480_INT_DM_CH_3               _BCM1480_INT_MASK1(K_BCM1480_INT_DM_CH_3)
-#define M_BCM1480_INT_MAC_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0)
-#define M_BCM1480_INT_MAC_0_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_0_CH1)
-#define M_BCM1480_INT_MAC_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1)
-#define M_BCM1480_INT_MAC_1_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_1_CH1)
-#define M_BCM1480_INT_MAC_2                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2)
-#define M_BCM1480_INT_MAC_2_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_2_CH1)
-#define M_BCM1480_INT_MAC_3                 _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3)
-#define M_BCM1480_INT_MAC_3_CH1             _BCM1480_INT_MASK1(K_BCM1480_INT_MAC_3_CH1)
-#define M_BCM1480_INT_PMI_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_LOW)
-#define M_BCM1480_INT_PMI_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMI_HIGH)
-#define M_BCM1480_INT_PMO_LOW               _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_LOW)
-#define M_BCM1480_INT_PMO_HIGH              _BCM1480_INT_MASK1(K_BCM1480_INT_PMO_HIGH)
-#define M_BCM1480_INT_MBOX_ALL              _BCM1480_INT_MASK(8, K_BCM1480_INT_MBOX_0_0)
-#define M_BCM1480_INT_MBOX_0_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_0)
-#define M_BCM1480_INT_MBOX_0_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_1)
-#define M_BCM1480_INT_MBOX_0_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_2)
-#define M_BCM1480_INT_MBOX_0_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_0_3)
-#define M_BCM1480_INT_MBOX_1_0              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_0)
-#define M_BCM1480_INT_MBOX_1_1              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_1)
-#define M_BCM1480_INT_MBOX_1_2              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_2)
-#define M_BCM1480_INT_MBOX_1_3              _BCM1480_INT_MASK1(K_BCM1480_INT_MBOX_1_3)
-#define M_BCM1480_INT_BAD_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_BAD_ECC)
-#define M_BCM1480_INT_COR_ECC               _BCM1480_INT_MASK1(K_BCM1480_INT_COR_ECC)
-#define M_BCM1480_INT_IO_BUS                _BCM1480_INT_MASK1(K_BCM1480_INT_IO_BUS)
-#define M_BCM1480_INT_PERF_CNT              _BCM1480_INT_MASK1(K_BCM1480_INT_PERF_CNT)
-#define M_BCM1480_INT_SW_PERF_CNT           _BCM1480_INT_MASK1(K_BCM1480_INT_SW_PERF_CNT)
-#define M_BCM1480_INT_TRACE_FREEZE          _BCM1480_INT_MASK1(K_BCM1480_INT_TRACE_FREEZE)
-#define M_BCM1480_INT_SW_TRACE_FREEZE       _BCM1480_INT_MASK1(K_BCM1480_INT_SW_TRACE_FREEZE)
-#define M_BCM1480_INT_WATCHDOG_TIMER_0      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_0)
-#define M_BCM1480_INT_WATCHDOG_TIMER_1      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_1)
-#define M_BCM1480_INT_WATCHDOG_TIMER_2      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_2)
-#define M_BCM1480_INT_WATCHDOG_TIMER_3      _BCM1480_INT_MASK1(K_BCM1480_INT_WATCHDOG_TIMER_3)
-#define M_BCM1480_INT_PCI_ERROR             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_ERROR)
-#define M_BCM1480_INT_PCI_RESET             _BCM1480_INT_MASK1(K_BCM1480_INT_PCI_RESET)
-#define M_BCM1480_INT_NODE_CONTROLLER       _BCM1480_INT_MASK1(K_BCM1480_INT_NODE_CONTROLLER)
-#define M_BCM1480_INT_HOST_BRIDGE           _BCM1480_INT_MASK1(K_BCM1480_INT_HOST_BRIDGE)
-#define M_BCM1480_INT_PORT_0_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_FATAL)
-#define M_BCM1480_INT_PORT_0_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_0_NONFATAL)
-#define M_BCM1480_INT_PORT_1_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_FATAL)
-#define M_BCM1480_INT_PORT_1_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_1_NONFATAL)
-#define M_BCM1480_INT_PORT_2_FATAL          _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_FATAL)
-#define M_BCM1480_INT_PORT_2_NONFATAL       _BCM1480_INT_MASK1(K_BCM1480_INT_PORT_2_NONFATAL)
-#define M_BCM1480_INT_LDT_SMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_SMI)
-#define M_BCM1480_INT_LDT_NMI               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_NMI)
-#define M_BCM1480_INT_LDT_INIT              _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_INIT)
-#define M_BCM1480_INT_LDT_STARTUP           _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_STARTUP)
-#define M_BCM1480_INT_LDT_EXT               _BCM1480_INT_MASK1(K_BCM1480_INT_LDT_EXT)
-#define M_BCM1480_INT_SMB_0                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_0)
-#define M_BCM1480_INT_SMB_1                 _BCM1480_INT_MASK1(K_BCM1480_INT_SMB_1)
-#define M_BCM1480_INT_PCMCIA                _BCM1480_INT_MASK1(K_BCM1480_INT_PCMCIA)
-#define M_BCM1480_INT_UART_0                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_0)
-#define M_BCM1480_INT_UART_1                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_1)
-#define M_BCM1480_INT_UART_2                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_2)
-#define M_BCM1480_INT_UART_3                _BCM1480_INT_MASK1(K_BCM1480_INT_UART_3)
-#define M_BCM1480_INT_GPIO_4                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_4)
-#define M_BCM1480_INT_GPIO_5                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_5)
-#define M_BCM1480_INT_GPIO_6                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_6)
-#define M_BCM1480_INT_GPIO_7                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_7)
-#define M_BCM1480_INT_GPIO_8                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_8)
-#define M_BCM1480_INT_GPIO_9                _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_9)
-#define M_BCM1480_INT_GPIO_10               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_10)
-#define M_BCM1480_INT_GPIO_11               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_11)
-#define M_BCM1480_INT_GPIO_12               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_12)
-#define M_BCM1480_INT_GPIO_13               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_13)
-#define M_BCM1480_INT_GPIO_14               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_14)
-#define M_BCM1480_INT_GPIO_15               _BCM1480_INT_MASK1(K_BCM1480_INT_GPIO_15)
-
-/*
- * Interrupt mappings (Table 18)
- */
-
-#define K_BCM1480_INT_MAP_I0    0               /* interrupt pins on processor */
-#define K_BCM1480_INT_MAP_I1    1
-#define K_BCM1480_INT_MAP_I2    2
-#define K_BCM1480_INT_MAP_I3    3
-#define K_BCM1480_INT_MAP_I4    4
-#define K_BCM1480_INT_MAP_I5    5
-#define K_BCM1480_INT_MAP_NMI   6               /* nonmaskable */
-#define K_BCM1480_INT_MAP_DINT  7               /* debug interrupt */
-
-/*
- * Interrupt LDT Set Register (Table 19)
- */
-
-#define S_BCM1480_INT_HT_INTMSG             0
-#define M_BCM1480_INT_HT_INTMSG             _SB_MAKEMASK(3, S_BCM1480_INT_HT_INTMSG)
-#define V_BCM1480_INT_HT_INTMSG(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTMSG)
-#define G_BCM1480_INT_HT_INTMSG(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_INTMSG, M_BCM1480_INT_HT_INTMSG)
-
-#define K_BCM1480_INT_HT_INTMSG_FIXED       0
-#define K_BCM1480_INT_HT_INTMSG_ARBITRATED  1
-#define K_BCM1480_INT_HT_INTMSG_SMI         2
-#define K_BCM1480_INT_HT_INTMSG_NMI         3
-#define K_BCM1480_INT_HT_INTMSG_INIT        4
-#define K_BCM1480_INT_HT_INTMSG_STARTUP     5
-#define K_BCM1480_INT_HT_INTMSG_EXTINT      6
-#define K_BCM1480_INT_HT_INTMSG_RESERVED    7
-
-#define M_BCM1480_INT_HT_TRIGGERMODE        _SB_MAKEMASK1(3)
-#define V_BCM1480_INT_HT_EDGETRIGGER        0
-#define V_BCM1480_INT_HT_LEVELTRIGGER       M_BCM1480_INT_HT_TRIGGERMODE
-
-#define M_BCM1480_INT_HT_DESTMODE           _SB_MAKEMASK1(4)
-#define V_BCM1480_INT_HT_PHYSICALDEST       0
-#define V_BCM1480_INT_HT_LOGICALDEST        M_BCM1480_INT_HT_DESTMODE
-
-#define S_BCM1480_INT_HT_INTDEST            5
-#define M_BCM1480_INT_HT_INTDEST            _SB_MAKEMASK(8, S_BCM1480_INT_HT_INTDEST)
-#define V_BCM1480_INT_HT_INTDEST(x)         _SB_MAKEVALUE(x, S_BCM1480_INT_HT_INTDEST)
-#define G_BCM1480_INT_HT_INTDEST(x)         _SB_GETVALUE(x, S_BCM1480_INT_HT_INTDEST, M_BCM1480_INT_HT_INTDEST)
-
-#define S_BCM1480_INT_HT_VECTOR             13
-#define M_BCM1480_INT_HT_VECTOR             _SB_MAKEMASK(8, S_BCM1480_INT_HT_VECTOR)
-#define V_BCM1480_INT_HT_VECTOR(x)          _SB_MAKEVALUE(x, S_BCM1480_INT_HT_VECTOR)
-#define G_BCM1480_INT_HT_VECTOR(x)          _SB_GETVALUE(x, S_BCM1480_INT_HT_VECTOR, M_BCM1480_INT_HT_VECTOR)
-
-/*
- * Vector prefix (Table 4-7)
- */
-
-#define M_BCM1480_HTVECT_RAISE_INTLDT_HIGH  0x00
-#define M_BCM1480_HTVECT_RAISE_MBOX_0       0x40
-#define M_BCM1480_HTVECT_RAISE_INTLDT_LO    0x80
-#define M_BCM1480_HTVECT_RAISE_MBOX_1       0xC0
-
-#endif /* _BCM1480_INT_H */
diff --git a/include/asm-mips/sibyte/bcm1480_l2c.h b/include/asm-mips/sibyte/bcm1480_l2c.h
deleted file mode 100644
index fd75817f7ac4..000000000000
--- a/include/asm-mips/sibyte/bcm1480_l2c.h
+++ /dev/null
@@ -1,176 +0,0 @@
-/*  *********************************************************************
-    *  BCM1280/BCM1480 Board Support Package
-    *
-    *  L2 Cache constants and macros            File: bcm1480_l2c.h
-    *
-    *  This module contains constants useful for manipulating the
-    *  level 2 cache.
-    *
-    *  BCM1400 specification level:  1280-UM100-D2 (11/14/03)
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _BCM1480_L2C_H
-#define _BCM1480_L2C_H
-
-#include "sb1250_defs.h"
-
-/*
- * Format of level 2 cache management address (Table 55)
- */
-
-#define S_BCM1480_L2C_MGMT_INDEX            5
-#define M_BCM1480_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_BCM1480_L2C_MGMT_INDEX)
-#define V_BCM1480_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_INDEX)
-#define G_BCM1480_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_INDEX, M_BCM1480_L2C_MGMT_INDEX)
-
-#define S_BCM1480_L2C_MGMT_WAY              17
-#define M_BCM1480_L2C_MGMT_WAY              _SB_MAKEMASK(3, S_BCM1480_L2C_MGMT_WAY)
-#define V_BCM1480_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_WAY)
-#define G_BCM1480_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_WAY, M_BCM1480_L2C_MGMT_WAY)
-
-#define M_BCM1480_L2C_MGMT_DIRTY            _SB_MAKEMASK1(20)
-#define M_BCM1480_L2C_MGMT_VALID            _SB_MAKEMASK1(21)
-
-#define S_BCM1480_L2C_MGMT_ECC_DIAG         22
-#define M_BCM1480_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_BCM1480_L2C_MGMT_ECC_DIAG)
-#define V_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG)
-#define G_BCM1480_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_BCM1480_L2C_MGMT_ECC_DIAG, M_BCM1480_L2C_MGMT_ECC_DIAG)
-
-#define A_BCM1480_L2C_MGMT_TAG_BASE         0x00D0000000
-
-#define BCM1480_L2C_ENTRIES_PER_WAY         4096
-#define BCM1480_L2C_NUM_WAYS                8
-
-
-/*
- * Level 2 Cache Tag register (Table 59)
- */
-
-#define S_BCM1480_L2C_TAG_MBZ               0
-#define M_BCM1480_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_BCM1480_L2C_TAG_MBZ)
-
-#define S_BCM1480_L2C_TAG_INDEX             5
-#define M_BCM1480_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_BCM1480_L2C_TAG_INDEX)
-#define V_BCM1480_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_INDEX)
-#define G_BCM1480_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_BCM1480_L2C_TAG_INDEX, M_BCM1480_L2C_TAG_INDEX)
-
-/* Note that index bit 16 is also tag bit 40 */
-#define S_BCM1480_L2C_TAG_TAG               17
-#define M_BCM1480_L2C_TAG_TAG               _SB_MAKEMASK(23, S_BCM1480_L2C_TAG_TAG)
-#define V_BCM1480_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_TAG)
-#define G_BCM1480_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_TAG, M_BCM1480_L2C_TAG_TAG)
-
-#define S_BCM1480_L2C_TAG_ECC               40
-#define M_BCM1480_L2C_TAG_ECC               _SB_MAKEMASK(6, S_BCM1480_L2C_TAG_ECC)
-#define V_BCM1480_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_ECC)
-#define G_BCM1480_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_ECC, M_BCM1480_L2C_TAG_ECC)
-
-#define S_BCM1480_L2C_TAG_WAY               46
-#define M_BCM1480_L2C_TAG_WAY               _SB_MAKEMASK(3, S_BCM1480_L2C_TAG_WAY)
-#define V_BCM1480_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_BCM1480_L2C_TAG_WAY)
-#define G_BCM1480_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_BCM1480_L2C_TAG_WAY, M_BCM1480_L2C_TAG_WAY)
-
-#define M_BCM1480_L2C_TAG_DIRTY             _SB_MAKEMASK1(49)
-#define M_BCM1480_L2C_TAG_VALID             _SB_MAKEMASK1(50)
-
-#define S_BCM1480_L2C_DATA_ECC              51
-#define M_BCM1480_L2C_DATA_ECC              _SB_MAKEMASK(10, S_BCM1480_L2C_DATA_ECC)
-#define V_BCM1480_L2C_DATA_ECC(x)           _SB_MAKEVALUE(x, S_BCM1480_L2C_DATA_ECC)
-#define G_BCM1480_L2C_DATA_ECC(x)           _SB_GETVALUE(x, S_BCM1480_L2C_DATA_ECC, M_BCM1480_L2C_DATA_ECC)
-
-
-/*
- * L2 Misc0 Value Register (Table 60)
- */
-
-#define S_BCM1480_L2C_MISC0_WAY_REMOTE      0
-#define M_BCM1480_L2C_MISC0_WAY_REMOTE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_REMOTE)
-#define G_BCM1480_L2C_MISC0_WAY_REMOTE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_REMOTE, M_BCM1480_L2C_MISC0_WAY_REMOTE)
-
-#define S_BCM1480_L2C_MISC0_WAY_LOCAL       8
-#define M_BCM1480_L2C_MISC0_WAY_LOCAL       _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_LOCAL)
-#define G_BCM1480_L2C_MISC0_WAY_LOCAL(x)    _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_LOCAL, M_BCM1480_L2C_MISC0_WAY_LOCAL)
-
-#define S_BCM1480_L2C_MISC0_WAY_ENABLE      16
-#define M_BCM1480_L2C_MISC0_WAY_ENABLE      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC0_WAY_ENABLE)
-#define G_BCM1480_L2C_MISC0_WAY_ENABLE(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_WAY_ENABLE, M_BCM1480_L2C_MISC0_WAY_ENABLE)
-
-#define S_BCM1480_L2C_MISC0_CACHE_DISABLE   24
-#define M_BCM1480_L2C_MISC0_CACHE_DISABLE   _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_DISABLE)
-#define G_BCM1480_L2C_MISC0_CACHE_DISABLE(x) _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_DISABLE, M_BCM1480_L2C_MISC0_CACHE_DISABLE)
-
-#define S_BCM1480_L2C_MISC0_CACHE_QUAD      26
-#define M_BCM1480_L2C_MISC0_CACHE_QUAD      _SB_MAKEMASK(2, S_BCM1480_L2C_MISC0_CACHE_QUAD)
-#define G_BCM1480_L2C_MISC0_CACHE_QUAD(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC0_CACHE_QUAD, M_BCM1480_L2C_MISC0_CACHE_QUAD)
-
-#define S_BCM1480_L2C_MISC0_MC_PRIORITY      30
-#define M_BCM1480_L2C_MISC0_MC_PRIORITY      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_MC_PRIORITY)
-
-#define S_BCM1480_L2C_MISC0_ECC_CLEANUP      31
-#define M_BCM1480_L2C_MISC0_ECC_CLEANUP      _SB_MAKEMASK1(S_BCM1480_L2C_MISC0_ECC_CLEANUP)
-
-
-/*
- * L2 Misc1 Value Register (Table 60)
- */
-
-#define S_BCM1480_L2C_MISC1_WAY_AGENT_0      0
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_0      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_0)
-#define G_BCM1480_L2C_MISC1_WAY_AGENT_0(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_0, M_BCM1480_L2C_MISC1_WAY_AGENT_0)
-
-#define S_BCM1480_L2C_MISC1_WAY_AGENT_1      8
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_1      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_1)
-#define G_BCM1480_L2C_MISC1_WAY_AGENT_1(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_1, M_BCM1480_L2C_MISC1_WAY_AGENT_1)
-
-#define S_BCM1480_L2C_MISC1_WAY_AGENT_2      16
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_2      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_2)
-#define G_BCM1480_L2C_MISC1_WAY_AGENT_2(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_2, M_BCM1480_L2C_MISC1_WAY_AGENT_2)
-
-#define S_BCM1480_L2C_MISC1_WAY_AGENT_3      24
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_3      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_3)
-#define G_BCM1480_L2C_MISC1_WAY_AGENT_3(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_3, M_BCM1480_L2C_MISC1_WAY_AGENT_3)
-
-#define S_BCM1480_L2C_MISC1_WAY_AGENT_4      32
-#define M_BCM1480_L2C_MISC1_WAY_AGENT_4      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC1_WAY_AGENT_4)
-#define G_BCM1480_L2C_MISC1_WAY_AGENT_4(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC1_WAY_AGENT_4, M_BCM1480_L2C_MISC1_WAY_AGENT_4)
-
-
-/*
- * L2 Misc2 Value Register (Table 60)
- */
-
-#define S_BCM1480_L2C_MISC2_WAY_AGENT_8      0
-#define M_BCM1480_L2C_MISC2_WAY_AGENT_8      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_8)
-#define G_BCM1480_L2C_MISC2_WAY_AGENT_8(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_8, M_BCM1480_L2C_MISC2_WAY_AGENT_8)
-
-#define S_BCM1480_L2C_MISC2_WAY_AGENT_9      8
-#define M_BCM1480_L2C_MISC2_WAY_AGENT_9      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_9)
-#define G_BCM1480_L2C_MISC2_WAY_AGENT_9(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_9, M_BCM1480_L2C_MISC2_WAY_AGENT_9)
-
-#define S_BCM1480_L2C_MISC2_WAY_AGENT_A      16
-#define M_BCM1480_L2C_MISC2_WAY_AGENT_A      _SB_MAKEMASK(8, S_BCM1480_L2C_MISC2_WAY_AGENT_A)
-#define G_BCM1480_L2C_MISC2_WAY_AGENT_A(x)   _SB_GETVALUE(x, S_BCM1480_L2C_MISC2_WAY_AGENT_A, M_BCM1480_L2C_MISC2_WAY_AGENT_A)
-
-
-#endif /* _BCM1480_L2C_H */
diff --git a/include/asm-mips/sibyte/bcm1480_mc.h b/include/asm-mips/sibyte/bcm1480_mc.h
deleted file mode 100644
index f26a41a82b59..000000000000
--- a/include/asm-mips/sibyte/bcm1480_mc.h
+++ /dev/null
@@ -1,984 +0,0 @@
-/*  *********************************************************************
-    *  BCM1280/BCM1480 Board Support Package
-    *
-    *  Memory Controller constants              File: bcm1480_mc.h
-    *
-    *  This module contains constants and macros useful for
-    *  programming the memory controller.
-    *
-    *  BCM1400 specification level:  1280-UM100-D1 (11/14/03 Review Copy)
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _BCM1480_MC_H
-#define _BCM1480_MC_H
-
-#include "sb1250_defs.h"
-
-/*
- * Memory Channel Configuration Register (Table 81)
- */
-
-#define S_BCM1480_MC_INTLV0                 0
-#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
-#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
-#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
-#define V_BCM1480_MC_INTLV0_DEFAULT         V_BCM1480_MC_INTLV0(0)
-
-#define S_BCM1480_MC_INTLV1                 8
-#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
-#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
-#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
-#define V_BCM1480_MC_INTLV1_DEFAULT         V_BCM1480_MC_INTLV1(0)
-
-#define S_BCM1480_MC_INTLV2                 16
-#define M_BCM1480_MC_INTLV2                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV2)
-#define V_BCM1480_MC_INTLV2(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV2)
-#define G_BCM1480_MC_INTLV2(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV2, M_BCM1480_MC_INTLV2)
-#define V_BCM1480_MC_INTLV2_DEFAULT         V_BCM1480_MC_INTLV2(0)
-
-#define S_BCM1480_MC_CS_MODE                32
-#define M_BCM1480_MC_CS_MODE                _SB_MAKEMASK(8, S_BCM1480_MC_CS_MODE)
-#define V_BCM1480_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS_MODE)
-#define G_BCM1480_MC_CS_MODE(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS_MODE, M_BCM1480_MC_CS_MODE)
-#define V_BCM1480_MC_CS_MODE_DEFAULT        V_BCM1480_MC_CS_MODE(0)
-
-#define V_BCM1480_MC_CONFIG_DEFAULT         (V_BCM1480_MC_INTLV0_DEFAULT  | \
-                                     V_BCM1480_MC_INTLV1_DEFAULT  | \
-                                     V_BCM1480_MC_INTLV2_DEFAULT  | \
-                                     V_BCM1480_MC_CS_MODE_DEFAULT)
-
-#define K_BCM1480_MC_CS01_MODE              0x03
-#define K_BCM1480_MC_CS02_MODE              0x05
-#define K_BCM1480_MC_CS0123_MODE            0x0F
-#define K_BCM1480_MC_CS0246_MODE            0x55
-#define K_BCM1480_MC_CS0145_MODE            0x33
-#define K_BCM1480_MC_CS0167_MODE            0xC3
-#define K_BCM1480_MC_CSFULL_MODE            0xFF
-
-/*
- * Chip Select Start Address Register (Table 82)
- */
-
-#define S_BCM1480_MC_CS0_START              0
-#define M_BCM1480_MC_CS0_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS0_START)
-#define V_BCM1480_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_START)
-#define G_BCM1480_MC_CS0_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS0_START, M_BCM1480_MC_CS0_START)
-
-#define S_BCM1480_MC_CS1_START              16
-#define M_BCM1480_MC_CS1_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS1_START)
-#define V_BCM1480_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_START)
-#define G_BCM1480_MC_CS1_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS1_START, M_BCM1480_MC_CS1_START)
-
-#define S_BCM1480_MC_CS2_START              32
-#define M_BCM1480_MC_CS2_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS2_START)
-#define V_BCM1480_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_START)
-#define G_BCM1480_MC_CS2_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS2_START, M_BCM1480_MC_CS2_START)
-
-#define S_BCM1480_MC_CS3_START              48
-#define M_BCM1480_MC_CS3_START              _SB_MAKEMASK(12, S_BCM1480_MC_CS3_START)
-#define V_BCM1480_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_START)
-#define G_BCM1480_MC_CS3_START(x)           _SB_GETVALUE(x, S_BCM1480_MC_CS3_START, M_BCM1480_MC_CS3_START)
-
-/*
- * Chip Select End Address Register (Table 83)
- */
-
-#define S_BCM1480_MC_CS0_END                0
-#define M_BCM1480_MC_CS0_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS0_END)
-#define V_BCM1480_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS0_END)
-#define G_BCM1480_MC_CS0_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS0_END, M_BCM1480_MC_CS0_END)
-
-#define S_BCM1480_MC_CS1_END                16
-#define M_BCM1480_MC_CS1_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS1_END)
-#define V_BCM1480_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS1_END)
-#define G_BCM1480_MC_CS1_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS1_END, M_BCM1480_MC_CS1_END)
-
-#define S_BCM1480_MC_CS2_END                32
-#define M_BCM1480_MC_CS2_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS2_END)
-#define V_BCM1480_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS2_END)
-#define G_BCM1480_MC_CS2_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS2_END, M_BCM1480_MC_CS2_END)
-
-#define S_BCM1480_MC_CS3_END                48
-#define M_BCM1480_MC_CS3_END                _SB_MAKEMASK(12, S_BCM1480_MC_CS3_END)
-#define V_BCM1480_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_CS3_END)
-#define G_BCM1480_MC_CS3_END(x)             _SB_GETVALUE(x, S_BCM1480_MC_CS3_END, M_BCM1480_MC_CS3_END)
-
-/*
- * Row Address Bit Select Register 0 (Table 84)
- */
-
-#define S_BCM1480_MC_ROW00                  0
-#define M_BCM1480_MC_ROW00                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW00)
-#define V_BCM1480_MC_ROW00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW00)
-#define G_BCM1480_MC_ROW00(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW00, M_BCM1480_MC_ROW00)
-
-#define S_BCM1480_MC_ROW01                  8
-#define M_BCM1480_MC_ROW01                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW01)
-#define V_BCM1480_MC_ROW01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW01)
-#define G_BCM1480_MC_ROW01(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW01, M_BCM1480_MC_ROW01)
-
-#define S_BCM1480_MC_ROW02                  16
-#define M_BCM1480_MC_ROW02                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW02)
-#define V_BCM1480_MC_ROW02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW02)
-#define G_BCM1480_MC_ROW02(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW02, M_BCM1480_MC_ROW02)
-
-#define S_BCM1480_MC_ROW03                  24
-#define M_BCM1480_MC_ROW03                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW03)
-#define V_BCM1480_MC_ROW03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW03)
-#define G_BCM1480_MC_ROW03(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW03, M_BCM1480_MC_ROW03)
-
-#define S_BCM1480_MC_ROW04                  32
-#define M_BCM1480_MC_ROW04                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW04)
-#define V_BCM1480_MC_ROW04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW04)
-#define G_BCM1480_MC_ROW04(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW04, M_BCM1480_MC_ROW04)
-
-#define S_BCM1480_MC_ROW05                  40
-#define M_BCM1480_MC_ROW05                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW05)
-#define V_BCM1480_MC_ROW05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW05)
-#define G_BCM1480_MC_ROW05(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW05, M_BCM1480_MC_ROW05)
-
-#define S_BCM1480_MC_ROW06                  48
-#define M_BCM1480_MC_ROW06                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW06)
-#define V_BCM1480_MC_ROW06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW06)
-#define G_BCM1480_MC_ROW06(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW06, M_BCM1480_MC_ROW06)
-
-#define S_BCM1480_MC_ROW07                  56
-#define M_BCM1480_MC_ROW07                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW07)
-#define V_BCM1480_MC_ROW07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW07)
-#define G_BCM1480_MC_ROW07(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW07, M_BCM1480_MC_ROW07)
-
-/*
- * Row Address Bit Select Register 1 (Table 85)
- */
-
-#define S_BCM1480_MC_ROW08                  0
-#define M_BCM1480_MC_ROW08                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW08)
-#define V_BCM1480_MC_ROW08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW08)
-#define G_BCM1480_MC_ROW08(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW08, M_BCM1480_MC_ROW08)
-
-#define S_BCM1480_MC_ROW09                  8
-#define M_BCM1480_MC_ROW09                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW09)
-#define V_BCM1480_MC_ROW09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW09)
-#define G_BCM1480_MC_ROW09(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW09, M_BCM1480_MC_ROW09)
-
-#define S_BCM1480_MC_ROW10                  16
-#define M_BCM1480_MC_ROW10                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW10)
-#define V_BCM1480_MC_ROW10(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW10)
-#define G_BCM1480_MC_ROW10(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW10, M_BCM1480_MC_ROW10)
-
-#define S_BCM1480_MC_ROW11                  24
-#define M_BCM1480_MC_ROW11                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW11)
-#define V_BCM1480_MC_ROW11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW11)
-#define G_BCM1480_MC_ROW11(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW11, M_BCM1480_MC_ROW11)
-
-#define S_BCM1480_MC_ROW12                  32
-#define M_BCM1480_MC_ROW12                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW12)
-#define V_BCM1480_MC_ROW12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW12)
-#define G_BCM1480_MC_ROW12(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW12, M_BCM1480_MC_ROW12)
-
-#define S_BCM1480_MC_ROW13                  40
-#define M_BCM1480_MC_ROW13                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW13)
-#define V_BCM1480_MC_ROW13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW13)
-#define G_BCM1480_MC_ROW13(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW13, M_BCM1480_MC_ROW13)
-
-#define S_BCM1480_MC_ROW14                  48
-#define M_BCM1480_MC_ROW14                  _SB_MAKEMASK(6, S_BCM1480_MC_ROW14)
-#define V_BCM1480_MC_ROW14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_ROW14)
-#define G_BCM1480_MC_ROW14(x)               _SB_GETVALUE(x, S_BCM1480_MC_ROW14, M_BCM1480_MC_ROW14)
-
-#define K_BCM1480_MC_ROWX_BIT_SPACING       8
-
-/*
- * Column Address Bit Select Register 0 (Table 86)
- */
-
-#define S_BCM1480_MC_COL00                  0
-#define M_BCM1480_MC_COL00                  _SB_MAKEMASK(6, S_BCM1480_MC_COL00)
-#define V_BCM1480_MC_COL00(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL00)
-#define G_BCM1480_MC_COL00(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL00, M_BCM1480_MC_COL00)
-
-#define S_BCM1480_MC_COL01                  8
-#define M_BCM1480_MC_COL01                  _SB_MAKEMASK(6, S_BCM1480_MC_COL01)
-#define V_BCM1480_MC_COL01(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL01)
-#define G_BCM1480_MC_COL01(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL01, M_BCM1480_MC_COL01)
-
-#define S_BCM1480_MC_COL02                  16
-#define M_BCM1480_MC_COL02                  _SB_MAKEMASK(6, S_BCM1480_MC_COL02)
-#define V_BCM1480_MC_COL02(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL02)
-#define G_BCM1480_MC_COL02(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL02, M_BCM1480_MC_COL02)
-
-#define S_BCM1480_MC_COL03                  24
-#define M_BCM1480_MC_COL03                  _SB_MAKEMASK(6, S_BCM1480_MC_COL03)
-#define V_BCM1480_MC_COL03(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL03)
-#define G_BCM1480_MC_COL03(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL03, M_BCM1480_MC_COL03)
-
-#define S_BCM1480_MC_COL04                  32
-#define M_BCM1480_MC_COL04                  _SB_MAKEMASK(6, S_BCM1480_MC_COL04)
-#define V_BCM1480_MC_COL04(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL04)
-#define G_BCM1480_MC_COL04(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL04, M_BCM1480_MC_COL04)
-
-#define S_BCM1480_MC_COL05                  40
-#define M_BCM1480_MC_COL05                  _SB_MAKEMASK(6, S_BCM1480_MC_COL05)
-#define V_BCM1480_MC_COL05(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL05)
-#define G_BCM1480_MC_COL05(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL05, M_BCM1480_MC_COL05)
-
-#define S_BCM1480_MC_COL06                  48
-#define M_BCM1480_MC_COL06                  _SB_MAKEMASK(6, S_BCM1480_MC_COL06)
-#define V_BCM1480_MC_COL06(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL06)
-#define G_BCM1480_MC_COL06(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL06, M_BCM1480_MC_COL06)
-
-#define S_BCM1480_MC_COL07                  56
-#define M_BCM1480_MC_COL07                  _SB_MAKEMASK(6, S_BCM1480_MC_COL07)
-#define V_BCM1480_MC_COL07(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL07)
-#define G_BCM1480_MC_COL07(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL07, M_BCM1480_MC_COL07)
-
-/*
- * Column Address Bit Select Register 1 (Table 87)
- */
-
-#define S_BCM1480_MC_COL08                  0
-#define M_BCM1480_MC_COL08                  _SB_MAKEMASK(6, S_BCM1480_MC_COL08)
-#define V_BCM1480_MC_COL08(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL08)
-#define G_BCM1480_MC_COL08(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL08, M_BCM1480_MC_COL08)
-
-#define S_BCM1480_MC_COL09                  8
-#define M_BCM1480_MC_COL09                  _SB_MAKEMASK(6, S_BCM1480_MC_COL09)
-#define V_BCM1480_MC_COL09(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL09)
-#define G_BCM1480_MC_COL09(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL09, M_BCM1480_MC_COL09)
-
-#define S_BCM1480_MC_COL10                  16   /* not a valid position, must be prog as 0 */
-
-#define S_BCM1480_MC_COL11                  24
-#define M_BCM1480_MC_COL11                  _SB_MAKEMASK(6, S_BCM1480_MC_COL11)
-#define V_BCM1480_MC_COL11(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL11)
-#define G_BCM1480_MC_COL11(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL11, M_BCM1480_MC_COL11)
-
-#define S_BCM1480_MC_COL12                  32
-#define M_BCM1480_MC_COL12                  _SB_MAKEMASK(6, S_BCM1480_MC_COL12)
-#define V_BCM1480_MC_COL12(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL12)
-#define G_BCM1480_MC_COL12(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL12, M_BCM1480_MC_COL12)
-
-#define S_BCM1480_MC_COL13                  40
-#define M_BCM1480_MC_COL13                  _SB_MAKEMASK(6, S_BCM1480_MC_COL13)
-#define V_BCM1480_MC_COL13(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL13)
-#define G_BCM1480_MC_COL13(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL13, M_BCM1480_MC_COL13)
-
-#define S_BCM1480_MC_COL14                  48
-#define M_BCM1480_MC_COL14                  _SB_MAKEMASK(6, S_BCM1480_MC_COL14)
-#define V_BCM1480_MC_COL14(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_COL14)
-#define G_BCM1480_MC_COL14(x)               _SB_GETVALUE(x, S_BCM1480_MC_COL14, M_BCM1480_MC_COL14)
-
-#define K_BCM1480_MC_COLX_BIT_SPACING       8
-
-/*
- * CS0 and CS1 Bank Address Bit Select Register (Table 88)
- */
-
-#define S_BCM1480_MC_CS01_BANK0             0
-#define M_BCM1480_MC_CS01_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK0)
-#define V_BCM1480_MC_CS01_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK0)
-#define G_BCM1480_MC_CS01_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK0, M_BCM1480_MC_CS01_BANK0)
-
-#define S_BCM1480_MC_CS01_BANK1             8
-#define M_BCM1480_MC_CS01_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK1)
-#define V_BCM1480_MC_CS01_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK1)
-#define G_BCM1480_MC_CS01_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK1, M_BCM1480_MC_CS01_BANK1)
-
-#define S_BCM1480_MC_CS01_BANK2             16
-#define M_BCM1480_MC_CS01_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS01_BANK2)
-#define V_BCM1480_MC_CS01_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS01_BANK2)
-#define G_BCM1480_MC_CS01_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS01_BANK2, M_BCM1480_MC_CS01_BANK2)
-
-/*
- * CS2 and CS3 Bank Address Bit Select Register (Table 89)
- */
-
-#define S_BCM1480_MC_CS23_BANK0             0
-#define M_BCM1480_MC_CS23_BANK0             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK0)
-#define V_BCM1480_MC_CS23_BANK0(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK0)
-#define G_BCM1480_MC_CS23_BANK0(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK0, M_BCM1480_MC_CS23_BANK0)
-
-#define S_BCM1480_MC_CS23_BANK1             8
-#define M_BCM1480_MC_CS23_BANK1             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK1)
-#define V_BCM1480_MC_CS23_BANK1(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK1)
-#define G_BCM1480_MC_CS23_BANK1(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK1, M_BCM1480_MC_CS23_BANK1)
-
-#define S_BCM1480_MC_CS23_BANK2             16
-#define M_BCM1480_MC_CS23_BANK2             _SB_MAKEMASK(6, S_BCM1480_MC_CS23_BANK2)
-#define V_BCM1480_MC_CS23_BANK2(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_CS23_BANK2)
-#define G_BCM1480_MC_CS23_BANK2(x)          _SB_GETVALUE(x, S_BCM1480_MC_CS23_BANK2, M_BCM1480_MC_CS23_BANK2)
-
-#define K_BCM1480_MC_CSXX_BANKX_BIT_SPACING  8
-
-/*
- * DRAM Command Register (Table 90)
- */
-
-#define S_BCM1480_MC_COMMAND                0
-#define M_BCM1480_MC_COMMAND                _SB_MAKEMASK(4, S_BCM1480_MC_COMMAND)
-#define V_BCM1480_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_COMMAND)
-#define G_BCM1480_MC_COMMAND(x)             _SB_GETVALUE(x, S_BCM1480_MC_COMMAND, M_BCM1480_MC_COMMAND)
-
-#define K_BCM1480_MC_COMMAND_EMRS           0
-#define K_BCM1480_MC_COMMAND_MRS            1
-#define K_BCM1480_MC_COMMAND_PRE            2
-#define K_BCM1480_MC_COMMAND_AR             3
-#define K_BCM1480_MC_COMMAND_SETRFSH        4
-#define K_BCM1480_MC_COMMAND_CLRRFSH        5
-#define K_BCM1480_MC_COMMAND_SETPWRDN       6
-#define K_BCM1480_MC_COMMAND_CLRPWRDN       7
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define K_BCM1480_MC_COMMAND_EMRS2          8
-#define K_BCM1480_MC_COMMAND_EMRS3          9
-#define K_BCM1480_MC_COMMAND_ENABLE_MCLK    10
-#define K_BCM1480_MC_COMMAND_DISABLE_MCLK   11
-#endif
-
-#define V_BCM1480_MC_COMMAND_EMRS           V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS)
-#define V_BCM1480_MC_COMMAND_MRS            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_MRS)
-#define V_BCM1480_MC_COMMAND_PRE            V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_PRE)
-#define V_BCM1480_MC_COMMAND_AR             V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_AR)
-#define V_BCM1480_MC_COMMAND_SETRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETRFSH)
-#define V_BCM1480_MC_COMMAND_CLRRFSH        V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRRFSH)
-#define V_BCM1480_MC_COMMAND_SETPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_SETPWRDN)
-#define V_BCM1480_MC_COMMAND_CLRPWRDN       V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_CLRPWRDN)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define V_BCM1480_MC_COMMAND_EMRS2          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS2)
-#define V_BCM1480_MC_COMMAND_EMRS3          V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_EMRS3)
-#define V_BCM1480_MC_COMMAND_ENABLE_MCLK    V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_ENABLE_MCLK)
-#define V_BCM1480_MC_COMMAND_DISABLE_MCLK   V_BCM1480_MC_COMMAND(K_BCM1480_MC_COMMAND_DISABLE_MCLK)
-#endif
-
-#define S_BCM1480_MC_CS0                    4
-#define M_BCM1480_MC_CS0                    _SB_MAKEMASK1(4)
-#define M_BCM1480_MC_CS1                    _SB_MAKEMASK1(5)
-#define M_BCM1480_MC_CS2                    _SB_MAKEMASK1(6)
-#define M_BCM1480_MC_CS3                    _SB_MAKEMASK1(7)
-#define M_BCM1480_MC_CS4                    _SB_MAKEMASK1(8)
-#define M_BCM1480_MC_CS5                    _SB_MAKEMASK1(9)
-#define M_BCM1480_MC_CS6                    _SB_MAKEMASK1(10)
-#define M_BCM1480_MC_CS7                    _SB_MAKEMASK1(11)
-
-#define M_BCM1480_MC_CS                  _SB_MAKEMASK(8, S_BCM1480_MC_CS0)
-#define V_BCM1480_MC_CS(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_CS0)
-#define G_BCM1480_MC_CS(x)               _SB_GETVALUE(x, S_BCM1480_MC_CS0, M_BCM1480_MC_CS0)
-
-#define M_BCM1480_MC_CMD_ACTIVE             _SB_MAKEMASK1(16)
-
-/*
- * DRAM Mode Register (Table 91)
- */
-
-#define S_BCM1480_MC_EMODE                  0
-#define M_BCM1480_MC_EMODE                  _SB_MAKEMASK(15, S_BCM1480_MC_EMODE)
-#define V_BCM1480_MC_EMODE(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_EMODE)
-#define G_BCM1480_MC_EMODE(x)               _SB_GETVALUE(x, S_BCM1480_MC_EMODE, M_BCM1480_MC_EMODE)
-#define V_BCM1480_MC_EMODE_DEFAULT          V_BCM1480_MC_EMODE(0)
-
-#define S_BCM1480_MC_MODE                   16
-#define M_BCM1480_MC_MODE                   _SB_MAKEMASK(15, S_BCM1480_MC_MODE)
-#define V_BCM1480_MC_MODE(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_MODE)
-#define G_BCM1480_MC_MODE(x)                _SB_GETVALUE(x, S_BCM1480_MC_MODE, M_BCM1480_MC_MODE)
-#define V_BCM1480_MC_MODE_DEFAULT           V_BCM1480_MC_MODE(0)
-
-#define S_BCM1480_MC_DRAM_TYPE              32
-#define M_BCM1480_MC_DRAM_TYPE              _SB_MAKEMASK(4, S_BCM1480_MC_DRAM_TYPE)
-#define V_BCM1480_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_DRAM_TYPE)
-#define G_BCM1480_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_BCM1480_MC_DRAM_TYPE, M_BCM1480_MC_DRAM_TYPE)
-
-#define K_BCM1480_MC_DRAM_TYPE_JEDEC        0
-#define K_BCM1480_MC_DRAM_TYPE_FCRAM        1
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define K_BCM1480_MC_DRAM_TYPE_DDR2         2
-#endif
-
-#define K_BCM1480_MC_DRAM_TYPE_DDR2_PASS1   0
-
-#define V_BCM1480_MC_DRAM_TYPE_JEDEC        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_JEDEC)
-#define V_BCM1480_MC_DRAM_TYPE_FCRAM        V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_FCRAM)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define V_BCM1480_MC_DRAM_TYPE_DDR2         V_BCM1480_MC_DRAM_TYPE(K_BCM1480_MC_DRAM_TYPE_DDR2)
-#endif
-
-#define M_BCM1480_MC_GANGED                 _SB_MAKEMASK1(36)
-#define M_BCM1480_MC_BY9_INTF               _SB_MAKEMASK1(37)
-#define M_BCM1480_MC_FORCE_ECC64            _SB_MAKEMASK1(38)
-#define M_BCM1480_MC_ECC_DISABLE            _SB_MAKEMASK1(39)
-
-#define S_BCM1480_MC_PG_POLICY              40
-#define M_BCM1480_MC_PG_POLICY              _SB_MAKEMASK(2, S_BCM1480_MC_PG_POLICY)
-#define V_BCM1480_MC_PG_POLICY(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_PG_POLICY)
-#define G_BCM1480_MC_PG_POLICY(x)           _SB_GETVALUE(x, S_BCM1480_MC_PG_POLICY, M_BCM1480_MC_PG_POLICY)
-
-#define K_BCM1480_MC_PG_POLICY_CLOSED       0
-#define K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK 1
-
-#define V_BCM1480_MC_PG_POLICY_CLOSED       V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CLOSED)
-#define V_BCM1480_MC_PG_POLICY_CAS_TIME_CHK V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define M_BCM1480_MC_2T_CMD                 _SB_MAKEMASK1(42)
-#define M_BCM1480_MC_ECC_COR_DIS            _SB_MAKEMASK1(43)
-#endif
-
-#define V_BCM1480_MC_DRAMMODE_DEFAULT   V_BCM1480_MC_EMODE_DEFAULT | V_BCM1480_MC_MODE_DEFAULT | V_BCM1480_MC_DRAM_TYPE_JEDEC | \
-                                V_BCM1480_MC_PG_POLICY(K_BCM1480_MC_PG_POLICY_CAS_TIME_CHK)
-
-/*
- * Memory Clock Configuration Register (Table 92)
- */
-
-#define S_BCM1480_MC_CLK_RATIO              0
-#define M_BCM1480_MC_CLK_RATIO              _SB_MAKEMASK(6, S_BCM1480_MC_CLK_RATIO)
-#define V_BCM1480_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_BCM1480_MC_CLK_RATIO)
-#define G_BCM1480_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_BCM1480_MC_CLK_RATIO, M_BCM1480_MC_CLK_RATIO)
-
-#define V_BCM1480_MC_CLK_RATIO_DEFAULT      V_BCM1480_MC_CLK_RATIO(10)
-
-#define S_BCM1480_MC_REF_RATE               8
-#define M_BCM1480_MC_REF_RATE               _SB_MAKEMASK(8, S_BCM1480_MC_REF_RATE)
-#define V_BCM1480_MC_REF_RATE(x)            _SB_MAKEVALUE(x, S_BCM1480_MC_REF_RATE)
-#define G_BCM1480_MC_REF_RATE(x)            _SB_GETVALUE(x, S_BCM1480_MC_REF_RATE, M_BCM1480_MC_REF_RATE)
-
-#define K_BCM1480_MC_REF_RATE_100MHz        0x31
-#define K_BCM1480_MC_REF_RATE_200MHz        0x62
-#define K_BCM1480_MC_REF_RATE_400MHz        0xC4
-
-#define V_BCM1480_MC_REF_RATE_100MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_100MHz)
-#define V_BCM1480_MC_REF_RATE_200MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_200MHz)
-#define V_BCM1480_MC_REF_RATE_400MHz        V_BCM1480_MC_REF_RATE(K_BCM1480_MC_REF_RATE_400MHz)
-#define V_BCM1480_MC_REF_RATE_DEFAULT       V_BCM1480_MC_REF_RATE_400MHz
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define M_BCM1480_MC_AUTO_REF_DIS           _SB_MAKEMASK1(16)
-#endif
-
-/*
- * ODT Register (Table 99)
- */
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define M_BCM1480_MC_RD_ODT0_CS0            _SB_MAKEMASK1(0)
-#define M_BCM1480_MC_RD_ODT0_CS2            _SB_MAKEMASK1(1)
-#define M_BCM1480_MC_RD_ODT0_CS4            _SB_MAKEMASK1(2)
-#define M_BCM1480_MC_RD_ODT0_CS6            _SB_MAKEMASK1(3)
-#define M_BCM1480_MC_WR_ODT0_CS0            _SB_MAKEMASK1(4)
-#define M_BCM1480_MC_WR_ODT0_CS2            _SB_MAKEMASK1(5)
-#define M_BCM1480_MC_WR_ODT0_CS4            _SB_MAKEMASK1(6)
-#define M_BCM1480_MC_WR_ODT0_CS6            _SB_MAKEMASK1(7)
-#define M_BCM1480_MC_RD_ODT2_CS0            _SB_MAKEMASK1(8)
-#define M_BCM1480_MC_RD_ODT2_CS2            _SB_MAKEMASK1(9)
-#define M_BCM1480_MC_RD_ODT2_CS4            _SB_MAKEMASK1(10)
-#define M_BCM1480_MC_RD_ODT2_CS6            _SB_MAKEMASK1(11)
-#define M_BCM1480_MC_WR_ODT2_CS0            _SB_MAKEMASK1(12)
-#define M_BCM1480_MC_WR_ODT2_CS2            _SB_MAKEMASK1(13)
-#define M_BCM1480_MC_WR_ODT2_CS4            _SB_MAKEMASK1(14)
-#define M_BCM1480_MC_WR_ODT2_CS6            _SB_MAKEMASK1(15)
-#define M_BCM1480_MC_RD_ODT4_CS0            _SB_MAKEMASK1(16)
-#define M_BCM1480_MC_RD_ODT4_CS2            _SB_MAKEMASK1(17)
-#define M_BCM1480_MC_RD_ODT4_CS4            _SB_MAKEMASK1(18)
-#define M_BCM1480_MC_RD_ODT4_CS6            _SB_MAKEMASK1(19)
-#define M_BCM1480_MC_WR_ODT4_CS0            _SB_MAKEMASK1(20)
-#define M_BCM1480_MC_WR_ODT4_CS2            _SB_MAKEMASK1(21)
-#define M_BCM1480_MC_WR_ODT4_CS4            _SB_MAKEMASK1(22)
-#define M_BCM1480_MC_WR_ODT4_CS6            _SB_MAKEMASK1(23)
-#define M_BCM1480_MC_RD_ODT6_CS0            _SB_MAKEMASK1(24)
-#define M_BCM1480_MC_RD_ODT6_CS2            _SB_MAKEMASK1(25)
-#define M_BCM1480_MC_RD_ODT6_CS4            _SB_MAKEMASK1(26)
-#define M_BCM1480_MC_RD_ODT6_CS6            _SB_MAKEMASK1(27)
-#define M_BCM1480_MC_WR_ODT6_CS0            _SB_MAKEMASK1(28)
-#define M_BCM1480_MC_WR_ODT6_CS2            _SB_MAKEMASK1(29)
-#define M_BCM1480_MC_WR_ODT6_CS4            _SB_MAKEMASK1(30)
-#define M_BCM1480_MC_WR_ODT6_CS6            _SB_MAKEMASK1(31)
-
-#define M_BCM1480_MC_CS_ODD_ODT_EN          _SB_MAKEMASK1(32)
-
-#define S_BCM1480_MC_ODT0                   0
-#define M_BCM1480_MC_ODT0                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT0)
-#define V_BCM1480_MC_ODT0(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT0)
-
-#define S_BCM1480_MC_ODT2                   8
-#define M_BCM1480_MC_ODT2                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT2)
-#define V_BCM1480_MC_ODT2(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT2)
-
-#define S_BCM1480_MC_ODT4                   16
-#define M_BCM1480_MC_ODT4                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT4)
-#define V_BCM1480_MC_ODT4(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT4)
-
-#define S_BCM1480_MC_ODT6                   24
-#define M_BCM1480_MC_ODT6                   _SB_MAKEMASK(8, S_BCM1480_MC_ODT6)
-#define V_BCM1480_MC_ODT6(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_ODT6)
-#endif
-
-/*
- * Memory DLL Configuration Register (Table 93)
- */
-
-#define S_BCM1480_MC_ADDR_COARSE_ADJ         0
-#define M_BCM1480_MC_ADDR_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_ADDR_COARSE_ADJ)
-#define V_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ)
-#define G_BCM1480_MC_ADDR_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_ADDR_COARSE_ADJ, M_BCM1480_MC_ADDR_COARSE_ADJ)
-#define V_BCM1480_MC_ADDR_COARSE_ADJ_DEFAULT V_BCM1480_MC_ADDR_COARSE_ADJ(0x0)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_ADDR_FREQ_RANGE            8
-#define M_BCM1480_MC_ADDR_FREQ_RANGE            _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FREQ_RANGE)
-#define V_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE)
-#define G_BCM1480_MC_ADDR_FREQ_RANGE(x)         _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FREQ_RANGE, M_BCM1480_MC_ADDR_FREQ_RANGE)
-#define V_BCM1480_MC_ADDR_FREQ_RANGE_DEFAULT    V_BCM1480_MC_ADDR_FREQ_RANGE(0x4)
-#endif
-
-#define S_BCM1480_MC_ADDR_FINE_ADJ          8
-#define M_BCM1480_MC_ADDR_FINE_ADJ          _SB_MAKEMASK(4, S_BCM1480_MC_ADDR_FINE_ADJ)
-#define V_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ)
-#define G_BCM1480_MC_ADDR_FINE_ADJ(x)       _SB_GETVALUE(x, S_BCM1480_MC_ADDR_FINE_ADJ, M_BCM1480_MC_ADDR_FINE_ADJ)
-#define V_BCM1480_MC_ADDR_FINE_ADJ_DEFAULT  V_BCM1480_MC_ADDR_FINE_ADJ(0x8)
-
-#define S_BCM1480_MC_DQI_COARSE_ADJ         16
-#define M_BCM1480_MC_DQI_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQI_COARSE_ADJ)
-#define V_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ)
-#define G_BCM1480_MC_DQI_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQI_COARSE_ADJ, M_BCM1480_MC_DQI_COARSE_ADJ)
-#define V_BCM1480_MC_DQI_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQI_COARSE_ADJ(0x0)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_DQI_FREQ_RANGE             24
-#define M_BCM1480_MC_DQI_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FREQ_RANGE)
-#define V_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE)
-#define G_BCM1480_MC_DQI_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DQI_FREQ_RANGE, M_BCM1480_MC_DQI_FREQ_RANGE)
-#define V_BCM1480_MC_DQI_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQI_FREQ_RANGE(0x4)
-#endif
-
-#define S_BCM1480_MC_DQI_FINE_ADJ           24
-#define M_BCM1480_MC_DQI_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQI_FINE_ADJ)
-#define V_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ)
-#define G_BCM1480_MC_DQI_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQI_FINE_ADJ, M_BCM1480_MC_DQI_FINE_ADJ)
-#define V_BCM1480_MC_DQI_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQI_FINE_ADJ(0x8)
-
-#define S_BCM1480_MC_DQO_COARSE_ADJ         32
-#define M_BCM1480_MC_DQO_COARSE_ADJ         _SB_MAKEMASK(6, S_BCM1480_MC_DQO_COARSE_ADJ)
-#define V_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ)
-#define G_BCM1480_MC_DQO_COARSE_ADJ(x)      _SB_GETVALUE(x, S_BCM1480_MC_DQO_COARSE_ADJ, M_BCM1480_MC_DQO_COARSE_ADJ)
-#define V_BCM1480_MC_DQO_COARSE_ADJ_DEFAULT V_BCM1480_MC_DQO_COARSE_ADJ(0x0)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_DQO_FREQ_RANGE             40
-#define M_BCM1480_MC_DQO_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FREQ_RANGE)
-#define V_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE)
-#define G_BCM1480_MC_DQO_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DQO_FREQ_RANGE, M_BCM1480_MC_DQO_FREQ_RANGE)
-#define V_BCM1480_MC_DQO_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DQO_FREQ_RANGE(0x4)
-#endif
-
-#define S_BCM1480_MC_DQO_FINE_ADJ           40
-#define M_BCM1480_MC_DQO_FINE_ADJ           _SB_MAKEMASK(4, S_BCM1480_MC_DQO_FINE_ADJ)
-#define V_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ)
-#define G_BCM1480_MC_DQO_FINE_ADJ(x)        _SB_GETVALUE(x, S_BCM1480_MC_DQO_FINE_ADJ, M_BCM1480_MC_DQO_FINE_ADJ)
-#define V_BCM1480_MC_DQO_FINE_ADJ_DEFAULT   V_BCM1480_MC_DQO_FINE_ADJ(0x8)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_DLL_PDSEL            44
-#define M_BCM1480_MC_DLL_PDSEL            _SB_MAKEMASK(2, S_BCM1480_MC_DLL_PDSEL)
-#define V_BCM1480_MC_DLL_PDSEL(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_PDSEL)
-#define G_BCM1480_MC_DLL_PDSEL(x)         _SB_GETVALUE(x, S_BCM1480_MC_DLL_PDSEL, M_BCM1480_MC_DLL_PDSEL)
-#define V_BCM1480_MC_DLL_DEFAULT_PDSEL    V_BCM1480_MC_DLL_PDSEL(0x0)
-
-#define M_BCM1480_MC_DLL_REGBYPASS        _SB_MAKEMASK1(46)
-#define M_BCM1480_MC_DQO_SHIFT            _SB_MAKEMASK1(47)
-#endif
-
-#define S_BCM1480_MC_DLL_DEFAULT           48
-#define M_BCM1480_MC_DLL_DEFAULT           _SB_MAKEMASK(6, S_BCM1480_MC_DLL_DEFAULT)
-#define V_BCM1480_MC_DLL_DEFAULT(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_DEFAULT)
-#define G_BCM1480_MC_DLL_DEFAULT(x)        _SB_GETVALUE(x, S_BCM1480_MC_DLL_DEFAULT, M_BCM1480_MC_DLL_DEFAULT)
-#define V_BCM1480_MC_DLL_DEFAULT_DEFAULT   V_BCM1480_MC_DLL_DEFAULT(0x10)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_DLL_REGCTRL          54
-#define M_BCM1480_MC_DLL_REGCTRL          _SB_MAKEMASK(2, S_BCM1480_MC_DLL_REGCTRL)
-#define V_BCM1480_MC_DLL_REGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_REGCTRL)
-#define G_BCM1480_MC_DLL_REGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_REGCTRL, M_BCM1480_MC_DLL_REGCTRL)
-#define V_BCM1480_MC_DLL_DEFAULT_REGCTRL  V_BCM1480_MC_DLL_REGCTRL(0x0)
-#endif
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_DLL_FREQ_RANGE             56
-#define M_BCM1480_MC_DLL_FREQ_RANGE             _SB_MAKEMASK(4, S_BCM1480_MC_DLL_FREQ_RANGE)
-#define V_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE)
-#define G_BCM1480_MC_DLL_FREQ_RANGE(x)          _SB_GETVALUE(x, S_BCM1480_MC_DLL_FREQ_RANGE, M_BCM1480_MC_DLL_FREQ_RANGE)
-#define V_BCM1480_MC_DLL_FREQ_RANGE_DEFAULT     V_BCM1480_MC_DLL_FREQ_RANGE(0x4)
-#endif
-
-#define S_BCM1480_MC_DLL_STEP_SIZE          56
-#define M_BCM1480_MC_DLL_STEP_SIZE          _SB_MAKEMASK(4, S_BCM1480_MC_DLL_STEP_SIZE)
-#define V_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE)
-#define G_BCM1480_MC_DLL_STEP_SIZE(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_STEP_SIZE, M_BCM1480_MC_DLL_STEP_SIZE)
-#define V_BCM1480_MC_DLL_STEP_SIZE_DEFAULT  V_BCM1480_MC_DLL_STEP_SIZE(0x8)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_DLL_BGCTRL   60
-#define M_BCM1480_MC_DLL_BGCTRL           _SB_MAKEMASK(2, S_BCM1480_MC_DLL_BGCTRL)
-#define V_BCM1480_MC_DLL_BGCTRL(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_DLL_BGCTRL)
-#define G_BCM1480_MC_DLL_BGCTRL(x)       _SB_GETVALUE(x, S_BCM1480_MC_DLL_BGCTRL, M_BCM1480_MC_DLL_BGCTRL)
-#define V_BCM1480_MC_DLL_DEFAULT_BGCTRL  V_BCM1480_MC_DLL_BGCTRL(0x0)
-#endif
-
-#define M_BCM1480_MC_DLL_BYPASS             _SB_MAKEMASK1(63)
-
-/*
- * Memory Drive Configuration Register (Table 94)
- */
-
-#define S_BCM1480_MC_RTT_BYP_PULLDOWN       0
-#define M_BCM1480_MC_RTT_BYP_PULLDOWN       _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLDOWN)
-#define V_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN)
-#define G_BCM1480_MC_RTT_BYP_PULLDOWN(x)    _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLDOWN, M_BCM1480_MC_RTT_BYP_PULLDOWN)
-
-#define S_BCM1480_MC_RTT_BYP_PULLUP         6
-#define M_BCM1480_MC_RTT_BYP_PULLUP         _SB_MAKEMASK(3, S_BCM1480_MC_RTT_BYP_PULLUP)
-#define V_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP)
-#define G_BCM1480_MC_RTT_BYP_PULLUP(x)      _SB_GETVALUE(x, S_BCM1480_MC_RTT_BYP_PULLUP, M_BCM1480_MC_RTT_BYP_PULLUP)
-
-#define M_BCM1480_MC_RTT_BYPASS             _SB_MAKEMASK1(8)
-#define M_BCM1480_MC_RTT_COMP_MOV_AVG       _SB_MAKEMASK1(9)
-
-#define S_BCM1480_MC_PVT_BYP_C1_PULLDOWN    10
-#define M_BCM1480_MC_PVT_BYP_C1_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
-#define V_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
-#define G_BCM1480_MC_PVT_BYP_C1_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLDOWN, M_BCM1480_MC_PVT_BYP_C1_PULLDOWN)
-
-#define S_BCM1480_MC_PVT_BYP_C1_PULLUP      15
-#define M_BCM1480_MC_PVT_BYP_C1_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
-#define V_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP)
-#define G_BCM1480_MC_PVT_BYP_C1_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C1_PULLUP, M_BCM1480_MC_PVT_BYP_C1_PULLUP)
-
-#define S_BCM1480_MC_PVT_BYP_C2_PULLDOWN    20
-#define M_BCM1480_MC_PVT_BYP_C2_PULLDOWN    _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
-#define V_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
-#define G_BCM1480_MC_PVT_BYP_C2_PULLDOWN(x) _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLDOWN, M_BCM1480_MC_PVT_BYP_C2_PULLDOWN)
-
-#define S_BCM1480_MC_PVT_BYP_C2_PULLUP      25
-#define M_BCM1480_MC_PVT_BYP_C2_PULLUP      _SB_MAKEMASK(4, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
-#define V_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_MAKEVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP)
-#define G_BCM1480_MC_PVT_BYP_C2_PULLUP(x)   _SB_GETVALUE(x, S_BCM1480_MC_PVT_BYP_C2_PULLUP, M_BCM1480_MC_PVT_BYP_C2_PULLUP)
-
-#define M_BCM1480_MC_PVT_BYPASS             _SB_MAKEMASK1(30)
-#define M_BCM1480_MC_PVT_COMP_MOV_AVG       _SB_MAKEMASK1(31)
-
-#define M_BCM1480_MC_CLK_CLASS              _SB_MAKEMASK1(34)
-#define M_BCM1480_MC_DATA_CLASS             _SB_MAKEMASK1(35)
-#define M_BCM1480_MC_ADDR_CLASS             _SB_MAKEMASK1(36)
-
-#define M_BCM1480_MC_DQ_ODT_75              _SB_MAKEMASK1(37)
-#define M_BCM1480_MC_DQ_ODT_150             _SB_MAKEMASK1(38)
-#define M_BCM1480_MC_DQS_ODT_75             _SB_MAKEMASK1(39)
-#define M_BCM1480_MC_DQS_ODT_150            _SB_MAKEMASK1(40)
-#define M_BCM1480_MC_DQS_DIFF               _SB_MAKEMASK1(41)
-
-/*
- * ECC Test Data Register (Table 95)
- */
-
-#define S_BCM1480_MC_DATA_INVERT            0
-#define M_DATA_ECC_INVERT           _SB_MAKEMASK(64, S_BCM1480_MC_ECC_INVERT)
-
-/*
- * ECC Test ECC Register (Table 96)
- */
-
-#define S_BCM1480_MC_ECC_INVERT             0
-#define M_BCM1480_MC_ECC_INVERT             _SB_MAKEMASK(8, S_BCM1480_MC_ECC_INVERT)
-
-/*
- * SDRAM Timing Register  (Table 97)
- */
-
-#define S_BCM1480_MC_tRCD                   0
-#define M_BCM1480_MC_tRCD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRCD)
-#define V_BCM1480_MC_tRCD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCD)
-#define G_BCM1480_MC_tRCD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCD, M_BCM1480_MC_tRCD)
-#define K_BCM1480_MC_tRCD_DEFAULT           3
-#define V_BCM1480_MC_tRCD_DEFAULT           V_BCM1480_MC_tRCD(K_BCM1480_MC_tRCD_DEFAULT)
-
-#define S_BCM1480_MC_tCL                    4
-#define M_BCM1480_MC_tCL                    _SB_MAKEMASK(4, S_BCM1480_MC_tCL)
-#define V_BCM1480_MC_tCL(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tCL)
-#define G_BCM1480_MC_tCL(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tCL, M_BCM1480_MC_tCL)
-#define K_BCM1480_MC_tCL_DEFAULT            2
-#define V_BCM1480_MC_tCL_DEFAULT            V_BCM1480_MC_tCL(K_BCM1480_MC_tCL_DEFAULT)
-
-#define M_BCM1480_MC_tCrDh                  _SB_MAKEMASK1(8)
-
-#define S_BCM1480_MC_tWR                    9
-#define M_BCM1480_MC_tWR                    _SB_MAKEMASK(3, S_BCM1480_MC_tWR)
-#define V_BCM1480_MC_tWR(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tWR)
-#define G_BCM1480_MC_tWR(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tWR, M_BCM1480_MC_tWR)
-#define K_BCM1480_MC_tWR_DEFAULT            2
-#define V_BCM1480_MC_tWR_DEFAULT            V_BCM1480_MC_tWR(K_BCM1480_MC_tWR_DEFAULT)
-
-#define S_BCM1480_MC_tCwD                   12
-#define M_BCM1480_MC_tCwD                   _SB_MAKEMASK(4, S_BCM1480_MC_tCwD)
-#define V_BCM1480_MC_tCwD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tCwD)
-#define G_BCM1480_MC_tCwD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tCwD, M_BCM1480_MC_tCwD)
-#define K_BCM1480_MC_tCwD_DEFAULT           1
-#define V_BCM1480_MC_tCwD_DEFAULT           V_BCM1480_MC_tCwD(K_BCM1480_MC_tCwD_DEFAULT)
-
-#define S_BCM1480_MC_tRP                    16
-#define M_BCM1480_MC_tRP                    _SB_MAKEMASK(4, S_BCM1480_MC_tRP)
-#define V_BCM1480_MC_tRP(x)                 _SB_MAKEVALUE(x, S_BCM1480_MC_tRP)
-#define G_BCM1480_MC_tRP(x)                 _SB_GETVALUE(x, S_BCM1480_MC_tRP, M_BCM1480_MC_tRP)
-#define K_BCM1480_MC_tRP_DEFAULT            4
-#define V_BCM1480_MC_tRP_DEFAULT            V_BCM1480_MC_tRP(K_BCM1480_MC_tRP_DEFAULT)
-
-#define S_BCM1480_MC_tRRD                   20
-#define M_BCM1480_MC_tRRD                   _SB_MAKEMASK(4, S_BCM1480_MC_tRRD)
-#define V_BCM1480_MC_tRRD(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRRD)
-#define G_BCM1480_MC_tRRD(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRRD, M_BCM1480_MC_tRRD)
-#define K_BCM1480_MC_tRRD_DEFAULT           2
-#define V_BCM1480_MC_tRRD_DEFAULT           V_BCM1480_MC_tRRD(K_BCM1480_MC_tRRD_DEFAULT)
-
-#define S_BCM1480_MC_tRCw                   24
-#define M_BCM1480_MC_tRCw                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCw)
-#define V_BCM1480_MC_tRCw(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCw)
-#define G_BCM1480_MC_tRCw(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCw, M_BCM1480_MC_tRCw)
-#define K_BCM1480_MC_tRCw_DEFAULT           10
-#define V_BCM1480_MC_tRCw_DEFAULT           V_BCM1480_MC_tRCw(K_BCM1480_MC_tRCw_DEFAULT)
-
-#define S_BCM1480_MC_tRCr                   32
-#define M_BCM1480_MC_tRCr                   _SB_MAKEMASK(5, S_BCM1480_MC_tRCr)
-#define V_BCM1480_MC_tRCr(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRCr)
-#define G_BCM1480_MC_tRCr(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRCr, M_BCM1480_MC_tRCr)
-#define K_BCM1480_MC_tRCr_DEFAULT           9
-#define V_BCM1480_MC_tRCr_DEFAULT           V_BCM1480_MC_tRCr(K_BCM1480_MC_tRCr_DEFAULT)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define S_BCM1480_MC_tFAW                   40
-#define M_BCM1480_MC_tFAW                   _SB_MAKEMASK(6, S_BCM1480_MC_tFAW)
-#define V_BCM1480_MC_tFAW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tFAW)
-#define G_BCM1480_MC_tFAW(x)                _SB_GETVALUE(x, S_BCM1480_MC_tFAW, M_BCM1480_MC_tFAW)
-#define K_BCM1480_MC_tFAW_DEFAULT           0
-#define V_BCM1480_MC_tFAW_DEFAULT           V_BCM1480_MC_tFAW(K_BCM1480_MC_tFAW_DEFAULT)
-#endif
-
-#define S_BCM1480_MC_tRFC                   48
-#define M_BCM1480_MC_tRFC                   _SB_MAKEMASK(7, S_BCM1480_MC_tRFC)
-#define V_BCM1480_MC_tRFC(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRFC)
-#define G_BCM1480_MC_tRFC(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRFC, M_BCM1480_MC_tRFC)
-#define K_BCM1480_MC_tRFC_DEFAULT           12
-#define V_BCM1480_MC_tRFC_DEFAULT           V_BCM1480_MC_tRFC(K_BCM1480_MC_tRFC_DEFAULT)
-
-#define S_BCM1480_MC_tFIFO                  56
-#define M_BCM1480_MC_tFIFO                  _SB_MAKEMASK(2, S_BCM1480_MC_tFIFO)
-#define V_BCM1480_MC_tFIFO(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tFIFO)
-#define G_BCM1480_MC_tFIFO(x)               _SB_GETVALUE(x, S_BCM1480_MC_tFIFO, M_BCM1480_MC_tFIFO)
-#define K_BCM1480_MC_tFIFO_DEFAULT          0
-#define V_BCM1480_MC_tFIFO_DEFAULT          V_BCM1480_MC_tFIFO(K_BCM1480_MC_tFIFO_DEFAULT)
-
-#define S_BCM1480_MC_tW2R                  58
-#define M_BCM1480_MC_tW2R                  _SB_MAKEMASK(2, S_BCM1480_MC_tW2R)
-#define V_BCM1480_MC_tW2R(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tW2R)
-#define G_BCM1480_MC_tW2R(x)               _SB_GETVALUE(x, S_BCM1480_MC_tW2R, M_BCM1480_MC_tW2R)
-#define K_BCM1480_MC_tW2R_DEFAULT          1
-#define V_BCM1480_MC_tW2R_DEFAULT          V_BCM1480_MC_tW2R(K_BCM1480_MC_tW2R_DEFAULT)
-
-#define S_BCM1480_MC_tR2W                  60
-#define M_BCM1480_MC_tR2W                  _SB_MAKEMASK(2, S_BCM1480_MC_tR2W)
-#define V_BCM1480_MC_tR2W(x)               _SB_MAKEVALUE(x, S_BCM1480_MC_tR2W)
-#define G_BCM1480_MC_tR2W(x)               _SB_GETVALUE(x, S_BCM1480_MC_tR2W, M_BCM1480_MC_tR2W)
-#define K_BCM1480_MC_tR2W_DEFAULT          0
-#define V_BCM1480_MC_tR2W_DEFAULT          V_BCM1480_MC_tR2W(K_BCM1480_MC_tR2W_DEFAULT)
-
-#define M_BCM1480_MC_tR2R                   _SB_MAKEMASK1(62)
-
-#define V_BCM1480_MC_TIMING_DEFAULT         (M_BCM1480_MC_tR2R | \
-                                     V_BCM1480_MC_tFIFO_DEFAULT | \
-                                     V_BCM1480_MC_tR2W_DEFAULT | \
-                                     V_BCM1480_MC_tW2R_DEFAULT | \
-                                     V_BCM1480_MC_tRFC_DEFAULT | \
-                                     V_BCM1480_MC_tRCr_DEFAULT | \
-                                     V_BCM1480_MC_tRCw_DEFAULT | \
-                                     V_BCM1480_MC_tRRD_DEFAULT | \
-                                     V_BCM1480_MC_tRP_DEFAULT | \
-                                     V_BCM1480_MC_tCwD_DEFAULT | \
-                                     V_BCM1480_MC_tWR_DEFAULT | \
-                                     M_BCM1480_MC_tCrDh | \
-                                     V_BCM1480_MC_tCL_DEFAULT | \
-                                     V_BCM1480_MC_tRCD_DEFAULT)
-
-/*
- * SDRAM Timing Register 2
- */
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-
-#define S_BCM1480_MC_tAL                   0
-#define M_BCM1480_MC_tAL                   _SB_MAKEMASK(4, S_BCM1480_MC_tAL)
-#define V_BCM1480_MC_tAL(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tAL)
-#define G_BCM1480_MC_tAL(x)                _SB_GETVALUE(x, S_BCM1480_MC_tAL, M_BCM1480_MC_tAL)
-#define K_BCM1480_MC_tAL_DEFAULT           0
-#define V_BCM1480_MC_tAL_DEFAULT           V_BCM1480_MC_tAL(K_BCM1480_MC_tAL_DEFAULT)
-
-#define S_BCM1480_MC_tRTP                   4
-#define M_BCM1480_MC_tRTP                   _SB_MAKEMASK(3, S_BCM1480_MC_tRTP)
-#define V_BCM1480_MC_tRTP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRTP)
-#define G_BCM1480_MC_tRTP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRTP, M_BCM1480_MC_tRTP)
-#define K_BCM1480_MC_tRTP_DEFAULT           2
-#define V_BCM1480_MC_tRTP_DEFAULT           V_BCM1480_MC_tRTP(K_BCM1480_MC_tRTP_DEFAULT)
-
-#define S_BCM1480_MC_tW2W                   8
-#define M_BCM1480_MC_tW2W                   _SB_MAKEMASK(2, S_BCM1480_MC_tW2W)
-#define V_BCM1480_MC_tW2W(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tW2W)
-#define G_BCM1480_MC_tW2W(x)                _SB_GETVALUE(x, S_BCM1480_MC_tW2W, M_BCM1480_MC_tW2W)
-#define K_BCM1480_MC_tW2W_DEFAULT           0
-#define V_BCM1480_MC_tW2W_DEFAULT           V_BCM1480_MC_tW2W(K_BCM1480_MC_tW2W_DEFAULT)
-
-#define S_BCM1480_MC_tRAP                   12
-#define M_BCM1480_MC_tRAP                  _SB_MAKEMASK(4, S_BCM1480_MC_tRAP)
-#define V_BCM1480_MC_tRAP(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_tRAP)
-#define G_BCM1480_MC_tRAP(x)                _SB_GETVALUE(x, S_BCM1480_MC_tRAP, M_BCM1480_MC_tRAP)
-#define K_BCM1480_MC_tRAP_DEFAULT           0
-#define V_BCM1480_MC_tRAP_DEFAULT           V_BCM1480_MC_tRAP(K_BCM1480_MC_tRAP_DEFAULT)
-
-#endif
-
-
-
-/*
- * Global Registers: single instances per BCM1480
- */
-
-/*
- * Global Configuration Register (Table 99)
- */
-
-#define S_BCM1480_MC_BLK_SET_MARK           8
-#define M_BCM1480_MC_BLK_SET_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_SET_MARK)
-#define V_BCM1480_MC_BLK_SET_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_SET_MARK)
-#define G_BCM1480_MC_BLK_SET_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_SET_MARK, M_BCM1480_MC_BLK_SET_MARK)
-
-#define S_BCM1480_MC_BLK_CLR_MARK           12
-#define M_BCM1480_MC_BLK_CLR_MARK           _SB_MAKEMASK(4, S_BCM1480_MC_BLK_CLR_MARK)
-#define V_BCM1480_MC_BLK_CLR_MARK(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_BLK_CLR_MARK)
-#define G_BCM1480_MC_BLK_CLR_MARK(x)        _SB_GETVALUE(x, S_BCM1480_MC_BLK_CLR_MARK, M_BCM1480_MC_BLK_CLR_MARK)
-
-#define M_BCM1480_MC_PKT_PRIORITY           _SB_MAKEMASK1(16)
-
-#define S_BCM1480_MC_MAX_AGE                20
-#define M_BCM1480_MC_MAX_AGE                _SB_MAKEMASK(4, S_BCM1480_MC_MAX_AGE)
-#define V_BCM1480_MC_MAX_AGE(x)             _SB_MAKEVALUE(x, S_BCM1480_MC_MAX_AGE)
-#define G_BCM1480_MC_MAX_AGE(x)             _SB_GETVALUE(x, S_BCM1480_MC_MAX_AGE, M_BCM1480_MC_MAX_AGE)
-
-#define M_BCM1480_MC_BERR_DISABLE           _SB_MAKEMASK1(29)
-#define M_BCM1480_MC_FORCE_SEQ              _SB_MAKEMASK1(30)
-#define M_BCM1480_MC_VGEN                   _SB_MAKEMASK1(32)
-
-#define S_BCM1480_MC_SLEW                   33
-#define M_BCM1480_MC_SLEW                   _SB_MAKEMASK(2, S_BCM1480_MC_SLEW)
-#define V_BCM1480_MC_SLEW(x)                _SB_MAKEVALUE(x, S_BCM1480_MC_SLEW)
-#define G_BCM1480_MC_SLEW(x)                _SB_GETVALUE(x, S_BCM1480_MC_SLEW, M_BCM1480_MC_SLEW)
-
-#define M_BCM1480_MC_SSTL_VOLTAGE           _SB_MAKEMASK1(35)
-
-/*
- * Global Channel Interleave Register (Table 100)
- */
-
-#define S_BCM1480_MC_INTLV0                 0
-#define M_BCM1480_MC_INTLV0                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV0)
-#define V_BCM1480_MC_INTLV0(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV0)
-#define G_BCM1480_MC_INTLV0(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV0, M_BCM1480_MC_INTLV0)
-
-#define S_BCM1480_MC_INTLV1                 8
-#define M_BCM1480_MC_INTLV1                 _SB_MAKEMASK(6, S_BCM1480_MC_INTLV1)
-#define V_BCM1480_MC_INTLV1(x)              _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV1)
-#define G_BCM1480_MC_INTLV1(x)              _SB_GETVALUE(x, S_BCM1480_MC_INTLV1, M_BCM1480_MC_INTLV1)
-
-#define S_BCM1480_MC_INTLV_MODE             16
-#define M_BCM1480_MC_INTLV_MODE             _SB_MAKEMASK(3, S_BCM1480_MC_INTLV_MODE)
-#define V_BCM1480_MC_INTLV_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_MC_INTLV_MODE)
-#define G_BCM1480_MC_INTLV_MODE(x)          _SB_GETVALUE(x, S_BCM1480_MC_INTLV_MODE, M_BCM1480_MC_INTLV_MODE)
-
-#define K_BCM1480_MC_INTLV_MODE_NONE        0x0
-#define K_BCM1480_MC_INTLV_MODE_01          0x1
-#define K_BCM1480_MC_INTLV_MODE_23          0x2
-#define K_BCM1480_MC_INTLV_MODE_01_23       0x3
-#define K_BCM1480_MC_INTLV_MODE_0123        0x4
-
-#define V_BCM1480_MC_INTLV_MODE_NONE        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_NONE)
-#define V_BCM1480_MC_INTLV_MODE_01          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01)
-#define V_BCM1480_MC_INTLV_MODE_23          V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_23)
-#define V_BCM1480_MC_INTLV_MODE_01_23       V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_01_23)
-#define V_BCM1480_MC_INTLV_MODE_0123        V_BCM1480_MC_INTLV_MODE(K_BCM1480_MC_INTLV_MODE_0123)
-
-/*
- * ECC Status Register
- */
-
-#define S_BCM1480_MC_ECC_ERR_ADDR           0
-#define M_BCM1480_MC_ECC_ERR_ADDR           _SB_MAKEMASK(37, S_BCM1480_MC_ECC_ERR_ADDR)
-#define V_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR)
-#define G_BCM1480_MC_ECC_ERR_ADDR(x)        _SB_GETVALUE(x, S_BCM1480_MC_ECC_ERR_ADDR, M_BCM1480_MC_ECC_ERR_ADDR)
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define M_BCM1480_MC_ECC_ERR_RMW            _SB_MAKEMASK1(60)
-#endif
-
-#define M_BCM1480_MC_ECC_MULT_ERR_DET       _SB_MAKEMASK1(61)
-#define M_BCM1480_MC_ECC_UERR_DET           _SB_MAKEMASK1(62)
-#define M_BCM1480_MC_ECC_CERR_DET           _SB_MAKEMASK1(63)
-
-/*
- * Global ECC Address Register (Table 102)
- */
-
-#define S_BCM1480_MC_ECC_CORR_ADDR          0
-#define M_BCM1480_MC_ECC_CORR_ADDR          _SB_MAKEMASK(37, S_BCM1480_MC_ECC_CORR_ADDR)
-#define V_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR)
-#define G_BCM1480_MC_ECC_CORR_ADDR(x)       _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORR_ADDR, M_BCM1480_MC_ECC_CORR_ADDR)
-
-/*
- * Global ECC Correction Register (Table 103)
- */
-
-#define S_BCM1480_MC_ECC_CORRECT            0
-#define M_BCM1480_MC_ECC_CORRECT            _SB_MAKEMASK(64, S_BCM1480_MC_ECC_CORRECT)
-#define V_BCM1480_MC_ECC_CORRECT(x)         _SB_MAKEVALUE(x, S_BCM1480_MC_ECC_CORRECT)
-#define G_BCM1480_MC_ECC_CORRECT(x)         _SB_GETVALUE(x, S_BCM1480_MC_ECC_CORRECT, M_BCM1480_MC_ECC_CORRECT)
-
-/*
- * Global ECC Performance Counters Control Register (Table 104)
- */
-
-#define S_BCM1480_MC_CHANNEL_SELECT         0
-#define M_BCM1480_MC_CHANNEL_SELECT         _SB_MAKEMASK(4, S_BCM1480_MC_CHANNEL_SELECT)
-#define V_BCM1480_MC_CHANNEL_SELECT(x)      _SB_MAKEVALUE(x, S_BCM1480_MC_CHANNEL_SELECT)
-#define G_BCM1480_MC_CHANNEL_SELECT(x)      _SB_GETVALUE(x, S_BCM1480_MC_CHANNEL_SELECT, M_BCM1480_MC_CHANNEL_SELECT)
-#define K_BCM1480_MC_CHANNEL_SELECT_0       0x1
-#define K_BCM1480_MC_CHANNEL_SELECT_1       0x2
-#define K_BCM1480_MC_CHANNEL_SELECT_2       0x4
-#define K_BCM1480_MC_CHANNEL_SELECT_3       0x8
-
-#endif /* _BCM1480_MC_H */
diff --git a/include/asm-mips/sibyte/bcm1480_regs.h b/include/asm-mips/sibyte/bcm1480_regs.h
deleted file mode 100644
index b4077bb72611..000000000000
--- a/include/asm-mips/sibyte/bcm1480_regs.h
+++ /dev/null
@@ -1,902 +0,0 @@
-/*  *********************************************************************
-    *  BCM1255/BCM1280/BCM1455/BCM1480 Board Support Package
-    *
-    *  Register Definitions                     File: bcm1480_regs.h
-    *
-    *  This module contains the addresses of the on-chip peripherals
-    *  on the BCM1280 and BCM1480.
-    *
-    *  BCM1480 specification level:  1X55_1X80-UM100-D4 (11/24/03)
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-#ifndef _BCM1480_REGS_H
-#define _BCM1480_REGS_H
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  Pull in the BCM1250's registers since a great deal of the 1480's
-    *  functions are the same as the BCM1250.
-    ********************************************************************* */
-
-#include "sb1250_regs.h"
-
-
-/*  *********************************************************************
-    *  Some general notes:
-    *
-    *  Register addresses are grouped by function and follow the order
-    *  of the User Manual.
-    *
-    *  For the most part, when there is more than one peripheral
-    *  of the same type on the SOC, the constants below will be
-    *  offsets from the base of each peripheral.  For example,
-    *  the MAC registers are described as offsets from the first
-    *  MAC register, and there will be a MAC_REGISTER() macro
-    *  to calculate the base address of a given MAC.
-    *
-    *  The information in this file is based on the BCM1X55/BCM1X80
-    *  User Manual, Document 1X55_1X80-UM100-R, 22/12/03.
-    *
-    *  This file is basically a "what's new" header file.  Since the
-    *  BCM1250 and the new BCM1480 (and derivatives) share many common
-    *  features, this file contains only what's new or changed from
-    *  the 1250.  (above, you can see that we include the 1250 symbols
-    *  to get the base functionality).
-    *
-    *  In software, be sure to use the correct symbols, particularly
-    *  for blocks that are different between the two chip families.
-    *  All BCM1480-specific symbols have _BCM1480_ in their names,
-    *  and all BCM1250-specific and "base" functions that are common in
-    *  both chips have no special names (this is for compatibility with
-    *  older include files).  Therefore, if you're working with the
-    *  SCD, which is very different on each chip, A_SCD_xxx implies
-    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
-    *  version.
-    ********************************************************************* */
-
-
-/*  *********************************************************************
-    * Memory Controller Registers (Section 6)
-    ********************************************************************* */
-
-#define A_BCM1480_MC_BASE_0                 0x0010050000
-#define A_BCM1480_MC_BASE_1                 0x0010051000
-#define A_BCM1480_MC_BASE_2                 0x0010052000
-#define A_BCM1480_MC_BASE_3                 0x0010053000
-#define BCM1480_MC_REGISTER_SPACING         0x1000
-
-#define A_BCM1480_MC_BASE(ctlid)            (A_BCM1480_MC_BASE_0+(ctlid)*BCM1480_MC_REGISTER_SPACING)
-#define A_BCM1480_MC_REGISTER(ctlid, reg)    (A_BCM1480_MC_BASE(ctlid)+(reg))
-
-#define R_BCM1480_MC_CONFIG                 0x0000000100
-#define R_BCM1480_MC_CS_START               0x0000000120
-#define R_BCM1480_MC_CS_END                 0x0000000140
-#define S_BCM1480_MC_CS_STARTEND            24
-
-#define R_BCM1480_MC_CS01_ROW0              0x0000000180
-#define R_BCM1480_MC_CS01_ROW1              0x00000001A0
-#define R_BCM1480_MC_CS23_ROW0              0x0000000200
-#define R_BCM1480_MC_CS23_ROW1              0x0000000220
-#define R_BCM1480_MC_CS01_COL0              0x0000000280
-#define R_BCM1480_MC_CS01_COL1              0x00000002A0
-#define R_BCM1480_MC_CS23_COL0              0x0000000300
-#define R_BCM1480_MC_CS23_COL1              0x0000000320
-
-#define R_BCM1480_MC_CSX_BASE               0x0000000180
-#define R_BCM1480_MC_CSX_ROW0               0x0000000000   /* relative to CSX_BASE */
-#define R_BCM1480_MC_CSX_ROW1               0x0000000020   /* relative to CSX_BASE */
-#define R_BCM1480_MC_CSX_COL0               0x0000000100   /* relative to CSX_BASE */
-#define R_BCM1480_MC_CSX_COL1               0x0000000120   /* relative to CSX_BASE */
-#define BCM1480_MC_CSX_SPACING              0x0000000080   /* CS23 relative to CS01 */
-
-#define R_BCM1480_MC_CS01_BA                0x0000000380
-#define R_BCM1480_MC_CS23_BA                0x00000003A0
-#define R_BCM1480_MC_DRAMCMD                0x0000000400
-#define R_BCM1480_MC_DRAMMODE               0x0000000420
-#define R_BCM1480_MC_CLOCK_CFG              0x0000000440
-#define R_BCM1480_MC_MCLK_CFG               R_BCM1480_MC_CLOCK_CFG
-#define R_BCM1480_MC_TEST_DATA              0x0000000480
-#define R_BCM1480_MC_TEST_ECC               0x00000004A0
-#define R_BCM1480_MC_TIMING1                0x00000004C0
-#define R_BCM1480_MC_TIMING2                0x00000004E0
-#define R_BCM1480_MC_DLL_CFG                0x0000000500
-#define R_BCM1480_MC_DRIVE_CFG              0x0000000520
-
-#if SIBYTE_HDR_FEATURE(1480, PASS2)
-#define R_BCM1480_MC_ODT                    0x0000000460
-#define R_BCM1480_MC_ECC_STATUS             0x0000000540
-#endif
-
-/* Global registers (single instance) */
-#define A_BCM1480_MC_GLB_CONFIG             0x0010054100
-#define A_BCM1480_MC_GLB_INTLV              0x0010054120
-#define A_BCM1480_MC_GLB_ECC_STATUS         0x0010054140
-#define A_BCM1480_MC_GLB_ECC_ADDR           0x0010054160
-#define A_BCM1480_MC_GLB_ECC_CORRECT        0x0010054180
-#define A_BCM1480_MC_GLB_PERF_CNT_CONTROL   0x00100541A0
-
-/*  *********************************************************************
-    * L2 Cache Control Registers (Section 5)
-    ********************************************************************* */
-
-#define A_BCM1480_L2_BASE                   0x0010040000
-
-#define A_BCM1480_L2_READ_TAG               0x0010040018
-#define A_BCM1480_L2_ECC_TAG                0x0010040038
-#define A_BCM1480_L2_MISC0_VALUE            0x0010040058
-#define A_BCM1480_L2_MISC1_VALUE            0x0010040078
-#define A_BCM1480_L2_MISC2_VALUE            0x0010040098
-#define A_BCM1480_L2_MISC_CONFIG            0x0010040040        /* x040 */
-#define A_BCM1480_L2_CACHE_DISABLE          0x0010040060        /* x060 */
-#define A_BCM1480_L2_MAKECACHEDISABLE(x)    (A_BCM1480_L2_CACHE_DISABLE | (((x)&0xF) << 12))
-#define A_BCM1480_L2_WAY_ENABLE_3_0         0x0010040080        /* x080 */
-#define A_BCM1480_L2_WAY_ENABLE_7_4         0x00100400A0        /* x0A0 */
-#define A_BCM1480_L2_MAKE_WAY_ENABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((x)&0xF) << 12))
-#define A_BCM1480_L2_MAKE_WAY_ENABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((x)&0xF) << 12))
-#define A_BCM1480_L2_MAKE_WAY_DISABLE_LO(x)  (A_BCM1480_L2_WAY_ENABLE_3_0 | (((~x)&0xF) << 12))
-#define A_BCM1480_L2_MAKE_WAY_DISABLE_HI(x)  (A_BCM1480_L2_WAY_ENABLE_7_4 | (((~x)&0xF) << 12))
-#define A_BCM1480_L2_WAY_LOCAL_3_0          0x0010040100        /* x100 */
-#define A_BCM1480_L2_WAY_LOCAL_7_4          0x0010040120        /* x120 */
-#define A_BCM1480_L2_WAY_REMOTE_3_0         0x0010040140        /* x140 */
-#define A_BCM1480_L2_WAY_REMOTE_7_4         0x0010040160        /* x160 */
-#define A_BCM1480_L2_WAY_AGENT_3_0          0x00100400C0        /* xxC0 */
-#define A_BCM1480_L2_WAY_AGENT_7_4          0x00100400E0        /* xxE0 */
-#define A_BCM1480_L2_WAY_ENABLE(A, banks)   (A | (((~(banks))&0x0F) << 8))
-#define A_BCM1480_L2_BANK_BASE              0x00D0300000
-#define A_BCM1480_L2_BANK_ADDRESS(b)        (A_BCM1480_L2_BANK_BASE | (((b)&0x7)<<17))
-#define A_BCM1480_L2_MGMT_TAG_BASE          0x00D0000000
-
-
-/*  *********************************************************************
-    * PCI-X Interface Registers (Section 7)
-    ********************************************************************* */
-
-#define A_BCM1480_PCI_BASE                  0x0010061400
-
-#define A_BCM1480_PCI_RESET                 0x0010061400
-#define A_BCM1480_PCI_DLL                   0x0010061500
-
-#define A_BCM1480_PCI_TYPE00_HEADER         0x002E000000
-
-/*  *********************************************************************
-    * Ethernet MAC Registers (Section 11) and DMA Registers (Section 10.6)
-    ********************************************************************* */
-
-/* No register changes with Rev.C BCM1250, but one additional MAC */
-
-#define A_BCM1480_MAC_BASE_2        0x0010066000
-
-#ifndef A_MAC_BASE_2
-#define A_MAC_BASE_2                A_BCM1480_MAC_BASE_2
-#endif
-
-#define A_BCM1480_MAC_BASE_3        0x0010067000
-#define A_MAC_BASE_3                A_BCM1480_MAC_BASE_3
-
-#define R_BCM1480_MAC_DMA_OODPKTLOST        0x00000038
-
-#ifndef R_MAC_DMA_OODPKTLOST
-#define R_MAC_DMA_OODPKTLOST        R_BCM1480_MAC_DMA_OODPKTLOST
-#endif
-
-
-/*  *********************************************************************
-    * DUART Registers (Section 14)
-    ********************************************************************* */
-
-/* No significant differences from BCM1250, two DUARTs */
-
-/*  Conventions, per user manual:
- *     DUART    generic, channels A,B,C,D
- *     DUART0   implementing channels A,B
- *     DUART1   inplementing channels C,D
- */
-
-#define BCM1480_DUART_NUM_PORTS           4
-
-#define A_BCM1480_DUART0                    0x0010060000
-#define A_BCM1480_DUART1                    0x0010060400
-#define A_BCM1480_DUART(chan)               ((((chan)&2) == 0)? A_BCM1480_DUART0 : A_BCM1480_DUART1)
-
-#define BCM1480_DUART_CHANREG_SPACING       0x100
-#define A_BCM1480_DUART_CHANREG(chan, reg)                              \
-        (A_BCM1480_DUART(chan) +                                        \
-         BCM1480_DUART_CHANREG_SPACING * (((chan) & 1) + 1) + (reg))
-#define A_BCM1480_DUART_CTRLREG(chan, reg)                              \
-        (A_BCM1480_DUART(chan) +                                        \
-         BCM1480_DUART_CHANREG_SPACING * 3 + (reg))
-
-#define DUART_IMRISR_SPACING        0x20
-#define DUART_INCHNG_SPACING        0x10
-
-#define R_BCM1480_DUART_IMRREG(chan)                                    \
-        (R_DUART_IMR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
-#define R_BCM1480_DUART_ISRREG(chan)                                    \
-        (R_DUART_ISR_A + ((chan) & 1) * DUART_IMRISR_SPACING)
-#define R_BCM1480_DUART_INCHREG(chan)                                   \
-        (R_DUART_IN_CHNG_A + ((chan) & 1) * DUART_INCHNG_SPACING)
-
-#define A_BCM1480_DUART_IMRREG(chan)                                    \
-        (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_IMRREG(chan)))
-#define A_BCM1480_DUART_ISRREG(chan)                                    \
-        (A_BCM1480_DUART_CTRLREG((chan), R_BCM1480_DUART_ISRREG(chan)))
-
-#define A_BCM1480_DUART_IN_PORT(chan)                                   \
-        (A_BCM1480_DUART_CTRLREG((chan), R_DUART_IN_PORT))
-
-/*
- * These constants are the absolute addresses.
- */
-
-#define A_BCM1480_DUART_MODE_REG_1_C        0x0010060400
-#define A_BCM1480_DUART_MODE_REG_2_C        0x0010060410
-#define A_BCM1480_DUART_STATUS_C            0x0010060420
-#define A_BCM1480_DUART_CLK_SEL_C           0x0010060430
-#define A_BCM1480_DUART_FULL_CTL_C          0x0010060440
-#define A_BCM1480_DUART_CMD_C               0x0010060450
-#define A_BCM1480_DUART_RX_HOLD_C           0x0010060460
-#define A_BCM1480_DUART_TX_HOLD_C           0x0010060470
-#define A_BCM1480_DUART_OPCR_C              0x0010060480
-#define A_BCM1480_DUART_AUX_CTRL_C          0x0010060490
-
-#define A_BCM1480_DUART_MODE_REG_1_D        0x0010060500
-#define A_BCM1480_DUART_MODE_REG_2_D        0x0010060510
-#define A_BCM1480_DUART_STATUS_D            0x0010060520
-#define A_BCM1480_DUART_CLK_SEL_D           0x0010060530
-#define A_BCM1480_DUART_FULL_CTL_D          0x0010060540
-#define A_BCM1480_DUART_CMD_D               0x0010060550
-#define A_BCM1480_DUART_RX_HOLD_D           0x0010060560
-#define A_BCM1480_DUART_TX_HOLD_D           0x0010060570
-#define A_BCM1480_DUART_OPCR_D              0x0010060580
-#define A_BCM1480_DUART_AUX_CTRL_D          0x0010060590
-
-#define A_BCM1480_DUART_INPORT_CHNG_CD      0x0010060600
-#define A_BCM1480_DUART_AUX_CTRL_CD         0x0010060610
-#define A_BCM1480_DUART_ISR_C               0x0010060620
-#define A_BCM1480_DUART_IMR_C               0x0010060630
-#define A_BCM1480_DUART_ISR_D               0x0010060640
-#define A_BCM1480_DUART_IMR_D               0x0010060650
-#define A_BCM1480_DUART_OUT_PORT_CD         0x0010060660
-#define A_BCM1480_DUART_OPCR_CD             0x0010060670
-#define A_BCM1480_DUART_IN_PORT_CD          0x0010060680
-#define A_BCM1480_DUART_ISR_CD              0x0010060690
-#define A_BCM1480_DUART_IMR_CD              0x00100606A0
-#define A_BCM1480_DUART_SET_OPR_CD          0x00100606B0
-#define A_BCM1480_DUART_CLEAR_OPR_CD        0x00100606C0
-#define A_BCM1480_DUART_INPORT_CHNG_C       0x00100606D0
-#define A_BCM1480_DUART_INPORT_CHNG_D       0x00100606E0
-
-
-/*  *********************************************************************
-    * Generic Bus Registers (Section 15) and PCMCIA Registers (Section 16)
-    ********************************************************************* */
-
-#define A_BCM1480_IO_PCMCIA_CFG_B       0x0010061A58
-#define A_BCM1480_IO_PCMCIA_STATUS_B    0x0010061A68
-
-/*  *********************************************************************
-    * GPIO Registers (Section 17)
-    ********************************************************************* */
-
-/* One additional GPIO register, placed _before_ the BCM1250's GPIO block base */
-
-#define A_BCM1480_GPIO_INT_ADD_TYPE         0x0010061A78
-#define R_BCM1480_GPIO_INT_ADD_TYPE         (-8)
-
-#define A_GPIO_INT_ADD_TYPE     A_BCM1480_GPIO_INT_ADD_TYPE
-#define R_GPIO_INT_ADD_TYPE     R_BCM1480_GPIO_INT_ADD_TYPE
-
-/*  *********************************************************************
-    * SMBus Registers (Section 18)
-    ********************************************************************* */
-
-/* No changes from BCM1250 */
-
-/*  *********************************************************************
-    * Timer Registers (Sections 4.6)
-    ********************************************************************* */
-
-/* BCM1480 has two additional watchdogs */
-
-/* Watchdog timers */
-
-#define A_BCM1480_SCD_WDOG_2                0x0010022050
-#define A_BCM1480_SCD_WDOG_3                0x0010022150
-
-#define BCM1480_SCD_NUM_WDOGS               4
-
-#define A_BCM1480_SCD_WDOG_BASE(w)       (A_BCM1480_SCD_WDOG_0+((w)&2)*0x1000 + ((w)&1)*0x100)
-#define A_BCM1480_SCD_WDOG_REGISTER(w, r) (A_BCM1480_SCD_WDOG_BASE(w) + (r))
-
-#define A_BCM1480_SCD_WDOG_INIT_2       0x0010022050
-#define A_BCM1480_SCD_WDOG_CNT_2        0x0010022058
-#define A_BCM1480_SCD_WDOG_CFG_2        0x0010022060
-
-#define A_BCM1480_SCD_WDOG_INIT_3       0x0010022150
-#define A_BCM1480_SCD_WDOG_CNT_3        0x0010022158
-#define A_BCM1480_SCD_WDOG_CFG_3        0x0010022160
-
-/* BCM1480 has two additional compare registers */
-
-#define A_BCM1480_SCD_ZBBUS_CYCLE_COUNT         A_SCD_ZBBUS_CYCLE_COUNT
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP_BASE       0x0010020C00
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP0           A_SCD_ZBBUS_CYCLE_CP0
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP1           A_SCD_ZBBUS_CYCLE_CP1
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP2           0x0010020C10
-#define A_BCM1480_SCD_ZBBUS_CYCLE_CP3           0x0010020C18
-
-/*  *********************************************************************
-    * System Control Registers (Section 4.2)
-    ********************************************************************* */
-
-/* Scratch register in different place */
-
-#define A_BCM1480_SCD_SCRATCH           0x100200A0
-
-/*  *********************************************************************
-    * System Address Trap Registers (Section 4.9)
-    ********************************************************************* */
-
-/* No changes from BCM1250 */
-
-/*  *********************************************************************
-    * System Interrupt Mapper Registers (Sections 4.3-4.5)
-    ********************************************************************* */
-
-#define A_BCM1480_IMR_CPU0_BASE             0x0010020000
-#define A_BCM1480_IMR_CPU1_BASE             0x0010022000
-#define A_BCM1480_IMR_CPU2_BASE             0x0010024000
-#define A_BCM1480_IMR_CPU3_BASE             0x0010026000
-#define BCM1480_IMR_REGISTER_SPACING        0x2000
-#define BCM1480_IMR_REGISTER_SPACING_SHIFT  13
-
-#define A_BCM1480_IMR_MAPPER(cpu)       (A_BCM1480_IMR_CPU0_BASE+(cpu)*BCM1480_IMR_REGISTER_SPACING)
-#define A_BCM1480_IMR_REGISTER(cpu, reg) (A_BCM1480_IMR_MAPPER(cpu)+(reg))
-
-/* Most IMR registers are 128 bits, implemented as non-contiguous
-   64-bit registers high (_H) and low (_L) */
-#define BCM1480_IMR_HL_SPACING                  0x1000
-
-#define R_BCM1480_IMR_INTERRUPT_DIAG_H          0x0010
-#define R_BCM1480_IMR_LDT_INTERRUPT_H           0x0018
-#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_H       0x0020
-#define R_BCM1480_IMR_INTERRUPT_MASK_H          0x0028
-#define R_BCM1480_IMR_INTERRUPT_TRACE_H         0x0038
-#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_H 0x0040
-#define R_BCM1480_IMR_LDT_INTERRUPT_SET         0x0048
-#define R_BCM1480_IMR_MAILBOX_0_CPU             0x00C0
-#define R_BCM1480_IMR_MAILBOX_0_SET_CPU         0x00C8
-#define R_BCM1480_IMR_MAILBOX_0_CLR_CPU         0x00D0
-#define R_BCM1480_IMR_MAILBOX_1_CPU             0x00E0
-#define R_BCM1480_IMR_MAILBOX_1_SET_CPU         0x00E8
-#define R_BCM1480_IMR_MAILBOX_1_CLR_CPU         0x00F0
-#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_H   0x0100
-#define BCM1480_IMR_INTERRUPT_STATUS_COUNT      8
-#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_H      0x0200
-#define BCM1480_IMR_INTERRUPT_MAP_COUNT         64
-
-#define R_BCM1480_IMR_INTERRUPT_DIAG_L          0x1010
-#define R_BCM1480_IMR_LDT_INTERRUPT_L           0x1018
-#define R_BCM1480_IMR_LDT_INTERRUPT_CLR_L       0x1020
-#define R_BCM1480_IMR_INTERRUPT_MASK_L          0x1028
-#define R_BCM1480_IMR_INTERRUPT_TRACE_L         0x1038
-#define R_BCM1480_IMR_INTERRUPT_SOURCE_STATUS_L 0x1040
-#define R_BCM1480_IMR_INTERRUPT_STATUS_BASE_L   0x1100
-#define R_BCM1480_IMR_INTERRUPT_MAP_BASE_L      0x1200
-
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE   0x0010028000
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU1_BASE   0x0010028100
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU2_BASE   0x0010028200
-#define A_BCM1480_IMR_ALIAS_MAILBOX_CPU3_BASE   0x0010028300
-#define BCM1480_IMR_ALIAS_MAILBOX_SPACING       0100
-
-#define A_BCM1480_IMR_ALIAS_MAILBOX(cpu)     (A_BCM1480_IMR_ALIAS_MAILBOX_CPU0_BASE + \
-                                        (cpu)*BCM1480_IMR_ALIAS_MAILBOX_SPACING)
-#define A_BCM1480_IMR_ALIAS_MAILBOX_REGISTER(cpu, reg) (A_BCM1480_IMR_ALIAS_MAILBOX(cpu)+(reg))
-
-#define R_BCM1480_IMR_ALIAS_MAILBOX_0           0x0000          /* 0x0x0 */
-#define R_BCM1480_IMR_ALIAS_MAILBOX_0_SET       0x0008          /* 0x0x8 */
-
-/*
- * these macros work together to build the address of a mailbox
- * register, e.g., A_BCM1480_MAILBOX_REGISTER(0,R_BCM1480_IMR_MAILBOX_SET,2)
- * for mbox_0_set_cpu2 returns 0x00100240C8
- */
-#define R_BCM1480_IMR_MAILBOX_CPU         0x00
-#define R_BCM1480_IMR_MAILBOX_SET         0x08
-#define R_BCM1480_IMR_MAILBOX_CLR         0x10
-#define R_BCM1480_IMR_MAILBOX_NUM_SPACING 0x20
-#define A_BCM1480_MAILBOX_REGISTER(num, reg, cpu) \
-    (A_BCM1480_IMR_CPU0_BASE + \
-     (num * R_BCM1480_IMR_MAILBOX_NUM_SPACING) + \
-     (cpu * BCM1480_IMR_REGISTER_SPACING) + \
-     (R_BCM1480_IMR_MAILBOX_0_CPU + reg))
-
-/*  *********************************************************************
-    * System Performance Counter Registers (Section 4.7)
-    ********************************************************************* */
-
-/* BCM1480 has four more performance counter registers, and two control
-   registers. */
-
-#define A_BCM1480_SCD_PERF_CNT_BASE         0x00100204C0
-
-#define A_BCM1480_SCD_PERF_CNT_CFG0         0x00100204C0
-#define A_BCM1480_SCD_PERF_CNT_CFG_0        A_BCM1480_SCD_PERF_CNT_CFG0
-#define A_BCM1480_SCD_PERF_CNT_CFG1         0x00100204C8
-#define A_BCM1480_SCD_PERF_CNT_CFG_1        A_BCM1480_SCD_PERF_CNT_CFG1
-
-#define A_BCM1480_SCD_PERF_CNT_0            A_SCD_PERF_CNT_0
-#define A_BCM1480_SCD_PERF_CNT_1            A_SCD_PERF_CNT_1
-#define A_BCM1480_SCD_PERF_CNT_2            A_SCD_PERF_CNT_2
-#define A_BCM1480_SCD_PERF_CNT_3            A_SCD_PERF_CNT_3
-
-#define A_BCM1480_SCD_PERF_CNT_4            0x00100204F0
-#define A_BCM1480_SCD_PERF_CNT_5            0x00100204F8
-#define A_BCM1480_SCD_PERF_CNT_6            0x0010020500
-#define A_BCM1480_SCD_PERF_CNT_7            0x0010020508
-
-#define BCM1480_SCD_NUM_PERF_CNT 8
-#define BCM1480_SCD_PERF_CNT_SPACING 8
-#define A_BCM1480_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*BCM1480_SCD_PERF_CNT_SPACING))
-
-/*  *********************************************************************
-    * System Bus Watcher Registers (Section 4.8)
-    ********************************************************************* */
-
-
-/* Same as 1250 except BUS_ERR_STATUS_DEBUG is in a different place. */
-
-#define A_BCM1480_BUS_ERR_STATUS_DEBUG      0x00100208D8
-
-/*  *********************************************************************
-    * System Debug Controller Registers (Section 19)
-    ********************************************************************* */
-
-/* Same as 1250 */
-
-/*  *********************************************************************
-    * System Trace Unit Registers (Sections 4.10)
-    ********************************************************************* */
-
-/* Same as 1250 */
-
-/*  *********************************************************************
-    * Data Mover DMA Registers (Section 10.7)
-    ********************************************************************* */
-
-/* Same as 1250 */
-
-
-/*  *********************************************************************
-    * HyperTransport Interface Registers (Section 8)
-    ********************************************************************* */
-
-#define BCM1480_HT_NUM_PORTS               3
-#define BCM1480_HT_PORT_SPACING            0x800
-#define A_BCM1480_HT_PORT_HEADER(x)        (A_BCM1480_HT_PORT0_HEADER + ((x)*BCM1480_HT_PORT_SPACING))
-
-#define A_BCM1480_HT_PORT0_HEADER          0x00FE000000
-#define A_BCM1480_HT_PORT1_HEADER          0x00FE000800
-#define A_BCM1480_HT_PORT2_HEADER          0x00FE001000
-#define A_BCM1480_HT_TYPE00_HEADER         0x00FE002000
-
-
-/*  *********************************************************************
-    * Node Controller Registers (Section 9)
-    ********************************************************************* */
-
-#define A_BCM1480_NC_BASE                   0x00DFBD0000
-
-#define A_BCM1480_NC_RLD_FIELD              0x00DFBD0000
-#define A_BCM1480_NC_RLD_TRIGGER            0x00DFBD0020
-#define A_BCM1480_NC_RLD_BAD_ERROR          0x00DFBD0040
-#define A_BCM1480_NC_RLD_COR_ERROR          0x00DFBD0060
-#define A_BCM1480_NC_RLD_ECC_STATUS         0x00DFBD0080
-#define A_BCM1480_NC_RLD_WAY_ENABLE         0x00DFBD00A0
-#define A_BCM1480_NC_RLD_RANDOM_LFSR        0x00DFBD00C0
-
-#define A_BCM1480_NC_INTERRUPT_STATUS       0x00DFBD00E0
-#define A_BCM1480_NC_INTERRUPT_ENABLE       0x00DFBD0100
-#define A_BCM1480_NC_TIMEOUT_COUNTER        0x00DFBD0120
-#define A_BCM1480_NC_TIMEOUT_COUNTER_SEL    0x00DFBD0140
-
-#define A_BCM1480_NC_CREDIT_STATUS_REG0     0x00DFBD0200
-#define A_BCM1480_NC_CREDIT_STATUS_REG1     0x00DFBD0220
-#define A_BCM1480_NC_CREDIT_STATUS_REG2     0x00DFBD0240
-#define A_BCM1480_NC_CREDIT_STATUS_REG3     0x00DFBD0260
-#define A_BCM1480_NC_CREDIT_STATUS_REG4     0x00DFBD0280
-#define A_BCM1480_NC_CREDIT_STATUS_REG5     0x00DFBD02A0
-#define A_BCM1480_NC_CREDIT_STATUS_REG6     0x00DFBD02C0
-#define A_BCM1480_NC_CREDIT_STATUS_REG7     0x00DFBD02E0
-#define A_BCM1480_NC_CREDIT_STATUS_REG8     0x00DFBD0300
-#define A_BCM1480_NC_CREDIT_STATUS_REG9     0x00DFBD0320
-#define A_BCM1480_NC_CREDIT_STATUS_REG10    0x00DFBE0000
-#define A_BCM1480_NC_CREDIT_STATUS_REG11    0x00DFBE0020
-#define A_BCM1480_NC_CREDIT_STATUS_REG12    0x00DFBE0040
-
-#define A_BCM1480_NC_SR_TIMEOUT_COUNTER     0x00DFBE0060
-#define A_BCM1480_NC_SR_TIMEOUT_COUNTER_SEL 0x00DFBE0080
-
-
-/*  *********************************************************************
-    * H&R Block Configuration Registers (Section 12.4)
-    ********************************************************************* */
-
-#define A_BCM1480_HR_BASE_0                 0x00DF820000
-#define A_BCM1480_HR_BASE_1                 0x00DF8A0000
-#define A_BCM1480_HR_BASE_2                 0x00DF920000
-#define BCM1480_HR_REGISTER_SPACING         0x80000
-
-#define A_BCM1480_HR_BASE(idx)              (A_BCM1480_HR_BASE_0 + ((idx)*BCM1480_HR_REGISTER_SPACING))
-#define A_BCM1480_HR_REGISTER(idx, reg)      (A_BCM1480_HR_BASE(idx) + (reg))
-
-#define R_BCM1480_HR_CFG                    0x0000000000
-
-#define R_BCM1480_HR_MAPPING                0x0000010010
-
-#define BCM1480_HR_RULE_SPACING             0x0000000010
-#define BCM1480_HR_NUM_RULES                16
-#define BCM1480_HR_OP_OFFSET                0x0000000100
-#define BCM1480_HR_TYPE_OFFSET              0x0000000108
-#define R_BCM1480_HR_RULE_OP(idx)           (BCM1480_HR_OP_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
-#define R_BCM1480_HR_RULE_TYPE(idx)         (BCM1480_HR_TYPE_OFFSET + ((idx)*BCM1480_HR_RULE_SPACING))
-
-#define BCM1480_HR_LEAF_SPACING             0x0000000010
-#define BCM1480_HR_NUM_LEAVES               10
-#define BCM1480_HR_LEAF_OFFSET              0x0000000300
-#define R_BCM1480_HR_HA_LEAF0(idx)          (BCM1480_HR_LEAF_OFFSET + ((idx)*BCM1480_HR_LEAF_SPACING))
-
-#define R_BCM1480_HR_EX_LEAF0               0x00000003A0
-
-#define BCM1480_HR_PATH_SPACING             0x0000000010
-#define BCM1480_HR_NUM_PATHS                16
-#define BCM1480_HR_PATH_OFFSET              0x0000000600
-#define R_BCM1480_HR_PATH(idx)              (BCM1480_HR_PATH_OFFSET + ((idx)*BCM1480_HR_PATH_SPACING))
-
-#define R_BCM1480_HR_PATH_DEFAULT           0x0000000700
-
-#define BCM1480_HR_ROUTE_SPACING            8
-#define BCM1480_HR_NUM_ROUTES               512
-#define BCM1480_HR_ROUTE_OFFSET             0x0000001000
-#define R_BCM1480_HR_RT_WORD(idx)           (BCM1480_HR_ROUTE_OFFSET + ((idx)*BCM1480_HR_ROUTE_SPACING))
-
-
-/* checked to here - ehs */
-/*  *********************************************************************
-    * Packet Manager DMA Registers (Section 12.5)
-    ********************************************************************* */
-
-#define A_BCM1480_PM_BASE                   0x0010056000
-
-#define A_BCM1480_PMI_LCL_0                 0x0010058000
-#define A_BCM1480_PMO_LCL_0                 0x001005C000
-#define A_BCM1480_PMI_OFFSET_0              (A_BCM1480_PMI_LCL_0 - A_BCM1480_PM_BASE)
-#define A_BCM1480_PMO_OFFSET_0              (A_BCM1480_PMO_LCL_0 - A_BCM1480_PM_BASE)
-
-#define BCM1480_PM_LCL_REGISTER_SPACING     0x100
-#define BCM1480_PM_NUM_CHANNELS             32
-
-#define A_BCM1480_PMI_LCL_BASE(idx)             (A_BCM1480_PMI_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
-#define A_BCM1480_PMI_LCL_REGISTER(idx, reg)     (A_BCM1480_PMI_LCL_BASE(idx) + (reg))
-#define A_BCM1480_PMO_LCL_BASE(idx)             (A_BCM1480_PMO_LCL_0 + ((idx)*BCM1480_PM_LCL_REGISTER_SPACING))
-#define A_BCM1480_PMO_LCL_REGISTER(idx, reg)     (A_BCM1480_PMO_LCL_BASE(idx) + (reg))
-
-#define BCM1480_PM_INT_PACKING              8
-#define BCM1480_PM_INT_FUNCTION_SPACING     0x40
-#define BCM1480_PM_INT_NUM_FUNCTIONS        3
-
-/*
- * DMA channel registers relative to A_BCM1480_PMI_LCL_BASE(n) and A_BCM1480_PMO_LCL_BASE(n)
- */
-
-#define R_BCM1480_PM_BASE_SIZE              0x0000000000
-#define R_BCM1480_PM_CNT                    0x0000000008
-#define R_BCM1480_PM_PFCNT                  0x0000000010
-#define R_BCM1480_PM_LAST                   0x0000000018
-#define R_BCM1480_PM_PFINDX                 0x0000000020
-#define R_BCM1480_PM_INT_WMK                0x0000000028
-#define R_BCM1480_PM_CONFIG0                0x0000000030
-#define R_BCM1480_PM_LOCALDEBUG             0x0000000078
-#define R_BCM1480_PM_CACHEABILITY           0x0000000080   /* PMI only */
-#define R_BCM1480_PM_INT_CNFG               0x0000000088
-#define R_BCM1480_PM_DESC_MERGE_TIMER       0x0000000090
-#define R_BCM1480_PM_LOCALDEBUG_PIB         0x00000000F8   /* PMI only */
-#define R_BCM1480_PM_LOCALDEBUG_POB         0x00000000F8   /* PMO only */
-
-/*
- * Global Registers (Not Channelized)
- */
-
-#define A_BCM1480_PMI_GLB_0                 0x0010056000
-#define A_BCM1480_PMO_GLB_0                 0x0010057000
-
-/*
- * PM to TX Mapping Register relative to A_BCM1480_PMI_GLB_0 and A_BCM1480_PMO_GLB_0
- */
-
-#define R_BCM1480_PM_PMO_MAPPING            0x00000008C8   /* PMO only */
-
-#define A_BCM1480_PM_PMO_MAPPING        (A_BCM1480_PMO_GLB_0 + R_BCM1480_PM_PMO_MAPPING)
-
-/*
- * Interrupt mapping registers
- */
-
-
-#define A_BCM1480_PMI_INT_0                 0x0010056800
-#define A_BCM1480_PMI_INT(q)                (A_BCM1480_PMI_INT_0 + ((q>>8)<<8))
-#define A_BCM1480_PMI_INT_OFFSET_0          (A_BCM1480_PMI_INT_0 - A_BCM1480_PM_BASE)
-#define A_BCM1480_PMO_INT_0                 0x0010057800
-#define A_BCM1480_PMO_INT(q)                (A_BCM1480_PMO_INT_0 + ((q>>8)<<8))
-#define A_BCM1480_PMO_INT_OFFSET_0          (A_BCM1480_PMO_INT_0 - A_BCM1480_PM_BASE)
-
-/*
- * Interrupt registers relative to A_BCM1480_PMI_INT_0 and A_BCM1480_PMO_INT_0
- */
-
-#define R_BCM1480_PM_INT_ST                 0x0000000000
-#define R_BCM1480_PM_INT_MSK                0x0000000040
-#define R_BCM1480_PM_INT_CLR                0x0000000080
-#define R_BCM1480_PM_MRGD_INT               0x00000000C0
-
-/*
- * Debug registers (global)
- */
-
-#define A_BCM1480_PM_GLOBALDEBUGMODE_PMI    0x0010056000
-#define A_BCM1480_PM_GLOBALDEBUG_PID        0x00100567F8
-#define A_BCM1480_PM_GLOBALDEBUG_PIB        0x0010056FF8
-#define A_BCM1480_PM_GLOBALDEBUGMODE_PMO    0x0010057000
-#define A_BCM1480_PM_GLOBALDEBUG_POD        0x00100577F8
-#define A_BCM1480_PM_GLOBALDEBUG_POB        0x0010057FF8
-
-/*  *********************************************************************
-    *  Switch performance counters
-    ********************************************************************* */
-
-#define A_BCM1480_SWPERF_CFG    0xdfb91800
-#define A_BCM1480_SWPERF_CNT0   0xdfb91880
-#define A_BCM1480_SWPERF_CNT1   0xdfb91888
-#define A_BCM1480_SWPERF_CNT2   0xdfb91890
-#define A_BCM1480_SWPERF_CNT3   0xdfb91898
-
-
-/*  *********************************************************************
-    *  Switch Trace Unit
-    ********************************************************************* */
-
-#define A_BCM1480_SWTRC_MATCH_CONTROL_0         0xDFB91000
-#define A_BCM1480_SWTRC_MATCH_DATA_VALUE_0      0xDFB91100
-#define A_BCM1480_SWTRC_MATCH_DATA_MASK_0       0xDFB91108
-#define A_BCM1480_SWTRC_MATCH_TAG_VALUE_0       0xDFB91200
-#define A_BCM1480_SWTRC_MATCH_TAG_MAKS_0        0xDFB91208
-#define A_BCM1480_SWTRC_EVENT_0                 0xDFB91300
-#define A_BCM1480_SWTRC_SEQUENCE_0              0xDFB91400
-
-#define A_BCM1480_SWTRC_CFG                     0xDFB91500
-#define A_BCM1480_SWTRC_READ                    0xDFB91508
-
-#define A_BCM1480_SWDEBUG_SCHEDSTOP             0xDFB92000
-
-#define A_BCM1480_SWTRC_MATCH_CONTROL(x) (A_BCM1480_SWTRC_MATCH_CONTROL_0 + ((x)*8))
-#define A_BCM1480_SWTRC_EVENT(x) (A_BCM1480_SWTRC_EVENT_0 + ((x)*8))
-#define A_BCM1480_SWTRC_SEQUENCE(x) (A_BCM1480_SWTRC_SEQUENCE_0 + ((x)*8))
-
-#define A_BCM1480_SWTRC_MATCH_DATA_VALUE(x) (A_BCM1480_SWTRC_MATCH_DATA_VALUE_0 + ((x)*16))
-#define A_BCM1480_SWTRC_MATCH_DATA_MASK(x) (A_BCM1480_SWTRC_MATCH_DATA_MASK_0 + ((x)*16))
-#define A_BCM1480_SWTRC_MATCH_TAG_VALUE(x) (A_BCM1480_SWTRC_MATCH_TAG_VALUE_0 + ((x)*16))
-#define A_BCM1480_SWTRC_MATCH_TAG_MASK(x) (A_BCM1480_SWTRC_MATCH_TAG_MASK_0 + ((x)*16))
-
-
-
-/*  *********************************************************************
-    *  High-Speed Port Registers (Section 13)
-    ********************************************************************* */
-
-#define A_BCM1480_HSP_BASE_0                0x00DF810000
-#define A_BCM1480_HSP_BASE_1                0x00DF890000
-#define A_BCM1480_HSP_BASE_2                0x00DF910000
-#define BCM1480_HSP_REGISTER_SPACING        0x80000
-
-#define A_BCM1480_HSP_BASE(idx)             (A_BCM1480_HSP_BASE_0 + ((idx)*BCM1480_HSP_REGISTER_SPACING))
-#define A_BCM1480_HSP_REGISTER(idx, reg)     (A_BCM1480_HSP_BASE(idx) + (reg))
-
-#define R_BCM1480_HSP_RX_SPI4_CFG_0           0x0000000000
-#define R_BCM1480_HSP_RX_SPI4_CFG_1           0x0000000008
-#define R_BCM1480_HSP_RX_SPI4_DESKEW_OVERRIDE 0x0000000010
-#define R_BCM1480_HSP_RX_SPI4_DESKEW_DATAPATH 0x0000000018
-#define R_BCM1480_HSP_RX_SPI4_PORT_INT_EN     0x0000000020
-#define R_BCM1480_HSP_RX_SPI4_PORT_INT_STATUS 0x0000000028
-
-#define R_BCM1480_HSP_RX_SPI4_CALENDAR_0      0x0000000200
-#define R_BCM1480_HSP_RX_SPI4_CALENDAR_1      0x0000000208
-
-#define R_BCM1480_HSP_RX_PLL_CNFG             0x0000000800
-#define R_BCM1480_HSP_RX_CALIBRATION          0x0000000808
-#define R_BCM1480_HSP_RX_TEST                 0x0000000810
-#define R_BCM1480_HSP_RX_DIAG_DETAILS         0x0000000818
-#define R_BCM1480_HSP_RX_DIAG_CRC_0           0x0000000820
-#define R_BCM1480_HSP_RX_DIAG_CRC_1           0x0000000828
-#define R_BCM1480_HSP_RX_DIAG_HTCMD           0x0000000830
-#define R_BCM1480_HSP_RX_DIAG_PKTCTL          0x0000000838
-
-#define R_BCM1480_HSP_RX_VIS_FLCTRL_COUNTER   0x0000000870
-
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_0       0x0000020020
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_1       0x0000020028
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_2       0x0000020030
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_3       0x0000020038
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_4       0x0000020040
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_5       0x0000020048
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_6       0x0000020050
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC_7       0x0000020058
-#define R_BCM1480_HSP_RX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_RX_PKT_RAMALLOC_0 + 8*(idx))
-
-/* XXX Following registers were shuffled.  Renamed/renumbered per errata. */
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_0      0x0000020078
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_1      0x0000020080
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_2      0x0000020088
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_3      0x0000020090
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_4      0x0000020098
-#define R_BCM1480_HSP_RX_HT_RAMALLOC_5      0x00000200A0
-
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_0      0x00000200B0
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_1      0x00000200B8
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_2      0x00000200C0
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_3      0x00000200C8
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_4      0x00000200D0
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_5      0x00000200D8
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_6      0x00000200E0
-#define R_BCM1480_HSP_RX_SPI_WATERMARK_7      0x00000200E8
-#define R_BCM1480_HSP_RX_SPI_WATERMARK(idx)   (R_BCM1480_HSP_RX_SPI_WATERMARK_0 + 8*(idx))
-
-#define R_BCM1480_HSP_RX_VIS_CMDQ_0           0x00000200F0
-#define R_BCM1480_HSP_RX_VIS_CMDQ_1           0x00000200F8
-#define R_BCM1480_HSP_RX_VIS_CMDQ_2           0x0000020100
-#define R_BCM1480_HSP_RX_RAM_READCTL          0x0000020108
-#define R_BCM1480_HSP_RX_RAM_READWINDOW       0x0000020110
-#define R_BCM1480_HSP_RX_RF_READCTL           0x0000020118
-#define R_BCM1480_HSP_RX_RF_READWINDOW        0x0000020120
-
-#define R_BCM1480_HSP_TX_SPI4_CFG_0           0x0000040000
-#define R_BCM1480_HSP_TX_SPI4_CFG_1           0x0000040008
-#define R_BCM1480_HSP_TX_SPI4_TRAINING_FMT    0x0000040010
-
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_0       0x0000040020
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_1       0x0000040028
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_2       0x0000040030
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_3       0x0000040038
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_4       0x0000040040
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_5       0x0000040048
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_6       0x0000040050
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC_7       0x0000040058
-#define R_BCM1480_HSP_TX_PKT_RAMALLOC(idx)    (R_BCM1480_HSP_TX_PKT_RAMALLOC_0 + 8*(idx))
-#define R_BCM1480_HSP_TX_NPC_RAMALLOC         0x0000040078
-#define R_BCM1480_HSP_TX_RSP_RAMALLOC         0x0000040080
-#define R_BCM1480_HSP_TX_PC_RAMALLOC          0x0000040088
-#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_0      0x0000040090
-#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_1      0x0000040098
-#define R_BCM1480_HSP_TX_HTCC_RAMALLOC_2      0x00000400A0
-
-#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_0      0x00000400B0
-#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_1      0x00000400B8
-#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_2      0x00000400C0
-#define R_BCM1480_HSP_TX_PKT_RXPHITCNT_3      0x00000400C8
-#define R_BCM1480_HSP_TX_PKT_RXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_RXPHITCNT_0 + 8*(idx))
-#define R_BCM1480_HSP_TX_HTIO_RXPHITCNT       0x00000400D0
-#define R_BCM1480_HSP_TX_HTCC_RXPHITCNT       0x00000400D8
-
-#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_0      0x00000400E0
-#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_1      0x00000400E8
-#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_2      0x00000400F0
-#define R_BCM1480_HSP_TX_PKT_TXPHITCNT_3      0x00000400F8
-#define R_BCM1480_HSP_TX_PKT_TXPHITCNT(idx)   (R_BCM1480_HSP_TX_PKT_TXPHITCNT_0 + 8*(idx))
-#define R_BCM1480_HSP_TX_HTIO_TXPHITCNT       0x0000040100
-#define R_BCM1480_HSP_TX_HTCC_TXPHITCNT       0x0000040108
-
-#define R_BCM1480_HSP_TX_SPI4_CALENDAR_0      0x0000040200
-#define R_BCM1480_HSP_TX_SPI4_CALENDAR_1      0x0000040208
-
-#define R_BCM1480_HSP_TX_PLL_CNFG             0x0000040800
-#define R_BCM1480_HSP_TX_CALIBRATION          0x0000040808
-#define R_BCM1480_HSP_TX_TEST                 0x0000040810
-
-#define R_BCM1480_HSP_TX_VIS_CMDQ_0           0x0000040840
-#define R_BCM1480_HSP_TX_VIS_CMDQ_1           0x0000040848
-#define R_BCM1480_HSP_TX_VIS_CMDQ_2           0x0000040850
-#define R_BCM1480_HSP_TX_RAM_READCTL          0x0000040860
-#define R_BCM1480_HSP_TX_RAM_READWINDOW       0x0000040868
-#define R_BCM1480_HSP_TX_RF_READCTL           0x0000040870
-#define R_BCM1480_HSP_TX_RF_READWINDOW        0x0000040878
-
-#define R_BCM1480_HSP_TX_SPI4_PORT_INT_STATUS 0x0000040880
-#define R_BCM1480_HSP_TX_SPI4_PORT_INT_EN     0x0000040888
-
-#define R_BCM1480_HSP_TX_NEXT_ADDR_BASE 0x000040400
-#define R_BCM1480_HSP_TX_NEXT_ADDR_REGISTER(x)  (R_BCM1480_HSP_TX_NEXT_ADDR_BASE+ 8*(x))
-
-
-
-/*  *********************************************************************
-    *  Physical Address Map (Table 10 and Figure 7)
-    ********************************************************************* */
-
-#define A_BCM1480_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
-#define A_BCM1480_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
-#define A_BCM1480_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
-#define A_BCM1480_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
-#define A_BCM1480_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
-#define A_BCM1480_PHYS_GENBUS_END               _SB_MAKE64(0x0028000000)
-#define A_BCM1480_PHYS_PCI_MISC_MATCH_BYTES     _SB_MAKE64(0x0028000000)
-#define A_BCM1480_PHYS_PCI_IACK_MATCH_BYTES     _SB_MAKE64(0x0029000000)
-#define A_BCM1480_PHYS_PCI_IO_MATCH_BYTES       _SB_MAKE64(0x002C000000)
-#define A_BCM1480_PHYS_PCI_CFG_MATCH_BYTES      _SB_MAKE64(0x002E000000)
-#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BYTES     _SB_MAKE64(0x002F000000)
-#define A_BCM1480_PHYS_PCI_MEM_MATCH_BYTES      _SB_MAKE64(0x0030000000)
-#define A_BCM1480_PHYS_HT_MEM_MATCH_BYTES       _SB_MAKE64(0x0040000000)
-#define A_BCM1480_PHYS_HT_MEM_MATCH_BITS        _SB_MAKE64(0x0060000000)
-#define A_BCM1480_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
-#define A_BCM1480_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
-#define A_BCM1480_PHYS_PCI_MISC_MATCH_BITS      _SB_MAKE64(0x00A8000000)
-#define A_BCM1480_PHYS_PCI_IACK_MATCH_BITS      _SB_MAKE64(0x00A9000000)
-#define A_BCM1480_PHYS_PCI_IO_MATCH_BITS        _SB_MAKE64(0x00AC000000)
-#define A_BCM1480_PHYS_PCI_CFG_MATCH_BITS       _SB_MAKE64(0x00AE000000)
-#define A_BCM1480_PHYS_PCI_OMAP_MATCH_BITS      _SB_MAKE64(0x00AF000000)
-#define A_BCM1480_PHYS_PCI_MEM_MATCH_BITS       _SB_MAKE64(0x00B0000000)
-#define A_BCM1480_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
-#define A_BCM1480_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
-#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BYTES   _SB_MAKE64(0x00D8000000)
-#define A_BCM1480_PHYS_HT_IO_MATCH_BYTES        _SB_MAKE64(0x00DC000000)
-#define A_BCM1480_PHYS_HT_CFG_MATCH_BYTES       _SB_MAKE64(0x00DE000000)
-#define A_BCM1480_PHYS_HS_SUBSYS                _SB_MAKE64(0x00DF000000)
-#define A_BCM1480_PHYS_HT_SPECIAL_MATCH_BITS    _SB_MAKE64(0x00F8000000)
-#define A_BCM1480_PHYS_HT_IO_MATCH_BITS         _SB_MAKE64(0x00FC000000)
-#define A_BCM1480_PHYS_HT_CFG_MATCH_BITS        _SB_MAKE64(0x00FE000000)
-#define A_BCM1480_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
-#define A_BCM1480_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
-#define A_BCM1480_PHYS_PCI_UPPER                _SB_MAKE64(0x1000000000)
-#define A_BCM1480_PHYS_HT_UPPER_MATCH_BYTES     _SB_MAKE64(0x2000000000)
-#define A_BCM1480_PHYS_HT_UPPER_MATCH_BITS      _SB_MAKE64(0x3000000000)
-#define A_BCM1480_PHYS_HT_NODE_ALIAS            _SB_MAKE64(0x4000000000)
-#define A_BCM1480_PHYS_HT_FULLACCESS            _SB_MAKE64(0xF000000000)
-
-
-/*  *********************************************************************
-    *  L2 Cache as RAM (Table 54)
-    ********************************************************************* */
-
-#define A_BCM1480_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
-#define BCM1480_PHYS_L2CACHE_NUM_WAYS           8
-#define A_BCM1480_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000100000)
-#define A_BCM1480_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0300000)
-#define A_BCM1480_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D0320000)
-#define A_BCM1480_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D0340000)
-#define A_BCM1480_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D0360000)
-#define A_BCM1480_PHYS_L2CACHE_WAY4             _SB_MAKE64(0x00D0380000)
-#define A_BCM1480_PHYS_L2CACHE_WAY5             _SB_MAKE64(0x00D03A0000)
-#define A_BCM1480_PHYS_L2CACHE_WAY6             _SB_MAKE64(0x00D03C0000)
-#define A_BCM1480_PHYS_L2CACHE_WAY7             _SB_MAKE64(0x00D03E0000)
-
-#endif /* _BCM1480_REGS_H */
diff --git a/include/asm-mips/sibyte/bcm1480_scd.h b/include/asm-mips/sibyte/bcm1480_scd.h
deleted file mode 100644
index 25ef24cbb92a..000000000000
--- a/include/asm-mips/sibyte/bcm1480_scd.h
+++ /dev/null
@@ -1,406 +0,0 @@
-/*  *********************************************************************
-    *  BCM1280/BCM1400 Board Support Package
-    *
-    *  SCD Constants and Macros                     File: bcm1480_scd.h
-    *
-    *  This module contains constants and macros useful for
-    *  manipulating the System Control and Debug module.
-    *
-    *  BCM1400 specification level: 1X55_1X80-UM100-R (12/18/03)
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003,2004,2005
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-#ifndef _BCM1480_SCD_H
-#define _BCM1480_SCD_H
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  Pull in the BCM1250's SCD since lots of stuff is the same.
-    ********************************************************************* */
-
-#include "sb1250_scd.h"
-
-/*  *********************************************************************
-    *  Some general notes:
-    *
-    *  This file is basically a "what's new" header file.  Since the
-    *  BCM1250 and the new BCM1480 (and derivatives) share many common
-    *  features, this file contains only what's new or changed from
-    *  the 1250.  (above, you can see that we include the 1250 symbols
-    *  to get the base functionality).
-    *
-    *  In software, be sure to use the correct symbols, particularly
-    *  for blocks that are different between the two chip families.
-    *  All BCM1480-specific symbols have _BCM1480_ in their names,
-    *  and all BCM1250-specific and "base" functions that are common in
-    *  both chips have no special names (this is for compatibility with
-    *  older include files).  Therefore, if you're working with the
-    *  SCD, which is very different on each chip, A_SCD_xxx implies
-    *  the BCM1250 version and A_BCM1480_SCD_xxx implies the BCM1480
-    *  version.
-    ********************************************************************* */
-
-/*  *********************************************************************
-    *  System control/debug registers
-    ********************************************************************* */
-
-/*
- * System Identification and Revision Register (Table 12)
- * Register: SCD_SYSTEM_REVISION
- * This register is field compatible with the 1250.
- */
-
-/*
- * New part definitions
- */
-
-#define K_SYS_PART_BCM1480          0x1406
-#define K_SYS_PART_BCM1280          0x1206
-#define K_SYS_PART_BCM1455          0x1407
-#define K_SYS_PART_BCM1255          0x1257
-#define K_SYS_PART_BCM1158          0x1156
-
-/*
- * Manufacturing Information Register (Table 14)
- * Register: SCD_SYSTEM_MANUF
- */
-
-/*
- * System Configuration Register (Table 15)
- * Register: SCD_SYSTEM_CFG
- * Entire register is different from 1250, all new constants below
- */
-
-#define M_BCM1480_SYS_RESERVED0             _SB_MAKEMASK1(0)
-#define M_BCM1480_SYS_HT_MINRSTCNT          _SB_MAKEMASK1(1)
-#define M_BCM1480_SYS_RESERVED2             _SB_MAKEMASK1(2)
-#define M_BCM1480_SYS_RESERVED3             _SB_MAKEMASK1(3)
-#define M_BCM1480_SYS_RESERVED4             _SB_MAKEMASK1(4)
-#define M_BCM1480_SYS_IOB_DIV               _SB_MAKEMASK1(5)
-
-#define S_BCM1480_SYS_PLL_DIV               _SB_MAKE64(6)
-#define M_BCM1480_SYS_PLL_DIV               _SB_MAKEMASK(5, S_BCM1480_SYS_PLL_DIV)
-#define V_BCM1480_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_BCM1480_SYS_PLL_DIV)
-#define G_BCM1480_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_BCM1480_SYS_PLL_DIV, M_BCM1480_SYS_PLL_DIV)
-
-#define S_BCM1480_SYS_SW_DIV                _SB_MAKE64(11)
-#define M_BCM1480_SYS_SW_DIV                _SB_MAKEMASK(5, S_BCM1480_SYS_SW_DIV)
-#define V_BCM1480_SYS_SW_DIV(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_SW_DIV)
-#define G_BCM1480_SYS_SW_DIV(x)             _SB_GETVALUE(x, S_BCM1480_SYS_SW_DIV, M_BCM1480_SYS_SW_DIV)
-
-#define M_BCM1480_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
-#define M_BCM1480_SYS_DUART1_ENABLE         _SB_MAKEMASK1(17)
-
-#define S_BCM1480_SYS_BOOT_MODE             _SB_MAKE64(18)
-#define M_BCM1480_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_BCM1480_SYS_BOOT_MODE)
-#define V_BCM1480_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_BCM1480_SYS_BOOT_MODE)
-#define G_BCM1480_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_BCM1480_SYS_BOOT_MODE, M_BCM1480_SYS_BOOT_MODE)
-#define K_BCM1480_SYS_BOOT_MODE_ROM32       0
-#define K_BCM1480_SYS_BOOT_MODE_ROM8        1
-#define K_BCM1480_SYS_BOOT_MODE_SMBUS_SMALL 2
-#define K_BCM1480_SYS_BOOT_MODE_SMBUS_BIG   3
-#define M_BCM1480_SYS_BOOT_MODE_SMBUS       _SB_MAKEMASK1(19)
-
-#define M_BCM1480_SYS_PCI_HOST              _SB_MAKEMASK1(20)
-#define M_BCM1480_SYS_PCI_ARBITER           _SB_MAKEMASK1(21)
-#define M_BCM1480_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
-#define M_BCM1480_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
-#define M_BCM1480_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(24)
-#define M_BCM1480_SYS_RESERVED25            _SB_MAKEMASK1(25)
-
-#define S_BCM1480_SYS_CONFIG                26
-#define M_BCM1480_SYS_CONFIG                _SB_MAKEMASK(6, S_BCM1480_SYS_CONFIG)
-#define V_BCM1480_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_CONFIG)
-#define G_BCM1480_SYS_CONFIG(x)             _SB_GETVALUE(x, S_BCM1480_SYS_CONFIG, M_BCM1480_SYS_CONFIG)
-
-#define M_BCM1480_SYS_RESERVED32            _SB_MAKEMASK(32, 15)
-
-#define S_BCM1480_SYS_NODEID                47
-#define M_BCM1480_SYS_NODEID                _SB_MAKEMASK(4, S_BCM1480_SYS_NODEID)
-#define V_BCM1480_SYS_NODEID(x)             _SB_MAKEVALUE(x, S_BCM1480_SYS_NODEID)
-#define G_BCM1480_SYS_NODEID(x)             _SB_GETVALUE(x, S_BCM1480_SYS_NODEID, M_BCM1480_SYS_NODEID)
-
-#define M_BCM1480_SYS_CCNUMA_EN             _SB_MAKEMASK1(51)
-#define M_BCM1480_SYS_CPU_RESET_0           _SB_MAKEMASK1(52)
-#define M_BCM1480_SYS_CPU_RESET_1           _SB_MAKEMASK1(53)
-#define M_BCM1480_SYS_CPU_RESET_2           _SB_MAKEMASK1(54)
-#define M_BCM1480_SYS_CPU_RESET_3           _SB_MAKEMASK1(55)
-#define S_BCM1480_SYS_DISABLECPU0           56
-#define M_BCM1480_SYS_DISABLECPU0           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU0)
-#define S_BCM1480_SYS_DISABLECPU1           57
-#define M_BCM1480_SYS_DISABLECPU1           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU1)
-#define S_BCM1480_SYS_DISABLECPU2           58
-#define M_BCM1480_SYS_DISABLECPU2           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU2)
-#define S_BCM1480_SYS_DISABLECPU3           59
-#define M_BCM1480_SYS_DISABLECPU3           _SB_MAKEMASK1(S_BCM1480_SYS_DISABLECPU3)
-
-#define M_BCM1480_SYS_SB_SOFTRES            _SB_MAKEMASK1(60)
-#define M_BCM1480_SYS_EXT_RESET             _SB_MAKEMASK1(61)
-#define M_BCM1480_SYS_SYSTEM_RESET          _SB_MAKEMASK1(62)
-#define M_BCM1480_SYS_SW_FLAG               _SB_MAKEMASK1(63)
-
-/*
- * Scratch Register (Table 16)
- * Register: SCD_SYSTEM_SCRATCH
- * Same as BCM1250
- */
-
-
-/*
- * Mailbox Registers (Table 17)
- * Registers: SCD_MBOX_{0,1}_CPU_x
- * Same as BCM1250
- */
-
-
-/*
- * See bcm1480_int.h for interrupt mapper registers.
- */
-
-
-/*
- * Watchdog Timer Initial Count Registers (Table 23)
- * Registers: SCD_WDOG_INIT_CNT_x
- *
- * The watchdogs are almost the same as the 1250, except
- * the configuration register has more bits to control the
- * other CPUs.
- */
-
-
-/*
- * Watchdog Timer Configuration Registers (Table 25)
- * Registers: SCD_WDOG_CFG_x
- */
-
-#define M_BCM1480_SCD_WDOG_ENABLE           _SB_MAKEMASK1(0)
-
-#define S_BCM1480_SCD_WDOG_RESET_TYPE       2
-#define M_BCM1480_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(5, S_BCM1480_SCD_WDOG_RESET_TYPE)
-#define V_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE)
-#define G_BCM1480_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_BCM1480_SCD_WDOG_RESET_TYPE, M_BCM1480_SCD_WDOG_RESET_TYPE)
-
-#define K_BCM1480_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
-#define K_BCM1480_SCD_WDOG_RESET_SOFT       1
-#define K_BCM1480_SCD_WDOG_RESET_CPU0       3
-#define K_BCM1480_SCD_WDOG_RESET_CPU1       5
-#define K_BCM1480_SCD_WDOG_RESET_CPU2       9
-#define K_BCM1480_SCD_WDOG_RESET_CPU3       17
-#define K_BCM1480_SCD_WDOG_RESET_ALL_CPUS   31
-
-
-#define M_BCM1480_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(8)
-
-/*
- * General Timer Initial Count Registers (Table 26)
- * Registers: SCD_TIMER_INIT_x
- *
- * The timer registers are the same as the BCM1250
- */
-
-
-/*
- * ZBbus Count Register (Table 29)
- * Register: ZBBUS_CYCLE_COUNT
- *
- * Same as BCM1250
- */
-
-/*
- * ZBbus Compare Registers (Table 30)
- * Registers: ZBBUS_CYCLE_CPx
- *
- * Same as BCM1250
- */
-
-
-/*
- * System Performance Counter Configuration Register (Table 31)
- * Register: PERF_CNT_CFG_0
- *
- * SPC_CFG_SRC[0-3] is the same as the 1250.
- * SPC_CFG_SRC[4-7] only exist on the 1480
- * The clear/enable bits are in different locations on the 1250 and 1480.
- */
-
-#define S_SPC_CFG_SRC4              32
-#define M_SPC_CFG_SRC4              _SB_MAKEMASK(8, S_SPC_CFG_SRC4)
-#define V_SPC_CFG_SRC4(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC4)
-#define G_SPC_CFG_SRC4(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC4, M_SPC_CFG_SRC4)
-
-#define S_SPC_CFG_SRC5              40
-#define M_SPC_CFG_SRC5              _SB_MAKEMASK(8, S_SPC_CFG_SRC5)
-#define V_SPC_CFG_SRC5(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC5)
-#define G_SPC_CFG_SRC5(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC5, M_SPC_CFG_SRC5)
-
-#define S_SPC_CFG_SRC6              48
-#define M_SPC_CFG_SRC6              _SB_MAKEMASK(8, S_SPC_CFG_SRC6)
-#define V_SPC_CFG_SRC6(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC6)
-#define G_SPC_CFG_SRC6(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC6, M_SPC_CFG_SRC6)
-
-#define S_SPC_CFG_SRC7              56
-#define M_SPC_CFG_SRC7              _SB_MAKEMASK(8, S_SPC_CFG_SRC7)
-#define V_SPC_CFG_SRC7(x)           _SB_MAKEVALUE(x, S_SPC_CFG_SRC7)
-#define G_SPC_CFG_SRC7(x)           _SB_GETVALUE(x, S_SPC_CFG_SRC7, M_SPC_CFG_SRC7)
-
-/*
- * System Performance Counter Control Register (Table 32)
- * Register: PERF_CNT_CFG_1
- * BCM1480 specific
- */
-#define M_BCM1480_SPC_CFG_CLEAR     _SB_MAKEMASK1(0)
-#define M_BCM1480_SPC_CFG_ENABLE    _SB_MAKEMASK1(1)
-#if SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_SPC_CFG_CLEAR                 M_BCM1480_SPC_CFG_CLEAR
-#define M_SPC_CFG_ENABLE                M_BCM1480_SPC_CFG_ENABLE
-#endif
-
-/*
- * System Performance Counters (Table 33)
- * Registers: PERF_CNT_x
- */
-
-#define S_BCM1480_SPC_CNT_COUNT             0
-#define M_BCM1480_SPC_CNT_COUNT             _SB_MAKEMASK(40, S_BCM1480_SPC_CNT_COUNT)
-#define V_BCM1480_SPC_CNT_COUNT(x)          _SB_MAKEVALUE(x, S_BCM1480_SPC_CNT_COUNT)
-#define G_BCM1480_SPC_CNT_COUNT(x)          _SB_GETVALUE(x, S_BCM1480_SPC_CNT_COUNT, M_BCM1480_SPC_CNT_COUNT)
-
-#define M_BCM1480_SPC_CNT_OFLOW             _SB_MAKEMASK1(40)
-
-
-/*
- * Bus Watcher Error Status Register (Tables 36, 37)
- * Registers: BUS_ERR_STATUS, BUS_ERR_STATUS_DEBUG
- * Same as BCM1250.
- */
-
-/*
- * Bus Watcher Error Data Registers (Table 38)
- * Registers: BUS_ERR_DATA_x
- * Same as BCM1250.
- */
-
-/*
- * Bus Watcher L2 ECC Counter Register (Table 39)
- * Register: BUS_L2_ERRORS
- * Same as BCM1250.
- */
-
-
-/*
- * Bus Watcher Memory and I/O Error Counter Register (Table 40)
- * Register: BUS_MEM_IO_ERRORS
- * Same as BCM1250.
- */
-
-
-/*
- * Address Trap Registers
- *
- * Register layout same as BCM1250, almost.  The bus agents
- * are different, and the address trap configuration bits are
- * slightly different.
- */
-
-#define M_BCM1480_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
-#define M_BCM1480_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
-
-#define S_BCM1480_ATRAP_CFG_CNT            0
-#define M_BCM1480_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_BCM1480_ATRAP_CFG_CNT)
-#define V_BCM1480_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CNT)
-#define G_BCM1480_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CNT, M_BCM1480_ATRAP_CFG_CNT)
-
-#define M_BCM1480_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
-#define M_BCM1480_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
-#define M_BCM1480_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
-#define M_BCM1480_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
-#define M_BCM1480_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
-
-#define S_BCM1480_ATRAP_CFG_AGENTID     8
-#define M_BCM1480_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_BCM1480_ATRAP_CFG_AGENTID)
-#define V_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID)
-#define G_BCM1480_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_AGENTID, M_BCM1480_ATRAP_CFG_AGENTID)
-
-
-#define K_BCM1480_BUS_AGENT_CPU0            0
-#define K_BCM1480_BUS_AGENT_CPU1            1
-#define K_BCM1480_BUS_AGENT_NC              2
-#define K_BCM1480_BUS_AGENT_IOB             3
-#define K_BCM1480_BUS_AGENT_SCD             4
-#define K_BCM1480_BUS_AGENT_L2C             6
-#define K_BCM1480_BUS_AGENT_MC              7
-#define K_BCM1480_BUS_AGENT_CPU2            8
-#define K_BCM1480_BUS_AGENT_CPU3            9
-#define K_BCM1480_BUS_AGENT_PM              10
-
-#define S_BCM1480_ATRAP_CFG_CATTR           12
-#define M_BCM1480_ATRAP_CFG_CATTR           _SB_MAKEMASK(2, S_BCM1480_ATRAP_CFG_CATTR)
-#define V_BCM1480_ATRAP_CFG_CATTR(x)        _SB_MAKEVALUE(x, S_BCM1480_ATRAP_CFG_CATTR)
-#define G_BCM1480_ATRAP_CFG_CATTR(x)        _SB_GETVALUE(x, S_BCM1480_ATRAP_CFG_CATTR, M_BCM1480_ATRAP_CFG_CATTR)
-
-#define K_BCM1480_ATRAP_CFG_CATTR_IGNORE    0
-#define K_BCM1480_ATRAP_CFG_CATTR_UNC       1
-#define K_BCM1480_ATRAP_CFG_CATTR_NONCOH    2
-#define K_BCM1480_ATRAP_CFG_CATTR_COHERENT  3
-
-#define M_BCM1480_ATRAP_CFG_CATTRINV        _SB_MAKEMASK1(14)
-
-
-/*
- * Trace Event Registers (Table 47)
- * Same as BCM1250.
- */
-
-/*
- * Trace Sequence Control Registers (Table 48)
- * Registers: TRACE_SEQUENCE_x
- *
- * Same as BCM1250 except for two new fields.
- */
-
-
-#define M_BCM1480_SCD_TRSEQ_TID_MATCH_EN    _SB_MAKEMASK1(25)
-
-#define S_BCM1480_SCD_TRSEQ_SWFUNC          26
-#define M_BCM1480_SCD_TRSEQ_SWFUNC          _SB_MAKEMASK(2, S_BCM1480_SCD_TRSEQ_SWFUNC)
-#define V_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_MAKEVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC)
-#define G_BCM1480_SCD_TRSEQ_SWFUNC(x)       _SB_GETVALUE(x, S_BCM1480_SCD_TRSEQ_SWFUNC, M_BCM1480_SCD_TRSEQ_SWFUNC)
-
-/*
- * Trace Control Register (Table 49)
- * Register: TRACE_CFG
- *
- * BCM1480 changes to this register (other than location of the CUR_ADDR field)
- * are defined below.
- */
-
-#define S_BCM1480_SCD_TRACE_CFG_MODE        16
-#define M_BCM1480_SCD_TRACE_CFG_MODE        _SB_MAKEMASK(2, S_BCM1480_SCD_TRACE_CFG_MODE)
-#define V_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_MAKEVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE)
-#define G_BCM1480_SCD_TRACE_CFG_MODE(x)     _SB_GETVALUE(x, S_BCM1480_SCD_TRACE_CFG_MODE, M_BCM1480_SCD_TRACE_CFG_MODE)
-
-#define K_BCM1480_SCD_TRACE_CFG_MODE_BLOCKERS   0
-#define K_BCM1480_SCD_TRACE_CFG_MODE_BYTEEN_INT 1
-#define K_BCM1480_SCD_TRACE_CFG_MODE_FLOW_ID    2
-
-#endif /* _BCM1480_SCD_H */
diff --git a/include/asm-mips/sibyte/bigsur.h b/include/asm-mips/sibyte/bigsur.h
deleted file mode 100644
index ebefe797fc1d..000000000000
--- a/include/asm-mips/sibyte/bigsur.h
+++ /dev/null
@@ -1,49 +0,0 @@
-/*
- * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-#ifndef __ASM_SIBYTE_BIGSUR_H
-#define __ASM_SIBYTE_BIGSUR_H
-
-#include <asm/sibyte/sb1250.h>
-#include <asm/sibyte/bcm1480_int.h>
-
-#ifdef CONFIG_SIBYTE_BIGSUR
-#define SIBYTE_BOARD_NAME "BCM91x80A/B (BigSur)"
-#define SIBYTE_HAVE_PCMCIA 1
-#define SIBYTE_HAVE_IDE    1
-#endif
-
-/* Generic bus chip selects */
-#define LEDS_CS         3
-#define LEDS_PHYS       0x100a0000
-
-#ifdef SIBYTE_HAVE_IDE
-#define IDE_CS          4
-#define IDE_PHYS        0x100b0000
-#define K_GPIO_GB_IDE   4
-#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
-#endif
-
-#ifdef SIBYTE_HAVE_PCMCIA
-#define PCMCIA_CS       6
-#define PCMCIA_PHYS     0x11000000
-#define K_GPIO_PC_READY 9
-#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
-#endif
-
-#endif /* __ASM_SIBYTE_BIGSUR_H */
-
diff --git a/include/asm-mips/sibyte/board.h b/include/asm-mips/sibyte/board.h
deleted file mode 100644
index 25372ae0e814..000000000000
--- a/include/asm-mips/sibyte/board.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2000,2001,2002,2003,2004 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef _SIBYTE_BOARD_H
-#define _SIBYTE_BOARD_H
-
-#if defined(CONFIG_SIBYTE_SWARM) || defined(CONFIG_SIBYTE_CRHONE) || \
-    defined(CONFIG_SIBYTE_CRHINE) || defined(CONFIG_SIBYTE_LITTLESUR)
-#include <asm/sibyte/swarm.h>
-#endif
-
-#if defined(CONFIG_SIBYTE_SENTOSA) || defined(CONFIG_SIBYTE_RHONE)
-#include <asm/sibyte/sentosa.h>
-#endif
-
-#ifdef CONFIG_SIBYTE_CARMEL
-#include <asm/sibyte/carmel.h>
-#endif
-
-#ifdef CONFIG_SIBYTE_BIGSUR
-#include <asm/sibyte/bigsur.h>
-#endif
-
-#ifdef __ASSEMBLY__
-
-#ifdef LEDS_PHYS
-#define setleds(t0, t1, c0, c1, c2, c3) \
-        li      t0, (LEDS_PHYS|0xa0000000); \
-        li      t1, c0; \
-        sb      t1, 0x18(t0); \
-        li      t1, c1; \
-        sb      t1, 0x10(t0); \
-        li      t1, c2; \
-        sb      t1, 0x08(t0); \
-        li      t1, c3; \
-        sb      t1, 0x00(t0)
-#else
-#define setleds(t0, t1, c0, c1, c2, c3)
-#endif /* LEDS_PHYS */
-
-#else
-
-void swarm_setup(void);
-
-#ifdef LEDS_PHYS
-extern void setleds(char *str);
-#else
-#define setleds(s) do { } while (0)
-#endif /* LEDS_PHYS */
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* _SIBYTE_BOARD_H */
diff --git a/include/asm-mips/sibyte/carmel.h b/include/asm-mips/sibyte/carmel.h
deleted file mode 100644
index 11cad71323e8..000000000000
--- a/include/asm-mips/sibyte/carmel.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2002 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-#ifndef __ASM_SIBYTE_CARMEL_H
-#define __ASM_SIBYTE_CARMEL_H
-
-#include <asm/sibyte/sb1250.h>
-#include <asm/sibyte/sb1250_int.h>
-
-#define SIBYTE_BOARD_NAME "Carmel"
-
-#define GPIO_PHY_INTERRUPT      2
-#define GPIO_NONMASKABLE_INT    3
-#define GPIO_CF_INSERTED        6
-#define GPIO_MONTEREY_RESET     7
-#define GPIO_QUADUART_INT       8
-#define GPIO_CF_INT             9
-#define GPIO_FPGA_CCLK          10
-#define GPIO_FPGA_DOUT          11
-#define GPIO_FPGA_DIN           12
-#define GPIO_FPGA_PGM           13
-#define GPIO_FPGA_DONE          14
-#define GPIO_FPGA_INIT          15
-
-#define LEDS_CS                 2
-#define LEDS_PHYS               0x100C0000
-#define MLEDS_CS                3
-#define MLEDS_PHYS              0x100A0000
-#define UART_CS                 4
-#define UART_PHYS               0x100D0000
-#define ARAVALI_CS              5
-#define ARAVALI_PHYS            0x11000000
-#define IDE_CS                  6
-#define IDE_PHYS                0x100B0000
-#define ARAVALI2_CS             7
-#define ARAVALI2_PHYS           0x100E0000
-
-#if defined(CONFIG_SIBYTE_CARMEL)
-#define K_GPIO_GB_IDE   9
-#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
-#endif
-
-
-#endif /* __ASM_SIBYTE_CARMEL_H */
diff --git a/include/asm-mips/sibyte/sb1250.h b/include/asm-mips/sibyte/sb1250.h
deleted file mode 100644
index 80c1a052662a..000000000000
--- a/include/asm-mips/sibyte/sb1250.h
+++ /dev/null
@@ -1,68 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-
-#ifndef _ASM_SIBYTE_SB1250_H
-#define _ASM_SIBYTE_SB1250_H
-
-/*
- * yymmddpp: year, month, day, patch.
- * should sync with Makefile EXTRAVERSION
- */
-#define SIBYTE_RELEASE 0x02111403
-
-#define SB1250_NR_IRQS 64
-
-#define BCM1480_NR_IRQS                 128
-#define BCM1480_NR_IRQS_HALF            64
-
-#define SB1250_DUART_MINOR_BASE         64
-
-#ifndef __ASSEMBLY__
-
-#include <asm/addrspace.h>
-
-/* For revision/pass information */
-#include <asm/sibyte/sb1250_scd.h>
-#include <asm/sibyte/bcm1480_scd.h>
-extern unsigned int sb1_pass;
-extern unsigned int soc_pass;
-extern unsigned int soc_type;
-extern unsigned int periph_rev;
-extern unsigned int zbbus_mhz;
-
-extern void sb1250_time_init(void);
-extern void sb1250_mask_irq(int cpu, int irq);
-extern void sb1250_unmask_irq(int cpu, int irq);
-
-extern void bcm1480_time_init(void);
-extern void bcm1480_mask_irq(int cpu, int irq);
-extern void bcm1480_unmask_irq(int cpu, int irq);
-
-#define AT_spin \
-        __asm__ __volatile__ (          \
-                ".set noat\n"           \
-                "li $at, 0\n"           \
-                "1: beqz $at, 1b\n"     \
-                ".set at\n"             \
-                )
-
-#endif
-
-#define IOADDR(a) ((void __iomem *)(IO_BASE + (a)))
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_defs.h b/include/asm-mips/sibyte/sb1250_defs.h
deleted file mode 100644
index 09365f9111fa..000000000000
--- a/include/asm-mips/sibyte/sb1250_defs.h
+++ /dev/null
@@ -1,259 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  Global constants and macros              File: sb1250_defs.h
-    *
-    *  This file contains macros and definitions used by the other
-    *  include files.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-#ifndef _SB1250_DEFS_H
-#define _SB1250_DEFS_H
-
-/*
- * These headers require ANSI C89 string concatenation, and GCC or other
- * 'long long' (64-bit integer) support.
- */
-#if !defined(__STDC__) && !defined(_MSC_VER)
-#error SiByte headers require ANSI C89 support
-#endif
-
-
-/*  *********************************************************************
-    *  Macros for feature tests, used to enable include file features
-    *  for chip features only present in certain chip revisions.
-    *
-    *  SIBYTE_HDR_FEATURES may be defined to be the mask value chip/revision
-    *  which is to be exposed by the headers.  If undefined, it defaults to
-    *  "all features."
-    *
-    *  Use like:
-    *
-    *    #define SIBYTE_HDR_FEATURES    SIBYTE_HDR_FMASK_112x_PASS1
-    *
-    *           Generate defines only for that revision of chip.
-    *
-    *    #if SIBYTE_HDR_FEATURE(chip,pass)
-    *
-    *           True if header features for that revision or later of
-    *           that particular chip type are enabled in SIBYTE_HDR_FEATURES.
-    *           (Use this to bracket #defines for features present in a given
-    *           revision and later.)
-    *
-    *           Note that there is no implied ordering between chip types.
-    *
-    *           Note also that 'chip' and 'pass' must textually exactly
-    *           match the defines below.  So, for example,
-    *           SIBYTE_HDR_FEATURE(112x, PASS1) is OK, but
-    *           SIBYTE_HDR_FEATURE(1120, pass1) is not (for two reasons).
-    *
-    *    #if SIBYTE_HDR_FEATURE_UP_TO(chip,pass)
-    *
-    *           Same as SIBYTE_HDR_FEATURE, but true for the named revision
-    *           and earlier revisions of the named chip type.
-    *
-    *    #if SIBYTE_HDR_FEATURE_EXACT(chip,pass)
-    *
-    *           Same as SIBYTE_HDR_FEATURE, but only true for the named
-    *           revision of the named chip type.  (Note that this CANNOT
-    *           be used to verify that you're compiling only for that
-    *           particular chip/revision.  It will be true any time this
-    *           chip/revision is included in SIBYTE_HDR_FEATURES.)
-    *
-    *    #if SIBYTE_HDR_FEATURE_CHIP(chip)
-    *
-    *           True if header features for (any revision of) that chip type
-    *           are enabled in SIBYTE_HDR_FEATURES.  (Use this to bracket
-    *           #defines for features specific to a given chip type.)
-    *
-    *  Mask values currently include room for additional revisions of each
-    *  chip type, but can be renumbered at will.  Note that they MUST fit
-    *  into 31 bits and may not include C type constructs, for safe use in
-    *  CPP conditionals.  Bit positions within chip types DO indicate
-    *  ordering, so be careful when adding support for new minor revs.
-    ********************************************************************* */
-
-#define SIBYTE_HDR_FMASK_1250_ALL               0x000000ff
-#define SIBYTE_HDR_FMASK_1250_PASS1             0x00000001
-#define SIBYTE_HDR_FMASK_1250_PASS2             0x00000002
-#define SIBYTE_HDR_FMASK_1250_PASS3             0x00000004
-
-#define SIBYTE_HDR_FMASK_112x_ALL               0x00000f00
-#define SIBYTE_HDR_FMASK_112x_PASS1             0x00000100
-
-#define SIBYTE_HDR_FMASK_1480_ALL               0x0000f000
-#define SIBYTE_HDR_FMASK_1480_PASS1             0x00001000
-#define SIBYTE_HDR_FMASK_1480_PASS2             0x00002000
-
-/* Bit mask for chip/revision.  (use _ALL for all revisions of a chip).  */
-#define SIBYTE_HDR_FMASK(chip, pass)                                    \
-    (SIBYTE_HDR_FMASK_ ## chip ## _ ## pass)
-#define SIBYTE_HDR_FMASK_ALLREVS(chip)                                  \
-    (SIBYTE_HDR_FMASK_ ## chip ## _ALL)
-
-/* Default constant value for all chips, all revisions */
-#define SIBYTE_HDR_FMASK_ALL                                            \
-    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL              \
-     | SIBYTE_HDR_FMASK_1480_ALL)
-
-/* This one is used for the "original" BCM1250/BCM112x chips.  We use this
-   to weed out constants and macros that do not exist on later chips like
-   the BCM1480  */
-#define SIBYTE_HDR_FMASK_1250_112x_ALL                                  \
-    (SIBYTE_HDR_FMASK_1250_ALL | SIBYTE_HDR_FMASK_112x_ALL)
-#define SIBYTE_HDR_FMASK_1250_112x SIBYTE_HDR_FMASK_1250_112x_ALL
-
-#ifndef SIBYTE_HDR_FEATURES
-#define SIBYTE_HDR_FEATURES                     SIBYTE_HDR_FMASK_ALL
-#endif
-
-
-/* Bit mask for revisions of chip exclusively before the named revision.  */
-#define SIBYTE_HDR_FMASK_BEFORE(chip, pass)                             \
-    ((SIBYTE_HDR_FMASK(chip, pass) - 1) & SIBYTE_HDR_FMASK_ALLREVS(chip))
-
-/* Bit mask for revisions of chip exclusively after the named revision.  */
-#define SIBYTE_HDR_FMASK_AFTER(chip, pass)                              \
-    (~(SIBYTE_HDR_FMASK(chip, pass)                                     \
-     | (SIBYTE_HDR_FMASK(chip, pass) - 1)) & SIBYTE_HDR_FMASK_ALLREVS(chip))
-
-
-/* True if header features enabled for (any revision of) that chip type.  */
-#define SIBYTE_HDR_FEATURE_CHIP(chip)                                   \
-    (!! (SIBYTE_HDR_FMASK_ALLREVS(chip) & SIBYTE_HDR_FEATURES))
-
-/* True for all versions of the BCM1250 and BCM1125, but not true for
-   anything else */
-#define SIBYTE_HDR_FEATURE_1250_112x \
-      (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
-/*    (!!  (SIBYTE_HDR_FEATURES & SIBYHTE_HDR_FMASK_1250_112x)) */
-
-/* True if header features enabled for that rev or later, inclusive.  */
-#define SIBYTE_HDR_FEATURE(chip, pass)                                  \
-    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
-          | SIBYTE_HDR_FMASK_AFTER(chip, pass)) & SIBYTE_HDR_FEATURES))
-
-/* True if header features enabled for exactly that rev.  */
-#define SIBYTE_HDR_FEATURE_EXACT(chip, pass)                            \
-    (!! (SIBYTE_HDR_FMASK(chip, pass) & SIBYTE_HDR_FEATURES))
-
-/* True if header features enabled for that rev or before, inclusive.  */
-#define SIBYTE_HDR_FEATURE_UP_TO(chip, pass)                            \
-    (!! ((SIBYTE_HDR_FMASK(chip, pass)                                  \
-         | SIBYTE_HDR_FMASK_BEFORE(chip, pass)) & SIBYTE_HDR_FEATURES))
-
-
-/*  *********************************************************************
-    *  Naming schemes for constants in these files:
-    *
-    *  M_xxx           MASK constant (identifies bits in a register).
-    *                  For multi-bit fields, all bits in the field will
-    *                  be set.
-    *
-    *  K_xxx           "Code" constant (value for data in a multi-bit
-    *                  field).  The value is right justified.
-    *
-    *  V_xxx           "Value" constant.  This is the same as the
-    *                  corresponding "K_xxx" constant, except it is
-    *                  shifted to the correct position in the register.
-    *
-    *  S_xxx           SHIFT constant.  This is the number of bits that
-    *                  a field value (code) needs to be shifted
-    *                  (towards the left) to put the value in the right
-    *                  position for the register.
-    *
-    *  A_xxx           ADDRESS constant.  This will be a physical
-    *                  address.  Use the PHYS_TO_K1 macro to generate
-    *                  a K1SEG address.
-    *
-    *  R_xxx           RELATIVE offset constant.  This is an offset from
-    *                  an A_xxx constant (usually the first register in
-    *                  a group).
-    *
-    *  G_xxx(X)        GET value.  This macro obtains a multi-bit field
-    *                  from a register, masks it, and shifts it to
-    *                  the bottom of the register (retrieving a K_xxx
-    *                  value, for example).
-    *
-    *  V_xxx(X)        VALUE.  This macro computes the value of a
-    *                  K_xxx constant shifted to the correct position
-    *                  in the register.
-    ********************************************************************* */
-
-
-
-
-/*
- * Cast to 64-bit number.  Presumably the syntax is different in
- * assembly language.
- *
- * Note: you'll need to define uint32_t and uint64_t in your headers.
- */
-
-#if !defined(__ASSEMBLY__)
-#define _SB_MAKE64(x) ((uint64_t)(x))
-#define _SB_MAKE32(x) ((uint32_t)(x))
-#else
-#define _SB_MAKE64(x) (x)
-#define _SB_MAKE32(x) (x)
-#endif
-
-
-/*
- * Make a mask for 1 bit at position 'n'
- */
-
-#define _SB_MAKEMASK1(n) (_SB_MAKE64(1) << _SB_MAKE64(n))
-#define _SB_MAKEMASK1_32(n) (_SB_MAKE32(1) << _SB_MAKE32(n))
-
-/*
- * Make a mask for 'v' bits at position 'n'
- */
-
-#define _SB_MAKEMASK(v, n) (_SB_MAKE64((_SB_MAKE64(1)<<(v))-1) << _SB_MAKE64(n))
-#define _SB_MAKEMASK_32(v, n) (_SB_MAKE32((_SB_MAKE32(1)<<(v))-1) << _SB_MAKE32(n))
-
-/*
- * Make a value at 'v' at bit position 'n'
- */
-
-#define _SB_MAKEVALUE(v, n) (_SB_MAKE64(v) << _SB_MAKE64(n))
-#define _SB_MAKEVALUE_32(v, n) (_SB_MAKE32(v) << _SB_MAKE32(n))
-
-#define _SB_GETVALUE(v, n, m) ((_SB_MAKE64(v) & _SB_MAKE64(m)) >> _SB_MAKE64(n))
-#define _SB_GETVALUE_32(v, n, m) ((_SB_MAKE32(v) & _SB_MAKE32(m)) >> _SB_MAKE32(n))
-
-/*
- * Macros to read/write on-chip registers
- * XXX should we do the PHYS_TO_K1 here?
- */
-
-
-#if defined(__mips64) && !defined(__ASSEMBLY__)
-#define SBWRITECSR(csr, val) *((volatile uint64_t *) PHYS_TO_K1(csr)) = (val)
-#define SBREADCSR(csr) (*((volatile uint64_t *) PHYS_TO_K1(csr)))
-#endif /* __ASSEMBLY__ */
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_dma.h b/include/asm-mips/sibyte/sb1250_dma.h
deleted file mode 100644
index bad56171d747..000000000000
--- a/include/asm-mips/sibyte/sb1250_dma.h
+++ /dev/null
@@ -1,594 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  DMA definitions                          File: sb1250_dma.h
-    *
-    *  This module contains constants and macros useful for
-    *  programming the SB1250's DMA controllers, both the data mover
-    *  and the Ethernet DMA.
-    *
-    *  SB1250 specification level:  User's manual 10/21/02
-    *  BCM1280 specification level: User's manual 11/24/03
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_DMA_H
-#define _SB1250_DMA_H
-
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  DMA Registers
-    ********************************************************************* */
-
-/*
- * Ethernet and Serial DMA Configuration Register 0  (Table 7-4)
- * Registers: DMA_CONFIG0_MAC_x_RX_CH_0
- * Registers: DMA_CONFIG0_MAC_x_TX_CH_0
- * Registers: DMA_CONFIG0_SER_x_RX
- * Registers: DMA_CONFIG0_SER_x_TX
- */
-
-
-#define M_DMA_DROP                  _SB_MAKEMASK1(0)
-
-#define M_DMA_CHAIN_SEL             _SB_MAKEMASK1(1)
-#define M_DMA_RESERVED1             _SB_MAKEMASK1(2)
-
-#define S_DMA_DESC_TYPE             _SB_MAKE64(1)
-#define M_DMA_DESC_TYPE             _SB_MAKEMASK(2, S_DMA_DESC_TYPE)
-#define V_DMA_DESC_TYPE(x)          _SB_MAKEVALUE(x, S_DMA_DESC_TYPE)
-#define G_DMA_DESC_TYPE(x)          _SB_GETVALUE(x, S_DMA_DESC_TYPE, M_DMA_DESC_TYPE)
-
-#define K_DMA_DESC_TYPE_RING_AL         0
-#define K_DMA_DESC_TYPE_CHAIN_AL        1
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define K_DMA_DESC_TYPE_RING_UAL_WI     2
-#define K_DMA_DESC_TYPE_RING_UAL_RMW    3
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define M_DMA_EOP_INT_EN            _SB_MAKEMASK1(3)
-#define M_DMA_HWM_INT_EN            _SB_MAKEMASK1(4)
-#define M_DMA_LWM_INT_EN            _SB_MAKEMASK1(5)
-#define M_DMA_TBX_EN                _SB_MAKEMASK1(6)
-#define M_DMA_TDX_EN                _SB_MAKEMASK1(7)
-
-#define S_DMA_INT_PKTCNT            _SB_MAKE64(8)
-#define M_DMA_INT_PKTCNT            _SB_MAKEMASK(8, S_DMA_INT_PKTCNT)
-#define V_DMA_INT_PKTCNT(x)         _SB_MAKEVALUE(x, S_DMA_INT_PKTCNT)
-#define G_DMA_INT_PKTCNT(x)         _SB_GETVALUE(x, S_DMA_INT_PKTCNT, M_DMA_INT_PKTCNT)
-
-#define S_DMA_RINGSZ                _SB_MAKE64(16)
-#define M_DMA_RINGSZ                _SB_MAKEMASK(16, S_DMA_RINGSZ)
-#define V_DMA_RINGSZ(x)             _SB_MAKEVALUE(x, S_DMA_RINGSZ)
-#define G_DMA_RINGSZ(x)             _SB_GETVALUE(x, S_DMA_RINGSZ, M_DMA_RINGSZ)
-
-#define S_DMA_HIGH_WATERMARK        _SB_MAKE64(32)
-#define M_DMA_HIGH_WATERMARK        _SB_MAKEMASK(16, S_DMA_HIGH_WATERMARK)
-#define V_DMA_HIGH_WATERMARK(x)     _SB_MAKEVALUE(x, S_DMA_HIGH_WATERMARK)
-#define G_DMA_HIGH_WATERMARK(x)     _SB_GETVALUE(x, S_DMA_HIGH_WATERMARK, M_DMA_HIGH_WATERMARK)
-
-#define S_DMA_LOW_WATERMARK         _SB_MAKE64(48)
-#define M_DMA_LOW_WATERMARK         _SB_MAKEMASK(16, S_DMA_LOW_WATERMARK)
-#define V_DMA_LOW_WATERMARK(x)      _SB_MAKEVALUE(x, S_DMA_LOW_WATERMARK)
-#define G_DMA_LOW_WATERMARK(x)      _SB_GETVALUE(x, S_DMA_LOW_WATERMARK, M_DMA_LOW_WATERMARK)
-
-/*
- * Ethernet and Serial DMA Configuration Register 1 (Table 7-5)
- * Registers: DMA_CONFIG1_MAC_x_RX_CH_0
- * Registers: DMA_CONFIG1_DMA_x_TX_CH_0
- * Registers: DMA_CONFIG1_SER_x_RX
- * Registers: DMA_CONFIG1_SER_x_TX
- */
-
-#define M_DMA_HDR_CF_EN             _SB_MAKEMASK1(0)
-#define M_DMA_ASIC_XFR_EN           _SB_MAKEMASK1(1)
-#define M_DMA_PRE_ADDR_EN           _SB_MAKEMASK1(2)
-#define M_DMA_FLOW_CTL_EN           _SB_MAKEMASK1(3)
-#define M_DMA_NO_DSCR_UPDT          _SB_MAKEMASK1(4)
-#define M_DMA_L2CA                  _SB_MAKEMASK1(5)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_DMA_RX_XTRA_STATUS        _SB_MAKEMASK1(6)
-#define M_DMA_TX_CPU_PAUSE          _SB_MAKEMASK1(6)
-#define M_DMA_TX_FC_PAUSE_EN        _SB_MAKEMASK1(7)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define M_DMA_MBZ1                  _SB_MAKEMASK(6, 15)
-
-#define S_DMA_HDR_SIZE              _SB_MAKE64(21)
-#define M_DMA_HDR_SIZE              _SB_MAKEMASK(9, S_DMA_HDR_SIZE)
-#define V_DMA_HDR_SIZE(x)           _SB_MAKEVALUE(x, S_DMA_HDR_SIZE)
-#define G_DMA_HDR_SIZE(x)           _SB_GETVALUE(x, S_DMA_HDR_SIZE, M_DMA_HDR_SIZE)
-
-#define M_DMA_MBZ2                  _SB_MAKEMASK(5, 32)
-
-#define S_DMA_ASICXFR_SIZE          _SB_MAKE64(37)
-#define M_DMA_ASICXFR_SIZE          _SB_MAKEMASK(9, S_DMA_ASICXFR_SIZE)
-#define V_DMA_ASICXFR_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_ASICXFR_SIZE)
-#define G_DMA_ASICXFR_SIZE(x)       _SB_GETVALUE(x, S_DMA_ASICXFR_SIZE, M_DMA_ASICXFR_SIZE)
-
-#define S_DMA_INT_TIMEOUT           _SB_MAKE64(48)
-#define M_DMA_INT_TIMEOUT           _SB_MAKEMASK(16, S_DMA_INT_TIMEOUT)
-#define V_DMA_INT_TIMEOUT(x)        _SB_MAKEVALUE(x, S_DMA_INT_TIMEOUT)
-#define G_DMA_INT_TIMEOUT(x)        _SB_GETVALUE(x, S_DMA_INT_TIMEOUT, M_DMA_INT_TIMEOUT)
-
-/*
- * Ethernet and Serial DMA Descriptor base address (Table 7-6)
- */
-
-#define M_DMA_DSCRBASE_MBZ          _SB_MAKEMASK(4, 0)
-
-
-/*
- * ASIC Mode Base Address (Table 7-7)
- */
-
-#define M_DMA_ASIC_BASE_MBZ         _SB_MAKEMASK(20, 0)
-
-/*
- * DMA Descriptor Count Registers (Table 7-8)
- */
-
-/* No bitfields */
-
-
-/*
- * Current Descriptor Address Register (Table 7-11)
- */
-
-#define S_DMA_CURDSCR_ADDR          _SB_MAKE64(0)
-#define M_DMA_CURDSCR_ADDR          _SB_MAKEMASK(40, S_DMA_CURDSCR_ADDR)
-#define S_DMA_CURDSCR_COUNT         _SB_MAKE64(40)
-#define M_DMA_CURDSCR_COUNT         _SB_MAKEMASK(16, S_DMA_CURDSCR_COUNT)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_DMA_TX_CH_PAUSE_ON        _SB_MAKEMASK1(56)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-/*
- * Receive Packet Drop Registers
- */
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_DMA_OODLOST_RX           _SB_MAKE64(0)
-#define M_DMA_OODLOST_RX           _SB_MAKEMASK(16, S_DMA_OODLOST_RX)
-#define G_DMA_OODLOST_RX(x)        _SB_GETVALUE(x, S_DMA_OODLOST_RX, M_DMA_OODLOST_RX)
-
-#define S_DMA_EOP_COUNT_RX         _SB_MAKE64(16)
-#define M_DMA_EOP_COUNT_RX         _SB_MAKEMASK(8, S_DMA_EOP_COUNT_RX)
-#define G_DMA_EOP_COUNT_RX(x)      _SB_GETVALUE(x, S_DMA_EOP_COUNT_RX, M_DMA_EOP_COUNT_RX)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-/*  *********************************************************************
-    *  DMA Descriptors
-    ********************************************************************* */
-
-/*
- * Descriptor doubleword "A"  (Table 7-12)
- */
-
-#define S_DMA_DSCRA_OFFSET          _SB_MAKE64(0)
-#define M_DMA_DSCRA_OFFSET          _SB_MAKEMASK(5, S_DMA_DSCRA_OFFSET)
-#define V_DMA_DSCRA_OFFSET(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_OFFSET)
-#define G_DMA_DSCRA_OFFSET(x)       _SB_GETVALUE(x, S_DMA_DSCRA_OFFSET, M_DMA_DSCRA_OFFSET)
-
-/* Note: Don't shift the address over, just mask it with the mask below */
-#define S_DMA_DSCRA_A_ADDR          _SB_MAKE64(5)
-#define M_DMA_DSCRA_A_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRA_A_ADDR)
-
-#define M_DMA_DSCRA_A_ADDR_OFFSET   (M_DMA_DSCRA_OFFSET | M_DMA_DSCRA_A_ADDR)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_DMA_DSCRA_A_ADDR_UA        _SB_MAKE64(0)
-#define M_DMA_DSCRA_A_ADDR_UA        _SB_MAKEMASK(40, S_DMA_DSCRA_A_ADDR_UA)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define S_DMA_DSCRA_A_SIZE          _SB_MAKE64(40)
-#define M_DMA_DSCRA_A_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRA_A_SIZE)
-#define V_DMA_DSCRA_A_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_A_SIZE)
-#define G_DMA_DSCRA_A_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRA_A_SIZE, M_DMA_DSCRA_A_SIZE)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_DMA_DSCRA_DSCR_CNT        _SB_MAKE64(40)
-#define M_DMA_DSCRA_DSCR_CNT        _SB_MAKEMASK(8, S_DMA_DSCRA_DSCR_CNT)
-#define G_DMA_DSCRA_DSCR_CNT(x)     _SB_GETVALUE(x, S_DMA_DSCRA_DSCR_CNT, M_DMA_DSCRA_DSCR_CNT)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define M_DMA_DSCRA_INTERRUPT       _SB_MAKEMASK1(49)
-#define M_DMA_DSCRA_OFFSETB         _SB_MAKEMASK1(50)
-
-#define S_DMA_DSCRA_STATUS          _SB_MAKE64(51)
-#define M_DMA_DSCRA_STATUS          _SB_MAKEMASK(13, S_DMA_DSCRA_STATUS)
-#define V_DMA_DSCRA_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRA_STATUS)
-#define G_DMA_DSCRA_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRA_STATUS, M_DMA_DSCRA_STATUS)
-
-/*
- * Descriptor doubleword "B"  (Table 7-13)
- */
-
-
-#define S_DMA_DSCRB_OPTIONS         _SB_MAKE64(0)
-#define M_DMA_DSCRB_OPTIONS         _SB_MAKEMASK(4, S_DMA_DSCRB_OPTIONS)
-#define V_DMA_DSCRB_OPTIONS(x)      _SB_MAKEVALUE(x, S_DMA_DSCRB_OPTIONS)
-#define G_DMA_DSCRB_OPTIONS(x)      _SB_GETVALUE(x, S_DMA_DSCRB_OPTIONS, M_DMA_DSCRB_OPTIONS)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_DMA_DSCRB_A_SIZE        _SB_MAKE64(8)
-#define M_DMA_DSCRB_A_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_A_SIZE)
-#define V_DMA_DSCRB_A_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_A_SIZE)
-#define G_DMA_DSCRB_A_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_A_SIZE, M_DMA_DSCRB_A_SIZE)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define R_DMA_DSCRB_ADDR            _SB_MAKE64(0x10)
-
-/* Note: Don't shift the address over, just mask it with the mask below */
-#define S_DMA_DSCRB_B_ADDR          _SB_MAKE64(5)
-#define M_DMA_DSCRB_B_ADDR          _SB_MAKEMASK(35, S_DMA_DSCRB_B_ADDR)
-
-#define S_DMA_DSCRB_B_SIZE          _SB_MAKE64(40)
-#define M_DMA_DSCRB_B_SIZE          _SB_MAKEMASK(9, S_DMA_DSCRB_B_SIZE)
-#define V_DMA_DSCRB_B_SIZE(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_B_SIZE)
-#define G_DMA_DSCRB_B_SIZE(x)       _SB_GETVALUE(x, S_DMA_DSCRB_B_SIZE, M_DMA_DSCRB_B_SIZE)
-
-#define M_DMA_DSCRB_B_VALID         _SB_MAKEMASK1(49)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKE64(48)
-#define M_DMA_DSCRB_PKT_SIZE_MSB    _SB_MAKEMASK(2, S_DMA_DSCRB_PKT_SIZE_MSB)
-#define V_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB)
-#define G_DMA_DSCRB_PKT_SIZE_MSB(x) _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE_MSB, M_DMA_DSCRB_PKT_SIZE_MSB)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define S_DMA_DSCRB_PKT_SIZE        _SB_MAKE64(50)
-#define M_DMA_DSCRB_PKT_SIZE        _SB_MAKEMASK(14, S_DMA_DSCRB_PKT_SIZE)
-#define V_DMA_DSCRB_PKT_SIZE(x)     _SB_MAKEVALUE(x, S_DMA_DSCRB_PKT_SIZE)
-#define G_DMA_DSCRB_PKT_SIZE(x)     _SB_GETVALUE(x, S_DMA_DSCRB_PKT_SIZE, M_DMA_DSCRB_PKT_SIZE)
-
-/*
- * from pass2 some bits in dscr_b are also used for rx status
- */
-#define S_DMA_DSCRB_STATUS          _SB_MAKE64(0)
-#define M_DMA_DSCRB_STATUS          _SB_MAKEMASK(1, S_DMA_DSCRB_STATUS)
-#define V_DMA_DSCRB_STATUS(x)       _SB_MAKEVALUE(x, S_DMA_DSCRB_STATUS)
-#define G_DMA_DSCRB_STATUS(x)       _SB_GETVALUE(x, S_DMA_DSCRB_STATUS, M_DMA_DSCRB_STATUS)
-
-/*
- * Ethernet Descriptor Status Bits (Table 7-15)
- */
-
-#define M_DMA_ETHRX_BADIP4CS        _SB_MAKEMASK1(51)
-#define M_DMA_ETHRX_DSCRERR         _SB_MAKEMASK1(52)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/* Note: This bit is in the DSCR_B options field */
-#define M_DMA_ETHRX_BADTCPCS    _SB_MAKEMASK1(0)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/* Note: These bits are in the DSCR_B options field */
-#define M_DMA_ETH_VLAN_FLAG     _SB_MAKEMASK1(1)
-#define M_DMA_ETH_CRC_FLAG      _SB_MAKEMASK1(2)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define S_DMA_ETHRX_RXCH            53
-#define M_DMA_ETHRX_RXCH            _SB_MAKEMASK(2, S_DMA_ETHRX_RXCH)
-#define V_DMA_ETHRX_RXCH(x)         _SB_MAKEVALUE(x, S_DMA_ETHRX_RXCH)
-#define G_DMA_ETHRX_RXCH(x)         _SB_GETVALUE(x, S_DMA_ETHRX_RXCH, M_DMA_ETHRX_RXCH)
-
-#define S_DMA_ETHRX_PKTTYPE         55
-#define M_DMA_ETHRX_PKTTYPE         _SB_MAKEMASK(3, S_DMA_ETHRX_PKTTYPE)
-#define V_DMA_ETHRX_PKTTYPE(x)      _SB_MAKEVALUE(x, S_DMA_ETHRX_PKTTYPE)
-#define G_DMA_ETHRX_PKTTYPE(x)      _SB_GETVALUE(x, S_DMA_ETHRX_PKTTYPE, M_DMA_ETHRX_PKTTYPE)
-
-#define K_DMA_ETHRX_PKTTYPE_IPV4    0
-#define K_DMA_ETHRX_PKTTYPE_ARPV4   1
-#define K_DMA_ETHRX_PKTTYPE_802     2
-#define K_DMA_ETHRX_PKTTYPE_OTHER   3
-#define K_DMA_ETHRX_PKTTYPE_USER0   4
-#define K_DMA_ETHRX_PKTTYPE_USER1   5
-#define K_DMA_ETHRX_PKTTYPE_USER2   6
-#define K_DMA_ETHRX_PKTTYPE_USER3   7
-
-#define M_DMA_ETHRX_MATCH_HASH      _SB_MAKEMASK1(58)
-#define M_DMA_ETHRX_MATCH_EXACT     _SB_MAKEMASK1(59)
-#define M_DMA_ETHRX_BCAST           _SB_MAKEMASK1(60)
-#define M_DMA_ETHRX_MCAST           _SB_MAKEMASK1(61)
-#define M_DMA_ETHRX_BAD             _SB_MAKEMASK1(62)
-#define M_DMA_ETHRX_SOP             _SB_MAKEMASK1(63)
-
-/*
- * Ethernet Transmit Status Bits (Table 7-16)
- */
-
-#define M_DMA_ETHTX_SOP             _SB_MAKEMASK1(63)
-
-/*
- * Ethernet Transmit Options (Table 7-17)
- */
-
-#define K_DMA_ETHTX_NOTSOP          _SB_MAKE64(0x00)
-#define K_DMA_ETHTX_APPENDCRC       _SB_MAKE64(0x01)
-#define K_DMA_ETHTX_REPLACECRC      _SB_MAKE64(0x02)
-#define K_DMA_ETHTX_APPENDCRC_APPENDPAD _SB_MAKE64(0x03)
-#define K_DMA_ETHTX_APPENDVLAN_REPLACECRC _SB_MAKE64(0x04)
-#define K_DMA_ETHTX_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x05)
-#define K_DMA_ETHTX_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x6)
-#define K_DMA_ETHTX_NOMODS          _SB_MAKE64(0x07)
-#define K_DMA_ETHTX_RESERVED1       _SB_MAKE64(0x08)
-#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC _SB_MAKE64(0x09)
-#define K_DMA_ETHTX_REPLACESADDR_REPLACECRC _SB_MAKE64(0x0A)
-#define K_DMA_ETHTX_REPLACESADDR_APPENDCRC_APPENDPAD _SB_MAKE64(0x0B)
-#define K_DMA_ETHTX_REPLACESADDR_APPENDVLAN_REPLACECRC _SB_MAKE64(0x0C)
-#define K_DMA_ETHTX_REPLACESADDR_REMOVEVLAN_REPLACECRC _SB_MAKE64(0x0D)
-#define K_DMA_ETHTX_REPLACESADDR_REPLACEVLAN_REPLACECRC _SB_MAKE64(0x0E)
-#define K_DMA_ETHTX_RESERVED2       _SB_MAKE64(0x0F)
-
-/*
- * Serial Receive Options (Table 7-18)
- */
-#define M_DMA_SERRX_CRC_ERROR       _SB_MAKEMASK1(56)
-#define M_DMA_SERRX_ABORT           _SB_MAKEMASK1(57)
-#define M_DMA_SERRX_OCTET_ERROR     _SB_MAKEMASK1(58)
-#define M_DMA_SERRX_LONGFRAME_ERROR _SB_MAKEMASK1(59)
-#define M_DMA_SERRX_SHORTFRAME_ERROR _SB_MAKEMASK1(60)
-#define M_DMA_SERRX_OVERRUN_ERROR   _SB_MAKEMASK1(61)
-#define M_DMA_SERRX_GOOD            _SB_MAKEMASK1(62)
-#define M_DMA_SERRX_SOP             _SB_MAKEMASK1(63)
-
-/*
- * Serial Transmit Status Bits (Table 7-20)
- */
-
-#define M_DMA_SERTX_FLAG            _SB_MAKEMASK1(63)
-
-/*
- * Serial Transmit Options (Table 7-21)
- */
-
-#define K_DMA_SERTX_RESERVED        _SB_MAKEMASK1(0)
-#define K_DMA_SERTX_APPENDCRC       _SB_MAKEMASK1(1)
-#define K_DMA_SERTX_APPENDPAD       _SB_MAKEMASK1(2)
-#define K_DMA_SERTX_ABORT           _SB_MAKEMASK1(3)
-
-
-/*  *********************************************************************
-    *  Data Mover Registers
-    ********************************************************************* */
-
-/*
- * Data Mover Descriptor Base Address Register (Table 7-22)
- * Register: DM_DSCR_BASE_0
- * Register: DM_DSCR_BASE_1
- * Register: DM_DSCR_BASE_2
- * Register: DM_DSCR_BASE_3
- */
-
-#define M_DM_DSCR_BASE_MBZ          _SB_MAKEMASK(4, 0)
-
-/*  Note: Just mask the base address and then OR it in. */
-#define S_DM_DSCR_BASE_ADDR         _SB_MAKE64(4)
-#define M_DM_DSCR_BASE_ADDR         _SB_MAKEMASK(36, S_DM_DSCR_BASE_ADDR)
-
-#define S_DM_DSCR_BASE_RINGSZ       _SB_MAKE64(40)
-#define M_DM_DSCR_BASE_RINGSZ       _SB_MAKEMASK(16, S_DM_DSCR_BASE_RINGSZ)
-#define V_DM_DSCR_BASE_RINGSZ(x)    _SB_MAKEVALUE(x, S_DM_DSCR_BASE_RINGSZ)
-#define G_DM_DSCR_BASE_RINGSZ(x)    _SB_GETVALUE(x, S_DM_DSCR_BASE_RINGSZ, M_DM_DSCR_BASE_RINGSZ)
-
-#define S_DM_DSCR_BASE_PRIORITY     _SB_MAKE64(56)
-#define M_DM_DSCR_BASE_PRIORITY     _SB_MAKEMASK(3, S_DM_DSCR_BASE_PRIORITY)
-#define V_DM_DSCR_BASE_PRIORITY(x)  _SB_MAKEVALUE(x, S_DM_DSCR_BASE_PRIORITY)
-#define G_DM_DSCR_BASE_PRIORITY(x)  _SB_GETVALUE(x, S_DM_DSCR_BASE_PRIORITY, M_DM_DSCR_BASE_PRIORITY)
-
-#define K_DM_DSCR_BASE_PRIORITY_1   0
-#define K_DM_DSCR_BASE_PRIORITY_2   1
-#define K_DM_DSCR_BASE_PRIORITY_4   2
-#define K_DM_DSCR_BASE_PRIORITY_8   3
-#define K_DM_DSCR_BASE_PRIORITY_16  4
-
-#define M_DM_DSCR_BASE_ACTIVE       _SB_MAKEMASK1(59)
-#define M_DM_DSCR_BASE_INTERRUPT    _SB_MAKEMASK1(60)
-#define M_DM_DSCR_BASE_RESET        _SB_MAKEMASK1(61)   /* write register */
-#define M_DM_DSCR_BASE_ERROR        _SB_MAKEMASK1(61)   /* read register */
-#define M_DM_DSCR_BASE_ABORT        _SB_MAKEMASK1(62)
-#define M_DM_DSCR_BASE_ENABL        _SB_MAKEMASK1(63)
-
-/*
- * Data Mover Descriptor Count Register (Table 7-25)
- */
-
-/* no bitfields */
-
-/*
- * Data Mover Current Descriptor Address (Table 7-24)
- * Register: DM_CUR_DSCR_ADDR_0
- * Register: DM_CUR_DSCR_ADDR_1
- * Register: DM_CUR_DSCR_ADDR_2
- * Register: DM_CUR_DSCR_ADDR_3
- */
-
-#define S_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKE64(0)
-#define M_DM_CUR_DSCR_DSCR_ADDR     _SB_MAKEMASK(40, S_DM_CUR_DSCR_DSCR_ADDR)
-
-#define S_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKE64(48)
-#define M_DM_CUR_DSCR_DSCR_COUNT    _SB_MAKEMASK(16, S_DM_CUR_DSCR_DSCR_COUNT)
-#define V_DM_CUR_DSCR_DSCR_COUNT(r) _SB_MAKEVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT)
-#define G_DM_CUR_DSCR_DSCR_COUNT(r) _SB_GETVALUE(r, S_DM_CUR_DSCR_DSCR_COUNT,\
-                                     M_DM_CUR_DSCR_DSCR_COUNT)
-
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/*
- * Data Mover Channel Partial Result Registers
- * Register: DM_PARTIAL_0
- * Register: DM_PARTIAL_1
- * Register: DM_PARTIAL_2
- * Register: DM_PARTIAL_3
- */
-#define S_DM_PARTIAL_CRC_PARTIAL      _SB_MAKE64(0)
-#define M_DM_PARTIAL_CRC_PARTIAL      _SB_MAKEMASK(32, S_DM_PARTIAL_CRC_PARTIAL)
-#define V_DM_PARTIAL_CRC_PARTIAL(r)   _SB_MAKEVALUE(r, S_DM_PARTIAL_CRC_PARTIAL)
-#define G_DM_PARTIAL_CRC_PARTIAL(r)   _SB_GETVALUE(r, S_DM_PARTIAL_CRC_PARTIAL,\
-                                       M_DM_PARTIAL_CRC_PARTIAL)
-
-#define S_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKE64(32)
-#define M_DM_PARTIAL_TCPCS_PARTIAL    _SB_MAKEMASK(16, S_DM_PARTIAL_TCPCS_PARTIAL)
-#define V_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_MAKEVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL)
-#define G_DM_PARTIAL_TCPCS_PARTIAL(r) _SB_GETVALUE(r, S_DM_PARTIAL_TCPCS_PARTIAL,\
-                                       M_DM_PARTIAL_TCPCS_PARTIAL)
-
-#define M_DM_PARTIAL_ODD_BYTE         _SB_MAKEMASK1(48)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/*
- * Data Mover CRC Definition Registers
- * Register: CRC_DEF_0
- * Register: CRC_DEF_1
- */
-#define S_CRC_DEF_CRC_INIT            _SB_MAKE64(0)
-#define M_CRC_DEF_CRC_INIT            _SB_MAKEMASK(32, S_CRC_DEF_CRC_INIT)
-#define V_CRC_DEF_CRC_INIT(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_INIT)
-#define G_CRC_DEF_CRC_INIT(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_INIT,\
-                                       M_CRC_DEF_CRC_INIT)
-
-#define S_CRC_DEF_CRC_POLY            _SB_MAKE64(32)
-#define M_CRC_DEF_CRC_POLY            _SB_MAKEMASK(32, S_CRC_DEF_CRC_POLY)
-#define V_CRC_DEF_CRC_POLY(r)         _SB_MAKEVALUE(r, S_CRC_DEF_CRC_POLY)
-#define G_CRC_DEF_CRC_POLY(r)         _SB_GETVALUE(r, S_CRC_DEF_CRC_POLY,\
-                                       M_CRC_DEF_CRC_POLY)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/*
- * Data Mover CRC/Checksum Definition Registers
- * Register: CTCP_DEF_0
- * Register: CTCP_DEF_1
- */
-#define S_CTCP_DEF_CRC_TXOR           _SB_MAKE64(0)
-#define M_CTCP_DEF_CRC_TXOR           _SB_MAKEMASK(32, S_CTCP_DEF_CRC_TXOR)
-#define V_CTCP_DEF_CRC_TXOR(r)        _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_TXOR)
-#define G_CTCP_DEF_CRC_TXOR(r)        _SB_GETVALUE(r, S_CTCP_DEF_CRC_TXOR,\
-                                       M_CTCP_DEF_CRC_TXOR)
-
-#define S_CTCP_DEF_TCPCS_INIT         _SB_MAKE64(32)
-#define M_CTCP_DEF_TCPCS_INIT         _SB_MAKEMASK(16, S_CTCP_DEF_TCPCS_INIT)
-#define V_CTCP_DEF_TCPCS_INIT(r)      _SB_MAKEVALUE(r, S_CTCP_DEF_TCPCS_INIT)
-#define G_CTCP_DEF_TCPCS_INIT(r)      _SB_GETVALUE(r, S_CTCP_DEF_TCPCS_INIT,\
-                                       M_CTCP_DEF_TCPCS_INIT)
-
-#define S_CTCP_DEF_CRC_WIDTH          _SB_MAKE64(48)
-#define M_CTCP_DEF_CRC_WIDTH          _SB_MAKEMASK(2, S_CTCP_DEF_CRC_WIDTH)
-#define V_CTCP_DEF_CRC_WIDTH(r)       _SB_MAKEVALUE(r, S_CTCP_DEF_CRC_WIDTH)
-#define G_CTCP_DEF_CRC_WIDTH(r)       _SB_GETVALUE(r, S_CTCP_DEF_CRC_WIDTH,\
-                                       M_CTCP_DEF_CRC_WIDTH)
-
-#define K_CTCP_DEF_CRC_WIDTH_4        0
-#define K_CTCP_DEF_CRC_WIDTH_2        1
-#define K_CTCP_DEF_CRC_WIDTH_1        2
-
-#define M_CTCP_DEF_CRC_BIT_ORDER      _SB_MAKEMASK1(50)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-
-/*
- * Data Mover Descriptor Doubleword "A"  (Table 7-26)
- */
-
-#define S_DM_DSCRA_DST_ADDR         _SB_MAKE64(0)
-#define M_DM_DSCRA_DST_ADDR         _SB_MAKEMASK(40, S_DM_DSCRA_DST_ADDR)
-
-#define M_DM_DSCRA_UN_DEST          _SB_MAKEMASK1(40)
-#define M_DM_DSCRA_UN_SRC           _SB_MAKEMASK1(41)
-#define M_DM_DSCRA_INTERRUPT        _SB_MAKEMASK1(42)
-#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
-#define M_DM_DSCRA_THROTTLE         _SB_MAKEMASK1(43)
-#endif /* up to 1250 PASS1 */
-
-#define S_DM_DSCRA_DIR_DEST         _SB_MAKE64(44)
-#define M_DM_DSCRA_DIR_DEST         _SB_MAKEMASK(2, S_DM_DSCRA_DIR_DEST)
-#define V_DM_DSCRA_DIR_DEST(x)      _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_DEST)
-#define G_DM_DSCRA_DIR_DEST(x)      _SB_GETVALUE(x, S_DM_DSCRA_DIR_DEST, M_DM_DSCRA_DIR_DEST)
-
-#define K_DM_DSCRA_DIR_DEST_INCR    0
-#define K_DM_DSCRA_DIR_DEST_DECR    1
-#define K_DM_DSCRA_DIR_DEST_CONST   2
-
-#define V_DM_DSCRA_DIR_DEST_INCR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_INCR, S_DM_DSCRA_DIR_DEST)
-#define V_DM_DSCRA_DIR_DEST_DECR    _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_DECR, S_DM_DSCRA_DIR_DEST)
-#define V_DM_DSCRA_DIR_DEST_CONST   _SB_MAKEVALUE(K_DM_DSCRA_DIR_DEST_CONST, S_DM_DSCRA_DIR_DEST)
-
-#define S_DM_DSCRA_DIR_SRC          _SB_MAKE64(46)
-#define M_DM_DSCRA_DIR_SRC          _SB_MAKEMASK(2, S_DM_DSCRA_DIR_SRC)
-#define V_DM_DSCRA_DIR_SRC(x)       _SB_MAKEVALUE(x, S_DM_DSCRA_DIR_SRC)
-#define G_DM_DSCRA_DIR_SRC(x)       _SB_GETVALUE(x, S_DM_DSCRA_DIR_SRC, M_DM_DSCRA_DIR_SRC)
-
-#define K_DM_DSCRA_DIR_SRC_INCR     0
-#define K_DM_DSCRA_DIR_SRC_DECR     1
-#define K_DM_DSCRA_DIR_SRC_CONST    2
-
-#define V_DM_DSCRA_DIR_SRC_INCR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_INCR, S_DM_DSCRA_DIR_SRC)
-#define V_DM_DSCRA_DIR_SRC_DECR     _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_DECR, S_DM_DSCRA_DIR_SRC)
-#define V_DM_DSCRA_DIR_SRC_CONST    _SB_MAKEVALUE(K_DM_DSCRA_DIR_SRC_CONST, S_DM_DSCRA_DIR_SRC)
-
-
-#define M_DM_DSCRA_ZERO_MEM         _SB_MAKEMASK1(48)
-#define M_DM_DSCRA_PREFETCH         _SB_MAKEMASK1(49)
-#define M_DM_DSCRA_L2C_DEST         _SB_MAKEMASK1(50)
-#define M_DM_DSCRA_L2C_SRC          _SB_MAKEMASK1(51)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_DM_DSCRA_RD_BKOFF         _SB_MAKEMASK1(52)
-#define M_DM_DSCRA_WR_BKOFF         _SB_MAKEMASK1(53)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_DM_DSCRA_TCPCS_EN         _SB_MAKEMASK1(54)
-#define M_DM_DSCRA_TCPCS_RES        _SB_MAKEMASK1(55)
-#define M_DM_DSCRA_TCPCS_AP         _SB_MAKEMASK1(56)
-#define M_DM_DSCRA_CRC_EN           _SB_MAKEMASK1(57)
-#define M_DM_DSCRA_CRC_RES          _SB_MAKEMASK1(58)
-#define M_DM_DSCRA_CRC_AP           _SB_MAKEMASK1(59)
-#define M_DM_DSCRA_CRC_DFN          _SB_MAKEMASK1(60)
-#define M_DM_DSCRA_CRC_XBIT         _SB_MAKEMASK1(61)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define M_DM_DSCRA_RESERVED2        _SB_MAKEMASK(3, 61)
-
-/*
- * Data Mover Descriptor Doubleword "B"  (Table 7-25)
- */
-
-#define S_DM_DSCRB_SRC_ADDR         _SB_MAKE64(0)
-#define M_DM_DSCRB_SRC_ADDR         _SB_MAKEMASK(40, S_DM_DSCRB_SRC_ADDR)
-
-#define S_DM_DSCRB_SRC_LENGTH       _SB_MAKE64(40)
-#define M_DM_DSCRB_SRC_LENGTH       _SB_MAKEMASK(20, S_DM_DSCRB_SRC_LENGTH)
-#define V_DM_DSCRB_SRC_LENGTH(x)    _SB_MAKEVALUE(x, S_DM_DSCRB_SRC_LENGTH)
-#define G_DM_DSCRB_SRC_LENGTH(x)    _SB_GETVALUE(x, S_DM_DSCRB_SRC_LENGTH, M_DM_DSCRB_SRC_LENGTH)
-
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_genbus.h b/include/asm-mips/sibyte/sb1250_genbus.h
deleted file mode 100644
index 94e9c7c8e783..000000000000
--- a/include/asm-mips/sibyte/sb1250_genbus.h
+++ /dev/null
@@ -1,474 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  Generic Bus Constants                     File: sb1250_genbus.h
-    *
-    *  This module contains constants and macros useful for
-    *  manipulating the SB1250's Generic Bus interface
-    *
-    *  SB1250 specification level:  User's manual 10/21/02
-    *  BCM1280 specification level: User's Manual 11/14/03
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000, 2001, 2002, 2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_GENBUS_H
-#define _SB1250_GENBUS_H
-
-#include "sb1250_defs.h"
-
-/*
- * Generic Bus Region Configuration Registers (Table 11-4)
- */
-
-#define S_IO_RDY_ACTIVE         0
-#define M_IO_RDY_ACTIVE         _SB_MAKEMASK1(S_IO_RDY_ACTIVE)
-
-#define S_IO_ENA_RDY            1
-#define M_IO_ENA_RDY            _SB_MAKEMASK1(S_IO_ENA_RDY)
-
-#define S_IO_WIDTH_SEL          2
-#define M_IO_WIDTH_SEL          _SB_MAKEMASK(2, S_IO_WIDTH_SEL)
-#define K_IO_WIDTH_SEL_1        0
-#define K_IO_WIDTH_SEL_2        1
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
-    || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define K_IO_WIDTH_SEL_1L       2
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#define K_IO_WIDTH_SEL_4        3
-#define V_IO_WIDTH_SEL(x)       _SB_MAKEVALUE(x, S_IO_WIDTH_SEL)
-#define G_IO_WIDTH_SEL(x)       _SB_GETVALUE(x, S_IO_WIDTH_SEL, M_IO_WIDTH_SEL)
-
-#define S_IO_PARITY_ENA         4
-#define M_IO_PARITY_ENA         _SB_MAKEMASK1(S_IO_PARITY_ENA)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
-    || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_IO_BURST_EN           5
-#define M_IO_BURST_EN           _SB_MAKEMASK1(S_IO_BURST_EN)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#define S_IO_PARITY_ODD         6
-#define M_IO_PARITY_ODD         _SB_MAKEMASK1(S_IO_PARITY_ODD)
-#define S_IO_NONMUX             7
-#define M_IO_NONMUX             _SB_MAKEMASK1(S_IO_NONMUX)
-
-#define S_IO_TIMEOUT            8
-#define M_IO_TIMEOUT            _SB_MAKEMASK(8, S_IO_TIMEOUT)
-#define V_IO_TIMEOUT(x)         _SB_MAKEVALUE(x, S_IO_TIMEOUT)
-#define G_IO_TIMEOUT(x)         _SB_GETVALUE(x, S_IO_TIMEOUT, M_IO_TIMEOUT)
-
-/*
- * Generic Bus Region Size register (Table 11-5)
- */
-
-#define S_IO_MULT_SIZE          0
-#define M_IO_MULT_SIZE          _SB_MAKEMASK(12, S_IO_MULT_SIZE)
-#define V_IO_MULT_SIZE(x)       _SB_MAKEVALUE(x, S_IO_MULT_SIZE)
-#define G_IO_MULT_SIZE(x)       _SB_GETVALUE(x, S_IO_MULT_SIZE, M_IO_MULT_SIZE)
-
-#define S_IO_REGSIZE            16       /* # bits to shift size for this reg */
-
-/*
- * Generic Bus Region Address (Table 11-6)
- */
-
-#define S_IO_START_ADDR         0
-#define M_IO_START_ADDR         _SB_MAKEMASK(14, S_IO_START_ADDR)
-#define V_IO_START_ADDR(x)      _SB_MAKEVALUE(x, S_IO_START_ADDR)
-#define G_IO_START_ADDR(x)      _SB_GETVALUE(x, S_IO_START_ADDR, M_IO_START_ADDR)
-
-#define S_IO_ADDRBASE           16       /* # bits to shift addr for this reg */
-
-#define M_IO_BLK_CACHE          _SB_MAKEMASK1(15)
-
-
-/*
- * Generic Bus Timing 0 Registers (Table 11-7)
- */
-
-#define S_IO_ALE_WIDTH          0
-#define M_IO_ALE_WIDTH          _SB_MAKEMASK(3, S_IO_ALE_WIDTH)
-#define V_IO_ALE_WIDTH(x)       _SB_MAKEVALUE(x, S_IO_ALE_WIDTH)
-#define G_IO_ALE_WIDTH(x)       _SB_GETVALUE(x, S_IO_ALE_WIDTH, M_IO_ALE_WIDTH)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
-    || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_IO_EARLY_CS           _SB_MAKEMASK1(3)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#define S_IO_ALE_TO_CS          4
-#define M_IO_ALE_TO_CS          _SB_MAKEMASK(2, S_IO_ALE_TO_CS)
-#define V_IO_ALE_TO_CS(x)       _SB_MAKEVALUE(x, S_IO_ALE_TO_CS)
-#define G_IO_ALE_TO_CS(x)       _SB_GETVALUE(x, S_IO_ALE_TO_CS, M_IO_ALE_TO_CS)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
-    || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_IO_BURST_WIDTH           _SB_MAKE64(6)
-#define M_IO_BURST_WIDTH           _SB_MAKEMASK(2, S_IO_BURST_WIDTH)
-#define V_IO_BURST_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_BURST_WIDTH)
-#define G_IO_BURST_WIDTH(x)        _SB_GETVALUE(x, S_IO_BURST_WIDTH, M_IO_BURST_WIDTH)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#define S_IO_CS_WIDTH           8
-#define M_IO_CS_WIDTH           _SB_MAKEMASK(5, S_IO_CS_WIDTH)
-#define V_IO_CS_WIDTH(x)        _SB_MAKEVALUE(x, S_IO_CS_WIDTH)
-#define G_IO_CS_WIDTH(x)        _SB_GETVALUE(x, S_IO_CS_WIDTH, M_IO_CS_WIDTH)
-
-#define S_IO_RDY_SMPLE          13
-#define M_IO_RDY_SMPLE          _SB_MAKEMASK(3, S_IO_RDY_SMPLE)
-#define V_IO_RDY_SMPLE(x)       _SB_MAKEVALUE(x, S_IO_RDY_SMPLE)
-#define G_IO_RDY_SMPLE(x)       _SB_GETVALUE(x, S_IO_RDY_SMPLE, M_IO_RDY_SMPLE)
-
-
-/*
- * Generic Bus Timing 1 Registers (Table 11-8)
- */
-
-#define S_IO_ALE_TO_WRITE       0
-#define M_IO_ALE_TO_WRITE       _SB_MAKEMASK(3, S_IO_ALE_TO_WRITE)
-#define V_IO_ALE_TO_WRITE(x)    _SB_MAKEVALUE(x, S_IO_ALE_TO_WRITE)
-#define G_IO_ALE_TO_WRITE(x)    _SB_GETVALUE(x, S_IO_ALE_TO_WRITE, M_IO_ALE_TO_WRITE)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) \
-    || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_IO_RDY_SYNC           _SB_MAKEMASK1(3)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#define S_IO_WRITE_WIDTH        4
-#define M_IO_WRITE_WIDTH        _SB_MAKEMASK(4, S_IO_WRITE_WIDTH)
-#define V_IO_WRITE_WIDTH(x)     _SB_MAKEVALUE(x, S_IO_WRITE_WIDTH)
-#define G_IO_WRITE_WIDTH(x)     _SB_GETVALUE(x, S_IO_WRITE_WIDTH, M_IO_WRITE_WIDTH)
-
-#define S_IO_IDLE_CYCLE         8
-#define M_IO_IDLE_CYCLE         _SB_MAKEMASK(4, S_IO_IDLE_CYCLE)
-#define V_IO_IDLE_CYCLE(x)      _SB_MAKEVALUE(x, S_IO_IDLE_CYCLE)
-#define G_IO_IDLE_CYCLE(x)      _SB_GETVALUE(x, S_IO_IDLE_CYCLE, M_IO_IDLE_CYCLE)
-
-#define S_IO_OE_TO_CS           12
-#define M_IO_OE_TO_CS           _SB_MAKEMASK(2, S_IO_OE_TO_CS)
-#define V_IO_OE_TO_CS(x)        _SB_MAKEVALUE(x, S_IO_OE_TO_CS)
-#define G_IO_OE_TO_CS(x)        _SB_GETVALUE(x, S_IO_OE_TO_CS, M_IO_OE_TO_CS)
-
-#define S_IO_CS_TO_OE           14
-#define M_IO_CS_TO_OE           _SB_MAKEMASK(2, S_IO_CS_TO_OE)
-#define V_IO_CS_TO_OE(x)        _SB_MAKEVALUE(x, S_IO_CS_TO_OE)
-#define G_IO_CS_TO_OE(x)        _SB_GETVALUE(x, S_IO_CS_TO_OE, M_IO_CS_TO_OE)
-
-/*
- * Generic Bus Interrupt Status Register (Table 11-9)
- */
-
-#define M_IO_CS_ERR_INT         _SB_MAKEMASK(0, 8)
-#define M_IO_CS0_ERR_INT        _SB_MAKEMASK1(0)
-#define M_IO_CS1_ERR_INT        _SB_MAKEMASK1(1)
-#define M_IO_CS2_ERR_INT        _SB_MAKEMASK1(2)
-#define M_IO_CS3_ERR_INT        _SB_MAKEMASK1(3)
-#define M_IO_CS4_ERR_INT        _SB_MAKEMASK1(4)
-#define M_IO_CS5_ERR_INT        _SB_MAKEMASK1(5)
-#define M_IO_CS6_ERR_INT        _SB_MAKEMASK1(6)
-#define M_IO_CS7_ERR_INT        _SB_MAKEMASK1(7)
-
-#define M_IO_RD_PAR_INT         _SB_MAKEMASK1(9)
-#define M_IO_TIMEOUT_INT        _SB_MAKEMASK1(10)
-#define M_IO_ILL_ADDR_INT       _SB_MAKEMASK1(11)
-#define M_IO_MULT_CS_INT        _SB_MAKEMASK1(12)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_IO_COH_ERR            _SB_MAKEMASK1(14)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-
-/*
- * Generic Bus Output Drive Control Register 0 (Table 14-18)
- */
-
-#define S_IO_SLEW0              0
-#define M_IO_SLEW0              _SB_MAKEMASK(2, S_IO_SLEW0)
-#define V_IO_SLEW0(x)           _SB_MAKEVALUE(x, S_IO_SLEW0)
-#define G_IO_SLEW0(x)           _SB_GETVALUE(x, S_IO_SLEW0, M_IO_SLEW0)
-
-#define S_IO_DRV_A              2
-#define M_IO_DRV_A              _SB_MAKEMASK(2, S_IO_DRV_A)
-#define V_IO_DRV_A(x)           _SB_MAKEVALUE(x, S_IO_DRV_A)
-#define G_IO_DRV_A(x)           _SB_GETVALUE(x, S_IO_DRV_A, M_IO_DRV_A)
-
-#define S_IO_DRV_B              6
-#define M_IO_DRV_B              _SB_MAKEMASK(2, S_IO_DRV_B)
-#define V_IO_DRV_B(x)           _SB_MAKEVALUE(x, S_IO_DRV_B)
-#define G_IO_DRV_B(x)           _SB_GETVALUE(x, S_IO_DRV_B, M_IO_DRV_B)
-
-#define S_IO_DRV_C              10
-#define M_IO_DRV_C              _SB_MAKEMASK(2, S_IO_DRV_C)
-#define V_IO_DRV_C(x)           _SB_MAKEVALUE(x, S_IO_DRV_C)
-#define G_IO_DRV_C(x)           _SB_GETVALUE(x, S_IO_DRV_C, M_IO_DRV_C)
-
-#define S_IO_DRV_D              14
-#define M_IO_DRV_D              _SB_MAKEMASK(2, S_IO_DRV_D)
-#define V_IO_DRV_D(x)           _SB_MAKEVALUE(x, S_IO_DRV_D)
-#define G_IO_DRV_D(x)           _SB_GETVALUE(x, S_IO_DRV_D, M_IO_DRV_D)
-
-/*
- * Generic Bus Output Drive Control Register 1 (Table 14-19)
- */
-
-#define S_IO_DRV_E              2
-#define M_IO_DRV_E              _SB_MAKEMASK(2, S_IO_DRV_E)
-#define V_IO_DRV_E(x)           _SB_MAKEVALUE(x, S_IO_DRV_E)
-#define G_IO_DRV_E(x)           _SB_GETVALUE(x, S_IO_DRV_E, M_IO_DRV_E)
-
-#define S_IO_DRV_F              6
-#define M_IO_DRV_F              _SB_MAKEMASK(2, S_IO_DRV_F)
-#define V_IO_DRV_F(x)           _SB_MAKEVALUE(x, S_IO_DRV_F)
-#define G_IO_DRV_F(x)           _SB_GETVALUE(x, S_IO_DRV_F, M_IO_DRV_F)
-
-#define S_IO_SLEW1              8
-#define M_IO_SLEW1              _SB_MAKEMASK(2, S_IO_SLEW1)
-#define V_IO_SLEW1(x)           _SB_MAKEVALUE(x, S_IO_SLEW1)
-#define G_IO_SLEW1(x)           _SB_GETVALUE(x, S_IO_SLEW1, M_IO_SLEW1)
-
-#define S_IO_DRV_G              10
-#define M_IO_DRV_G              _SB_MAKEMASK(2, S_IO_DRV_G)
-#define V_IO_DRV_G(x)           _SB_MAKEVALUE(x, S_IO_DRV_G)
-#define G_IO_DRV_G(x)           _SB_GETVALUE(x, S_IO_DRV_G, M_IO_DRV_G)
-
-#define S_IO_SLEW2              12
-#define M_IO_SLEW2              _SB_MAKEMASK(2, S_IO_SLEW2)
-#define V_IO_SLEW2(x)           _SB_MAKEVALUE(x, S_IO_SLEW2)
-#define G_IO_SLEW2(x)           _SB_GETVALUE(x, S_IO_SLEW2, M_IO_SLEW2)
-
-#define S_IO_DRV_H              14
-#define M_IO_DRV_H              _SB_MAKEMASK(2, S_IO_DRV_H)
-#define V_IO_DRV_H(x)           _SB_MAKEVALUE(x, S_IO_DRV_H)
-#define G_IO_DRV_H(x)           _SB_GETVALUE(x, S_IO_DRV_H, M_IO_DRV_H)
-
-/*
- * Generic Bus Output Drive Control Register 2 (Table 14-20)
- */
-
-#define S_IO_DRV_J              2
-#define M_IO_DRV_J              _SB_MAKEMASK(2, S_IO_DRV_J)
-#define V_IO_DRV_J(x)           _SB_MAKEVALUE(x, S_IO_DRV_J)
-#define G_IO_DRV_J(x)           _SB_GETVALUE(x, S_IO_DRV_J, M_IO_DRV_J)
-
-#define S_IO_DRV_K              6
-#define M_IO_DRV_K              _SB_MAKEMASK(2, S_IO_DRV_K)
-#define V_IO_DRV_K(x)           _SB_MAKEVALUE(x, S_IO_DRV_K)
-#define G_IO_DRV_K(x)           _SB_GETVALUE(x, S_IO_DRV_K, M_IO_DRV_K)
-
-#define S_IO_DRV_L              10
-#define M_IO_DRV_L              _SB_MAKEMASK(2, S_IO_DRV_L)
-#define V_IO_DRV_L(x)           _SB_MAKEVALUE(x, S_IO_DRV_L)
-#define G_IO_DRV_L(x)           _SB_GETVALUE(x, S_IO_DRV_L, M_IO_DRV_L)
-
-#define S_IO_DRV_M              14
-#define M_IO_DRV_M              _SB_MAKEMASK(2, S_IO_DRV_M)
-#define V_IO_DRV_M(x)           _SB_MAKEVALUE(x, S_IO_DRV_M)
-#define G_IO_DRV_M(x)           _SB_GETVALUE(x, S_IO_DRV_M, M_IO_DRV_M)
-
-/*
- * Generic Bus Output Drive Control Register 3 (Table 14-21)
- */
-
-#define S_IO_SLEW3              0
-#define M_IO_SLEW3              _SB_MAKEMASK(2, S_IO_SLEW3)
-#define V_IO_SLEW3(x)           _SB_MAKEVALUE(x, S_IO_SLEW3)
-#define G_IO_SLEW3(x)           _SB_GETVALUE(x, S_IO_SLEW3, M_IO_SLEW3)
-
-#define S_IO_DRV_N              2
-#define M_IO_DRV_N              _SB_MAKEMASK(2, S_IO_DRV_N)
-#define V_IO_DRV_N(x)           _SB_MAKEVALUE(x, S_IO_DRV_N)
-#define G_IO_DRV_N(x)           _SB_GETVALUE(x, S_IO_DRV_N, M_IO_DRV_N)
-
-#define S_IO_DRV_P              6
-#define M_IO_DRV_P              _SB_MAKEMASK(2, S_IO_DRV_P)
-#define V_IO_DRV_P(x)           _SB_MAKEVALUE(x, S_IO_DRV_P)
-#define G_IO_DRV_P(x)           _SB_GETVALUE(x, S_IO_DRV_P, M_IO_DRV_P)
-
-#define S_IO_DRV_Q              10
-#define M_IO_DRV_Q              _SB_MAKEMASK(2, S_IO_DRV_Q)
-#define V_IO_DRV_Q(x)           _SB_MAKEVALUE(x, S_IO_DRV_Q)
-#define G_IO_DRV_Q(x)           _SB_GETVALUE(x, S_IO_DRV_Q, M_IO_DRV_Q)
-
-#define S_IO_DRV_R              14
-#define M_IO_DRV_R              _SB_MAKEMASK(2, S_IO_DRV_R)
-#define V_IO_DRV_R(x)           _SB_MAKEVALUE(x, S_IO_DRV_R)
-#define G_IO_DRV_R(x)           _SB_GETVALUE(x, S_IO_DRV_R, M_IO_DRV_R)
-
-
-/*
- * PCMCIA configuration register (Table 12-6)
- */
-
-#define M_PCMCIA_CFG_ATTRMEM    _SB_MAKEMASK1(0)
-#define M_PCMCIA_CFG_3VEN       _SB_MAKEMASK1(1)
-#define M_PCMCIA_CFG_5VEN       _SB_MAKEMASK1(2)
-#define M_PCMCIA_CFG_VPPEN      _SB_MAKEMASK1(3)
-#define M_PCMCIA_CFG_RESET      _SB_MAKEMASK1(4)
-#define M_PCMCIA_CFG_APWRONEN   _SB_MAKEMASK1(5)
-#define M_PCMCIA_CFG_CDMASK     _SB_MAKEMASK1(6)
-#define M_PCMCIA_CFG_WPMASK     _SB_MAKEMASK1(7)
-#define M_PCMCIA_CFG_RDYMASK    _SB_MAKEMASK1(8)
-#define M_PCMCIA_CFG_PWRCTL     _SB_MAKEMASK1(9)
-
-#if SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_PCMCIA_MODE           16
-#define M_PCMCIA_MODE           _SB_MAKEMASK(3, S_PCMCIA_MODE)
-#define V_PCMCIA_MODE(x)        _SB_MAKEVALUE(x, S_PCMCIA_MODE)
-#define G_PCMCIA_MODE(x)        _SB_GETVALUE(x, S_PCMCIA_MODE, M_PCMCIA_MODE)
-
-#define K_PCMCIA_MODE_PCMA_NOB  0       /* standard PCMCIA "A", no "B" */
-#define K_PCMCIA_MODE_IDEA_NOB  1       /* IDE "A", no "B" */
-#define K_PCMCIA_MODE_PCMIOA_NOB 2      /* PCMCIA with I/O "A", no "B" */
-#define K_PCMCIA_MODE_PCMA_PCMB 4       /* standard PCMCIA "A", standard PCMCIA "B" */
-#define K_PCMCIA_MODE_IDEA_PCMB 5       /* IDE "A", standard PCMCIA "B" */
-#define K_PCMCIA_MODE_PCMA_IDEB 6       /* standard PCMCIA "A", IDE "B" */
-#define K_PCMCIA_MODE_IDEA_IDEB 7       /* IDE "A", IDE "B" */
-#endif
-
-
-/*
- * PCMCIA status register (Table 12-7)
- */
-
-#define M_PCMCIA_STATUS_CD1     _SB_MAKEMASK1(0)
-#define M_PCMCIA_STATUS_CD2     _SB_MAKEMASK1(1)
-#define M_PCMCIA_STATUS_VS1     _SB_MAKEMASK1(2)
-#define M_PCMCIA_STATUS_VS2     _SB_MAKEMASK1(3)
-#define M_PCMCIA_STATUS_WP      _SB_MAKEMASK1(4)
-#define M_PCMCIA_STATUS_RDY     _SB_MAKEMASK1(5)
-#define M_PCMCIA_STATUS_3VEN    _SB_MAKEMASK1(6)
-#define M_PCMCIA_STATUS_5VEN    _SB_MAKEMASK1(7)
-#define M_PCMCIA_STATUS_CDCHG   _SB_MAKEMASK1(8)
-#define M_PCMCIA_STATUS_WPCHG   _SB_MAKEMASK1(9)
-#define M_PCMCIA_STATUS_RDYCHG  _SB_MAKEMASK1(10)
-
-/*
- * GPIO Interrupt Type Register (table 13-3)
- */
-
-#define K_GPIO_INTR_DISABLE     0
-#define K_GPIO_INTR_EDGE        1
-#define K_GPIO_INTR_LEVEL       2
-#define K_GPIO_INTR_SPLIT       3
-
-#define S_GPIO_INTR_TYPEX(n)    (((n)/2)*2)
-#define M_GPIO_INTR_TYPEX(n)    _SB_MAKEMASK(2, S_GPIO_INTR_TYPEX(n))
-#define V_GPIO_INTR_TYPEX(n, x) _SB_MAKEVALUE(x, S_GPIO_INTR_TYPEX(n))
-#define G_GPIO_INTR_TYPEX(n, x) _SB_GETVALUE(x, S_GPIO_INTR_TYPEX(n), M_GPIO_INTR_TYPEX(n))
-
-#define S_GPIO_INTR_TYPE0       0
-#define M_GPIO_INTR_TYPE0       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE0)
-#define V_GPIO_INTR_TYPE0(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE0)
-#define G_GPIO_INTR_TYPE0(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE0, M_GPIO_INTR_TYPE0)
-
-#define S_GPIO_INTR_TYPE2       2
-#define M_GPIO_INTR_TYPE2       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE2)
-#define V_GPIO_INTR_TYPE2(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE2)
-#define G_GPIO_INTR_TYPE2(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE2, M_GPIO_INTR_TYPE2)
-
-#define S_GPIO_INTR_TYPE4       4
-#define M_GPIO_INTR_TYPE4       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE4)
-#define V_GPIO_INTR_TYPE4(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE4)
-#define G_GPIO_INTR_TYPE4(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE4, M_GPIO_INTR_TYPE4)
-
-#define S_GPIO_INTR_TYPE6       6
-#define M_GPIO_INTR_TYPE6       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE6)
-#define V_GPIO_INTR_TYPE6(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE6)
-#define G_GPIO_INTR_TYPE6(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE6, M_GPIO_INTR_TYPE6)
-
-#define S_GPIO_INTR_TYPE8       8
-#define M_GPIO_INTR_TYPE8       _SB_MAKEMASK(2, S_GPIO_INTR_TYPE8)
-#define V_GPIO_INTR_TYPE8(x)    _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE8)
-#define G_GPIO_INTR_TYPE8(x)    _SB_GETVALUE(x, S_GPIO_INTR_TYPE8, M_GPIO_INTR_TYPE8)
-
-#define S_GPIO_INTR_TYPE10      10
-#define M_GPIO_INTR_TYPE10      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE10)
-#define V_GPIO_INTR_TYPE10(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE10)
-#define G_GPIO_INTR_TYPE10(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE10, M_GPIO_INTR_TYPE10)
-
-#define S_GPIO_INTR_TYPE12      12
-#define M_GPIO_INTR_TYPE12      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE12)
-#define V_GPIO_INTR_TYPE12(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE12)
-#define G_GPIO_INTR_TYPE12(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE12, M_GPIO_INTR_TYPE12)
-
-#define S_GPIO_INTR_TYPE14      14
-#define M_GPIO_INTR_TYPE14      _SB_MAKEMASK(2, S_GPIO_INTR_TYPE14)
-#define V_GPIO_INTR_TYPE14(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_TYPE14)
-#define G_GPIO_INTR_TYPE14(x)   _SB_GETVALUE(x, S_GPIO_INTR_TYPE14, M_GPIO_INTR_TYPE14)
-
-#if SIBYTE_HDR_FEATURE_CHIP(1480)
-
-/*
- * GPIO Interrupt Additional Type Register
- */
-
-#define K_GPIO_INTR_BOTHEDGE    0
-#define K_GPIO_INTR_RISEEDGE    1
-#define K_GPIO_INTR_UNPRED1     2
-#define K_GPIO_INTR_UNPRED2     3
-
-#define S_GPIO_INTR_ATYPEX(n)   (((n)/2)*2)
-#define M_GPIO_INTR_ATYPEX(n)   _SB_MAKEMASK(2, S_GPIO_INTR_ATYPEX(n))
-#define V_GPIO_INTR_ATYPEX(n, x)        _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPEX(n))
-#define G_GPIO_INTR_ATYPEX(n, x)        _SB_GETVALUE(x, S_GPIO_INTR_ATYPEX(n), M_GPIO_INTR_ATYPEX(n))
-
-#define S_GPIO_INTR_ATYPE0      0
-#define M_GPIO_INTR_ATYPE0      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE0)
-#define V_GPIO_INTR_ATYPE0(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE0)
-#define G_GPIO_INTR_ATYPE0(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE0, M_GPIO_INTR_ATYPE0)
-
-#define S_GPIO_INTR_ATYPE2      2
-#define M_GPIO_INTR_ATYPE2      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE2)
-#define V_GPIO_INTR_ATYPE2(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE2)
-#define G_GPIO_INTR_ATYPE2(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE2, M_GPIO_INTR_ATYPE2)
-
-#define S_GPIO_INTR_ATYPE4      4
-#define M_GPIO_INTR_ATYPE4      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE4)
-#define V_GPIO_INTR_ATYPE4(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE4)
-#define G_GPIO_INTR_ATYPE4(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE4, M_GPIO_INTR_ATYPE4)
-
-#define S_GPIO_INTR_ATYPE6      6
-#define M_GPIO_INTR_ATYPE6      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE6)
-#define V_GPIO_INTR_ATYPE6(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE6)
-#define G_GPIO_INTR_ATYPE6(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE6, M_GPIO_INTR_ATYPE6)
-
-#define S_GPIO_INTR_ATYPE8      8
-#define M_GPIO_INTR_ATYPE8      _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE8)
-#define V_GPIO_INTR_ATYPE8(x)   _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE8)
-#define G_GPIO_INTR_ATYPE8(x)   _SB_GETVALUE(x, S_GPIO_INTR_ATYPE8, M_GPIO_INTR_ATYPE8)
-
-#define S_GPIO_INTR_ATYPE10     10
-#define M_GPIO_INTR_ATYPE10     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE10)
-#define V_GPIO_INTR_ATYPE10(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE10)
-#define G_GPIO_INTR_ATYPE10(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE10, M_GPIO_INTR_ATYPE10)
-
-#define S_GPIO_INTR_ATYPE12     12
-#define M_GPIO_INTR_ATYPE12     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE12)
-#define V_GPIO_INTR_ATYPE12(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE12)
-#define G_GPIO_INTR_ATYPE12(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE12, M_GPIO_INTR_ATYPE12)
-
-#define S_GPIO_INTR_ATYPE14     14
-#define M_GPIO_INTR_ATYPE14     _SB_MAKEMASK(2, S_GPIO_INTR_ATYPE14)
-#define V_GPIO_INTR_ATYPE14(x)  _SB_MAKEVALUE(x, S_GPIO_INTR_ATYPE14)
-#define G_GPIO_INTR_ATYPE14(x)  _SB_GETVALUE(x, S_GPIO_INTR_ATYPE14, M_GPIO_INTR_ATYPE14)
-#endif
-
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_int.h b/include/asm-mips/sibyte/sb1250_int.h
deleted file mode 100644
index f2850b4bcfd4..000000000000
--- a/include/asm-mips/sibyte/sb1250_int.h
+++ /dev/null
@@ -1,248 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  Interrupt Mapper definitions             File: sb1250_int.h
-    *
-    *  This module contains constants for manipulating the SB1250's
-    *  interrupt mapper and definitions for the interrupt sources.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000, 2001, 2002, 2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_INT_H
-#define _SB1250_INT_H
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  Interrupt Mapper Constants
-    ********************************************************************* */
-
-/*
- * Interrupt sources (Table 4-8, UM 0.2)
- *
- * First, the interrupt numbers.
- */
-
-#define K_INT_SOURCES               64
-
-#define K_INT_WATCHDOG_TIMER_0      0
-#define K_INT_WATCHDOG_TIMER_1      1
-#define K_INT_TIMER_0               2
-#define K_INT_TIMER_1               3
-#define K_INT_TIMER_2               4
-#define K_INT_TIMER_3               5
-#define K_INT_SMB_0                 6
-#define K_INT_SMB_1                 7
-#define K_INT_UART_0                8
-#define K_INT_UART_1                9
-#define K_INT_SER_0                 10
-#define K_INT_SER_1                 11
-#define K_INT_PCMCIA                12
-#define K_INT_ADDR_TRAP             13
-#define K_INT_PERF_CNT              14
-#define K_INT_TRACE_FREEZE          15
-#define K_INT_BAD_ECC               16
-#define K_INT_COR_ECC               17
-#define K_INT_IO_BUS                18
-#define K_INT_MAC_0                 19
-#define K_INT_MAC_1                 20
-#define K_INT_MAC_2                 21
-#define K_INT_DM_CH_0               22
-#define K_INT_DM_CH_1               23
-#define K_INT_DM_CH_2               24
-#define K_INT_DM_CH_3               25
-#define K_INT_MBOX_0                26
-#define K_INT_MBOX_1                27
-#define K_INT_MBOX_2                28
-#define K_INT_MBOX_3                29
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define K_INT_CYCLE_CP0_INT         30
-#define K_INT_CYCLE_CP1_INT         31
-#endif /* 1250 PASS2 || 112x PASS1 */
-#define K_INT_GPIO_0                32
-#define K_INT_GPIO_1                33
-#define K_INT_GPIO_2                34
-#define K_INT_GPIO_3                35
-#define K_INT_GPIO_4                36
-#define K_INT_GPIO_5                37
-#define K_INT_GPIO_6                38
-#define K_INT_GPIO_7                39
-#define K_INT_GPIO_8                40
-#define K_INT_GPIO_9                41
-#define K_INT_GPIO_10               42
-#define K_INT_GPIO_11               43
-#define K_INT_GPIO_12               44
-#define K_INT_GPIO_13               45
-#define K_INT_GPIO_14               46
-#define K_INT_GPIO_15               47
-#define K_INT_LDT_FATAL             48
-#define K_INT_LDT_NONFATAL          49
-#define K_INT_LDT_SMI               50
-#define K_INT_LDT_NMI               51
-#define K_INT_LDT_INIT              52
-#define K_INT_LDT_STARTUP           53
-#define K_INT_LDT_EXT               54
-#define K_INT_PCI_ERROR             55
-#define K_INT_PCI_INTA              56
-#define K_INT_PCI_INTB              57
-#define K_INT_PCI_INTC              58
-#define K_INT_PCI_INTD              59
-#define K_INT_SPARE_2               60
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define K_INT_MAC_0_CH1             61
-#define K_INT_MAC_1_CH1             62
-#define K_INT_MAC_2_CH1             63
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-/*
- * Mask values for each interrupt
- */
-
-#define M_INT_WATCHDOG_TIMER_0      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_0)
-#define M_INT_WATCHDOG_TIMER_1      _SB_MAKEMASK1(K_INT_WATCHDOG_TIMER_1)
-#define M_INT_TIMER_0               _SB_MAKEMASK1(K_INT_TIMER_0)
-#define M_INT_TIMER_1               _SB_MAKEMASK1(K_INT_TIMER_1)
-#define M_INT_TIMER_2               _SB_MAKEMASK1(K_INT_TIMER_2)
-#define M_INT_TIMER_3               _SB_MAKEMASK1(K_INT_TIMER_3)
-#define M_INT_SMB_0                 _SB_MAKEMASK1(K_INT_SMB_0)
-#define M_INT_SMB_1                 _SB_MAKEMASK1(K_INT_SMB_1)
-#define M_INT_UART_0                _SB_MAKEMASK1(K_INT_UART_0)
-#define M_INT_UART_1                _SB_MAKEMASK1(K_INT_UART_1)
-#define M_INT_SER_0                 _SB_MAKEMASK1(K_INT_SER_0)
-#define M_INT_SER_1                 _SB_MAKEMASK1(K_INT_SER_1)
-#define M_INT_PCMCIA                _SB_MAKEMASK1(K_INT_PCMCIA)
-#define M_INT_ADDR_TRAP             _SB_MAKEMASK1(K_INT_ADDR_TRAP)
-#define M_INT_PERF_CNT              _SB_MAKEMASK1(K_INT_PERF_CNT)
-#define M_INT_TRACE_FREEZE          _SB_MAKEMASK1(K_INT_TRACE_FREEZE)
-#define M_INT_BAD_ECC               _SB_MAKEMASK1(K_INT_BAD_ECC)
-#define M_INT_COR_ECC               _SB_MAKEMASK1(K_INT_COR_ECC)
-#define M_INT_IO_BUS                _SB_MAKEMASK1(K_INT_IO_BUS)
-#define M_INT_MAC_0                 _SB_MAKEMASK1(K_INT_MAC_0)
-#define M_INT_MAC_1                 _SB_MAKEMASK1(K_INT_MAC_1)
-#define M_INT_MAC_2                 _SB_MAKEMASK1(K_INT_MAC_2)
-#define M_INT_DM_CH_0               _SB_MAKEMASK1(K_INT_DM_CH_0)
-#define M_INT_DM_CH_1               _SB_MAKEMASK1(K_INT_DM_CH_1)
-#define M_INT_DM_CH_2               _SB_MAKEMASK1(K_INT_DM_CH_2)
-#define M_INT_DM_CH_3               _SB_MAKEMASK1(K_INT_DM_CH_3)
-#define M_INT_MBOX_0                _SB_MAKEMASK1(K_INT_MBOX_0)
-#define M_INT_MBOX_1                _SB_MAKEMASK1(K_INT_MBOX_1)
-#define M_INT_MBOX_2                _SB_MAKEMASK1(K_INT_MBOX_2)
-#define M_INT_MBOX_3                _SB_MAKEMASK1(K_INT_MBOX_3)
-#define M_INT_MBOX_ALL              _SB_MAKEMASK(4, K_INT_MBOX_0)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_INT_CYCLE_CP0_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP0_INT)
-#define M_INT_CYCLE_CP1_INT         _SB_MAKEMASK1(K_INT_CYCLE_CP1_INT)
-#endif /* 1250 PASS2 || 112x PASS1 */
-#define M_INT_GPIO_0                _SB_MAKEMASK1(K_INT_GPIO_0)
-#define M_INT_GPIO_1                _SB_MAKEMASK1(K_INT_GPIO_1)
-#define M_INT_GPIO_2                _SB_MAKEMASK1(K_INT_GPIO_2)
-#define M_INT_GPIO_3                _SB_MAKEMASK1(K_INT_GPIO_3)
-#define M_INT_GPIO_4                _SB_MAKEMASK1(K_INT_GPIO_4)
-#define M_INT_GPIO_5                _SB_MAKEMASK1(K_INT_GPIO_5)
-#define M_INT_GPIO_6                _SB_MAKEMASK1(K_INT_GPIO_6)
-#define M_INT_GPIO_7                _SB_MAKEMASK1(K_INT_GPIO_7)
-#define M_INT_GPIO_8                _SB_MAKEMASK1(K_INT_GPIO_8)
-#define M_INT_GPIO_9                _SB_MAKEMASK1(K_INT_GPIO_9)
-#define M_INT_GPIO_10               _SB_MAKEMASK1(K_INT_GPIO_10)
-#define M_INT_GPIO_11               _SB_MAKEMASK1(K_INT_GPIO_11)
-#define M_INT_GPIO_12               _SB_MAKEMASK1(K_INT_GPIO_12)
-#define M_INT_GPIO_13               _SB_MAKEMASK1(K_INT_GPIO_13)
-#define M_INT_GPIO_14               _SB_MAKEMASK1(K_INT_GPIO_14)
-#define M_INT_GPIO_15               _SB_MAKEMASK1(K_INT_GPIO_15)
-#define M_INT_LDT_FATAL             _SB_MAKEMASK1(K_INT_LDT_FATAL)
-#define M_INT_LDT_NONFATAL          _SB_MAKEMASK1(K_INT_LDT_NONFATAL)
-#define M_INT_LDT_SMI               _SB_MAKEMASK1(K_INT_LDT_SMI)
-#define M_INT_LDT_NMI               _SB_MAKEMASK1(K_INT_LDT_NMI)
-#define M_INT_LDT_INIT              _SB_MAKEMASK1(K_INT_LDT_INIT)
-#define M_INT_LDT_STARTUP           _SB_MAKEMASK1(K_INT_LDT_STARTUP)
-#define M_INT_LDT_EXT               _SB_MAKEMASK1(K_INT_LDT_EXT)
-#define M_INT_PCI_ERROR             _SB_MAKEMASK1(K_INT_PCI_ERROR)
-#define M_INT_PCI_INTA              _SB_MAKEMASK1(K_INT_PCI_INTA)
-#define M_INT_PCI_INTB              _SB_MAKEMASK1(K_INT_PCI_INTB)
-#define M_INT_PCI_INTC              _SB_MAKEMASK1(K_INT_PCI_INTC)
-#define M_INT_PCI_INTD              _SB_MAKEMASK1(K_INT_PCI_INTD)
-#define M_INT_SPARE_2               _SB_MAKEMASK1(K_INT_SPARE_2)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_INT_MAC_0_CH1             _SB_MAKEMASK1(K_INT_MAC_0_CH1)
-#define M_INT_MAC_1_CH1             _SB_MAKEMASK1(K_INT_MAC_1_CH1)
-#define M_INT_MAC_2_CH1             _SB_MAKEMASK1(K_INT_MAC_2_CH1)
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-/*
- * Interrupt mappings
- */
-
-#define K_INT_MAP_I0    0               /* interrupt pins on processor */
-#define K_INT_MAP_I1    1
-#define K_INT_MAP_I2    2
-#define K_INT_MAP_I3    3
-#define K_INT_MAP_I4    4
-#define K_INT_MAP_I5    5
-#define K_INT_MAP_NMI   6               /* nonmaskable */
-#define K_INT_MAP_DINT  7               /* debug interrupt */
-
-/*
- * LDT Interrupt Set Register (table 4-5)
- */
-
-#define S_INT_LDT_INTMSG              0
-#define M_INT_LDT_INTMSG              _SB_MAKEMASK(3, S_INT_LDT_INTMSG)
-#define V_INT_LDT_INTMSG(x)           _SB_MAKEVALUE(x, S_INT_LDT_INTMSG)
-#define G_INT_LDT_INTMSG(x)           _SB_GETVALUE(x, S_INT_LDT_INTMSG, M_INT_LDT_INTMSG)
-
-#define K_INT_LDT_INTMSG_FIXED        0
-#define K_INT_LDT_INTMSG_ARBITRATED   1
-#define K_INT_LDT_INTMSG_SMI          2
-#define K_INT_LDT_INTMSG_NMI          3
-#define K_INT_LDT_INTMSG_INIT         4
-#define K_INT_LDT_INTMSG_STARTUP      5
-#define K_INT_LDT_INTMSG_EXTINT       6
-#define K_INT_LDT_INTMSG_RESERVED     7
-
-#define M_INT_LDT_EDGETRIGGER         0
-#define M_INT_LDT_LEVELTRIGGER        _SB_MAKEMASK1(3)
-
-#define M_INT_LDT_PHYSICALDEST        0
-#define M_INT_LDT_LOGICALDEST         _SB_MAKEMASK1(4)
-
-#define S_INT_LDT_INTDEST             5
-#define M_INT_LDT_INTDEST             _SB_MAKEMASK(10, S_INT_LDT_INTDEST)
-#define V_INT_LDT_INTDEST(x)          _SB_MAKEVALUE(x, S_INT_LDT_INTDEST)
-#define G_INT_LDT_INTDEST(x)          _SB_GETVALUE(x, S_INT_LDT_INTDEST, M_INT_LDT_INTDEST)
-
-#define S_INT_LDT_VECTOR              13
-#define M_INT_LDT_VECTOR              _SB_MAKEMASK(8, S_INT_LDT_VECTOR)
-#define V_INT_LDT_VECTOR(x)           _SB_MAKEVALUE(x, S_INT_LDT_VECTOR)
-#define G_INT_LDT_VECTOR(x)           _SB_GETVALUE(x, S_INT_LDT_VECTOR, M_INT_LDT_VECTOR)
-
-/*
- * Vector format (Table 4-6)
- */
-
-#define M_LDTVECT_RAISEINT              0x00
-#define M_LDTVECT_RAISEMBOX             0x40
-
-
-#endif  /* 1250/112x */
diff --git a/include/asm-mips/sibyte/sb1250_l2c.h b/include/asm-mips/sibyte/sb1250_l2c.h
deleted file mode 100644
index 6554dcf05cfe..000000000000
--- a/include/asm-mips/sibyte/sb1250_l2c.h
+++ /dev/null
@@ -1,131 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  L2 Cache constants and macros            File: sb1250_l2c.h
-    *
-    *  This module contains constants useful for manipulating the
-    *  level 2 cache.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_L2C_H
-#define _SB1250_L2C_H
-
-#include "sb1250_defs.h"
-
-/*
- * Level 2 Cache Tag register (Table 5-3)
- */
-
-#define S_L2C_TAG_MBZ               0
-#define M_L2C_TAG_MBZ               _SB_MAKEMASK(5, S_L2C_TAG_MBZ)
-
-#define S_L2C_TAG_INDEX             5
-#define M_L2C_TAG_INDEX             _SB_MAKEMASK(12, S_L2C_TAG_INDEX)
-#define V_L2C_TAG_INDEX(x)          _SB_MAKEVALUE(x, S_L2C_TAG_INDEX)
-#define G_L2C_TAG_INDEX(x)          _SB_GETVALUE(x, S_L2C_TAG_INDEX, M_L2C_TAG_INDEX)
-
-#define S_L2C_TAG_TAG               17
-#define M_L2C_TAG_TAG               _SB_MAKEMASK(23, S_L2C_TAG_TAG)
-#define V_L2C_TAG_TAG(x)            _SB_MAKEVALUE(x, S_L2C_TAG_TAG)
-#define G_L2C_TAG_TAG(x)            _SB_GETVALUE(x, S_L2C_TAG_TAG, M_L2C_TAG_TAG)
-
-#define S_L2C_TAG_ECC               40
-#define M_L2C_TAG_ECC               _SB_MAKEMASK(6, S_L2C_TAG_ECC)
-#define V_L2C_TAG_ECC(x)            _SB_MAKEVALUE(x, S_L2C_TAG_ECC)
-#define G_L2C_TAG_ECC(x)            _SB_GETVALUE(x, S_L2C_TAG_ECC, M_L2C_TAG_ECC)
-
-#define S_L2C_TAG_WAY               46
-#define M_L2C_TAG_WAY               _SB_MAKEMASK(2, S_L2C_TAG_WAY)
-#define V_L2C_TAG_WAY(x)            _SB_MAKEVALUE(x, S_L2C_TAG_WAY)
-#define G_L2C_TAG_WAY(x)            _SB_GETVALUE(x, S_L2C_TAG_WAY, M_L2C_TAG_WAY)
-
-#define M_L2C_TAG_DIRTY             _SB_MAKEMASK1(48)
-#define M_L2C_TAG_VALID             _SB_MAKEMASK1(49)
-
-/*
- * Format of level 2 cache management address (table 5-2)
- */
-
-#define S_L2C_MGMT_INDEX            5
-#define M_L2C_MGMT_INDEX            _SB_MAKEMASK(12, S_L2C_MGMT_INDEX)
-#define V_L2C_MGMT_INDEX(x)         _SB_MAKEVALUE(x, S_L2C_MGMT_INDEX)
-#define G_L2C_MGMT_INDEX(x)         _SB_GETVALUE(x, S_L2C_MGMT_INDEX, M_L2C_MGMT_INDEX)
-
-#define S_L2C_MGMT_QUADRANT         15
-#define M_L2C_MGMT_QUADRANT         _SB_MAKEMASK(2, S_L2C_MGMT_QUADRANT)
-#define V_L2C_MGMT_QUADRANT(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_QUADRANT)
-#define G_L2C_MGMT_QUADRANT(x)      _SB_GETVALUE(x, S_L2C_MGMT_QUADRANT, M_L2C_MGMT_QUADRANT)
-
-#define S_L2C_MGMT_HALF             16
-#define M_L2C_MGMT_HALF             _SB_MAKEMASK(1, S_L2C_MGMT_HALF)
-
-#define S_L2C_MGMT_WAY              17
-#define M_L2C_MGMT_WAY              _SB_MAKEMASK(2, S_L2C_MGMT_WAY)
-#define V_L2C_MGMT_WAY(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_WAY)
-#define G_L2C_MGMT_WAY(x)           _SB_GETVALUE(x, S_L2C_MGMT_WAY, M_L2C_MGMT_WAY)
-
-#define S_L2C_MGMT_ECC_DIAG         21
-#define M_L2C_MGMT_ECC_DIAG         _SB_MAKEMASK(2, S_L2C_MGMT_ECC_DIAG)
-#define V_L2C_MGMT_ECC_DIAG(x)      _SB_MAKEVALUE(x, S_L2C_MGMT_ECC_DIAG)
-#define G_L2C_MGMT_ECC_DIAG(x)      _SB_GETVALUE(x, S_L2C_MGMT_ECC_DIAG, M_L2C_MGMT_ECC_DIAG)
-
-#define S_L2C_MGMT_TAG              23
-#define M_L2C_MGMT_TAG              _SB_MAKEMASK(4, S_L2C_MGMT_TAG)
-#define V_L2C_MGMT_TAG(x)           _SB_MAKEVALUE(x, S_L2C_MGMT_TAG)
-#define G_L2C_MGMT_TAG(x)           _SB_GETVALUE(x, S_L2C_MGMT_TAG, M_L2C_MGMT_TAG)
-
-#define M_L2C_MGMT_DIRTY            _SB_MAKEMASK1(19)
-#define M_L2C_MGMT_VALID            _SB_MAKEMASK1(20)
-
-#define A_L2C_MGMT_TAG_BASE         0x00D0000000
-
-#define L2C_ENTRIES_PER_WAY       4096
-#define L2C_NUM_WAYS              4
-
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-/*
- * L2 Read Misc. register (A_L2_READ_MISC)
- */
-#define S_L2C_MISC_NO_WAY               10
-#define M_L2C_MISC_NO_WAY               _SB_MAKEMASK(4, S_L2C_MISC_NO_WAY)
-#define V_L2C_MISC_NO_WAY(x)            _SB_MAKEVALUE(x, S_L2C_MISC_NO_WAY)
-#define G_L2C_MISC_NO_WAY(x)            _SB_GETVALUE(x, S_L2C_MISC_NO_WAY, M_L2C_MISC_NO_WAY)
-
-#define M_L2C_MISC_ECC_CLEANUP_DIS      _SB_MAKEMASK1(9)
-#define M_L2C_MISC_MC_PRIO_LOW          _SB_MAKEMASK1(8)
-#define M_L2C_MISC_SOFT_DISABLE_T       _SB_MAKEMASK1(7)
-#define M_L2C_MISC_SOFT_DISABLE_B       _SB_MAKEMASK1(6)
-#define M_L2C_MISC_SOFT_DISABLE_R       _SB_MAKEMASK1(5)
-#define M_L2C_MISC_SOFT_DISABLE_L       _SB_MAKEMASK1(4)
-#define M_L2C_MISC_SCACHE_DISABLE_T     _SB_MAKEMASK1(3)
-#define M_L2C_MISC_SCACHE_DISABLE_B     _SB_MAKEMASK1(2)
-#define M_L2C_MISC_SCACHE_DISABLE_R     _SB_MAKEMASK1(1)
-#define M_L2C_MISC_SCACHE_DISABLE_L     _SB_MAKEMASK1(0)
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_ldt.h b/include/asm-mips/sibyte/sb1250_ldt.h
deleted file mode 100644
index 081e8b1c4ad0..000000000000
--- a/include/asm-mips/sibyte/sb1250_ldt.h
+++ /dev/null
@@ -1,423 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  LDT constants                            File: sb1250_ldt.h
-    *
-    *  This module contains constants and macros to describe
-    *  the LDT interface on the SB1250.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000, 2001, 2002, 2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_LDT_H
-#define _SB1250_LDT_H
-
-#include "sb1250_defs.h"
-
-#define K_LDT_VENDOR_SIBYTE     0x166D
-#define K_LDT_DEVICE_SB1250     0x0002
-
-/*
- * LDT Interface Type 1 (bridge) configuration header
- */
-
-#define R_LDT_TYPE1_DEVICEID    0x0000
-#define R_LDT_TYPE1_CMDSTATUS   0x0004
-#define R_LDT_TYPE1_CLASSREV    0x0008
-#define R_LDT_TYPE1_DEVHDR      0x000C
-#define R_LDT_TYPE1_BAR0        0x0010  /* not used */
-#define R_LDT_TYPE1_BAR1        0x0014  /* not used */
-
-#define R_LDT_TYPE1_BUSID       0x0018  /* bus ID register */
-#define R_LDT_TYPE1_SECSTATUS   0x001C  /* secondary status / I/O base/limit */
-#define R_LDT_TYPE1_MEMLIMIT    0x0020
-#define R_LDT_TYPE1_PREFETCH    0x0024
-#define R_LDT_TYPE1_PREF_BASE   0x0028
-#define R_LDT_TYPE1_PREF_LIMIT  0x002C
-#define R_LDT_TYPE1_IOLIMIT     0x0030
-#define R_LDT_TYPE1_CAPPTR      0x0034
-#define R_LDT_TYPE1_ROMADDR     0x0038
-#define R_LDT_TYPE1_BRCTL       0x003C
-#define R_LDT_TYPE1_CMD         0x0040
-#define R_LDT_TYPE1_LINKCTRL    0x0044
-#define R_LDT_TYPE1_LINKFREQ    0x0048
-#define R_LDT_TYPE1_RESERVED1   0x004C
-#define R_LDT_TYPE1_SRICMD      0x0050
-#define R_LDT_TYPE1_SRITXNUM    0x0054
-#define R_LDT_TYPE1_SRIRXNUM    0x0058
-#define R_LDT_TYPE1_ERRSTATUS   0x0068
-#define R_LDT_TYPE1_SRICTRL     0x006C
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define R_LDT_TYPE1_ADDSTATUS   0x0070
-#endif /* 1250 PASS2 || 112x PASS1 */
-#define R_LDT_TYPE1_TXBUFCNT    0x00C8
-#define R_LDT_TYPE1_EXPCRC      0x00DC
-#define R_LDT_TYPE1_RXCRC       0x00F0
-
-
-/*
- * LDT Device ID register
- */
-
-#define S_LDT_DEVICEID_VENDOR           0
-#define M_LDT_DEVICEID_VENDOR           _SB_MAKEMASK_32(16, S_LDT_DEVICEID_VENDOR)
-#define V_LDT_DEVICEID_VENDOR(x)        _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_VENDOR)
-#define G_LDT_DEVICEID_VENDOR(x)        _SB_GETVALUE_32(x, S_LDT_DEVICEID_VENDOR, M_LDT_DEVICEID_VENDOR)
-
-#define S_LDT_DEVICEID_DEVICEID         16
-#define M_LDT_DEVICEID_DEVICEID         _SB_MAKEMASK_32(16, S_LDT_DEVICEID_DEVICEID)
-#define V_LDT_DEVICEID_DEVICEID(x)      _SB_MAKEVALUE_32(x, S_LDT_DEVICEID_DEVICEID)
-#define G_LDT_DEVICEID_DEVICEID(x)      _SB_GETVALUE_32(x, S_LDT_DEVICEID_DEVICEID, M_LDT_DEVICEID_DEVICEID)
-
-
-/*
- * LDT Command Register (Table 8-13)
- */
-
-#define M_LDT_CMD_IOSPACE_EN            _SB_MAKEMASK1_32(0)
-#define M_LDT_CMD_MEMSPACE_EN           _SB_MAKEMASK1_32(1)
-#define M_LDT_CMD_MASTER_EN             _SB_MAKEMASK1_32(2)
-#define M_LDT_CMD_SPECCYC_EN            _SB_MAKEMASK1_32(3)
-#define M_LDT_CMD_MEMWRINV_EN           _SB_MAKEMASK1_32(4)
-#define M_LDT_CMD_VGAPALSNP_EN          _SB_MAKEMASK1_32(5)
-#define M_LDT_CMD_PARERRRESP            _SB_MAKEMASK1_32(6)
-#define M_LDT_CMD_WAITCYCCTRL           _SB_MAKEMASK1_32(7)
-#define M_LDT_CMD_SERR_EN               _SB_MAKEMASK1_32(8)
-#define M_LDT_CMD_FASTB2B_EN            _SB_MAKEMASK1_32(9)
-
-/*
- * LDT class and revision registers
- */
-
-#define S_LDT_CLASSREV_REV              0
-#define M_LDT_CLASSREV_REV              _SB_MAKEMASK_32(8, S_LDT_CLASSREV_REV)
-#define V_LDT_CLASSREV_REV(x)           _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_REV)
-#define G_LDT_CLASSREV_REV(x)           _SB_GETVALUE_32(x, S_LDT_CLASSREV_REV, M_LDT_CLASSREV_REV)
-
-#define S_LDT_CLASSREV_CLASS            8
-#define M_LDT_CLASSREV_CLASS            _SB_MAKEMASK_32(24, S_LDT_CLASSREV_CLASS)
-#define V_LDT_CLASSREV_CLASS(x)         _SB_MAKEVALUE_32(x, S_LDT_CLASSREV_CLASS)
-#define G_LDT_CLASSREV_CLASS(x)         _SB_GETVALUE_32(x, S_LDT_CLASSREV_CLASS, M_LDT_CLASSREV_CLASS)
-
-#define K_LDT_REV                       0x01
-#define K_LDT_CLASS                     0x060000
-
-/*
- * Device Header (offset 0x0C)
- */
-
-#define S_LDT_DEVHDR_CLINESZ            0
-#define M_LDT_DEVHDR_CLINESZ            _SB_MAKEMASK_32(8, S_LDT_DEVHDR_CLINESZ)
-#define V_LDT_DEVHDR_CLINESZ(x)         _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_CLINESZ)
-#define G_LDT_DEVHDR_CLINESZ(x)         _SB_GETVALUE_32(x, S_LDT_DEVHDR_CLINESZ, M_LDT_DEVHDR_CLINESZ)
-
-#define S_LDT_DEVHDR_LATTMR             8
-#define M_LDT_DEVHDR_LATTMR             _SB_MAKEMASK_32(8, S_LDT_DEVHDR_LATTMR)
-#define V_LDT_DEVHDR_LATTMR(x)          _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_LATTMR)
-#define G_LDT_DEVHDR_LATTMR(x)          _SB_GETVALUE_32(x, S_LDT_DEVHDR_LATTMR, M_LDT_DEVHDR_LATTMR)
-
-#define S_LDT_DEVHDR_HDRTYPE            16
-#define M_LDT_DEVHDR_HDRTYPE            _SB_MAKEMASK_32(8, S_LDT_DEVHDR_HDRTYPE)
-#define V_LDT_DEVHDR_HDRTYPE(x)         _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_HDRTYPE)
-#define G_LDT_DEVHDR_HDRTYPE(x)         _SB_GETVALUE_32(x, S_LDT_DEVHDR_HDRTYPE, M_LDT_DEVHDR_HDRTYPE)
-
-#define K_LDT_DEVHDR_HDRTYPE_TYPE1      1
-
-#define S_LDT_DEVHDR_BIST               24
-#define M_LDT_DEVHDR_BIST               _SB_MAKEMASK_32(8, S_LDT_DEVHDR_BIST)
-#define V_LDT_DEVHDR_BIST(x)            _SB_MAKEVALUE_32(x, S_LDT_DEVHDR_BIST)
-#define G_LDT_DEVHDR_BIST(x)            _SB_GETVALUE_32(x, S_LDT_DEVHDR_BIST, M_LDT_DEVHDR_BIST)
-
-
-
-/*
- * LDT Status Register (Table 8-14).  Note that these constants
- * assume you've read the command and status register
- * together (32-bit read at offset 0x04)
- *
- * These bits also apply to the secondary status
- * register (Table 8-15), offset 0x1C
- */
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_LDT_STATUS_VGAEN              _SB_MAKEMASK1_32(3)
-#endif /* 1250 PASS2 || 112x PASS1 */
-#define M_LDT_STATUS_CAPLIST            _SB_MAKEMASK1_32(20)
-#define M_LDT_STATUS_66MHZCAP           _SB_MAKEMASK1_32(21)
-#define M_LDT_STATUS_RESERVED2          _SB_MAKEMASK1_32(22)
-#define M_LDT_STATUS_FASTB2BCAP         _SB_MAKEMASK1_32(23)
-#define M_LDT_STATUS_MSTRDPARERR        _SB_MAKEMASK1_32(24)
-
-#define S_LDT_STATUS_DEVSELTIMING       25
-#define M_LDT_STATUS_DEVSELTIMING       _SB_MAKEMASK_32(2, S_LDT_STATUS_DEVSELTIMING)
-#define V_LDT_STATUS_DEVSELTIMING(x)    _SB_MAKEVALUE_32(x, S_LDT_STATUS_DEVSELTIMING)
-#define G_LDT_STATUS_DEVSELTIMING(x)    _SB_GETVALUE_32(x, S_LDT_STATUS_DEVSELTIMING, M_LDT_STATUS_DEVSELTIMING)
-
-#define M_LDT_STATUS_SIGDTGTABORT       _SB_MAKEMASK1_32(27)
-#define M_LDT_STATUS_RCVDTGTABORT       _SB_MAKEMASK1_32(28)
-#define M_LDT_STATUS_RCVDMSTRABORT      _SB_MAKEMASK1_32(29)
-#define M_LDT_STATUS_SIGDSERR           _SB_MAKEMASK1_32(30)
-#define M_LDT_STATUS_DETPARERR          _SB_MAKEMASK1_32(31)
-
-/*
- * Bridge Control Register (Table 8-16).  Note that these
- * constants assume you've read the register as a 32-bit
- * read (offset 0x3C)
- */
-
-#define M_LDT_BRCTL_PARERRRESP_EN       _SB_MAKEMASK1_32(16)
-#define M_LDT_BRCTL_SERR_EN             _SB_MAKEMASK1_32(17)
-#define M_LDT_BRCTL_ISA_EN              _SB_MAKEMASK1_32(18)
-#define M_LDT_BRCTL_VGA_EN              _SB_MAKEMASK1_32(19)
-#define M_LDT_BRCTL_MSTRABORTMODE       _SB_MAKEMASK1_32(21)
-#define M_LDT_BRCTL_SECBUSRESET         _SB_MAKEMASK1_32(22)
-#define M_LDT_BRCTL_FASTB2B_EN          _SB_MAKEMASK1_32(23)
-#define M_LDT_BRCTL_PRIDISCARD          _SB_MAKEMASK1_32(24)
-#define M_LDT_BRCTL_SECDISCARD          _SB_MAKEMASK1_32(25)
-#define M_LDT_BRCTL_DISCARDSTAT         _SB_MAKEMASK1_32(26)
-#define M_LDT_BRCTL_DISCARDSERR_EN      _SB_MAKEMASK1_32(27)
-
-/*
- * LDT Command Register (Table 8-17).  Note that these constants
- * assume you've read the command and status register together
- * 32-bit read at offset 0x40
- */
-
-#define M_LDT_CMD_WARMRESET             _SB_MAKEMASK1_32(16)
-#define M_LDT_CMD_DOUBLEENDED           _SB_MAKEMASK1_32(17)
-
-#define S_LDT_CMD_CAPTYPE               29
-#define M_LDT_CMD_CAPTYPE               _SB_MAKEMASK_32(3, S_LDT_CMD_CAPTYPE)
-#define V_LDT_CMD_CAPTYPE(x)            _SB_MAKEVALUE_32(x, S_LDT_CMD_CAPTYPE)
-#define G_LDT_CMD_CAPTYPE(x)            _SB_GETVALUE_32(x, S_LDT_CMD_CAPTYPE, M_LDT_CMD_CAPTYPE)
-
-/*
- * LDT link control register (Table 8-18), and (Table 8-19)
- */
-
-#define M_LDT_LINKCTRL_CAPSYNCFLOOD_EN  _SB_MAKEMASK1_32(1)
-#define M_LDT_LINKCTRL_CRCSTARTTEST     _SB_MAKEMASK1_32(2)
-#define M_LDT_LINKCTRL_CRCFORCEERR      _SB_MAKEMASK1_32(3)
-#define M_LDT_LINKCTRL_LINKFAIL         _SB_MAKEMASK1_32(4)
-#define M_LDT_LINKCTRL_INITDONE         _SB_MAKEMASK1_32(5)
-#define M_LDT_LINKCTRL_EOC              _SB_MAKEMASK1_32(6)
-#define M_LDT_LINKCTRL_XMITOFF          _SB_MAKEMASK1_32(7)
-
-#define S_LDT_LINKCTRL_CRCERR           8
-#define M_LDT_LINKCTRL_CRCERR           _SB_MAKEMASK_32(4, S_LDT_LINKCTRL_CRCERR)
-#define V_LDT_LINKCTRL_CRCERR(x)        _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_CRCERR)
-#define G_LDT_LINKCTRL_CRCERR(x)        _SB_GETVALUE_32(x, S_LDT_LINKCTRL_CRCERR, M_LDT_LINKCTRL_CRCERR)
-
-#define S_LDT_LINKCTRL_MAXIN            16
-#define M_LDT_LINKCTRL_MAXIN            _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXIN)
-#define V_LDT_LINKCTRL_MAXIN(x)         _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXIN)
-#define G_LDT_LINKCTRL_MAXIN(x)         _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXIN, M_LDT_LINKCTRL_MAXIN)
-
-#define M_LDT_LINKCTRL_DWFCLN           _SB_MAKEMASK1_32(19)
-
-#define S_LDT_LINKCTRL_MAXOUT           20
-#define M_LDT_LINKCTRL_MAXOUT           _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_MAXOUT)
-#define V_LDT_LINKCTRL_MAXOUT(x)        _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_MAXOUT)
-#define G_LDT_LINKCTRL_MAXOUT(x)        _SB_GETVALUE_32(x, S_LDT_LINKCTRL_MAXOUT, M_LDT_LINKCTRL_MAXOUT)
-
-#define M_LDT_LINKCTRL_DWFCOUT          _SB_MAKEMASK1_32(23)
-
-#define S_LDT_LINKCTRL_WIDTHIN          24
-#define M_LDT_LINKCTRL_WIDTHIN          _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHIN)
-#define V_LDT_LINKCTRL_WIDTHIN(x)       _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN)
-#define G_LDT_LINKCTRL_WIDTHIN(x)       _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHIN, M_LDT_LINKCTRL_WIDTHIN)
-
-#define M_LDT_LINKCTRL_DWFCLIN_EN       _SB_MAKEMASK1_32(27)
-
-#define S_LDT_LINKCTRL_WIDTHOUT         28
-#define M_LDT_LINKCTRL_WIDTHOUT         _SB_MAKEMASK_32(3, S_LDT_LINKCTRL_WIDTHOUT)
-#define V_LDT_LINKCTRL_WIDTHOUT(x)      _SB_MAKEVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT)
-#define G_LDT_LINKCTRL_WIDTHOUT(x)      _SB_GETVALUE_32(x, S_LDT_LINKCTRL_WIDTHOUT, M_LDT_LINKCTRL_WIDTHOUT)
-
-#define M_LDT_LINKCTRL_DWFCOUT_EN       _SB_MAKEMASK1_32(31)
-
-/*
- * LDT Link frequency register  (Table 8-20) offset 0x48
- */
-
-#define S_LDT_LINKFREQ_FREQ             8
-#define M_LDT_LINKFREQ_FREQ             _SB_MAKEMASK_32(4, S_LDT_LINKFREQ_FREQ)
-#define V_LDT_LINKFREQ_FREQ(x)          _SB_MAKEVALUE_32(x, S_LDT_LINKFREQ_FREQ)
-#define G_LDT_LINKFREQ_FREQ(x)          _SB_GETVALUE_32(x, S_LDT_LINKFREQ_FREQ, M_LDT_LINKFREQ_FREQ)
-
-#define K_LDT_LINKFREQ_200MHZ           0
-#define K_LDT_LINKFREQ_300MHZ           1
-#define K_LDT_LINKFREQ_400MHZ           2
-#define K_LDT_LINKFREQ_500MHZ           3
-#define K_LDT_LINKFREQ_600MHZ           4
-#define K_LDT_LINKFREQ_800MHZ           5
-#define K_LDT_LINKFREQ_1000MHZ          6
-
-/*
- * LDT SRI Command Register (Table 8-21).  Note that these constants
- * assume you've read the command and status register together
- * 32-bit read at offset 0x50
- */
-
-#define M_LDT_SRICMD_SIPREADY           _SB_MAKEMASK1_32(16)
-#define M_LDT_SRICMD_SYNCPTRCTL         _SB_MAKEMASK1_32(17)
-#define M_LDT_SRICMD_REDUCESYNCZERO     _SB_MAKEMASK1_32(18)
-#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
-#define M_LDT_SRICMD_DISSTARVATIONCNT   _SB_MAKEMASK1_32(19)    /* PASS1 */
-#endif /* up to 1250 PASS1 */
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_LDT_SRICMD_DISMULTTXVLD       _SB_MAKEMASK1_32(19)
-#define M_LDT_SRICMD_EXPENDIAN          _SB_MAKEMASK1_32(26)
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-
-#define S_LDT_SRICMD_RXMARGIN           20
-#define M_LDT_SRICMD_RXMARGIN           _SB_MAKEMASK_32(5, S_LDT_SRICMD_RXMARGIN)
-#define V_LDT_SRICMD_RXMARGIN(x)        _SB_MAKEVALUE_32(x, S_LDT_SRICMD_RXMARGIN)
-#define G_LDT_SRICMD_RXMARGIN(x)        _SB_GETVALUE_32(x, S_LDT_SRICMD_RXMARGIN, M_LDT_SRICMD_RXMARGIN)
-
-#define M_LDT_SRICMD_LDTPLLCOMPAT       _SB_MAKEMASK1_32(25)
-
-#define S_LDT_SRICMD_TXINITIALOFFSET    28
-#define M_LDT_SRICMD_TXINITIALOFFSET    _SB_MAKEMASK_32(3, S_LDT_SRICMD_TXINITIALOFFSET)
-#define V_LDT_SRICMD_TXINITIALOFFSET(x) _SB_MAKEVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET)
-#define G_LDT_SRICMD_TXINITIALOFFSET(x) _SB_GETVALUE_32(x, S_LDT_SRICMD_TXINITIALOFFSET, M_LDT_SRICMD_TXINITIALOFFSET)
-
-#define M_LDT_SRICMD_LINKFREQDIRECT     _SB_MAKEMASK1_32(31)
-
-/*
- * LDT Error control and status register (Table 8-22) (Table 8-23)
- */
-
-#define M_LDT_ERRCTL_PROTFATAL_EN       _SB_MAKEMASK1_32(0)
-#define M_LDT_ERRCTL_PROTNONFATAL_EN    _SB_MAKEMASK1_32(1)
-#define M_LDT_ERRCTL_PROTSYNCFLOOD_EN   _SB_MAKEMASK1_32(2)
-#define M_LDT_ERRCTL_OVFFATAL_EN        _SB_MAKEMASK1_32(3)
-#define M_LDT_ERRCTL_OVFNONFATAL_EN     _SB_MAKEMASK1_32(4)
-#define M_LDT_ERRCTL_OVFSYNCFLOOD_EN    _SB_MAKEMASK1_32(5)
-#define M_LDT_ERRCTL_EOCNXAFATAL_EN     _SB_MAKEMASK1_32(6)
-#define M_LDT_ERRCTL_EOCNXANONFATAL_EN  _SB_MAKEMASK1_32(7)
-#define M_LDT_ERRCTL_EOCNXASYNCFLOOD_EN _SB_MAKEMASK1_32(8)
-#define M_LDT_ERRCTL_CRCFATAL_EN        _SB_MAKEMASK1_32(9)
-#define M_LDT_ERRCTL_CRCNONFATAL_EN     _SB_MAKEMASK1_32(10)
-#define M_LDT_ERRCTL_SERRFATAL_EN       _SB_MAKEMASK1_32(11)
-#define M_LDT_ERRCTL_SRCTAGFATAL_EN     _SB_MAKEMASK1_32(12)
-#define M_LDT_ERRCTL_SRCTAGNONFATAL_EN  _SB_MAKEMASK1_32(13)
-#define M_LDT_ERRCTL_SRCTAGSYNCFLOOD_EN _SB_MAKEMASK1_32(14)
-#define M_LDT_ERRCTL_MAPNXAFATAL_EN     _SB_MAKEMASK1_32(15)
-#define M_LDT_ERRCTL_MAPNXANONFATAL_EN  _SB_MAKEMASK1_32(16)
-#define M_LDT_ERRCTL_MAPNXASYNCFLOOD_EN _SB_MAKEMASK1_32(17)
-
-#define M_LDT_ERRCTL_PROTOERR           _SB_MAKEMASK1_32(24)
-#define M_LDT_ERRCTL_OVFERR             _SB_MAKEMASK1_32(25)
-#define M_LDT_ERRCTL_EOCNXAERR          _SB_MAKEMASK1_32(26)
-#define M_LDT_ERRCTL_SRCTAGERR          _SB_MAKEMASK1_32(27)
-#define M_LDT_ERRCTL_MAPNXAERR          _SB_MAKEMASK1_32(28)
-
-/*
- * SRI Control register (Table 8-24, 8-25)  Offset 0x6C
- */
-
-#define S_LDT_SRICTRL_NEEDRESP          0
-#define M_LDT_SRICTRL_NEEDRESP          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDRESP)
-#define V_LDT_SRICTRL_NEEDRESP(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDRESP)
-#define G_LDT_SRICTRL_NEEDRESP(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDRESP, M_LDT_SRICTRL_NEEDRESP)
-
-#define S_LDT_SRICTRL_NEEDNPREQ         2
-#define M_LDT_SRICTRL_NEEDNPREQ         _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDNPREQ)
-#define V_LDT_SRICTRL_NEEDNPREQ(x)      _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ)
-#define G_LDT_SRICTRL_NEEDNPREQ(x)      _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDNPREQ, M_LDT_SRICTRL_NEEDNPREQ)
-
-#define S_LDT_SRICTRL_NEEDPREQ          4
-#define M_LDT_SRICTRL_NEEDPREQ          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_NEEDPREQ)
-#define V_LDT_SRICTRL_NEEDPREQ(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ)
-#define G_LDT_SRICTRL_NEEDPREQ(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_NEEDPREQ, M_LDT_SRICTRL_NEEDPREQ)
-
-#define S_LDT_SRICTRL_WANTRESP          8
-#define M_LDT_SRICTRL_WANTRESP          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTRESP)
-#define V_LDT_SRICTRL_WANTRESP(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTRESP)
-#define G_LDT_SRICTRL_WANTRESP(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTRESP, M_LDT_SRICTRL_WANTRESP)
-
-#define S_LDT_SRICTRL_WANTNPREQ         10
-#define M_LDT_SRICTRL_WANTNPREQ         _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTNPREQ)
-#define V_LDT_SRICTRL_WANTNPREQ(x)      _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ)
-#define G_LDT_SRICTRL_WANTNPREQ(x)      _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTNPREQ, M_LDT_SRICTRL_WANTNPREQ)
-
-#define S_LDT_SRICTRL_WANTPREQ          12
-#define M_LDT_SRICTRL_WANTPREQ          _SB_MAKEMASK_32(2, S_LDT_SRICTRL_WANTPREQ)
-#define V_LDT_SRICTRL_WANTPREQ(x)       _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_WANTPREQ)
-#define G_LDT_SRICTRL_WANTPREQ(x)       _SB_GETVALUE_32(x, S_LDT_SRICTRL_WANTPREQ, M_LDT_SRICTRL_WANTPREQ)
-
-#define S_LDT_SRICTRL_BUFRELSPACE       16
-#define M_LDT_SRICTRL_BUFRELSPACE       _SB_MAKEMASK_32(4, S_LDT_SRICTRL_BUFRELSPACE)
-#define V_LDT_SRICTRL_BUFRELSPACE(x)    _SB_MAKEVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE)
-#define G_LDT_SRICTRL_BUFRELSPACE(x)    _SB_GETVALUE_32(x, S_LDT_SRICTRL_BUFRELSPACE, M_LDT_SRICTRL_BUFRELSPACE)
-
-/*
- * LDT SRI Transmit Buffer Count register (Table 8-26)
- */
-
-#define S_LDT_TXBUFCNT_PCMD             0
-#define M_LDT_TXBUFCNT_PCMD             _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PCMD)
-#define V_LDT_TXBUFCNT_PCMD(x)          _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PCMD)
-#define G_LDT_TXBUFCNT_PCMD(x)          _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PCMD, M_LDT_TXBUFCNT_PCMD)
-
-#define S_LDT_TXBUFCNT_PDATA            4
-#define M_LDT_TXBUFCNT_PDATA            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_PDATA)
-#define V_LDT_TXBUFCNT_PDATA(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_PDATA)
-#define G_LDT_TXBUFCNT_PDATA(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_PDATA, M_LDT_TXBUFCNT_PDATA)
-
-#define S_LDT_TXBUFCNT_NPCMD            8
-#define M_LDT_TXBUFCNT_NPCMD            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPCMD)
-#define V_LDT_TXBUFCNT_NPCMD(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPCMD)
-#define G_LDT_TXBUFCNT_NPCMD(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPCMD, M_LDT_TXBUFCNT_NPCMD)
-
-#define S_LDT_TXBUFCNT_NPDATA           12
-#define M_LDT_TXBUFCNT_NPDATA           _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_NPDATA)
-#define V_LDT_TXBUFCNT_NPDATA(x)        _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_NPDATA)
-#define G_LDT_TXBUFCNT_NPDATA(x)        _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_NPDATA, M_LDT_TXBUFCNT_NPDATA)
-
-#define S_LDT_TXBUFCNT_RCMD             16
-#define M_LDT_TXBUFCNT_RCMD             _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RCMD)
-#define V_LDT_TXBUFCNT_RCMD(x)          _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RCMD)
-#define G_LDT_TXBUFCNT_RCMD(x)          _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RCMD, M_LDT_TXBUFCNT_RCMD)
-
-#define S_LDT_TXBUFCNT_RDATA            20
-#define M_LDT_TXBUFCNT_RDATA            _SB_MAKEMASK_32(4, S_LDT_TXBUFCNT_RDATA)
-#define V_LDT_TXBUFCNT_RDATA(x)         _SB_MAKEVALUE_32(x, S_LDT_TXBUFCNT_RDATA)
-#define G_LDT_TXBUFCNT_RDATA(x)         _SB_GETVALUE_32(x, S_LDT_TXBUFCNT_RDATA, M_LDT_TXBUFCNT_RDATA)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-/*
- * Additional Status Register
- */
-
-#define S_LDT_ADDSTATUS_TGTDONE         0
-#define M_LDT_ADDSTATUS_TGTDONE         _SB_MAKEMASK_32(8, S_LDT_ADDSTATUS_TGTDONE)
-#define V_LDT_ADDSTATUS_TGTDONE(x)      _SB_MAKEVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE)
-#define G_LDT_ADDSTATUS_TGTDONE(x)      _SB_GETVALUE_32(x, S_LDT_ADDSTATUS_TGTDONE, M_LDT_ADDSTATUS_TGTDONE)
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-#endif
-
diff --git a/include/asm-mips/sibyte/sb1250_mac.h b/include/asm-mips/sibyte/sb1250_mac.h
deleted file mode 100644
index b6faf08ca81d..000000000000
--- a/include/asm-mips/sibyte/sb1250_mac.h
+++ /dev/null
@@ -1,656 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  MAC constants and macros                 File: sb1250_mac.h
-    *
-    *  This module contains constants and macros for the SB1250's
-    *  ethernet controllers.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_MAC_H
-#define _SB1250_MAC_H
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  Ethernet MAC Registers
-    ********************************************************************* */
-
-/*
- * MAC Configuration Register (Table 9-13)
- * Register: MAC_CFG_0
- * Register: MAC_CFG_1
- * Register: MAC_CFG_2
- */
-
-
-#define M_MAC_RESERVED0             _SB_MAKEMASK1(0)
-#define M_MAC_TX_HOLD_SOP_EN        _SB_MAKEMASK1(1)
-#define M_MAC_RETRY_EN              _SB_MAKEMASK1(2)
-#define M_MAC_RET_DRPREQ_EN         _SB_MAKEMASK1(3)
-#define M_MAC_RET_UFL_EN            _SB_MAKEMASK1(4)
-#define M_MAC_BURST_EN              _SB_MAKEMASK1(5)
-
-#define S_MAC_TX_PAUSE              _SB_MAKE64(6)
-#define M_MAC_TX_PAUSE_CNT          _SB_MAKEMASK(3, S_MAC_TX_PAUSE)
-#define V_MAC_TX_PAUSE_CNT(x)       _SB_MAKEVALUE(x, S_MAC_TX_PAUSE)
-
-#define K_MAC_TX_PAUSE_CNT_512      0
-#define K_MAC_TX_PAUSE_CNT_1K       1
-#define K_MAC_TX_PAUSE_CNT_2K       2
-#define K_MAC_TX_PAUSE_CNT_4K       3
-#define K_MAC_TX_PAUSE_CNT_8K       4
-#define K_MAC_TX_PAUSE_CNT_16K      5
-#define K_MAC_TX_PAUSE_CNT_32K      6
-#define K_MAC_TX_PAUSE_CNT_64K      7
-
-#define V_MAC_TX_PAUSE_CNT_512      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_512)
-#define V_MAC_TX_PAUSE_CNT_1K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_1K)
-#define V_MAC_TX_PAUSE_CNT_2K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_2K)
-#define V_MAC_TX_PAUSE_CNT_4K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_4K)
-#define V_MAC_TX_PAUSE_CNT_8K       V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_8K)
-#define V_MAC_TX_PAUSE_CNT_16K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_16K)
-#define V_MAC_TX_PAUSE_CNT_32K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_32K)
-#define V_MAC_TX_PAUSE_CNT_64K      V_MAC_TX_PAUSE_CNT(K_MAC_TX_PAUSE_CNT_64K)
-
-#define M_MAC_RESERVED1             _SB_MAKEMASK(8, 9)
-
-#define M_MAC_AP_STAT_EN            _SB_MAKEMASK1(17)
-
-#if SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_TIMESTAMP             _SB_MAKEMASK1(18)
-#endif
-#define M_MAC_DRP_ERRPKT_EN         _SB_MAKEMASK1(19)
-#define M_MAC_DRP_FCSERRPKT_EN      _SB_MAKEMASK1(20)
-#define M_MAC_DRP_CODEERRPKT_EN     _SB_MAKEMASK1(21)
-#define M_MAC_DRP_DRBLERRPKT_EN     _SB_MAKEMASK1(22)
-#define M_MAC_DRP_RNTPKT_EN         _SB_MAKEMASK1(23)
-#define M_MAC_DRP_OSZPKT_EN         _SB_MAKEMASK1(24)
-#define M_MAC_DRP_LENERRPKT_EN      _SB_MAKEMASK1(25)
-
-#define M_MAC_RESERVED3             _SB_MAKEMASK(6, 26)
-
-#define M_MAC_BYPASS_SEL            _SB_MAKEMASK1(32)
-#define M_MAC_HDX_EN                _SB_MAKEMASK1(33)
-
-#define S_MAC_SPEED_SEL             _SB_MAKE64(34)
-#define M_MAC_SPEED_SEL             _SB_MAKEMASK(2, S_MAC_SPEED_SEL)
-#define V_MAC_SPEED_SEL(x)          _SB_MAKEVALUE(x, S_MAC_SPEED_SEL)
-#define G_MAC_SPEED_SEL(x)          _SB_GETVALUE(x, S_MAC_SPEED_SEL, M_MAC_SPEED_SEL)
-
-#define K_MAC_SPEED_SEL_10MBPS      0
-#define K_MAC_SPEED_SEL_100MBPS     1
-#define K_MAC_SPEED_SEL_1000MBPS    2
-#define K_MAC_SPEED_SEL_RESERVED    3
-
-#define V_MAC_SPEED_SEL_10MBPS      V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_10MBPS)
-#define V_MAC_SPEED_SEL_100MBPS     V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_100MBPS)
-#define V_MAC_SPEED_SEL_1000MBPS    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_1000MBPS)
-#define V_MAC_SPEED_SEL_RESERVED    V_MAC_SPEED_SEL(K_MAC_SPEED_SEL_RESERVED)
-
-#define M_MAC_TX_CLK_EDGE_SEL       _SB_MAKEMASK1(36)
-#define M_MAC_LOOPBACK_SEL          _SB_MAKEMASK1(37)
-#define M_MAC_FAST_SYNC             _SB_MAKEMASK1(38)
-#define M_MAC_SS_EN                 _SB_MAKEMASK1(39)
-
-#define S_MAC_BYPASS_CFG            _SB_MAKE64(40)
-#define M_MAC_BYPASS_CFG            _SB_MAKEMASK(2, S_MAC_BYPASS_CFG)
-#define V_MAC_BYPASS_CFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_CFG)
-#define G_MAC_BYPASS_CFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_CFG, M_MAC_BYPASS_CFG)
-
-#define K_MAC_BYPASS_GMII           0
-#define K_MAC_BYPASS_ENCODED        1
-#define K_MAC_BYPASS_SOP            2
-#define K_MAC_BYPASS_EOP            3
-
-#define M_MAC_BYPASS_16             _SB_MAKEMASK1(42)
-#define M_MAC_BYPASS_FCS_CHK        _SB_MAKEMASK1(43)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_RX_CH_SEL_MSB         _SB_MAKEMASK1(44)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480*/
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_SPLIT_CH_SEL          _SB_MAKEMASK1(45)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define S_MAC_BYPASS_IFG            _SB_MAKE64(46)
-#define M_MAC_BYPASS_IFG            _SB_MAKEMASK(8, S_MAC_BYPASS_IFG)
-#define V_MAC_BYPASS_IFG(x)         _SB_MAKEVALUE(x, S_MAC_BYPASS_IFG)
-#define G_MAC_BYPASS_IFG(x)         _SB_GETVALUE(x, S_MAC_BYPASS_IFG, M_MAC_BYPASS_IFG)
-
-#define K_MAC_FC_CMD_DISABLED       0
-#define K_MAC_FC_CMD_ENABLED        1
-#define K_MAC_FC_CMD_ENAB_FALSECARR 2
-
-#define V_MAC_FC_CMD_DISABLED       V_MAC_FC_CMD(K_MAC_FC_CMD_DISABLED)
-#define V_MAC_FC_CMD_ENABLED        V_MAC_FC_CMD(K_MAC_FC_CMD_ENABLED)
-#define V_MAC_FC_CMD_ENAB_FALSECARR V_MAC_FC_CMD(K_MAC_FC_CMD_ENAB_FALSECARR)
-
-#define M_MAC_FC_SEL                _SB_MAKEMASK1(54)
-
-#define S_MAC_FC_CMD                _SB_MAKE64(55)
-#define M_MAC_FC_CMD                _SB_MAKEMASK(2, S_MAC_FC_CMD)
-#define V_MAC_FC_CMD(x)             _SB_MAKEVALUE(x, S_MAC_FC_CMD)
-#define G_MAC_FC_CMD(x)             _SB_GETVALUE(x, S_MAC_FC_CMD, M_MAC_FC_CMD)
-
-#define S_MAC_RX_CH_SEL             _SB_MAKE64(57)
-#define M_MAC_RX_CH_SEL             _SB_MAKEMASK(7, S_MAC_RX_CH_SEL)
-#define V_MAC_RX_CH_SEL(x)          _SB_MAKEVALUE(x, S_MAC_RX_CH_SEL)
-#define G_MAC_RX_CH_SEL(x)          _SB_GETVALUE(x, S_MAC_RX_CH_SEL, M_MAC_RX_CH_SEL)
-
-
-/*
- * MAC Enable Registers
- * Register: MAC_ENABLE_0
- * Register: MAC_ENABLE_1
- * Register: MAC_ENABLE_2
- */
-
-#define M_MAC_RXDMA_EN0             _SB_MAKEMASK1(0)
-#define M_MAC_RXDMA_EN1             _SB_MAKEMASK1(1)
-#define M_MAC_TXDMA_EN0             _SB_MAKEMASK1(4)
-#define M_MAC_TXDMA_EN1             _SB_MAKEMASK1(5)
-
-#define M_MAC_PORT_RESET            _SB_MAKEMASK1(8)
-
-#if (SIBYTE_HDR_FEATURE_CHIP(1250) || SIBYTE_HDR_FEATURE_CHIP(112x))
-#define M_MAC_RX_ENABLE             _SB_MAKEMASK1(10)
-#define M_MAC_TX_ENABLE             _SB_MAKEMASK1(11)
-#define M_MAC_BYP_RX_ENABLE         _SB_MAKEMASK1(12)
-#define M_MAC_BYP_TX_ENABLE         _SB_MAKEMASK1(13)
-#endif
-
-/*
- * MAC reset information register (1280/1255)
- */
-#if SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_RX_CH0_PAUSE_ON   _SB_MAKEMASK1(8)
-#define M_MAC_RX_CH1_PAUSE_ON   _SB_MAKEMASK1(16)
-#define M_MAC_TX_CH0_PAUSE_ON   _SB_MAKEMASK1(24)
-#define M_MAC_TX_CH1_PAUSE_ON   _SB_MAKEMASK1(32)
-#endif
-
-/*
- * MAC DMA Control Register
- * Register: MAC_TXD_CTL_0
- * Register: MAC_TXD_CTL_1
- * Register: MAC_TXD_CTL_2
- */
-
-#define S_MAC_TXD_WEIGHT0           _SB_MAKE64(0)
-#define M_MAC_TXD_WEIGHT0           _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT0)
-#define V_MAC_TXD_WEIGHT0(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT0)
-#define G_MAC_TXD_WEIGHT0(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT0, M_MAC_TXD_WEIGHT0)
-
-#define S_MAC_TXD_WEIGHT1           _SB_MAKE64(4)
-#define M_MAC_TXD_WEIGHT1           _SB_MAKEMASK(4, S_MAC_TXD_WEIGHT1)
-#define V_MAC_TXD_WEIGHT1(x)        _SB_MAKEVALUE(x, S_MAC_TXD_WEIGHT1)
-#define G_MAC_TXD_WEIGHT1(x)        _SB_GETVALUE(x, S_MAC_TXD_WEIGHT1, M_MAC_TXD_WEIGHT1)
-
-/*
- * MAC Fifo Threshhold registers (Table 9-14)
- * Register: MAC_THRSH_CFG_0
- * Register: MAC_THRSH_CFG_1
- * Register: MAC_THRSH_CFG_2
- */
-
-#define S_MAC_TX_WR_THRSH           _SB_MAKE64(0)
-#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
-/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
-/* #define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(6, S_MAC_TX_WR_THRSH) */
-#endif /* up to 1250 PASS1 */
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_TX_WR_THRSH           _SB_MAKEMASK(7, S_MAC_TX_WR_THRSH)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#define V_MAC_TX_WR_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_WR_THRSH)
-#define G_MAC_TX_WR_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_WR_THRSH, M_MAC_TX_WR_THRSH)
-
-#define S_MAC_TX_RD_THRSH           _SB_MAKE64(8)
-#if SIBYTE_HDR_FEATURE_UP_TO(1250, PASS1)
-/* XXX: Can't enable, as it has the same name as a pass2+ define below.  */
-/* #define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_TX_RD_THRSH) */
-#endif /* up to 1250 PASS1 */
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_TX_RD_THRSH           _SB_MAKEMASK(7, S_MAC_TX_RD_THRSH)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#define V_MAC_TX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RD_THRSH)
-#define G_MAC_TX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RD_THRSH, M_MAC_TX_RD_THRSH)
-
-#define S_MAC_TX_RL_THRSH           _SB_MAKE64(16)
-#define M_MAC_TX_RL_THRSH           _SB_MAKEMASK(4, S_MAC_TX_RL_THRSH)
-#define V_MAC_TX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_TX_RL_THRSH)
-#define G_MAC_TX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_TX_RL_THRSH, M_MAC_TX_RL_THRSH)
-
-#define S_MAC_RX_PL_THRSH           _SB_MAKE64(24)
-#define M_MAC_RX_PL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_PL_THRSH)
-#define V_MAC_RX_PL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_PL_THRSH)
-#define G_MAC_RX_PL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_PL_THRSH, M_MAC_RX_PL_THRSH)
-
-#define S_MAC_RX_RD_THRSH           _SB_MAKE64(32)
-#define M_MAC_RX_RD_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RD_THRSH)
-#define V_MAC_RX_RD_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RD_THRSH)
-#define G_MAC_RX_RD_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RD_THRSH, M_MAC_RX_RD_THRSH)
-
-#define S_MAC_RX_RL_THRSH           _SB_MAKE64(40)
-#define M_MAC_RX_RL_THRSH           _SB_MAKEMASK(6, S_MAC_RX_RL_THRSH)
-#define V_MAC_RX_RL_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_RX_RL_THRSH)
-#define G_MAC_RX_RL_THRSH(x)        _SB_GETVALUE(x, S_MAC_RX_RL_THRSH, M_MAC_RX_RL_THRSH)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_MAC_ENC_FC_THRSH           _SB_MAKE64(56)
-#define M_MAC_ENC_FC_THRSH           _SB_MAKEMASK(6, S_MAC_ENC_FC_THRSH)
-#define V_MAC_ENC_FC_THRSH(x)        _SB_MAKEVALUE(x, S_MAC_ENC_FC_THRSH)
-#define G_MAC_ENC_FC_THRSH(x)        _SB_GETVALUE(x, S_MAC_ENC_FC_THRSH, M_MAC_ENC_FC_THRSH)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-/*
- * MAC Frame Configuration Registers (Table 9-15)
- * Register: MAC_FRAME_CFG_0
- * Register: MAC_FRAME_CFG_1
- * Register: MAC_FRAME_CFG_2
- */
-
-/* XXXCGD: ??? Unused in pass2? */
-#define S_MAC_IFG_RX                _SB_MAKE64(0)
-#define M_MAC_IFG_RX                _SB_MAKEMASK(6, S_MAC_IFG_RX)
-#define V_MAC_IFG_RX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_RX)
-#define G_MAC_IFG_RX(x)             _SB_GETVALUE(x, S_MAC_IFG_RX, M_MAC_IFG_RX)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_MAC_PRE_LEN               _SB_MAKE64(0)
-#define M_MAC_PRE_LEN               _SB_MAKEMASK(6, S_MAC_PRE_LEN)
-#define V_MAC_PRE_LEN(x)            _SB_MAKEVALUE(x, S_MAC_PRE_LEN)
-#define G_MAC_PRE_LEN(x)            _SB_GETVALUE(x, S_MAC_PRE_LEN, M_MAC_PRE_LEN)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define S_MAC_IFG_TX                _SB_MAKE64(6)
-#define M_MAC_IFG_TX                _SB_MAKEMASK(6, S_MAC_IFG_TX)
-#define V_MAC_IFG_TX(x)             _SB_MAKEVALUE(x, S_MAC_IFG_TX)
-#define G_MAC_IFG_TX(x)             _SB_GETVALUE(x, S_MAC_IFG_TX, M_MAC_IFG_TX)
-
-#define S_MAC_IFG_THRSH             _SB_MAKE64(12)
-#define M_MAC_IFG_THRSH             _SB_MAKEMASK(6, S_MAC_IFG_THRSH)
-#define V_MAC_IFG_THRSH(x)          _SB_MAKEVALUE(x, S_MAC_IFG_THRSH)
-#define G_MAC_IFG_THRSH(x)          _SB_GETVALUE(x, S_MAC_IFG_THRSH, M_MAC_IFG_THRSH)
-
-#define S_MAC_BACKOFF_SEL           _SB_MAKE64(18)
-#define M_MAC_BACKOFF_SEL           _SB_MAKEMASK(4, S_MAC_BACKOFF_SEL)
-#define V_MAC_BACKOFF_SEL(x)        _SB_MAKEVALUE(x, S_MAC_BACKOFF_SEL)
-#define G_MAC_BACKOFF_SEL(x)        _SB_GETVALUE(x, S_MAC_BACKOFF_SEL, M_MAC_BACKOFF_SEL)
-
-#define S_MAC_LFSR_SEED             _SB_MAKE64(22)
-#define M_MAC_LFSR_SEED             _SB_MAKEMASK(8, S_MAC_LFSR_SEED)
-#define V_MAC_LFSR_SEED(x)          _SB_MAKEVALUE(x, S_MAC_LFSR_SEED)
-#define G_MAC_LFSR_SEED(x)          _SB_GETVALUE(x, S_MAC_LFSR_SEED, M_MAC_LFSR_SEED)
-
-#define S_MAC_SLOT_SIZE             _SB_MAKE64(30)
-#define M_MAC_SLOT_SIZE             _SB_MAKEMASK(10, S_MAC_SLOT_SIZE)
-#define V_MAC_SLOT_SIZE(x)          _SB_MAKEVALUE(x, S_MAC_SLOT_SIZE)
-#define G_MAC_SLOT_SIZE(x)          _SB_GETVALUE(x, S_MAC_SLOT_SIZE, M_MAC_SLOT_SIZE)
-
-#define S_MAC_MIN_FRAMESZ           _SB_MAKE64(40)
-#define M_MAC_MIN_FRAMESZ           _SB_MAKEMASK(8, S_MAC_MIN_FRAMESZ)
-#define V_MAC_MIN_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MIN_FRAMESZ)
-#define G_MAC_MIN_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MIN_FRAMESZ, M_MAC_MIN_FRAMESZ)
-
-#define S_MAC_MAX_FRAMESZ           _SB_MAKE64(48)
-#define M_MAC_MAX_FRAMESZ           _SB_MAKEMASK(16, S_MAC_MAX_FRAMESZ)
-#define V_MAC_MAX_FRAMESZ(x)        _SB_MAKEVALUE(x, S_MAC_MAX_FRAMESZ)
-#define G_MAC_MAX_FRAMESZ(x)        _SB_GETVALUE(x, S_MAC_MAX_FRAMESZ, M_MAC_MAX_FRAMESZ)
-
-/*
- * These constants are used to configure the fields within the Frame
- * Configuration Register.
- */
-
-#define K_MAC_IFG_RX_10             _SB_MAKE64(0)       /* See table 176, not used */
-#define K_MAC_IFG_RX_100            _SB_MAKE64(0)
-#define K_MAC_IFG_RX_1000           _SB_MAKE64(0)
-
-#define K_MAC_IFG_TX_10             _SB_MAKE64(20)
-#define K_MAC_IFG_TX_100            _SB_MAKE64(20)
-#define K_MAC_IFG_TX_1000           _SB_MAKE64(8)
-
-#define K_MAC_IFG_THRSH_10          _SB_MAKE64(4)
-#define K_MAC_IFG_THRSH_100         _SB_MAKE64(4)
-#define K_MAC_IFG_THRSH_1000        _SB_MAKE64(0)
-
-#define K_MAC_SLOT_SIZE_10          _SB_MAKE64(0)
-#define K_MAC_SLOT_SIZE_100         _SB_MAKE64(0)
-#define K_MAC_SLOT_SIZE_1000        _SB_MAKE64(0)
-
-#define V_MAC_IFG_RX_10        V_MAC_IFG_RX(K_MAC_IFG_RX_10)
-#define V_MAC_IFG_RX_100       V_MAC_IFG_RX(K_MAC_IFG_RX_100)
-#define V_MAC_IFG_RX_1000      V_MAC_IFG_RX(K_MAC_IFG_RX_1000)
-
-#define V_MAC_IFG_TX_10        V_MAC_IFG_TX(K_MAC_IFG_TX_10)
-#define V_MAC_IFG_TX_100       V_MAC_IFG_TX(K_MAC_IFG_TX_100)
-#define V_MAC_IFG_TX_1000      V_MAC_IFG_TX(K_MAC_IFG_TX_1000)
-
-#define V_MAC_IFG_THRSH_10     V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_10)
-#define V_MAC_IFG_THRSH_100    V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_100)
-#define V_MAC_IFG_THRSH_1000   V_MAC_IFG_THRSH(K_MAC_IFG_THRSH_1000)
-
-#define V_MAC_SLOT_SIZE_10     V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_10)
-#define V_MAC_SLOT_SIZE_100    V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_100)
-#define V_MAC_SLOT_SIZE_1000   V_MAC_SLOT_SIZE(K_MAC_SLOT_SIZE_1000)
-
-#define K_MAC_MIN_FRAMESZ_FIFO      _SB_MAKE64(9)
-#define K_MAC_MIN_FRAMESZ_DEFAULT   _SB_MAKE64(64)
-#define K_MAC_MAX_FRAMESZ_DEFAULT   _SB_MAKE64(1518)
-#define K_MAC_MAX_FRAMESZ_JUMBO     _SB_MAKE64(9216)
-
-#define V_MAC_MIN_FRAMESZ_FIFO      V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_FIFO)
-#define V_MAC_MIN_FRAMESZ_DEFAULT   V_MAC_MIN_FRAMESZ(K_MAC_MIN_FRAMESZ_DEFAULT)
-#define V_MAC_MAX_FRAMESZ_DEFAULT   V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_DEFAULT)
-#define V_MAC_MAX_FRAMESZ_JUMBO     V_MAC_MAX_FRAMESZ(K_MAC_MAX_FRAMESZ_JUMBO)
-
-/*
- * MAC VLAN Tag Registers (Table 9-16)
- * Register: MAC_VLANTAG_0
- * Register: MAC_VLANTAG_1
- * Register: MAC_VLANTAG_2
- */
-
-#define S_MAC_VLAN_TAG           _SB_MAKE64(0)
-#define M_MAC_VLAN_TAG           _SB_MAKEMASK(32, S_MAC_VLAN_TAG)
-#define V_MAC_VLAN_TAG(x)        _SB_MAKEVALUE(x, S_MAC_VLAN_TAG)
-#define G_MAC_VLAN_TAG(x)        _SB_GETVALUE(x, S_MAC_VLAN_TAG, M_MAC_VLAN_TAG)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define S_MAC_TX_PKT_OFFSET      _SB_MAKE64(32)
-#define M_MAC_TX_PKT_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_PKT_OFFSET)
-#define V_MAC_TX_PKT_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_PKT_OFFSET)
-#define G_MAC_TX_PKT_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_PKT_OFFSET, M_MAC_TX_PKT_OFFSET)
-
-#define S_MAC_TX_CRC_OFFSET      _SB_MAKE64(40)
-#define M_MAC_TX_CRC_OFFSET      _SB_MAKEMASK(8, S_MAC_TX_CRC_OFFSET)
-#define V_MAC_TX_CRC_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_TX_CRC_OFFSET)
-#define G_MAC_TX_CRC_OFFSET(x)   _SB_GETVALUE(x, S_MAC_TX_CRC_OFFSET, M_MAC_TX_CRC_OFFSET)
-
-#define M_MAC_CH_BASE_FC_EN      _SB_MAKEMASK1(48)
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-/*
- * MAC Status Registers (Table 9-17)
- * Also used for the MAC Interrupt Mask Register (Table 9-18)
- * Register: MAC_STATUS_0
- * Register: MAC_STATUS_1
- * Register: MAC_STATUS_2
- * Register: MAC_INT_MASK_0
- * Register: MAC_INT_MASK_1
- * Register: MAC_INT_MASK_2
- */
-
-/*
- * Use these constants to shift the appropriate channel
- * into the CH0 position so the same tests can be used
- * on each channel.
- */
-
-#define S_MAC_RX_CH0                _SB_MAKE64(0)
-#define S_MAC_RX_CH1                _SB_MAKE64(8)
-#define S_MAC_TX_CH0                _SB_MAKE64(16)
-#define S_MAC_TX_CH1                _SB_MAKE64(24)
-
-#define S_MAC_TXCHANNELS            _SB_MAKE64(16)      /* this is 1st TX chan */
-#define S_MAC_CHANWIDTH             _SB_MAKE64(8)       /* bits between channels */
-
-/*
- *  These are the same as RX channel 0.  The idea here
- *  is that you'll use one of the "S_" things above
- *  and pass just the six bits to a DMA-channel-specific ISR
- */
-#define M_MAC_INT_CHANNEL           _SB_MAKEMASK(8, 0)
-#define M_MAC_INT_EOP_COUNT         _SB_MAKEMASK1(0)
-#define M_MAC_INT_EOP_TIMER         _SB_MAKEMASK1(1)
-#define M_MAC_INT_EOP_SEEN          _SB_MAKEMASK1(2)
-#define M_MAC_INT_HWM               _SB_MAKEMASK1(3)
-#define M_MAC_INT_LWM               _SB_MAKEMASK1(4)
-#define M_MAC_INT_DSCR              _SB_MAKEMASK1(5)
-#define M_MAC_INT_ERR               _SB_MAKEMASK1(6)
-#define M_MAC_INT_DZERO             _SB_MAKEMASK1(7)    /* only for TX channels */
-#define M_MAC_INT_DROP              _SB_MAKEMASK1(7)    /* only for RX channels */
-
-/*
- * In the following definitions we use ch (0/1) and txrx (TX=1, RX=0, see
- * also DMA_TX/DMA_RX in sb_regs.h).
- */
-#define S_MAC_STATUS_CH_OFFSET(ch, txrx) _SB_MAKE64(((ch) + 2 * (txrx)) * S_MAC_CHANWIDTH)
-
-#define M_MAC_STATUS_CHANNEL(ch, txrx)   _SB_MAKEVALUE(_SB_MAKEMASK(8, 0), S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_EOP_COUNT(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_COUNT, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_EOP_TIMER(ch, txrx) _SB_MAKEVALUE(M_MAC_INT_EOP_TIMER, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_EOP_SEEN(ch, txrx)  _SB_MAKEVALUE(M_MAC_INT_EOP_SEEN, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_HWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_HWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_LWM(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_LWM, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_DSCR(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DSCR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_ERR(ch, txrx)       _SB_MAKEVALUE(M_MAC_INT_ERR, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_DZERO(ch, txrx)     _SB_MAKEVALUE(M_MAC_INT_DZERO, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_DROP(ch, txrx)      _SB_MAKEVALUE(M_MAC_INT_DROP, S_MAC_STATUS_CH_OFFSET(ch, txrx))
-#define M_MAC_STATUS_OTHER_ERR           _SB_MAKEVALUE(_SB_MAKEMASK(7, 0), 40)
-
-
-#define M_MAC_RX_UNDRFL             _SB_MAKEMASK1(40)
-#define M_MAC_RX_OVRFL              _SB_MAKEMASK1(41)
-#define M_MAC_TX_UNDRFL             _SB_MAKEMASK1(42)
-#define M_MAC_TX_OVRFL              _SB_MAKEMASK1(43)
-#define M_MAC_LTCOL_ERR             _SB_MAKEMASK1(44)
-#define M_MAC_EXCOL_ERR             _SB_MAKEMASK1(45)
-#define M_MAC_CNTR_OVRFL_ERR        _SB_MAKEMASK1(46)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_SPLIT_EN              _SB_MAKEMASK1(47)   /* interrupt mask only */
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#define S_MAC_COUNTER_ADDR          _SB_MAKE64(47)
-#define M_MAC_COUNTER_ADDR          _SB_MAKEMASK(5, S_MAC_COUNTER_ADDR)
-#define V_MAC_COUNTER_ADDR(x)       _SB_MAKEVALUE(x, S_MAC_COUNTER_ADDR)
-#define G_MAC_COUNTER_ADDR(x)       _SB_GETVALUE(x, S_MAC_COUNTER_ADDR, M_MAC_COUNTER_ADDR)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_TX_PAUSE_ON           _SB_MAKEMASK1(52)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-/*
- * MAC Fifo Pointer Registers (Table 9-19)    [Debug register]
- * Register: MAC_FIFO_PTRS_0
- * Register: MAC_FIFO_PTRS_1
- * Register: MAC_FIFO_PTRS_2
- */
-
-#define S_MAC_TX_WRPTR              _SB_MAKE64(0)
-#define M_MAC_TX_WRPTR              _SB_MAKEMASK(6, S_MAC_TX_WRPTR)
-#define V_MAC_TX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_WRPTR)
-#define G_MAC_TX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_TX_WRPTR, M_MAC_TX_WRPTR)
-
-#define S_MAC_TX_RDPTR              _SB_MAKE64(8)
-#define M_MAC_TX_RDPTR              _SB_MAKEMASK(6, S_MAC_TX_RDPTR)
-#define V_MAC_TX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_TX_RDPTR)
-#define G_MAC_TX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_TX_RDPTR, M_MAC_TX_RDPTR)
-
-#define S_MAC_RX_WRPTR              _SB_MAKE64(16)
-#define M_MAC_RX_WRPTR              _SB_MAKEMASK(6, S_MAC_RX_WRPTR)
-#define V_MAC_RX_WRPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_WRPTR)
-#define G_MAC_RX_WRPTR(x)           _SB_GETVALUE(x, S_MAC_RX_WRPTR, M_MAC_TX_WRPTR)
-
-#define S_MAC_RX_RDPTR              _SB_MAKE64(24)
-#define M_MAC_RX_RDPTR              _SB_MAKEMASK(6, S_MAC_RX_RDPTR)
-#define V_MAC_RX_RDPTR(x)           _SB_MAKEVALUE(x, S_MAC_RX_RDPTR)
-#define G_MAC_RX_RDPTR(x)           _SB_GETVALUE(x, S_MAC_RX_RDPTR, M_MAC_TX_RDPTR)
-
-/*
- * MAC Fifo End Of Packet Count Registers (Table 9-20)  [Debug register]
- * Register: MAC_EOPCNT_0
- * Register: MAC_EOPCNT_1
- * Register: MAC_EOPCNT_2
- */
-
-#define S_MAC_TX_EOP_COUNTER        _SB_MAKE64(0)
-#define M_MAC_TX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_TX_EOP_COUNTER)
-#define V_MAC_TX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_TX_EOP_COUNTER)
-#define G_MAC_TX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_TX_EOP_COUNTER, M_MAC_TX_EOP_COUNTER)
-
-#define S_MAC_RX_EOP_COUNTER        _SB_MAKE64(8)
-#define M_MAC_RX_EOP_COUNTER        _SB_MAKEMASK(6, S_MAC_RX_EOP_COUNTER)
-#define V_MAC_RX_EOP_COUNTER(x)     _SB_MAKEVALUE(x, S_MAC_RX_EOP_COUNTER)
-#define G_MAC_RX_EOP_COUNTER(x)     _SB_GETVALUE(x, S_MAC_RX_EOP_COUNTER, M_MAC_RX_EOP_COUNTER)
-
-/*
- * MAC Recieve Address Filter Exact Match Registers (Table 9-21)
- * Registers: MAC_ADDR0_0 through MAC_ADDR7_0
- * Registers: MAC_ADDR0_1 through MAC_ADDR7_1
- * Registers: MAC_ADDR0_2 through MAC_ADDR7_2
- */
-
-/* No bitfields */
-
-/*
- * MAC Receive Address Filter Mask Registers
- * Registers: MAC_ADDRMASK0_0 and MAC_ADDRMASK0_1
- * Registers: MAC_ADDRMASK1_0 and MAC_ADDRMASK1_1
- * Registers: MAC_ADDRMASK2_0 and MAC_ADDRMASK2_1
- */
-
-/* No bitfields */
-
-/*
- * MAC Recieve Address Filter Hash Match Registers (Table 9-22)
- * Registers: MAC_HASH0_0 through MAC_HASH7_0
- * Registers: MAC_HASH0_1 through MAC_HASH7_1
- * Registers: MAC_HASH0_2 through MAC_HASH7_2
- */
-
-/* No bitfields */
-
-/*
- * MAC Transmit Source Address Registers (Table 9-23)
- * Register: MAC_ETHERNET_ADDR_0
- * Register: MAC_ETHERNET_ADDR_1
- * Register: MAC_ETHERNET_ADDR_2
- */
-
-/* No bitfields */
-
-/*
- * MAC Packet Type Configuration Register
- * Register: MAC_TYPE_CFG_0
- * Register: MAC_TYPE_CFG_1
- * Register: MAC_TYPE_CFG_2
- */
-
-#define S_TYPECFG_TYPESIZE      _SB_MAKE64(16)
-
-#define S_TYPECFG_TYPE0         _SB_MAKE64(0)
-#define M_TYPECFG_TYPE0         _SB_MAKEMASK(16, S_TYPECFG_TYPE0)
-#define V_TYPECFG_TYPE0(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE0)
-#define G_TYPECFG_TYPE0(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE0, M_TYPECFG_TYPE0)
-
-#define S_TYPECFG_TYPE1         _SB_MAKE64(0)
-#define M_TYPECFG_TYPE1         _SB_MAKEMASK(16, S_TYPECFG_TYPE1)
-#define V_TYPECFG_TYPE1(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE1)
-#define G_TYPECFG_TYPE1(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE1, M_TYPECFG_TYPE1)
-
-#define S_TYPECFG_TYPE2         _SB_MAKE64(0)
-#define M_TYPECFG_TYPE2         _SB_MAKEMASK(16, S_TYPECFG_TYPE2)
-#define V_TYPECFG_TYPE2(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE2)
-#define G_TYPECFG_TYPE2(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE2, M_TYPECFG_TYPE2)
-
-#define S_TYPECFG_TYPE3         _SB_MAKE64(0)
-#define M_TYPECFG_TYPE3         _SB_MAKEMASK(16, S_TYPECFG_TYPE3)
-#define V_TYPECFG_TYPE3(x)      _SB_MAKEVALUE(x, S_TYPECFG_TYPE3)
-#define G_TYPECFG_TYPE3(x)      _SB_GETVALUE(x, S_TYPECFG_TYPE3, M_TYPECFG_TYPE3)
-
-/*
- * MAC Receive Address Filter Control Registers (Table 9-24)
- * Register: MAC_ADFILTER_CFG_0
- * Register: MAC_ADFILTER_CFG_1
- * Register: MAC_ADFILTER_CFG_2
- */
-
-#define M_MAC_ALLPKT_EN         _SB_MAKEMASK1(0)
-#define M_MAC_UCAST_EN          _SB_MAKEMASK1(1)
-#define M_MAC_UCAST_INV         _SB_MAKEMASK1(2)
-#define M_MAC_MCAST_EN          _SB_MAKEMASK1(3)
-#define M_MAC_MCAST_INV         _SB_MAKEMASK1(4)
-#define M_MAC_BCAST_EN          _SB_MAKEMASK1(5)
-#define M_MAC_DIRECT_INV        _SB_MAKEMASK1(6)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_MAC_ALLMCAST_EN       _SB_MAKEMASK1(7)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#define S_MAC_IPHDR_OFFSET      _SB_MAKE64(8)
-#define M_MAC_IPHDR_OFFSET      _SB_MAKEMASK(8, S_MAC_IPHDR_OFFSET)
-#define V_MAC_IPHDR_OFFSET(x)   _SB_MAKEVALUE(x, S_MAC_IPHDR_OFFSET)
-#define G_MAC_IPHDR_OFFSET(x)   _SB_GETVALUE(x, S_MAC_IPHDR_OFFSET, M_MAC_IPHDR_OFFSET)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_MAC_RX_CRC_OFFSET     _SB_MAKE64(16)
-#define M_MAC_RX_CRC_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_CRC_OFFSET)
-#define V_MAC_RX_CRC_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_RX_CRC_OFFSET)
-#define G_MAC_RX_CRC_OFFSET(x)  _SB_GETVALUE(x, S_MAC_RX_CRC_OFFSET, M_MAC_RX_CRC_OFFSET)
-
-#define S_MAC_RX_PKT_OFFSET     _SB_MAKE64(24)
-#define M_MAC_RX_PKT_OFFSET     _SB_MAKEMASK(8, S_MAC_RX_PKT_OFFSET)
-#define V_MAC_RX_PKT_OFFSET(x)  _SB_MAKEVALUE(x, S_MAC_RX_PKT_OFFSET)
-#define G_MAC_RX_PKT_OFFSET(x)  _SB_GETVALUE(x, S_MAC_RX_PKT_OFFSET, M_MAC_RX_PKT_OFFSET)
-
-#define M_MAC_FWDPAUSE_EN       _SB_MAKEMASK1(32)
-#define M_MAC_VLAN_DET_EN       _SB_MAKEMASK1(33)
-
-#define S_MAC_RX_CH_MSN_SEL     _SB_MAKE64(34)
-#define M_MAC_RX_CH_MSN_SEL     _SB_MAKEMASK(8, S_MAC_RX_CH_MSN_SEL)
-#define V_MAC_RX_CH_MSN_SEL(x)  _SB_MAKEVALUE(x, S_MAC_RX_CH_MSN_SEL)
-#define G_MAC_RX_CH_MSN_SEL(x)  _SB_GETVALUE(x, S_MAC_RX_CH_MSN_SEL, M_MAC_RX_CH_MSN_SEL)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-/*
- * MAC Receive Channel Select Registers (Table 9-25)
- */
-
-/* no bitfields */
-
-/*
- * MAC MII Management Interface Registers (Table 9-26)
- * Register: MAC_MDIO_0
- * Register: MAC_MDIO_1
- * Register: MAC_MDIO_2
- */
-
-#define S_MAC_MDC               0
-#define S_MAC_MDIO_DIR          1
-#define S_MAC_MDIO_OUT          2
-#define S_MAC_GENC              3
-#define S_MAC_MDIO_IN           4
-
-#define M_MAC_MDC               _SB_MAKEMASK1(S_MAC_MDC)
-#define M_MAC_MDIO_DIR          _SB_MAKEMASK1(S_MAC_MDIO_DIR)
-#define M_MAC_MDIO_DIR_INPUT    _SB_MAKEMASK1(S_MAC_MDIO_DIR)
-#define M_MAC_MDIO_OUT          _SB_MAKEMASK1(S_MAC_MDIO_OUT)
-#define M_MAC_GENC              _SB_MAKEMASK1(S_MAC_GENC)
-#define M_MAC_MDIO_IN           _SB_MAKEMASK1(S_MAC_MDIO_IN)
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_mc.h b/include/asm-mips/sibyte/sb1250_mc.h
deleted file mode 100644
index 1eb1b5a88736..000000000000
--- a/include/asm-mips/sibyte/sb1250_mc.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  Memory Controller constants              File: sb1250_mc.h
-    *
-    *  This module contains constants and macros useful for
-    *  programming the memory controller.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000, 2001, 2002, 2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_MC_H
-#define _SB1250_MC_H
-
-#include "sb1250_defs.h"
-
-/*
- * Memory Channel Config Register (table 6-14)
- */
-
-#define S_MC_RESERVED0              0
-#define M_MC_RESERVED0              _SB_MAKEMASK(8, S_MC_RESERVED0)
-
-#define S_MC_CHANNEL_SEL            8
-#define M_MC_CHANNEL_SEL            _SB_MAKEMASK(8, S_MC_CHANNEL_SEL)
-#define V_MC_CHANNEL_SEL(x)         _SB_MAKEVALUE(x, S_MC_CHANNEL_SEL)
-#define G_MC_CHANNEL_SEL(x)         _SB_GETVALUE(x, S_MC_CHANNEL_SEL, M_MC_CHANNEL_SEL)
-
-#define S_MC_BANK0_MAP              16
-#define M_MC_BANK0_MAP              _SB_MAKEMASK(4, S_MC_BANK0_MAP)
-#define V_MC_BANK0_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK0_MAP)
-#define G_MC_BANK0_MAP(x)           _SB_GETVALUE(x, S_MC_BANK0_MAP, M_MC_BANK0_MAP)
-
-#define K_MC_BANK0_MAP_DEFAULT      0x00
-#define V_MC_BANK0_MAP_DEFAULT      V_MC_BANK0_MAP(K_MC_BANK0_MAP_DEFAULT)
-
-#define S_MC_BANK1_MAP              20
-#define M_MC_BANK1_MAP              _SB_MAKEMASK(4, S_MC_BANK1_MAP)
-#define V_MC_BANK1_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK1_MAP)
-#define G_MC_BANK1_MAP(x)           _SB_GETVALUE(x, S_MC_BANK1_MAP, M_MC_BANK1_MAP)
-
-#define K_MC_BANK1_MAP_DEFAULT      0x08
-#define V_MC_BANK1_MAP_DEFAULT      V_MC_BANK1_MAP(K_MC_BANK1_MAP_DEFAULT)
-
-#define S_MC_BANK2_MAP              24
-#define M_MC_BANK2_MAP              _SB_MAKEMASK(4, S_MC_BANK2_MAP)
-#define V_MC_BANK2_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK2_MAP)
-#define G_MC_BANK2_MAP(x)           _SB_GETVALUE(x, S_MC_BANK2_MAP, M_MC_BANK2_MAP)
-
-#define K_MC_BANK2_MAP_DEFAULT      0x09
-#define V_MC_BANK2_MAP_DEFAULT      V_MC_BANK2_MAP(K_MC_BANK2_MAP_DEFAULT)
-
-#define S_MC_BANK3_MAP              28
-#define M_MC_BANK3_MAP              _SB_MAKEMASK(4, S_MC_BANK3_MAP)
-#define V_MC_BANK3_MAP(x)           _SB_MAKEVALUE(x, S_MC_BANK3_MAP)
-#define G_MC_BANK3_MAP(x)           _SB_GETVALUE(x, S_MC_BANK3_MAP, M_MC_BANK3_MAP)
-
-#define K_MC_BANK3_MAP_DEFAULT      0x0C
-#define V_MC_BANK3_MAP_DEFAULT      V_MC_BANK3_MAP(K_MC_BANK3_MAP_DEFAULT)
-
-#define M_MC_RESERVED1              _SB_MAKEMASK(8, 32)
-
-#define S_MC_QUEUE_SIZE             40
-#define M_MC_QUEUE_SIZE             _SB_MAKEMASK(4, S_MC_QUEUE_SIZE)
-#define V_MC_QUEUE_SIZE(x)          _SB_MAKEVALUE(x, S_MC_QUEUE_SIZE)
-#define G_MC_QUEUE_SIZE(x)          _SB_GETVALUE(x, S_MC_QUEUE_SIZE, M_MC_QUEUE_SIZE)
-#define V_MC_QUEUE_SIZE_DEFAULT     V_MC_QUEUE_SIZE(0x0A)
-
-#define S_MC_AGE_LIMIT              44
-#define M_MC_AGE_LIMIT              _SB_MAKEMASK(4, S_MC_AGE_LIMIT)
-#define V_MC_AGE_LIMIT(x)           _SB_MAKEVALUE(x, S_MC_AGE_LIMIT)
-#define G_MC_AGE_LIMIT(x)           _SB_GETVALUE(x, S_MC_AGE_LIMIT, M_MC_AGE_LIMIT)
-#define V_MC_AGE_LIMIT_DEFAULT      V_MC_AGE_LIMIT(8)
-
-#define S_MC_WR_LIMIT               48
-#define M_MC_WR_LIMIT               _SB_MAKEMASK(4, S_MC_WR_LIMIT)
-#define V_MC_WR_LIMIT(x)            _SB_MAKEVALUE(x, S_MC_WR_LIMIT)
-#define G_MC_WR_LIMIT(x)            _SB_GETVALUE(x, S_MC_WR_LIMIT, M_MC_WR_LIMIT)
-#define V_MC_WR_LIMIT_DEFAULT       V_MC_WR_LIMIT(5)
-
-#define M_MC_IOB1HIGHPRIORITY       _SB_MAKEMASK1(52)
-
-#define M_MC_RESERVED2              _SB_MAKEMASK(3, 53)
-
-#define S_MC_CS_MODE                56
-#define M_MC_CS_MODE                _SB_MAKEMASK(4, S_MC_CS_MODE)
-#define V_MC_CS_MODE(x)             _SB_MAKEVALUE(x, S_MC_CS_MODE)
-#define G_MC_CS_MODE(x)             _SB_GETVALUE(x, S_MC_CS_MODE, M_MC_CS_MODE)
-
-#define K_MC_CS_MODE_MSB_CS         0
-#define K_MC_CS_MODE_INTLV_CS       15
-#define K_MC_CS_MODE_MIXED_CS_10    12
-#define K_MC_CS_MODE_MIXED_CS_30    6
-#define K_MC_CS_MODE_MIXED_CS_32    3
-
-#define V_MC_CS_MODE_MSB_CS         V_MC_CS_MODE(K_MC_CS_MODE_MSB_CS)
-#define V_MC_CS_MODE_INTLV_CS       V_MC_CS_MODE(K_MC_CS_MODE_INTLV_CS)
-#define V_MC_CS_MODE_MIXED_CS_10    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_10)
-#define V_MC_CS_MODE_MIXED_CS_30    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_30)
-#define V_MC_CS_MODE_MIXED_CS_32    V_MC_CS_MODE(K_MC_CS_MODE_MIXED_CS_32)
-
-#define M_MC_ECC_DISABLE            _SB_MAKEMASK1(60)
-#define M_MC_BERR_DISABLE           _SB_MAKEMASK1(61)
-#define M_MC_FORCE_SEQ              _SB_MAKEMASK1(62)
-#define M_MC_DEBUG                  _SB_MAKEMASK1(63)
-
-#define V_MC_CONFIG_DEFAULT     V_MC_WR_LIMIT_DEFAULT | V_MC_AGE_LIMIT_DEFAULT | \
-                                V_MC_BANK0_MAP_DEFAULT | V_MC_BANK1_MAP_DEFAULT | \
-                                V_MC_BANK2_MAP_DEFAULT | V_MC_BANK3_MAP_DEFAULT | V_MC_CHANNEL_SEL(0) | \
-                                M_MC_IOB1HIGHPRIORITY | V_MC_QUEUE_SIZE_DEFAULT
-
-
-/*
- * Memory clock config register (Table 6-15)
- *
- * Note: this field has been updated to be consistent with the errata to 0.2
- */
-
-#define S_MC_CLK_RATIO              0
-#define M_MC_CLK_RATIO              _SB_MAKEMASK(4, S_MC_CLK_RATIO)
-#define V_MC_CLK_RATIO(x)           _SB_MAKEVALUE(x, S_MC_CLK_RATIO)
-#define G_MC_CLK_RATIO(x)           _SB_GETVALUE(x, S_MC_CLK_RATIO, M_MC_CLK_RATIO)
-
-#define K_MC_CLK_RATIO_2X           4
-#define K_MC_CLK_RATIO_25X          5
-#define K_MC_CLK_RATIO_3X           6
-#define K_MC_CLK_RATIO_35X          7
-#define K_MC_CLK_RATIO_4X           8
-#define K_MC_CLK_RATIO_45X          9
-
-#define V_MC_CLK_RATIO_2X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_2X)
-#define V_MC_CLK_RATIO_25X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_25X)
-#define V_MC_CLK_RATIO_3X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_3X)
-#define V_MC_CLK_RATIO_35X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_35X)
-#define V_MC_CLK_RATIO_4X           V_MC_CLK_RATIO(K_MC_CLK_RATIO_4X)
-#define V_MC_CLK_RATIO_45X          V_MC_CLK_RATIO(K_MC_CLK_RATIO_45X)
-#define V_MC_CLK_RATIO_DEFAULT      V_MC_CLK_RATIO_25X
-
-#define S_MC_REF_RATE                8
-#define M_MC_REF_RATE                _SB_MAKEMASK(8, S_MC_REF_RATE)
-#define V_MC_REF_RATE(x)             _SB_MAKEVALUE(x, S_MC_REF_RATE)
-#define G_MC_REF_RATE(x)             _SB_GETVALUE(x, S_MC_REF_RATE, M_MC_REF_RATE)
-
-#define K_MC_REF_RATE_100MHz         0x62
-#define K_MC_REF_RATE_133MHz         0x81
-#define K_MC_REF_RATE_200MHz         0xC4
-
-#define V_MC_REF_RATE_100MHz         V_MC_REF_RATE(K_MC_REF_RATE_100MHz)
-#define V_MC_REF_RATE_133MHz         V_MC_REF_RATE(K_MC_REF_RATE_133MHz)
-#define V_MC_REF_RATE_200MHz         V_MC_REF_RATE(K_MC_REF_RATE_200MHz)
-#define V_MC_REF_RATE_DEFAULT        V_MC_REF_RATE_100MHz
-
-#define S_MC_CLOCK_DRIVE             16
-#define M_MC_CLOCK_DRIVE             _SB_MAKEMASK(4, S_MC_CLOCK_DRIVE)
-#define V_MC_CLOCK_DRIVE(x)          _SB_MAKEVALUE(x, S_MC_CLOCK_DRIVE)
-#define G_MC_CLOCK_DRIVE(x)          _SB_GETVALUE(x, S_MC_CLOCK_DRIVE, M_MC_CLOCK_DRIVE)
-#define V_MC_CLOCK_DRIVE_DEFAULT     V_MC_CLOCK_DRIVE(0xF)
-
-#define S_MC_DATA_DRIVE              20
-#define M_MC_DATA_DRIVE              _SB_MAKEMASK(4, S_MC_DATA_DRIVE)
-#define V_MC_DATA_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_DATA_DRIVE)
-#define G_MC_DATA_DRIVE(x)           _SB_GETVALUE(x, S_MC_DATA_DRIVE, M_MC_DATA_DRIVE)
-#define V_MC_DATA_DRIVE_DEFAULT      V_MC_DATA_DRIVE(0x0)
-
-#define S_MC_ADDR_DRIVE              24
-#define M_MC_ADDR_DRIVE              _SB_MAKEMASK(4, S_MC_ADDR_DRIVE)
-#define V_MC_ADDR_DRIVE(x)           _SB_MAKEVALUE(x, S_MC_ADDR_DRIVE)
-#define G_MC_ADDR_DRIVE(x)           _SB_GETVALUE(x, S_MC_ADDR_DRIVE, M_MC_ADDR_DRIVE)
-#define V_MC_ADDR_DRIVE_DEFAULT      V_MC_ADDR_DRIVE(0x0)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_MC_REF_DISABLE             _SB_MAKEMASK1(30)
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-#define M_MC_DLL_BYPASS              _SB_MAKEMASK1(31)
-
-#define S_MC_DQI_SKEW               32
-#define M_MC_DQI_SKEW               _SB_MAKEMASK(8, S_MC_DQI_SKEW)
-#define V_MC_DQI_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQI_SKEW)
-#define G_MC_DQI_SKEW(x)            _SB_GETVALUE(x, S_MC_DQI_SKEW, M_MC_DQI_SKEW)
-#define V_MC_DQI_SKEW_DEFAULT       V_MC_DQI_SKEW(0)
-
-#define S_MC_DQO_SKEW               40
-#define M_MC_DQO_SKEW               _SB_MAKEMASK(8, S_MC_DQO_SKEW)
-#define V_MC_DQO_SKEW(x)            _SB_MAKEVALUE(x, S_MC_DQO_SKEW)
-#define G_MC_DQO_SKEW(x)            _SB_GETVALUE(x, S_MC_DQO_SKEW, M_MC_DQO_SKEW)
-#define V_MC_DQO_SKEW_DEFAULT       V_MC_DQO_SKEW(0)
-
-#define S_MC_ADDR_SKEW               48
-#define M_MC_ADDR_SKEW               _SB_MAKEMASK(8, S_MC_ADDR_SKEW)
-#define V_MC_ADDR_SKEW(x)            _SB_MAKEVALUE(x, S_MC_ADDR_SKEW)
-#define G_MC_ADDR_SKEW(x)            _SB_GETVALUE(x, S_MC_ADDR_SKEW, M_MC_ADDR_SKEW)
-#define V_MC_ADDR_SKEW_DEFAULT       V_MC_ADDR_SKEW(0x0F)
-
-#define S_MC_DLL_DEFAULT             56
-#define M_MC_DLL_DEFAULT             _SB_MAKEMASK(8, S_MC_DLL_DEFAULT)
-#define V_MC_DLL_DEFAULT(x)          _SB_MAKEVALUE(x, S_MC_DLL_DEFAULT)
-#define G_MC_DLL_DEFAULT(x)          _SB_GETVALUE(x, S_MC_DLL_DEFAULT, M_MC_DLL_DEFAULT)
-#define V_MC_DLL_DEFAULT_DEFAULT     V_MC_DLL_DEFAULT(0x10)
-
-#define V_MC_CLKCONFIG_DEFAULT       V_MC_DLL_DEFAULT_DEFAULT |  \
-                                     V_MC_ADDR_SKEW_DEFAULT | \
-                                     V_MC_DQO_SKEW_DEFAULT | \
-                                     V_MC_DQI_SKEW_DEFAULT | \
-                                     V_MC_ADDR_DRIVE_DEFAULT | \
-                                     V_MC_DATA_DRIVE_DEFAULT | \
-                                     V_MC_CLOCK_DRIVE_DEFAULT | \
-                                     V_MC_REF_RATE_DEFAULT
-
-
-
-/*
- * DRAM Command Register (Table 6-13)
- */
-
-#define S_MC_COMMAND                0
-#define M_MC_COMMAND                _SB_MAKEMASK(4, S_MC_COMMAND)
-#define V_MC_COMMAND(x)             _SB_MAKEVALUE(x, S_MC_COMMAND)
-#define G_MC_COMMAND(x)             _SB_GETVALUE(x, S_MC_COMMAND, M_MC_COMMAND)
-
-#define K_MC_COMMAND_EMRS           0
-#define K_MC_COMMAND_MRS            1
-#define K_MC_COMMAND_PRE            2
-#define K_MC_COMMAND_AR             3
-#define K_MC_COMMAND_SETRFSH        4
-#define K_MC_COMMAND_CLRRFSH        5
-#define K_MC_COMMAND_SETPWRDN       6
-#define K_MC_COMMAND_CLRPWRDN       7
-
-#define V_MC_COMMAND_EMRS           V_MC_COMMAND(K_MC_COMMAND_EMRS)
-#define V_MC_COMMAND_MRS            V_MC_COMMAND(K_MC_COMMAND_MRS)
-#define V_MC_COMMAND_PRE            V_MC_COMMAND(K_MC_COMMAND_PRE)
-#define V_MC_COMMAND_AR             V_MC_COMMAND(K_MC_COMMAND_AR)
-#define V_MC_COMMAND_SETRFSH        V_MC_COMMAND(K_MC_COMMAND_SETRFSH)
-#define V_MC_COMMAND_CLRRFSH        V_MC_COMMAND(K_MC_COMMAND_CLRRFSH)
-#define V_MC_COMMAND_SETPWRDN       V_MC_COMMAND(K_MC_COMMAND_SETPWRDN)
-#define V_MC_COMMAND_CLRPWRDN       V_MC_COMMAND(K_MC_COMMAND_CLRPWRDN)
-
-#define M_MC_CS0                    _SB_MAKEMASK1(4)
-#define M_MC_CS1                    _SB_MAKEMASK1(5)
-#define M_MC_CS2                    _SB_MAKEMASK1(6)
-#define M_MC_CS3                    _SB_MAKEMASK1(7)
-
-/*
- * DRAM Mode Register (Table 6-14)
- */
-
-#define S_MC_EMODE                  0
-#define M_MC_EMODE                  _SB_MAKEMASK(15, S_MC_EMODE)
-#define V_MC_EMODE(x)               _SB_MAKEVALUE(x, S_MC_EMODE)
-#define G_MC_EMODE(x)               _SB_GETVALUE(x, S_MC_EMODE, M_MC_EMODE)
-#define V_MC_EMODE_DEFAULT          V_MC_EMODE(0)
-
-#define S_MC_MODE                   16
-#define M_MC_MODE                   _SB_MAKEMASK(15, S_MC_MODE)
-#define V_MC_MODE(x)                _SB_MAKEVALUE(x, S_MC_MODE)
-#define G_MC_MODE(x)                _SB_GETVALUE(x, S_MC_MODE, M_MC_MODE)
-#define V_MC_MODE_DEFAULT           V_MC_MODE(0x22)
-
-#define S_MC_DRAM_TYPE              32
-#define M_MC_DRAM_TYPE              _SB_MAKEMASK(3, S_MC_DRAM_TYPE)
-#define V_MC_DRAM_TYPE(x)           _SB_MAKEVALUE(x, S_MC_DRAM_TYPE)
-#define G_MC_DRAM_TYPE(x)           _SB_GETVALUE(x, S_MC_DRAM_TYPE, M_MC_DRAM_TYPE)
-
-#define K_MC_DRAM_TYPE_JEDEC        0
-#define K_MC_DRAM_TYPE_FCRAM        1
-#define K_MC_DRAM_TYPE_SGRAM        2
-
-#define V_MC_DRAM_TYPE_JEDEC        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_JEDEC)
-#define V_MC_DRAM_TYPE_FCRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_FCRAM)
-#define V_MC_DRAM_TYPE_SGRAM        V_MC_DRAM_TYPE(K_MC_DRAM_TYPE_SGRAM)
-
-#define M_MC_EXTERNALDECODE         _SB_MAKEMASK1(35)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_MC_PRE_ON_A8              _SB_MAKEMASK1(36)
-#define M_MC_RAM_WITH_A13           _SB_MAKEMASK1(37)
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-
-
-/*
- * SDRAM Timing Register  (Table 6-15)
- */
-
-#define M_MC_w2rIDLE_TWOCYCLES    _SB_MAKEMASK1(60)
-#define M_MC_r2wIDLE_TWOCYCLES    _SB_MAKEMASK1(61)
-#define M_MC_r2rIDLE_TWOCYCLES    _SB_MAKEMASK1(62)
-
-#define S_MC_tFIFO                56
-#define M_MC_tFIFO                _SB_MAKEMASK(4, S_MC_tFIFO)
-#define V_MC_tFIFO(x)             _SB_MAKEVALUE(x, S_MC_tFIFO)
-#define G_MC_tFIFO(x)             _SB_GETVALUE(x, S_MC_tFIFO, M_MC_tFIFO)
-#define K_MC_tFIFO_DEFAULT        1
-#define V_MC_tFIFO_DEFAULT        V_MC_tFIFO(K_MC_tFIFO_DEFAULT)
-
-#define S_MC_tRFC                 52
-#define M_MC_tRFC                 _SB_MAKEMASK(4, S_MC_tRFC)
-#define V_MC_tRFC(x)              _SB_MAKEVALUE(x, S_MC_tRFC)
-#define G_MC_tRFC(x)              _SB_GETVALUE(x, S_MC_tRFC, M_MC_tRFC)
-#define K_MC_tRFC_DEFAULT         12
-#define V_MC_tRFC_DEFAULT         V_MC_tRFC(K_MC_tRFC_DEFAULT)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3)
-#define M_MC_tRFC_PLUS16          _SB_MAKEMASK1(51)     /* 1250C3 and later.  */
-#endif
-
-#define S_MC_tCwCr                40
-#define M_MC_tCwCr                _SB_MAKEMASK(4, S_MC_tCwCr)
-#define V_MC_tCwCr(x)             _SB_MAKEVALUE(x, S_MC_tCwCr)
-#define G_MC_tCwCr(x)             _SB_GETVALUE(x, S_MC_tCwCr, M_MC_tCwCr)
-#define K_MC_tCwCr_DEFAULT        4
-#define V_MC_tCwCr_DEFAULT        V_MC_tCwCr(K_MC_tCwCr_DEFAULT)
-
-#define S_MC_tRCr                 28
-#define M_MC_tRCr                 _SB_MAKEMASK(4, S_MC_tRCr)
-#define V_MC_tRCr(x)              _SB_MAKEVALUE(x, S_MC_tRCr)
-#define G_MC_tRCr(x)              _SB_GETVALUE(x, S_MC_tRCr, M_MC_tRCr)
-#define K_MC_tRCr_DEFAULT         9
-#define V_MC_tRCr_DEFAULT         V_MC_tRCr(K_MC_tRCr_DEFAULT)
-
-#define S_MC_tRCw                 24
-#define M_MC_tRCw                 _SB_MAKEMASK(4, S_MC_tRCw)
-#define V_MC_tRCw(x)              _SB_MAKEVALUE(x, S_MC_tRCw)
-#define G_MC_tRCw(x)              _SB_GETVALUE(x, S_MC_tRCw, M_MC_tRCw)
-#define K_MC_tRCw_DEFAULT         10
-#define V_MC_tRCw_DEFAULT         V_MC_tRCw(K_MC_tRCw_DEFAULT)
-
-#define S_MC_tRRD                 20
-#define M_MC_tRRD                 _SB_MAKEMASK(4, S_MC_tRRD)
-#define V_MC_tRRD(x)              _SB_MAKEVALUE(x, S_MC_tRRD)
-#define G_MC_tRRD(x)              _SB_GETVALUE(x, S_MC_tRRD, M_MC_tRRD)
-#define K_MC_tRRD_DEFAULT         2
-#define V_MC_tRRD_DEFAULT         V_MC_tRRD(K_MC_tRRD_DEFAULT)
-
-#define S_MC_tRP                  16
-#define M_MC_tRP                  _SB_MAKEMASK(4, S_MC_tRP)
-#define V_MC_tRP(x)               _SB_MAKEVALUE(x, S_MC_tRP)
-#define G_MC_tRP(x)               _SB_GETVALUE(x, S_MC_tRP, M_MC_tRP)
-#define K_MC_tRP_DEFAULT          4
-#define V_MC_tRP_DEFAULT          V_MC_tRP(K_MC_tRP_DEFAULT)
-
-#define S_MC_tCwD                 8
-#define M_MC_tCwD                 _SB_MAKEMASK(4, S_MC_tCwD)
-#define V_MC_tCwD(x)              _SB_MAKEVALUE(x, S_MC_tCwD)
-#define G_MC_tCwD(x)              _SB_GETVALUE(x, S_MC_tCwD, M_MC_tCwD)
-#define K_MC_tCwD_DEFAULT         1
-#define V_MC_tCwD_DEFAULT         V_MC_tCwD(K_MC_tCwD_DEFAULT)
-
-#define M_tCrDh                   _SB_MAKEMASK1(7)
-#define M_MC_tCrDh                M_tCrDh
-
-#define S_MC_tCrD                 4
-#define M_MC_tCrD                 _SB_MAKEMASK(3, S_MC_tCrD)
-#define V_MC_tCrD(x)              _SB_MAKEVALUE(x, S_MC_tCrD)
-#define G_MC_tCrD(x)              _SB_GETVALUE(x, S_MC_tCrD, M_MC_tCrD)
-#define K_MC_tCrD_DEFAULT         2
-#define V_MC_tCrD_DEFAULT         V_MC_tCrD(K_MC_tCrD_DEFAULT)
-
-#define S_MC_tRCD                 0
-#define M_MC_tRCD                 _SB_MAKEMASK(4, S_MC_tRCD)
-#define V_MC_tRCD(x)              _SB_MAKEVALUE(x, S_MC_tRCD)
-#define G_MC_tRCD(x)              _SB_GETVALUE(x, S_MC_tRCD, M_MC_tRCD)
-#define K_MC_tRCD_DEFAULT         3
-#define V_MC_tRCD_DEFAULT         V_MC_tRCD(K_MC_tRCD_DEFAULT)
-
-#define V_MC_TIMING_DEFAULT     V_MC_tFIFO(K_MC_tFIFO_DEFAULT) | \
-                                V_MC_tRFC(K_MC_tRFC_DEFAULT) | \
-                                V_MC_tCwCr(K_MC_tCwCr_DEFAULT) | \
-                                V_MC_tRCr(K_MC_tRCr_DEFAULT) | \
-                                V_MC_tRCw(K_MC_tRCw_DEFAULT) | \
-                                V_MC_tRRD(K_MC_tRRD_DEFAULT) | \
-                                V_MC_tRP(K_MC_tRP_DEFAULT) | \
-                                V_MC_tCwD(K_MC_tCwD_DEFAULT) | \
-                                V_MC_tCrD(K_MC_tCrD_DEFAULT) | \
-                                V_MC_tRCD(K_MC_tRCD_DEFAULT) | \
-                                M_MC_r2rIDLE_TWOCYCLES
-
-/*
- * Errata says these are not the default
- *                               M_MC_w2rIDLE_TWOCYCLES | \
- *                               M_MC_r2wIDLE_TWOCYCLES | \
- */
-
-
-/*
- * Chip Select Start Address Register (Table 6-17)
- */
-
-#define S_MC_CS0_START              0
-#define M_MC_CS0_START              _SB_MAKEMASK(16, S_MC_CS0_START)
-#define V_MC_CS0_START(x)           _SB_MAKEVALUE(x, S_MC_CS0_START)
-#define G_MC_CS0_START(x)           _SB_GETVALUE(x, S_MC_CS0_START, M_MC_CS0_START)
-
-#define S_MC_CS1_START              16
-#define M_MC_CS1_START              _SB_MAKEMASK(16, S_MC_CS1_START)
-#define V_MC_CS1_START(x)           _SB_MAKEVALUE(x, S_MC_CS1_START)
-#define G_MC_CS1_START(x)           _SB_GETVALUE(x, S_MC_CS1_START, M_MC_CS1_START)
-
-#define S_MC_CS2_START              32
-#define M_MC_CS2_START              _SB_MAKEMASK(16, S_MC_CS2_START)
-#define V_MC_CS2_START(x)           _SB_MAKEVALUE(x, S_MC_CS2_START)
-#define G_MC_CS2_START(x)           _SB_GETVALUE(x, S_MC_CS2_START, M_MC_CS2_START)
-
-#define S_MC_CS3_START              48
-#define M_MC_CS3_START              _SB_MAKEMASK(16, S_MC_CS3_START)
-#define V_MC_CS3_START(x)           _SB_MAKEVALUE(x, S_MC_CS3_START)
-#define G_MC_CS3_START(x)           _SB_GETVALUE(x, S_MC_CS3_START, M_MC_CS3_START)
-
-/*
- * Chip Select End Address Register (Table 6-18)
- */
-
-#define S_MC_CS0_END                0
-#define M_MC_CS0_END                _SB_MAKEMASK(16, S_MC_CS0_END)
-#define V_MC_CS0_END(x)             _SB_MAKEVALUE(x, S_MC_CS0_END)
-#define G_MC_CS0_END(x)             _SB_GETVALUE(x, S_MC_CS0_END, M_MC_CS0_END)
-
-#define S_MC_CS1_END                16
-#define M_MC_CS1_END                _SB_MAKEMASK(16, S_MC_CS1_END)
-#define V_MC_CS1_END(x)             _SB_MAKEVALUE(x, S_MC_CS1_END)
-#define G_MC_CS1_END(x)             _SB_GETVALUE(x, S_MC_CS1_END, M_MC_CS1_END)
-
-#define S_MC_CS2_END                32
-#define M_MC_CS2_END                _SB_MAKEMASK(16, S_MC_CS2_END)
-#define V_MC_CS2_END(x)             _SB_MAKEVALUE(x, S_MC_CS2_END)
-#define G_MC_CS2_END(x)             _SB_GETVALUE(x, S_MC_CS2_END, M_MC_CS2_END)
-
-#define S_MC_CS3_END                48
-#define M_MC_CS3_END                _SB_MAKEMASK(16, S_MC_CS3_END)
-#define V_MC_CS3_END(x)             _SB_MAKEVALUE(x, S_MC_CS3_END)
-#define G_MC_CS3_END(x)             _SB_GETVALUE(x, S_MC_CS3_END, M_MC_CS3_END)
-
-/*
- * Chip Select Interleave Register (Table 6-19)
- */
-
-#define S_MC_INTLV_RESERVED         0
-#define M_MC_INTLV_RESERVED         _SB_MAKEMASK(5, S_MC_INTLV_RESERVED)
-
-#define S_MC_INTERLEAVE             7
-#define M_MC_INTERLEAVE             _SB_MAKEMASK(18, S_MC_INTERLEAVE)
-#define V_MC_INTERLEAVE(x)          _SB_MAKEVALUE(x, S_MC_INTERLEAVE)
-
-#define S_MC_INTLV_MBZ              25
-#define M_MC_INTLV_MBZ              _SB_MAKEMASK(39, S_MC_INTLV_MBZ)
-
-/*
- * Row Address Bits Register (Table 6-20)
- */
-
-#define S_MC_RAS_RESERVED           0
-#define M_MC_RAS_RESERVED           _SB_MAKEMASK(5, S_MC_RAS_RESERVED)
-
-#define S_MC_RAS_SELECT             12
-#define M_MC_RAS_SELECT             _SB_MAKEMASK(25, S_MC_RAS_SELECT)
-#define V_MC_RAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_RAS_SELECT)
-
-#define S_MC_RAS_MBZ                37
-#define M_MC_RAS_MBZ                _SB_MAKEMASK(27, S_MC_RAS_MBZ)
-
-
-/*
- * Column Address Bits Register (Table 6-21)
- */
-
-#define S_MC_CAS_RESERVED           0
-#define M_MC_CAS_RESERVED           _SB_MAKEMASK(5, S_MC_CAS_RESERVED)
-
-#define S_MC_CAS_SELECT             5
-#define M_MC_CAS_SELECT             _SB_MAKEMASK(18, S_MC_CAS_SELECT)
-#define V_MC_CAS_SELECT(x)          _SB_MAKEVALUE(x, S_MC_CAS_SELECT)
-
-#define S_MC_CAS_MBZ                23
-#define M_MC_CAS_MBZ                _SB_MAKEMASK(41, S_MC_CAS_MBZ)
-
-
-/*
- * Bank Address Address Bits Register (Table 6-22)
- */
-
-#define S_MC_BA_RESERVED            0
-#define M_MC_BA_RESERVED            _SB_MAKEMASK(5, S_MC_BA_RESERVED)
-
-#define S_MC_BA_SELECT              5
-#define M_MC_BA_SELECT              _SB_MAKEMASK(20, S_MC_BA_SELECT)
-#define V_MC_BA_SELECT(x)           _SB_MAKEVALUE(x, S_MC_BA_SELECT)
-
-#define S_MC_BA_MBZ                 25
-#define M_MC_BA_MBZ                 _SB_MAKEMASK(39, S_MC_BA_MBZ)
-
-/*
- * Chip Select Attribute Register (Table 6-23)
- */
-
-#define K_MC_CS_ATTR_CLOSED         0
-#define K_MC_CS_ATTR_CASCHECK       1
-#define K_MC_CS_ATTR_HINT           2
-#define K_MC_CS_ATTR_OPEN           3
-
-#define S_MC_CS0_PAGE               0
-#define M_MC_CS0_PAGE               _SB_MAKEMASK(2, S_MC_CS0_PAGE)
-#define V_MC_CS0_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS0_PAGE)
-#define G_MC_CS0_PAGE(x)            _SB_GETVALUE(x, S_MC_CS0_PAGE, M_MC_CS0_PAGE)
-
-#define S_MC_CS1_PAGE               16
-#define M_MC_CS1_PAGE               _SB_MAKEMASK(2, S_MC_CS1_PAGE)
-#define V_MC_CS1_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS1_PAGE)
-#define G_MC_CS1_PAGE(x)            _SB_GETVALUE(x, S_MC_CS1_PAGE, M_MC_CS1_PAGE)
-
-#define S_MC_CS2_PAGE               32
-#define M_MC_CS2_PAGE               _SB_MAKEMASK(2, S_MC_CS2_PAGE)
-#define V_MC_CS2_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS2_PAGE)
-#define G_MC_CS2_PAGE(x)            _SB_GETVALUE(x, S_MC_CS2_PAGE, M_MC_CS2_PAGE)
-
-#define S_MC_CS3_PAGE               48
-#define M_MC_CS3_PAGE               _SB_MAKEMASK(2, S_MC_CS3_PAGE)
-#define V_MC_CS3_PAGE(x)            _SB_MAKEVALUE(x, S_MC_CS3_PAGE)
-#define G_MC_CS3_PAGE(x)            _SB_GETVALUE(x, S_MC_CS3_PAGE, M_MC_CS3_PAGE)
-
-/*
- * ECC Test ECC Register (Table 6-25)
- */
-
-#define S_MC_ECC_INVERT             0
-#define M_MC_ECC_INVERT             _SB_MAKEMASK(8, S_MC_ECC_INVERT)
-
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_regs.h b/include/asm-mips/sibyte/sb1250_regs.h
deleted file mode 100644
index 8f53ec817a5e..000000000000
--- a/include/asm-mips/sibyte/sb1250_regs.h
+++ /dev/null
@@ -1,893 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  Register Definitions                     File: sb1250_regs.h
-    *
-    *  This module contains the addresses of the on-chip peripherals
-    *  on the SB1250.
-    *
-    *  SB1250 specification level:  01/02/2002
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_REGS_H
-#define _SB1250_REGS_H
-
-#include "sb1250_defs.h"
-
-
-/*  *********************************************************************
-    *  Some general notes:
-    *
-    *  For the most part, when there is more than one peripheral
-    *  of the same type on the SOC, the constants below will be
-    *  offsets from the base of each peripheral.  For example,
-    *  the MAC registers are described as offsets from the first
-    *  MAC register, and there will be a MAC_REGISTER() macro
-    *  to calculate the base address of a given MAC.
-    *
-    *  The information in this file is based on the SB1250 SOC
-    *  manual version 0.2, July 2000.
-    ********************************************************************* */
-
-
-/*  *********************************************************************
-    * Memory Controller Registers
-    ********************************************************************* */
-
-/*
- * XXX: can't remove MC base 0 if 112x, since it's used by other macros,
- * since there is one reg there (but it could get its addr/offset constant).
- */
-
-#if SIBYTE_HDR_FEATURE_1250_112x                /* This MC only on 1250 & 112x */
-#define A_MC_BASE_0                 0x0010051000
-#define A_MC_BASE_1                 0x0010052000
-#define MC_REGISTER_SPACING         0x1000
-
-#define A_MC_BASE(ctlid)            ((ctlid)*MC_REGISTER_SPACING+A_MC_BASE_0)
-#define A_MC_REGISTER(ctlid, reg)    (A_MC_BASE(ctlid)+(reg))
-
-#define R_MC_CONFIG                 0x0000000100
-#define R_MC_DRAMCMD                0x0000000120
-#define R_MC_DRAMMODE               0x0000000140
-#define R_MC_TIMING1                0x0000000160
-#define R_MC_TIMING2                0x0000000180
-#define R_MC_CS_START               0x00000001A0
-#define R_MC_CS_END                 0x00000001C0
-#define R_MC_CS_INTERLEAVE          0x00000001E0
-#define S_MC_CS_STARTEND            16
-
-#define R_MC_CSX_BASE               0x0000000200
-#define R_MC_CSX_ROW                0x0000000000        /* relative to CSX_BASE, above */
-#define R_MC_CSX_COL                0x0000000020        /* relative to CSX_BASE, above */
-#define R_MC_CSX_BA                 0x0000000040        /* relative to CSX_BASE, above */
-#define MC_CSX_SPACING              0x0000000060        /* relative to CSX_BASE, above */
-
-#define R_MC_CS0_ROW                0x0000000200
-#define R_MC_CS0_COL                0x0000000220
-#define R_MC_CS0_BA                 0x0000000240
-#define R_MC_CS1_ROW                0x0000000260
-#define R_MC_CS1_COL                0x0000000280
-#define R_MC_CS1_BA                 0x00000002A0
-#define R_MC_CS2_ROW                0x00000002C0
-#define R_MC_CS2_COL                0x00000002E0
-#define R_MC_CS2_BA                 0x0000000300
-#define R_MC_CS3_ROW                0x0000000320
-#define R_MC_CS3_COL                0x0000000340
-#define R_MC_CS3_BA                 0x0000000360
-#define R_MC_CS_ATTR                0x0000000380
-#define R_MC_TEST_DATA              0x0000000400
-#define R_MC_TEST_ECC               0x0000000420
-#define R_MC_MCLK_CFG               0x0000000500
-
-#endif  /* 1250 & 112x */
-
-/*  *********************************************************************
-    * L2 Cache Control Registers
-    ********************************************************************* */
-
-#if SIBYTE_HDR_FEATURE_1250_112x        /* This L2C only on 1250/112x */
-
-#define A_L2_READ_TAG               0x0010040018
-#define A_L2_ECC_TAG                0x0010040038
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_L2_READ_MISC              0x0010040058
-#endif /* 1250 PASS3 || 112x PASS1 */
-#define A_L2_WAY_DISABLE            0x0010041000
-#define A_L2_MAKEDISABLE(x)         (A_L2_WAY_DISABLE | (((~(x))&0x0F) << 8))
-#define A_L2_MGMT_TAG_BASE          0x00D0000000
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_L2_CACHE_DISABLE         0x0010042000
-#define A_L2_MAKECACHEDISABLE(x)   (A_L2_CACHE_DISABLE | (((x)&0x0F) << 8))
-#define A_L2_MISC_CONFIG           0x0010043000
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-/* Backward-compatibility definitions.  */
-/* XXX: discourage people from using these constants.  */
-#define A_L2_READ_ADDRESS           A_L2_READ_TAG
-#define A_L2_EEC_ADDRESS            A_L2_ECC_TAG
-
-#endif
-
-
-/*  *********************************************************************
-    * PCI Interface Registers
-    ********************************************************************* */
-
-#if SIBYTE_HDR_FEATURE_1250_112x        /* This PCI/HT only on 1250/112x */
-#define A_PCI_TYPE00_HEADER         0x00DE000000
-#define A_PCI_TYPE01_HEADER         0x00DE000800
-#endif
-
-
-/*  *********************************************************************
-    * Ethernet DMA and MACs
-    ********************************************************************* */
-
-#define A_MAC_BASE_0                0x0010064000
-#define A_MAC_BASE_1                0x0010065000
-#if SIBYTE_HDR_FEATURE_CHIP(1250)
-#define A_MAC_BASE_2                0x0010066000
-#endif /* 1250 */
-
-#define MAC_SPACING                 0x1000
-#define MAC_DMA_TXRX_SPACING        0x0400
-#define MAC_DMA_CHANNEL_SPACING     0x0100
-#define DMA_RX                      0
-#define DMA_TX                      1
-#define MAC_NUM_DMACHAN             2               /* channels per direction */
-
-/* XXX: not correct; depends on SOC type.  */
-#define MAC_NUM_PORTS               3
-
-#define A_MAC_CHANNEL_BASE(macnum)                  \
-            (A_MAC_BASE_0 +                         \
-             MAC_SPACING*(macnum))
-
-#define A_MAC_REGISTER(macnum,reg)                  \
-            (A_MAC_BASE_0 +                         \
-             MAC_SPACING*(macnum) + (reg))
-
-
-#define R_MAC_DMA_CHANNELS              0x800 /* Relative to A_MAC_CHANNEL_BASE */
-
-#define A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan)  \
-             ((A_MAC_CHANNEL_BASE(macnum)) +        \
-             R_MAC_DMA_CHANNELS +                   \
-             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
-             (MAC_DMA_CHANNEL_SPACING*(chan)))
-
-#define R_MAC_DMA_CHANNEL_BASE(txrx, chan)              \
-             (R_MAC_DMA_CHANNELS +                   \
-             (MAC_DMA_TXRX_SPACING*(txrx)) +        \
-             (MAC_DMA_CHANNEL_SPACING*(chan)))
-
-#define A_MAC_DMA_REGISTER(macnum, txrx, chan, reg)           \
-            (A_MAC_DMA_CHANNEL_BASE(macnum, txrx, chan) +    \
-            (reg))
-
-#define R_MAC_DMA_REGISTER(txrx, chan, reg)           \
-            (R_MAC_DMA_CHANNEL_BASE(txrx, chan) +    \
-            (reg))
-
-/*
- * DMA channel registers, relative to A_MAC_DMA_CHANNEL_BASE
- */
-
-#define R_MAC_DMA_CONFIG0               0x00000000
-#define R_MAC_DMA_CONFIG1               0x00000008
-#define R_MAC_DMA_DSCR_BASE             0x00000010
-#define R_MAC_DMA_DSCR_CNT              0x00000018
-#define R_MAC_DMA_CUR_DSCRA             0x00000020
-#define R_MAC_DMA_CUR_DSCRB             0x00000028
-#define R_MAC_DMA_CUR_DSCRADDR          0x00000030
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define R_MAC_DMA_OODPKTLOST_RX         0x00000038      /* rx only */
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-/*
- * RMON Counters
- */
-
-#define R_MAC_RMON_TX_BYTES             0x00000000
-#define R_MAC_RMON_COLLISIONS           0x00000008
-#define R_MAC_RMON_LATE_COL             0x00000010
-#define R_MAC_RMON_EX_COL               0x00000018
-#define R_MAC_RMON_FCS_ERROR            0x00000020
-#define R_MAC_RMON_TX_ABORT             0x00000028
-/* Counter #6 (0x30) now reserved */
-#define R_MAC_RMON_TX_BAD               0x00000038
-#define R_MAC_RMON_TX_GOOD              0x00000040
-#define R_MAC_RMON_TX_RUNT              0x00000048
-#define R_MAC_RMON_TX_OVERSIZE          0x00000050
-#define R_MAC_RMON_RX_BYTES             0x00000080
-#define R_MAC_RMON_RX_MCAST             0x00000088
-#define R_MAC_RMON_RX_BCAST             0x00000090
-#define R_MAC_RMON_RX_BAD               0x00000098
-#define R_MAC_RMON_RX_GOOD              0x000000A0
-#define R_MAC_RMON_RX_RUNT              0x000000A8
-#define R_MAC_RMON_RX_OVERSIZE          0x000000B0
-#define R_MAC_RMON_RX_FCS_ERROR         0x000000B8
-#define R_MAC_RMON_RX_LENGTH_ERROR      0x000000C0
-#define R_MAC_RMON_RX_CODE_ERROR        0x000000C8
-#define R_MAC_RMON_RX_ALIGN_ERROR       0x000000D0
-
-/* Updated to spec 0.2 */
-#define R_MAC_CFG                       0x00000100
-#define R_MAC_THRSH_CFG                 0x00000108
-#define R_MAC_VLANTAG                   0x00000110
-#define R_MAC_FRAMECFG                  0x00000118
-#define R_MAC_EOPCNT                    0x00000120
-#define R_MAC_FIFO_PTRS                 0x00000128
-#define R_MAC_ADFILTER_CFG              0x00000200
-#define R_MAC_ETHERNET_ADDR             0x00000208
-#define R_MAC_PKT_TYPE                  0x00000210
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define R_MAC_ADMASK0                   0x00000218
-#define R_MAC_ADMASK1                   0x00000220
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-#define R_MAC_HASH_BASE                 0x00000240
-#define R_MAC_ADDR_BASE                 0x00000280
-#define R_MAC_CHLO0_BASE                0x00000300
-#define R_MAC_CHUP0_BASE                0x00000320
-#define R_MAC_ENABLE                    0x00000400
-#define R_MAC_STATUS                    0x00000408
-#define R_MAC_INT_MASK                  0x00000410
-#define R_MAC_TXD_CTL                   0x00000420
-#define R_MAC_MDIO                      0x00000428
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define R_MAC_STATUS1                   0x00000430
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-#define R_MAC_DEBUG_STATUS              0x00000448
-
-#define MAC_HASH_COUNT                  8
-#define MAC_ADDR_COUNT                  8
-#define MAC_CHMAP_COUNT                 4
-
-
-/*  *********************************************************************
-    * DUART Registers
-    ********************************************************************* */
-
-
-#if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
-#define R_DUART_NUM_PORTS           2
-
-#define A_DUART                     0x0010060000
-
-#define DUART_CHANREG_SPACING       0x100
-
-#define A_DUART_CHANREG(chan, reg)                                      \
-        (A_DUART + DUART_CHANREG_SPACING * ((chan) + 1) + (reg))
-#endif  /* 1250 & 112x */
-
-#define R_DUART_MODE_REG_1          0x000
-#define R_DUART_MODE_REG_2          0x010
-#define R_DUART_STATUS              0x020
-#define R_DUART_CLK_SEL             0x030
-#define R_DUART_CMD                 0x050
-#define R_DUART_RX_HOLD             0x060
-#define R_DUART_TX_HOLD             0x070
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define R_DUART_FULL_CTL            0x040
-#define R_DUART_OPCR_X              0x080
-#define R_DUART_AUXCTL_X            0x090
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-
-/*
- * The IMR and ISR can't be addressed with A_DUART_CHANREG,
- * so use these macros instead.
- */
-
-#if SIBYTE_HDR_FEATURE_1250_112x    /* This MC only on 1250 & 112x */
-#define DUART_IMRISR_SPACING        0x20
-#define DUART_INCHNG_SPACING        0x10
-
-#define A_DUART_CTRLREG(reg)                                            \
-        (A_DUART + DUART_CHANREG_SPACING * 3 + (reg))
-
-#define R_DUART_IMRREG(chan)                                            \
-        (R_DUART_IMR_A + (chan) * DUART_IMRISR_SPACING)
-#define R_DUART_ISRREG(chan)                                            \
-        (R_DUART_ISR_A + (chan) * DUART_IMRISR_SPACING)
-#define R_DUART_INCHREG(chan)                                           \
-        (R_DUART_IN_CHNG_A + (chan) * DUART_INCHNG_SPACING)
-
-#define A_DUART_IMRREG(chan)        A_DUART_CTRLREG(R_DUART_IMRREG(chan))
-#define A_DUART_ISRREG(chan)        A_DUART_CTRLREG(R_DUART_ISRREG(chan))
-#define A_DUART_INCHREG(chan)       A_DUART_CTRLREG(R_DUART_INCHREG(chan))
-#endif  /* 1250 & 112x */
-
-#define R_DUART_AUX_CTRL            0x010
-#define R_DUART_ISR_A               0x020
-#define R_DUART_IMR_A               0x030
-#define R_DUART_ISR_B               0x040
-#define R_DUART_IMR_B               0x050
-#define R_DUART_OUT_PORT            0x060
-#define R_DUART_OPCR                0x070
-#define R_DUART_IN_PORT             0x080
-
-#define R_DUART_SET_OPR             0x0B0
-#define R_DUART_CLEAR_OPR           0x0C0
-#define R_DUART_IN_CHNG_A           0x0D0
-#define R_DUART_IN_CHNG_B           0x0E0
-
-
-/*
- * These constants are the absolute addresses.
- */
-
-#define A_DUART_MODE_REG_1_A        0x0010060100
-#define A_DUART_MODE_REG_2_A        0x0010060110
-#define A_DUART_STATUS_A            0x0010060120
-#define A_DUART_CLK_SEL_A           0x0010060130
-#define A_DUART_CMD_A               0x0010060150
-#define A_DUART_RX_HOLD_A           0x0010060160
-#define A_DUART_TX_HOLD_A           0x0010060170
-
-#define A_DUART_MODE_REG_1_B        0x0010060200
-#define A_DUART_MODE_REG_2_B        0x0010060210
-#define A_DUART_STATUS_B            0x0010060220
-#define A_DUART_CLK_SEL_B           0x0010060230
-#define A_DUART_CMD_B               0x0010060250
-#define A_DUART_RX_HOLD_B           0x0010060260
-#define A_DUART_TX_HOLD_B           0x0010060270
-
-#define A_DUART_INPORT_CHNG         0x0010060300
-#define A_DUART_AUX_CTRL            0x0010060310
-#define A_DUART_ISR_A               0x0010060320
-#define A_DUART_IMR_A               0x0010060330
-#define A_DUART_ISR_B               0x0010060340
-#define A_DUART_IMR_B               0x0010060350
-#define A_DUART_OUT_PORT            0x0010060360
-#define A_DUART_OPCR                0x0010060370
-#define A_DUART_IN_PORT             0x0010060380
-#define A_DUART_ISR                 0x0010060390
-#define A_DUART_IMR                 0x00100603A0
-#define A_DUART_SET_OPR             0x00100603B0
-#define A_DUART_CLEAR_OPR           0x00100603C0
-#define A_DUART_INPORT_CHNG_A       0x00100603D0
-#define A_DUART_INPORT_CHNG_B       0x00100603E0
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_DUART_FULL_CTL_A          0x0010060140
-#define A_DUART_FULL_CTL_B          0x0010060240
-
-#define A_DUART_OPCR_A              0x0010060180
-#define A_DUART_OPCR_B              0x0010060280
-
-#define A_DUART_INPORT_CHNG_DEBUG   0x00100603F0
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-
-/*  *********************************************************************
-    * Synchronous Serial Registers
-    ********************************************************************* */
-
-
-#if SIBYTE_HDR_FEATURE_1250_112x        /* sync serial only on 1250/112x */
-
-#define A_SER_BASE_0                0x0010060400
-#define A_SER_BASE_1                0x0010060800
-#define SER_SPACING                 0x400
-
-#define SER_DMA_TXRX_SPACING        0x80
-
-#define SER_NUM_PORTS               2
-
-#define A_SER_CHANNEL_BASE(sernum)                  \
-            (A_SER_BASE_0 +                         \
-             SER_SPACING*(sernum))
-
-#define A_SER_REGISTER(sernum,reg)                  \
-            (A_SER_BASE_0 +                         \
-             SER_SPACING*(sernum) + (reg))
-
-
-#define R_SER_DMA_CHANNELS              0   /* Relative to A_SER_BASE_x */
-
-#define A_SER_DMA_CHANNEL_BASE(sernum,txrx)    \
-             ((A_SER_CHANNEL_BASE(sernum)) +        \
-             R_SER_DMA_CHANNELS +                   \
-             (SER_DMA_TXRX_SPACING*(txrx)))
-
-#define A_SER_DMA_REGISTER(sernum, txrx, reg)           \
-            (A_SER_DMA_CHANNEL_BASE(sernum, txrx) +    \
-            (reg))
-
-
-/*
- * DMA channel registers, relative to A_SER_DMA_CHANNEL_BASE
- */
-
-#define R_SER_DMA_CONFIG0           0x00000000
-#define R_SER_DMA_CONFIG1           0x00000008
-#define R_SER_DMA_DSCR_BASE         0x00000010
-#define R_SER_DMA_DSCR_CNT          0x00000018
-#define R_SER_DMA_CUR_DSCRA         0x00000020
-#define R_SER_DMA_CUR_DSCRB         0x00000028
-#define R_SER_DMA_CUR_DSCRADDR      0x00000030
-
-#define R_SER_DMA_CONFIG0_RX        0x00000000
-#define R_SER_DMA_CONFIG1_RX        0x00000008
-#define R_SER_DMA_DSCR_BASE_RX      0x00000010
-#define R_SER_DMA_DSCR_COUNT_RX     0x00000018
-#define R_SER_DMA_CUR_DSCR_A_RX     0x00000020
-#define R_SER_DMA_CUR_DSCR_B_RX     0x00000028
-#define R_SER_DMA_CUR_DSCR_ADDR_RX  0x00000030
-
-#define R_SER_DMA_CONFIG0_TX        0x00000080
-#define R_SER_DMA_CONFIG1_TX        0x00000088
-#define R_SER_DMA_DSCR_BASE_TX      0x00000090
-#define R_SER_DMA_DSCR_COUNT_TX     0x00000098
-#define R_SER_DMA_CUR_DSCR_A_TX     0x000000A0
-#define R_SER_DMA_CUR_DSCR_B_TX     0x000000A8
-#define R_SER_DMA_CUR_DSCR_ADDR_TX  0x000000B0
-
-#define R_SER_MODE                  0x00000100
-#define R_SER_MINFRM_SZ             0x00000108
-#define R_SER_MAXFRM_SZ             0x00000110
-#define R_SER_ADDR                  0x00000118
-#define R_SER_USR0_ADDR             0x00000120
-#define R_SER_USR1_ADDR             0x00000128
-#define R_SER_USR2_ADDR             0x00000130
-#define R_SER_USR3_ADDR             0x00000138
-#define R_SER_CMD                   0x00000140
-#define R_SER_TX_RD_THRSH           0x00000160
-#define R_SER_TX_WR_THRSH           0x00000168
-#define R_SER_RX_RD_THRSH           0x00000170
-#define R_SER_LINE_MODE             0x00000178
-#define R_SER_DMA_ENABLE            0x00000180
-#define R_SER_INT_MASK              0x00000190
-#define R_SER_STATUS                0x00000188
-#define R_SER_STATUS_DEBUG          0x000001A8
-#define R_SER_RX_TABLE_BASE         0x00000200
-#define SER_RX_TABLE_COUNT          16
-#define R_SER_TX_TABLE_BASE         0x00000300
-#define SER_TX_TABLE_COUNT          16
-
-/* RMON Counters */
-#define R_SER_RMON_TX_BYTE_LO       0x000001C0
-#define R_SER_RMON_TX_BYTE_HI       0x000001C8
-#define R_SER_RMON_RX_BYTE_LO       0x000001D0
-#define R_SER_RMON_RX_BYTE_HI       0x000001D8
-#define R_SER_RMON_TX_UNDERRUN      0x000001E0
-#define R_SER_RMON_RX_OVERFLOW      0x000001E8
-#define R_SER_RMON_RX_ERRORS        0x000001F0
-#define R_SER_RMON_RX_BADADDR       0x000001F8
-
-#endif  /* 1250/112x */
-
-/*  *********************************************************************
-    * Generic Bus Registers
-    ********************************************************************* */
-
-#define IO_EXT_CFG_COUNT            8
-
-#define A_IO_EXT_BASE               0x0010061000
-#define A_IO_EXT_REG(r)             (A_IO_EXT_BASE + (r))
-
-#define A_IO_EXT_CFG_BASE           0x0010061000
-#define A_IO_EXT_MULT_SIZE_BASE     0x0010061100
-#define A_IO_EXT_START_ADDR_BASE    0x0010061200
-#define A_IO_EXT_TIME_CFG0_BASE     0x0010061600
-#define A_IO_EXT_TIME_CFG1_BASE     0x0010061700
-
-#define IO_EXT_REGISTER_SPACING     8
-#define A_IO_EXT_CS_BASE(cs)        (A_IO_EXT_CFG_BASE+IO_EXT_REGISTER_SPACING*(cs))
-#define R_IO_EXT_REG(reg, cs)       ((cs)*IO_EXT_REGISTER_SPACING + (reg))
-
-#define R_IO_EXT_CFG                0x0000
-#define R_IO_EXT_MULT_SIZE          0x0100
-#define R_IO_EXT_START_ADDR         0x0200
-#define R_IO_EXT_TIME_CFG0          0x0600
-#define R_IO_EXT_TIME_CFG1          0x0700
-
-
-#define A_IO_INTERRUPT_STATUS       0x0010061A00
-#define A_IO_INTERRUPT_DATA0        0x0010061A10
-#define A_IO_INTERRUPT_DATA1        0x0010061A18
-#define A_IO_INTERRUPT_DATA2        0x0010061A20
-#define A_IO_INTERRUPT_DATA3        0x0010061A28
-#define A_IO_INTERRUPT_ADDR0        0x0010061A30
-#define A_IO_INTERRUPT_ADDR1        0x0010061A40
-#define A_IO_INTERRUPT_PARITY       0x0010061A50
-#define A_IO_PCMCIA_CFG             0x0010061A60
-#define A_IO_PCMCIA_STATUS          0x0010061A70
-#define A_IO_DRIVE_0                0x0010061300
-#define A_IO_DRIVE_1                0x0010061308
-#define A_IO_DRIVE_2                0x0010061310
-#define A_IO_DRIVE_3                0x0010061318
-#define A_IO_DRIVE_BASE             A_IO_DRIVE_0
-#define IO_DRIVE_REGISTER_SPACING   8
-#define R_IO_DRIVE(x)               ((x)*IO_DRIVE_REGISTER_SPACING)
-#define A_IO_DRIVE(x)               (A_IO_DRIVE_BASE + R_IO_DRIVE(x))
-
-#define R_IO_INTERRUPT_STATUS       0x0A00
-#define R_IO_INTERRUPT_DATA0        0x0A10
-#define R_IO_INTERRUPT_DATA1        0x0A18
-#define R_IO_INTERRUPT_DATA2        0x0A20
-#define R_IO_INTERRUPT_DATA3        0x0A28
-#define R_IO_INTERRUPT_ADDR0        0x0A30
-#define R_IO_INTERRUPT_ADDR1        0x0A40
-#define R_IO_INTERRUPT_PARITY       0x0A50
-#define R_IO_PCMCIA_CFG             0x0A60
-#define R_IO_PCMCIA_STATUS          0x0A70
-
-/*  *********************************************************************
-    * GPIO Registers
-    ********************************************************************* */
-
-#define A_GPIO_CLR_EDGE             0x0010061A80
-#define A_GPIO_INT_TYPE             0x0010061A88
-#define A_GPIO_INPUT_INVERT         0x0010061A90
-#define A_GPIO_GLITCH               0x0010061A98
-#define A_GPIO_READ                 0x0010061AA0
-#define A_GPIO_DIRECTION            0x0010061AA8
-#define A_GPIO_PIN_CLR              0x0010061AB0
-#define A_GPIO_PIN_SET              0x0010061AB8
-
-#define A_GPIO_BASE                 0x0010061A80
-
-#define R_GPIO_CLR_EDGE             0x00
-#define R_GPIO_INT_TYPE             0x08
-#define R_GPIO_INPUT_INVERT         0x10
-#define R_GPIO_GLITCH               0x18
-#define R_GPIO_READ                 0x20
-#define R_GPIO_DIRECTION            0x28
-#define R_GPIO_PIN_CLR              0x30
-#define R_GPIO_PIN_SET              0x38
-
-/*  *********************************************************************
-    * SMBus Registers
-    ********************************************************************* */
-
-#define A_SMB_XTRA_0                0x0010060000
-#define A_SMB_XTRA_1                0x0010060008
-#define A_SMB_FREQ_0                0x0010060010
-#define A_SMB_FREQ_1                0x0010060018
-#define A_SMB_STATUS_0              0x0010060020
-#define A_SMB_STATUS_1              0x0010060028
-#define A_SMB_CMD_0                 0x0010060030
-#define A_SMB_CMD_1                 0x0010060038
-#define A_SMB_START_0               0x0010060040
-#define A_SMB_START_1               0x0010060048
-#define A_SMB_DATA_0                0x0010060050
-#define A_SMB_DATA_1                0x0010060058
-#define A_SMB_CONTROL_0             0x0010060060
-#define A_SMB_CONTROL_1             0x0010060068
-#define A_SMB_PEC_0                 0x0010060070
-#define A_SMB_PEC_1                 0x0010060078
-
-#define A_SMB_0                     0x0010060000
-#define A_SMB_1                     0x0010060008
-#define SMB_REGISTER_SPACING        0x8
-#define A_SMB_BASE(idx)             (A_SMB_0+(idx)*SMB_REGISTER_SPACING)
-#define A_SMB_REGISTER(idx, reg)    (A_SMB_BASE(idx)+(reg))
-
-#define R_SMB_XTRA                  0x0000000000
-#define R_SMB_FREQ                  0x0000000010
-#define R_SMB_STATUS                0x0000000020
-#define R_SMB_CMD                   0x0000000030
-#define R_SMB_START                 0x0000000040
-#define R_SMB_DATA                  0x0000000050
-#define R_SMB_CONTROL               0x0000000060
-#define R_SMB_PEC                   0x0000000070
-
-/*  *********************************************************************
-    * Timer Registers
-    ********************************************************************* */
-
-/*
- * Watchdog timers
- */
-
-#define A_SCD_WDOG_0                0x0010020050
-#define A_SCD_WDOG_1                0x0010020150
-#define SCD_WDOG_SPACING            0x100
-#define SCD_NUM_WDOGS               2
-#define A_SCD_WDOG_BASE(w)          (A_SCD_WDOG_0+SCD_WDOG_SPACING*(w))
-#define A_SCD_WDOG_REGISTER(w, r)   (A_SCD_WDOG_BASE(w) + (r))
-
-#define R_SCD_WDOG_INIT             0x0000000000
-#define R_SCD_WDOG_CNT              0x0000000008
-#define R_SCD_WDOG_CFG              0x0000000010
-
-#define A_SCD_WDOG_INIT_0           0x0010020050
-#define A_SCD_WDOG_CNT_0            0x0010020058
-#define A_SCD_WDOG_CFG_0            0x0010020060
-
-#define A_SCD_WDOG_INIT_1           0x0010020150
-#define A_SCD_WDOG_CNT_1            0x0010020158
-#define A_SCD_WDOG_CFG_1            0x0010020160
-
-/*
- * Generic timers
- */
-
-#define A_SCD_TIMER_0               0x0010020070
-#define A_SCD_TIMER_1               0x0010020078
-#define A_SCD_TIMER_2               0x0010020170
-#define A_SCD_TIMER_3               0x0010020178
-#define SCD_NUM_TIMERS              4
-#define A_SCD_TIMER_BASE(w)         (A_SCD_TIMER_0+0x08*((w)&1)+0x100*(((w)&2)>>1))
-#define A_SCD_TIMER_REGISTER(w, r)  (A_SCD_TIMER_BASE(w) + (r))
-
-#define R_SCD_TIMER_INIT            0x0000000000
-#define R_SCD_TIMER_CNT             0x0000000010
-#define R_SCD_TIMER_CFG             0x0000000020
-
-#define A_SCD_TIMER_INIT_0          0x0010020070
-#define A_SCD_TIMER_CNT_0           0x0010020080
-#define A_SCD_TIMER_CFG_0           0x0010020090
-
-#define A_SCD_TIMER_INIT_1          0x0010020078
-#define A_SCD_TIMER_CNT_1           0x0010020088
-#define A_SCD_TIMER_CFG_1           0x0010020098
-
-#define A_SCD_TIMER_INIT_2          0x0010020170
-#define A_SCD_TIMER_CNT_2           0x0010020180
-#define A_SCD_TIMER_CFG_2           0x0010020190
-
-#define A_SCD_TIMER_INIT_3          0x0010020178
-#define A_SCD_TIMER_CNT_3           0x0010020188
-#define A_SCD_TIMER_CFG_3           0x0010020198
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_SCD_SCRATCH              0x0010020C10
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define A_SCD_ZBBUS_CYCLE_COUNT    0x0010030000
-#define A_SCD_ZBBUS_CYCLE_CP0      0x0010020C00
-#define A_SCD_ZBBUS_CYCLE_CP1      0x0010020C08
-#endif
-
-/*  *********************************************************************
-    * System Control Registers
-    ********************************************************************* */
-
-#define A_SCD_SYSTEM_REVISION       0x0010020000
-#define A_SCD_SYSTEM_CFG            0x0010020008
-#define A_SCD_SYSTEM_MANUF          0x0010038000
-
-/*  *********************************************************************
-    * System Address Trap Registers
-    ********************************************************************* */
-
-#define A_ADDR_TRAP_INDEX           0x00100200B0
-#define A_ADDR_TRAP_REG             0x00100200B8
-#define A_ADDR_TRAP_UP_0            0x0010020400
-#define A_ADDR_TRAP_UP_1            0x0010020408
-#define A_ADDR_TRAP_UP_2            0x0010020410
-#define A_ADDR_TRAP_UP_3            0x0010020418
-#define A_ADDR_TRAP_DOWN_0          0x0010020420
-#define A_ADDR_TRAP_DOWN_1          0x0010020428
-#define A_ADDR_TRAP_DOWN_2          0x0010020430
-#define A_ADDR_TRAP_DOWN_3          0x0010020438
-#define A_ADDR_TRAP_CFG_0           0x0010020440
-#define A_ADDR_TRAP_CFG_1           0x0010020448
-#define A_ADDR_TRAP_CFG_2           0x0010020450
-#define A_ADDR_TRAP_CFG_3           0x0010020458
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define A_ADDR_TRAP_REG_DEBUG       0x0010020460
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#define ADDR_TRAP_SPACING 8
-#define NUM_ADDR_TRAP 4
-#define A_ADDR_TRAP_UP(n) (A_ADDR_TRAP_UP_0 + ((n) * ADDR_TRAP_SPACING))
-#define A_ADDR_TRAP_DOWN(n) (A_ADDR_TRAP_DOWN_0 + ((n) * ADDR_TRAP_SPACING))
-#define A_ADDR_TRAP_CFG(n) (A_ADDR_TRAP_CFG_0 + ((n) * ADDR_TRAP_SPACING))
-
-
-/*  *********************************************************************
-    * System Interrupt Mapper Registers
-    ********************************************************************* */
-
-#define A_IMR_CPU0_BASE                 0x0010020000
-#define A_IMR_CPU1_BASE                 0x0010022000
-#define IMR_REGISTER_SPACING            0x2000
-#define IMR_REGISTER_SPACING_SHIFT      13
-
-#define A_IMR_MAPPER(cpu) (A_IMR_CPU0_BASE+(cpu)*IMR_REGISTER_SPACING)
-#define A_IMR_REGISTER(cpu, reg) (A_IMR_MAPPER(cpu)+(reg))
-
-#define R_IMR_INTERRUPT_DIAG            0x0010
-#define R_IMR_INTERRUPT_LDT             0x0018
-#define R_IMR_INTERRUPT_MASK            0x0028
-#define R_IMR_INTERRUPT_TRACE           0x0038
-#define R_IMR_INTERRUPT_SOURCE_STATUS   0x0040
-#define R_IMR_LDT_INTERRUPT_SET         0x0048
-#define R_IMR_LDT_INTERRUPT             0x0018
-#define R_IMR_LDT_INTERRUPT_CLR         0x0020
-#define R_IMR_MAILBOX_CPU               0x00c0
-#define R_IMR_ALIAS_MAILBOX_CPU         0x1000
-#define R_IMR_MAILBOX_SET_CPU           0x00C8
-#define R_IMR_ALIAS_MAILBOX_SET_CPU     0x1008
-#define R_IMR_MAILBOX_CLR_CPU           0x00D0
-#define R_IMR_INTERRUPT_STATUS_BASE     0x0100
-#define R_IMR_INTERRUPT_STATUS_COUNT    7
-#define R_IMR_INTERRUPT_MAP_BASE        0x0200
-#define R_IMR_INTERRUPT_MAP_COUNT       64
-
-/*
- * these macros work together to build the address of a mailbox
- * register, e.g., A_MAILBOX_REGISTER(R_IMR_MAILBOX_SET_CPU,1)
- * for mbox_0_set_cpu2 returns 0x00100240C8
- */
-#define A_MAILBOX_REGISTER(reg,cpu) \
-    (A_IMR_CPU0_BASE + (cpu * IMR_REGISTER_SPACING) + reg)
-
-/*  *********************************************************************
-    * System Performance Counter Registers
-    ********************************************************************* */
-
-#define A_SCD_PERF_CNT_CFG          0x00100204C0
-#define A_SCD_PERF_CNT_0            0x00100204D0
-#define A_SCD_PERF_CNT_1            0x00100204D8
-#define A_SCD_PERF_CNT_2            0x00100204E0
-#define A_SCD_PERF_CNT_3            0x00100204E8
-
-#define SCD_NUM_PERF_CNT 4
-#define SCD_PERF_CNT_SPACING 8
-#define A_SCD_PERF_CNT(n) (A_SCD_PERF_CNT_0+(n*SCD_PERF_CNT_SPACING))
-
-/*  *********************************************************************
-    * System Bus Watcher Registers
-    ********************************************************************* */
-
-#define A_SCD_BUS_ERR_STATUS        0x0010020880
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_SCD_BUS_ERR_STATUS_DEBUG  0x00100208D0
-#define A_BUS_ERR_STATUS_DEBUG  0x00100208D0
-#endif /* 1250 PASS2 || 112x PASS1 */
-#define A_BUS_ERR_DATA_0            0x00100208A0
-#define A_BUS_ERR_DATA_1            0x00100208A8
-#define A_BUS_ERR_DATA_2            0x00100208B0
-#define A_BUS_ERR_DATA_3            0x00100208B8
-#define A_BUS_L2_ERRORS             0x00100208C0
-#define A_BUS_MEM_IO_ERRORS         0x00100208C8
-
-/*  *********************************************************************
-    * System Debug Controller Registers
-    ********************************************************************* */
-
-#define A_SCD_JTAG_BASE             0x0010000000
-
-/*  *********************************************************************
-    * System Trace Buffer Registers
-    ********************************************************************* */
-
-#define A_SCD_TRACE_CFG             0x0010020A00
-#define A_SCD_TRACE_READ            0x0010020A08
-#define A_SCD_TRACE_EVENT_0         0x0010020A20
-#define A_SCD_TRACE_EVENT_1         0x0010020A28
-#define A_SCD_TRACE_EVENT_2         0x0010020A30
-#define A_SCD_TRACE_EVENT_3         0x0010020A38
-#define A_SCD_TRACE_SEQUENCE_0      0x0010020A40
-#define A_SCD_TRACE_SEQUENCE_1      0x0010020A48
-#define A_SCD_TRACE_SEQUENCE_2      0x0010020A50
-#define A_SCD_TRACE_SEQUENCE_3      0x0010020A58
-#define A_SCD_TRACE_EVENT_4         0x0010020A60
-#define A_SCD_TRACE_EVENT_5         0x0010020A68
-#define A_SCD_TRACE_EVENT_6         0x0010020A70
-#define A_SCD_TRACE_EVENT_7         0x0010020A78
-#define A_SCD_TRACE_SEQUENCE_4      0x0010020A80
-#define A_SCD_TRACE_SEQUENCE_5      0x0010020A88
-#define A_SCD_TRACE_SEQUENCE_6      0x0010020A90
-#define A_SCD_TRACE_SEQUENCE_7      0x0010020A98
-
-#define TRACE_REGISTER_SPACING 8
-#define TRACE_NUM_REGISTERS    8
-#define A_SCD_TRACE_EVENT(n) (((n) & 4) ? \
-   (A_SCD_TRACE_EVENT_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
-   (A_SCD_TRACE_EVENT_0 + ((n) * TRACE_REGISTER_SPACING)))
-#define A_SCD_TRACE_SEQUENCE(n) (((n) & 4) ? \
-   (A_SCD_TRACE_SEQUENCE_4 + (((n) & 3) * TRACE_REGISTER_SPACING)) : \
-   (A_SCD_TRACE_SEQUENCE_0 + ((n) * TRACE_REGISTER_SPACING)))
-
-/*  *********************************************************************
-    * System Generic DMA Registers
-    ********************************************************************* */
-
-#define A_DM_0                      0x0010020B00
-#define A_DM_1                      0x0010020B20
-#define A_DM_2                      0x0010020B40
-#define A_DM_3                      0x0010020B60
-#define DM_REGISTER_SPACING         0x20
-#define DM_NUM_CHANNELS             4
-#define A_DM_BASE(idx) (A_DM_0 + ((idx) * DM_REGISTER_SPACING))
-#define A_DM_REGISTER(idx, reg) (A_DM_BASE(idx) + (reg))
-
-#define R_DM_DSCR_BASE              0x0000000000
-#define R_DM_DSCR_COUNT             0x0000000008
-#define R_DM_CUR_DSCR_ADDR          0x0000000010
-#define R_DM_DSCR_BASE_DEBUG        0x0000000018
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_DM_PARTIAL_0              0x0010020ba0
-#define A_DM_PARTIAL_1              0x0010020ba8
-#define A_DM_PARTIAL_2              0x0010020bb0
-#define A_DM_PARTIAL_3              0x0010020bb8
-#define DM_PARTIAL_REGISTER_SPACING 0x8
-#define A_DM_PARTIAL(idx)           (A_DM_PARTIAL_0 + ((idx) * DM_PARTIAL_REGISTER_SPACING))
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define A_DM_CRC_0                  0x0010020b80
-#define A_DM_CRC_1                  0x0010020b90
-#define DM_CRC_REGISTER_SPACING     0x10
-#define DM_CRC_NUM_CHANNELS         2
-#define A_DM_CRC_BASE(idx)          (A_DM_CRC_0 + ((idx) * DM_CRC_REGISTER_SPACING))
-#define A_DM_CRC_REGISTER(idx, reg)  (A_DM_CRC_BASE(idx) + (reg))
-
-#define R_CRC_DEF_0                 0x00
-#define R_CTCP_DEF_0                0x08
-#endif /* 1250 PASS3 || 112x PASS1 */
-
-/*  *********************************************************************
-    *  Physical Address Map
-    ********************************************************************* */
-
-#if SIBYTE_HDR_FEATURE_1250_112x
-#define A_PHYS_MEMORY_0                 _SB_MAKE64(0x0000000000)
-#define A_PHYS_MEMORY_SIZE              _SB_MAKE64((256*1024*1024))
-#define A_PHYS_SYSTEM_CTL               _SB_MAKE64(0x0010000000)
-#define A_PHYS_IO_SYSTEM                _SB_MAKE64(0x0010060000)
-#define A_PHYS_GENBUS                   _SB_MAKE64(0x0010090000)
-#define A_PHYS_GENBUS_END               _SB_MAKE64(0x0040000000)
-#define A_PHYS_LDTPCI_IO_MATCH_BYTES_32 _SB_MAKE64(0x0040000000)
-#define A_PHYS_LDTPCI_IO_MATCH_BITS_32  _SB_MAKE64(0x0060000000)
-#define A_PHYS_MEMORY_1                 _SB_MAKE64(0x0080000000)
-#define A_PHYS_MEMORY_2                 _SB_MAKE64(0x0090000000)
-#define A_PHYS_MEMORY_3                 _SB_MAKE64(0x00C0000000)
-#define A_PHYS_L2_CACHE_TEST            _SB_MAKE64(0x00D0000000)
-#define A_PHYS_LDT_SPECIAL_MATCH_BYTES  _SB_MAKE64(0x00D8000000)
-#define A_PHYS_LDTPCI_IO_MATCH_BYTES    _SB_MAKE64(0x00DC000000)
-#define A_PHYS_LDTPCI_CFG_MATCH_BYTES   _SB_MAKE64(0x00DE000000)
-#define A_PHYS_LDT_SPECIAL_MATCH_BITS   _SB_MAKE64(0x00F8000000)
-#define A_PHYS_LDTPCI_IO_MATCH_BITS     _SB_MAKE64(0x00FC000000)
-#define A_PHYS_LDTPCI_CFG_MATCH_BITS    _SB_MAKE64(0x00FE000000)
-#define A_PHYS_MEMORY_EXP               _SB_MAKE64(0x0100000000)
-#define A_PHYS_MEMORY_EXP_SIZE          _SB_MAKE64((508*1024*1024*1024))
-#define A_PHYS_LDT_EXP                  _SB_MAKE64(0x8000000000)
-#define A_PHYS_PCI_FULLACCESS_BYTES     _SB_MAKE64(0xF000000000)
-#define A_PHYS_PCI_FULLACCESS_BITS      _SB_MAKE64(0xF100000000)
-#define A_PHYS_RESERVED                 _SB_MAKE64(0xF200000000)
-#define A_PHYS_RESERVED_SPECIAL_LDT     _SB_MAKE64(0xFD00000000)
-
-#define A_PHYS_L2CACHE_WAY_SIZE         _SB_MAKE64(0x0000020000)
-#define PHYS_L2CACHE_NUM_WAYS           4
-#define A_PHYS_L2CACHE_TOTAL_SIZE       _SB_MAKE64(0x0000080000)
-#define A_PHYS_L2CACHE_WAY0             _SB_MAKE64(0x00D0180000)
-#define A_PHYS_L2CACHE_WAY1             _SB_MAKE64(0x00D01A0000)
-#define A_PHYS_L2CACHE_WAY2             _SB_MAKE64(0x00D01C0000)
-#define A_PHYS_L2CACHE_WAY3             _SB_MAKE64(0x00D01E0000)
-#endif
-
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_scd.h b/include/asm-mips/sibyte/sb1250_scd.h
deleted file mode 100644
index e49c3e89b5ee..000000000000
--- a/include/asm-mips/sibyte/sb1250_scd.h
+++ /dev/null
@@ -1,654 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  SCD Constants and Macros                 File: sb1250_scd.h
-    *
-    *  This module contains constants and macros useful for
-    *  manipulating the System Control and Debug module on the 1250.
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003,2004,2005
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-#ifndef _SB1250_SCD_H
-#define _SB1250_SCD_H
-
-#include "sb1250_defs.h"
-
-/*  *********************************************************************
-    *  System control/debug registers
-    ********************************************************************* */
-
-/*
- * System Revision Register (Table 4-1)
- */
-
-#define M_SYS_RESERVED              _SB_MAKEMASK(8, 0)
-
-#define S_SYS_REVISION              _SB_MAKE64(8)
-#define M_SYS_REVISION              _SB_MAKEMASK(8, S_SYS_REVISION)
-#define V_SYS_REVISION(x)           _SB_MAKEVALUE(x, S_SYS_REVISION)
-#define G_SYS_REVISION(x)           _SB_GETVALUE(x, S_SYS_REVISION, M_SYS_REVISION)
-
-#define K_SYS_REVISION_BCM1250_PASS1    0x01
-
-#define K_SYS_REVISION_BCM1250_PASS2    0x03
-#define K_SYS_REVISION_BCM1250_A1       0x03    /* Pass 2.0 WB */
-#define K_SYS_REVISION_BCM1250_A2       0x04    /* Pass 2.0 FC */
-#define K_SYS_REVISION_BCM1250_A3       0x05    /* Pass 2.1 FC */
-#define K_SYS_REVISION_BCM1250_A4       0x06    /* Pass 2.1 WB */
-#define K_SYS_REVISION_BCM1250_A6       0x07    /* OR 0x04 (A2) w/WID != 0 */
-#define K_SYS_REVISION_BCM1250_A8       0x0b    /* A8/A10 */
-#define K_SYS_REVISION_BCM1250_A9       0x08
-#define K_SYS_REVISION_BCM1250_A10      K_SYS_REVISION_BCM1250_A8
-
-#define K_SYS_REVISION_BCM1250_PASS2_2  0x10
-#define K_SYS_REVISION_BCM1250_B0       K_SYS_REVISION_BCM1250_B1
-#define K_SYS_REVISION_BCM1250_B1       0x10
-#define K_SYS_REVISION_BCM1250_B2       0x11
-
-#define K_SYS_REVISION_BCM1250_C0       0x20
-#define K_SYS_REVISION_BCM1250_C1       0x21
-#define K_SYS_REVISION_BCM1250_C2       0x22
-#define K_SYS_REVISION_BCM1250_C3       0x23
-
-#if SIBYTE_HDR_FEATURE_CHIP(1250)
-/* XXX: discourage people from using these constants.  */
-#define K_SYS_REVISION_PASS1        K_SYS_REVISION_BCM1250_PASS1
-#define K_SYS_REVISION_PASS2        K_SYS_REVISION_BCM1250_PASS2
-#define K_SYS_REVISION_PASS2_2      K_SYS_REVISION_BCM1250_PASS2_2
-#define K_SYS_REVISION_PASS3        K_SYS_REVISION_BCM1250_PASS3
-#define K_SYS_REVISION_BCM1250_PASS3    K_SYS_REVISION_BCM1250_C0
-#endif /* 1250 */
-
-#define K_SYS_REVISION_BCM112x_A1       0x20
-#define K_SYS_REVISION_BCM112x_A2       0x21
-#define K_SYS_REVISION_BCM112x_A3       0x22
-#define K_SYS_REVISION_BCM112x_A4       0x23
-#define K_SYS_REVISION_BCM112x_B0       0x30
-
-#define K_SYS_REVISION_BCM1480_S0       0x01
-#define K_SYS_REVISION_BCM1480_A1       0x02
-#define K_SYS_REVISION_BCM1480_A2       0x03
-#define K_SYS_REVISION_BCM1480_A3       0x04
-#define K_SYS_REVISION_BCM1480_B0       0x11
-
-/*Cache size - 23:20  of revision register*/
-#define S_SYS_L2C_SIZE            _SB_MAKE64(20)
-#define M_SYS_L2C_SIZE            _SB_MAKEMASK(4, S_SYS_L2C_SIZE)
-#define V_SYS_L2C_SIZE(x)         _SB_MAKEVALUE(x, S_SYS_L2C_SIZE)
-#define G_SYS_L2C_SIZE(x)         _SB_GETVALUE(x, S_SYS_L2C_SIZE, M_SYS_L2C_SIZE)
-
-#define K_SYS_L2C_SIZE_1MB      0
-#define K_SYS_L2C_SIZE_512KB    5
-#define K_SYS_L2C_SIZE_256KB    2
-#define K_SYS_L2C_SIZE_128KB    1
-
-#define K_SYS_L2C_SIZE_BCM1250  K_SYS_L2C_SIZE_512KB
-#define K_SYS_L2C_SIZE_BCM1125  K_SYS_L2C_SIZE_256KB
-#define K_SYS_L2C_SIZE_BCM1122  K_SYS_L2C_SIZE_128KB
-
-
-/* Number of CPU cores, bits 27:24  of revision register*/
-#define S_SYS_NUM_CPUS            _SB_MAKE64(24)
-#define M_SYS_NUM_CPUS            _SB_MAKEMASK(4, S_SYS_NUM_CPUS)
-#define V_SYS_NUM_CPUS(x)         _SB_MAKEVALUE(x, S_SYS_NUM_CPUS)
-#define G_SYS_NUM_CPUS(x)         _SB_GETVALUE(x, S_SYS_NUM_CPUS, M_SYS_NUM_CPUS)
-
-
-/* XXX: discourage people from using these constants.  */
-#define S_SYS_PART                  _SB_MAKE64(16)
-#define M_SYS_PART                  _SB_MAKEMASK(16, S_SYS_PART)
-#define V_SYS_PART(x)               _SB_MAKEVALUE(x, S_SYS_PART)
-#define G_SYS_PART(x)               _SB_GETVALUE(x, S_SYS_PART, M_SYS_PART)
-
-/* XXX: discourage people from using these constants.  */
-#define K_SYS_PART_SB1250           0x1250
-#define K_SYS_PART_BCM1120          0x1121
-#define K_SYS_PART_BCM1125          0x1123
-#define K_SYS_PART_BCM1125H         0x1124
-#define K_SYS_PART_BCM1122          0x1113
-
-
-/* The "peripheral set" (SOC type) is the low 4 bits of the "part" field.  */
-#define S_SYS_SOC_TYPE              _SB_MAKE64(16)
-#define M_SYS_SOC_TYPE              _SB_MAKEMASK(4, S_SYS_SOC_TYPE)
-#define V_SYS_SOC_TYPE(x)           _SB_MAKEVALUE(x, S_SYS_SOC_TYPE)
-#define G_SYS_SOC_TYPE(x)           _SB_GETVALUE(x, S_SYS_SOC_TYPE, M_SYS_SOC_TYPE)
-
-#define K_SYS_SOC_TYPE_BCM1250      0x0
-#define K_SYS_SOC_TYPE_BCM1120      0x1
-#define K_SYS_SOC_TYPE_BCM1250_ALT  0x2         /* 1250pass2 w/ 1/4 L2.  */
-#define K_SYS_SOC_TYPE_BCM1125      0x3
-#define K_SYS_SOC_TYPE_BCM1125H     0x4
-#define K_SYS_SOC_TYPE_BCM1250_ALT2 0x5         /* 1250pass2 w/ 1/2 L2.  */
-#define K_SYS_SOC_TYPE_BCM1x80      0x6
-#define K_SYS_SOC_TYPE_BCM1x55      0x7
-
-/*
- * Calculate correct SOC type given a copy of system revision register.
- *
- * (For the assembler version, sysrev and dest may be the same register.
- * Also, it clobbers AT.)
- */
-#ifdef __ASSEMBLER__
-#define SYS_SOC_TYPE(dest, sysrev)                                      \
-        .set push ;                                                     \
-        .set reorder ;                                                  \
-        dsrl    dest, sysrev, S_SYS_SOC_TYPE ;                          \
-        andi    dest, dest, (M_SYS_SOC_TYPE >> S_SYS_SOC_TYPE);         \
-        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT, 991f ;                \
-        beq     dest, K_SYS_SOC_TYPE_BCM1250_ALT2, 991f  ;              \
-        b       992f ;                                                  \
-991:    li      dest, K_SYS_SOC_TYPE_BCM1250 ;                          \
-992:                                                                    \
-        .set pop
-#else
-#define SYS_SOC_TYPE(sysrev)                                            \
-        ((G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT          \
-          || G_SYS_SOC_TYPE(sysrev) == K_SYS_SOC_TYPE_BCM1250_ALT2)     \
-         ? K_SYS_SOC_TYPE_BCM1250 : G_SYS_SOC_TYPE(sysrev))
-#endif
-
-#define S_SYS_WID                   _SB_MAKE64(32)
-#define M_SYS_WID                   _SB_MAKEMASK(32, S_SYS_WID)
-#define V_SYS_WID(x)                _SB_MAKEVALUE(x, S_SYS_WID)
-#define G_SYS_WID(x)                _SB_GETVALUE(x, S_SYS_WID, M_SYS_WID)
-
-/*
- * System Manufacturing Register
- * Register: SCD_SYSTEM_MANUF
- */
-
-#if SIBYTE_HDR_FEATURE_1250_112x
-/* Wafer ID: bits 31:0 */
-#define S_SYS_WAFERID1_200        _SB_MAKE64(0)
-#define M_SYS_WAFERID1_200        _SB_MAKEMASK(32, S_SYS_WAFERID1_200)
-#define V_SYS_WAFERID1_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID1_200)
-#define G_SYS_WAFERID1_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID1_200, M_SYS_WAFERID1_200)
-
-#define S_SYS_BIN                 _SB_MAKE64(32)
-#define M_SYS_BIN                 _SB_MAKEMASK(4, S_SYS_BIN)
-#define V_SYS_BIN(x)              _SB_MAKEVALUE(x, S_SYS_BIN)
-#define G_SYS_BIN(x)              _SB_GETVALUE(x, S_SYS_BIN, M_SYS_BIN)
-
-/* Wafer ID: bits 39:36 */
-#define S_SYS_WAFERID2_200        _SB_MAKE64(36)
-#define M_SYS_WAFERID2_200        _SB_MAKEMASK(4, S_SYS_WAFERID2_200)
-#define V_SYS_WAFERID2_200(x)     _SB_MAKEVALUE(x, S_SYS_WAFERID2_200)
-#define G_SYS_WAFERID2_200(x)     _SB_GETVALUE(x, S_SYS_WAFERID2_200, M_SYS_WAFERID2_200)
-
-/* Wafer ID: bits 39:0 */
-#define S_SYS_WAFERID_300         _SB_MAKE64(0)
-#define M_SYS_WAFERID_300         _SB_MAKEMASK(40, S_SYS_WAFERID_300)
-#define V_SYS_WAFERID_300(x)      _SB_MAKEVALUE(x, S_SYS_WAFERID_300)
-#define G_SYS_WAFERID_300(x)      _SB_GETVALUE(x, S_SYS_WAFERID_300, M_SYS_WAFERID_300)
-
-#define S_SYS_XPOS                _SB_MAKE64(40)
-#define M_SYS_XPOS                _SB_MAKEMASK(6, S_SYS_XPOS)
-#define V_SYS_XPOS(x)             _SB_MAKEVALUE(x, S_SYS_XPOS)
-#define G_SYS_XPOS(x)             _SB_GETVALUE(x, S_SYS_XPOS, M_SYS_XPOS)
-
-#define S_SYS_YPOS                _SB_MAKE64(46)
-#define M_SYS_YPOS                _SB_MAKEMASK(6, S_SYS_YPOS)
-#define V_SYS_YPOS(x)             _SB_MAKEVALUE(x, S_SYS_YPOS)
-#define G_SYS_YPOS(x)             _SB_GETVALUE(x, S_SYS_YPOS, M_SYS_YPOS)
-#endif
-
-
-/*
- * System Config Register (Table 4-2)
- * Register: SCD_SYSTEM_CFG
- */
-
-#if SIBYTE_HDR_FEATURE_1250_112x
-#define M_SYS_LDT_PLL_BYP           _SB_MAKEMASK1(3)
-#define M_SYS_PCI_SYNC_TEST_MODE    _SB_MAKEMASK1(4)
-#define M_SYS_IOB0_DIV              _SB_MAKEMASK1(5)
-#define M_SYS_IOB1_DIV              _SB_MAKEMASK1(6)
-
-#define S_SYS_PLL_DIV               _SB_MAKE64(7)
-#define M_SYS_PLL_DIV               _SB_MAKEMASK(5, S_SYS_PLL_DIV)
-#define V_SYS_PLL_DIV(x)            _SB_MAKEVALUE(x, S_SYS_PLL_DIV)
-#define G_SYS_PLL_DIV(x)            _SB_GETVALUE(x, S_SYS_PLL_DIV, M_SYS_PLL_DIV)
-
-#define M_SYS_SER0_ENABLE           _SB_MAKEMASK1(12)
-#define M_SYS_SER0_RSTB_EN          _SB_MAKEMASK1(13)
-#define M_SYS_SER1_ENABLE           _SB_MAKEMASK1(14)
-#define M_SYS_SER1_RSTB_EN          _SB_MAKEMASK1(15)
-#define M_SYS_PCMCIA_ENABLE         _SB_MAKEMASK1(16)
-
-#define S_SYS_BOOT_MODE             _SB_MAKE64(17)
-#define M_SYS_BOOT_MODE             _SB_MAKEMASK(2, S_SYS_BOOT_MODE)
-#define V_SYS_BOOT_MODE(x)          _SB_MAKEVALUE(x, S_SYS_BOOT_MODE)
-#define G_SYS_BOOT_MODE(x)          _SB_GETVALUE(x, S_SYS_BOOT_MODE, M_SYS_BOOT_MODE)
-#define K_SYS_BOOT_MODE_ROM32       0
-#define K_SYS_BOOT_MODE_ROM8        1
-#define K_SYS_BOOT_MODE_SMBUS_SMALL 2
-#define K_SYS_BOOT_MODE_SMBUS_BIG   3
-
-#define M_SYS_PCI_HOST              _SB_MAKEMASK1(19)
-#define M_SYS_PCI_ARBITER           _SB_MAKEMASK1(20)
-#define M_SYS_SOUTH_ON_LDT          _SB_MAKEMASK1(21)
-#define M_SYS_BIG_ENDIAN            _SB_MAKEMASK1(22)
-#define M_SYS_GENCLK_EN             _SB_MAKEMASK1(23)
-#define M_SYS_LDT_TEST_EN           _SB_MAKEMASK1(24)
-#define M_SYS_GEN_PARITY_EN         _SB_MAKEMASK1(25)
-
-#define S_SYS_CONFIG                26
-#define M_SYS_CONFIG                _SB_MAKEMASK(6, S_SYS_CONFIG)
-#define V_SYS_CONFIG(x)             _SB_MAKEVALUE(x, S_SYS_CONFIG)
-#define G_SYS_CONFIG(x)             _SB_GETVALUE(x, S_SYS_CONFIG, M_SYS_CONFIG)
-
-/* The following bits are writeable by JTAG only. */
-
-#define M_SYS_CLKSTOP               _SB_MAKEMASK1(32)
-#define M_SYS_CLKSTEP               _SB_MAKEMASK1(33)
-
-#define S_SYS_CLKCOUNT              34
-#define M_SYS_CLKCOUNT              _SB_MAKEMASK(8, S_SYS_CLKCOUNT)
-#define V_SYS_CLKCOUNT(x)           _SB_MAKEVALUE(x, S_SYS_CLKCOUNT)
-#define G_SYS_CLKCOUNT(x)           _SB_GETVALUE(x, S_SYS_CLKCOUNT, M_SYS_CLKCOUNT)
-
-#define M_SYS_PLL_BYPASS            _SB_MAKEMASK1(42)
-
-#define S_SYS_PLL_IREF              43
-#define M_SYS_PLL_IREF              _SB_MAKEMASK(2, S_SYS_PLL_IREF)
-
-#define S_SYS_PLL_VCO               45
-#define M_SYS_PLL_VCO               _SB_MAKEMASK(2, S_SYS_PLL_VCO)
-
-#define S_SYS_PLL_VREG              47
-#define M_SYS_PLL_VREG              _SB_MAKEMASK(2, S_SYS_PLL_VREG)
-
-#define M_SYS_MEM_RESET             _SB_MAKEMASK1(49)
-#define M_SYS_L2C_RESET             _SB_MAKEMASK1(50)
-#define M_SYS_IO_RESET_0            _SB_MAKEMASK1(51)
-#define M_SYS_IO_RESET_1            _SB_MAKEMASK1(52)
-#define M_SYS_SCD_RESET             _SB_MAKEMASK1(53)
-
-/* End of bits writable by JTAG only. */
-
-#define M_SYS_CPU_RESET_0           _SB_MAKEMASK1(54)
-#define M_SYS_CPU_RESET_1           _SB_MAKEMASK1(55)
-
-#define M_SYS_UNICPU0               _SB_MAKEMASK1(56)
-#define M_SYS_UNICPU1               _SB_MAKEMASK1(57)
-
-#define M_SYS_SB_SOFTRES            _SB_MAKEMASK1(58)
-#define M_SYS_EXT_RESET             _SB_MAKEMASK1(59)
-#define M_SYS_SYSTEM_RESET          _SB_MAKEMASK1(60)
-
-#define M_SYS_MISR_MODE             _SB_MAKEMASK1(61)
-#define M_SYS_MISR_RESET            _SB_MAKEMASK1(62)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1)
-#define M_SYS_SW_FLAG               _SB_MAKEMASK1(63)
-#endif /* 1250 PASS2 || 112x PASS1 */
-
-#endif
-
-
-/*
- * Mailbox Registers (Table 4-3)
- * Registers: SCD_MBOX_CPU_x
- */
-
-#define S_MBOX_INT_3                0
-#define M_MBOX_INT_3                _SB_MAKEMASK(16, S_MBOX_INT_3)
-#define S_MBOX_INT_2                16
-#define M_MBOX_INT_2                _SB_MAKEMASK(16, S_MBOX_INT_2)
-#define S_MBOX_INT_1                32
-#define M_MBOX_INT_1                _SB_MAKEMASK(16, S_MBOX_INT_1)
-#define S_MBOX_INT_0                48
-#define M_MBOX_INT_0                _SB_MAKEMASK(16, S_MBOX_INT_0)
-
-/*
- * Watchdog Registers (Table 4-8) (Table 4-9) (Table 4-10)
- * Registers: SCD_WDOG_INIT_CNT_x
- */
-
-#define V_SCD_WDOG_FREQ             1000000
-
-#define S_SCD_WDOG_INIT             0
-#define M_SCD_WDOG_INIT             _SB_MAKEMASK(23, S_SCD_WDOG_INIT)
-
-#define S_SCD_WDOG_CNT              0
-#define M_SCD_WDOG_CNT              _SB_MAKEMASK(23, S_SCD_WDOG_CNT)
-
-#define S_SCD_WDOG_ENABLE           0
-#define M_SCD_WDOG_ENABLE           _SB_MAKEMASK1(S_SCD_WDOG_ENABLE)
-
-#define S_SCD_WDOG_RESET_TYPE       2
-#define M_SCD_WDOG_RESET_TYPE       _SB_MAKEMASK(3, S_SCD_WDOG_RESET_TYPE)
-#define V_SCD_WDOG_RESET_TYPE(x)    _SB_MAKEVALUE(x, S_SCD_WDOG_RESET_TYPE)
-#define G_SCD_WDOG_RESET_TYPE(x)    _SB_GETVALUE(x, S_SCD_WDOG_RESET_TYPE, M_SCD_WDOG_RESET_TYPE)
-
-#define K_SCD_WDOG_RESET_FULL       0   /* actually, (x & 1) == 0  */
-#define K_SCD_WDOG_RESET_SOFT       1
-#define K_SCD_WDOG_RESET_CPU0       3
-#define K_SCD_WDOG_RESET_CPU1       5
-#define K_SCD_WDOG_RESET_BOTH_CPUS  7
-
-/* This feature is present in 1250 C0 and later, but *not* in 112x A revs.  */
-#if SIBYTE_HDR_FEATURE(1250, PASS3)
-#define S_SCD_WDOG_HAS_RESET        8
-#define M_SCD_WDOG_HAS_RESET        _SB_MAKEMASK1(S_SCD_WDOG_HAS_RESET)
-#endif
-
-
-/*
- * Timer Registers (Table 4-11) (Table 4-12) (Table 4-13)
- */
-
-#define V_SCD_TIMER_FREQ            1000000
-
-#define S_SCD_TIMER_INIT            0
-#define M_SCD_TIMER_INIT            _SB_MAKEMASK(23, S_SCD_TIMER_INIT)
-#define V_SCD_TIMER_INIT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_INIT)
-#define G_SCD_TIMER_INIT(x)         _SB_GETVALUE(x, S_SCD_TIMER_INIT, M_SCD_TIMER_INIT)
-
-#define V_SCD_TIMER_WIDTH           23
-#define S_SCD_TIMER_CNT             0
-#define M_SCD_TIMER_CNT             _SB_MAKEMASK(V_SCD_TIMER_WIDTH, S_SCD_TIMER_CNT)
-#define V_SCD_TIMER_CNT(x)         _SB_MAKEVALUE(x, S_SCD_TIMER_CNT)
-#define G_SCD_TIMER_CNT(x)         _SB_GETVALUE(x, S_SCD_TIMER_CNT, M_SCD_TIMER_CNT)
-
-#define M_SCD_TIMER_ENABLE          _SB_MAKEMASK1(0)
-#define M_SCD_TIMER_MODE            _SB_MAKEMASK1(1)
-#define M_SCD_TIMER_MODE_CONTINUOUS M_SCD_TIMER_MODE
-
-/*
- * System Performance Counters
- */
-
-#define S_SPC_CFG_SRC0            0
-#define M_SPC_CFG_SRC0            _SB_MAKEMASK(8, S_SPC_CFG_SRC0)
-#define V_SPC_CFG_SRC0(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC0)
-#define G_SPC_CFG_SRC0(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC0, M_SPC_CFG_SRC0)
-
-#define S_SPC_CFG_SRC1            8
-#define M_SPC_CFG_SRC1            _SB_MAKEMASK(8, S_SPC_CFG_SRC1)
-#define V_SPC_CFG_SRC1(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC1)
-#define G_SPC_CFG_SRC1(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC1, M_SPC_CFG_SRC1)
-
-#define S_SPC_CFG_SRC2            16
-#define M_SPC_CFG_SRC2            _SB_MAKEMASK(8, S_SPC_CFG_SRC2)
-#define V_SPC_CFG_SRC2(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC2)
-#define G_SPC_CFG_SRC2(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC2, M_SPC_CFG_SRC2)
-
-#define S_SPC_CFG_SRC3            24
-#define M_SPC_CFG_SRC3            _SB_MAKEMASK(8, S_SPC_CFG_SRC3)
-#define V_SPC_CFG_SRC3(x)         _SB_MAKEVALUE(x, S_SPC_CFG_SRC3)
-#define G_SPC_CFG_SRC3(x)         _SB_GETVALUE(x, S_SPC_CFG_SRC3, M_SPC_CFG_SRC3)
-
-#if SIBYTE_HDR_FEATURE_1250_112x
-#define M_SPC_CFG_CLEAR         _SB_MAKEMASK1(32)
-#define M_SPC_CFG_ENABLE        _SB_MAKEMASK1(33)
-#endif
-
-
-/*
- * Bus Watcher
- */
-
-#define S_SCD_BERR_TID            8
-#define M_SCD_BERR_TID            _SB_MAKEMASK(10, S_SCD_BERR_TID)
-#define V_SCD_BERR_TID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_TID)
-#define G_SCD_BERR_TID(x)         _SB_GETVALUE(x, S_SCD_BERR_TID, M_SCD_BERR_TID)
-
-#define S_SCD_BERR_RID            18
-#define M_SCD_BERR_RID            _SB_MAKEMASK(4, S_SCD_BERR_RID)
-#define V_SCD_BERR_RID(x)         _SB_MAKEVALUE(x, S_SCD_BERR_RID)
-#define G_SCD_BERR_RID(x)         _SB_GETVALUE(x, S_SCD_BERR_RID, M_SCD_BERR_RID)
-
-#define S_SCD_BERR_DCODE          22
-#define M_SCD_BERR_DCODE          _SB_MAKEMASK(3, S_SCD_BERR_DCODE)
-#define V_SCD_BERR_DCODE(x)       _SB_MAKEVALUE(x, S_SCD_BERR_DCODE)
-#define G_SCD_BERR_DCODE(x)       _SB_GETVALUE(x, S_SCD_BERR_DCODE, M_SCD_BERR_DCODE)
-
-#define M_SCD_BERR_MULTERRS       _SB_MAKEMASK1(30)
-
-
-#define S_SCD_L2ECC_CORR_D        0
-#define M_SCD_L2ECC_CORR_D        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_D)
-#define V_SCD_L2ECC_CORR_D(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_D)
-#define G_SCD_L2ECC_CORR_D(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_D, M_SCD_L2ECC_CORR_D)
-
-#define S_SCD_L2ECC_BAD_D         8
-#define M_SCD_L2ECC_BAD_D         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_D)
-#define V_SCD_L2ECC_BAD_D(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_D)
-#define G_SCD_L2ECC_BAD_D(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_D, M_SCD_L2ECC_BAD_D)
-
-#define S_SCD_L2ECC_CORR_T        16
-#define M_SCD_L2ECC_CORR_T        _SB_MAKEMASK(8, S_SCD_L2ECC_CORR_T)
-#define V_SCD_L2ECC_CORR_T(x)     _SB_MAKEVALUE(x, S_SCD_L2ECC_CORR_T)
-#define G_SCD_L2ECC_CORR_T(x)     _SB_GETVALUE(x, S_SCD_L2ECC_CORR_T, M_SCD_L2ECC_CORR_T)
-
-#define S_SCD_L2ECC_BAD_T         24
-#define M_SCD_L2ECC_BAD_T         _SB_MAKEMASK(8, S_SCD_L2ECC_BAD_T)
-#define V_SCD_L2ECC_BAD_T(x)      _SB_MAKEVALUE(x, S_SCD_L2ECC_BAD_T)
-#define G_SCD_L2ECC_BAD_T(x)      _SB_GETVALUE(x, S_SCD_L2ECC_BAD_T, M_SCD_L2ECC_BAD_T)
-
-#define S_SCD_MEM_ECC_CORR        0
-#define M_SCD_MEM_ECC_CORR        _SB_MAKEMASK(8, S_SCD_MEM_ECC_CORR)
-#define V_SCD_MEM_ECC_CORR(x)     _SB_MAKEVALUE(x, S_SCD_MEM_ECC_CORR)
-#define G_SCD_MEM_ECC_CORR(x)     _SB_GETVALUE(x, S_SCD_MEM_ECC_CORR, M_SCD_MEM_ECC_CORR)
-
-#define S_SCD_MEM_ECC_BAD         8
-#define M_SCD_MEM_ECC_BAD         _SB_MAKEMASK(8, S_SCD_MEM_ECC_BAD)
-#define V_SCD_MEM_ECC_BAD(x)      _SB_MAKEVALUE(x, S_SCD_MEM_ECC_BAD)
-#define G_SCD_MEM_ECC_BAD(x)      _SB_GETVALUE(x, S_SCD_MEM_ECC_BAD, M_SCD_MEM_ECC_BAD)
-
-#define S_SCD_MEM_BUSERR          16
-#define M_SCD_MEM_BUSERR          _SB_MAKEMASK(8, S_SCD_MEM_BUSERR)
-#define V_SCD_MEM_BUSERR(x)       _SB_MAKEVALUE(x, S_SCD_MEM_BUSERR)
-#define G_SCD_MEM_BUSERR(x)       _SB_GETVALUE(x, S_SCD_MEM_BUSERR, M_SCD_MEM_BUSERR)
-
-
-/*
- * Address Trap Registers
- */
-
-#if SIBYTE_HDR_FEATURE_1250_112x
-#define M_ATRAP_INDEX             _SB_MAKEMASK(4, 0)
-#define M_ATRAP_ADDRESS           _SB_MAKEMASK(40, 0)
-
-#define S_ATRAP_CFG_CNT            0
-#define M_ATRAP_CFG_CNT            _SB_MAKEMASK(3, S_ATRAP_CFG_CNT)
-#define V_ATRAP_CFG_CNT(x)         _SB_MAKEVALUE(x, S_ATRAP_CFG_CNT)
-#define G_ATRAP_CFG_CNT(x)         _SB_GETVALUE(x, S_ATRAP_CFG_CNT, M_ATRAP_CFG_CNT)
-
-#define M_ATRAP_CFG_WRITE          _SB_MAKEMASK1(3)
-#define M_ATRAP_CFG_ALL            _SB_MAKEMASK1(4)
-#define M_ATRAP_CFG_INV            _SB_MAKEMASK1(5)
-#define M_ATRAP_CFG_USESRC         _SB_MAKEMASK1(6)
-#define M_ATRAP_CFG_SRCINV         _SB_MAKEMASK1(7)
-
-#define S_ATRAP_CFG_AGENTID     8
-#define M_ATRAP_CFG_AGENTID     _SB_MAKEMASK(4, S_ATRAP_CFG_AGENTID)
-#define V_ATRAP_CFG_AGENTID(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_AGENTID)
-#define G_ATRAP_CFG_AGENTID(x)  _SB_GETVALUE(x, S_ATRAP_CFG_AGENTID, M_ATRAP_CFG_AGENTID)
-
-#define K_BUS_AGENT_CPU0        0
-#define K_BUS_AGENT_CPU1        1
-#define K_BUS_AGENT_IOB0        2
-#define K_BUS_AGENT_IOB1        3
-#define K_BUS_AGENT_SCD 4
-#define K_BUS_AGENT_L2C 6
-#define K_BUS_AGENT_MC  7
-
-#define S_ATRAP_CFG_CATTR     12
-#define M_ATRAP_CFG_CATTR     _SB_MAKEMASK(3, S_ATRAP_CFG_CATTR)
-#define V_ATRAP_CFG_CATTR(x)  _SB_MAKEVALUE(x, S_ATRAP_CFG_CATTR)
-#define G_ATRAP_CFG_CATTR(x)  _SB_GETVALUE(x, S_ATRAP_CFG_CATTR, M_ATRAP_CFG_CATTR)
-
-#define K_ATRAP_CFG_CATTR_IGNORE        0
-#define K_ATRAP_CFG_CATTR_UNC           1
-#define K_ATRAP_CFG_CATTR_CACHEABLE     2
-#define K_ATRAP_CFG_CATTR_NONCOH        3
-#define K_ATRAP_CFG_CATTR_COHERENT      4
-#define K_ATRAP_CFG_CATTR_NOTUNC        5
-#define K_ATRAP_CFG_CATTR_NOTNONCOH     6
-#define K_ATRAP_CFG_CATTR_NOTCOHERENT   7
-
-#endif  /* 1250/112x */
-
-/*
- * Trace Buffer Config register
- */
-
-#define M_SCD_TRACE_CFG_RESET           _SB_MAKEMASK1(0)
-#define M_SCD_TRACE_CFG_START_READ      _SB_MAKEMASK1(1)
-#define M_SCD_TRACE_CFG_START           _SB_MAKEMASK1(2)
-#define M_SCD_TRACE_CFG_STOP            _SB_MAKEMASK1(3)
-#define M_SCD_TRACE_CFG_FREEZE          _SB_MAKEMASK1(4)
-#define M_SCD_TRACE_CFG_FREEZE_FULL     _SB_MAKEMASK1(5)
-#define M_SCD_TRACE_CFG_DEBUG_FULL      _SB_MAKEMASK1(6)
-#define M_SCD_TRACE_CFG_FULL            _SB_MAKEMASK1(7)
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define M_SCD_TRACE_CFG_FORCECNT        _SB_MAKEMASK1(8)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-/*
- * This field is the same on the 1250/112x and 1480, just located in
- * a slightly different place in the register.
- */
-#if SIBYTE_HDR_FEATURE_1250_112x
-#define S_SCD_TRACE_CFG_CUR_ADDR        10
-#else
-#if SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_SCD_TRACE_CFG_CUR_ADDR        24
-#endif  /* 1480 */
-#endif  /* 1250/112x */
-
-#define M_SCD_TRACE_CFG_CUR_ADDR        _SB_MAKEMASK(8, S_SCD_TRACE_CFG_CUR_ADDR)
-#define V_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_MAKEVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR)
-#define G_SCD_TRACE_CFG_CUR_ADDR(x)     _SB_GETVALUE(x, S_SCD_TRACE_CFG_CUR_ADDR, M_SCD_TRACE_CFG_CUR_ADDR)
-
-/*
- * Trace Event registers
- */
-
-#define S_SCD_TREVT_ADDR_MATCH          0
-#define M_SCD_TREVT_ADDR_MATCH          _SB_MAKEMASK(4, S_SCD_TREVT_ADDR_MATCH)
-#define V_SCD_TREVT_ADDR_MATCH(x)       _SB_MAKEVALUE(x, S_SCD_TREVT_ADDR_MATCH)
-#define G_SCD_TREVT_ADDR_MATCH(x)       _SB_GETVALUE(x, S_SCD_TREVT_ADDR_MATCH, M_SCD_TREVT_ADDR_MATCH)
-
-#define M_SCD_TREVT_REQID_MATCH         _SB_MAKEMASK1(4)
-#define M_SCD_TREVT_DATAID_MATCH        _SB_MAKEMASK1(5)
-#define M_SCD_TREVT_RESPID_MATCH        _SB_MAKEMASK1(6)
-#define M_SCD_TREVT_INTERRUPT           _SB_MAKEMASK1(7)
-#define M_SCD_TREVT_DEBUG_PIN           _SB_MAKEMASK1(9)
-#define M_SCD_TREVT_WRITE               _SB_MAKEMASK1(10)
-#define M_SCD_TREVT_READ                _SB_MAKEMASK1(11)
-
-#define S_SCD_TREVT_REQID               12
-#define M_SCD_TREVT_REQID               _SB_MAKEMASK(4, S_SCD_TREVT_REQID)
-#define V_SCD_TREVT_REQID(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_REQID)
-#define G_SCD_TREVT_REQID(x)            _SB_GETVALUE(x, S_SCD_TREVT_REQID, M_SCD_TREVT_REQID)
-
-#define S_SCD_TREVT_RESPID              16
-#define M_SCD_TREVT_RESPID              _SB_MAKEMASK(4, S_SCD_TREVT_RESPID)
-#define V_SCD_TREVT_RESPID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_RESPID)
-#define G_SCD_TREVT_RESPID(x)           _SB_GETVALUE(x, S_SCD_TREVT_RESPID, M_SCD_TREVT_RESPID)
-
-#define S_SCD_TREVT_DATAID              20
-#define M_SCD_TREVT_DATAID              _SB_MAKEMASK(4, S_SCD_TREVT_DATAID)
-#define V_SCD_TREVT_DATAID(x)           _SB_MAKEVALUE(x, S_SCD_TREVT_DATAID)
-#define G_SCD_TREVT_DATAID(x)           _SB_GETVALUE(x, S_SCD_TREVT_DATAID, M_SCD_TREVT_DATID)
-
-#define S_SCD_TREVT_COUNT               24
-#define M_SCD_TREVT_COUNT               _SB_MAKEMASK(8, S_SCD_TREVT_COUNT)
-#define V_SCD_TREVT_COUNT(x)            _SB_MAKEVALUE(x, S_SCD_TREVT_COUNT)
-#define G_SCD_TREVT_COUNT(x)            _SB_GETVALUE(x, S_SCD_TREVT_COUNT, M_SCD_TREVT_COUNT)
-
-/*
- * Trace Sequence registers
- */
-
-#define S_SCD_TRSEQ_EVENT4              0
-#define M_SCD_TRSEQ_EVENT4              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT4)
-#define V_SCD_TRSEQ_EVENT4(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT4)
-#define G_SCD_TRSEQ_EVENT4(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT4, M_SCD_TRSEQ_EVENT4)
-
-#define S_SCD_TRSEQ_EVENT3              4
-#define M_SCD_TRSEQ_EVENT3              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT3)
-#define V_SCD_TRSEQ_EVENT3(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT3)
-#define G_SCD_TRSEQ_EVENT3(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT3, M_SCD_TRSEQ_EVENT3)
-
-#define S_SCD_TRSEQ_EVENT2              8
-#define M_SCD_TRSEQ_EVENT2              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT2)
-#define V_SCD_TRSEQ_EVENT2(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT2)
-#define G_SCD_TRSEQ_EVENT2(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT2, M_SCD_TRSEQ_EVENT2)
-
-#define S_SCD_TRSEQ_EVENT1              12
-#define M_SCD_TRSEQ_EVENT1              _SB_MAKEMASK(4, S_SCD_TRSEQ_EVENT1)
-#define V_SCD_TRSEQ_EVENT1(x)           _SB_MAKEVALUE(x, S_SCD_TRSEQ_EVENT1)
-#define G_SCD_TRSEQ_EVENT1(x)           _SB_GETVALUE(x, S_SCD_TRSEQ_EVENT1, M_SCD_TRSEQ_EVENT1)
-
-#define K_SCD_TRSEQ_E0                  0
-#define K_SCD_TRSEQ_E1                  1
-#define K_SCD_TRSEQ_E2                  2
-#define K_SCD_TRSEQ_E3                  3
-#define K_SCD_TRSEQ_E0_E1               4
-#define K_SCD_TRSEQ_E1_E2               5
-#define K_SCD_TRSEQ_E2_E3               6
-#define K_SCD_TRSEQ_E0_E1_E2            7
-#define K_SCD_TRSEQ_E0_E1_E2_E3         8
-#define K_SCD_TRSEQ_E0E1                9
-#define K_SCD_TRSEQ_E0E1E2              10
-#define K_SCD_TRSEQ_E0E1E2E3            11
-#define K_SCD_TRSEQ_E0E1_E2             12
-#define K_SCD_TRSEQ_E0E1_E2E3           13
-#define K_SCD_TRSEQ_E0E1_E2_E3          14
-#define K_SCD_TRSEQ_IGNORED             15
-
-#define K_SCD_TRSEQ_TRIGGER_ALL         (V_SCD_TRSEQ_EVENT1(K_SCD_TRSEQ_IGNORED) | \
-                                         V_SCD_TRSEQ_EVENT2(K_SCD_TRSEQ_IGNORED) | \
-                                         V_SCD_TRSEQ_EVENT3(K_SCD_TRSEQ_IGNORED) | \
-                                         V_SCD_TRSEQ_EVENT4(K_SCD_TRSEQ_IGNORED))
-
-#define S_SCD_TRSEQ_FUNCTION            16
-#define M_SCD_TRSEQ_FUNCTION            _SB_MAKEMASK(4, S_SCD_TRSEQ_FUNCTION)
-#define V_SCD_TRSEQ_FUNCTION(x)         _SB_MAKEVALUE(x, S_SCD_TRSEQ_FUNCTION)
-#define G_SCD_TRSEQ_FUNCTION(x)         _SB_GETVALUE(x, S_SCD_TRSEQ_FUNCTION, M_SCD_TRSEQ_FUNCTION)
-
-#define K_SCD_TRSEQ_FUNC_NOP            0
-#define K_SCD_TRSEQ_FUNC_START          1
-#define K_SCD_TRSEQ_FUNC_STOP           2
-#define K_SCD_TRSEQ_FUNC_FREEZE         3
-
-#define V_SCD_TRSEQ_FUNC_NOP            V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_NOP)
-#define V_SCD_TRSEQ_FUNC_START          V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_START)
-#define V_SCD_TRSEQ_FUNC_STOP           V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_STOP)
-#define V_SCD_TRSEQ_FUNC_FREEZE         V_SCD_TRSEQ_FUNCTION(K_SCD_TRSEQ_FUNC_FREEZE)
-
-#define M_SCD_TRSEQ_ASAMPLE             _SB_MAKEMASK1(18)
-#define M_SCD_TRSEQ_DSAMPLE             _SB_MAKEMASK1(19)
-#define M_SCD_TRSEQ_DEBUGPIN            _SB_MAKEMASK1(20)
-#define M_SCD_TRSEQ_DEBUGCPU            _SB_MAKEMASK1(21)
-#define M_SCD_TRSEQ_CLEARUSE            _SB_MAKEMASK1(22)
-#define M_SCD_TRSEQ_ALLD_A              _SB_MAKEMASK1(23)
-#define M_SCD_TRSEQ_ALL_A               _SB_MAKEMASK1(24)
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_smbus.h b/include/asm-mips/sibyte/sb1250_smbus.h
deleted file mode 100644
index 04769923cf1e..000000000000
--- a/include/asm-mips/sibyte/sb1250_smbus.h
+++ /dev/null
@@ -1,204 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  SMBUS Constants                          File: sb1250_smbus.h
-    *
-    *  This module contains constants and macros useful for
-    *  manipulating the SB1250's SMbus devices.
-    *
-    *  SB1250 specification level:  10/21/02
-    *  BCM1280 specification level:  11/24/03
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_SMBUS_H
-#define _SB1250_SMBUS_H
-
-#include "sb1250_defs.h"
-
-/*
- * SMBus Clock Frequency Register (Table 14-2)
- */
-
-#define S_SMB_FREQ_DIV              0
-#define M_SMB_FREQ_DIV              _SB_MAKEMASK(13, S_SMB_FREQ_DIV)
-#define V_SMB_FREQ_DIV(x)           _SB_MAKEVALUE(x, S_SMB_FREQ_DIV)
-
-#define K_SMB_FREQ_400KHZ           0x1F
-#define K_SMB_FREQ_100KHZ           0x7D
-#define K_SMB_FREQ_10KHZ            1250
-
-#define S_SMB_CMD                   0
-#define M_SMB_CMD                   _SB_MAKEMASK(8, S_SMB_CMD)
-#define V_SMB_CMD(x)                _SB_MAKEVALUE(x, S_SMB_CMD)
-
-/*
- * SMBus control register (Table 14-4)
- */
-
-#define M_SMB_ERR_INTR              _SB_MAKEMASK1(0)
-#define M_SMB_FINISH_INTR           _SB_MAKEMASK1(1)
-
-#define S_SMB_DATA_OUT              4
-#define M_SMB_DATA_OUT              _SB_MAKEMASK1(S_SMB_DATA_OUT)
-#define V_SMB_DATA_OUT(x)           _SB_MAKEVALUE(x, S_SMB_DATA_OUT)
-
-#define M_SMB_DATA_DIR              _SB_MAKEMASK1(5)
-#define M_SMB_DATA_DIR_OUTPUT       M_SMB_DATA_DIR
-#define M_SMB_CLK_OUT               _SB_MAKEMASK1(6)
-#define M_SMB_DIRECT_ENABLE         _SB_MAKEMASK1(7)
-
-/*
- * SMBus status registers (Table 14-5)
- */
-
-#define M_SMB_BUSY                  _SB_MAKEMASK1(0)
-#define M_SMB_ERROR                 _SB_MAKEMASK1(1)
-#define M_SMB_ERROR_TYPE            _SB_MAKEMASK1(2)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS3) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-#define S_SMB_SCL_IN                5
-#define M_SMB_SCL_IN                _SB_MAKEMASK1(S_SMB_SCL_IN)
-#define V_SMB_SCL_IN(x)             _SB_MAKEVALUE(x, S_SMB_SCL_IN)
-#define G_SMB_SCL_IN(x)             _SB_GETVALUE(x, S_SMB_SCL_IN, M_SMB_SCL_IN)
-#endif /* 1250 PASS3 || 112x PASS1 || 1480 */
-
-#define S_SMB_REF                   6
-#define M_SMB_REF                   _SB_MAKEMASK1(S_SMB_REF)
-#define V_SMB_REF(x)                _SB_MAKEVALUE(x, S_SMB_REF)
-#define G_SMB_REF(x)                _SB_GETVALUE(x, S_SMB_REF, M_SMB_REF)
-
-#define S_SMB_DATA_IN               7
-#define M_SMB_DATA_IN               _SB_MAKEMASK1(S_SMB_DATA_IN)
-#define V_SMB_DATA_IN(x)            _SB_MAKEVALUE(x, S_SMB_DATA_IN)
-#define G_SMB_DATA_IN(x)            _SB_GETVALUE(x, S_SMB_DATA_IN, M_SMB_DATA_IN)
-
-/*
- * SMBus Start/Command registers (Table 14-9)
- */
-
-#define S_SMB_ADDR                  0
-#define M_SMB_ADDR                  _SB_MAKEMASK(7, S_SMB_ADDR)
-#define V_SMB_ADDR(x)               _SB_MAKEVALUE(x, S_SMB_ADDR)
-#define G_SMB_ADDR(x)               _SB_GETVALUE(x, S_SMB_ADDR, M_SMB_ADDR)
-
-#define M_SMB_QDATA                 _SB_MAKEMASK1(7)
-
-#define S_SMB_TT                    8
-#define M_SMB_TT                    _SB_MAKEMASK(3, S_SMB_TT)
-#define V_SMB_TT(x)                 _SB_MAKEVALUE(x, S_SMB_TT)
-#define G_SMB_TT(x)                 _SB_GETVALUE(x, S_SMB_TT, M_SMB_TT)
-
-#define K_SMB_TT_WR1BYTE            0
-#define K_SMB_TT_WR2BYTE            1
-#define K_SMB_TT_WR3BYTE            2
-#define K_SMB_TT_CMD_RD1BYTE        3
-#define K_SMB_TT_CMD_RD2BYTE        4
-#define K_SMB_TT_RD1BYTE            5
-#define K_SMB_TT_QUICKCMD           6
-#define K_SMB_TT_EEPROMREAD         7
-
-#define V_SMB_TT_WR1BYTE            V_SMB_TT(K_SMB_TT_WR1BYTE)
-#define V_SMB_TT_WR2BYTE            V_SMB_TT(K_SMB_TT_WR2BYTE)
-#define V_SMB_TT_WR3BYTE            V_SMB_TT(K_SMB_TT_WR3BYTE)
-#define V_SMB_TT_CMD_RD1BYTE        V_SMB_TT(K_SMB_TT_CMD_RD1BYTE)
-#define V_SMB_TT_CMD_RD2BYTE        V_SMB_TT(K_SMB_TT_CMD_RD2BYTE)
-#define V_SMB_TT_RD1BYTE            V_SMB_TT(K_SMB_TT_RD1BYTE)
-#define V_SMB_TT_QUICKCMD           V_SMB_TT(K_SMB_TT_QUICKCMD)
-#define V_SMB_TT_EEPROMREAD         V_SMB_TT(K_SMB_TT_EEPROMREAD)
-
-#define M_SMB_PEC                   _SB_MAKEMASK1(15)
-
-/*
- * SMBus Data Register (Table 14-6) and SMBus Extra Register (Table 14-7)
- */
-
-#define S_SMB_LB                    0
-#define M_SMB_LB                    _SB_MAKEMASK(8, S_SMB_LB)
-#define V_SMB_LB(x)                 _SB_MAKEVALUE(x, S_SMB_LB)
-
-#define S_SMB_MB                    8
-#define M_SMB_MB                    _SB_MAKEMASK(8, S_SMB_MB)
-#define V_SMB_MB(x)                 _SB_MAKEVALUE(x, S_SMB_MB)
-
-
-/*
- * SMBus Packet Error Check register (Table 14-8)
- */
-
-#define S_SPEC_PEC                  0
-#define M_SPEC_PEC                  _SB_MAKEMASK(8, S_SPEC_PEC)
-#define V_SPEC_MB(x)                _SB_MAKEVALUE(x, S_SPEC_PEC)
-
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-
-#define S_SMB_CMDH                  8
-#define M_SMB_CMDH                  _SB_MAKEMASK(8, S_SMB_CMDH)
-#define V_SMB_CMDH(x)               _SB_MAKEVALUE(x, S_SMB_CMDH)
-
-#define M_SMB_EXTEND                _SB_MAKEMASK1(14)
-
-#define S_SMB_DFMT                  8
-#define M_SMB_DFMT                  _SB_MAKEMASK(3, S_SMB_DFMT)
-#define V_SMB_DFMT(x)               _SB_MAKEVALUE(x, S_SMB_DFMT)
-#define G_SMB_DFMT(x)               _SB_GETVALUE(x, S_SMB_DFMT, M_SMB_DFMT)
-
-#define K_SMB_DFMT_1BYTE            0
-#define K_SMB_DFMT_2BYTE            1
-#define K_SMB_DFMT_3BYTE            2
-#define K_SMB_DFMT_4BYTE            3
-#define K_SMB_DFMT_NODATA           4
-#define K_SMB_DFMT_CMD4BYTE         5
-#define K_SMB_DFMT_CMD5BYTE         6
-#define K_SMB_DFMT_RESERVED         7
-
-#define V_SMB_DFMT_1BYTE            V_SMB_DFMT(K_SMB_DFMT_1BYTE)
-#define V_SMB_DFMT_2BYTE            V_SMB_DFMT(K_SMB_DFMT_2BYTE)
-#define V_SMB_DFMT_3BYTE            V_SMB_DFMT(K_SMB_DFMT_3BYTE)
-#define V_SMB_DFMT_4BYTE            V_SMB_DFMT(K_SMB_DFMT_4BYTE)
-#define V_SMB_DFMT_NODATA           V_SMB_DFMT(K_SMB_DFMT_NODATA)
-#define V_SMB_DFMT_CMD4BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD4BYTE)
-#define V_SMB_DFMT_CMD5BYTE         V_SMB_DFMT(K_SMB_DFMT_CMD5BYTE)
-#define V_SMB_DFMT_RESERVED         V_SMB_DFMT(K_SMB_DFMT_RESERVED)
-
-#define S_SMB_AFMT                  11
-#define M_SMB_AFMT                  _SB_MAKEMASK(2, S_SMB_AFMT)
-#define V_SMB_AFMT(x)               _SB_MAKEVALUE(x, S_SMB_AFMT)
-#define G_SMB_AFMT(x)               _SB_GETVALUE(x, S_SMB_AFMT, M_SMB_AFMT)
-
-#define K_SMB_AFMT_NONE             0
-#define K_SMB_AFMT_ADDR             1
-#define K_SMB_AFMT_ADDR_CMD1BYTE    2
-#define K_SMB_AFMT_ADDR_CMD2BYTE    3
-
-#define V_SMB_AFMT_NONE             V_SMB_AFMT(K_SMB_AFMT_NONE)
-#define V_SMB_AFMT_ADDR             V_SMB_AFMT(K_SMB_AFMT_ADDR)
-#define V_SMB_AFMT_ADDR_CMD1BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD1BYTE)
-#define V_SMB_AFMT_ADDR_CMD2BYTE    V_SMB_AFMT(K_SMB_AFMT_ADDR_CMD2BYTE)
-
-#define M_SMB_DIR                   _SB_MAKEMASK1(13)
-
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_syncser.h b/include/asm-mips/sibyte/sb1250_syncser.h
deleted file mode 100644
index d4b8558e0bf1..000000000000
--- a/include/asm-mips/sibyte/sb1250_syncser.h
+++ /dev/null
@@ -1,146 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  Synchronous Serial Constants              File: sb1250_syncser.h
-    *
-    *  This module contains constants and macros useful for
-    *  manipulating the SB1250's Synchronous Serial
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_SYNCSER_H
-#define _SB1250_SYNCSER_H
-
-#include "sb1250_defs.h"
-
-/*
- * Serial Mode Configuration Register
- */
-
-#define M_SYNCSER_CRC_MODE                 _SB_MAKEMASK1(0)
-#define M_SYNCSER_MSB_FIRST                _SB_MAKEMASK1(1)
-
-#define S_SYNCSER_FLAG_NUM                 2
-#define M_SYNCSER_FLAG_NUM                 _SB_MAKEMASK(4, S_SYNCSER_FLAG_NUM)
-#define V_SYNCSER_FLAG_NUM                 _SB_MAKEVALUE(x, S_SYNCSER_FLAG_NUM)
-
-#define M_SYNCSER_FLAG_EN                  _SB_MAKEMASK1(6)
-#define M_SYNCSER_HDLC_EN                  _SB_MAKEMASK1(7)
-#define M_SYNCSER_LOOP_MODE                _SB_MAKEMASK1(8)
-#define M_SYNCSER_LOOPBACK                 _SB_MAKEMASK1(9)
-
-/*
- * Serial Clock Source and Line Interface Mode Register
- */
-
-#define M_SYNCSER_RXCLK_INV                _SB_MAKEMASK1(0)
-#define M_SYNCSER_RXCLK_EXT                _SB_MAKEMASK1(1)
-
-#define S_SYNCSER_RXSYNC_DLY               2
-#define M_SYNCSER_RXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_RXSYNC_DLY)
-#define V_SYNCSER_RXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_RXSYNC_DLY)
-
-#define M_SYNCSER_RXSYNC_LOW               _SB_MAKEMASK1(4)
-#define M_SYNCSER_RXSTRB_LOW               _SB_MAKEMASK1(5)
-
-#define M_SYNCSER_RXSYNC_EDGE              _SB_MAKEMASK1(6)
-#define M_SYNCSER_RXSYNC_INT               _SB_MAKEMASK1(7)
-
-#define M_SYNCSER_TXCLK_INV                _SB_MAKEMASK1(8)
-#define M_SYNCSER_TXCLK_EXT                _SB_MAKEMASK1(9)
-
-#define S_SYNCSER_TXSYNC_DLY               10
-#define M_SYNCSER_TXSYNC_DLY               _SB_MAKEMASK(2, S_SYNCSER_TXSYNC_DLY)
-#define V_SYNCSER_TXSYNC_DLY(x)            _SB_MAKEVALUE(x, S_SYNCSER_TXSYNC_DLY)
-
-#define M_SYNCSER_TXSYNC_LOW               _SB_MAKEMASK1(12)
-#define M_SYNCSER_TXSTRB_LOW               _SB_MAKEMASK1(13)
-
-#define M_SYNCSER_TXSYNC_EDGE              _SB_MAKEMASK1(14)
-#define M_SYNCSER_TXSYNC_INT               _SB_MAKEMASK1(15)
-
-/*
- * Serial Command Register
- */
-
-#define M_SYNCSER_CMD_RX_EN                _SB_MAKEMASK1(0)
-#define M_SYNCSER_CMD_TX_EN                _SB_MAKEMASK1(1)
-#define M_SYNCSER_CMD_RX_RESET             _SB_MAKEMASK1(2)
-#define M_SYNCSER_CMD_TX_RESET             _SB_MAKEMASK1(3)
-#define M_SYNCSER_CMD_TX_PAUSE             _SB_MAKEMASK1(5)
-
-/*
- * Serial DMA Enable Register
- */
-
-#define M_SYNCSER_DMA_RX_EN                _SB_MAKEMASK1(0)
-#define M_SYNCSER_DMA_TX_EN                _SB_MAKEMASK1(4)
-
-/*
- * Serial Status Register
- */
-
-#define M_SYNCSER_RX_CRCERR                _SB_MAKEMASK1(0)
-#define M_SYNCSER_RX_ABORT                 _SB_MAKEMASK1(1)
-#define M_SYNCSER_RX_OCTET                 _SB_MAKEMASK1(2)
-#define M_SYNCSER_RX_LONGFRM               _SB_MAKEMASK1(3)
-#define M_SYNCSER_RX_SHORTFRM              _SB_MAKEMASK1(4)
-#define M_SYNCSER_RX_OVERRUN               _SB_MAKEMASK1(5)
-#define M_SYNCSER_RX_SYNC_ERR              _SB_MAKEMASK1(6)
-#define M_SYNCSER_TX_CRCERR                _SB_MAKEMASK1(8)
-#define M_SYNCSER_TX_UNDERRUN              _SB_MAKEMASK1(9)
-#define M_SYNCSER_TX_SYNC_ERR              _SB_MAKEMASK1(10)
-#define M_SYNCSER_TX_PAUSE_COMPLETE        _SB_MAKEMASK1(11)
-#define M_SYNCSER_RX_EOP_COUNT             _SB_MAKEMASK1(16)
-#define M_SYNCSER_RX_EOP_TIMER             _SB_MAKEMASK1(17)
-#define M_SYNCSER_RX_EOP_SEEN              _SB_MAKEMASK1(18)
-#define M_SYNCSER_RX_HWM                   _SB_MAKEMASK1(19)
-#define M_SYNCSER_RX_LWM                   _SB_MAKEMASK1(20)
-#define M_SYNCSER_RX_DSCR                  _SB_MAKEMASK1(21)
-#define M_SYNCSER_RX_DERR                  _SB_MAKEMASK1(22)
-#define M_SYNCSER_TX_EOP_COUNT             _SB_MAKEMASK1(24)
-#define M_SYNCSER_TX_EOP_TIMER             _SB_MAKEMASK1(25)
-#define M_SYNCSER_TX_EOP_SEEN              _SB_MAKEMASK1(26)
-#define M_SYNCSER_TX_HWM                   _SB_MAKEMASK1(27)
-#define M_SYNCSER_TX_LWM                   _SB_MAKEMASK1(28)
-#define M_SYNCSER_TX_DSCR                  _SB_MAKEMASK1(29)
-#define M_SYNCSER_TX_DERR                  _SB_MAKEMASK1(30)
-#define M_SYNCSER_TX_DZERO                 _SB_MAKEMASK1(31)
-
-/*
- * Sequencer Table Entry format
- */
-
-#define M_SYNCSER_SEQ_LAST                 _SB_MAKEMASK1(0)
-#define M_SYNCSER_SEQ_BYTE                 _SB_MAKEMASK1(1)
-
-#define S_SYNCSER_SEQ_COUNT                2
-#define M_SYNCSER_SEQ_COUNT                _SB_MAKEMASK(4, S_SYNCSER_SEQ_COUNT)
-#define V_SYNCSER_SEQ_COUNT(x)             _SB_MAKEVALUE(x, S_SYNCSER_SEQ_COUNT)
-
-#define M_SYNCSER_SEQ_ENABLE               _SB_MAKEMASK1(6)
-#define M_SYNCSER_SEQ_STROBE               _SB_MAKEMASK1(7)
-
-#endif
diff --git a/include/asm-mips/sibyte/sb1250_uart.h b/include/asm-mips/sibyte/sb1250_uart.h
deleted file mode 100644
index d835bf280140..000000000000
--- a/include/asm-mips/sibyte/sb1250_uart.h
+++ /dev/null
@@ -1,362 +0,0 @@
-/*  *********************************************************************
-    *  SB1250 Board Support Package
-    *
-    *  UART Constants                           File: sb1250_uart.h
-    *
-    *  This module contains constants and macros useful for
-    *  manipulating the SB1250's UARTs
-    *
-    *  SB1250 specification level:  User's manual 1/02/02
-    *
-    *********************************************************************
-    *
-    *  Copyright 2000,2001,2002,2003
-    *  Broadcom Corporation. All rights reserved.
-    *
-    *  This program is free software; you can redistribute it and/or
-    *  modify it under the terms of the GNU General Public License as
-    *  published by the Free Software Foundation; either version 2 of
-    *  the License, or (at your option) any later version.
-    *
-    *  This program is distributed in the hope that it will be useful,
-    *  but WITHOUT ANY WARRANTY; without even the implied warranty of
-    *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-    *  GNU General Public License for more details.
-    *
-    *  You should have received a copy of the GNU General Public License
-    *  along with this program; if not, write to the Free Software
-    *  Foundation, Inc., 59 Temple Place, Suite 330, Boston,
-    *  MA 02111-1307 USA
-    ********************************************************************* */
-
-
-#ifndef _SB1250_UART_H
-#define _SB1250_UART_H
-
-#include "sb1250_defs.h"
-
-/* **********************************************************************
-   * DUART Registers
-   ********************************************************************** */
-
-/*
- * DUART Mode Register #1 (Table 10-3)
- * Register: DUART_MODE_REG_1_A
- * Register: DUART_MODE_REG_1_B
- */
-
-#define S_DUART_BITS_PER_CHAR       0
-#define M_DUART_BITS_PER_CHAR       _SB_MAKEMASK(2, S_DUART_BITS_PER_CHAR)
-#define V_DUART_BITS_PER_CHAR(x)    _SB_MAKEVALUE(x, S_DUART_BITS_PER_CHAR)
-
-#define K_DUART_BITS_PER_CHAR_RSV0  0
-#define K_DUART_BITS_PER_CHAR_RSV1  1
-#define K_DUART_BITS_PER_CHAR_7     2
-#define K_DUART_BITS_PER_CHAR_8     3
-
-#define V_DUART_BITS_PER_CHAR_RSV0  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV0)
-#define V_DUART_BITS_PER_CHAR_RSV1  V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_RSV1)
-#define V_DUART_BITS_PER_CHAR_7     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_7)
-#define V_DUART_BITS_PER_CHAR_8     V_DUART_BITS_PER_CHAR(K_DUART_BITS_PER_CHAR_8)
-
-
-#define M_DUART_PARITY_TYPE_EVEN    0x00
-#define M_DUART_PARITY_TYPE_ODD     _SB_MAKEMASK1(2)
-
-#define S_DUART_PARITY_MODE          3
-#define M_DUART_PARITY_MODE         _SB_MAKEMASK(2, S_DUART_PARITY_MODE)
-#define V_DUART_PARITY_MODE(x)      _SB_MAKEVALUE(x, S_DUART_PARITY_MODE)
-
-#define K_DUART_PARITY_MODE_ADD       0
-#define K_DUART_PARITY_MODE_ADD_FIXED 1
-#define K_DUART_PARITY_MODE_NONE      2
-
-#define V_DUART_PARITY_MODE_ADD       V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD)
-#define V_DUART_PARITY_MODE_ADD_FIXED V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_ADD_FIXED)
-#define V_DUART_PARITY_MODE_NONE      V_DUART_PARITY_MODE(K_DUART_PARITY_MODE_NONE)
-
-#define M_DUART_TX_IRQ_SEL_TXRDY    0
-#define M_DUART_TX_IRQ_SEL_TXEMPT   _SB_MAKEMASK1(5)
-
-#define M_DUART_RX_IRQ_SEL_RXRDY    0
-#define M_DUART_RX_IRQ_SEL_RXFULL   _SB_MAKEMASK1(6)
-
-#define M_DUART_RX_RTS_ENA          _SB_MAKEMASK1(7)
-
-/*
- * DUART Mode Register #2 (Table 10-4)
- * Register: DUART_MODE_REG_2_A
- * Register: DUART_MODE_REG_2_B
- */
-
-#define M_DUART_MODE_RESERVED1      _SB_MAKEMASK(3, 0)   /* ignored */
-
-#define M_DUART_STOP_BIT_LEN_2      _SB_MAKEMASK1(3)
-#define M_DUART_STOP_BIT_LEN_1      0
-
-#define M_DUART_TX_CTS_ENA          _SB_MAKEMASK1(4)
-
-
-#define M_DUART_MODE_RESERVED2      _SB_MAKEMASK1(5)    /* must be zero */
-
-#define S_DUART_CHAN_MODE           6
-#define M_DUART_CHAN_MODE           _SB_MAKEMASK(2, S_DUART_CHAN_MODE)
-#define V_DUART_CHAN_MODE(x)        _SB_MAKEVALUE(x, S_DUART_CHAN_MODE)
-
-#define K_DUART_CHAN_MODE_NORMAL    0
-#define K_DUART_CHAN_MODE_LCL_LOOP  2
-#define K_DUART_CHAN_MODE_REM_LOOP  3
-
-#define V_DUART_CHAN_MODE_NORMAL    V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_NORMAL)
-#define V_DUART_CHAN_MODE_LCL_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_LCL_LOOP)
-#define V_DUART_CHAN_MODE_REM_LOOP  V_DUART_CHAN_MODE(K_DUART_CHAN_MODE_REM_LOOP)
-
-/*
- * DUART Command Register (Table 10-5)
- * Register: DUART_CMD_A
- * Register: DUART_CMD_B
- */
-
-#define M_DUART_RX_EN               _SB_MAKEMASK1(0)
-#define M_DUART_RX_DIS              _SB_MAKEMASK1(1)
-#define M_DUART_TX_EN               _SB_MAKEMASK1(2)
-#define M_DUART_TX_DIS              _SB_MAKEMASK1(3)
-
-#define S_DUART_MISC_CMD            4
-#define M_DUART_MISC_CMD            _SB_MAKEMASK(3, S_DUART_MISC_CMD)
-#define V_DUART_MISC_CMD(x)         _SB_MAKEVALUE(x, S_DUART_MISC_CMD)
-
-#define K_DUART_MISC_CMD_NOACTION0       0
-#define K_DUART_MISC_CMD_NOACTION1       1
-#define K_DUART_MISC_CMD_RESET_RX        2
-#define K_DUART_MISC_CMD_RESET_TX        3
-#define K_DUART_MISC_CMD_NOACTION4       4
-#define K_DUART_MISC_CMD_RESET_BREAK_INT 5
-#define K_DUART_MISC_CMD_START_BREAK     6
-#define K_DUART_MISC_CMD_STOP_BREAK      7
-
-#define V_DUART_MISC_CMD_NOACTION0       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION0)
-#define V_DUART_MISC_CMD_NOACTION1       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION1)
-#define V_DUART_MISC_CMD_RESET_RX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_RX)
-#define V_DUART_MISC_CMD_RESET_TX        V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_TX)
-#define V_DUART_MISC_CMD_NOACTION4       V_DUART_MISC_CMD(K_DUART_MISC_CMD_NOACTION4)
-#define V_DUART_MISC_CMD_RESET_BREAK_INT V_DUART_MISC_CMD(K_DUART_MISC_CMD_RESET_BREAK_INT)
-#define V_DUART_MISC_CMD_START_BREAK     V_DUART_MISC_CMD(K_DUART_MISC_CMD_START_BREAK)
-#define V_DUART_MISC_CMD_STOP_BREAK      V_DUART_MISC_CMD(K_DUART_MISC_CMD_STOP_BREAK)
-
-#define M_DUART_CMD_RESERVED             _SB_MAKEMASK1(7)
-
-/*
- * DUART Status Register (Table 10-6)
- * Register: DUART_STATUS_A
- * Register: DUART_STATUS_B
- * READ-ONLY
- */
-
-#define M_DUART_RX_RDY              _SB_MAKEMASK1(0)
-#define M_DUART_RX_FFUL             _SB_MAKEMASK1(1)
-#define M_DUART_TX_RDY              _SB_MAKEMASK1(2)
-#define M_DUART_TX_EMT              _SB_MAKEMASK1(3)
-#define M_DUART_OVRUN_ERR           _SB_MAKEMASK1(4)
-#define M_DUART_PARITY_ERR          _SB_MAKEMASK1(5)
-#define M_DUART_FRM_ERR             _SB_MAKEMASK1(6)
-#define M_DUART_RCVD_BRK            _SB_MAKEMASK1(7)
-
-/*
- * DUART Baud Rate Register (Table 10-7)
- * Register: DUART_CLK_SEL_A
- * Register: DUART_CLK_SEL_B
- */
-
-#define M_DUART_CLK_COUNTER         _SB_MAKEMASK(12, 0)
-#define V_DUART_BAUD_RATE(x)        (100000000/((x)*20)-1)
-
-/*
- * DUART Data Registers (Table 10-8 and 10-9)
- * Register: DUART_RX_HOLD_A
- * Register: DUART_RX_HOLD_B
- * Register: DUART_TX_HOLD_A
- * Register: DUART_TX_HOLD_B
- */
-
-#define M_DUART_RX_DATA             _SB_MAKEMASK(8, 0)
-#define M_DUART_TX_DATA             _SB_MAKEMASK(8, 0)
-
-/*
- * DUART Input Port Register (Table 10-10)
- * Register: DUART_IN_PORT
- */
-
-#define M_DUART_IN_PIN0_VAL         _SB_MAKEMASK1(0)
-#define M_DUART_IN_PIN1_VAL         _SB_MAKEMASK1(1)
-#define M_DUART_IN_PIN2_VAL         _SB_MAKEMASK1(2)
-#define M_DUART_IN_PIN3_VAL         _SB_MAKEMASK1(3)
-#define M_DUART_IN_PIN4_VAL         _SB_MAKEMASK1(4)
-#define M_DUART_IN_PIN5_VAL         _SB_MAKEMASK1(5)
-#define M_DUART_RIN0_PIN            _SB_MAKEMASK1(6)
-#define M_DUART_RIN1_PIN            _SB_MAKEMASK1(7)
-
-/*
- * DUART Input Port Change Status Register (Tables 10-11, 10-12, and 10-13)
- * Register: DUART_INPORT_CHNG
- */
-
-#define S_DUART_IN_PIN_VAL          0
-#define M_DUART_IN_PIN_VAL          _SB_MAKEMASK(4, S_DUART_IN_PIN_VAL)
-
-#define S_DUART_IN_PIN_CHNG         4
-#define M_DUART_IN_PIN_CHNG         _SB_MAKEMASK(4, S_DUART_IN_PIN_CHNG)
-
-
-/*
- * DUART Output port control register (Table 10-14)
- * Register: DUART_OPCR
- */
-
-#define M_DUART_OPCR_RESERVED0      _SB_MAKEMASK1(0)   /* must be zero */
-#define M_DUART_OPC2_SEL            _SB_MAKEMASK1(1)
-#define M_DUART_OPCR_RESERVED1      _SB_MAKEMASK1(2)   /* must be zero */
-#define M_DUART_OPC3_SEL            _SB_MAKEMASK1(3)
-#define M_DUART_OPCR_RESERVED2      _SB_MAKEMASK(4, 4)  /* must be zero */
-
-/*
- * DUART Aux Control Register (Table 10-15)
- * Register: DUART_AUX_CTRL
- */
-
-#define M_DUART_IP0_CHNG_ENA        _SB_MAKEMASK1(0)
-#define M_DUART_IP1_CHNG_ENA        _SB_MAKEMASK1(1)
-#define M_DUART_IP2_CHNG_ENA        _SB_MAKEMASK1(2)
-#define M_DUART_IP3_CHNG_ENA        _SB_MAKEMASK1(3)
-#define M_DUART_ACR_RESERVED        _SB_MAKEMASK(4, 4)
-
-#define M_DUART_CTS_CHNG_ENA        _SB_MAKEMASK1(0)
-#define M_DUART_CIN_CHNG_ENA        _SB_MAKEMASK1(2)
-
-/*
- * DUART Interrupt Status Register (Table 10-16)
- * Register: DUART_ISR
- */
-
-#define M_DUART_ISR_TX_A            _SB_MAKEMASK1(0)
-
-#define S_DUART_ISR_RX_A            1
-#define M_DUART_ISR_RX_A            _SB_MAKEMASK1(S_DUART_ISR_RX_A)
-#define V_DUART_ISR_RX_A(x)         _SB_MAKEVALUE(x, S_DUART_ISR_RX_A)
-#define G_DUART_ISR_RX_A(x)         _SB_GETVALUE(x, S_DUART_ISR_RX_A, M_DUART_ISR_RX_A)
-
-#define M_DUART_ISR_BRK_A           _SB_MAKEMASK1(2)
-#define M_DUART_ISR_IN_A            _SB_MAKEMASK1(3)
-#define M_DUART_ISR_ALL_A           _SB_MAKEMASK(4, 0)
-
-#define M_DUART_ISR_TX_B            _SB_MAKEMASK1(4)
-#define M_DUART_ISR_RX_B            _SB_MAKEMASK1(5)
-#define M_DUART_ISR_BRK_B           _SB_MAKEMASK1(6)
-#define M_DUART_ISR_IN_B            _SB_MAKEMASK1(7)
-#define M_DUART_ISR_ALL_B           _SB_MAKEMASK(4, 4)
-
-/*
- * DUART Channel A Interrupt Status Register (Table 10-17)
- * DUART Channel B Interrupt Status Register (Table 10-18)
- * Register: DUART_ISR_A
- * Register: DUART_ISR_B
- */
-
-#define M_DUART_ISR_TX              _SB_MAKEMASK1(0)
-#define M_DUART_ISR_RX              _SB_MAKEMASK1(1)
-#define M_DUART_ISR_BRK             _SB_MAKEMASK1(2)
-#define M_DUART_ISR_IN              _SB_MAKEMASK1(3)
-#define M_DUART_ISR_ALL             _SB_MAKEMASK(4, 0)
-#define M_DUART_ISR_RESERVED        _SB_MAKEMASK(4, 4)
-
-/*
- * DUART Interrupt Mask Register (Table 10-19)
- * Register: DUART_IMR
- */
-
-#define M_DUART_IMR_TX_A            _SB_MAKEMASK1(0)
-#define M_DUART_IMR_RX_A            _SB_MAKEMASK1(1)
-#define M_DUART_IMR_BRK_A           _SB_MAKEMASK1(2)
-#define M_DUART_IMR_IN_A            _SB_MAKEMASK1(3)
-#define M_DUART_IMR_ALL_A           _SB_MAKEMASK(4, 0)
-
-#define M_DUART_IMR_TX_B            _SB_MAKEMASK1(4)
-#define M_DUART_IMR_RX_B            _SB_MAKEMASK1(5)
-#define M_DUART_IMR_BRK_B           _SB_MAKEMASK1(6)
-#define M_DUART_IMR_IN_B            _SB_MAKEMASK1(7)
-#define M_DUART_IMR_ALL_B           _SB_MAKEMASK(4, 4)
-
-/*
- * DUART Channel A Interrupt Mask Register (Table 10-20)
- * DUART Channel B Interrupt Mask Register (Table 10-21)
- * Register: DUART_IMR_A
- * Register: DUART_IMR_B
- */
-
-#define M_DUART_IMR_TX              _SB_MAKEMASK1(0)
-#define M_DUART_IMR_RX              _SB_MAKEMASK1(1)
-#define M_DUART_IMR_BRK             _SB_MAKEMASK1(2)
-#define M_DUART_IMR_IN              _SB_MAKEMASK1(3)
-#define M_DUART_IMR_ALL             _SB_MAKEMASK(4, 0)
-#define M_DUART_IMR_RESERVED        _SB_MAKEMASK(4, 4)
-
-
-/*
- * DUART Output Port Set Register (Table 10-22)
- * Register: DUART_SET_OPR
- */
-
-#define M_DUART_SET_OPR0            _SB_MAKEMASK1(0)
-#define M_DUART_SET_OPR1            _SB_MAKEMASK1(1)
-#define M_DUART_SET_OPR2            _SB_MAKEMASK1(2)
-#define M_DUART_SET_OPR3            _SB_MAKEMASK1(3)
-#define M_DUART_OPSR_RESERVED       _SB_MAKEMASK(4, 4)
-
-/*
- * DUART Output Port Clear Register (Table 10-23)
- * Register: DUART_CLEAR_OPR
- */
-
-#define M_DUART_CLR_OPR0            _SB_MAKEMASK1(0)
-#define M_DUART_CLR_OPR1            _SB_MAKEMASK1(1)
-#define M_DUART_CLR_OPR2            _SB_MAKEMASK1(2)
-#define M_DUART_CLR_OPR3            _SB_MAKEMASK1(3)
-#define M_DUART_OPCR_RESERVED       _SB_MAKEMASK(4, 4)
-
-/*
- * DUART Output Port RTS Register (Table 10-24)
- * Register: DUART_OUT_PORT
- */
-
-#define M_DUART_OUT_PIN_SET0        _SB_MAKEMASK1(0)
-#define M_DUART_OUT_PIN_SET1        _SB_MAKEMASK1(1)
-#define M_DUART_OUT_PIN_CLR0        _SB_MAKEMASK1(2)
-#define M_DUART_OUT_PIN_CLR1        _SB_MAKEMASK1(3)
-#define M_DUART_OPRR_RESERVED       _SB_MAKEMASK(4, 4)
-
-#define M_DUART_OUT_PIN_SET(chan) \
-    (chan == 0 ? M_DUART_OUT_PIN_SET0 : M_DUART_OUT_PIN_SET1)
-#define M_DUART_OUT_PIN_CLR(chan) \
-    (chan == 0 ? M_DUART_OUT_PIN_CLR0 : M_DUART_OUT_PIN_CLR1)
-
-#if SIBYTE_HDR_FEATURE(1250, PASS2) || SIBYTE_HDR_FEATURE(112x, PASS1) || SIBYTE_HDR_FEATURE_CHIP(1480)
-/*
- * Full Interrupt Control Register
- */
-
-#define S_DUART_SIG_FULL           _SB_MAKE64(0)
-#define M_DUART_SIG_FULL           _SB_MAKEMASK(4, S_DUART_SIG_FULL)
-#define V_DUART_SIG_FULL(x)        _SB_MAKEVALUE(x, S_DUART_SIG_FULL)
-#define G_DUART_SIG_FULL(x)        _SB_GETVALUE(x, S_DUART_SIG_FULL, M_DUART_SIG_FULL)
-
-#define S_DUART_INT_TIME           _SB_MAKE64(4)
-#define M_DUART_INT_TIME           _SB_MAKEMASK(4, S_DUART_INT_TIME)
-#define V_DUART_INT_TIME(x)        _SB_MAKEVALUE(x, S_DUART_INT_TIME)
-#define G_DUART_INT_TIME(x)        _SB_GETVALUE(x, S_DUART_INT_TIME, M_DUART_INT_TIME)
-#endif /* 1250 PASS2 || 112x PASS1 || 1480 */
-
-
-/* ********************************************************************** */
-
-
-#endif
diff --git a/include/asm-mips/sibyte/sentosa.h b/include/asm-mips/sibyte/sentosa.h
deleted file mode 100644
index 64c47874f32d..000000000000
--- a/include/asm-mips/sibyte/sentosa.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * Copyright (C) 2000, 2001 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-#ifndef __ASM_SIBYTE_SENTOSA_H
-#define __ASM_SIBYTE_SENTOSA_H
-
-#include <asm/sibyte/sb1250.h>
-#include <asm/sibyte/sb1250_int.h>
-
-#ifdef CONFIG_SIBYTE_SENTOSA
-#define SIBYTE_BOARD_NAME "BCM91250E (Sentosa)"
-#endif
-#ifdef CONFIG_SIBYTE_RHONE
-#define SIBYTE_BOARD_NAME "BCM91125E (Rhone)"
-#endif
-
-/* Generic bus chip selects */
-#ifdef CONFIG_SIBYTE_RHONE
-#define LEDS_CS         6
-#define LEDS_PHYS       0x1d0a0000
-#endif
-
-/* GPIOs */
-#define K_GPIO_DBG_LED  0
-
-#endif /* __ASM_SIBYTE_SENTOSA_H */
diff --git a/include/asm-mips/sibyte/swarm.h b/include/asm-mips/sibyte/swarm.h
deleted file mode 100644
index 114d9d29ca9d..000000000000
--- a/include/asm-mips/sibyte/swarm.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * Copyright (C) 2000, 2001, 2002, 2003 Broadcom Corporation
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version 2
- * of the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA  02111-1307, USA.
- */
-#ifndef __ASM_SIBYTE_SWARM_H
-#define __ASM_SIBYTE_SWARM_H
-
-#include <asm/sibyte/sb1250.h>
-#include <asm/sibyte/sb1250_int.h>
-
-#ifdef CONFIG_SIBYTE_SWARM
-#define SIBYTE_BOARD_NAME "BCM91250A (SWARM)"
-#define SIBYTE_HAVE_PCMCIA 1
-#define SIBYTE_HAVE_IDE    1
-#endif
-#ifdef CONFIG_SIBYTE_LITTLESUR
-#define SIBYTE_BOARD_NAME "BCM91250C2 (LittleSur)"
-#define SIBYTE_HAVE_PCMCIA 0
-#define SIBYTE_HAVE_IDE    1
-#define SIBYTE_DEFAULT_CONSOLE "cfe0"
-#endif
-#ifdef CONFIG_SIBYTE_CRHONE
-#define SIBYTE_BOARD_NAME "BCM91125C (CRhone)"
-#define SIBYTE_HAVE_PCMCIA 0
-#define SIBYTE_HAVE_IDE    0
-#endif
-#ifdef CONFIG_SIBYTE_CRHINE
-#define SIBYTE_BOARD_NAME "BCM91120C (CRhine)"
-#define SIBYTE_HAVE_PCMCIA 0
-#define SIBYTE_HAVE_IDE    0
-#endif
-
-/* Generic bus chip selects */
-#define LEDS_CS         3
-#define LEDS_PHYS       0x100a0000
-
-#ifdef SIBYTE_HAVE_IDE
-#define IDE_CS          4
-#define IDE_PHYS        0x100b0000
-#define K_GPIO_GB_IDE   4
-#define K_INT_GB_IDE    (K_INT_GPIO_0 + K_GPIO_GB_IDE)
-#endif
-
-#ifdef SIBYTE_HAVE_PCMCIA
-#define PCMCIA_CS       6
-#define PCMCIA_PHYS     0x11000000
-#define K_GPIO_PC_READY 9
-#define K_INT_PC_READY  (K_INT_GPIO_0 + K_GPIO_PC_READY)
-#endif
-
-#endif /* __ASM_SIBYTE_SWARM_H */
diff --git a/include/asm-mips/sigcontext.h b/include/asm-mips/sigcontext.h
deleted file mode 100644
index 9ce0607d7a4e..000000000000
--- a/include/asm-mips/sigcontext.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1999 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SIGCONTEXT_H
-#define _ASM_SIGCONTEXT_H
-
-#include <asm/sgidefs.h>
-
-#if _MIPS_SIM == _MIPS_SIM_ABI32
-
-/*
- * Keep this struct definition in sync with the sigcontext fragment
- * in arch/mips/tools/offset.c
- */
-struct sigcontext {
-        unsigned int            sc_regmask;     /* Unused */
-        unsigned int            sc_status;      /* Unused */
-        unsigned long long      sc_pc;
-        unsigned long long      sc_regs[32];
-        unsigned long long      sc_fpregs[32];
-        unsigned int            sc_acx;         /* Was sc_ownedfp */
-        unsigned int            sc_fpc_csr;
-        unsigned int            sc_fpc_eir;     /* Unused */
-        unsigned int            sc_used_math;
-        unsigned int            sc_dsp;         /* dsp status, was sc_ssflags */
-        unsigned long long      sc_mdhi;
-        unsigned long long      sc_mdlo;
-        unsigned long           sc_hi1;         /* Was sc_cause */
-        unsigned long           sc_lo1;         /* Was sc_badvaddr */
-        unsigned long           sc_hi2;         /* Was sc_sigset[4] */
-        unsigned long           sc_lo2;
-        unsigned long           sc_hi3;
-        unsigned long           sc_lo3;
-};
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32
-
-#include <linux/posix_types.h>
-/*
- * Keep this struct definition in sync with the sigcontext fragment
- * in arch/mips/tools/offset.c
- *
- * Warning: this structure illdefined with sc_badvaddr being just an unsigned
- * int so it was changed to unsigned long in 2.6.0-test1.  This may break
- * binary compatibility - no prisoners.
- * DSP ASE in 2.6.12-rc4.  Turn sc_mdhi and sc_mdlo into an array of four
- * entries, add sc_dsp and sc_reserved for padding.  No prisoners.
- */
-struct sigcontext {
-        __u64   sc_regs[32];
-        __u64   sc_fpregs[32];
-        __u64   sc_mdhi;
-        __u64   sc_hi1;
-        __u64   sc_hi2;
-        __u64   sc_hi3;
-        __u64   sc_mdlo;
-        __u64   sc_lo1;
-        __u64   sc_lo2;
-        __u64   sc_lo3;
-        __u64   sc_pc;
-        __u32   sc_fpc_csr;
-        __u32   sc_used_math;
-        __u32   sc_dsp;
-        __u32   sc_reserved;
-};
-
-#ifdef __KERNEL__
-
-struct sigcontext32 {
-        __u32           sc_regmask;     /* Unused */
-        __u32           sc_status;      /* Unused */
-        __u64           sc_pc;
-        __u64           sc_regs[32];
-        __u64           sc_fpregs[32];
-        __u32           sc_acx;         /* Only MIPS32; was sc_ownedfp */
-        __u32           sc_fpc_csr;
-        __u32           sc_fpc_eir;     /* Unused */
-        __u32           sc_used_math;
-        __u32           sc_dsp;         /* dsp status, was sc_ssflags */
-        __u64           sc_mdhi;
-        __u64           sc_mdlo;
-        __u32           sc_hi1;         /* Was sc_cause */
-        __u32           sc_lo1;         /* Was sc_badvaddr */
-        __u32           sc_hi2;         /* Was sc_sigset[4] */
-        __u32           sc_lo2;
-        __u32           sc_hi3;
-        __u32           sc_lo3;
-};
-#endif /* __KERNEL__ */
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 || _MIPS_SIM == _MIPS_SIM_NABI32 */
-
-#endif /* _ASM_SIGCONTEXT_H */
diff --git a/include/asm-mips/siginfo.h b/include/asm-mips/siginfo.h
deleted file mode 100644
index 96e28f18dad1..000000000000
--- a/include/asm-mips/siginfo.h
+++ /dev/null
@@ -1,130 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 1999, 2001, 2003 Ralf Baechle
- * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SIGINFO_H
-#define _ASM_SIGINFO_H
-
-
-#define __ARCH_SIGEV_PREAMBLE_SIZE (sizeof(long) + 2*sizeof(int))
-#undef __ARCH_SI_TRAPNO /* exception code needs to fill this ...  */
-
-#define HAVE_ARCH_SIGINFO_T
-
-/*
- * We duplicate the generic versions - <asm-generic/siginfo.h> is just borked
- * by design ...
- */
-#define HAVE_ARCH_COPY_SIGINFO
-struct siginfo;
-
-/*
- * Careful to keep union _sifields from shifting ...
- */
-#ifdef CONFIG_32BIT
-#define __ARCH_SI_PREAMBLE_SIZE (3 * sizeof(int))
-#endif
-#ifdef CONFIG_64BIT
-#define __ARCH_SI_PREAMBLE_SIZE (4 * sizeof(int))
-#endif
-
-#include <asm-generic/siginfo.h>
-
-typedef struct siginfo {
-        int si_signo;
-        int si_code;
-        int si_errno;
-        int __pad0[SI_MAX_SIZE / sizeof(int) - SI_PAD_SIZE - 3];
-
-        union {
-                int _pad[SI_PAD_SIZE];
-
-                /* kill() */
-                struct {
-                        pid_t _pid;             /* sender's pid */
-                        __ARCH_SI_UID_T _uid;   /* sender's uid */
-                } _kill;
-
-                /* POSIX.1b timers */
-                struct {
-                        timer_t _tid;           /* timer id */
-                        int _overrun;           /* overrun count */
-                        char _pad[sizeof( __ARCH_SI_UID_T) - sizeof(int)];
-                        sigval_t _sigval;       /* same as below */
-                        int _sys_private;       /* not to be passed to user */
-                } _timer;
-
-                /* POSIX.1b signals */
-                struct {
-                        pid_t _pid;             /* sender's pid */
-                        __ARCH_SI_UID_T _uid;   /* sender's uid */
-                        sigval_t _sigval;
-                } _rt;
-
-                /* SIGCHLD */
-                struct {
-                        pid_t _pid;             /* which child */
-                        __ARCH_SI_UID_T _uid;   /* sender's uid */
-                        int _status;            /* exit code */
-                        clock_t _utime;
-                        clock_t _stime;
-                } _sigchld;
-
-                /* IRIX SIGCHLD */
-                struct {
-                        pid_t _pid;             /* which child */
-                        clock_t _utime;
-                        int _status;            /* exit code */
-                        clock_t _stime;
-                } _irix_sigchld;
-
-                /* SIGILL, SIGFPE, SIGSEGV, SIGBUS */
-                struct {
-                        void __user *_addr; /* faulting insn/memory ref. */
-#ifdef __ARCH_SI_TRAPNO
-                        int _trapno;    /* TRAP # which caused the signal */
-#endif
-                } _sigfault;
-
-                /* SIGPOLL, SIGXFSZ (To do ...)  */
-                struct {
-                        __ARCH_SI_BAND_T _band; /* POLL_IN, POLL_OUT, POLL_MSG */
-                        int _fd;
-                } _sigpoll;
-        } _sifields;
-} siginfo_t;
-
-/*
- * si_code values
- * Again these have been choosen to be IRIX compatible.
- */
-#undef SI_ASYNCIO
-#undef SI_TIMER
-#undef SI_MESGQ
-#define SI_ASYNCIO      -2      /* sent by AIO completion */
-#define SI_TIMER __SI_CODE(__SI_TIMER, -3) /* sent by timer expiration */
-#define SI_MESGQ __SI_CODE(__SI_MESGQ, -4) /* sent by real time mesq state change */
-
-#ifdef __KERNEL__
-
-/*
- * Duplicated here because of <asm-generic/siginfo.h> braindamage ...
- */
-#include <linux/string.h>
-
-static inline void copy_siginfo(struct siginfo *to, struct siginfo *from)
-{
-        if (from->si_code < 0)
-                memcpy(to, from, sizeof(*to));
-        else
-                /* _sigchld is currently the largest know union member */
-                memcpy(to, from, 3*sizeof(int) + sizeof(from->_sifields._sigchld));
-}
-
-#endif
-
-#endif /* _ASM_SIGINFO_H */
diff --git a/include/asm-mips/signal.h b/include/asm-mips/signal.h
deleted file mode 100644
index bee5153aca48..000000000000
--- a/include/asm-mips/signal.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 97, 98, 99, 2003 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SIGNAL_H
-#define _ASM_SIGNAL_H
-
-#include <linux/types.h>
-
-#define _NSIG           128
-#define _NSIG_BPW       (sizeof(unsigned long) * 8)
-#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
-
-typedef struct {
-        unsigned long sig[_NSIG_WORDS];
-} sigset_t;
-
-typedef unsigned long old_sigset_t;             /* at least 32 bits */
-
-#define SIGHUP           1      /* Hangup (POSIX).  */
-#define SIGINT           2      /* Interrupt (ANSI).  */
-#define SIGQUIT          3      /* Quit (POSIX).  */
-#define SIGILL           4      /* Illegal instruction (ANSI).  */
-#define SIGTRAP          5      /* Trace trap (POSIX).  */
-#define SIGIOT           6      /* IOT trap (4.2 BSD).  */
-#define SIGABRT          SIGIOT /* Abort (ANSI).  */
-#define SIGEMT           7
-#define SIGFPE           8      /* Floating-point exception (ANSI).  */
-#define SIGKILL          9      /* Kill, unblockable (POSIX).  */
-#define SIGBUS          10      /* BUS error (4.2 BSD).  */
-#define SIGSEGV         11      /* Segmentation violation (ANSI).  */
-#define SIGSYS          12
-#define SIGPIPE         13      /* Broken pipe (POSIX).  */
-#define SIGALRM         14      /* Alarm clock (POSIX).  */
-#define SIGTERM         15      /* Termination (ANSI).  */
-#define SIGUSR1         16      /* User-defined signal 1 (POSIX).  */
-#define SIGUSR2         17      /* User-defined signal 2 (POSIX).  */
-#define SIGCHLD         18      /* Child status has changed (POSIX).  */
-#define SIGCLD          SIGCHLD /* Same as SIGCHLD (System V).  */
-#define SIGPWR          19      /* Power failure restart (System V).  */
-#define SIGWINCH        20      /* Window size change (4.3 BSD, Sun).  */
-#define SIGURG          21      /* Urgent condition on socket (4.2 BSD).  */
-#define SIGIO           22      /* I/O now possible (4.2 BSD).  */
-#define SIGPOLL         SIGIO   /* Pollable event occurred (System V).  */
-#define SIGSTOP         23      /* Stop, unblockable (POSIX).  */
-#define SIGTSTP         24      /* Keyboard stop (POSIX).  */
-#define SIGCONT         25      /* Continue (POSIX).  */
-#define SIGTTIN         26      /* Background read from tty (POSIX).  */
-#define SIGTTOU         27      /* Background write to tty (POSIX).  */
-#define SIGVTALRM       28      /* Virtual alarm clock (4.2 BSD).  */
-#define SIGPROF         29      /* Profiling alarm clock (4.2 BSD).  */
-#define SIGXCPU         30      /* CPU limit exceeded (4.2 BSD).  */
-#define SIGXFSZ         31      /* File size limit exceeded (4.2 BSD).  */
-
-/* These should not be considered constants from userland.  */
-#define SIGRTMIN        32
-#define SIGRTMAX        _NSIG
-
-/*
- * SA_FLAGS values:
- *
- * SA_ONSTACK indicates that a registered stack_t will be used.
- * SA_RESTART flag to get restarting signals (which were the default long ago)
- * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
- * SA_RESETHAND clears the handler when the signal is delivered.
- * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
- * SA_NODEFER prevents the current signal from being masked in the handler.
- *
- * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
- * Unix names RESETHAND and NODEFER respectively.
- */
-#define SA_ONSTACK      0x08000000
-#define SA_RESETHAND    0x80000000
-#define SA_RESTART      0x10000000
-#define SA_SIGINFO      0x00000008
-#define SA_NODEFER      0x40000000
-#define SA_NOCLDWAIT    0x00010000
-#define SA_NOCLDSTOP    0x00000001
-
-#define SA_NOMASK       SA_NODEFER
-#define SA_ONESHOT      SA_RESETHAND
-
-#define SA_RESTORER     0x04000000      /* Only for o32 */
-
-/*
- * sigaltstack controls
- */
-#define SS_ONSTACK     1
-#define SS_DISABLE     2
-
-#define MINSIGSTKSZ    2048
-#define SIGSTKSZ       8192
-
-#ifdef __KERNEL__
-
-#ifdef CONFIG_TRAD_SIGNALS
-#define sig_uses_siginfo(ka)    ((ka)->sa.sa_flags & SA_SIGINFO)
-#else
-#define sig_uses_siginfo(ka)    (1)
-#endif
-
-#endif /* __KERNEL__ */
-
-#define SIG_BLOCK       1       /* for blocking signals */
-#define SIG_UNBLOCK     2       /* for unblocking signals */
-#define SIG_SETMASK     3       /* for setting the signal mask */
-
-#include <asm-generic/signal.h>
-
-struct sigaction {
-        unsigned int    sa_flags;
-        __sighandler_t  sa_handler;
-        sigset_t        sa_mask;
-};
-
-struct k_sigaction {
-        struct sigaction sa;
-};
-
-/* IRIX compatible stack_t  */
-typedef struct sigaltstack {
-        void __user *ss_sp;
-        size_t ss_size;
-        int ss_flags;
-} stack_t;
-
-#ifdef __KERNEL__
-#include <asm/sigcontext.h>
-#include <asm/siginfo.h>
-
-#define ptrace_signal_deliver(regs, cookie) do { } while (0)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_SIGNAL_H */
diff --git a/include/asm-mips/sim.h b/include/asm-mips/sim.h
deleted file mode 100644
index 0cd719fabb51..000000000000
--- a/include/asm-mips/sim.h
+++ /dev/null
@@ -1,82 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999, 2000, 2003 Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SIM_H
-#define _ASM_SIM_H
-
-
-#include <asm/asm-offsets.h>
-
-#define __str2(x) #x
-#define __str(x) __str2(x)
-
-#ifdef CONFIG_32BIT
-
-#define save_static_function(symbol)                                    \
-__asm__(                                                                \
-        ".text\n\t"                                                     \
-        ".globl\t" #symbol "\n\t"                                       \
-        ".align\t2\n\t"                                                 \
-        ".type\t" #symbol ", @function\n\t"                             \
-        ".ent\t" #symbol ", 0\n"                                        \
-        #symbol":\n\t"                                                  \
-        ".frame\t$29, 0, $31\n\t"                                       \
-        "sw\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
-        "sw\t$17,"__str(PT_R17)"($29)\n\t"                              \
-        "sw\t$18,"__str(PT_R18)"($29)\n\t"                              \
-        "sw\t$19,"__str(PT_R19)"($29)\n\t"                              \
-        "sw\t$20,"__str(PT_R20)"($29)\n\t"                              \
-        "sw\t$21,"__str(PT_R21)"($29)\n\t"                              \
-        "sw\t$22,"__str(PT_R22)"($29)\n\t"                              \
-        "sw\t$23,"__str(PT_R23)"($29)\n\t"                              \
-        "sw\t$30,"__str(PT_R30)"($29)\n\t"                              \
-        "j\t_" #symbol "\n\t"                                           \
-        ".end\t" #symbol "\n\t"                                         \
-        ".size\t" #symbol",. - " #symbol)
-
-#define nabi_no_regargs
-
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-
-#define save_static_function(symbol)                                    \
-__asm__(                                                                \
-        ".text\n\t"                                                     \
-        ".globl\t" #symbol "\n\t"                                       \
-        ".align\t2\n\t"                                                 \
-        ".type\t" #symbol ", @function\n\t"                             \
-        ".ent\t" #symbol ", 0\n"                                        \
-        #symbol":\n\t"                                                  \
-        ".frame\t$29, 0, $31\n\t"                                       \
-        "sd\t$16,"__str(PT_R16)"($29)\t\t\t# save_static_function\n\t"  \
-        "sd\t$17,"__str(PT_R17)"($29)\n\t"                              \
-        "sd\t$18,"__str(PT_R18)"($29)\n\t"                              \
-        "sd\t$19,"__str(PT_R19)"($29)\n\t"                              \
-        "sd\t$20,"__str(PT_R20)"($29)\n\t"                              \
-        "sd\t$21,"__str(PT_R21)"($29)\n\t"                              \
-        "sd\t$22,"__str(PT_R22)"($29)\n\t"                              \
-        "sd\t$23,"__str(PT_R23)"($29)\n\t"                              \
-        "sd\t$30,"__str(PT_R30)"($29)\n\t"                              \
-        "j\t_" #symbol "\n\t"                                           \
-        ".end\t" #symbol "\n\t"                                         \
-        ".size\t" #symbol",. - " #symbol)
-
-#define nabi_no_regargs                                                 \
-        unsigned long __dummy0,                                         \
-        unsigned long __dummy1,                                         \
-        unsigned long __dummy2,                                         \
-        unsigned long __dummy3,                                         \
-        unsigned long __dummy4,                                         \
-        unsigned long __dummy5,                                         \
-        unsigned long __dummy6,                                         \
-        unsigned long __dummy7,
-
-#endif /* CONFIG_64BIT */
-
-#endif /* _ASM_SIM_H */
diff --git a/include/asm-mips/smp-ops.h b/include/asm-mips/smp-ops.h
deleted file mode 100644
index 43c207e72a63..000000000000
--- a/include/asm-mips/smp-ops.h
+++ /dev/null
@@ -1,57 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file "COPYING" in the main directory of this
- * archive for more details.
- *
- * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
- * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
- * Copyright (C) 2000, 2001, 2002 Ralf Baechle
- * Copyright (C) 2000, 2001 Broadcom Corporation
- */
-#ifndef __ASM_SMP_OPS_H
-#define __ASM_SMP_OPS_H
-
-#ifdef CONFIG_SMP
-
-#include <linux/cpumask.h>
-
-struct plat_smp_ops {
-        void (*send_ipi_single)(int cpu, unsigned int action);
-        void (*send_ipi_mask)(cpumask_t mask, unsigned int action);
-        void (*init_secondary)(void);
-        void (*smp_finish)(void);
-        void (*cpus_done)(void);
-        void (*boot_secondary)(int cpu, struct task_struct *idle);
-        void (*smp_setup)(void);
-        void (*prepare_cpus)(unsigned int max_cpus);
-};
-
-extern void register_smp_ops(struct plat_smp_ops *ops);
-
-static inline void plat_smp_setup(void)
-{
-        extern struct plat_smp_ops *mp_ops;     /* private */
-
-        mp_ops->smp_setup();
-}
-
-#else /* !CONFIG_SMP */
-
-struct plat_smp_ops;
-
-static inline void plat_smp_setup(void)
-{
-        /* UP, nothing to do ...  */
-}
-
-static inline void register_smp_ops(struct plat_smp_ops *ops)
-{
-}
-
-#endif /* !CONFIG_SMP */
-
-extern struct plat_smp_ops up_smp_ops;
-extern struct plat_smp_ops cmp_smp_ops;
-extern struct plat_smp_ops vsmp_smp_ops;
-
-#endif /* __ASM_SMP_OPS_H */
diff --git a/include/asm-mips/smp.h b/include/asm-mips/smp.h
deleted file mode 100644
index 0ff5b523ea77..000000000000
--- a/include/asm-mips/smp.h
+++ /dev/null
@@ -1,63 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General
- * Public License.  See the file "COPYING" in the main directory of this
- * archive for more details.
- *
- * Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
- * Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
- * Copyright (C) 2000, 2001, 2002 Ralf Baechle
- * Copyright (C) 2000, 2001 Broadcom Corporation
- */
-#ifndef __ASM_SMP_H
-#define __ASM_SMP_H
-
-#include <linux/bitops.h>
-#include <linux/linkage.h>
-#include <linux/threads.h>
-#include <linux/cpumask.h>
-
-#include <asm/atomic.h>
-#include <asm/smp-ops.h>
-
-extern int smp_num_siblings;
-extern cpumask_t cpu_sibling_map[];
-
-#define raw_smp_processor_id() (current_thread_info()->cpu)
-
-/* Map from cpu id to sequential logical cpu number.  This will only
-   not be idempotent when cpus failed to come on-line.  */
-extern int __cpu_number_map[NR_CPUS];
-#define cpu_number_map(cpu)  __cpu_number_map[cpu]
-
-/* The reverse map from sequential logical cpu number to cpu id.  */
-extern int __cpu_logical_map[NR_CPUS];
-#define cpu_logical_map(cpu)  __cpu_logical_map[cpu]
-
-#define NO_PROC_ID      (-1)
-
-#define SMP_RESCHEDULE_YOURSELF 0x1     /* XXX braindead */
-#define SMP_CALL_FUNCTION       0x2
-
-extern cpumask_t phys_cpu_present_map;
-#define cpu_possible_map        phys_cpu_present_map
-
-extern void asmlinkage smp_bootstrap(void);
-
-/*
- * this function sends a 'reschedule' IPI to another CPU.
- * it goes straight through and wastes no time serializing
- * anything. Worst case is that we lose a reschedule ...
- */
-static inline void smp_send_reschedule(int cpu)
-{
-        extern struct plat_smp_ops *mp_ops;     /* private */
-
-        mp_ops->send_ipi_single(cpu, SMP_RESCHEDULE_YOURSELF);
-}
-
-extern asmlinkage void smp_call_function_interrupt(void);
-
-extern void arch_send_call_function_single_ipi(int cpu);
-extern void arch_send_call_function_ipi(cpumask_t mask);
-
-#endif /* __ASM_SMP_H */
diff --git a/include/asm-mips/smtc.h b/include/asm-mips/smtc.h
deleted file mode 100644
index 3639b28f80db..000000000000
--- a/include/asm-mips/smtc.h
+++ /dev/null
@@ -1,69 +0,0 @@
-#ifndef _ASM_SMTC_MT_H
-#define _ASM_SMTC_MT_H
-
-/*
- * Definitions for SMTC multitasking on MIPS MT cores
- */
-
-#include <asm/mips_mt.h>
-
-/*
- * System-wide SMTC status information
- */
-
-extern unsigned int smtc_status;
-
-#define SMTC_TLB_SHARED 0x00000001
-#define SMTC_MTC_ACTIVE 0x00000002
-
-/*
- * TLB/ASID Management information
- */
-
-#define MAX_SMTC_TLBS 2
-#define MAX_SMTC_ASIDS 256
-#if NR_CPUS <= 8
-typedef char asiduse;
-#else
-#if NR_CPUS <= 16
-typedef short asiduse;
-#else
-typedef long asiduse;
-#endif
-#endif
-
-extern asiduse smtc_live_asid[MAX_SMTC_TLBS][MAX_SMTC_ASIDS];
-
-struct mm_struct;
-struct task_struct;
-
-void smtc_get_new_mmu_context(struct mm_struct *mm, unsigned long cpu);
-
-void smtc_flush_tlb_asid(unsigned long asid);
-extern int mipsmt_build_cpu_map(int startslot);
-extern void mipsmt_prepare_cpus(void);
-extern void smtc_smp_finish(void);
-extern void smtc_boot_secondary(int cpu, struct task_struct *t);
-extern void smtc_cpus_done(void);
-
-/*
- * Sharing the TLB between multiple VPEs means that the
- * "random" index selection function is not allowed to
- * select the current value of the Index register. To
- * avoid additional TLB pressure, the Index registers
- * are "parked" with an non-Valid value.
- */
-
-#define PARKED_INDEX    ((unsigned int)0x80000000)
-
-/*
- * Define low-level interrupt mask for IPIs, if necessary.
- * By default, use SW interrupt 1, which requires no external
- * hardware support, but which works only for single-core
- * MIPS MT systems.
- */
-#ifndef MIPS_CPU_IPI_IRQ
-#define MIPS_CPU_IPI_IRQ 1
-#endif
-
-#endif /*  _ASM_SMTC_MT_H */
diff --git a/include/asm-mips/smtc_ipi.h b/include/asm-mips/smtc_ipi.h
deleted file mode 100644
index 8ce517574340..000000000000
--- a/include/asm-mips/smtc_ipi.h
+++ /dev/null
@@ -1,128 +0,0 @@
-/*
- * Definitions used in MIPS MT SMTC "Interprocessor Interrupt" code.
- */
-#ifndef __ASM_SMTC_IPI_H
-#define __ASM_SMTC_IPI_H
-
-#include <linux/spinlock.h>
-
-//#define SMTC_IPI_DEBUG
-
-#ifdef SMTC_IPI_DEBUG
-#include <asm/mipsregs.h>
-#include <asm/mipsmtregs.h>
-#endif /* SMTC_IPI_DEBUG */
-
-/*
- * An IPI "message"
- */
-
-struct smtc_ipi {
-        struct smtc_ipi *flink;
-        int type;
-        void *arg;
-        int dest;
-#ifdef  SMTC_IPI_DEBUG
-        int sender;
-        long stamp;
-#endif /* SMTC_IPI_DEBUG */
-};
-
-/*
- * Defined IPI Types
- */
-
-#define LINUX_SMP_IPI 1
-#define SMTC_CLOCK_TICK 2
-#define IRQ_AFFINITY_IPI 3
-
-/*
- * A queue of IPI messages
- */
-
-struct smtc_ipi_q {
-        struct smtc_ipi *head;
-        spinlock_t lock;
-        struct smtc_ipi *tail;
-        int depth;
-};
-
-static inline void smtc_ipi_nq(struct smtc_ipi_q *q, struct smtc_ipi *p)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&q->lock, flags);
-        if (q->head == NULL)
-                q->head = q->tail = p;
-        else
-                q->tail->flink = p;
-        p->flink = NULL;
-        q->tail = p;
-        q->depth++;
-#ifdef  SMTC_IPI_DEBUG
-        p->sender = read_c0_tcbind();
-        p->stamp = read_c0_count();
-#endif /* SMTC_IPI_DEBUG */
-        spin_unlock_irqrestore(&q->lock, flags);
-}
-
-static inline struct smtc_ipi *__smtc_ipi_dq(struct smtc_ipi_q *q)
-{
-        struct smtc_ipi *p;
-
-        if (q->head == NULL)
-                p = NULL;
-        else {
-                p = q->head;
-                q->head = q->head->flink;
-                q->depth--;
-                /* Arguably unnecessary, but leaves queue cleaner */
-                if (q->head == NULL)
-                        q->tail = NULL;
-        }
-
-        return p;
-}
-
-static inline struct smtc_ipi *smtc_ipi_dq(struct smtc_ipi_q *q)
-{
-        unsigned long flags;
-        struct smtc_ipi *p;
-
-        spin_lock_irqsave(&q->lock, flags);
-        p = __smtc_ipi_dq(q);
-        spin_unlock_irqrestore(&q->lock, flags);
-
-        return p;
-}
-
-static inline void smtc_ipi_req(struct smtc_ipi_q *q, struct smtc_ipi *p)
-{
-        unsigned long flags;
-
-        spin_lock_irqsave(&q->lock, flags);
-        if (q->head == NULL) {
-                q->head = q->tail = p;
-                p->flink = NULL;
-        } else {
-                p->flink = q->head;
-                q->head = p;
-        }
-        q->depth++;
-        spin_unlock_irqrestore(&q->lock, flags);
-}
-
-static inline int smtc_ipi_qdepth(struct smtc_ipi_q *q)
-{
-        unsigned long flags;
-        int retval;
-
-        spin_lock_irqsave(&q->lock, flags);
-        retval = q->depth;
-        spin_unlock_irqrestore(&q->lock, flags);
-        return retval;
-}
-
-extern void smtc_send_ipi(int cpu, int type, unsigned int action);
-
-#endif /* __ASM_SMTC_IPI_H */
diff --git a/include/asm-mips/smtc_proc.h b/include/asm-mips/smtc_proc.h
deleted file mode 100644
index 25da651f1f5f..000000000000
--- a/include/asm-mips/smtc_proc.h
+++ /dev/null
@@ -1,23 +0,0 @@
-/*
- * Definitions for SMTC /proc entries
- * Copyright(C) 2005 MIPS Technologies Inc.
- */
-#ifndef __ASM_SMTC_PROC_H
-#define __ASM_SMTC_PROC_H
-
-/*
- * per-"CPU" statistics
- */
-
-struct smtc_cpu_proc {
-        unsigned long timerints;
-        unsigned long selfipis;
-};
-
-extern struct smtc_cpu_proc smtc_cpu_stats[NR_CPUS];
-
-/* Count of number of recoveries of "stolen" FPU access rights on 34K */
-
-extern atomic_t smtc_fpu_recoveries;
-
-#endif /* __ASM_SMTC_PROC_H */
diff --git a/include/asm-mips/smvp.h b/include/asm-mips/smvp.h
deleted file mode 100644
index 0d0e80a39e8a..000000000000
--- a/include/asm-mips/smvp.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef _ASM_SMVP_H
-#define _ASM_SMVP_H
-
-/*
- * Definitions for SMVP multitasking on MIPS MT cores
- */
-struct task_struct;
-
-extern void smvp_smp_setup(void);
-extern void smvp_smp_finish(void);
-extern void smvp_boot_secondary(int cpu, struct task_struct *t);
-extern void smvp_init_secondary(void);
-extern void smvp_smp_finish(void);
-extern void smvp_cpus_done(void);
-extern void smvp_prepare_cpus(unsigned int max_cpus);
-
-/* This is platform specific */
-extern void smvp_send_ipi(int cpu, unsigned int action);
-#endif /*  _ASM_SMVP_H */
diff --git a/include/asm-mips/sn/addrs.h b/include/asm-mips/sn/addrs.h
deleted file mode 100644
index fec9bdd34913..000000000000
--- a/include/asm-mips/sn/addrs.h
+++ /dev/null
@@ -1,430 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 1999, 2000 by Ralf Baechle
- */
-#ifndef _ASM_SN_ADDRS_H
-#define _ASM_SN_ADDRS_H
-
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif /* !__ASSEMBLY__ */
-
-#include <asm/addrspace.h>
-#include <asm/sn/kldir.h>
-
-#if defined(CONFIG_SGI_IP27)
-#include <asm/sn/sn0/addrs.h>
-#elif defined(CONFIG_SGI_IP35)
-#include <asm/sn/sn1/addrs.h>
-#endif
-
-
-#ifndef __ASSEMBLY__
-
-#define PS_UINT_CAST            (unsigned long)
-#define UINT64_CAST             (unsigned long)
-
-#define HUBREG_CAST             (volatile hubreg_t *)
-
-#else /* __ASSEMBLY__ */
-
-#define PS_UINT_CAST
-#define UINT64_CAST
-#define HUBREG_CAST
-
-#endif /* __ASSEMBLY__ */
-
-
-#define NASID_GET_META(_n)      ((_n) >> NASID_LOCAL_BITS)
-#ifdef CONFIG_SGI_IP27
-#define NASID_GET_LOCAL(_n)     ((_n) & 0xf)
-#endif
-#define NASID_MAKE(_m, _l)      (((_m) << NASID_LOCAL_BITS) | (_l))
-
-#define NODE_ADDRSPACE_MASK     (NODE_ADDRSPACE_SIZE - 1)
-#define TO_NODE_ADDRSPACE(_pa)  (UINT64_CAST (_pa) & NODE_ADDRSPACE_MASK)
-
-#define CHANGE_ADDR_NASID(_pa, _nasid)  \
-                ((UINT64_CAST(_pa) & ~NASID_MASK) | \
-                 (UINT64_CAST(_nasid) <<  NASID_SHFT))
-
-
-/*
- * The following macros are used to index to the beginning of a specific
- * node's address space.
- */
-
-#define NODE_OFFSET(_n)         (UINT64_CAST (_n) << NODE_SIZE_BITS)
-
-#define NODE_CAC_BASE(_n)       (CAC_BASE   + NODE_OFFSET(_n))
-#define NODE_HSPEC_BASE(_n)     (HSPEC_BASE + NODE_OFFSET(_n))
-#define NODE_IO_BASE(_n)        (IO_BASE    + NODE_OFFSET(_n))
-#define NODE_MSPEC_BASE(_n)     (MSPEC_BASE + NODE_OFFSET(_n))
-#define NODE_UNCAC_BASE(_n)     (UNCAC_BASE + NODE_OFFSET(_n))
-
-#define TO_NODE(_n, _x)         (NODE_OFFSET(_n)     | ((_x)               ))
-#define TO_NODE_CAC(_n, _x)     (NODE_CAC_BASE(_n)   | ((_x) & TO_PHYS_MASK))
-#define TO_NODE_UNCAC(_n, _x)   (NODE_UNCAC_BASE(_n) | ((_x) & TO_PHYS_MASK))
-#define TO_NODE_MSPEC(_n, _x)   (NODE_MSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
-#define TO_NODE_HSPEC(_n, _x)   (NODE_HSPEC_BASE(_n) | ((_x) & TO_PHYS_MASK))
-
-
-#define RAW_NODE_SWIN_BASE(nasid, widget)                               \
-        (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
-
-#define WIDGETID_GET(addr)      ((unsigned char)((addr >> SWIN_SIZE_BITS) & 0xff))
-
-/*
- * The following definitions pertain to the IO special address
- * space.  They define the location of the big and little windows
- * of any given node.
- */
-
-#define SWIN_SIZE_BITS          24
-#define SWIN_SIZE               (UINT64_CAST 1 << 24)
-#define SWIN_SIZEMASK           (SWIN_SIZE - 1)
-#define SWIN_WIDGET_MASK        0xF
-
-/*
- * Convert smallwindow address to xtalk address.
- *
- * 'addr' can be physical or virtual address, but will be converted
- * to Xtalk address in the range 0 -> SWINZ_SIZEMASK
- */
-#define SWIN_WIDGETADDR(addr)   ((addr) & SWIN_SIZEMASK)
-#define SWIN_WIDGETNUM(addr)    (((addr)  >> SWIN_SIZE_BITS) & SWIN_WIDGET_MASK)
-/*
- * Verify if addr belongs to small window address on node with "nasid"
- *
- *
- * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
- * address
- *
- *
- */
-#define NODE_SWIN_ADDR(nasid, addr)     \
-                (((addr) >= NODE_SWIN_BASE(nasid, 0))  && \
-                 ((addr) <  (NODE_SWIN_BASE(nasid, HUB_NUM_WIDGET) + SWIN_SIZE)\
-                 ))
-
-/*
- * The following define the major position-independent aliases used
- * in SN.
- *      UALIAS -- 256MB in size, reads in the UALIAS result in
- *                      uncached references to the memory of the reader's node.
- *      CPU_UALIAS -- 128kb in size, the bottom part of UALIAS is flipped
- *                      depending on which CPU does the access to provide
- *                      all CPUs with unique uncached memory at low addresses.
- *      LBOOT  -- 256MB in size, reads in the LBOOT area result in
- *                      uncached references to the local hub's boot prom and
- *                      other directory-bus connected devices.
- *      IALIAS -- 8MB in size, reads in the IALIAS result in uncached
- *                      references to the local hub's registers.
- */
-
-#define UALIAS_BASE             HSPEC_BASE
-#define UALIAS_SIZE             0x10000000      /* 256 Megabytes */
-#define UALIAS_LIMIT            (UALIAS_BASE + UALIAS_SIZE)
-
-/*
- * The bottom of ualias space is flipped depending on whether you're
- * processor 0 or 1 within a node.
- */
-#ifdef CONFIG_SGI_IP27
-#define UALIAS_FLIP_BASE        UALIAS_BASE
-#define UALIAS_FLIP_SIZE        0x20000
-#define UALIAS_FLIP_BIT         0x10000
-#define UALIAS_FLIP_ADDR(_x)    (cputoslice(smp_processor_id()) ? \
-                                 (_x) ^ UALIAS_FLIP_BIT : (_x))
-
-#define LBOOT_BASE              (HSPEC_BASE + 0x10000000)
-#define LBOOT_SIZE              0x10000000
-#define LBOOT_LIMIT             (LBOOT_BASE + LBOOT_SIZE)
-#define LBOOT_STRIDE            0               /* IP27 has only one CPU PROM */
-
-#endif
-
-#define HUB_REGISTER_WIDGET     1
-#define IALIAS_BASE             NODE_SWIN_BASE(0, HUB_REGISTER_WIDGET)
-#define IALIAS_SIZE             0x800000        /* 8 Megabytes */
-#define IS_IALIAS(_a)           (((_a) >= IALIAS_BASE) &&               \
-                                 ((_a) < (IALIAS_BASE + IALIAS_SIZE)))
-
-/*
- * Macro for referring to Hub's RBOOT space
- */
-
-#ifdef CONFIG_SGI_IP27
-#define RBOOT_SIZE              0x10000000      /* 256 Megabytes */
-#define NODE_RBOOT_BASE(_n)     (NODE_HSPEC_BASE(_n) + 0x30000000)
-#define NODE_RBOOT_LIMIT(_n)    (NODE_RBOOT_BASE(_n) + RBOOT_SIZE)
-
-#endif
-
-/*
- * Macros for referring the Hub's back door space
- *
- *   These macros correctly process addresses in any node's space.
- *   WARNING: They won't work in assembler.
- *
- *   BDDIR_ENTRY_LO returns the address of the low double-word of the dir
- *                  entry corresponding to a physical (Cac or Uncac) address.
- *   BDDIR_ENTRY_HI returns the address of the high double-word of the entry.
- *   BDPRT_ENTRY    returns the address of the double-word protection entry
- *                  corresponding to the page containing the physical address.
- *   BDPRT_ENTRY_S  Stores the value into the protection entry.
- *   BDPRT_ENTRY_L  Load the value from the protection entry.
- *   BDECC_ENTRY    returns the address of the ECC byte corresponding to a
- *                  double-word at a specified physical address.
- *   BDECC_ENTRY_H  returns the address of the two ECC bytes corresponding to a
- *                  quad-word at a specified physical address.
- */
-#define NODE_BDOOR_BASE(_n)     (NODE_HSPEC_BASE(_n) + (NODE_ADDRSPACE_SIZE/2))
-
-#define NODE_BDECC_BASE(_n)     (NODE_BDOOR_BASE(_n))
-#define NODE_BDDIR_BASE(_n)     (NODE_BDOOR_BASE(_n) + (NODE_ADDRSPACE_SIZE/4))
-#ifdef CONFIG_SGI_IP27
-#define BDDIR_ENTRY_LO(_pa)     ((HSPEC_BASE +                                \
-                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
-                                  0x200)                                    | \
-                                 UINT64_CAST(_pa)        & NASID_MASK       | \
-                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
-                                 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
-
-#define BDDIR_ENTRY_HI(_pa)     ((HSPEC_BASE +                                \
-                                  NODE_ADDRSPACE_SIZE * 3 / 4 +               \
-                                  0x208)                                    | \
-                                 UINT64_CAST(_pa)        & NASID_MASK       | \
-                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
-                                 UINT64_CAST(_pa) >> 3 & 0x1f << 4)
-
-#define BDPRT_ENTRY(_pa, _rgn)  ((HSPEC_BASE +                                \
-                                  NODE_ADDRSPACE_SIZE * 3 / 4)              | \
-                                 UINT64_CAST(_pa)        & NASID_MASK       | \
-                                 UINT64_CAST(_pa) >> 2 & BDDIR_UPPER_MASK  | \
-                                 (_rgn) << 3)
-#define BDPRT_ENTRY_ADDR(_pa, _rgn) (BDPRT_ENTRY((_pa), (_rgn)))
-#define BDPRT_ENTRY_S(_pa, _rgn, _val) (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn))=(_val))
-#define BDPRT_ENTRY_L(_pa, _rgn)        (*(__psunsigned_t *)BDPRT_ENTRY((_pa), (_rgn)))
-
-#define BDECC_ENTRY(_pa)        ((HSPEC_BASE +                                \
-                                  NODE_ADDRSPACE_SIZE / 2)                  | \
-                                 UINT64_CAST(_pa)        & NASID_MASK       | \
-                                 UINT64_CAST(_pa) >> 2 & BDECC_UPPER_MASK  | \
-                                 UINT64_CAST(_pa) >> 3 & 3)
-
-/*
- * Macro to convert a back door directory or protection address into the
- *   raw physical address of the associated cache line or protection page.
- */
-#define BDADDR_IS_DIR(_ba)      ((UINT64_CAST  (_ba) & 0x200) != 0)
-#define BDADDR_IS_PRT(_ba)      ((UINT64_CAST  (_ba) & 0x200) == 0)
-
-#define BDDIR_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK            | \
-                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2  | \
-                                 (UINT64_CAST(_ba) & 0x1f << 4) << 3)
-
-#define BDPRT_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
-                                 (UINT64_CAST(_ba) & BDDIR_UPPER_MASK)<<2)
-
-#define BDECC_TO_MEM(_ba)       (UINT64_CAST (_ba) & NASID_MASK     | \
-                                 (UINT64_CAST(_ba) & BDECC_UPPER_MASK)<<2  | \
-                                 (UINT64_CAST(_ba) & 3) << 3)
-#endif /* CONFIG_SGI_IP27 */
-
-
-/*
- * The following macros produce the correct base virtual address for
- * the hub registers.  The LOCAL_HUB_* macros produce the appropriate
- * address for the local registers.  The REMOTE_HUB_* macro produce
- * the address for the specified hub's registers.  The intent is
- * that the appropriate PI, MD, NI, or II register would be substituted
- * for _x.
- */
-
-/*
- * WARNING:
- *      When certain Hub chip workaround are defined, it's not sufficient
- *      to dereference the *_HUB_ADDR() macros.  You should instead use
- *      HUB_L() and HUB_S() if you must deal with pointers to hub registers.
- *      Otherwise, the recommended approach is to use *_HUB_L() and *_HUB_S().
- *      They're always safe.
- */
-#define LOCAL_HUB_ADDR(_x)      (HUBREG_CAST (IALIAS_BASE + (_x)))
-#define REMOTE_HUB_ADDR(_n, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
-                                              0x800000 + (_x)))
-#ifdef CONFIG_SGI_IP27
-#define REMOTE_HUB_PI_ADDR(_n, _sn, _x) (HUBREG_CAST (NODE_SWIN_BASE(_n, 1) +   \
-                                              0x800000 + (_x)))
-#endif /* CONFIG_SGI_IP27 */
-
-#ifndef __ASSEMBLY__
-
-#define HUB_L(_a)                       *(_a)
-#define HUB_S(_a, _d)                   *(_a) = (_d)
-
-#define LOCAL_HUB_L(_r)                 HUB_L(LOCAL_HUB_ADDR(_r))
-#define LOCAL_HUB_S(_r, _d)             HUB_S(LOCAL_HUB_ADDR(_r), (_d))
-#define REMOTE_HUB_L(_n, _r)            HUB_L(REMOTE_HUB_ADDR((_n), (_r)))
-#define REMOTE_HUB_S(_n, _r, _d)        HUB_S(REMOTE_HUB_ADDR((_n), (_r)), (_d))
-#define REMOTE_HUB_PI_L(_n, _sn, _r)    HUB_L(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)))
-#define REMOTE_HUB_PI_S(_n, _sn, _r, _d) HUB_S(REMOTE_HUB_PI_ADDR((_n), (_sn), (_r)), (_d))
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * The following macros are used to get to a hub/bridge register, given
- * the base of the register space.
- */
-#define HUB_REG_PTR(_base, _off)        \
-        (HUBREG_CAST((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
-
-#define HUB_REG_PTR_L(_base, _off)      \
-        HUB_L(HUB_REG_PTR((_base), (_off)))
-
-#define HUB_REG_PTR_S(_base, _off, _data)       \
-        HUB_S(HUB_REG_PTR((_base), (_off)), (_data))
-
-/*
- * Software structure locations -- permanently fixed
- *    See diagram in kldir.h
- */
-
-#define PHYS_RAMBASE            0x0
-#define K0_RAMBASE              PHYS_TO_K0(PHYS_RAMBASE)
-
-#define EX_HANDLER_OFFSET(slice) ((slice) << 16)
-#define EX_HANDLER_ADDR(nasid, slice)                                   \
-        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_HANDLER_OFFSET(slice))
-#define EX_HANDLER_SIZE         0x0400
-
-#define EX_FRAME_OFFSET(slice)  ((slice) << 16 | 0x400)
-#define EX_FRAME_ADDR(nasid, slice)                                     \
-        PHYS_TO_K0(NODE_OFFSET(nasid) | EX_FRAME_OFFSET(slice))
-#define EX_FRAME_SIZE           0x0c00
-
-#define ARCS_SPB_OFFSET         0x1000
-#define ARCS_SPB_ADDR(nasid)                                            \
-        PHYS_TO_K0(NODE_OFFSET(nasid) | ARCS_SPB_OFFSET)
-#define ARCS_SPB_SIZE           0x0400
-
-#define KLDIR_OFFSET            0x2000
-#define KLDIR_ADDR(nasid)                                               \
-        TO_NODE_UNCAC((nasid), KLDIR_OFFSET)
-#define KLDIR_SIZE              0x0400
-
-
-/*
- * Software structure locations -- indirected through KLDIR
- *    See diagram in kldir.h
- *
- * Important:   All low memory structures must only be accessed
- *              uncached, except for the symmon stacks.
- */
-
-#define KLI_LAUNCH              0               /* Dir. entries */
-#define KLI_KLCONFIG            1
-#define KLI_NMI                 2
-#define KLI_GDA                 3
-#define KLI_FREEMEM             4
-#define KLI_SYMMON_STK          5
-#define KLI_PI_ERROR            6
-#define KLI_KERN_VARS           7
-#define KLI_KERN_XP             8
-#define KLI_KERN_PARTID         9
-
-#ifndef __ASSEMBLY__
-
-#define KLD_BASE(nasid)         ((kldir_ent_t *) KLDIR_ADDR(nasid))
-#define KLD_LAUNCH(nasid)       (KLD_BASE(nasid) + KLI_LAUNCH)
-#define KLD_NMI(nasid)          (KLD_BASE(nasid) + KLI_NMI)
-#define KLD_KLCONFIG(nasid)     (KLD_BASE(nasid) + KLI_KLCONFIG)
-#define KLD_PI_ERROR(nasid)     (KLD_BASE(nasid) + KLI_PI_ERROR)
-#define KLD_GDA(nasid)          (KLD_BASE(nasid) + KLI_GDA)
-#define KLD_SYMMON_STK(nasid)   (KLD_BASE(nasid) + KLI_SYMMON_STK)
-#define KLD_FREEMEM(nasid)      (KLD_BASE(nasid) + KLI_FREEMEM)
-#define KLD_KERN_VARS(nasid)    (KLD_BASE(nasid) + KLI_KERN_VARS)
-#define KLD_KERN_XP(nasid)      (KLD_BASE(nasid) + KLI_KERN_XP)
-#define KLD_KERN_PARTID(nasid)  (KLD_BASE(nasid) + KLI_KERN_PARTID)
-
-#define LAUNCH_OFFSET(nasid, slice)                                     \
-        (KLD_LAUNCH(nasid)->offset +                                    \
-         KLD_LAUNCH(nasid)->stride * (slice))
-#define LAUNCH_ADDR(nasid, slice)                                       \
-        TO_NODE_UNCAC((nasid), LAUNCH_OFFSET(nasid, slice))
-#define LAUNCH_SIZE(nasid)      KLD_LAUNCH(nasid)->size
-
-#define NMI_OFFSET(nasid, slice)                                        \
-        (KLD_NMI(nasid)->offset +                                       \
-         KLD_NMI(nasid)->stride * (slice))
-#define NMI_ADDR(nasid, slice)                                          \
-        TO_NODE_UNCAC((nasid), NMI_OFFSET(nasid, slice))
-#define NMI_SIZE(nasid) KLD_NMI(nasid)->size
-
-#define KLCONFIG_OFFSET(nasid)  KLD_KLCONFIG(nasid)->offset
-#define KLCONFIG_ADDR(nasid)                                            \
-        TO_NODE_UNCAC((nasid), KLCONFIG_OFFSET(nasid))
-#define KLCONFIG_SIZE(nasid)    KLD_KLCONFIG(nasid)->size
-
-#define GDA_ADDR(nasid)         KLD_GDA(nasid)->pointer
-#define GDA_SIZE(nasid)         KLD_GDA(nasid)->size
-
-#define SYMMON_STK_OFFSET(nasid, slice)                                 \
-        (KLD_SYMMON_STK(nasid)->offset +                                \
-         KLD_SYMMON_STK(nasid)->stride * (slice))
-#define SYMMON_STK_STRIDE(nasid)        KLD_SYMMON_STK(nasid)->stride
-
-#define SYMMON_STK_ADDR(nasid, slice)                                   \
-        TO_NODE_CAC((nasid), SYMMON_STK_OFFSET(nasid, slice))
-
-#define SYMMON_STK_SIZE(nasid)  KLD_SYMMON_STK(nasid)->stride
-
-#define SYMMON_STK_END(nasid)   (SYMMON_STK_ADDR(nasid, 0) + KLD_SYMMON_STK(nasid)->size)
-
-/* loading symmon 4k below UNIX. the arcs loader needs the topaddr for a
- * relocatable program
- */
-#define UNIX_DEBUG_LOADADDR     0x300000
-#define SYMMON_LOADADDR(nasid)                                          \
-        TO_NODE(nasid, PHYS_TO_K0(UNIX_DEBUG_LOADADDR - 0x1000))
-
-#define FREEMEM_OFFSET(nasid)   KLD_FREEMEM(nasid)->offset
-#define FREEMEM_ADDR(nasid)     SYMMON_STK_END(nasid)
-/*
- * XXX
- * Fix this. FREEMEM_ADDR should be aware of if symmon is loaded.
- * Also, it should take into account what prom thinks to be a safe
- * address
-        PHYS_TO_K0(NODE_OFFSET(nasid) + FREEMEM_OFFSET(nasid))
- */
-#define FREEMEM_SIZE(nasid)     KLD_FREEMEM(nasid)->size
-
-#define PI_ERROR_OFFSET(nasid)  KLD_PI_ERROR(nasid)->offset
-#define PI_ERROR_ADDR(nasid)                                            \
-        TO_NODE_UNCAC((nasid), PI_ERROR_OFFSET(nasid))
-#define PI_ERROR_SIZE(nasid)    KLD_PI_ERROR(nasid)->size
-
-#define NODE_OFFSET_TO_K0(_nasid, _off)                                 \
-        PHYS_TO_K0((NODE_OFFSET(_nasid) + (_off)) | CAC_BASE)
-#define NODE_OFFSET_TO_K1(_nasid, _off)                                 \
-        TO_UNCAC((NODE_OFFSET(_nasid) + (_off)) | UNCAC_BASE)
-#define K0_TO_NODE_OFFSET(_k0addr)                                      \
-        ((__psunsigned_t)(_k0addr) & NODE_ADDRSPACE_MASK)
-
-#define KERN_VARS_ADDR(nasid)   KLD_KERN_VARS(nasid)->pointer
-#define KERN_VARS_SIZE(nasid)   KLD_KERN_VARS(nasid)->size
-
-#define KERN_XP_ADDR(nasid)     KLD_KERN_XP(nasid)->pointer
-#define KERN_XP_SIZE(nasid)     KLD_KERN_XP(nasid)->size
-
-#define GPDA_ADDR(nasid)        TO_NODE_CAC(nasid, GPDA_OFFSET)
-
-#endif /* !__ASSEMBLY__ */
-
-
-#endif /* _ASM_SN_ADDRS_H */
diff --git a/include/asm-mips/sn/agent.h b/include/asm-mips/sn/agent.h
deleted file mode 100644
index ac4ea85c3a5c..000000000000
--- a/include/asm-mips/sn/agent.h
+++ /dev/null
@@ -1,46 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * This file has definitions for the hub and snac interfaces.
- *
- * Copyright (C) 1992 - 1997, 1999, 2000 Silcon Graphics, Inc.
- * Copyright (C) 1999, 2000 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_SGI_SN_AGENT_H
-#define _ASM_SGI_SN_AGENT_H
-
-#include <linux/topology.h>
-#include <asm/sn/addrs.h>
-#include <asm/sn/arch.h>
-
-#if defined(CONFIG_SGI_IP27)
-#include <asm/sn/sn0/hub.h>
-#elif defined(CONFIG_SGI_IP35)
-#include <asm/sn/sn1/hub.h>
-#endif  /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
-
-/*
- * NIC register macros
- */
-
-#if defined(CONFIG_SGI_IP27)
-#define HUB_NIC_ADDR(_cpuid)                                               \
-        REMOTE_HUB_ADDR(COMPACT_TO_NASID_NODEID(cpu_to_node(_cpuid)),       \
-                MD_MLAN_CTL)
-#endif
-
-#define SET_HUB_NIC(_my_cpuid, _val)                                       \
-        (HUB_S(HUB_NIC_ADDR(_my_cpuid), (_val)))
-
-#define SET_MY_HUB_NIC(_v)                                                 \
-        SET_HUB_NIC(cpuid(), (_v))
-
-#define GET_HUB_NIC(_my_cpuid)                                             \
-        (HUB_L(HUB_NIC_ADDR(_my_cpuid)))
-
-#define GET_MY_HUB_NIC()                                                   \
-        GET_HUB_NIC(cpuid())
-
-#endif /* _ASM_SGI_SN_AGENT_H */
diff --git a/include/asm-mips/sn/arch.h b/include/asm-mips/sn/arch.h
deleted file mode 100644
index bd75945e10ff..000000000000
--- a/include/asm-mips/sn/arch.h
+++ /dev/null
@@ -1,64 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI specific setup.
- *
- * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_SN_ARCH_H
-#define _ASM_SN_ARCH_H
-
-#include <linux/types.h>
-#include <asm/sn/types.h>
-#ifdef CONFIG_SGI_IP27
-#include <asm/sn/sn0/arch.h>
-#endif
-
-typedef u64     hubreg_t;
-
-#define cputonasid(cpu)         (sn_cpu_info[(cpu)].p_nasid)
-#define cputoslice(cpu)         (sn_cpu_info[(cpu)].p_slice)
-#define makespnum(_nasid, _slice)                                       \
-                (((_nasid) << CPUS_PER_NODE_SHFT) | (_slice))
-
-#define INVALID_NASID           (nasid_t)-1
-#define INVALID_CNODEID         (cnodeid_t)-1
-#define INVALID_PNODEID         (pnodeid_t)-1
-#define INVALID_MODULE          (moduleid_t)-1
-#define INVALID_PARTID          (partid_t)-1
-
-extern nasid_t get_nasid(void);
-extern cnodeid_t get_cpu_cnode(cpuid_t);
-extern int get_cpu_slice(cpuid_t);
-
-/*
- * NO ONE should access these arrays directly.  The only reason we refer to
- * them here is to avoid the procedure call that would be required in the
- * macros below.  (Really want private data members here :-)
- */
-extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
-extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
-
-/*
- * These macros are used by various parts of the kernel to convert
- * between the three different kinds of node numbering.   At least some
- * of them may change to procedure calls in the future, but the macros
- * will continue to work.  Don't use the arrays above directly.
- */
-
-#define NASID_TO_REGION(nnode)          \
-    ((nnode) >> \
-     (is_fine_dirmode() ? NASID_TO_FINEREG_SHFT : NASID_TO_COARSEREG_SHFT))
-
-extern cnodeid_t nasid_to_compact_node[MAX_NASIDS];
-extern nasid_t compact_to_nasid_node[MAX_COMPACT_NODES];
-extern cnodeid_t cpuid_to_compact_node[MAXCPUS];
-
-#define NASID_TO_COMPACT_NODEID(nnode)  (nasid_to_compact_node[nnode])
-#define COMPACT_TO_NASID_NODEID(cnode)  (compact_to_nasid_node[cnode])
-#define CPUID_TO_COMPACT_NODEID(cpu)    (cpuid_to_compact_node[(cpu)])
-
-#endif /* _ASM_SN_ARCH_H */
diff --git a/include/asm-mips/sn/fru.h b/include/asm-mips/sn/fru.h
deleted file mode 100644
index b3e3606723b7..000000000000
--- a/include/asm-mips/sn/fru.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/sn0_fru.h>
- *
- * Copyright (C) 1992 - 1997, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999, 2006 Ralf Baechle (ralf@linux-mips)
- */
-#ifndef __ASM_SN_FRU_H
-#define __ASM_SN_FRU_H
-
-#define MAX_DIMMS                       8        /* max # of dimm banks */
-#define MAX_PCIDEV                      8        /* max # of pci devices on a pci bus */
-
-typedef unsigned char confidence_t;
-
-typedef struct kf_mem_s {
-        confidence_t km_confidence; /* confidence level that the memory is bad
-                                     * is this necessary ?
-                                     */
-        confidence_t km_dimm[MAX_DIMMS];
-                                    /* confidence level that dimm[i] is bad
-                                     *I think this is the right number
-                                     */
-
-} kf_mem_t;
-
-typedef struct kf_cpu_s {
-        confidence_t    kc_confidence; /* confidence level that cpu is bad */
-        confidence_t    kc_icache; /* confidence level that instr. cache is bad */
-        confidence_t    kc_dcache; /* confidence level that data   cache is bad */
-        confidence_t    kc_scache; /* confidence level that sec.   cache is bad */
-        confidence_t    kc_sysbus; /* confidence level that sysad/cmd/state bus is bad */
-} kf_cpu_t;
-
-typedef struct kf_pci_bus_s {
-        confidence_t    kpb_belief;     /* confidence level  that the  pci bus is bad */
-        confidence_t    kpb_pcidev_belief[MAX_PCIDEV];
-                                        /* confidence level that the pci dev is bad */
-} kf_pci_bus_t;
-
-#endif /* __ASM_SN_FRU_H */
diff --git a/include/asm-mips/sn/gda.h b/include/asm-mips/sn/gda.h
deleted file mode 100644
index 9cb6ff770915..000000000000
--- a/include/asm-mips/sn/gda.h
+++ /dev/null
@@ -1,107 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/gda.h>.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- *
- * gda.h -- Contains the data structure for the global data area,
- *      The GDA contains information communicated between the
- *      PROM, SYMMON, and the kernel.
- */
-#ifndef _ASM_SN_GDA_H
-#define _ASM_SN_GDA_H
-
-#include <asm/sn/addrs.h>
-
-#define GDA_MAGIC       0x58464552
-
-/*
- * GDA Version History
- *
- * Version #    | Change
- * -------------+-------------------------------------------------------
- *      1       | Initial SN0 version
- *      2       | Prom sets g_partid field to the partition number. 0 IS
- *              | a valid partition #.
- */
-
-#define GDA_VERSION     2       /* Current GDA version # */
-
-#define G_MAGICOFF      0
-#define G_VERSIONOFF    4
-#define G_PROMOPOFF     6
-#define G_MASTEROFF     8
-#define G_VDSOFF        12
-#define G_HKDNORMOFF    16
-#define G_HKDUTLBOFF    24
-#define G_HKDXUTLBOFF   32
-#define G_PARTIDOFF     40
-#define G_TABLEOFF      128
-
-#ifndef __ASSEMBLY__
-
-typedef struct gda {
-        u32     g_magic;        /* GDA magic number */
-        u16     g_version;      /* Version of this structure */
-        u16     g_masterid;     /* The NASID:CPUNUM of the master cpu */
-        u32     g_promop;       /* Passes requests from the kernel to prom */
-        u32     g_vds;          /* Store the virtual dipswitches here */
-        void    **g_hooked_norm;/* ptr to pda loc for norm hndlr */
-        void    **g_hooked_utlb;/* ptr to pda loc for utlb hndlr */
-        void    **g_hooked_xtlb;/* ptr to pda loc for xtlb hndlr */
-        int     g_partid;       /* partition id */
-        int     g_symmax;       /* Max symbols in name table. */
-        void    *g_dbstab;      /* Address of idbg symbol table */
-        char    *g_nametab;     /* Address of idbg name table */
-        void    *g_ktext_repmask;
-                                /* Pointer to a mask of nodes with copies
-                                 * of the kernel. */
-        char    g_padding[56];  /* pad out to 128 bytes */
-        nasid_t g_nasidtable[MAX_COMPACT_NODES]; /* NASID of each node,
-                                                  * indexed by cnodeid.
-                                                  */
-} gda_t;
-
-#define GDA ((gda_t*) GDA_ADDR(get_nasid()))
-
-#endif /* !__ASSEMBLY__ */
-/*
- * Define:      PART_GDA_VERSION
- * Purpose:     Define the minimum version of the GDA required, lower
- *              revisions assume GDA is NOT set up, and read partition
- *              information from the board info.
- */
-#define PART_GDA_VERSION        2
-
-/*
- * The following requests can be sent to the PROM during startup.
- */
-
-#define PROMOP_MAGIC            0x0ead0000
-#define PROMOP_MAGIC_MASK       0x0fff0000
-
-#define PROMOP_BIST_SHIFT       11
-#define PROMOP_BIST_MASK        (0x3 << 11)
-
-#define PROMOP_REG              PI_ERR_STACK_ADDR_A
-
-#define PROMOP_INVALID          (PROMOP_MAGIC | 0x00)
-#define PROMOP_HALT             (PROMOP_MAGIC | 0x10)
-#define PROMOP_POWERDOWN        (PROMOP_MAGIC | 0x20)
-#define PROMOP_RESTART          (PROMOP_MAGIC | 0x30)
-#define PROMOP_REBOOT           (PROMOP_MAGIC | 0x40)
-#define PROMOP_IMODE            (PROMOP_MAGIC | 0x50)
-
-#define PROMOP_CMD_MASK         0x00f0
-#define PROMOP_OPTIONS_MASK     0xfff0
-
-#define PROMOP_SKIP_DIAGS       0x0100          /* don't bother running diags */
-#define PROMOP_SKIP_MEMINIT     0x0200          /* don't bother initing memory */
-#define PROMOP_SKIP_DEVINIT     0x0400          /* don't bother initing devices */
-#define PROMOP_BIST1            0x0800          /* keep track of which BIST ran */
-#define PROMOP_BIST2            0x1000          /* keep track of which BIST ran */
-
-#endif /* _ASM_SN_GDA_H */
diff --git a/include/asm-mips/sn/hub.h b/include/asm-mips/sn/hub.h
deleted file mode 100644
index 1992d9254a08..000000000000
--- a/include/asm-mips/sn/hub.h
+++ /dev/null
@@ -1,16 +0,0 @@
-#ifndef __ASM_SN_HUB_H
-#define __ASM_SN_HUB_H
-
-#include <linux/types.h>
-#include <linux/cpumask.h>
-#include <asm/sn/types.h>
-#include <asm/sn/io.h>
-#include <asm/sn/klkernvars.h>
-#include <asm/xtalk/xtalk.h>
-
-/* ip27-hubio.c */
-extern unsigned long hub_pio_map(cnodeid_t cnode, xwidgetnum_t widget,
-                          unsigned long xtalk_addr, size_t size);
-extern void hub_pio_init(cnodeid_t cnode);
-
-#endif /* __ASM_SN_HUB_H */
diff --git a/include/asm-mips/sn/intr.h b/include/asm-mips/sn/intr.h
deleted file mode 100644
index 6718b644b970..000000000000
--- a/include/asm-mips/sn/intr.h
+++ /dev/null
@@ -1,129 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
- */
-#ifndef __ASM_SN_INTR_H
-#define __ASM_SN_INTR_H
-
-/* Number of interrupt levels associated with each interrupt register. */
-#define N_INTPEND_BITS          64
-
-#define INT_PEND0_BASELVL       0
-#define INT_PEND1_BASELVL       64
-
-#define N_INTPENDJUNK_BITS      8
-#define INTPENDJUNK_CLRBIT      0x80
-
-/*
- * Macros to manipulate the interrupt register on the calling hub chip.
- */
-
-#define LOCAL_HUB_SEND_INTR(level)                              \
-        LOCAL_HUB_S(PI_INT_PEND_MOD, (0x100 | (level)))
-#define REMOTE_HUB_SEND_INTR(hub, level)                        \
-        REMOTE_HUB_S((hub), PI_INT_PEND_MOD, (0x100 | (level)))
-
-/*
- * When clearing the interrupt, make sure this clear does make it
- * to the hub. Otherwise we could end up losing interrupts.
- * We do an uncached load of the int_pend0 register to ensure this.
- */
-
-#define LOCAL_HUB_CLR_INTR(level)                               \
-do {                                                            \
-        LOCAL_HUB_S(PI_INT_PEND_MOD, (level));                  \
-        LOCAL_HUB_L(PI_INT_PEND0);                              \
-} while (0);
-
-#define REMOTE_HUB_CLR_INTR(hub, level)                         \
-do {                                                            \
-        nasid_t  __hub = (hub);                                 \
-                                                                \
-        REMOTE_HUB_S(__hub, PI_INT_PEND_MOD, (level));          \
-        REMOTE_HUB_L(__hub, PI_INT_PEND0);                      \
-} while (0);
-
-/*
- * Hard-coded interrupt levels:
- */
-
-/*
- *      L0 = SW1
- *      L1 = SW2
- *      L2 = INT_PEND0
- *      L3 = INT_PEND1
- *      L4 = RTC
- *      L5 = Profiling Timer
- *      L6 = Hub Errors
- *      L7 = Count/Compare (T5 counters)
- */
-
-
-/*
- * INT_PEND0 hard-coded bits.
- */
-
-/*
- * INT_PEND0 bits determined by hardware:
- */
-#define RESERVED_INTR            0      /* What is this bit? */
-#define GFX_INTR_A               1
-#define GFX_INTR_B               2
-#define PG_MIG_INTR              3
-#define UART_INTR                4
-#define CC_PEND_A                5
-#define CC_PEND_B                6
-
-/*
- * INT_PEND0 used by the kernel for itself ...
- */
-#define CPU_RESCHED_A_IRQ        7
-#define CPU_RESCHED_B_IRQ        8
-#define CPU_CALL_A_IRQ           9
-#define CPU_CALL_B_IRQ          10
-#define MSC_MESG_INTR           11
-#define BASE_PCI_IRQ            12
-
-/*
- * INT_PEND0 again, bits determined by hardware / hardcoded:
- */
-#define SDISK_INTR              63      /* SABLE name */
-#define IP_PEND0_6_63           63      /* What is this bit? */
-
-/*
- * INT_PEND1 hard-coded bits:
- */
-#define NI_BRDCAST_ERR_A        39
-#define NI_BRDCAST_ERR_B        40
-
-#define LLP_PFAIL_INTR_A        41      /* see ml/SN/SN0/sysctlr.c */
-#define LLP_PFAIL_INTR_B        42
-
-#define TLB_INTR_A              43      /* used for tlb flush random */
-#define TLB_INTR_B              44
-
-#define IP27_INTR_0             45      /* Reserved for PROM use */
-#define IP27_INTR_1             46      /* do not use in Kernel */
-#define IP27_INTR_2             47
-#define IP27_INTR_3             48
-#define IP27_INTR_4             49
-#define IP27_INTR_5             50
-#define IP27_INTR_6             51
-#define IP27_INTR_7             52
-
-#define BRIDGE_ERROR_INTR       53      /* Setup by PROM to catch       */
-                                        /* Bridge Errors */
-#define DEBUG_INTR_A            54
-#define DEBUG_INTR_B            55      /* Used by symmon to stop all cpus */
-#define IO_ERROR_INTR           57      /* Setup by PROM */
-#define CLK_ERR_INTR            58
-#define COR_ERR_INTR_A          59
-#define COR_ERR_INTR_B          60
-#define MD_COR_ERR_INTR         61
-#define NI_ERROR_INTR           62
-#define MSC_PANIC_INTR          63
-
-#endif /* __ASM_SN_INTR_H */
diff --git a/include/asm-mips/sn/io.h b/include/asm-mips/sn/io.h
deleted file mode 100644
index 24c6775fbb0f..000000000000
--- a/include/asm-mips/sn/io.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000, 2003 Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SN_IO_H
-#define _ASM_SN_IO_H
-
-#if defined(CONFIG_SGI_IP27)
-#include <asm/sn/sn0/hubio.h>
-#endif
-
-
-#define IIO_ITTE_BASE           0x400160 /* base of translation table entries */
-#define IIO_ITTE(bigwin)        (IIO_ITTE_BASE + 8*(bigwin))
-
-#define IIO_ITTE_OFFSET_BITS    5       /* size of offset field */
-#define IIO_ITTE_OFFSET_MASK    ((1<<IIO_ITTE_OFFSET_BITS)-1)
-#define IIO_ITTE_OFFSET_SHIFT   0
-
-#define IIO_ITTE_WIDGET_BITS    4       /* size of widget field */
-#define IIO_ITTE_WIDGET_MASK    ((1<<IIO_ITTE_WIDGET_BITS)-1)
-#define IIO_ITTE_WIDGET_SHIFT   8
-
-#define IIO_ITTE_IOSP           1       /* I/O Space bit */
-#define IIO_ITTE_IOSP_MASK      1
-#define IIO_ITTE_IOSP_SHIFT     12
-#define HUB_PIO_MAP_TO_MEM      0
-#define HUB_PIO_MAP_TO_IO       1
-
-#define IIO_ITTE_INVALID_WIDGET 3       /* an invalid widget  */
-
-#define IIO_ITTE_PUT(nasid, bigwin, io_or_mem, widget, addr) \
-        REMOTE_HUB_S((nasid), IIO_ITTE(bigwin), \
-                (((((addr) >> BWIN_SIZE_BITS) & \
-                   IIO_ITTE_OFFSET_MASK) << IIO_ITTE_OFFSET_SHIFT) | \
-                (io_or_mem << IIO_ITTE_IOSP_SHIFT) | \
-                (((widget) & IIO_ITTE_WIDGET_MASK) << IIO_ITTE_WIDGET_SHIFT)))
-
-#define IIO_ITTE_DISABLE(nasid, bigwin) \
-        IIO_ITTE_PUT((nasid), HUB_PIO_MAP_TO_MEM, \
-                     (bigwin), IIO_ITTE_INVALID_WIDGET, 0)
-
-#define IIO_ITTE_GET(nasid, bigwin) REMOTE_HUB_ADDR((nasid), IIO_ITTE(bigwin))
-
-/*
- * Macro which takes the widget number, and returns the
- * IO PRB address of that widget.
- * value _x is expected to be a widget number in the range
- * 0, 8 - 0xF
- */
-#define IIO_IOPRB(_x)   (IIO_IOPRB_0 + ( ( (_x) < HUB_WIDGET_ID_MIN ? \
-                        (_x) : \
-                        (_x) - (HUB_WIDGET_ID_MIN-1)) << 3) )
-
-#endif /* _ASM_SN_IO_H */
diff --git a/include/asm-mips/sn/ioc3.h b/include/asm-mips/sn/ioc3.h
deleted file mode 100644
index 099677774d71..000000000000
--- a/include/asm-mips/sn/ioc3.h
+++ /dev/null
@@ -1,663 +0,0 @@
-/*
- * Copyright (C) 1999, 2000 Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _IOC3_H
-#define _IOC3_H
-
-#include <linux/types.h>
-
-/* SUPERIO uart register map */
-typedef volatile struct ioc3_uartregs {
-        union {
-                volatile u8     rbr;    /* read only, DLAB == 0 */
-                volatile u8     thr;    /* write only, DLAB == 0 */
-                volatile u8     dll;    /* DLAB == 1 */
-        } u1;
-        union {
-                volatile u8     ier;    /* DLAB == 0 */
-                volatile u8     dlm;    /* DLAB == 1 */
-        } u2;
-        union {
-                volatile u8     iir;    /* read only */
-                volatile u8     fcr;    /* write only */
-        } u3;
-        volatile u8         iu_lcr;
-        volatile u8         iu_mcr;
-        volatile u8         iu_lsr;
-        volatile u8         iu_msr;
-        volatile u8         iu_scr;
-} ioc3_uregs_t;
-
-#define iu_rbr u1.rbr
-#define iu_thr u1.thr
-#define iu_dll u1.dll
-#define iu_ier u2.ier
-#define iu_dlm u2.dlm
-#define iu_iir u3.iir
-#define iu_fcr u3.fcr
-
-struct ioc3_sioregs {
-        volatile u8             fill[0x141];    /* starts at 0x141 */
-
-        volatile u8             uartc;
-        volatile u8             kbdcg;
-
-        volatile u8             fill0[0x150 - 0x142 - 1];
-
-        volatile u8             pp_data;
-        volatile u8             pp_dsr;
-        volatile u8             pp_dcr;
-
-        volatile u8             fill1[0x158 - 0x152 - 1];
-
-        volatile u8             pp_fifa;
-        volatile u8             pp_cfgb;
-        volatile u8             pp_ecr;
-
-        volatile u8             fill2[0x168 - 0x15a - 1];
-
-        volatile u8             rtcad;
-        volatile u8             rtcdat;
-
-        volatile u8             fill3[0x170 - 0x169 - 1];
-
-        struct ioc3_uartregs    uartb;  /* 0x20170  */
-        struct ioc3_uartregs    uarta;  /* 0x20178  */
-};
-
-/* Register layout of IOC3 in configuration space.  */
-struct ioc3 {
-        volatile u32    pad0[7];        /* 0x00000  */
-        volatile u32    sio_ir;         /* 0x0001c  */
-        volatile u32    sio_ies;        /* 0x00020  */
-        volatile u32    sio_iec;        /* 0x00024  */
-        volatile u32    sio_cr;         /* 0x00028  */
-        volatile u32    int_out;        /* 0x0002c  */
-        volatile u32    mcr;            /* 0x00030  */
-
-        /* General Purpose I/O registers  */
-        volatile u32    gpcr_s;         /* 0x00034  */
-        volatile u32    gpcr_c;         /* 0x00038  */
-        volatile u32    gpdr;           /* 0x0003c  */
-        volatile u32    gppr_0;         /* 0x00040  */
-        volatile u32    gppr_1;         /* 0x00044  */
-        volatile u32    gppr_2;         /* 0x00048  */
-        volatile u32    gppr_3;         /* 0x0004c  */
-        volatile u32    gppr_4;         /* 0x00050  */
-        volatile u32    gppr_5;         /* 0x00054  */
-        volatile u32    gppr_6;         /* 0x00058  */
-        volatile u32    gppr_7;         /* 0x0005c  */
-        volatile u32    gppr_8;         /* 0x00060  */
-        volatile u32    gppr_9;         /* 0x00064  */
-        volatile u32    gppr_10;        /* 0x00068  */
-        volatile u32    gppr_11;        /* 0x0006c  */
-        volatile u32    gppr_12;        /* 0x00070  */
-        volatile u32    gppr_13;        /* 0x00074  */
-        volatile u32    gppr_14;        /* 0x00078  */
-        volatile u32    gppr_15;        /* 0x0007c  */
-
-        /* Parallel Port Registers  */
-        volatile u32    ppbr_h_a;       /* 0x00080  */
-        volatile u32    ppbr_l_a;       /* 0x00084  */
-        volatile u32    ppcr_a;         /* 0x00088  */
-        volatile u32    ppcr;           /* 0x0008c  */
-        volatile u32    ppbr_h_b;       /* 0x00090  */
-        volatile u32    ppbr_l_b;       /* 0x00094  */
-        volatile u32    ppcr_b;         /* 0x00098  */
-
-        /* Keyboard and Mouse Registers  */
-        volatile u32    km_csr;         /* 0x0009c  */
-        volatile u32    k_rd;           /* 0x000a0  */
-        volatile u32    m_rd;           /* 0x000a4  */
-        volatile u32    k_wd;           /* 0x000a8  */
-        volatile u32    m_wd;           /* 0x000ac  */
-
-        /* Serial Port Registers  */
-        volatile u32    sbbr_h;         /* 0x000b0  */
-        volatile u32    sbbr_l;         /* 0x000b4  */
-        volatile u32    sscr_a;         /* 0x000b8  */
-        volatile u32    stpir_a;        /* 0x000bc  */
-        volatile u32    stcir_a;        /* 0x000c0  */
-        volatile u32    srpir_a;        /* 0x000c4  */
-        volatile u32    srcir_a;        /* 0x000c8  */
-        volatile u32    srtr_a;         /* 0x000cc  */
-        volatile u32    shadow_a;       /* 0x000d0  */
-        volatile u32    sscr_b;         /* 0x000d4  */
-        volatile u32    stpir_b;        /* 0x000d8  */
-        volatile u32    stcir_b;        /* 0x000dc  */
-        volatile u32    srpir_b;        /* 0x000e0  */
-        volatile u32    srcir_b;        /* 0x000e4  */
-        volatile u32    srtr_b;         /* 0x000e8  */
-        volatile u32    shadow_b;       /* 0x000ec  */
-
-        /* Ethernet Registers  */
-        volatile u32    emcr;           /* 0x000f0  */
-        volatile u32    eisr;           /* 0x000f4  */
-        volatile u32    eier;           /* 0x000f8  */
-        volatile u32    ercsr;          /* 0x000fc  */
-        volatile u32    erbr_h;         /* 0x00100  */
-        volatile u32    erbr_l;         /* 0x00104  */
-        volatile u32    erbar;          /* 0x00108  */
-        volatile u32    ercir;          /* 0x0010c  */
-        volatile u32    erpir;          /* 0x00110  */
-        volatile u32    ertr;           /* 0x00114  */
-        volatile u32    etcsr;          /* 0x00118  */
-        volatile u32    ersr;           /* 0x0011c  */
-        volatile u32    etcdc;          /* 0x00120  */
-        volatile u32    ebir;           /* 0x00124  */
-        volatile u32    etbr_h;         /* 0x00128  */
-        volatile u32    etbr_l;         /* 0x0012c  */
-        volatile u32    etcir;          /* 0x00130  */
-        volatile u32    etpir;          /* 0x00134  */
-        volatile u32    emar_h;         /* 0x00138  */
-        volatile u32    emar_l;         /* 0x0013c  */
-        volatile u32    ehar_h;         /* 0x00140  */
-        volatile u32    ehar_l;         /* 0x00144  */
-        volatile u32    micr;           /* 0x00148  */
-        volatile u32    midr_r;         /* 0x0014c  */
-        volatile u32    midr_w;         /* 0x00150  */
-        volatile u32    pad1[(0x20000 - 0x00154) / 4];
-
-        /* SuperIO Registers  XXX */
-        struct ioc3_sioregs     sregs;  /* 0x20000 */
-        volatile u32    pad2[(0x40000 - 0x20180) / 4];
-
-        /* SSRAM Diagnostic Access */
-        volatile u32    ssram[(0x80000 - 0x40000) / 4];
-
-        /* Bytebus device offsets
-           0x80000 -   Access to the generic devices selected with   DEV0
-           0x9FFFF     bytebus DEV_SEL_0
-           0xA0000 -   Access to the generic devices selected with   DEV1
-           0xBFFFF     bytebus DEV_SEL_1
-           0xC0000 -   Access to the generic devices selected with   DEV2
-           0xDFFFF     bytebus DEV_SEL_2
-           0xE0000 -   Access to the generic devices selected with   DEV3
-           0xFFFFF     bytebus DEV_SEL_3  */
-};
-
-/*
- * Ethernet RX Buffer
- */
-struct ioc3_erxbuf {
-        u32     w0;                     /* first word (valid,bcnt,cksum) */
-        u32     err;                    /* second word various errors */
-        /* next comes n bytes of padding */
-        /* then the received ethernet frame itself */
-};
-
-#define ERXBUF_IPCKSUM_MASK     0x0000ffff
-#define ERXBUF_BYTECNT_MASK     0x07ff0000
-#define ERXBUF_BYTECNT_SHIFT    16
-#define ERXBUF_V                0x80000000
-
-#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
-#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
-#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
-#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
-#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
-#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
-#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
-#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
-#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
-#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
-#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
-#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
-
-/*
- * Ethernet TX Descriptor
- */
-#define ETXD_DATALEN    104
-struct ioc3_etxd {
-        u32     cmd;                            /* command field */
-        u32     bufcnt;                         /* buffer counts field */
-        u64     p1;                             /* buffer pointer 1 */
-        u64     p2;                             /* buffer pointer 2 */
-        u8      data[ETXD_DATALEN];             /* opt. tx data */
-};
-
-#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
-#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
-#define ETXD_D0V                0x00010000      /* data 0 valid */
-#define ETXD_B1V                0x00020000      /* buf 1 valid */
-#define ETXD_B2V                0x00040000      /* buf 2 valid */
-#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
-#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
-#define ETXD_CHKOFF_SHIFT       20
-
-#define ETXD_D0CNT_MASK         0x0000007f
-#define ETXD_B1CNT_MASK         0x0007ff00
-#define ETXD_B1CNT_SHIFT        8
-#define ETXD_B2CNT_MASK         0x7ff00000
-#define ETXD_B2CNT_SHIFT        20
-
-/*
- * Bytebus device space
- */
-#define IOC3_BYTEBUS_DEV0       0x80000L
-#define IOC3_BYTEBUS_DEV1       0xa0000L
-#define IOC3_BYTEBUS_DEV2       0xc0000L
-#define IOC3_BYTEBUS_DEV3       0xe0000L
-
-/* ------------------------------------------------------------------------- */
-
-/* Superio Registers (PIO Access) */
-#define IOC3_SIO_BASE           0x20000
-#define IOC3_SIO_UARTC          (IOC3_SIO_BASE+0x141)   /* UART Config */
-#define IOC3_SIO_KBDCG          (IOC3_SIO_BASE+0x142)   /* KBD Config */
-#define IOC3_SIO_PP_BASE        (IOC3_SIO_BASE+PP_BASE)         /* Parallel Port */
-#define IOC3_SIO_RTC_BASE       (IOC3_SIO_BASE+0x168)   /* Real Time Clock */
-#define IOC3_SIO_UB_BASE        (IOC3_SIO_BASE+UARTB_BASE)      /* UART B */
-#define IOC3_SIO_UA_BASE        (IOC3_SIO_BASE+UARTA_BASE)      /* UART A */
-
-/* SSRAM Diagnostic Access */
-#define IOC3_SSRAM      IOC3_RAM_OFF    /* base of SSRAM diagnostic access */
-#define IOC3_SSRAM_LEN  0x40000 /* 256kb (address space size, may not be fully populated) */
-#define IOC3_SSRAM_DM   0x0000ffff      /* data mask */
-#define IOC3_SSRAM_PM   0x00010000      /* parity mask */
-
-/* bitmasks for PCI_SCR */
-#define PCI_SCR_PAR_RESP_EN     0x00000040      /* enb PCI parity checking */
-#define PCI_SCR_SERR_EN         0x00000100      /* enable the SERR# driver */
-#define PCI_SCR_DROP_MODE_EN    0x00008000      /* drop pios on parity err */
-#define PCI_SCR_RX_SERR         (0x1 << 16)
-#define PCI_SCR_DROP_MODE       (0x1 << 17)
-#define PCI_SCR_SIG_PAR_ERR     (0x1 << 24)
-#define PCI_SCR_SIG_TAR_ABRT    (0x1 << 27)
-#define PCI_SCR_RX_TAR_ABRT     (0x1 << 28)
-#define PCI_SCR_SIG_MST_ABRT    (0x1 << 29)
-#define PCI_SCR_SIG_SERR        (0x1 << 30)
-#define PCI_SCR_PAR_ERR         (0x1 << 31)
-
-/* bitmasks for IOC3_KM_CSR */
-#define KM_CSR_K_WRT_PEND 0x00000001    /* kbd port xmitting or resetting */
-#define KM_CSR_M_WRT_PEND 0x00000002    /* mouse port xmitting or resetting */
-#define KM_CSR_K_LCB      0x00000004    /* Line Cntrl Bit for last KBD write */
-#define KM_CSR_M_LCB      0x00000008    /* same for mouse */
-#define KM_CSR_K_DATA     0x00000010    /* state of kbd data line */
-#define KM_CSR_K_CLK      0x00000020    /* state of kbd clock line */
-#define KM_CSR_K_PULL_DATA 0x00000040   /* pull kbd data line low */
-#define KM_CSR_K_PULL_CLK 0x00000080    /* pull kbd clock line low */
-#define KM_CSR_M_DATA     0x00000100    /* state of ms data line */
-#define KM_CSR_M_CLK      0x00000200    /* state of ms clock line */
-#define KM_CSR_M_PULL_DATA 0x00000400   /* pull ms data line low */
-#define KM_CSR_M_PULL_CLK 0x00000800    /* pull ms clock line low */
-#define KM_CSR_EMM_MODE   0x00001000    /* emulation mode */
-#define KM_CSR_SIM_MODE   0x00002000    /* clock X8 */
-#define KM_CSR_K_SM_IDLE  0x00004000    /* Keyboard is idle */
-#define KM_CSR_M_SM_IDLE  0x00008000    /* Mouse is idle */
-#define KM_CSR_K_TO       0x00010000    /* Keyboard trying to send/receive */
-#define KM_CSR_M_TO       0x00020000    /* Mouse trying to send/receive */
-#define KM_CSR_K_TO_EN    0x00040000    /* KM_CSR_K_TO + KM_CSR_K_TO_EN = cause
-                                           SIO_IR to assert */
-#define KM_CSR_M_TO_EN    0x00080000    /* KM_CSR_M_TO + KM_CSR_M_TO_EN = cause
-                                           SIO_IR to assert */
-#define KM_CSR_K_CLAMP_ONE      0x00100000      /* Pull K_CLK low after rec. one char */
-#define KM_CSR_M_CLAMP_ONE      0x00200000      /* Pull M_CLK low after rec. one char */
-#define KM_CSR_K_CLAMP_THREE    0x00400000      /* Pull K_CLK low after rec. three chars */
-#define KM_CSR_M_CLAMP_THREE    0x00800000      /* Pull M_CLK low after rec. three char */
-
-/* bitmasks for IOC3_K_RD and IOC3_M_RD */
-#define KM_RD_DATA_2    0x000000ff      /* 3rd char recvd since last read */
-#define KM_RD_DATA_2_SHIFT 0
-#define KM_RD_DATA_1    0x0000ff00      /* 2nd char recvd since last read */
-#define KM_RD_DATA_1_SHIFT 8
-#define KM_RD_DATA_0    0x00ff0000      /* 1st char recvd since last read */
-#define KM_RD_DATA_0_SHIFT 16
-#define KM_RD_FRAME_ERR_2 0x01000000    /*  framing or parity error in byte 2 */
-#define KM_RD_FRAME_ERR_1 0x02000000    /* same for byte 1 */
-#define KM_RD_FRAME_ERR_0 0x04000000    /* same for byte 0 */
-
-#define KM_RD_KBD_MSE   0x08000000      /* 0 if from kbd, 1 if from mouse */
-#define KM_RD_OFLO      0x10000000      /* 4th char recvd before this read */
-#define KM_RD_VALID_2   0x20000000      /* DATA_2 valid */
-#define KM_RD_VALID_1   0x40000000      /* DATA_1 valid */
-#define KM_RD_VALID_0   0x80000000      /* DATA_0 valid */
-#define KM_RD_VALID_ALL (KM_RD_VALID_0|KM_RD_VALID_1|KM_RD_VALID_2)
-
-/* bitmasks for IOC3_K_WD & IOC3_M_WD */
-#define KM_WD_WRT_DATA  0x000000ff      /* write to keyboard/mouse port */
-#define KM_WD_WRT_DATA_SHIFT 0
-
-/* bitmasks for serial RX status byte */
-#define RXSB_OVERRUN    0x01    /* char(s) lost */
-#define RXSB_PAR_ERR    0x02    /* parity error */
-#define RXSB_FRAME_ERR  0x04    /* framing error */
-#define RXSB_BREAK      0x08    /* break character */
-#define RXSB_CTS        0x10    /* state of CTS */
-#define RXSB_DCD        0x20    /* state of DCD */
-#define RXSB_MODEM_VALID 0x40   /* DCD, CTS and OVERRUN are valid */
-#define RXSB_DATA_VALID 0x80    /* data byte, FRAME_ERR PAR_ERR & BREAK valid */
-
-/* bitmasks for serial TX control byte */
-#define TXCB_INT_WHEN_DONE 0x20 /* interrupt after this byte is sent */
-#define TXCB_INVALID    0x00    /* byte is invalid */
-#define TXCB_VALID      0x40    /* byte is valid */
-#define TXCB_MCR        0x80    /* data<7:0> to modem control register */
-#define TXCB_DELAY      0xc0    /* delay data<7:0> mSec */
-
-/* bitmasks for IOC3_SBBR_L */
-#define SBBR_L_SIZE     0x00000001      /* 0 == 1KB rings, 1 == 4KB rings */
-#define SBBR_L_BASE     0xfffff000      /* lower serial ring base addr */
-
-/* bitmasks for IOC3_SSCR_<A:B> */
-#define SSCR_RX_THRESHOLD 0x000001ff    /* hiwater mark */
-#define SSCR_TX_TIMER_BUSY 0x00010000   /* TX timer in progress */
-#define SSCR_HFC_EN     0x00020000      /* hardware flow control enabled */
-#define SSCR_RX_RING_DCD 0x00040000     /* post RX record on delta-DCD */
-#define SSCR_RX_RING_CTS 0x00080000     /* post RX record on delta-CTS */
-#define SSCR_HIGH_SPD   0x00100000      /* 4X speed */
-#define SSCR_DIAG       0x00200000      /* bypass clock divider for sim */
-#define SSCR_RX_DRAIN   0x08000000      /* drain RX buffer to memory */
-#define SSCR_DMA_EN     0x10000000      /* enable ring buffer DMA */
-#define SSCR_DMA_PAUSE  0x20000000      /* pause DMA */
-#define SSCR_PAUSE_STATE 0x40000000     /* sets when PAUSE takes effect */
-#define SSCR_RESET      0x80000000      /* reset DMA channels */
-
-/* all producer/comsumer pointers are the same bitfield */
-#define PROD_CONS_PTR_4K 0x00000ff8     /* for 4K buffers */
-#define PROD_CONS_PTR_1K 0x000003f8     /* for 1K buffers */
-#define PROD_CONS_PTR_OFF 3
-
-/* bitmasks for IOC3_SRCIR_<A:B> */
-#define SRCIR_ARM       0x80000000      /* arm RX timer */
-
-/* bitmasks for IOC3_SRPIR_<A:B> */
-#define SRPIR_BYTE_CNT  0x07000000      /* bytes in packer */
-#define SRPIR_BYTE_CNT_SHIFT 24
-
-/* bitmasks for IOC3_STCIR_<A:B> */
-#define STCIR_BYTE_CNT  0x0f000000      /* bytes in unpacker */
-#define STCIR_BYTE_CNT_SHIFT 24
-
-/* bitmasks for IOC3_SHADOW_<A:B> */
-#define SHADOW_DR       0x00000001      /* data ready */
-#define SHADOW_OE       0x00000002      /* overrun error */
-#define SHADOW_PE       0x00000004      /* parity error */
-#define SHADOW_FE       0x00000008      /* framing error */
-#define SHADOW_BI       0x00000010      /* break interrupt */
-#define SHADOW_THRE     0x00000020      /* transmit holding register empty */
-#define SHADOW_TEMT     0x00000040      /* transmit shift register empty */
-#define SHADOW_RFCE     0x00000080      /* char in RX fifo has an error */
-#define SHADOW_DCTS     0x00010000      /* delta clear to send */
-#define SHADOW_DDCD     0x00080000      /* delta data carrier detect */
-#define SHADOW_CTS      0x00100000      /* clear to send */
-#define SHADOW_DCD      0x00800000      /* data carrier detect */
-#define SHADOW_DTR      0x01000000      /* data terminal ready */
-#define SHADOW_RTS      0x02000000      /* request to send */
-#define SHADOW_OUT1     0x04000000      /* 16550 OUT1 bit */
-#define SHADOW_OUT2     0x08000000      /* 16550 OUT2 bit */
-#define SHADOW_LOOP     0x10000000      /* loopback enabled */
-
-/* bitmasks for IOC3_SRTR_<A:B> */
-#define SRTR_CNT        0x00000fff      /* reload value for RX timer */
-#define SRTR_CNT_VAL    0x0fff0000      /* current value of RX timer */
-#define SRTR_CNT_VAL_SHIFT 16
-#define SRTR_HZ         16000   /* SRTR clock frequency */
-
-/* bitmasks for IOC3_SIO_IR, IOC3_SIO_IEC and IOC3_SIO_IES  */
-#define SIO_IR_SA_TX_MT         0x00000001      /* Serial port A TX empty */
-#define SIO_IR_SA_RX_FULL       0x00000002      /* port A RX buf full */
-#define SIO_IR_SA_RX_HIGH       0x00000004      /* port A RX hiwat */
-#define SIO_IR_SA_RX_TIMER      0x00000008      /* port A RX timeout */
-#define SIO_IR_SA_DELTA_DCD     0x00000010      /* port A delta DCD */
-#define SIO_IR_SA_DELTA_CTS     0x00000020      /* port A delta CTS */
-#define SIO_IR_SA_INT           0x00000040      /* port A pass-thru intr */
-#define SIO_IR_SA_TX_EXPLICIT   0x00000080      /* port A explicit TX thru */
-#define SIO_IR_SA_MEMERR        0x00000100      /* port A PCI error */
-#define SIO_IR_SB_TX_MT         0x00000200      /* */
-#define SIO_IR_SB_RX_FULL       0x00000400      /* */
-#define SIO_IR_SB_RX_HIGH       0x00000800      /* */
-#define SIO_IR_SB_RX_TIMER      0x00001000      /* */
-#define SIO_IR_SB_DELTA_DCD     0x00002000      /* */
-#define SIO_IR_SB_DELTA_CTS     0x00004000      /* */
-#define SIO_IR_SB_INT           0x00008000      /* */
-#define SIO_IR_SB_TX_EXPLICIT   0x00010000      /* */
-#define SIO_IR_SB_MEMERR        0x00020000      /* */
-#define SIO_IR_PP_INT           0x00040000      /* P port pass-thru intr */
-#define SIO_IR_PP_INTA          0x00080000      /* PP context A thru */
-#define SIO_IR_PP_INTB          0x00100000      /* PP context B thru */
-#define SIO_IR_PP_MEMERR        0x00200000      /* PP PCI error */
-#define SIO_IR_KBD_INT          0x00400000      /* kbd/mouse intr */
-#define SIO_IR_RT_INT           0x08000000      /* RT output pulse */
-#define SIO_IR_GEN_INT1         0x10000000      /* RT input pulse */
-#define SIO_IR_GEN_INT_SHIFT    28
-
-/* per device interrupt masks */
-#define SIO_IR_SA               (SIO_IR_SA_TX_MT | SIO_IR_SA_RX_FULL | \
-                                 SIO_IR_SA_RX_HIGH | SIO_IR_SA_RX_TIMER | \
-                                 SIO_IR_SA_DELTA_DCD | SIO_IR_SA_DELTA_CTS | \
-                                 SIO_IR_SA_INT | SIO_IR_SA_TX_EXPLICIT | \
-                                 SIO_IR_SA_MEMERR)
-#define SIO_IR_SB               (SIO_IR_SB_TX_MT | SIO_IR_SB_RX_FULL | \
-                                 SIO_IR_SB_RX_HIGH | SIO_IR_SB_RX_TIMER | \
-                                 SIO_IR_SB_DELTA_DCD | SIO_IR_SB_DELTA_CTS | \
-                                 SIO_IR_SB_INT | SIO_IR_SB_TX_EXPLICIT | \
-                                 SIO_IR_SB_MEMERR)
-#define SIO_IR_PP               (SIO_IR_PP_INT | SIO_IR_PP_INTA | \
-                                 SIO_IR_PP_INTB | SIO_IR_PP_MEMERR)
-#define SIO_IR_RT               (SIO_IR_RT_INT | SIO_IR_GEN_INT1)
-
-/* macro to load pending interrupts */
-#define IOC3_PENDING_INTRS(mem) (PCI_INW(&((mem)->sio_ir)) & \
-                                 PCI_INW(&((mem)->sio_ies_ro)))
-
-/* bitmasks for SIO_CR */
-#define SIO_CR_SIO_RESET        0x00000001      /* reset the SIO */
-#define SIO_CR_SER_A_BASE       0x000000fe      /* DMA poll addr port A */
-#define SIO_CR_SER_A_BASE_SHIFT 1
-#define SIO_CR_SER_B_BASE       0x00007f00      /* DMA poll addr port B */
-#define SIO_CR_SER_B_BASE_SHIFT 8
-#define SIO_SR_CMD_PULSE        0x00078000      /* byte bus strobe length */
-#define SIO_CR_CMD_PULSE_SHIFT  15
-#define SIO_CR_ARB_DIAG         0x00380000      /* cur !enet PCI requet (ro) */
-#define SIO_CR_ARB_DIAG_TXA     0x00000000
-#define SIO_CR_ARB_DIAG_RXA     0x00080000
-#define SIO_CR_ARB_DIAG_TXB     0x00100000
-#define SIO_CR_ARB_DIAG_RXB     0x00180000
-#define SIO_CR_ARB_DIAG_PP      0x00200000
-#define SIO_CR_ARB_DIAG_IDLE    0x00400000      /* 0 -> active request (ro) */
-
-/* bitmasks for INT_OUT */
-#define INT_OUT_COUNT   0x0000ffff      /* pulse interval timer */
-#define INT_OUT_MODE    0x00070000      /* mode mask */
-#define INT_OUT_MODE_0  0x00000000      /* set output to 0 */
-#define INT_OUT_MODE_1  0x00040000      /* set output to 1 */
-#define INT_OUT_MODE_1PULSE 0x00050000  /* send 1 pulse */
-#define INT_OUT_MODE_PULSES 0x00060000  /* send 1 pulse every interval */
-#define INT_OUT_MODE_SQW 0x00070000     /* toggle output every interval */
-#define INT_OUT_DIAG    0x40000000      /* diag mode */
-#define INT_OUT_INT_OUT 0x80000000      /* current state of INT_OUT */
-
-/* time constants for INT_OUT */
-#define INT_OUT_NS_PER_TICK (30 * 260)  /* 30 ns PCI clock, divisor=260 */
-#define INT_OUT_TICKS_PER_PULSE 3       /* outgoing pulse lasts 3 ticks */
-#define INT_OUT_US_TO_COUNT(x)          /* convert uS to a count value */ \
-        (((x) * 10 + INT_OUT_NS_PER_TICK / 200) *       \
-         100 / INT_OUT_NS_PER_TICK - 1)
-#define INT_OUT_COUNT_TO_US(x)          /* convert count value to uS */ \
-        (((x) + 1) * INT_OUT_NS_PER_TICK / 1000)
-#define INT_OUT_MIN_TICKS 3     /* min period is width of pulse in "ticks" */
-#define INT_OUT_MAX_TICKS INT_OUT_COUNT         /* largest possible count */
-
-/* bitmasks for GPCR */
-#define GPCR_DIR        0x000000ff      /* tristate pin input or output */
-#define GPCR_DIR_PIN(x) (1<<(x))        /* access one of the DIR bits */
-#define GPCR_EDGE       0x000f0000      /* extint edge or level sensitive */
-#define GPCR_EDGE_PIN(x) (1<<((x)+15))  /* access one of the EDGE bits */
-
-/* values for GPCR */
-#define GPCR_INT_OUT_EN 0x00100000      /* enable INT_OUT to pin 0 */
-#define GPCR_MLAN_EN    0x00200000      /* enable MCR to pin 8 */
-#define GPCR_DIR_SERA_XCVR 0x00000080   /* Port A Transceiver select enable */
-#define GPCR_DIR_SERB_XCVR 0x00000040   /* Port B Transceiver select enable */
-#define GPCR_DIR_PHY_RST   0x00000020   /* ethernet PHY reset enable */
-
-/* defs for some of the generic I/O pins */
-#define GPCR_PHY_RESET          0x20    /* pin is output to PHY reset */
-#define GPCR_UARTB_MODESEL      0x40    /* pin is output to port B mode sel */
-#define GPCR_UARTA_MODESEL      0x80    /* pin is output to port A mode sel */
-
-#define GPPR_PHY_RESET_PIN      5       /* GIO pin controlling phy reset */
-#define GPPR_UARTB_MODESEL_PIN  6       /* GIO pin controlling uart b mode select */
-#define GPPR_UARTA_MODESEL_PIN  7       /* GIO pin controlling uart a mode select */
-
-#define EMCR_DUPLEX             0x00000001
-#define EMCR_PROMISC            0x00000002
-#define EMCR_PADEN              0x00000004
-#define EMCR_RXOFF_MASK         0x000001f8
-#define EMCR_RXOFF_SHIFT        3
-#define EMCR_RAMPAR             0x00000200
-#define EMCR_BADPAR             0x00000800
-#define EMCR_BUFSIZ             0x00001000
-#define EMCR_TXDMAEN            0x00002000
-#define EMCR_TXEN               0x00004000
-#define EMCR_RXDMAEN            0x00008000
-#define EMCR_RXEN               0x00010000
-#define EMCR_LOOPBACK           0x00020000
-#define EMCR_ARB_DIAG           0x001c0000
-#define EMCR_ARB_DIAG_IDLE      0x00200000
-#define EMCR_RST                0x80000000
-
-#define EISR_RXTIMERINT         0x00000001
-#define EISR_RXTHRESHINT        0x00000002
-#define EISR_RXOFLO             0x00000004
-#define EISR_RXBUFOFLO          0x00000008
-#define EISR_RXMEMERR           0x00000010
-#define EISR_RXPARERR           0x00000020
-#define EISR_TXEMPTY            0x00010000
-#define EISR_TXRTRY             0x00020000
-#define EISR_TXEXDEF            0x00040000
-#define EISR_TXLCOL             0x00080000
-#define EISR_TXGIANT            0x00100000
-#define EISR_TXBUFUFLO          0x00200000
-#define EISR_TXEXPLICIT         0x00400000
-#define EISR_TXCOLLWRAP         0x00800000
-#define EISR_TXDEFERWRAP        0x01000000
-#define EISR_TXMEMERR           0x02000000
-#define EISR_TXPARERR           0x04000000
-
-#define ERCSR_THRESH_MASK       0x000001ff      /* enet RX threshold */
-#define ERCSR_RX_TMR            0x40000000      /* simulation only */
-#define ERCSR_DIAG_OFLO         0x80000000      /* simulation only */
-
-#define ERBR_ALIGNMENT          4096
-#define ERBR_L_RXRINGBASE_MASK  0xfffff000
-
-#define ERBAR_BARRIER_BIT       0x0100
-#define ERBAR_RXBARR_MASK       0xffff0000
-#define ERBAR_RXBARR_SHIFT      16
-
-#define ERCIR_RXCONSUME_MASK    0x00000fff
-
-#define ERPIR_RXPRODUCE_MASK    0x00000fff
-#define ERPIR_ARM               0x80000000
-
-#define ERTR_CNT_MASK           0x000007ff
-
-#define ETCSR_IPGT_MASK         0x0000007f
-#define ETCSR_IPGR1_MASK        0x00007f00
-#define ETCSR_IPGR1_SHIFT       8
-#define ETCSR_IPGR2_MASK        0x007f0000
-#define ETCSR_IPGR2_SHIFT       16
-#define ETCSR_NOTXCLK           0x80000000
-
-#define ETCDC_COLLCNT_MASK      0x0000ffff
-#define ETCDC_DEFERCNT_MASK     0xffff0000
-#define ETCDC_DEFERCNT_SHIFT    16
-
-#define ETBR_ALIGNMENT          (64*1024)
-#define ETBR_L_RINGSZ_MASK      0x00000001
-#define ETBR_L_RINGSZ128        0
-#define ETBR_L_RINGSZ512        1
-#define ETBR_L_TXRINGBASE_MASK  0xffffc000
-
-#define ETCIR_TXCONSUME_MASK    0x0000ffff
-#define ETCIR_IDLE              0x80000000
-
-#define ETPIR_TXPRODUCE_MASK    0x0000ffff
-
-#define EBIR_TXBUFPROD_MASK     0x0000001f
-#define EBIR_TXBUFCONS_MASK     0x00001f00
-#define EBIR_TXBUFCONS_SHIFT    8
-#define EBIR_RXBUFPROD_MASK     0x007fc000
-#define EBIR_RXBUFPROD_SHIFT    14
-#define EBIR_RXBUFCONS_MASK     0xff800000
-#define EBIR_RXBUFCONS_SHIFT    23
-
-#define MICR_REGADDR_MASK       0x0000001f
-#define MICR_PHYADDR_MASK       0x000003e0
-#define MICR_PHYADDR_SHIFT      5
-#define MICR_READTRIG           0x00000400
-#define MICR_BUSY               0x00000800
-
-#define MIDR_DATA_MASK          0x0000ffff
-
-#define ERXBUF_IPCKSUM_MASK     0x0000ffff
-#define ERXBUF_BYTECNT_MASK     0x07ff0000
-#define ERXBUF_BYTECNT_SHIFT    16
-#define ERXBUF_V                0x80000000
-
-#define ERXBUF_CRCERR           0x00000001      /* aka RSV15 */
-#define ERXBUF_FRAMERR          0x00000002      /* aka RSV14 */
-#define ERXBUF_CODERR           0x00000004      /* aka RSV13 */
-#define ERXBUF_INVPREAMB        0x00000008      /* aka RSV18 */
-#define ERXBUF_LOLEN            0x00007000      /* aka RSV2_0 */
-#define ERXBUF_HILEN            0x03ff0000      /* aka RSV12_3 */
-#define ERXBUF_MULTICAST        0x04000000      /* aka RSV16 */
-#define ERXBUF_BROADCAST        0x08000000      /* aka RSV17 */
-#define ERXBUF_LONGEVENT        0x10000000      /* aka RSV19 */
-#define ERXBUF_BADPKT           0x20000000      /* aka RSV20 */
-#define ERXBUF_GOODPKT          0x40000000      /* aka RSV21 */
-#define ERXBUF_CARRIER          0x80000000      /* aka RSV22 */
-
-#define ETXD_BYTECNT_MASK       0x000007ff      /* total byte count */
-#define ETXD_INTWHENDONE        0x00001000      /* intr when done */
-#define ETXD_D0V                0x00010000      /* data 0 valid */
-#define ETXD_B1V                0x00020000      /* buf 1 valid */
-#define ETXD_B2V                0x00040000      /* buf 2 valid */
-#define ETXD_DOCHECKSUM         0x00080000      /* insert ip cksum */
-#define ETXD_CHKOFF_MASK        0x07f00000      /* cksum byte offset */
-#define ETXD_CHKOFF_SHIFT       20
-
-#define ETXD_D0CNT_MASK         0x0000007f
-#define ETXD_B1CNT_MASK         0x0007ff00
-#define ETXD_B1CNT_SHIFT        8
-#define ETXD_B2CNT_MASK         0x7ff00000
-#define ETXD_B2CNT_SHIFT        20
-
-typedef enum ioc3_subdevs_e {
-    ioc3_subdev_ether,
-    ioc3_subdev_generic,
-    ioc3_subdev_nic,
-    ioc3_subdev_kbms,
-    ioc3_subdev_ttya,
-    ioc3_subdev_ttyb,
-    ioc3_subdev_ecpp,
-    ioc3_subdev_rt,
-    ioc3_nsubdevs
-} ioc3_subdev_t;
-
-/* subdevice disable bits,
- * from the standard INFO_LBL_SUBDEVS
- */
-#define IOC3_SDB_ETHER          (1<<ioc3_subdev_ether)
-#define IOC3_SDB_GENERIC        (1<<ioc3_subdev_generic)
-#define IOC3_SDB_NIC            (1<<ioc3_subdev_nic)
-#define IOC3_SDB_KBMS           (1<<ioc3_subdev_kbms)
-#define IOC3_SDB_TTYA           (1<<ioc3_subdev_ttya)
-#define IOC3_SDB_TTYB           (1<<ioc3_subdev_ttyb)
-#define IOC3_SDB_ECPP           (1<<ioc3_subdev_ecpp)
-#define IOC3_SDB_RT             (1<<ioc3_subdev_rt)
-
-#define IOC3_ALL_SUBDEVS        ((1<<ioc3_nsubdevs)-1)
-
-#define IOC3_SDB_SERIAL         (IOC3_SDB_TTYA|IOC3_SDB_TTYB)
-
-#define IOC3_STD_SUBDEVS        IOC3_ALL_SUBDEVS
-
-#define IOC3_INTA_SUBDEVS       IOC3_SDB_ETHER
-#define IOC3_INTB_SUBDEVS       (IOC3_SDB_GENERIC|IOC3_SDB_KBMS|IOC3_SDB_SERIAL|IOC3_SDB_ECPP|IOC3_SDB_RT)
-
-#endif /* _IOC3_H */
diff --git a/include/asm-mips/sn/klconfig.h b/include/asm-mips/sn/klconfig.h
deleted file mode 100644
index 96cfd2ab1bcd..000000000000
--- a/include/asm-mips/sn/klconfig.h
+++ /dev/null
@@ -1,898 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/klconfig.h>.
- *
- * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 1999, 2000 by Ralf Baechle
- */
-#ifndef _ASM_SN_KLCONFIG_H
-#define _ASM_SN_KLCONFIG_H
-
-/*
- * The KLCONFIG structures store info about the various BOARDs found
- * during Hardware Discovery. In addition, it stores info about the
- * components found on the BOARDs.
- */
-
-/*
- * WARNING:
- *      Certain assembly language routines (notably xxxxx.s) in the IP27PROM
- *      will depend on the format of the data structures in this file.  In
- *      most cases, rearranging the fields can seriously break things.
- *      Adding fields in the beginning or middle can also break things.
- *      Add fields if necessary, to the end of a struct in such a way
- *      that offsets of existing fields do not change.
- */
-
-#include <linux/types.h>
-#include <asm/sn/types.h>
-
-#if defined(CONFIG_SGI_IP27)
-
-#include <asm/sn/sn0/addrs.h>
-//#include <sys/SN/router.h>
-// XXX Stolen from <sys/SN/router.h>:
-#define MAX_ROUTER_PORTS (6)    /* Max. number of ports on a router */
-#include <asm/sn/fru.h>
-//#include <sys/graph.h>
-//#include <sys/xtalk/xbow.h>
-
-#elif defined(CONFIG_SGI_IP35)
-
-#include <asm/sn/sn1/addrs.h>
-#include <sys/sn/router.h>
-#include <sys/graph.h>
-#include <asm/xtalk/xbow.h>
-
-#endif /* !CONFIG_SGI_IP27 && !CONFIG_SGI_IP35 */
-
-#if defined(CONFIG_SGI_IP27) || defined(CONFIG_SGI_IP35)
-#include <asm/sn/agent.h>
-#include <asm/fw/arc/types.h>
-#include <asm/fw/arc/hinv.h>
-#if defined(CONFIG_SGI_IP35)
-// The hack file has to be before vector and after sn0_fru....
-#include <asm/hack.h>
-#include <asm/sn/vector.h>
-#include <asm/xtalk/xtalk.h>
-#endif /* CONFIG_SGI_IP35 */
-#endif /* CONFIG_SGI_IP27 || CONFIG_SGI_IP35 */
-
-typedef u64  nic_t;
-
-#define KLCFGINFO_MAGIC 0xbeedbabe
-
-typedef s32 klconf_off_t;
-
-/*
- * Some IMPORTANT OFFSETS. These are the offsets on all NODES.
- */
-#define MAX_MODULE_ID           255
-#define SIZE_PAD                4096 /* 4k padding for structures */
-/*
- * 1 NODE brd, 2 Router brd (1 8p, 1 meta), 6 Widgets,
- * 2 Midplanes assuming no pci card cages
- */
-#define MAX_SLOTS_PER_NODE      (1 + 2 + 6 + 2)
-
-/* XXX if each node is guranteed to have some memory */
-
-#define MAX_PCI_DEVS            8
-
-/* lboard_t->brd_flags fields */
-/* All bits in this field are currently used. Try the pad fields if
-   you need more flag bits */
-
-#define ENABLE_BOARD            0x01
-#define FAILED_BOARD            0x02
-#define DUPLICATE_BOARD         0x04    /* Boards like midplanes/routers which
-                                           are discovered twice. Use one of them */
-#define VISITED_BOARD           0x08    /* Used for compact hub numbering. */
-#define LOCAL_MASTER_IO6        0x10    /* master io6 for that node */
-#define GLOBAL_MASTER_IO6       0x20
-#define THIRD_NIC_PRESENT       0x40    /* for future use */
-#define SECOND_NIC_PRESENT      0x80    /* addons like MIO are present */
-
-/* klinfo->flags fields */
-
-#define KLINFO_ENABLE           0x01    /* This component is enabled */
-#define KLINFO_FAILED           0x02    /* This component failed */
-#define KLINFO_DEVICE           0x04    /* This component is a device */
-#define KLINFO_VISITED          0x08    /* This component has been visited */
-#define KLINFO_CONTROLLER       0x10    /* This component is a device controller */
-#define KLINFO_INSTALL          0x20    /* Install a driver */
-#define KLINFO_HEADLESS         0x40    /* Headless (or hubless) component */
-#define IS_CONSOLE_IOC3(i)      ((((klinfo_t *)i)->flags) & KLINFO_INSTALL)
-
-#define GB2             0x80000000
-
-#define MAX_RSV_PTRS    32
-
-/* Structures to manage various data storage areas */
-/* The numbers must be contiguous since the array index i
-   is used in the code to allocate various areas.
-*/
-
-#define BOARD_STRUCT            0
-#define COMPONENT_STRUCT        1
-#define ERRINFO_STRUCT          2
-#define KLMALLOC_TYPE_MAX       (ERRINFO_STRUCT + 1)
-#define DEVICE_STRUCT           3
-
-
-typedef struct console_s {
-        unsigned long   uart_base;
-        unsigned long   config_base;
-        unsigned long   memory_base;
-        short           baud;
-        short           flag;
-        int             type;
-        nasid_t         nasid;
-        char            wid;
-        char            npci;
-        nic_t           baseio_nic;
-} console_t;
-
-typedef struct klc_malloc_hdr {
-        klconf_off_t km_base;
-        klconf_off_t km_limit;
-        klconf_off_t km_current;
-} klc_malloc_hdr_t;
-
-/* Functions/macros needed to use this structure */
-
-typedef struct kl_config_hdr {
-        u64             ch_magic;       /* set this to KLCFGINFO_MAGIC */
-        u32             ch_version;    /* structure version number */
-        klconf_off_t    ch_malloc_hdr_off; /* offset of ch_malloc_hdr */
-        klconf_off_t    ch_cons_off;       /* offset of ch_cons */
-        klconf_off_t    ch_board_info;  /* the link list of boards */
-        console_t       ch_cons_info;   /* address info of the console */
-        klc_malloc_hdr_t ch_malloc_hdr[KLMALLOC_TYPE_MAX];
-        confidence_t    ch_sw_belief;   /* confidence that software is bad*/
-        confidence_t    ch_sn0net_belief; /* confidence that sn0net is bad */
-} kl_config_hdr_t;
-
-
-#define KL_CONFIG_HDR(_nasid)   ((kl_config_hdr_t *)(KLCONFIG_ADDR(_nasid)))
-#define KL_CONFIG_INFO_OFFSET(_nasid)                                   \
-        (KL_CONFIG_HDR(_nasid)->ch_board_info)
-#define KL_CONFIG_INFO_SET_OFFSET(_nasid, _off)                         \
-        (KL_CONFIG_HDR(_nasid)->ch_board_info = (_off))
-
-#define KL_CONFIG_INFO(_nasid)                                          \
-        (lboard_t *)((KL_CONFIG_HDR(_nasid)->ch_board_info) ?           \
-         NODE_OFFSET_TO_K1((_nasid), KL_CONFIG_HDR(_nasid)->ch_board_info) : \
-         0)
-#define KL_CONFIG_MAGIC(_nasid)         (KL_CONFIG_HDR(_nasid)->ch_magic)
-
-#define KL_CONFIG_CHECK_MAGIC(_nasid)                                   \
-        (KL_CONFIG_HDR(_nasid)->ch_magic == KLCFGINFO_MAGIC)
-
-#define KL_CONFIG_HDR_INIT_MAGIC(_nasid)        \
-                  (KL_CONFIG_HDR(_nasid)->ch_magic = KLCFGINFO_MAGIC)
-
-/* --- New Macros for the changed kl_config_hdr_t structure --- */
-
-#define PTR_CH_MALLOC_HDR(_k)   ((klc_malloc_hdr_t *)\
-                        ((unsigned long)_k + (_k->ch_malloc_hdr_off)))
-
-#define KL_CONFIG_CH_MALLOC_HDR(_n)   PTR_CH_MALLOC_HDR(KL_CONFIG_HDR(_n))
-
-#define PTR_CH_CONS_INFO(_k)    ((console_t *)\
-                        ((unsigned long)_k + (_k->ch_cons_off)))
-
-#define KL_CONFIG_CH_CONS_INFO(_n)   PTR_CH_CONS_INFO(KL_CONFIG_HDR(_n))
-
-/* ------------------------------------------------------------- */
-
-#define KL_CONFIG_INFO_START(_nasid)    \
-        (klconf_off_t)(KLCONFIG_OFFSET(_nasid) + sizeof(kl_config_hdr_t))
-
-#define KL_CONFIG_BOARD_NASID(_brd)     ((_brd)->brd_nasid)
-#define KL_CONFIG_BOARD_SET_NEXT(_brd, _off)    ((_brd)->brd_next = (_off))
-
-#define KL_CONFIG_DUPLICATE_BOARD(_brd) ((_brd)->brd_flags & DUPLICATE_BOARD)
-
-#define XBOW_PORT_TYPE_HUB(_xbowp, _link)       \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_HUB)
-#define XBOW_PORT_TYPE_IO(_xbowp, _link)        \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_IO)
-
-#define XBOW_PORT_IS_ENABLED(_xbowp, _link)     \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_flag & XBOW_PORT_ENABLE)
-#define XBOW_PORT_NASID(_xbowp, _link)  \
-               ((_xbowp)->xbow_port_info[(_link) - BASE_XBOW_PORT].port_nasid)
-
-#define XBOW_PORT_IO     0x1
-#define XBOW_PORT_HUB    0x2
-#define XBOW_PORT_ENABLE 0x4
-
-#define SN0_PORT_FENCE_SHFT     0
-#define SN0_PORT_FENCE_MASK     (1 << SN0_PORT_FENCE_SHFT)
-
-/*
- * The KLCONFIG area is organized as a LINKED LIST of BOARDs. A BOARD
- * can be either 'LOCAL' or 'REMOTE'. LOCAL means it is attached to
- * the LOCAL/current NODE. REMOTE means it is attached to a different
- * node.(TBD - Need a way to treat ROUTER boards.)
- *
- * There are 2 different structures to represent these boards -
- * lboard - Local board, rboard - remote board. These 2 structures
- * can be arbitrarily mixed in the LINKED LIST of BOARDs. (Refer
- * Figure below). The first byte of the rboard or lboard structure
- * is used to find out its type - no unions are used.
- * If it is a lboard, then the config info of this board will be found
- * on the local node. (LOCAL NODE BASE + offset value gives pointer to
- * the structure.
- * If it is a rboard, the local structure contains the node number
- * and the offset of the beginning of the LINKED LIST on the remote node.
- * The details of the hardware on a remote node can be built locally,
- * if required, by reading the LINKED LIST on the remote node and
- * ignoring all the rboards on that node.
- *
- * The local node uses the REMOTE NODE NUMBER + OFFSET to point to the
- * First board info on the remote node. The remote node list is
- * traversed as the local list, using the REMOTE BASE ADDRESS and not
- * the local base address and ignoring all rboard values.
- *
- *
- KLCONFIG
-
- +------------+      +------------+      +------------+      +------------+
- |  lboard    |  +-->|   lboard   |  +-->|   rboard   |  +-->|   lboard   |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | board info |  |   | board info |  |   |errinfo,bptr|  |   | board info |
- +------------+  |   +------------+  |   +------------+  |   +------------+
- | offset     |--+   |  offset    |--+   |  offset    |--+   |offset=NULL |
- +------------+      +------------+      +------------+      +------------+
-
-
- +------------+
- | board info |
- +------------+       +--------------------------------+
- | compt 1    |------>| type, rev, diaginfo, size ...  |  (CPU)
- +------------+       +--------------------------------+
- | compt 2    |--+
- +------------+  |    +--------------------------------+
- |  ...       |  +--->| type, rev, diaginfo, size ...  |  (MEM_BANK)
- +------------+       +--------------------------------+
- | errinfo    |--+
- +------------+  |    +--------------------------------+
-                 +--->|r/l brd errinfo,compt err flags |
-                      +--------------------------------+
-
- *
- * Each BOARD consists of COMPONENTs and the BOARD structure has
- * pointers (offsets) to its COMPONENT structure.
- * The COMPONENT structure has version info, size and speed info, revision,
- * error info and the NIC info. This structure can accommodate any
- * BOARD with arbitrary COMPONENT composition.
- *
- * The ERRORINFO part of each BOARD has error information
- * that describes errors about the BOARD itself. It also has flags to
- * indicate the COMPONENT(s) on the board that have errors. The error
- * information specific to the COMPONENT is present in the respective
- * COMPONENT structure.
- *
- * The ERRORINFO structure is also treated like a COMPONENT, ie. the
- * BOARD has pointers(offset) to the ERRORINFO structure. The rboard
- * structure also has a pointer to the ERRORINFO structure. This is
- * the place to store ERRORINFO about a REMOTE NODE, if the HUB on
- * that NODE is not working or if the REMOTE MEMORY is BAD. In cases where
- * only the CPU of the REMOTE NODE is disabled, the ERRORINFO pointer can
- * be a NODE NUMBER, REMOTE OFFSET combination, pointing to error info
- * which is present on the REMOTE NODE.(TBD)
- * REMOTE ERRINFO can be stored on any of the nearest nodes
- * or on all the nearest nodes.(TBD)
- * Like BOARD structures, REMOTE ERRINFO structures can be built locally
- * using the rboard errinfo pointer.
- *
- * In order to get useful information from this Data organization, a set of
- * interface routines are provided (TBD). The important thing to remember while
- * manipulating the structures, is that, the NODE number information should
- * be used. If the NODE is non-zero (remote) then each offset should
- * be added to the REMOTE BASE ADDR else it should be added to the LOCAL BASE ADDR.
- * This includes offsets for BOARDS, COMPONENTS and ERRORINFO.
- *
- * Note that these structures do not provide much info about connectivity.
- * That info will be part of HWGRAPH, which is an extension of the cfg_t
- * data structure. (ref IP27prom/cfg.h) It has to be extended to include
- * the IO part of the Network(TBD).
- *
- * The data structures below define the above concepts.
- */
-
-/*
- * Values for CPU types
- */
-#define KL_CPU_R4000            0x1     /* Standard R4000 */
-#define KL_CPU_TFP              0x2     /* TFP processor */
-#define KL_CPU_R10000           0x3     /* R10000 (T5) */
-#define KL_CPU_NONE             (-1)    /* no cpu present in slot */
-
-/*
- * IP27 BOARD classes
- */
-
-#define KLCLASS_MASK    0xf0
-#define KLCLASS_NONE    0x00
-#define KLCLASS_NODE    0x10             /* CPU, Memory and HUB board */
-#define KLCLASS_CPU     KLCLASS_NODE
-#define KLCLASS_IO      0x20             /* BaseIO, 4 ch SCSI, ethernet, FDDI
-                                            and the non-graphics widget boards */
-#define KLCLASS_ROUTER  0x30             /* Router board */
-#define KLCLASS_MIDPLANE 0x40            /* We need to treat this as a board
-                                            so that we can record error info */
-#define KLCLASS_GFX     0x50            /* graphics boards */
-
-#define KLCLASS_PSEUDO_GFX      0x60    /* HDTV type cards that use a gfx
-                                         * hw ifc to xtalk and are not gfx
-                                         * class for sw purposes */
-
-#define KLCLASS_MAX     7               /* Bump this if a new CLASS is added */
-#define KLTYPE_MAX      10              /* Bump this if a new CLASS is added */
-
-#define KLCLASS_UNKNOWN 0xf0
-
-#define KLCLASS(_x) ((_x) & KLCLASS_MASK)
-
-/*
- * IP27 board types
- */
-
-#define KLTYPE_MASK     0x0f
-#define KLTYPE_NONE     0x00
-#define KLTYPE_EMPTY    0x00
-
-#define KLTYPE_WEIRDCPU (KLCLASS_CPU | 0x0)
-#define KLTYPE_IP27     (KLCLASS_CPU | 0x1) /* 2 CPUs(R10K) per board */
-
-#define KLTYPE_WEIRDIO  (KLCLASS_IO  | 0x0)
-#define KLTYPE_BASEIO   (KLCLASS_IO  | 0x1) /* IOC3, SuperIO, Bridge, SCSI */
-#define KLTYPE_IO6      KLTYPE_BASEIO       /* Additional name */
-#define KLTYPE_4CHSCSI  (KLCLASS_IO  | 0x2)
-#define KLTYPE_MSCSI    KLTYPE_4CHSCSI      /* Additional name */
-#define KLTYPE_ETHERNET (KLCLASS_IO  | 0x3)
-#define KLTYPE_MENET    KLTYPE_ETHERNET     /* Additional name */
-#define KLTYPE_FDDI     (KLCLASS_IO  | 0x4)
-#define KLTYPE_UNUSED   (KLCLASS_IO  | 0x5) /* XXX UNUSED */
-#define KLTYPE_HAROLD   (KLCLASS_IO  | 0x6) /* PCI SHOE BOX */
-#define KLTYPE_PCI      KLTYPE_HAROLD
-#define KLTYPE_VME      (KLCLASS_IO  | 0x7) /* Any 3rd party VME card */
-#define KLTYPE_MIO      (KLCLASS_IO  | 0x8)
-#define KLTYPE_FC       (KLCLASS_IO  | 0x9)
-#define KLTYPE_LINC     (KLCLASS_IO  | 0xA)
-#define KLTYPE_TPU      (KLCLASS_IO  | 0xB) /* Tensor Processing Unit */
-#define KLTYPE_GSN_A    (KLCLASS_IO  | 0xC) /* Main GSN board */
-#define KLTYPE_GSN_B    (KLCLASS_IO  | 0xD) /* Auxiliary GSN board */
-
-#define KLTYPE_GFX      (KLCLASS_GFX | 0x0) /* unknown graphics type */
-#define KLTYPE_GFX_KONA (KLCLASS_GFX | 0x1) /* KONA graphics on IP27 */
-#define KLTYPE_GFX_MGRA (KLCLASS_GFX | 0x3) /* MGRAS graphics on IP27 */
-
-#define KLTYPE_WEIRDROUTER (KLCLASS_ROUTER | 0x0)
-#define KLTYPE_ROUTER     (KLCLASS_ROUTER | 0x1)
-#define KLTYPE_ROUTER2    KLTYPE_ROUTER         /* Obsolete! */
-#define KLTYPE_NULL_ROUTER (KLCLASS_ROUTER | 0x2)
-#define KLTYPE_META_ROUTER (KLCLASS_ROUTER | 0x3)
-
-#define KLTYPE_WEIRDMIDPLANE (KLCLASS_MIDPLANE | 0x0)
-#define KLTYPE_MIDPLANE8  (KLCLASS_MIDPLANE | 0x1) /* 8 slot backplane */
-#define KLTYPE_MIDPLANE    KLTYPE_MIDPLANE8
-#define KLTYPE_PBRICK_XBOW      (KLCLASS_MIDPLANE | 0x2)
-
-#define KLTYPE_IOBRICK          (KLCLASS_IOBRICK | 0x0)
-#define KLTYPE_IBRICK           (KLCLASS_IOBRICK | 0x1)
-#define KLTYPE_PBRICK           (KLCLASS_IOBRICK | 0x2)
-#define KLTYPE_XBRICK           (KLCLASS_IOBRICK | 0x3)
-
-#define KLTYPE_PBRICK_BRIDGE    KLTYPE_PBRICK
-
-/* The value of type should be more than 8 so that hinv prints
- * out the board name from the NIC string. For values less than
- * 8 the name of the board needs to be hard coded in a few places.
- * When bringup started nic names had not standardized and so we
- * had to hard code. (For people interested in history.)
- */
-#define KLTYPE_XTHD     (KLCLASS_PSEUDO_GFX | 0x9)
-
-#define KLTYPE_UNKNOWN  (KLCLASS_UNKNOWN | 0xf)
-
-#define KLTYPE(_x)      ((_x) & KLTYPE_MASK)
-#define IS_MIO_PRESENT(l)       ((l->brd_type == KLTYPE_BASEIO) && \
-                                 (l->brd_flags & SECOND_NIC_PRESENT))
-#define IS_MIO_IOC3(l, n)       (IS_MIO_PRESENT(l) && (n > 2))
-
-/*
- * board structures
- */
-
-#define MAX_COMPTS_PER_BRD 24
-
-#define LOCAL_BOARD 1
-#define REMOTE_BOARD 2
-
-#define LBOARD_STRUCT_VERSION   2
-
-typedef struct lboard_s {
-        klconf_off_t    brd_next;         /* Next BOARD */
-        unsigned char   struct_type;      /* type of structure, local or remote */
-        unsigned char   brd_type;         /* type+class */
-        unsigned char   brd_sversion;     /* version of this structure */
-        unsigned char   brd_brevision;    /* board revision */
-        unsigned char   brd_promver;      /* board prom version, if any */
-        unsigned char   brd_flags;        /* Enabled, Disabled etc */
-        unsigned char   brd_slot;         /* slot number */
-        unsigned short  brd_debugsw;      /* Debug switches */
-        moduleid_t      brd_module;       /* module to which it belongs */
-        partid_t        brd_partition;    /* Partition number */
-        unsigned short  brd_diagval;      /* diagnostic value */
-        unsigned short  brd_diagparm;     /* diagnostic parameter */
-        unsigned char   brd_inventory;    /* inventory history */
-        unsigned char   brd_numcompts;    /* Number of components */
-        nic_t           brd_nic;          /* Number in CAN */
-        nasid_t         brd_nasid;        /* passed parameter */
-        klconf_off_t    brd_compts[MAX_COMPTS_PER_BRD]; /* pointers to COMPONENTS */
-        klconf_off_t    brd_errinfo;      /* Board's error information */
-        struct lboard_s *brd_parent;      /* Logical parent for this brd */
-        vertex_hdl_t    brd_graph_link;   /* vertex hdl to connect extern compts */
-        confidence_t    brd_confidence;   /* confidence that the board is bad */
-        nasid_t         brd_owner;        /* who owns this board */
-        unsigned char   brd_nic_flags;    /* To handle 8 more NICs */
-        char            brd_name[32];
-} lboard_t;
-
-
-/*
- *      Make sure we pass back the calias space address for local boards.
- *      klconfig board traversal and error structure extraction defines.
- */
-
-#define BOARD_SLOT(_brd)        ((_brd)->brd_slot)
-
-#define KLCF_CLASS(_brd)        KLCLASS((_brd)->brd_type)
-#define KLCF_TYPE(_brd)         KLTYPE((_brd)->brd_type)
-#define KLCF_REMOTE(_brd)       (((_brd)->struct_type & LOCAL_BOARD) ? 0 : 1)
-#define KLCF_NUM_COMPS(_brd)    ((_brd)->brd_numcompts)
-#define KLCF_MODULE_ID(_brd)    ((_brd)->brd_module)
-
-#define KLCF_NEXT(_brd)         \
-        ((_brd)->brd_next ?     \
-         (lboard_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), (_brd)->brd_next)):\
-         NULL)
-#define KLCF_COMP(_brd, _ndx)   \
-                (klinfo_t *)(NODE_OFFSET_TO_K1(NASID_GET(_brd), \
-                                               (_brd)->brd_compts[(_ndx)]))
-
-#define KLCF_COMP_ERROR(_brd, _comp)    \
-               (NODE_OFFSET_TO_K1(NASID_GET(_brd), (_comp)->errinfo))
-
-#define KLCF_COMP_TYPE(_comp)   ((_comp)->struct_type)
-#define KLCF_BRIDGE_W_ID(_comp) ((_comp)->physid)       /* Widget ID */
-
-
-
-/*
- * Generic info structure. This stores common info about a
- * component.
- */
-
-typedef struct klinfo_s {                  /* Generic info */
-        unsigned char   struct_type;       /* type of this structure */
-        unsigned char   struct_version;    /* version of this structure */
-        unsigned char   flags;            /* Enabled, disabled etc */
-        unsigned char   revision;         /* component revision */
-        unsigned short  diagval;          /* result of diagnostics */
-        unsigned short  diagparm;         /* diagnostic parameter */
-        unsigned char   inventory;        /* previous inventory status */
-        nic_t           nic;              /* MUst be aligned properly */
-        unsigned char   physid;           /* physical id of component */
-        unsigned int    virtid;           /* virtual id as seen by system */
-        unsigned char   widid;            /* Widget id - if applicable */
-        nasid_t         nasid;            /* node number - from parent */
-        char            pad1;             /* pad out structure. */
-        char            pad2;             /* pad out structure. */
-        COMPONENT       *arcs_compt;      /* ptr to the arcs struct for ease*/
-        klconf_off_t    errinfo;          /* component specific errors */
-        unsigned short  pad3;             /* pci fields have moved over to */
-        unsigned short  pad4;             /* klbri_t */
-} klinfo_t ;
-
-#define KLCONFIG_INFO_ENABLED(_i)       ((_i)->flags & KLINFO_ENABLE)
-/*
- * Component structures.
- * Following are the currently identified components:
- *      CPU, HUB, MEM_BANK,
- *      XBOW(consists of 16 WIDGETs, each of which can be HUB or GRAPHICS or BRIDGE)
- *      BRIDGE, IOC3, SuperIO, SCSI, FDDI
- *      ROUTER
- *      GRAPHICS
- */
-#define KLSTRUCT_UNKNOWN        0
-#define KLSTRUCT_CPU            1
-#define KLSTRUCT_HUB            2
-#define KLSTRUCT_MEMBNK         3
-#define KLSTRUCT_XBOW           4
-#define KLSTRUCT_BRI            5
-#define KLSTRUCT_IOC3           6
-#define KLSTRUCT_PCI            7
-#define KLSTRUCT_VME            8
-#define KLSTRUCT_ROU            9
-#define KLSTRUCT_GFX            10
-#define KLSTRUCT_SCSI           11
-#define KLSTRUCT_FDDI           12
-#define KLSTRUCT_MIO            13
-#define KLSTRUCT_DISK           14
-#define KLSTRUCT_TAPE           15
-#define KLSTRUCT_CDROM          16
-#define KLSTRUCT_HUB_UART       17
-#define KLSTRUCT_IOC3ENET       18
-#define KLSTRUCT_IOC3UART       19
-#define KLSTRUCT_UNUSED         20 /* XXX UNUSED */
-#define KLSTRUCT_IOC3PCKM       21
-#define KLSTRUCT_RAD            22
-#define KLSTRUCT_HUB_TTY        23
-#define KLSTRUCT_IOC3_TTY       24
-
-/* Early Access IO proms are compatible
-   only with KLSTRUCT values upto 24. */
-
-#define KLSTRUCT_FIBERCHANNEL   25
-#define KLSTRUCT_MOD_SERIAL_NUM 26
-#define KLSTRUCT_IOC3MS         27
-#define KLSTRUCT_TPU            28
-#define KLSTRUCT_GSN_A          29
-#define KLSTRUCT_GSN_B          30
-#define KLSTRUCT_XTHD           31
-
-/*
- * These are the indices of various components within a lboard structure.
- */
-
-#define IP27_CPU0_INDEX 0
-#define IP27_CPU1_INDEX 1
-#define IP27_HUB_INDEX 2
-#define IP27_MEM_INDEX 3
-
-#define BASEIO_BRIDGE_INDEX 0
-#define BASEIO_IOC3_INDEX 1
-#define BASEIO_SCSI1_INDEX 2
-#define BASEIO_SCSI2_INDEX 3
-
-#define MIDPLANE_XBOW_INDEX 0
-#define ROUTER_COMPONENT_INDEX 0
-
-#define CH4SCSI_BRIDGE_INDEX 0
-
-/* Info holders for various hardware components */
-
-typedef u64 *pci_t;
-typedef u64 *vmeb_t;
-typedef u64 *vmed_t;
-typedef u64 *fddi_t;
-typedef u64 *scsi_t;
-typedef u64 *mio_t;
-typedef u64 *graphics_t;
-typedef u64 *router_t;
-
-/*
- * The port info in ip27_cfg area translates to a lboart_t in the
- * KLCONFIG area. But since KLCONFIG does not use pointers, lboart_t
- * is stored in terms of a nasid and a offset from start of KLCONFIG
- * area  on that nasid.
- */
-typedef struct klport_s {
-        nasid_t         port_nasid;
-        unsigned char   port_flag;
-        klconf_off_t    port_offset;
-} klport_t;
-
-typedef struct klcpu_s {                          /* CPU */
-        klinfo_t        cpu_info;
-        unsigned short  cpu_prid;       /* Processor PRID value */
-        unsigned short  cpu_fpirr;      /* FPU IRR value */
-        unsigned short  cpu_speed;      /* Speed in MHZ */
-        unsigned short  cpu_scachesz;   /* secondary cache size in MB */
-        unsigned short  cpu_scachespeed;/* secondary cache speed in MHz */
-} klcpu_t ;
-
-#define CPU_STRUCT_VERSION   2
-
-typedef struct klhub_s {                        /* HUB */
-        klinfo_t        hub_info;
-        unsigned int            hub_flags;              /* PCFG_HUB_xxx flags */
-        klport_t        hub_port;               /* hub is connected to this */
-        nic_t           hub_box_nic;            /* nic of containing box */
-        klconf_off_t    hub_mfg_nic;            /* MFG NIC string */
-        u64             hub_speed;              /* Speed of hub in HZ */
-} klhub_t ;
-
-typedef struct klhub_uart_s {                   /* HUB */
-        klinfo_t        hubuart_info;
-        unsigned int            hubuart_flags;          /* PCFG_HUB_xxx flags */
-        nic_t           hubuart_box_nic;        /* nic of containing box */
-} klhub_uart_t ;
-
-#define MEMORY_STRUCT_VERSION   2
-
-typedef struct klmembnk_s {                     /* MEMORY BANK */
-        klinfo_t        membnk_info;
-        short           membnk_memsz;           /* Total memory in megabytes */
-        short           membnk_dimm_select; /* bank to physical addr mapping*/
-        short           membnk_bnksz[MD_MEM_BANKS]; /* Memory bank sizes */
-        short           membnk_attr;
-} klmembnk_t ;
-
-#define KLCONFIG_MEMBNK_SIZE(_info, _bank)      \
-                            ((_info)->membnk_bnksz[(_bank)])
-
-
-#define MEMBNK_PREMIUM 1
-#define KLCONFIG_MEMBNK_PREMIUM(_info, _bank)   \
-                            ((_info)->membnk_attr & (MEMBNK_PREMIUM << (_bank)))
-
-#define MAX_SERIAL_NUM_SIZE 10
-
-typedef struct klmod_serial_num_s {
-      klinfo_t        snum_info;
-      union {
-              char snum_str[MAX_SERIAL_NUM_SIZE];
-              unsigned long long       snum_int;
-      } snum;
-} klmod_serial_num_t;
-
-/* Macros needed to access serial number structure in lboard_t.
-   Hard coded values are necessary since we cannot treat
-   serial number struct as a component without losing compatibility
-   between prom versions. */
-
-#define GET_SNUM_COMP(_l)       ((klmod_serial_num_t *)\
-                                KLCF_COMP(_l, _l->brd_numcompts))
-
-#define MAX_XBOW_LINKS 16
-
-typedef struct klxbow_s {                          /* XBOW */
-        klinfo_t        xbow_info ;
-        klport_t        xbow_port_info[MAX_XBOW_LINKS] ; /* Module number */
-        int             xbow_master_hub_link;
-        /* type of brd connected+component struct ptr+flags */
-} klxbow_t ;
-
-#define MAX_PCI_SLOTS 8
-
-typedef struct klpci_device_s {
-        s32     pci_device_id;  /* 32 bits of vendor/device ID. */
-        s32     pci_device_pad; /* 32 bits of padding. */
-} klpci_device_t;
-
-#define BRIDGE_STRUCT_VERSION   2
-
-typedef struct klbri_s {                          /* BRIDGE */
-        klinfo_t        bri_info ;
-        unsigned char   bri_eprominfo ;    /* IO6prom connected to bridge */
-        unsigned char   bri_bustype ;      /* PCI/VME BUS bridge/GIO */
-        pci_t           pci_specific  ;    /* PCI Board config info */
-        klpci_device_t  bri_devices[MAX_PCI_DEVS] ;     /* PCI IDs */
-        klconf_off_t    bri_mfg_nic ;
-} klbri_t ;
-
-#define MAX_IOC3_TTY    2
-
-typedef struct klioc3_s {                          /* IOC3 */
-        klinfo_t        ioc3_info ;
-        unsigned char   ioc3_ssram ;        /* Info about ssram */
-        unsigned char   ioc3_nvram ;        /* Info about nvram */
-        klinfo_t        ioc3_superio ;      /* Info about superio */
-        klconf_off_t    ioc3_tty_off ;
-        klinfo_t        ioc3_enet ;
-        klconf_off_t    ioc3_enet_off ;
-        klconf_off_t    ioc3_kbd_off ;
-} klioc3_t ;
-
-#define MAX_VME_SLOTS 8
-
-typedef struct klvmeb_s {                          /* VME BRIDGE - PCI CTLR */
-        klinfo_t        vmeb_info ;
-        vmeb_t          vmeb_specific ;
-        klconf_off_t    vmeb_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
-} klvmeb_t ;
-
-typedef struct klvmed_s {                          /* VME DEVICE - VME BOARD */
-        klinfo_t        vmed_info ;
-        vmed_t          vmed_specific ;
-        klconf_off_t    vmed_brdinfo[MAX_VME_SLOTS]   ;    /* VME Board config info */
-} klvmed_t ;
-
-#define ROUTER_VECTOR_VERS      2
-
-/* XXX - Don't we need the number of ports here?!? */
-typedef struct klrou_s {                          /* ROUTER */
-        klinfo_t        rou_info ;
-        unsigned int            rou_flags ;           /* PCFG_ROUTER_xxx flags */
-        nic_t           rou_box_nic ;         /* nic of the containing module */
-        klport_t        rou_port[MAX_ROUTER_PORTS + 1] ; /* array index 1 to 6 */
-        klconf_off_t    rou_mfg_nic ;     /* MFG NIC string */
-        u64     rou_vector;       /* vector from master node */
-} klrou_t ;
-
-/*
- *  Graphics Controller/Device
- *
- *  (IP27/IO6) Prom versions 6.13 (and 6.5.1 kernels) and earlier
- *  used a couple different structures to store graphics information.
- *  For compatibility reasons, the newer data structure preserves some
- *  of the layout so that fields that are used in the old versions remain
- *  in the same place (with the same info).  Determination of what version
- *  of this structure we have is done by checking the cookie field.
- */
-#define KLGFX_COOKIE    0x0c0de000
-
-typedef struct klgfx_s {                /* GRAPHICS Device */
-        klinfo_t        gfx_info;
-        klconf_off_t    old_gndevs;     /* for compatibility with older proms */
-        klconf_off_t    old_gdoff0;     /* for compatibility with older proms */
-        unsigned int            cookie;         /* for compatibility with older proms */
-        unsigned int            moduleslot;
-        struct klgfx_s  *gfx_next_pipe;
-        graphics_t      gfx_specific;
-        klconf_off_t    pad0;           /* for compatibility with older proms */
-        klconf_off_t    gfx_mfg_nic;
-} klgfx_t;
-
-typedef struct klxthd_s {
-        klinfo_t        xthd_info ;
-        klconf_off_t    xthd_mfg_nic ;        /* MFG NIC string */
-} klxthd_t ;
-
-typedef struct kltpu_s {                     /* TPU board */
-        klinfo_t        tpu_info ;
-        klconf_off_t    tpu_mfg_nic ;        /* MFG NIC string */
-} kltpu_t ;
-
-typedef struct klgsn_s {                     /* GSN board */
-        klinfo_t        gsn_info ;
-        klconf_off_t    gsn_mfg_nic ;        /* MFG NIC string */
-} klgsn_t ;
-
-#define MAX_SCSI_DEVS 16
-
-/*
- * NOTE: THis is the max sized kl* structure and is used in klmalloc.c
- * to allocate space of type COMPONENT. Make sure that if the size of
- * any other component struct becomes more than this, then redefine
- * that as the size to be klmalloced.
- */
-
-typedef struct klscsi_s {                          /* SCSI Controller */
-        klinfo_t        scsi_info ;
-        scsi_t          scsi_specific   ;
-        unsigned char   scsi_numdevs ;
-        klconf_off_t    scsi_devinfo[MAX_SCSI_DEVS] ;
-} klscsi_t ;
-
-typedef struct klscdev_s {                          /* SCSI device */
-        klinfo_t        scdev_info ;
-        struct scsidisk_data *scdev_cfg ; /* driver fills up this */
-} klscdev_t ;
-
-typedef struct klttydev_s {                          /* TTY device */
-        klinfo_t        ttydev_info ;
-        struct terminal_data *ttydev_cfg ; /* driver fills up this */
-} klttydev_t ;
-
-typedef struct klenetdev_s {                          /* ENET device */
-        klinfo_t        enetdev_info ;
-        struct net_data *enetdev_cfg ; /* driver fills up this */
-} klenetdev_t ;
-
-typedef struct klkbddev_s {                          /* KBD device */
-        klinfo_t        kbddev_info ;
-        struct keyboard_data *kbddev_cfg ; /* driver fills up this */
-} klkbddev_t ;
-
-typedef struct klmsdev_s {                          /* mouse device */
-        klinfo_t        msdev_info ;
-        void            *msdev_cfg ;
-} klmsdev_t ;
-
-#define MAX_FDDI_DEVS 10 /* XXX Is this true */
-
-typedef struct klfddi_s {                          /* FDDI */
-        klinfo_t        fddi_info ;
-        fddi_t          fddi_specific ;
-        klconf_off_t    fddi_devinfo[MAX_FDDI_DEVS] ;
-} klfddi_t ;
-
-typedef struct klmio_s {                          /* MIO */
-        klinfo_t        mio_info ;
-        mio_t           mio_specific   ;
-} klmio_t ;
-
-
-typedef union klcomp_s {
-        klcpu_t         kc_cpu;
-        klhub_t         kc_hub;
-        klmembnk_t      kc_mem;
-        klxbow_t        kc_xbow;
-        klbri_t         kc_bri;
-        klioc3_t        kc_ioc3;
-        klvmeb_t        kc_vmeb;
-        klvmed_t        kc_vmed;
-        klrou_t         kc_rou;
-        klgfx_t         kc_gfx;
-        klscsi_t        kc_scsi;
-        klscdev_t       kc_scsi_dev;
-        klfddi_t        kc_fddi;
-        klmio_t         kc_mio;
-        klmod_serial_num_t kc_snum ;
-} klcomp_t;
-
-typedef union kldev_s {      /* for device structure allocation */
-        klscdev_t       kc_scsi_dev ;
-        klttydev_t      kc_tty_dev ;
-        klenetdev_t     kc_enet_dev ;
-        klkbddev_t      kc_kbd_dev ;
-} kldev_t ;
-
-/* Data structure interface routines. TBD */
-
-/* Include launch info in this file itself? TBD */
-
-/*
- * TBD - Can the ARCS and device driver related info also be included in the
- * KLCONFIG area. On the IO4PROM, prom device driver info is part of cfgnode_t
- * structure, viz private to the IO4prom.
- */
-
-/*
- * TBD - Allocation issues.
- *
- * Do we need to Mark off sepatate heaps for lboard_t, rboard_t, component,
- * errinfo and allocate from them, or have a single heap and allocate all
- * structures from it. Debug is easier in the former method since we can
- * dump all similar structs in one command, but there will be lots of holes,
- * in memory and max limits are needed for number of structures.
- * Another way to make it organized, is to have a union of all components
- * and allocate a aligned chunk of memory greater than the biggest
- * component.
- */
-
-typedef union {
-        lboard_t *lbinfo ;
-} biptr_t ;
-
-
-#define BRI_PER_XBOW 6
-#define PCI_PER_BRI  8
-#define DEV_PER_PCI  16
-
-
-/* Virtual dipswitch values (starting from switch "7"): */
-
-#define VDS_NOGFX               0x8000  /* Don't enable gfx and autoboot */
-#define VDS_NOMP                0x100   /* Don't start slave processors */
-#define VDS_MANUMODE            0x80    /* Manufacturing mode */
-#define VDS_NOARB               0x40    /* No bootmaster arbitration */
-#define VDS_PODMODE             0x20    /* Go straight to POD mode */
-#define VDS_NO_DIAGS            0x10    /* Don't run any diags after BM arb */
-#define VDS_DEFAULTS            0x08    /* Use default environment values */
-#define VDS_NOMEMCLEAR          0x04    /* Don't run mem cfg code */
-#define VDS_2ND_IO4             0x02    /* Boot from the second IO4 */
-#define VDS_DEBUG_PROM          0x01    /* Print PROM debugging messages */
-
-/* external declarations of Linux kernel functions. */
-
-extern lboard_t *find_lboard(lboard_t *start, unsigned char type);
-extern klinfo_t *find_component(lboard_t *brd, klinfo_t *kli, unsigned char type);
-extern klinfo_t *find_first_component(lboard_t *brd, unsigned char type);
-extern klcpu_t *nasid_slice_to_cpuinfo(nasid_t, int);
-extern lboard_t *find_lboard_class(lboard_t *start, unsigned char brd_class);
-
-
-extern klcpu_t *sn_get_cpuinfo(cpuid_t cpu);
-
-#endif /* _ASM_SN_KLCONFIG_H */
diff --git a/include/asm-mips/sn/kldir.h b/include/asm-mips/sn/kldir.h
deleted file mode 100644
index 1327e12e9645..000000000000
--- a/include/asm-mips/sn/kldir.h
+++ /dev/null
@@ -1,217 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/kldir.h>, revision 1.21.
- *
- * Copyright (C) 1992 - 1997, 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 1999, 2000 by Ralf Baechle
- */
-#ifndef _ASM_SN_KLDIR_H
-#define _ASM_SN_KLDIR_H
-
-
-/*
- * The kldir memory area resides at a fixed place in each node's memory and
- * provides pointers to most other IP27 memory areas.  This allows us to
- * resize and/or relocate memory areas at a later time without breaking all
- * firmware and kernels that use them.  Indices in the array are
- * permanently dedicated to areas listed below.  Some memory areas (marked
- * below) reside at a permanently fixed location, but are included in the
- * directory for completeness.
- */
-
-#define KLDIR_MAGIC             0x434d5f53505f5357
-
-/*
- * The upper portion of the memory map applies during boot
- * only and is overwritten by IRIX/SYMMON.
- *
- *                                    MEMORY MAP PER NODE
- *
- * 0x2000000 (32M)         +-----------------------------------------+
- *                         |      IO6 BUFFERS FOR FLASH ENET IOC3    |
- * 0x1F80000 (31.5M)       +-----------------------------------------+
- *                         |      IO6 TEXT/DATA/BSS/stack            |
- * 0x1C00000 (30M)         +-----------------------------------------+
- *                         |      IO6 PROM DEBUG TEXT/DATA/BSS/stack |
- * 0x0800000 (28M)         +-----------------------------------------+
- *                         |      IP27 PROM TEXT/DATA/BSS/stack      |
- * 0x1B00000 (27M)         +-----------------------------------------+
- *                         |      IP27 CFG                           |
- * 0x1A00000 (26M)         +-----------------------------------------+
- *                         |      Graphics PROM                      |
- * 0x1800000 (24M)         +-----------------------------------------+
- *                         |      3rd Party PROM drivers             |
- * 0x1600000 (22M)         +-----------------------------------------+
- *                         |                                         |
- *                         |      Free                               |
- *                         |                                         |
- *                         +-----------------------------------------+
- *                         |      UNIX DEBUG Version                 |
- * 0x190000 (2M--)         +-----------------------------------------+
- *                         |      SYMMON                             |
- *                         |      (For UNIX Debug only)              |
- * 0x34000 (208K)          +-----------------------------------------+
- *                         |      SYMMON STACK [NUM_CPU_PER_NODE]    |
- *                         |      (For UNIX Debug only)              |
- * 0x25000 (148K)          +-----------------------------------------+
- *                         |      KLCONFIG - II (temp)               |
- *                         |                                         |
- *                         |    ----------------------------         |
- *                         |                                         |
- *                         |      UNIX NON-DEBUG Version             |
- * 0x19000 (100K)          +-----------------------------------------+
- *
- *
- * The lower portion of the memory map contains information that is
- * permanent and is used by the IP27PROM, IO6PROM and IRIX.
- *
- * 0x19000 (100K)          +-----------------------------------------+
- *                         |                                         |
- *                         |      PI Error Spools (32K)              |
- *                         |                                         |
- * 0x12000 (72K)           +-----------------------------------------+
- *                         |      Unused                             |
- * 0x11c00 (71K)           +-----------------------------------------+
- *                         |      CPU 1 NMI Eframe area              |
- * 0x11a00 (70.5K)         +-----------------------------------------+
- *                         |      CPU 0 NMI Eframe area              |
- * 0x11800 (70K)           +-----------------------------------------+
- *                         |      CPU 1 NMI Register save area       |
- * 0x11600 (69.5K)         +-----------------------------------------+
- *                         |      CPU 0 NMI Register save area       |
- * 0x11400 (69K)           +-----------------------------------------+
- *                         |      GDA (1k)                           |
- * 0x11000 (68K)           +-----------------------------------------+
- *                         |      Early cache Exception stack        |
- *                         |             and/or                      |
- *                         |      kernel/io6prom nmi registers       |
- * 0x10800  (66k)          +-----------------------------------------+
- *                         |      cache error eframe                 |
- * 0x10400 (65K)           +-----------------------------------------+
- *                         |      Exception Handlers (UALIAS copy)   |
- * 0x10000 (64K)           +-----------------------------------------+
- *                         |                                         |
- *                         |                                         |
- *                         |      KLCONFIG - I (permanent) (48K)     |
- *                         |                                         |
- *                         |                                         |
- *                         |                                         |
- * 0x4000 (16K)            +-----------------------------------------+
- *                         |      NMI Handler (Protected Page)       |
- * 0x3000 (12K)            +-----------------------------------------+
- *                         |      ARCS PVECTORS (master node only)   |
- * 0x2c00 (11K)            +-----------------------------------------+
- *                         |      ARCS TVECTORS (master node only)   |
- * 0x2800 (10K)            +-----------------------------------------+
- *                         |      LAUNCH [NUM_CPU]                   |
- * 0x2400 (9K)             +-----------------------------------------+
- *                         |      Low memory directory (KLDIR)       |
- * 0x2000 (8K)             +-----------------------------------------+
- *                         |      ARCS SPB (1K)                      |
- * 0x1000 (4K)             +-----------------------------------------+
- *                         |      Early cache Exception stack        |
- *                         |             and/or                      |
- *                         |      kernel/io6prom nmi registers       |
- * 0x800  (2k)             +-----------------------------------------+
- *                         |      cache error eframe                 |
- * 0x400 (1K)              +-----------------------------------------+
- *                         |      Exception Handlers                 |
- * 0x0   (0K)              +-----------------------------------------+
- */
-
-#ifdef __ASSEMBLY__
-#define KLDIR_OFF_MAGIC                 0x00
-#define KLDIR_OFF_OFFSET                0x08
-#define KLDIR_OFF_POINTER               0x10
-#define KLDIR_OFF_SIZE                  0x18
-#define KLDIR_OFF_COUNT                 0x20
-#define KLDIR_OFF_STRIDE                0x28
-#endif /* __ASSEMBLY__ */
-
-/*
- * This is defined here because IP27_SYMMON_STK_SIZE must be at least what
- * we define here.  Since it's set up in the prom.  We can't redefine it later
- * and expect more space to be allocated.  The way to find out the true size
- * of the symmon stacks is to divide SYMMON_STK_SIZE by SYMMON_STK_STRIDE
- * for a particular node.
- */
-#define SYMMON_STACK_SIZE               0x8000
-
-#if defined(PROM)
-
-/*
- * These defines are prom version dependent.  No code other than the IP27
- * prom should attempt to use these values.
- */
-#define IP27_LAUNCH_OFFSET              0x2400
-#define IP27_LAUNCH_SIZE                0x400
-#define IP27_LAUNCH_COUNT               2
-#define IP27_LAUNCH_STRIDE              0x200
-
-#define IP27_KLCONFIG_OFFSET            0x4000
-#define IP27_KLCONFIG_SIZE              0xc000
-#define IP27_KLCONFIG_COUNT             1
-#define IP27_KLCONFIG_STRIDE            0
-
-#define IP27_NMI_OFFSET                 0x3000
-#define IP27_NMI_SIZE                   0x40
-#define IP27_NMI_COUNT                  2
-#define IP27_NMI_STRIDE                 0x40
-
-#define IP27_PI_ERROR_OFFSET            0x12000
-#define IP27_PI_ERROR_SIZE              0x4000
-#define IP27_PI_ERROR_COUNT             1
-#define IP27_PI_ERROR_STRIDE            0
-
-#define IP27_SYMMON_STK_OFFSET          0x25000
-#define IP27_SYMMON_STK_SIZE            0xe000
-#define IP27_SYMMON_STK_COUNT           2
-/* IP27_SYMMON_STK_STRIDE must be >= SYMMON_STACK_SIZE */
-#define IP27_SYMMON_STK_STRIDE          0x7000
-
-#define IP27_FREEMEM_OFFSET             0x19000
-#define IP27_FREEMEM_SIZE               -1
-#define IP27_FREEMEM_COUNT              1
-#define IP27_FREEMEM_STRIDE             0
-
-#endif /* PROM */
-/*
- * There will be only one of these in a partition so the IO6 must set it up.
- */
-#define IO6_GDA_OFFSET                  0x11000
-#define IO6_GDA_SIZE                    0x400
-#define IO6_GDA_COUNT                   1
-#define IO6_GDA_STRIDE                  0
-
-/*
- * save area of kernel nmi regs in the prom format
- */
-#define IP27_NMI_KREGS_OFFSET           0x11400
-#define IP27_NMI_KREGS_CPU_SIZE         0x200
-/*
- * save area of kernel nmi regs in eframe format
- */
-#define IP27_NMI_EFRAME_OFFSET          0x11800
-#define IP27_NMI_EFRAME_SIZE            0x200
-
-#define KLDIR_ENT_SIZE                  0x40
-#define KLDIR_MAX_ENTRIES               (0x400 / 0x40)
-
-#ifndef __ASSEMBLY__
-typedef struct kldir_ent_s {
-        u64             magic;          /* Indicates validity of entry      */
-        off_t           offset;         /* Offset from start of node space  */
-        unsigned long   pointer;        /* Pointer to area in some cases    */
-        size_t          size;           /* Size in bytes                    */
-        u64             count;          /* Repeat count if array, 1 if not  */
-        size_t          stride;         /* Stride if array, 0 if not        */
-        char            rsvd[16];       /* Pad entry to 0x40 bytes          */
-        /* NOTE: These 16 bytes are used in the Partition KLDIR
-           entry to store partition info. Refer to klpart.h for this. */
-} kldir_ent_t;
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_SN_KLDIR_H */
diff --git a/include/asm-mips/sn/klkernvars.h b/include/asm-mips/sn/klkernvars.h
deleted file mode 100644
index 5de4c5e8ab30..000000000000
--- a/include/asm-mips/sn/klkernvars.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * File ported from IRIX to Linux by Kanoj Sarcar, 06/08/00.
- * Copyright 2000 Silicon Graphics, Inc.
- */
-#ifndef __ASM_SN_KLKERNVARS_H
-#define __ASM_SN_KLKERNVARS_H
-
-#define KV_MAGIC_OFFSET         0x0
-#define KV_RO_NASID_OFFSET      0x4
-#define KV_RW_NASID_OFFSET      0x6
-
-#define KV_MAGIC                0x5f4b565f
-
-#ifndef __ASSEMBLY__
-
-#include <asm/sn/types.h>
-
-typedef struct kern_vars_s {
-        int             kv_magic;
-        nasid_t         kv_ro_nasid;
-        nasid_t         kv_rw_nasid;
-        unsigned long   kv_ro_baseaddr;
-        unsigned long   kv_rw_baseaddr;
-} kern_vars_t;
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* __ASM_SN_KLKERNVARS_H */
-
diff --git a/include/asm-mips/sn/launch.h b/include/asm-mips/sn/launch.h
deleted file mode 100644
index b7c2226312c6..000000000000
--- a/include/asm-mips/sn/launch.h
+++ /dev/null
@@ -1,106 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2000 by Colin Ngam
- */
-#ifndef _ASM_SN_LAUNCH_H
-#define _ASM_SN_LAUNCH_H
-
-#include <asm/sn/types.h>
-#include <asm/sn/addrs.h>
-
-/*
- * The launch data structure resides at a fixed place in each node's memory
- * and is used to communicate between the master processor and the slave
- * processors.
- *
- * The master stores launch parameters in the launch structure
- * corresponding to a target processor that is in a slave loop, then sends
- * an interrupt to the slave processor.  The slave calls the desired
- * function, then returns to the slave loop.  The master may poll or wait
- * for the slaves to finish.
- *
- * There is an array of launch structures, one per CPU on the node.  One
- * interrupt level is used per local CPU.
- */
-
-#define LAUNCH_MAGIC            0xaddbead2addbead3
-#ifdef CONFIG_SGI_IP27
-#define LAUNCH_SIZEOF           0x100
-#define LAUNCH_PADSZ            0xa0
-#endif
-
-#define LAUNCH_OFF_MAGIC        0x00    /* Struct offsets for assembly      */
-#define LAUNCH_OFF_BUSY         0x08
-#define LAUNCH_OFF_CALL         0x10
-#define LAUNCH_OFF_CALLC        0x18
-#define LAUNCH_OFF_CALLPARM     0x20
-#define LAUNCH_OFF_STACK        0x28
-#define LAUNCH_OFF_GP           0x30
-#define LAUNCH_OFF_BEVUTLB      0x38
-#define LAUNCH_OFF_BEVNORMAL    0x40
-#define LAUNCH_OFF_BEVECC       0x48
-
-#define LAUNCH_STATE_DONE       0       /* Return value of LAUNCH_POLL      */
-#define LAUNCH_STATE_SENT       1
-#define LAUNCH_STATE_RECD       2
-
-/*
- * The launch routine is called only if the complement address is correct.
- *
- * Before control is transferred to a routine, the complement address
- * is zeroed (invalidated) to prevent an accidental call from a spurious
- * interrupt.
- *
- * The slave_launch routine turns on the BUSY flag, and the slave loop
- * clears the BUSY flag after control is returned to it.
- */
-
-#ifndef __ASSEMBLY__
-
-typedef int launch_state_t;
-typedef void (*launch_proc_t)(u64 call_parm);
-
-typedef struct launch_s {
-        volatile u64            magic;  /* Magic number                     */
-        volatile u64            busy;   /* Slave currently active           */
-        volatile launch_proc_t  call_addr;      /* Func. for slave to call  */
-        volatile u64            call_addr_c;    /* 1's complement of call_addr*/
-        volatile u64            call_parm;      /* Single parm passed to call*/
-        volatile void *stack_addr;      /* Stack pointer for slave function */
-        volatile void *gp_addr;         /* Global pointer for slave func.   */
-        volatile char           *bevutlb;/* Address of bev utlb ex handler   */
-        volatile char           *bevnormal;/*Address of bev normal ex handler */
-        volatile char           *bevecc;/* Address of bev cache err handler */
-        volatile char           pad[160];       /* Pad to LAUNCH_SIZEOF     */
-} launch_t;
-
-/*
- * PROM entry points for launch routines are determined by IPxxprom/start.s
- */
-
-#define LAUNCH_SLAVE    (*(void (*)(int nasid, int cpu, \
-                                    launch_proc_t call_addr, \
-                                    u64 call_parm, \
-                                    void *stack_addr, \
-                                    void *gp_addr)) \
-                         IP27PROM_LAUNCHSLAVE)
-
-#define LAUNCH_WAIT     (*(void (*)(int nasid, int cpu, int timeout_msec)) \
-                         IP27PROM_WAITSLAVE)
-
-#define LAUNCH_POLL     (*(launch_state_t (*)(int nasid, int cpu)) \
-                         IP27PROM_POLLSLAVE)
-
-#define LAUNCH_LOOP     (*(void (*)(void)) \
-                         IP27PROM_SLAVELOOP)
-
-#define LAUNCH_FLASH    (*(void (*)(void)) \
-                         IP27PROM_FLASHLEDS)
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_SN_LAUNCH_H */
diff --git a/include/asm-mips/sn/mapped_kernel.h b/include/asm-mips/sn/mapped_kernel.h
deleted file mode 100644
index c3dd5d0d525f..000000000000
--- a/include/asm-mips/sn/mapped_kernel.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * File created by Kanoj Sarcar 06/06/00.
- * Copyright 2000 Silicon Graphics, Inc.
- */
-#ifndef __ASM_SN_MAPPED_KERNEL_H
-#define __ASM_SN_MAPPED_KERNEL_H
-
-/*
- * Note on how mapped kernels work: the text and data section is
- * compiled at cksseg segment (LOADADDR = 0xc001c000), and the
- * init/setup/data section gets a 16M virtual address bump in the
- * ld.script file (so that tlblo0 and tlblo1 maps the sections).
- * The vmlinux.64 section addresses are put in the xkseg range
- * using the change-addresses makefile option. Use elfdump -of
- * on IRIX to see where the sections go. The Origin loader loads
- * the two sections contiguously in physical memory. The loader
- * sets the entry point into kernel_entry using a xkphys address,
- * but instead of using 0xa800000001160000, it uses the address
- * 0xa800000000160000, which is where it physically loaded that
- * code. So no jumps can be done before we have switched to using
- * cksseg addresses.
- */
-#include <asm/addrspace.h>
-
-#define REP_BASE        CAC_BASE
-
-#ifdef CONFIG_MAPPED_KERNEL
-
-#define MAPPED_ADDR_RO_TO_PHYS(x)       (x - REP_BASE)
-#define MAPPED_ADDR_RW_TO_PHYS(x)       (x - REP_BASE - 16777216)
-
-#define MAPPED_KERN_RO_PHYSBASE(n) \
-                        (PLAT_NODE_DATA(n)->kern_vars.kv_ro_baseaddr)
-#define MAPPED_KERN_RW_PHYSBASE(n) \
-                        (PLAT_NODE_DATA(n)->kern_vars.kv_rw_baseaddr)
-
-#define MAPPED_KERN_RO_TO_PHYS(x) \
-                                ((unsigned long)MAPPED_ADDR_RO_TO_PHYS(x) | \
-                                MAPPED_KERN_RO_PHYSBASE(get_compact_nodeid()))
-#define MAPPED_KERN_RW_TO_PHYS(x) \
-                                ((unsigned long)MAPPED_ADDR_RW_TO_PHYS(x) | \
-                                MAPPED_KERN_RW_PHYSBASE(get_compact_nodeid()))
-
-#else /* CONFIG_MAPPED_KERNEL */
-
-#define MAPPED_KERN_RO_TO_PHYS(x)       (x - REP_BASE)
-#define MAPPED_KERN_RW_TO_PHYS(x)       (x - REP_BASE)
-
-#endif /* CONFIG_MAPPED_KERNEL */
-
-#define MAPPED_KERN_RO_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RO_TO_PHYS(x))
-#define MAPPED_KERN_RW_TO_K0(x) PHYS_TO_K0(MAPPED_KERN_RW_TO_PHYS(x))
-
-#endif /* __ASM_SN_MAPPED_KERNEL_H  */
diff --git a/include/asm-mips/sn/nmi.h b/include/asm-mips/sn/nmi.h
deleted file mode 100644
index 6b7b0b5f3729..000000000000
--- a/include/asm-mips/sn/nmi.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997 Silicon Graphics, Inc.
- */
-#ifndef __ASM_SN_NMI_H
-#define __ASM_SN_NMI_H
-
-#ident "$Revision: 1.5 $"
-
-#include <asm/sn/addrs.h>
-
-/*
- * The launch data structure resides at a fixed place in each node's memory
- * and is used to communicate between the master processor and the slave
- * processors.
- *
- * The master stores launch parameters in the launch structure
- * corresponding to a target processor that is in a slave loop, then sends
- * an interrupt to the slave processor.  The slave calls the desired
- * function, followed by an optional rendezvous function, then returns to
- * the slave loop.  The master does not wait for the slaves before
- * returning.
- *
- * There is an array of launch structures, one per CPU on the node.  One
- * interrupt level is used per CPU.
- */
-
-#define NMI_MAGIC               0x48414d4d455201
-#define NMI_SIZEOF              0x40
-
-#define NMI_OFF_MAGIC           0x00    /* Struct offsets for assembly      */
-#define NMI_OFF_FLAGS           0x08
-#define NMI_OFF_CALL            0x10
-#define NMI_OFF_CALLC           0x18
-#define NMI_OFF_CALLPARM        0x20
-#define NMI_OFF_GMASTER         0x28
-
-/*
- * The NMI routine is called only if the complement address is
- * correct.
- *
- * Before control is transferred to a routine, the complement address
- * is zeroed (invalidated) to prevent an accidental call from a spurious
- * interrupt.
- *
- */
-
-#ifndef __ASSEMBLY__
-
-typedef struct nmi_s {
-        volatile unsigned long   magic;         /* Magic number */
-        volatile unsigned long   flags;         /* Combination of flags above */
-        volatile void *call_addr;       /* Routine for slave to call        */
-        volatile void *call_addr_c;     /* 1's complement of address        */
-        volatile void *call_parm;       /* Single parm passed to call       */
-        volatile unsigned long   gmaster;       /* Flag true only on global master*/
-} nmi_t;
-
-#endif /* !__ASSEMBLY__ */
-
-/* Following definitions are needed both in the prom & the kernel
- * to identify the format of the nmi cpu register save area in the
- * low memory on each node.
- */
-#ifndef __ASSEMBLY__
-
-struct reg_struct {
-        unsigned long   gpr[32];
-        unsigned long   sr;
-        unsigned long   cause;
-        unsigned long   epc;
-        unsigned long   badva;
-        unsigned long   error_epc;
-        unsigned long   cache_err;
-        unsigned long   nmi_sr;
-};
-
-#endif /* !__ASSEMBLY__ */
-
-/* These are the assembly language offsets into the reg_struct structure */
-
-#define R0_OFF          0x0
-#define R1_OFF          0x8
-#define R2_OFF          0x10
-#define R3_OFF          0x18
-#define R4_OFF          0x20
-#define R5_OFF          0x28
-#define R6_OFF          0x30
-#define R7_OFF          0x38
-#define R8_OFF          0x40
-#define R9_OFF          0x48
-#define R10_OFF         0x50
-#define R11_OFF         0x58
-#define R12_OFF         0x60
-#define R13_OFF         0x68
-#define R14_OFF         0x70
-#define R15_OFF         0x78
-#define R16_OFF         0x80
-#define R17_OFF         0x88
-#define R18_OFF         0x90
-#define R19_OFF         0x98
-#define R20_OFF         0xa0
-#define R21_OFF         0xa8
-#define R22_OFF         0xb0
-#define R23_OFF         0xb8
-#define R24_OFF         0xc0
-#define R25_OFF         0xc8
-#define R26_OFF         0xd0
-#define R27_OFF         0xd8
-#define R28_OFF         0xe0
-#define R29_OFF         0xe8
-#define R30_OFF         0xf0
-#define R31_OFF         0xf8
-#define SR_OFF          0x100
-#define CAUSE_OFF       0x108
-#define EPC_OFF         0x110
-#define BADVA_OFF       0x118
-#define ERROR_EPC_OFF   0x120
-#define CACHE_ERR_OFF   0x128
-#define NMISR_OFF       0x130
-
-#endif /* __ASM_SN_NMI_H */
diff --git a/include/asm-mips/sn/sn0/addrs.h b/include/asm-mips/sn/sn0/addrs.h
deleted file mode 100644
index b06190093bbc..000000000000
--- a/include/asm-mips/sn/sn0/addrs.h
+++ /dev/null
@@ -1,288 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/addrs.h>, revision 1.126.
- *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SN_SN0_ADDRS_H
-#define _ASM_SN_SN0_ADDRS_H
-
-
-/*
- * SN0 (on a T5) Address map
- *
- * This file contains a set of definitions and macros which are used
- * to reference into the major address spaces (CAC, HSPEC, IO, MSPEC,
- * and UNCAC) used by the SN0 architecture.  It also contains addresses
- * for "major" statically locatable PROM/Kernel data structures, such as
- * the partition table, the configuration data structure, etc.
- * We make an implicit assumption that the processor using this file
- * follows the R10K's provisions for specifying uncached attributes;
- * should this change, the base registers may very well become processor-
- * dependent.
- *
- * For more information on the address spaces, see the "Local Resources"
- * chapter of the Hub specification.
- *
- * NOTE: This header file is included both by C and by assembler source
- *       files.  Please bracket any language-dependent definitions
- *       appropriately.
- */
-
-/*
- * Some of the macros here need to be casted to appropriate types when used
- * from C.  They definitely must not be casted from assembly language so we
- * use some new ANSI preprocessor stuff to paste these on where needed.
- */
-
-/*
- * The following couple of definitions will eventually need to be variables,
- * since the amount of address space assigned to each node depends on
- * whether the system is running in N-mode (more nodes with less memory)
- * or M-mode (fewer nodes with more memory).  We expect that it will
- * be a while before we need to make this decision dynamically, though,
- * so for now we just use defines bracketed by an ifdef.
- */
-
-#ifdef CONFIG_SGI_SN_N_MODE
-
-#define NODE_SIZE_BITS          31
-#define BWIN_SIZE_BITS          28
-
-#define NASID_BITS              9
-#define NASID_BITMASK           (0x1ffLL)
-#define NASID_SHFT              31
-#define NASID_META_BITS         5
-#define NASID_LOCAL_BITS        4
-
-#define BDDIR_UPPER_MASK        (UINT64_CAST 0x7ffff << 10)
-#define BDECC_UPPER_MASK        (UINT64_CAST 0x3ffffff << 3)
-
-#else /* !defined(CONFIG_SGI_SN_N_MODE), assume that M-mode is desired */
-
-#define NODE_SIZE_BITS          32
-#define BWIN_SIZE_BITS          29
-
-#define NASID_BITMASK           (0xffLL)
-#define NASID_BITS              8
-#define NASID_SHFT              32
-#define NASID_META_BITS         4
-#define NASID_LOCAL_BITS        4
-
-#define BDDIR_UPPER_MASK        (UINT64_CAST 0xfffff << 10)
-#define BDECC_UPPER_MASK        (UINT64_CAST 0x7ffffff << 3)
-
-#endif /* !defined(CONFIG_SGI_SN_N_MODE) */
-
-#define NODE_ADDRSPACE_SIZE     (UINT64_CAST 1 << NODE_SIZE_BITS)
-
-#define NASID_MASK              (UINT64_CAST NASID_BITMASK << NASID_SHFT)
-#define NASID_GET(_pa)          (int) ((UINT64_CAST (_pa) >>            \
-                                        NASID_SHFT) & NASID_BITMASK)
-
-#if !defined(__ASSEMBLY__)
-
-#define NODE_SWIN_BASE(nasid, widget)                                   \
-        ((widget == 0) ? NODE_BWIN_BASE((nasid), SWIN0_BIGWIN)          \
-        : RAW_NODE_SWIN_BASE(nasid, widget))
-#else /* __ASSEMBLY__ */
-#define NODE_SWIN_BASE(nasid, widget) \
-     (NODE_IO_BASE(nasid) + (UINT64_CAST(widget) << SWIN_SIZE_BITS))
-#endif /* __ASSEMBLY__ */
-
-/*
- * The following definitions pertain to the IO special address
- * space.  They define the location of the big and little windows
- * of any given node.
- */
-
-#define BWIN_INDEX_BITS         3
-#define BWIN_SIZE               (UINT64_CAST 1 << BWIN_SIZE_BITS)
-#define BWIN_SIZEMASK           (BWIN_SIZE - 1)
-#define BWIN_WIDGET_MASK        0x7
-#define NODE_BWIN_BASE0(nasid)  (NODE_IO_BASE(nasid) + BWIN_SIZE)
-#define NODE_BWIN_BASE(nasid, bigwin)   (NODE_BWIN_BASE0(nasid) +       \
-                        (UINT64_CAST(bigwin) << BWIN_SIZE_BITS))
-
-#define BWIN_WIDGETADDR(addr)   ((addr) & BWIN_SIZEMASK)
-#define BWIN_WINDOWNUM(addr)    (((addr) >> BWIN_SIZE_BITS) & BWIN_WIDGET_MASK)
-/*
- * Verify if addr belongs to large window address of node with "nasid"
- *
- *
- * NOTE: "addr" is expected to be XKPHYS address, and NOT physical
- * address
- *
- *
- */
-
-#define NODE_BWIN_ADDR(nasid, addr)     \
-                (((addr) >= NODE_BWIN_BASE0(nasid)) && \
-                 ((addr) < (NODE_BWIN_BASE(nasid, HUB_NUM_BIG_WINDOW) + \
-                                BWIN_SIZE)))
-
-/*
- * The following define the major position-independent aliases used
- * in SN0.
- *      CALIAS -- Varies in size, points to the first n bytes of memory
- *                      on the reader's node.
- */
-
-#define CALIAS_BASE             CAC_BASE
-
-
-
-#define BRIDGE_REG_PTR(_base, _off)     ((volatile bridgereg_t *) \
-        ((__psunsigned_t)(_base) + (__psunsigned_t)(_off)))
-
-#define SN0_WIDGET_BASE(_nasid, _wid)   (NODE_SWIN_BASE((_nasid), (_wid)))
-
-/* Turn on sable logging for the processors whose bits are set. */
-#define SABLE_LOG_TRIGGER(_map)
-
-#ifndef __ASSEMBLY__
-#define KERN_NMI_ADDR(nasid, slice)                                     \
-                    TO_NODE_UNCAC((nasid), IP27_NMI_KREGS_OFFSET +      \
-                                  (IP27_NMI_KREGS_CPU_SIZE * (slice)))
-#endif /* !__ASSEMBLY__ */
-
-#ifdef PROM
-
-#define MISC_PROM_BASE          PHYS_TO_K0(0x01300000)
-#define MISC_PROM_SIZE          0x200000
-
-#define DIAG_BASE               PHYS_TO_K0(0x01500000)
-#define DIAG_SIZE               0x300000
-
-#define ROUTE_BASE              PHYS_TO_K0(0x01800000)
-#define ROUTE_SIZE              0x200000
-
-#define IP27PROM_FLASH_HDR      PHYS_TO_K0(0x01300000)
-#define IP27PROM_FLASH_DATA     PHYS_TO_K0(0x01301000)
-#define IP27PROM_CORP_MAX       32
-#define IP27PROM_CORP           PHYS_TO_K0(0x01800000)
-#define IP27PROM_CORP_SIZE      0x10000
-#define IP27PROM_CORP_STK       PHYS_TO_K0(0x01810000)
-#define IP27PROM_CORP_STKSIZE   0x2000
-#define IP27PROM_DECOMP_BUF     PHYS_TO_K0(0x01900000)
-#define IP27PROM_DECOMP_SIZE    0xfff00
-
-#define IP27PROM_BASE           PHYS_TO_K0(0x01a00000)
-#define IP27PROM_BASE_MAPPED    (UNCAC_BASE | 0x1fc00000)
-#define IP27PROM_SIZE_MAX       0x100000
-
-#define IP27PROM_PCFG           PHYS_TO_K0(0x01b00000)
-#define IP27PROM_PCFG_SIZE      0xd0000
-#define IP27PROM_ERRDMP         PHYS_TO_K1(0x01bd0000)
-#define IP27PROM_ERRDMP_SIZE    0xf000
-
-#define IP27PROM_INIT_START     PHYS_TO_K1(0x01bd0000)
-#define IP27PROM_CONSOLE        PHYS_TO_K1(0x01bdf000)
-#define IP27PROM_CONSOLE_SIZE   0x200
-#define IP27PROM_NETUART        PHYS_TO_K1(0x01bdf200)
-#define IP27PROM_NETUART_SIZE   0x100
-#define IP27PROM_UNUSED1        PHYS_TO_K1(0x01bdf300)
-#define IP27PROM_UNUSED1_SIZE   0x500
-#define IP27PROM_ELSC_BASE_A    PHYS_TO_K0(0x01bdf800)
-#define IP27PROM_ELSC_BASE_B    PHYS_TO_K0(0x01bdfc00)
-#define IP27PROM_STACK_A        PHYS_TO_K0(0x01be0000)
-#define IP27PROM_STACK_B        PHYS_TO_K0(0x01bf0000)
-#define IP27PROM_STACK_SHFT     16
-#define IP27PROM_STACK_SIZE     (1 << IP27PROM_STACK_SHFT)
-#define IP27PROM_INIT_END       PHYS_TO_K0(0x01c00000)
-
-#define SLAVESTACK_BASE         PHYS_TO_K0(0x01580000)
-#define SLAVESTACK_SIZE         0x40000
-
-#define ENETBUFS_BASE           PHYS_TO_K0(0x01f80000)
-#define ENETBUFS_SIZE           0x20000
-
-#define IO6PROM_BASE            PHYS_TO_K0(0x01c00000)
-#define IO6PROM_SIZE            0x400000
-#define IO6PROM_BASE_MAPPED     (UNCAC_BASE | 0x11c00000)
-#define IO6DPROM_BASE           PHYS_TO_K0(0x01c00000)
-#define IO6DPROM_SIZE           0x200000
-
-#define NODEBUGUNIX_ADDR        PHYS_TO_K0(0x00019000)
-#define DEBUGUNIX_ADDR          PHYS_TO_K0(0x00100000)
-
-#define IP27PROM_INT_LAUNCH     10      /* and 11 */
-#define IP27PROM_INT_NETUART    12      /* through 17 */
-
-#endif /* PROM */
-
-/*
- * needed by symmon so it needs to be outside #if PROM
- */
-#define IP27PROM_ELSC_SHFT      10
-#define IP27PROM_ELSC_SIZE      (1 << IP27PROM_ELSC_SHFT)
-
-/*
- * This address is used by IO6PROM to build MemoryDescriptors of
- * free memory. This address is important since unix gets loaded
- * at this address, and this memory has to be FREE if unix is to
- * be loaded.
- */
-
-#define FREEMEM_BASE            PHYS_TO_K0(0x2000000)
-
-#define IO6PROM_STACK_SHFT      14      /* stack per cpu */
-#define IO6PROM_STACK_SIZE      (1 << IO6PROM_STACK_SHFT)
-
-/*
- * IP27 PROM vectors
- */
-
-#define IP27PROM_ENTRY          PHYS_TO_COMPATK1(0x1fc00000)
-#define IP27PROM_RESTART        PHYS_TO_COMPATK1(0x1fc00008)
-#define IP27PROM_SLAVELOOP      PHYS_TO_COMPATK1(0x1fc00010)
-#define IP27PROM_PODMODE        PHYS_TO_COMPATK1(0x1fc00018)
-#define IP27PROM_IOC3UARTPOD    PHYS_TO_COMPATK1(0x1fc00020)
-#define IP27PROM_FLASHLEDS      PHYS_TO_COMPATK1(0x1fc00028)
-#define IP27PROM_REPOD          PHYS_TO_COMPATK1(0x1fc00030)
-#define IP27PROM_LAUNCHSLAVE    PHYS_TO_COMPATK1(0x1fc00038)
-#define IP27PROM_WAITSLAVE      PHYS_TO_COMPATK1(0x1fc00040)
-#define IP27PROM_POLLSLAVE      PHYS_TO_COMPATK1(0x1fc00048)
-
-#define KL_UART_BASE    LOCAL_HUB_ADDR(MD_UREG0_0)      /* base of UART regs */
-#define KL_UART_CMD     LOCAL_HUB_ADDR(MD_UREG0_0)      /* UART command reg */
-#define KL_UART_DATA    LOCAL_HUB_ADDR(MD_UREG0_1)      /* UART data reg */
-#define KL_I2C_REG      MD_UREG0_0                      /* I2C reg */
-
-#ifndef __ASSEMBLY__
-
-/* Address 0x400 to 0x1000 ualias points to cache error eframe + misc
- * CACHE_ERR_SP_PTR could either contain an address to the stack, or
- * the stack could start at CACHE_ERR_SP_PTR
- */
-#if defined(HUB_ERR_STS_WAR)
-#define CACHE_ERR_EFRAME        0x480
-#else /* HUB_ERR_STS_WAR */
-#define CACHE_ERR_EFRAME        0x400
-#endif /* HUB_ERR_STS_WAR */
-
-#define CACHE_ERR_ECCFRAME      (CACHE_ERR_EFRAME + EF_SIZE)
-#define CACHE_ERR_SP_PTR        (0x1000 - 32)   /* why -32? TBD */
-#define CACHE_ERR_IBASE_PTR     (0x1000 - 40)
-#define CACHE_ERR_SP            (CACHE_ERR_SP_PTR - 16)
-#define CACHE_ERR_AREA_SIZE     (ARCS_SPB_OFFSET - CACHE_ERR_EFRAME)
-
-#endif  /* !__ASSEMBLY__ */
-
-#define _ARCSPROM
-
-#if defined(HUB_ERR_STS_WAR)
-
-#define ERR_STS_WAR_REGISTER    IIO_IIBUSERR
-#define ERR_STS_WAR_ADDR        LOCAL_HUB_ADDR(IIO_IIBUSERR)
-#define ERR_STS_WAR_PHYSADDR    TO_PHYS((__psunsigned_t)ERR_STS_WAR_ADDR)
-                                /* Used to match addr in error reg. */
-#define OLD_ERR_STS_WAR_OFFSET  ((MD_MEM_BANKS * MD_BANK_SIZE) - 0x100)
-
-#endif /* HUB_ERR_STS_WAR */
-
-#endif /* _ASM_SN_SN0_ADDRS_H */
diff --git a/include/asm-mips/sn/sn0/arch.h b/include/asm-mips/sn/sn0/arch.h
deleted file mode 100644
index f734f2007f24..000000000000
--- a/include/asm-mips/sn/sn0/arch.h
+++ /dev/null
@@ -1,72 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * SGI IP27 specific setup.
- *
- * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_SN_SN0_ARCH_H
-#define _ASM_SN_SN0_ARCH_H
-
-
-#ifndef SN0XXL  /* 128 cpu SMP max */
-/*
- * This is the maximum number of nodes that can be part of a kernel.
- * Effectively, it's the maximum number of compact node ids (cnodeid_t).
- */
-#define MAX_COMPACT_NODES       64
-
-/*
- * MAXCPUS refers to the maximum number of CPUs in a single kernel.
- * This is not necessarily the same as MAXNODES * CPUS_PER_NODE
- */
-#define MAXCPUS                 128
-
-#else /* SN0XXL system */
-
-#define MAX_COMPACT_NODES       128
-#define MAXCPUS                 256
-
-#endif /* SN0XXL */
-
-/*
- * This is the maximum number of NASIDS that can be present in a system.
- * (Highest NASID plus one.)
- */
-#define MAX_NASIDS              256
-
-/*
- * MAX_REGIONS refers to the maximum number of hardware partitioned regions.
- */
-#define MAX_REGIONS             64
-#define MAX_NONPREMIUM_REGIONS  16
-#define MAX_PREMIUM_REGIONS     MAX_REGIONS
-
-/*
- * MAX_PARITIONS refers to the maximum number of logically defined
- * partitions the system can support.
- */
-#define MAX_PARTITIONS          MAX_REGIONS
-
-#define NASID_MASK_BYTES        ((MAX_NASIDS + 7) / 8)
-
-/*
- * Slot constants for SN0
- */
-#ifdef CONFIG_SGI_SN_N_MODE
-#define MAX_MEM_SLOTS   16                      /* max slots per node */
-#else /* !CONFIG_SGI_SN_N_MODE, assume CONFIG_SGI_SN_M_MODE */
-#define MAX_MEM_SLOTS   32                      /* max slots per node */
-#endif /* CONFIG_SGI_SN_M_MODE */
-
-#define SLOT_SHIFT              (27)
-#define SLOT_MIN_MEM_SIZE       (32*1024*1024)
-
-#define CPUS_PER_NODE           2       /* CPUs on a single hub */
-#define CPUS_PER_NODE_SHFT      1       /* Bits to shift in the node number */
-#define CPUS_PER_SUBNODE        2       /* CPUs on a single hub PI */
-
-#endif /* _ASM_SN_SN0_ARCH_H */
diff --git a/include/asm-mips/sn/sn0/hub.h b/include/asm-mips/sn/sn0/hub.h
deleted file mode 100644
index 3e228f8e7969..000000000000
--- a/include/asm-mips/sn/sn0/hub.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SN_SN0_HUB_H
-#define _ASM_SN_SN0_HUB_H
-
-/* The secret password; used to release protection */
-#define HUB_PASSWORD            0x53474972756c6573ull
-
-#define CHIPID_HUB              0
-#define CHIPID_ROUTER           1
-
-#define HUB_REV_1_0             1
-#define HUB_REV_2_0             2
-#define HUB_REV_2_1             3
-#define HUB_REV_2_2             4
-#define HUB_REV_2_3             5
-#define HUB_REV_2_4             6
-
-#define MAX_HUB_PATH            80
-
-#include <asm/sn/sn0/addrs.h>
-#include <asm/sn/sn0/hubpi.h>
-#include <asm/sn/sn0/hubmd.h>
-#include <asm/sn/sn0/hubio.h>
-#include <asm/sn/sn0/hubni.h>
-//#include <asm/sn/sn0/hubcore.h>
-
-/* Translation of uncached attributes */
-#define UATTR_HSPEC     0
-#define UATTR_IO        1
-#define UATTR_MSPEC     2
-#define UATTR_UNCAC     3
-
-#endif /* _ASM_SN_SN0_HUB_H */
diff --git a/include/asm-mips/sn/sn0/hubio.h b/include/asm-mips/sn/sn0/hubio.h
deleted file mode 100644
index 0187895e556c..000000000000
--- a/include/asm-mips/sn/sn0/hubio.h
+++ /dev/null
@@ -1,972 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/hubio.h>, Revision 1.80.
- *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SGI_SN_SN0_HUBIO_H
-#define _ASM_SGI_SN_SN0_HUBIO_H
-
-/*
- * Hub I/O interface registers
- *
- * All registers in this file are subject to change until Hub chip tapeout.
- * In general, the longer software name should be used when available.
- */
-
-/*
- * Slightly friendlier names for some common registers.
- * The hardware definitions follow.
- */
-#define IIO_WIDGET              IIO_WID      /* Widget identification */
-#define IIO_WIDGET_STAT         IIO_WSTAT    /* Widget status register */
-#define IIO_WIDGET_CTRL         IIO_WCR      /* Widget control register */
-#define IIO_WIDGET_TOUT         IIO_WRTO     /* Widget request timeout */
-#define IIO_WIDGET_FLUSH        IIO_WTFR     /* Widget target flush */
-#define IIO_PROTECT             IIO_ILAPR    /* IO interface protection */
-#define IIO_PROTECT_OVRRD       IIO_ILAPO    /* IO protect override */
-#define IIO_OUTWIDGET_ACCESS    IIO_IOWA     /* Outbound widget access */
-#define IIO_INWIDGET_ACCESS     IIO_IIWA     /* Inbound widget access */
-#define IIO_INDEV_ERR_MASK      IIO_IIDEM    /* Inbound device error mask */
-#define IIO_LLP_CSR             IIO_ILCSR    /* LLP control and status */
-#define IIO_LLP_LOG             IIO_ILLR     /* LLP log */
-#define IIO_XTALKCC_TOUT        IIO_IXCC     /* Xtalk credit count timeout*/
-#define IIO_XTALKTT_TOUT        IIO_IXTT     /* Xtalk tail timeout */
-#define IIO_IO_ERR_CLR          IIO_IECLR    /* IO error clear */
-#define IIO_BTE_CRB_CNT         IIO_IBCN     /* IO BTE CRB count */
-
-#define IIO_LLP_CSR_IS_UP               0x00002000
-#define IIO_LLP_CSR_LLP_STAT_MASK       0x00003000
-#define IIO_LLP_CSR_LLP_STAT_SHFT       12
-
-/* key to IIO_PROTECT_OVRRD */
-#define IIO_PROTECT_OVRRD_KEY   0x53474972756c6573ull   /* "SGIrules" */
-
-/* BTE register names */
-#define IIO_BTE_STAT_0          IIO_IBLS_0   /* Also BTE length/status 0 */
-#define IIO_BTE_SRC_0           IIO_IBSA_0   /* Also BTE source address  0 */
-#define IIO_BTE_DEST_0          IIO_IBDA_0   /* Also BTE dest. address 0 */
-#define IIO_BTE_CTRL_0          IIO_IBCT_0   /* Also BTE control/terminate 0 */
-#define IIO_BTE_NOTIFY_0        IIO_IBNA_0   /* Also BTE notification 0 */
-#define IIO_BTE_INT_0           IIO_IBIA_0   /* Also BTE interrupt 0 */
-#define IIO_BTE_OFF_0           0            /* Base offset from BTE 0 regs. */
-#define IIO_BTE_OFF_1   IIO_IBLS_1 - IIO_IBLS_0 /* Offset from base to BTE 1 */
-
-/* BTE register offsets from base */
-#define BTEOFF_STAT             0
-#define BTEOFF_SRC              (IIO_BTE_SRC_0 - IIO_BTE_STAT_0)
-#define BTEOFF_DEST             (IIO_BTE_DEST_0 - IIO_BTE_STAT_0)
-#define BTEOFF_CTRL             (IIO_BTE_CTRL_0 - IIO_BTE_STAT_0)
-#define BTEOFF_NOTIFY           (IIO_BTE_NOTIFY_0 - IIO_BTE_STAT_0)
-#define BTEOFF_INT              (IIO_BTE_INT_0 - IIO_BTE_STAT_0)
-
-
-/*
- * The following definitions use the names defined in the IO interface
- * document for ease of reference.  When possible, software should
- * generally use the longer but clearer names defined above.
- */
-
-#define IIO_BASE        0x400000
-#define IIO_BASE_BTE0   0x410000
-#define IIO_BASE_BTE1   0x420000
-#define IIO_BASE_PERF   0x430000
-#define IIO_PERF_CNT    0x430008
-
-#define IO_PERF_SETS    32
-
-#define IIO_WID         0x400000        /* Widget identification */
-#define IIO_WSTAT       0x400008        /* Widget status */
-#define IIO_WCR         0x400020        /* Widget control */
-
-#define IIO_WSTAT_ECRAZY        (1ULL << 32)    /* Hub gone crazy */
-#define IIO_WSTAT_TXRETRY       (1ULL << 9)     /* Hub Tx Retry timeout */
-#define IIO_WSTAT_TXRETRY_MASK  (0x7F)
-#define IIO_WSTAT_TXRETRY_SHFT  (16)
-#define IIO_WSTAT_TXRETRY_CNT(w)        (((w) >> IIO_WSTAT_TXRETRY_SHFT) & \
-                                          IIO_WSTAT_TXRETRY_MASK)
-
-#define IIO_ILAPR       0x400100        /* Local Access Protection */
-#define IIO_ILAPO       0x400108        /* Protection override */
-#define IIO_IOWA        0x400110        /* outbound widget access */
-#define IIO_IIWA        0x400118        /* inbound widget access */
-#define IIO_IIDEM       0x400120        /* Inbound Device Error Mask */
-#define IIO_ILCSR       0x400128        /* LLP control and status */
-#define IIO_ILLR        0x400130        /* LLP Log */
-#define IIO_IIDSR       0x400138        /* Interrupt destination */
-
-#define IIO_IIBUSERR    0x1400208       /* Reads here cause a bus error. */
-
-/* IO Interrupt Destination Register */
-#define IIO_IIDSR_SENT_SHIFT    28
-#define IIO_IIDSR_SENT_MASK     0x10000000
-#define IIO_IIDSR_ENB_SHIFT     24
-#define IIO_IIDSR_ENB_MASK      0x01000000
-#define IIO_IIDSR_NODE_SHIFT    8
-#define IIO_IIDSR_NODE_MASK     0x0000ff00
-#define IIO_IIDSR_LVL_SHIFT     0
-#define IIO_IIDSR_LVL_MASK      0x0000003f
-
-
-/* GFX Flow Control Node/Widget Register */
-#define IIO_IGFX_0      0x400140        /* gfx node/widget register 0 */
-#define IIO_IGFX_1      0x400148        /* gfx node/widget register 1 */
-#define IIO_IGFX_W_NUM_BITS     4       /* size of widget num field */
-#define IIO_IGFX_W_NUM_MASK     ((1<<IIO_IGFX_W_NUM_BITS)-1)
-#define IIO_IGFX_W_NUM_SHIFT    0
-#define IIO_IGFX_N_NUM_BITS     9       /* size of node num field */
-#define IIO_IGFX_N_NUM_MASK     ((1<<IIO_IGFX_N_NUM_BITS)-1)
-#define IIO_IGFX_N_NUM_SHIFT    4
-#define IIO_IGFX_P_NUM_BITS     1       /* size of processor num field */
-#define IIO_IGFX_P_NUM_MASK     ((1<<IIO_IGFX_P_NUM_BITS)-1)
-#define IIO_IGFX_P_NUM_SHIFT    16
-#define IIO_IGFX_VLD_BITS       1       /* size of valid field */
-#define IIO_IGFX_VLD_MASK       ((1<<IIO_IGFX_VLD_BITS)-1)
-#define IIO_IGFX_VLD_SHIFT      20
-#define IIO_IGFX_INIT(widget, node, cpu, valid)                         (\
-        (((widget) & IIO_IGFX_W_NUM_MASK) << IIO_IGFX_W_NUM_SHIFT) |     \
-        (((node)   & IIO_IGFX_N_NUM_MASK) << IIO_IGFX_N_NUM_SHIFT) |     \
-        (((cpu)    & IIO_IGFX_P_NUM_MASK) << IIO_IGFX_P_NUM_SHIFT) |     \
-        (((valid)  & IIO_IGFX_VLD_MASK)   << IIO_IGFX_VLD_SHIFT)         )
-
-/* Scratch registers (not all bits available) */
-#define IIO_SCRATCH_REG0        0x400150
-#define IIO_SCRATCH_REG1        0x400158
-#define IIO_SCRATCH_MASK        0x0000000f00f11fff
-
-#define IIO_SCRATCH_BIT0_0      0x0000000800000000
-#define IIO_SCRATCH_BIT0_1      0x0000000400000000
-#define IIO_SCRATCH_BIT0_2      0x0000000200000000
-#define IIO_SCRATCH_BIT0_3      0x0000000100000000
-#define IIO_SCRATCH_BIT0_4      0x0000000000800000
-#define IIO_SCRATCH_BIT0_5      0x0000000000400000
-#define IIO_SCRATCH_BIT0_6      0x0000000000200000
-#define IIO_SCRATCH_BIT0_7      0x0000000000100000
-#define IIO_SCRATCH_BIT0_8      0x0000000000010000
-#define IIO_SCRATCH_BIT0_9      0x0000000000001000
-#define IIO_SCRATCH_BIT0_R      0x0000000000000fff
-
-/* IO Translation Table Entries */
-#define IIO_NUM_ITTES   7               /* ITTEs numbered 0..6 */
-                                        /* Hw manuals number them 1..7! */
-
-/*
- * As a permanent workaround for a bug in the PI side of the hub, we've
- * redefined big window 7 as small window 0.
- */
-#define HUB_NUM_BIG_WINDOW      IIO_NUM_ITTES - 1
-
-/*
- * Use the top big window as a surrogate for the first small window
- */
-#define SWIN0_BIGWIN            HUB_NUM_BIG_WINDOW
-
-#define ILCSR_WARM_RESET        0x100
-/*
- * The IO LLP control status register and widget control register
- */
-#ifndef __ASSEMBLY__
-
-typedef union hubii_wid_u {
-        u64     wid_reg_value;
-        struct {
-                u64     wid_rsvd:       32,     /* unused */
-                        wid_rev_num:     4,     /* revision number */
-                        wid_part_num:   16,     /* the widget type: hub=c101 */
-                        wid_mfg_num:    11,     /* Manufacturer id (IBM) */
-                        wid_rsvd1:       1;     /* Reserved */
-        } wid_fields_s;
-} hubii_wid_t;
-
-
-typedef union hubii_wcr_u {
-        u64     wcr_reg_value;
-        struct {
-                u64     wcr_rsvd:       41,     /* unused */
-                        wcr_e_thresh:    5,     /* elasticity threshold */
-                        wcr_dir_con:     1,     /* widget direct connect */
-                        wcr_f_bad_pkt:   1,     /* Force bad llp pkt enable */
-                        wcr_xbar_crd:    3,     /* LLP crossbar credit */
-                        wcr_rsvd1:       8,     /* Reserved */
-                        wcr_tag_mode:    1,     /* Tag mode */
-                        wcr_widget_id:   4;     /* LLP crossbar credit */
-        } wcr_fields_s;
-} hubii_wcr_t;
-
-#define iwcr_dir_con    wcr_fields_s.wcr_dir_con
-
-typedef union hubii_wstat_u {
-        u64      reg_value;
-        struct {
-                u64     rsvd1:          31,
-                        crazy:           1,     /* Crazy bit            */
-                        rsvd2:           8,
-                        llp_tx_cnt:      8,     /* LLP Xmit retry counter */
-                        rsvd3:           6,
-                        tx_max_rtry:     1,     /* LLP Retry Timeout Signal */
-                        rsvd4:           2,
-                        xt_tail_to:      1,     /* Xtalk Tail Timeout   */
-                        xt_crd_to:       1,     /* Xtalk Credit Timeout */
-                        pending:         4;     /* Pending Requests     */
-        } wstat_fields_s;
-} hubii_wstat_t;
-
-
-typedef union hubii_ilcsr_u {
-        u64     icsr_reg_value;
-        struct {
-                u64     icsr_rsvd:      22,     /* unused */
-                        icsr_max_burst: 10,     /* max burst */
-                        icsr_rsvd4:      6,     /* reserved */
-                        icsr_max_retry: 10,     /* max retry */
-                        icsr_rsvd3:      2,     /* reserved */
-                        icsr_lnk_stat:   2,     /* link status */
-                        icsr_bm8:        1,     /* Bit mode 8 */
-                        icsr_llp_en:     1,     /* LLP enable bit */
-                        icsr_rsvd2:      1,     /* reserver */
-                        icsr_wrm_reset:  1,     /* Warm reset bit */
-                        icsr_rsvd1:      2,     /* Data ready offset */
-                        icsr_null_to:    6;     /* Null timeout   */
-
-        } icsr_fields_s;
-} hubii_ilcsr_t;
-
-
-typedef union hubii_iowa_u {
-        u64     iowa_reg_value;
-        struct {
-                u64     iowa_rsvd:      48,     /* unused */
-                        iowa_wxoac:      8,     /* xtalk widget access bits */
-                        iowa_rsvd1:      7,     /* xtalk widget access bits */
-                        iowa_w0oac:      1;     /* xtalk widget access bits */
-        } iowa_fields_s;
-} hubii_iowa_t;
-
-typedef union hubii_iiwa_u {
-        u64     iiwa_reg_value;
-        struct {
-                u64     iiwa_rsvd:      48,     /* unused */
-                        iiwa_wxiac:      8,     /* hub wid access bits */
-                        iiwa_rsvd1:      7,     /* reserved */
-                        iiwa_w0iac:      1;     /* hub wid0 access */
-        } iiwa_fields_s;
-} hubii_iiwa_t;
-
-typedef union   hubii_illr_u {
-        u64     illr_reg_value;
-        struct {
-                u64     illr_rsvd:      32,     /* unused */
-                        illr_cb_cnt:    16,     /* checkbit error count */
-                        illr_sn_cnt:    16;     /* sequence number count */
-        } illr_fields_s;
-} hubii_illr_t;
-
-/* The structures below are defined to extract and modify the ii
-performance registers */
-
-/* io_perf_sel allows the caller to specify what tests will be
-   performed */
-typedef union io_perf_sel {
-        u64 perf_sel_reg;
-        struct {
-                u64     perf_rsvd  : 48,
-                        perf_icct  :  8,
-                        perf_ippr1 :  4,
-                        perf_ippr0 :  4;
-        } perf_sel_bits;
-} io_perf_sel_t;
-
-/* io_perf_cnt is to extract the count from the hub registers. Due to
-   hardware problems there is only one counter, not two. */
-
-typedef union io_perf_cnt {
-        u64     perf_cnt;
-        struct {
-                u64     perf_rsvd1 : 32,
-                        perf_rsvd2 : 12,
-                        perf_cnt   : 20;
-        } perf_cnt_bits;
-} io_perf_cnt_t;
-
-#endif /* !__ASSEMBLY__ */
-
-
-#define LNK_STAT_WORKING        0x2
-
-#define IIO_LLP_CB_MAX  0xffff
-#define IIO_LLP_SN_MAX  0xffff
-
-/* IO PRB Entries */
-#define IIO_NUM_IPRBS   (9)
-#define IIO_IOPRB_0     0x400198        /* PRB entry 0 */
-#define IIO_IOPRB_8     0x4001a0        /* PRB entry 8 */
-#define IIO_IOPRB_9     0x4001a8        /* PRB entry 9 */
-#define IIO_IOPRB_A     0x4001b0        /* PRB entry a */
-#define IIO_IOPRB_B     0x4001b8        /* PRB entry b */
-#define IIO_IOPRB_C     0x4001c0        /* PRB entry c */
-#define IIO_IOPRB_D     0x4001c8        /* PRB entry d */
-#define IIO_IOPRB_E     0x4001d0        /* PRB entry e */
-#define IIO_IOPRB_F     0x4001d8        /* PRB entry f */
-
-
-#define IIO_IXCC        0x4001e0        /* Crosstalk credit count timeout */
-#define IIO_IXTCC       IIO_IXCC
-#define IIO_IMEM        0x4001e8        /* Miscellaneous Enable Mask */
-#define IIO_IXTT        0x4001f0        /* Crosstalk tail timeout */
-#define IIO_IECLR       0x4001f8        /* IO error clear */
-#define IIO_IBCN        0x400200        /* IO BTE CRB count */
-
-/*
- * IIO_IMEM Register fields.
- */
-#define IIO_IMEM_W0ESD  0x1             /* Widget 0 shut down due to error */
-#define IIO_IMEM_B0ESD  (1 << 4)        /* BTE 0 shut down due to error */
-#define IIO_IMEM_B1ESD  (1 << 8)        /* BTE 1 Shut down due to error */
-
-/* PIO Read address Table Entries */
-#define IIO_IPCA        0x400300        /* PRB Counter adjust */
-#define IIO_NUM_PRTES   8               /* Total number of PRB table entries */
-#define IIO_PRTE_0      0x400308        /* PIO Read address table entry 0 */
-#define IIO_PRTE(_x)    (IIO_PRTE_0 + (8 * (_x)))
-#define IIO_WIDPRTE(x)  IIO_PRTE(((x) - 8)) /* widget ID to its PRTE num */
-#define IIO_IPDR        0x400388        /* PIO table entry deallocation */
-#define IIO_ICDR        0x400390        /* CRB Entry Deallocation */
-#define IIO_IFDR        0x400398        /* IOQ FIFO Depth */
-#define IIO_IIAP        0x4003a0        /* IIQ Arbitration Parameters */
-#define IIO_IMMR        IIO_IIAP
-#define IIO_ICMR        0x4003a8        /* CRB Management Register */
-#define IIO_ICCR        0x4003b0        /* CRB Control Register */
-#define IIO_ICTO        0x4003b8        /* CRB Time Out Register */
-#define IIO_ICTP        0x4003c0        /* CRB Time Out Prescalar */
-
-
-/*
- * ICMR register fields
- */
-#define IIO_ICMR_PC_VLD_SHFT    36
-#define IIO_ICMR_PC_VLD_MASK    (0x7fffUL << IIO_ICMR_PC_VLD_SHFT)
-
-#define IIO_ICMR_CRB_VLD_SHFT   20
-#define IIO_ICMR_CRB_VLD_MASK   (0x7fffUL << IIO_ICMR_CRB_VLD_SHFT)
-
-#define IIO_ICMR_FC_CNT_SHFT    16
-#define IIO_ICMR_FC_CNT_MASK    (0xf << IIO_ICMR_FC_CNT_SHFT)
-
-#define IIO_ICMR_C_CNT_SHFT     4
-#define IIO_ICMR_C_CNT_MASK     (0xf << IIO_ICMR_C_CNT_SHFT)
-
-#define IIO_ICMR_P_CNT_SHFT     0
-#define IIO_ICMR_P_CNT_MASK     (0xf << IIO_ICMR_P_CNT_SHFT)
-
-#define IIO_ICMR_PRECISE        (1UL << 52)
-#define IIO_ICMR_CLR_RPPD       (1UL << 13)
-#define IIO_ICMR_CLR_RQPD       (1UL << 12)
-
-/*
- * IIO PIO Deallocation register field masks : (IIO_IPDR)
- */
-#define IIO_IPDR_PND    (1 << 4)
-
-/*
- * IIO CRB deallocation register field masks: (IIO_ICDR)
- */
-#define IIO_ICDR_PND    (1 << 4)
-
-/*
- * IIO CRB control register Fields: IIO_ICCR
- */
-#define IIO_ICCR_PENDING        (0x10000)
-#define IIO_ICCR_CMD_MASK       (0xFF)
-#define IIO_ICCR_CMD_SHFT       (7)
-#define IIO_ICCR_CMD_NOP        (0x0)   /* No Op */
-#define IIO_ICCR_CMD_WAKE       (0x100) /* Reactivate CRB entry and process */
-#define IIO_ICCR_CMD_TIMEOUT    (0x200) /* Make CRB timeout & mark invalid */
-#define IIO_ICCR_CMD_EJECT      (0x400) /* Contents of entry written to memory
-                                         * via a WB
-                                         */
-#define IIO_ICCR_CMD_FLUSH      (0x800)
-
-/*
- * CRB manipulation macros
- *      The CRB macros are slightly complicated, since there are up to
- *      four registers associated with each CRB entry.
- */
-#define IIO_NUM_CRBS            15      /* Number of CRBs */
-#define IIO_NUM_NORMAL_CRBS     12      /* Number of regular CRB entries */
-#define IIO_NUM_PC_CRBS         4       /* Number of partial cache CRBs */
-#define IIO_ICRB_OFFSET         8
-#define IIO_ICRB_0              0x400400
-/* XXX - This is now tuneable:
-        #define IIO_FIRST_PC_ENTRY 12
- */
-
-#define IIO_ICRB_A(_x)  (IIO_ICRB_0 + (4 * IIO_ICRB_OFFSET * (_x)))
-#define IIO_ICRB_B(_x)  (IIO_ICRB_A(_x) + 1*IIO_ICRB_OFFSET)
-#define IIO_ICRB_C(_x)  (IIO_ICRB_A(_x) + 2*IIO_ICRB_OFFSET)
-#define IIO_ICRB_D(_x)  (IIO_ICRB_A(_x) + 3*IIO_ICRB_OFFSET)
-
-/* XXX - IBUE register coming for Hub 2 */
-
-/*
- *
- * CRB Register description.
- *
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING * WARNING
- *
- * Many of the fields in CRB are status bits used by hardware
- * for implementation of the protocol. It's very dangerous to
- * mess around with the CRB registers.
- *
- * It's OK to read the CRB registers and try to make sense out of the
- * fields in CRB.
- *
- * Updating CRB requires all activities in Hub IIO to be quiesced.
- * otherwise, a write to CRB could corrupt other CRB entries.
- * CRBs are here only as a back door peek to hub IIO's status.
- * Quiescing implies  no dmas no PIOs
- * either directly from the cpu or from sn0net.
- * this is not something that can be done easily. So, AVOID updating
- * CRBs.
- */
-
-/*
- * Fields in CRB Register A
- */
-#ifndef __ASSEMBLY__
-typedef union icrba_u {
-        u64     reg_value;
-        struct {
-                u64     resvd:  6,
-                        stall_bte0: 1,  /* Stall BTE 0 */
-                        stall_bte1: 1,  /* Stall BTE 1 */
-                        error:  1,      /* CRB has an error     */
-                        ecode:  3,      /* Error Code           */
-                        lnetuce: 1,     /* SN0net Uncorrectable error */
-                        mark:   1,      /* CRB Has been marked  */
-                        xerr:   1,      /* Error bit set in xtalk header */
-                        sidn:   4,      /* SIDN field from xtalk        */
-                        tnum:   5,      /* TNUM field in xtalk          */
-                        addr:   38,     /* Address of request   */
-                        valid:  1,      /* Valid status         */
-                        iow:    1;      /* IO Write operation   */
-        } icrba_fields_s;
-} icrba_t;
-
-/* This is an alternate typedef for the HUB1 CRB A in order to allow
-   runtime selection of the format based on the REV_ID field of the
-   NI_STATUS_REV_ID register. */
-typedef union h1_icrba_u {
-        u64     reg_value;
-
-        struct {
-                u64     resvd:  6,
-                        unused: 1,      /* Unused but RW!!      */
-                        error:  1,      /* CRB has an error     */
-                        ecode:  4,      /* Error Code           */
-                        lnetuce: 1,     /* SN0net Uncorrectable error */
-                        mark:   1,      /* CRB Has been marked  */
-                        xerr:   1,      /* Error bit set in xtalk header */
-                        sidn:   4,      /* SIDN field from xtalk        */
-                        tnum:   5,      /* TNUM field in xtalk          */
-                        addr:   38,     /* Address of request   */
-                        valid:  1,      /* Valid status         */
-                        iow:    1;      /* IO Write operation   */
-        } h1_icrba_fields_s;
-} h1_icrba_t;
-
-/* XXX - Is this still right?  Check the spec. */
-#define ICRBN_A_CERR_SHFT       54
-#define ICRBN_A_ERR_MASK        0x3ff
-
-#endif /* !__ASSEMBLY__ */
-
-#define IIO_ICRB_ADDR_SHFT      2       /* Shift to get proper address */
-
-/*
- * values for "ecode" field
- */
-#define IIO_ICRB_ECODE_DERR     0       /* Directory error due to IIO access */
-#define IIO_ICRB_ECODE_PERR     1       /* Poison error on IO access */
-#define IIO_ICRB_ECODE_WERR     2       /* Write error by IIO access
-                                         * e.g. WINV to a Read only line.
-                                         */
-#define IIO_ICRB_ECODE_AERR     3       /* Access error caused by IIO access */
-#define IIO_ICRB_ECODE_PWERR    4       /* Error on partial write       */
-#define IIO_ICRB_ECODE_PRERR    5       /* Error on partial read        */
-#define IIO_ICRB_ECODE_TOUT     6       /* CRB timeout before deallocating */
-#define IIO_ICRB_ECODE_XTERR    7       /* Incoming xtalk pkt had error bit */
-
-
-
-/*
- * Fields in CRB Register B
- */
-#ifndef __ASSEMBLY__
-typedef union icrbb_u {
-        u64     reg_value;
-        struct {
-            u64 rsvd1:  5,
-                btenum: 1,      /* BTE to which entry belongs to */
-                cohtrans: 1,    /* Coherent transaction */
-                xtsize: 2,      /* Xtalk operation size
-                                 * 0: Double Word
-                                 * 1: 32 Bytes.
-                                 * 2: 128 Bytes,
-                                 * 3: Reserved.
-                                 */
-                srcnode: 9,     /* Source Node ID               */
-                srcinit: 2,     /* Source Initiator:
-                                 * See below for field values.
-                                 */
-                useold: 1,      /* Use OLD command for processing */
-                imsgtype: 2,    /* Incoming message type
-                                 * see below for field values
-                                 */
-                imsg:   8,      /* Incoming message     */
-                initator: 3,    /* Initiator of original request
-                                 * See below for field values.
-                                 */
-                reqtype: 5,     /* Identifies type of request
-                                 * See below for field values.
-                                 */
-                rsvd2:  7,
-                ackcnt: 11,     /* Invalidate ack count */
-                resp:   1,      /* data response  given to processor */
-                ack:    1,      /* indicates data ack received  */
-                hold:   1,      /* entry is gathering inval acks */
-                wb_pend:1,      /* waiting for writeback to complete */
-                intvn:  1,      /* Intervention */
-                stall_ib: 1,    /* Stall Ibuf (from crosstalk) */
-                stall_intr: 1;  /* Stall internal interrupts */
-        } icrbb_field_s;
-} icrbb_t;
-
-/* This is an alternate typedef for the HUB1 CRB B in order to allow
-   runtime selection of the format based on the REV_ID field of the
-   NI_STATUS_REV_ID register. */
-typedef union h1_icrbb_u {
-        u64     reg_value;
-        struct {
-                u64     rsvd1:  5,
-                        btenum: 1,      /* BTE to which entry belongs to */
-                        cohtrans: 1,    /* Coherent transaction */
-                        xtsize: 2,      /* Xtalk operation size
-                                         * 0: Double Word
-                                         * 1: 32 Bytes.
-                                         * 2: 128 Bytes,
-                                         * 3: Reserved.
-                                         */
-                        srcnode: 9,     /* Source Node ID               */
-                        srcinit: 2,     /* Source Initiator:
-                                         * See below for field values.
-                                         */
-                        useold: 1,      /* Use OLD command for processing */
-                        imsgtype: 2,    /* Incoming message type
-                                         * see below for field values
-                                         */
-                        imsg:   8,      /* Incoming message     */
-                        initator: 3,    /* Initiator of original request
-                                         * See below for field values.
-                                         */
-                        rsvd2:  1,
-                        pcache: 1,      /* entry belongs to partial cache */
-                        reqtype: 5,     /* Identifies type of request
-                                         * See below for field values.
-                                         */
-                        stl_ib: 1,      /* stall Ibus coming from xtalk */
-                        stl_intr: 1,    /* Stall internal interrupts */
-                        stl_bte0: 1,    /* Stall BTE 0  */
-                        stl_bte1: 1,    /* Stall BTE 1  */
-                        intrvn: 1,      /* Req was target of intervention */
-                        ackcnt: 11,     /* Invalidate ack count */
-                        resp:   1,      /* data response  given to processor */
-                        ack:    1,      /* indicates data ack received  */
-                        hold:   1,      /* entry is gathering inval acks */
-                        wb_pend:1,      /* waiting for writeback to complete */
-                        sleep:  1,      /* xtalk req sleeping till IO-sync */
-                        pnd_reply: 1,   /* replies not issed due to IOQ full */
-                        pnd_req: 1;     /* reqs not issued due to IOQ full */
-        } h1_icrbb_field_s;
-} h1_icrbb_t;
-
-
-#define b_imsgtype      icrbb_field_s.imsgtype
-#define b_btenum        icrbb_field_s.btenum
-#define b_cohtrans      icrbb_field_s.cohtrans
-#define b_xtsize        icrbb_field_s.xtsize
-#define b_srcnode       icrbb_field_s.srcnode
-#define b_srcinit       icrbb_field_s.srcinit
-#define b_imsgtype      icrbb_field_s.imsgtype
-#define b_imsg          icrbb_field_s.imsg
-#define b_initiator     icrbb_field_s.initiator
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * values for field xtsize
- */
-#define IIO_ICRB_XTSIZE_DW      0       /* Xtalk operation size is 8 bytes  */
-#define IIO_ICRB_XTSIZE_32      1       /* Xtalk operation size is 32 bytes */
-#define IIO_ICRB_XTSIZE_128     2       /* Xtalk operation size is 128 bytes */
-
-/*
- * values for field srcinit
- */
-#define IIO_ICRB_PROC0          0       /* Source of request is Proc 0 */
-#define IIO_ICRB_PROC1          1       /* Source of request is Proc 1 */
-#define IIO_ICRB_GB_REQ         2       /* Source is Guranteed BW request */
-#define IIO_ICRB_IO_REQ         3       /* Source is Normal IO request  */
-
-/*
- * Values for field imsgtype
- */
-#define IIO_ICRB_IMSGT_XTALK    0       /* Incoming Meessage from Xtalk */
-#define IIO_ICRB_IMSGT_BTE      1       /* Incoming message from BTE    */
-#define IIO_ICRB_IMSGT_SN0NET   2       /* Incoming message from SN0 net */
-#define IIO_ICRB_IMSGT_CRB      3       /* Incoming message from CRB ???  */
-
-/*
- * values for field initiator.
- */
-#define IIO_ICRB_INIT_XTALK     0       /* Message originated in xtalk  */
-#define IIO_ICRB_INIT_BTE0      0x1     /* Message originated in BTE 0  */
-#define IIO_ICRB_INIT_SN0NET    0x2     /* Message originated in SN0net */
-#define IIO_ICRB_INIT_CRB       0x3     /* Message originated in CRB ?  */
-#define IIO_ICRB_INIT_BTE1      0x5     /* MEssage originated in BTE 1  */
-
-/*
- * Values for field reqtype.
- */
-/* XXX - Need to fix this for Hub 2 */
-#define IIO_ICRB_REQ_DWRD       0       /* Request type double word     */
-#define IIO_ICRB_REQ_QCLRD      1       /* Request is Qrtr Caceh line Rd */
-#define IIO_ICRB_REQ_BLKRD      2       /* Request is block read        */
-#define IIO_ICRB_REQ_RSHU       6       /* Request is BTE block read    */
-#define IIO_ICRB_REQ_REXU       7       /* request is BTE Excl Read     */
-#define IIO_ICRB_REQ_RDEX       8       /* Request is Read Exclusive    */
-#define IIO_ICRB_REQ_WINC       9       /* Request is Write Invalidate  */
-#define IIO_ICRB_REQ_BWINV      10      /* Request is BTE Winv          */
-#define IIO_ICRB_REQ_PIORD      11      /* Request is PIO read          */
-#define IIO_ICRB_REQ_PIOWR      12      /* Request is PIO Write         */
-#define IIO_ICRB_REQ_PRDM       13      /* Request is Fetch&Op          */
-#define IIO_ICRB_REQ_PWRM       14      /* Request is Store &Op         */
-#define IIO_ICRB_REQ_PTPWR      15      /* Request is Peer to peer      */
-#define IIO_ICRB_REQ_WB         16      /* Request is Write back        */
-#define IIO_ICRB_REQ_DEX        17      /* Retained DEX Cache line      */
-
-/*
- * Fields in CRB Register C
- */
-
-#ifndef __ASSEMBLY__
-
-typedef union icrbc_s {
-        u64     reg_value;
-        struct {
-                u64     rsvd:   6,
-                        sleep:  1,
-                        pricnt: 4,      /* Priority count sent with Read req */
-                        pripsc: 4,      /* Priority Pre scalar  */
-                        bteop:  1,      /* BTE Operation        */
-                        push_be: 34,    /* Push address Byte enable
-                                         * Holds push addr, if CRB is for BTE
-                                         * If CRB belongs to Partial cache,
-                                         * this contains byte enables bits
-                                         * ([47:46] = 0)
-                                         */
-                        suppl:  11,     /* Supplemental field   */
-                        barrop: 1,      /* Barrier Op bit set in xtalk req */
-                        doresp: 1,      /* Xtalk req needs a response   */
-                        gbr:    1;      /* GBR bit set in xtalk packet  */
-        } icrbc_field_s;
-} icrbc_t;
-
-#define c_pricnt        icrbc_field_s.pricnt
-#define c_pripsc        icrbc_field_s.pripsc
-#define c_bteop         icrbc_field_s.bteop
-#define c_bteaddr       icrbc_field_s.push_be   /* push_be field has 2 names */
-#define c_benable       icrbc_field_s.push_be   /* push_be field has 2 names */
-#define c_suppl         icrbc_field_s.suppl
-#define c_barrop        icrbc_field_s.barrop
-#define c_doresp        icrbc_field_s.doresp
-#define c_gbr   icrbc_field_s.gbr
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Fields in CRB Register D
- */
-
-#ifndef __ASSEMBLY__
-typedef union icrbd_s {
-        u64     reg_value;
-        struct {
-            u64 rsvd:   38,
-                toutvld: 1,     /* Timeout in progress for this CRB */
-                ctxtvld: 1,     /* Context field below is valid */
-                rsvd2:  1,
-                context: 15,    /* Bit vector:
-                                 * Has a bit set for each CRB entry
-                                 * which needs to be deallocated
-                                 * before this CRB entry is processed.
-                                 * Set only for barrier operations.
-                                 */
-                timeout: 8;     /* Timeout Upper 8 bits */
-        } icrbd_field_s;
-} icrbd_t;
-
-#define icrbd_toutvld   icrbd_field_s.toutvld
-#define icrbd_ctxtvld   icrbd_field_s.ctxtvld
-#define icrbd_context   icrbd_field_s.context
-
-
-typedef union hubii_ifdr_u {
-        u64     hi_ifdr_value;
-        struct {
-                u64     ifdr_rsvd:      49,
-                        ifdr_maxrp:      7,
-                        ifdr_rsvd1:      1,
-                        ifdr_maxrq:      7;
-        } hi_ifdr_fields;
-} hubii_ifdr_t;
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * Hardware designed names for the BTE control registers.
- */
-#define IIO_IBLS_0      0x410000        /* BTE length/status 0 */
-#define IIO_IBSA_0      0x410008        /* BTE source address 0 */
-#define IIO_IBDA_0      0x410010        /* BTE destination address 0 */
-#define IIO_IBCT_0      0x410018        /* BTE control/terminate 0 */
-#define IIO_IBNA_0      0x410020        /* BTE notification address 0 */
-#define IIO_IBNR_0      IIO_IBNA_0
-#define IIO_IBIA_0      0x410028        /* BTE interrupt address 0 */
-
-#define IIO_IBLS_1      0x420000        /* BTE length/status 1 */
-#define IIO_IBSA_1      0x420008        /* BTE source address 1 */
-#define IIO_IBDA_1      0x420010        /* BTE destination address 1 */
-#define IIO_IBCT_1      0x420018        /* BTE control/terminate 1 */
-#define IIO_IBNA_1      0x420020        /* BTE notification address 1 */
-#define IIO_IBNR_1      IIO_IBNA_1
-#define IIO_IBIA_1      0x420028        /* BTE interrupt address 1 */
-
-/*
- * More miscellaneous registers
- */
-#define IIO_IPCR        0x430000        /* Performance Control */
-#define IIO_IPPR        0x430008        /* Performance Profiling */
-
-/*
- * IO Error Clear register bit field definitions
- */
-#define IECLR_BTE1              (1 << 18)  /* clear bte error 1 ??? */
-#define IECLR_BTE0              (1 << 17)  /* clear bte error 0 ??? */
-#define IECLR_CRAZY             (1 << 16)  /* clear crazy bit in wstat reg */
-#define IECLR_PRB_F             (1 << 15)  /* clear err bit in PRB_F reg */
-#define IECLR_PRB_E             (1 << 14)  /* clear err bit in PRB_E reg */
-#define IECLR_PRB_D             (1 << 13)  /* clear err bit in PRB_D reg */
-#define IECLR_PRB_C             (1 << 12)  /* clear err bit in PRB_C reg */
-#define IECLR_PRB_B             (1 << 11)  /* clear err bit in PRB_B reg */
-#define IECLR_PRB_A             (1 << 10)  /* clear err bit in PRB_A reg */
-#define IECLR_PRB_9             (1 << 9)   /* clear err bit in PRB_9 reg */
-#define IECLR_PRB_8             (1 << 8)   /* clear err bit in PRB_8 reg */
-#define IECLR_PRB_0             (1 << 0)   /* clear err bit in PRB_0 reg */
-
-/*
- * IO PIO Read Table Entry format
- */
-
-#ifndef __ASSEMBLY__
-
-typedef union iprte_a {
-        u64     entry;
-        struct {
-            u64 rsvd1     : 7,  /* Reserved field               */
-                valid     : 1,  /* Maps to a timeout entry      */
-                rsvd2     : 1,
-                srcnode   : 9,  /* Node which did this PIO      */
-                initiator : 2,  /* If T5A or T5B or IO          */
-                rsvd3     : 3,
-                addr      : 38, /* Physical address of PIO      */
-                rsvd4     : 3;
-        } iprte_fields;
-} iprte_a_t;
-
-#define iprte_valid     iprte_fields.valid
-#define iprte_timeout   iprte_fields.timeout
-#define iprte_srcnode   iprte_fields.srcnode
-#define iprte_init      iprte_fields.initiator
-#define iprte_addr      iprte_fields.addr
-
-#endif /* !__ASSEMBLY__ */
-
-#define IPRTE_ADDRSHFT  3
-
-/*
- * Hub IIO PRB Register format.
- */
-
-#ifndef __ASSEMBLY__
-/*
- * Note: Fields bnakctr, anakctr, xtalkctrmode, ovflow fields are
- * "Status" fields, and should only be used in case of clean up after errors.
- */
-
-typedef union iprb_u {
-        u64     reg_value;
-        struct {
-            u64 rsvd1:  15,
-                error:  1,      /* Widget rcvd wr resp pkt w/ error */
-                ovflow: 5,      /* Over flow count. perf measurement */
-                fire_and_forget: 1, /* Launch Write without response */
-                mode:   2,      /* Widget operation Mode        */
-                rsvd2:  2,
-                bnakctr: 14,
-                rsvd3:  2,
-                anakctr: 14,
-                xtalkctr: 8;
-        } iprb_fields_s;
-} iprb_t;
-
-#define iprb_regval     reg_value
-
-#define iprb_error      iprb_fields_s.error
-#define iprb_ovflow     iprb_fields_s.ovflow
-#define iprb_ff         iprb_fields_s.fire_and_forget
-#define iprb_mode       iprb_fields_s.mode
-#define iprb_bnakctr    iprb_fields_s.bnakctr
-#define iprb_anakctr    iprb_fields_s.anakctr
-#define iprb_xtalkctr   iprb_fields_s.xtalkctr
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * values for mode field in iprb_t.
- * For details of the meanings of NAK and Accept, refer the PIO flow
- * document
- */
-#define IPRB_MODE_NORMAL        (0)
-#define IPRB_MODE_COLLECT_A     (1)     /* PRB in collect A mode */
-#define IPRB_MODE_SERVICE_A     (2)     /* NAK B and Accept A */
-#define IPRB_MODE_SERVICE_B     (3)     /* NAK A and Accept B */
-
-/*
- * IO CRB entry C_A to E_A : Partial (cache) CRBS
- */
-#ifndef __ASSEMBLY__
-typedef union icrbp_a {
-        u64   ip_reg;       /* the entire register value        */
-        struct {
-             u64 error: 1,  /*    63, error occurred            */
-                ln_uce: 1,  /*    62: uncorrectable memory      */
-                ln_ae:  1,  /*    61: protection violation      */
-                ln_werr:1,  /*    60: write access error        */
-                ln_aerr:1,  /*    59: sn0net: Address error     */
-                ln_perr:1,  /*    58: sn0net: poison error      */
-                timeout:1,  /*    57: CRB timed out             */
-                l_bdpkt:1,  /*    56: truncated pkt on sn0net   */
-                c_bdpkt:1,  /*    55: truncated pkt on xtalk    */
-                c_err:  1,  /*    54: incoming xtalk req, err set*/
-                rsvd1: 12,  /* 53-42: reserved                  */
-                valid:  1,  /*    41: Valid status              */
-                sidn:   4,  /* 40-37: SIDN field of xtalk rqst  */
-                tnum:   5,  /* 36-32: TNUM of xtalk request     */
-                bo:     1,  /*    31: barrier op set in xtalk rqst*/
-                resprqd:1,  /*    30: xtalk rqst requires response*/
-                gbr:    1,  /*    29: gbr bit set in xtalk rqst */
-                size:   2,  /* 28-27: size of xtalk request     */
-                excl:   4,  /* 26-23: exclusive bit(s)          */
-                stall:  3,  /* 22-20: stall (xtalk, bte 0/1)    */
-                intvn:  1,  /*    19: rqst target of intervention*/
-                resp:   1,  /*    18: Data response given to t5 */
-                ack:    1,  /*    17: Data ack received.        */
-                hold:   1,  /*    16: crb gathering invalidate acks*/
-                wb:     1,  /*    15: writeback pending.        */
-                ack_cnt:11, /* 14-04: counter of invalidate acks*/
-                tscaler:4;  /* 03-00: Timeout prescaler         */
-        } ip_fmt;
-} icrbp_a_t;
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * A couple of defines to go with the above structure.
- */
-#define ICRBP_A_CERR_SHFT       54
-#define ICRBP_A_ERR_MASK        0x3ff
-
-#ifndef __ASSEMBLY__
-typedef union hubii_idsr {
-        u64 iin_reg;
-        struct {
-                u64 rsvd1 : 35,
-                    isent : 1,
-                    rsvd2 : 3,
-                    ienable: 1,
-                    rsvd  : 7,
-                    node  : 9,
-                    rsvd4 : 1,
-                    level : 7;
-        } iin_fmt;
-} hubii_idsr_t;
-#endif /* !__ASSEMBLY__ */
-
-/*
- * IO BTE Length/Status (IIO_IBLS) register bit field definitions
- */
-#define IBLS_BUSY               (0x1 << 20)
-#define IBLS_ERROR_SHFT         16
-#define IBLS_ERROR              (0x1 << IBLS_ERROR_SHFT)
-#define IBLS_LENGTH_MASK        0xffff
-
-/*
- * IO BTE Control/Terminate register (IBCT) register bit field definitions
- */
-#define IBCT_POISON             (0x1 << 8)
-#define IBCT_NOTIFY             (0x1 << 4)
-#define IBCT_ZFIL_MODE          (0x1 << 0)
-
-/*
- * IO BTE Interrupt Address Register (IBIA) register bit field definitions
- */
-#define IBIA_LEVEL_SHFT         16
-#define IBIA_LEVEL_MASK         (0x7f << IBIA_LEVEL_SHFT)
-#define IBIA_NODE_ID_SHFT       0
-#define IBIA_NODE_ID_MASK       (0x1ff)
-
-/*
- * Miscellaneous hub constants
- */
-
-/* Number of widgets supported by hub */
-#define HUB_NUM_WIDGET          9
-#define HUB_WIDGET_ID_MIN       0x8
-#define HUB_WIDGET_ID_MAX       0xf
-
-#define HUB_WIDGET_PART_NUM     0xc101
-#define MAX_HUBS_PER_XBOW       2
-
-/*
- * Get a hub's widget id from widget control register
- */
-#define IIO_WCR_WID_GET(nasid)  (REMOTE_HUB_L(nasid, III_WCR) & 0xf)
-#define IIO_WST_ERROR_MASK      (UINT64_CAST 1 << 32) /* Widget status error */
-
-/*
- * Number of credits Hub widget has while sending req/response to
- * xbow.
- * Value of 3 is required by Xbow 1.1
- * We may be able to increase this to 4 with Xbow 1.2.
- */
-#define       HUBII_XBOW_CREDIT       3
-#define       HUBII_XBOW_REV2_CREDIT  4
-
-#endif /* _ASM_SGI_SN_SN0_HUBIO_H */
diff --git a/include/asm-mips/sn/sn0/hubmd.h b/include/asm-mips/sn/sn0/hubmd.h
deleted file mode 100644
index 14c225d80664..000000000000
--- a/include/asm-mips/sn/sn0/hubmd.h
+++ /dev/null
@@ -1,789 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/hubmd.h>, revision 1.59.
- *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SN_SN0_HUBMD_H
-#define _ASM_SN_SN0_HUBMD_H
-
-
-/*
- * Hub Memory/Directory interface registers
- */
-#define CACHE_SLINE_SIZE        128     /* Secondary cache line size on SN0 */
-
-#define MAX_REGIONS             64
-
-/* Hardware page size and shift */
-
-#define MD_PAGE_SIZE            4096     /* Page size in bytes              */
-#define MD_PAGE_NUM_SHFT        12       /* Address to page number shift    */
-
-/* Register offsets from LOCAL_HUB or REMOTE_HUB */
-
-#define MD_BASE                 0x200000
-#define MD_BASE_PERF            0x210000
-#define MD_BASE_JUNK            0x220000
-
-#define MD_IO_PROTECT           0x200000 /* MD and core register protection */
-#define MD_IO_PROT_OVRRD        0x200008 /* Clear my bit in MD_IO_PROTECT   */
-#define MD_HSPEC_PROTECT        0x200010 /* BDDIR, LBOOT, RBOOT protection  */
-#define MD_MEMORY_CONFIG        0x200018 /* Memory/Directory DIMM control   */
-#define MD_REFRESH_CONTROL      0x200020 /* Memory/Directory refresh ctrl   */
-#define MD_FANDOP_CAC_STAT      0x200028 /* Fetch-and-op cache status       */
-#define MD_MIG_DIFF_THRESH      0x200030 /* Page migr. count diff thresh.   */
-#define MD_MIG_VALUE_THRESH     0x200038 /* Page migr. count abs. thresh.   */
-#define MD_MIG_CANDIDATE        0x200040 /* Latest page migration candidate */
-#define MD_MIG_CANDIDATE_CLR    0x200048 /* Clear page migration candidate  */
-#define MD_DIR_ERROR            0x200050 /* Directory DIMM error            */
-#define MD_DIR_ERROR_CLR        0x200058 /* Directory DIMM error clear      */
-#define MD_PROTOCOL_ERROR       0x200060 /* Directory protocol error        */
-#define MD_PROTOCOL_ERROR_CLR   0x200068 /* Directory protocol error clear  */
-#define MD_MEM_ERROR            0x200070 /* Memory DIMM error               */
-#define MD_MEM_ERROR_CLR        0x200078 /* Memory DIMM error clear         */
-#define MD_MISC_ERROR           0x200080 /* Miscellaneous MD error          */
-#define MD_MISC_ERROR_CLR       0x200088 /* Miscellaneous MD error clear    */
-#define MD_MEM_DIMM_INIT        0x200090 /* Memory DIMM mode initization.   */
-#define MD_DIR_DIMM_INIT        0x200098 /* Directory DIMM mode init.       */
-#define MD_MOQ_SIZE             0x2000a0 /* MD outgoing queue size          */
-#define MD_MLAN_CTL             0x2000a8 /* NIC (Microlan) control register */
-
-#define MD_PERF_SEL             0x210000 /* Select perf monitor events      */
-#define MD_PERF_CNT0            0x210010 /* Performance counter 0           */
-#define MD_PERF_CNT1            0x210018 /* Performance counter 1           */
-#define MD_PERF_CNT2            0x210020 /* Performance counter 2           */
-#define MD_PERF_CNT3            0x210028 /* Performance counter 3           */
-#define MD_PERF_CNT4            0x210030 /* Performance counter 4           */
-#define MD_PERF_CNT5            0x210038 /* Performance counter 5           */
-
-#define MD_UREG0_0              0x220000 /* uController/UART 0 register     */
-#define MD_UREG0_1              0x220008 /* uController/UART 0 register     */
-#define MD_UREG0_2              0x220010 /* uController/UART 0 register     */
-#define MD_UREG0_3              0x220018 /* uController/UART 0 register     */
-#define MD_UREG0_4              0x220020 /* uController/UART 0 register     */
-#define MD_UREG0_5              0x220028 /* uController/UART 0 register     */
-#define MD_UREG0_6              0x220030 /* uController/UART 0 register     */
-#define MD_UREG0_7              0x220038 /* uController/UART 0 register     */
-
-#define MD_SLOTID_USTAT         0x220048 /* Hub slot ID & UART/uCtlr status */
-#define MD_LED0                 0x220050 /* Eight-bit LED for CPU A         */
-#define MD_LED1                 0x220058 /* Eight-bit LED for CPU B         */
-
-#define MD_UREG1_0              0x220080 /* uController/UART 1 register     */
-#define MD_UREG1_1              0x220088 /* uController/UART 1 register     */
-#define MD_UREG1_2              0x220090 /* uController/UART 1 register     */
-#define MD_UREG1_3              0x220098 /* uController/UART 1 register     */
-#define MD_UREG1_4              0x2200a0 /* uController/UART 1 register     */
-#define MD_UREG1_5              0x2200a8 /* uController/UART 1 register     */
-#define MD_UREG1_6              0x2200b0 /* uController/UART 1 register     */
-#define MD_UREG1_7              0x2200b8 /* uController/UART 1 register     */
-#define MD_UREG1_8              0x2200c0 /* uController/UART 1 register     */
-#define MD_UREG1_9              0x2200c8 /* uController/UART 1 register     */
-#define MD_UREG1_10             0x2200d0 /* uController/UART 1 register     */
-#define MD_UREG1_11             0x2200d8 /* uController/UART 1 register     */
-#define MD_UREG1_12             0x2200e0 /* uController/UART 1 register     */
-#define MD_UREG1_13             0x2200e8 /* uController/UART 1 register     */
-#define MD_UREG1_14             0x2200f0 /* uController/UART 1 register     */
-#define MD_UREG1_15             0x2200f8 /* uController/UART 1 register     */
-
-#ifdef CONFIG_SGI_SN_N_MODE
-#define MD_MEM_BANKS            4        /* 4 banks of memory max in N mode */
-#else
-#define MD_MEM_BANKS            8        /* 8 banks of memory max in M mode */
-#endif
-
-/*
- * MD_MEMORY_CONFIG fields
- *
- *   MD_SIZE_xxx are useful for representing the size of a SIMM or bank
- *   (SIMM pair).  They correspond to the values needed for the bit
- *   triplets (MMC_BANK_MASK) in the MD_MEMORY_CONFIG register for bank size.
- *   Bits not used by the MD are used by software.
- */
-
-#define MD_SIZE_EMPTY           0       /* Valid in MEMORY_CONFIG           */
-#define MD_SIZE_8MB             1
-#define MD_SIZE_16MB            2
-#define MD_SIZE_32MB            3       /* Broken in Hub 1                  */
-#define MD_SIZE_64MB            4       /* Valid in MEMORY_CONFIG           */
-#define MD_SIZE_128MB           5       /* Valid in MEMORY_CONFIG           */
-#define MD_SIZE_256MB           6
-#define MD_SIZE_512MB           7       /* Valid in MEMORY_CONFIG           */
-#define MD_SIZE_1GB             8
-#define MD_SIZE_2GB             9
-#define MD_SIZE_4GB             10
-
-#define MD_SIZE_BYTES(size)     ((size) == 0 ? 0 : 0x400000L << (size))
-#define MD_SIZE_MBYTES(size)    ((size) == 0 ? 0 :   4       << (size))
-
-#define MMC_FPROM_CYC_SHFT      49      /* Have to use UINT64_CAST, instead */
-#define MMC_FPROM_CYC_MASK      (UINT64_CAST 31 << 49)  /* of 'L' suffix,   */
-#define MMC_FPROM_WR_SHFT       44                      /* for assembler    */
-#define MMC_FPROM_WR_MASK       (UINT64_CAST 31 << 44)
-#define MMC_UCTLR_CYC_SHFT      39
-#define MMC_UCTLR_CYC_MASK      (UINT64_CAST 31 << 39)
-#define MMC_UCTLR_WR_SHFT       34
-#define MMC_UCTLR_WR_MASK       (UINT64_CAST 31 << 34)
-#define MMC_DIMM0_SEL_SHFT      32
-#define MMC_DIMM0_SEL_MASK      (UINT64_CAST 3 << 32)
-#define MMC_IO_PROT_EN_SHFT     31
-#define MMC_IO_PROT_EN_MASK     (UINT64_CAST 1 << 31)
-#define MMC_IO_PROT             (UINT64_CAST 1 << 31)
-#define MMC_ARB_MLSS_SHFT       30
-#define MMC_ARB_MLSS_MASK       (UINT64_CAST 1 << 30)
-#define MMC_ARB_MLSS            (UINT64_CAST 1 << 30)
-#define MMC_IGNORE_ECC_SHFT     29
-#define MMC_IGNORE_ECC_MASK     (UINT64_CAST 1 << 29)
-#define MMC_IGNORE_ECC          (UINT64_CAST 1 << 29)
-#define MMC_DIR_PREMIUM_SHFT    28
-#define MMC_DIR_PREMIUM_MASK    (UINT64_CAST 1 << 28)
-#define MMC_DIR_PREMIUM         (UINT64_CAST 1 << 28)
-#define MMC_REPLY_GUAR_SHFT     24
-#define MMC_REPLY_GUAR_MASK     (UINT64_CAST 15 << 24)
-#define MMC_BANK_SHFT(_b)       ((_b) * 3)
-#define MMC_BANK_MASK(_b)       (UINT64_CAST 7 << MMC_BANK_SHFT(_b))
-#define MMC_BANK_ALL_MASK       0xffffff
-#define MMC_RESET_DEFAULTS      (UINT64_CAST 0x0f << MMC_FPROM_CYC_SHFT | \
-                                 UINT64_CAST 0x07 << MMC_FPROM_WR_SHFT | \
-                                 UINT64_CAST 0x1f << MMC_UCTLR_CYC_SHFT | \
-                                 UINT64_CAST 0x0f << MMC_UCTLR_WR_SHFT | \
-                                 MMC_IGNORE_ECC | MMC_DIR_PREMIUM | \
-                                 UINT64_CAST 0x0f << MMC_REPLY_GUAR_SHFT | \
-                                 MMC_BANK_ALL_MASK)
-
-/* MD_REFRESH_CONTROL fields */
-
-#define MRC_ENABLE_SHFT         63
-#define MRC_ENABLE_MASK         (UINT64_CAST 1 << 63)
-#define MRC_ENABLE              (UINT64_CAST 1 << 63)
-#define MRC_COUNTER_SHFT        12
-#define MRC_COUNTER_MASK        (UINT64_CAST 0xfff << 12)
-#define MRC_CNT_THRESH_MASK     0xfff
-#define MRC_RESET_DEFAULTS      (UINT64_CAST 0x400)
-
-/* MD_MEM_DIMM_INIT and MD_DIR_DIMM_INIT fields */
-
-#define MDI_SELECT_SHFT         32
-#define MDI_SELECT_MASK         (UINT64_CAST 0x0f << 32)
-#define MDI_DIMM_MODE_MASK      (UINT64_CAST 0xfff)
-
-/* MD_MOQ_SIZE fields */
-
-#define MMS_RP_SIZE_SHFT        8
-#define MMS_RP_SIZE_MASK        (UINT64_CAST 0x3f << 8)
-#define MMS_RQ_SIZE_SHFT        0
-#define MMS_RQ_SIZE_MASK        (UINT64_CAST 0x1f)
-#define MMS_RESET_DEFAULTS      (0x32 << 8 | 0x12)
-
-/* MD_FANDOP_CAC_STAT fields */
-
-#define MFC_VALID_SHFT          63
-#define MFC_VALID_MASK          (UINT64_CAST 1 << 63)
-#define MFC_VALID               (UINT64_CAST 1 << 63)
-#define MFC_ADDR_SHFT           6
-#define MFC_ADDR_MASK           (UINT64_CAST 0x3ffffff)
-
-/* MD_MLAN_CTL fields */
-
-#define MLAN_PHI1_SHFT          27
-#define MLAN_PHI1_MASK          (UINT64_CAST 0x7f << 27)
-#define MLAN_PHI0_SHFT          20
-#define MLAN_PHI0_MASK          (UINT64_CAST 0x7f << 27)
-#define MLAN_PULSE_SHFT         10
-#define MLAN_PULSE_MASK         (UINT64_CAST 0x3ff << 10)
-#define MLAN_SAMPLE_SHFT        2
-#define MLAN_SAMPLE_MASK        (UINT64_CAST 0xff << 2)
-#define MLAN_DONE_SHFT          1
-#define MLAN_DONE_MASK          2
-#define MLAN_DONE               (UINT64_CAST 0x02)
-#define MLAN_RD_DATA            (UINT64_CAST 0x01)
-#define MLAN_RESET_DEFAULTS     (UINT64_CAST 0x31 << MLAN_PHI1_SHFT | \
-                                 UINT64_CAST 0x31 << MLAN_PHI0_SHFT)
-
-/* MD_SLOTID_USTAT bit definitions */
-
-#define MSU_CORECLK_TST_SHFT    7       /* You don't wanna know             */
-#define MSU_CORECLK_TST_MASK    (UINT64_CAST 1 << 7)
-#define MSU_CORECLK_TST         (UINT64_CAST 1 << 7)
-#define MSU_CORECLK_SHFT        6       /* You don't wanna know             */
-#define MSU_CORECLK_MASK        (UINT64_CAST 1 << 6)
-#define MSU_CORECLK             (UINT64_CAST 1 << 6)
-#define MSU_NETSYNC_SHFT        5       /* You don't wanna know             */
-#define MSU_NETSYNC_MASK        (UINT64_CAST 1 << 5)
-#define MSU_NETSYNC             (UINT64_CAST 1 << 5)
-#define MSU_FPROMRDY_SHFT       4       /* Flash PROM ready bit             */
-#define MSU_FPROMRDY_MASK       (UINT64_CAST 1 << 4)
-#define MSU_FPROMRDY            (UINT64_CAST 1 << 4)
-#define MSU_I2CINTR_SHFT                3       /* I2C interrupt bit   */
-#define MSU_I2CINTR_MASK                (UINT64_CAST 1 << 3)
-#define MSU_I2CINTR             (UINT64_CAST 1 << 3)
-#define MSU_SLOTID_MASK         0xff
-#define MSU_SN0_SLOTID_SHFT     0       /* Slot ID                          */
-#define MSU_SN0_SLOTID_MASK     (UINT64_CAST 7)
-#define MSU_SN00_SLOTID_SHFT    7
-#define MSU_SN00_SLOTID_MASK    (UINT64_CAST 0x80)
-
-#define MSU_PIMM_PSC_SHFT       4
-#define MSU_PIMM_PSC_MASK       (0xf << MSU_PIMM_PSC_SHFT)
-
-/* MD_MIG_DIFF_THRESH bit definitions */
-
-#define MD_MIG_DIFF_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
-#define MD_MIG_DIFF_THRES_VALID_SHFT 63
-#define MD_MIG_DIFF_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
-
-/* MD_MIG_VALUE_THRESH bit definitions */
-
-#define MD_MIG_VALUE_THRES_VALID_MASK (UINT64_CAST 0x1 << 63)
-#define MD_MIG_VALUE_THRES_VALID_SHFT 63
-#define MD_MIG_VALUE_THRES_VALUE_MASK (UINT64_CAST 0xfffff)
-
-/* MD_MIG_CANDIDATE bit definitions */
-
-#define MD_MIG_CANDIDATE_VALID_MASK (UINT64_CAST 0x1 << 63)
-#define MD_MIG_CANDIDATE_VALID_SHFT 63
-#define MD_MIG_CANDIDATE_TYPE_MASK (UINT64_CAST 0x1 << 30)
-#define MD_MIG_CANDIDATE_TYPE_SHFT 30
-#define MD_MIG_CANDIDATE_OVERRUN_MASK (UINT64_CAST 0x1 << 29)
-#define MD_MIG_CANDIDATE_OVERRUN_SHFT 29
-#define MD_MIG_CANDIDATE_INITIATOR_MASK (UINT64_CAST 0x7ff << 18)
-#define MD_MIG_CANDIDATE_INITIATOR_SHFT 18
-#define MD_MIG_CANDIDATE_NODEID_MASK (UINT64_CAST 0x1ff << 20)
-#define MD_MIG_CANDIDATE_NODEID_SHFT 20
-#define MD_MIG_CANDIDATE_ADDR_MASK (UINT64_CAST 0x3ffff)
-#define MD_MIG_CANDIDATE_ADDR_SHFT 14  /* The address starts at bit 14 */
-
-/* Other MD definitions */
-
-#define MD_BANK_SHFT            29                      /* log2(512 MB)     */
-#define MD_BANK_MASK            (UINT64_CAST 7 << 29)
-#define MD_BANK_SIZE            (UINT64_CAST 1 << MD_BANK_SHFT)   /* 512 MB */
-#define MD_BANK_OFFSET(_b)      (UINT64_CAST (_b) << MD_BANK_SHFT)
-
-/*
- * The following definitions cover the bit field definitions for the
- * various MD registers.  For multi-bit registers, we define both
- * a shift amount and a mask value.  By convention, if you want to
- * isolate a field, you should mask the field and then shift it down,
- * since this makes the masks useful without a shift.
- */
-
-/* Directory entry states for both premium and standard SIMMs. */
-
-#define MD_DIR_SHARED           (UINT64_CAST 0x0)       /* 000 */
-#define MD_DIR_POISONED         (UINT64_CAST 0x1)       /* 001 */
-#define MD_DIR_EXCLUSIVE        (UINT64_CAST 0x2)       /* 010 */
-#define MD_DIR_BUSY_SHARED      (UINT64_CAST 0x3)       /* 011 */
-#define MD_DIR_BUSY_EXCL        (UINT64_CAST 0x4)       /* 100 */
-#define MD_DIR_WAIT             (UINT64_CAST 0x5)       /* 101 */
-#define MD_DIR_UNOWNED          (UINT64_CAST 0x7)       /* 111 */
-
-/*
- * The MD_DIR_FORCE_ECC bit can be added directory entry write data
- * to forcing the ECC to be written as-is instead of recalculated.
- */
-
-#define MD_DIR_FORCE_ECC        (UINT64_CAST 1 << 63)
-
-/*
- * Premium SIMM directory entry shifts and masks.  Each is valid only in the
- * context(s) indicated, where A, B, and C indicate the directory entry format
- * as shown, and low and/or high indicates which double-word of the entry.
- *
- * Format A:  STATE = shared, FINE = 1
- * Format B:  STATE = shared, FINE = 0
- * Format C:  STATE != shared (FINE must be 0)
- */
-
-#define MD_PDIR_MASK            0xffffffffffff          /* Whole entry      */
-#define MD_PDIR_ECC_SHFT        0                       /* ABC low or high  */
-#define MD_PDIR_ECC_MASK        0x7f
-#define MD_PDIR_PRIO_SHFT       8                       /* ABC low          */
-#define MD_PDIR_PRIO_MASK       (0xf << 8)
-#define MD_PDIR_AX_SHFT         7                       /* ABC low          */
-#define MD_PDIR_AX_MASK         (1 << 7)
-#define MD_PDIR_AX              (1 << 7)
-#define MD_PDIR_FINE_SHFT       12                      /* ABC low          */
-#define MD_PDIR_FINE_MASK       (1 << 12)
-#define MD_PDIR_FINE            (1 << 12)
-#define MD_PDIR_OCT_SHFT        13                      /* A low            */
-#define MD_PDIR_OCT_MASK        (7 << 13)
-#define MD_PDIR_STATE_SHFT      13                      /* BC low           */
-#define MD_PDIR_STATE_MASK      (7 << 13)
-#define MD_PDIR_ONECNT_SHFT     16                      /* BC low           */
-#define MD_PDIR_ONECNT_MASK     (0x3f << 16)
-#define MD_PDIR_PTR_SHFT        22                      /* C low            */
-#define MD_PDIR_PTR_MASK        (UINT64_CAST 0x7ff << 22)
-#define MD_PDIR_VECMSB_SHFT     22                      /* AB low           */
-#define MD_PDIR_VECMSB_BITMASK  0x3ffffff
-#define MD_PDIR_VECMSB_BITSHFT  27
-#define MD_PDIR_VECMSB_MASK     (UINT64_CAST MD_PDIR_VECMSB_BITMASK << 22)
-#define MD_PDIR_CWOFF_SHFT      7                       /* C high           */
-#define MD_PDIR_CWOFF_MASK      (7 << 7)
-#define MD_PDIR_VECLSB_SHFT     10                      /* AB high          */
-#define MD_PDIR_VECLSB_BITMASK  (UINT64_CAST 0x3fffffffff)
-#define MD_PDIR_VECLSB_BITSHFT  0
-#define MD_PDIR_VECLSB_MASK     (MD_PDIR_VECLSB_BITMASK << 10)
-
-/*
- * Directory initialization values
- */
-
-#define MD_PDIR_INIT_LO         (MD_DIR_UNOWNED << MD_PDIR_STATE_SHFT | \
-                                 MD_PDIR_AX)
-#define MD_PDIR_INIT_HI         0
-#define MD_PDIR_INIT_PROT       (MD_PROT_RW << MD_PPROT_IO_SHFT | \
-                                 MD_PROT_RW << MD_PPROT_SHFT)
-
-/*
- * Standard SIMM directory entry shifts and masks.  Each is valid only in the
- * context(s) indicated, where A and C indicate the directory entry format
- * as shown, and low and/or high indicates which double-word of the entry.
- *
- * Format A:  STATE == shared
- * Format C:  STATE != shared
- */
-
-#define MD_SDIR_MASK            0xffff                  /* Whole entry      */
-#define MD_SDIR_ECC_SHFT        0                       /* AC low or high   */
-#define MD_SDIR_ECC_MASK        0x1f
-#define MD_SDIR_PRIO_SHFT       6                       /* AC low           */
-#define MD_SDIR_PRIO_MASK       (1 << 6)
-#define MD_SDIR_AX_SHFT         5                       /* AC low           */
-#define MD_SDIR_AX_MASK         (1 << 5)
-#define MD_SDIR_AX              (1 << 5)
-#define MD_SDIR_STATE_SHFT      7                       /* AC low           */
-#define MD_SDIR_STATE_MASK      (7 << 7)
-#define MD_SDIR_PTR_SHFT        10                      /* C low            */
-#define MD_SDIR_PTR_MASK        (0x3f << 10)
-#define MD_SDIR_CWOFF_SHFT      5                       /* C high           */
-#define MD_SDIR_CWOFF_MASK      (7 << 5)
-#define MD_SDIR_VECMSB_SHFT     11                      /* A low            */
-#define MD_SDIR_VECMSB_BITMASK  0x1f
-#define MD_SDIR_VECMSB_BITSHFT  7
-#define MD_SDIR_VECMSB_MASK     (MD_SDIR_VECMSB_BITMASK << 11)
-#define MD_SDIR_VECLSB_SHFT     5                       /* A high           */
-#define MD_SDIR_VECLSB_BITMASK  0x7ff
-#define MD_SDIR_VECLSB_BITSHFT  0
-#define MD_SDIR_VECLSB_MASK     (MD_SDIR_VECLSB_BITMASK << 5)
-
-/*
- * Directory initialization values
- */
-
-#define MD_SDIR_INIT_LO         (MD_DIR_UNOWNED << MD_SDIR_STATE_SHFT | \
-                                 MD_SDIR_AX)
-#define MD_SDIR_INIT_HI         0
-#define MD_SDIR_INIT_PROT       (MD_PROT_RW << MD_SPROT_SHFT)
-
-/* Protection and migration field values */
-
-#define MD_PROT_RW              (UINT64_CAST 0x6)
-#define MD_PROT_RO              (UINT64_CAST 0x3)
-#define MD_PROT_NO              (UINT64_CAST 0x0)
-#define MD_PROT_BAD             (UINT64_CAST 0x5)
-
-/* Premium SIMM protection entry shifts and masks. */
-
-#define MD_PPROT_SHFT           0                       /* Prot. field      */
-#define MD_PPROT_MASK           7
-#define MD_PPROT_MIGMD_SHFT     3                       /* Migration mode   */
-#define MD_PPROT_MIGMD_MASK     (3 << 3)
-#define MD_PPROT_REFCNT_SHFT    5                       /* Reference count  */
-#define MD_PPROT_REFCNT_WIDTH   0x7ffff
-#define MD_PPROT_REFCNT_MASK    (MD_PPROT_REFCNT_WIDTH << 5)
-
-#define MD_PPROT_IO_SHFT        45                      /* I/O Prot field   */
-#define MD_PPROT_IO_MASK        (UINT64_CAST 7 << 45)
-
-/* Standard SIMM protection entry shifts and masks. */
-
-#define MD_SPROT_SHFT           0                       /* Prot. field      */
-#define MD_SPROT_MASK           7
-#define MD_SPROT_MIGMD_SHFT     3                       /* Migration mode   */
-#define MD_SPROT_MIGMD_MASK     (3 << 3)
-#define MD_SPROT_REFCNT_SHFT    5                       /* Reference count  */
-#define MD_SPROT_REFCNT_WIDTH   0x7ff
-#define MD_SPROT_REFCNT_MASK    (MD_SPROT_REFCNT_WIDTH << 5)
-
-/* Migration modes used in protection entries */
-
-#define MD_PROT_MIGMD_IREL      (UINT64_CAST 0x3 << 3)
-#define MD_PROT_MIGMD_IABS      (UINT64_CAST 0x2 << 3)
-#define MD_PROT_MIGMD_PREL      (UINT64_CAST 0x1 << 3)
-#define MD_PROT_MIGMD_OFF       (UINT64_CAST 0x0 << 3)
-
-
-/*
- * Operations on page migration threshold register
- */
-
-#ifndef __ASSEMBLY__
-
-/*
- * LED register macros
- */
-
-#define CPU_LED_ADDR(_nasid, _slice)                                       \
-        (private.p_sn00 ?                                                  \
-         REMOTE_HUB_ADDR((_nasid), MD_UREG1_0 + ((_slice) << 5)) :         \
-         REMOTE_HUB_ADDR((_nasid), MD_LED0    + ((_slice) << 3)))
-
-#define SET_CPU_LEDS(_nasid, _slice,  _val)                                \
-        (HUB_S(CPU_LED_ADDR(_nasid, _slice), (_val)))
-
-#define SET_MY_LEDS(_v)                                                    \
-        SET_CPU_LEDS(get_nasid(), get_slice(), (_v))
-
-/*
- * Operations on Memory/Directory DIMM control register
- */
-
-#define DIRTYPE_PREMIUM 1
-#define DIRTYPE_STANDARD 0
-#define MD_MEMORY_CONFIG_DIR_TYPE_GET(region) (\
-        (REMOTE_HUB_L(region, MD_MEMORY_CONFIG) & MMC_DIR_PREMIUM_MASK) >> \
-        MMC_DIR_PREMIUM_SHFT)
-
-
-/*
- * Operations on page migration count difference and absolute threshold
- * registers
- */
-
-#define MD_MIG_DIFF_THRESH_GET(region) ( \
-        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) & \
-        MD_MIG_DIFF_THRES_VALUE_MASK)
-
-#define MD_MIG_DIFF_THRESH_SET(region, value) (                         \
-        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
-                MD_MIG_DIFF_THRES_VALID_MASK | (value)))
-
-#define MD_MIG_DIFF_THRESH_DISABLE(region) (                    \
-        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
-                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
-                             & ~MD_MIG_DIFF_THRES_VALID_MASK))
-
-#define MD_MIG_DIFF_THRESH_ENABLE(region) (                     \
-        REMOTE_HUB_S((region), MD_MIG_DIFF_THRESH,                      \
-                REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH)              \
-                             | MD_MIG_DIFF_THRES_VALID_MASK))
-
-#define MD_MIG_DIFF_THRESH_IS_ENABLED(region) (                         \
-        REMOTE_HUB_L((region), MD_MIG_DIFF_THRESH) &                    \
-               MD_MIG_DIFF_THRES_VALID_MASK)
-
-#define MD_MIG_VALUE_THRESH_GET(region) (                               \
-        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &  \
-        MD_MIG_VALUE_THRES_VALUE_MASK)
-
-#define MD_MIG_VALUE_THRESH_SET(region, value) (                        \
-        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
-                MD_MIG_VALUE_THRES_VALID_MASK | (value)))
-
-#define MD_MIG_VALUE_THRESH_DISABLE(region) (                   \
-        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
-                REMOTE_HUB_L(region, MD_MIG_VALUE_THRESH)               \
-                             & ~MD_MIG_VALUE_THRES_VALID_MASK))
-
-#define MD_MIG_VALUE_THRESH_ENABLE(region) (                    \
-        REMOTE_HUB_S((region), MD_MIG_VALUE_THRESH,                     \
-                REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH)             \
-                             | MD_MIG_VALUE_THRES_VALID_MASK))
-
-#define MD_MIG_VALUE_THRESH_IS_ENABLED(region) (                        \
-        REMOTE_HUB_L((region), MD_MIG_VALUE_THRESH) &                    \
-               MD_MIG_VALUE_THRES_VALID_MASK)
-
-/*
- * Operations on page migration candidate register
- */
-
-#define MD_MIG_CANDIDATE_GET(my_region_id) ( \
-        REMOTE_HUB_L((my_region_id), MD_MIG_CANDIDATE_CLR))
-
-#define MD_MIG_CANDIDATE_HWPFN(value) ((value) & MD_MIG_CANDIDATE_ADDR_MASK)
-
-#define MD_MIG_CANDIDATE_NODEID(value) ( \
-        ((value) & MD_MIG_CANDIDATE_NODEID_MASK) >> MD_MIG_CANDIDATE_NODEID_SHFT)
-
-#define MD_MIG_CANDIDATE_TYPE(value) ( \
-        ((value) & MD_MIG_CANDIDATE_TYPE_MASK) >> MD_MIG_CANDIDATE_TYPE_SHFT)
-
-#define MD_MIG_CANDIDATE_VALID(value) ( \
-        ((value) & MD_MIG_CANDIDATE_VALID_MASK) >> MD_MIG_CANDIDATE_VALID_SHFT)
-
-/*
- * Macros to retrieve fields in the protection entry
- */
-
-/* for Premium SIMM */
-#define MD_PPROT_REFCNT_GET(value) ( \
-        ((value) & MD_PPROT_REFCNT_MASK) >> MD_PPROT_REFCNT_SHFT)
-
-#define MD_PPROT_MIGMD_GET(value) ( \
-        ((value) & MD_PPROT_MIGMD_MASK) >> MD_PPROT_MIGMD_SHFT)
-
-/* for Standard SIMM */
-#define MD_SPROT_REFCNT_GET(value) ( \
-        ((value) & MD_SPROT_REFCNT_MASK) >> MD_SPROT_REFCNT_SHFT)
-
-#define MD_SPROT_MIGMD_GET(value) ( \
-        ((value) & MD_SPROT_MIGMD_MASK) >> MD_SPROT_MIGMD_SHFT)
-
-/*
- * Format of dir_error, mem_error, protocol_error and misc_error registers
- */
-
-struct dir_error_reg {
-        u64     uce_vld:   1,   /*    63: valid directory uce   */
-                ae_vld:    1,   /*    62: valid dir prot ecc error */
-                ce_vld:    1,   /*    61: valid correctable ECC err*/
-                rsvd1:    19,   /* 60-42: reserved              */
-                bad_prot:  3,   /* 41-39: encoding, bad access rights*/
-                bad_syn:   7,   /* 38-32: bad dir syndrome      */
-                rsvd2:     2,   /* 31-30: reserved              */
-                hspec_addr:27,  /* 29-03: bddir space bad entry */
-                uce_ovr:   1,   /*     2: multiple dir uce's    */
-                ae_ovr:    1,   /*     1: multiple prot ecc errs*/
-                ce_ovr:    1;   /*     0: multiple correctable errs */
-};
-
-typedef union md_dir_error {
-        u64     derr_reg;       /* the entire register          */
-        struct dir_error_reg derr_fmt;  /* the register format          */
-} md_dir_error_t;
-
-
-struct mem_error_reg {
-        u64     uce_vld:   1,   /*    63: valid memory uce      */
-                ce_vld:    1,   /*    62: valid correctable ECC err*/
-                rsvd1:    22,   /* 61-40: reserved              */
-                bad_syn:   8,   /* 39-32: bad mem ecc syndrome  */
-                address:  29,   /* 31-03: bad entry pointer     */
-                rsvd2:     1,   /*     2: reserved              */
-                uce_ovr:   1,   /*     1: multiple mem uce's    */
-                ce_ovr:    1;   /*     0: multiple correctable errs */
-};
-
-
-typedef union md_mem_error {
-        u64     merr_reg;       /* the entire register          */
-        struct mem_error_reg  merr_fmt; /* format of the mem_error reg  */
-} md_mem_error_t;
-
-
-struct proto_error_reg {
-        u64     valid:     1,   /*    63: valid protocol error  */
-                rsvd1:     2,   /* 62-61: reserved              */
-                initiator:11,   /* 60-50: id of request initiator*/
-                backoff:   2,   /* 49-48: backoff control       */
-                msg_type:  8,   /* 47-40: type of request       */
-                access:    2,   /* 39-38: access rights of initiator*/
-                priority:  1,   /*    37: priority level of requestor*/
-                dir_state: 4,   /* 36-33: state of directory    */
-                pointer_me:1,   /*    32: initiator same as dir ptr */
-                address:  29,   /* 31-03: request address       */
-                rsvd2:     2,   /* 02-01: reserved              */
-                overrun:   1;   /*     0: multiple protocol errs */
-};
-
-typedef union md_proto_error {
-        u64     perr_reg;       /* the entire register          */
-        struct proto_error_reg  perr_fmt; /* format of the register     */
-} md_proto_error_t;
-
-
-struct md_sdir_high_fmt {
-        unsigned short sd_hi_bvec : 11,
-                       sd_hi_ecc  : 5;
-};
-
-
-typedef union md_sdir_high {
-        /* The 16 bits of standard directory, upper word */
-        unsigned short sd_hi_val;
-        struct  md_sdir_high_fmt sd_hi_fmt;
-}md_sdir_high_t;
-
-
-struct md_sdir_low_shared_fmt {
-        /* The meaning of lower directory, shared */
-        unsigned short  sds_lo_bvec  : 5,
-                        sds_lo_unused: 1,
-                        sds_lo_state : 3,
-                        sds_lo_prio  : 1,
-                        sds_lo_ax    : 1,
-                        sds_lo_ecc   : 5;
-};
-
-struct md_sdir_low_exclusive_fmt {
-        /* The meaning of lower directory, exclusive */
-        unsigned short  sde_lo_ptr   : 6,
-                        sde_lo_state : 3,
-                        sde_lo_prio  : 1,
-                        sde_lo_ax    : 1,
-                        sde_lo_ecc   : 5;
-};
-
-
-typedef union md_sdir_low {
-        /* The 16 bits of standard directory, lower word */
-        unsigned short  sd_lo_val;
-        struct  md_sdir_low_exclusive_fmt sde_lo_fmt;
-        struct  md_sdir_low_shared_fmt sds_lo_fmt;
-}md_sdir_low_t;
-
-
-
-struct md_pdir_high_fmt {
-        u64     pd_hi_unused   : 16,
-                pd_hi_bvec     : 38,
-                pd_hi_unused1  : 3,
-                pd_hi_ecc      : 7;
-};
-
-
-typedef union md_pdir_high {
-        /* The 48 bits of standard directory, upper word */
-        u64     pd_hi_val;
-        struct md_pdir_high_fmt pd_hi_fmt;
-}md_pdir_high_t;
-
-
-struct md_pdir_low_shared_fmt {
-        /* The meaning of lower directory, shared */
-        u64     pds_lo_unused   : 16,
-                pds_lo_bvec     : 26,
-                pds_lo_cnt      :  6,
-                pds_lo_state    :  3,
-                pds_lo_ste      :  1,
-                pds_lo_prio     :  4,
-                pds_lo_ax       :  1,
-                pds_lo_ecc      :  7;
-};
-
-struct md_pdir_low_exclusive_fmt {
-        /* The meaning of lower directory, exclusive */
-        u64     pde_lo_unused   : 31,
-                pde_lo_ptr      : 11,
-                pde_lo_unused1  :  6,
-                pde_lo_state    :  3,
-                pde_lo_ste      :  1,
-                pde_lo_prio     :  4,
-                pde_lo_ax       :  1,
-                pde_lo_ecc      :  7;
-};
-
-
-typedef union md_pdir_loent {
-        /* The 48 bits of premium directory, lower word */
-        u64     pd_lo_val;
-        struct md_pdir_low_exclusive_fmt pde_lo_fmt;
-        struct md_pdir_low_shared_fmt   pds_lo_fmt;
-}md_pdir_low_t;
-
-
-/*
- *   the following two "union" definitions and two
- *   "struct" definitions are used in vmdump.c to
- *   represent directory memory information.
- */
-
-typedef union   md_dir_high     {
-        md_sdir_high_t  md_sdir_high;
-        md_pdir_high_t  md_pdir_high;
-} md_dir_high_t;
-
-typedef union   md_dir_low      {
-        md_sdir_low_t   md_sdir_low;
-        md_pdir_low_t   md_pdir_low;
-} md_dir_low_t;
-
-typedef struct  bddir_entry     {
-        md_dir_low_t    md_dir_low;
-        md_dir_high_t   md_dir_high;
-} bddir_entry_t;
-
-typedef struct  dir_mem_entry   {
-        u64             prcpf[MAX_REGIONS];
-        bddir_entry_t   directory_words[MD_PAGE_SIZE/CACHE_SLINE_SIZE];
-} dir_mem_entry_t;
-
-
-
-typedef union md_perf_sel {
-        u64     perf_sel_reg;
-        struct  {
-                u64     perf_rsvd : 60,
-                        perf_en   :  1,
-                        perf_sel  :  3;
-        } perf_sel_bits;
-} md_perf_sel_t;
-
-typedef union md_perf_cnt {
-        u64     perf_cnt;
-        struct  {
-                u64     perf_rsvd : 44,
-                        perf_cnt  : 20;
-        } perf_cnt_bits;
-} md_perf_cnt_t;
-
-
-#endif /* !__ASSEMBLY__ */
-
-
-#define DIR_ERROR_VALID_MASK    0xe000000000000000
-#define DIR_ERROR_VALID_SHFT    61
-#define DIR_ERROR_VALID_UCE     0x8000000000000000
-#define DIR_ERROR_VALID_AE      0x4000000000000000
-#define DIR_ERROR_VALID_CE      0x2000000000000000
-
-#define MEM_ERROR_VALID_MASK    0xc000000000000000
-#define MEM_ERROR_VALID_SHFT    62
-#define MEM_ERROR_VALID_UCE     0x8000000000000000
-#define MEM_ERROR_VALID_CE      0x4000000000000000
-
-#define PROTO_ERROR_VALID_MASK  0x8000000000000000
-
-#define MISC_ERROR_VALID_MASK   0x3ff
-
-/*
- * Mask for hspec address that is stored in the dir error register.
- * This represents bits 29 through 3.
- */
-#define DIR_ERR_HSPEC_MASK      0x3ffffff8
-#define ERROR_HSPEC_MASK        0x3ffffff8
-#define ERROR_HSPEC_SHFT        3
-#define ERROR_ADDR_MASK         0xfffffff8
-#define ERROR_ADDR_SHFT         3
-
-/*
- * MD_MISC_ERROR register defines.
- */
-
-#define MMCE_VALID_MASK         0x3ff
-#define MMCE_ILL_MSG_SHFT       8
-#define MMCE_ILL_MSG_MASK       (UINT64_CAST 0x03 << MMCE_ILL_MSG_SHFT)
-#define MMCE_ILL_REV_SHFT       6
-#define MMCE_ILL_REV_MASK       (UINT64_CAST 0x03 << MMCE_ILL_REV_SHFT)
-#define MMCE_LONG_PACK_SHFT     4
-#define MMCE_LONG_PACK_MASK     (UINT64_CAST 0x03 << MMCE_lONG_PACK_SHFT)
-#define MMCE_SHORT_PACK_SHFT    2
-#define MMCE_SHORT_PACK_MASK    (UINT64_CAST 0x03 << MMCE_SHORT_PACK_SHFT)
-#define MMCE_BAD_DATA_SHFT      0
-#define MMCE_BAD_DATA_MASK      (UINT64_CAST 0x03 << MMCE_BAD_DATA_SHFT)
-
-
-#define MD_PERF_COUNTERS        6
-#define MD_PERF_SETS            6
-
-#define MEM_DIMM_MASK                           0xe0000000
-#define MEM_DIMM_SHFT                           29
-
-#endif /* _ASM_SN_SN0_HUBMD_H */
diff --git a/include/asm-mips/sn/sn0/hubni.h b/include/asm-mips/sn/sn0/hubni.h
deleted file mode 100644
index b40d3ef97a12..000000000000
--- a/include/asm-mips/sn/sn0/hubni.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/hubni.h>, Revision 1.27.
- *
- * Copyright (C) 1992-1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SGI_SN0_HUBNI_H
-#define _ASM_SGI_SN0_HUBNI_H
-
-#ifndef __ASSEMBLY__
-#include <linux/types.h>
-#endif
-
-/*
- * Hub Network Interface registers
- *
- * All registers in this file are subject to change until Hub chip tapeout.
- */
-
-#define NI_BASE                 0x600000
-#define NI_BASE_TABLES          0x630000
-
-#define NI_STATUS_REV_ID        0x600000 /* Hub network status, rev, and ID */
-#define NI_PORT_RESET           0x600008 /* Reset the network interface     */
-#define NI_PROTECTION           0x600010 /* NI register access permissions  */
-#define NI_GLOBAL_PARMS         0x600018 /* LLP parameters                  */
-#define NI_SCRATCH_REG0         0x600100 /* Scratch register 0 (64 bits)    */
-#define NI_SCRATCH_REG1         0x600108 /* Scratch register 1 (64 bits)    */
-#define NI_DIAG_PARMS           0x600110 /* Parameters for diags            */
-
-#define NI_VECTOR_PARMS         0x600200 /* Vector PIO routing parameters   */
-#define NI_VECTOR               0x600208 /* Vector PIO route                */
-#define NI_VECTOR_DATA          0x600210 /* Vector PIO data                 */
-#define NI_VECTOR_STATUS        0x600300 /* Vector PIO return status        */
-#define NI_RETURN_VECTOR        0x600308 /* Vector PIO return vector        */
-#define NI_VECTOR_READ_DATA     0x600310 /* Vector PIO read data            */
-#define NI_VECTOR_CLEAR         0x600380 /* Vector PIO read & clear status  */
-
-#define NI_IO_PROTECT           0x600400 /* PIO protection bits             */
-#define NI_IO_PROT_OVRRD        0x600408 /* PIO protection bit override     */
-
-#define NI_AGE_CPU0_MEMORY      0x600500 /* CPU 0 memory age control        */
-#define NI_AGE_CPU0_PIO         0x600508 /* CPU 0 PIO age control           */
-#define NI_AGE_CPU1_MEMORY      0x600510 /* CPU 1 memory age control        */
-#define NI_AGE_CPU1_PIO         0x600518 /* CPU 1 PIO age control           */
-#define NI_AGE_GBR_MEMORY       0x600520 /* GBR memory age control          */
-#define NI_AGE_GBR_PIO          0x600528 /* GBR PIO age control             */
-#define NI_AGE_IO_MEMORY        0x600530 /* IO memory age control           */
-#define NI_AGE_IO_PIO           0x600538 /* IO PIO age control              */
-#define NI_AGE_REG_MIN          NI_AGE_CPU0_MEMORY
-#define NI_AGE_REG_MAX          NI_AGE_IO_PIO
-
-#define NI_PORT_PARMS           0x608000 /* LLP Parameters                  */
-#define NI_PORT_ERROR           0x608008 /* LLP Errors                      */
-#define NI_PORT_ERROR_CLEAR     0x608088 /* Clear the error bits            */
-
-#define NI_META_TABLE0          0x638000 /* First meta routing table entry  */
-#define NI_META_TABLE(_x)       (NI_META_TABLE0 + (8 * (_x)))
-#define NI_META_ENTRIES         32
-
-#define NI_LOCAL_TABLE0         0x638100 /* First local routing table entry */
-#define NI_LOCAL_TABLE(_x)      (NI_LOCAL_TABLE0 + (8 * (_x)))
-#define NI_LOCAL_ENTRIES        16
-
-/*
- * NI_STATUS_REV_ID mask and shift definitions
- * Have to use UINT64_CAST instead of 'L' suffix, for assembler.
- */
-
-#define NSRI_8BITMODE_SHFT      30
-#define NSRI_8BITMODE_MASK      (UINT64_CAST 0x1 << 30)
-#define NSRI_LINKUP_SHFT        29
-#define NSRI_LINKUP_MASK        (UINT64_CAST 0x1 << 29)
-#define NSRI_DOWNREASON_SHFT    28              /* 0=failed, 1=never came   */
-#define NSRI_DOWNREASON_MASK    (UINT64_CAST 0x1 << 28) /*    out of reset. */
-#define NSRI_MORENODES_SHFT     18
-#define NSRI_MORENODES_MASK     (UINT64_CAST 1 << 18)   /* Max. # of nodes  */
-#define  MORE_MEMORY            0
-#define  MORE_NODES             1
-#define NSRI_REGIONSIZE_SHFT    17
-#define NSRI_REGIONSIZE_MASK    (UINT64_CAST 1 << 17)   /* Granularity      */
-#define  REGIONSIZE_FINE        1
-#define  REGIONSIZE_COARSE      0
-#define NSRI_NODEID_SHFT        8
-#define NSRI_NODEID_MASK        (UINT64_CAST 0x1ff << 8)/* Node (Hub) ID    */
-#define NSRI_REV_SHFT           4
-#define NSRI_REV_MASK           (UINT64_CAST 0xf << 4)  /* Chip Revision    */
-#define NSRI_CHIPID_SHFT        0
-#define NSRI_CHIPID_MASK        (UINT64_CAST 0xf)       /* Chip type ID     */
-
-/*
- * In fine mode, each node is a region.  In coarse mode, there are
- * eight nodes per region.
- */
-#define NASID_TO_FINEREG_SHFT   0
-#define NASID_TO_COARSEREG_SHFT 3
-
-/* NI_PORT_RESET mask definitions */
-
-#define NPR_PORTRESET           (UINT64_CAST 1 << 7)    /* Send warm reset  */
-#define NPR_LINKRESET           (UINT64_CAST 1 << 1)    /* Send link reset  */
-#define NPR_LOCALRESET          (UINT64_CAST 1)         /* Reset entire hub */
-
-/* NI_PROTECTION mask and shift definitions */
-
-#define NPROT_RESETOK           (UINT64_CAST 1)
-
-/* NI_GLOBAL_PARMS mask and shift definitions */
-
-#define NGP_MAXRETRY_SHFT       48              /* Maximum retries          */
-#define NGP_MAXRETRY_MASK       (UINT64_CAST 0x3ff << 48)
-#define NGP_TAILTOWRAP_SHFT     32              /* Tail timeout wrap        */
-#define NGP_TAILTOWRAP_MASK     (UINT64_CAST 0xffff << 32)
-
-#define NGP_CREDITTOVAL_SHFT    16              /* Tail timeout wrap        */
-#define NGP_CREDITTOVAL_MASK    (UINT64_CAST 0xf << 16)
-#define NGP_TAILTOVAL_SHFT      4               /* Tail timeout value       */
-#define NGP_TAILTOVAL_MASK      (UINT64_CAST 0xf << 4)
-
-/* NI_DIAG_PARMS mask and shift definitions */
-
-#define NDP_PORTTORESET         (UINT64_CAST 1 << 18)   /* Port tmout reset */
-#define NDP_LLP8BITMODE         (UINT64_CAST 1 << 12)   /* LLP 8-bit mode   */
-#define NDP_PORTDISABLE         (UINT64_CAST 1 <<  6)   /* Port disable     */
-#define NDP_SENDERROR           (UINT64_CAST 1)         /* Send data error  */
-
-/*
- * NI_VECTOR_PARMS mask and shift definitions.
- * TYPE may be any of the first four PIOTYPEs defined under NI_VECTOR_STATUS.
- */
-
-#define NVP_PIOID_SHFT          40
-#define NVP_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
-#define NVP_WRITEID_SHFT        32
-#define NVP_WRITEID_MASK        (UINT64_CAST 0xff << 32)
-#define NVP_ADDRESS_MASK        (UINT64_CAST 0xffff8)   /* Bits 19:3        */
-#define NVP_TYPE_SHFT           0
-#define NVP_TYPE_MASK           (UINT64_CAST 0x3)
-
-/* NI_VECTOR_STATUS mask and shift definitions */
-
-#define NVS_VALID               (UINT64_CAST 1 << 63)
-#define NVS_OVERRUN             (UINT64_CAST 1 << 62)
-#define NVS_TARGET_SHFT         51
-#define NVS_TARGET_MASK         (UINT64_CAST 0x3ff << 51)
-#define NVS_PIOID_SHFT          40
-#define NVS_PIOID_MASK          (UINT64_CAST 0x3ff << 40)
-#define NVS_WRITEID_SHFT        32
-#define NVS_WRITEID_MASK        (UINT64_CAST 0xff << 32)
-#define NVS_ADDRESS_MASK        (UINT64_CAST 0xfffffff8)   /* Bits 31:3     */
-#define NVS_TYPE_SHFT           0
-#define NVS_TYPE_MASK           (UINT64_CAST 0x7)
-#define NVS_ERROR_MASK          (UINT64_CAST 0x4)  /* bit set means error */
-
-
-#define  PIOTYPE_READ           0       /* VECTOR_PARMS and VECTOR_STATUS   */
-#define  PIOTYPE_WRITE          1       /* VECTOR_PARMS and VECTOR_STATUS   */
-#define  PIOTYPE_UNDEFINED      2       /* VECTOR_PARMS and VECTOR_STATUS   */
-#define  PIOTYPE_EXCHANGE       3       /* VECTOR_PARMS and VECTOR_STATUS   */
-#define  PIOTYPE_ADDR_ERR       4       /* VECTOR_STATUS only               */
-#define  PIOTYPE_CMD_ERR        5       /* VECTOR_STATUS only               */
-#define  PIOTYPE_PROT_ERR       6       /* VECTOR_STATUS only               */
-#define  PIOTYPE_UNKNOWN        7       /* VECTOR_STATUS only               */
-
-/* NI_AGE_XXX mask and shift definitions */
-
-#define NAGE_VCH_SHFT           10
-#define NAGE_VCH_MASK           (UINT64_CAST 3 << 10)
-#define NAGE_CC_SHFT            8
-#define NAGE_CC_MASK            (UINT64_CAST 3 << 8)
-#define NAGE_AGE_SHFT           0
-#define NAGE_AGE_MASK           (UINT64_CAST 0xff)
-#define NAGE_MASK               (NAGE_VCH_MASK | NAGE_CC_MASK | NAGE_AGE_MASK)
-
-#define  VCHANNEL_A             0
-#define  VCHANNEL_B             1
-#define  VCHANNEL_ANY           2
-
-/* NI_PORT_PARMS mask and shift definitions */
-
-#define NPP_NULLTO_SHFT         10
-#define NPP_NULLTO_MASK         (UINT64_CAST 0x3f << 16)
-#define NPP_MAXBURST_SHFT       0
-#define NPP_MAXBURST_MASK       (UINT64_CAST 0x3ff)
-#define NPP_RESET_DFLT_HUB20    ((UINT64_CAST 1     << NPP_NULLTO_SHFT) | \
-                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
-#define NPP_RESET_DEFAULTS      ((UINT64_CAST 6     << NPP_NULLTO_SHFT) | \
-                                 (UINT64_CAST 0x3f0 << NPP_MAXBURST_SHFT))
-
-
-/* NI_PORT_ERROR mask and shift definitions */
-
-#define NPE_LINKRESET           (UINT64_CAST 1 << 37)
-#define NPE_INTERNALERROR       (UINT64_CAST 1 << 36)
-#define NPE_BADMESSAGE          (UINT64_CAST 1 << 35)
-#define NPE_BADDEST             (UINT64_CAST 1 << 34)
-#define NPE_FIFOOVERFLOW        (UINT64_CAST 1 << 33)
-#define NPE_CREDITTO_SHFT       28
-#define NPE_CREDITTO_MASK       (UINT64_CAST 0xf << 28)
-#define NPE_TAILTO_SHFT         24
-#define NPE_TAILTO_MASK         (UINT64_CAST 0xf << 24)
-#define NPE_RETRYCOUNT_SHFT     16
-#define NPE_RETRYCOUNT_MASK     (UINT64_CAST 0xff << 16)
-#define NPE_CBERRCOUNT_SHFT     8
-#define NPE_CBERRCOUNT_MASK     (UINT64_CAST 0xff << 8)
-#define NPE_SNERRCOUNT_SHFT     0
-#define NPE_SNERRCOUNT_MASK     (UINT64_CAST 0xff << 0)
-#define NPE_MASK                0x3effffffff
-
-#define NPE_COUNT_MAX           0xff
-
-#define NPE_FATAL_ERRORS        (NPE_LINKRESET | NPE_INTERNALERROR |    \
-                                 NPE_BADMESSAGE | NPE_BADDEST |         \
-                                 NPE_FIFOOVERFLOW | NPE_CREDITTO_MASK | \
-                                 NPE_TAILTO_MASK)
-
-/* NI_META_TABLE mask and shift definitions */
-
-#define NMT_EXIT_PORT_MASK (UINT64_CAST 0xf)
-
-/* NI_LOCAL_TABLE mask and shift definitions */
-
-#define NLT_EXIT_PORT_MASK (UINT64_CAST 0xf)
-
-#ifndef __ASSEMBLY__
-
-typedef union   hubni_port_error_u {
-        u64     nipe_reg_value;
-        struct {
-            u64 nipe_rsvd:      26,     /* unused */
-                nipe_lnk_reset:  1,     /* link reset */
-                nipe_intl_err:   1,     /* internal error */
-                nipe_bad_msg:    1,     /* bad message */
-                nipe_bad_dest:   1,     /* bad dest     */
-                nipe_fifo_ovfl:  1,     /* fifo overflow */
-                nipe_rsvd1:      1,     /* unused */
-                nipe_credit_to:  4,     /* credit timeout */
-                nipe_tail_to:    4,     /* tail timeout */
-                nipe_retry_cnt:  8,     /* retry error count */
-                nipe_cb_cnt:     8,     /* checkbit error count */
-                nipe_sn_cnt:     8;     /* sequence number count */
-        } nipe_fields_s;
-} hubni_port_error_t;
-
-#define NI_LLP_RETRY_MAX        0xff
-#define NI_LLP_CB_MAX           0xff
-#define NI_LLP_SN_MAX           0xff
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_SGI_SN0_HUBNI_H */
diff --git a/include/asm-mips/sn/sn0/hubpi.h b/include/asm-mips/sn/sn0/hubpi.h
deleted file mode 100644
index e39f5f9da040..000000000000
--- a/include/asm-mips/sn/sn0/hubpi.h
+++ /dev/null
@@ -1,409 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/hubpi.h>, revision 1.28.
- *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SN_SN0_HUBPI_H
-#define _ASM_SN_SN0_HUBPI_H
-
-#include <linux/types.h>
-
-/*
- * Hub I/O interface registers
- *
- * All registers in this file are subject to change until Hub chip tapeout.
- * All register "addresses" are actually offsets.  Use the LOCAL_HUB
- * or REMOTE_HUB macros to synthesize an actual address
- */
-
-#define PI_BASE                 0x000000
-
-/* General protection and control registers */
-
-#define PI_CPU_PROTECT          0x000000 /* CPU Protection                  */
-#define PI_PROT_OVERRD          0x000008 /* Clear CPU Protection bit        */
-#define PI_IO_PROTECT           0x000010 /* Interrupt Pending Protection    */
-#define PI_REGION_PRESENT       0x000018 /* Indicates whether region exists */
-#define PI_CPU_NUM              0x000020 /* CPU Number ID                   */
-#define PI_CALIAS_SIZE          0x000028 /* Cached Alias Size               */
-#define PI_MAX_CRB_TIMEOUT      0x000030 /* Maximum Timeout for CRB         */
-#define PI_CRB_SFACTOR          0x000038 /* Scale factor for CRB timeout    */
-
-/* CALIAS values */
-#define PI_CALIAS_SIZE_0        0
-#define PI_CALIAS_SIZE_4K       1
-#define PI_CALIAS_SIZE_8K       2
-#define PI_CALIAS_SIZE_16K      3
-#define PI_CALIAS_SIZE_32K      4
-#define PI_CALIAS_SIZE_64K      5
-#define PI_CALIAS_SIZE_128K     6
-#define PI_CALIAS_SIZE_256K     7
-#define PI_CALIAS_SIZE_512K     8
-#define PI_CALIAS_SIZE_1M       9
-#define PI_CALIAS_SIZE_2M       10
-#define PI_CALIAS_SIZE_4M       11
-#define PI_CALIAS_SIZE_8M       12
-#define PI_CALIAS_SIZE_16M      13
-#define PI_CALIAS_SIZE_32M      14
-#define PI_CALIAS_SIZE_64M      15
-
-/* Processor control and status checking */
-
-#define PI_CPU_PRESENT_A        0x000040 /* CPU Present A                   */
-#define PI_CPU_PRESENT_B        0x000048 /* CPU Present B                   */
-#define PI_CPU_ENABLE_A         0x000050 /* CPU Enable A                    */
-#define PI_CPU_ENABLE_B         0x000058 /* CPU Enable B                    */
-#define PI_REPLY_LEVEL          0x000060 /* Reply Level                     */
-#define PI_HARDRESET_BIT        0x020068 /* Bit cleared by s/w on SR        */
-#define PI_NMI_A                0x000070 /* NMI to CPU A                    */
-#define PI_NMI_B                0x000078 /* NMI to CPU B                    */
-#define PI_NMI_OFFSET           (PI_NMI_B - PI_NMI_A)
-#define PI_SOFTRESET            0x000080 /* Softreset (to both CPUs)        */
-
-/* Regular Interrupt register checking.  */
-
-#define PI_INT_PEND_MOD         0x000090 /* Write to set pending ints       */
-#define PI_INT_PEND0            0x000098 /* Read to get pending ints        */
-#define PI_INT_PEND1            0x0000a0 /* Read to get pending ints        */
-#define PI_INT_MASK0_A          0x0000a8 /* Interrupt Mask 0 for CPU A      */
-#define PI_INT_MASK1_A          0x0000b0 /* Interrupt Mask 1 for CPU A      */
-#define PI_INT_MASK0_B          0x0000b8 /* Interrupt Mask 0 for CPU B      */
-#define PI_INT_MASK1_B          0x0000c0 /* Interrupt Mask 1 for CPU B      */
-
-#define PI_INT_MASK_OFFSET      0x10     /* Offset from A to B              */
-
-/* Crosscall interrupts */
-
-#define PI_CC_PEND_SET_A        0x0000c8 /* CC Interrupt Pending Set, CPU A */
-#define PI_CC_PEND_SET_B        0x0000d0 /* CC Interrupt Pending Set, CPU B */
-#define PI_CC_PEND_CLR_A        0x0000d8 /* CC Interrupt Pending Clr, CPU A */
-#define PI_CC_PEND_CLR_B        0x0000e0 /* CC Interrupt Pending Clr, CPU B */
-#define PI_CC_MASK              0x0000e8 /* CC Interrupt mask               */
-
-#define PI_INT_SET_OFFSET       0x08     /* Offset from A to B              */
-
-/* Realtime Counter and Profiler control registers */
-
-#define PI_RT_COUNT             0x030100 /* Real Time Counter               */
-#define PI_RT_COMPARE_A         0x000108 /* Real Time Compare A             */
-#define PI_RT_COMPARE_B         0x000110 /* Real Time Compare B             */
-#define PI_PROFILE_COMPARE      0x000118 /* L5 int to both cpus when == RTC */
-#define PI_RT_PEND_A            0x000120 /* Set if RT int for A pending     */
-#define PI_RT_PEND_B            0x000128 /* Set if RT int for B pending     */
-#define PI_PROF_PEND_A          0x000130 /* Set if Prof int for A pending   */
-#define PI_PROF_PEND_B          0x000138 /* Set if Prof int for B pending   */
-#define PI_RT_EN_A              0x000140 /* RT int for CPU A enable         */
-#define PI_RT_EN_B              0x000148 /* RT int for CPU B enable         */
-#define PI_PROF_EN_A            0x000150 /* PROF int for CPU A enable       */
-#define PI_PROF_EN_B            0x000158 /* PROF int for CPU B enable       */
-#define PI_RT_LOCAL_CTRL        0x000160 /* RT control register             */
-#define PI_RT_FILTER_CTRL       0x000168 /* GCLK Filter control register    */
-
-#define PI_COUNT_OFFSET         0x08     /* A to B offset for all counts    */
-
-/* Built-In Self Test support */
-
-#define PI_BIST_WRITE_DATA      0x000200 /* BIST write data                 */
-#define PI_BIST_READ_DATA       0x000208 /* BIST read data                  */
-#define PI_BIST_COUNT_TARG      0x000210 /* BIST Count and Target           */
-#define PI_BIST_READY           0x000218 /* BIST Ready indicator            */
-#define PI_BIST_SHIFT_LOAD      0x000220 /* BIST control                    */
-#define PI_BIST_SHIFT_UNLOAD    0x000228 /* BIST control                    */
-#define PI_BIST_ENTER_RUN       0x000230 /* BIST control                    */
-
-/* Graphics control registers */
-
-#define PI_GFX_PAGE_A           0x000300 /* Graphics page A                 */
-#define PI_GFX_CREDIT_CNTR_A    0x000308 /* Graphics credit counter A       */
-#define PI_GFX_BIAS_A           0x000310 /* Graphics bias A                 */
-#define PI_GFX_INT_CNTR_A       0x000318 /* Graphics interrupt counter A    */
-#define PI_GFX_INT_CMP_A        0x000320 /* Graphics interrupt comparator A */
-#define PI_GFX_PAGE_B           0x000328 /* Graphics page B                 */
-#define PI_GFX_CREDIT_CNTR_B    0x000330 /* Graphics credit counter B       */
-#define PI_GFX_BIAS_B           0x000338 /* Graphics bias B                 */
-#define PI_GFX_INT_CNTR_B       0x000340 /* Graphics interrupt counter B    */
-#define PI_GFX_INT_CMP_B        0x000348 /* Graphics interrupt comparator B */
-
-#define PI_GFX_OFFSET           (PI_GFX_PAGE_B - PI_GFX_PAGE_A)
-#define PI_GFX_PAGE_ENABLE      0x0000010000000000LL
-
-/* Error and timeout registers */
-#define PI_ERR_INT_PEND         0x000400 /* Error Interrupt Pending         */
-#define PI_ERR_INT_MASK_A       0x000408 /* Error Interrupt mask for CPU A  */
-#define PI_ERR_INT_MASK_B       0x000410 /* Error Interrupt mask for CPU B  */
-#define PI_ERR_STACK_ADDR_A     0x000418 /* Error stack address for CPU A   */
-#define PI_ERR_STACK_ADDR_B     0x000420 /* Error stack address for CPU B   */
-#define PI_ERR_STACK_SIZE       0x000428 /* Error Stack Size                */
-#define PI_ERR_STATUS0_A        0x000430 /* Error Status 0A                 */
-#define PI_ERR_STATUS0_A_RCLR   0x000438 /* Error Status 0A clear on read   */
-#define PI_ERR_STATUS1_A        0x000440 /* Error Status 1A                 */
-#define PI_ERR_STATUS1_A_RCLR   0x000448 /* Error Status 1A clear on read   */
-#define PI_ERR_STATUS0_B        0x000450 /* Error Status 0B                 */
-#define PI_ERR_STATUS0_B_RCLR   0x000458 /* Error Status 0B clear on read   */
-#define PI_ERR_STATUS1_B        0x000460 /* Error Status 1B                 */
-#define PI_ERR_STATUS1_B_RCLR   0x000468 /* Error Status 1B clear on read   */
-#define PI_SPOOL_CMP_A          0x000470 /* Spool compare for CPU A         */
-#define PI_SPOOL_CMP_B          0x000478 /* Spool compare for CPU B         */
-#define PI_CRB_TIMEOUT_A        0x000480 /* Timed out CRB entries for A     */
-#define PI_CRB_TIMEOUT_B        0x000488 /* Timed out CRB entries for B     */
-#define PI_SYSAD_ERRCHK_EN      0x000490 /* Enables SYSAD error checking    */
-#define PI_BAD_CHECK_BIT_A      0x000498 /* Force SYSAD check bit error     */
-#define PI_BAD_CHECK_BIT_B      0x0004a0 /* Force SYSAD check bit error     */
-#define PI_NACK_CNT_A           0x0004a8 /* Consecutive NACK counter        */
-#define PI_NACK_CNT_B           0x0004b0 /*     "       " for CPU B         */
-#define PI_NACK_CMP             0x0004b8 /* NACK count compare              */
-#define PI_STACKADDR_OFFSET     (PI_ERR_STACK_ADDR_B - PI_ERR_STACK_ADDR_A)
-#define PI_ERRSTAT_OFFSET       (PI_ERR_STATUS0_B - PI_ERR_STATUS0_A)
-#define PI_RDCLR_OFFSET         (PI_ERR_STATUS0_A_RCLR - PI_ERR_STATUS0_A)
-
-/* Bits in PI_ERR_INT_PEND */
-#define PI_ERR_SPOOL_CMP_B      0x00000001      /* Spool end hit high water */
-#define PI_ERR_SPOOL_CMP_A      0x00000002
-#define PI_ERR_SPUR_MSG_B       0x00000004      /* Spurious message intr.   */
-#define PI_ERR_SPUR_MSG_A       0x00000008
-#define PI_ERR_WRB_TERR_B       0x00000010      /* WRB TERR                 */
-#define PI_ERR_WRB_TERR_A       0x00000020
-#define PI_ERR_WRB_WERR_B       0x00000040      /* WRB WERR                 */
-#define PI_ERR_WRB_WERR_A       0x00000080
-#define PI_ERR_SYSSTATE_B       0x00000100      /* SysState parity error    */
-#define PI_ERR_SYSSTATE_A       0x00000200
-#define PI_ERR_SYSAD_DATA_B     0x00000400      /* SysAD data parity error  */
-#define PI_ERR_SYSAD_DATA_A     0x00000800
-#define PI_ERR_SYSAD_ADDR_B     0x00001000      /* SysAD addr parity error  */
-#define PI_ERR_SYSAD_ADDR_A     0x00002000
-#define PI_ERR_SYSCMD_DATA_B    0x00004000      /* SysCmd data parity error */
-#define PI_ERR_SYSCMD_DATA_A    0x00008000
-#define PI_ERR_SYSCMD_ADDR_B    0x00010000      /* SysCmd addr parity error */
-#define PI_ERR_SYSCMD_ADDR_A    0x00020000
-#define PI_ERR_BAD_SPOOL_B      0x00040000      /* Error spooling to memory */
-#define PI_ERR_BAD_SPOOL_A      0x00080000
-#define PI_ERR_UNCAC_UNCORR_B   0x00100000      /* Uncached uncorrectable   */
-#define PI_ERR_UNCAC_UNCORR_A   0x00200000
-#define PI_ERR_SYSSTATE_TAG_B   0x00400000      /* SysState tag parity error */
-#define PI_ERR_SYSSTATE_TAG_A   0x00800000
-#define PI_ERR_MD_UNCORR        0x01000000      /* Must be cleared in MD    */
-
-#define PI_ERR_CLEAR_ALL_A      0x00aaaaaa
-#define PI_ERR_CLEAR_ALL_B      0x00555555
-
-
-/*
- * The following three macros define all possible error int pends.
- */
-
-#define PI_FATAL_ERR_CPU_A      (PI_ERR_SYSSTATE_TAG_A  | \
-                                 PI_ERR_BAD_SPOOL_A     | \
-                                 PI_ERR_SYSCMD_ADDR_A   | \
-                                 PI_ERR_SYSCMD_DATA_A   | \
-                                 PI_ERR_SYSAD_ADDR_A    | \
-                                 PI_ERR_SYSAD_DATA_A    | \
-                                 PI_ERR_SYSSTATE_A)
-
-#define PI_MISC_ERR_CPU_A       (PI_ERR_UNCAC_UNCORR_A  | \
-                                 PI_ERR_WRB_WERR_A      | \
-                                 PI_ERR_WRB_TERR_A      | \
-                                 PI_ERR_SPUR_MSG_A      | \
-                                 PI_ERR_SPOOL_CMP_A)
-
-#define PI_FATAL_ERR_CPU_B      (PI_ERR_SYSSTATE_TAG_B  | \
-                                 PI_ERR_BAD_SPOOL_B     | \
-                                 PI_ERR_SYSCMD_ADDR_B   | \
-                                 PI_ERR_SYSCMD_DATA_B   | \
-                                 PI_ERR_SYSAD_ADDR_B    | \
-                                 PI_ERR_SYSAD_DATA_B    | \
-                                 PI_ERR_SYSSTATE_B)
-
-#define PI_MISC_ERR_CPU_B       (PI_ERR_UNCAC_UNCORR_B  | \
-                                 PI_ERR_WRB_WERR_B      | \
-                                 PI_ERR_WRB_TERR_B      | \
-                                 PI_ERR_SPUR_MSG_B      | \
-                                 PI_ERR_SPOOL_CMP_B)
-
-#define PI_ERR_GENERIC  (PI_ERR_MD_UNCORR)
-
-/*
- * Error types for PI_ERR_STATUS0_[AB] and error stack:
- * Use the write types if WRBRRB is 1 else use the read types
- */
-
-/* Fields in PI_ERR_STATUS0_[AB] */
-#define PI_ERR_ST0_TYPE_MASK    0x0000000000000007
-#define PI_ERR_ST0_TYPE_SHFT    0
-#define PI_ERR_ST0_REQNUM_MASK  0x0000000000000038
-#define PI_ERR_ST0_REQNUM_SHFT  3
-#define PI_ERR_ST0_SUPPL_MASK   0x000000000001ffc0
-#define PI_ERR_ST0_SUPPL_SHFT   6
-#define PI_ERR_ST0_CMD_MASK     0x0000000001fe0000
-#define PI_ERR_ST0_CMD_SHFT     17
-#define PI_ERR_ST0_ADDR_MASK    0x3ffffffffe000000
-#define PI_ERR_ST0_ADDR_SHFT    25
-#define PI_ERR_ST0_OVERRUN_MASK 0x4000000000000000
-#define PI_ERR_ST0_OVERRUN_SHFT 62
-#define PI_ERR_ST0_VALID_MASK   0x8000000000000000
-#define PI_ERR_ST0_VALID_SHFT   63
-
-/* Fields in PI_ERR_STATUS1_[AB] */
-#define PI_ERR_ST1_SPOOL_MASK   0x00000000001fffff
-#define PI_ERR_ST1_SPOOL_SHFT   0
-#define PI_ERR_ST1_TOUTCNT_MASK 0x000000001fe00000
-#define PI_ERR_ST1_TOUTCNT_SHFT 21
-#define PI_ERR_ST1_INVCNT_MASK  0x0000007fe0000000
-#define PI_ERR_ST1_INVCNT_SHFT  29
-#define PI_ERR_ST1_CRBNUM_MASK  0x0000038000000000
-#define PI_ERR_ST1_CRBNUM_SHFT  39
-#define PI_ERR_ST1_WRBRRB_MASK  0x0000040000000000
-#define PI_ERR_ST1_WRBRRB_SHFT  42
-#define PI_ERR_ST1_CRBSTAT_MASK 0x001ff80000000000
-#define PI_ERR_ST1_CRBSTAT_SHFT 43
-#define PI_ERR_ST1_MSGSRC_MASK  0xffe0000000000000
-#define PI_ERR_ST1_MSGSRC_SHFT  53
-
-/* Fields in the error stack */
-#define PI_ERR_STK_TYPE_MASK    0x0000000000000003
-#define PI_ERR_STK_TYPE_SHFT    0
-#define PI_ERR_STK_SUPPL_MASK   0x0000000000000038
-#define PI_ERR_STK_SUPPL_SHFT   3
-#define PI_ERR_STK_REQNUM_MASK  0x00000000000001c0
-#define PI_ERR_STK_REQNUM_SHFT  6
-#define PI_ERR_STK_CRBNUM_MASK  0x0000000000000e00
-#define PI_ERR_STK_CRBNUM_SHFT  9
-#define PI_ERR_STK_WRBRRB_MASK  0x0000000000001000
-#define PI_ERR_STK_WRBRRB_SHFT  12
-#define PI_ERR_STK_CRBSTAT_MASK 0x00000000007fe000
-#define PI_ERR_STK_CRBSTAT_SHFT 13
-#define PI_ERR_STK_CMD_MASK     0x000000007f800000
-#define PI_ERR_STK_CMD_SHFT     23
-#define PI_ERR_STK_ADDR_MASK    0xffffffff80000000
-#define PI_ERR_STK_ADDR_SHFT    31
-
-/* Error type in the error status or stack on Read CRBs */
-#define PI_ERR_RD_PRERR         1
-#define PI_ERR_RD_DERR          2
-#define PI_ERR_RD_TERR          3
-
-/* Error type in the error status or stack on Write CRBs */
-#define PI_ERR_WR_WERR          0
-#define PI_ERR_WR_PWERR         1
-#define PI_ERR_WR_TERR          3
-
-/* Read or Write CRB in error status or stack */
-#define PI_ERR_RRB      0
-#define PI_ERR_WRB      1
-#define PI_ERR_ANY_CRB  2
-
-/* Address masks in the error status and error stack are not the same */
-#define ERR_STK_ADDR_SHFT       7
-#define ERR_STAT0_ADDR_SHFT     3
-
-#define PI_MIN_STACK_SIZE 4096  /* For figuring out the size to set */
-#define PI_STACK_SIZE_SHFT      12      /* 4k */
-
-#define ERR_STACK_SIZE_BYTES(_sz) \
-       ((_sz) ? (PI_MIN_STACK_SIZE << ((_sz) - 1)) : 0)
-
-#ifndef __ASSEMBLY__
-/*
- * format of error stack and error status registers.
- */
-
-struct err_stack_format {
-        u64     sk_addr    : 33,   /* address */
-                sk_cmd     :  8,   /* message command */
-                sk_crb_sts : 10,   /* status from RRB or WRB */
-                sk_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
-                sk_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
-                sk_t5_req  :  3,   /* RRB T5 request number */
-                sk_suppl   :  3,   /* lowest 3 bit of supplemental */
-                sk_err_type:  3;   /* error type        */
-};
-
-typedef union pi_err_stack {
-        u64     pi_stk_word;
-        struct  err_stack_format pi_stk_fmt;
-} pi_err_stack_t;
-
-struct err_status0_format {
-        u64     s0_valid   :  1,   /* Valid */
-                s0_ovr_run :  1,   /* Overrun, spooled to memory */
-                s0_addr    : 37,   /* address */
-                s0_cmd     :  8,   /* message command */
-                s0_supl    : 11,   /* message supplemental field */
-                s0_t5_req  :  3,   /* RRB T5 request number */
-                s0_err_type:  3;   /* error type */
-};
-
-typedef union pi_err_stat0 {
-        u64     pi_stat0_word;
-        struct err_status0_format pi_stat0_fmt;
-} pi_err_stat0_t;
-
-struct err_status1_format {
-        u64     s1_src     : 11,   /* message source */
-                s1_crb_sts : 10,   /* status from RRB or WRB */
-                s1_rw_rb   :  1,   /* RRB == 0, WRB == 1 */
-                s1_crb_num :  3,   /* WRB (0 to 7) or RRB (0 to 4) */
-                s1_inval_cnt:10,   /* signed invalidate counter RRB */
-                s1_to_cnt  :  8,   /* crb timeout counter */
-                s1_spl_cnt : 21;   /* number spooled to memory */
-};
-
-typedef union pi_err_stat1 {
-        u64     pi_stat1_word;
-        struct err_status1_format pi_stat1_fmt;
-} pi_err_stat1_t;
-
-typedef u64     rtc_time_t;
-
-#endif /* !__ASSEMBLY__ */
-
-
-/* Bits in PI_SYSAD_ERRCHK_EN */
-#define PI_SYSAD_ERRCHK_ECCGEN  0x01    /* Enable ECC generation            */
-#define PI_SYSAD_ERRCHK_QUALGEN 0x02    /* Enable data quality signal gen.  */
-#define PI_SYSAD_ERRCHK_SADP    0x04    /* Enable SysAD parity checking     */
-#define PI_SYSAD_ERRCHK_CMDP    0x08    /* Enable SysCmd parity checking    */
-#define PI_SYSAD_ERRCHK_STATE   0x10    /* Enable SysState parity checking  */
-#define PI_SYSAD_ERRCHK_QUAL    0x20    /* Enable data quality checking     */
-#define PI_SYSAD_CHECK_ALL      0x3f    /* Generate and check all signals.  */
-
-/* Interrupt pending bits on R10000 */
-
-#define HUB_IP_PEND0            0x0400
-#define HUB_IP_PEND1_CC         0x0800
-#define HUB_IP_RT               0x1000
-#define HUB_IP_PROF             0x2000
-#define HUB_IP_ERROR            0x4000
-#define HUB_IP_MASK             0x7c00
-
-/* PI_RT_LOCAL_CTRL mask and shift definitions */
-
-#define PRLC_USE_INT_SHFT       16
-#define PRLC_USE_INT_MASK       (UINT64_CAST 1 << 16)
-#define PRLC_USE_INT            (UINT64_CAST 1 << 16)
-#define PRLC_GCLK_SHFT          15
-#define PRLC_GCLK_MASK          (UINT64_CAST 1 << 15)
-#define PRLC_GCLK               (UINT64_CAST 1 << 15)
-#define PRLC_GCLK_COUNT_SHFT    8
-#define PRLC_GCLK_COUNT_MASK    (UINT64_CAST 0x7f << 8)
-#define PRLC_MAX_COUNT_SHFT     1
-#define PRLC_MAX_COUNT_MASK     (UINT64_CAST 0x7f << 1)
-#define PRLC_GCLK_EN_SHFT       0
-#define PRLC_GCLK_EN_MASK       (UINT64_CAST 1)
-#define PRLC_GCLK_EN            (UINT64_CAST 1)
-
-/* PI_RT_FILTER_CTRL mask and shift definitions */
-
-/*
- * Bits for NACK_CNT_A/B and NACK_CMP
- */
-#define PI_NACK_CNT_EN_SHFT     20
-#define PI_NACK_CNT_EN_MASK     0x100000
-#define PI_NACK_CNT_MASK        0x0fffff
-#define PI_NACK_CNT_MAX         0x0fffff
-
-#endif /* _ASM_SN_SN0_HUBPI_H */
diff --git a/include/asm-mips/sn/sn0/ip27.h b/include/asm-mips/sn/sn0/ip27.h
deleted file mode 100644
index 3c97e0855c8d..000000000000
--- a/include/asm-mips/sn/sn0/ip27.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Derived from IRIX <sys/SN/SN0/IP27.h>.
- *
- * Copyright (C) 1992 - 1997, 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999, 2006 by Ralf Baechle
- */
-#ifndef _ASM_SN_SN0_IP27_H
-#define _ASM_SN_SN0_IP27_H
-
-#include <asm/mipsregs.h>
-
-/*
- * Simple definitions for the masks which remove SW bits from pte.
- */
-
-#define TLBLO_HWBITSHIFT        0               /* Shift value, for masking */
-
-#ifndef __ASSEMBLY__
-
-#define CAUSE_BERRINTR          IE_IRQ5
-
-#define ECCF_CACHE_ERR  0
-#define ECCF_TAGLO      1
-#define ECCF_ECC        2
-#define ECCF_ERROREPC   3
-#define ECCF_PADDR      4
-#define ECCF_SIZE       (5 * sizeof(long))
-
-#endif /* !__ASSEMBLY__ */
-
-#ifdef __ASSEMBLY__
-
-/*
- * KL_GET_CPUNUM (similar to EV_GET_SPNUM for EVEREST platform) reads
- * the processor number of the calling processor.  The proc parameters
- * must be a register.
- */
-#define KL_GET_CPUNUM(proc)                             \
-        dli     proc, LOCAL_HUB(0);                     \
-        ld      proc, PI_CPU_NUM(proc)
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * R10000 status register interrupt bit mask usage for IP27.
- */
-#define SRB_SWTIMO      IE_SW0          /* 0x0100 */
-#define SRB_NET         IE_SW1          /* 0x0200 */
-#define SRB_DEV0        IE_IRQ0         /* 0x0400 */
-#define SRB_DEV1        IE_IRQ1         /* 0x0800 */
-#define SRB_TIMOCLK     IE_IRQ2         /* 0x1000 */
-#define SRB_PROFCLK     IE_IRQ3         /* 0x2000 */
-#define SRB_ERR         IE_IRQ4         /* 0x4000 */
-#define SRB_SCHEDCLK    IE_IRQ5         /* 0x8000 */
-
-#define SR_IBIT_HI      SRB_DEV0
-#define SR_IBIT_PROF    SRB_PROFCLK
-
-#define SRB_SWTIMO_IDX          0
-#define SRB_NET_IDX             1
-#define SRB_DEV0_IDX            2
-#define SRB_DEV1_IDX            3
-#define SRB_TIMOCLK_IDX         4
-#define SRB_PROFCLK_IDX         5
-#define SRB_ERR_IDX             6
-#define SRB_SCHEDCLK_IDX        7
-
-#define NUM_CAUSE_INTRS         8
-
-#define SCACHE_LINESIZE 128
-#define SCACHE_LINEMASK (SCACHE_LINESIZE - 1)
-
-#include <asm/sn/addrs.h>
-
-#define LED_CYCLE_MASK  0x0f
-#define LED_CYCLE_SHFT  4
-
-#define SEND_NMI(_nasid, _slice)        \
-          REMOTE_HUB_S((_nasid),  (PI_NMI_A + ((_slice) * PI_NMI_OFFSET)), 1)
-
-#endif /* _ASM_SN_SN0_IP27_H */
diff --git a/include/asm-mips/sn/sn_private.h b/include/asm-mips/sn/sn_private.h
deleted file mode 100644
index 1a2c3025bf28..000000000000
--- a/include/asm-mips/sn/sn_private.h
+++ /dev/null
@@ -1,19 +0,0 @@
-#ifndef __ASM_SN_SN_PRIVATE_H
-#define __ASM_SN_SN_PRIVATE_H
-
-#include <asm/sn/types.h>
-
-extern nasid_t master_nasid;
-
-extern void cpu_node_probe(void);
-extern cnodeid_t get_compact_nodeid(void);
-extern void hub_rtc_init(cnodeid_t);
-extern void cpu_time_init(void);
-extern void per_cpu_init(void);
-extern void install_cpu_nmi_handler(int slice);
-extern void install_ipi(void);
-extern void setup_replication_mask(void);
-extern void replicate_kernel_text(void);
-extern pfn_t node_getfirstfree(cnodeid_t);
-
-#endif /* __ASM_SN_SN_PRIVATE_H */
diff --git a/include/asm-mips/sn/types.h b/include/asm-mips/sn/types.h
deleted file mode 100644
index 74d0bb260b86..000000000000
--- a/include/asm-mips/sn/types.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 1999 by Ralf Baechle
- */
-#ifndef _ASM_SN_TYPES_H
-#define _ASM_SN_TYPES_H
-
-#include <linux/types.h>
-
-typedef unsigned long   cpuid_t;
-typedef unsigned long   cnodemask_t;
-typedef signed short    nasid_t;        /* node id in numa-as-id space */
-typedef signed short    cnodeid_t;      /* node id in compact-id space */
-typedef signed char     partid_t;       /* partition ID type */
-typedef signed short    moduleid_t;     /* user-visible module number type */
-typedef signed short    cmoduleid_t;    /* kernel compact module id type */
-typedef unsigned char   clusterid_t;    /* Clusterid of the cell */
-typedef unsigned long   pfn_t;
-
-typedef dev_t           vertex_hdl_t;   /* hardware graph vertex handle */
-
-#endif /* _ASM_SN_TYPES_H */
diff --git a/include/asm-mips/sni.h b/include/asm-mips/sni.h
deleted file mode 100644
index 8c1eb02c6d16..000000000000
--- a/include/asm-mips/sni.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * SNI specific definitions
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 1998 by Ralf Baechle
- * Copyright (C) 2006 Thomas Bogendoerfer (tsbogend@alpha.franken.de)
- */
-#ifndef __ASM_SNI_H
-#define __ASM_SNI_H
-
-extern unsigned int sni_brd_type;
-
-#define SNI_BRD_10                 2
-#define SNI_BRD_10NEW              3
-#define SNI_BRD_TOWER_OASIC        4
-#define SNI_BRD_MINITOWER          5
-#define SNI_BRD_PCI_TOWER          6
-#define SNI_BRD_RM200              7
-#define SNI_BRD_PCI_MTOWER         8
-#define SNI_BRD_PCI_DESKTOP        9
-#define SNI_BRD_PCI_TOWER_CPLUS   10
-#define SNI_BRD_PCI_MTOWER_CPLUS  11
-
-/* RM400 cpu types */
-#define SNI_CPU_M8021           0x01
-#define SNI_CPU_M8030           0x04
-#define SNI_CPU_M8031           0x06
-#define SNI_CPU_M8034           0x0f
-#define SNI_CPU_M8037           0x07
-#define SNI_CPU_M8040           0x05
-#define SNI_CPU_M8043           0x09
-#define SNI_CPU_M8050           0x0b
-#define SNI_CPU_M8053           0x0d
-
-#define SNI_PORT_BASE           CKSEG1ADDR(0xb4000000)
-
-#ifndef __MIPSEL__
-/*
- * ASIC PCI registers for big endian configuration.
- */
-#define PCIMT_UCONF             CKSEG1ADDR(0xbfff0004)
-#define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff000c)
-#define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0014)
-#define PCIMT_IOMMU             CKSEG1ADDR(0xbfff001c)
-#define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0024)
-#define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff002c)
-#define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0034)
-#define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff003c)
-#define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0044)
-#define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff004c)
-#define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0054)
-#define  IT_INT2                0x01
-#define  IT_INTD                0x02
-#define  IT_INTC                0x04
-#define  IT_INTB                0x08
-#define  IT_INTA                0x10
-#define  IT_EISA                0x20
-#define  IT_SCSI                0x40
-#define  IT_ETH                 0x80
-#define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff005c)
-#define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0064)
-#define PCIMT_ECCREG            CKSEG1ADDR(0xbfff006c)
-#define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0074)
-#define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff007c)  /* read */
-#define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff007c)  /* write */
-#define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0084)
-#define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff008c)
-#define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0094)
-#define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff009c)
-#define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a4)
-#else
-/*
- * ASIC PCI registers for little endian configuration.
- */
-#define PCIMT_UCONF             CKSEG1ADDR(0xbfff0000)
-#define PCIMT_IOADTIMEOUT2      CKSEG1ADDR(0xbfff0008)
-#define PCIMT_IOMEMCONF         CKSEG1ADDR(0xbfff0010)
-#define PCIMT_IOMMU             CKSEG1ADDR(0xbfff0018)
-#define PCIMT_IOADTIMEOUT1      CKSEG1ADDR(0xbfff0020)
-#define PCIMT_DMAACCESS         CKSEG1ADDR(0xbfff0028)
-#define PCIMT_DMAHIT            CKSEG1ADDR(0xbfff0030)
-#define PCIMT_ERRSTATUS         CKSEG1ADDR(0xbfff0038)
-#define PCIMT_ERRADDR           CKSEG1ADDR(0xbfff0040)
-#define PCIMT_SYNDROME          CKSEG1ADDR(0xbfff0048)
-#define PCIMT_ITPEND            CKSEG1ADDR(0xbfff0050)
-#define  IT_INT2                0x01
-#define  IT_INTD                0x02
-#define  IT_INTC                0x04
-#define  IT_INTB                0x08
-#define  IT_INTA                0x10
-#define  IT_EISA                0x20
-#define  IT_SCSI                0x40
-#define  IT_ETH                 0x80
-#define PCIMT_IRQSEL            CKSEG1ADDR(0xbfff0058)
-#define PCIMT_TESTMEM           CKSEG1ADDR(0xbfff0060)
-#define PCIMT_ECCREG            CKSEG1ADDR(0xbfff0068)
-#define PCIMT_CONFIG_ADDRESS    CKSEG1ADDR(0xbfff0070)
-#define PCIMT_ASIC_ID           CKSEG1ADDR(0xbfff0078)  /* read */
-#define PCIMT_SOFT_RESET        CKSEG1ADDR(0xbfff0078)  /* write */
-#define PCIMT_PIA_OE            CKSEG1ADDR(0xbfff0080)
-#define PCIMT_PIA_DATAOUT       CKSEG1ADDR(0xbfff0088)
-#define PCIMT_PIA_DATAIN        CKSEG1ADDR(0xbfff0090)
-#define PCIMT_CACHECONF         CKSEG1ADDR(0xbfff0098)
-#define PCIMT_INVSPACE          CKSEG1ADDR(0xbfff00a0)
-#endif
-
-#define PCIMT_PCI_CONF          CKSEG1ADDR(0xbfff0100)
-
-/*
- * Data port for the PCI bus in IO space
- */
-#define PCIMT_CONFIG_DATA       0x0cfc
-
-/*
- * Board specific registers
- */
-#define PCIMT_CSMSR             CKSEG1ADDR(0xbfd00000)
-#define PCIMT_CSSWITCH          CKSEG1ADDR(0xbfd10000)
-#define PCIMT_CSITPEND          CKSEG1ADDR(0xbfd20000)
-#define PCIMT_AUTO_PO_EN        CKSEG1ADDR(0xbfd30000)
-#define PCIMT_CLR_TEMP          CKSEG1ADDR(0xbfd40000)
-#define PCIMT_AUTO_PO_DIS       CKSEG1ADDR(0xbfd50000)
-#define PCIMT_EXMSR             CKSEG1ADDR(0xbfd60000)
-#define PCIMT_UNUSED1           CKSEG1ADDR(0xbfd70000)
-#define PCIMT_CSWCSM            CKSEG1ADDR(0xbfd80000)
-#define PCIMT_UNUSED2           CKSEG1ADDR(0xbfd90000)
-#define PCIMT_CSLED             CKSEG1ADDR(0xbfda0000)
-#define PCIMT_CSMAPISA          CKSEG1ADDR(0xbfdb0000)
-#define PCIMT_CSRSTBP           CKSEG1ADDR(0xbfdc0000)
-#define PCIMT_CLRPOFF           CKSEG1ADDR(0xbfdd0000)
-#define PCIMT_CSTIMER           CKSEG1ADDR(0xbfde0000)
-#define PCIMT_PWDN              CKSEG1ADDR(0xbfdf0000)
-
-/*
- * A20R based boards
- */
-#define A20R_PT_CLOCK_BASE      CKSEG1ADDR(0xbc040000)
-#define A20R_PT_TIM0_ACK        CKSEG1ADDR(0xbc050000)
-#define A20R_PT_TIM1_ACK        CKSEG1ADDR(0xbc060000)
-
-#define SNI_A20R_IRQ_BASE       MIPS_CPU_IRQ_BASE
-#define SNI_A20R_IRQ_TIMER      (SNI_A20R_IRQ_BASE+5)
-
-#define SNI_PCIT_INT_REG        CKSEG1ADDR(0xbfff000c)
-
-#define SNI_PCIT_INT_START      24
-#define SNI_PCIT_INT_END        30
-
-#define PCIT_IRQ_ETHERNET       (MIPS_CPU_IRQ_BASE + 5)
-#define PCIT_IRQ_INTA           (SNI_PCIT_INT_START + 0)
-#define PCIT_IRQ_INTB           (SNI_PCIT_INT_START + 1)
-#define PCIT_IRQ_INTC           (SNI_PCIT_INT_START + 2)
-#define PCIT_IRQ_INTD           (SNI_PCIT_INT_START + 3)
-#define PCIT_IRQ_SCSI0          (SNI_PCIT_INT_START + 4)
-#define PCIT_IRQ_SCSI1          (SNI_PCIT_INT_START + 5)
-
-
-/*
- * Interrupt 0-16 are EISA interrupts.  Interrupts from 16 on are assigned
- * to the other interrupts generated by ASIC PCI.
- *
- * INT2 is a wired-or of the push button interrupt, high temperature interrupt
- * ASIC PCI interrupt.
- */
-#define PCIMT_KEYBOARD_IRQ       1
-#define PCIMT_IRQ_INT2          24
-#define PCIMT_IRQ_INTD          25
-#define PCIMT_IRQ_INTC          26
-#define PCIMT_IRQ_INTB          27
-#define PCIMT_IRQ_INTA          28
-#define PCIMT_IRQ_EISA          29
-#define PCIMT_IRQ_SCSI          30
-
-#define PCIMT_IRQ_ETHERNET      (MIPS_CPU_IRQ_BASE+6)
-
-#if 0
-#define PCIMT_IRQ_TEMPERATURE   24
-#define PCIMT_IRQ_EISA_NMI      25
-#define PCIMT_IRQ_POWER_OFF     26
-#define PCIMT_IRQ_BUTTON        27
-#endif
-
-/*
- * Base address for the mapped 16mb EISA bus segment.
- */
-#define PCIMT_EISA_BASE         CKSEG1ADDR(0xb0000000)
-
-/* PCI EISA Interrupt acknowledge  */
-#define PCIMT_INT_ACKNOWLEDGE   CKSEG1ADDR(0xba000000)
-
-/*
- *  SNI ID PROM
- *
- * SNI_IDPROM_MEMSIZE  Memsize in 16MB quantities
- * SNI_IDPROM_BRDTYPE  Board Type
- * SNI_IDPROM_CPUTYPE  CPU Type on RM400
- */
-#ifdef CONFIG_CPU_BIG_ENDIAN
-#define __SNI_END 0
-#endif
-#ifdef CONFIG_CPU_LITTLE_ENDIAN
-#define __SNI_END 3
-#endif
-#define SNI_IDPROM_BASE        CKSEG1ADDR(0x1ff00000)
-#define SNI_IDPROM_MEMSIZE     (SNI_IDPROM_BASE + (0x28 ^ __SNI_END))
-#define SNI_IDPROM_BRDTYPE     (SNI_IDPROM_BASE + (0x29 ^ __SNI_END))
-#define SNI_IDPROM_CPUTYPE     (SNI_IDPROM_BASE + (0x30 ^ __SNI_END))
-
-#define SNI_IDPROM_SIZE 0x1000
-
-/* board specific init functions */
-extern void sni_a20r_init(void);
-extern void sni_pcit_init(void);
-extern void sni_rm200_init(void);
-extern void sni_pcimt_init(void);
-
-/* board specific irq init functions */
-extern void sni_a20r_irq_init(void);
-extern void sni_pcit_irq_init(void);
-extern void sni_pcit_cplus_irq_init(void);
-extern void sni_rm200_irq_init(void);
-extern void sni_pcimt_irq_init(void);
-
-/* timer inits */
-extern void sni_cpu_time_init(void);
-
-/* eisa init for RM200/400 */
-#ifdef CONFIG_EISA
-extern int sni_eisa_root_init(void);
-#else
-static inline int sni_eisa_root_init(void)
-{
-        return 0;
-}
-#endif
-
-/* common irq stuff */
-extern void (*sni_hwint)(void);
-extern struct irqaction sni_isa_irq;
-
-#endif /* __ASM_SNI_H */
diff --git a/include/asm-mips/socket.h b/include/asm-mips/socket.h
deleted file mode 100644
index facc2d7a87ca..000000000000
--- a/include/asm-mips/socket.h
+++ /dev/null
@@ -1,117 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1997, 1999, 2000, 2001 Ralf Baechle
- * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
-
-#include <asm/sockios.h>
-
-/*
- * For setsockopt(2)
- *
- * This defines are ABI conformant as far as Linux supports these ...
- */
-#define SOL_SOCKET      0xffff
-
-#define SO_DEBUG        0x0001  /* Record debugging information.  */
-#define SO_REUSEADDR    0x0004  /* Allow reuse of local addresses.  */
-#define SO_KEEPALIVE    0x0008  /* Keep connections alive and send
-                                   SIGPIPE when they die.  */
-#define SO_DONTROUTE    0x0010  /* Don't do local routing.  */
-#define SO_BROADCAST    0x0020  /* Allow transmission of
-                                   broadcast messages.  */
-#define SO_LINGER       0x0080  /* Block on close of a reliable
-                                   socket to transmit pending data.  */
-#define SO_OOBINLINE 0x0100     /* Receive out-of-band data in-band.  */
-#if 0
-To add: #define SO_REUSEPORT 0x0200     /* Allow local address and port reuse.  */
-#endif
-
-#define SO_TYPE         0x1008  /* Compatible name for SO_STYLE.  */
-#define SO_STYLE        SO_TYPE /* Synonym */
-#define SO_ERROR        0x1007  /* get error status and clear */
-#define SO_SNDBUF       0x1001  /* Send buffer size. */
-#define SO_RCVBUF       0x1002  /* Receive buffer. */
-#define SO_SNDLOWAT     0x1003  /* send low-water mark */
-#define SO_RCVLOWAT     0x1004  /* receive low-water mark */
-#define SO_SNDTIMEO     0x1005  /* send timeout */
-#define SO_RCVTIMEO     0x1006  /* receive timeout */
-#define SO_ACCEPTCONN   0x1009
-
-/* linux-specific, might as well be the same as on i386 */
-#define SO_NO_CHECK     11
-#define SO_PRIORITY     12
-#define SO_BSDCOMPAT    14
-
-#define SO_PASSCRED     17
-#define SO_PEERCRED     18
-
-/* Security levels - as per NRL IPv6 - don't actually do anything */
-#define SO_SECURITY_AUTHENTICATION              22
-#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
-#define SO_SECURITY_ENCRYPTION_NETWORK          24
-
-#define SO_BINDTODEVICE         25
-
-/* Socket filtering */
-#define SO_ATTACH_FILTER        26
-#define SO_DETACH_FILTER        27
-
-#define SO_PEERNAME             28
-#define SO_TIMESTAMP            29
-#define SCM_TIMESTAMP           SO_TIMESTAMP
-
-#define SO_PEERSEC              30
-#define SO_SNDBUFFORCE          31
-#define SO_RCVBUFFORCE          33
-#define SO_PASSSEC              34
-#define SO_TIMESTAMPNS          35
-#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
-
-#define SO_MARK                 36
-
-#ifdef __KERNEL__
-
-/** sock_type - Socket types
- *
- * Please notice that for binary compat reasons MIPS has to
- * override the enum sock_type in include/linux/net.h, so
- * we define ARCH_HAS_SOCKET_TYPES here.
- *
- * @SOCK_DGRAM - datagram (conn.less) socket
- * @SOCK_STREAM - stream (connection) socket
- * @SOCK_RAW - raw socket
- * @SOCK_RDM - reliably-delivered message
- * @SOCK_SEQPACKET - sequential packet socket
- * @SOCK_PACKET - linux specific way of getting packets at the dev level.
- *                For writing rarp and other similar things on the user level.
- */
-enum sock_type {
-        SOCK_DGRAM      = 1,
-        SOCK_STREAM     = 2,
-        SOCK_RAW        = 3,
-        SOCK_RDM        = 4,
-        SOCK_SEQPACKET  = 5,
-        SOCK_DCCP       = 6,
-        SOCK_PACKET     = 10,
-};
-
-#define SOCK_MAX (SOCK_PACKET + 1)
-/* Mask which covers at least up to SOCK_MASK-1.  The
- *  * remaining bits are used as flags. */
-#define SOCK_TYPE_MASK 0xf
-
-/* Flags for socket, socketpair, paccept */
-#define SOCK_CLOEXEC    O_CLOEXEC
-#define SOCK_NONBLOCK   O_NONBLOCK
-
-#define ARCH_HAS_SOCKET_TYPES 1
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_SOCKET_H */
diff --git a/include/asm-mips/sockios.h b/include/asm-mips/sockios.h
deleted file mode 100644
index ed1a5f78d22f..000000000000
--- a/include/asm-mips/sockios.h
+++ /dev/null
@@ -1,26 +0,0 @@
-/*
- * Socket-level I/O control calls.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995 by Ralf Baechle
- */
-#ifndef _ASM_SOCKIOS_H
-#define _ASM_SOCKIOS_H
-
-#include <asm/ioctl.h>
-
-/* Socket-level I/O control calls. */
-#define FIOGETOWN       _IOR('f', 123, int)
-#define FIOSETOWN       _IOW('f', 124, int)
-
-#define SIOCATMARK      _IOR('s', 7, int)
-#define SIOCSPGRP       _IOW('s', 8, pid_t)
-#define SIOCGPGRP       _IOR('s', 9, pid_t)
-
-#define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
-#define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
-
-#endif /* _ASM_SOCKIOS_H */
diff --git a/include/asm-mips/sparsemem.h b/include/asm-mips/sparsemem.h
deleted file mode 100644
index 795ac6c23203..000000000000
--- a/include/asm-mips/sparsemem.h
+++ /dev/null
@@ -1,14 +0,0 @@
-#ifndef _MIPS_SPARSEMEM_H
-#define _MIPS_SPARSEMEM_H
-#ifdef CONFIG_SPARSEMEM
-
-/*
- * SECTION_SIZE_BITS            2^N: how big each section will be
- * MAX_PHYSMEM_BITS             2^N: how much memory we can have in that space
- */
-#define SECTION_SIZE_BITS       28
-#define MAX_PHYSMEM_BITS        35
-
-#endif /* CONFIG_SPARSEMEM */
-#endif /* _MIPS_SPARSEMEM_H */
-
diff --git a/include/asm-mips/spinlock.h b/include/asm-mips/spinlock.h
deleted file mode 100644
index bb897016c491..000000000000
--- a/include/asm-mips/spinlock.h
+++ /dev/null
@@ -1,376 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1999, 2000, 06 Ralf Baechle (ralf@linux-mips.org)
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_SPINLOCK_H
-#define _ASM_SPINLOCK_H
-
-#include <asm/barrier.h>
-#include <asm/war.h>
-
-/*
- * Your basic SMP spinlocks, allowing only a single CPU anywhere
- */
-
-#define __raw_spin_is_locked(x)       ((x)->lock != 0)
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
-#define __raw_spin_unlock_wait(x) \
-        do { cpu_relax(); } while ((x)->lock)
-
-/*
- * Simple spin lock operations.  There are two variants, one clears IRQ's
- * on the local processor, one does not.
- *
- * We make no fairness assumptions.  They have a cost.
- */
-
-static inline void __raw_spin_lock(raw_spinlock_t *lock)
-{
-        unsigned int tmp;
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_spin_lock       \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bnez    %1, 1b                                  \n"
-                "        li     %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                : "=m" (lock->lock), "=&r" (tmp)
-                : "m" (lock->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_spin_lock       \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bnez    %1, 2f                                  \n"
-                "        li     %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 2f                                  \n"
-                "        nop                                            \n"
-                "       .subsection 2                                   \n"
-                "2:     ll      %1, %2                                  \n"
-                "       bnez    %1, 2b                                  \n"
-                "        li     %1, 1                                   \n"
-                "       b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    reorder                                 \n"
-                : "=m" (lock->lock), "=&r" (tmp)
-                : "m" (lock->lock)
-                : "memory");
-        }
-
-        smp_llsc_mb();
-}
-
-static inline void __raw_spin_unlock(raw_spinlock_t *lock)
-{
-        smp_mb();
-
-        __asm__ __volatile__(
-        "       .set    noreorder       # __raw_spin_unlock     \n"
-        "       sw      $0, %0                                  \n"
-        "       .set\treorder                                   \n"
-        : "=m" (lock->lock)
-        : "m" (lock->lock)
-        : "memory");
-}
-
-static inline unsigned int __raw_spin_trylock(raw_spinlock_t *lock)
-{
-        unsigned int temp, res;
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_spin_trylock    \n"
-                "1:     ll      %0, %3                                  \n"
-                "       ori     %2, %0, 1                               \n"
-                "       sc      %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "        nop                                            \n"
-                "       andi    %2, %0, 1                               \n"
-                "       .set    reorder"
-                : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
-                : "m" (lock->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_spin_trylock    \n"
-                "1:     ll      %0, %3                                  \n"
-                "       ori     %2, %0, 1                               \n"
-                "       sc      %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "        andi   %2, %0, 1                               \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    reorder"
-                : "=&r" (temp), "=m" (lock->lock), "=&r" (res)
-                : "m" (lock->lock)
-                : "memory");
-        }
-
-        smp_llsc_mb();
-
-        return res == 0;
-}
-
-/*
- * Read-write spinlocks, allowing multiple readers but only one writer.
- *
- * NOTE! it is quite common to have readers in interrupts but no interrupt
- * writers. For those circumstances we can "mix" irq-safe locks - any writer
- * needs to get a irq-safe write-lock, but readers can get non-irqsafe
- * read-locks.
- */
-
-/*
- * read_can_lock - would read_trylock() succeed?
- * @lock: the rwlock in question.
- */
-#define __raw_read_can_lock(rw) ((rw)->lock >= 0)
-
-/*
- * write_can_lock - would write_trylock() succeed?
- * @lock: the rwlock in question.
- */
-#define __raw_write_can_lock(rw)        (!(rw)->lock)
-
-static inline void __raw_read_lock(raw_rwlock_t *rw)
-{
-        unsigned int tmp;
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_lock       \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bltz    %1, 1b                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                : "=m" (rw->lock), "=&r" (tmp)
-                : "m" (rw->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_lock       \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bltz    %1, 2f                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .subsection 2                                   \n"
-                "2:     ll      %1, %2                                  \n"
-                "       bltz    %1, 2b                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    reorder                                 \n"
-                : "=m" (rw->lock), "=&r" (tmp)
-                : "m" (rw->lock)
-                : "memory");
-        }
-
-        smp_llsc_mb();
-}
-
-/* Note the use of sub, not subu which will make the kernel die with an
-   overflow exception if we ever try to unlock an rwlock that is already
-   unlocked or is being held by a writer.  */
-static inline void __raw_read_unlock(raw_rwlock_t *rw)
-{
-        unsigned int tmp;
-
-        smp_llsc_mb();
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "1:     ll      %1, %2          # __raw_read_unlock     \n"
-                "       sub     %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                : "=m" (rw->lock), "=&r" (tmp)
-                : "m" (rw->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_unlock     \n"
-                "1:     ll      %1, %2                                  \n"
-                "       sub     %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 2f                                  \n"
-                "        nop                                            \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    reorder                                 \n"
-                : "=m" (rw->lock), "=&r" (tmp)
-                : "m" (rw->lock)
-                : "memory");
-        }
-}
-
-static inline void __raw_write_lock(raw_rwlock_t *rw)
-{
-        unsigned int tmp;
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_lock      \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bnez    %1, 1b                                  \n"
-                "        lui    %1, 0x8000                              \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                : "=m" (rw->lock), "=&r" (tmp)
-                : "m" (rw->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_lock      \n"
-                "1:     ll      %1, %2                                  \n"
-                "       bnez    %1, 2f                                  \n"
-                "        lui    %1, 0x8000                              \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 2f                                  \n"
-                "        nop                                            \n"
-                "       .subsection 2                                   \n"
-                "2:     ll      %1, %2                                  \n"
-                "       bnez    %1, 2b                                  \n"
-                "        lui    %1, 0x8000                              \n"
-                "       b       1b                                      \n"
-                "        nop                                            \n"
-                "       .previous                                       \n"
-                "       .set    reorder                                 \n"
-                : "=m" (rw->lock), "=&r" (tmp)
-                : "m" (rw->lock)
-                : "memory");
-        }
-
-        smp_llsc_mb();
-}
-
-static inline void __raw_write_unlock(raw_rwlock_t *rw)
-{
-        smp_mb();
-
-        __asm__ __volatile__(
-        "                               # __raw_write_unlock    \n"
-        "       sw      $0, %0                                  \n"
-        : "=m" (rw->lock)
-        : "m" (rw->lock)
-        : "memory");
-}
-
-static inline int __raw_read_trylock(raw_rwlock_t *rw)
-{
-        unsigned int tmp;
-        int ret;
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_trylock    \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bltz    %1, 2f                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       .set    reorder                                 \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                __WEAK_LLSC_MB
-                "       li      %2, 1                                   \n"
-                "2:                                                     \n"
-                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : "m" (rw->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_read_trylock    \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bltz    %1, 2f                                  \n"
-                "        addu   %1, 1                                   \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 1b                                  \n"
-                "        nop                                            \n"
-                "       .set    reorder                                 \n"
-                __WEAK_LLSC_MB
-                "       li      %2, 1                                   \n"
-                "2:                                                     \n"
-                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : "m" (rw->lock)
-                : "memory");
-        }
-
-        return ret;
-}
-
-static inline int __raw_write_trylock(raw_rwlock_t *rw)
-{
-        unsigned int tmp;
-        int ret;
-
-        if (R10000_LLSC_WAR) {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_trylock   \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bnez    %1, 2f                                  \n"
-                "        lui    %1, 0x8000                              \n"
-                "       sc      %1, %0                                  \n"
-                "       beqzl   %1, 1b                                  \n"
-                "        nop                                            \n"
-                __WEAK_LLSC_MB
-                "       li      %2, 1                                   \n"
-                "       .set    reorder                                 \n"
-                "2:                                                     \n"
-                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : "m" (rw->lock)
-                : "memory");
-        } else {
-                __asm__ __volatile__(
-                "       .set    noreorder       # __raw_write_trylock   \n"
-                "       li      %2, 0                                   \n"
-                "1:     ll      %1, %3                                  \n"
-                "       bnez    %1, 2f                                  \n"
-                "       lui     %1, 0x8000                              \n"
-                "       sc      %1, %0                                  \n"
-                "       beqz    %1, 3f                                  \n"
-                "        li     %2, 1                                   \n"
-                "2:                                                     \n"
-                __WEAK_LLSC_MB
-                "       .subsection 2                                   \n"
-                "3:     b       1b                                      \n"
-                "        li     %2, 0                                   \n"
-                "       .previous                                       \n"
-                "       .set    reorder                                 \n"
-                : "=m" (rw->lock), "=&r" (tmp), "=&r" (ret)
-                : "m" (rw->lock)
-                : "memory");
-        }
-
-        return ret;
-}
-
-
-#define _raw_spin_relax(lock)   cpu_relax()
-#define _raw_read_relax(lock)   cpu_relax()
-#define _raw_write_relax(lock)  cpu_relax()
-
-#endif /* _ASM_SPINLOCK_H */
diff --git a/include/asm-mips/spinlock_types.h b/include/asm-mips/spinlock_types.h
deleted file mode 100644
index ce26c5048b15..000000000000
--- a/include/asm-mips/spinlock_types.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef _ASM_SPINLOCK_TYPES_H
-#define _ASM_SPINLOCK_TYPES_H
-
-#ifndef __LINUX_SPINLOCK_TYPES_H
-# error "please don't include this file directly"
-#endif
-
-typedef struct {
-        volatile unsigned int lock;
-} raw_spinlock_t;
-
-#define __RAW_SPIN_LOCK_UNLOCKED        { 0 }
-
-typedef struct {
-        volatile unsigned int lock;
-} raw_rwlock_t;
-
-#define __RAW_RW_LOCK_UNLOCKED          { 0 }
-
-#endif
diff --git a/include/asm-mips/stackframe.h b/include/asm-mips/stackframe.h
deleted file mode 100644
index 051e1af0bb95..000000000000
--- a/include/asm-mips/stackframe.h
+++ /dev/null
@@ -1,524 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 99, 2001 Ralf Baechle
- * Copyright (C) 1994, 1995, 1996 Paul M. Antoine.
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2007  Maciej W. Rozycki
- */
-#ifndef _ASM_STACKFRAME_H
-#define _ASM_STACKFRAME_H
-
-#include <linux/threads.h>
-
-#include <asm/asm.h>
-#include <asm/asmmacro.h>
-#include <asm/mipsregs.h>
-#include <asm/asm-offsets.h>
-
-/*
- * For SMTC kernel, global IE should be left set, and interrupts
- * controlled exclusively via IXMT.
- */
-#ifdef CONFIG_MIPS_MT_SMTC
-#define STATMASK 0x1e
-#elif defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-#define STATMASK 0x3f
-#else
-#define STATMASK 0x1f
-#endif
-
-#ifdef CONFIG_MIPS_MT_SMTC
-#include <asm/mipsmtregs.h>
-#endif /* CONFIG_MIPS_MT_SMTC */
-
-                .macro  SAVE_AT
-                .set    push
-                .set    noat
-                LONG_S  $1, PT_R1(sp)
-                .set    pop
-                .endm
-
-                .macro  SAVE_TEMP
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-                mflhxu  v1
-                LONG_S  v1, PT_LO(sp)
-                mflhxu  v1
-                LONG_S  v1, PT_HI(sp)
-                mflhxu  v1
-                LONG_S  v1, PT_ACX(sp)
-#else
-                mfhi    v1
-                LONG_S  v1, PT_HI(sp)
-                mflo    v1
-                LONG_S  v1, PT_LO(sp)
-#endif
-#ifdef CONFIG_32BIT
-                LONG_S  $8, PT_R8(sp)
-                LONG_S  $9, PT_R9(sp)
-#endif
-                LONG_S  $10, PT_R10(sp)
-                LONG_S  $11, PT_R11(sp)
-                LONG_S  $12, PT_R12(sp)
-                LONG_S  $13, PT_R13(sp)
-                LONG_S  $14, PT_R14(sp)
-                LONG_S  $15, PT_R15(sp)
-                LONG_S  $24, PT_R24(sp)
-                .endm
-
-                .macro  SAVE_STATIC
-                LONG_S  $16, PT_R16(sp)
-                LONG_S  $17, PT_R17(sp)
-                LONG_S  $18, PT_R18(sp)
-                LONG_S  $19, PT_R19(sp)
-                LONG_S  $20, PT_R20(sp)
-                LONG_S  $21, PT_R21(sp)
-                LONG_S  $22, PT_R22(sp)
-                LONG_S  $23, PT_R23(sp)
-                LONG_S  $30, PT_R30(sp)
-                .endm
-
-#ifdef CONFIG_SMP
-#ifdef CONFIG_MIPS_MT_SMTC
-#define PTEBASE_SHIFT   19      /* TCBIND */
-#else
-#define PTEBASE_SHIFT   23      /* CONTEXT */
-#endif
-                .macro  get_saved_sp    /* SMP variation */
-#ifdef CONFIG_MIPS_MT_SMTC
-                mfc0    k0, CP0_TCBIND
-#else
-                MFC0    k0, CP0_CONTEXT
-#endif
-#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
-                lui     k1, %hi(kernelsp)
-#else
-                lui     k1, %highest(kernelsp)
-                daddiu  k1, %higher(kernelsp)
-                dsll    k1, 16
-                daddiu  k1, %hi(kernelsp)
-                dsll    k1, 16
-#endif
-                LONG_SRL        k0, PTEBASE_SHIFT
-                LONG_ADDU       k1, k0
-                LONG_L  k1, %lo(kernelsp)(k1)
-                .endm
-
-                .macro  set_saved_sp stackp temp temp2
-#ifdef CONFIG_MIPS_MT_SMTC
-                mfc0    \temp, CP0_TCBIND
-#else
-                MFC0    \temp, CP0_CONTEXT
-#endif
-                LONG_SRL        \temp, PTEBASE_SHIFT
-                LONG_S  \stackp, kernelsp(\temp)
-                .endm
-#else
-                .macro  get_saved_sp    /* Uniprocessor variation */
-#if defined(CONFIG_32BIT) || defined(KBUILD_64BIT_SYM32)
-                lui     k1, %hi(kernelsp)
-#else
-                lui     k1, %highest(kernelsp)
-                daddiu  k1, %higher(kernelsp)
-                dsll    k1, k1, 16
-                daddiu  k1, %hi(kernelsp)
-                dsll    k1, k1, 16
-#endif
-                LONG_L  k1, %lo(kernelsp)(k1)
-                .endm
-
-                .macro  set_saved_sp stackp temp temp2
-                LONG_S  \stackp, kernelsp
-                .endm
-#endif
-
-                .macro  SAVE_SOME
-                .set    push
-                .set    noat
-                .set    reorder
-                mfc0    k0, CP0_STATUS
-                sll     k0, 3           /* extract cu0 bit */
-                .set    noreorder
-                bltz    k0, 8f
-                 move   k1, sp
-                .set    reorder
-                /* Called from user mode, new stack. */
-                get_saved_sp
-#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
-8:              move    k0, sp
-                PTR_SUBU sp, k1, PT_SIZE
-#else
-                .set    at=k0
-8:              PTR_SUBU k1, PT_SIZE
-                .set    noat
-                move    k0, sp
-                move    sp, k1
-#endif
-                LONG_S  k0, PT_R29(sp)
-                LONG_S  $3, PT_R3(sp)
-                /*
-                 * You might think that you don't need to save $0,
-                 * but the FPU emulator and gdb remote debug stub
-                 * need it to operate correctly
-                 */
-                LONG_S  $0, PT_R0(sp)
-                mfc0    v1, CP0_STATUS
-                LONG_S  $2, PT_R2(sp)
-                LONG_S  v1, PT_STATUS(sp)
-#ifdef CONFIG_MIPS_MT_SMTC
-                /*
-                 * Ideally, these instructions would be shuffled in
-                 * to cover the pipeline delay.
-                 */
-                .set    mips32
-                mfc0    v1, CP0_TCSTATUS
-                .set    mips0
-                LONG_S  v1, PT_TCSTATUS(sp)
-#endif /* CONFIG_MIPS_MT_SMTC */
-                LONG_S  $4, PT_R4(sp)
-                mfc0    v1, CP0_CAUSE
-                LONG_S  $5, PT_R5(sp)
-                LONG_S  v1, PT_CAUSE(sp)
-                LONG_S  $6, PT_R6(sp)
-                MFC0    v1, CP0_EPC
-                LONG_S  $7, PT_R7(sp)
-#ifdef CONFIG_64BIT
-                LONG_S  $8, PT_R8(sp)
-                LONG_S  $9, PT_R9(sp)
-#endif
-                LONG_S  v1, PT_EPC(sp)
-                LONG_S  $25, PT_R25(sp)
-                LONG_S  $28, PT_R28(sp)
-                LONG_S  $31, PT_R31(sp)
-                ori     $28, sp, _THREAD_MASK
-                xori    $28, _THREAD_MASK
-                .set    pop
-                .endm
-
-                .macro  SAVE_ALL
-                SAVE_SOME
-                SAVE_AT
-                SAVE_TEMP
-                SAVE_STATIC
-                .endm
-
-                .macro  RESTORE_AT
-                .set    push
-                .set    noat
-                LONG_L  $1,  PT_R1(sp)
-                .set    pop
-                .endm
-
-                .macro  RESTORE_TEMP
-#ifdef CONFIG_CPU_HAS_SMARTMIPS
-                LONG_L  $24, PT_ACX(sp)
-                mtlhx   $24
-                LONG_L  $24, PT_HI(sp)
-                mtlhx   $24
-                LONG_L  $24, PT_LO(sp)
-                mtlhx   $24
-#else
-                LONG_L  $24, PT_LO(sp)
-                mtlo    $24
-                LONG_L  $24, PT_HI(sp)
-                mthi    $24
-#endif
-#ifdef CONFIG_32BIT
-                LONG_L  $8, PT_R8(sp)
-                LONG_L  $9, PT_R9(sp)
-#endif
-                LONG_L  $10, PT_R10(sp)
-                LONG_L  $11, PT_R11(sp)
-                LONG_L  $12, PT_R12(sp)
-                LONG_L  $13, PT_R13(sp)
-                LONG_L  $14, PT_R14(sp)
-                LONG_L  $15, PT_R15(sp)
-                LONG_L  $24, PT_R24(sp)
-                .endm
-
-                .macro  RESTORE_STATIC
-                LONG_L  $16, PT_R16(sp)
-                LONG_L  $17, PT_R17(sp)
-                LONG_L  $18, PT_R18(sp)
-                LONG_L  $19, PT_R19(sp)
-                LONG_L  $20, PT_R20(sp)
-                LONG_L  $21, PT_R21(sp)
-                LONG_L  $22, PT_R22(sp)
-                LONG_L  $23, PT_R23(sp)
-                LONG_L  $30, PT_R30(sp)
-                .endm
-
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-
-                .macro  RESTORE_SOME
-                .set    push
-                .set    reorder
-                .set    noat
-                mfc0    a0, CP0_STATUS
-                li      v1, 0xff00
-                ori     a0, STATMASK
-                xori    a0, STATMASK
-                mtc0    a0, CP0_STATUS
-                and     a0, v1
-                LONG_L  v0, PT_STATUS(sp)
-                nor     v1, $0, v1
-                and     v0, v1
-                or      v0, a0
-                mtc0    v0, CP0_STATUS
-                LONG_L  $31, PT_R31(sp)
-                LONG_L  $28, PT_R28(sp)
-                LONG_L  $25, PT_R25(sp)
-                LONG_L  $7,  PT_R7(sp)
-                LONG_L  $6,  PT_R6(sp)
-                LONG_L  $5,  PT_R5(sp)
-                LONG_L  $4,  PT_R4(sp)
-                LONG_L  $3,  PT_R3(sp)
-                LONG_L  $2,  PT_R2(sp)
-                .set    pop
-                .endm
-
-                .macro  RESTORE_SP_AND_RET
-                .set    push
-                .set    noreorder
-                LONG_L  k0, PT_EPC(sp)
-                LONG_L  sp, PT_R29(sp)
-                jr      k0
-                 rfe
-                .set    pop
-                .endm
-
-#else
-                .macro  RESTORE_SOME
-                .set    push
-                .set    reorder
-                .set    noat
-#ifdef CONFIG_MIPS_MT_SMTC
-                .set    mips32r2
-                /*
-                 * This may not really be necessary if ints are already
-                 * inhibited here.
-                 */
-                mfc0    v0, CP0_TCSTATUS
-                ori     v0, TCSTATUS_IXMT
-                mtc0    v0, CP0_TCSTATUS
-                _ehb
-                DMT     5                               # dmt a1
-                jal     mips_ihb
-#endif /* CONFIG_MIPS_MT_SMTC */
-                mfc0    a0, CP0_STATUS
-                ori     a0, STATMASK
-                xori    a0, STATMASK
-                mtc0    a0, CP0_STATUS
-                li      v1, 0xff00
-                and     a0, v1
-                LONG_L  v0, PT_STATUS(sp)
-                nor     v1, $0, v1
-                and     v0, v1
-                or      v0, a0
-                mtc0    v0, CP0_STATUS
-#ifdef CONFIG_MIPS_MT_SMTC
-/*
- * Only after EXL/ERL have been restored to status can we
- * restore TCStatus.IXMT.
- */
-                LONG_L  v1, PT_TCSTATUS(sp)
-                _ehb
-                mfc0    v0, CP0_TCSTATUS
-                andi    v1, TCSTATUS_IXMT
-                /* We know that TCStatua.IXMT should be set from above */
-                xori    v0, v0, TCSTATUS_IXMT
-                or      v0, v0, v1
-                mtc0    v0, CP0_TCSTATUS
-                _ehb
-                andi    a1, a1, VPECONTROL_TE
-                beqz    a1, 1f
-                emt
-1:
-                .set    mips0
-#endif /* CONFIG_MIPS_MT_SMTC */
-                LONG_L  v1, PT_EPC(sp)
-                MTC0    v1, CP0_EPC
-                LONG_L  $31, PT_R31(sp)
-                LONG_L  $28, PT_R28(sp)
-                LONG_L  $25, PT_R25(sp)
-#ifdef CONFIG_64BIT
-                LONG_L  $8, PT_R8(sp)
-                LONG_L  $9, PT_R9(sp)
-#endif
-                LONG_L  $7,  PT_R7(sp)
-                LONG_L  $6,  PT_R6(sp)
-                LONG_L  $5,  PT_R5(sp)
-                LONG_L  $4,  PT_R4(sp)
-                LONG_L  $3,  PT_R3(sp)
-                LONG_L  $2,  PT_R2(sp)
-                .set    pop
-                .endm
-
-                .macro  RESTORE_SP_AND_RET
-                LONG_L  sp, PT_R29(sp)
-                .set    mips3
-                eret
-                .set    mips0
-                .endm
-
-#endif
-
-                .macro  RESTORE_SP
-                LONG_L  sp, PT_R29(sp)
-                .endm
-
-                .macro  RESTORE_ALL
-                RESTORE_TEMP
-                RESTORE_STATIC
-                RESTORE_AT
-                RESTORE_SOME
-                RESTORE_SP
-                .endm
-
-                .macro  RESTORE_ALL_AND_RET
-                RESTORE_TEMP
-                RESTORE_STATIC
-                RESTORE_AT
-                RESTORE_SOME
-                RESTORE_SP_AND_RET
-                .endm
-
-/*
- * Move to kernel mode and disable interrupts.
- * Set cp0 enable bit as sign that we're running on the kernel stack
- */
-                .macro  CLI
-#if !defined(CONFIG_MIPS_MT_SMTC)
-                mfc0    t0, CP0_STATUS
-                li      t1, ST0_CU0 | STATMASK
-                or      t0, t1
-                xori    t0, STATMASK
-                mtc0    t0, CP0_STATUS
-#else /* CONFIG_MIPS_MT_SMTC */
-                /*
-                 * For SMTC, we need to set privilege
-                 * and disable interrupts only for the
-                 * current TC, using the TCStatus register.
-                 */
-                mfc0    t0, CP0_TCSTATUS
-                /* Fortunately CU 0 is in the same place in both registers */
-                /* Set TCU0, TMX, TKSU (for later inversion) and IXMT */
-                li      t1, ST0_CU0 | 0x08001c00
-                or      t0, t1
-                /* Clear TKSU, leave IXMT */
-                xori    t0, 0x00001800
-                mtc0    t0, CP0_TCSTATUS
-                _ehb
-                /* We need to leave the global IE bit set, but clear EXL...*/
-                mfc0    t0, CP0_STATUS
-                ori     t0, ST0_EXL | ST0_ERL
-                xori    t0, ST0_EXL | ST0_ERL
-                mtc0    t0, CP0_STATUS
-#endif /* CONFIG_MIPS_MT_SMTC */
-                irq_disable_hazard
-                .endm
-
-/*
- * Move to kernel mode and enable interrupts.
- * Set cp0 enable bit as sign that we're running on the kernel stack
- */
-                .macro  STI
-#if !defined(CONFIG_MIPS_MT_SMTC)
-                mfc0    t0, CP0_STATUS
-                li      t1, ST0_CU0 | STATMASK
-                or      t0, t1
-                xori    t0, STATMASK & ~1
-                mtc0    t0, CP0_STATUS
-#else /* CONFIG_MIPS_MT_SMTC */
-                /*
-                 * For SMTC, we need to set privilege
-                 * and enable interrupts only for the
-                 * current TC, using the TCStatus register.
-                 */
-                _ehb
-                mfc0    t0, CP0_TCSTATUS
-                /* Fortunately CU 0 is in the same place in both registers */
-                /* Set TCU0, TKSU (for later inversion) and IXMT */
-                li      t1, ST0_CU0 | 0x08001c00
-                or      t0, t1
-                /* Clear TKSU *and* IXMT */
-                xori    t0, 0x00001c00
-                mtc0    t0, CP0_TCSTATUS
-                _ehb
-                /* We need to leave the global IE bit set, but clear EXL...*/
-                mfc0    t0, CP0_STATUS
-                ori     t0, ST0_EXL
-                xori    t0, ST0_EXL
-                mtc0    t0, CP0_STATUS
-                /* irq_enable_hazard below should expand to EHB for 24K/34K cpus */
-#endif /* CONFIG_MIPS_MT_SMTC */
-                irq_enable_hazard
-                .endm
-
-/*
- * Just move to kernel mode and leave interrupts as they are.  Note
- * for the R3000 this means copying the previous enable from IEp.
- * Set cp0 enable bit as sign that we're running on the kernel stack
- */
-                .macro  KMODE
-#ifdef CONFIG_MIPS_MT_SMTC
-                /*
-                 * This gets baroque in SMTC.  We want to
-                 * protect the non-atomic clearing of EXL
-                 * with DMT/EMT, but we don't want to take
-                 * an interrupt while DMT is still in effect.
-                 */
-
-                /* KMODE gets invoked from both reorder and noreorder code */
-                .set    push
-                .set    mips32r2
-                .set    noreorder
-                mfc0    v0, CP0_TCSTATUS
-                andi    v1, v0, TCSTATUS_IXMT
-                ori     v0, TCSTATUS_IXMT
-                mtc0    v0, CP0_TCSTATUS
-                _ehb
-                DMT     2                               # dmt   v0
-                /*
-                 * We don't know a priori if ra is "live"
-                 */
-                move    t0, ra
-                jal     mips_ihb
-                nop     /* delay slot */
-                move    ra, t0
-#endif /* CONFIG_MIPS_MT_SMTC */
-                mfc0    t0, CP0_STATUS
-                li      t1, ST0_CU0 | (STATMASK & ~1)
-#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
-                andi    t2, t0, ST0_IEP
-                srl     t2, 2
-                or      t0, t2
-#endif
-                or      t0, t1
-                xori    t0, STATMASK & ~1
-                mtc0    t0, CP0_STATUS
-#ifdef CONFIG_MIPS_MT_SMTC
-                _ehb
-                andi    v0, v0, VPECONTROL_TE
-                beqz    v0, 2f
-                nop     /* delay slot */
-                emt
-2:
-                mfc0    v0, CP0_TCSTATUS
-                /* Clear IXMT, then OR in previous value */
-                ori     v0, TCSTATUS_IXMT
-                xori    v0, TCSTATUS_IXMT
-                or      v0, v1, v0
-                mtc0    v0, CP0_TCSTATUS
-                /*
-                 * irq_disable_hazard below should expand to EHB
-                 * on 24K/34K CPUS
-                 */
-                .set pop
-#endif /* CONFIG_MIPS_MT_SMTC */
-                irq_disable_hazard
-                .endm
-
-#endif /* _ASM_STACKFRAME_H */
diff --git a/include/asm-mips/stacktrace.h b/include/asm-mips/stacktrace.h
deleted file mode 100644
index 0bf82818aa53..000000000000
--- a/include/asm-mips/stacktrace.h
+++ /dev/null
@@ -1,48 +0,0 @@
-#ifndef _ASM_STACKTRACE_H
-#define _ASM_STACKTRACE_H
-
-#include <asm/ptrace.h>
-
-#ifdef CONFIG_KALLSYMS
-extern int raw_show_trace;
-extern unsigned long unwind_stack(struct task_struct *task, unsigned long *sp,
-                                  unsigned long pc, unsigned long *ra);
-#else
-#define raw_show_trace 1
-static inline unsigned long unwind_stack(struct task_struct *task,
-        unsigned long *sp, unsigned long pc, unsigned long *ra)
-{
-        return 0;
-}
-#endif
-
-static __always_inline void prepare_frametrace(struct pt_regs *regs)
-{
-#ifndef CONFIG_KALLSYMS
-        /*
-         * Remove any garbage that may be in regs (specially func
-         * addresses) to avoid show_raw_backtrace() to report them
-         */
-        memset(regs, 0, sizeof(*regs));
-#endif
-        __asm__ __volatile__(
-                ".set push\n\t"
-                ".set noat\n\t"
-#ifdef CONFIG_64BIT
-                "1: dla $1, 1b\n\t"
-                "sd $1, %0\n\t"
-                "sd $29, %1\n\t"
-                "sd $31, %2\n\t"
-#else
-                "1: la $1, 1b\n\t"
-                "sw $1, %0\n\t"
-                "sw $29, %1\n\t"
-                "sw $31, %2\n\t"
-#endif
-                ".set pop\n\t"
-                : "=m" (regs->cp0_epc),
-                "=m" (regs->regs[29]), "=m" (regs->regs[31])
-                : : "memory");
-}
-
-#endif /* _ASM_STACKTRACE_H */
diff --git a/include/asm-mips/stat.h b/include/asm-mips/stat.h
deleted file mode 100644
index 6e00f751ab6d..000000000000
--- a/include/asm-mips/stat.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999, 2000 Ralf Baechle
- * Copyright (C) 2000 Silicon Graphics, Inc.
- */
-#ifndef _ASM_STAT_H
-#define _ASM_STAT_H
-
-#include <linux/types.h>
-
-#include <asm/sgidefs.h>
-
-#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
-
-struct stat {
-        unsigned        st_dev;
-        long            st_pad1[3];             /* Reserved for network id */
-        ino_t           st_ino;
-        mode_t          st_mode;
-        nlink_t         st_nlink;
-        uid_t           st_uid;
-        gid_t           st_gid;
-        unsigned        st_rdev;
-        long            st_pad2[2];
-        off_t           st_size;
-        long            st_pad3;
-        /*
-         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
-         * but we don't have it under Linux.
-         */
-        time_t          st_atime;
-        long            st_atime_nsec;
-        time_t          st_mtime;
-        long            st_mtime_nsec;
-        time_t          st_ctime;
-        long            st_ctime_nsec;
-        long            st_blksize;
-        long            st_blocks;
-        long            st_pad4[14];
-};
-
-/*
- * This matches struct stat64 in glibc2.1, hence the absolutely insane
- * amounts of padding around dev_t's.  The memory layout is the same as of
- * struct stat of the 64-bit kernel.
- */
-
-struct stat64 {
-        unsigned long   st_dev;
-        unsigned long   st_pad0[3];     /* Reserved for st_dev expansion  */
-
-        unsigned long long      st_ino;
-
-        mode_t          st_mode;
-        nlink_t         st_nlink;
-
-        uid_t           st_uid;
-        gid_t           st_gid;
-
-        unsigned long   st_rdev;
-        unsigned long   st_pad1[3];     /* Reserved for st_rdev expansion  */
-
-        long long       st_size;
-
-        /*
-         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
-         * but we don't have it under Linux.
-         */
-        time_t          st_atime;
-        unsigned long   st_atime_nsec;  /* Reserved for st_atime expansion  */
-
-        time_t          st_mtime;
-        unsigned long   st_mtime_nsec;  /* Reserved for st_mtime expansion  */
-
-        time_t          st_ctime;
-        unsigned long   st_ctime_nsec;  /* Reserved for st_ctime expansion  */
-
-        unsigned long   st_blksize;
-        unsigned long   st_pad2;
-
-        long long       st_blocks;
-};
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64
-
-/* The memory layout is the same as of struct stat64 of the 32-bit kernel.  */
-struct stat {
-        unsigned int            st_dev;
-        unsigned int            st_pad0[3]; /* Reserved for st_dev expansion */
-
-        unsigned long           st_ino;
-
-        mode_t                  st_mode;
-        nlink_t                 st_nlink;
-
-        uid_t                   st_uid;
-        gid_t                   st_gid;
-
-        unsigned int            st_rdev;
-        unsigned int            st_pad1[3]; /* Reserved for st_rdev expansion */
-
-        off_t                   st_size;
-
-        /*
-         * Actually this should be timestruc_t st_atime, st_mtime and st_ctime
-         * but we don't have it under Linux.
-         */
-        unsigned int            st_atime;
-        unsigned int            st_atime_nsec;
-
-        unsigned int            st_mtime;
-        unsigned int            st_mtime_nsec;
-
-        unsigned int            st_ctime;
-        unsigned int            st_ctime_nsec;
-
-        unsigned int            st_blksize;
-        unsigned int            st_pad2;
-
-        unsigned long           st_blocks;
-};
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
-
-#define STAT_HAVE_NSEC 1
-
-#endif /* _ASM_STAT_H */
diff --git a/include/asm-mips/statfs.h b/include/asm-mips/statfs.h
deleted file mode 100644
index c3ddf973c1c0..000000000000
--- a/include/asm-mips/statfs.h
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1999 by Ralf Baechle
- */
-#ifndef _ASM_STATFS_H
-#define _ASM_STATFS_H
-
-#include <linux/posix_types.h>
-#include <asm/sgidefs.h>
-
-#ifndef __KERNEL_STRICT_NAMES
-
-#include <linux/types.h>
-
-typedef __kernel_fsid_t        fsid_t;
-
-#endif
-
-struct statfs {
-        long            f_type;
-#define f_fstyp f_type
-        long            f_bsize;
-        long            f_frsize;       /* Fragment size - unsupported */
-        long            f_blocks;
-        long            f_bfree;
-        long            f_files;
-        long            f_ffree;
-        long            f_bavail;
-
-        /* Linux specials */
-        __kernel_fsid_t f_fsid;
-        long            f_namelen;
-        long            f_spare[6];
-};
-
-#if (_MIPS_SIM == _MIPS_SIM_ABI32) || (_MIPS_SIM == _MIPS_SIM_NABI32)
-
-/*
- * Unlike the traditional version the LFAPI version has none of the ABI junk
- */
-struct statfs64 {
-        __u32   f_type;
-        __u32   f_bsize;
-        __u32   f_frsize;       /* Fragment size - unsupported */
-        __u32   __pad;
-        __u64   f_blocks;
-        __u64   f_bfree;
-        __u64   f_files;
-        __u64   f_ffree;
-        __u64   f_bavail;
-        __kernel_fsid_t f_fsid;
-        __u32   f_namelen;
-        __u32   f_spare[6];
-};
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64
-
-struct statfs64 {                       /* Same as struct statfs */
-        long            f_type;
-        long            f_bsize;
-        long            f_frsize;       /* Fragment size - unsupported */
-        long            f_blocks;
-        long            f_bfree;
-        long            f_files;
-        long            f_ffree;
-        long            f_bavail;
-
-        /* Linux specials */
-        __kernel_fsid_t f_fsid;
-        long            f_namelen;
-        long            f_spare[6];
-};
-
-struct compat_statfs64 {
-        __u32   f_type;
-        __u32   f_bsize;
-        __u32   f_frsize;       /* Fragment size - unsupported */
-        __u32   __pad;
-        __u64   f_blocks;
-        __u64   f_bfree;
-        __u64   f_files;
-        __u64   f_ffree;
-        __u64   f_bavail;
-        __kernel_fsid_t f_fsid;
-        __u32   f_namelen;
-        __u32   f_spare[6];
-};
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
-
-#endif /* _ASM_STATFS_H */
diff --git a/include/asm-mips/string.h b/include/asm-mips/string.h
deleted file mode 100644
index 436e3ad352d9..000000000000
--- a/include/asm-mips/string.h
+++ /dev/null
@@ -1,143 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1994, 95, 96, 97, 98, 2000, 01 Ralf Baechle
- * Copyright (c) 2000 by Silicon Graphics, Inc.
- * Copyright (c) 2001 MIPS Technologies, Inc.
- */
-#ifndef _ASM_STRING_H
-#define _ASM_STRING_H
-
-
-/*
- * Most of the inline functions are rather naive implementations so I just
- * didn't bother updating them for 64-bit ...
- */
-#ifdef CONFIG_32BIT
-
-#ifndef IN_STRING_C
-
-#define __HAVE_ARCH_STRCPY
-static __inline__ char *strcpy(char *__dest, __const__ char *__src)
-{
-  char *__xdest = __dest;
-
-  __asm__ __volatile__(
-        ".set\tnoreorder\n\t"
-        ".set\tnoat\n"
-        "1:\tlbu\t$1,(%1)\n\t"
-        "addiu\t%1,1\n\t"
-        "sb\t$1,(%0)\n\t"
-        "bnez\t$1,1b\n\t"
-        "addiu\t%0,1\n\t"
-        ".set\tat\n\t"
-        ".set\treorder"
-        : "=r" (__dest), "=r" (__src)
-        : "0" (__dest), "1" (__src)
-        : "memory");
-
-  return __xdest;
-}
-
-#define __HAVE_ARCH_STRNCPY
-static __inline__ char *strncpy(char *__dest, __const__ char *__src, size_t __n)
-{
-  char *__xdest = __dest;
-
-  if (__n == 0)
-    return __xdest;
-
-  __asm__ __volatile__(
-        ".set\tnoreorder\n\t"
-        ".set\tnoat\n"
-        "1:\tlbu\t$1,(%1)\n\t"
-        "subu\t%2,1\n\t"
-        "sb\t$1,(%0)\n\t"
-        "beqz\t$1,2f\n\t"
-        "addiu\t%0,1\n\t"
-        "bnez\t%2,1b\n\t"
-        "addiu\t%1,1\n"
-        "2:\n\t"
-        ".set\tat\n\t"
-        ".set\treorder"
-        : "=r" (__dest), "=r" (__src), "=r" (__n)
-        : "0" (__dest), "1" (__src), "2" (__n)
-        : "memory");
-
-  return __xdest;
-}
-
-#define __HAVE_ARCH_STRCMP
-static __inline__ int strcmp(__const__ char *__cs, __const__ char *__ct)
-{
-  int __res;
-
-  __asm__ __volatile__(
-        ".set\tnoreorder\n\t"
-        ".set\tnoat\n\t"
-        "lbu\t%2,(%0)\n"
-        "1:\tlbu\t$1,(%1)\n\t"
-        "addiu\t%0,1\n\t"
-        "bne\t$1,%2,2f\n\t"
-        "addiu\t%1,1\n\t"
-        "bnez\t%2,1b\n\t"
-        "lbu\t%2,(%0)\n\t"
-#if defined(CONFIG_CPU_R3000)
-        "nop\n\t"
-#endif
-        "move\t%2,$1\n"
-        "2:\tsubu\t%2,$1\n"
-        "3:\t.set\tat\n\t"
-        ".set\treorder"
-        : "=r" (__cs), "=r" (__ct), "=r" (__res)
-        : "0" (__cs), "1" (__ct));
-
-  return __res;
-}
-
-#endif /* !defined(IN_STRING_C) */
-
-#define __HAVE_ARCH_STRNCMP
-static __inline__ int
-strncmp(__const__ char *__cs, __const__ char *__ct, size_t __count)
-{
-        int __res;
-
-        __asm__ __volatile__(
-        ".set\tnoreorder\n\t"
-        ".set\tnoat\n"
-        "1:\tlbu\t%3,(%0)\n\t"
-        "beqz\t%2,2f\n\t"
-        "lbu\t$1,(%1)\n\t"
-        "subu\t%2,1\n\t"
-        "bne\t$1,%3,3f\n\t"
-        "addiu\t%0,1\n\t"
-        "bnez\t%3,1b\n\t"
-        "addiu\t%1,1\n"
-        "2:\n\t"
-#if defined(CONFIG_CPU_R3000)
-        "nop\n\t"
-#endif
-        "move\t%3,$1\n"
-        "3:\tsubu\t%3,$1\n\t"
-        ".set\tat\n\t"
-        ".set\treorder"
-        : "=r" (__cs), "=r" (__ct), "=r" (__count), "=r" (__res)
-        : "0" (__cs), "1" (__ct), "2" (__count));
-
-        return __res;
-}
-#endif /* CONFIG_32BIT */
-
-#define __HAVE_ARCH_MEMSET
-extern void *memset(void *__s, int __c, size_t __count);
-
-#define __HAVE_ARCH_MEMCPY
-extern void *memcpy(void *__to, __const__ void *__from, size_t __n);
-
-#define __HAVE_ARCH_MEMMOVE
-extern void *memmove(void *__dest, __const__ void *__src, size_t __n);
-
-#endif /* _ASM_STRING_H */
diff --git a/include/asm-mips/suspend.h b/include/asm-mips/suspend.h
deleted file mode 100644
index 2562f8f9be0e..000000000000
--- a/include/asm-mips/suspend.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef __ASM_SUSPEND_H
-#define __ASM_SUSPEND_H
-
-/* Somewhen...  Maybe :-)  */
-
-#endif /* __ASM_SUSPEND_H */
diff --git a/include/asm-mips/sysmips.h b/include/asm-mips/sysmips.h
deleted file mode 100644
index 4f47b7d6a5f7..000000000000
--- a/include/asm-mips/sysmips.h
+++ /dev/null
@@ -1,25 +0,0 @@
-/*
- * Definitions for the MIPS sysmips(2) call
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995 by Ralf Baechle
- */
-#ifndef _ASM_SYSMIPS_H
-#define _ASM_SYSMIPS_H
-
-/*
- * Commands for the sysmips(2) call
- *
- * sysmips(2) is deprecated - though some existing software uses it.
- * We only support the following commands.
- */
-#define SETNAME                    1    /* set hostname                  */
-#define FLUSH_CACHE                3    /* writeback and invalidate caches */
-#define MIPS_FIXADE                7    /* control address error fixing  */
-#define MIPS_RDNVRAM              10    /* read NVRAM */
-#define MIPS_ATOMIC_SET         2001    /* atomically set variable       */
-
-#endif /* _ASM_SYSMIPS_H */
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
deleted file mode 100644
index a944eda4faf5..000000000000
--- a/include/asm-mips/system.h
+++ /dev/null
@@ -1,220 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 95, 96, 97, 98, 99, 2003, 06 by Ralf Baechle
- * Copyright (C) 1996 by Paul M. Antoine
- * Copyright (C) 1999 Silicon Graphics
- * Kevin D. Kissell, kevink@mips.org and Carsten Langgaard, carstenl@mips.com
- * Copyright (C) 2000 MIPS Technologies, Inc.
- */
-#ifndef _ASM_SYSTEM_H
-#define _ASM_SYSTEM_H
-
-#include <linux/types.h>
-#include <linux/irqflags.h>
-
-#include <asm/addrspace.h>
-#include <asm/barrier.h>
-#include <asm/cmpxchg.h>
-#include <asm/cpu-features.h>
-#include <asm/dsp.h>
-#include <asm/war.h>
-
-
-/*
- * switch_to(n) should switch tasks to task nr n, first
- * checking that n isn't the current task, in which case it does nothing.
- */
-extern asmlinkage void *resume(void *last, void *next, void *next_ti);
-
-struct task_struct;
-
-#ifdef CONFIG_MIPS_MT_FPAFF
-
-/*
- * Handle the scheduler resume end of FPU affinity management.  We do this
- * inline to try to keep the overhead down. If we have been forced to run on
- * a "CPU" with an FPU because of a previous high level of FP computation,
- * but did not actually use the FPU during the most recent time-slice (CU1
- * isn't set), we undo the restriction on cpus_allowed.
- *
- * We're not calling set_cpus_allowed() here, because we have no need to
- * force prompt migration - we're already switching the current CPU to a
- * different thread.
- */
-
-#define __mips_mt_fpaff_switch_to(prev)                                 \
-do {                                                                    \
-        struct thread_info *__prev_ti = task_thread_info(prev);         \
-                                                                        \
-        if (cpu_has_fpu &&                                              \
-            test_ti_thread_flag(__prev_ti, TIF_FPUBOUND) &&             \
-            (!(KSTK_STATUS(prev) & ST0_CU1))) {                         \
-                clear_ti_thread_flag(__prev_ti, TIF_FPUBOUND);          \
-                prev->cpus_allowed = prev->thread.user_cpus_allowed;    \
-        }                                                               \
-        next->thread.emulated_fp = 0;                                   \
-} while(0)
-
-#else
-#define __mips_mt_fpaff_switch_to(prev) do { (void) (prev); } while (0)
-#endif
-
-#define switch_to(prev, next, last)                                     \
-do {                                                                    \
-        __mips_mt_fpaff_switch_to(prev);                                \
-        if (cpu_has_dsp)                                                \
-                __save_dsp(prev);                                       \
-        (last) = resume(prev, next, task_thread_info(next));            \
-} while (0)
-
-#define finish_arch_switch(prev)                                        \
-do {                                                                    \
-        if (cpu_has_dsp)                                                \
-                __restore_dsp(current);                                 \
-        if (cpu_has_userlocal)                                          \
-                write_c0_userlocal(current_thread_info()->tp_value);    \
-} while (0)
-
-static inline unsigned long __xchg_u32(volatile int * m, unsigned int val)
-{
-        __u32 retval;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long dummy;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %3                  # xchg_u32      \n"
-                "       .set    mips0                                   \n"
-                "       move    %2, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "       sc      %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long dummy;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     ll      %0, %3                  # xchg_u32      \n"
-                "       .set    mips0                                   \n"
-                "       move    %2, %z4                                 \n"
-                "       .set    mips3                                   \n"
-                "       sc      %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                retval = *m;
-                *m = val;
-                raw_local_irq_restore(flags);   /* implies memory barrier  */
-        }
-
-        smp_llsc_mb();
-
-        return retval;
-}
-
-#ifdef CONFIG_64BIT
-static inline __u64 __xchg_u64(volatile __u64 * m, __u64 val)
-{
-        __u64 retval;
-
-        if (cpu_has_llsc && R10000_LLSC_WAR) {
-                unsigned long dummy;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %3                  # xchg_u64      \n"
-                "       move    %2, %z4                                 \n"
-                "       scd     %2, %1                                  \n"
-                "       beqzl   %2, 1b                                  \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
-        } else if (cpu_has_llsc) {
-                unsigned long dummy;
-
-                __asm__ __volatile__(
-                "       .set    mips3                                   \n"
-                "1:     lld     %0, %3                  # xchg_u64      \n"
-                "       move    %2, %z4                                 \n"
-                "       scd     %2, %1                                  \n"
-                "       beqz    %2, 2f                                  \n"
-                "       .subsection 2                                   \n"
-                "2:     b       1b                                      \n"
-                "       .previous                                       \n"
-                "       .set    mips0                                   \n"
-                : "=&r" (retval), "=m" (*m), "=&r" (dummy)
-                : "R" (*m), "Jr" (val)
-                : "memory");
-        } else {
-                unsigned long flags;
-
-                raw_local_irq_save(flags);
-                retval = *m;
-                *m = val;
-                raw_local_irq_restore(flags);   /* implies memory barrier  */
-        }
-
-        smp_llsc_mb();
-
-        return retval;
-}
-#else
-extern __u64 __xchg_u64_unsupported_on_32bit_kernels(volatile __u64 * m, __u64 val);
-#define __xchg_u64 __xchg_u64_unsupported_on_32bit_kernels
-#endif
-
-/* This function doesn't exist, so you'll get a linker error
-   if something tries to do an invalid xchg().  */
-extern void __xchg_called_with_bad_pointer(void);
-
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-        switch (size) {
-        case 4:
-                return __xchg_u32(ptr, x);
-        case 8:
-                return __xchg_u64(ptr, x);
-        }
-        __xchg_called_with_bad_pointer();
-        return x;
-}
-
-#define xchg(ptr, x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x), (ptr), sizeof(*(ptr))))
-
-extern void set_handler(unsigned long offset, void *addr, unsigned long len);
-extern void set_uncached_handler(unsigned long offset, void *addr, unsigned long len);
-
-typedef void (*vi_handler_t)(void);
-extern void *set_vi_handler(int n, vi_handler_t addr);
-
-extern void *set_except_vector(int n, void *addr);
-extern unsigned long ebase;
-extern void per_cpu_trap_init(void);
-
-/*
- * See include/asm-ia64/system.h; prevents deadlock on SMP
- * systems.
- */
-#define __ARCH_WANT_UNLOCKED_CTXSW
-
-extern unsigned long arch_align_stack(unsigned long sp);
-
-#endif /* _ASM_SYSTEM_H */
diff --git a/include/asm-mips/termbits.h b/include/asm-mips/termbits.h
deleted file mode 100644
index c83c68444e86..000000000000
--- a/include/asm-mips/termbits.h
+++ /dev/null
@@ -1,226 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 99, 2001, 06 Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- * Copyright (C) 2001 MIPS Technologies, Inc.
- */
-#ifndef _ASM_TERMBITS_H
-#define _ASM_TERMBITS_H
-
-#include <linux/posix_types.h>
-
-typedef unsigned char cc_t;
-typedef unsigned int speed_t;
-typedef unsigned int tcflag_t;
-
-/*
- * The ABI says nothing about NCC but seems to use NCCS as
- * replacement for it in struct termio
- */
-#define NCCS    23
-struct termios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-};
-
-struct termios2 {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-struct ktermios {
-        tcflag_t c_iflag;               /* input mode flags */
-        tcflag_t c_oflag;               /* output mode flags */
-        tcflag_t c_cflag;               /* control mode flags */
-        tcflag_t c_lflag;               /* local mode flags */
-        cc_t c_line;                    /* line discipline */
-        cc_t c_cc[NCCS];                /* control characters */
-        speed_t c_ispeed;               /* input speed */
-        speed_t c_ospeed;               /* output speed */
-};
-
-/* c_cc characters */
-#define VINTR            0              /* Interrupt character [ISIG].  */
-#define VQUIT            1              /* Quit character [ISIG].  */
-#define VERASE           2              /* Erase character [ICANON].  */
-#define VKILL            3              /* Kill-line character [ICANON].  */
-#define VMIN             4              /* Minimum number of bytes read at once [!ICANON].  */
-#define VTIME            5              /* Time-out value (tenths of a second) [!ICANON].  */
-#define VEOL2            6              /* Second EOL character [ICANON].  */
-#define VSWTC            7              /* ??? */
-#define VSWTCH          VSWTC
-#define VSTART           8              /* Start (X-ON) character [IXON, IXOFF].  */
-#define VSTOP            9              /* Stop (X-OFF) character [IXON, IXOFF].  */
-#define VSUSP           10              /* Suspend character [ISIG].  */
-#if 0
-/*
- * VDSUSP is not supported
- */
-#define VDSUSP          11              /* Delayed suspend character [ISIG].  */
-#endif
-#define VREPRINT        12              /* Reprint-line character [ICANON].  */
-#define VDISCARD        13              /* Discard character [IEXTEN].  */
-#define VWERASE         14              /* Word-erase character [ICANON].  */
-#define VLNEXT          15              /* Literal-next character [IEXTEN].  */
-#define VEOF            16              /* End-of-file character [ICANON].  */
-#define VEOL            17              /* End-of-line character [ICANON].  */
-
-/* c_iflag bits */
-#define IGNBRK  0000001         /* Ignore break condition.  */
-#define BRKINT  0000002         /* Signal interrupt on break.  */
-#define IGNPAR  0000004         /* Ignore characters with parity errors.  */
-#define PARMRK  0000010         /* Mark parity and framing errors.  */
-#define INPCK   0000020         /* Enable input parity check.  */
-#define ISTRIP  0000040         /* Strip 8th bit off characters.  */
-#define INLCR   0000100         /* Map NL to CR on input.  */
-#define IGNCR   0000200         /* Ignore CR.  */
-#define ICRNL   0000400         /* Map CR to NL on input.  */
-#define IUCLC   0001000         /* Map upper case to lower case on input.  */
-#define IXON    0002000         /* Enable start/stop output control.  */
-#define IXANY   0004000         /* Any character will restart after stop.  */
-#define IXOFF   0010000         /* Enable start/stop input control.  */
-#define IMAXBEL 0020000         /* Ring bell when input queue is full.  */
-#define IUTF8   0040000         /* Input is UTF-8 */
-
-/* c_oflag bits */
-#define OPOST   0000001         /* Perform output processing.  */
-#define OLCUC   0000002         /* Map lower case to upper case on output.  */
-#define ONLCR   0000004         /* Map NL to CR-NL on output.  */
-#define OCRNL   0000010
-#define ONOCR   0000020
-#define ONLRET  0000040
-#define OFILL   0000100
-#define OFDEL   0000200
-#define NLDLY   0000400
-#define   NL0   0000000
-#define   NL1   0000400
-#define CRDLY   0003000
-#define   CR0   0000000
-#define   CR1   0001000
-#define   CR2   0002000
-#define   CR3   0003000
-#define TABDLY  0014000
-#define   TAB0  0000000
-#define   TAB1  0004000
-#define   TAB2  0010000
-#define   TAB3  0014000
-#define   XTABS 0014000
-#define BSDLY   0020000
-#define   BS0   0000000
-#define   BS1   0020000
-#define VTDLY   0040000
-#define   VT0   0000000
-#define   VT1   0040000
-#define FFDLY   0100000
-#define   FF0   0000000
-#define   FF1   0100000
-/*
-#define PAGEOUT ???
-#define WRAP    ???
- */
-
-/* c_cflag bit meaning */
-#define CBAUD   0010017
-#define  B0     0000000         /* hang up */
-#define  B50    0000001
-#define  B75    0000002
-#define  B110   0000003
-#define  B134   0000004
-#define  B150   0000005
-#define  B200   0000006
-#define  B300   0000007
-#define  B600   0000010
-#define  B1200  0000011
-#define  B1800  0000012
-#define  B2400  0000013
-#define  B4800  0000014
-#define  B9600  0000015
-#define  B19200 0000016
-#define  B38400 0000017
-#define EXTA B19200
-#define EXTB B38400
-#define CSIZE   0000060         /* Number of bits per byte (mask).  */
-#define   CS5   0000000         /* 5 bits per byte.  */
-#define   CS6   0000020         /* 6 bits per byte.  */
-#define   CS7   0000040         /* 7 bits per byte.  */
-#define   CS8   0000060         /* 8 bits per byte.  */
-#define CSTOPB  0000100         /* Two stop bits instead of one.  */
-#define CREAD   0000200         /* Enable receiver.  */
-#define PARENB  0000400         /* Parity enable.  */
-#define PARODD  0001000         /* Odd parity instead of even.  */
-#define HUPCL   0002000         /* Hang up on last close.  */
-#define CLOCAL  0004000         /* Ignore modem status lines.  */
-#define CBAUDEX 0010000
-#define    BOTHER 0010000
-#define    B57600 0010001
-#define   B115200 0010002
-#define   B230400 0010003
-#define   B460800 0010004
-#define   B500000 0010005
-#define   B576000 0010006
-#define   B921600 0010007
-#define  B1000000 0010010
-#define  B1152000 0010011
-#define  B1500000 0010012
-#define  B2000000 0010013
-#define  B2500000 0010014
-#define  B3000000 0010015
-#define  B3500000 0010016
-#define  B4000000 0010017
-#define CIBAUD    002003600000  /* input baud rate */
-#define CMSPAR    010000000000  /* mark or space (stick) parity */
-#define CRTSCTS   020000000000  /* flow control */
-
-#define IBSHIFT 16              /* Shift from CBAUD to CIBAUD */
-
-/* c_lflag bits */
-#define ISIG    0000001         /* Enable signals.  */
-#define ICANON  0000002         /* Do erase and kill processing.  */
-#define XCASE   0000004
-#define ECHO    0000010         /* Enable echo.  */
-#define ECHOE   0000020         /* Visual erase for ERASE.  */
-#define ECHOK   0000040         /* Echo NL after KILL.  */
-#define ECHONL  0000100         /* Echo NL even if ECHO is off.  */
-#define NOFLSH  0000200         /* Disable flush after interrupt.  */
-#define IEXTEN  0000400         /* Enable DISCARD and LNEXT.  */
-#define ECHOCTL 0001000         /* Echo control characters as ^X.  */
-#define ECHOPRT 0002000         /* Hardcopy visual erase.  */
-#define ECHOKE  0004000         /* Visual erase for KILL.  */
-#define FLUSHO  0020000
-#define PENDIN  0040000         /* Retype pending input (state).  */
-#define TOSTOP  0100000         /* Send SIGTTOU for background output.  */
-#define ITOSTOP TOSTOP
-
-/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
-#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
-
-/* tcflow() and TCXONC use these */
-#define TCOOFF          0       /* Suspend output.  */
-#define TCOON           1       /* Restart suspended output.  */
-#define TCIOFF          2       /* Send a STOP character.  */
-#define TCION           3       /* Send a START character.  */
-
-/* tcflush() and TCFLSH use these */
-#define TCIFLUSH        0       /* Discard data received but not yet read.  */
-#define TCOFLUSH        1       /* Discard data written but not yet sent.  */
-#define TCIOFLUSH       2       /* Discard all pending data.  */
-
-/* tcsetattr uses these */
-#define TCSANOW         TCSETS  /* Change immediately.  */
-#define TCSADRAIN       TCSETSW /* Change when pending output is written.  */
-#define TCSAFLUSH       TCSETSF /* Flush pending input before changing.  */
-
-#endif /* _ASM_TERMBITS_H */
diff --git a/include/asm-mips/termios.h b/include/asm-mips/termios.h
deleted file mode 100644
index a275661fa7e1..000000000000
--- a/include/asm-mips/termios.h
+++ /dev/null
@@ -1,132 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 1996, 2000, 2001 by Ralf Baechle
- * Copyright (C) 2000, 2001 Silicon Graphics, Inc.
- */
-#ifndef _ASM_TERMIOS_H
-#define _ASM_TERMIOS_H
-
-#include <asm/termbits.h>
-#include <asm/ioctls.h>
-
-struct sgttyb {
-        char    sg_ispeed;
-        char    sg_ospeed;
-        char    sg_erase;
-        char    sg_kill;
-        int     sg_flags;       /* SGI special - int, not short */
-};
-
-struct tchars {
-        char    t_intrc;
-        char    t_quitc;
-        char    t_startc;
-        char    t_stopc;
-        char    t_eofc;
-        char    t_brkc;
-};
-
-struct ltchars {
-        char    t_suspc;        /* stop process signal */
-        char    t_dsuspc;       /* delayed stop process signal */
-        char    t_rprntc;       /* reprint line */
-        char    t_flushc;       /* flush output (toggles) */
-        char    t_werasc;       /* word erase */
-        char    t_lnextc;       /* literal next character */
-};
-
-/* TIOCGSIZE, TIOCSSIZE not defined yet.  Only needed for SunOS source
-   compatibility anyway ... */
-
-struct winsize {
-        unsigned short ws_row;
-        unsigned short ws_col;
-        unsigned short ws_xpixel;
-        unsigned short ws_ypixel;
-};
-
-#define NCC     8
-struct termio {
-        unsigned short c_iflag;         /* input mode flags */
-        unsigned short c_oflag;         /* output mode flags */
-        unsigned short c_cflag;         /* control mode flags */
-        unsigned short c_lflag;         /* local mode flags */
-        char c_line;                    /* line discipline */
-        unsigned char c_cc[NCCS];       /* control characters */
-};
-
-#ifdef __KERNEL__
-#include <linux/module.h>
-
-/*
- *      intr=^C         quit=^\         erase=del       kill=^U
- *      vmin=\1         vtime=\0        eol2=\0         swtc=\0
- *      start=^Q        stop=^S         susp=^Z         vdsusp=
- *      reprint=^R      discard=^U      werase=^W       lnext=^V
- *      eof=^D          eol=\0
- */
-#define INIT_C_CC "\003\034\177\025\1\0\0\0\021\023\032\0\022\017\027\026\004\0"
-#endif
-
-/* modem lines */
-#define TIOCM_LE        0x001           /* line enable */
-#define TIOCM_DTR       0x002           /* data terminal ready */
-#define TIOCM_RTS       0x004           /* request to send */
-#define TIOCM_ST        0x010           /* secondary transmit */
-#define TIOCM_SR        0x020           /* secondary receive */
-#define TIOCM_CTS       0x040           /* clear to send */
-#define TIOCM_CAR       0x100           /* carrier detect */
-#define TIOCM_CD        TIOCM_CAR
-#define TIOCM_RNG       0x200           /* ring */
-#define TIOCM_RI        TIOCM_RNG
-#define TIOCM_DSR       0x400           /* data set ready */
-#define TIOCM_OUT1      0x2000
-#define TIOCM_OUT2      0x4000
-#define TIOCM_LOOP      0x8000
-
-#ifdef __KERNEL__
-
-#include <linux/string.h>
-
-/*
- * Translate a "termio" structure into a "termios". Ugh.
- */
-#define user_termio_to_kernel_termios(termios, termio) \
-({ \
-        unsigned short tmp; \
-        get_user(tmp, &(termio)->c_iflag); \
-        (termios)->c_iflag = (0xffff0000 & ((termios)->c_iflag)) | tmp; \
-        get_user(tmp, &(termio)->c_oflag); \
-        (termios)->c_oflag = (0xffff0000 & ((termios)->c_oflag)) | tmp; \
-        get_user(tmp, &(termio)->c_cflag); \
-        (termios)->c_cflag = (0xffff0000 & ((termios)->c_cflag)) | tmp; \
-        get_user(tmp, &(termio)->c_lflag); \
-        (termios)->c_lflag = (0xffff0000 & ((termios)->c_lflag)) | tmp; \
-        get_user((termios)->c_line, &(termio)->c_line); \
-        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
-})
-
-/*
- * Translate a "termios" structure into a "termio". Ugh.
- */
-#define kernel_termios_to_user_termio(termio, termios) \
-({ \
-        put_user((termios)->c_iflag, &(termio)->c_iflag); \
-        put_user((termios)->c_oflag, &(termio)->c_oflag); \
-        put_user((termios)->c_cflag, &(termio)->c_cflag); \
-        put_user((termios)->c_lflag, &(termio)->c_lflag); \
-        put_user((termios)->c_line, &(termio)->c_line); \
-        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
-})
-
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
-#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
-
-#endif /* defined(__KERNEL__) */
-
-#endif /* _ASM_TERMIOS_H */
diff --git a/include/asm-mips/thread_info.h b/include/asm-mips/thread_info.h
deleted file mode 100644
index bb3060699df2..000000000000
--- a/include/asm-mips/thread_info.h
+++ /dev/null
@@ -1,151 +0,0 @@
-/* thread_info.h: MIPS low-level thread information
- *
- * Copyright (C) 2002  David Howells (dhowells@redhat.com)
- * - Incorporating suggestions made by Linus Torvalds and Dave Miller
- */
-
-#ifndef _ASM_THREAD_INFO_H
-#define _ASM_THREAD_INFO_H
-
-#ifdef __KERNEL__
-
-
-#ifndef __ASSEMBLY__
-
-#include <asm/processor.h>
-
-/*
- * low level task data that entry.S needs immediate access to
- * - this struct should fit entirely inside of one cache line
- * - this struct shares the supervisor stack pages
- * - if the contents of this structure are changed, the assembly constants
- *   must also be changed
- */
-struct thread_info {
-        struct task_struct      *task;          /* main task structure */
-        struct exec_domain      *exec_domain;   /* execution domain */
-        unsigned long           flags;          /* low level flags */
-        unsigned long           tp_value;       /* thread pointer */
-        __u32                   cpu;            /* current CPU */
-        int                     preempt_count;  /* 0 => preemptable, <0 => BUG */
-
-        mm_segment_t            addr_limit;     /* thread address space:
-                                                   0-0xBFFFFFFF for user-thead
-                                                   0-0xFFFFFFFF for kernel-thread
-                                                */
-        struct restart_block    restart_block;
-        struct pt_regs          *regs;
-};
-
-/*
- * macros/functions for gaining access to the thread information structure
- *
- * preempt_count needs to be 1 initially, until the scheduler is functional.
- */
-#define INIT_THREAD_INFO(tsk)                   \
-{                                               \
-        .task           = &tsk,                 \
-        .exec_domain    = &default_exec_domain, \
-        .flags          = _TIF_FIXADE,          \
-        .cpu            = 0,                    \
-        .preempt_count  = 1,                    \
-        .addr_limit     = KERNEL_DS,            \
-        .restart_block  = {                     \
-                .fn = do_no_restart_syscall,    \
-        },                                      \
-}
-
-#define init_thread_info        (init_thread_union.thread_info)
-#define init_stack              (init_thread_union.stack)
-
-/* How to get the thread information struct from C.  */
-register struct thread_info *__current_thread_info __asm__("$28");
-#define current_thread_info()  __current_thread_info
-
-/* thread information allocation */
-#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_32BIT)
-#define THREAD_SIZE_ORDER (1)
-#endif
-#if defined(CONFIG_PAGE_SIZE_4KB) && defined(CONFIG_64BIT)
-#define THREAD_SIZE_ORDER (2)
-#endif
-#ifdef CONFIG_PAGE_SIZE_8KB
-#define THREAD_SIZE_ORDER (1)
-#endif
-#ifdef CONFIG_PAGE_SIZE_16KB
-#define THREAD_SIZE_ORDER (0)
-#endif
-#ifdef CONFIG_PAGE_SIZE_64KB
-#define THREAD_SIZE_ORDER (0)
-#endif
-
-#define THREAD_SIZE (PAGE_SIZE << THREAD_SIZE_ORDER)
-#define THREAD_MASK (THREAD_SIZE - 1UL)
-
-#define __HAVE_ARCH_THREAD_INFO_ALLOCATOR
-
-#ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(tsk)                                  \
-({                                                              \
-        struct thread_info *ret;                                \
-                                                                \
-        ret = kzalloc(THREAD_SIZE, GFP_KERNEL);                 \
-                                                                \
-        ret;                                                    \
-})
-#else
-#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
-#endif
-
-#define free_thread_info(info) kfree(info)
-
-#endif /* !__ASSEMBLY__ */
-
-#define PREEMPT_ACTIVE          0x10000000
-
-/*
- * thread information flags
- * - these are process state flags that various assembly files may need to
- *   access
- * - pending work-to-be-done flags are in LSW
- * - other flags in MSW
- */
-#define TIF_SIGPENDING          1       /* signal pending */
-#define TIF_NEED_RESCHED        2       /* rescheduling necessary */
-#define TIF_SYSCALL_AUDIT       3       /* syscall auditing active */
-#define TIF_SECCOMP             4       /* secure computing */
-#define TIF_RESTORE_SIGMASK     9       /* restore signal mask in do_signal() */
-#define TIF_USEDFPU             16      /* FPU was used by this task this quantum (SMP) */
-#define TIF_POLLING_NRFLAG      17      /* true if poll_idle() is polling TIF_NEED_RESCHED */
-#define TIF_MEMDIE              18
-#define TIF_FREEZE              19
-#define TIF_FIXADE              20      /* Fix address errors in software */
-#define TIF_LOGADE              21      /* Log address errors to syslog */
-#define TIF_32BIT_REGS          22      /* also implies 16/32 fprs */
-#define TIF_32BIT_ADDR          23      /* 32-bit address space (o32/n32) */
-#define TIF_FPUBOUND            24      /* thread bound to FPU-full CPU set */
-#define TIF_SYSCALL_TRACE       31      /* syscall trace active */
-
-#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
-#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
-#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
-#define _TIF_SYSCALL_AUDIT      (1<<TIF_SYSCALL_AUDIT)
-#define _TIF_SECCOMP            (1<<TIF_SECCOMP)
-#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
-#define _TIF_USEDFPU            (1<<TIF_USEDFPU)
-#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
-#define _TIF_FREEZE             (1<<TIF_FREEZE)
-#define _TIF_FIXADE             (1<<TIF_FIXADE)
-#define _TIF_LOGADE             (1<<TIF_LOGADE)
-#define _TIF_32BIT_REGS         (1<<TIF_32BIT_REGS)
-#define _TIF_32BIT_ADDR         (1<<TIF_32BIT_ADDR)
-#define _TIF_FPUBOUND           (1<<TIF_FPUBOUND)
-
-/* work to do on interrupt/exception return */
-#define _TIF_WORK_MASK          (0x0000ffef & ~_TIF_SECCOMP)
-/* work to do on any return to u-space */
-#define _TIF_ALLWORK_MASK       (0x8000ffff & ~_TIF_SECCOMP)
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-mips/time.h b/include/asm-mips/time.h
deleted file mode 100644
index d3bd5c5aa2ec..000000000000
--- a/include/asm-mips/time.h
+++ /dev/null
@@ -1,79 +0,0 @@
-/*
- * Copyright (C) 2001, 2002, MontaVista Software Inc.
- * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
- * Copyright (c) 2003  Maciej W. Rozycki
- *
- * include/asm-mips/time.h
- *     header file for the new style time.c file and time services.
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-#ifndef _ASM_TIME_H
-#define _ASM_TIME_H
-
-#include <linux/rtc.h>
-#include <linux/spinlock.h>
-#include <linux/clockchips.h>
-#include <linux/clocksource.h>
-
-extern spinlock_t rtc_lock;
-
-/*
- * RTC ops.  By default, they point to weak no-op RTC functions.
- *      rtc_mips_set_time - reverse the above translation and set time to RTC.
- *      rtc_mips_set_mmss - similar to rtc_set_time, but only min and sec need
- *                      to be set.  Used by RTC sync-up.
- */
-extern int rtc_mips_set_time(unsigned long);
-extern int rtc_mips_set_mmss(unsigned long);
-
-/*
- * board specific routines required by time_init().
- */
-extern void plat_time_init(void);
-
-/*
- * mips_hpt_frequency - must be set if you intend to use an R4k-compatible
- * counter as a timer interrupt source.
- */
-extern unsigned int mips_hpt_frequency;
-
-/*
- * The performance counter IRQ on MIPS is a close relative to the timer IRQ
- * so it lives here.
- */
-extern int (*perf_irq)(void);
-
-/*
- * Initialize the calling CPU's compare interrupt as clockevent device
- */
-#ifdef CONFIG_CEVT_R4K
-extern int mips_clockevent_init(void);
-extern unsigned int __weak get_c0_compare_int(void);
-#else
-static inline int mips_clockevent_init(void)
-{
-        return -ENXIO;
-}
-#endif
-
-/*
- * Initialize the count register as a clocksource
- */
-#ifdef CONFIG_CEVT_R4K
-extern int init_mips_clocksource(void);
-#else
-static inline int init_mips_clocksource(void)
-{
-        return 0;
-}
-#endif
-
-extern void clocksource_set_clock(struct clocksource *cs, unsigned int clock);
-extern void clockevent_set_clock(struct clock_event_device *cd,
-                unsigned int clock);
-
-#endif /* _ASM_TIME_H */
diff --git a/include/asm-mips/timex.h b/include/asm-mips/timex.h
deleted file mode 100644
index 6529704aa73a..000000000000
--- a/include/asm-mips/timex.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1998, 1999, 2003 by Ralf Baechle
- */
-#ifndef _ASM_TIMEX_H
-#define _ASM_TIMEX_H
-
-#ifdef __KERNEL__
-
-#include <asm/mipsregs.h>
-
-/*
- * This is the clock rate of the i8253 PIT.  A MIPS system may not have
- * a PIT by the symbol is used all over the kernel including some APIs.
- * So keeping it defined to the number for the PIT is the only sane thing
- * for now.
- */
-#define CLOCK_TICK_RATE 1193182
-
-/*
- * Standard way to access the cycle counter.
- * Currently only used on SMP for scheduling.
- *
- * Only the low 32 bits are available as a continuously counting entity.
- * But this only means we'll force a reschedule every 8 seconds or so,
- * which isn't an evil thing.
- *
- * We know that all SMP capable CPUs have cycle counters.
- */
-
-typedef unsigned int cycles_t;
-
-static inline cycles_t get_cycles(void)
-{
-        return 0;
-}
-
-#endif /* __KERNEL__ */
-
-#endif /*  _ASM_TIMEX_H */
diff --git a/include/asm-mips/titan_dep.h b/include/asm-mips/titan_dep.h
deleted file mode 100644
index fee1908c65d2..000000000000
--- a/include/asm-mips/titan_dep.h
+++ /dev/null
@@ -1,231 +0,0 @@
-/*
- * Copyright 2003 PMC-Sierra
- * Author: Manish Lachwani (lachwani@pmc-sierra.com)
- *
- * Board specific definititions for the PMC-Sierra Yosemite
- *
- * This program is free software; you can redistribute  it and/or modify it
- * under  the terms of  the GNU General  Public License as published by the
- * Free Software Foundation;  either version 2 of the  License, or (at your
- * option) any later version.
- */
-
-#ifndef __TITAN_DEP_H__
-#define __TITAN_DEP_H__
-
-#include <asm/addrspace.h>              /* for KSEG1ADDR() */
-#include <asm/byteorder.h>              /* for cpu_to_le32() */
-
-#define TITAN_READ(ofs)                                                 \
-        (*(volatile u32 *)(ocd_base+(ofs)))
-#define TITAN_READ_16(ofs)                                              \
-        (*(volatile u16 *)(ocd_base+(ofs)))
-#define TITAN_READ_8(ofs)                                               \
-        (*(volatile u8 *)(ocd_base+(ofs)))
-
-#define TITAN_WRITE(ofs, data)                                          \
-        do { *(volatile u32 *)(ocd_base+(ofs)) = (data); } while (0)
-#define TITAN_WRITE_16(ofs, data)                                       \
-        do { *(volatile u16 *)(ocd_base+(ofs)) = (data); } while (0)
-#define TITAN_WRITE_8(ofs, data)                                        \
-        do { *(volatile u8 *)(ocd_base+(ofs)) = (data); } while (0)
-
-/*
- * PCI specific defines
- */
-#define TITAN_PCI_0_CONFIG_ADDRESS      0x780
-#define TITAN_PCI_0_CONFIG_DATA         0x784
-
-/*
- * HT specific defines
- */
-#define RM9000x2_HTLINK_REG             0xbb000644
-#define RM9000x2_BASE_ADDR              0xbb000000
-
-#define OCD_BASE                        0xfb000000UL
-#define OCD_SIZE                        0x3000UL
-
-extern unsigned long ocd_base;
-
-/*
- * OCD Registers
- */
-#define RM9000x2_OCD_LKB5               0x0128          /* Ethernet */
-#define RM9000x2_OCD_LKM5               0x012c
-
-#define RM9000x2_OCD_LKB7               0x0138          /* HT Region 0 */
-#define RM9000x2_OCD_LKM7               0x013c
-#define RM9000x2_OCD_LKB8               0x0140          /* HT Region 1 */
-#define RM9000x2_OCD_LKM8               0x0144
-
-#define RM9000x2_OCD_LKB9               0x0148          /* Local Bus */
-#define RM9000x2_OCD_LKM9               0x014c
-#define RM9000x2_OCD_LKB10              0x0150
-#define RM9000x2_OCD_LKM10              0x0154
-#define RM9000x2_OCD_LKB11              0x0158
-#define RM9000x2_OCD_LKM11              0x015c
-#define RM9000x2_OCD_LKB12              0x0160
-#define RM9000x2_OCD_LKM12              0x0164
-
-#define RM9000x2_OCD_LKB13              0x0168          /* Scratch RAM */
-#define RM9000x2_OCD_LKM13              0x016c
-
-#define RM9000x2_OCD_LPD0               0x0200          /* Local Bus */
-#define RM9000x2_OCD_LPD1               0x0210
-#define RM9000x2_OCD_LPD2               0x0220
-#define RM9000x2_OCD_LPD3               0x0230
-
-#define RM9000x2_OCD_HTDVID             0x0600  /* HT Device Header */
-#define RM9000x2_OCD_HTSC               0x0604
-#define RM9000x2_OCD_HTCCR              0x0608
-#define RM9000x2_OCD_HTBHL              0x060c
-#define RM9000x2_OCD_HTBAR0             0x0610
-#define RM9000x2_OCD_HTBAR1             0x0614
-#define RM9000x2_OCD_HTBAR2             0x0618
-#define RM9000x2_OCD_HTBAR3             0x061c
-#define RM9000x2_OCD_HTBAR4             0x0620
-#define RM9000x2_OCD_HTBAR5             0x0624
-#define RM9000x2_OCD_HTCBCPT            0x0628
-#define RM9000x2_OCD_HTSDVID            0x062c
-#define RM9000x2_OCD_HTXRA              0x0630
-#define RM9000x2_OCD_HTCAP1             0x0634
-#define RM9000x2_OCD_HTIL               0x063c
-
-#define RM9000x2_OCD_HTLCC              0x0640  /* HT Capability Block */
-#define RM9000x2_OCD_HTLINK             0x0644
-#define RM9000x2_OCD_HTFQREV            0x0648
-
-#define RM9000x2_OCD_HTERCTL            0x0668  /* HT Controller */
-#define RM9000x2_OCD_HTRXDB             0x066c
-#define RM9000x2_OCD_HTIMPED            0x0670
-#define RM9000x2_OCD_HTSWIMP            0x0674
-#define RM9000x2_OCD_HTCAL              0x0678
-
-#define RM9000x2_OCD_HTBAA30            0x0680
-#define RM9000x2_OCD_HTBAA54            0x0684
-#define RM9000x2_OCD_HTMASK0            0x0688
-#define RM9000x2_OCD_HTMASK1            0x068c
-#define RM9000x2_OCD_HTMASK2            0x0690
-#define RM9000x2_OCD_HTMASK3            0x0694
-#define RM9000x2_OCD_HTMASK4            0x0698
-#define RM9000x2_OCD_HTMASK5            0x069c
-
-#define RM9000x2_OCD_HTIFCTL            0x06a0
-#define RM9000x2_OCD_HTPLL              0x06a4
-
-#define RM9000x2_OCD_HTSRI              0x06b0
-#define RM9000x2_OCD_HTRXNUM            0x06b4
-#define RM9000x2_OCD_HTTXNUM            0x06b8
-
-#define RM9000x2_OCD_HTTXCNT            0x06c8
-
-#define RM9000x2_OCD_HTERROR            0x06d8
-#define RM9000x2_OCD_HTRCRCE            0x06dc
-#define RM9000x2_OCD_HTEOI              0x06e0
-
-#define RM9000x2_OCD_CRCR               0x06f0
-
-#define RM9000x2_OCD_HTCFGA             0x06f8
-#define RM9000x2_OCD_HTCFGD             0x06fc
-
-#define RM9000x2_OCD_INTMSG             0x0a00
-
-#define RM9000x2_OCD_INTPIN0            0x0a40
-#define RM9000x2_OCD_INTPIN1            0x0a44
-#define RM9000x2_OCD_INTPIN2            0x0a48
-#define RM9000x2_OCD_INTPIN3            0x0a4c
-#define RM9000x2_OCD_INTPIN4            0x0a50
-#define RM9000x2_OCD_INTPIN5            0x0a54
-#define RM9000x2_OCD_INTPIN6            0x0a58
-#define RM9000x2_OCD_INTPIN7            0x0a5c
-#define RM9000x2_OCD_SEM                0x0a60
-#define RM9000x2_OCD_SEMSET             0x0a64
-#define RM9000x2_OCD_SEMCLR             0x0a68
-
-#define RM9000x2_OCD_TKT                0x0a70
-#define RM9000x2_OCD_TKTINC             0x0a74
-
-#define RM9000x2_OCD_NMICONFIG          0x0ac0          /* Interrupts */
-#define RM9000x2_OCD_INTP0PRI           0x1a80
-#define RM9000x2_OCD_INTP1PRI           0x1a80
-#define RM9000x2_OCD_INTP0STATUS0       0x1b00
-#define RM9000x2_OCD_INTP0MASK0         0x1b04
-#define RM9000x2_OCD_INTP0SET0          0x1b08
-#define RM9000x2_OCD_INTP0CLEAR0        0x1b0c
-#define RM9000x2_OCD_INTP0STATUS1       0x1b10
-#define RM9000x2_OCD_INTP0MASK1         0x1b14
-#define RM9000x2_OCD_INTP0SET1          0x1b18
-#define RM9000x2_OCD_INTP0CLEAR1        0x1b1c
-#define RM9000x2_OCD_INTP0STATUS2       0x1b20
-#define RM9000x2_OCD_INTP0MASK2         0x1b24
-#define RM9000x2_OCD_INTP0SET2          0x1b28
-#define RM9000x2_OCD_INTP0CLEAR2        0x1b2c
-#define RM9000x2_OCD_INTP0STATUS3       0x1b30
-#define RM9000x2_OCD_INTP0MASK3         0x1b34
-#define RM9000x2_OCD_INTP0SET3          0x1b38
-#define RM9000x2_OCD_INTP0CLEAR3        0x1b3c
-#define RM9000x2_OCD_INTP0STATUS4       0x1b40
-#define RM9000x2_OCD_INTP0MASK4         0x1b44
-#define RM9000x2_OCD_INTP0SET4          0x1b48
-#define RM9000x2_OCD_INTP0CLEAR4        0x1b4c
-#define RM9000x2_OCD_INTP0STATUS5       0x1b50
-#define RM9000x2_OCD_INTP0MASK5         0x1b54
-#define RM9000x2_OCD_INTP0SET5          0x1b58
-#define RM9000x2_OCD_INTP0CLEAR5        0x1b5c
-#define RM9000x2_OCD_INTP0STATUS6       0x1b60
-#define RM9000x2_OCD_INTP0MASK6         0x1b64
-#define RM9000x2_OCD_INTP0SET6          0x1b68
-#define RM9000x2_OCD_INTP0CLEAR6        0x1b6c
-#define RM9000x2_OCD_INTP0STATUS7       0x1b70
-#define RM9000x2_OCD_INTP0MASK7         0x1b74
-#define RM9000x2_OCD_INTP0SET7          0x1b78
-#define RM9000x2_OCD_INTP0CLEAR7        0x1b7c
-#define RM9000x2_OCD_INTP1STATUS0       0x2b00
-#define RM9000x2_OCD_INTP1MASK0         0x2b04
-#define RM9000x2_OCD_INTP1SET0          0x2b08
-#define RM9000x2_OCD_INTP1CLEAR0        0x2b0c
-#define RM9000x2_OCD_INTP1STATUS1       0x2b10
-#define RM9000x2_OCD_INTP1MASK1         0x2b14
-#define RM9000x2_OCD_INTP1SET1          0x2b18
-#define RM9000x2_OCD_INTP1CLEAR1        0x2b1c
-#define RM9000x2_OCD_INTP1STATUS2       0x2b20
-#define RM9000x2_OCD_INTP1MASK2         0x2b24
-#define RM9000x2_OCD_INTP1SET2          0x2b28
-#define RM9000x2_OCD_INTP1CLEAR2        0x2b2c
-#define RM9000x2_OCD_INTP1STATUS3       0x2b30
-#define RM9000x2_OCD_INTP1MASK3         0x2b34
-#define RM9000x2_OCD_INTP1SET3          0x2b38
-#define RM9000x2_OCD_INTP1CLEAR3        0x2b3c
-#define RM9000x2_OCD_INTP1STATUS4       0x2b40
-#define RM9000x2_OCD_INTP1MASK4         0x2b44
-#define RM9000x2_OCD_INTP1SET4          0x2b48
-#define RM9000x2_OCD_INTP1CLEAR4        0x2b4c
-#define RM9000x2_OCD_INTP1STATUS5       0x2b50
-#define RM9000x2_OCD_INTP1MASK5         0x2b54
-#define RM9000x2_OCD_INTP1SET5          0x2b58
-#define RM9000x2_OCD_INTP1CLEAR5        0x2b5c
-#define RM9000x2_OCD_INTP1STATUS6       0x2b60
-#define RM9000x2_OCD_INTP1MASK6         0x2b64
-#define RM9000x2_OCD_INTP1SET6          0x2b68
-#define RM9000x2_OCD_INTP1CLEAR6        0x2b6c
-#define RM9000x2_OCD_INTP1STATUS7       0x2b70
-#define RM9000x2_OCD_INTP1MASK7         0x2b74
-#define RM9000x2_OCD_INTP1SET7          0x2b78
-#define RM9000x2_OCD_INTP1CLEAR7        0x2b7c
-
-#define OCD_READ(reg)           (*(volatile unsigned int *)(ocd_base + (reg)))
-#define OCD_WRITE(reg, val)                                     \
-        do { *(volatile unsigned int *)(ocd_base + (reg)) = (val); } while (0)
-
-/*
- * Hypertransport specific macros
- */
-#define RM9K_WRITE(ofs, data)   *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs) = data
-#define RM9K_WRITE_8(ofs, data) *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs) = data
-#define RM9K_WRITE_16(ofs, data) *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs) = data
-
-#define RM9K_READ(ofs, val)     *(val) = *(volatile u_int32_t *)(RM9000x2_BASE_ADDR+ofs)
-#define RM9K_READ_8(ofs, val)   *(val) = *(volatile u8 *)(RM9000x2_BASE_ADDR+ofs)
-#define RM9K_READ_16(ofs, val)  *(val) = *(volatile u16 *)(RM9000x2_BASE_ADDR+ofs)
-
-#endif
diff --git a/include/asm-mips/tlb.h b/include/asm-mips/tlb.h
deleted file mode 100644
index 80d9dfcf1e88..000000000000
--- a/include/asm-mips/tlb.h
+++ /dev/null
@@ -1,23 +0,0 @@
-#ifndef __ASM_TLB_H
-#define __ASM_TLB_H
-
-/*
- * MIPS doesn't need any special per-pte or per-vma handling, except
- * we need to flush cache for area to be unmapped.
- */
-#define tlb_start_vma(tlb, vma)                                 \
-        do {                                                    \
-                if (!tlb->fullmm)                               \
-                        flush_cache_range(vma, vma->vm_start, vma->vm_end); \
-        }  while (0)
-#define tlb_end_vma(tlb, vma) do { } while (0)
-#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
-
-/*
- * .. because we flush the whole mm when it fills up.
- */
-#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
-
-#include <asm-generic/tlb.h>
-
-#endif /* __ASM_TLB_H */
diff --git a/include/asm-mips/tlbdebug.h b/include/asm-mips/tlbdebug.h
deleted file mode 100644
index bb8f5c29c3d9..000000000000
--- a/include/asm-mips/tlbdebug.h
+++ /dev/null
@@ -1,16 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002 by Ralf Baechle
- */
-#ifndef __ASM_TLBDEBUG_H
-#define __ASM_TLBDEBUG_H
-
-/*
- * TLB debugging functions:
- */
-extern void dump_tlb_all(void);
-
-#endif /* __ASM_TLBDEBUG_H */
diff --git a/include/asm-mips/tlbflush.h b/include/asm-mips/tlbflush.h
deleted file mode 100644
index 86b21de12e91..000000000000
--- a/include/asm-mips/tlbflush.h
+++ /dev/null
@@ -1,47 +0,0 @@
-#ifndef __ASM_TLBFLUSH_H
-#define __ASM_TLBFLUSH_H
-
-#include <linux/mm.h>
-
-/*
- * TLB flushing:
- *
- *  - flush_tlb_all() flushes all processes TLB entries
- *  - flush_tlb_mm(mm) flushes the specified mm context TLB entries
- *  - flush_tlb_page(vma, vmaddr) flushes one page
- *  - flush_tlb_range(vma, start, end) flushes a range of pages
- *  - flush_tlb_kernel_range(start, end) flushes a range of kernel pages
- */
-extern void local_flush_tlb_all(void);
-extern void local_flush_tlb_mm(struct mm_struct *mm);
-extern void local_flush_tlb_range(struct vm_area_struct *vma,
-        unsigned long start, unsigned long end);
-extern void local_flush_tlb_kernel_range(unsigned long start,
-        unsigned long end);
-extern void local_flush_tlb_page(struct vm_area_struct *vma,
-        unsigned long page);
-extern void local_flush_tlb_one(unsigned long vaddr);
-
-#ifdef CONFIG_SMP
-
-extern void flush_tlb_all(void);
-extern void flush_tlb_mm(struct mm_struct *);
-extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long,
-        unsigned long);
-extern void flush_tlb_kernel_range(unsigned long, unsigned long);
-extern void flush_tlb_page(struct vm_area_struct *, unsigned long);
-extern void flush_tlb_one(unsigned long vaddr);
-
-#else /* CONFIG_SMP */
-
-#define flush_tlb_all()                 local_flush_tlb_all()
-#define flush_tlb_mm(mm)                local_flush_tlb_mm(mm)
-#define flush_tlb_range(vma, vmaddr, end)       local_flush_tlb_range(vma, vmaddr, end)
-#define flush_tlb_kernel_range(vmaddr,end) \
-        local_flush_tlb_kernel_range(vmaddr, end)
-#define flush_tlb_page(vma, page)       local_flush_tlb_page(vma, page)
-#define flush_tlb_one(vaddr)            local_flush_tlb_one(vaddr)
-
-#endif /* CONFIG_SMP */
-
-#endif /* __ASM_TLBFLUSH_H */
diff --git a/include/asm-mips/topology.h b/include/asm-mips/topology.h
deleted file mode 100644
index 259145e07e97..000000000000
--- a/include/asm-mips/topology.h
+++ /dev/null
@@ -1,17 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 by Ralf Baechle
- */
-#ifndef __ASM_TOPOLOGY_H
-#define __ASM_TOPOLOGY_H
-
-#include <topology.h>
-
-#ifdef CONFIG_SMP
-#define smt_capable()   (smp_num_siblings > 1)
-#endif
-
-#endif /* __ASM_TOPOLOGY_H */
diff --git a/include/asm-mips/traps.h b/include/asm-mips/traps.h
deleted file mode 100644
index 90ff2f497c50..000000000000
--- a/include/asm-mips/traps.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- *      Trap handling definitions.
- *
- *      Copyright (C) 2002, 2003  Maciej W. Rozycki
- *
- *      This program is free software; you can redistribute it and/or
- *      modify it under the terms of the GNU General Public License
- *      as published by the Free Software Foundation; either version
- *      2 of the License, or (at your option) any later version.
- */
-#ifndef _ASM_TRAPS_H
-#define _ASM_TRAPS_H
-
-/*
- * Possible status responses for a board_be_handler backend.
- */
-#define MIPS_BE_DISCARD 0               /* return with no action */
-#define MIPS_BE_FIXUP   1               /* return to the fixup code */
-#define MIPS_BE_FATAL   2               /* treat as an unrecoverable error */
-
-extern void (*board_be_init)(void);
-extern int (*board_be_handler)(struct pt_regs *regs, int is_fixup);
-
-extern void (*board_nmi_handler_setup)(void);
-extern void (*board_ejtag_handler_setup)(void);
-extern void (*board_bind_eic_interrupt)(int irq, int regset);
-
-#endif /* _ASM_TRAPS_H */
diff --git a/include/asm-mips/txx9/generic.h b/include/asm-mips/txx9/generic.h
deleted file mode 100644
index 5b1ccf901c62..000000000000
--- a/include/asm-mips/txx9/generic.h
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * linux/include/asm-mips/txx9/generic.h
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9_GENERIC_H
-#define __ASM_TXX9_GENERIC_H
-
-#include <linux/init.h>
-#include <linux/ioport.h>       /* for struct resource */
-
-extern struct resource txx9_ce_res[];
-#define TXX9_CE(n)      (unsigned long)(txx9_ce_res[(n)].start)
-extern unsigned int txx9_pcode;
-extern char txx9_pcode_str[8];
-void txx9_reg_res_init(unsigned int pcode, unsigned long base,
-                       unsigned long size);
-
-extern unsigned int txx9_master_clock;
-extern unsigned int txx9_cpu_clock;
-extern unsigned int txx9_gbus_clock;
-#define TXX9_IMCLK      (txx9_gbus_clock / 2)
-
-extern int txx9_ccfg_toeon;
-struct uart_port;
-int early_serial_txx9_setup(struct uart_port *port);
-
-struct pci_dev;
-struct txx9_board_vec {
-        const char *system;
-        void (*prom_init)(void);
-        void (*mem_setup)(void);
-        void (*irq_setup)(void);
-        void (*time_init)(void);
-        void (*arch_init)(void);
-        void (*device_init)(void);
-#ifdef CONFIG_PCI
-        int (*pci_map_irq)(const struct pci_dev *dev, u8 slot, u8 pin);
-#endif
-};
-extern struct txx9_board_vec *txx9_board_vec;
-extern int (*txx9_irq_dispatch)(int pending);
-void prom_init_cmdline(void);
-char *prom_getcmdline(void);
-void txx9_wdt_init(unsigned long base);
-void txx9_spi_init(int busid, unsigned long base, int irq);
-void txx9_ethaddr_init(unsigned int id, unsigned char *ethaddr);
-void txx9_sio_init(unsigned long baseaddr, int irq,
-                   unsigned int line, unsigned int sclk, int nocts);
-void prom_putchar(char c);
-#ifdef CONFIG_EARLY_PRINTK
-extern void (*txx9_prom_putchar)(char c);
-void txx9_sio_putchar_init(unsigned long baseaddr);
-#else
-static inline void txx9_sio_putchar_init(unsigned long baseaddr)
-{
-}
-#endif
-
-#endif /* __ASM_TXX9_GENERIC_H */
diff --git a/include/asm-mips/txx9/jmr3927.h b/include/asm-mips/txx9/jmr3927.h
deleted file mode 100644
index a409c446bf18..000000000000
--- a/include/asm-mips/txx9/jmr3927.h
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Defines for the TJSYS JMR-TX3927
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- */
-#ifndef __ASM_TXX9_JMR3927_H
-#define __ASM_TXX9_JMR3927_H
-
-#include <asm/txx9/tx3927.h>
-#include <asm/addrspace.h>
-#include <asm/system.h>
-#include <asm/txx9irq.h>
-
-/* CS */
-#define JMR3927_ROMCE0  0x1fc00000      /* 4M */
-#define JMR3927_ROMCE1  0x1e000000      /* 4M */
-#define JMR3927_ROMCE2  0x14000000      /* 16M */
-#define JMR3927_ROMCE3  0x10000000      /* 64M */
-#define JMR3927_ROMCE5  0x1d000000      /* 4M */
-#define JMR3927_SDCS0   0x00000000      /* 32M */
-#define JMR3927_SDCS1   0x02000000      /* 32M */
-/* PCI Direct Mappings */
-
-#define JMR3927_PCIMEM  0x08000000
-#define JMR3927_PCIMEM_SIZE     0x08000000      /* 128M */
-#define JMR3927_PCIIO   0x15000000
-#define JMR3927_PCIIO_SIZE      0x01000000      /* 16M */
-
-#define JMR3927_SDRAM_SIZE      0x02000000      /* 32M */
-#define JMR3927_PORT_BASE       KSEG1
-
-/* Address map (virtual address) */
-#define JMR3927_ROM0_BASE       (KSEG1 + JMR3927_ROMCE0)
-#define JMR3927_ROM1_BASE       (KSEG1 + JMR3927_ROMCE1)
-#define JMR3927_IOC_BASE        (KSEG1 + JMR3927_ROMCE2)
-#define JMR3927_PCIMEM_BASE     (KSEG1 + JMR3927_PCIMEM)
-#define JMR3927_PCIIO_BASE      (KSEG1 + JMR3927_PCIIO)
-
-#define JMR3927_IOC_REV_ADDR    (JMR3927_IOC_BASE + 0x00000000)
-#define JMR3927_IOC_NVRAMB_ADDR (JMR3927_IOC_BASE + 0x00010000)
-#define JMR3927_IOC_LED_ADDR    (JMR3927_IOC_BASE + 0x00020000)
-#define JMR3927_IOC_DIPSW_ADDR  (JMR3927_IOC_BASE + 0x00030000)
-#define JMR3927_IOC_BREV_ADDR   (JMR3927_IOC_BASE + 0x00040000)
-#define JMR3927_IOC_DTR_ADDR    (JMR3927_IOC_BASE + 0x00050000)
-#define JMR3927_IOC_INTS1_ADDR  (JMR3927_IOC_BASE + 0x00080000)
-#define JMR3927_IOC_INTS2_ADDR  (JMR3927_IOC_BASE + 0x00090000)
-#define JMR3927_IOC_INTM_ADDR   (JMR3927_IOC_BASE + 0x000a0000)
-#define JMR3927_IOC_INTP_ADDR   (JMR3927_IOC_BASE + 0x000b0000)
-#define JMR3927_IOC_RESET_ADDR  (JMR3927_IOC_BASE + 0x000f0000)
-
-/* Flash ROM */
-#define JMR3927_FLASH_BASE      (JMR3927_ROM0_BASE)
-#define JMR3927_FLASH_SIZE      0x00400000
-
-/* bits for IOC_REV/IOC_BREV (high byte) */
-#define JMR3927_IDT_MASK        0xfc
-#define JMR3927_REV_MASK        0x03
-#define JMR3927_IOC_IDT         0xe0
-
-/* bits for IOC_INTS1/IOC_INTS2/IOC_INTM/IOC_INTP (high byte) */
-#define JMR3927_IOC_INTB_PCIA   0
-#define JMR3927_IOC_INTB_PCIB   1
-#define JMR3927_IOC_INTB_PCIC   2
-#define JMR3927_IOC_INTB_PCID   3
-#define JMR3927_IOC_INTB_MODEM  4
-#define JMR3927_IOC_INTB_INT6   5
-#define JMR3927_IOC_INTB_INT7   6
-#define JMR3927_IOC_INTB_SOFT   7
-#define JMR3927_IOC_INTF_PCIA   (1 << JMR3927_IOC_INTF_PCIA)
-#define JMR3927_IOC_INTF_PCIB   (1 << JMR3927_IOC_INTB_PCIB)
-#define JMR3927_IOC_INTF_PCIC   (1 << JMR3927_IOC_INTB_PCIC)
-#define JMR3927_IOC_INTF_PCID   (1 << JMR3927_IOC_INTB_PCID)
-#define JMR3927_IOC_INTF_MODEM  (1 << JMR3927_IOC_INTB_MODEM)
-#define JMR3927_IOC_INTF_INT6   (1 << JMR3927_IOC_INTB_INT6)
-#define JMR3927_IOC_INTF_INT7   (1 << JMR3927_IOC_INTB_INT7)
-#define JMR3927_IOC_INTF_SOFT   (1 << JMR3927_IOC_INTB_SOFT)
-
-/* bits for IOC_RESET (high byte) */
-#define JMR3927_IOC_RESET_CPU   1
-#define JMR3927_IOC_RESET_PCI   2
-
-#if defined(__BIG_ENDIAN)
-#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)(a)) = (d))
-#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)(a))
-#elif defined(__LITTLE_ENDIAN)
-#define jmr3927_ioc_reg_out(d, a)       ((*(volatile unsigned char *)((a)^1)) = (d))
-#define jmr3927_ioc_reg_in(a)           (*(volatile unsigned char *)((a)^1))
-#else
-#error "No Endian"
-#endif
-
-/* LED macro */
-#define jmr3927_led_set(n/*0-16*/)      jmr3927_ioc_reg_out(~(n), JMR3927_IOC_LED_ADDR)
-
-#define jmr3927_led_and_set(n/*0-16*/)  jmr3927_ioc_reg_out((~(n)) & jmr3927_ioc_reg_in(JMR3927_IOC_LED_ADDR), JMR3927_IOC_LED_ADDR)
-
-/* DIPSW4 macro */
-#define jmr3927_dipsw1()        (gpio_get_value(11) == 0)
-#define jmr3927_dipsw2()        (gpio_get_value(10) == 0)
-#define jmr3927_dipsw3()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 2) == 0)
-#define jmr3927_dipsw4()        ((jmr3927_ioc_reg_in(JMR3927_IOC_DIPSW_ADDR) & 1) == 0)
-
-/*
- * IRQ mappings
- */
-
-/* These are the virtual IRQ numbers, we divide all IRQ's into
- * 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an JMR machine.  Add new 'spaces' as new
- * IRQ hardware is supported.
- */
-#define JMR3927_NR_IRQ_IRC      16      /* On-Chip IRC */
-#define JMR3927_NR_IRQ_IOC      8       /* PCI/MODEM/INT[6:7] */
-
-#define JMR3927_IRQ_IRC TXX9_IRQ_BASE
-#define JMR3927_IRQ_IOC (JMR3927_IRQ_IRC + JMR3927_NR_IRQ_IRC)
-#define JMR3927_IRQ_END (JMR3927_IRQ_IOC + JMR3927_NR_IRQ_IOC)
-
-#define JMR3927_IRQ_IRC_INT0    (JMR3927_IRQ_IRC + TX3927_IR_INT0)
-#define JMR3927_IRQ_IRC_INT1    (JMR3927_IRQ_IRC + TX3927_IR_INT1)
-#define JMR3927_IRQ_IRC_INT2    (JMR3927_IRQ_IRC + TX3927_IR_INT2)
-#define JMR3927_IRQ_IRC_INT3    (JMR3927_IRQ_IRC + TX3927_IR_INT3)
-#define JMR3927_IRQ_IRC_INT4    (JMR3927_IRQ_IRC + TX3927_IR_INT4)
-#define JMR3927_IRQ_IRC_INT5    (JMR3927_IRQ_IRC + TX3927_IR_INT5)
-#define JMR3927_IRQ_IRC_SIO0    (JMR3927_IRQ_IRC + TX3927_IR_SIO0)
-#define JMR3927_IRQ_IRC_SIO1    (JMR3927_IRQ_IRC + TX3927_IR_SIO1)
-#define JMR3927_IRQ_IRC_SIO(ch) (JMR3927_IRQ_IRC + TX3927_IR_SIO(ch))
-#define JMR3927_IRQ_IRC_DMA     (JMR3927_IRQ_IRC + TX3927_IR_DMA)
-#define JMR3927_IRQ_IRC_PIO     (JMR3927_IRQ_IRC + TX3927_IR_PIO)
-#define JMR3927_IRQ_IRC_PCI     (JMR3927_IRQ_IRC + TX3927_IR_PCI)
-#define JMR3927_IRQ_IRC_TMR(ch) (JMR3927_IRQ_IRC + TX3927_IR_TMR(ch))
-#define JMR3927_IRQ_IOC_PCIA    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIA)
-#define JMR3927_IRQ_IOC_PCIB    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIB)
-#define JMR3927_IRQ_IOC_PCIC    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCIC)
-#define JMR3927_IRQ_IOC_PCID    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_PCID)
-#define JMR3927_IRQ_IOC_MODEM   (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_MODEM)
-#define JMR3927_IRQ_IOC_INT6    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT6)
-#define JMR3927_IRQ_IOC_INT7    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_INT7)
-#define JMR3927_IRQ_IOC_SOFT    (JMR3927_IRQ_IOC + JMR3927_IOC_INTB_SOFT)
-
-/* IOC (PCI, MODEM) */
-#define JMR3927_IRQ_IOCINT      JMR3927_IRQ_IRC_INT1
-/* TC35815 100M Ether (JMR-TX3912:JPW4:2-3 Short) */
-#define JMR3927_IRQ_ETHER0      JMR3927_IRQ_IRC_INT3
-
-/* Clocks */
-#define JMR3927_CORECLK 132710400       /* 132.7MHz */
-
-/*
- * TX3927 Pin Configuration:
- *
- *      PCFG bits               Avail                   Dead
- *      SELSIO[1:0]:11          RXD[1:0], TXD[1:0]      PIO[6:3]
- *      SELSIOC[0]:1            CTS[0], RTS[0]          INT[5:4]
- *      SELSIOC[1]:0,SELDSF:0,  GSDAO[0],GPCST[3]       CTS[1], RTS[1],DSF,
- *        GDBGE*                                          PIO[2:1]
- *      SELDMA[2]:1             DMAREQ[2],DMAACK[2]     PIO[13:12]
- *      SELTMR[2:0]:000                                 TIMER[1:0]
- *      SELCS:0,SELDMA[1]:0     PIO[11;10]              SDCS_CE[7:6],
- *                                                        DMAREQ[1],DMAACK[1]
- *      SELDMA[0]:1             DMAREQ[0],DMAACK[0]     PIO[9:8]
- *      SELDMA[3]:1             DMAREQ[3],DMAACK[3]     PIO[15:14]
- *      SELDONE:1               DMADONE                 PIO[7]
- *
- * Usable pins are:
- *      RXD[1;0],TXD[1:0],CTS[0],RTS[0],
- *      DMAREQ[0,2,3],DMAACK[0,2,3],DMADONE,PIO[0,10,11]
- *      INT[3:0]
- */
-
-void jmr3927_prom_init(void);
-void jmr3927_irq_setup(void);
-struct pci_dev;
-int jmr3927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_JMR3927_H */
diff --git a/include/asm-mips/txx9/pci.h b/include/asm-mips/txx9/pci.h
deleted file mode 100644
index 3d32529060aa..000000000000
--- a/include/asm-mips/txx9/pci.h
+++ /dev/null
@@ -1,39 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9_PCI_H
-#define __ASM_TXX9_PCI_H
-
-#include <linux/pci.h>
-
-extern struct pci_controller txx9_primary_pcic;
-struct pci_controller *
-txx9_alloc_pci_controller(struct pci_controller *pcic,
-                          unsigned long mem_base, unsigned long mem_size,
-                          unsigned long io_base, unsigned long io_size);
-
-int txx9_pci66_check(struct pci_controller *hose, int top_bus,
-                        int current_bus);
-extern int txx9_pci_mem_high __initdata;
-
-extern int txx9_pci_option;
-#define TXX9_PCI_OPT_PICMG      0x0002
-#define TXX9_PCI_OPT_CLK_33     0x0008
-#define TXX9_PCI_OPT_CLK_66     0x0010
-#define TXX9_PCI_OPT_CLK_MASK   \
-        (TXX9_PCI_OPT_CLK_33 | TXX9_PCI_OPT_CLK_66)
-#define TXX9_PCI_OPT_CLK_AUTO   TXX9_PCI_OPT_CLK_MASK
-
-enum txx9_pci_err_action {
-        TXX9_PCI_ERR_REPORT,
-        TXX9_PCI_ERR_IGNORE,
-        TXX9_PCI_ERR_PANIC,
-};
-extern enum txx9_pci_err_action txx9_pci_err_action;
-
-extern char * (*txx9_board_pcibios_setup)(char *str);
-char *txx9_pcibios_setup(char *str);
-
-#endif /* __ASM_TXX9_PCI_H */
diff --git a/include/asm-mips/txx9/rbtx4927.h b/include/asm-mips/txx9/rbtx4927.h
deleted file mode 100644
index 6fcec912c143..000000000000
--- a/include/asm-mips/txx9/rbtx4927.h
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2001-2002 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TXX9_RBTX4927_H
-#define __ASM_TXX9_RBTX4927_H
-
-#include <asm/txx9/tx4927.h>
-
-#define RBTX4927_PCIMEM         0x08000000
-#define RBTX4927_PCIMEM_SIZE    0x08000000
-#define RBTX4927_PCIIO          0x16000000
-#define RBTX4927_PCIIO_SIZE     0x01000000
-
-#define RBTX4927_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
-#define RBTX4927_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002006)
-#define RBTX4927_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x0000f000)
-#define RBTX4927_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000f002)
-#define RBTX4927_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x0000f006)
-#define RBTX4927_BRAMRTC_BASE   (IO_BASE + TXX9_CE(2) + 0x00010000)
-#define RBTX4927_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
-
-/* Ethernet port address */
-#define RBTX4927_ETHER_ADDR     (RBTX4927_ETHER_BASE + 0x280)
-
-#define rbtx4927_imask_addr     ((__u8 __iomem *)RBTX4927_IMASK_ADDR)
-#define rbtx4927_imstat_addr    ((__u8 __iomem *)RBTX4927_IMSTAT_ADDR)
-#define rbtx4927_softreset_addr ((__u8 __iomem *)RBTX4927_SOFTRESET_ADDR)
-#define rbtx4927_softresetlock_addr     \
-                                ((__u8 __iomem *)RBTX4927_SOFTRESETLOCK_ADDR)
-#define rbtx4927_pcireset_addr  ((__u8 __iomem *)RBTX4927_PCIRESET_ADDR)
-
-/* bits for ISTAT/IMASK/IMSTAT */
-#define RBTX4927_INTB_PCID      0
-#define RBTX4927_INTB_PCIC      1
-#define RBTX4927_INTB_PCIB      2
-#define RBTX4927_INTB_PCIA      3
-#define RBTX4927_INTF_PCID      (1 << RBTX4927_INTB_PCID)
-#define RBTX4927_INTF_PCIC      (1 << RBTX4927_INTB_PCIC)
-#define RBTX4927_INTF_PCIB      (1 << RBTX4927_INTB_PCIB)
-#define RBTX4927_INTF_PCIA      (1 << RBTX4927_INTB_PCIA)
-
-#define RBTX4927_NR_IRQ_IOC     8       /* IOC */
-
-#define RBTX4927_IRQ_IOC        (TXX9_IRQ_BASE + TX4927_NUM_IR)
-#define RBTX4927_IRQ_IOC_PCID   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCID)
-#define RBTX4927_IRQ_IOC_PCIC   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIC)
-#define RBTX4927_IRQ_IOC_PCIB   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIB)
-#define RBTX4927_IRQ_IOC_PCIA   (RBTX4927_IRQ_IOC + RBTX4927_INTB_PCIA)
-
-#define RBTX4927_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4927_IR_INT(1))
-
-#ifdef CONFIG_PCI
-#define RBTX4927_ISA_IO_OFFSET RBTX4927_PCIIO
-#else
-#define RBTX4927_ISA_IO_OFFSET 0
-#endif
-
-#define RBTX4927_RTL_8019_BASE (RBTX4927_ETHER_ADDR - mips_io_port_base)
-#define RBTX4927_RTL_8019_IRQ  (TXX9_IRQ_BASE + TX4927_IR_INT(3))
-
-void rbtx4927_prom_init(void);
-void rbtx4927_irq_setup(void);
-struct pci_dev;
-int rbtx4927_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_RBTX4927_H */
diff --git a/include/asm-mips/txx9/rbtx4938.h b/include/asm-mips/txx9/rbtx4938.h
deleted file mode 100644
index 9f0441a28126..000000000000
--- a/include/asm-mips/txx9/rbtx4938.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/*
- * Definitions for TX4937/TX4938
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_RBTX4938_H
-#define __ASM_TXX9_RBTX4938_H
-
-#include <asm/addrspace.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/tx4938.h>
-
-/* Address map */
-#define RBTX4938_FPGA_REG_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000000)
-#define RBTX4938_FPGA_REV_ADDR  (IO_BASE + TXX9_CE(2) + 0x00000002)
-#define RBTX4938_CONFIG1_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000004)
-#define RBTX4938_CONFIG2_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000006)
-#define RBTX4938_CONFIG3_ADDR   (IO_BASE + TXX9_CE(2) + 0x00000008)
-#define RBTX4938_LED_ADDR       (IO_BASE + TXX9_CE(2) + 0x00001000)
-#define RBTX4938_DIPSW_ADDR     (IO_BASE + TXX9_CE(2) + 0x00001002)
-#define RBTX4938_BDIPSW_ADDR    (IO_BASE + TXX9_CE(2) + 0x00001004)
-#define RBTX4938_IMASK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002000)
-#define RBTX4938_IMASK2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002002)
-#define RBTX4938_INTPOL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002004)
-#define RBTX4938_ISTAT_ADDR     (IO_BASE + TXX9_CE(2) + 0x00002006)
-#define RBTX4938_ISTAT2_ADDR    (IO_BASE + TXX9_CE(2) + 0x00002008)
-#define RBTX4938_IMSTAT_ADDR    (IO_BASE + TXX9_CE(2) + 0x0000200a)
-#define RBTX4938_IMSTAT2_ADDR   (IO_BASE + TXX9_CE(2) + 0x0000200c)
-#define RBTX4938_SOFTINT_ADDR   (IO_BASE + TXX9_CE(2) + 0x00003000)
-#define RBTX4938_PIOSEL_ADDR    (IO_BASE + TXX9_CE(2) + 0x00005000)
-#define RBTX4938_SPICS_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005002)
-#define RBTX4938_SFPWR_ADDR     (IO_BASE + TXX9_CE(2) + 0x00005008)
-#define RBTX4938_SFVOL_ADDR     (IO_BASE + TXX9_CE(2) + 0x0000500a)
-#define RBTX4938_SOFTRESET_ADDR (IO_BASE + TXX9_CE(2) + 0x00007000)
-#define RBTX4938_SOFTRESETLOCK_ADDR     (IO_BASE + TXX9_CE(2) + 0x00007002)
-#define RBTX4938_PCIRESET_ADDR  (IO_BASE + TXX9_CE(2) + 0x00007004)
-#define RBTX4938_ETHER_BASE     (IO_BASE + TXX9_CE(2) + 0x00020000)
-
-/* Ethernet port address (Jumperless Mode (W12:Open)) */
-#define RBTX4938_ETHER_ADDR     (RBTX4938_ETHER_BASE + 0x280)
-
-/* bits for ISTAT/IMASK/IMSTAT */
-#define RBTX4938_INTB_PCID      0
-#define RBTX4938_INTB_PCIC      1
-#define RBTX4938_INTB_PCIB      2
-#define RBTX4938_INTB_PCIA      3
-#define RBTX4938_INTB_RTC       4
-#define RBTX4938_INTB_ATA       5
-#define RBTX4938_INTB_MODEM     6
-#define RBTX4938_INTB_SWINT     7
-#define RBTX4938_INTF_PCID      (1 << RBTX4938_INTB_PCID)
-#define RBTX4938_INTF_PCIC      (1 << RBTX4938_INTB_PCIC)
-#define RBTX4938_INTF_PCIB      (1 << RBTX4938_INTB_PCIB)
-#define RBTX4938_INTF_PCIA      (1 << RBTX4938_INTB_PCIA)
-#define RBTX4938_INTF_RTC       (1 << RBTX4938_INTB_RTC)
-#define RBTX4938_INTF_ATA       (1 << RBTX4938_INTB_ATA)
-#define RBTX4938_INTF_MODEM     (1 << RBTX4938_INTB_MODEM)
-#define RBTX4938_INTF_SWINT     (1 << RBTX4938_INTB_SWINT)
-
-#define rbtx4938_fpga_rev_addr  ((__u8 __iomem *)RBTX4938_FPGA_REV_ADDR)
-#define rbtx4938_led_addr       ((__u8 __iomem *)RBTX4938_LED_ADDR)
-#define rbtx4938_dipsw_addr     ((__u8 __iomem *)RBTX4938_DIPSW_ADDR)
-#define rbtx4938_bdipsw_addr    ((__u8 __iomem *)RBTX4938_BDIPSW_ADDR)
-#define rbtx4938_imask_addr     ((__u8 __iomem *)RBTX4938_IMASK_ADDR)
-#define rbtx4938_imask2_addr    ((__u8 __iomem *)RBTX4938_IMASK2_ADDR)
-#define rbtx4938_intpol_addr    ((__u8 __iomem *)RBTX4938_INTPOL_ADDR)
-#define rbtx4938_istat_addr     ((__u8 __iomem *)RBTX4938_ISTAT_ADDR)
-#define rbtx4938_istat2_addr    ((__u8 __iomem *)RBTX4938_ISTAT2_ADDR)
-#define rbtx4938_imstat_addr    ((__u8 __iomem *)RBTX4938_IMSTAT_ADDR)
-#define rbtx4938_imstat2_addr   ((__u8 __iomem *)RBTX4938_IMSTAT2_ADDR)
-#define rbtx4938_softint_addr   ((__u8 __iomem *)RBTX4938_SOFTINT_ADDR)
-#define rbtx4938_piosel_addr    ((__u8 __iomem *)RBTX4938_PIOSEL_ADDR)
-#define rbtx4938_spics_addr     ((__u8 __iomem *)RBTX4938_SPICS_ADDR)
-#define rbtx4938_sfpwr_addr     ((__u8 __iomem *)RBTX4938_SFPWR_ADDR)
-#define rbtx4938_sfvol_addr     ((__u8 __iomem *)RBTX4938_SFVOL_ADDR)
-#define rbtx4938_softreset_addr ((__u8 __iomem *)RBTX4938_SOFTRESET_ADDR)
-#define rbtx4938_softresetlock_addr     \
-                                ((__u8 __iomem *)RBTX4938_SOFTRESETLOCK_ADDR)
-#define rbtx4938_pcireset_addr  ((__u8 __iomem *)RBTX4938_PCIRESET_ADDR)
-
-/*
- * IRQ mappings
- */
-
-#define RBTX4938_SOFT_INT0      0       /* not used */
-#define RBTX4938_SOFT_INT1      1       /* not used */
-#define RBTX4938_IRC_INT        2
-#define RBTX4938_TIMER_INT      7
-
-/* These are the virtual IRQ numbers, we divide all IRQ's into
- * 'spaces', the 'space' determines where and how to enable/disable
- * that particular IRQ on an RBTX4938 machine.  Add new 'spaces' as new
- * IRQ hardware is supported.
- */
-#define RBTX4938_NR_IRQ_IOC     8
-
-#define RBTX4938_IRQ_IRC        TXX9_IRQ_BASE
-#define RBTX4938_IRQ_IOC        (TXX9_IRQ_BASE + TX4938_NUM_IR)
-#define RBTX4938_IRQ_END        (RBTX4938_IRQ_IOC + RBTX4938_NR_IRQ_IOC)
-
-#define RBTX4938_IRQ_IRC_ECCERR (RBTX4938_IRQ_IRC + TX4938_IR_ECCERR)
-#define RBTX4938_IRQ_IRC_WTOERR (RBTX4938_IRQ_IRC + TX4938_IR_WTOERR)
-#define RBTX4938_IRQ_IRC_INT(n) (RBTX4938_IRQ_IRC + TX4938_IR_INT(n))
-#define RBTX4938_IRQ_IRC_SIO(n) (RBTX4938_IRQ_IRC + TX4938_IR_SIO(n))
-#define RBTX4938_IRQ_IRC_DMA(ch, n)     (RBTX4938_IRQ_IRC + TX4938_IR_DMA(ch, n))
-#define RBTX4938_IRQ_IRC_PIO    (RBTX4938_IRQ_IRC + TX4938_IR_PIO)
-#define RBTX4938_IRQ_IRC_PDMAC  (RBTX4938_IRQ_IRC + TX4938_IR_PDMAC)
-#define RBTX4938_IRQ_IRC_PCIC   (RBTX4938_IRQ_IRC + TX4938_IR_PCIC)
-#define RBTX4938_IRQ_IRC_TMR(n) (RBTX4938_IRQ_IRC + TX4938_IR_TMR(n))
-#define RBTX4938_IRQ_IRC_NDFMC  (RBTX4938_IRQ_IRC + TX4938_IR_NDFMC)
-#define RBTX4938_IRQ_IRC_PCIERR (RBTX4938_IRQ_IRC + TX4938_IR_PCIERR)
-#define RBTX4938_IRQ_IRC_PCIPME (RBTX4938_IRQ_IRC + TX4938_IR_PCIPME)
-#define RBTX4938_IRQ_IRC_ACLC   (RBTX4938_IRQ_IRC + TX4938_IR_ACLC)
-#define RBTX4938_IRQ_IRC_ACLCPME        (RBTX4938_IRQ_IRC + TX4938_IR_ACLCPME)
-#define RBTX4938_IRQ_IRC_PCIC1  (RBTX4938_IRQ_IRC + TX4938_IR_PCIC1)
-#define RBTX4938_IRQ_IRC_SPI    (RBTX4938_IRQ_IRC + TX4938_IR_SPI)
-#define RBTX4938_IRQ_IOC_PCID   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCID)
-#define RBTX4938_IRQ_IOC_PCIC   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIC)
-#define RBTX4938_IRQ_IOC_PCIB   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIB)
-#define RBTX4938_IRQ_IOC_PCIA   (RBTX4938_IRQ_IOC + RBTX4938_INTB_PCIA)
-#define RBTX4938_IRQ_IOC_RTC    (RBTX4938_IRQ_IOC + RBTX4938_INTB_RTC)
-#define RBTX4938_IRQ_IOC_ATA    (RBTX4938_IRQ_IOC + RBTX4938_INTB_ATA)
-#define RBTX4938_IRQ_IOC_MODEM  (RBTX4938_IRQ_IOC + RBTX4938_INTB_MODEM)
-#define RBTX4938_IRQ_IOC_SWINT  (RBTX4938_IRQ_IOC + RBTX4938_INTB_SWINT)
-
-
-/* IOC (PCI, etc) */
-#define RBTX4938_IRQ_IOCINT     (TXX9_IRQ_BASE + TX4938_IR_INT(0))
-/* Onboard 10M Ether */
-#define RBTX4938_IRQ_ETHER      (TXX9_IRQ_BASE + TX4938_IR_INT(1))
-
-#define RBTX4938_RTL_8019_BASE (RBTX4938_ETHER_ADDR - mips_io_port_base)
-#define RBTX4938_RTL_8019_IRQ  (RBTX4938_IRQ_ETHER)
-
-void rbtx4938_prom_init(void);
-void rbtx4938_irq_setup(void);
-struct pci_dev;
-int rbtx4938_pci_map_irq(const struct pci_dev *dev, u8 slot, u8 pin);
-
-#endif /* __ASM_TXX9_RBTX4938_H */
diff --git a/include/asm-mips/txx9/smsc_fdc37m81x.h b/include/asm-mips/txx9/smsc_fdc37m81x.h
deleted file mode 100644
index 02e161d0755d..000000000000
--- a/include/asm-mips/txx9/smsc_fdc37m81x.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Interface for smsc fdc48m81x Super IO chip
- *
- * Author: MontaVista Software, Inc. source@mvista.com
- *
- * 2001-2003 (c) MontaVista Software, Inc. This file is licensed under
- * the terms of the GNU General Public License version 2. This program
- * is licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Copyright (C) 2004 MontaVista Software Inc.
- * Manish Lachwani, mlachwani@mvista.com
- */
-
-#ifndef _SMSC_FDC37M81X_H_
-#define _SMSC_FDC37M81X_H_
-
-/* Common Registers */
-#define SMSC_FDC37M81X_CONFIG_INDEX  0x00
-#define SMSC_FDC37M81X_CONFIG_DATA   0x01
-#define SMSC_FDC37M81X_CONF          0x02
-#define SMSC_FDC37M81X_INDEX         0x03
-#define SMSC_FDC37M81X_DNUM          0x07
-#define SMSC_FDC37M81X_DID           0x20
-#define SMSC_FDC37M81X_DREV          0x21
-#define SMSC_FDC37M81X_PCNT          0x22
-#define SMSC_FDC37M81X_PMGT          0x23
-#define SMSC_FDC37M81X_OSC           0x24
-#define SMSC_FDC37M81X_CONFPA0       0x26
-#define SMSC_FDC37M81X_CONFPA1       0x27
-#define SMSC_FDC37M81X_TEST4         0x2B
-#define SMSC_FDC37M81X_TEST5         0x2C
-#define SMSC_FDC37M81X_TEST1         0x2D
-#define SMSC_FDC37M81X_TEST2         0x2E
-#define SMSC_FDC37M81X_TEST3         0x2F
-
-/* Logical device numbers */
-#define SMSC_FDC37M81X_FDD           0x00
-#define SMSC_FDC37M81X_PARALLEL      0x03
-#define SMSC_FDC37M81X_SERIAL1       0x04
-#define SMSC_FDC37M81X_SERIAL2       0x05
-#define SMSC_FDC37M81X_KBD           0x07
-#define SMSC_FDC37M81X_AUXIO         0x08
-#define SMSC_FDC37M81X_NONE          0xff
-
-/* Logical device Config Registers */
-#define SMSC_FDC37M81X_ACTIVE        0x30
-#define SMSC_FDC37M81X_BASEADDR0     0x60
-#define SMSC_FDC37M81X_BASEADDR1     0x61
-#define SMSC_FDC37M81X_INT           0x70
-#define SMSC_FDC37M81X_INT2          0x72
-#define SMSC_FDC37M81X_LDCR_F0       0xF0
-
-/* Chip Config Values */
-#define SMSC_FDC37M81X_CONFIG_ENTER  0x55
-#define SMSC_FDC37M81X_CONFIG_EXIT   0xaa
-#define SMSC_FDC37M81X_CHIP_ID       0x4d
-
-unsigned long smsc_fdc37m81x_init(unsigned long port);
-
-void smsc_fdc37m81x_config_beg(void);
-
-void smsc_fdc37m81x_config_end(void);
-
-void smsc_fdc37m81x_config_set(u8 reg, u8 val);
-
-#endif
diff --git a/include/asm-mips/txx9/spi.h b/include/asm-mips/txx9/spi.h
deleted file mode 100644
index ddfb2a0dc432..000000000000
--- a/include/asm-mips/txx9/spi.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/*
- * Definitions for TX4937/TX4938 SPI
- *
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_SPI_H
-#define __ASM_TXX9_SPI_H
-
-extern int spi_eeprom_register(int chipid);
-extern int spi_eeprom_read(int chipid, int address, unsigned char *buf, int len);
-
-#endif /* __ASM_TXX9_SPI_H */
diff --git a/include/asm-mips/txx9/tx3927.h b/include/asm-mips/txx9/tx3927.h
deleted file mode 100644
index 587deb9592d2..000000000000
--- a/include/asm-mips/txx9/tx3927.h
+++ /dev/null
@@ -1,339 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2000 Toshiba Corporation
- */
-#ifndef __ASM_TXX9_TX3927_H
-#define __ASM_TXX9_TX3927_H
-
-#define TX3927_REG_BASE 0xfffe0000UL
-#define TX3927_REG_SIZE 0x00010000
-#define TX3927_SDRAMC_REG       (TX3927_REG_BASE + 0x8000)
-#define TX3927_ROMC_REG         (TX3927_REG_BASE + 0x9000)
-#define TX3927_DMA_REG          (TX3927_REG_BASE + 0xb000)
-#define TX3927_IRC_REG          (TX3927_REG_BASE + 0xc000)
-#define TX3927_PCIC_REG         (TX3927_REG_BASE + 0xd000)
-#define TX3927_CCFG_REG         (TX3927_REG_BASE + 0xe000)
-#define TX3927_NR_TMR   3
-#define TX3927_TMR_REG(ch)      (TX3927_REG_BASE + 0xf000 + (ch) * 0x100)
-#define TX3927_NR_SIO   2
-#define TX3927_SIO_REG(ch)      (TX3927_REG_BASE + 0xf300 + (ch) * 0x100)
-#define TX3927_PIO_REG          (TX3927_REG_BASE + 0xf500)
-
-struct tx3927_sdramc_reg {
-        volatile unsigned long cr[8];
-        volatile unsigned long tr[3];
-        volatile unsigned long cmd;
-        volatile unsigned long smrs[2];
-};
-
-struct tx3927_romc_reg {
-        volatile unsigned long cr[8];
-};
-
-struct tx3927_dma_reg {
-        struct tx3927_dma_ch_reg {
-                volatile unsigned long cha;
-                volatile unsigned long sar;
-                volatile unsigned long dar;
-                volatile unsigned long cntr;
-                volatile unsigned long sair;
-                volatile unsigned long dair;
-                volatile unsigned long ccr;
-                volatile unsigned long csr;
-        } ch[4];
-        volatile unsigned long dbr[8];
-        volatile unsigned long tdhr;
-        volatile unsigned long mcr;
-        volatile unsigned long unused0;
-};
-
-#include <asm/byteorder.h>
-
-#ifdef __BIG_ENDIAN
-#define endian_def_s2(e1, e2)   \
-        volatile unsigned short e1, e2
-#define endian_def_sb2(e1, e2, e3)      \
-        volatile unsigned short e1;volatile unsigned char e2, e3
-#define endian_def_b2s(e1, e2, e3)      \
-        volatile unsigned char e1, e2;volatile unsigned short e3
-#define endian_def_b4(e1, e2, e3, e4)   \
-        volatile unsigned char e1, e2, e3, e4
-#else
-#define endian_def_s2(e1, e2)   \
-        volatile unsigned short e2, e1
-#define endian_def_sb2(e1, e2, e3)      \
-        volatile unsigned char e3, e2;volatile unsigned short e1
-#define endian_def_b2s(e1, e2, e3)      \
-        volatile unsigned short e3;volatile unsigned char e2, e1
-#define endian_def_b4(e1, e2, e3, e4)   \
-        volatile unsigned char e4, e3, e2, e1
-#endif
-
-struct tx3927_pcic_reg {
-        endian_def_s2(did, vid);
-        endian_def_s2(pcistat, pcicmd);
-        endian_def_b4(cc, scc, rpli, rid);
-        endian_def_b4(unused0, ht, mlt, cls);
-        volatile unsigned long ioba;            /* +10 */
-        volatile unsigned long mba;
-        volatile unsigned long unused1[5];
-        endian_def_s2(svid, ssvid);
-        volatile unsigned long unused2;         /* +30 */
-        endian_def_sb2(unused3, unused4, capptr);
-        volatile unsigned long unused5;
-        endian_def_b4(ml, mg, ip, il);
-        volatile unsigned long unused6;         /* +40 */
-        volatile unsigned long istat;
-        volatile unsigned long iim;
-        volatile unsigned long rrt;
-        volatile unsigned long unused7[3];              /* +50 */
-        volatile unsigned long ipbmma;
-        volatile unsigned long ipbioma;         /* +60 */
-        volatile unsigned long ilbmma;
-        volatile unsigned long ilbioma;
-        volatile unsigned long unused8[9];
-        volatile unsigned long tc;              /* +90 */
-        volatile unsigned long tstat;
-        volatile unsigned long tim;
-        volatile unsigned long tccmd;
-        volatile unsigned long pcirrt;          /* +a0 */
-        volatile unsigned long pcirrt_cmd;
-        volatile unsigned long pcirrdt;
-        volatile unsigned long unused9[3];
-        volatile unsigned long tlboap;
-        volatile unsigned long tlbiap;
-        volatile unsigned long tlbmma;          /* +c0 */
-        volatile unsigned long tlbioma;
-        volatile unsigned long sc_msg;
-        volatile unsigned long sc_be;
-        volatile unsigned long tbl;             /* +d0 */
-        volatile unsigned long unused10[3];
-        volatile unsigned long pwmng;           /* +e0 */
-        volatile unsigned long pwmngs;
-        volatile unsigned long unused11[6];
-        volatile unsigned long req_trace;               /* +100 */
-        volatile unsigned long pbapmc;
-        volatile unsigned long pbapms;
-        volatile unsigned long pbapmim;
-        volatile unsigned long bm;              /* +110 */
-        volatile unsigned long cpcibrs;
-        volatile unsigned long cpcibgs;
-        volatile unsigned long pbacs;
-        volatile unsigned long iobas;           /* +120 */
-        volatile unsigned long mbas;
-        volatile unsigned long lbc;
-        volatile unsigned long lbstat;
-        volatile unsigned long lbim;            /* +130 */
-        volatile unsigned long pcistatim;
-        volatile unsigned long ica;
-        volatile unsigned long icd;
-        volatile unsigned long iiadp;           /* +140 */
-        volatile unsigned long iscdp;
-        volatile unsigned long mmas;
-        volatile unsigned long iomas;
-        volatile unsigned long ipciaddr;                /* +150 */
-        volatile unsigned long ipcidata;
-        volatile unsigned long ipcibe;
-};
-
-struct tx3927_ccfg_reg {
-        volatile unsigned long ccfg;
-        volatile unsigned long crir;
-        volatile unsigned long pcfg;
-        volatile unsigned long tear;
-        volatile unsigned long pdcr;
-};
-
-/*
- * SDRAMC
- */
-
-/*
- * ROMC
- */
-
-/*
- * DMA
- */
-/* bits for MCR */
-#define TX3927_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
-#define TX3927_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
-#define TX3927_DMA_MCR_RSFIF    0x00000080
-#define TX3927_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
-#define TX3927_DMA_MCR_LE       0x00000004
-#define TX3927_DMA_MCR_RPRT     0x00000002
-#define TX3927_DMA_MCR_MSTEN    0x00000001
-
-/* bits for CCRn */
-#define TX3927_DMA_CCR_DBINH    0x04000000
-#define TX3927_DMA_CCR_SBINH    0x02000000
-#define TX3927_DMA_CCR_CHRST    0x01000000
-#define TX3927_DMA_CCR_RVBYTE   0x00800000
-#define TX3927_DMA_CCR_ACKPOL   0x00400000
-#define TX3927_DMA_CCR_REQPL    0x00200000
-#define TX3927_DMA_CCR_EGREQ    0x00100000
-#define TX3927_DMA_CCR_CHDN     0x00080000
-#define TX3927_DMA_CCR_DNCTL    0x00060000
-#define TX3927_DMA_CCR_EXTRQ    0x00010000
-#define TX3927_DMA_CCR_INTRQD   0x0000e000
-#define TX3927_DMA_CCR_INTENE   0x00001000
-#define TX3927_DMA_CCR_INTENC   0x00000800
-#define TX3927_DMA_CCR_INTENT   0x00000400
-#define TX3927_DMA_CCR_CHNEN    0x00000200
-#define TX3927_DMA_CCR_XFACT    0x00000100
-#define TX3927_DMA_CCR_SNOP     0x00000080
-#define TX3927_DMA_CCR_DSTINC   0x00000040
-#define TX3927_DMA_CCR_SRCINC   0x00000020
-#define TX3927_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
-#define TX3927_DMA_CCR_XFSZ_1W  TX3927_DMA_CCR_XFSZ(2)
-#define TX3927_DMA_CCR_XFSZ_4W  TX3927_DMA_CCR_XFSZ(4)
-#define TX3927_DMA_CCR_XFSZ_8W  TX3927_DMA_CCR_XFSZ(5)
-#define TX3927_DMA_CCR_XFSZ_16W TX3927_DMA_CCR_XFSZ(6)
-#define TX3927_DMA_CCR_XFSZ_32W TX3927_DMA_CCR_XFSZ(7)
-#define TX3927_DMA_CCR_MEMIO    0x00000002
-#define TX3927_DMA_CCR_ONEAD    0x00000001
-
-/* bits for CSRn */
-#define TX3927_DMA_CSR_CHNACT   0x00000100
-#define TX3927_DMA_CSR_ABCHC    0x00000080
-#define TX3927_DMA_CSR_NCHNC    0x00000040
-#define TX3927_DMA_CSR_NTRNFC   0x00000020
-#define TX3927_DMA_CSR_EXTDN    0x00000010
-#define TX3927_DMA_CSR_CFERR    0x00000008
-#define TX3927_DMA_CSR_CHERR    0x00000004
-#define TX3927_DMA_CSR_DESERR   0x00000002
-#define TX3927_DMA_CSR_SORERR   0x00000001
-
-/*
- * IRC
- */
-#define TX3927_IR_INT0  0
-#define TX3927_IR_INT1  1
-#define TX3927_IR_INT2  2
-#define TX3927_IR_INT3  3
-#define TX3927_IR_INT4  4
-#define TX3927_IR_INT5  5
-#define TX3927_IR_SIO0  6
-#define TX3927_IR_SIO1  7
-#define TX3927_IR_SIO(ch)       (6 + (ch))
-#define TX3927_IR_DMA   8
-#define TX3927_IR_PIO   9
-#define TX3927_IR_PCI   10
-#define TX3927_IR_TMR(ch)       (13 + (ch))
-#define TX3927_NUM_IR   16
-
-/*
- * PCIC
- */
-/* bits for PCICMD */
-/* see PCI_COMMAND_XXX in linux/pci.h */
-
-/* bits for PCISTAT */
-/* see PCI_STATUS_XXX in linux/pci.h */
-#define PCI_STATUS_NEW_CAP      0x0010
-
-/* bits for ISTAT/IIM */
-#define TX3927_PCIC_IIM_ALL     0x00001600
-
-/* bits for TC */
-#define TX3927_PCIC_TC_OF16E    0x00000020
-#define TX3927_PCIC_TC_IF8E     0x00000010
-#define TX3927_PCIC_TC_OF8E     0x00000008
-
-/* bits for TSTAT/TIM */
-#define TX3927_PCIC_TIM_ALL     0x0003ffff
-
-/* bits for IOBA/MBA */
-/* see PCI_BASE_ADDRESS_XXX in linux/pci.h */
-
-/* bits for PBAPMC */
-#define TX3927_PCIC_PBAPMC_RPBA 0x00000004
-#define TX3927_PCIC_PBAPMC_PBAEN        0x00000002
-#define TX3927_PCIC_PBAPMC_BMCEN        0x00000001
-
-/* bits for LBSTAT/LBIM */
-#define TX3927_PCIC_LBIM_ALL    0x0000003e
-
-/* bits for PCISTATIM (see also PCI_STATUS_XXX in linux/pci.h */
-#define TX3927_PCIC_PCISTATIM_ALL       0x0000f900
-
-/* bits for LBC */
-#define TX3927_PCIC_LBC_IBSE    0x00004000
-#define TX3927_PCIC_LBC_TIBSE   0x00002000
-#define TX3927_PCIC_LBC_TMFBSE  0x00001000
-#define TX3927_PCIC_LBC_HRST    0x00000800
-#define TX3927_PCIC_LBC_SRST    0x00000400
-#define TX3927_PCIC_LBC_EPCAD   0x00000200
-#define TX3927_PCIC_LBC_MSDSE   0x00000100
-#define TX3927_PCIC_LBC_CRR     0x00000080
-#define TX3927_PCIC_LBC_ILMDE   0x00000040
-#define TX3927_PCIC_LBC_ILIDE   0x00000020
-
-#define TX3927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
-#define TX3927_PCIC_MAX_DEVNU   TX3927_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX3927_CCFG_TLBOFF      0x00020000
-#define TX3927_CCFG_BEOW        0x00010000
-#define TX3927_CCFG_WR  0x00008000
-#define TX3927_CCFG_TOE 0x00004000
-#define TX3927_CCFG_PCIXARB     0x00002000
-#define TX3927_CCFG_PCI3        0x00001000
-#define TX3927_CCFG_PSNP        0x00000800
-#define TX3927_CCFG_PPRI        0x00000400
-#define TX3927_CCFG_PLLM        0x00000030
-#define TX3927_CCFG_ENDIAN      0x00000004
-#define TX3927_CCFG_HALT        0x00000002
-#define TX3927_CCFG_ACEHOLD     0x00000001
-
-/* PCFG : Pin Configuration */
-#define TX3927_PCFG_SYSCLKEN    0x08000000
-#define TX3927_PCFG_SDRCLKEN_ALL        0x07c00000
-#define TX3927_PCFG_SDRCLKEN(ch)        (0x00400000<<(ch))
-#define TX3927_PCFG_PCICLKEN_ALL        0x003c0000
-#define TX3927_PCFG_PCICLKEN(ch)        (0x00040000<<(ch))
-#define TX3927_PCFG_SELALL      0x0003ffff
-#define TX3927_PCFG_SELCS       0x00020000
-#define TX3927_PCFG_SELDSF      0x00010000
-#define TX3927_PCFG_SELSIOC_ALL 0x0000c000
-#define TX3927_PCFG_SELSIOC(ch) (0x00004000<<(ch))
-#define TX3927_PCFG_SELSIO_ALL  0x00003000
-#define TX3927_PCFG_SELSIO(ch)  (0x00001000<<(ch))
-#define TX3927_PCFG_SELTMR_ALL  0x00000e00
-#define TX3927_PCFG_SELTMR(ch)  (0x00000200<<(ch))
-#define TX3927_PCFG_SELDONE     0x00000100
-#define TX3927_PCFG_INTDMA_ALL  0x000000f0
-#define TX3927_PCFG_INTDMA(ch)  (0x00000010<<(ch))
-#define TX3927_PCFG_SELDMA_ALL  0x0000000f
-#define TX3927_PCFG_SELDMA(ch)  (0x00000001<<(ch))
-
-#define tx3927_sdramcptr        ((struct tx3927_sdramc_reg *)TX3927_SDRAMC_REG)
-#define tx3927_romcptr          ((struct tx3927_romc_reg *)TX3927_ROMC_REG)
-#define tx3927_dmaptr           ((struct tx3927_dma_reg *)TX3927_DMA_REG)
-#define tx3927_pcicptr          ((struct tx3927_pcic_reg *)TX3927_PCIC_REG)
-#define tx3927_ccfgptr          ((struct tx3927_ccfg_reg *)TX3927_CCFG_REG)
-#define tx3927_sioptr(ch)       ((struct txx927_sio_reg *)TX3927_SIO_REG(ch))
-#define tx3927_pioptr           ((struct txx9_pio_reg __iomem *)TX3927_PIO_REG)
-
-#define TX3927_REV_PCODE()      (tx3927_ccfgptr->crir >> 16)
-#define TX3927_ROMC_BA(ch)      (tx3927_romcptr->cr[(ch)] & 0xfff00000)
-#define TX3927_ROMC_SIZE(ch)    \
-        (0x00100000 << ((tx3927_romcptr->cr[(ch)] >> 8) & 0xf))
-
-void tx3927_wdt_init(void);
-void tx3927_setup(void);
-void tx3927_time_init(unsigned int evt_tmrnr, unsigned int src_tmrnr);
-void tx3927_sio_init(unsigned int sclk, unsigned int cts_mask);
-struct pci_controller;
-void tx3927_pcic_setup(struct pci_controller *channel,
-                       unsigned long sdram_size, int extarb);
-void tx3927_setup_pcierr_irq(void);
-void tx3927_irq_init(void);
-
-#endif /* __ASM_TXX9_TX3927_H */
diff --git a/include/asm-mips/txx9/tx4927.h b/include/asm-mips/txx9/tx4927.h
deleted file mode 100644
index 195f6515db9a..000000000000
--- a/include/asm-mips/txx9/tx4927.h
+++ /dev/null
@@ -1,255 +0,0 @@
-/*
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * Copyright 2001-2006 MontaVista Software Inc.
- *
- *  This program is free software; you can redistribute it and/or modify it
- *  under the terms of the GNU General Public License as published by the
- *  Free Software Foundation; either version 2 of the License, or (at your
- *  option) any later version.
- *
- *  THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
- *  WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
- *  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
- *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- *  BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- *  OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
- *  ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
- *  TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
- *  USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  675 Mass Ave, Cambridge, MA 02139, USA.
- */
-#ifndef __ASM_TXX9_TX4927_H
-#define __ASM_TXX9_TX4927_H
-
-#include <linux/types.h>
-#include <linux/io.h>
-#include <asm/txx9irq.h>
-#include <asm/txx9/tx4927pcic.h>
-
-#ifdef CONFIG_64BIT
-#define TX4927_REG_BASE 0xffffffffff1f0000UL
-#else
-#define TX4927_REG_BASE 0xff1f0000UL
-#endif
-#define TX4927_REG_SIZE 0x00010000
-
-#define TX4927_SDRAMC_REG       (TX4927_REG_BASE + 0x8000)
-#define TX4927_EBUSC_REG        (TX4927_REG_BASE + 0x9000)
-#define TX4927_PCIC_REG         (TX4927_REG_BASE + 0xd000)
-#define TX4927_CCFG_REG         (TX4927_REG_BASE + 0xe000)
-#define TX4927_IRC_REG          (TX4927_REG_BASE + 0xf600)
-#define TX4927_NR_TMR   3
-#define TX4927_TMR_REG(ch)      (TX4927_REG_BASE + 0xf000 + (ch) * 0x100)
-#define TX4927_NR_SIO   2
-#define TX4927_SIO_REG(ch)      (TX4927_REG_BASE + 0xf300 + (ch) * 0x100)
-#define TX4927_PIO_REG          (TX4927_REG_BASE + 0xf500)
-
-#define TX4927_IR_INT(n)        (2 + (n))
-#define TX4927_IR_SIO(n)        (8 + (n))
-#define TX4927_IR_PCIC          16
-#define TX4927_NUM_IR_TMR       3
-#define TX4927_IR_TMR(n)        (17 + (n))
-#define TX4927_IR_PCIERR        22
-#define TX4927_NUM_IR   32
-
-#define TX4927_IRC_INT  2       /* IP[2] in Status register */
-
-#define TX4927_NUM_PIO  16
-
-struct tx4927_sdramc_reg {
-        u64 cr[4];
-        u64 unused0[4];
-        u64 tr;
-        u64 unused1[2];
-        u64 cmd;
-};
-
-struct tx4927_ebusc_reg {
-        u64 cr[8];
-};
-
-struct tx4927_ccfg_reg {
-        u64 ccfg;
-        u64 crir;
-        u64 pcfg;
-        u64 toea;
-        u64 clkctr;
-        u64 unused0;
-        u64 garbc;
-        u64 unused1;
-        u64 unused2;
-        u64 ramp;
-};
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4927_CCFG_WDRST       0x0000020000000000ULL
-#define TX4927_CCFG_WDREXEN     0x0000010000000000ULL
-#define TX4927_CCFG_BCFG_MASK   0x000000ff00000000ULL
-#define TX4927_CCFG_TINTDIS     0x01000000
-#define TX4927_CCFG_PCI66       0x00800000
-#define TX4927_CCFG_PCIMODE     0x00400000
-#define TX4927_CCFG_DIVMODE_MASK        0x000e0000
-#define TX4927_CCFG_DIVMODE_8   (0x0 << 17)
-#define TX4927_CCFG_DIVMODE_12  (0x1 << 17)
-#define TX4927_CCFG_DIVMODE_16  (0x2 << 17)
-#define TX4927_CCFG_DIVMODE_10  (0x3 << 17)
-#define TX4927_CCFG_DIVMODE_2   (0x4 << 17)
-#define TX4927_CCFG_DIVMODE_3   (0x5 << 17)
-#define TX4927_CCFG_DIVMODE_4   (0x6 << 17)
-#define TX4927_CCFG_DIVMODE_2_5 (0x7 << 17)
-#define TX4927_CCFG_BEOW        0x00010000
-#define TX4927_CCFG_WR  0x00008000
-#define TX4927_CCFG_TOE 0x00004000
-#define TX4927_CCFG_PCIARB      0x00002000
-#define TX4927_CCFG_PCIDIVMODE_MASK     0x00001800
-#define TX4927_CCFG_PCIDIVMODE_2_5      0x00000000
-#define TX4927_CCFG_PCIDIVMODE_3        0x00000800
-#define TX4927_CCFG_PCIDIVMODE_5        0x00001000
-#define TX4927_CCFG_PCIDIVMODE_6        0x00001800
-#define TX4927_CCFG_SYSSP_MASK  0x000000c0
-#define TX4927_CCFG_ENDIAN      0x00000004
-#define TX4927_CCFG_HALT        0x00000002
-#define TX4927_CCFG_ACEHOLD     0x00000001
-#define TX4927_CCFG_W1CBITS     (TX4927_CCFG_WDRST | TX4927_CCFG_BEOW)
-
-/* PCFG : Pin Configuration */
-#define TX4927_PCFG_SDCLKDLY_MASK       0x30000000
-#define TX4927_PCFG_SDCLKDLY(d) ((d)<<28)
-#define TX4927_PCFG_SYSCLKEN    0x08000000
-#define TX4927_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4927_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
-#define TX4927_PCFG_PCICLKEN_ALL        0x003f0000
-#define TX4927_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
-#define TX4927_PCFG_SEL2        0x00000200
-#define TX4927_PCFG_SEL1        0x00000100
-#define TX4927_PCFG_DMASEL_ALL  0x000000ff
-#define TX4927_PCFG_DMASEL0_MASK        0x00000003
-#define TX4927_PCFG_DMASEL1_MASK        0x0000000c
-#define TX4927_PCFG_DMASEL2_MASK        0x00000030
-#define TX4927_PCFG_DMASEL3_MASK        0x000000c0
-#define TX4927_PCFG_DMASEL0_DRQ0        0x00000000
-#define TX4927_PCFG_DMASEL0_SIO1        0x00000001
-#define TX4927_PCFG_DMASEL0_ACL0        0x00000002
-#define TX4927_PCFG_DMASEL0_ACL2        0x00000003
-#define TX4927_PCFG_DMASEL1_DRQ1        0x00000000
-#define TX4927_PCFG_DMASEL1_SIO1        0x00000004
-#define TX4927_PCFG_DMASEL1_ACL1        0x00000008
-#define TX4927_PCFG_DMASEL1_ACL3        0x0000000c
-#define TX4927_PCFG_DMASEL2_DRQ2        0x00000000      /* SEL2=0 */
-#define TX4927_PCFG_DMASEL2_SIO0        0x00000010      /* SEL2=0 */
-#define TX4927_PCFG_DMASEL2_ACL1        0x00000000      /* SEL2=1 */
-#define TX4927_PCFG_DMASEL2_ACL2        0x00000020      /* SEL2=1 */
-#define TX4927_PCFG_DMASEL2_ACL0        0x00000030      /* SEL2=1 */
-#define TX4927_PCFG_DMASEL3_DRQ3        0x00000000
-#define TX4927_PCFG_DMASEL3_SIO0        0x00000040
-#define TX4927_PCFG_DMASEL3_ACL3        0x00000080
-#define TX4927_PCFG_DMASEL3_ACL1        0x000000c0
-
-/* CLKCTR : Clock Control */
-#define TX4927_CLKCTR_ACLCKD    0x02000000
-#define TX4927_CLKCTR_PIOCKD    0x01000000
-#define TX4927_CLKCTR_DMACKD    0x00800000
-#define TX4927_CLKCTR_PCICKD    0x00400000
-#define TX4927_CLKCTR_TM0CKD    0x00100000
-#define TX4927_CLKCTR_TM1CKD    0x00080000
-#define TX4927_CLKCTR_TM2CKD    0x00040000
-#define TX4927_CLKCTR_SIO0CKD   0x00020000
-#define TX4927_CLKCTR_SIO1CKD   0x00010000
-#define TX4927_CLKCTR_ACLRST    0x00000200
-#define TX4927_CLKCTR_PIORST    0x00000100
-#define TX4927_CLKCTR_DMARST    0x00000080
-#define TX4927_CLKCTR_PCIRST    0x00000040
-#define TX4927_CLKCTR_TM0RST    0x00000010
-#define TX4927_CLKCTR_TM1RST    0x00000008
-#define TX4927_CLKCTR_TM2RST    0x00000004
-#define TX4927_CLKCTR_SIO0RST   0x00000002
-#define TX4927_CLKCTR_SIO1RST   0x00000001
-
-#define tx4927_sdramcptr \
-                ((struct tx4927_sdramc_reg __iomem *)TX4927_SDRAMC_REG)
-#define tx4927_pcicptr \
-                ((struct tx4927_pcic_reg __iomem *)TX4927_PCIC_REG)
-#define tx4927_ccfgptr \
-                ((struct tx4927_ccfg_reg __iomem *)TX4927_CCFG_REG)
-#define tx4927_ebuscptr \
-                ((struct tx4927_ebusc_reg __iomem *)TX4927_EBUSC_REG)
-#define tx4927_pioptr           ((struct txx9_pio_reg __iomem *)TX4927_PIO_REG)
-
-#define TX4927_REV_PCODE()      \
-        ((__u32)__raw_readq(&tx4927_ccfgptr->crir) >> 16)
-
-#define TX4927_SDRAMC_CR(ch)    __raw_readq(&tx4927_sdramcptr->cr[(ch)])
-#define TX4927_SDRAMC_BA(ch)    ((TX4927_SDRAMC_CR(ch) >> 49) << 21)
-#define TX4927_SDRAMC_SIZE(ch)  \
-        ((((TX4927_SDRAMC_CR(ch) >> 33) & 0x7fff) + 1) << 21)
-
-#define TX4927_EBUSC_CR(ch)     __raw_readq(&tx4927_ebuscptr->cr[(ch)])
-#define TX4927_EBUSC_BA(ch)     ((TX4927_EBUSC_CR(ch) >> 48) << 20)
-#define TX4927_EBUSC_SIZE(ch)   \
-        (0x00100000 << ((unsigned long)(TX4927_EBUSC_CR(ch) >> 8) & 0xf))
-
-/* utilities */
-static inline void txx9_clear64(__u64 __iomem *adr, __u64 bits)
-{
-#ifdef CONFIG_32BIT
-        unsigned long flags;
-        local_irq_save(flags);
-#endif
-        ____raw_writeq(____raw_readq(adr) & ~bits, adr);
-#ifdef CONFIG_32BIT
-        local_irq_restore(flags);
-#endif
-}
-static inline void txx9_set64(__u64 __iomem *adr, __u64 bits)
-{
-#ifdef CONFIG_32BIT
-        unsigned long flags;
-        local_irq_save(flags);
-#endif
-        ____raw_writeq(____raw_readq(adr) | bits, adr);
-#ifdef CONFIG_32BIT
-        local_irq_restore(flags);
-#endif
-}
-
-/* These functions are not interrupt safe. */
-static inline void tx4927_ccfg_clear(__u64 bits)
-{
-        ____raw_writeq(____raw_readq(&tx4927_ccfgptr->ccfg)
-                       & ~(TX4927_CCFG_W1CBITS | bits),
-                       &tx4927_ccfgptr->ccfg);
-}
-static inline void tx4927_ccfg_set(__u64 bits)
-{
-        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
-                        & ~TX4927_CCFG_W1CBITS) | bits,
-                       &tx4927_ccfgptr->ccfg);
-}
-static inline void tx4927_ccfg_change(__u64 change, __u64 new)
-{
-        ____raw_writeq((____raw_readq(&tx4927_ccfgptr->ccfg)
-                        & ~(TX4927_CCFG_W1CBITS | change)) |
-                       new,
-                       &tx4927_ccfgptr->ccfg);
-}
-
-unsigned int tx4927_get_mem_size(void);
-void tx4927_wdt_init(void);
-void tx4927_setup(void);
-void tx4927_time_init(unsigned int tmrnr);
-void tx4927_sio_init(unsigned int sclk, unsigned int cts_mask);
-int tx4927_report_pciclk(void);
-int tx4927_pciclk66_setup(void);
-void tx4927_setup_pcierr_irq(void);
-void tx4927_irq_init(void);
-
-#endif /* __ASM_TXX9_TX4927_H */
diff --git a/include/asm-mips/txx9/tx4927pcic.h b/include/asm-mips/txx9/tx4927pcic.h
deleted file mode 100644
index c470b8a5fe57..000000000000
--- a/include/asm-mips/txx9/tx4927pcic.h
+++ /dev/null
@@ -1,203 +0,0 @@
-/*
- * include/asm-mips/txx9/tx4927pcic.h
- * TX4927 PCI controller definitions.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9_TX4927PCIC_H
-#define __ASM_TXX9_TX4927PCIC_H
-
-#include <linux/pci.h>
-#include <linux/irqreturn.h>
-
-struct tx4927_pcic_reg {
-        u32 pciid;
-        u32 pcistatus;
-        u32 pciccrev;
-        u32 pcicfg1;
-        u32 p2gm0plbase;                /* +10 */
-        u32 p2gm0pubase;
-        u32 p2gm1plbase;
-        u32 p2gm1pubase;
-        u32 p2gm2pbase;         /* +20 */
-        u32 p2giopbase;
-        u32 unused0;
-        u32 pcisid;
-        u32 unused1;            /* +30 */
-        u32 pcicapptr;
-        u32 unused2;
-        u32 pcicfg2;
-        u32 g2ptocnt;           /* +40 */
-        u32 unused3[15];
-        u32 g2pstatus;          /* +80 */
-        u32 g2pmask;
-        u32 pcisstatus;
-        u32 pcimask;
-        u32 p2gcfg;             /* +90 */
-        u32 p2gstatus;
-        u32 p2gmask;
-        u32 p2gccmd;
-        u32 unused4[24];                /* +a0 */
-        u32 pbareqport;         /* +100 */
-        u32 pbacfg;
-        u32 pbastatus;
-        u32 pbamask;
-        u32 pbabm;              /* +110 */
-        u32 pbacreq;
-        u32 pbacgnt;
-        u32 pbacstate;
-        u64 g2pmgbase[3];               /* +120 */
-        u64 g2piogbase;
-        u32 g2pmmask[3];                /* +140 */
-        u32 g2piomask;
-        u64 g2pmpbase[3];               /* +150 */
-        u64 g2piopbase;
-        u32 pciccfg;            /* +170 */
-        u32 pcicstatus;
-        u32 pcicmask;
-        u32 unused5;
-        u64 p2gmgbase[3];               /* +180 */
-        u64 p2giogbase;
-        u32 g2pcfgadrs;         /* +1a0 */
-        u32 g2pcfgdata;
-        u32 unused6[8];
-        u32 g2pintack;
-        u32 g2pspc;
-        u32 unused7[12];                /* +1d0 */
-        u64 pdmca;              /* +200 */
-        u64 pdmga;
-        u64 pdmpa;
-        u64 pdmctr;
-        u64 pdmcfg;             /* +220 */
-        u64 pdmsts;
-};
-
-/* bits for PCICMD */
-/* see PCI_COMMAND_XXX in linux/pci_regs.h */
-
-/* bits for PCISTAT */
-/* see PCI_STATUS_XXX in linux/pci_regs.h */
-
-/* bits for IOBA/MBA */
-/* see PCI_BASE_ADDRESS_XXX in linux/pci_regs.h */
-
-/* bits for G2PSTATUS/G2PMASK */
-#define TX4927_PCIC_G2PSTATUS_ALL       0x00000003
-#define TX4927_PCIC_G2PSTATUS_TTOE      0x00000002
-#define TX4927_PCIC_G2PSTATUS_RTOE      0x00000001
-
-/* bits for PCIMASK (see also PCI_STATUS_XXX in linux/pci_regs.h */
-#define TX4927_PCIC_PCISTATUS_ALL       0x0000f900
-
-/* bits for PBACFG */
-#define TX4927_PCIC_PBACFG_FIXPA        0x00000008
-#define TX4927_PCIC_PBACFG_RPBA 0x00000004
-#define TX4927_PCIC_PBACFG_PBAEN        0x00000002
-#define TX4927_PCIC_PBACFG_BMCEN        0x00000001
-
-/* bits for PBASTATUS/PBAMASK */
-#define TX4927_PCIC_PBASTATUS_ALL       0x00000001
-#define TX4927_PCIC_PBASTATUS_BM        0x00000001
-
-/* bits for G2PMnGBASE */
-#define TX4927_PCIC_G2PMnGBASE_BSDIS    0x0000002000000000ULL
-#define TX4927_PCIC_G2PMnGBASE_ECHG     0x0000001000000000ULL
-
-/* bits for G2PIOGBASE */
-#define TX4927_PCIC_G2PIOGBASE_BSDIS    0x0000002000000000ULL
-#define TX4927_PCIC_G2PIOGBASE_ECHG     0x0000001000000000ULL
-
-/* bits for PCICSTATUS/PCICMASK */
-#define TX4927_PCIC_PCICSTATUS_ALL      0x000007b8
-#define TX4927_PCIC_PCICSTATUS_PME      0x00000400
-#define TX4927_PCIC_PCICSTATUS_TLB      0x00000200
-#define TX4927_PCIC_PCICSTATUS_NIB      0x00000100
-#define TX4927_PCIC_PCICSTATUS_ZIB      0x00000080
-#define TX4927_PCIC_PCICSTATUS_PERR     0x00000020
-#define TX4927_PCIC_PCICSTATUS_SERR     0x00000010
-#define TX4927_PCIC_PCICSTATUS_GBE      0x00000008
-#define TX4927_PCIC_PCICSTATUS_IWB      0x00000002
-#define TX4927_PCIC_PCICSTATUS_E2PDONE  0x00000001
-
-/* bits for PCICCFG */
-#define TX4927_PCIC_PCICCFG_GBWC_MASK   0x0fff0000
-#define TX4927_PCIC_PCICCFG_HRST        0x00000800
-#define TX4927_PCIC_PCICCFG_SRST        0x00000400
-#define TX4927_PCIC_PCICCFG_IRBER       0x00000200
-#define TX4927_PCIC_PCICCFG_G2PMEN(ch)  (0x00000100>>(ch))
-#define TX4927_PCIC_PCICCFG_G2PM0EN     0x00000100
-#define TX4927_PCIC_PCICCFG_G2PM1EN     0x00000080
-#define TX4927_PCIC_PCICCFG_G2PM2EN     0x00000040
-#define TX4927_PCIC_PCICCFG_G2PIOEN     0x00000020
-#define TX4927_PCIC_PCICCFG_TCAR        0x00000010
-#define TX4927_PCIC_PCICCFG_ICAEN       0x00000008
-
-/* bits for P2GMnGBASE */
-#define TX4927_PCIC_P2GMnGBASE_TMEMEN   0x0000004000000000ULL
-#define TX4927_PCIC_P2GMnGBASE_TBSDIS   0x0000002000000000ULL
-#define TX4927_PCIC_P2GMnGBASE_TECHG    0x0000001000000000ULL
-
-/* bits for P2GIOGBASE */
-#define TX4927_PCIC_P2GIOGBASE_TIOEN    0x0000004000000000ULL
-#define TX4927_PCIC_P2GIOGBASE_TBSDIS   0x0000002000000000ULL
-#define TX4927_PCIC_P2GIOGBASE_TECHG    0x0000001000000000ULL
-
-#define TX4927_PCIC_IDSEL_AD_TO_SLOT(ad)        ((ad) - 11)
-#define TX4927_PCIC_MAX_DEVNU   TX4927_PCIC_IDSEL_AD_TO_SLOT(32)
-
-/* bits for PDMCFG */
-#define TX4927_PCIC_PDMCFG_RSTFIFO      0x00200000
-#define TX4927_PCIC_PDMCFG_EXFER        0x00100000
-#define TX4927_PCIC_PDMCFG_REQDLY_MASK  0x00003800
-#define TX4927_PCIC_PDMCFG_REQDLY_NONE  (0 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_16    (1 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_32    (2 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_64    (3 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_128   (4 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_256   (5 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_512   (6 << 11)
-#define TX4927_PCIC_PDMCFG_REQDLY_1024  (7 << 11)
-#define TX4927_PCIC_PDMCFG_ERRIE        0x00000400
-#define TX4927_PCIC_PDMCFG_NCCMPIE      0x00000200
-#define TX4927_PCIC_PDMCFG_NTCMPIE      0x00000100
-#define TX4927_PCIC_PDMCFG_CHNEN        0x00000080
-#define TX4927_PCIC_PDMCFG_XFRACT       0x00000040
-#define TX4927_PCIC_PDMCFG_BSWAP        0x00000020
-#define TX4927_PCIC_PDMCFG_XFRSIZE_MASK 0x0000000c
-#define TX4927_PCIC_PDMCFG_XFRSIZE_1DW  0x00000000
-#define TX4927_PCIC_PDMCFG_XFRSIZE_1QW  0x00000004
-#define TX4927_PCIC_PDMCFG_XFRSIZE_4QW  0x00000008
-#define TX4927_PCIC_PDMCFG_XFRDIRC      0x00000002
-#define TX4927_PCIC_PDMCFG_CHRST        0x00000001
-
-/* bits for PDMSTS */
-#define TX4927_PCIC_PDMSTS_REQCNT_MASK  0x3f000000
-#define TX4927_PCIC_PDMSTS_FIFOCNT_MASK 0x00f00000
-#define TX4927_PCIC_PDMSTS_FIFOWP_MASK  0x000c0000
-#define TX4927_PCIC_PDMSTS_FIFORP_MASK  0x00030000
-#define TX4927_PCIC_PDMSTS_ERRINT       0x00000800
-#define TX4927_PCIC_PDMSTS_DONEINT      0x00000400
-#define TX4927_PCIC_PDMSTS_CHNEN        0x00000200
-#define TX4927_PCIC_PDMSTS_XFRACT       0x00000100
-#define TX4927_PCIC_PDMSTS_ACCMP        0x00000080
-#define TX4927_PCIC_PDMSTS_NCCMP        0x00000040
-#define TX4927_PCIC_PDMSTS_NTCMP        0x00000020
-#define TX4927_PCIC_PDMSTS_CFGERR       0x00000008
-#define TX4927_PCIC_PDMSTS_PCIERR       0x00000004
-#define TX4927_PCIC_PDMSTS_CHNERR       0x00000002
-#define TX4927_PCIC_PDMSTS_DATAERR      0x00000001
-#define TX4927_PCIC_PDMSTS_ALL_CMP      0x000000e0
-#define TX4927_PCIC_PDMSTS_ALL_ERR      0x0000000f
-
-struct tx4927_pcic_reg __iomem *get_tx4927_pcicptr(
-        struct pci_controller *channel);
-void tx4927_pcic_setup(struct tx4927_pcic_reg __iomem *pcicptr,
-                       struct pci_controller *channel, int extarb);
-void tx4927_report_pcic_status(void);
-char *tx4927_pcibios_setup(char *str);
-void tx4927_dump_pcic_settings(void);
-irqreturn_t tx4927_pcierr_interrupt(int irq, void *dev_id);
-
-#endif /* __ASM_TXX9_TX4927PCIC_H */
diff --git a/include/asm-mips/txx9/tx4938.h b/include/asm-mips/txx9/tx4938.h
deleted file mode 100644
index 8175d4ccbc39..000000000000
--- a/include/asm-mips/txx9/tx4938.h
+++ /dev/null
@@ -1,293 +0,0 @@
-/*
- * Definitions for TX4937/TX4938
- * Copyright (C) 2000-2001 Toshiba Corporation
- *
- * 2003-2005 (c) MontaVista Software, Inc. This file is licensed under the
- * terms of the GNU General Public License version 2. This program is
- * licensed "as is" without any warranty of any kind, whether express
- * or implied.
- *
- * Support for TX4938 in 2.6 - Manish Lachwani (mlachwani@mvista.com)
- */
-#ifndef __ASM_TXX9_TX4938_H
-#define __ASM_TXX9_TX4938_H
-
-/* some controllers are compatible with 4927 */
-#include <asm/txx9/tx4927.h>
-
-#ifdef CONFIG_64BIT
-#define TX4938_REG_BASE 0xffffffffff1f0000UL /* == TX4937_REG_BASE */
-#else
-#define TX4938_REG_BASE 0xff1f0000UL /* == TX4937_REG_BASE */
-#endif
-#define TX4938_REG_SIZE 0x00010000 /* == TX4937_REG_SIZE */
-
-/* NDFMC, SRAMC, PCIC1, SPIC: TX4938 only */
-#define TX4938_NDFMC_REG        (TX4938_REG_BASE + 0x5000)
-#define TX4938_SRAMC_REG        (TX4938_REG_BASE + 0x6000)
-#define TX4938_PCIC1_REG        (TX4938_REG_BASE + 0x7000)
-#define TX4938_SDRAMC_REG       (TX4938_REG_BASE + 0x8000)
-#define TX4938_EBUSC_REG        (TX4938_REG_BASE + 0x9000)
-#define TX4938_DMA_REG(ch)      (TX4938_REG_BASE + 0xb000 + (ch) * 0x800)
-#define TX4938_PCIC_REG         (TX4938_REG_BASE + 0xd000)
-#define TX4938_CCFG_REG         (TX4938_REG_BASE + 0xe000)
-#define TX4938_NR_TMR   3
-#define TX4938_TMR_REG(ch)      ((TX4938_REG_BASE + 0xf000) + (ch) * 0x100)
-#define TX4938_NR_SIO   2
-#define TX4938_SIO_REG(ch)      ((TX4938_REG_BASE + 0xf300) + (ch) * 0x100)
-#define TX4938_PIO_REG          (TX4938_REG_BASE + 0xf500)
-#define TX4938_IRC_REG          (TX4938_REG_BASE + 0xf600)
-#define TX4938_ACLC_REG         (TX4938_REG_BASE + 0xf700)
-#define TX4938_SPI_REG          (TX4938_REG_BASE + 0xf800)
-
-struct tx4938_sramc_reg {
-        u64 cr;
-};
-
-struct tx4938_ccfg_reg {
-        u64 ccfg;
-        u64 crir;
-        u64 pcfg;
-        u64 toea;
-        u64 clkctr;
-        u64 unused0;
-        u64 garbc;
-        u64 unused1;
-        u64 unused2;
-        u64 ramp;
-        u64 unused3;
-        u64 jmpadr;
-};
-
-/*
- * IRC
- */
-
-#define TX4938_IR_ECCERR        0
-#define TX4938_IR_WTOERR        1
-#define TX4938_NUM_IR_INT       6
-#define TX4938_IR_INT(n)        (2 + (n))
-#define TX4938_NUM_IR_SIO       2
-#define TX4938_IR_SIO(n)        (8 + (n))
-#define TX4938_NUM_IR_DMA       4
-#define TX4938_IR_DMA(ch, n)    ((ch ? 27 : 10) + (n)) /* 10-13, 27-30 */
-#define TX4938_IR_PIO   14
-#define TX4938_IR_PDMAC 15
-#define TX4938_IR_PCIC  16
-#define TX4938_NUM_IR_TMR       3
-#define TX4938_IR_TMR(n)        (17 + (n))
-#define TX4938_IR_NDFMC 21
-#define TX4938_IR_PCIERR        22
-#define TX4938_IR_PCIPME        23
-#define TX4938_IR_ACLC  24
-#define TX4938_IR_ACLCPME       25
-#define TX4938_IR_PCIC1 26
-#define TX4938_IR_SPI   31
-#define TX4938_NUM_IR   32
-/* multiplex */
-#define TX4938_IR_ETH0  TX4938_IR_INT(4)
-#define TX4938_IR_ETH1  TX4938_IR_INT(3)
-
-#define TX4938_IRC_INT  2       /* IP[2] in Status register */
-
-#define TX4938_NUM_PIO  16
-
-/*
- * CCFG
- */
-/* CCFG : Chip Configuration */
-#define TX4938_CCFG_WDRST       0x0000020000000000ULL
-#define TX4938_CCFG_WDREXEN     0x0000010000000000ULL
-#define TX4938_CCFG_BCFG_MASK   0x000000ff00000000ULL
-#define TX4938_CCFG_TINTDIS     0x01000000
-#define TX4938_CCFG_PCI66       0x00800000
-#define TX4938_CCFG_PCIMODE     0x00400000
-#define TX4938_CCFG_PCI1_66     0x00200000
-#define TX4938_CCFG_DIVMODE_MASK        0x001e0000
-#define TX4938_CCFG_DIVMODE_2   (0x4 << 17)
-#define TX4938_CCFG_DIVMODE_2_5 (0xf << 17)
-#define TX4938_CCFG_DIVMODE_3   (0x5 << 17)
-#define TX4938_CCFG_DIVMODE_4   (0x6 << 17)
-#define TX4938_CCFG_DIVMODE_4_5 (0xd << 17)
-#define TX4938_CCFG_DIVMODE_8   (0x0 << 17)
-#define TX4938_CCFG_DIVMODE_10  (0xb << 17)
-#define TX4938_CCFG_DIVMODE_12  (0x1 << 17)
-#define TX4938_CCFG_DIVMODE_16  (0x2 << 17)
-#define TX4938_CCFG_DIVMODE_18  (0x9 << 17)
-#define TX4938_CCFG_BEOW        0x00010000
-#define TX4938_CCFG_WR  0x00008000
-#define TX4938_CCFG_TOE 0x00004000
-#define TX4938_CCFG_PCIARB      0x00002000
-#define TX4938_CCFG_PCIDIVMODE_MASK     0x00001c00
-#define TX4938_CCFG_PCIDIVMODE_4        (0x1 << 10)
-#define TX4938_CCFG_PCIDIVMODE_4_5      (0x3 << 10)
-#define TX4938_CCFG_PCIDIVMODE_5        (0x5 << 10)
-#define TX4938_CCFG_PCIDIVMODE_5_5      (0x7 << 10)
-#define TX4938_CCFG_PCIDIVMODE_8        (0x0 << 10)
-#define TX4938_CCFG_PCIDIVMODE_9        (0x2 << 10)
-#define TX4938_CCFG_PCIDIVMODE_10       (0x4 << 10)
-#define TX4938_CCFG_PCIDIVMODE_11       (0x6 << 10)
-#define TX4938_CCFG_PCI1DMD     0x00000100
-#define TX4938_CCFG_SYSSP_MASK  0x000000c0
-#define TX4938_CCFG_ENDIAN      0x00000004
-#define TX4938_CCFG_HALT        0x00000002
-#define TX4938_CCFG_ACEHOLD     0x00000001
-
-/* PCFG : Pin Configuration */
-#define TX4938_PCFG_ETH0_SEL    0x8000000000000000ULL
-#define TX4938_PCFG_ETH1_SEL    0x4000000000000000ULL
-#define TX4938_PCFG_ATA_SEL     0x2000000000000000ULL
-#define TX4938_PCFG_ISA_SEL     0x1000000000000000ULL
-#define TX4938_PCFG_SPI_SEL     0x0800000000000000ULL
-#define TX4938_PCFG_NDF_SEL     0x0400000000000000ULL
-#define TX4938_PCFG_SDCLKDLY_MASK       0x30000000
-#define TX4938_PCFG_SDCLKDLY(d) ((d)<<28)
-#define TX4938_PCFG_SYSCLKEN    0x08000000
-#define TX4938_PCFG_SDCLKEN_ALL 0x07800000
-#define TX4938_PCFG_SDCLKEN(ch) (0x00800000<<(ch))
-#define TX4938_PCFG_PCICLKEN_ALL        0x003f0000
-#define TX4938_PCFG_PCICLKEN(ch)        (0x00010000<<(ch))
-#define TX4938_PCFG_SEL2        0x00000200
-#define TX4938_PCFG_SEL1        0x00000100
-#define TX4938_PCFG_DMASEL_ALL  0x0000000f
-#define TX4938_PCFG_DMASEL0_DRQ0        0x00000000
-#define TX4938_PCFG_DMASEL0_SIO1        0x00000001
-#define TX4938_PCFG_DMASEL1_DRQ1        0x00000000
-#define TX4938_PCFG_DMASEL1_SIO1        0x00000002
-#define TX4938_PCFG_DMASEL2_DRQ2        0x00000000
-#define TX4938_PCFG_DMASEL2_SIO0        0x00000004
-#define TX4938_PCFG_DMASEL3_DRQ3        0x00000000
-#define TX4938_PCFG_DMASEL3_SIO0        0x00000008
-
-/* CLKCTR : Clock Control */
-#define TX4938_CLKCTR_NDFCKD    0x0001000000000000ULL
-#define TX4938_CLKCTR_NDFRST    0x0000000100000000ULL
-#define TX4938_CLKCTR_ETH1CKD   0x80000000
-#define TX4938_CLKCTR_ETH0CKD   0x40000000
-#define TX4938_CLKCTR_SPICKD    0x20000000
-#define TX4938_CLKCTR_SRAMCKD   0x10000000
-#define TX4938_CLKCTR_PCIC1CKD  0x08000000
-#define TX4938_CLKCTR_DMA1CKD   0x04000000
-#define TX4938_CLKCTR_ACLCKD    0x02000000
-#define TX4938_CLKCTR_PIOCKD    0x01000000
-#define TX4938_CLKCTR_DMACKD    0x00800000
-#define TX4938_CLKCTR_PCICKD    0x00400000
-#define TX4938_CLKCTR_TM0CKD    0x00100000
-#define TX4938_CLKCTR_TM1CKD    0x00080000
-#define TX4938_CLKCTR_TM2CKD    0x00040000
-#define TX4938_CLKCTR_SIO0CKD   0x00020000
-#define TX4938_CLKCTR_SIO1CKD   0x00010000
-#define TX4938_CLKCTR_ETH1RST   0x00008000
-#define TX4938_CLKCTR_ETH0RST   0x00004000
-#define TX4938_CLKCTR_SPIRST    0x00002000
-#define TX4938_CLKCTR_SRAMRST   0x00001000
-#define TX4938_CLKCTR_PCIC1RST  0x00000800
-#define TX4938_CLKCTR_DMA1RST   0x00000400
-#define TX4938_CLKCTR_ACLRST    0x00000200
-#define TX4938_CLKCTR_PIORST    0x00000100
-#define TX4938_CLKCTR_DMARST    0x00000080
-#define TX4938_CLKCTR_PCIRST    0x00000040
-#define TX4938_CLKCTR_TM0RST    0x00000010
-#define TX4938_CLKCTR_TM1RST    0x00000008
-#define TX4938_CLKCTR_TM2RST    0x00000004
-#define TX4938_CLKCTR_SIO0RST   0x00000002
-#define TX4938_CLKCTR_SIO1RST   0x00000001
-
-/*
- * DMA
- */
-/* bits for MCR */
-#define TX4938_DMA_MCR_EIS(ch)  (0x10000000<<(ch))
-#define TX4938_DMA_MCR_DIS(ch)  (0x01000000<<(ch))
-#define TX4938_DMA_MCR_RSFIF    0x00000080
-#define TX4938_DMA_MCR_FIFUM(ch)        (0x00000008<<(ch))
-#define TX4938_DMA_MCR_RPRT     0x00000002
-#define TX4938_DMA_MCR_MSTEN    0x00000001
-
-/* bits for CCRn */
-#define TX4938_DMA_CCR_IMMCHN   0x20000000
-#define TX4938_DMA_CCR_USEXFSZ  0x10000000
-#define TX4938_DMA_CCR_LE       0x08000000
-#define TX4938_DMA_CCR_DBINH    0x04000000
-#define TX4938_DMA_CCR_SBINH    0x02000000
-#define TX4938_DMA_CCR_CHRST    0x01000000
-#define TX4938_DMA_CCR_RVBYTE   0x00800000
-#define TX4938_DMA_CCR_ACKPOL   0x00400000
-#define TX4938_DMA_CCR_REQPL    0x00200000
-#define TX4938_DMA_CCR_EGREQ    0x00100000
-#define TX4938_DMA_CCR_CHDN     0x00080000
-#define TX4938_DMA_CCR_DNCTL    0x00060000
-#define TX4938_DMA_CCR_EXTRQ    0x00010000
-#define TX4938_DMA_CCR_INTRQD   0x0000e000
-#define TX4938_DMA_CCR_INTENE   0x00001000
-#define TX4938_DMA_CCR_INTENC   0x00000800
-#define TX4938_DMA_CCR_INTENT   0x00000400
-#define TX4938_DMA_CCR_CHNEN    0x00000200
-#define TX4938_DMA_CCR_XFACT    0x00000100
-#define TX4938_DMA_CCR_SMPCHN   0x00000020
-#define TX4938_DMA_CCR_XFSZ(order)      (((order) << 2) & 0x0000001c)
-#define TX4938_DMA_CCR_XFSZ_1W  TX4938_DMA_CCR_XFSZ(2)
-#define TX4938_DMA_CCR_XFSZ_2W  TX4938_DMA_CCR_XFSZ(3)
-#define TX4938_DMA_CCR_XFSZ_4W  TX4938_DMA_CCR_XFSZ(4)
-#define TX4938_DMA_CCR_XFSZ_8W  TX4938_DMA_CCR_XFSZ(5)
-#define TX4938_DMA_CCR_XFSZ_16W TX4938_DMA_CCR_XFSZ(6)
-#define TX4938_DMA_CCR_XFSZ_32W TX4938_DMA_CCR_XFSZ(7)
-#define TX4938_DMA_CCR_MEMIO    0x00000002
-#define TX4938_DMA_CCR_SNGAD    0x00000001
-
-/* bits for CSRn */
-#define TX4938_DMA_CSR_CHNEN    0x00000400
-#define TX4938_DMA_CSR_STLXFER  0x00000200
-#define TX4938_DMA_CSR_CHNACT   0x00000100
-#define TX4938_DMA_CSR_ABCHC    0x00000080
-#define TX4938_DMA_CSR_NCHNC    0x00000040
-#define TX4938_DMA_CSR_NTRNFC   0x00000020
-#define TX4938_DMA_CSR_EXTDN    0x00000010
-#define TX4938_DMA_CSR_CFERR    0x00000008
-#define TX4938_DMA_CSR_CHERR    0x00000004
-#define TX4938_DMA_CSR_DESERR   0x00000002
-#define TX4938_DMA_CSR_SORERR   0x00000001
-
-#define tx4938_sdramcptr        tx4927_sdramcptr
-#define tx4938_ebuscptr         tx4927_ebuscptr
-#define tx4938_pcicptr          tx4927_pcicptr
-#define tx4938_pcic1ptr \
-                ((struct tx4927_pcic_reg __iomem *)TX4938_PCIC1_REG)
-#define tx4938_ccfgptr \
-                ((struct tx4938_ccfg_reg __iomem *)TX4938_CCFG_REG)
-#define tx4938_pioptr           ((struct txx9_pio_reg __iomem *)TX4938_PIO_REG)
-#define tx4938_sramcptr \
-                ((struct tx4938_sramc_reg __iomem *)TX4938_SRAMC_REG)
-
-
-#define TX4938_REV_PCODE()      \
-        ((__u32)__raw_readq(&tx4938_ccfgptr->crir) >> 16)
-
-#define tx4938_ccfg_clear(bits) tx4927_ccfg_clear(bits)
-#define tx4938_ccfg_set(bits)   tx4927_ccfg_set(bits)
-#define tx4938_ccfg_change(change, new) tx4927_ccfg_change(change, new)
-
-#define TX4938_SDRAMC_CR(ch)    TX4927_SDRAMC_CR(ch)
-#define TX4938_SDRAMC_BA(ch)    TX4927_SDRAMC_BA(ch)
-#define TX4938_SDRAMC_SIZE(ch)  TX4927_SDRAMC_SIZE(ch)
-
-#define TX4938_EBUSC_CR(ch)     TX4927_EBUSC_CR(ch)
-#define TX4938_EBUSC_BA(ch)     TX4927_EBUSC_BA(ch)
-#define TX4938_EBUSC_SIZE(ch)   TX4927_EBUSC_SIZE(ch)
-
-#define tx4938_get_mem_size() tx4927_get_mem_size()
-void tx4938_wdt_init(void);
-void tx4938_setup(void);
-void tx4938_time_init(unsigned int tmrnr);
-void tx4938_sio_init(unsigned int sclk, unsigned int cts_mask);
-void tx4938_spi_init(int busid);
-void tx4938_ethaddr_init(unsigned char *addr0, unsigned char *addr1);
-int tx4938_report_pciclk(void);
-void tx4938_report_pci1clk(void);
-int tx4938_pciclk66_setup(void);
-struct pci_dev;
-int tx4938_pcic1_map_irq(const struct pci_dev *dev, u8 slot);
-void tx4938_setup_pcierr_irq(void);
-void tx4938_irq_init(void);
-
-#endif
diff --git a/include/asm-mips/txx9irq.h b/include/asm-mips/txx9irq.h
deleted file mode 100644
index 5620879be37f..000000000000
--- a/include/asm-mips/txx9irq.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * include/asm-mips/txx9irq.h
- * TX39/TX49 interrupt controller definitions.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9IRQ_H
-#define __ASM_TXX9IRQ_H
-
-#include <irq.h>
-
-#ifdef CONFIG_IRQ_CPU
-#define TXX9_IRQ_BASE   (MIPS_CPU_IRQ_BASE + 8)
-#else
-#ifdef CONFIG_I8259
-#define TXX9_IRQ_BASE   (I8259A_IRQ_BASE + 16)
-#else
-#define TXX9_IRQ_BASE   0
-#endif
-#endif
-
-#ifdef CONFIG_CPU_TX39XX
-#define TXx9_MAX_IR 16
-#else
-#define TXx9_MAX_IR 32
-#endif
-
-void txx9_irq_init(unsigned long baseaddr);
-int txx9_irq(void);
-int txx9_irq_set_pri(int irc_irq, int new_pri);
-
-#endif /* __ASM_TXX9IRQ_H */
diff --git a/include/asm-mips/txx9pio.h b/include/asm-mips/txx9pio.h
deleted file mode 100644
index 3d6fa9f8d513..000000000000
--- a/include/asm-mips/txx9pio.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * include/asm-mips/txx9pio.h
- * TX39/TX49 PIO controller definitions.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9PIO_H
-#define __ASM_TXX9PIO_H
-
-#include <linux/types.h>
-
-struct txx9_pio_reg {
-        __u32 dout;
-        __u32 din;
-        __u32 dir;
-        __u32 od;
-        __u32 flag[2];
-        __u32 pol;
-        __u32 intc;
-        __u32 maskcpu;
-        __u32 maskext;
-};
-
-int txx9_gpio_init(unsigned long baseaddr,
-                   unsigned int base, unsigned int num);
-
-#endif /* __ASM_TXX9PIO_H */
diff --git a/include/asm-mips/txx9tmr.h b/include/asm-mips/txx9tmr.h
deleted file mode 100644
index 67f70a8f09bd..000000000000
--- a/include/asm-mips/txx9tmr.h
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * include/asm-mips/txx9tmr.h
- * TX39/TX49 timer controller definitions.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- */
-#ifndef __ASM_TXX9TMR_H
-#define __ASM_TXX9TMR_H
-
-#include <linux/types.h>
-
-struct txx9_tmr_reg {
-        u32 tcr;
-        u32 tisr;
-        u32 cpra;
-        u32 cprb;
-        u32 itmr;
-        u32 unused0[3];
-        u32 ccdr;
-        u32 unused1[3];
-        u32 pgmr;
-        u32 unused2[3];
-        u32 wtmr;
-        u32 unused3[43];
-        u32 trr;
-};
-
-/* TMTCR : Timer Control */
-#define TXx9_TMTCR_TCE          0x00000080
-#define TXx9_TMTCR_CCDE         0x00000040
-#define TXx9_TMTCR_CRE          0x00000020
-#define TXx9_TMTCR_ECES         0x00000008
-#define TXx9_TMTCR_CCS          0x00000004
-#define TXx9_TMTCR_TMODE_MASK   0x00000003
-#define TXx9_TMTCR_TMODE_ITVL   0x00000000
-#define TXx9_TMTCR_TMODE_PGEN   0x00000001
-#define TXx9_TMTCR_TMODE_WDOG   0x00000002
-
-/* TMTISR : Timer Int. Status */
-#define TXx9_TMTISR_TPIBS       0x00000004
-#define TXx9_TMTISR_TPIAS       0x00000002
-#define TXx9_TMTISR_TIIS        0x00000001
-
-/* TMITMR : Interval Timer Mode */
-#define TXx9_TMITMR_TIIE        0x00008000
-#define TXx9_TMITMR_TZCE        0x00000001
-
-/* TMWTMR : Watchdog Timer Mode */
-#define TXx9_TMWTMR_TWIE        0x00008000
-#define TXx9_TMWTMR_WDIS        0x00000080
-#define TXx9_TMWTMR_TWC         0x00000001
-
-void txx9_clocksource_init(unsigned long baseaddr,
-                           unsigned int imbusclk);
-void txx9_clockevent_init(unsigned long baseaddr, int irq,
-                          unsigned int imbusclk);
-void txx9_tmr_init(unsigned long baseaddr);
-
-#ifdef CONFIG_CPU_TX39XX
-#define TXX9_TIMER_BITS 24
-#else
-#define TXX9_TIMER_BITS 32
-#endif
-
-#endif /* __ASM_TXX9TMR_H */
diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h
deleted file mode 100644
index bcbb8d675af5..000000000000
--- a/include/asm-mips/types.h
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
- * Copyright (C) 1999 Silicon Graphics, Inc.
- */
-#ifndef _ASM_TYPES_H
-#define _ASM_TYPES_H
-
-#if _MIPS_SZLONG == 64
-# include <asm-generic/int-l64.h>
-#else
-# include <asm-generic/int-ll64.h>
-#endif
-
-#ifndef __ASSEMBLY__
-
-typedef unsigned short umode_t;
-
-#endif /* __ASSEMBLY__ */
-
-/*
- * These aren't exported outside the kernel to avoid name space clashes
- */
-#ifdef __KERNEL__
-
-#define BITS_PER_LONG _MIPS_SZLONG
-
-#ifndef __ASSEMBLY__
-
-#if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \
-    || defined(CONFIG_64BIT)
-typedef u64 dma_addr_t;
-#else
-typedef u32 dma_addr_t;
-#endif
-typedef u64 dma64_addr_t;
-
-/*
- * Don't use phys_t.  You've been warned.
- */
-#ifdef CONFIG_64BIT_PHYS_ADDR
-typedef unsigned long long phys_t;
-#else
-typedef unsigned long phys_t;
-#endif
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __KERNEL__ */
-
-#endif /* _ASM_TYPES_H */
diff --git a/include/asm-mips/uaccess.h b/include/asm-mips/uaccess.h
deleted file mode 100644
index 66523d610950..000000000000
--- a/include/asm-mips/uaccess.h
+++ /dev/null
@@ -1,852 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1996, 1997, 1998, 1999, 2000, 03, 04 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- * Copyright (C) 2007  Maciej W. Rozycki
- */
-#ifndef _ASM_UACCESS_H
-#define _ASM_UACCESS_H
-
-#include <linux/kernel.h>
-#include <linux/errno.h>
-#include <linux/thread_info.h>
-#include <asm-generic/uaccess.h>
-
-/*
- * The fs value determines whether argument validity checking should be
- * performed or not.  If get_fs() == USER_DS, checking is performed, with
- * get_fs() == KERNEL_DS, checking is bypassed.
- *
- * For historical reasons, these macros are grossly misnamed.
- */
-#ifdef CONFIG_32BIT
-
-#define __UA_LIMIT      0x80000000UL
-
-#define __UA_ADDR       ".word"
-#define __UA_LA         "la"
-#define __UA_ADDU       "addu"
-#define __UA_t0         "$8"
-#define __UA_t1         "$9"
-
-#endif /* CONFIG_32BIT */
-
-#ifdef CONFIG_64BIT
-
-#define __UA_LIMIT      (- TASK_SIZE)
-
-#define __UA_ADDR       ".dword"
-#define __UA_LA         "dla"
-#define __UA_ADDU       "daddu"
-#define __UA_t0         "$12"
-#define __UA_t1         "$13"
-
-#endif /* CONFIG_64BIT */
-
-/*
- * USER_DS is a bitmask that has the bits set that may not be set in a valid
- * userspace address.  Note that we limit 32-bit userspace to 0x7fff8000 but
- * the arithmetic we're doing only works if the limit is a power of two, so
- * we use 0x80000000 here on 32-bit kernels.  If a process passes an invalid
- * address in this range it's the process's problem, not ours :-)
- */
-
-#define KERNEL_DS       ((mm_segment_t) { 0UL })
-#define USER_DS         ((mm_segment_t) { __UA_LIMIT })
-
-#define VERIFY_READ    0
-#define VERIFY_WRITE   1
-
-#define get_ds()        (KERNEL_DS)
-#define get_fs()        (current_thread_info()->addr_limit)
-#define set_fs(x)       (current_thread_info()->addr_limit = (x))
-
-#define segment_eq(a, b)        ((a).seg == (b).seg)
-
-
-/*
- * Is a address valid? This does a straighforward calculation rather
- * than tests.
- *
- * Address valid if:
- *  - "addr" doesn't have any high-bits set
- *  - AND "size" doesn't have any high-bits set
- *  - AND "addr+size" doesn't have any high-bits set
- *  - OR we are in kernel mode.
- *
- * __ua_size() is a trick to avoid runtime checking of positive constant
- * sizes; for those we already know at compile time that the size is ok.
- */
-#define __ua_size(size)                                                 \
-        ((__builtin_constant_p(size) && (signed long) (size) > 0) ? 0 : (size))
-
-/*
- * access_ok: - Checks if a user space pointer is valid
- * @type: Type of access: %VERIFY_READ or %VERIFY_WRITE.  Note that
- *        %VERIFY_WRITE is a superset of %VERIFY_READ - if it is safe
- *        to write to a block, it is always safe to read from it.
- * @addr: User space pointer to start of block to check
- * @size: Size of block to check
- *
- * Context: User context only.  This function may sleep.
- *
- * Checks if a pointer to a block of memory in user space is valid.
- *
- * Returns true (nonzero) if the memory block may be valid, false (zero)
- * if it is definitely invalid.
- *
- * Note that, depending on architecture, this function probably just
- * checks that the pointer is in the user space range - after calling
- * this function, memory access functions may still return -EFAULT.
- */
-
-#define __access_mask get_fs().seg
-
-#define __access_ok(addr, size, mask)                                   \
-        (((signed long)((mask) & ((addr) | ((addr) + (size)) | __ua_size(size)))) == 0)
-
-#define access_ok(type, addr, size)                                     \
-        likely(__access_ok((unsigned long)(addr), (size), __access_mask))
-
-/*
- * put_user: - Write a simple value into user space.
- * @x:   Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple value from kernel space to user
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define put_user(x,ptr) \
-        __put_user_check((x), (ptr), sizeof(*(ptr)))
-
-/*
- * get_user: - Get a simple variable from user space.
- * @x:   Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple variable from user space to kernel
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define get_user(x,ptr) \
-        __get_user_check((x), (ptr), sizeof(*(ptr)))
-
-/*
- * __put_user: - Write a simple value into user space, with less checking.
- * @x:   Value to copy to user space.
- * @ptr: Destination address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple value from kernel space to user
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and @x must be assignable
- * to the result of dereferencing @ptr.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- */
-#define __put_user(x,ptr) \
-        __put_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-/*
- * __get_user: - Get a simple variable from user space, with less checking.
- * @x:   Variable to store result.
- * @ptr: Source address, in user space.
- *
- * Context: User context only.  This function may sleep.
- *
- * This macro copies a single simple variable from user space to kernel
- * space.  It supports simple types like char and int, but not larger
- * data types like structures or arrays.
- *
- * @ptr must have pointer-to-simple-variable type, and the result of
- * dereferencing @ptr must be assignable to @x without a cast.
- *
- * Caller must check the pointer with access_ok() before calling this
- * function.
- *
- * Returns zero on success, or -EFAULT on error.
- * On error, the variable @x is set to zero.
- */
-#define __get_user(x,ptr) \
-        __get_user_nocheck((x), (ptr), sizeof(*(ptr)))
-
-struct __large_struct { unsigned long buf[100]; };
-#define __m(x) (*(struct __large_struct __user *)(x))
-
-/*
- * Yuck.  We need two variants, one for 64bit operation and one
- * for 32 bit mode and old iron.
- */
-#ifdef CONFIG_32BIT
-#define __GET_USER_DW(val, ptr) __get_user_asm_ll32(val, ptr)
-#endif
-#ifdef CONFIG_64BIT
-#define __GET_USER_DW(val, ptr) __get_user_asm(val, "ld", ptr)
-#endif
-
-extern void __get_user_unknown(void);
-
-#define __get_user_common(val, size, ptr)                               \
-do {                                                                    \
-        switch (size) {                                                 \
-        case 1: __get_user_asm(val, "lb", ptr); break;                  \
-        case 2: __get_user_asm(val, "lh", ptr); break;                  \
-        case 4: __get_user_asm(val, "lw", ptr); break;                  \
-        case 8: __GET_USER_DW(val, ptr); break;                         \
-        default: __get_user_unknown(); break;                           \
-        }                                                               \
-} while (0)
-
-#define __get_user_nocheck(x, ptr, size)                                \
-({                                                                      \
-        long __gu_err;                                                  \
-                                                                        \
-        __get_user_common((x), size, ptr);                              \
-        __gu_err;                                                       \
-})
-
-#define __get_user_check(x, ptr, size)                                  \
-({                                                                      \
-        long __gu_err = -EFAULT;                                        \
-        const __typeof__(*(ptr)) __user * __gu_ptr = (ptr);             \
-                                                                        \
-        if (likely(access_ok(VERIFY_READ,  __gu_ptr, size)))            \
-                __get_user_common((x), size, __gu_ptr);                 \
-                                                                        \
-        __gu_err;                                                       \
-})
-
-#define __get_user_asm(val, insn, addr)                                 \
-{                                                                       \
-        long __gu_tmp;                                                  \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "1:     " insn "        %1, %3                          \n"     \
-        "2:                                                     \n"     \
-        "       .section .fixup,\"ax\"                          \n"     \
-        "3:     li      %0, %4                                  \n"     \
-        "       j       2b                                      \n"     \
-        "       .previous                                       \n"     \
-        "       .section __ex_table,\"a\"                       \n"     \
-        "       "__UA_ADDR "\t1b, 3b                            \n"     \
-        "       .previous                                       \n"     \
-        : "=r" (__gu_err), "=r" (__gu_tmp)                              \
-        : "0" (0), "o" (__m(addr)), "i" (-EFAULT));                     \
-                                                                        \
-        (val) = (__typeof__(*(addr))) __gu_tmp;                         \
-}
-
-/*
- * Get a long long 64 using 32 bit registers.
- */
-#define __get_user_asm_ll32(val, addr)                                  \
-{                                                                       \
-        union {                                                         \
-                unsigned long long      l;                              \
-                __typeof__(*(addr))     t;                              \
-        } __gu_tmp;                                                     \
-                                                                        \
-        __asm__ __volatile__(                                           \
-        "1:     lw      %1, (%3)                                \n"     \
-        "2:     lw      %D1, 4(%3)                              \n"     \
-        "3:     .section        .fixup,\"ax\"                   \n"     \
-        "4:     li      %0, %4                                  \n"     \
-        "       move    %1, $0                                  \n"     \
-        "       move    %D1, $0                                 \n"     \
-        "       j       3b                                      \n"     \
-        "       .previous                                       \n"     \
-        "       .section        __ex_table,\"a\"                \n"     \
-        "       " __UA_ADDR "   1b, 4b                          \n"     \
-        "       " __UA_ADDR "   2b, 4b                          \n"     \
-        "       .previous                                       \n"     \
-        : "=r" (__gu_err), "=&r" (__gu_tmp.l)                           \
-        : "0" (0), "r" (addr), "i" (-EFAULT));                          \
-                                                                        \
-        (val) = __gu_tmp.t;                                             \
-}
-
-/*
- * Yuck.  We need two variants, one for 64bit operation and one
- * for 32 bit mode and old iron.
- */
-#ifdef CONFIG_32BIT
-#define __PUT_USER_DW(ptr) __put_user_asm_ll32(ptr)
-#endif
-#ifdef CONFIG_64BIT
-#define __PUT_USER_DW(ptr) __put_user_asm("sd", ptr)
-#endif
-
-#define __put_user_nocheck(x, ptr, size)                                \
-({                                                                      \
-        __typeof__(*(ptr)) __pu_val;                                    \
-        long __pu_err = 0;                                              \
-                                                                        \
-        __pu_val = (x);                                                 \
-        switch (size) {                                                 \
-        case 1: __put_user_asm("sb", ptr); break;                       \
-        case 2: __put_user_asm("sh", ptr); break;                       \
-        case 4: __put_user_asm("sw", ptr); break;                       \
-        case 8: __PUT_USER_DW(ptr); break;                              \
-        default: __put_user_unknown(); break;                           \
-        }                                                               \
-        __pu_err;                                                       \
-})
-
-#define __put_user_check(x, ptr, size)                                  \
-({                                                                      \
-        __typeof__(*(ptr)) __user *__pu_addr = (ptr);                   \
-        __typeof__(*(ptr)) __pu_val = (x);                              \
-        long __pu_err = -EFAULT;                                        \
-                                                                        \
-        if (likely(access_ok(VERIFY_WRITE,  __pu_addr, size))) {        \
-                switch (size) {                                         \
-                case 1: __put_user_asm("sb", __pu_addr); break;         \
-                case 2: __put_user_asm("sh", __pu_addr); break;         \
-                case 4: __put_user_asm("sw", __pu_addr); break;         \
-                case 8: __PUT_USER_DW(__pu_addr); break;                \
-                default: __put_user_unknown(); break;                   \
-                }                                                       \
-        }                                                               \
-        __pu_err;                                                       \
-})
-
-#define __put_user_asm(insn, ptr)                                       \
-{                                                                       \
-        __asm__ __volatile__(                                           \
-        "1:     " insn "        %z2, %3         # __put_user_asm\n"     \
-        "2:                                                     \n"     \
-        "       .section        .fixup,\"ax\"                   \n"     \
-        "3:     li      %0, %4                                  \n"     \
-        "       j       2b                                      \n"     \
-        "       .previous                                       \n"     \
-        "       .section        __ex_table,\"a\"                \n"     \
-        "       " __UA_ADDR "   1b, 3b                          \n"     \
-        "       .previous                                       \n"     \
-        : "=r" (__pu_err)                                               \
-        : "0" (0), "Jr" (__pu_val), "o" (__m(ptr)),                     \
-          "i" (-EFAULT));                                               \
-}
-
-#define __put_user_asm_ll32(ptr)                                        \
-{                                                                       \
-        __asm__ __volatile__(                                           \
-        "1:     sw      %2, (%3)        # __put_user_asm_ll32   \n"     \
-        "2:     sw      %D2, 4(%3)                              \n"     \
-        "3:                                                     \n"     \
-        "       .section        .fixup,\"ax\"                   \n"     \
-        "4:     li      %0, %4                                  \n"     \
-        "       j       3b                                      \n"     \
-        "       .previous                                       \n"     \
-        "       .section        __ex_table,\"a\"                \n"     \
-        "       " __UA_ADDR "   1b, 4b                          \n"     \
-        "       " __UA_ADDR "   2b, 4b                          \n"     \
-        "       .previous"                                              \
-        : "=r" (__pu_err)                                               \
-        : "0" (0), "r" (__pu_val), "r" (ptr),                           \
-          "i" (-EFAULT));                                               \
-}
-
-extern void __put_user_unknown(void);
-
-/*
- * We're generating jump to subroutines which will be outside the range of
- * jump instructions
- */
-#ifdef MODULE
-#define __MODULE_JAL(destination)                                       \
-        ".set\tnoat\n\t"                                                \
-        __UA_LA "\t$1, " #destination "\n\t"                            \
-        "jalr\t$1\n\t"                                                  \
-        ".set\tat\n\t"
-#else
-#define __MODULE_JAL(destination)                                       \
-        "jal\t" #destination "\n\t"
-#endif
-
-#ifndef CONFIG_CPU_DADDI_WORKAROUNDS
-#define DADDI_SCRATCH "$0"
-#else
-#define DADDI_SCRATCH "$3"
-#endif
-
-extern size_t __copy_user(void *__to, const void *__from, size_t __n);
-
-#define __invoke_copy_to_user(to, from, n)                              \
-({                                                                      \
-        register void __user *__cu_to_r __asm__("$4");                  \
-        register const void *__cu_from_r __asm__("$5");                 \
-        register long __cu_len_r __asm__("$6");                         \
-                                                                        \
-        __cu_to_r = (to);                                               \
-        __cu_from_r = (from);                                           \
-        __cu_len_r = (n);                                               \
-        __asm__ __volatile__(                                           \
-        __MODULE_JAL(__copy_user)                                       \
-        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
-        :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
-          DADDI_SCRATCH, "memory");                                     \
-        __cu_len_r;                                                     \
-})
-
-/*
- * __copy_to_user: - Copy a block of data into user space, with less checking.
- * @to:   Destination address, in user space.
- * @from: Source address, in kernel space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.  This function may sleep.
- *
- * Copy data from kernel space to user space.  Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be copied.
- * On success, this will be zero.
- */
-#define __copy_to_user(to, from, n)                                     \
-({                                                                      \
-        void __user *__cu_to;                                           \
-        const void *__cu_from;                                          \
-        long __cu_len;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
-        __cu_len;                                                       \
-})
-
-extern size_t __copy_user_inatomic(void *__to, const void *__from, size_t __n);
-
-#define __copy_to_user_inatomic(to, from, n)                            \
-({                                                                      \
-        void __user *__cu_to;                                           \
-        const void *__cu_from;                                          \
-        long __cu_len;                                                  \
-                                                                        \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        __cu_len = __invoke_copy_to_user(__cu_to, __cu_from, __cu_len); \
-        __cu_len;                                                       \
-})
-
-#define __copy_from_user_inatomic(to, from, n)                          \
-({                                                                      \
-        void *__cu_to;                                                  \
-        const void __user *__cu_from;                                   \
-        long __cu_len;                                                  \
-                                                                        \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        __cu_len = __invoke_copy_from_user_inatomic(__cu_to, __cu_from, \
-                                                    __cu_len);          \
-        __cu_len;                                                       \
-})
-
-/*
- * copy_to_user: - Copy a block of data into user space.
- * @to:   Destination address, in user space.
- * @from: Source address, in kernel space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.  This function may sleep.
- *
- * Copy data from kernel space to user space.
- *
- * Returns number of bytes that could not be copied.
- * On success, this will be zero.
- */
-#define copy_to_user(to, from, n)                                       \
-({                                                                      \
-        void __user *__cu_to;                                           \
-        const void *__cu_from;                                          \
-        long __cu_len;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        if (access_ok(VERIFY_WRITE, __cu_to, __cu_len))                 \
-                __cu_len = __invoke_copy_to_user(__cu_to, __cu_from,    \
-                                                 __cu_len);             \
-        __cu_len;                                                       \
-})
-
-#define __invoke_copy_from_user(to, from, n)                            \
-({                                                                      \
-        register void *__cu_to_r __asm__("$4");                         \
-        register const void __user *__cu_from_r __asm__("$5");          \
-        register long __cu_len_r __asm__("$6");                         \
-                                                                        \
-        __cu_to_r = (to);                                               \
-        __cu_from_r = (from);                                           \
-        __cu_len_r = (n);                                               \
-        __asm__ __volatile__(                                           \
-        ".set\tnoreorder\n\t"                                           \
-        __MODULE_JAL(__copy_user)                                       \
-        ".set\tnoat\n\t"                                                \
-        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
-        ".set\tat\n\t"                                                  \
-        ".set\treorder"                                                 \
-        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
-        :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
-          DADDI_SCRATCH, "memory");                                     \
-        __cu_len_r;                                                     \
-})
-
-#define __invoke_copy_from_user_inatomic(to, from, n)                   \
-({                                                                      \
-        register void *__cu_to_r __asm__("$4");                         \
-        register const void __user *__cu_from_r __asm__("$5");          \
-        register long __cu_len_r __asm__("$6");                         \
-                                                                        \
-        __cu_to_r = (to);                                               \
-        __cu_from_r = (from);                                           \
-        __cu_len_r = (n);                                               \
-        __asm__ __volatile__(                                           \
-        ".set\tnoreorder\n\t"                                           \
-        __MODULE_JAL(__copy_user_inatomic)                              \
-        ".set\tnoat\n\t"                                                \
-        __UA_ADDU "\t$1, %1, %2\n\t"                                    \
-        ".set\tat\n\t"                                                  \
-        ".set\treorder"                                                 \
-        : "+r" (__cu_to_r), "+r" (__cu_from_r), "+r" (__cu_len_r)       \
-        :                                                               \
-        : "$8", "$9", "$10", "$11", "$12", "$15", "$24", "$31",         \
-          DADDI_SCRATCH, "memory");                                     \
-        __cu_len_r;                                                     \
-})
-
-/*
- * __copy_from_user: - Copy a block of data from user space, with less checking.
- * @to:   Destination address, in kernel space.
- * @from: Source address, in user space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.  This function may sleep.
- *
- * Copy data from user space to kernel space.  Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be copied.
- * On success, this will be zero.
- *
- * If some data could not be copied, this function will pad the copied
- * data to the requested size using zero bytes.
- */
-#define __copy_from_user(to, from, n)                                   \
-({                                                                      \
-        void *__cu_to;                                                  \
-        const void __user *__cu_from;                                   \
-        long __cu_len;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,          \
-                                           __cu_len);                   \
-        __cu_len;                                                       \
-})
-
-/*
- * copy_from_user: - Copy a block of data from user space.
- * @to:   Destination address, in kernel space.
- * @from: Source address, in user space.
- * @n:    Number of bytes to copy.
- *
- * Context: User context only.  This function may sleep.
- *
- * Copy data from user space to kernel space.
- *
- * Returns number of bytes that could not be copied.
- * On success, this will be zero.
- *
- * If some data could not be copied, this function will pad the copied
- * data to the requested size using zero bytes.
- */
-#define copy_from_user(to, from, n)                                     \
-({                                                                      \
-        void *__cu_to;                                                  \
-        const void __user *__cu_from;                                   \
-        long __cu_len;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        if (access_ok(VERIFY_READ, __cu_from, __cu_len))                \
-                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
-                                                   __cu_len);           \
-        __cu_len;                                                       \
-})
-
-#define __copy_in_user(to, from, n)     __copy_from_user(to, from, n)
-
-#define copy_in_user(to, from, n)                                       \
-({                                                                      \
-        void __user *__cu_to;                                           \
-        const void __user *__cu_from;                                   \
-        long __cu_len;                                                  \
-                                                                        \
-        might_sleep();                                                  \
-        __cu_to = (to);                                                 \
-        __cu_from = (from);                                             \
-        __cu_len = (n);                                                 \
-        if (likely(access_ok(VERIFY_READ, __cu_from, __cu_len) &&       \
-                   access_ok(VERIFY_WRITE, __cu_to, __cu_len)))         \
-                __cu_len = __invoke_copy_from_user(__cu_to, __cu_from,  \
-                                                   __cu_len);           \
-        __cu_len;                                                       \
-})
-
-/*
- * __clear_user: - Zero a block of memory in user space, with less checking.
- * @to:   Destination address, in user space.
- * @n:    Number of bytes to zero.
- *
- * Zero a block of memory in user space.  Caller must check
- * the specified block with access_ok() before calling this function.
- *
- * Returns number of bytes that could not be cleared.
- * On success, this will be zero.
- */
-static inline __kernel_size_t
-__clear_user(void __user *addr, __kernel_size_t size)
-{
-        __kernel_size_t res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                "move\t$5, $0\n\t"
-                "move\t$6, %2\n\t"
-                __MODULE_JAL(__bzero)
-                "move\t%0, $6"
-                : "=r" (res)
-                : "r" (addr), "r" (size)
-                : "$4", "$5", "$6", __UA_t0, __UA_t1, "$31");
-
-        return res;
-}
-
-#define clear_user(addr,n)                                              \
-({                                                                      \
-        void __user * __cl_addr = (addr);                               \
-        unsigned long __cl_size = (n);                                  \
-        if (__cl_size && access_ok(VERIFY_WRITE,                        \
-                ((unsigned long)(__cl_addr)), __cl_size))               \
-                __cl_size = __clear_user(__cl_addr, __cl_size);         \
-        __cl_size;                                                      \
-})
-
-/*
- * __strncpy_from_user: - Copy a NUL terminated string from userspace, with less checking.
- * @dst:   Destination address, in kernel space.  This buffer must be at
- *         least @count bytes long.
- * @src:   Source address, in user space.
- * @count: Maximum number of bytes to copy, including the trailing NUL.
- *
- * Copies a NUL-terminated string from userspace to kernel space.
- * Caller must check the specified block with access_ok() before calling
- * this function.
- *
- * On success, returns the length of the string (not including the trailing
- * NUL).
- *
- * If access to userspace fails, returns -EFAULT (some data may have been
- * copied).
- *
- * If @count is smaller than the length of the string, copies @count bytes
- * and returns @count.
- */
-static inline long
-__strncpy_from_user(char *__to, const char __user *__from, long __len)
-{
-        long res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
-                "move\t$6, %3\n\t"
-                __MODULE_JAL(__strncpy_from_user_nocheck_asm)
-                "move\t%0, $2"
-                : "=r" (res)
-                : "r" (__to), "r" (__from), "r" (__len)
-                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
-
-        return res;
-}
-
-/*
- * strncpy_from_user: - Copy a NUL terminated string from userspace.
- * @dst:   Destination address, in kernel space.  This buffer must be at
- *         least @count bytes long.
- * @src:   Source address, in user space.
- * @count: Maximum number of bytes to copy, including the trailing NUL.
- *
- * Copies a NUL-terminated string from userspace to kernel space.
- *
- * On success, returns the length of the string (not including the trailing
- * NUL).
- *
- * If access to userspace fails, returns -EFAULT (some data may have been
- * copied).
- *
- * If @count is smaller than the length of the string, copies @count bytes
- * and returns @count.
- */
-static inline long
-strncpy_from_user(char *__to, const char __user *__from, long __len)
-{
-        long res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
-                "move\t$6, %3\n\t"
-                __MODULE_JAL(__strncpy_from_user_asm)
-                "move\t%0, $2"
-                : "=r" (res)
-                : "r" (__to), "r" (__from), "r" (__len)
-                : "$2", "$3", "$4", "$5", "$6", __UA_t0, "$31", "memory");
-
-        return res;
-}
-
-/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-static inline long __strlen_user(const char __user *s)
-{
-        long res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                __MODULE_JAL(__strlen_user_nocheck_asm)
-                "move\t%0, $2"
-                : "=r" (res)
-                : "r" (s)
-                : "$2", "$4", __UA_t0, "$31");
-
-        return res;
-}
-
-/*
- * strlen_user: - Get the size of a string in user space.
- * @str: The string to measure.
- *
- * Context: User context only.  This function may sleep.
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- *
- * If there is a limit on the length of a valid string, you may wish to
- * consider using strnlen_user() instead.
- */
-static inline long strlen_user(const char __user *s)
-{
-        long res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                __MODULE_JAL(__strlen_user_asm)
-                "move\t%0, $2"
-                : "=r" (res)
-                : "r" (s)
-                : "$2", "$4", __UA_t0, "$31");
-
-        return res;
-}
-
-/* Returns: 0 if bad, string length+1 (memory size) of string if ok */
-static inline long __strnlen_user(const char __user *s, long n)
-{
-        long res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
-                __MODULE_JAL(__strnlen_user_nocheck_asm)
-                "move\t%0, $2"
-                : "=r" (res)
-                : "r" (s), "r" (n)
-                : "$2", "$4", "$5", __UA_t0, "$31");
-
-        return res;
-}
-
-/*
- * strlen_user: - Get the size of a string in user space.
- * @str: The string to measure.
- *
- * Context: User context only.  This function may sleep.
- *
- * Get the size of a NUL-terminated string in user space.
- *
- * Returns the size of the string INCLUDING the terminating NUL.
- * On exception, returns 0.
- *
- * If there is a limit on the length of a valid string, you may wish to
- * consider using strnlen_user() instead.
- */
-static inline long strnlen_user(const char __user *s, long n)
-{
-        long res;
-
-        might_sleep();
-        __asm__ __volatile__(
-                "move\t$4, %1\n\t"
-                "move\t$5, %2\n\t"
-                __MODULE_JAL(__strnlen_user_asm)
-                "move\t%0, $2"
-                : "=r" (res)
-                : "r" (s), "r" (n)
-                : "$2", "$4", "$5", __UA_t0, "$31");
-
-        return res;
-}
-
-struct exception_table_entry
-{
-        unsigned long insn;
-        unsigned long nextinsn;
-};
-
-extern int fixup_exception(struct pt_regs *regs);
-
-#endif /* _ASM_UACCESS_H */
diff --git a/include/asm-mips/ucontext.h b/include/asm-mips/ucontext.h
deleted file mode 100644
index 8a4b20e88b81..000000000000
--- a/include/asm-mips/ucontext.h
+++ /dev/null
@@ -1,21 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Low level exception handling
- *
- * Copyright (C) 1998, 1999 by Ralf Baechle
- */
-#ifndef _ASM_UCONTEXT_H
-#define _ASM_UCONTEXT_H
-
-struct ucontext {
-        unsigned long     uc_flags;
-        struct ucontext  *uc_link;
-        stack_t           uc_stack;
-        struct sigcontext uc_mcontext;
-        sigset_t          uc_sigmask;   /* mask last for extensibility */
-};
-
-#endif /* _ASM_UCONTEXT_H */
diff --git a/include/asm-mips/unaligned.h b/include/asm-mips/unaligned.h
deleted file mode 100644
index 792404948571..000000000000
--- a/include/asm-mips/unaligned.h
+++ /dev/null
@@ -1,28 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2007 Ralf Baechle (ralf@linux-mips.org)
- */
-#ifndef _ASM_MIPS_UNALIGNED_H
-#define _ASM_MIPS_UNALIGNED_H
-
-#include <linux/compiler.h>
-#if defined(__MIPSEB__)
-# include <linux/unaligned/be_struct.h>
-# include <linux/unaligned/le_byteshift.h>
-# include <linux/unaligned/generic.h>
-# define get_unaligned  __get_unaligned_be
-# define put_unaligned  __put_unaligned_be
-#elif defined(__MIPSEL__)
-# include <linux/unaligned/le_struct.h>
-# include <linux/unaligned/be_byteshift.h>
-# include <linux/unaligned/generic.h>
-# define get_unaligned  __get_unaligned_le
-# define put_unaligned  __put_unaligned_le
-#else
-#  error "MIPS, but neither __MIPSEB__, nor __MIPSEL__???"
-#endif
-
-#endif /* _ASM_MIPS_UNALIGNED_H */
diff --git a/include/asm-mips/unistd.h b/include/asm-mips/unistd.h
deleted file mode 100644
index 4964c82f85f9..000000000000
--- a/include/asm-mips/unistd.h
+++ /dev/null
@@ -1,1019 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1995, 96, 97, 98, 99, 2000 by Ralf Baechle
- * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
- *
- * Changed system calls macros _syscall5 - _syscall7 to push args 5 to 7 onto
- * the stack. Robin Farine for ACN S.A, Copyright (C) 1996 by ACN S.A
- */
-#ifndef _ASM_UNISTD_H
-#define _ASM_UNISTD_H
-
-#include <asm/sgidefs.h>
-
-#if _MIPS_SIM == _MIPS_SIM_ABI32
-
-/*
- * Linux o32 style syscalls are in the range from 4000 to 4999.
- */
-#define __NR_Linux                      4000
-#define __NR_syscall                    (__NR_Linux +   0)
-#define __NR_exit                       (__NR_Linux +   1)
-#define __NR_fork                       (__NR_Linux +   2)
-#define __NR_read                       (__NR_Linux +   3)
-#define __NR_write                      (__NR_Linux +   4)
-#define __NR_open                       (__NR_Linux +   5)
-#define __NR_close                      (__NR_Linux +   6)
-#define __NR_waitpid                    (__NR_Linux +   7)
-#define __NR_creat                      (__NR_Linux +   8)
-#define __NR_link                       (__NR_Linux +   9)
-#define __NR_unlink                     (__NR_Linux +  10)
-#define __NR_execve                     (__NR_Linux +  11)
-#define __NR_chdir                      (__NR_Linux +  12)
-#define __NR_time                       (__NR_Linux +  13)
-#define __NR_mknod                      (__NR_Linux +  14)
-#define __NR_chmod                      (__NR_Linux +  15)
-#define __NR_lchown                     (__NR_Linux +  16)
-#define __NR_break                      (__NR_Linux +  17)
-#define __NR_unused18                   (__NR_Linux +  18)
-#define __NR_lseek                      (__NR_Linux +  19)
-#define __NR_getpid                     (__NR_Linux +  20)
-#define __NR_mount                      (__NR_Linux +  21)
-#define __NR_umount                     (__NR_Linux +  22)
-#define __NR_setuid                     (__NR_Linux +  23)
-#define __NR_getuid                     (__NR_Linux +  24)
-#define __NR_stime                      (__NR_Linux +  25)
-#define __NR_ptrace                     (__NR_Linux +  26)
-#define __NR_alarm                      (__NR_Linux +  27)
-#define __NR_unused28                   (__NR_Linux +  28)
-#define __NR_pause                      (__NR_Linux +  29)
-#define __NR_utime                      (__NR_Linux +  30)
-#define __NR_stty                       (__NR_Linux +  31)
-#define __NR_gtty                       (__NR_Linux +  32)
-#define __NR_access                     (__NR_Linux +  33)
-#define __NR_nice                       (__NR_Linux +  34)
-#define __NR_ftime                      (__NR_Linux +  35)
-#define __NR_sync                       (__NR_Linux +  36)
-#define __NR_kill                       (__NR_Linux +  37)
-#define __NR_rename                     (__NR_Linux +  38)
-#define __NR_mkdir                      (__NR_Linux +  39)
-#define __NR_rmdir                      (__NR_Linux +  40)
-#define __NR_dup                        (__NR_Linux +  41)
-#define __NR_pipe                       (__NR_Linux +  42)
-#define __NR_times                      (__NR_Linux +  43)
-#define __NR_prof                       (__NR_Linux +  44)
-#define __NR_brk                        (__NR_Linux +  45)
-#define __NR_setgid                     (__NR_Linux +  46)
-#define __NR_getgid                     (__NR_Linux +  47)
-#define __NR_signal                     (__NR_Linux +  48)
-#define __NR_geteuid                    (__NR_Linux +  49)
-#define __NR_getegid                    (__NR_Linux +  50)
-#define __NR_acct                       (__NR_Linux +  51)
-#define __NR_umount2                    (__NR_Linux +  52)
-#define __NR_lock                       (__NR_Linux +  53)
-#define __NR_ioctl                      (__NR_Linux +  54)
-#define __NR_fcntl                      (__NR_Linux +  55)
-#define __NR_mpx                        (__NR_Linux +  56)
-#define __NR_setpgid                    (__NR_Linux +  57)
-#define __NR_ulimit                     (__NR_Linux +  58)
-#define __NR_unused59                   (__NR_Linux +  59)
-#define __NR_umask                      (__NR_Linux +  60)
-#define __NR_chroot                     (__NR_Linux +  61)
-#define __NR_ustat                      (__NR_Linux +  62)
-#define __NR_dup2                       (__NR_Linux +  63)
-#define __NR_getppid                    (__NR_Linux +  64)
-#define __NR_getpgrp                    (__NR_Linux +  65)
-#define __NR_setsid                     (__NR_Linux +  66)
-#define __NR_sigaction                  (__NR_Linux +  67)
-#define __NR_sgetmask                   (__NR_Linux +  68)
-#define __NR_ssetmask                   (__NR_Linux +  69)
-#define __NR_setreuid                   (__NR_Linux +  70)
-#define __NR_setregid                   (__NR_Linux +  71)
-#define __NR_sigsuspend                 (__NR_Linux +  72)
-#define __NR_sigpending                 (__NR_Linux +  73)
-#define __NR_sethostname                (__NR_Linux +  74)
-#define __NR_setrlimit                  (__NR_Linux +  75)
-#define __NR_getrlimit                  (__NR_Linux +  76)
-#define __NR_getrusage                  (__NR_Linux +  77)
-#define __NR_gettimeofday               (__NR_Linux +  78)
-#define __NR_settimeofday               (__NR_Linux +  79)
-#define __NR_getgroups                  (__NR_Linux +  80)
-#define __NR_setgroups                  (__NR_Linux +  81)
-#define __NR_reserved82                 (__NR_Linux +  82)
-#define __NR_symlink                    (__NR_Linux +  83)
-#define __NR_unused84                   (__NR_Linux +  84)
-#define __NR_readlink                   (__NR_Linux +  85)
-#define __NR_uselib                     (__NR_Linux +  86)
-#define __NR_swapon                     (__NR_Linux +  87)
-#define __NR_reboot                     (__NR_Linux +  88)
-#define __NR_readdir                    (__NR_Linux +  89)
-#define __NR_mmap                       (__NR_Linux +  90)
-#define __NR_munmap                     (__NR_Linux +  91)
-#define __NR_truncate                   (__NR_Linux +  92)
-#define __NR_ftruncate                  (__NR_Linux +  93)
-#define __NR_fchmod                     (__NR_Linux +  94)
-#define __NR_fchown                     (__NR_Linux +  95)
-#define __NR_getpriority                (__NR_Linux +  96)
-#define __NR_setpriority                (__NR_Linux +  97)
-#define __NR_profil                     (__NR_Linux +  98)
-#define __NR_statfs                     (__NR_Linux +  99)
-#define __NR_fstatfs                    (__NR_Linux + 100)
-#define __NR_ioperm                     (__NR_Linux + 101)
-#define __NR_socketcall                 (__NR_Linux + 102)
-#define __NR_syslog                     (__NR_Linux + 103)
-#define __NR_setitimer                  (__NR_Linux + 104)
-#define __NR_getitimer                  (__NR_Linux + 105)
-#define __NR_stat                       (__NR_Linux + 106)
-#define __NR_lstat                      (__NR_Linux + 107)
-#define __NR_fstat                      (__NR_Linux + 108)
-#define __NR_unused109                  (__NR_Linux + 109)
-#define __NR_iopl                       (__NR_Linux + 110)
-#define __NR_vhangup                    (__NR_Linux + 111)
-#define __NR_idle                       (__NR_Linux + 112)
-#define __NR_vm86                       (__NR_Linux + 113)
-#define __NR_wait4                      (__NR_Linux + 114)
-#define __NR_swapoff                    (__NR_Linux + 115)
-#define __NR_sysinfo                    (__NR_Linux + 116)
-#define __NR_ipc                        (__NR_Linux + 117)
-#define __NR_fsync                      (__NR_Linux + 118)
-#define __NR_sigreturn                  (__NR_Linux + 119)
-#define __NR_clone                      (__NR_Linux + 120)
-#define __NR_setdomainname              (__NR_Linux + 121)
-#define __NR_uname                      (__NR_Linux + 122)
-#define __NR_modify_ldt                 (__NR_Linux + 123)
-#define __NR_adjtimex                   (__NR_Linux + 124)
-#define __NR_mprotect                   (__NR_Linux + 125)
-#define __NR_sigprocmask                (__NR_Linux + 126)
-#define __NR_create_module              (__NR_Linux + 127)
-#define __NR_init_module                (__NR_Linux + 128)
-#define __NR_delete_module              (__NR_Linux + 129)
-#define __NR_get_kernel_syms            (__NR_Linux + 130)
-#define __NR_quotactl                   (__NR_Linux + 131)
-#define __NR_getpgid                    (__NR_Linux + 132)
-#define __NR_fchdir                     (__NR_Linux + 133)
-#define __NR_bdflush                    (__NR_Linux + 134)
-#define __NR_sysfs                      (__NR_Linux + 135)
-#define __NR_personality                (__NR_Linux + 136)
-#define __NR_afs_syscall                (__NR_Linux + 137) /* Syscall for Andrew File System */
-#define __NR_setfsuid                   (__NR_Linux + 138)
-#define __NR_setfsgid                   (__NR_Linux + 139)
-#define __NR__llseek                    (__NR_Linux + 140)
-#define __NR_getdents                   (__NR_Linux + 141)
-#define __NR__newselect                 (__NR_Linux + 142)
-#define __NR_flock                      (__NR_Linux + 143)
-#define __NR_msync                      (__NR_Linux + 144)
-#define __NR_readv                      (__NR_Linux + 145)
-#define __NR_writev                     (__NR_Linux + 146)
-#define __NR_cacheflush                 (__NR_Linux + 147)
-#define __NR_cachectl                   (__NR_Linux + 148)
-#define __NR_sysmips                    (__NR_Linux + 149)
-#define __NR_unused150                  (__NR_Linux + 150)
-#define __NR_getsid                     (__NR_Linux + 151)
-#define __NR_fdatasync                  (__NR_Linux + 152)
-#define __NR__sysctl                    (__NR_Linux + 153)
-#define __NR_mlock                      (__NR_Linux + 154)
-#define __NR_munlock                    (__NR_Linux + 155)
-#define __NR_mlockall                   (__NR_Linux + 156)
-#define __NR_munlockall                 (__NR_Linux + 157)
-#define __NR_sched_setparam             (__NR_Linux + 158)
-#define __NR_sched_getparam             (__NR_Linux + 159)
-#define __NR_sched_setscheduler         (__NR_Linux + 160)
-#define __NR_sched_getscheduler         (__NR_Linux + 161)
-#define __NR_sched_yield                (__NR_Linux + 162)
-#define __NR_sched_get_priority_max     (__NR_Linux + 163)
-#define __NR_sched_get_priority_min     (__NR_Linux + 164)
-#define __NR_sched_rr_get_interval      (__NR_Linux + 165)
-#define __NR_nanosleep                  (__NR_Linux + 166)
-#define __NR_mremap                     (__NR_Linux + 167)
-#define __NR_accept                     (__NR_Linux + 168)
-#define __NR_bind                       (__NR_Linux + 169)
-#define __NR_connect                    (__NR_Linux + 170)
-#define __NR_getpeername                (__NR_Linux + 171)
-#define __NR_getsockname                (__NR_Linux + 172)
-#define __NR_getsockopt                 (__NR_Linux + 173)
-#define __NR_listen                     (__NR_Linux + 174)
-#define __NR_recv                       (__NR_Linux + 175)
-#define __NR_recvfrom                   (__NR_Linux + 176)
-#define __NR_recvmsg                    (__NR_Linux + 177)
-#define __NR_send                       (__NR_Linux + 178)
-#define __NR_sendmsg                    (__NR_Linux + 179)
-#define __NR_sendto                     (__NR_Linux + 180)
-#define __NR_setsockopt                 (__NR_Linux + 181)
-#define __NR_shutdown                   (__NR_Linux + 182)
-#define __NR_socket                     (__NR_Linux + 183)
-#define __NR_socketpair                 (__NR_Linux + 184)
-#define __NR_setresuid                  (__NR_Linux + 185)
-#define __NR_getresuid                  (__NR_Linux + 186)
-#define __NR_query_module               (__NR_Linux + 187)
-#define __NR_poll                       (__NR_Linux + 188)
-#define __NR_nfsservctl                 (__NR_Linux + 189)
-#define __NR_setresgid                  (__NR_Linux + 190)
-#define __NR_getresgid                  (__NR_Linux + 191)
-#define __NR_prctl                      (__NR_Linux + 192)
-#define __NR_rt_sigreturn               (__NR_Linux + 193)
-#define __NR_rt_sigaction               (__NR_Linux + 194)
-#define __NR_rt_sigprocmask             (__NR_Linux + 195)
-#define __NR_rt_sigpending              (__NR_Linux + 196)
-#define __NR_rt_sigtimedwait            (__NR_Linux + 197)
-#define __NR_rt_sigqueueinfo            (__NR_Linux + 198)
-#define __NR_rt_sigsuspend              (__NR_Linux + 199)
-#define __NR_pread64                    (__NR_Linux + 200)
-#define __NR_pwrite64                   (__NR_Linux + 201)
-#define __NR_chown                      (__NR_Linux + 202)
-#define __NR_getcwd                     (__NR_Linux + 203)
-#define __NR_capget                     (__NR_Linux + 204)
-#define __NR_capset                     (__NR_Linux + 205)
-#define __NR_sigaltstack                (__NR_Linux + 206)
-#define __NR_sendfile                   (__NR_Linux + 207)
-#define __NR_getpmsg                    (__NR_Linux + 208)
-#define __NR_putpmsg                    (__NR_Linux + 209)
-#define __NR_mmap2                      (__NR_Linux + 210)
-#define __NR_truncate64                 (__NR_Linux + 211)
-#define __NR_ftruncate64                (__NR_Linux + 212)
-#define __NR_stat64                     (__NR_Linux + 213)
-#define __NR_lstat64                    (__NR_Linux + 214)
-#define __NR_fstat64                    (__NR_Linux + 215)
-#define __NR_pivot_root                 (__NR_Linux + 216)
-#define __NR_mincore                    (__NR_Linux + 217)
-#define __NR_madvise                    (__NR_Linux + 218)
-#define __NR_getdents64                 (__NR_Linux + 219)
-#define __NR_fcntl64                    (__NR_Linux + 220)
-#define __NR_reserved221                (__NR_Linux + 221)
-#define __NR_gettid                     (__NR_Linux + 222)
-#define __NR_readahead                  (__NR_Linux + 223)
-#define __NR_setxattr                   (__NR_Linux + 224)
-#define __NR_lsetxattr                  (__NR_Linux + 225)
-#define __NR_fsetxattr                  (__NR_Linux + 226)
-#define __NR_getxattr                   (__NR_Linux + 227)
-#define __NR_lgetxattr                  (__NR_Linux + 228)
-#define __NR_fgetxattr                  (__NR_Linux + 229)
-#define __NR_listxattr                  (__NR_Linux + 230)
-#define __NR_llistxattr                 (__NR_Linux + 231)
-#define __NR_flistxattr                 (__NR_Linux + 232)
-#define __NR_removexattr                (__NR_Linux + 233)
-#define __NR_lremovexattr               (__NR_Linux + 234)
-#define __NR_fremovexattr               (__NR_Linux + 235)
-#define __NR_tkill                      (__NR_Linux + 236)
-#define __NR_sendfile64                 (__NR_Linux + 237)
-#define __NR_futex                      (__NR_Linux + 238)
-#define __NR_sched_setaffinity          (__NR_Linux + 239)
-#define __NR_sched_getaffinity          (__NR_Linux + 240)
-#define __NR_io_setup                   (__NR_Linux + 241)
-#define __NR_io_destroy                 (__NR_Linux + 242)
-#define __NR_io_getevents               (__NR_Linux + 243)
-#define __NR_io_submit                  (__NR_Linux + 244)
-#define __NR_io_cancel                  (__NR_Linux + 245)
-#define __NR_exit_group                 (__NR_Linux + 246)
-#define __NR_lookup_dcookie             (__NR_Linux + 247)
-#define __NR_epoll_create               (__NR_Linux + 248)
-#define __NR_epoll_ctl                  (__NR_Linux + 249)
-#define __NR_epoll_wait                 (__NR_Linux + 250)
-#define __NR_remap_file_pages           (__NR_Linux + 251)
-#define __NR_set_tid_address            (__NR_Linux + 252)
-#define __NR_restart_syscall            (__NR_Linux + 253)
-#define __NR_fadvise64                  (__NR_Linux + 254)
-#define __NR_statfs64                   (__NR_Linux + 255)
-#define __NR_fstatfs64                  (__NR_Linux + 256)
-#define __NR_timer_create               (__NR_Linux + 257)
-#define __NR_timer_settime              (__NR_Linux + 258)
-#define __NR_timer_gettime              (__NR_Linux + 259)
-#define __NR_timer_getoverrun           (__NR_Linux + 260)
-#define __NR_timer_delete               (__NR_Linux + 261)
-#define __NR_clock_settime              (__NR_Linux + 262)
-#define __NR_clock_gettime              (__NR_Linux + 263)
-#define __NR_clock_getres               (__NR_Linux + 264)
-#define __NR_clock_nanosleep            (__NR_Linux + 265)
-#define __NR_tgkill                     (__NR_Linux + 266)
-#define __NR_utimes                     (__NR_Linux + 267)
-#define __NR_mbind                      (__NR_Linux + 268)
-#define __NR_get_mempolicy              (__NR_Linux + 269)
-#define __NR_set_mempolicy              (__NR_Linux + 270)
-#define __NR_mq_open                    (__NR_Linux + 271)
-#define __NR_mq_unlink                  (__NR_Linux + 272)
-#define __NR_mq_timedsend               (__NR_Linux + 273)
-#define __NR_mq_timedreceive            (__NR_Linux + 274)
-#define __NR_mq_notify                  (__NR_Linux + 275)
-#define __NR_mq_getsetattr              (__NR_Linux + 276)
-#define __NR_vserver                    (__NR_Linux + 277)
-#define __NR_waitid                     (__NR_Linux + 278)
-/* #define __NR_sys_setaltroot          (__NR_Linux + 279) */
-#define __NR_add_key                    (__NR_Linux + 280)
-#define __NR_request_key                (__NR_Linux + 281)
-#define __NR_keyctl                     (__NR_Linux + 282)
-#define __NR_set_thread_area            (__NR_Linux + 283)
-#define __NR_inotify_init               (__NR_Linux + 284)
-#define __NR_inotify_add_watch          (__NR_Linux + 285)
-#define __NR_inotify_rm_watch           (__NR_Linux + 286)
-#define __NR_migrate_pages              (__NR_Linux + 287)
-#define __NR_openat                     (__NR_Linux + 288)
-#define __NR_mkdirat                    (__NR_Linux + 289)
-#define __NR_mknodat                    (__NR_Linux + 290)
-#define __NR_fchownat                   (__NR_Linux + 291)
-#define __NR_futimesat                  (__NR_Linux + 292)
-#define __NR_fstatat64                  (__NR_Linux + 293)
-#define __NR_unlinkat                   (__NR_Linux + 294)
-#define __NR_renameat                   (__NR_Linux + 295)
-#define __NR_linkat                     (__NR_Linux + 296)
-#define __NR_symlinkat                  (__NR_Linux + 297)
-#define __NR_readlinkat                 (__NR_Linux + 298)
-#define __NR_fchmodat                   (__NR_Linux + 299)
-#define __NR_faccessat                  (__NR_Linux + 300)
-#define __NR_pselect6                   (__NR_Linux + 301)
-#define __NR_ppoll                      (__NR_Linux + 302)
-#define __NR_unshare                    (__NR_Linux + 303)
-#define __NR_splice                     (__NR_Linux + 304)
-#define __NR_sync_file_range            (__NR_Linux + 305)
-#define __NR_tee                        (__NR_Linux + 306)
-#define __NR_vmsplice                   (__NR_Linux + 307)
-#define __NR_move_pages                 (__NR_Linux + 308)
-#define __NR_set_robust_list            (__NR_Linux + 309)
-#define __NR_get_robust_list            (__NR_Linux + 310)
-#define __NR_kexec_load                 (__NR_Linux + 311)
-#define __NR_getcpu                     (__NR_Linux + 312)
-#define __NR_epoll_pwait                (__NR_Linux + 313)
-#define __NR_ioprio_set                 (__NR_Linux + 314)
-#define __NR_ioprio_get                 (__NR_Linux + 315)
-#define __NR_utimensat                  (__NR_Linux + 316)
-#define __NR_signalfd                   (__NR_Linux + 317)
-#define __NR_timerfd                    (__NR_Linux + 318)
-#define __NR_eventfd                    (__NR_Linux + 319)
-#define __NR_fallocate                  (__NR_Linux + 320)
-#define __NR_timerfd_create             (__NR_Linux + 321)
-#define __NR_timerfd_gettime            (__NR_Linux + 322)
-#define __NR_timerfd_settime            (__NR_Linux + 323)
-
-/*
- * Offset of the last Linux o32 flavoured syscall
- */
-#define __NR_Linux_syscalls             323
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI32 */
-
-#define __NR_O32_Linux                  4000
-#define __NR_O32_Linux_syscalls         323
-
-#if _MIPS_SIM == _MIPS_SIM_ABI64
-
-/*
- * Linux 64-bit syscalls are in the range from 5000 to 5999.
- */
-#define __NR_Linux                      5000
-#define __NR_read                       (__NR_Linux +   0)
-#define __NR_write                      (__NR_Linux +   1)
-#define __NR_open                       (__NR_Linux +   2)
-#define __NR_close                      (__NR_Linux +   3)
-#define __NR_stat                       (__NR_Linux +   4)
-#define __NR_fstat                      (__NR_Linux +   5)
-#define __NR_lstat                      (__NR_Linux +   6)
-#define __NR_poll                       (__NR_Linux +   7)
-#define __NR_lseek                      (__NR_Linux +   8)
-#define __NR_mmap                       (__NR_Linux +   9)
-#define __NR_mprotect                   (__NR_Linux +  10)
-#define __NR_munmap                     (__NR_Linux +  11)
-#define __NR_brk                        (__NR_Linux +  12)
-#define __NR_rt_sigaction               (__NR_Linux +  13)
-#define __NR_rt_sigprocmask             (__NR_Linux +  14)
-#define __NR_ioctl                      (__NR_Linux +  15)
-#define __NR_pread64                    (__NR_Linux +  16)
-#define __NR_pwrite64                   (__NR_Linux +  17)
-#define __NR_readv                      (__NR_Linux +  18)
-#define __NR_writev                     (__NR_Linux +  19)
-#define __NR_access                     (__NR_Linux +  20)
-#define __NR_pipe                       (__NR_Linux +  21)
-#define __NR__newselect                 (__NR_Linux +  22)
-#define __NR_sched_yield                (__NR_Linux +  23)
-#define __NR_mremap                     (__NR_Linux +  24)
-#define __NR_msync                      (__NR_Linux +  25)
-#define __NR_mincore                    (__NR_Linux +  26)
-#define __NR_madvise                    (__NR_Linux +  27)
-#define __NR_shmget                     (__NR_Linux +  28)
-#define __NR_shmat                      (__NR_Linux +  29)
-#define __NR_shmctl                     (__NR_Linux +  30)
-#define __NR_dup                        (__NR_Linux +  31)
-#define __NR_dup2                       (__NR_Linux +  32)
-#define __NR_pause                      (__NR_Linux +  33)
-#define __NR_nanosleep                  (__NR_Linux +  34)
-#define __NR_getitimer                  (__NR_Linux +  35)
-#define __NR_setitimer                  (__NR_Linux +  36)
-#define __NR_alarm                      (__NR_Linux +  37)
-#define __NR_getpid                     (__NR_Linux +  38)
-#define __NR_sendfile                   (__NR_Linux +  39)
-#define __NR_socket                     (__NR_Linux +  40)
-#define __NR_connect                    (__NR_Linux +  41)
-#define __NR_accept                     (__NR_Linux +  42)
-#define __NR_sendto                     (__NR_Linux +  43)
-#define __NR_recvfrom                   (__NR_Linux +  44)
-#define __NR_sendmsg                    (__NR_Linux +  45)
-#define __NR_recvmsg                    (__NR_Linux +  46)
-#define __NR_shutdown                   (__NR_Linux +  47)
-#define __NR_bind                       (__NR_Linux +  48)
-#define __NR_listen                     (__NR_Linux +  49)
-#define __NR_getsockname                (__NR_Linux +  50)
-#define __NR_getpeername                (__NR_Linux +  51)
-#define __NR_socketpair                 (__NR_Linux +  52)
-#define __NR_setsockopt                 (__NR_Linux +  53)
-#define __NR_getsockopt                 (__NR_Linux +  54)
-#define __NR_clone                      (__NR_Linux +  55)
-#define __NR_fork                       (__NR_Linux +  56)
-#define __NR_execve                     (__NR_Linux +  57)
-#define __NR_exit                       (__NR_Linux +  58)
-#define __NR_wait4                      (__NR_Linux +  59)
-#define __NR_kill                       (__NR_Linux +  60)
-#define __NR_uname                      (__NR_Linux +  61)
-#define __NR_semget                     (__NR_Linux +  62)
-#define __NR_semop                      (__NR_Linux +  63)
-#define __NR_semctl                     (__NR_Linux +  64)
-#define __NR_shmdt                      (__NR_Linux +  65)
-#define __NR_msgget                     (__NR_Linux +  66)
-#define __NR_msgsnd                     (__NR_Linux +  67)
-#define __NR_msgrcv                     (__NR_Linux +  68)
-#define __NR_msgctl                     (__NR_Linux +  69)
-#define __NR_fcntl                      (__NR_Linux +  70)
-#define __NR_flock                      (__NR_Linux +  71)
-#define __NR_fsync                      (__NR_Linux +  72)
-#define __NR_fdatasync                  (__NR_Linux +  73)
-#define __NR_truncate                   (__NR_Linux +  74)
-#define __NR_ftruncate                  (__NR_Linux +  75)
-#define __NR_getdents                   (__NR_Linux +  76)
-#define __NR_getcwd                     (__NR_Linux +  77)
-#define __NR_chdir                      (__NR_Linux +  78)
-#define __NR_fchdir                     (__NR_Linux +  79)
-#define __NR_rename                     (__NR_Linux +  80)
-#define __NR_mkdir                      (__NR_Linux +  81)
-#define __NR_rmdir                      (__NR_Linux +  82)
-#define __NR_creat                      (__NR_Linux +  83)
-#define __NR_link                       (__NR_Linux +  84)
-#define __NR_unlink                     (__NR_Linux +  85)
-#define __NR_symlink                    (__NR_Linux +  86)
-#define __NR_readlink                   (__NR_Linux +  87)
-#define __NR_chmod                      (__NR_Linux +  88)
-#define __NR_fchmod                     (__NR_Linux +  89)
-#define __NR_chown                      (__NR_Linux +  90)
-#define __NR_fchown                     (__NR_Linux +  91)
-#define __NR_lchown                     (__NR_Linux +  92)
-#define __NR_umask                      (__NR_Linux +  93)
-#define __NR_gettimeofday               (__NR_Linux +  94)
-#define __NR_getrlimit                  (__NR_Linux +  95)
-#define __NR_getrusage                  (__NR_Linux +  96)
-#define __NR_sysinfo                    (__NR_Linux +  97)
-#define __NR_times                      (__NR_Linux +  98)
-#define __NR_ptrace                     (__NR_Linux +  99)
-#define __NR_getuid                     (__NR_Linux + 100)
-#define __NR_syslog                     (__NR_Linux + 101)
-#define __NR_getgid                     (__NR_Linux + 102)
-#define __NR_setuid                     (__NR_Linux + 103)
-#define __NR_setgid                     (__NR_Linux + 104)
-#define __NR_geteuid                    (__NR_Linux + 105)
-#define __NR_getegid                    (__NR_Linux + 106)
-#define __NR_setpgid                    (__NR_Linux + 107)
-#define __NR_getppid                    (__NR_Linux + 108)
-#define __NR_getpgrp                    (__NR_Linux + 109)
-#define __NR_setsid                     (__NR_Linux + 110)
-#define __NR_setreuid                   (__NR_Linux + 111)
-#define __NR_setregid                   (__NR_Linux + 112)
-#define __NR_getgroups                  (__NR_Linux + 113)
-#define __NR_setgroups                  (__NR_Linux + 114)
-#define __NR_setresuid                  (__NR_Linux + 115)
-#define __NR_getresuid                  (__NR_Linux + 116)
-#define __NR_setresgid                  (__NR_Linux + 117)
-#define __NR_getresgid                  (__NR_Linux + 118)
-#define __NR_getpgid                    (__NR_Linux + 119)
-#define __NR_setfsuid                   (__NR_Linux + 120)
-#define __NR_setfsgid                   (__NR_Linux + 121)
-#define __NR_getsid                     (__NR_Linux + 122)
-#define __NR_capget                     (__NR_Linux + 123)
-#define __NR_capset                     (__NR_Linux + 124)
-#define __NR_rt_sigpending              (__NR_Linux + 125)
-#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
-#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
-#define __NR_rt_sigsuspend              (__NR_Linux + 128)
-#define __NR_sigaltstack                (__NR_Linux + 129)
-#define __NR_utime                      (__NR_Linux + 130)
-#define __NR_mknod                      (__NR_Linux + 131)
-#define __NR_personality                (__NR_Linux + 132)
-#define __NR_ustat                      (__NR_Linux + 133)
-#define __NR_statfs                     (__NR_Linux + 134)
-#define __NR_fstatfs                    (__NR_Linux + 135)
-#define __NR_sysfs                      (__NR_Linux + 136)
-#define __NR_getpriority                (__NR_Linux + 137)
-#define __NR_setpriority                (__NR_Linux + 138)
-#define __NR_sched_setparam             (__NR_Linux + 139)
-#define __NR_sched_getparam             (__NR_Linux + 140)
-#define __NR_sched_setscheduler         (__NR_Linux + 141)
-#define __NR_sched_getscheduler         (__NR_Linux + 142)
-#define __NR_sched_get_priority_max     (__NR_Linux + 143)
-#define __NR_sched_get_priority_min     (__NR_Linux + 144)
-#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
-#define __NR_mlock                      (__NR_Linux + 146)
-#define __NR_munlock                    (__NR_Linux + 147)
-#define __NR_mlockall                   (__NR_Linux + 148)
-#define __NR_munlockall                 (__NR_Linux + 149)
-#define __NR_vhangup                    (__NR_Linux + 150)
-#define __NR_pivot_root                 (__NR_Linux + 151)
-#define __NR__sysctl                    (__NR_Linux + 152)
-#define __NR_prctl                      (__NR_Linux + 153)
-#define __NR_adjtimex                   (__NR_Linux + 154)
-#define __NR_setrlimit                  (__NR_Linux + 155)
-#define __NR_chroot                     (__NR_Linux + 156)
-#define __NR_sync                       (__NR_Linux + 157)
-#define __NR_acct                       (__NR_Linux + 158)
-#define __NR_settimeofday               (__NR_Linux + 159)
-#define __NR_mount                      (__NR_Linux + 160)
-#define __NR_umount2                    (__NR_Linux + 161)
-#define __NR_swapon                     (__NR_Linux + 162)
-#define __NR_swapoff                    (__NR_Linux + 163)
-#define __NR_reboot                     (__NR_Linux + 164)
-#define __NR_sethostname                (__NR_Linux + 165)
-#define __NR_setdomainname              (__NR_Linux + 166)
-#define __NR_create_module              (__NR_Linux + 167)
-#define __NR_init_module                (__NR_Linux + 168)
-#define __NR_delete_module              (__NR_Linux + 169)
-#define __NR_get_kernel_syms            (__NR_Linux + 170)
-#define __NR_query_module               (__NR_Linux + 171)
-#define __NR_quotactl                   (__NR_Linux + 172)
-#define __NR_nfsservctl                 (__NR_Linux + 173)
-#define __NR_getpmsg                    (__NR_Linux + 174)
-#define __NR_putpmsg                    (__NR_Linux + 175)
-#define __NR_afs_syscall                (__NR_Linux + 176)
-#define __NR_reserved177                (__NR_Linux + 177)
-#define __NR_gettid                     (__NR_Linux + 178)
-#define __NR_readahead                  (__NR_Linux + 179)
-#define __NR_setxattr                   (__NR_Linux + 180)
-#define __NR_lsetxattr                  (__NR_Linux + 181)
-#define __NR_fsetxattr                  (__NR_Linux + 182)
-#define __NR_getxattr                   (__NR_Linux + 183)
-#define __NR_lgetxattr                  (__NR_Linux + 184)
-#define __NR_fgetxattr                  (__NR_Linux + 185)
-#define __NR_listxattr                  (__NR_Linux + 186)
-#define __NR_llistxattr                 (__NR_Linux + 187)
-#define __NR_flistxattr                 (__NR_Linux + 188)
-#define __NR_removexattr                (__NR_Linux + 189)
-#define __NR_lremovexattr               (__NR_Linux + 190)
-#define __NR_fremovexattr               (__NR_Linux + 191)
-#define __NR_tkill                      (__NR_Linux + 192)
-#define __NR_reserved193                (__NR_Linux + 193)
-#define __NR_futex                      (__NR_Linux + 194)
-#define __NR_sched_setaffinity          (__NR_Linux + 195)
-#define __NR_sched_getaffinity          (__NR_Linux + 196)
-#define __NR_cacheflush                 (__NR_Linux + 197)
-#define __NR_cachectl                   (__NR_Linux + 198)
-#define __NR_sysmips                    (__NR_Linux + 199)
-#define __NR_io_setup                   (__NR_Linux + 200)
-#define __NR_io_destroy                 (__NR_Linux + 201)
-#define __NR_io_getevents               (__NR_Linux + 202)
-#define __NR_io_submit                  (__NR_Linux + 203)
-#define __NR_io_cancel                  (__NR_Linux + 204)
-#define __NR_exit_group                 (__NR_Linux + 205)
-#define __NR_lookup_dcookie             (__NR_Linux + 206)
-#define __NR_epoll_create               (__NR_Linux + 207)
-#define __NR_epoll_ctl                  (__NR_Linux + 208)
-#define __NR_epoll_wait                 (__NR_Linux + 209)
-#define __NR_remap_file_pages           (__NR_Linux + 210)
-#define __NR_rt_sigreturn               (__NR_Linux + 211)
-#define __NR_set_tid_address            (__NR_Linux + 212)
-#define __NR_restart_syscall            (__NR_Linux + 213)
-#define __NR_semtimedop                 (__NR_Linux + 214)
-#define __NR_fadvise64                  (__NR_Linux + 215)
-#define __NR_timer_create               (__NR_Linux + 216)
-#define __NR_timer_settime              (__NR_Linux + 217)
-#define __NR_timer_gettime              (__NR_Linux + 218)
-#define __NR_timer_getoverrun           (__NR_Linux + 219)
-#define __NR_timer_delete               (__NR_Linux + 220)
-#define __NR_clock_settime              (__NR_Linux + 221)
-#define __NR_clock_gettime              (__NR_Linux + 222)
-#define __NR_clock_getres               (__NR_Linux + 223)
-#define __NR_clock_nanosleep            (__NR_Linux + 224)
-#define __NR_tgkill                     (__NR_Linux + 225)
-#define __NR_utimes                     (__NR_Linux + 226)
-#define __NR_mbind                      (__NR_Linux + 227)
-#define __NR_get_mempolicy              (__NR_Linux + 228)
-#define __NR_set_mempolicy              (__NR_Linux + 229)
-#define __NR_mq_open                    (__NR_Linux + 230)
-#define __NR_mq_unlink                  (__NR_Linux + 231)
-#define __NR_mq_timedsend               (__NR_Linux + 232)
-#define __NR_mq_timedreceive            (__NR_Linux + 233)
-#define __NR_mq_notify                  (__NR_Linux + 234)
-#define __NR_mq_getsetattr              (__NR_Linux + 235)
-#define __NR_vserver                    (__NR_Linux + 236)
-#define __NR_waitid                     (__NR_Linux + 237)
-/* #define __NR_sys_setaltroot          (__NR_Linux + 238) */
-#define __NR_add_key                    (__NR_Linux + 239)
-#define __NR_request_key                (__NR_Linux + 240)
-#define __NR_keyctl                     (__NR_Linux + 241)
-#define __NR_set_thread_area            (__NR_Linux + 242)
-#define __NR_inotify_init               (__NR_Linux + 243)
-#define __NR_inotify_add_watch          (__NR_Linux + 244)
-#define __NR_inotify_rm_watch           (__NR_Linux + 245)
-#define __NR_migrate_pages              (__NR_Linux + 246)
-#define __NR_openat                     (__NR_Linux + 247)
-#define __NR_mkdirat                    (__NR_Linux + 248)
-#define __NR_mknodat                    (__NR_Linux + 249)
-#define __NR_fchownat                   (__NR_Linux + 250)
-#define __NR_futimesat                  (__NR_Linux + 251)
-#define __NR_newfstatat                 (__NR_Linux + 252)
-#define __NR_unlinkat                   (__NR_Linux + 253)
-#define __NR_renameat                   (__NR_Linux + 254)
-#define __NR_linkat                     (__NR_Linux + 255)
-#define __NR_symlinkat                  (__NR_Linux + 256)
-#define __NR_readlinkat                 (__NR_Linux + 257)
-#define __NR_fchmodat                   (__NR_Linux + 258)
-#define __NR_faccessat                  (__NR_Linux + 259)
-#define __NR_pselect6                   (__NR_Linux + 260)
-#define __NR_ppoll                      (__NR_Linux + 261)
-#define __NR_unshare                    (__NR_Linux + 262)
-#define __NR_splice                     (__NR_Linux + 263)
-#define __NR_sync_file_range            (__NR_Linux + 264)
-#define __NR_tee                        (__NR_Linux + 265)
-#define __NR_vmsplice                   (__NR_Linux + 266)
-#define __NR_move_pages                 (__NR_Linux + 267)
-#define __NR_set_robust_list            (__NR_Linux + 268)
-#define __NR_get_robust_list            (__NR_Linux + 269)
-#define __NR_kexec_load                 (__NR_Linux + 270)
-#define __NR_getcpu                     (__NR_Linux + 271)
-#define __NR_epoll_pwait                (__NR_Linux + 272)
-#define __NR_ioprio_set                 (__NR_Linux + 273)
-#define __NR_ioprio_get                 (__NR_Linux + 274)
-#define __NR_utimensat                  (__NR_Linux + 275)
-#define __NR_signalfd                   (__NR_Linux + 276)
-#define __NR_timerfd                    (__NR_Linux + 277)
-#define __NR_eventfd                    (__NR_Linux + 278)
-#define __NR_fallocate                  (__NR_Linux + 279)
-#define __NR_timerfd_create             (__NR_Linux + 280)
-#define __NR_timerfd_gettime            (__NR_Linux + 281)
-#define __NR_timerfd_settime            (__NR_Linux + 282)
-
-/*
- * Offset of the last Linux 64-bit flavoured syscall
- */
-#define __NR_Linux_syscalls             282
-
-#endif /* _MIPS_SIM == _MIPS_SIM_ABI64 */
-
-#define __NR_64_Linux                   5000
-#define __NR_64_Linux_syscalls          282
-
-#if _MIPS_SIM == _MIPS_SIM_NABI32
-
-/*
- * Linux N32 syscalls are in the range from 6000 to 6999.
- */
-#define __NR_Linux                      6000
-#define __NR_read                       (__NR_Linux +   0)
-#define __NR_write                      (__NR_Linux +   1)
-#define __NR_open                       (__NR_Linux +   2)
-#define __NR_close                      (__NR_Linux +   3)
-#define __NR_stat                       (__NR_Linux +   4)
-#define __NR_fstat                      (__NR_Linux +   5)
-#define __NR_lstat                      (__NR_Linux +   6)
-#define __NR_poll                       (__NR_Linux +   7)
-#define __NR_lseek                      (__NR_Linux +   8)
-#define __NR_mmap                       (__NR_Linux +   9)
-#define __NR_mprotect                   (__NR_Linux +  10)
-#define __NR_munmap                     (__NR_Linux +  11)
-#define __NR_brk                        (__NR_Linux +  12)
-#define __NR_rt_sigaction               (__NR_Linux +  13)
-#define __NR_rt_sigprocmask             (__NR_Linux +  14)
-#define __NR_ioctl                      (__NR_Linux +  15)
-#define __NR_pread64                    (__NR_Linux +  16)
-#define __NR_pwrite64                   (__NR_Linux +  17)
-#define __NR_readv                      (__NR_Linux +  18)
-#define __NR_writev                     (__NR_Linux +  19)
-#define __NR_access                     (__NR_Linux +  20)
-#define __NR_pipe                       (__NR_Linux +  21)
-#define __NR__newselect                 (__NR_Linux +  22)
-#define __NR_sched_yield                (__NR_Linux +  23)
-#define __NR_mremap                     (__NR_Linux +  24)
-#define __NR_msync                      (__NR_Linux +  25)
-#define __NR_mincore                    (__NR_Linux +  26)
-#define __NR_madvise                    (__NR_Linux +  27)
-#define __NR_shmget                     (__NR_Linux +  28)
-#define __NR_shmat                      (__NR_Linux +  29)
-#define __NR_shmctl                     (__NR_Linux +  30)
-#define __NR_dup                        (__NR_Linux +  31)
-#define __NR_dup2                       (__NR_Linux +  32)
-#define __NR_pause                      (__NR_Linux +  33)
-#define __NR_nanosleep                  (__NR_Linux +  34)
-#define __NR_getitimer                  (__NR_Linux +  35)
-#define __NR_setitimer                  (__NR_Linux +  36)
-#define __NR_alarm                      (__NR_Linux +  37)
-#define __NR_getpid                     (__NR_Linux +  38)
-#define __NR_sendfile                   (__NR_Linux +  39)
-#define __NR_socket                     (__NR_Linux +  40)
-#define __NR_connect                    (__NR_Linux +  41)
-#define __NR_accept                     (__NR_Linux +  42)
-#define __NR_sendto                     (__NR_Linux +  43)
-#define __NR_recvfrom                   (__NR_Linux +  44)
-#define __NR_sendmsg                    (__NR_Linux +  45)
-#define __NR_recvmsg                    (__NR_Linux +  46)
-#define __NR_shutdown                   (__NR_Linux +  47)
-#define __NR_bind                       (__NR_Linux +  48)
-#define __NR_listen                     (__NR_Linux +  49)
-#define __NR_getsockname                (__NR_Linux +  50)
-#define __NR_getpeername                (__NR_Linux +  51)
-#define __NR_socketpair                 (__NR_Linux +  52)
-#define __NR_setsockopt                 (__NR_Linux +  53)
-#define __NR_getsockopt                 (__NR_Linux +  54)
-#define __NR_clone                      (__NR_Linux +  55)
-#define __NR_fork                       (__NR_Linux +  56)
-#define __NR_execve                     (__NR_Linux +  57)
-#define __NR_exit                       (__NR_Linux +  58)
-#define __NR_wait4                      (__NR_Linux +  59)
-#define __NR_kill                       (__NR_Linux +  60)
-#define __NR_uname                      (__NR_Linux +  61)
-#define __NR_semget                     (__NR_Linux +  62)
-#define __NR_semop                      (__NR_Linux +  63)
-#define __NR_semctl                     (__NR_Linux +  64)
-#define __NR_shmdt                      (__NR_Linux +  65)
-#define __NR_msgget                     (__NR_Linux +  66)
-#define __NR_msgsnd                     (__NR_Linux +  67)
-#define __NR_msgrcv                     (__NR_Linux +  68)
-#define __NR_msgctl                     (__NR_Linux +  69)
-#define __NR_fcntl                      (__NR_Linux +  70)
-#define __NR_flock                      (__NR_Linux +  71)
-#define __NR_fsync                      (__NR_Linux +  72)
-#define __NR_fdatasync                  (__NR_Linux +  73)
-#define __NR_truncate                   (__NR_Linux +  74)
-#define __NR_ftruncate                  (__NR_Linux +  75)
-#define __NR_getdents                   (__NR_Linux +  76)
-#define __NR_getcwd                     (__NR_Linux +  77)
-#define __NR_chdir                      (__NR_Linux +  78)
-#define __NR_fchdir                     (__NR_Linux +  79)
-#define __NR_rename                     (__NR_Linux +  80)
-#define __NR_mkdir                      (__NR_Linux +  81)
-#define __NR_rmdir                      (__NR_Linux +  82)
-#define __NR_creat                      (__NR_Linux +  83)
-#define __NR_link                       (__NR_Linux +  84)
-#define __NR_unlink                     (__NR_Linux +  85)
-#define __NR_symlink                    (__NR_Linux +  86)
-#define __NR_readlink                   (__NR_Linux +  87)
-#define __NR_chmod                      (__NR_Linux +  88)
-#define __NR_fchmod                     (__NR_Linux +  89)
-#define __NR_chown                      (__NR_Linux +  90)
-#define __NR_fchown                     (__NR_Linux +  91)
-#define __NR_lchown                     (__NR_Linux +  92)
-#define __NR_umask                      (__NR_Linux +  93)
-#define __NR_gettimeofday               (__NR_Linux +  94)
-#define __NR_getrlimit                  (__NR_Linux +  95)
-#define __NR_getrusage                  (__NR_Linux +  96)
-#define __NR_sysinfo                    (__NR_Linux +  97)
-#define __NR_times                      (__NR_Linux +  98)
-#define __NR_ptrace                     (__NR_Linux +  99)
-#define __NR_getuid                     (__NR_Linux + 100)
-#define __NR_syslog                     (__NR_Linux + 101)
-#define __NR_getgid                     (__NR_Linux + 102)
-#define __NR_setuid                     (__NR_Linux + 103)
-#define __NR_setgid                     (__NR_Linux + 104)
-#define __NR_geteuid                    (__NR_Linux + 105)
-#define __NR_getegid                    (__NR_Linux + 106)
-#define __NR_setpgid                    (__NR_Linux + 107)
-#define __NR_getppid                    (__NR_Linux + 108)
-#define __NR_getpgrp                    (__NR_Linux + 109)
-#define __NR_setsid                     (__NR_Linux + 110)
-#define __NR_setreuid                   (__NR_Linux + 111)
-#define __NR_setregid                   (__NR_Linux + 112)
-#define __NR_getgroups                  (__NR_Linux + 113)
-#define __NR_setgroups                  (__NR_Linux + 114)
-#define __NR_setresuid                  (__NR_Linux + 115)
-#define __NR_getresuid                  (__NR_Linux + 116)
-#define __NR_setresgid                  (__NR_Linux + 117)
-#define __NR_getresgid                  (__NR_Linux + 118)
-#define __NR_getpgid                    (__NR_Linux + 119)
-#define __NR_setfsuid                   (__NR_Linux + 120)
-#define __NR_setfsgid                   (__NR_Linux + 121)
-#define __NR_getsid                     (__NR_Linux + 122)
-#define __NR_capget                     (__NR_Linux + 123)
-#define __NR_capset                     (__NR_Linux + 124)
-#define __NR_rt_sigpending              (__NR_Linux + 125)
-#define __NR_rt_sigtimedwait            (__NR_Linux + 126)
-#define __NR_rt_sigqueueinfo            (__NR_Linux + 127)
-#define __NR_rt_sigsuspend              (__NR_Linux + 128)
-#define __NR_sigaltstack                (__NR_Linux + 129)
-#define __NR_utime                      (__NR_Linux + 130)
-#define __NR_mknod                      (__NR_Linux + 131)
-#define __NR_personality                (__NR_Linux + 132)
-#define __NR_ustat                      (__NR_Linux + 133)
-#define __NR_statfs                     (__NR_Linux + 134)
-#define __NR_fstatfs                    (__NR_Linux + 135)
-#define __NR_sysfs                      (__NR_Linux + 136)
-#define __NR_getpriority                (__NR_Linux + 137)
-#define __NR_setpriority                (__NR_Linux + 138)
-#define __NR_sched_setparam             (__NR_Linux + 139)
-#define __NR_sched_getparam             (__NR_Linux + 140)
-#define __NR_sched_setscheduler         (__NR_Linux + 141)
-#define __NR_sched_getscheduler         (__NR_Linux + 142)
-#define __NR_sched_get_priority_max     (__NR_Linux + 143)
-#define __NR_sched_get_priority_min     (__NR_Linux + 144)
-#define __NR_sched_rr_get_interval      (__NR_Linux + 145)
-#define __NR_mlock                      (__NR_Linux + 146)
-#define __NR_munlock                    (__NR_Linux + 147)
-#define __NR_mlockall                   (__NR_Linux + 148)
-#define __NR_munlockall                 (__NR_Linux + 149)
-#define __NR_vhangup                    (__NR_Linux + 150)
-#define __NR_pivot_root                 (__NR_Linux + 151)
-#define __NR__sysctl                    (__NR_Linux + 152)
-#define __NR_prctl                      (__NR_Linux + 153)
-#define __NR_adjtimex                   (__NR_Linux + 154)
-#define __NR_setrlimit                  (__NR_Linux + 155)
-#define __NR_chroot                     (__NR_Linux + 156)
-#define __NR_sync                       (__NR_Linux + 157)
-#define __NR_acct                       (__NR_Linux + 158)
-#define __NR_settimeofday               (__NR_Linux + 159)
-#define __NR_mount                      (__NR_Linux + 160)
-#define __NR_umount2                    (__NR_Linux + 161)
-#define __NR_swapon                     (__NR_Linux + 162)
-#define __NR_swapoff                    (__NR_Linux + 163)
-#define __NR_reboot                     (__NR_Linux + 164)
-#define __NR_sethostname                (__NR_Linux + 165)
-#define __NR_setdomainname              (__NR_Linux + 166)
-#define __NR_create_module              (__NR_Linux + 167)
-#define __NR_init_module                (__NR_Linux + 168)
-#define __NR_delete_module              (__NR_Linux + 169)
-#define __NR_get_kernel_syms            (__NR_Linux + 170)
-#define __NR_query_module               (__NR_Linux + 171)
-#define __NR_quotactl                   (__NR_Linux + 172)
-#define __NR_nfsservctl                 (__NR_Linux + 173)
-#define __NR_getpmsg                    (__NR_Linux + 174)
-#define __NR_putpmsg                    (__NR_Linux + 175)
-#define __NR_afs_syscall                (__NR_Linux + 176)
-#define __NR_reserved177                (__NR_Linux + 177)
-#define __NR_gettid                     (__NR_Linux + 178)
-#define __NR_readahead                  (__NR_Linux + 179)
-#define __NR_setxattr                   (__NR_Linux + 180)
-#define __NR_lsetxattr                  (__NR_Linux + 181)
-#define __NR_fsetxattr                  (__NR_Linux + 182)
-#define __NR_getxattr                   (__NR_Linux + 183)
-#define __NR_lgetxattr                  (__NR_Linux + 184)
-#define __NR_fgetxattr                  (__NR_Linux + 185)
-#define __NR_listxattr                  (__NR_Linux + 186)
-#define __NR_llistxattr                 (__NR_Linux + 187)
-#define __NR_flistxattr                 (__NR_Linux + 188)
-#define __NR_removexattr                (__NR_Linux + 189)
-#define __NR_lremovexattr               (__NR_Linux + 190)
-#define __NR_fremovexattr               (__NR_Linux + 191)
-#define __NR_tkill                      (__NR_Linux + 192)
-#define __NR_reserved193                (__NR_Linux + 193)
-#define __NR_futex                      (__NR_Linux + 194)
-#define __NR_sched_setaffinity          (__NR_Linux + 195)
-#define __NR_sched_getaffinity          (__NR_Linux + 196)
-#define __NR_cacheflush                 (__NR_Linux + 197)
-#define __NR_cachectl                   (__NR_Linux + 198)
-#define __NR_sysmips                    (__NR_Linux + 199)
-#define __NR_io_setup                   (__NR_Linux + 200)
-#define __NR_io_destroy                 (__NR_Linux + 201)
-#define __NR_io_getevents               (__NR_Linux + 202)
-#define __NR_io_submit                  (__NR_Linux + 203)
-#define __NR_io_cancel                  (__NR_Linux + 204)
-#define __NR_exit_group                 (__NR_Linux + 205)
-#define __NR_lookup_dcookie             (__NR_Linux + 206)
-#define __NR_epoll_create               (__NR_Linux + 207)
-#define __NR_epoll_ctl                  (__NR_Linux + 208)
-#define __NR_epoll_wait                 (__NR_Linux + 209)
-#define __NR_remap_file_pages           (__NR_Linux + 210)
-#define __NR_rt_sigreturn               (__NR_Linux + 211)
-#define __NR_fcntl64                    (__NR_Linux + 212)
-#define __NR_set_tid_address            (__NR_Linux + 213)
-#define __NR_restart_syscall            (__NR_Linux + 214)
-#define __NR_semtimedop                 (__NR_Linux + 215)
-#define __NR_fadvise64                  (__NR_Linux + 216)
-#define __NR_statfs64                   (__NR_Linux + 217)
-#define __NR_fstatfs64                  (__NR_Linux + 218)
-#define __NR_sendfile64                 (__NR_Linux + 219)
-#define __NR_timer_create               (__NR_Linux + 220)
-#define __NR_timer_settime              (__NR_Linux + 221)
-#define __NR_timer_gettime              (__NR_Linux + 222)
-#define __NR_timer_getoverrun           (__NR_Linux + 223)
-#define __NR_timer_delete               (__NR_Linux + 224)
-#define __NR_clock_settime              (__NR_Linux + 225)
-#define __NR_clock_gettime              (__NR_Linux + 226)
-#define __NR_clock_getres               (__NR_Linux + 227)
-#define __NR_clock_nanosleep            (__NR_Linux + 228)
-#define __NR_tgkill                     (__NR_Linux + 229)
-#define __NR_utimes                     (__NR_Linux + 230)
-#define __NR_mbind                      (__NR_Linux + 231)
-#define __NR_get_mempolicy              (__NR_Linux + 232)
-#define __NR_set_mempolicy              (__NR_Linux + 233)
-#define __NR_mq_open                    (__NR_Linux + 234)
-#define __NR_mq_unlink                  (__NR_Linux + 235)
-#define __NR_mq_timedsend               (__NR_Linux + 236)
-#define __NR_mq_timedreceive            (__NR_Linux + 237)
-#define __NR_mq_notify                  (__NR_Linux + 238)
-#define __NR_mq_getsetattr              (__NR_Linux + 239)
-#define __NR_vserver                    (__NR_Linux + 240)
-#define __NR_waitid                     (__NR_Linux + 241)
-/* #define __NR_sys_setaltroot          (__NR_Linux + 242) */
-#define __NR_add_key                    (__NR_Linux + 243)
-#define __NR_request_key                (__NR_Linux + 244)
-#define __NR_keyctl                     (__NR_Linux + 245)
-#define __NR_set_thread_area            (__NR_Linux + 246)
-#define __NR_inotify_init               (__NR_Linux + 247)
-#define __NR_inotify_add_watch          (__NR_Linux + 248)
-#define __NR_inotify_rm_watch           (__NR_Linux + 249)
-#define __NR_migrate_pages              (__NR_Linux + 250)
-#define __NR_openat                     (__NR_Linux + 251)
-#define __NR_mkdirat                    (__NR_Linux + 252)
-#define __NR_mknodat                    (__NR_Linux + 253)
-#define __NR_fchownat                   (__NR_Linux + 254)
-#define __NR_futimesat                  (__NR_Linux + 255)
-#define __NR_newfstatat                 (__NR_Linux + 256)
-#define __NR_unlinkat                   (__NR_Linux + 257)
-#define __NR_renameat                   (__NR_Linux + 258)
-#define __NR_linkat                     (__NR_Linux + 259)
-#define __NR_symlinkat                  (__NR_Linux + 260)
-#define __NR_readlinkat                 (__NR_Linux + 261)
-#define __NR_fchmodat                   (__NR_Linux + 262)
-#define __NR_faccessat                  (__NR_Linux + 263)
-#define __NR_pselect6                   (__NR_Linux + 264)
-#define __NR_ppoll                      (__NR_Linux + 265)
-#define __NR_unshare                    (__NR_Linux + 266)
-#define __NR_splice                     (__NR_Linux + 267)
-#define __NR_sync_file_range            (__NR_Linux + 268)
-#define __NR_tee                        (__NR_Linux + 269)
-#define __NR_vmsplice                   (__NR_Linux + 270)
-#define __NR_move_pages                 (__NR_Linux + 271)
-#define __NR_set_robust_list            (__NR_Linux + 272)
-#define __NR_get_robust_list            (__NR_Linux + 273)
-#define __NR_kexec_load                 (__NR_Linux + 274)
-#define __NR_getcpu                     (__NR_Linux + 275)
-#define __NR_epoll_pwait                (__NR_Linux + 276)
-#define __NR_ioprio_set                 (__NR_Linux + 277)
-#define __NR_ioprio_get                 (__NR_Linux + 278)
-#define __NR_utimensat                  (__NR_Linux + 279)
-#define __NR_signalfd                   (__NR_Linux + 280)
-#define __NR_timerfd                    (__NR_Linux + 281)
-#define __NR_eventfd                    (__NR_Linux + 282)
-#define __NR_fallocate                  (__NR_Linux + 283)
-#define __NR_timerfd_create             (__NR_Linux + 284)
-#define __NR_timerfd_gettime            (__NR_Linux + 285)
-#define __NR_timerfd_settime            (__NR_Linux + 286)
-
-/*
- * Offset of the last N32 flavoured syscall
- */
-#define __NR_Linux_syscalls             286
-
-#endif /* _MIPS_SIM == _MIPS_SIM_NABI32 */
-
-#define __NR_N32_Linux                  6000
-#define __NR_N32_Linux_syscalls         286
-
-#ifdef __KERNEL__
-
-#ifndef __ASSEMBLY__
-
-#define __ARCH_OMIT_COMPAT_SYS_GETDENTS64
-#define __ARCH_WANT_IPC_PARSE_VERSION
-#define __ARCH_WANT_OLD_READDIR
-#define __ARCH_WANT_SYS_ALARM
-#define __ARCH_WANT_SYS_GETHOSTNAME
-#define __ARCH_WANT_SYS_PAUSE
-#define __ARCH_WANT_SYS_SGETMASK
-#define __ARCH_WANT_SYS_UTIME
-#define __ARCH_WANT_SYS_WAITPID
-#define __ARCH_WANT_SYS_SOCKETCALL
-#define __ARCH_WANT_SYS_GETPGRP
-#define __ARCH_WANT_SYS_LLSEEK
-#define __ARCH_WANT_SYS_NICE
-#define __ARCH_WANT_SYS_OLD_GETRLIMIT
-#define __ARCH_WANT_SYS_OLDUMOUNT
-#define __ARCH_WANT_SYS_SIGPENDING
-#define __ARCH_WANT_SYS_SIGPROCMASK
-#define __ARCH_WANT_SYS_RT_SIGACTION
-# ifdef CONFIG_32BIT
-#  define __ARCH_WANT_STAT64
-#  define __ARCH_WANT_SYS_TIME
-# endif
-# ifdef CONFIG_MIPS32_O32
-#  define __ARCH_WANT_COMPAT_SYS_TIME
-# endif
-
-/* whitelists for checksyscalls */
-#define __IGNORE_select
-#define __IGNORE_vfork
-#define __IGNORE_time
-#define __IGNORE_uselib
-#define __IGNORE_fadvise64_64
-#define __IGNORE_getdents64
-#if _MIPS_SIM == _MIPS_SIM_NABI32
-#define __IGNORE_truncate64
-#define __IGNORE_ftruncate64
-#define __IGNORE_stat64
-#define __IGNORE_lstat64
-#define __IGNORE_fstat64
-#define __IGNORE_fstatat64
-#endif
-
-#endif /* !__ASSEMBLY__ */
-
-/*
- * "Conditional" syscalls
- *
- * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
- * but it doesn't work on all toolchains, so we just do it by hand
- */
-#define cond_syscall(x) asm(".weak\t" #x "\n" #x "\t=\tsys_ni_syscall")
-
-#endif /* __KERNEL__ */
-#endif /* _ASM_UNISTD_H */
diff --git a/include/asm-mips/user.h b/include/asm-mips/user.h
deleted file mode 100644
index afa83a4c1888..000000000000
--- a/include/asm-mips/user.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 1994, 1995, 1996, 1999 by Ralf Baechle
- */
-#ifndef _ASM_USER_H
-#define _ASM_USER_H
-
-#include <asm/page.h>
-#include <asm/reg.h>
-
-/*
- * Core file format: The core file is written in such a way that gdb
- * can understand it and provide useful information to the user (under
- * linux we use the `trad-core' bfd, NOT the irix-core).  The file
- * contents are as follows:
- *
- *  upage: 1 page consisting of a user struct that tells gdb
- *      what is present in the file.  Directly after this is a
- *      copy of the task_struct, which is currently not used by gdb,
- *      but it may come in handy at some point.  All of the registers
- *      are stored as part of the upage.  The upage should always be
- *      only one page long.
- *  data: The data segment follows next.  We use current->end_text to
- *      current->brk to pick up all of the user variables, plus any memory
- *      that may have been sbrk'ed.  No attempt is made to determine if a
- *      page is demand-zero or if a page is totally unused, we just cover
- *      the entire range.  All of the addresses are rounded in such a way
- *      that an integral number of pages is written.
- *  stack: We need the stack information in order to get a meaningful
- *      backtrace.  We need to write the data from usp to
- *      current->start_stack, so we round each of these in order to be able
- *      to write an integer number of pages.
- */
-struct user {
-        unsigned long   regs[EF_SIZE /          /* integer and fp regs */
-                        sizeof(unsigned long) + 64];
-        size_t          u_tsize;                /* text size (pages) */
-        size_t          u_dsize;                /* data size (pages) */
-        size_t          u_ssize;                /* stack size (pages) */
-        unsigned long   start_code;             /* text starting address */
-        unsigned long   start_data;             /* data starting address */
-        unsigned long   start_stack;            /* stack starting address */
-        long int        signal;                 /* signal causing core dump */
-        unsigned long   u_ar0;                  /* help gdb find registers */
-        unsigned long   magic;                  /* identifies a core file */
-        char            u_comm[32];             /* user command name */
-};
-
-#define NBPG                    PAGE_SIZE
-#define UPAGES                  1
-#define HOST_TEXT_START_ADDR    (u.start_code)
-#define HOST_DATA_START_ADDR    (u.start_data)
-#define HOST_STACK_END_ADDR     (u.start_stack + u.u_ssize * NBPG)
-
-#endif /* _ASM_USER_H */
diff --git a/include/asm-mips/vga.h b/include/asm-mips/vga.h
deleted file mode 100644
index f4cff7e4fa8a..000000000000
--- a/include/asm-mips/vga.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- *      Access to VGA videoram
- *
- *      (c) 1998 Martin Mares <mj@ucw.cz>
- */
-#ifndef _ASM_VGA_H
-#define _ASM_VGA_H
-
-#include <asm/byteorder.h>
-
-/*
- *      On the PC, we can just recalculate addresses and then
- *      access the videoram directly without any black magic.
- */
-
-#define VGA_MAP_MEM(x, s)       (0xb0000000L + (unsigned long)(x))
-
-#define vga_readb(x)    (*(x))
-#define vga_writeb(x, y)        (*(y) = (x))
-
-#define VT_BUF_HAVE_RW
-/*
- *  These are only needed for supporting VGA or MDA text mode, which use little
- *  endian byte ordering.
- *  In other cases, we can optimize by using native byte ordering and
- *  <linux/vt_buffer.h> has already done the right job for us.
- */
-
-#undef scr_writew
-#undef scr_readw
-
-static inline void scr_writew(u16 val, volatile u16 *addr)
-{
-        *addr = cpu_to_le16(val);
-}
-
-static inline u16 scr_readw(volatile const u16 *addr)
-{
-        return le16_to_cpu(*addr);
-}
-
-#define scr_memcpyw(d, s, c) memcpy(d, s, c)
-#define scr_memmovew(d, s, c) memmove(d, s, c)
-#define VT_BUF_HAVE_MEMCPYW
-#define VT_BUF_HAVE_MEMMOVEW
-
-#endif /* _ASM_VGA_H */
diff --git a/include/asm-mips/vpe.h b/include/asm-mips/vpe.h
deleted file mode 100644
index c6e1b961537d..000000000000
--- a/include/asm-mips/vpe.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- * Copyright (C) 2005 MIPS Technologies, Inc.  All rights reserved.
- *
- *  This program is free software; you can distribute it and/or modify it
- *  under the terms of the GNU General Public License (Version 2) as
- *  published by the Free Software Foundation.
- *
- *  This program is distributed in the hope it will be useful, but WITHOUT
- *  ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- *  FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
- *  for more details.
- *
- *  You should have received a copy of the GNU General Public License along
- *  with this program; if not, write to the Free Software Foundation, Inc.,
- *  59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
- *
- */
-
-#ifndef _ASM_VPE_H
-#define _ASM_VPE_H
-
-struct vpe_notifications {
-        void (*start)(int vpe);
-        void (*stop)(int vpe);
-
-        struct list_head list;
-};
-
-
-extern int vpe_notify(int index, struct vpe_notifications *notify);
-
-extern void *vpe_get_shared(int index);
-extern int vpe_getuid(int index);
-extern int vpe_getgid(int index);
-extern char *vpe_getcwd(int index);
-
-#endif /* _ASM_VPE_H */
diff --git a/include/asm-mips/vr41xx/capcella.h b/include/asm-mips/vr41xx/capcella.h
deleted file mode 100644
index e0ee05a3dfcc..000000000000
--- a/include/asm-mips/vr41xx/capcella.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  capcella.h, Include file for ZAO Networks Capcella.
- *
- *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __ZAO_CAPCELLA_H
-#define __ZAO_CAPCELLA_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define PC104PLUS_INTA_PIN              2
-#define PC104PLUS_INTB_PIN              3
-#define PC104PLUS_INTC_PIN              4
-#define PC104PLUS_INTD_PIN              5
-
-/*
- * Interrupt Number
- */
-#define RTL8139_1_IRQ                   GIU_IRQ(PC104PLUS_INTC_PIN)
-#define RTL8139_2_IRQ                   GIU_IRQ(PC104PLUS_INTD_PIN)
-#define PC104PLUS_INTA_IRQ              GIU_IRQ(PC104PLUS_INTA_PIN)
-#define PC104PLUS_INTB_IRQ              GIU_IRQ(PC104PLUS_INTB_PIN)
-#define PC104PLUS_INTC_IRQ              GIU_IRQ(PC104PLUS_INTC_PIN)
-#define PC104PLUS_INTD_IRQ              GIU_IRQ(PC104PLUS_INTD_PIN)
-
-#endif /* __ZAO_CAPCELLA_H */
diff --git a/include/asm-mips/vr41xx/giu.h b/include/asm-mips/vr41xx/giu.h
deleted file mode 100644
index 0bcdd3a5c256..000000000000
--- a/include/asm-mips/vr41xx/giu.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/*
- *  Include file for NEC VR4100 series General-purpose I/O Unit.
- *
- *  Copyright (C) 2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __NEC_VR41XX_GIU_H
-#define __NEC_VR41XX_GIU_H
-
-/*
- * NEC VR4100 series GIU platform device IDs.
- */
-enum {
-        GPIO_50PINS_PULLUPDOWN,
-        GPIO_36PINS,
-        GPIO_48PINS_EDGE_SELECT,
-};
-
-typedef enum {
-        IRQ_TRIGGER_LEVEL,
-        IRQ_TRIGGER_EDGE,
-        IRQ_TRIGGER_EDGE_FALLING,
-        IRQ_TRIGGER_EDGE_RISING,
-} irq_trigger_t;
-
-typedef enum {
-        IRQ_SIGNAL_THROUGH,
-        IRQ_SIGNAL_HOLD,
-} irq_signal_t;
-
-extern void vr41xx_set_irq_trigger(unsigned int pin, irq_trigger_t trigger, irq_signal_t signal);
-
-typedef enum {
-        IRQ_LEVEL_LOW,
-        IRQ_LEVEL_HIGH,
-} irq_level_t;
-
-extern void vr41xx_set_irq_level(unsigned int pin, irq_level_t level);
-
-typedef enum {
-        GPIO_DATA_LOW,
-        GPIO_DATA_HIGH,
-        GPIO_DATA_INVAL,
-} gpio_data_t;
-
-extern gpio_data_t vr41xx_gpio_get_pin(unsigned int pin);
-extern int vr41xx_gpio_set_pin(unsigned int pin, gpio_data_t data);
-
-typedef enum {
-        GPIO_INPUT,
-        GPIO_OUTPUT,
-        GPIO_OUTPUT_DISABLE,
-} gpio_direction_t;
-
-extern int vr41xx_gpio_set_direction(unsigned int pin, gpio_direction_t dir);
-
-typedef enum {
-        GPIO_PULL_DOWN,
-        GPIO_PULL_UP,
-        GPIO_PULL_DISABLE,
-} gpio_pull_t;
-
-extern int vr41xx_gpio_pullupdown(unsigned int pin, gpio_pull_t pull);
-
-#endif /* __NEC_VR41XX_GIU_H */
diff --git a/include/asm-mips/vr41xx/irq.h b/include/asm-mips/vr41xx/irq.h
deleted file mode 100644
index d315dfbc08f2..000000000000
--- a/include/asm-mips/vr41xx/irq.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * include/asm-mips/vr41xx/irq.h
- *
- * Interrupt numbers for NEC VR4100 series.
- *
- * Copyright (C) 1999 Michael Klar
- * Copyright (C) 2001, 2002 Paul Mundt
- * Copyright (C) 2002 MontaVista Software, Inc.
- * Copyright (C) 2002 TimeSys Corp.
- * Copyright (C) 2003-2006 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef __NEC_VR41XX_IRQ_H
-#define __NEC_VR41XX_IRQ_H
-
-/*
- * CPU core Interrupt Numbers
- */
-#define MIPS_CPU_IRQ_BASE       0
-#define MIPS_CPU_IRQ(x)         (MIPS_CPU_IRQ_BASE + (x))
-#define MIPS_SOFTINT0_IRQ       MIPS_CPU_IRQ(0)
-#define MIPS_SOFTINT1_IRQ       MIPS_CPU_IRQ(1)
-#define INT0_IRQ                MIPS_CPU_IRQ(2)
-#define INT1_IRQ                MIPS_CPU_IRQ(3)
-#define INT2_IRQ                MIPS_CPU_IRQ(4)
-#define INT3_IRQ                MIPS_CPU_IRQ(5)
-#define INT4_IRQ                MIPS_CPU_IRQ(6)
-#define TIMER_IRQ               MIPS_CPU_IRQ(7)
-
-/*
- * SYINT1 Interrupt Numbers
- */
-#define SYSINT1_IRQ_BASE        8
-#define SYSINT1_IRQ(x)          (SYSINT1_IRQ_BASE + (x))
-#define BATTRY_IRQ              SYSINT1_IRQ(0)
-#define POWER_IRQ               SYSINT1_IRQ(1)
-#define RTCLONG1_IRQ            SYSINT1_IRQ(2)
-#define ELAPSEDTIME_IRQ         SYSINT1_IRQ(3)
-/* RFU */
-#define PIU_IRQ                 SYSINT1_IRQ(5)
-#define AIU_IRQ                 SYSINT1_IRQ(6)
-#define KIU_IRQ                 SYSINT1_IRQ(7)
-#define GIUINT_IRQ              SYSINT1_IRQ(8)
-#define SIU_IRQ                 SYSINT1_IRQ(9)
-#define BUSERR_IRQ              SYSINT1_IRQ(10)
-#define SOFTINT_IRQ             SYSINT1_IRQ(11)
-#define CLKRUN_IRQ              SYSINT1_IRQ(12)
-#define DOZEPIU_IRQ             SYSINT1_IRQ(13)
-#define SYSINT1_IRQ_LAST        DOZEPIU_IRQ
-
-/*
- * SYSINT2 Interrupt Numbers
- */
-#define SYSINT2_IRQ_BASE        24
-#define SYSINT2_IRQ(x)          (SYSINT2_IRQ_BASE + (x))
-#define RTCLONG2_IRQ            SYSINT2_IRQ(0)
-#define LED_IRQ                 SYSINT2_IRQ(1)
-#define HSP_IRQ                 SYSINT2_IRQ(2)
-#define TCLOCK_IRQ              SYSINT2_IRQ(3)
-#define FIR_IRQ                 SYSINT2_IRQ(4)
-#define CEU_IRQ                 SYSINT2_IRQ(4)  /* same number as FIR_IRQ */
-#define DSIU_IRQ                SYSINT2_IRQ(5)
-#define PCI_IRQ                 SYSINT2_IRQ(6)
-#define SCU_IRQ                 SYSINT2_IRQ(7)
-#define CSI_IRQ                 SYSINT2_IRQ(8)
-#define BCU_IRQ                 SYSINT2_IRQ(9)
-#define ETHERNET_IRQ            SYSINT2_IRQ(10)
-#define SYSINT2_IRQ_LAST        ETHERNET_IRQ
-
-/*
- * GIU Interrupt Numbers
- */
-#define GIU_IRQ_BASE            40
-#define GIU_IRQ(x)              (GIU_IRQ_BASE + (x))    /* IRQ 40-71 */
-#define GIU_IRQ_LAST            GIU_IRQ(31)
-
-/*
- * VRC4173 Interrupt Numbers
- */
-#define VRC4173_IRQ_BASE        72
-#define VRC4173_IRQ(x)          (VRC4173_IRQ_BASE + (x))
-#define VRC4173_USB_IRQ         VRC4173_IRQ(0)
-#define VRC4173_PCMCIA2_IRQ     VRC4173_IRQ(1)
-#define VRC4173_PCMCIA1_IRQ     VRC4173_IRQ(2)
-#define VRC4173_PS2CH2_IRQ      VRC4173_IRQ(3)
-#define VRC4173_PS2CH1_IRQ      VRC4173_IRQ(4)
-#define VRC4173_PIU_IRQ         VRC4173_IRQ(5)
-#define VRC4173_AIU_IRQ         VRC4173_IRQ(6)
-#define VRC4173_KIU_IRQ         VRC4173_IRQ(7)
-#define VRC4173_GIU_IRQ         VRC4173_IRQ(8)
-#define VRC4173_AC97_IRQ        VRC4173_IRQ(9)
-#define VRC4173_AC97INT1_IRQ    VRC4173_IRQ(10)
-/* RFU */
-#define VRC4173_DOZEPIU_IRQ     VRC4173_IRQ(13)
-#define VRC4173_IRQ_LAST        VRC4173_DOZEPIU_IRQ
-
-#endif /* __NEC_VR41XX_IRQ_H */
diff --git a/include/asm-mips/vr41xx/mpc30x.h b/include/asm-mips/vr41xx/mpc30x.h
deleted file mode 100644
index 1d67df843dc3..000000000000
--- a/include/asm-mips/vr41xx/mpc30x.h
+++ /dev/null
@@ -1,37 +0,0 @@
-/*
- *  mpc30x.h, Include file for Victor MP-C303/304.
- *
- *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __VICTOR_MPC30X_H
-#define __VICTOR_MPC30X_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define VRC4173_PIN                     1
-#define MQ200_PIN                       4
-
-/*
- * Interrupt Number
- */
-#define VRC4173_CASCADE_IRQ             GIU_IRQ(VRC4173_PIN)
-#define MQ200_IRQ                       GIU_IRQ(MQ200_PIN)
-
-#endif /* __VICTOR_MPC30X_H */
diff --git a/include/asm-mips/vr41xx/pci.h b/include/asm-mips/vr41xx/pci.h
deleted file mode 100644
index 6fc01ce19777..000000000000
--- a/include/asm-mips/vr41xx/pci.h
+++ /dev/null
@@ -1,90 +0,0 @@
-/*
- *  Include file for NEC VR4100 series PCI Control Unit.
- *
- *  Copyright (C) 2004-2005  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __NEC_VR41XX_PCI_H
-#define __NEC_VR41XX_PCI_H
-
-#define PCI_MASTER_ADDRESS_MASK 0x7fffffffU
-
-struct pci_master_address_conversion {
-        uint32_t bus_base_address;
-        uint32_t address_mask;
-        uint32_t pci_base_address;
-};
-
-struct pci_target_address_conversion {
-        uint32_t address_mask;
-        uint32_t bus_base_address;
-};
-
-typedef enum {
-        CANNOT_LOCK_FROM_DEVICE,
-        CAN_LOCK_FROM_DEVICE,
-} pci_exclusive_access_t;
-
-struct pci_mailbox_address {
-        uint32_t base_address;
-};
-
-struct pci_target_address_window {
-        uint32_t base_address;
-};
-
-typedef enum {
-        PCI_ARBITRATION_MODE_FAIR,
-        PCI_ARBITRATION_MODE_ALTERNATE_0,
-        PCI_ARBITRATION_MODE_ALTERNATE_B,
-} pci_arbiter_priority_control_t;
-
-typedef enum {
-        PCI_TAKE_AWAY_GNT_DISABLE,
-        PCI_TAKE_AWAY_GNT_ENABLE,
-} pci_take_away_gnt_mode_t;
-
-struct pci_controller_unit_setup {
-        struct pci_master_address_conversion *master_memory1;
-        struct pci_master_address_conversion *master_memory2;
-
-        struct pci_target_address_conversion *target_memory1;
-        struct pci_target_address_conversion *target_memory2;
-
-        struct pci_master_address_conversion *master_io;
-
-        pci_exclusive_access_t exclusive_access;
-
-        uint32_t pci_clock_max;
-        uint8_t wait_time_limit_from_irdy_to_trdy;      /* Only VR4122 is supported */
-
-        struct pci_mailbox_address *mailbox;
-        struct pci_target_address_window *target_window1;
-        struct pci_target_address_window *target_window2;
-
-        uint8_t master_latency_timer;
-        uint8_t retry_limit;
-
-        pci_arbiter_priority_control_t arbiter_priority_control;
-        pci_take_away_gnt_mode_t take_away_gnt_mode;
-
-        struct resource *mem_resource;
-        struct resource *io_resource;
-};
-
-extern void vr41xx_pciu_setup(struct pci_controller_unit_setup *setup);
-
-#endif /* __NEC_VR41XX_PCI_H */
diff --git a/include/asm-mips/vr41xx/siu.h b/include/asm-mips/vr41xx/siu.h
deleted file mode 100644
index da9f6e373409..000000000000
--- a/include/asm-mips/vr41xx/siu.h
+++ /dev/null
@@ -1,58 +0,0 @@
-/*
- *  Include file for NEC VR4100 series Serial Interface Unit.
- *
- *  Copyright (C) 2005-2008  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __NEC_VR41XX_SIU_H
-#define __NEC_VR41XX_SIU_H
-
-#define SIU_PORTS_MAX 2
-
-typedef enum {
-        SIU_INTERFACE_RS232C,
-        SIU_INTERFACE_IRDA,
-} siu_interface_t;
-
-extern void vr41xx_select_siu_interface(siu_interface_t interface);
-
-typedef enum {
-        SIU_USE_IRDA,
-        FIR_USE_IRDA,
-} irda_use_t;
-
-extern void vr41xx_use_irda(irda_use_t use);
-
-typedef enum {
-        SHARP_IRDA,
-        TEMIC_IRDA,
-        HP_IRDA,
-} irda_module_t;
-
-typedef enum {
-        IRDA_TX_1_5MBPS,
-        IRDA_TX_4MBPS,
-} irda_speed_t;
-
-extern void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed);
-
-#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
-extern void vr41xx_siu_early_setup(struct uart_port *port);
-#else
-static inline void vr41xx_siu_early_setup(struct uart_port *port) {}
-#endif
-
-#endif /* __NEC_VR41XX_SIU_H */
diff --git a/include/asm-mips/vr41xx/tb0219.h b/include/asm-mips/vr41xx/tb0219.h
deleted file mode 100644
index dc981b4be0a4..000000000000
--- a/include/asm-mips/vr41xx/tb0219.h
+++ /dev/null
@@ -1,42 +0,0 @@
-/*
- *  tb0219.h, Include file for TANBAC TB0219.
- *
- *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  Modified for TANBAC TB0219:
- *  Copyright (C) 2003 Megasolution Inc.  <matsu@megasolution.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TANBAC_TB0219_H
-#define __TANBAC_TB0219_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define TB0219_PCI_SLOT1_PIN            2
-#define TB0219_PCI_SLOT2_PIN            3
-#define TB0219_PCI_SLOT3_PIN            4
-
-/*
- * Interrupt Number
- */
-#define TB0219_PCI_SLOT1_IRQ            GIU_IRQ(TB0219_PCI_SLOT1_PIN)
-#define TB0219_PCI_SLOT2_IRQ            GIU_IRQ(TB0219_PCI_SLOT2_PIN)
-#define TB0219_PCI_SLOT3_IRQ            GIU_IRQ(TB0219_PCI_SLOT3_PIN)
-
-#endif /* __TANBAC_TB0219_H */
diff --git a/include/asm-mips/vr41xx/tb0226.h b/include/asm-mips/vr41xx/tb0226.h
deleted file mode 100644
index de527dcfa5f3..000000000000
--- a/include/asm-mips/vr41xx/tb0226.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  tb0226.h, Include file for TANBAC TB0226.
- *
- *  Copyright (C) 2002-2004  Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TANBAC_TB0226_H
-#define __TANBAC_TB0226_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define GD82559_1_PIN                   2
-#define GD82559_2_PIN                   3
-#define UPD720100_INTA_PIN              4
-#define UPD720100_INTB_PIN              8
-#define UPD720100_INTC_PIN              13
-
-/*
- * Interrupt Number
- */
-#define GD82559_1_IRQ                   GIU_IRQ(GD82559_1_PIN)
-#define GD82559_2_IRQ                   GIU_IRQ(GD82559_2_PIN)
-#define UPD720100_INTA_IRQ              GIU_IRQ(UPD720100_INTA_PIN)
-#define UPD720100_INTB_IRQ              GIU_IRQ(UPD720100_INTB_PIN)
-#define UPD720100_INTC_IRQ              GIU_IRQ(UPD720100_INTC_PIN)
-
-#endif /* __TANBAC_TB0226_H */
diff --git a/include/asm-mips/vr41xx/tb0287.h b/include/asm-mips/vr41xx/tb0287.h
deleted file mode 100644
index 61bead68abf0..000000000000
--- a/include/asm-mips/vr41xx/tb0287.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- *  tb0287.h, Include file for TANBAC TB0287 mini-ITX board.
- *
- *  Copyright (C) 2005  Media Lab Inc. <ito@mlb.co.jp>
- *
- *  This code is largely based on tb0219.h.
- *
- *  This program is free software; you can redistribute it and/or modify
- *  it under the terms of the GNU General Public License as published by
- *  the Free Software Foundation; either version 2 of the License, or
- *  (at your option) any later version.
- *
- *  This program is distributed in the hope that it will be useful,
- *  but WITHOUT ANY WARRANTY; without even the implied warranty of
- *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *  GNU General Public License for more details.
- *
- *  You should have received a copy of the GNU General Public License
- *  along with this program; if not, write to the Free Software
- *  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
- */
-#ifndef __TANBAC_TB0287_H
-#define __TANBAC_TB0287_H
-
-#include <asm/vr41xx/irq.h>
-
-/*
- * General-Purpose I/O Pin Number
- */
-#define TB0287_PCI_SLOT_PIN             2
-#define TB0287_SM501_PIN                3
-#define TB0287_SIL680A_PIN              8
-#define TB0287_RTL8110_PIN              13
-
-/*
- * Interrupt Number
- */
-#define TB0287_PCI_SLOT_IRQ             GIU_IRQ(TB0287_PCI_SLOT_PIN)
-#define TB0287_SM501_IRQ                GIU_IRQ(TB0287_SM501_PIN)
-#define TB0287_SIL680A_IRQ              GIU_IRQ(TB0287_SIL680A_PIN)
-#define TB0287_RTL8110_IRQ              GIU_IRQ(TB0287_RTL8110_PIN)
-
-#endif /* __TANBAC_TB0287_H */
diff --git a/include/asm-mips/vr41xx/vr41xx.h b/include/asm-mips/vr41xx/vr41xx.h
deleted file mode 100644
index 22be64971cc6..000000000000
--- a/include/asm-mips/vr41xx/vr41xx.h
+++ /dev/null
@@ -1,152 +0,0 @@
-/*
- * include/asm-mips/vr41xx/vr41xx.h
- *
- * Include file for NEC VR4100 series.
- *
- * Copyright (C) 1999 Michael Klar
- * Copyright (C) 2001, 2002 Paul Mundt
- * Copyright (C) 2002 MontaVista Software, Inc.
- * Copyright (C) 2002 TimeSys Corp.
- * Copyright (C) 2003-2008 Yoichi Yuasa <yoichi_yuasa@tripeaks.co.jp>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#ifndef __NEC_VR41XX_H
-#define __NEC_VR41XX_H
-
-#include <linux/interrupt.h>
-
-/*
- * CPU Revision
- */
-/* VR4122 0x00000c70-0x00000c72 */
-#define PRID_VR4122_REV1_0      0x00000c70
-#define PRID_VR4122_REV2_0      0x00000c70
-#define PRID_VR4122_REV2_1      0x00000c70
-#define PRID_VR4122_REV3_0      0x00000c71
-#define PRID_VR4122_REV3_1      0x00000c72
-
-/* VR4181A 0x00000c73-0x00000c7f */
-#define PRID_VR4181A_REV1_0     0x00000c73
-#define PRID_VR4181A_REV1_1     0x00000c74
-
-/* VR4131 0x00000c80-0x00000c83 */
-#define PRID_VR4131_REV1_2      0x00000c80
-#define PRID_VR4131_REV2_0      0x00000c81
-#define PRID_VR4131_REV2_1      0x00000c82
-#define PRID_VR4131_REV2_2      0x00000c83
-
-/* VR4133 0x00000c84- */
-#define PRID_VR4133             0x00000c84
-
-/*
- * Bus Control Uint
- */
-extern unsigned long vr41xx_calculate_clock_frequency(void);
-extern unsigned long vr41xx_get_vtclock_frequency(void);
-extern unsigned long vr41xx_get_tclock_frequency(void);
-
-/*
- * Clock Mask Unit
- */
-typedef enum {
-        PIU_CLOCK,
-        SIU_CLOCK,
-        AIU_CLOCK,
-        KIU_CLOCK,
-        FIR_CLOCK,
-        DSIU_CLOCK,
-        CSI_CLOCK,
-        PCIU_CLOCK,
-        HSP_CLOCK,
-        PCI_CLOCK,
-        CEU_CLOCK,
-        ETHER0_CLOCK,
-        ETHER1_CLOCK
-} vr41xx_clock_t;
-
-extern void vr41xx_supply_clock(vr41xx_clock_t clock);
-extern void vr41xx_mask_clock(vr41xx_clock_t clock);
-
-/*
- * Interrupt Control Unit
- */
-extern int vr41xx_set_intassign(unsigned int irq, unsigned char intassign);
-extern int cascade_irq(unsigned int irq, int (*get_irq)(unsigned int));
-
-#define PIUINT_COMMAND          0x0040
-#define PIUINT_DATA             0x0020
-#define PIUINT_PAGE1            0x0010
-#define PIUINT_PAGE0            0x0008
-#define PIUINT_DATALOST         0x0004
-#define PIUINT_STATUSCHANGE     0x0001
-
-extern void vr41xx_enable_piuint(uint16_t mask);
-extern void vr41xx_disable_piuint(uint16_t mask);
-
-#define AIUINT_INPUT_DMAEND     0x0800
-#define AIUINT_INPUT_DMAHALT    0x0400
-#define AIUINT_INPUT_DATALOST   0x0200
-#define AIUINT_INPUT_DATA       0x0100
-#define AIUINT_OUTPUT_DMAEND    0x0008
-#define AIUINT_OUTPUT_DMAHALT   0x0004
-#define AIUINT_OUTPUT_NODATA    0x0002
-
-extern void vr41xx_enable_aiuint(uint16_t mask);
-extern void vr41xx_disable_aiuint(uint16_t mask);
-
-#define KIUINT_DATALOST         0x0004
-#define KIUINT_DATAREADY        0x0002
-#define KIUINT_SCAN             0x0001
-
-extern void vr41xx_enable_kiuint(uint16_t mask);
-extern void vr41xx_disable_kiuint(uint16_t mask);
-
-#define DSIUINT_CTS             0x0800
-#define DSIUINT_RXERR           0x0400
-#define DSIUINT_RX              0x0200
-#define DSIUINT_TX              0x0100
-#define DSIUINT_ALL             0x0f00
-
-extern void vr41xx_enable_dsiuint(uint16_t mask);
-extern void vr41xx_disable_dsiuint(uint16_t mask);
-
-#define FIRINT_UNIT             0x0010
-#define FIRINT_RX_DMAEND        0x0008
-#define FIRINT_RX_DMAHALT       0x0004
-#define FIRINT_TX_DMAEND        0x0002
-#define FIRINT_TX_DMAHALT       0x0001
-
-extern void vr41xx_enable_firint(uint16_t mask);
-extern void vr41xx_disable_firint(uint16_t mask);
-
-extern void vr41xx_enable_pciint(void);
-extern void vr41xx_disable_pciint(void);
-
-extern void vr41xx_enable_scuint(void);
-extern void vr41xx_disable_scuint(void);
-
-#define CSIINT_TX_DMAEND        0x0040
-#define CSIINT_TX_DMAHALT       0x0020
-#define CSIINT_TX_DATA          0x0010
-#define CSIINT_TX_FIFOEMPTY     0x0008
-#define CSIINT_RX_DMAEND        0x0004
-#define CSIINT_RX_DMAHALT       0x0002
-#define CSIINT_RX_FIFOEMPTY     0x0001
-
-extern void vr41xx_enable_csiint(uint16_t mask);
-extern void vr41xx_disable_csiint(uint16_t mask);
-
-extern void vr41xx_enable_bcuint(void);
-extern void vr41xx_disable_bcuint(void);
-
-#ifdef CONFIG_SERIAL_VR41XX_CONSOLE
-extern void vr41xx_siu_setup(void);
-#else
-static inline void vr41xx_siu_setup(void) {}
-#endif
-
-#endif /* __NEC_VR41XX_H */
diff --git a/include/asm-mips/war.h b/include/asm-mips/war.h
deleted file mode 100644
index 22361d5e3bf0..000000000000
--- a/include/asm-mips/war.h
+++ /dev/null
@@ -1,244 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2002, 2004, 2007 by Ralf Baechle
- * Copyright (C) 2007  Maciej W. Rozycki
- */
-#ifndef _ASM_WAR_H
-#define _ASM_WAR_H
-
-#include <war.h>
-
-/*
- * Work around certain R4000 CPU errata (as implemented by GCC):
- *
- * - A double-word or a variable shift may give an incorrect result
- *   if executed immediately after starting an integer division:
- *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
- *   erratum #28
- *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
- *   #19
- *
- * - A double-word or a variable shift may give an incorrect result
- *   if executed while an integer multiplication is in progress:
- *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
- *   errata #16 & #28
- *
- * - An integer division may give an incorrect result if started in
- *   a delay slot of a taken branch or a jump:
- *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
- *   erratum #52
- */
-#ifdef CONFIG_CPU_R4000_WORKAROUNDS
-#define R4000_WAR 1
-#else
-#define R4000_WAR 0
-#endif
-
-/*
- * Work around certain R4400 CPU errata (as implemented by GCC):
- *
- * - A double-word or a variable shift may give an incorrect result
- *   if executed immediately after starting an integer division:
- *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #10
- *   "MIPS R4400MC Errata, Processor Revision 2.0 & 3.0", erratum #4
- */
-#ifdef CONFIG_CPU_R4400_WORKAROUNDS
-#define R4400_WAR 1
-#else
-#define R4400_WAR 0
-#endif
-
-/*
- * Work around the "daddi" and "daddiu" CPU errata:
- *
- * - The `daddi' instruction fails to trap on overflow.
- *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
- *   erratum #23
- *
- * - The `daddiu' instruction can produce an incorrect result.
- *   "MIPS R4000PC/SC Errata, Processor Revision 2.2 and 3.0",
- *   erratum #41
- *   "MIPS R4000MC Errata, Processor Revision 2.2 and 3.0", erratum
- *   #15
- *   "MIPS R4400PC/SC Errata, Processor Revision 1.0", erratum #7
- *   "MIPS R4400MC Errata, Processor Revision 1.0", erratum #5
- */
-#ifdef CONFIG_CPU_DADDI_WORKAROUNDS
-#define DADDI_WAR 1
-#else
-#define DADDI_WAR 0
-#endif
-
-/*
- * Another R4600 erratum.  Due to the lack of errata information the exact
- * technical details aren't known.  I've experimentally found that disabling
- * interrupts during indexed I-cache flushes seems to be sufficient to deal
- * with the issue.
- */
-#ifndef R4600_V1_INDEX_ICACHEOP_WAR
-#error Check setting of R4600_V1_INDEX_ICACHEOP_WAR for your platform
-#endif
-
-/*
- * Pleasures of the R4600 V1.x.  Cite from the IDT R4600 V1.7 errata:
- *
- *  18. The CACHE instructions Hit_Writeback_Invalidate_D, Hit_Writeback_D,
- *      Hit_Invalidate_D and Create_Dirty_Excl_D should only be
- *      executed if there is no other dcache activity. If the dcache is
- *      accessed for another instruction immeidately preceding when these
- *      cache instructions are executing, it is possible that the dcache
- *      tag match outputs used by these cache instructions will be
- *      incorrect. These cache instructions should be preceded by at least
- *      four instructions that are not any kind of load or store
- *      instruction.
- *
- *      This is not allowed:    lw
- *                              nop
- *                              nop
- *                              nop
- *                              cache       Hit_Writeback_Invalidate_D
- *
- *      This is allowed:        lw
- *                              nop
- *                              nop
- *                              nop
- *                              nop
- *                              cache       Hit_Writeback_Invalidate_D
- */
-#ifndef R4600_V1_HIT_CACHEOP_WAR
-#error Check setting of R4600_V1_HIT_CACHEOP_WAR for your platform
-#endif
-
-
-/*
- * Writeback and invalidate the primary cache dcache before DMA.
- *
- * R4600 v2.0 bug: "The CACHE instructions Hit_Writeback_Inv_D,
- * Hit_Writeback_D, Hit_Invalidate_D and Create_Dirty_Exclusive_D will only
- * operate correctly if the internal data cache refill buffer is empty.  These
- * CACHE instructions should be separated from any potential data cache miss
- * by a load instruction to an uncached address to empty the response buffer."
- * (Revision 2.0 device errata from IDT available on http://www.idt.com/
- * in .pdf format.)
- */
-#ifndef R4600_V2_HIT_CACHEOP_WAR
-#error Check setting of R4600_V2_HIT_CACHEOP_WAR for your platform
-#endif
-
-/*
- * When an interrupt happens on a CP0 register read instruction, CPU may
- * lock up or read corrupted values of CP0 registers after it enters
- * the exception handler.
- *
- * This workaround makes sure that we read a "safe" CP0 register as the
- * first thing in the exception handler, which breaks one of the
- * pre-conditions for this problem.
- */
-#ifndef R5432_CP0_INTERRUPT_WAR
-#error Check setting of R5432_CP0_INTERRUPT_WAR for your platform
-#endif
-
-/*
- * Workaround for the Sibyte M3 errata the text of which can be found at
- *
- *   http://sibyte.broadcom.com/hw/bcm1250/docs/pass2errata.txt
- *
- * This will enable the use of a special TLB refill handler which does a
- * consistency check on the information in c0_badvaddr and c0_entryhi and
- * will just return and take the exception again if the information was
- * found to be inconsistent.
- */
-#ifndef BCM1250_M3_WAR
-#error Check setting of BCM1250_M3_WAR for your platform
-#endif
-
-/*
- * This is a DUART workaround related to glitches around register accesses
- */
-#ifndef SIBYTE_1956_WAR
-#error Check setting of SIBYTE_1956_WAR for your platform
-#endif
-
-/*
- * Fill buffers not flushed on CACHE instructions
- *
- * Hit_Invalidate_I cacheops invalidate an icache line but the refill
- * for that line can get stale data from the fill buffer instead of
- * accessing memory if the previous icache miss was also to that line.
- *
- * Workaround: generate an icache refill from a different line
- *
- * Affects:
- *  MIPS 4K             RTL revision <3.0, PRID revision <4
- */
-#ifndef MIPS4K_ICACHE_REFILL_WAR
-#error Check setting of MIPS4K_ICACHE_REFILL_WAR for your platform
-#endif
-
-/*
- * Missing implicit forced flush of evictions caused by CACHE
- * instruction
- *
- * Evictions caused by a CACHE instructions are not forced on to the
- * bus. The BIU gives higher priority to fetches than to the data from
- * the eviction buffer and no collision detection is performed between
- * fetches and pending data from the eviction buffer.
- *
- * Workaround: Execute a SYNC instruction after the cache instruction
- *
- * Affects:
- *   MIPS 5Kc,5Kf       RTL revision <2.3, PRID revision <8
- *   MIPS 20Kc          RTL revision <4.0, PRID revision <?
- */
-#ifndef MIPS_CACHE_SYNC_WAR
-#error Check setting of MIPS_CACHE_SYNC_WAR for your platform
-#endif
-
-/*
- * From TX49/H2 manual: "If the instruction (i.e. CACHE) is issued for
- * the line which this instruction itself exists, the following
- * operation is not guaranteed."
- *
- * Workaround: do two phase flushing for Index_Invalidate_I
- */
-#ifndef TX49XX_ICACHE_INDEX_INV_WAR
-#error Check setting of TX49XX_ICACHE_INDEX_INV_WAR for your platform
-#endif
-
-/*
- * On the RM9000 there is a problem which makes the CreateDirtyExclusive
- * eache operation unusable on SMP systems.
- */
-#ifndef RM9000_CDEX_SMP_WAR
-#error Check setting of RM9000_CDEX_SMP_WAR for your platform
-#endif
-
-/*
- * The RM7000 processors and the E9000 cores have a bug (though PMC-Sierra
- * opposes it being called that) where invalid instructions in the same
- * I-cache line worth of instructions being fetched may case spurious
- * exceptions.
- */
-#ifndef ICACHE_REFILLS_WORKAROUND_WAR
-#error Check setting of ICACHE_REFILLS_WORKAROUND_WAR for your platform
-#endif
-
-/*
- * On the R10000 upto version 2.6 (not sure about 2.7) there is a bug that
- * may cause ll / sc and lld / scd sequences to execute non-atomically.
- */
-#ifndef R10000_LLSC_WAR
-#error Check setting of R10000_LLSC_WAR for your platform
-#endif
-
-/*
- * 34K core erratum: "Problems Executing the TLBR Instruction"
- */
-#ifndef MIPS34K_MISSED_ITLB_WAR
-#error Check setting of MIPS34K_MISSED_ITLB_WAR for your platform
-#endif
-
-#endif /* _ASM_WAR_H */
diff --git a/include/asm-mips/wbflush.h b/include/asm-mips/wbflush.h
deleted file mode 100644
index eadc0ac47e24..000000000000
--- a/include/asm-mips/wbflush.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Header file for using the wbflush routine
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (c) 1998 Harald Koerfgen
- * Copyright (C) 2002 Maciej W. Rozycki
- */
-#ifndef _ASM_WBFLUSH_H
-#define _ASM_WBFLUSH_H
-
-
-#ifdef CONFIG_CPU_HAS_WB
-
-extern void (*__wbflush)(void);
-extern void wbflush_setup(void);
-
-#define wbflush()                       \
-        do {                            \
-                __sync();               \
-                __wbflush();            \
-        } while (0)
-
-#else /* !CONFIG_CPU_HAS_WB */
-
-#define wbflush_setup() do { } while (0)
-
-#define wbflush() fast_iob()
-
-#endif /* !CONFIG_CPU_HAS_WB */
-
-#endif /* _ASM_WBFLUSH_H */
diff --git a/include/asm-mips/xor.h b/include/asm-mips/xor.h
deleted file mode 100644
index c82eb12a5b18..000000000000
--- a/include/asm-mips/xor.h
+++ /dev/null
@@ -1 +0,0 @@
-#include <asm-generic/xor.h>
diff --git a/include/asm-mips/xtalk/xtalk.h b/include/asm-mips/xtalk/xtalk.h
deleted file mode 100644
index 79bac882a739..000000000000
--- a/include/asm-mips/xtalk/xtalk.h
+++ /dev/null
@@ -1,52 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * xtalk.h -- platform-independent crosstalk interface, derived from
- * IRIX <sys/PCI/bridge.h>, revision 1.38.
- *
- * Copyright (C) 1995 - 1997, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_XTALK_XTALK_H
-#define _ASM_XTALK_XTALK_H
-
-#ifndef __ASSEMBLY__
-/*
- * User-level device driver visible types
- */
-typedef char            xwidgetnum_t;   /* xtalk widget number  (0..15) */
-
-#define XWIDGET_NONE            -1
-
-typedef int xwidget_part_num_t; /* xtalk widget part number */
-
-#define XWIDGET_PART_NUM_NONE   -1
-
-typedef int             xwidget_rev_num_t;      /* xtalk widget revision number */
-
-#define XWIDGET_REV_NUM_NONE    -1
-
-typedef int xwidget_mfg_num_t;  /* xtalk widget manufacturing ID */
-
-#define XWIDGET_MFG_NUM_NONE    -1
-
-typedef struct xtalk_piomap_s *xtalk_piomap_t;
-
-/* It is often convenient to fold the XIO target port
- * number into the XIO address.
- */
-#define XIO_NOWHERE     (0xFFFFFFFFFFFFFFFFull)
-#define XIO_ADDR_BITS   (0x0000FFFFFFFFFFFFull)
-#define XIO_PORT_BITS   (0xF000000000000000ull)
-#define XIO_PORT_SHIFT  (60)
-
-#define XIO_PACKED(x)   (((x)&XIO_PORT_BITS) != 0)
-#define XIO_ADDR(x)     ((x)&XIO_ADDR_BITS)
-#define XIO_PORT(x)     ((xwidgetnum_t)(((x)&XIO_PORT_BITS) >> XIO_PORT_SHIFT))
-#define XIO_PACK(p, o)  ((((uint64_t)(p))<<XIO_PORT_SHIFT) | ((o)&XIO_ADDR_BITS))
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_XTALK_XTALK_H */
diff --git a/include/asm-mips/xtalk/xwidget.h b/include/asm-mips/xtalk/xwidget.h
deleted file mode 100644
index b4a13d7405ee..000000000000
--- a/include/asm-mips/xtalk/xwidget.h
+++ /dev/null
@@ -1,167 +0,0 @@
-/*
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * xwidget.h - generic crosstalk widget header file, derived from IRIX
- * <sys/xtalk/xtalkwidget.h>, revision 1.32.
- *
- * Copyright (C) 1996, 1999 Silcon Graphics, Inc.
- * Copyright (C) 1999 Ralf Baechle (ralf@gnu.org)
- */
-#ifndef _ASM_XTALK_XWIDGET_H
-#define _ASM_XTALK_XWIDGET_H
-
-#include <linux/types.h>
-#include <asm/xtalk/xtalk.h>
-
-#define WIDGET_ID                       0x04
-#define WIDGET_STATUS                   0x0c
-#define WIDGET_ERR_UPPER_ADDR           0x14
-#define WIDGET_ERR_LOWER_ADDR           0x1c
-#define WIDGET_CONTROL                  0x24
-#define WIDGET_REQ_TIMEOUT              0x2c
-#define WIDGET_INTDEST_UPPER_ADDR       0x34
-#define WIDGET_INTDEST_LOWER_ADDR       0x3c
-#define WIDGET_ERR_CMD_WORD             0x44
-#define WIDGET_LLP_CFG                  0x4c
-#define WIDGET_TFLUSH                   0x54
-
-/* WIDGET_ID */
-#define WIDGET_REV_NUM                  0xf0000000
-#define WIDGET_PART_NUM                 0x0ffff000
-#define WIDGET_MFG_NUM                  0x00000ffe
-#define WIDGET_REV_NUM_SHFT             28
-#define WIDGET_PART_NUM_SHFT            12
-#define WIDGET_MFG_NUM_SHFT             1
-
-#define XWIDGET_PART_NUM(widgetid) (((widgetid) & WIDGET_PART_NUM) >> WIDGET_PART_NUM_SHFT)
-#define XWIDGET_REV_NUM(widgetid) (((widgetid) & WIDGET_REV_NUM) >> WIDGET_REV_NUM_SHFT)
-#define XWIDGET_MFG_NUM(widgetid) (((widgetid) & WIDGET_MFG_NUM) >> WIDGET_MFG_NUM_SHFT)
-
-/* WIDGET_STATUS */
-#define WIDGET_LLP_REC_CNT              0xff000000
-#define WIDGET_LLP_TX_CNT               0x00ff0000
-#define WIDGET_PENDING                  0x0000001f
-
-/* WIDGET_ERR_UPPER_ADDR */
-#define WIDGET_ERR_UPPER_ADDR_ONLY      0x0000ffff
-
-/* WIDGET_CONTROL */
-#define WIDGET_F_BAD_PKT                0x00010000
-#define WIDGET_LLP_XBAR_CRD             0x0000f000
-#define WIDGET_LLP_XBAR_CRD_SHFT        12
-#define WIDGET_CLR_RLLP_CNT             0x00000800
-#define WIDGET_CLR_TLLP_CNT             0x00000400
-#define WIDGET_SYS_END                  0x00000200
-#define WIDGET_MAX_TRANS                0x000001f0
-#define WIDGET_WIDGET_ID                0x0000000f
-
-/* WIDGET_INTDEST_UPPER_ADDR */
-#define WIDGET_INT_VECTOR               0xff000000
-#define WIDGET_INT_VECTOR_SHFT          24
-#define WIDGET_TARGET_ID                0x000f0000
-#define WIDGET_TARGET_ID_SHFT           16
-#define WIDGET_UPP_ADDR                 0x0000ffff
-
-/* WIDGET_ERR_CMD_WORD */
-#define WIDGET_DIDN                     0xf0000000
-#define WIDGET_SIDN                     0x0f000000
-#define WIDGET_PACTYP                   0x00f00000
-#define WIDGET_TNUM                     0x000f8000
-#define WIDGET_COHERENT                 0x00004000
-#define WIDGET_DS                       0x00003000
-#define WIDGET_GBR                      0x00000800
-#define WIDGET_VBPM                     0x00000400
-#define WIDGET_ERROR                    0x00000200
-#define WIDGET_BARRIER                  0x00000100
-
-/* WIDGET_LLP_CFG */
-#define WIDGET_LLP_MAXRETRY             0x03ff0000
-#define WIDGET_LLP_MAXRETRY_SHFT        16
-#define WIDGET_LLP_NULLTIMEOUT          0x0000fc00
-#define WIDGET_LLP_NULLTIMEOUT_SHFT     10
-#define WIDGET_LLP_MAXBURST             0x000003ff
-#define WIDGET_LLP_MAXBURST_SHFT        0
-
-/*
- * according to the crosstalk spec, only 32-bits access to the widget
- * configuration registers is allowed.  some widgets may allow 64-bits
- * access but software should not depend on it.  registers beyond the
- * widget target flush register are widget dependent thus will not be
- * defined here
- */
-#ifndef __ASSEMBLY__
-typedef u32 widgetreg_t;
-
-/* widget configuration registers */
-typedef volatile struct widget_cfg {
-        widgetreg_t             w_pad_0;                /* 0x00 */
-        widgetreg_t             w_id;                   /* 0x04 */
-        widgetreg_t             w_pad_1;                /* 0x08 */
-        widgetreg_t             w_status;               /* 0x0c */
-        widgetreg_t             w_pad_2;                /* 0x10 */
-        widgetreg_t             w_err_upper_addr;       /* 0x14 */
-        widgetreg_t             w_pad_3;                /* 0x18 */
-        widgetreg_t             w_err_lower_addr;       /* 0x1c */
-        widgetreg_t             w_pad_4;                /* 0x20 */
-        widgetreg_t             w_control;              /* 0x24 */
-        widgetreg_t             w_pad_5;                /* 0x28 */
-        widgetreg_t             w_req_timeout;          /* 0x2c */
-        widgetreg_t             w_pad_6;                /* 0x30 */
-        widgetreg_t             w_intdest_upper_addr;   /* 0x34 */
-        widgetreg_t             w_pad_7;                /* 0x38 */
-        widgetreg_t             w_intdest_lower_addr;   /* 0x3c */
-        widgetreg_t             w_pad_8;                /* 0x40 */
-        widgetreg_t             w_err_cmd_word;         /* 0x44 */
-        widgetreg_t             w_pad_9;                /* 0x48 */
-        widgetreg_t             w_llp_cfg;              /* 0x4c */
-        widgetreg_t             w_pad_10;               /* 0x50 */
-        widgetreg_t             w_tflush;               /* 0x54 */
-} widget_cfg_t;
-
-typedef struct {
-        unsigned        didn:4;
-        unsigned        sidn:4;
-        unsigned        pactyp:4;
-        unsigned        tnum:5;
-        unsigned        ct:1;
-        unsigned        ds:2;
-        unsigned        gbr:1;
-        unsigned        vbpm:1;
-        unsigned        error:1;
-        unsigned        bo:1;
-        unsigned        other:8;
-} w_err_cmd_word_f;
-
-typedef union {
-        widgetreg_t             r;
-        w_err_cmd_word_f        f;
-} w_err_cmd_word_u;
-
-typedef struct xwidget_info_s *xwidget_info_t;
-
-/*
- * Crosstalk Widget Hardware Identification, as defined in the Crosstalk spec.
- */
-typedef struct xwidget_hwid_s {
-        xwidget_part_num_t      part_num;
-        xwidget_rev_num_t       rev_num;
-        xwidget_mfg_num_t       mfg_num;
-} *xwidget_hwid_t;
-
-
-/*
- * Returns 1 if a driver that handles devices described by hwid1 is able
- * to manage a device with hardwareid hwid2.  NOTE: We don't check rev
- * numbers at all.
- */
-#define XWIDGET_HARDWARE_ID_MATCH(hwid1, hwid2) \
-        (((hwid1)->part_num == (hwid2)->part_num) && \
-        (((hwid1)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
-        ((hwid2)->mfg_num == XWIDGET_MFG_NUM_NONE) || \
-        ((hwid1)->mfg_num == (hwid2)->mfg_num)))
-
-#endif /* !__ASSEMBLY__ */
-
-#endif /* _ASM_XTALK_XWIDGET_H */
diff --git a/include/asm-mn10300/elf.h b/include/asm-mn10300/elf.h
index 256a70466ca4..bf09f8bb392e 100644
--- a/include/asm-mn10300/elf.h
+++ b/include/asm-mn10300/elf.h
@@ -141,7 +141,7 @@ do {						\
 #define ELF_PLATFORM  (NULL)
 
 #ifdef __KERNEL__
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX)
 #endif
 
 #endif /* _ASM_ELF_H */
diff --git a/include/asm-parisc/a.out.h b/include/asm-parisc/a.out.h
deleted file mode 100644
index eb04e34c5bb1..000000000000
--- a/include/asm-parisc/a.out.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __PARISC_A_OUT_H__
-#define __PARISC_A_OUT_H__
-
-struct exec
-{
-  unsigned int a_info;          /* Use macros N_MAGIC, etc for access */
-  unsigned a_text;              /* length of text, in bytes */
-  unsigned a_data;              /* length of data, in bytes */
-  unsigned a_bss;               /* length of uninitialized data area for file, in bytes */
-  unsigned a_syms;              /* length of symbol table data in file, in bytes */
-  unsigned a_entry;             /* start address */
-  unsigned a_trsize;            /* length of relocation info for text, in bytes */
-  unsigned a_drsize;            /* length of relocation info for data, in bytes */
-};
-
-#define N_TRSIZE(a)     ((a).a_trsize)
-#define N_DRSIZE(a)     ((a).a_drsize)
-#define N_SYMSIZE(a)    ((a).a_syms)
-
-#endif /* __A_OUT_GNU_H__ */
diff --git a/include/asm-parisc/elf.h b/include/asm-parisc/elf.h
index d0a4a8262818..7fa675799e6d 100644
--- a/include/asm-parisc/elf.h
+++ b/include/asm-parisc/elf.h
@@ -236,7 +236,7 @@ typedef unsigned long elf_greg_t;
 
 #define ELF_PLATFORM  ("PARISC\0")
 
-#define SET_PERSONALITY(ex, ibcs2) \
+#define SET_PERSONALITY(ex) \
         current->personality = PER_LINUX; \
         current->thread.map_base = DEFAULT_MAP_BASE; \
         current->thread.task_size = DEFAULT_TASK_SIZE \
diff --git a/include/asm-parisc/sections.h b/include/asm-parisc/sections.h
index fdd43ec42ec5..9d13c3507ad6 100644
--- a/include/asm-parisc/sections.h
+++ b/include/asm-parisc/sections.h
@@ -4,4 +4,9 @@
 /* nothing to see, move along */
 #include <asm-generic/sections.h>
 
+#ifdef CONFIG_64BIT
+#undef dereference_function_descriptor
+void *dereference_function_descriptor(void *);
+#endif
+
 #endif
diff --git a/include/asm-parisc/siginfo.h b/include/asm-parisc/siginfo.h
index d4909f55fe35..d7034728f377 100644
--- a/include/asm-parisc/siginfo.h
+++ b/include/asm-parisc/siginfo.h
@@ -3,11 +3,6 @@
 
 #include <asm-generic/siginfo.h>
 
-/*
- * SIGTRAP si_codes
- */
-#define TRAP_BRANCH     (__SI_FAULT|3)  /* process taken branch trap */
-#define TRAP_HWBKPT     (__SI_FAULT|4)  /* hardware breakpoint or watchpoint */
 #undef NSIGTRAP
 #define NSIGTRAP        4
 
diff --git a/include/asm-parisc/statfs.h b/include/asm-parisc/statfs.h
index 1d2b8130b23d..324bea905dc6 100644
--- a/include/asm-parisc/statfs.h
+++ b/include/asm-parisc/statfs.h
@@ -1,58 +1,7 @@
 #ifndef _PARISC_STATFS_H
 #define _PARISC_STATFS_H
 
-#ifndef __KERNEL_STRICT_NAMES
-
-#include <linux/types.h>
-
-typedef __kernel_fsid_t fsid_t;
-
-#endif
-
-/*
- * It appears that PARISC could be 64 _or_ 32 bit.
- * 64-bit fields must be explicitly 64-bit in statfs64.
- */
-struct statfs {
-        long f_type;
-        long f_bsize;
-        long f_blocks;
-        long f_bfree;
-        long f_bavail;
-        long f_files;
-        long f_ffree;
-        __kernel_fsid_t f_fsid;
-        long f_namelen;
-        long f_frsize;
-        long f_spare[5];
-};
-
-struct statfs64 {
-        long f_type;
-        long f_bsize;
-        __u64 f_blocks;
-        __u64 f_bfree;
-        __u64 f_bavail;
-        __u64 f_files;
-        __u64 f_ffree;
-        __kernel_fsid_t f_fsid;
-        long f_namelen;
-        long f_frsize;
-        long f_spare[5];
-};
-
-struct compat_statfs64 {
-        __u32 f_type;
-        __u32 f_bsize;
-        __u64 f_blocks;
-        __u64 f_bfree;
-        __u64 f_bavail;
-        __u64 f_files;
-        __u64 f_ffree;
-        __kernel_fsid_t f_fsid;
-        __u32 f_namelen;
-        __u32 f_frsize;
-        __u32 f_spare[5];
-};
+#define __statfs_word long
+#include <asm-generic/statfs.h>
 
 #endif
diff --git a/include/asm-um/dma-mapping.h b/include/asm-um/dma-mapping.h
index f0ee4fb55911..90fc708b320e 100644
--- a/include/asm-um/dma-mapping.h
+++ b/include/asm-um/dma-mapping.h
@@ -118,4 +118,11 @@ dma_cache_sync(struct device *dev, void *vaddr, size_t size,
         BUG();
 }
 
+static inline int
+dma_mapping_error(struct device *dev, dma_addr_t dma_handle)
+{
+        BUG();
+        return 0;
+}
+
 #endif
diff --git a/include/asm-um/elf-i386.h b/include/asm-um/elf-i386.h
index 23d6893e8617..d0da9d7c5371 100644
--- a/include/asm-um/elf-i386.h
+++ b/include/asm-um/elf-i386.h
@@ -86,7 +86,7 @@ extern long elf_aux_hwcap;
 extern char * elf_aux_platform;
 #define ELF_PLATFORM (elf_aux_platform)
 
-#define SET_PERSONALITY(ex, ibcs2) do { } while (0)
+#define SET_PERSONALITY(ex) do { } while (0)
 
 extern unsigned long vsyscall_ehdr;
 extern unsigned long vsyscall_end;
diff --git a/include/asm-um/elf-ppc.h b/include/asm-um/elf-ppc.h
index d3b90b7ac3e9..af9463cd8ce5 100644
--- a/include/asm-um/elf-ppc.h
+++ b/include/asm-um/elf-ppc.h
@@ -5,7 +5,7 @@
 extern long elf_aux_hwcap;
 #define ELF_HWCAP (elf_aux_hwcap)
 
-#define SET_PERSONALITY(ex, ibcs2) do ; while(0)
+#define SET_PERSONALITY(ex) do ; while(0)
 
 #define ELF_EXEC_PAGESIZE 4096
 
diff --git a/include/asm-um/elf-x86_64.h b/include/asm-um/elf-x86_64.h
index 3b2d5224a7e1..6e8a9195e952 100644
--- a/include/asm-um/elf-x86_64.h
+++ b/include/asm-um/elf-x86_64.h
@@ -114,6 +114,6 @@ extern long elf_aux_hwcap;
 
 #define ELF_PLATFORM "x86_64"
 
-#define SET_PERSONALITY(ex, ibcs2) do ; while(0)
+#define SET_PERSONALITY(ex) do ; while(0)
 
 #endif
diff --git a/include/asm-x86/a.out-core.h b/include/asm-x86/a.out-core.h
index 714207a1c387..f5705761a37b 100644
--- a/include/asm-x86/a.out-core.h
+++ b/include/asm-x86/a.out-core.h
@@ -9,8 +9,8 @@
  * 2 of the Licence, or (at your option) any later version.
  */
 
-#ifndef _ASM_A_OUT_CORE_H
-#define _ASM_A_OUT_CORE_H
+#ifndef ASM_X86__A_OUT_CORE_H
+#define ASM_X86__A_OUT_CORE_H
 
 #ifdef __KERNEL__
 #ifdef CONFIG_X86_32
@@ -70,4 +70,4 @@ static inline void aout_dump_thread(struct pt_regs *regs, struct user *dump)
 
 #endif /* CONFIG_X86_32 */
 #endif /* __KERNEL__ */
-#endif /* _ASM_A_OUT_CORE_H */
+#endif /* ASM_X86__A_OUT_CORE_H */
diff --git a/include/asm-x86/a.out.h b/include/asm-x86/a.out.h
index 4684f97a5bbd..0948748bc69c 100644
--- a/include/asm-x86/a.out.h
+++ b/include/asm-x86/a.out.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_A_OUT_H
-#define _ASM_X86_A_OUT_H
+#ifndef ASM_X86__A_OUT_H
+#define ASM_X86__A_OUT_H
 
 struct exec
 {
@@ -17,4 +17,4 @@ struct exec
 #define N_DRSIZE(a)     ((a).a_drsize)
 #define N_SYMSIZE(a)    ((a).a_syms)
 
-#endif /* _ASM_X86_A_OUT_H */
+#endif /* ASM_X86__A_OUT_H */
diff --git a/include/asm-x86/acpi.h b/include/asm-x86/acpi.h
index 635d764dc13e..392e17336be1 100644
--- a/include/asm-x86/acpi.h
+++ b/include/asm-x86/acpi.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_ACPI_H
-#define _ASM_X86_ACPI_H
+#ifndef ASM_X86__ACPI_H
+#define ASM_X86__ACPI_H
 
 /*
  *  Copyright (C) 2001 Paul Diefenbaugh <paul.s.diefenbaugh@intel.com>
@@ -140,6 +140,8 @@ static inline unsigned int acpi_processor_cstate_check(unsigned int max_cstate)
             boot_cpu_data.x86_model <= 0x05 &&
             boot_cpu_data.x86_mask < 0x0A)
                 return 1;
+        else if (boot_cpu_has(X86_FEATURE_AMDC1E))
+                return 1;
         else
                 return max_cstate;
 }
@@ -173,4 +175,4 @@ static inline void acpi_fake_nodes(const struct bootnode *fake_nodes,
 
 #define acpi_unlazy_tlb(x)      leave_mm(x)
 
-#endif /*__X86_ASM_ACPI_H*/
+#endif /* ASM_X86__ACPI_H */
diff --git a/include/asm-x86/agp.h b/include/asm-x86/agp.h
index e4004a9f6a9a..3617fd4fcdf9 100644
--- a/include/asm-x86/agp.h
+++ b/include/asm-x86/agp.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_AGP_H
-#define _ASM_X86_AGP_H
+#ifndef ASM_X86__AGP_H
+#define ASM_X86__AGP_H
 
 #include <asm/pgtable.h>
 #include <asm/cacheflush.h>
@@ -32,4 +32,4 @@
 #define free_gatt_pages(table, order)   \
         free_pages((unsigned long)(table), (order))
 
-#endif
+#endif /* ASM_X86__AGP_H */
diff --git a/include/asm-x86/alternative.h b/include/asm-x86/alternative.h
index f6aa18eadf71..22d3c9862bf3 100644
--- a/include/asm-x86/alternative.h
+++ b/include/asm-x86/alternative.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_ALTERNATIVE_H
-#define _ASM_X86_ALTERNATIVE_H
+#ifndef ASM_X86__ALTERNATIVE_H
+#define ASM_X86__ALTERNATIVE_H
 
 #include <linux/types.h>
 #include <linux/stddef.h>
@@ -180,4 +180,4 @@ extern void add_nops(void *insns, unsigned int len);
 extern void *text_poke(void *addr, const void *opcode, size_t len);
 extern void *text_poke_early(void *addr, const void *opcode, size_t len);
 
-#endif /* _ASM_X86_ALTERNATIVE_H */
+#endif /* ASM_X86__ALTERNATIVE_H */
diff --git a/include/asm-x86/amd_iommu.h b/include/asm-x86/amd_iommu.h
index 30a12049353b..041d0db7da27 100644
--- a/include/asm-x86/amd_iommu.h
+++ b/include/asm-x86/amd_iommu.h
@@ -17,16 +17,19 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-#ifndef _ASM_X86_AMD_IOMMU_H
-#define _ASM_X86_AMD_IOMMU_H
+#ifndef ASM_X86__AMD_IOMMU_H
+#define ASM_X86__AMD_IOMMU_H
+
+#include <linux/irqreturn.h>
 
 #ifdef CONFIG_AMD_IOMMU
 extern int amd_iommu_init(void);
 extern int amd_iommu_init_dma_ops(void);
 extern void amd_iommu_detect(void);
+extern irqreturn_t amd_iommu_int_handler(int irq, void *data);
 #else
 static inline int amd_iommu_init(void) { return -ENODEV; }
 static inline void amd_iommu_detect(void) { }
 #endif
 
-#endif
+#endif /* ASM_X86__AMD_IOMMU_H */
diff --git a/include/asm-x86/amd_iommu_types.h b/include/asm-x86/amd_iommu_types.h
index dcc812067394..b3085869a17b 100644
--- a/include/asm-x86/amd_iommu_types.h
+++ b/include/asm-x86/amd_iommu_types.h
@@ -17,8 +17,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-#ifndef __AMD_IOMMU_TYPES_H__
-#define __AMD_IOMMU_TYPES_H__
+#ifndef ASM_X86__AMD_IOMMU_TYPES_H
+#define ASM_X86__AMD_IOMMU_TYPES_H
 
 #include <linux/types.h>
 #include <linux/list.h>
@@ -37,6 +37,7 @@
 /* Capability offsets used by the driver */
 #define MMIO_CAP_HDR_OFFSET     0x00
 #define MMIO_RANGE_OFFSET       0x0c
+#define MMIO_MISC_OFFSET        0x10
 
 /* Masks, shifts and macros to parse the device range capability */
 #define MMIO_RANGE_LD_MASK      0xff000000
@@ -48,6 +49,7 @@
 #define MMIO_GET_LD(x)  (((x) & MMIO_RANGE_LD_MASK) >> MMIO_RANGE_LD_SHIFT)
 #define MMIO_GET_FD(x)  (((x) & MMIO_RANGE_FD_MASK) >> MMIO_RANGE_FD_SHIFT)
 #define MMIO_GET_BUS(x) (((x) & MMIO_RANGE_BUS_MASK) >> MMIO_RANGE_BUS_SHIFT)
+#define MMIO_MSI_NUM(x) ((x) & 0x1f)
 
 /* Flag masks for the AMD IOMMU exclusion range */
 #define MMIO_EXCL_ENABLE_MASK 0x01ULL
@@ -69,6 +71,25 @@
 /* MMIO status bits */
 #define MMIO_STATUS_COM_WAIT_INT_MASK   0x04
 
+/* event logging constants */
+#define EVENT_ENTRY_SIZE        0x10
+#define EVENT_TYPE_SHIFT        28
+#define EVENT_TYPE_MASK         0xf
+#define EVENT_TYPE_ILL_DEV      0x1
+#define EVENT_TYPE_IO_FAULT     0x2
+#define EVENT_TYPE_DEV_TAB_ERR  0x3
+#define EVENT_TYPE_PAGE_TAB_ERR 0x4
+#define EVENT_TYPE_ILL_CMD      0x5
+#define EVENT_TYPE_CMD_HARD_ERR 0x6
+#define EVENT_TYPE_IOTLB_INV_TO 0x7
+#define EVENT_TYPE_INV_DEV_REQ  0x8
+#define EVENT_DEVID_MASK        0xffff
+#define EVENT_DEVID_SHIFT       0
+#define EVENT_DOMID_MASK        0xffff
+#define EVENT_DOMID_SHIFT       0
+#define EVENT_FLAGS_MASK        0xfff
+#define EVENT_FLAGS_SHIFT       0x10
+
 /* feature control bits */
 #define CONTROL_IOMMU_EN        0x00ULL
 #define CONTROL_HT_TUN_EN       0x01ULL
@@ -109,6 +130,8 @@
 #define DEV_ENTRY_NMI_PASS      0xba
 #define DEV_ENTRY_LINT0_PASS    0xbe
 #define DEV_ENTRY_LINT1_PASS    0xbf
+#define DEV_ENTRY_MODE_MASK     0x07
+#define DEV_ENTRY_MODE_SHIFT    0x09
 
 /* constants to configure the command buffer */
 #define CMD_BUFFER_SIZE    8192
@@ -116,6 +139,10 @@
 #define MMIO_CMD_SIZE_SHIFT 56
 #define MMIO_CMD_SIZE_512 (0x9ULL << MMIO_CMD_SIZE_SHIFT)
 
+/* constants for event buffer handling */
+#define EVT_BUFFER_SIZE         8192 /* 512 entries */
+#define EVT_LEN_MASK            (0x9ULL << 56)
+
 #define PAGE_MODE_1_LEVEL 0x01
 #define PAGE_MODE_2_LEVEL 0x02
 #define PAGE_MODE_3_LEVEL 0x03
@@ -134,6 +161,7 @@
 #define IOMMU_MAP_SIZE_L3 (1ULL << 39)
 
 #define IOMMU_PTE_P  (1ULL << 0)
+#define IOMMU_PTE_TV (1ULL << 1)
 #define IOMMU_PTE_U  (1ULL << 59)
 #define IOMMU_PTE_FC (1ULL << 60)
 #define IOMMU_PTE_IR (1ULL << 61)
@@ -159,6 +187,9 @@
 
 #define MAX_DOMAIN_ID 65536
 
+/* FIXME: move this macro to <linux/pci.h> */
+#define PCI_BUS(x) (((x) >> 8) & 0xff)
+
 /*
  * This structure contains generic data for  IOMMU protection domains
  * independent of their use.
@@ -196,6 +227,15 @@ struct dma_ops_domain {
          * just calculate its address in constant time.
          */
         u64 **pte_pages;
+
+        /* This will be set to true when TLB needs to be flushed */
+        bool need_flush;
+
+        /*
+         * if this is a preallocated domain, keep the device for which it was
+         * preallocated in this variable
+         */
+        u16 target_dev;
 };
 
 /*
@@ -208,8 +248,9 @@ struct amd_iommu {
         /* locks the accesses to the hardware */
         spinlock_t lock;
 
-        /* device id of this IOMMU */
-        u16 devid;
+        /* Pointer to PCI device of this IOMMU */
+        struct pci_dev *dev;
+
         /*
          * Capability pointer. There could be more than one IOMMU per PCI
          * device function if there are more than one AMD IOMMU capability
@@ -225,6 +266,9 @@ struct amd_iommu {
         /* capabilities of that IOMMU read from ACPI */
         u32 cap;
 
+        /* pci domain of this IOMMU */
+        u16 pci_seg;
+
         /* first device this IOMMU handles. read from PCI */
         u16 first_device;
         /* last device this IOMMU handles. read from PCI */
@@ -240,9 +284,19 @@ struct amd_iommu {
         /* size of command buffer */
         u32 cmd_buf_size;
 
+        /* event buffer virtual address */
+        u8 *evt_buf;
+        /* size of event buffer */
+        u32 evt_buf_size;
+        /* MSI number for event interrupt */
+        u16 evt_msi_num;
+
         /* if one, we need to send a completion wait command */
         int need_sync;
 
+        /* true if interrupts for this IOMMU are already enabled */
+        bool int_enabled;
+
         /* default dma_ops domain for that IOMMU */
         struct dma_ops_domain *default_dom;
 };
@@ -322,6 +376,12 @@ extern unsigned long *amd_iommu_pd_alloc_bitmap;
 /* will be 1 if device isolation is enabled */
 extern int amd_iommu_isolate;
 
+/*
+ * If true, the addresses will be flushed on unmap time, not when
+ * they are reused
+ */
+extern bool amd_iommu_unmap_flush;
+
 /* takes a PCI device id and prints it out in a readable form */
 static inline void print_devid(u16 devid, int nl)
 {
@@ -341,4 +401,4 @@ static inline u16 calc_devid(u8 bus, u8 devfn)
         return (((u16)bus) << 8) | devfn;
 }
 
-#endif
+#endif /* ASM_X86__AMD_IOMMU_TYPES_H */
diff --git a/include/asm-x86/apic.h b/include/asm-x86/apic.h
index 133c998161ca..d76a0839abe9 100644
--- a/include/asm-x86/apic.h
+++ b/include/asm-x86/apic.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_APIC_H
-#define _ASM_X86_APIC_H
+#ifndef ASM_X86__APIC_H
+#define ASM_X86__APIC_H
 
 #include <linux/pm.h>
 #include <linux/delay.h>
@@ -9,6 +9,8 @@
 #include <asm/apicdef.h>
 #include <asm/processor.h>
 #include <asm/system.h>
+#include <asm/cpufeature.h>
+#include <asm/msr.h>
 
 #define ARCH_APICTIMER_STOPS_ON_C3      1
 
@@ -47,15 +49,18 @@ extern int disable_apic;
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
-#define apic_write native_apic_write
-#define apic_read native_apic_read
 #define setup_boot_clock setup_boot_APIC_clock
 #define setup_secondary_clock setup_secondary_APIC_clock
 #endif
 
 extern int is_vsmp_box(void);
+extern void xapic_wait_icr_idle(void);
+extern u32 safe_xapic_wait_icr_idle(void);
+extern u64 xapic_icr_read(void);
+extern void xapic_icr_write(u32, u32);
+extern int setup_profiling_timer(unsigned int);
 
-static inline void native_apic_write(unsigned long reg, u32 v)
+static inline void native_apic_mem_write(u32 reg, u32 v)
 {
         volatile u32 *addr = (volatile u32 *)(APIC_BASE + reg);
 
@@ -64,21 +69,72 @@ static inline void native_apic_write(unsigned long reg, u32 v)
                        ASM_OUTPUT2("0" (v), "m" (*addr)));
 }
 
-static inline u32 native_apic_read(unsigned long reg)
+static inline u32 native_apic_mem_read(u32 reg)
 {
         return *((volatile u32 *)(APIC_BASE + reg));
 }
 
-extern void apic_wait_icr_idle(void);
-extern u32 safe_apic_wait_icr_idle(void);
+static inline void native_apic_msr_write(u32 reg, u32 v)
+{
+        if (reg == APIC_DFR || reg == APIC_ID || reg == APIC_LDR ||
+            reg == APIC_LVR)
+                return;
+
+        wrmsr(APIC_BASE_MSR + (reg >> 4), v, 0);
+}
+
+static inline u32 native_apic_msr_read(u32 reg)
+{
+        u32 low, high;
+
+        if (reg == APIC_DFR)
+                return -1;
+
+        rdmsr(APIC_BASE_MSR + (reg >> 4), low, high);
+        return low;
+}
+
+#ifndef CONFIG_X86_32
+extern int x2apic, x2apic_preenabled;
+extern void check_x2apic(void);
+extern void enable_x2apic(void);
+extern void enable_IR_x2apic(void);
+extern void x2apic_icr_write(u32 low, u32 id);
+#endif
+
+struct apic_ops {
+        u32 (*read)(u32 reg);
+        void (*write)(u32 reg, u32 v);
+        u64 (*icr_read)(void);
+        void (*icr_write)(u32 low, u32 high);
+        void (*wait_icr_idle)(void);
+        u32 (*safe_wait_icr_idle)(void);
+};
+
+extern struct apic_ops *apic_ops;
+
+#define apic_read (apic_ops->read)
+#define apic_write (apic_ops->write)
+#define apic_icr_read (apic_ops->icr_read)
+#define apic_icr_write (apic_ops->icr_write)
+#define apic_wait_icr_idle (apic_ops->wait_icr_idle)
+#define safe_apic_wait_icr_idle (apic_ops->safe_wait_icr_idle)
+
 extern int get_physical_broadcast(void);
 
+#ifdef CONFIG_X86_64
+static inline void ack_x2APIC_irq(void)
+{
+        /* Docs say use 0 for future compatibility */
+        native_apic_msr_write(APIC_EOI, 0);
+}
+#endif
+
+
 static inline void ack_APIC_irq(void)
 {
         /*
-         * ack_APIC_irq() actually gets compiled as a single instruction:
-         * - a single rmw on Pentium/82489DX
-         * - a single write on P6+ cores (CONFIG_X86_GOOD_APIC)
+         * ack_APIC_irq() actually gets compiled as a single instruction
          * ... yummie.
          */
 
@@ -128,4 +184,4 @@ static inline void init_apic_mappings(void) { }
 
 #endif /* !CONFIG_X86_LOCAL_APIC */
 
-#endif /* __ASM_APIC_H */
+#endif /* ASM_X86__APIC_H */
diff --git a/include/asm-x86/apicdef.h b/include/asm-x86/apicdef.h
index 6b9008c78731..b922c85ac91d 100644
--- a/include/asm-x86/apicdef.h
+++ b/include/asm-x86/apicdef.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_APICDEF_H
-#define _ASM_X86_APICDEF_H
+#ifndef ASM_X86__APICDEF_H
+#define ASM_X86__APICDEF_H
 
 /*
  * Constants for various Intel APICs. (local APIC, IOAPIC, etc.)
@@ -105,6 +105,7 @@
 #define APIC_TMICT      0x380
 #define APIC_TMCCT      0x390
 #define APIC_TDCR       0x3E0
+#define APIC_SELF_IPI   0x3F0
 #define         APIC_TDR_DIV_TMBASE     (1 << 2)
 #define         APIC_TDR_DIV_1          0xB
 #define         APIC_TDR_DIV_2          0x0
@@ -128,6 +129,8 @@
 #define APIC_EILVT3     0x530
 
 #define APIC_BASE (fix_to_virt(FIX_APIC_BASE))
+#define APIC_BASE_MSR   0x800
+#define X2APIC_ENABLE   (1UL << 10)
 
 #ifdef CONFIG_X86_32
 # define MAX_IO_APICS 64
@@ -411,4 +414,4 @@ struct local_apic {
 #else
  #define BAD_APICID 0xFFFFu
 #endif
-#endif
+#endif /* ASM_X86__APICDEF_H */
diff --git a/include/asm-x86/arch_hooks.h b/include/asm-x86/arch_hooks.h
index 8411750ceb63..de4596b24c23 100644
--- a/include/asm-x86/arch_hooks.h
+++ b/include/asm-x86/arch_hooks.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_ARCH_HOOKS_H
-#define _ASM_ARCH_HOOKS_H
+#ifndef ASM_X86__ARCH_HOOKS_H
+#define ASM_X86__ARCH_HOOKS_H
 
 #include <linux/interrupt.h>
 
@@ -12,8 +12,6 @@
 /* these aren't arch hooks, they are generic routines
  * that can be used by the hooks */
 extern void init_ISA_irqs(void);
-extern void apic_intr_init(void);
-extern void smp_intr_init(void);
 extern irqreturn_t timer_interrupt(int irq, void *dev_id);
 
 /* these are the defined hooks */
@@ -25,4 +23,4 @@ extern void pre_time_init_hook(void);
 extern void time_init_hook(void);
 extern void mca_nmi_hook(void);
 
-#endif
+#endif /* ASM_X86__ARCH_HOOKS_H */
diff --git a/include/asm-x86/asm.h b/include/asm-x86/asm.h
index 97220321f39d..e1355f44d7c3 100644
--- a/include/asm-x86/asm.h
+++ b/include/asm-x86/asm.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_ASM_H
-#define _ASM_X86_ASM_H
+#ifndef ASM_X86__ASM_H
+#define ASM_X86__ASM_H
 
 #ifdef __ASSEMBLY__
 # define __ASM_FORM(x)  x
@@ -20,17 +20,22 @@
 
 #define _ASM_PTR        __ASM_SEL(.long, .quad)
 #define _ASM_ALIGN      __ASM_SEL(.balign 4, .balign 8)
-#define _ASM_MOV_UL     __ASM_SIZE(mov)
 
+#define _ASM_MOV        __ASM_SIZE(mov)
 #define _ASM_INC        __ASM_SIZE(inc)
 #define _ASM_DEC        __ASM_SIZE(dec)
 #define _ASM_ADD        __ASM_SIZE(add)
 #define _ASM_SUB        __ASM_SIZE(sub)
 #define _ASM_XADD       __ASM_SIZE(xadd)
+
 #define _ASM_AX         __ASM_REG(ax)
 #define _ASM_BX         __ASM_REG(bx)
 #define _ASM_CX         __ASM_REG(cx)
 #define _ASM_DX         __ASM_REG(dx)
+#define _ASM_SP         __ASM_REG(sp)
+#define _ASM_BP         __ASM_REG(bp)
+#define _ASM_SI         __ASM_REG(si)
+#define _ASM_DI         __ASM_REG(di)
 
 /* Exception table entry */
 # define _ASM_EXTABLE(from,to) \
@@ -39,4 +44,4 @@
         _ASM_PTR #from "," #to "\n" \
         " .previous\n"
 
-#endif /* _ASM_X86_ASM_H */
+#endif /* ASM_X86__ASM_H */
diff --git a/include/asm-x86/atomic_32.h b/include/asm-x86/atomic_32.h
index 21a4825148c0..14d3f0beb889 100644
--- a/include/asm-x86/atomic_32.h
+++ b/include/asm-x86/atomic_32.h
@@ -1,5 +1,5 @@
-#ifndef __ARCH_I386_ATOMIC__
-#define __ARCH_I386_ATOMIC__
+#ifndef ASM_X86__ATOMIC_32_H
+#define ASM_X86__ATOMIC_32_H
 
 #include <linux/compiler.h>
 #include <asm/processor.h>
@@ -256,4 +256,4 @@ static inline int atomic_add_unless(atomic_t *v, int a, int u)
 #define smp_mb__after_atomic_inc()      barrier()
 
 #include <asm-generic/atomic.h>
-#endif
+#endif /* ASM_X86__ATOMIC_32_H */
diff --git a/include/asm-x86/atomic_64.h b/include/asm-x86/atomic_64.h
index 91c7d03e65bc..2cb218c4a356 100644
--- a/include/asm-x86/atomic_64.h
+++ b/include/asm-x86/atomic_64.h
@@ -1,5 +1,5 @@
-#ifndef __ARCH_X86_64_ATOMIC__
-#define __ARCH_X86_64_ATOMIC__
+#ifndef ASM_X86__ATOMIC_64_H
+#define ASM_X86__ATOMIC_64_H
 
 #include <asm/alternative.h>
 #include <asm/cmpxchg.h>
@@ -470,4 +470,4 @@ static inline void atomic_or_long(unsigned long *v1, unsigned long v2)
 #define smp_mb__after_atomic_inc()      barrier()
 
 #include <asm-generic/atomic.h>
-#endif
+#endif /* ASM_X86__ATOMIC_64_H */
diff --git a/include/asm-x86/auxvec.h b/include/asm-x86/auxvec.h
index 87f5e6d5a020..12c7cac74202 100644
--- a/include/asm-x86/auxvec.h
+++ b/include/asm-x86/auxvec.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_AUXVEC_H
-#define _ASM_X86_AUXVEC_H
+#ifndef ASM_X86__AUXVEC_H
+#define ASM_X86__AUXVEC_H
 /*
  * Architecture-neutral AT_ values in 0-17, leave some room
  * for more of them, start the x86-specific ones at 32.
@@ -9,4 +9,4 @@
 #endif
 #define AT_SYSINFO_EHDR         33
 
-#endif
+#endif /* ASM_X86__AUXVEC_H */
diff --git a/include/asm-x86/mach-bigsmp/mach_apic.h b/include/asm-x86/bigsmp/apic.h
index c3b9dc6970c9..0a9cd7c5ca0c 100644
--- a/include/asm-x86/mach-bigsmp/mach_apic.h
+++ b/include/asm-x86/bigsmp/apic.h
@@ -11,7 +11,7 @@ static inline int apic_id_registered(void)
 
 /* Round robin the irqs amoung the online cpus */
 static inline cpumask_t target_cpus(void)
-{ 
+{
         static unsigned long cpu = NR_CPUS;
         do {
                 if (cpu >= NR_CPUS)
@@ -23,7 +23,7 @@ static inline cpumask_t target_cpus(void)
 }
 
 #undef APIC_DEST_LOGICAL
-#define APIC_DEST_LOGICAL       0
+#define APIC_DEST_LOGICAL       0
 #define TARGET_CPUS             (target_cpus())
 #define APIC_DFR_VALUE          (APIC_DFR_FLAT)
 #define INT_DELIVERY_MODE       (dest_Fixed)
diff --git a/include/asm-x86/mach-bigsmp/mach_apicdef.h b/include/asm-x86/bigsmp/apicdef.h
index a58ab5a75c8c..392c3f5ef2fe 100644
--- a/include/asm-x86/mach-bigsmp/mach_apicdef.h
+++ b/include/asm-x86/bigsmp/apicdef.h
@@ -3,10 +3,10 @@
 
 #define         APIC_ID_MASK            (0xFF<<24)
 
-static inline unsigned get_apic_id(unsigned long x) 
-{ 
+static inline unsigned get_apic_id(unsigned long x)
+{
         return (((x)>>24)&0xFF);
-} 
+}
 
 #define         GET_APIC_ID(x)  get_apic_id(x)
 
diff --git a/include/asm-x86/mach-bigsmp/mach_ipi.h b/include/asm-x86/bigsmp/ipi.h
index 9404c535b7ec..9404c535b7ec 100644
--- a/include/asm-x86/mach-bigsmp/mach_ipi.h
+++ b/include/asm-x86/bigsmp/ipi.h
diff --git a/include/asm-x86/bios_ebda.h b/include/asm-x86/bios_ebda.h
index 0033e50c13b2..79b4b88505d7 100644
--- a/include/asm-x86/bios_ebda.h
+++ b/include/asm-x86/bios_ebda.h
@@ -1,5 +1,5 @@
-#ifndef _MACH_BIOS_EBDA_H
-#define _MACH_BIOS_EBDA_H
+#ifndef ASM_X86__BIOS_EBDA_H
+#define ASM_X86__BIOS_EBDA_H
 
 #include <asm/io.h>
 
@@ -16,4 +16,21 @@ static inline unsigned int get_bios_ebda(void)
 
 void reserve_ebda_region(void);
 
-#endif /* _MACH_BIOS_EBDA_H */
+#ifdef CONFIG_X86_CHECK_BIOS_CORRUPTION
+/*
+ * This is obviously not a great place for this, but we want to be
+ * able to scatter it around anywhere in the kernel.
+ */
+void check_for_bios_corruption(void);
+void start_periodic_check_for_corruption(void);
+#else
+static inline void check_for_bios_corruption(void)
+{
+}
+
+static inline void start_periodic_check_for_corruption(void)
+{
+}
+#endif
+
+#endif /* ASM_X86__BIOS_EBDA_H */
diff --git a/include/asm-x86/bitops.h b/include/asm-x86/bitops.h
index cfb2b64f76e7..451a74762bd4 100644
--- a/include/asm-x86/bitops.h
+++ b/include/asm-x86/bitops.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_BITOPS_H
-#define _ASM_X86_BITOPS_H
+#ifndef ASM_X86__BITOPS_H
+#define ASM_X86__BITOPS_H
 
 /*
  * Copyright 1992, Linus Torvalds.
@@ -424,16 +424,6 @@ static inline int fls(int x)
 
 #undef ADDR
 
-static inline void set_bit_string(unsigned long *bitmap,
-                unsigned long i, int len)
-{
-        unsigned long end = i + len;
-        while (i < end) {
-                __set_bit(i, bitmap);
-                i++;
-        }
-}
-
 #ifdef __KERNEL__
 
 #include <asm-generic/bitops/sched.h>
@@ -458,4 +448,4 @@ static inline void set_bit_string(unsigned long *bitmap,
 #include <asm-generic/bitops/minix.h>
 
 #endif /* __KERNEL__ */
-#endif  /* _ASM_X86_BITOPS_H */
+#endif /* ASM_X86__BITOPS_H */
diff --git a/include/asm-x86/boot.h b/include/asm-x86/boot.h
index 2faed7ecb092..1d63bd5d5946 100644
--- a/include/asm-x86/boot.h
+++ b/include/asm-x86/boot.h
@@ -1,10 +1,8 @@
-#ifndef _ASM_BOOT_H
-#define _ASM_BOOT_H
+#ifndef ASM_X86__BOOT_H
+#define ASM_X86__BOOT_H
 
 /* Don't touch these, unless you really know what you're doing. */
-#define DEF_INITSEG     0x9000
 #define DEF_SYSSEG      0x1000
-#define DEF_SETUPSEG    0x9020
 #define DEF_SYSSIZE     0x7F00
 
 /* Internal svga startup constants */
@@ -25,4 +23,4 @@
 #define BOOT_STACK_SIZE 0x1000
 #endif
 
-#endif /* _ASM_BOOT_H */
+#endif /* ASM_X86__BOOT_H */
diff --git a/include/asm-x86/bootparam.h b/include/asm-x86/bootparam.h
index ae22bdf0ab14..ccf027e2d97d 100644
--- a/include/asm-x86/bootparam.h
+++ b/include/asm-x86/bootparam.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_BOOTPARAM_H
-#define _ASM_BOOTPARAM_H
+#ifndef ASM_X86__BOOTPARAM_H
+#define ASM_X86__BOOTPARAM_H
 
 #include <linux/types.h>
 #include <linux/screen_info.h>
@@ -108,4 +108,4 @@ struct boot_params {
         __u8  _pad9[276];                               /* 0xeec */
 } __attribute__((packed));
 
-#endif /* _ASM_BOOTPARAM_H */
+#endif /* ASM_X86__BOOTPARAM_H */
diff --git a/include/asm-x86/bug.h b/include/asm-x86/bug.h
index b69aa64b82a4..91ad43a54c47 100644
--- a/include/asm-x86/bug.h
+++ b/include/asm-x86/bug.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_BUG_H
-#define _ASM_X86_BUG_H
+#ifndef ASM_X86__BUG_H
+#define ASM_X86__BUG_H
 
 #ifdef CONFIG_BUG
 #define HAVE_ARCH_BUG
@@ -36,4 +36,4 @@ do {								\
 #endif /* !CONFIG_BUG */
 
 #include <asm-generic/bug.h>
-#endif
+#endif /* ASM_X86__BUG_H */
diff --git a/include/asm-x86/bugs.h b/include/asm-x86/bugs.h
index 021cbdd5f258..dc604985f2ad 100644
--- a/include/asm-x86/bugs.h
+++ b/include/asm-x86/bugs.h
@@ -1,7 +1,12 @@
-#ifndef _ASM_X86_BUGS_H
-#define _ASM_X86_BUGS_H
+#ifndef ASM_X86__BUGS_H
+#define ASM_X86__BUGS_H
 
 extern void check_bugs(void);
+
+#if defined(CONFIG_CPU_SUP_INTEL) && defined(CONFIG_X86_32)
 int ppro_with_ram_bug(void);
+#else
+static inline int ppro_with_ram_bug(void) { return 0; }
+#endif
 
-#endif /* _ASM_X86_BUGS_H */
+#endif /* ASM_X86__BUGS_H */
diff --git a/include/asm-x86/byteorder.h b/include/asm-x86/byteorder.h
index e02ae2d89acf..722f27d68105 100644
--- a/include/asm-x86/byteorder.h
+++ b/include/asm-x86/byteorder.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_BYTEORDER_H
-#define _ASM_X86_BYTEORDER_H
+#ifndef ASM_X86__BYTEORDER_H
+#define ASM_X86__BYTEORDER_H
 
 #include <asm/types.h>
 #include <linux/compiler.h>
@@ -78,4 +78,4 @@ static inline __attribute_const__ __u32 ___arch__swab32(__u32 x)
 
 #include <linux/byteorder/little_endian.h>
 
-#endif /* _ASM_X86_BYTEORDER_H */
+#endif /* ASM_X86__BYTEORDER_H */
diff --git a/include/asm-x86/cache.h b/include/asm-x86/cache.h
index 1e0bac86f38f..ea3f1cc06a97 100644
--- a/include/asm-x86/cache.h
+++ b/include/asm-x86/cache.h
@@ -1,5 +1,5 @@
-#ifndef _ARCH_X86_CACHE_H
-#define _ARCH_X86_CACHE_H
+#ifndef ASM_X86__CACHE_H
+#define ASM_X86__CACHE_H
 
 /* L1 cache line size */
 #define L1_CACHE_SHIFT  (CONFIG_X86_L1_CACHE_SHIFT)
@@ -17,4 +17,4 @@
 #endif
 #endif
 
-#endif
+#endif /* ASM_X86__CACHE_H */
diff --git a/include/asm-x86/cacheflush.h b/include/asm-x86/cacheflush.h
index f4c0ab50d2c2..68840ef1b35a 100644
--- a/include/asm-x86/cacheflush.h
+++ b/include/asm-x86/cacheflush.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_CACHEFLUSH_H
-#define _ASM_X86_CACHEFLUSH_H
+#ifndef ASM_X86__CACHEFLUSH_H
+#define ASM_X86__CACHEFLUSH_H
 
 /* Keep includes the same across arches.  */
 #include <linux/mm.h>
@@ -24,6 +24,8 @@
 #define copy_from_user_page(vma, page, vaddr, dst, src, len)    \
         memcpy((dst), (src), (len))
 
+#define PG_non_WB                               PG_arch_1
+PAGEFLAG(NonWB, non_WB)
 
 /*
  * The set_memory_* API can be used to change various attributes of a virtual
@@ -66,6 +68,9 @@ int set_memory_rw(unsigned long addr, int numpages);
 int set_memory_np(unsigned long addr, int numpages);
 int set_memory_4k(unsigned long addr, int numpages);
 
+int set_memory_array_uc(unsigned long *addr, int addrinarray);
+int set_memory_array_wb(unsigned long *addr, int addrinarray);
+
 /*
  * For legacy compatibility with the old APIs, a few functions
  * are provided that work on a "struct page".
@@ -96,8 +101,6 @@ int set_pages_rw(struct page *page, int numpages);
 
 void clflush_cache_range(void *addr, unsigned int size);
 
-void cpa_init(void);
-
 #ifdef CONFIG_DEBUG_RODATA
 void mark_rodata_ro(void);
 extern const int rodata_test_data;
@@ -112,4 +115,4 @@ static inline int rodata_test(void)
 }
 #endif
 
-#endif
+#endif /* ASM_X86__CACHEFLUSH_H */
diff --git a/include/asm-x86/calgary.h b/include/asm-x86/calgary.h
index 67f60406e2d8..933fd272f826 100644
--- a/include/asm-x86/calgary.h
+++ b/include/asm-x86/calgary.h
@@ -21,8 +21,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-#ifndef _ASM_X86_64_CALGARY_H
-#define _ASM_X86_64_CALGARY_H
+#ifndef ASM_X86__CALGARY_H
+#define ASM_X86__CALGARY_H
 
 #include <linux/spinlock.h>
 #include <linux/device.h>
@@ -69,4 +69,4 @@ static inline int calgary_iommu_init(void) { return 1; }
 static inline void detect_calgary(void) { return; }
 #endif
 
-#endif /* _ASM_X86_64_CALGARY_H */
+#endif /* ASM_X86__CALGARY_H */
diff --git a/include/asm-x86/checksum_32.h b/include/asm-x86/checksum_32.h
index 52bbb0d8c4c1..d041e8cda227 100644
--- a/include/asm-x86/checksum_32.h
+++ b/include/asm-x86/checksum_32.h
@@ -1,5 +1,5 @@
-#ifndef _I386_CHECKSUM_H
-#define _I386_CHECKSUM_H
+#ifndef ASM_X86__CHECKSUM_32_H
+#define ASM_X86__CHECKSUM_32_H
 
 #include <linux/in6.h>
 
@@ -186,4 +186,4 @@ static inline __wsum csum_and_copy_to_user(const void *src,
         return (__force __wsum)-1; /* invalid checksum */
 }
 
-#endif
+#endif /* ASM_X86__CHECKSUM_32_H */
diff --git a/include/asm-x86/checksum_64.h b/include/asm-x86/checksum_64.h
index 8bd861cc5267..110f403beb89 100644
--- a/include/asm-x86/checksum_64.h
+++ b/include/asm-x86/checksum_64.h
@@ -1,5 +1,5 @@
-#ifndef _X86_64_CHECKSUM_H
-#define _X86_64_CHECKSUM_H
+#ifndef ASM_X86__CHECKSUM_64_H
+#define ASM_X86__CHECKSUM_64_H
 
 /*
  * Checksums for x86-64
@@ -188,4 +188,4 @@ static inline unsigned add32_with_carry(unsigned a, unsigned b)
         return a;
 }
 
-#endif
+#endif /* ASM_X86__CHECKSUM_64_H */
diff --git a/include/asm-x86/cmpxchg_32.h b/include/asm-x86/cmpxchg_32.h
index bf5a69d1329e..0622e45cdf7c 100644
--- a/include/asm-x86/cmpxchg_32.h
+++ b/include/asm-x86/cmpxchg_32.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_CMPXCHG_H
-#define __ASM_CMPXCHG_H
+#ifndef ASM_X86__CMPXCHG_32_H
+#define ASM_X86__CMPXCHG_32_H
 
 #include <linux/bitops.h> /* for LOCK_PREFIX */
 
@@ -341,4 +341,4 @@ extern unsigned long long cmpxchg_486_u64(volatile void *, u64, u64);
 
 #endif
 
-#endif
+#endif /* ASM_X86__CMPXCHG_32_H */
diff --git a/include/asm-x86/cmpxchg_64.h b/include/asm-x86/cmpxchg_64.h
index 17463ccf8166..63c1a5e61b99 100644
--- a/include/asm-x86/cmpxchg_64.h
+++ b/include/asm-x86/cmpxchg_64.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_CMPXCHG_H
-#define __ASM_CMPXCHG_H
+#ifndef ASM_X86__CMPXCHG_64_H
+#define ASM_X86__CMPXCHG_64_H
 
 #include <asm/alternative.h> /* Provides LOCK_PREFIX */
 
@@ -182,4 +182,4 @@ static inline unsigned long __cmpxchg_local(volatile void *ptr,
         cmpxchg_local((ptr), (o), (n));                                 \
 })
 
-#endif
+#endif /* ASM_X86__CMPXCHG_64_H */
diff --git a/include/asm-x86/compat.h b/include/asm-x86/compat.h
index 1793ac317a30..6732b150949e 100644
--- a/include/asm-x86/compat.h
+++ b/include/asm-x86/compat.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_COMPAT_H
-#define _ASM_X86_64_COMPAT_H
+#ifndef ASM_X86__COMPAT_H
+#define ASM_X86__COMPAT_H
 
 /*
  * Architecture specific compatibility types
@@ -215,4 +215,4 @@ static inline int is_compat_task(void)
         return current_thread_info()->status & TS_COMPAT;
 }
 
-#endif /* _ASM_X86_64_COMPAT_H */
+#endif /* ASM_X86__COMPAT_H */
diff --git a/include/asm-x86/cpu.h b/include/asm-x86/cpu.h
index 73f2ea84fd74..83a115083f0d 100644
--- a/include/asm-x86/cpu.h
+++ b/include/asm-x86/cpu.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_I386_CPU_H_
-#define _ASM_I386_CPU_H_
+#ifndef ASM_X86__CPU_H
+#define ASM_X86__CPU_H
 
 #include <linux/device.h>
 #include <linux/cpu.h>
@@ -17,4 +17,4 @@ extern void arch_unregister_cpu(int);
 #endif
 
 DECLARE_PER_CPU(int, cpu_state);
-#endif /* _ASM_I386_CPU_H_ */
+#endif /* ASM_X86__CPU_H */
diff --git a/include/asm-x86/cpufeature.h b/include/asm-x86/cpufeature.h
index 2f5a792b0acc..adfeae6586e1 100644
--- a/include/asm-x86/cpufeature.h
+++ b/include/asm-x86/cpufeature.h
@@ -1,12 +1,18 @@
 /*
  * Defines x86 CPU feature bits
  */
-#ifndef _ASM_X86_CPUFEATURE_H
-#define _ASM_X86_CPUFEATURE_H
+#ifndef ASM_X86__CPUFEATURE_H
+#define ASM_X86__CPUFEATURE_H
 
 #include <asm/required-features.h>
 
-#define NCAPINTS        8       /* N 32-bit words worth of info */
+#define NCAPINTS        9       /* N 32-bit words worth of info */
+
+/*
+ * Note: If the comment begins with a quoted string, that string is used
+ * in /proc/cpuinfo instead of the macro name.  If the string is "",
+ * this feature bit is not displayed in /proc/cpuinfo at all.
+ */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (edx), word 0 */
 #define X86_FEATURE_FPU         (0*32+ 0) /* Onboard FPU */
@@ -14,7 +20,7 @@
 #define X86_FEATURE_DE          (0*32+ 2) /* Debugging Extensions */
 #define X86_FEATURE_PSE         (0*32+ 3) /* Page Size Extensions */
 #define X86_FEATURE_TSC         (0*32+ 4) /* Time Stamp Counter */
-#define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers, RDMSR, WRMSR */
+#define X86_FEATURE_MSR         (0*32+ 5) /* Model-Specific Registers */
 #define X86_FEATURE_PAE         (0*32+ 6) /* Physical Address Extensions */
 #define X86_FEATURE_MCE         (0*32+ 7) /* Machine Check Architecture */
 #define X86_FEATURE_CX8         (0*32+ 8) /* CMPXCHG8 instruction */
@@ -23,22 +29,23 @@
 #define X86_FEATURE_MTRR        (0*32+12) /* Memory Type Range Registers */
 #define X86_FEATURE_PGE         (0*32+13) /* Page Global Enable */
 #define X86_FEATURE_MCA         (0*32+14) /* Machine Check Architecture */
-#define X86_FEATURE_CMOV        (0*32+15) /* CMOV instruction (FCMOVCC and FCOMI too if FPU present) */
+#define X86_FEATURE_CMOV        (0*32+15) /* CMOV instructions */
+                                          /* (plus FCMOVcc, FCOMI with FPU) */
 #define X86_FEATURE_PAT         (0*32+16) /* Page Attribute Table */
 #define X86_FEATURE_PSE36       (0*32+17) /* 36-bit PSEs */
 #define X86_FEATURE_PN          (0*32+18) /* Processor serial number */
-#define X86_FEATURE_CLFLSH      (0*32+19) /* Supports the CLFLUSH instruction */
-#define X86_FEATURE_DS          (0*32+21) /* Debug Store */
+#define X86_FEATURE_CLFLSH      (0*32+19) /* "clflush" CLFLUSH instruction */
+#define X86_FEATURE_DS          (0*32+21) /* "dts" Debug Store */
 #define X86_FEATURE_ACPI        (0*32+22) /* ACPI via MSR */
 #define X86_FEATURE_MMX         (0*32+23) /* Multimedia Extensions */
-#define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE and FXRSTOR instructions (fast save and restore */
-                                          /* of FPU context), and CR4.OSFXSR available */
-#define X86_FEATURE_XMM         (0*32+25) /* Streaming SIMD Extensions */
-#define X86_FEATURE_XMM2        (0*32+26) /* Streaming SIMD Extensions-2 */
-#define X86_FEATURE_SELFSNOOP   (0*32+27) /* CPU self snoop */
+#define X86_FEATURE_FXSR        (0*32+24) /* FXSAVE/FXRSTOR, CR4.OSFXSR */
+#define X86_FEATURE_XMM         (0*32+25) /* "sse" */
+#define X86_FEATURE_XMM2        (0*32+26) /* "sse2" */
+#define X86_FEATURE_SELFSNOOP   (0*32+27) /* "ss" CPU self snoop */
 #define X86_FEATURE_HT          (0*32+28) /* Hyper-Threading */
-#define X86_FEATURE_ACC         (0*32+29) /* Automatic clock control */
+#define X86_FEATURE_ACC         (0*32+29) /* "tm" Automatic clock control */
 #define X86_FEATURE_IA64        (0*32+30) /* IA-64 processor */
+#define X86_FEATURE_PBE         (0*32+31) /* Pending Break Enable */
 
 /* AMD-defined CPU features, CPUID level 0x80000001, word 1 */
 /* Don't duplicate feature flags which are redundant with Intel! */
@@ -46,7 +53,8 @@
 #define X86_FEATURE_MP          (1*32+19) /* MP Capable. */
 #define X86_FEATURE_NX          (1*32+20) /* Execute Disable */
 #define X86_FEATURE_MMXEXT      (1*32+22) /* AMD MMX extensions */
-#define X86_FEATURE_GBPAGES     (1*32+26) /* GB pages */
+#define X86_FEATURE_FXSR_OPT    (1*32+25) /* FXSAVE/FXRSTOR optimizations */
+#define X86_FEATURE_GBPAGES     (1*32+26) /* "pdpe1gb" GB pages */
 #define X86_FEATURE_RDTSCP      (1*32+27) /* RDTSCP */
 #define X86_FEATURE_LM          (1*32+29) /* Long Mode (x86-64) */
 #define X86_FEATURE_3DNOWEXT    (1*32+30) /* AMD 3DNow! extensions */
@@ -64,50 +72,79 @@
 #define X86_FEATURE_CYRIX_ARR   (3*32+ 2) /* Cyrix ARRs (= MTRRs) */
 #define X86_FEATURE_CENTAUR_MCR (3*32+ 3) /* Centaur MCRs (= MTRRs) */
 /* cpu types for specific tunings: */
-#define X86_FEATURE_K8          (3*32+ 4) /* Opteron, Athlon64 */
-#define X86_FEATURE_K7          (3*32+ 5) /* Athlon */
-#define X86_FEATURE_P3          (3*32+ 6) /* P3 */
-#define X86_FEATURE_P4          (3*32+ 7) /* P4 */
+#define X86_FEATURE_K8          (3*32+ 4) /* "" Opteron, Athlon64 */
+#define X86_FEATURE_K7          (3*32+ 5) /* "" Athlon */
+#define X86_FEATURE_P3          (3*32+ 6) /* "" P3 */
+#define X86_FEATURE_P4          (3*32+ 7) /* "" P4 */
 #define X86_FEATURE_CONSTANT_TSC (3*32+ 8) /* TSC ticks at a constant rate */
 #define X86_FEATURE_UP          (3*32+ 9) /* smp kernel running on up */
-#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* FXSAVE leaks FOP/FIP/FOP */
+#define X86_FEATURE_FXSAVE_LEAK (3*32+10) /* "" FXSAVE leaks FOP/FIP/FOP */
 #define X86_FEATURE_ARCH_PERFMON (3*32+11) /* Intel Architectural PerfMon */
-#define X86_FEATURE_PEBS        (3*32+12)  /* Precise-Event Based Sampling */
-#define X86_FEATURE_BTS         (3*32+13)  /* Branch Trace Store */
-#define X86_FEATURE_SYSCALL32   (3*32+14)  /* syscall in ia32 userspace */
-#define X86_FEATURE_SYSENTER32  (3*32+15)  /* sysenter in ia32 userspace */
-#define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well on this CPU */
-#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* Mfence synchronizes RDTSC */
-#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* Lfence synchronizes RDTSC */
-#define X86_FEATURE_11AP        (3*32+19)  /* Bad local APIC aka 11AP */
+#define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
+#define X86_FEATURE_PEBS        (3*32+12) /* Precise-Event Based Sampling */
+#define X86_FEATURE_BTS         (3*32+13) /* Branch Trace Store */
+#define X86_FEATURE_SYSCALL32   (3*32+14) /* "" syscall in ia32 userspace */
+#define X86_FEATURE_SYSENTER32  (3*32+15) /* "" sysenter in ia32 userspace */
+#define X86_FEATURE_REP_GOOD    (3*32+16) /* rep microcode works well */
+#define X86_FEATURE_MFENCE_RDTSC (3*32+17) /* "" Mfence synchronizes RDTSC */
+#define X86_FEATURE_LFENCE_RDTSC (3*32+18) /* "" Lfence synchronizes RDTSC */
+#define X86_FEATURE_11AP        (3*32+19) /* "" Bad local APIC aka 11AP */
+#define X86_FEATURE_NOPL        (3*32+20) /* The NOPL (0F 1F) instructions */
+#define X86_FEATURE_AMDC1E      (3*32+21) /* AMD C1E detected */
+#define X86_FEATURE_XTOPOLOGY   (3*32+21) /* cpu topology enum extensions */
 
 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
-#define X86_FEATURE_XMM3        (4*32+ 0) /* Streaming SIMD Extensions-3 */
-#define X86_FEATURE_MWAIT       (4*32+ 3) /* Monitor/Mwait support */
-#define X86_FEATURE_DSCPL       (4*32+ 4) /* CPL Qualified Debug Store */
+#define X86_FEATURE_XMM3        (4*32+ 0) /* "pni" SSE-3 */
+#define X86_FEATURE_PCLMULQDQ   (4*32+ 1) /* PCLMULQDQ instruction */
+#define X86_FEATURE_DTES64      (4*32+ 2) /* 64-bit Debug Store */
+#define X86_FEATURE_MWAIT       (4*32+ 3) /* "monitor" Monitor/Mwait support */
+#define X86_FEATURE_DSCPL       (4*32+ 4) /* "ds_cpl" CPL Qual. Debug Store */
+#define X86_FEATURE_VMX         (4*32+ 5) /* Hardware virtualization */
+#define X86_FEATURE_SMX         (4*32+ 6) /* Safer mode */
 #define X86_FEATURE_EST         (4*32+ 7) /* Enhanced SpeedStep */
 #define X86_FEATURE_TM2         (4*32+ 8) /* Thermal Monitor 2 */
+#define X86_FEATURE_SSSE3       (4*32+ 9) /* Supplemental SSE-3 */
 #define X86_FEATURE_CID         (4*32+10) /* Context ID */
+#define X86_FEATURE_FMA         (4*32+12) /* Fused multiply-add */
 #define X86_FEATURE_CX16        (4*32+13) /* CMPXCHG16B */
 #define X86_FEATURE_XTPR        (4*32+14) /* Send Task Priority Messages */
+#define X86_FEATURE_PDCM        (4*32+15) /* Performance Capabilities */
 #define X86_FEATURE_DCA         (4*32+18) /* Direct Cache Access */
+#define X86_FEATURE_XMM4_1      (4*32+19) /* "sse4_1" SSE-4.1 */
+#define X86_FEATURE_XMM4_2      (4*32+20) /* "sse4_2" SSE-4.2 */
+#define X86_FEATURE_X2APIC      (4*32+21) /* x2APIC */
+#define X86_FEATURE_AES         (4*32+25) /* AES instructions */
+#define X86_FEATURE_XSAVE       (4*32+26) /* XSAVE/XRSTOR/XSETBV/XGETBV */
+#define X86_FEATURE_OSXSAVE     (4*32+27) /* "" XSAVE enabled in the OS */
+#define X86_FEATURE_AVX         (4*32+28) /* Advanced Vector Extensions */
 
 /* VIA/Cyrix/Centaur-defined CPU features, CPUID level 0xC0000001, word 5 */
-#define X86_FEATURE_XSTORE      (5*32+ 2) /* on-CPU RNG present (xstore insn) */
-#define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* on-CPU RNG enabled */
-#define X86_FEATURE_XCRYPT      (5*32+ 6) /* on-CPU crypto (xcrypt insn) */
-#define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* on-CPU crypto enabled */
+#define X86_FEATURE_XSTORE      (5*32+ 2) /* "rng" RNG present (xstore) */
+#define X86_FEATURE_XSTORE_EN   (5*32+ 3) /* "rng_en" RNG enabled */
+#define X86_FEATURE_XCRYPT      (5*32+ 6) /* "ace" on-CPU crypto (xcrypt) */
+#define X86_FEATURE_XCRYPT_EN   (5*32+ 7) /* "ace_en" on-CPU crypto enabled */
 #define X86_FEATURE_ACE2        (5*32+ 8) /* Advanced Cryptography Engine v2 */
 #define X86_FEATURE_ACE2_EN     (5*32+ 9) /* ACE v2 enabled */
-#define X86_FEATURE_PHE         (5*32+ 10) /* PadLock Hash Engine */
-#define X86_FEATURE_PHE_EN      (5*32+ 11) /* PHE enabled */
-#define X86_FEATURE_PMM         (5*32+ 12) /* PadLock Montgomery Multiplier */
-#define X86_FEATURE_PMM_EN      (5*32+ 13) /* PMM enabled */
+#define X86_FEATURE_PHE         (5*32+10) /* PadLock Hash Engine */
+#define X86_FEATURE_PHE_EN      (5*32+11) /* PHE enabled */
+#define X86_FEATURE_PMM         (5*32+12) /* PadLock Montgomery Multiplier */
+#define X86_FEATURE_PMM_EN      (5*32+13) /* PMM enabled */
 
 /* More extended AMD flags: CPUID level 0x80000001, ecx, word 6 */
 #define X86_FEATURE_LAHF_LM     (6*32+ 0) /* LAHF/SAHF in long mode */
 #define X86_FEATURE_CMP_LEGACY  (6*32+ 1) /* If yes HyperThreading not valid */
-#define X86_FEATURE_IBS         (6*32+ 10) /* Instruction Based Sampling */
+#define X86_FEATURE_SVM         (6*32+ 2) /* Secure virtual machine */
+#define X86_FEATURE_EXTAPIC     (6*32+ 3) /* Extended APIC space */
+#define X86_FEATURE_CR8_LEGACY  (6*32+ 4) /* CR8 in 32-bit mode */
+#define X86_FEATURE_ABM         (6*32+ 5) /* Advanced bit manipulation */
+#define X86_FEATURE_SSE4A       (6*32+ 6) /* SSE-4A */
+#define X86_FEATURE_MISALIGNSSE (6*32+ 7) /* Misaligned SSE mode */
+#define X86_FEATURE_3DNOWPREFETCH (6*32+ 8) /* 3DNow prefetch instructions */
+#define X86_FEATURE_OSVW        (6*32+ 9) /* OS Visible Workaround */
+#define X86_FEATURE_IBS         (6*32+10) /* Instruction Based Sampling */
+#define X86_FEATURE_SSE5        (6*32+11) /* SSE-5 */
+#define X86_FEATURE_SKINIT      (6*32+12) /* SKINIT/STGI instructions */
+#define X86_FEATURE_WDT         (6*32+13) /* Watchdog timer */
 
 /*
  * Auxiliary flags: Linux defined - For features scattered in various
@@ -115,6 +152,13 @@
  */
 #define X86_FEATURE_IDA         (7*32+ 0) /* Intel Dynamic Acceleration */
 
+/* Virtualization flags: Linux defined */
+#define X86_FEATURE_TPR_SHADOW  (8*32+ 0) /* Intel TPR Shadow */
+#define X86_FEATURE_VNMI        (8*32+ 1) /* Intel Virtual NMI */
+#define X86_FEATURE_FLEXPRIORITY (8*32+ 2) /* Intel FlexPriority */
+#define X86_FEATURE_EPT         (8*32+ 3) /* Intel Extended Page Table */
+#define X86_FEATURE_VPID        (8*32+ 4) /* Intel Virtual Processor ID */
+
 #if defined(__KERNEL__) && !defined(__ASSEMBLY__)
 
 #include <linux/bitops.h>
@@ -148,7 +192,7 @@ extern const char * const x86_power_flags[32];
 } while (0)
 #define setup_force_cpu_cap(bit) do { \
         set_cpu_cap(&boot_cpu_data, bit);       \
-        clear_bit(bit, (unsigned long *)cleared_cpu_caps);      \
+        clear_bit(bit, (unsigned long *)cleared_cpu_caps);      \
 } while (0)
 
 #define cpu_has_fpu             boot_cpu_has(X86_FEATURE_FPU)
@@ -189,6 +233,10 @@ extern const char * const x86_power_flags[32];
 #define cpu_has_gbpages         boot_cpu_has(X86_FEATURE_GBPAGES)
 #define cpu_has_arch_perfmon    boot_cpu_has(X86_FEATURE_ARCH_PERFMON)
 #define cpu_has_pat             boot_cpu_has(X86_FEATURE_PAT)
+#define cpu_has_xmm4_1          boot_cpu_has(X86_FEATURE_XMM4_1)
+#define cpu_has_xmm4_2          boot_cpu_has(X86_FEATURE_XMM4_2)
+#define cpu_has_x2apic          boot_cpu_has(X86_FEATURE_X2APIC)
+#define cpu_has_xsave           boot_cpu_has(X86_FEATURE_XSAVE)
 
 #if defined(CONFIG_X86_INVLPG) || defined(CONFIG_X86_64)
 # define cpu_has_invlpg         1
@@ -220,4 +268,4 @@ extern const char * const x86_power_flags[32];
 
 #endif /* defined(__KERNEL__) && !defined(__ASSEMBLY__) */
 
-#endif /* _ASM_X86_CPUFEATURE_H */
+#endif /* ASM_X86__CPUFEATURE_H */
diff --git a/include/asm-x86/current.h b/include/asm-x86/current.h
index 7515c19d4988..a863ead856f3 100644
--- a/include/asm-x86/current.h
+++ b/include/asm-x86/current.h
@@ -1,5 +1,5 @@
-#ifndef _X86_CURRENT_H
-#define _X86_CURRENT_H
+#ifndef ASM_X86__CURRENT_H
+#define ASM_X86__CURRENT_H
 
 #ifdef CONFIG_X86_32
 #include <linux/compiler.h>
@@ -36,4 +36,4 @@ static __always_inline struct task_struct *get_current(void)
 
 #define current get_current()
 
-#endif /* X86_CURRENT_H */
+#endif /* ASM_X86__CURRENT_H */
diff --git a/include/asm-x86/debugreg.h b/include/asm-x86/debugreg.h
index c6344d572b03..ecb6907c3ea4 100644
--- a/include/asm-x86/debugreg.h
+++ b/include/asm-x86/debugreg.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_DEBUGREG_H
-#define _ASM_X86_DEBUGREG_H
+#ifndef ASM_X86__DEBUGREG_H
+#define ASM_X86__DEBUGREG_H
 
 
 /* Indicate the register numbers for a number of the specific
@@ -67,4 +67,4 @@
 #define DR_LOCAL_SLOWDOWN (0x100)   /* Local slow the pipeline */
 #define DR_GLOBAL_SLOWDOWN (0x200)  /* Global slow the pipeline */
 
-#endif
+#endif /* ASM_X86__DEBUGREG_H */
diff --git a/include/asm-x86/delay.h b/include/asm-x86/delay.h
index 409a649204aa..8a0da95b4fc5 100644
--- a/include/asm-x86/delay.h
+++ b/include/asm-x86/delay.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_DELAY_H
-#define _ASM_X86_DELAY_H
+#ifndef ASM_X86__DELAY_H
+#define ASM_X86__DELAY_H
 
 /*
  * Copyright (C) 1993 Linus Torvalds
@@ -28,4 +28,4 @@ extern void __delay(unsigned long loops);
 
 void use_tsc_delay(void);
 
-#endif /* _ASM_X86_DELAY_H */
+#endif /* ASM_X86__DELAY_H */
diff --git a/include/asm-x86/desc.h b/include/asm-x86/desc.h
index a44c4dc70590..f06adac7938c 100644
--- a/include/asm-x86/desc.h
+++ b/include/asm-x86/desc.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_DESC_H_
-#define _ASM_DESC_H_
+#ifndef ASM_X86__DESC_H
+#define ASM_X86__DESC_H
 
 #ifndef __ASSEMBLY__
 #include <asm/desc_defs.h>
@@ -24,6 +24,11 @@ static inline void fill_ldt(struct desc_struct *desc,
         desc->d = info->seg_32bit;
         desc->g = info->limit_in_pages;
         desc->base2 = (info->base_addr & 0xff000000) >> 24;
+        /*
+         * Don't allow setting of the lm bit. It is useless anyway
+         * because 64bit system calls require __USER_CS:
+         */
+        desc->l = 0;
 }
 
 extern struct desc_ptr idt_descr;
@@ -97,7 +102,15 @@ static inline int desc_empty(const void *ptr)
         native_write_gdt_entry(dt, entry, desc, type)
 #define write_idt_entry(dt, entry, g)           \
         native_write_idt_entry(dt, entry, g)
-#endif
+
+static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
+{
+}
+
+static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
+{
+}
+#endif  /* CONFIG_PARAVIRT */
 
 static inline void native_write_idt_entry(gate_desc *idt, int entry,
                                           const gate_desc *gate)
@@ -338,20 +351,16 @@ static inline void set_system_intr_gate(unsigned int n, void *addr)
         _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
 }
 
-static inline void set_trap_gate(unsigned int n, void *addr)
+static inline void set_system_trap_gate(unsigned int n, void *addr)
 {
         BUG_ON((unsigned)n > 0xFF);
-        _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
+        _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
 }
 
-static inline void set_system_gate(unsigned int n, void *addr)
+static inline void set_trap_gate(unsigned int n, void *addr)
 {
         BUG_ON((unsigned)n > 0xFF);
-#ifdef CONFIG_X86_32
-        _set_gate(n, GATE_TRAP, addr, 0x3, 0, __KERNEL_CS);
-#else
-        _set_gate(n, GATE_INTERRUPT, addr, 0x3, 0, __KERNEL_CS);
-#endif
+        _set_gate(n, GATE_TRAP, addr, 0, 0, __KERNEL_CS);
 }
 
 static inline void set_task_gate(unsigned int n, unsigned int gdt_entry)
@@ -366,7 +375,7 @@ static inline void set_intr_gate_ist(int n, void *addr, unsigned ist)
         _set_gate(n, GATE_INTERRUPT, addr, 0, ist, __KERNEL_CS);
 }
 
-static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
+static inline void set_system_intr_gate_ist(int n, void *addr, unsigned ist)
 {
         BUG_ON((unsigned)n > 0xFF);
         _set_gate(n, GATE_INTERRUPT, addr, 0x3, ist, __KERNEL_CS);
@@ -397,4 +406,4 @@ static inline void set_system_gate_ist(int n, void *addr, unsigned ist)
 
 #endif /* __ASSEMBLY__ */
 
-#endif
+#endif /* ASM_X86__DESC_H */
diff --git a/include/asm-x86/desc_defs.h b/include/asm-x86/desc_defs.h
index f7bacf357dac..b881db664b46 100644
--- a/include/asm-x86/desc_defs.h
+++ b/include/asm-x86/desc_defs.h
@@ -1,6 +1,6 @@
 /* Written 2000 by Andi Kleen */
-#ifndef __ARCH_DESC_DEFS_H
-#define __ARCH_DESC_DEFS_H
+#ifndef ASM_X86__DESC_DEFS_H
+#define ASM_X86__DESC_DEFS_H
 
 /*
  * Segment descriptor structure definitions, usable from both x86_64 and i386
@@ -92,4 +92,4 @@ struct desc_ptr {
 
 #endif /* !__ASSEMBLY__ */
 
-#endif
+#endif /* ASM_X86__DESC_DEFS_H */
diff --git a/include/asm-x86/device.h b/include/asm-x86/device.h
index 3c034f48fdb0..1bece04c7d9d 100644
--- a/include/asm-x86/device.h
+++ b/include/asm-x86/device.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_DEVICE_H
-#define _ASM_X86_DEVICE_H
+#ifndef ASM_X86__DEVICE_H
+#define ASM_X86__DEVICE_H
 
 struct dev_archdata {
 #ifdef CONFIG_ACPI
@@ -13,4 +13,4 @@ struct dma_mapping_ops *dma_ops;
 #endif
 };
 
-#endif /* _ASM_X86_DEVICE_H */
+#endif /* ASM_X86__DEVICE_H */
diff --git a/include/asm-x86/div64.h b/include/asm-x86/div64.h
index 9a2d644c08ef..f9530f23f1d6 100644
--- a/include/asm-x86/div64.h
+++ b/include/asm-x86/div64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_DIV64_H
-#define _ASM_X86_DIV64_H
+#ifndef ASM_X86__DIV64_H
+#define ASM_X86__DIV64_H
 
 #ifdef CONFIG_X86_32
 
@@ -57,4 +57,4 @@ static inline u64 div_u64_rem(u64 dividend, u32 divisor, u32 *remainder)
 # include <asm-generic/div64.h>
 #endif /* CONFIG_X86_32 */
 
-#endif /* _ASM_X86_DIV64_H */
+#endif /* ASM_X86__DIV64_H */
diff --git a/include/asm-x86/dma-mapping.h b/include/asm-x86/dma-mapping.h
index ad9cd6d49bfc..219c33d6361c 100644
--- a/include/asm-x86/dma-mapping.h
+++ b/include/asm-x86/dma-mapping.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_DMA_MAPPING_H_
-#define _ASM_DMA_MAPPING_H_
+#ifndef ASM_X86__DMA_MAPPING_H
+#define ASM_X86__DMA_MAPPING_H
 
 /*
  * IOMMU interface. See Documentation/DMA-mapping.txt and DMA-API.txt for
@@ -9,12 +9,12 @@
 #include <linux/scatterlist.h>
 #include <asm/io.h>
 #include <asm/swiotlb.h>
+#include <asm-generic/dma-coherent.h>
 
 extern dma_addr_t bad_dma_address;
 extern int iommu_merge;
-extern struct device fallback_dev;
+extern struct device x86_dma_fallback_dev;
 extern int panic_on_overflow;
-extern int force_iommu;
 
 struct dma_mapping_ops {
         int             (*mapping_error)(struct device *dev,
@@ -25,9 +25,6 @@ struct dma_mapping_ops {
                                 void *vaddr, dma_addr_t dma_handle);
         dma_addr_t      (*map_single)(struct device *hwdev, phys_addr_t ptr,
                                 size_t size, int direction);
-        /* like map_single, but doesn't check the device mask */
-        dma_addr_t      (*map_simple)(struct device *hwdev, phys_addr_t ptr,
-                                size_t size, int direction);
         void            (*unmap_single)(struct device *dev, dma_addr_t addr,
                                 size_t size, int direction);
         void            (*sync_single_for_cpu)(struct device *hwdev,
@@ -68,7 +65,7 @@ static inline struct dma_mapping_ops *get_dma_ops(struct device *dev)
                 return dma_ops;
         else
                 return dev->archdata.dma_ops;
-#endif
+#endif /* ASM_X86__DMA_MAPPING_H */
 }
 
 /* Make sure we keep the same behaviour */
@@ -87,17 +84,14 @@ static inline int dma_mapping_error(struct device *dev, dma_addr_t dma_addr)
 
 #define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
 #define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-
-void *dma_alloc_coherent(struct device *dev, size_t size,
-                           dma_addr_t *dma_handle, gfp_t flag);
-
-void dma_free_coherent(struct device *dev, size_t size,
-                         void *vaddr, dma_addr_t dma_handle);
-
+#define dma_is_consistent(d, h) (1)
 
 extern int dma_supported(struct device *hwdev, u64 mask);
 extern int dma_set_mask(struct device *dev, u64 mask);
 
+extern void *dma_generic_alloc_coherent(struct device *dev, size_t size,
+                                        dma_addr_t *dma_addr, gfp_t flag);
+
 static inline dma_addr_t
 dma_map_single(struct device *hwdev, void *ptr, size_t size,
                int direction)
@@ -247,7 +241,68 @@ static inline int dma_get_cache_alignment(void)
         return boot_cpu_data.x86_clflush_size;
 }
 
-#define dma_is_consistent(d, h) (1)
+static inline unsigned long dma_alloc_coherent_mask(struct device *dev,
+                                                    gfp_t gfp)
+{
+        unsigned long dma_mask = 0;
+
+        dma_mask = dev->coherent_dma_mask;
+        if (!dma_mask)
+                dma_mask = (gfp & GFP_DMA) ? DMA_24BIT_MASK : DMA_32BIT_MASK;
+
+        return dma_mask;
+}
+
+static inline gfp_t dma_alloc_coherent_gfp_flags(struct device *dev, gfp_t gfp)
+{
+#ifdef CONFIG_X86_64
+        unsigned long dma_mask = dma_alloc_coherent_mask(dev, gfp);
+
+        if (dma_mask <= DMA_32BIT_MASK && !(gfp & GFP_DMA))
+                gfp |= GFP_DMA32;
+#endif
+       return gfp;
+}
+
+static inline void *
+dma_alloc_coherent(struct device *dev, size_t size, dma_addr_t *dma_handle,
+                gfp_t gfp)
+{
+        struct dma_mapping_ops *ops = get_dma_ops(dev);
+        void *memory;
+
+        gfp &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
+
+        if (dma_alloc_from_coherent(dev, size, dma_handle, &memory))
+                return memory;
+
+        if (!dev) {
+                dev = &x86_dma_fallback_dev;
+                gfp |= GFP_DMA;
+        }
+
+        if (!is_device_dma_capable(dev))
+                return NULL;
+
+        if (!ops->alloc_coherent)
+                return NULL;
+
+        return ops->alloc_coherent(dev, size, dma_handle,
+                                   dma_alloc_coherent_gfp_flags(dev, gfp));
+}
+
+static inline void dma_free_coherent(struct device *dev, size_t size,
+                                     void *vaddr, dma_addr_t bus)
+{
+        struct dma_mapping_ops *ops = get_dma_ops(dev);
+
+        WARN_ON(irqs_disabled());       /* for portability */
+
+        if (dma_release_from_coherent(dev, get_order(size), vaddr))
+                return;
+
+        if (ops->free_coherent)
+                ops->free_coherent(dev, size, vaddr, bus);
+}
 
-#include <asm-generic/dma-coherent.h>
 #endif
diff --git a/include/asm-x86/dma.h b/include/asm-x86/dma.h
index ca1098a7e580..c9f7a4eec555 100644
--- a/include/asm-x86/dma.h
+++ b/include/asm-x86/dma.h
@@ -5,8 +5,8 @@
  * and John Boyd, Nov. 1992.
  */
 
-#ifndef _ASM_X86_DMA_H
-#define _ASM_X86_DMA_H
+#ifndef ASM_X86__DMA_H
+#define ASM_X86__DMA_H
 
 #include <linux/spinlock.h>     /* And spinlocks */
 #include <asm/io.h>             /* need byte IO */
@@ -315,4 +315,4 @@ extern int isa_dma_bridge_buggy;
 #define isa_dma_bridge_buggy    (0)
 #endif
 
-#endif /* _ASM_X86_DMA_H */
+#endif /* ASM_X86__DMA_H */
diff --git a/include/asm-x86/dmi.h b/include/asm-x86/dmi.h
index 58a86571fe0f..1cff6fe81fa5 100644
--- a/include/asm-x86/dmi.h
+++ b/include/asm-x86/dmi.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_DMI_H
-#define _ASM_X86_DMI_H
+#ifndef ASM_X86__DMI_H
+#define ASM_X86__DMI_H
 
 #include <asm/io.h>
 
@@ -23,4 +23,4 @@ static inline void *dmi_alloc(unsigned len)
 #define dmi_ioremap early_ioremap
 #define dmi_iounmap early_iounmap
 
-#endif
+#endif /* ASM_X86__DMI_H */
diff --git a/include/asm-x86/ds.h b/include/asm-x86/ds.h
index 7881368142fa..c3c953a45b21 100644
--- a/include/asm-x86/ds.h
+++ b/include/asm-x86/ds.h
@@ -2,71 +2,237 @@
  * Debug Store (DS) support
  *
  * This provides a low-level interface to the hardware's Debug Store
- * feature that is used for last branch recording (LBR) and
+ * feature that is used for branch trace store (BTS) and
  * precise-event based sampling (PEBS).
  *
- * Different architectures use a different DS layout/pointer size.
- * The below functions therefore work on a void*.
+ * It manages:
+ * - per-thread and per-cpu allocation of BTS and PEBS
+ * - buffer memory allocation (optional)
+ * - buffer overflow handling
+ * - buffer access
  *
+ * It assumes:
+ * - get_task_struct on all parameter tasks
+ * - current is allowed to trace parameter tasks
  *
- * Since there is no user for PEBS, yet, only LBR (or branch
- * trace store, BTS) is supported.
  *
- *
- * Copyright (C) 2007 Intel Corporation.
- * Markus Metzger <markus.t.metzger@intel.com>, Dec 2007
+ * Copyright (C) 2007-2008 Intel Corporation.
+ * Markus Metzger <markus.t.metzger@intel.com>, 2007-2008
  */
 
-#ifndef _ASM_X86_DS_H
-#define _ASM_X86_DS_H
+#ifndef ASM_X86__DS_H
+#define ASM_X86__DS_H
+
+#ifdef CONFIG_X86_DS
 
 #include <linux/types.h>
 #include <linux/init.h>
 
-struct cpuinfo_x86;
 
+struct task_struct;
 
-/* a branch trace record entry
+/*
+ * Request BTS or PEBS
+ *
+ * Due to alignement constraints, the actual buffer may be slightly
+ * smaller than the requested or provided buffer.
  *
- * In order to unify the interface between various processor versions,
- * we use the below data structure for all processors.
+ * Returns 0 on success; -Eerrno otherwise
+ *
+ * task: the task to request recording for;
+ *       NULL for per-cpu recording on the current cpu
+ * base: the base pointer for the (non-pageable) buffer;
+ *       NULL if buffer allocation requested
+ * size: the size of the requested or provided buffer
+ * ovfl: pointer to a function to be called on buffer overflow;
+ *       NULL if cyclic buffer requested
  */
-enum bts_qualifier {
-        BTS_INVALID = 0,
-        BTS_BRANCH,
-        BTS_TASK_ARRIVES,
-        BTS_TASK_DEPARTS
-};
+typedef void (*ds_ovfl_callback_t)(struct task_struct *);
+extern int ds_request_bts(struct task_struct *task, void *base, size_t size,
+                          ds_ovfl_callback_t ovfl);
+extern int ds_request_pebs(struct task_struct *task, void *base, size_t size,
+                           ds_ovfl_callback_t ovfl);
 
-struct bts_struct {
-        u64 qualifier;
-        union {
-                /* BTS_BRANCH */
-                struct {
-                        u64 from_ip;
-                        u64 to_ip;
-                } lbr;
-                /* BTS_TASK_ARRIVES or
-                   BTS_TASK_DEPARTS */
-                u64 jiffies;
-        } variant;
+/*
+ * Release BTS or PEBS resources
+ *
+ * Frees buffers allocated on ds_request.
+ *
+ * Returns 0 on success; -Eerrno otherwise
+ *
+ * task: the task to release resources for;
+ *       NULL to release resources for the current cpu
+ */
+extern int ds_release_bts(struct task_struct *task);
+extern int ds_release_pebs(struct task_struct *task);
+
+/*
+ * Return the (array) index of the write pointer.
+ * (assuming an array of BTS/PEBS records)
+ *
+ * Returns -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ * pos (out): if not NULL, will hold the result
+ */
+extern int ds_get_bts_index(struct task_struct *task, size_t *pos);
+extern int ds_get_pebs_index(struct task_struct *task, size_t *pos);
+
+/*
+ * Return the (array) index one record beyond the end of the array.
+ * (assuming an array of BTS/PEBS records)
+ *
+ * Returns -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ * pos (out): if not NULL, will hold the result
+ */
+extern int ds_get_bts_end(struct task_struct *task, size_t *pos);
+extern int ds_get_pebs_end(struct task_struct *task, size_t *pos);
+
+/*
+ * Provide a pointer to the BTS/PEBS record at parameter index.
+ * (assuming an array of BTS/PEBS records)
+ *
+ * The pointer points directly into the buffer. The user is
+ * responsible for copying the record.
+ *
+ * Returns the size of a single record on success; -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ * index: the index of the requested record
+ * record (out): pointer to the requested record
+ */
+extern int ds_access_bts(struct task_struct *task,
+                         size_t index, const void **record);
+extern int ds_access_pebs(struct task_struct *task,
+                          size_t index, const void **record);
+
+/*
+ * Write one or more BTS/PEBS records at the write pointer index and
+ * advance the write pointer.
+ *
+ * If size is not a multiple of the record size, trailing bytes are
+ * zeroed out.
+ *
+ * May result in one or more overflow notifications.
+ *
+ * If called during overflow handling, that is, with index >=
+ * interrupt threshold, the write will wrap around.
+ *
+ * An overflow notification is given if and when the interrupt
+ * threshold is reached during or after the write.
+ *
+ * Returns the number of bytes written or -Eerrno.
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ * buffer: the buffer to write
+ * size: the size of the buffer
+ */
+extern int ds_write_bts(struct task_struct *task,
+                        const void *buffer, size_t size);
+extern int ds_write_pebs(struct task_struct *task,
+                         const void *buffer, size_t size);
+
+/*
+ * Same as ds_write_bts/pebs, but omit ownership checks.
+ *
+ * This is needed to have some other task than the owner of the
+ * BTS/PEBS buffer or the parameter task itself write into the
+ * respective buffer.
+ */
+extern int ds_unchecked_write_bts(struct task_struct *task,
+                                  const void *buffer, size_t size);
+extern int ds_unchecked_write_pebs(struct task_struct *task,
+                                   const void *buffer, size_t size);
+
+/*
+ * Reset the write pointer of the BTS/PEBS buffer.
+ *
+ * Returns 0 on success; -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ */
+extern int ds_reset_bts(struct task_struct *task);
+extern int ds_reset_pebs(struct task_struct *task);
+
+/*
+ * Clear the BTS/PEBS buffer and reset the write pointer.
+ * The entire buffer will be zeroed out.
+ *
+ * Returns 0 on success; -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ */
+extern int ds_clear_bts(struct task_struct *task);
+extern int ds_clear_pebs(struct task_struct *task);
+
+/*
+ * Provide the PEBS counter reset value.
+ *
+ * Returns 0 on success; -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ * value (out): the counter reset value
+ */
+extern int ds_get_pebs_reset(struct task_struct *task, u64 *value);
+
+/*
+ * Set the PEBS counter reset value.
+ *
+ * Returns 0 on success; -Eerrno on error
+ *
+ * task: the task to access;
+ *       NULL to access the current cpu
+ * value: the new counter reset value
+ */
+extern int ds_set_pebs_reset(struct task_struct *task, u64 value);
+
+/*
+ * Initialization
+ */
+struct cpuinfo_x86;
+extern void __cpuinit ds_init_intel(struct cpuinfo_x86 *);
+
+
+
+/*
+ * The DS context - part of struct thread_struct.
+ */
+struct ds_context {
+        /* pointer to the DS configuration; goes into MSR_IA32_DS_AREA */
+        unsigned char *ds;
+        /* the owner of the BTS and PEBS configuration, respectively */
+        struct task_struct *owner[2];
+        /* buffer overflow notification function for BTS and PEBS */
+        ds_ovfl_callback_t callback[2];
+        /* the original buffer address */
+        void *buffer[2];
+        /* the number of allocated pages for on-request allocated buffers */
+        unsigned int pages[2];
+        /* use count */
+        unsigned long count;
+        /* a pointer to the context location inside the thread_struct
+         * or the per_cpu context array */
+        struct ds_context **this;
+        /* a pointer to the task owning this context, or NULL, if the
+         * context is owned by a cpu */
+        struct task_struct *task;
 };
 
-/* Overflow handling mechanisms */
-#define DS_O_SIGNAL     1 /* send overflow signal */
-#define DS_O_WRAP       2 /* wrap around */
-
-extern int ds_allocate(void **, size_t);
-extern int ds_free(void **);
-extern int ds_get_bts_size(void *);
-extern int ds_get_bts_end(void *);
-extern int ds_get_bts_index(void *);
-extern int ds_set_overflow(void *, int);
-extern int ds_get_overflow(void *);
-extern int ds_clear(void *);
-extern int ds_read_bts(void *, int, struct bts_struct *);
-extern int ds_write_bts(void *, const struct bts_struct *);
-extern unsigned long ds_debugctl_mask(void);
-extern void __cpuinit ds_init_intel(struct cpuinfo_x86 *c);
-
-#endif /* _ASM_X86_DS_H */
+/* called by exit_thread() to free leftover contexts */
+extern void ds_free(struct ds_context *context);
+
+#else /* CONFIG_X86_DS */
+
+#define ds_init_intel(config) do {} while (0)
+
+#endif /* CONFIG_X86_DS */
+#endif /* ASM_X86__DS_H */
diff --git a/include/asm-x86/dwarf2.h b/include/asm-x86/dwarf2.h
index 738bb9fb3e53..21d1bc32ad7c 100644
--- a/include/asm-x86/dwarf2.h
+++ b/include/asm-x86/dwarf2.h
@@ -1,5 +1,5 @@
-#ifndef _DWARF2_H
-#define _DWARF2_H
+#ifndef ASM_X86__DWARF2_H
+#define ASM_X86__DWARF2_H
 
 #ifndef __ASSEMBLY__
 #warning "asm/dwarf2.h should be only included in pure assembly files"
@@ -58,4 +58,4 @@
 
 #endif
 
-#endif
+#endif /* ASM_X86__DWARF2_H */
diff --git a/include/asm-x86/e820.h b/include/asm-x86/e820.h
index 16a31e2c7c57..5abbdec06bd2 100644
--- a/include/asm-x86/e820.h
+++ b/include/asm-x86/e820.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_E820_H
-#define __ASM_E820_H
+#ifndef ASM_X86__E820_H
+#define ASM_X86__E820_H
 #define E820MAP 0x2d0           /* our map */
 #define E820MAX 128             /* number of entries in E820MAP */
 
@@ -43,6 +43,7 @@
 #define E820_RESERVED   2
 #define E820_ACPI       3
 #define E820_NVS        4
+#define E820_UNUSABLE   5
 
 /* reserved RAM used by kernel itself */
 #define E820_RESERVED_KERN        128
@@ -64,6 +65,7 @@ struct e820map {
 extern struct e820map e820;
 extern struct e820map e820_saved;
 
+extern unsigned long pci_mem_start;
 extern int e820_any_mapped(u64 start, u64 end, unsigned type);
 extern int e820_all_mapped(u64 start, u64 end, unsigned type);
 extern void e820_add_region(u64 start, u64 size, int type);
@@ -120,6 +122,7 @@ extern void e820_register_active_regions(int nid, unsigned long start_pfn,
 extern u64 e820_hole_size(u64 start, u64 end);
 extern void finish_e820_parsing(void);
 extern void e820_reserve_resources(void);
+extern void e820_reserve_resources_late(void);
 extern void setup_memory_map(void);
 extern char *default_machine_specific_memory_setup(void);
 extern char *machine_specific_memory_setup(void);
@@ -140,4 +143,4 @@ extern char *memory_setup(void);
 #define HIGH_MEMORY     (1024*1024)
 #endif /* __KERNEL__ */
 
-#endif  /* __ASM_E820_H */
+#endif /* ASM_X86__E820_H */
diff --git a/include/asm-x86/edac.h b/include/asm-x86/edac.h
index a8088f63a30e..9493c5b27bbd 100644
--- a/include/asm-x86/edac.h
+++ b/include/asm-x86/edac.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_EDAC_H
-#define _ASM_X86_EDAC_H
+#ifndef ASM_X86__EDAC_H
+#define ASM_X86__EDAC_H
 
 /* ECC atomic, DMA, SMP and interrupt safe scrub function */
 
@@ -15,4 +15,4 @@ static inline void atomic_scrub(void *va, u32 size)
                 asm volatile("lock; addl $0, %0"::"m" (*virt_addr));
 }
 
-#endif
+#endif /* ASM_X86__EDAC_H */
diff --git a/include/asm-x86/efi.h b/include/asm-x86/efi.h
index d4f2b0abe929..ed2de22e8705 100644
--- a/include/asm-x86/efi.h
+++ b/include/asm-x86/efi.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_EFI_H
-#define _ASM_X86_EFI_H
+#ifndef ASM_X86__EFI_H
+#define ASM_X86__EFI_H
 
 #ifdef CONFIG_X86_32
 
@@ -94,4 +94,4 @@ extern void efi_reserve_early(void);
 extern void efi_call_phys_prelog(void);
 extern void efi_call_phys_epilog(void);
 
-#endif
+#endif /* ASM_X86__EFI_H */
diff --git a/include/asm-x86/elf.h b/include/asm-x86/elf.h
index 7be4733c793e..26bc15f01e78 100644
--- a/include/asm-x86/elf.h
+++ b/include/asm-x86/elf.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_ELF_H
-#define _ASM_X86_ELF_H
+#ifndef ASM_X86__ELF_H
+#define ASM_X86__ELF_H
 
 /*
  * ELF register definitions..
@@ -148,8 +148,9 @@ do {						\
 
 static inline void start_ia32_thread(struct pt_regs *regs, u32 ip, u32 sp)
 {
-        asm volatile("movl %0,%%fs" :: "r" (0));
-        asm volatile("movl %0,%%es; movl %0,%%ds" : : "r" (__USER32_DS));
+        loadsegment(fs, 0);
+        loadsegment(ds, __USER32_DS);
+        loadsegment(es, __USER32_DS);
         load_gs_index(0);
         regs->ip = ip;
         regs->sp = sp;
@@ -185,7 +186,7 @@ do {							\
         set_fs(USER_DS);                                \
 } while (0)
 
-#define COMPAT_SET_PERSONALITY(ex, ibcs2)               \
+#define COMPAT_SET_PERSONALITY(ex)                      \
 do {                                                    \
         if (test_thread_flag(TIF_IA32))                 \
                 clear_thread_flag(TIF_ABI_PENDING);     \
@@ -266,7 +267,7 @@ extern int force_personality32;
    For the moment, we have only optimizations for the Intel generations,
    but that could change... */
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality_64bit()
+#define SET_PERSONALITY(ex) set_personality_64bit()
 
 /*
  * An executable for which elf_read_implies_exec() returns TRUE will
@@ -332,4 +333,4 @@ extern int syscall32_setup_pages(struct linux_binprm *, int exstack);
 extern unsigned long arch_randomize_brk(struct mm_struct *mm);
 #define arch_randomize_brk arch_randomize_brk
 
-#endif
+#endif /* ASM_X86__ELF_H */
diff --git a/include/asm-x86/emergency-restart.h b/include/asm-x86/emergency-restart.h
index 8e6aef19f8f0..190d0d8b71e3 100644
--- a/include/asm-x86/emergency-restart.h
+++ b/include/asm-x86/emergency-restart.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_EMERGENCY_RESTART_H
-#define _ASM_EMERGENCY_RESTART_H
+#ifndef ASM_X86__EMERGENCY_RESTART_H
+#define ASM_X86__EMERGENCY_RESTART_H
 
 enum reboot_type {
         BOOT_TRIPLE = 't',
@@ -15,4 +15,4 @@ extern enum reboot_type reboot_type;
 
 extern void machine_emergency_restart(void);
 
-#endif /* _ASM_EMERGENCY_RESTART_H */
+#endif /* ASM_X86__EMERGENCY_RESTART_H */
diff --git a/include/asm-x86/mach-es7000/mach_apic.h b/include/asm-x86/es7000/apic.h
index 0a3fdf930672..aae50c2fb303 100644
--- a/include/asm-x86/mach-es7000/mach_apic.h
+++ b/include/asm-x86/es7000/apic.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
+#ifndef __ASM_ES7000_APIC_H
+#define __ASM_ES7000_APIC_H
 
 #define xapic_phys_to_log_apicid(cpu) per_cpu(x86_bios_cpu_apicid, cpu)
 #define esr_disable (1)
@@ -10,7 +10,7 @@ static inline int apic_id_registered(void)
 }
 
 static inline cpumask_t target_cpus(void)
-{ 
+{
 #if defined CONFIG_ES7000_CLUSTERED_APIC
         return CPU_MASK_ALL;
 #else
@@ -23,24 +23,24 @@ static inline cpumask_t target_cpus(void)
 #define APIC_DFR_VALUE          (APIC_DFR_CLUSTER)
 #define INT_DELIVERY_MODE       (dest_LowestPrio)
 #define INT_DEST_MODE           (1)    /* logical delivery broadcast to all procs */
-#define NO_BALANCE_IRQ          (1)
+#define NO_BALANCE_IRQ          (1)
 #undef  WAKE_SECONDARY_VIA_INIT
 #define WAKE_SECONDARY_VIA_MIP
 #else
 #define APIC_DFR_VALUE          (APIC_DFR_FLAT)
 #define INT_DELIVERY_MODE       (dest_Fixed)
 #define INT_DEST_MODE           (0)    /* phys delivery to target procs */
-#define NO_BALANCE_IRQ          (0)
+#define NO_BALANCE_IRQ          (0)
 #undef  APIC_DEST_LOGICAL
 #define APIC_DEST_LOGICAL       0x0
 #define WAKE_SECONDARY_VIA_INIT
 #endif
 
 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
-{ 
+{
         return 0;
-} 
-static inline unsigned long check_apicid_present(int bit) 
+}
+static inline unsigned long check_apicid_present(int bit)
 {
         return physid_isset(bit, phys_cpu_present_map);
 }
@@ -80,7 +80,7 @@ static inline void setup_apic_routing(void)
 {
         int apic = per_cpu(x86_bios_cpu_apicid, smp_processor_id());
         printk("Enabling APIC mode:  %s.  Using %d I/O APICs, target cpus %lx\n",
-                (apic_version[apic] == 0x14) ? 
+                (apic_version[apic] == 0x14) ?
                 "Physical Cluster" : "Logical Cluster", nr_ioapics, cpus_addr(TARGET_CPUS)[0]);
 }
 
@@ -141,7 +141,7 @@ static inline void setup_portio_remap(void)
 extern unsigned int boot_cpu_physical_apicid;
 static inline int check_phys_apicid_present(int cpu_physical_apicid)
 {
-        boot_cpu_physical_apicid = GET_APIC_ID(read_apic_id());
+        boot_cpu_physical_apicid = read_apic_id();
         return (1);
 }
 
@@ -150,7 +150,7 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
         int num_bits_set;
         int cpus_found = 0;
         int cpu;
-        int apicid;     
+        int apicid;
 
         num_bits_set = cpus_weight(cpumask);
         /* Return id to all */
@@ -160,18 +160,18 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
 #else
                 return cpu_to_logical_apicid(0);
 #endif
-        /* 
-         * The cpus in the mask must all be on the apic cluster.  If are not 
-         * on the same apicid cluster return default value of TARGET_CPUS. 
+        /*
+         * The cpus in the mask must all be on the apic cluster.  If are not
+         * on the same apicid cluster return default value of TARGET_CPUS.
          */
         cpu = first_cpu(cpumask);
         apicid = cpu_to_logical_apicid(cpu);
         while (cpus_found < num_bits_set) {
                 if (cpu_isset(cpu, cpumask)) {
                         int new_apicid = cpu_to_logical_apicid(cpu);
-                        if (apicid_cluster(apicid) != 
+                        if (apicid_cluster(apicid) !=
                                         apicid_cluster(new_apicid)){
-                                printk ("%s: Not a valid mask!\n",__FUNCTION__);
+                                printk ("%s: Not a valid mask!\n", __func__);
 #if defined CONFIG_ES7000_CLUSTERED_APIC
                                 return 0xFF;
 #else
@@ -191,4 +191,4 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
         return cpuid_apic >> index_msb;
 }
 
-#endif /* __ASM_MACH_APIC_H */
+#endif /* __ASM_ES7000_APIC_H */
diff --git a/include/asm-x86/es7000/apicdef.h b/include/asm-x86/es7000/apicdef.h
new file mode 100644
index 000000000000..8b234a3cb851
--- /dev/null
+++ b/include/asm-x86/es7000/apicdef.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_ES7000_APICDEF_H
+#define __ASM_ES7000_APICDEF_H
+
+#define         APIC_ID_MASK            (0xFF<<24)
+
+static inline unsigned get_apic_id(unsigned long x)
+{
+        return (((x)>>24)&0xFF);
+}
+
+#define         GET_APIC_ID(x)  get_apic_id(x)
+
+#endif
diff --git a/include/asm-x86/mach-es7000/mach_ipi.h b/include/asm-x86/es7000/ipi.h
index 5e61bd220b06..632a955fcc0a 100644
--- a/include/asm-x86/mach-es7000/mach_ipi.h
+++ b/include/asm-x86/es7000/ipi.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_IPI_H
-#define __ASM_MACH_IPI_H
+#ifndef __ASM_ES7000_IPI_H
+#define __ASM_ES7000_IPI_H
 
 void send_IPI_mask_sequence(cpumask_t mask, int vector);
 
@@ -21,4 +21,4 @@ static inline void send_IPI_all(int vector)
         send_IPI_mask(cpu_online_map, vector);
 }
 
-#endif /* __ASM_MACH_IPI_H */
+#endif /* __ASM_ES7000_IPI_H */
diff --git a/include/asm-x86/mach-es7000/mach_mpparse.h b/include/asm-x86/es7000/mpparse.h
index ef26d3523625..ed5a3caae141 100644
--- a/include/asm-x86/mach-es7000/mach_mpparse.h
+++ b/include/asm-x86/es7000/mpparse.h
@@ -1,10 +1,11 @@
-#ifndef __ASM_MACH_MPPARSE_H
-#define __ASM_MACH_MPPARSE_H
+#ifndef __ASM_ES7000_MPPARSE_H
+#define __ASM_ES7000_MPPARSE_H
 
 #include <linux/acpi.h>
 
 extern int parse_unisys_oem (char *oemptr);
 extern int find_unisys_acpi_oem_table(unsigned long *oem_addr);
+extern void unmap_unisys_acpi_oem_table(unsigned long oem_addr);
 extern void setup_unisys(void);
 
 #ifndef CONFIG_X86_GENERICARCH
diff --git a/include/asm-x86/mach-es7000/mach_wakecpu.h b/include/asm-x86/es7000/wakecpu.h
index 84ff58314501..3ffc5a7bf667 100644
--- a/include/asm-x86/mach-es7000/mach_wakecpu.h
+++ b/include/asm-x86/es7000/wakecpu.h
@@ -1,7 +1,7 @@
-#ifndef __ASM_MACH_WAKECPU_H
-#define __ASM_MACH_WAKECPU_H
+#ifndef __ASM_ES7000_WAKECPU_H
+#define __ASM_ES7000_WAKECPU_H
 
-/* 
+/*
  * This file copes with machines that wakeup secondary CPUs by the
  * INIT, INIT, STARTUP sequence.
  */
diff --git a/include/asm-x86/fb.h b/include/asm-x86/fb.h
index 53018464aea6..aca38dbd9a64 100644
--- a/include/asm-x86/fb.h
+++ b/include/asm-x86/fb.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_FB_H
-#define _ASM_X86_FB_H
+#ifndef ASM_X86__FB_H
+#define ASM_X86__FB_H
 
 #include <linux/fb.h>
 #include <linux/fs.h>
@@ -18,4 +18,4 @@ extern int fb_is_primary_device(struct fb_info *info);
 static inline int fb_is_primary_device(struct fb_info *info) { return 0; }
 #endif
 
-#endif /* _ASM_X86_FB_H */
+#endif /* ASM_X86__FB_H */
diff --git a/include/asm-x86/fixmap.h b/include/asm-x86/fixmap.h
index 44d4f8217349..78e33a1bc591 100644
--- a/include/asm-x86/fixmap.h
+++ b/include/asm-x86/fixmap.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_FIXMAP_H
-#define _ASM_FIXMAP_H
+#ifndef ASM_X86__FIXMAP_H
+#define ASM_X86__FIXMAP_H
 
 #ifdef CONFIG_X86_32
 # include "fixmap_32.h"
@@ -65,4 +65,4 @@ static inline unsigned long virt_to_fix(const unsigned long vaddr)
         BUG_ON(vaddr >= FIXADDR_TOP || vaddr < FIXADDR_START);
         return __virt_to_fix(vaddr);
 }
-#endif
+#endif /* ASM_X86__FIXMAP_H */
diff --git a/include/asm-x86/fixmap_32.h b/include/asm-x86/fixmap_32.h
index f1ac2b2167d7..8844002da0e0 100644
--- a/include/asm-x86/fixmap_32.h
+++ b/include/asm-x86/fixmap_32.h
@@ -10,8 +10,8 @@
  * Support of BIGMEM added by Gerhard Wichert, Siemens AG, July 1999
  */
 
-#ifndef _ASM_FIXMAP_32_H
-#define _ASM_FIXMAP_32_H
+#ifndef ASM_X86__FIXMAP_32_H
+#define ASM_X86__FIXMAP_32_H
 
 
 /* used by vmalloc.c, vsyscall.lds.S.
@@ -94,10 +94,10 @@ enum fixed_addresses {
          * can have a single pgd entry and a single pte table:
          */
 #define NR_FIX_BTMAPS           64
-#define FIX_BTMAPS_NESTING      4
+#define FIX_BTMAPS_SLOTS        4
         FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 256 -
                         (__end_of_permanent_fixed_addresses & 255),
-        FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_NESTING - 1,
+        FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_SLOTS - 1,
         FIX_WP_TEST,
 #ifdef CONFIG_ACPI
         FIX_ACPI_BEGIN,
@@ -120,4 +120,4 @@ extern void reserve_top_address(unsigned long reserve);
 #define FIXADDR_BOOT_START      (FIXADDR_TOP - __FIXADDR_BOOT_SIZE)
 
 #endif /* !__ASSEMBLY__ */
-#endif
+#endif /* ASM_X86__FIXMAP_32_H */
diff --git a/include/asm-x86/fixmap_64.h b/include/asm-x86/fixmap_64.h
index 00f3d74a0524..dab4751d1307 100644
--- a/include/asm-x86/fixmap_64.h
+++ b/include/asm-x86/fixmap_64.h
@@ -8,8 +8,8 @@
  * Copyright (C) 1998 Ingo Molnar
  */
 
-#ifndef _ASM_FIXMAP_64_H
-#define _ASM_FIXMAP_64_H
+#ifndef ASM_X86__FIXMAP_64_H
+#define ASM_X86__FIXMAP_64_H
 
 #include <linux/kernel.h>
 #include <asm/acpi.h>
@@ -49,6 +49,7 @@ enum fixed_addresses {
 #ifdef CONFIG_PARAVIRT
         FIX_PARAVIRT_BOOTMAP,
 #endif
+        __end_of_permanent_fixed_addresses,
 #ifdef CONFIG_ACPI
         FIX_ACPI_BEGIN,
         FIX_ACPI_END = FIX_ACPI_BEGIN + FIX_ACPI_PAGES - 1,
@@ -56,19 +57,18 @@ enum fixed_addresses {
 #ifdef CONFIG_PROVIDE_OHCI1394_DMA_INIT
         FIX_OHCI1394_BASE,
 #endif
-        __end_of_permanent_fixed_addresses,
         /*
          * 256 temporary boot-time mappings, used by early_ioremap(),
          * before ioremap() is functional.
          *
-         * We round it up to the next 512 pages boundary so that we
+         * We round it up to the next 256 pages boundary so that we
          * can have a single pgd entry and a single pte table:
          */
 #define NR_FIX_BTMAPS           64
-#define FIX_BTMAPS_NESTING      4
-        FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 512 -
-                        (__end_of_permanent_fixed_addresses & 511),
-        FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_NESTING - 1,
+#define FIX_BTMAPS_SLOTS        4
+        FIX_BTMAP_END = __end_of_permanent_fixed_addresses + 256 -
+                        (__end_of_permanent_fixed_addresses & 255),
+        FIX_BTMAP_BEGIN = FIX_BTMAP_END + NR_FIX_BTMAPS*FIX_BTMAPS_SLOTS - 1,
         __end_of_fixed_addresses
 };
 
@@ -80,4 +80,4 @@ enum fixed_addresses {
 #define FIXADDR_USER_START      ((unsigned long)VSYSCALL32_VSYSCALL)
 #define FIXADDR_USER_END        (FIXADDR_USER_START + PAGE_SIZE)
 
-#endif
+#endif /* ASM_X86__FIXMAP_64_H */
diff --git a/include/asm-x86/floppy.h b/include/asm-x86/floppy.h
index dbe82a5c5eac..7d83a3a83e37 100644
--- a/include/asm-x86/floppy.h
+++ b/include/asm-x86/floppy.h
@@ -7,8 +7,8 @@
  *
  * Copyright (C) 1995
  */
-#ifndef _ASM_X86_FLOPPY_H
-#define _ASM_X86_FLOPPY_H
+#ifndef ASM_X86__FLOPPY_H
+#define ASM_X86__FLOPPY_H
 
 #include <linux/vmalloc.h>
 
@@ -278,4 +278,4 @@ static int FDC2 = -1;
 
 #define EXTRA_FLOPPY_PARAMS
 
-#endif /* _ASM_X86_FLOPPY_H */
+#endif /* ASM_X86__FLOPPY_H */
diff --git a/include/asm-x86/ftrace.h b/include/asm-x86/ftrace.h
index 5c68b32ee1c8..be0e004ad148 100644
--- a/include/asm-x86/ftrace.h
+++ b/include/asm-x86/ftrace.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_FTRACE
-#define _ASM_X86_FTRACE
+#ifndef ASM_X86__FTRACE_H
+#define ASM_X86__FTRACE_H
 
 #ifdef CONFIG_FTRACE
 #define MCOUNT_ADDR             ((long)(mcount))
@@ -11,4 +11,4 @@ extern void mcount(void);
 
 #endif /* CONFIG_FTRACE */
 
-#endif /* _ASM_X86_FTRACE */
+#endif /* ASM_X86__FTRACE_H */
diff --git a/include/asm-x86/futex.h b/include/asm-x86/futex.h
index e7a76b37b333..06b924ef6fa5 100644
--- a/include/asm-x86/futex.h
+++ b/include/asm-x86/futex.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_FUTEX_H
-#define _ASM_X86_FUTEX_H
+#ifndef ASM_X86__FUTEX_H
+#define ASM_X86__FUTEX_H
 
 #ifdef __KERNEL__
 
@@ -25,7 +25,7 @@
         asm volatile("1:\tmovl  %2, %0\n"                       \
                      "\tmovl\t%0, %3\n"                         \
                      "\t" insn "\n"                             \
-                     "2:\tlock; cmpxchgl %3, %2\n"              \
+                     "2:\t" LOCK_PREFIX "cmpxchgl %3, %2\n"     \
                      "\tjnz\t1b\n"                              \
                      "3:\t.section .fixup,\"ax\"\n"             \
                      "4:\tmov\t%5, %1\n"                        \
@@ -64,7 +64,7 @@ static inline int futex_atomic_op_inuser(int encoded_op, int __user *uaddr)
                 __futex_atomic_op1("xchgl %0, %2", ret, oldval, uaddr, oparg);
                 break;
         case FUTEX_OP_ADD:
-                __futex_atomic_op1("lock; xaddl %0, %2", ret, oldval,
+                __futex_atomic_op1(LOCK_PREFIX "xaddl %0, %2", ret, oldval,
                                    uaddr, oparg);
                 break;
         case FUTEX_OP_OR:
@@ -122,7 +122,7 @@ static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval,
         if (!access_ok(VERIFY_WRITE, uaddr, sizeof(int)))
                 return -EFAULT;
 
-        asm volatile("1:\tlock; cmpxchgl %3, %1\n"
+        asm volatile("1:\t" LOCK_PREFIX "cmpxchgl %3, %1\n"
                      "2:\t.section .fixup, \"ax\"\n"
                      "3:\tmov     %2, %0\n"
                      "\tjmp     2b\n"
@@ -137,4 +137,4 @@ static inline int futex_atomic_cmpxchg_inatomic(int __user *uaddr, int oldval,
 }
 
 #endif
-#endif
+#endif /* ASM_X86__FUTEX_H */
diff --git a/include/asm-x86/gart.h b/include/asm-x86/gart.h
index 3f62a83887f3..605edb39ef9e 100644
--- a/include/asm-x86/gart.h
+++ b/include/asm-x86/gart.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X8664_GART_H
-#define _ASM_X8664_GART_H 1
+#ifndef ASM_X86__GART_H
+#define ASM_X86__GART_H
 
 #include <asm/e820.h>
 
@@ -29,6 +29,8 @@ extern int fix_aperture;
 #define AMD64_GARTCACHECTL      0x9c
 #define AMD64_GARTEN            (1<<0)
 
+extern int agp_amd64_init(void);
+
 static inline void enable_gart_translation(struct pci_dev *dev, u64 addr)
 {
         u32 tmp, ctl;
@@ -52,15 +54,15 @@ static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
                 return 0;
 
         if (aper_base + aper_size > 0x100000000ULL) {
-                printk(KERN_ERR "Aperture beyond 4GB. Ignoring.\n");
+                printk(KERN_INFO "Aperture beyond 4GB. Ignoring.\n");
                 return 0;
         }
         if (e820_any_mapped(aper_base, aper_base + aper_size, E820_RAM)) {
-                printk(KERN_ERR "Aperture pointing to e820 RAM. Ignoring.\n");
+                printk(KERN_INFO "Aperture pointing to e820 RAM. Ignoring.\n");
                 return 0;
         }
         if (aper_size < min_size) {
-                printk(KERN_ERR "Aperture too small (%d MB) than (%d MB)\n",
+                printk(KERN_INFO "Aperture too small (%d MB) than (%d MB)\n",
                                  aper_size>>20, min_size>>20);
                 return 0;
         }
@@ -68,4 +70,4 @@ static inline int aperture_valid(u64 aper_base, u32 aper_size, u32 min_size)
         return 1;
 }
 
-#endif
+#endif /* ASM_X86__GART_H */
diff --git a/include/asm-x86/genapic_32.h b/include/asm-x86/genapic_32.h
index b02ea6e17de8..34280f027664 100644
--- a/include/asm-x86/genapic_32.h
+++ b/include/asm-x86/genapic_32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_GENAPIC_H
-#define _ASM_GENAPIC_H 1
+#ifndef ASM_X86__GENAPIC_32_H
+#define ASM_X86__GENAPIC_32_H
 
 #include <asm/mpspec.h>
 
@@ -118,6 +118,7 @@ enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
 #define get_uv_system_type()            UV_NONE
 #define is_uv_system()                  0
 #define uv_wakeup_secondary(a, b)       1
+#define uv_system_init()                do {} while (0)
 
 
-#endif
+#endif /* ASM_X86__GENAPIC_32_H */
diff --git a/include/asm-x86/genapic_64.h b/include/asm-x86/genapic_64.h
index 0f8504627c41..ed6a4886c082 100644
--- a/include/asm-x86/genapic_64.h
+++ b/include/asm-x86/genapic_64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_GENAPIC_H
-#define _ASM_GENAPIC_H 1
+#ifndef ASM_X86__GENAPIC_64_H
+#define ASM_X86__GENAPIC_64_H
 
 /*
  * Copyright 2004 James Cleverdon, IBM.
@@ -14,6 +14,7 @@
 
 struct genapic {
         char *name;
+        int (*acpi_madt_oem_check)(char *oem_id, char *oem_table_id);
         u32 int_delivery_mode;
         u32 int_dest_mode;
         int (*apic_id_registered)(void);
@@ -24,17 +25,24 @@ struct genapic {
         void (*send_IPI_mask)(cpumask_t mask, int vector);
         void (*send_IPI_allbutself)(int vector);
         void (*send_IPI_all)(int vector);
+        void (*send_IPI_self)(int vector);
         /* */
         unsigned int (*cpu_mask_to_apicid)(cpumask_t cpumask);
         unsigned int (*phys_pkg_id)(int index_msb);
+        unsigned int (*get_apic_id)(unsigned long x);
+        unsigned long (*set_apic_id)(unsigned int id);
+        unsigned long apic_id_mask;
 };
 
 extern struct genapic *genapic;
 
 extern struct genapic apic_flat;
 extern struct genapic apic_physflat;
+extern struct genapic apic_x2apic_cluster;
+extern struct genapic apic_x2apic_phys;
 extern int acpi_madt_oem_check(char *, char *);
 
+extern void apic_send_IPI_self(int vector);
 enum uv_system_type {UV_NONE, UV_LEGACY_APIC, UV_X2APIC, UV_NON_UNIQUE_APIC};
 extern enum uv_system_type get_uv_system_type(void);
 extern int is_uv_system(void);
@@ -42,8 +50,9 @@ extern int is_uv_system(void);
 extern struct genapic apic_x2apic_uv_x;
 DECLARE_PER_CPU(int, x2apic_extra_bits);
 extern void uv_cpu_init(void);
+extern void uv_system_init(void);
 extern int uv_wakeup_secondary(int phys_apicid, unsigned int start_rip);
 
 extern void setup_apic_routing(void);
 
-#endif
+#endif /* ASM_X86__GENAPIC_64_H */
diff --git a/include/asm-x86/geode.h b/include/asm-x86/geode.h
index 2c1cda0b8a86..3f3444be2638 100644
--- a/include/asm-x86/geode.h
+++ b/include/asm-x86/geode.h
@@ -7,8 +7,8 @@
  * as published by the Free Software Foundation.
  */
 
-#ifndef _ASM_GEODE_H_
-#define _ASM_GEODE_H_
+#ifndef ASM_X86__GEODE_H
+#define ASM_X86__GEODE_H
 
 #include <asm/processor.h>
 #include <linux/io.h>
@@ -250,4 +250,4 @@ extern int __init mfgpt_timer_setup(void);
 static inline int mfgpt_timer_setup(void) { return 0; }
 #endif
 
-#endif
+#endif /* ASM_X86__GEODE_H */
diff --git a/include/asm-x86/gpio.h b/include/asm-x86/gpio.h
index c4c91b37c104..497fb980d962 100644
--- a/include/asm-x86/gpio.h
+++ b/include/asm-x86/gpio.h
@@ -53,4 +53,4 @@ static inline int irq_to_gpio(unsigned int irq)
 
 #endif /* CONFIG_GPIOLIB */
 
-#endif /* _ASM_I386_GPIO_H */
+#endif /* ASM_X86__GPIO_H */
diff --git a/include/asm-x86/hardirq_32.h b/include/asm-x86/hardirq_32.h
index 4f85f0f4b563..700fe230d919 100644
--- a/include/asm-x86/hardirq_32.h
+++ b/include/asm-x86/hardirq_32.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
+#ifndef ASM_X86__HARDIRQ_32_H
+#define ASM_X86__HARDIRQ_32_H
 
 #include <linux/threads.h>
 #include <linux/irq.h>
@@ -25,4 +25,4 @@ DECLARE_PER_CPU(irq_cpustat_t, irq_stat);
 void ack_bad_irq(unsigned int irq);
 #include <linux/irq_cpustat.h>
 
-#endif /* __ASM_HARDIRQ_H */
+#endif /* ASM_X86__HARDIRQ_32_H */
diff --git a/include/asm-x86/hardirq_64.h b/include/asm-x86/hardirq_64.h
index 95d5e090ed89..f8bd2919a8ce 100644
--- a/include/asm-x86/hardirq_64.h
+++ b/include/asm-x86/hardirq_64.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_HARDIRQ_H
-#define __ASM_HARDIRQ_H
+#ifndef ASM_X86__HARDIRQ_64_H
+#define ASM_X86__HARDIRQ_64_H
 
 #include <linux/threads.h>
 #include <linux/irq.h>
@@ -20,4 +20,4 @@
 
 extern void ack_bad_irq(unsigned int irq);
 
-#endif /* __ASM_HARDIRQ_H */
+#endif /* ASM_X86__HARDIRQ_64_H */
diff --git a/include/asm-x86/highmem.h b/include/asm-x86/highmem.h
index 4514b16cc723..bc3f6a280316 100644
--- a/include/asm-x86/highmem.h
+++ b/include/asm-x86/highmem.h
@@ -15,8 +15,8 @@
  * Copyright (C) 1999 Ingo Molnar <mingo@redhat.com>
  */
 
-#ifndef _ASM_HIGHMEM_H
-#define _ASM_HIGHMEM_H
+#ifndef ASM_X86__HIGHMEM_H
+#define ASM_X86__HIGHMEM_H
 
 #ifdef __KERNEL__
 
@@ -79,4 +79,4 @@ extern void add_highpages_with_active_regions(int nid, unsigned long start_pfn,
 
 #endif /* __KERNEL__ */
 
-#endif /* _ASM_HIGHMEM_H */
+#endif /* ASM_X86__HIGHMEM_H */
diff --git a/include/asm-x86/hpet.h b/include/asm-x86/hpet.h
index 82f1ac641bd7..cbbbb6d4dd32 100644
--- a/include/asm-x86/hpet.h
+++ b/include/asm-x86/hpet.h
@@ -1,5 +1,5 @@
-#ifndef ASM_X86_HPET_H
-#define ASM_X86_HPET_H
+#ifndef ASM_X86__HPET_H
+#define ASM_X86__HPET_H
 
 #ifdef CONFIG_HPET_TIMER
 
@@ -90,4 +90,4 @@ static inline int is_hpet_enabled(void) { return 0; }
 #define hpet_readl(a) 0
 
 #endif
-#endif /* ASM_X86_HPET_H */
+#endif /* ASM_X86__HPET_H */
diff --git a/include/asm-x86/hugetlb.h b/include/asm-x86/hugetlb.h
index 439a9acc132d..0b7ec5dc0884 100644
--- a/include/asm-x86/hugetlb.h
+++ b/include/asm-x86/hugetlb.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_HUGETLB_H
-#define _ASM_X86_HUGETLB_H
+#ifndef ASM_X86__HUGETLB_H
+#define ASM_X86__HUGETLB_H
 
 #include <asm/page.h>
 
@@ -90,4 +90,4 @@ static inline void arch_release_hugepage(struct page *page)
 {
 }
 
-#endif /* _ASM_X86_HUGETLB_H */
+#endif /* ASM_X86__HUGETLB_H */
diff --git a/include/asm-x86/hw_irq.h b/include/asm-x86/hw_irq.h
index edd0b95f14d0..50f6e0316b50 100644
--- a/include/asm-x86/hw_irq.h
+++ b/include/asm-x86/hw_irq.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_HW_IRQ_H
-#define _ASM_HW_IRQ_H
+#ifndef ASM_X86__HW_IRQ_H
+#define ASM_X86__HW_IRQ_H
 
 /*
  * (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
@@ -64,7 +64,6 @@ extern unsigned long io_apic_irqs;
 extern void init_VISWS_APIC_irqs(void);
 extern void setup_IO_APIC(void);
 extern void disable_IO_APIC(void);
-extern void print_IO_APIC(void);
 extern int IO_APIC_get_PCI_irq_vector(int bus, int slot, int fn);
 extern void setup_ioapic_dest(void);
 
@@ -73,7 +72,9 @@ extern void enable_IO_APIC(void);
 #endif
 
 /* IPI functions */
+#ifdef CONFIG_X86_32
 extern void send_IPI_self(int vector);
+#endif
 extern void send_IPI(int dest, int vector);
 
 /* Statistics */
@@ -93,6 +94,26 @@ extern asmlinkage void qic_reschedule_interrupt(void);
 extern asmlinkage void qic_enable_irq_interrupt(void);
 extern asmlinkage void qic_call_function_interrupt(void);
 
+/* SMP */
+extern void smp_apic_timer_interrupt(struct pt_regs *);
+#ifdef CONFIG_X86_32
+extern void smp_spurious_interrupt(struct pt_regs *);
+extern void smp_error_interrupt(struct pt_regs *);
+#else
+extern asmlinkage void smp_spurious_interrupt(void);
+extern asmlinkage void smp_error_interrupt(void);
+#endif
+#ifdef CONFIG_X86_SMP
+extern void smp_reschedule_interrupt(struct pt_regs *);
+extern void smp_call_function_interrupt(struct pt_regs *);
+extern void smp_call_function_single_interrupt(struct pt_regs *);
+#ifdef CONFIG_X86_32
+extern void smp_invalidate_interrupt(struct pt_regs *);
+#else
+extern asmlinkage void smp_invalidate_interrupt(struct pt_regs *);
+#endif
+#endif
+
 #ifdef CONFIG_X86_32
 extern void (*const interrupt[NR_IRQS])(void);
 #else
@@ -112,4 +133,4 @@ static inline void __setup_vector_irq(int cpu) {}
 
 #endif /* !ASSEMBLY_ */
 
-#endif
+#endif /* ASM_X86__HW_IRQ_H */
diff --git a/include/asm-x86/hypertransport.h b/include/asm-x86/hypertransport.h
index d2bbd238b3e1..cc011a3bc1c2 100644
--- a/include/asm-x86/hypertransport.h
+++ b/include/asm-x86/hypertransport.h
@@ -1,5 +1,5 @@
-#ifndef ASM_HYPERTRANSPORT_H
-#define ASM_HYPERTRANSPORT_H
+#ifndef ASM_X86__HYPERTRANSPORT_H
+#define ASM_X86__HYPERTRANSPORT_H
 
 /*
  * Constants for x86 Hypertransport Interrupts.
@@ -42,4 +42,4 @@
 #define HT_IRQ_HIGH_DEST_ID(v)                                          \
         ((((v) >> 8) << HT_IRQ_HIGH_DEST_ID_SHIFT) & HT_IRQ_HIGH_DEST_ID_MASK)
 
-#endif /* ASM_HYPERTRANSPORT_H */
+#endif /* ASM_X86__HYPERTRANSPORT_H */
diff --git a/include/asm-x86/i387.h b/include/asm-x86/i387.h
index 56d00e31aec0..9ba862a4eac0 100644
--- a/include/asm-x86/i387.h
+++ b/include/asm-x86/i387.h
@@ -7,8 +7,8 @@
  * x86-64 work by Andi Kleen 2002
  */
 
-#ifndef _ASM_X86_I387_H
-#define _ASM_X86_I387_H
+#ifndef ASM_X86__I387_H
+#define ASM_X86__I387_H
 
 #include <linux/sched.h>
 #include <linux/kernel_stat.h>
@@ -19,23 +19,32 @@
 #include <asm/sigcontext.h>
 #include <asm/user.h>
 #include <asm/uaccess.h>
+#include <asm/xsave.h>
 
+extern unsigned int sig_xstate_size;
 extern void fpu_init(void);
 extern void mxcsr_feature_mask_init(void);
 extern int init_fpu(struct task_struct *child);
 extern asmlinkage void math_state_restore(void);
 extern void init_thread_xstate(void);
+extern int dump_fpu(struct pt_regs *, struct user_i387_struct *);
 
 extern user_regset_active_fn fpregs_active, xfpregs_active;
 extern user_regset_get_fn fpregs_get, xfpregs_get, fpregs_soft_get;
 extern user_regset_set_fn fpregs_set, xfpregs_set, fpregs_soft_set;
 
+extern struct _fpx_sw_bytes fx_sw_reserved;
 #ifdef CONFIG_IA32_EMULATION
+extern unsigned int sig_xstate_ia32_size;
+extern struct _fpx_sw_bytes fx_sw_reserved_ia32;
 struct _fpstate_ia32;
-extern int save_i387_ia32(struct _fpstate_ia32 __user *buf);
-extern int restore_i387_ia32(struct _fpstate_ia32 __user *buf);
+struct _xstate_ia32;
+extern int save_i387_xstate_ia32(void __user *buf);
+extern int restore_i387_xstate_ia32(void __user *buf);
 #endif
 
+#define X87_FSW_ES (1 << 7)     /* Exception Summary */
+
 #ifdef CONFIG_X86_64
 
 /* Ignore delayed exceptions from user space */
@@ -46,7 +55,7 @@ static inline void tolerant_fwait(void)
                      _ASM_EXTABLE(1b, 2b));
 }
 
-static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
+static inline int fxrstor_checking(struct i387_fxsave_struct *fx)
 {
         int err;
 
@@ -66,15 +75,31 @@ static inline int restore_fpu_checking(struct i387_fxsave_struct *fx)
         return err;
 }
 
-#define X87_FSW_ES (1 << 7)     /* Exception Summary */
+static inline int restore_fpu_checking(struct task_struct *tsk)
+{
+        if (task_thread_info(tsk)->status & TS_XSAVE)
+                return xrstor_checking(&tsk->thread.xstate->xsave);
+        else
+                return fxrstor_checking(&tsk->thread.xstate->fxsave);
+}
 
 /* AMD CPUs don't save/restore FDP/FIP/FOP unless an exception
    is pending. Clear the x87 state here by setting it to fixed
    values. The kernel data segment can be sometimes 0 and sometimes
    new user value. Both should be ok.
    Use the PDA as safe address because it should be already in L1. */
-static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
+static inline void clear_fpu_state(struct task_struct *tsk)
 {
+        struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
+        struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
+
+        /*
+         * xsave header may indicate the init state of the FP.
+         */
+        if ((task_thread_info(tsk)->status & TS_XSAVE) &&
+            !(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
+                return;
+
         if (unlikely(fx->swd & X87_FSW_ES))
                 asm volatile("fnclex");
         alternative_input(ASM_NOP8 ASM_NOP2,
@@ -83,7 +108,7 @@ static inline void clear_fpu_state(struct i387_fxsave_struct *fx)
                           X86_FEATURE_FXSAVE_LEAK);
 }
 
-static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
+static inline int fxsave_user(struct i387_fxsave_struct __user *fx)
 {
         int err;
 
@@ -107,7 +132,7 @@ static inline int save_i387_checking(struct i387_fxsave_struct __user *fx)
         return err;
 }
 
-static inline void __save_init_fpu(struct task_struct *tsk)
+static inline void fxsave(struct task_struct *tsk)
 {
         /* Using "rex64; fxsave %0" is broken because, if the memory operand
            uses any extended registers for addressing, a second REX prefix
@@ -132,7 +157,16 @@ static inline void __save_init_fpu(struct task_struct *tsk)
                              : "=m" (tsk->thread.xstate->fxsave)
                              : "cdaSDb" (&tsk->thread.xstate->fxsave));
 #endif
-        clear_fpu_state(&tsk->thread.xstate->fxsave);
+}
+
+static inline void __save_init_fpu(struct task_struct *tsk)
+{
+        if (task_thread_info(tsk)->status & TS_XSAVE)
+                xsave(tsk);
+        else
+                fxsave(tsk);
+
+        clear_fpu_state(tsk);
         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 }
 
@@ -147,6 +181,10 @@ static inline void tolerant_fwait(void)
 
 static inline void restore_fpu(struct task_struct *tsk)
 {
+        if (task_thread_info(tsk)->status & TS_XSAVE) {
+                xrstor_checking(&tsk->thread.xstate->xsave);
+                return;
+        }
         /*
          * The "nop" is needed to make the instructions the same
          * length.
@@ -172,6 +210,27 @@ static inline void restore_fpu(struct task_struct *tsk)
  */
 static inline void __save_init_fpu(struct task_struct *tsk)
 {
+        if (task_thread_info(tsk)->status & TS_XSAVE) {
+                struct xsave_struct *xstate = &tsk->thread.xstate->xsave;
+                struct i387_fxsave_struct *fx = &tsk->thread.xstate->fxsave;
+
+                xsave(tsk);
+
+                /*
+                 * xsave header may indicate the init state of the FP.
+                 */
+                if (!(xstate->xsave_hdr.xstate_bv & XSTATE_FP))
+                        goto end;
+
+                if (unlikely(fx->swd & X87_FSW_ES))
+                        asm volatile("fnclex");
+
+                /*
+                 * we can do a simple return here or be paranoid :)
+                 */
+                goto clear_state;
+        }
+
         /* Use more nops than strictly needed in case the compiler
            varies code */
         alternative_input(
@@ -181,6 +240,7 @@ static inline void __save_init_fpu(struct task_struct *tsk)
                 X86_FEATURE_FXSR,
                 [fx] "m" (tsk->thread.xstate->fxsave),
                 [fsw] "m" (tsk->thread.xstate->fxsave.swd) : "memory");
+clear_state:
         /* AMD K7/K8 CPUs don't save/restore FDP/FIP/FOP unless an exception
            is pending.  Clear the x87 state here by setting it to fixed
            values. safe_address is a random variable that should be in L1 */
@@ -190,16 +250,17 @@ static inline void __save_init_fpu(struct task_struct *tsk)
                 "fildl %[addr]",        /* set F?P to defined value */
                 X86_FEATURE_FXSAVE_LEAK,
                 [addr] "m" (safe_address));
+end:
         task_thread_info(tsk)->status &= ~TS_USEDFPU;
 }
 
+#endif  /* CONFIG_X86_64 */
+
 /*
  * Signal frame handlers...
  */
-extern int save_i387(struct _fpstate __user *buf);
-extern int restore_i387(struct _fpstate __user *buf);
-
-#endif  /* CONFIG_X86_64 */
+extern int save_i387_xstate(void __user *buf);
+extern int restore_i387_xstate(void __user *buf);
 
 static inline void __unlazy_fpu(struct task_struct *tsk)
 {
@@ -336,4 +397,4 @@ static inline unsigned short get_fpu_mxcsr(struct task_struct *tsk)
         }
 }
 
-#endif  /* _ASM_X86_I387_H */
+#endif /* ASM_X86__I387_H */
diff --git a/include/asm-x86/i8253.h b/include/asm-x86/i8253.h
index b51c0487fc41..15a5b530044e 100644
--- a/include/asm-x86/i8253.h
+++ b/include/asm-x86/i8253.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_I8253_H__
-#define __ASM_I8253_H__
+#ifndef ASM_X86__I8253_H
+#define ASM_X86__I8253_H
 
 /* i8253A PIT registers */
 #define PIT_MODE                0x43
@@ -15,4 +15,4 @@ extern void setup_pit_timer(void);
 #define inb_pit         inb_p
 #define outb_pit        outb_p
 
-#endif  /* __ASM_I8253_H__ */
+#endif /* ASM_X86__I8253_H */
diff --git a/include/asm-x86/i8259.h b/include/asm-x86/i8259.h
index 2f98df91f1f2..23c1b3baaecd 100644
--- a/include/asm-x86/i8259.h
+++ b/include/asm-x86/i8259.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_I8259_H__
-#define __ASM_I8259_H__
+#ifndef ASM_X86__I8259_H
+#define ASM_X86__I8259_H
 
 #include <linux/delay.h>
 
@@ -57,4 +57,7 @@ static inline void outb_pic(unsigned char value, unsigned int port)
 
 extern struct irq_chip i8259A_chip;
 
-#endif  /* __ASM_I8259_H__ */
+extern void mask_8259A(void);
+extern void unmask_8259A(void);
+
+#endif /* ASM_X86__I8259_H */
diff --git a/include/asm-x86/ia32.h b/include/asm-x86/ia32.h
index 55d3abe5276f..f932f7ad51dd 100644
--- a/include/asm-x86/ia32.h
+++ b/include/asm-x86/ia32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_IA32_H
-#define _ASM_X86_64_IA32_H
+#ifndef ASM_X86__IA32_H
+#define ASM_X86__IA32_H
 
 
 #ifdef CONFIG_IA32_EMULATION
@@ -167,4 +167,4 @@ extern void ia32_pick_mmap_layout(struct mm_struct *mm);
 
 #endif /* !CONFIG_IA32_SUPPORT */
 
-#endif
+#endif /* ASM_X86__IA32_H */
diff --git a/include/asm-x86/ia32_unistd.h b/include/asm-x86/ia32_unistd.h
index 61cea9e7c5c1..dbd887d8a5a5 100644
--- a/include/asm-x86/ia32_unistd.h
+++ b/include/asm-x86/ia32_unistd.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_IA32_UNISTD_H_
-#define _ASM_X86_64_IA32_UNISTD_H_
+#ifndef ASM_X86__IA32_UNISTD_H
+#define ASM_X86__IA32_UNISTD_H
 
 /*
  * This file contains the system call numbers of the ia32 port,
@@ -15,4 +15,4 @@
 #define __NR_ia32_sigreturn     119
 #define __NR_ia32_rt_sigreturn  173
 
-#endif /* _ASM_X86_64_IA32_UNISTD_H_ */
+#endif /* ASM_X86__IA32_UNISTD_H */
diff --git a/include/asm-x86/idle.h b/include/asm-x86/idle.h
index d240e5b30a45..baa3f783d27d 100644
--- a/include/asm-x86/idle.h
+++ b/include/asm-x86/idle.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_IDLE_H
-#define _ASM_X86_64_IDLE_H 1
+#ifndef ASM_X86__IDLE_H
+#define ASM_X86__IDLE_H
 
 #define IDLE_START 1
 #define IDLE_END 2
@@ -10,4 +10,6 @@ void idle_notifier_register(struct notifier_block *n);
 void enter_idle(void);
 void exit_idle(void);
 
-#endif
+void c1e_remove_cpu(int cpu);
+
+#endif /* ASM_X86__IDLE_H */
diff --git a/include/asm-x86/intel_arch_perfmon.h b/include/asm-x86/intel_arch_perfmon.h
index fa0fd068bc2e..07c03c6c9a16 100644
--- a/include/asm-x86/intel_arch_perfmon.h
+++ b/include/asm-x86/intel_arch_perfmon.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_INTEL_ARCH_PERFMON_H
-#define _ASM_X86_INTEL_ARCH_PERFMON_H
+#ifndef ASM_X86__INTEL_ARCH_PERFMON_H
+#define ASM_X86__INTEL_ARCH_PERFMON_H
 
 #define MSR_ARCH_PERFMON_PERFCTR0               0xc1
 #define MSR_ARCH_PERFMON_PERFCTR1               0xc2
@@ -28,4 +28,4 @@ union cpuid10_eax {
         unsigned int full;
 };
 
-#endif /* _ASM_X86_INTEL_ARCH_PERFMON_H */
+#endif /* ASM_X86__INTEL_ARCH_PERFMON_H */
diff --git a/include/asm-x86/io.h b/include/asm-x86/io.h
index 0f954dc89cb3..a233f835e0b5 100644
--- a/include/asm-x86/io.h
+++ b/include/asm-x86/io.h
@@ -1,24 +1,10 @@
-#ifndef _ASM_X86_IO_H
-#define _ASM_X86_IO_H
+#ifndef ASM_X86__IO_H
+#define ASM_X86__IO_H
 
 #define ARCH_HAS_IOREMAP_WC
 
 #include <linux/compiler.h>
 
-/*
- * early_ioremap() and early_iounmap() are for temporary early boot-time
- * mappings, before the real ioremap() is functional.
- * A boot-time mapping is currently limited to at most 16 pages.
- */
-#ifndef __ASSEMBLY__
-extern void early_ioremap_init(void);
-extern void early_ioremap_clear(void);
-extern void early_ioremap_reset(void);
-extern void *early_ioremap(unsigned long offset, unsigned long size);
-extern void early_iounmap(void *addr, unsigned long size);
-extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
-#endif
-
 #define build_mmio_read(name, size, type, reg, barrier) \
 static inline type name(const volatile void __iomem *addr) \
 { type ret; asm volatile("mov" size " %1,%0":reg (ret) \
@@ -73,6 +59,8 @@ build_mmio_write(__writeq, "q", unsigned long, "r", )
 #define writeq writeq
 #endif
 
+extern int iommu_bio_merge;
+
 #ifdef CONFIG_X86_32
 # include "io_32.h"
 #else
@@ -95,8 +83,9 @@ extern void early_ioremap_init(void);
 extern void early_ioremap_clear(void);
 extern void early_ioremap_reset(void);
 extern void *early_ioremap(unsigned long offset, unsigned long size);
+extern void *early_memremap(unsigned long offset, unsigned long size);
 extern void early_iounmap(void *addr, unsigned long size);
 extern void __iomem *fix_ioremap(unsigned idx, unsigned long phys);
 
 
-#endif /* _ASM_X86_IO_H */
+#endif /* ASM_X86__IO_H */
diff --git a/include/asm-x86/io_32.h b/include/asm-x86/io_32.h
index e876d89ac156..4f7d878bda18 100644
--- a/include/asm-x86/io_32.h
+++ b/include/asm-x86/io_32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
+#ifndef ASM_X86__IO_32_H
+#define ASM_X86__IO_32_H
 
 #include <linux/string.h>
 #include <linux/compiler.h>
@@ -281,4 +281,4 @@ BUILDIO(b, b, char)
 BUILDIO(w, w, short)
 BUILDIO(l, , int)
 
-#endif
+#endif /* ASM_X86__IO_32_H */
diff --git a/include/asm-x86/io_64.h b/include/asm-x86/io_64.h
index 22995c5c5adc..ee6e086b7dfe 100644
--- a/include/asm-x86/io_64.h
+++ b/include/asm-x86/io_64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_IO_H
-#define _ASM_IO_H
+#ifndef ASM_X86__IO_64_H
+#define ASM_X86__IO_64_H
 
 
 /*
@@ -165,9 +165,6 @@ static inline void *phys_to_virt(unsigned long address)
 
 #include <asm-generic/iomap.h>
 
-extern void *early_ioremap(unsigned long addr, unsigned long size);
-extern void early_iounmap(void *addr, unsigned long size);
-
 /*
  * This one maps high address device memory and turns off caching for that area.
  * it's useful if some control registers are in such an area and write combining
@@ -235,7 +232,6 @@ void memset_io(volatile void __iomem *a, int b, size_t c);
 
 #define flush_write_buffers()
 
-extern int iommu_bio_merge;
 #define BIO_VMERGE_BOUNDARY iommu_bio_merge
 
 /*
@@ -245,4 +241,4 @@ extern int iommu_bio_merge;
 
 #endif /* __KERNEL__ */
 
-#endif
+#endif /* ASM_X86__IO_64_H */
diff --git a/include/asm-x86/io_apic.h b/include/asm-x86/io_apic.h
index 14f82bbcb5fd..8ec68a50cf10 100644
--- a/include/asm-x86/io_apic.h
+++ b/include/asm-x86/io_apic.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_IO_APIC_H
-#define __ASM_IO_APIC_H
+#ifndef ASM_X86__IO_APIC_H
+#define ASM_X86__IO_APIC_H
 
 #include <linux/types.h>
 #include <asm/mpspec.h>
@@ -107,6 +107,20 @@ struct IO_APIC_route_entry {
 
 } __attribute__ ((packed));
 
+struct IR_IO_APIC_route_entry {
+        __u64   vector          : 8,
+                zero            : 3,
+                index2          : 1,
+                delivery_status : 1,
+                polarity        : 1,
+                irr             : 1,
+                trigger         : 1,
+                mask            : 1,
+                reserved        : 31,
+                format          : 1,
+                index           : 15;
+} __attribute__ ((packed));
+
 #ifdef CONFIG_X86_IO_APIC
 
 /*
@@ -183,10 +197,16 @@ extern int io_apic_set_pci_routing(int ioapic, int pin, int irq,
 extern int (*ioapic_renumber_irq)(int ioapic, int irq);
 extern void ioapic_init_mappings(void);
 
+#ifdef CONFIG_X86_64
+extern int save_mask_IO_APIC_setup(void);
+extern void restore_IO_APIC_setup(void);
+extern void reinit_intr_remapped_IO_APIC(int);
+#endif
+
 #else  /* !CONFIG_X86_IO_APIC */
 #define io_apic_assign_pci_irqs 0
 static const int timer_through_8259 = 0;
 static inline void ioapic_init_mappings(void) { }
 #endif
 
-#endif
+#endif /* ASM_X86__IO_APIC_H */
diff --git a/include/asm-x86/ioctls.h b/include/asm-x86/ioctls.h
index c0c338bd4068..06752a649044 100644
--- a/include/asm-x86/ioctls.h
+++ b/include/asm-x86/ioctls.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_IOCTLS_H
-#define _ASM_X86_IOCTLS_H
+#ifndef ASM_X86__IOCTLS_H
+#define ASM_X86__IOCTLS_H
 
 #include <asm/ioctl.h>
 
@@ -51,9 +51,15 @@
 #define TCSETS2         _IOW('T', 0x2B, struct termios2)
 #define TCSETSW2        _IOW('T', 0x2C, struct termios2)
 #define TCSETSF2        _IOW('T', 0x2D, struct termios2)
+#define TIOCGRS485      0x542E
+#define TIOCSRS485      0x542F
 #define TIOCGPTN        _IOR('T', 0x30, unsigned int)
                                 /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T', 0x31, int)  /* Lock/unlock Pty */
+#define TCGETX          0x5432 /* SYS5 TCGETX compatibility */
+#define TCSETX          0x5433
+#define TCSETXF         0x5434
+#define TCSETXW         0x5435
 
 #define FIONCLEX        0x5450
 #define FIOCLEX         0x5451
@@ -85,4 +91,4 @@
 
 #define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
 
-#endif
+#endif /* ASM_X86__IOCTLS_H */
diff --git a/include/asm-x86/iommu.h b/include/asm-x86/iommu.h
index 5f888cc5be49..961e746da977 100644
--- a/include/asm-x86/iommu.h
+++ b/include/asm-x86/iommu.h
@@ -1,13 +1,14 @@
-#ifndef _ASM_X8664_IOMMU_H
-#define _ASM_X8664_IOMMU_H 1
+#ifndef ASM_X86__IOMMU_H
+#define ASM_X86__IOMMU_H
 
 extern void pci_iommu_shutdown(void);
 extern void no_iommu_init(void);
 extern struct dma_mapping_ops nommu_dma_ops;
 extern int force_iommu, no_iommu;
 extern int iommu_detected;
+extern int dmar_disabled;
 
-extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len);
+extern unsigned long iommu_nr_pages(unsigned long addr, unsigned long len);
 
 #ifdef CONFIG_GART_IOMMU
 extern int gart_iommu_aperture;
@@ -42,4 +43,4 @@ static inline void gart_iommu_hole_init(void)
 }
 #endif
 
-#endif
+#endif /* ASM_X86__IOMMU_H */
diff --git a/include/asm-x86/ipcbuf.h b/include/asm-x86/ipcbuf.h
index ee678fd51594..910304fbdc8f 100644
--- a/include/asm-x86/ipcbuf.h
+++ b/include/asm-x86/ipcbuf.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_IPCBUF_H
-#define _ASM_X86_IPCBUF_H
+#ifndef ASM_X86__IPCBUF_H
+#define ASM_X86__IPCBUF_H
 
 /*
  * The ipc64_perm structure for x86 architecture.
@@ -25,4 +25,4 @@ struct ipc64_perm {
         unsigned long           __unused2;
 };
 
-#endif /* _ASM_X86_IPCBUF_H */
+#endif /* ASM_X86__IPCBUF_H */
diff --git a/include/asm-x86/ipi.h b/include/asm-x86/ipi.h
index bb1c09f7a76c..30a692cfaff8 100644
--- a/include/asm-x86/ipi.h
+++ b/include/asm-x86/ipi.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_IPI_H
-#define __ASM_IPI_H
+#ifndef ASM_X86__IPI_H
+#define ASM_X86__IPI_H
 
 /*
  * Copyright 2004 James Cleverdon, IBM.
@@ -49,6 +49,12 @@ static inline int __prepare_ICR2(unsigned int mask)
         return SET_APIC_DEST_FIELD(mask);
 }
 
+static inline void __xapic_wait_icr_idle(void)
+{
+        while (native_apic_mem_read(APIC_ICR) & APIC_ICR_BUSY)
+                cpu_relax();
+}
+
 static inline void __send_IPI_shortcut(unsigned int shortcut, int vector,
                                        unsigned int dest)
 {
@@ -64,7 +70,7 @@ static inline void __send_IPI_shortcut(unsigned int shortcut, int vector,
         /*
          * Wait for idle.
          */
-        apic_wait_icr_idle();
+        __xapic_wait_icr_idle();
 
         /*
          * No need to touch the target chip field
@@ -74,7 +80,7 @@ static inline void __send_IPI_shortcut(unsigned int shortcut, int vector,
         /*
          * Send the IPI. The write to APIC_ICR fires this off.
          */
-        apic_write(APIC_ICR, cfg);
+        native_apic_mem_write(APIC_ICR, cfg);
 }
 
 /*
@@ -92,13 +98,13 @@ static inline void __send_IPI_dest_field(unsigned int mask, int vector,
         if (unlikely(vector == NMI_VECTOR))
                 safe_apic_wait_icr_idle();
         else
-                apic_wait_icr_idle();
+                __xapic_wait_icr_idle();
 
         /*
          * prepare target chip field
          */
         cfg = __prepare_ICR2(mask);
-        apic_write(APIC_ICR2, cfg);
+        native_apic_mem_write(APIC_ICR2, cfg);
 
         /*
          * program the ICR
@@ -108,7 +114,7 @@ static inline void __send_IPI_dest_field(unsigned int mask, int vector,
         /*
          * Send the IPI. The write to APIC_ICR fires this off.
          */
-        apic_write(APIC_ICR, cfg);
+        native_apic_mem_write(APIC_ICR, cfg);
 }
 
 static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
@@ -129,4 +135,4 @@ static inline void send_IPI_mask_sequence(cpumask_t mask, int vector)
         local_irq_restore(flags);
 }
 
-#endif /* __ASM_IPI_H */
+#endif /* ASM_X86__IPI_H */
diff --git a/include/asm-x86/irq.h b/include/asm-x86/irq.h
index 1a2925757317..1e5f2909c1db 100644
--- a/include/asm-x86/irq.h
+++ b/include/asm-x86/irq.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_IRQ_H
-#define _ASM_IRQ_H
+#ifndef ASM_X86__IRQ_H
+#define ASM_X86__IRQ_H
 /*
  *      (C) 1992, 1993 Linus Torvalds, (C) 1997 Ingo Molnar
  *
@@ -47,4 +47,4 @@ extern void native_init_IRQ(void);
 /* Interrupt vector management */
 extern DECLARE_BITMAP(used_vectors, NR_VECTORS);
 
-#endif /* _ASM_IRQ_H */
+#endif /* ASM_X86__IRQ_H */
diff --git a/include/asm-x86/irq_regs_32.h b/include/asm-x86/irq_regs_32.h
index 3368b20c0b48..316a3b258871 100644
--- a/include/asm-x86/irq_regs_32.h
+++ b/include/asm-x86/irq_regs_32.h
@@ -4,8 +4,8 @@
  *
  * Jeremy Fitzhardinge <jeremy@goop.org>
  */
-#ifndef _ASM_I386_IRQ_REGS_H
-#define _ASM_I386_IRQ_REGS_H
+#ifndef ASM_X86__IRQ_REGS_32_H
+#define ASM_X86__IRQ_REGS_32_H
 
 #include <asm/percpu.h>
 
@@ -26,4 +26,4 @@ static inline struct pt_regs *set_irq_regs(struct pt_regs *new_regs)
         return old_regs;
 }
 
-#endif /* _ASM_I386_IRQ_REGS_H */
+#endif /* ASM_X86__IRQ_REGS_32_H */
diff --git a/include/asm-x86/irq_remapping.h b/include/asm-x86/irq_remapping.h
new file mode 100644
index 000000000000..78242c6ffa58
--- /dev/null
+++ b/include/asm-x86/irq_remapping.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_IRQ_REMAPPING_H
+#define _ASM_IRQ_REMAPPING_H
+
+extern int x2apic;
+
+#define IRTE_DEST(dest) ((x2apic) ? dest : dest << 8)
+
+#endif
diff --git a/include/asm-x86/irq_vectors.h b/include/asm-x86/irq_vectors.h
index b95d167b7fb2..c5d2d767a1f3 100644
--- a/include/asm-x86/irq_vectors.h
+++ b/include/asm-x86/irq_vectors.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_IRQ_VECTORS_H
-#define _ASM_IRQ_VECTORS_H
+#ifndef ASM_X86__IRQ_VECTORS_H
+#define ASM_X86__IRQ_VECTORS_H
 
 #include <linux/threads.h>
 
@@ -76,6 +76,7 @@
 #define CALL_FUNCTION_SINGLE_VECTOR     0xfb
 #define THERMAL_APIC_VECTOR             0xfa
 #define THRESHOLD_APIC_VECTOR           0xf9
+#define UV_BAU_MESSAGE                  0xf8
 #define INVALIDATE_TLB_VECTOR_END       0xf7
 #define INVALIDATE_TLB_VECTOR_START     0xf0    /* f0-f7 used for TLB flush */
 
@@ -178,4 +179,4 @@
 #define VIC_CPU_BOOT_ERRATA_CPI         (VIC_CPI_LEVEL0 + 8)
 
 
-#endif /* _ASM_IRQ_VECTORS_H */
+#endif /* ASM_X86__IRQ_VECTORS_H */
diff --git a/include/asm-x86/irqflags.h b/include/asm-x86/irqflags.h
index 424acb48cd61..2bdab21f0898 100644
--- a/include/asm-x86/irqflags.h
+++ b/include/asm-x86/irqflags.h
@@ -166,27 +166,6 @@ static inline int raw_irqs_disabled(void)
         return raw_irqs_disabled_flags(flags);
 }
 
-/*
- * makes the traced hardirq state match with the machine state
- *
- * should be a rarely used function, only in places where its
- * otherwise impossible to know the irq state, like in traps.
- */
-static inline void trace_hardirqs_fixup_flags(unsigned long flags)
-{
-        if (raw_irqs_disabled_flags(flags))
-                trace_hardirqs_off();
-        else
-                trace_hardirqs_on();
-}
-
-static inline void trace_hardirqs_fixup(void)
-{
-        unsigned long flags = __raw_local_save_flags();
-
-        trace_hardirqs_fixup_flags(flags);
-}
-
 #else
 
 #ifdef CONFIG_X86_64
diff --git a/include/asm-x86/ist.h b/include/asm-x86/ist.h
index 6ec6ceed95a7..35a2fe9bc921 100644
--- a/include/asm-x86/ist.h
+++ b/include/asm-x86/ist.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_IST_H
-#define _ASM_IST_H
+#ifndef ASM_X86__IST_H
+#define ASM_X86__IST_H
 
 /*
  * Include file for the interface to IST BIOS
@@ -31,4 +31,4 @@ struct ist_info {
 extern struct ist_info ist_info;
 
 #endif  /* __KERNEL__ */
-#endif  /* _ASM_IST_H */
+#endif /* ASM_X86__IST_H */
diff --git a/include/asm-x86/k8.h b/include/asm-x86/k8.h
index 452e2b696ff4..2bbaf4370a55 100644
--- a/include/asm-x86/k8.h
+++ b/include/asm-x86/k8.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_K8_H
-#define _ASM_K8_H 1
+#ifndef ASM_X86__K8_H
+#define ASM_X86__K8_H
 
 #include <linux/pci.h>
 
@@ -12,4 +12,4 @@ extern int cache_k8_northbridges(void);
 extern void k8_flush_garts(void);
 extern int k8_scan_nodes(unsigned long start, unsigned long end);
 
-#endif
+#endif /* ASM_X86__K8_H */
diff --git a/include/asm-x86/kdebug.h b/include/asm-x86/kdebug.h
index 96651bb59ba1..fbbab66ee9df 100644
--- a/include/asm-x86/kdebug.h
+++ b/include/asm-x86/kdebug.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_KDEBUG_H
-#define _ASM_X86_KDEBUG_H
+#ifndef ASM_X86__KDEBUG_H
+#define ASM_X86__KDEBUG_H
 
 #include <linux/notifier.h>
 
@@ -27,12 +27,11 @@ extern void printk_address(unsigned long address, int reliable);
 extern void die(const char *, struct pt_regs *,long);
 extern int __must_check __die(const char *, struct pt_regs *, long);
 extern void show_registers(struct pt_regs *regs);
-extern void __show_registers(struct pt_regs *, int all);
 extern void show_trace(struct task_struct *t, struct pt_regs *regs,
                        unsigned long *sp, unsigned long bp);
-extern void __show_regs(struct pt_regs *regs);
+extern void __show_regs(struct pt_regs *regs, int all);
 extern void show_regs(struct pt_regs *regs);
 extern unsigned long oops_begin(void);
 extern void oops_end(unsigned long, struct pt_regs *, int signr);
 
-#endif
+#endif /* ASM_X86__KDEBUG_H */
diff --git a/include/asm-x86/kexec.h b/include/asm-x86/kexec.h
index 4246ab7dc988..ea09600d6129 100644
--- a/include/asm-x86/kexec.h
+++ b/include/asm-x86/kexec.h
@@ -1,5 +1,5 @@
-#ifndef _KEXEC_H
-#define _KEXEC_H
+#ifndef ASM_X86__KEXEC_H
+#define ASM_X86__KEXEC_H
 
 #ifdef CONFIG_X86_32
 # define PA_CONTROL_PAGE        0
@@ -172,4 +172,4 @@ relocate_kernel(unsigned long indirection_page,
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* _KEXEC_H */
+#endif /* ASM_X86__KEXEC_H */
diff --git a/include/asm-x86/kgdb.h b/include/asm-x86/kgdb.h
index 484c47554f3b..d283863354de 100644
--- a/include/asm-x86/kgdb.h
+++ b/include/asm-x86/kgdb.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_KGDB_H_
-#define _ASM_KGDB_H_
+#ifndef ASM_X86__KGDB_H
+#define ASM_X86__KGDB_H
 
 /*
  * Copyright (C) 2001-2004 Amit S. Kale
@@ -39,12 +39,13 @@ enum regnames {
         GDB_FS,                 /* 14 */
         GDB_GS,                 /* 15 */
 };
+#define NUMREGBYTES             ((GDB_GS+1)*4)
 #else /* ! CONFIG_X86_32 */
-enum regnames {
+enum regnames64 {
         GDB_AX,                 /* 0 */
-        GDB_DX,                 /* 1 */
+        GDB_BX,                 /* 1 */
         GDB_CX,                 /* 2 */
-        GDB_BX,                 /* 3 */
+        GDB_DX,                 /* 3 */
         GDB_SI,                 /* 4 */
         GDB_DI,                 /* 5 */
         GDB_BP,                 /* 6 */
@@ -58,18 +59,15 @@ enum regnames {
         GDB_R14,                /* 14 */
         GDB_R15,                /* 15 */
         GDB_PC,                 /* 16 */
-        GDB_PS,                 /* 17 */
 };
-#endif /* CONFIG_X86_32 */
 
-/*
- * Number of bytes of registers:
- */
-#ifdef CONFIG_X86_32
-# define NUMREGBYTES            64
-#else
-# define NUMREGBYTES            ((GDB_PS+1)*8)
-#endif
+enum regnames32 {
+        GDB_PS = 34,
+        GDB_CS,
+        GDB_SS,
+};
+#define NUMREGBYTES             ((GDB_SS+1)*4)
+#endif /* CONFIG_X86_32 */
 
 static inline void arch_kgdb_breakpoint(void)
 {
@@ -78,4 +76,4 @@ static inline void arch_kgdb_breakpoint(void)
 #define BREAK_INSTR_SIZE        1
 #define CACHE_FLUSH_IS_SAFE     1
 
-#endif                          /* _ASM_KGDB_H_ */
+#endif /* ASM_X86__KGDB_H */
diff --git a/include/asm-x86/kmap_types.h b/include/asm-x86/kmap_types.h
index 5f4174132a22..89f44493e643 100644
--- a/include/asm-x86/kmap_types.h
+++ b/include/asm-x86/kmap_types.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_KMAP_TYPES_H
-#define _ASM_X86_KMAP_TYPES_H
+#ifndef ASM_X86__KMAP_TYPES_H
+#define ASM_X86__KMAP_TYPES_H
 
 #if defined(CONFIG_X86_32) && defined(CONFIG_DEBUG_HIGHMEM)
 # define D(n) __KM_FENCE_##n ,
@@ -26,4 +26,4 @@ D(13)	KM_TYPE_NR
 
 #undef D
 
-#endif
+#endif /* ASM_X86__KMAP_TYPES_H */
diff --git a/include/asm-x86/kprobes.h b/include/asm-x86/kprobes.h
index 54980b0b3892..8a0748d01036 100644
--- a/include/asm-x86/kprobes.h
+++ b/include/asm-x86/kprobes.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_KPROBES_H
-#define _ASM_KPROBES_H
+#ifndef ASM_X86__KPROBES_H
+#define ASM_X86__KPROBES_H
 /*
  *  Kernel Probes (KProbes)
  *
@@ -82,16 +82,7 @@ struct kprobe_ctlblk {
         struct prev_kprobe prev_kprobe;
 };
 
-/* trap3/1 are intr gates for kprobes.  So, restore the status of IF,
- * if necessary, before executing the original int3/1 (trap) handler.
- */
-static inline void restore_interrupts(struct pt_regs *regs)
-{
-        if (regs->flags & X86_EFLAGS_IF)
-                local_irq_enable();
-}
-
 extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
 extern int kprobe_exceptions_notify(struct notifier_block *self,
                                     unsigned long val, void *data);
-#endif                          /* _ASM_KPROBES_H */
+#endif /* ASM_X86__KPROBES_H */
diff --git a/include/asm-x86/kvm.h b/include/asm-x86/kvm.h
index 6f1840812e59..ba0dd791fadf 100644
--- a/include/asm-x86/kvm.h
+++ b/include/asm-x86/kvm.h
@@ -1,5 +1,5 @@
-#ifndef __LINUX_KVM_X86_H
-#define __LINUX_KVM_X86_H
+#ifndef ASM_X86__KVM_H
+#define ASM_X86__KVM_H
 
 /*
  * KVM x86 specific structures and definitions
@@ -208,26 +208,4 @@ struct kvm_pit_channel_state {
 struct kvm_pit_state {
         struct kvm_pit_channel_state channels[3];
 };
-
-#define KVM_TRC_INJ_VIRQ         (KVM_TRC_HANDLER + 0x02)
-#define KVM_TRC_REDELIVER_EVT    (KVM_TRC_HANDLER + 0x03)
-#define KVM_TRC_PEND_INTR        (KVM_TRC_HANDLER + 0x04)
-#define KVM_TRC_IO_READ          (KVM_TRC_HANDLER + 0x05)
-#define KVM_TRC_IO_WRITE         (KVM_TRC_HANDLER + 0x06)
-#define KVM_TRC_CR_READ          (KVM_TRC_HANDLER + 0x07)
-#define KVM_TRC_CR_WRITE         (KVM_TRC_HANDLER + 0x08)
-#define KVM_TRC_DR_READ          (KVM_TRC_HANDLER + 0x09)
-#define KVM_TRC_DR_WRITE         (KVM_TRC_HANDLER + 0x0A)
-#define KVM_TRC_MSR_READ         (KVM_TRC_HANDLER + 0x0B)
-#define KVM_TRC_MSR_WRITE        (KVM_TRC_HANDLER + 0x0C)
-#define KVM_TRC_CPUID            (KVM_TRC_HANDLER + 0x0D)
-#define KVM_TRC_INTR             (KVM_TRC_HANDLER + 0x0E)
-#define KVM_TRC_NMI              (KVM_TRC_HANDLER + 0x0F)
-#define KVM_TRC_VMMCALL          (KVM_TRC_HANDLER + 0x10)
-#define KVM_TRC_HLT              (KVM_TRC_HANDLER + 0x11)
-#define KVM_TRC_CLTS             (KVM_TRC_HANDLER + 0x12)
-#define KVM_TRC_LMSW             (KVM_TRC_HANDLER + 0x13)
-#define KVM_TRC_APIC_ACCESS      (KVM_TRC_HANDLER + 0x14)
-#define KVM_TRC_TDP_FAULT        (KVM_TRC_HANDLER + 0x15)
-
-#endif
+#endif /* ASM_X86__KVM_H */
diff --git a/include/asm-x86/kvm_host.h b/include/asm-x86/kvm_host.h
index 0f3c53114614..411fb8cfb24e 100644
--- a/include/asm-x86/kvm_host.h
+++ b/include/asm-x86/kvm_host.h
@@ -1,4 +1,4 @@
-#/*
+/*
  * Kernel-based Virtual Machine driver for Linux
  *
  * This header defines architecture specific interfaces, x86 version
@@ -8,8 +8,8 @@
  *
  */
 
-#ifndef ASM_KVM_HOST_H
-#define ASM_KVM_HOST_H
+#ifndef ASM_X86__KVM_HOST_H
+#define ASM_X86__KVM_HOST_H
 
 #include <linux/types.h>
 #include <linux/mm.h>
@@ -57,6 +57,10 @@
 #define KVM_PAGES_PER_HPAGE (KVM_HPAGE_SIZE / PAGE_SIZE)
 
 #define DE_VECTOR 0
+#define DB_VECTOR 1
+#define BP_VECTOR 3
+#define OF_VECTOR 4
+#define BR_VECTOR 5
 #define UD_VECTOR 6
 #define NM_VECTOR 7
 #define DF_VECTOR 8
@@ -65,6 +69,7 @@
 #define SS_VECTOR 12
 #define GP_VECTOR 13
 #define PF_VECTOR 14
+#define MF_VECTOR 16
 #define MC_VECTOR 18
 
 #define SELECTOR_TI_MASK (1 << 2)
@@ -89,7 +94,7 @@ extern struct list_head vm_list;
 struct kvm_vcpu;
 struct kvm;
 
-enum {
+enum kvm_reg {
         VCPU_REGS_RAX = 0,
         VCPU_REGS_RCX = 1,
         VCPU_REGS_RDX = 2,
@@ -108,6 +113,7 @@ enum {
         VCPU_REGS_R14 = 14,
         VCPU_REGS_R15 = 15,
 #endif
+        VCPU_REGS_RIP,
         NR_VCPU_REGS
 };
 
@@ -189,10 +195,20 @@ struct kvm_mmu_page {
                                     */
         int multimapped;         /* More than one parent_pte? */
         int root_count;          /* Currently serving as active root */
+        bool unsync;
+        bool unsync_children;
         union {
                 u64 *parent_pte;               /* !multimapped */
                 struct hlist_head parent_ptes; /* multimapped, kvm_pte_chain */
         };
+        DECLARE_BITMAP(unsync_child_bitmap, 512);
+};
+
+struct kvm_pv_mmu_op_buffer {
+        void *ptr;
+        unsigned len;
+        unsigned processed;
+        char buf[512] __aligned(sizeof(long));
 };
 
 /*
@@ -207,6 +223,9 @@ struct kvm_mmu {
         gpa_t (*gva_to_gpa)(struct kvm_vcpu *vcpu, gva_t gva);
         void (*prefetch_page)(struct kvm_vcpu *vcpu,
                               struct kvm_mmu_page *page);
+        int (*sync_page)(struct kvm_vcpu *vcpu,
+                         struct kvm_mmu_page *sp);
+        void (*invlpg)(struct kvm_vcpu *vcpu, gva_t gva);
         hpa_t root_hpa;
         int root_level;
         int shadow_root_level;
@@ -219,8 +238,13 @@ struct kvm_vcpu_arch {
         int interrupt_window_open;
         unsigned long irq_summary; /* bit vector: 1 per word in irq_pending */
         DECLARE_BITMAP(irq_pending, KVM_NR_INTERRUPTS);
-        unsigned long regs[NR_VCPU_REGS]; /* for rsp: vcpu_load_rsp_rip() */
-        unsigned long rip;      /* needs vcpu_load_rsp_rip() */
+        /*
+         * rip and regs accesses must go through
+         * kvm_{register,rip}_{read,write} functions.
+         */
+        unsigned long regs[NR_VCPU_REGS];
+        u32 regs_avail;
+        u32 regs_dirty;
 
         unsigned long cr0;
         unsigned long cr2;
@@ -237,6 +261,9 @@ struct kvm_vcpu_arch {
         bool tpr_access_reporting;
 
         struct kvm_mmu mmu;
+        /* only needed in kvm_pv_mmu_op() path, but it's hot so
+         * put it here to avoid allocation */
+        struct kvm_pv_mmu_op_buffer mmu_op_buffer;
 
         struct kvm_mmu_memory_cache mmu_pte_chain_cache;
         struct kvm_mmu_memory_cache mmu_rmap_desc_cache;
@@ -269,6 +296,11 @@ struct kvm_vcpu_arch {
                 u32 error_code;
         } exception;
 
+        struct kvm_queued_interrupt {
+                bool pending;
+                u8 nr;
+        } interrupt;
+
         struct {
                 int active;
                 u8 save_iopl;
@@ -294,6 +326,7 @@ struct kvm_vcpu_arch {
         struct page *time_page;
 
         bool nmi_pending;
+        bool nmi_injected;
 
         u64 mtrr[0x100];
 };
@@ -316,9 +349,12 @@ struct kvm_arch{
          * Hash table of struct kvm_mmu_page.
          */
         struct list_head active_mmu_pages;
+        struct list_head assigned_dev_head;
+        struct dmar_domain *intel_iommu_domain;
         struct kvm_pic *vpic;
         struct kvm_ioapic *vioapic;
         struct kvm_pit *vpit;
+        struct hlist_head irq_ack_notifier_list;
 
         int round_robin_prev_vcpu;
         unsigned int tss_addr;
@@ -338,6 +374,7 @@ struct kvm_vm_stat {
         u32 mmu_flooded;
         u32 mmu_recycled;
         u32 mmu_cache_miss;
+        u32 mmu_unsync;
         u32 remote_tlb_flush;
         u32 lpages;
 };
@@ -364,6 +401,7 @@ struct kvm_vcpu_stat {
         u32 insn_emulation;
         u32 insn_emulation_fail;
         u32 hypercalls;
+        u32 irq_injections;
 };
 
 struct descriptor_table {
@@ -414,8 +452,7 @@ struct kvm_x86_ops {
         unsigned long (*get_dr)(struct kvm_vcpu *vcpu, int dr);
         void (*set_dr)(struct kvm_vcpu *vcpu, int dr, unsigned long value,
                        int *exception);
-        void (*cache_regs)(struct kvm_vcpu *vcpu);
-        void (*decache_regs)(struct kvm_vcpu *vcpu);
+        void (*cache_reg)(struct kvm_vcpu *vcpu, enum kvm_reg reg);
         unsigned long (*get_rflags)(struct kvm_vcpu *vcpu);
         void (*set_rflags)(struct kvm_vcpu *vcpu, unsigned long rflags);
 
@@ -528,6 +565,8 @@ void kvm_queue_exception_e(struct kvm_vcpu *vcpu, unsigned nr, u32 error_code);
 void kvm_inject_page_fault(struct kvm_vcpu *vcpu, unsigned long cr2,
                            u32 error_code);
 
+void kvm_pic_set_irq(void *opaque, int irq, int level);
+
 void kvm_inject_nmi(struct kvm_vcpu *vcpu);
 
 void fx_init(struct kvm_vcpu *vcpu);
@@ -550,12 +589,14 @@ int kvm_mmu_unprotect_page_virt(struct kvm_vcpu *vcpu, gva_t gva);
 void __kvm_mmu_free_some_pages(struct kvm_vcpu *vcpu);
 int kvm_mmu_load(struct kvm_vcpu *vcpu);
 void kvm_mmu_unload(struct kvm_vcpu *vcpu);
+void kvm_mmu_sync_roots(struct kvm_vcpu *vcpu);
 
 int kvm_emulate_hypercall(struct kvm_vcpu *vcpu);
 
 int kvm_fix_hypercall(struct kvm_vcpu *vcpu);
 
 int kvm_mmu_page_fault(struct kvm_vcpu *vcpu, gva_t gva, u32 error_code);
+void kvm_mmu_invlpg(struct kvm_vcpu *vcpu, gva_t gva);
 
 void kvm_enable_tdp(void);
 void kvm_disable_tdp(void);
@@ -686,33 +727,6 @@ enum {
         TASK_SWITCH_GATE = 3,
 };
 
-#define KVMTRACE_5D(evt, vcpu, d1, d2, d3, d4, d5, name) \
-        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-                                                vcpu, 5, d1, d2, d3, d4, d5)
-#define KVMTRACE_4D(evt, vcpu, d1, d2, d3, d4, name) \
-        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-                                                vcpu, 4, d1, d2, d3, d4, 0)
-#define KVMTRACE_3D(evt, vcpu, d1, d2, d3, name) \
-        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-                                                vcpu, 3, d1, d2, d3, 0, 0)
-#define KVMTRACE_2D(evt, vcpu, d1, d2, name) \
-        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-                                                vcpu, 2, d1, d2, 0, 0, 0)
-#define KVMTRACE_1D(evt, vcpu, d1, name) \
-        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-                                                vcpu, 1, d1, 0, 0, 0, 0)
-#define KVMTRACE_0D(evt, vcpu, name) \
-        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
-                                                vcpu, 0, 0, 0, 0, 0, 0)
-
-#ifdef CONFIG_64BIT
-# define KVM_EX_ENTRY ".quad"
-# define KVM_EX_PUSH "pushq"
-#else
-# define KVM_EX_ENTRY ".long"
-# define KVM_EX_PUSH "pushl"
-#endif
-
 /*
  * Hardware virtualization extension instructions may fault if a
  * reboot turns off virtualization while processes are running.
@@ -722,17 +736,17 @@ asmlinkage void kvm_handle_fault_on_reboot(void);
 
 #define __kvm_handle_fault_on_reboot(insn) \
         "666: " insn "\n\t" \
-        ".pushsection .text.fixup, \"ax\" \n" \
+        ".pushsection .fixup, \"ax\" \n" \
         "667: \n\t" \
-        KVM_EX_PUSH " $666b \n\t" \
+        __ASM_SIZE(push) " $666b \n\t"        \
         "jmp kvm_handle_fault_on_reboot \n\t" \
         ".popsection \n\t" \
         ".pushsection __ex_table, \"a\" \n\t" \
-        KVM_EX_ENTRY " 666b, 667b \n\t" \
+        _ASM_PTR " 666b, 667b \n\t" \
         ".popsection"
 
 #define KVM_ARCH_WANT_MMU_NOTIFIER
 int kvm_unmap_hva(struct kvm *kvm, unsigned long hva);
 int kvm_age_hva(struct kvm *kvm, unsigned long hva);
 
-#endif
+#endif /* ASM_X86__KVM_HOST_H */
diff --git a/include/asm-x86/kvm_para.h b/include/asm-x86/kvm_para.h
index 76f392146daa..30054fded4fb 100644
--- a/include/asm-x86/kvm_para.h
+++ b/include/asm-x86/kvm_para.h
@@ -1,5 +1,5 @@
-#ifndef __X86_KVM_PARA_H
-#define __X86_KVM_PARA_H
+#ifndef ASM_X86__KVM_PARA_H
+#define ASM_X86__KVM_PARA_H
 
 /* This CPUID returns the signature 'KVMKVMKVM' in ebx, ecx, and edx.  It
  * should be used to determine that a VM is running under KVM.
@@ -144,4 +144,4 @@ static inline unsigned int kvm_arch_para_features(void)
 
 #endif
 
-#endif
+#endif /* ASM_X86__KVM_PARA_H */
diff --git a/include/asm-x86/kvm_x86_emulate.h b/include/asm-x86/kvm_x86_emulate.h
index 4e8c1e48d91d..e2d9b030c1ac 100644
--- a/include/asm-x86/kvm_x86_emulate.h
+++ b/include/asm-x86/kvm_x86_emulate.h
@@ -8,8 +8,8 @@
  * From: xen-unstable 10676:af9809f51f81a3c43f276f00c81a52ef558afda4
  */
 
-#ifndef __X86_EMULATE_H__
-#define __X86_EMULATE_H__
+#ifndef ASM_X86__KVM_X86_EMULATE_H
+#define ASM_X86__KVM_X86_EMULATE_H
 
 struct x86_emulate_ctxt;
 
@@ -181,4 +181,4 @@ int x86_decode_insn(struct x86_emulate_ctxt *ctxt,
 int x86_emulate_insn(struct x86_emulate_ctxt *ctxt,
                      struct x86_emulate_ops *ops);
 
-#endif                          /* __X86_EMULATE_H__ */
+#endif /* ASM_X86__KVM_X86_EMULATE_H */
diff --git a/include/asm-x86/ldt.h b/include/asm-x86/ldt.h
index 20c597242b53..a5228504d867 100644
--- a/include/asm-x86/ldt.h
+++ b/include/asm-x86/ldt.h
@@ -3,8 +3,8 @@
  *
  * Definitions of structures used with the modify_ldt system call.
  */
-#ifndef _ASM_X86_LDT_H
-#define _ASM_X86_LDT_H
+#ifndef ASM_X86__LDT_H
+#define ASM_X86__LDT_H
 
 /* Maximum number of LDT entries supported. */
 #define LDT_ENTRIES     8192
@@ -37,4 +37,4 @@ struct user_desc {
 #define MODIFY_LDT_CONTENTS_CODE        2
 
 #endif /* !__ASSEMBLY__ */
-#endif
+#endif /* ASM_X86__LDT_H */
diff --git a/include/asm-x86/lguest.h b/include/asm-x86/lguest.h
index be4a7247fa2b..7505e947ed27 100644
--- a/include/asm-x86/lguest.h
+++ b/include/asm-x86/lguest.h
@@ -1,5 +1,5 @@
-#ifndef _X86_LGUEST_H
-#define _X86_LGUEST_H
+#ifndef ASM_X86__LGUEST_H
+#define ASM_X86__LGUEST_H
 
 #define GDT_ENTRY_LGUEST_CS     10
 #define GDT_ENTRY_LGUEST_DS     11
@@ -91,4 +91,4 @@ static inline void lguest_set_ts(void)
 
 #endif /* __ASSEMBLY__ */
 
-#endif
+#endif /* ASM_X86__LGUEST_H */
diff --git a/include/asm-x86/lguest_hcall.h b/include/asm-x86/lguest_hcall.h
index a3241f28e34a..8f034ba4b53e 100644
--- a/include/asm-x86/lguest_hcall.h
+++ b/include/asm-x86/lguest_hcall.h
@@ -1,6 +1,6 @@
 /* Architecture specific portion of the lguest hypercalls */
-#ifndef _X86_LGUEST_HCALL_H
-#define _X86_LGUEST_HCALL_H
+#ifndef ASM_X86__LGUEST_HCALL_H
+#define ASM_X86__LGUEST_HCALL_H
 
 #define LHCALL_FLUSH_ASYNC      0
 #define LHCALL_LGUEST_INIT      1
@@ -68,4 +68,4 @@ struct hcall_args {
 };
 
 #endif /* !__ASSEMBLY__ */
-#endif  /* _I386_LGUEST_HCALL_H */
+#endif /* ASM_X86__LGUEST_HCALL_H */
diff --git a/include/asm-x86/linkage.h b/include/asm-x86/linkage.h
index 64e444f8e85b..42d8b62ee8ab 100644
--- a/include/asm-x86/linkage.h
+++ b/include/asm-x86/linkage.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
+#ifndef ASM_X86__LINKAGE_H
+#define ASM_X86__LINKAGE_H
 
 #undef notrace
 #define notrace __attribute__((no_instrument_function))
@@ -57,5 +57,5 @@
 #define __ALIGN_STR ".align 16,0x90"
 #endif
 
-#endif
+#endif /* ASM_X86__LINKAGE_H */
 
diff --git a/include/asm-x86/local.h b/include/asm-x86/local.h
index 330a72496abd..ae91994fd6c9 100644
--- a/include/asm-x86/local.h
+++ b/include/asm-x86/local.h
@@ -1,5 +1,5 @@
-#ifndef _ARCH_LOCAL_H
-#define _ARCH_LOCAL_H
+#ifndef ASM_X86__LOCAL_H
+#define ASM_X86__LOCAL_H
 
 #include <linux/percpu.h>
 
@@ -232,4 +232,4 @@ static inline long local_sub_return(long i, local_t *l)
 #define __cpu_local_add(i, l)   cpu_local_add((i), (l))
 #define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
 
-#endif /* _ARCH_LOCAL_H */
+#endif /* ASM_X86__LOCAL_H */
diff --git a/include/asm-x86/mach-default/apm.h b/include/asm-x86/mach-default/apm.h
index 989f34c37d32..2aa61b54fbd5 100644
--- a/include/asm-x86/mach-default/apm.h
+++ b/include/asm-x86/mach-default/apm.h
@@ -3,8 +3,8 @@
  *  Split out from apm.c by Osamu Tomita <tomita@cinet.co.jp>
  */
 
-#ifndef _ASM_APM_H
-#define _ASM_APM_H
+#ifndef ASM_X86__MACH_DEFAULT__APM_H
+#define ASM_X86__MACH_DEFAULT__APM_H
 
 #ifdef APM_ZERO_SEGS
 #       define APM_DO_ZERO_SEGS \
@@ -70,4 +70,4 @@ static inline u8 apm_bios_call_simple_asm(u32 func, u32 ebx_in,
         return error;
 }
 
-#endif /* _ASM_APM_H */
+#endif /* ASM_X86__MACH_DEFAULT__APM_H */
diff --git a/include/asm-x86/mach-default/mach_apic.h b/include/asm-x86/mach-default/mach_apic.h
index f3226b9a6b82..2a330a41b3dd 100644
--- a/include/asm-x86/mach-default/mach_apic.h
+++ b/include/asm-x86/mach-default/mach_apic.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_APIC_H
+#define ASM_X86__MACH_DEFAULT__MACH_APIC_H
 
 #ifdef CONFIG_X86_LOCAL_APIC
 
@@ -30,6 +30,8 @@ static inline cpumask_t target_cpus(void)
 #define cpu_mask_to_apicid (genapic->cpu_mask_to_apicid)
 #define phys_pkg_id     (genapic->phys_pkg_id)
 #define vector_allocation_domain    (genapic->vector_allocation_domain)
+#define read_apic_id()  (GET_APIC_ID(apic_read(APIC_ID)))
+#define send_IPI_self (genapic->send_IPI_self)
 extern void setup_apic_routing(void);
 #else
 #define INT_DELIVERY_MODE dest_LowestPrio
@@ -54,7 +56,7 @@ static inline void init_apic_ldr(void)
 
 static inline int apic_id_registered(void)
 {
-        return physid_isset(GET_APIC_ID(read_apic_id()), phys_cpu_present_map);
+        return physid_isset(read_apic_id(), phys_cpu_present_map);
 }
 
 static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
@@ -138,4 +140,4 @@ static inline void enable_apic_mode(void)
 }
 
 #endif /* CONFIG_X86_LOCAL_APIC */
-#endif /* __ASM_MACH_APIC_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_APIC_H */
diff --git a/include/asm-x86/mach-default/mach_apicdef.h b/include/asm-x86/mach-default/mach_apicdef.h
index e4b29ba37de6..0c2d41c41b20 100644
--- a/include/asm-x86/mach-default/mach_apicdef.h
+++ b/include/asm-x86/mach-default/mach_apicdef.h
@@ -1,12 +1,12 @@
-#ifndef __ASM_MACH_APICDEF_H
-#define __ASM_MACH_APICDEF_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_APICDEF_H
+#define ASM_X86__MACH_DEFAULT__MACH_APICDEF_H
 
 #include <asm/apic.h>
 
 #ifdef CONFIG_X86_64
-#define APIC_ID_MASK            (0xFFu<<24)
-#define GET_APIC_ID(x)          (((x)>>24)&0xFFu)
-#define SET_APIC_ID(x)          (((x)<<24))
+#define APIC_ID_MASK            (genapic->apic_id_mask)
+#define GET_APIC_ID(x)          (genapic->get_apic_id(x))
+#define SET_APIC_ID(x)          (genapic->set_apic_id(x))
 #else
 #define         APIC_ID_MASK            (0xF<<24)
 static inline unsigned get_apic_id(unsigned long x) 
@@ -21,4 +21,4 @@ static inline unsigned get_apic_id(unsigned long x)
 #define         GET_APIC_ID(x)  get_apic_id(x)
 #endif
 
-#endif
+#endif /* ASM_X86__MACH_DEFAULT__MACH_APICDEF_H */
diff --git a/include/asm-x86/mach-default/mach_ipi.h b/include/asm-x86/mach-default/mach_ipi.h
index be323364e68f..674bc7e50c35 100644
--- a/include/asm-x86/mach-default/mach_ipi.h
+++ b/include/asm-x86/mach-default/mach_ipi.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_IPI_H
-#define __ASM_MACH_IPI_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_IPI_H
+#define ASM_X86__MACH_DEFAULT__MACH_IPI_H
 
 /* Avoid include hell */
 #define NMI_VECTOR 0x02
@@ -61,4 +61,4 @@ static inline void send_IPI_all(int vector)
 }
 #endif
 
-#endif /* __ASM_MACH_IPI_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_IPI_H */
diff --git a/include/asm-x86/mach-default/mach_mpparse.h b/include/asm-x86/mach-default/mach_mpparse.h
index d14108505bb8..9c381f2815ac 100644
--- a/include/asm-x86/mach-default/mach_mpparse.h
+++ b/include/asm-x86/mach-default/mach_mpparse.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_MPPARSE_H
-#define __ASM_MACH_MPPARSE_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_MPPARSE_H
+#define ASM_X86__MACH_DEFAULT__MACH_MPPARSE_H
 
 static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 
                 char *productid)
@@ -14,4 +14,4 @@ static inline int acpi_madt_oem_check(char *oem_id, char *oem_table_id)
 }
 
 
-#endif /* __ASM_MACH_MPPARSE_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_MPPARSE_H */
diff --git a/include/asm-x86/mach-default/mach_mpspec.h b/include/asm-x86/mach-default/mach_mpspec.h
index 51c9a9775932..d77646f011f1 100644
--- a/include/asm-x86/mach-default/mach_mpspec.h
+++ b/include/asm-x86/mach-default/mach_mpspec.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_MPSPEC_H
-#define __ASM_MACH_MPSPEC_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_MPSPEC_H
+#define ASM_X86__MACH_DEFAULT__MACH_MPSPEC_H
 
 #define MAX_IRQ_SOURCES 256
 
@@ -9,4 +9,4 @@
 #define MAX_MP_BUSSES 32
 #endif
 
-#endif /* __ASM_MACH_MPSPEC_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-default/mach_timer.h b/include/asm-x86/mach-default/mach_timer.h
index 4b76e536cd98..990b15833834 100644
--- a/include/asm-x86/mach-default/mach_timer.h
+++ b/include/asm-x86/mach-default/mach_timer.h
@@ -10,8 +10,8 @@
  * directly because of the awkward 8-bit access mechanism of the 82C54
  * device.
  */
-#ifndef _MACH_TIMER_H
-#define _MACH_TIMER_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_TIMER_H
+#define ASM_X86__MACH_DEFAULT__MACH_TIMER_H
 
 #define CALIBRATE_TIME_MSEC 30 /* 30 msecs */
 #define CALIBRATE_LATCH \
@@ -45,4 +45,4 @@ static inline void mach_countup(unsigned long *count_p)
         *count_p = count;
 }
 
-#endif /* !_MACH_TIMER_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_TIMER_H */
diff --git a/include/asm-x86/mach-default/mach_traps.h b/include/asm-x86/mach-default/mach_traps.h
index 2fe7705c0484..ff8778f26b84 100644
--- a/include/asm-x86/mach-default/mach_traps.h
+++ b/include/asm-x86/mach-default/mach_traps.h
@@ -2,17 +2,11 @@
  *  Machine specific NMI handling for generic.
  *  Split out from traps.c by Osamu Tomita <tomita@cinet.co.jp>
  */
-#ifndef _MACH_TRAPS_H
-#define _MACH_TRAPS_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_TRAPS_H
+#define ASM_X86__MACH_DEFAULT__MACH_TRAPS_H
 
 #include <asm/mc146818rtc.h>
 
-static inline void clear_mem_error(unsigned char reason)
-{
-        reason = (reason & 0xf) | 4;
-        outb(reason, 0x61);
-}
-
 static inline unsigned char get_nmi_reason(void)
 {
         return inb(0x61);
@@ -36,4 +30,4 @@ static inline void reassert_nmi(void)
                 unlock_cmos();
 }
 
-#endif /* !_MACH_TRAPS_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_TRAPS_H */
diff --git a/include/asm-x86/mach-default/mach_wakecpu.h b/include/asm-x86/mach-default/mach_wakecpu.h
index 3ebb17893aa5..361b810f5160 100644
--- a/include/asm-x86/mach-default/mach_wakecpu.h
+++ b/include/asm-x86/mach-default/mach_wakecpu.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_WAKECPU_H
-#define __ASM_MACH_WAKECPU_H
+#ifndef ASM_X86__MACH_DEFAULT__MACH_WAKECPU_H
+#define ASM_X86__MACH_DEFAULT__MACH_WAKECPU_H
 
 /* 
  * This file copes with machines that wakeup secondary CPUs by the
@@ -39,4 +39,4 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low)
  #define inquire_remote_apic(apicid) {}
 #endif
 
-#endif /* __ASM_MACH_WAKECPU_H */
+#endif /* ASM_X86__MACH_DEFAULT__MACH_WAKECPU_H */
diff --git a/include/asm-x86/mach-es7000/mach_apicdef.h b/include/asm-x86/mach-es7000/mach_apicdef.h
deleted file mode 100644
index a58ab5a75c8c..000000000000
--- a/include/asm-x86/mach-es7000/mach_apicdef.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_MACH_APICDEF_H
-#define __ASM_MACH_APICDEF_H
-
-#define         APIC_ID_MASK            (0xFF<<24)
-
-static inline unsigned get_apic_id(unsigned long x) 
-{ 
-        return (((x)>>24)&0xFF);
-} 
-
-#define         GET_APIC_ID(x)  get_apic_id(x)
-
-#endif
diff --git a/include/asm-x86/mach-generic/gpio.h b/include/asm-x86/mach-generic/gpio.h
index 5305dcb96df2..6ce0f7786ef8 100644
--- a/include/asm-x86/mach-generic/gpio.h
+++ b/include/asm-x86/mach-generic/gpio.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_GENERIC_GPIO_H
-#define __ASM_MACH_GENERIC_GPIO_H
+#ifndef ASM_X86__MACH_GENERIC__GPIO_H
+#define ASM_X86__MACH_GENERIC__GPIO_H
 
 int gpio_request(unsigned gpio, const char *label);
 void gpio_free(unsigned gpio);
@@ -12,4 +12,4 @@ int irq_to_gpio(unsigned irq);
 
 #include <asm-generic/gpio.h>           /* cansleep wrappers */
 
-#endif /* __ASM_MACH_GENERIC_GPIO_H */
+#endif /* ASM_X86__MACH_GENERIC__GPIO_H */
diff --git a/include/asm-x86/mach-generic/irq_vectors_limits.h b/include/asm-x86/mach-generic/irq_vectors_limits.h
index 890ce3f5e09a..f7870e1a220d 100644
--- a/include/asm-x86/mach-generic/irq_vectors_limits.h
+++ b/include/asm-x86/mach-generic/irq_vectors_limits.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_IRQ_VECTORS_LIMITS_H
-#define _ASM_IRQ_VECTORS_LIMITS_H
+#ifndef ASM_X86__MACH_GENERIC__IRQ_VECTORS_LIMITS_H
+#define ASM_X86__MACH_GENERIC__IRQ_VECTORS_LIMITS_H
 
 /*
  * For Summit or generic (i.e. installer) kernels, we have lots of I/O APICs,
@@ -11,4 +11,4 @@
 #define NR_IRQS 224
 #define NR_IRQ_VECTORS  1024
 
-#endif /* _ASM_IRQ_VECTORS_LIMITS_H */
+#endif /* ASM_X86__MACH_GENERIC__IRQ_VECTORS_LIMITS_H */
diff --git a/include/asm-x86/mach-generic/mach_apic.h b/include/asm-x86/mach-generic/mach_apic.h
index 6eff343e1233..5d010c6881dd 100644
--- a/include/asm-x86/mach-generic/mach_apic.h
+++ b/include/asm-x86/mach-generic/mach_apic.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
+#ifndef ASM_X86__MACH_GENERIC__MACH_APIC_H
+#define ASM_X86__MACH_GENERIC__MACH_APIC_H
 
 #include <asm/genapic.h>
 
@@ -29,4 +29,4 @@
 
 extern void generic_bigsmp_probe(void);
 
-#endif /* __ASM_MACH_APIC_H */
+#endif /* ASM_X86__MACH_GENERIC__MACH_APIC_H */
diff --git a/include/asm-x86/mach-generic/mach_apicdef.h b/include/asm-x86/mach-generic/mach_apicdef.h
index 28ed98972ca8..1657f38b8f27 100644
--- a/include/asm-x86/mach-generic/mach_apicdef.h
+++ b/include/asm-x86/mach-generic/mach_apicdef.h
@@ -1,5 +1,5 @@
-#ifndef _GENAPIC_MACH_APICDEF_H
-#define _GENAPIC_MACH_APICDEF_H 1
+#ifndef ASM_X86__MACH_GENERIC__MACH_APICDEF_H
+#define ASM_X86__MACH_GENERIC__MACH_APICDEF_H
 
 #ifndef APIC_DEFINITION
 #include <asm/genapic.h>
@@ -8,4 +8,4 @@
 #define APIC_ID_MASK (genapic->apic_id_mask)
 #endif
 
-#endif
+#endif /* ASM_X86__MACH_GENERIC__MACH_APICDEF_H */
diff --git a/include/asm-x86/mach-generic/mach_ipi.h b/include/asm-x86/mach-generic/mach_ipi.h
index 441b0fe3ed1d..f67433dbd65f 100644
--- a/include/asm-x86/mach-generic/mach_ipi.h
+++ b/include/asm-x86/mach-generic/mach_ipi.h
@@ -1,5 +1,5 @@
-#ifndef _MACH_IPI_H
-#define _MACH_IPI_H 1
+#ifndef ASM_X86__MACH_GENERIC__MACH_IPI_H
+#define ASM_X86__MACH_GENERIC__MACH_IPI_H
 
 #include <asm/genapic.h>
 
@@ -7,4 +7,4 @@
 #define send_IPI_allbutself (genapic->send_IPI_allbutself)
 #define send_IPI_all (genapic->send_IPI_all)
 
-#endif
+#endif /* ASM_X86__MACH_GENERIC__MACH_IPI_H */
diff --git a/include/asm-x86/mach-generic/mach_mpparse.h b/include/asm-x86/mach-generic/mach_mpparse.h
index 586cadbf3787..3115564e557c 100644
--- a/include/asm-x86/mach-generic/mach_mpparse.h
+++ b/include/asm-x86/mach-generic/mach_mpparse.h
@@ -1,5 +1,5 @@
-#ifndef _MACH_MPPARSE_H
-#define _MACH_MPPARSE_H 1
+#ifndef ASM_X86__MACH_GENERIC__MACH_MPPARSE_H
+#define ASM_X86__MACH_GENERIC__MACH_MPPARSE_H
 
 
 extern int mps_oem_check(struct mp_config_table *mpc, char *oem,
@@ -7,4 +7,4 @@ extern int mps_oem_check(struct mp_config_table *mpc, char *oem,
 
 extern int acpi_madt_oem_check(char *oem_id, char *oem_table_id);
 
-#endif
+#endif /* ASM_X86__MACH_GENERIC__MACH_MPPARSE_H */
diff --git a/include/asm-x86/mach-generic/mach_mpspec.h b/include/asm-x86/mach-generic/mach_mpspec.h
index c83c120be538..6061b153613e 100644
--- a/include/asm-x86/mach-generic/mach_mpspec.h
+++ b/include/asm-x86/mach-generic/mach_mpspec.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_MPSPEC_H
-#define __ASM_MACH_MPSPEC_H
+#ifndef ASM_X86__MACH_GENERIC__MACH_MPSPEC_H
+#define ASM_X86__MACH_GENERIC__MACH_MPSPEC_H
 
 #define MAX_IRQ_SOURCES 256
 
@@ -9,4 +9,4 @@
 
 extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
                                 char *productid);
-#endif /* __ASM_MACH_MPSPEC_H */
+#endif /* ASM_X86__MACH_GENERIC__MACH_MPSPEC_H */
diff --git a/include/asm-x86/mach-rdc321x/gpio.h b/include/asm-x86/mach-rdc321x/gpio.h
index acce0b7d397b..94b6cdf532e2 100644
--- a/include/asm-x86/mach-rdc321x/gpio.h
+++ b/include/asm-x86/mach-rdc321x/gpio.h
@@ -1,5 +1,7 @@
-#ifndef _RDC321X_GPIO_H
-#define _RDC321X_GPIO_H
+#ifndef ASM_X86__MACH_RDC321X__GPIO_H
+#define ASM_X86__MACH_RDC321X__GPIO_H
+
+#include <linux/kernel.h>
 
 extern int rdc_gpio_get_value(unsigned gpio);
 extern void rdc_gpio_set_value(unsigned gpio, int value);
@@ -18,6 +20,7 @@ static inline int gpio_request(unsigned gpio, const char *label)
 
 static inline void gpio_free(unsigned gpio)
 {
+        might_sleep();
         rdc_gpio_free(gpio);
 }
 
@@ -54,4 +57,4 @@ static inline int irq_to_gpio(unsigned irq)
 /* For cansleep */
 #include <asm-generic/gpio.h>
 
-#endif /* _RDC321X_GPIO_H_ */
+#endif /* ASM_X86__MACH_RDC321X__GPIO_H */
diff --git a/include/asm-x86/mach-summit/mach_apicdef.h b/include/asm-x86/mach-summit/mach_apicdef.h
deleted file mode 100644
index a58ab5a75c8c..000000000000
--- a/include/asm-x86/mach-summit/mach_apicdef.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef __ASM_MACH_APICDEF_H
-#define __ASM_MACH_APICDEF_H
-
-#define         APIC_ID_MASK            (0xFF<<24)
-
-static inline unsigned get_apic_id(unsigned long x) 
-{ 
-        return (((x)>>24)&0xFF);
-} 
-
-#define         GET_APIC_ID(x)  get_apic_id(x)
-
-#endif
diff --git a/include/asm-x86/math_emu.h b/include/asm-x86/math_emu.h
index 9bf4ae93ab10..5768d8e95c8c 100644
--- a/include/asm-x86/math_emu.h
+++ b/include/asm-x86/math_emu.h
@@ -1,5 +1,5 @@
-#ifndef _I386_MATH_EMU_H
-#define _I386_MATH_EMU_H
+#ifndef ASM_X86__MATH_EMU_H
+#define ASM_X86__MATH_EMU_H
 
 /* This structure matches the layout of the data saved to the stack
    following a device-not-present interrupt, part of it saved
@@ -28,4 +28,4 @@ struct info {
         long ___vm86_fs;
         long ___vm86_gs;
 };
-#endif
+#endif /* ASM_X86__MATH_EMU_H */
diff --git a/include/asm-x86/mc146818rtc.h b/include/asm-x86/mc146818rtc.h
index daf1ccde77af..a995f33176cd 100644
--- a/include/asm-x86/mc146818rtc.h
+++ b/include/asm-x86/mc146818rtc.h
@@ -1,8 +1,8 @@
 /*
  * Machine dependent access functions for RTC registers.
  */
-#ifndef _ASM_MC146818RTC_H
-#define _ASM_MC146818RTC_H
+#ifndef ASM_X86__MC146818RTC_H
+#define ASM_X86__MC146818RTC_H
 
 #include <asm/io.h>
 #include <asm/system.h>
@@ -101,4 +101,4 @@ extern unsigned long mach_get_cmos_time(void);
 
 #define RTC_IRQ 8
 
-#endif /* _ASM_MC146818RTC_H */
+#endif /* ASM_X86__MC146818RTC_H */
diff --git a/include/asm-x86/mca.h b/include/asm-x86/mca.h
index 09adf2eac4dc..60d1ed287b13 100644
--- a/include/asm-x86/mca.h
+++ b/include/asm-x86/mca.h
@@ -1,8 +1,8 @@
 /* -*- mode: c; c-basic-offset: 8 -*- */
 
 /* Platform specific MCA defines */
-#ifndef _ASM_MCA_H
-#define _ASM_MCA_H
+#ifndef ASM_X86__MCA_H
+#define ASM_X86__MCA_H
 
 /* Maximal number of MCA slots - actually, some machines have less, but
  * they all have sufficient number of POS registers to cover 8.
@@ -40,4 +40,4 @@
  */
 #define MCA_NUMADAPTERS (MCA_MAX_SLOT_NR+3)
 
-#endif
+#endif /* ASM_X86__MCA_H */
diff --git a/include/asm-x86/mca_dma.h b/include/asm-x86/mca_dma.h
index c3dca6edc6b1..49f22be237d2 100644
--- a/include/asm-x86/mca_dma.h
+++ b/include/asm-x86/mca_dma.h
@@ -1,5 +1,5 @@
-#ifndef MCA_DMA_H
-#define MCA_DMA_H
+#ifndef ASM_X86__MCA_DMA_H
+#define ASM_X86__MCA_DMA_H
 
 #include <asm/io.h>
 #include <linux/ioport.h>
@@ -198,4 +198,4 @@ static inline void mca_set_dma_mode(unsigned int dmanr, unsigned int mode)
         outb(mode, MCA_DMA_REG_EXE);
 }
 
-#endif /* MCA_DMA_H */
+#endif /* ASM_X86__MCA_DMA_H */
diff --git a/include/asm-x86/mce.h b/include/asm-x86/mce.h
index 94f1fd79e22a..036133eaf744 100644
--- a/include/asm-x86/mce.h
+++ b/include/asm-x86/mce.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_MCE_H
-#define _ASM_X86_MCE_H
+#ifndef ASM_X86__MCE_H
+#define ASM_X86__MCE_H
 
 #ifdef __x86_64__
 
@@ -92,6 +92,7 @@ extern int mce_disabled;
 
 void mce_log(struct mce *m);
 DECLARE_PER_CPU(struct sys_device, device_mce);
+extern void (*threshold_cpu_callback)(unsigned long action, unsigned int cpu);
 
 #ifdef CONFIG_X86_MCE_INTEL
 void mce_intel_feature_init(struct cpuinfo_x86 *c);
@@ -126,4 +127,4 @@ extern void restart_mce(void);
 
 #endif /* __KERNEL__ */
 
-#endif
+#endif /* ASM_X86__MCE_H */
diff --git a/include/asm-x86/microcode.h b/include/asm-x86/microcode.h
new file mode 100644
index 000000000000..62c793bb70ca
--- /dev/null
+++ b/include/asm-x86/microcode.h
@@ -0,0 +1,47 @@
+#ifndef ASM_X86__MICROCODE_H
+#define ASM_X86__MICROCODE_H
+
+struct cpu_signature {
+        unsigned int sig;
+        unsigned int pf;
+        unsigned int rev;
+};
+
+struct device;
+
+struct microcode_ops {
+        int  (*request_microcode_user) (int cpu, const void __user *buf, size_t size);
+        int  (*request_microcode_fw) (int cpu, struct device *device);
+
+        void (*apply_microcode) (int cpu);
+
+        int  (*collect_cpu_info) (int cpu, struct cpu_signature *csig);
+        void (*microcode_fini_cpu) (int cpu);
+};
+
+struct ucode_cpu_info {
+        struct cpu_signature cpu_sig;
+        int valid;
+        void *mc;
+};
+extern struct ucode_cpu_info ucode_cpu_info[];
+
+#ifdef CONFIG_MICROCODE_INTEL
+extern struct microcode_ops * __init init_intel_microcode(void);
+#else
+static inline struct microcode_ops * __init init_intel_microcode(void)
+{
+        return NULL;
+}
+#endif /* CONFIG_MICROCODE_INTEL */
+
+#ifdef CONFIG_MICROCODE_AMD
+extern struct microcode_ops * __init init_amd_microcode(void);
+#else
+static inline struct microcode_ops * __init init_amd_microcode(void)
+{
+        return NULL;
+}
+#endif
+
+#endif /* ASM_X86__MICROCODE_H */
diff --git a/include/asm-x86/mman.h b/include/asm-x86/mman.h
index 90bc4108a4fd..4ef28e6de383 100644
--- a/include/asm-x86/mman.h
+++ b/include/asm-x86/mman.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_MMAN_H
-#define _ASM_X86_MMAN_H
+#ifndef ASM_X86__MMAN_H
+#define ASM_X86__MMAN_H
 
 #include <asm-generic/mman.h>
 
@@ -17,4 +17,4 @@
 #define MCL_CURRENT     1               /* lock all current mappings */
 #define MCL_FUTURE      2               /* lock all future mappings */
 
-#endif /* _ASM_X86_MMAN_H */
+#endif /* ASM_X86__MMAN_H */
diff --git a/include/asm-x86/mmconfig.h b/include/asm-x86/mmconfig.h
index e293ab81e850..fb79b1cf5d07 100644
--- a/include/asm-x86/mmconfig.h
+++ b/include/asm-x86/mmconfig.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_MMCONFIG_H
-#define _ASM_MMCONFIG_H
+#ifndef ASM_X86__MMCONFIG_H
+#define ASM_X86__MMCONFIG_H
 
 #ifdef CONFIG_PCI_MMCONFIG
 extern void __cpuinit fam10h_check_enable_mmcfg(void);
@@ -9,4 +9,4 @@ static inline void fam10h_check_enable_mmcfg(void) { }
 static inline void check_enable_amd_mmconf_dmi(void) { }
 #endif
 
-#endif
+#endif /* ASM_X86__MMCONFIG_H */
diff --git a/include/asm-x86/mmu.h b/include/asm-x86/mmu.h
index 00e88679e11f..9d5aff14334a 100644
--- a/include/asm-x86/mmu.h
+++ b/include/asm-x86/mmu.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_MMU_H
-#define _ASM_X86_MMU_H
+#ifndef ASM_X86__MMU_H
+#define ASM_X86__MMU_H
 
 #include <linux/spinlock.h>
 #include <linux/mutex.h>
@@ -7,14 +7,9 @@
 /*
  * The x86 doesn't have a mmu context, but
  * we put the segment information here.
- *
- * cpu_vm_mask is used to optimize ldt flushing.
  */
 typedef struct {
         void *ldt;
-#ifdef CONFIG_X86_64
-        rwlock_t ldtlock;
-#endif
         int size;
         struct mutex lock;
         void *vdso;
@@ -28,4 +23,4 @@ static inline void leave_mm(int cpu)
 }
 #endif
 
-#endif /* _ASM_X86_MMU_H */
+#endif /* ASM_X86__MMU_H */
diff --git a/include/asm-x86/mmu_context.h b/include/asm-x86/mmu_context.h
index fac57014e7c6..8ec940bfd079 100644
--- a/include/asm-x86/mmu_context.h
+++ b/include/asm-x86/mmu_context.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_X86_MMU_CONTEXT_H
-#define __ASM_X86_MMU_CONTEXT_H
+#ifndef ASM_X86__MMU_CONTEXT_H
+#define ASM_X86__MMU_CONTEXT_H
 
 #include <asm/desc.h>
 #include <asm/atomic.h>
@@ -34,4 +34,4 @@ do {						\
 } while (0);
 
 
-#endif /* __ASM_X86_MMU_CONTEXT_H */
+#endif /* ASM_X86__MMU_CONTEXT_H */
diff --git a/include/asm-x86/mmu_context_32.h b/include/asm-x86/mmu_context_32.h
index 824fc575c6d8..cce6f6e4afd6 100644
--- a/include/asm-x86/mmu_context_32.h
+++ b/include/asm-x86/mmu_context_32.h
@@ -1,5 +1,5 @@
-#ifndef __I386_SCHED_H
-#define __I386_SCHED_H
+#ifndef ASM_X86__MMU_CONTEXT_32_H
+#define ASM_X86__MMU_CONTEXT_32_H
 
 static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 {
@@ -53,4 +53,4 @@ static inline void switch_mm(struct mm_struct *prev,
 #define deactivate_mm(tsk, mm)                  \
         asm("movl %0,%%gs": :"r" (0));
 
-#endif
+#endif /* ASM_X86__MMU_CONTEXT_32_H */
diff --git a/include/asm-x86/mmu_context_64.h b/include/asm-x86/mmu_context_64.h
index c7000634ccae..26758673c828 100644
--- a/include/asm-x86/mmu_context_64.h
+++ b/include/asm-x86/mmu_context_64.h
@@ -1,5 +1,5 @@
-#ifndef __X86_64_MMU_CONTEXT_H
-#define __X86_64_MMU_CONTEXT_H
+#ifndef ASM_X86__MMU_CONTEXT_64_H
+#define ASM_X86__MMU_CONTEXT_64_H
 
 #include <asm/pda.h>
 
@@ -51,4 +51,4 @@ do {						\
         asm volatile("movl %0,%%fs"::"r"(0));   \
 } while (0)
 
-#endif
+#endif /* ASM_X86__MMU_CONTEXT_64_H */
diff --git a/include/asm-x86/mmx.h b/include/asm-x86/mmx.h
index 940881218ff8..2e7299bb3653 100644
--- a/include/asm-x86/mmx.h
+++ b/include/asm-x86/mmx.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_MMX_H
-#define _ASM_MMX_H
+#ifndef ASM_X86__MMX_H
+#define ASM_X86__MMX_H
 
 /*
  *      MMX 3Dnow! helper operations
@@ -11,4 +11,4 @@ extern void *_mmx_memcpy(void *to, const void *from, size_t size);
 extern void mmx_clear_page(void *page);
 extern void mmx_copy_page(void *to, void *from);
 
-#endif
+#endif /* ASM_X86__MMX_H */
diff --git a/include/asm-x86/mmzone_32.h b/include/asm-x86/mmzone_32.h
index 5862e6460658..121b65d61d86 100644
--- a/include/asm-x86/mmzone_32.h
+++ b/include/asm-x86/mmzone_32.h
@@ -3,8 +3,8 @@
  *
  */
 
-#ifndef _ASM_MMZONE_H_
-#define _ASM_MMZONE_H_
+#ifndef ASM_X86__MMZONE_32_H
+#define ASM_X86__MMZONE_32_H
 
 #include <asm/smp.h>
 
@@ -131,4 +131,4 @@ static inline int pfn_valid(int pfn)
 })
 #endif /* CONFIG_NEED_MULTIPLE_NODES */
 
-#endif /* _ASM_MMZONE_H_ */
+#endif /* ASM_X86__MMZONE_32_H */
diff --git a/include/asm-x86/mmzone_64.h b/include/asm-x86/mmzone_64.h
index 594bd0dc1d08..6480f3333b2a 100644
--- a/include/asm-x86/mmzone_64.h
+++ b/include/asm-x86/mmzone_64.h
@@ -1,13 +1,13 @@
 /* K8 NUMA support */
 /* Copyright 2002,2003 by Andi Kleen, SuSE Labs */
 /* 2.5 Version loosely based on the NUMAQ Code by Pat Gaughen. */
-#ifndef _ASM_X86_64_MMZONE_H
-#define _ASM_X86_64_MMZONE_H 1
+#ifndef ASM_X86__MMZONE_64_H
+#define ASM_X86__MMZONE_64_H
 
 
 #ifdef CONFIG_NUMA
 
-#define VIRTUAL_BUG_ON(x)
+#include <linux/mmdebug.h>
 
 #include <asm/smp.h>
 
@@ -29,7 +29,6 @@ static inline __attribute__((pure)) int phys_to_nid(unsigned long addr)
 {
         unsigned nid;
         VIRTUAL_BUG_ON(!memnodemap);
-        VIRTUAL_BUG_ON((addr >> memnode_shift) >= memnodemapsize);
         nid = memnodemap[addr >> memnode_shift];
         VIRTUAL_BUG_ON(nid >= MAX_NUMNODES || !node_data[nid]);
         return nid;
@@ -49,4 +48,4 @@ extern int early_pfn_to_nid(unsigned long pfn);
 #endif
 
 #endif
-#endif
+#endif /* ASM_X86__MMZONE_64_H */
diff --git a/include/asm-x86/module.h b/include/asm-x86/module.h
index bfedb247871c..864f2005fc1d 100644
--- a/include/asm-x86/module.h
+++ b/include/asm-x86/module.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_MODULE_H
-#define _ASM_MODULE_H
+#ifndef ASM_X86__MODULE_H
+#define ASM_X86__MODULE_H
 
 /* x86_32/64 are simple */
 struct mod_arch_specific {};
@@ -52,8 +52,6 @@ struct mod_arch_specific {};
 #define MODULE_PROC_FAMILY "EFFICEON "
 #elif defined CONFIG_MWINCHIPC6
 #define MODULE_PROC_FAMILY "WINCHIPC6 "
-#elif defined CONFIG_MWINCHIP2
-#define MODULE_PROC_FAMILY "WINCHIP2 "
 #elif defined CONFIG_MWINCHIP3D
 #define MODULE_PROC_FAMILY "WINCHIP3D "
 #elif defined CONFIG_MCYRIXIII
@@ -79,4 +77,4 @@ struct mod_arch_specific {};
 # define MODULE_ARCH_VERMAGIC MODULE_PROC_FAMILY MODULE_STACKSIZE
 #endif
 
-#endif /* _ASM_MODULE_H */
+#endif /* ASM_X86__MODULE_H */
diff --git a/include/asm-x86/mpspec.h b/include/asm-x86/mpspec.h
index b6995e567fcc..be2241a818f1 100644
--- a/include/asm-x86/mpspec.h
+++ b/include/asm-x86/mpspec.h
@@ -1,15 +1,16 @@
-#ifndef _AM_X86_MPSPEC_H
-#define _AM_X86_MPSPEC_H
+#ifndef ASM_X86__MPSPEC_H
+#define ASM_X86__MPSPEC_H
 
 #include <linux/init.h>
 
 #include <asm/mpspec_def.h>
 
+extern int apic_version[MAX_APICS];
+
 #ifdef CONFIG_X86_32
 #include <mach_mpspec.h>
 
 extern unsigned int def_to_bigsmp;
-extern int apic_version[MAX_APICS];
 extern u8 apicid_2_node[];
 extern int pic_mode;
 
@@ -141,4 +142,4 @@ static inline void physid_set_mask_of_physid(int physid, physid_mask_t *map)
 
 extern physid_mask_t phys_cpu_present_map;
 
-#endif
+#endif /* ASM_X86__MPSPEC_H */
diff --git a/include/asm-x86/mpspec_def.h b/include/asm-x86/mpspec_def.h
index 38d1e73b49e4..79166b048012 100644
--- a/include/asm-x86/mpspec_def.h
+++ b/include/asm-x86/mpspec_def.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MPSPEC_DEF_H
-#define __ASM_MPSPEC_DEF_H
+#ifndef ASM_X86__MPSPEC_DEF_H
+#define ASM_X86__MPSPEC_DEF_H
 
 /*
  * Structure definitions for SMP machines following the
@@ -177,4 +177,4 @@ enum mp_bustype {
         MP_BUS_PCI,
         MP_BUS_MCA,
 };
-#endif
+#endif /* ASM_X86__MPSPEC_DEF_H */
diff --git a/include/asm-x86/msgbuf.h b/include/asm-x86/msgbuf.h
index 7e4e9481f51c..1b538c907a3d 100644
--- a/include/asm-x86/msgbuf.h
+++ b/include/asm-x86/msgbuf.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_MSGBUF_H
-#define _ASM_X86_MSGBUF_H
+#ifndef ASM_X86__MSGBUF_H
+#define ASM_X86__MSGBUF_H
 
 /*
  * The msqid64_ds structure for i386 architecture.
@@ -36,4 +36,4 @@ struct msqid64_ds {
         unsigned long  __unused5;
 };
 
-#endif /* _ASM_X86_MSGBUF_H */
+#endif /* ASM_X86__MSGBUF_H */
diff --git a/include/asm-x86/msidef.h b/include/asm-x86/msidef.h
index 296f29ce426d..ed9190246876 100644
--- a/include/asm-x86/msidef.h
+++ b/include/asm-x86/msidef.h
@@ -1,5 +1,5 @@
-#ifndef ASM_MSIDEF_H
-#define ASM_MSIDEF_H
+#ifndef ASM_X86__MSIDEF_H
+#define ASM_X86__MSIDEF_H
 
 /*
  * Constants for Intel APIC based MSI messages.
@@ -48,4 +48,8 @@
 #define  MSI_ADDR_DEST_ID(dest)         (((dest) << MSI_ADDR_DEST_ID_SHIFT) & \
                                          MSI_ADDR_DEST_ID_MASK)
 
-#endif /* ASM_MSIDEF_H */
+#define MSI_ADDR_IR_EXT_INT             (1 << 4)
+#define MSI_ADDR_IR_SHV                 (1 << 3)
+#define MSI_ADDR_IR_INDEX1(index)       ((index & 0x8000) >> 13)
+#define MSI_ADDR_IR_INDEX2(index)       ((index & 0x7fff) << 5)
+#endif /* ASM_X86__MSIDEF_H */
diff --git a/include/asm-x86/msr-index.h b/include/asm-x86/msr-index.h
index 44bce773012e..dabd10f0bbee 100644
--- a/include/asm-x86/msr-index.h
+++ b/include/asm-x86/msr-index.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MSR_INDEX_H
-#define __ASM_MSR_INDEX_H
+#ifndef ASM_X86__MSR_INDEX_H
+#define ASM_X86__MSR_INDEX_H
 
 /* CPU model specific register (MSR) numbers */
 
@@ -176,6 +176,10 @@
 #define MSR_IA32_TSC                    0x00000010
 #define MSR_IA32_PLATFORM_ID            0x00000017
 #define MSR_IA32_EBL_CR_POWERON         0x0000002a
+#define MSR_IA32_FEATURE_CONTROL        0x0000003a
+
+#define FEATURE_CONTROL_LOCKED          (1<<0)
+#define FEATURE_CONTROL_VMXON_ENABLED   (1<<2)
 
 #define MSR_IA32_APICBASE               0x0000001b
 #define MSR_IA32_APICBASE_BSP           (1<<8)
@@ -310,4 +314,19 @@
 /* Geode defined MSRs */
 #define MSR_GEODE_BUSCONT_CONF0         0x00001900
 
-#endif /* __ASM_MSR_INDEX_H */
+/* Intel VT MSRs */
+#define MSR_IA32_VMX_BASIC              0x00000480
+#define MSR_IA32_VMX_PINBASED_CTLS      0x00000481
+#define MSR_IA32_VMX_PROCBASED_CTLS     0x00000482
+#define MSR_IA32_VMX_EXIT_CTLS          0x00000483
+#define MSR_IA32_VMX_ENTRY_CTLS         0x00000484
+#define MSR_IA32_VMX_MISC               0x00000485
+#define MSR_IA32_VMX_CR0_FIXED0         0x00000486
+#define MSR_IA32_VMX_CR0_FIXED1         0x00000487
+#define MSR_IA32_VMX_CR4_FIXED0         0x00000488
+#define MSR_IA32_VMX_CR4_FIXED1         0x00000489
+#define MSR_IA32_VMX_VMCS_ENUM          0x0000048a
+#define MSR_IA32_VMX_PROCBASED_CTLS2    0x0000048b
+#define MSR_IA32_VMX_EPT_VPID_CAP       0x0000048c
+
+#endif /* ASM_X86__MSR_INDEX_H */
diff --git a/include/asm-x86/msr.h b/include/asm-x86/msr.h
index ca110ee73f07..530af1f6389e 100644
--- a/include/asm-x86/msr.h
+++ b/include/asm-x86/msr.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_X86_MSR_H_
-#define __ASM_X86_MSR_H_
+#ifndef ASM_X86__MSR_H
+#define ASM_X86__MSR_H
 
 #include <asm/msr-index.h>
 
@@ -52,6 +52,22 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
 {
         DECLARE_ARGS(val, low, high);
 
+        asm volatile("2: rdmsr ; xor %[err],%[err]\n"
+                     "1:\n\t"
+                     ".section .fixup,\"ax\"\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
+                     ".previous\n\t"
+                     _ASM_EXTABLE(2b, 3b)
+                     : [err] "=r" (*err), EAX_EDX_RET(val, low, high)
+                     : "c" (msr), [fault] "i" (-EFAULT));
+        return EAX_EDX_VAL(val, low, high);
+}
+
+static inline unsigned long long native_read_msr_amd_safe(unsigned int msr,
+                                                      int *err)
+{
+        DECLARE_ARGS(val, low, high);
+
         asm volatile("2: rdmsr ; xor %0,%0\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
@@ -59,7 +75,7 @@ static inline unsigned long long native_read_msr_safe(unsigned int msr,
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
                      : "=r" (*err), EAX_EDX_RET(val, low, high)
-                     : "c" (msr), "i" (-EFAULT));
+                     : "c" (msr), "D" (0x9c5a203a), "i" (-EFAULT));
         return EAX_EDX_VAL(val, low, high);
 }
 
@@ -73,15 +89,15 @@ static inline int native_write_msr_safe(unsigned int msr,
                                         unsigned low, unsigned high)
 {
         int err;
-        asm volatile("2: wrmsr ; xor %0,%0\n"
+        asm volatile("2: wrmsr ; xor %[err],%[err]\n"
                      "1:\n\t"
                      ".section .fixup,\"ax\"\n\t"
-                     "3:  mov %4,%0 ; jmp 1b\n\t"
+                     "3:  mov %[fault],%[err] ; jmp 1b\n\t"
                      ".previous\n\t"
                      _ASM_EXTABLE(2b, 3b)
-                     : "=a" (err)
+                     : [err] "=a" (err)
                      : "c" (msr), "0" (low), "d" (high),
-                       "i" (-EFAULT)
+                       [fault] "i" (-EFAULT)
                      : "memory");
         return err;
 }
@@ -158,6 +174,13 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
         *p = native_read_msr_safe(msr, &err);
         return err;
 }
+static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
+{
+        int err;
+
+        *p = native_read_msr_amd_safe(msr, &err);
+        return err;
+}
 
 #define rdtscl(low)                                             \
         ((low) = (u32)native_read_tsc())
@@ -192,19 +215,20 @@ do {                                                            \
 #define write_rdtscp_aux(val) wrmsr(0xc0000103, (val), 0)
 
 #ifdef CONFIG_SMP
-void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
-
 int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 #else  /*  CONFIG_SMP  */
-static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+static inline int rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
         rdmsr(msr_no, *l, *h);
+        return 0;
 }
-static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+static inline int wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
         wrmsr(msr_no, l, h);
+        return 0;
 }
 static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no,
                                     u32 *l, u32 *h)
@@ -220,4 +244,4 @@ static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 #endif /* __KERNEL__ */
 
 
-#endif
+#endif /* ASM_X86__MSR_H */
diff --git a/include/asm-x86/mtrr.h b/include/asm-x86/mtrr.h
index a69a01a51729..23a7f83da953 100644
--- a/include/asm-x86/mtrr.h
+++ b/include/asm-x86/mtrr.h
@@ -20,8 +20,8 @@
     The postal address is:
       Richard Gooch, c/o ATNF, P. O. Box 76, Epping, N.S.W., 2121, Australia.
 */
-#ifndef _ASM_X86_MTRR_H
-#define _ASM_X86_MTRR_H
+#ifndef ASM_X86__MTRR_H
+#define ASM_X86__MTRR_H
 
 #include <linux/ioctl.h>
 #include <linux/errno.h>
@@ -170,4 +170,4 @@ struct mtrr_gentry32 {
 
 #endif /* __KERNEL__ */
 
-#endif  /*  _ASM_X86_MTRR_H  */
+#endif /* ASM_X86__MTRR_H */
diff --git a/include/asm-x86/mutex_32.h b/include/asm-x86/mutex_32.h
index 73e928ef5f03..25c16d8ba3c7 100644
--- a/include/asm-x86/mutex_32.h
+++ b/include/asm-x86/mutex_32.h
@@ -6,8 +6,8 @@
  *
  *  Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com>
  */
-#ifndef _ASM_MUTEX_H
-#define _ASM_MUTEX_H
+#ifndef ASM_X86__MUTEX_32_H
+#define ASM_X86__MUTEX_32_H
 
 #include <asm/alternative.h>
 
@@ -122,4 +122,4 @@ static inline int __mutex_fastpath_trylock(atomic_t *count,
 #endif
 }
 
-#endif
+#endif /* ASM_X86__MUTEX_32_H */
diff --git a/include/asm-x86/mutex_64.h b/include/asm-x86/mutex_64.h
index f3fae9becb38..918ba21ab9d9 100644
--- a/include/asm-x86/mutex_64.h
+++ b/include/asm-x86/mutex_64.h
@@ -6,8 +6,8 @@
  *
  *  Copyright (C) 2004, 2005, 2006 Red Hat, Inc., Ingo Molnar <mingo@redhat.com>
  */
-#ifndef _ASM_MUTEX_H
-#define _ASM_MUTEX_H
+#ifndef ASM_X86__MUTEX_64_H
+#define ASM_X86__MUTEX_64_H
 
 /**
  * __mutex_fastpath_lock - decrement and call function if negative
@@ -97,4 +97,4 @@ static inline int __mutex_fastpath_trylock(atomic_t *count,
                 return 0;
 }
 
-#endif
+#endif /* ASM_X86__MUTEX_64_H */
diff --git a/include/asm-x86/nmi.h b/include/asm-x86/nmi.h
index 21f8d0202a82..a53f829a97c5 100644
--- a/include/asm-x86/nmi.h
+++ b/include/asm-x86/nmi.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_NMI_H_
-#define _ASM_X86_NMI_H_
+#ifndef ASM_X86__NMI_H
+#define ASM_X86__NMI_H
 
 #include <linux/pm.h>
 #include <asm/irq.h>
@@ -15,10 +15,6 @@
  */
 int do_nmi_callback(struct pt_regs *regs, int cpu);
 
-#ifdef CONFIG_X86_64
-extern void default_do_nmi(struct pt_regs *);
-#endif
-
 extern void die_nmi(char *str, struct pt_regs *regs, int do_panic);
 extern int check_nmi_watchdog(void);
 extern int nmi_watchdog_enabled;
@@ -34,6 +30,7 @@ extern void stop_apic_nmi_watchdog(void *);
 extern void disable_timer_nmi_watchdog(void);
 extern void enable_timer_nmi_watchdog(void);
 extern int nmi_watchdog_tick(struct pt_regs *regs, unsigned reason);
+extern void cpu_nmi_set_wd_enabled(void);
 
 extern atomic_t nmi_active;
 extern unsigned int nmi_watchdog;
@@ -81,4 +78,4 @@ void enable_lapic_nmi_watchdog(void);
 void stop_nmi(void);
 void restart_nmi(void);
 
-#endif
+#endif /* ASM_X86__NMI_H */
diff --git a/include/asm-x86/nops.h b/include/asm-x86/nops.h
index ad0bedd10b89..ae742721ae73 100644
--- a/include/asm-x86/nops.h
+++ b/include/asm-x86/nops.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_NOPS_H
-#define _ASM_NOPS_H 1
+#ifndef ASM_X86__NOPS_H
+#define ASM_X86__NOPS_H
 
 /* Define nops for use with alternative() */
 
@@ -115,4 +115,4 @@
 
 #define ASM_NOP_MAX 8
 
-#endif
+#endif /* ASM_X86__NOPS_H */
diff --git a/include/asm-x86/numa_32.h b/include/asm-x86/numa_32.h
index 220d7b7707a0..44cb07855c5b 100644
--- a/include/asm-x86/numa_32.h
+++ b/include/asm-x86/numa_32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_32_NUMA_H
-#define _ASM_X86_32_NUMA_H 1
+#ifndef ASM_X86__NUMA_32_H
+#define ASM_X86__NUMA_32_H
 
 extern int pxm_to_nid(int pxm);
 extern void numa_remove_cpu(int cpu);
@@ -8,4 +8,4 @@ extern void numa_remove_cpu(int cpu);
 extern void set_highmem_pages_init(void);
 #endif
 
-#endif /* _ASM_X86_32_NUMA_H */
+#endif /* ASM_X86__NUMA_32_H */
diff --git a/include/asm-x86/numa_64.h b/include/asm-x86/numa_64.h
index 3830094434a9..15c990395b02 100644
--- a/include/asm-x86/numa_64.h
+++ b/include/asm-x86/numa_64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X8664_NUMA_H
-#define _ASM_X8664_NUMA_H 1
+#ifndef ASM_X86__NUMA_64_H
+#define ASM_X86__NUMA_64_H
 
 #include <linux/nodemask.h>
 #include <asm/apicdef.h>
@@ -40,4 +40,4 @@ static inline void numa_add_cpu(int cpu, int node)	{ }
 static inline void numa_remove_cpu(int cpu)             { }
 #endif
 
-#endif
+#endif /* ASM_X86__NUMA_64_H */
diff --git a/include/asm-x86/numaq.h b/include/asm-x86/numaq.h
index 34b92d581fa3..124bf7d4b70a 100644
--- a/include/asm-x86/numaq.h
+++ b/include/asm-x86/numaq.h
@@ -23,8 +23,8 @@
  * Send feedback to <gone@us.ibm.com>
  */
 
-#ifndef NUMAQ_H
-#define NUMAQ_H
+#ifndef ASM_X86__NUMAQ_H
+#define ASM_X86__NUMAQ_H
 
 #ifdef CONFIG_X86_NUMAQ
 
@@ -165,5 +165,5 @@ static inline int get_memcfg_numaq(void)
         return 0;
 }
 #endif /* CONFIG_X86_NUMAQ */
-#endif /* NUMAQ_H */
+#endif /* ASM_X86__NUMAQ_H */
 
diff --git a/include/asm-x86/mach-numaq/mach_apic.h b/include/asm-x86/numaq/apic.h
index d802465e026a..a8344ba6ea15 100644
--- a/include/asm-x86/mach-numaq/mach_apic.h
+++ b/include/asm-x86/numaq/apic.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
+#ifndef __ASM_NUMAQ_APIC_H
+#define __ASM_NUMAQ_APIC_H
 
 #include <asm/io.h>
 #include <linux/mmzone.h>
@@ -135,4 +135,4 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
         return cpuid_apic >> index_msb;
 }
 
-#endif /* __ASM_MACH_APIC_H */
+#endif /* __ASM_NUMAQ_APIC_H */
diff --git a/include/asm-x86/mach-numaq/mach_apicdef.h b/include/asm-x86/numaq/apicdef.h
index bf439d0690f5..e012a46cc22a 100644
--- a/include/asm-x86/mach-numaq/mach_apicdef.h
+++ b/include/asm-x86/numaq/apicdef.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_APICDEF_H
-#define __ASM_MACH_APICDEF_H
+#ifndef __ASM_NUMAQ_APICDEF_H
+#define __ASM_NUMAQ_APICDEF_H
 
 
 #define APIC_ID_MASK (0xF<<24)
diff --git a/include/asm-x86/mach-numaq/mach_ipi.h b/include/asm-x86/numaq/ipi.h
index c6044488e9e6..935588d286cf 100644
--- a/include/asm-x86/mach-numaq/mach_ipi.h
+++ b/include/asm-x86/numaq/ipi.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_IPI_H
-#define __ASM_MACH_IPI_H
+#ifndef __ASM_NUMAQ_IPI_H
+#define __ASM_NUMAQ_IPI_H
 
 void send_IPI_mask_sequence(cpumask_t, int vector);
 
@@ -22,4 +22,4 @@ static inline void send_IPI_all(int vector)
         send_IPI_mask(cpu_online_map, vector);
 }
 
-#endif /* __ASM_MACH_IPI_H */
+#endif /* __ASM_NUMAQ_IPI_H */
diff --git a/include/asm-x86/mach-numaq/mach_mpparse.h b/include/asm-x86/numaq/mpparse.h
index 626aef6b155f..252292e077b6 100644
--- a/include/asm-x86/mach-numaq/mach_mpparse.h
+++ b/include/asm-x86/numaq/mpparse.h
@@ -1,7 +1,7 @@
-#ifndef __ASM_MACH_MPPARSE_H
-#define __ASM_MACH_MPPARSE_H
+#ifndef __ASM_NUMAQ_MPPARSE_H
+#define __ASM_NUMAQ_MPPARSE_H
 
 extern void numaq_mps_oem_check(struct mp_config_table *mpc, char *oem,
                                 char *productid);
 
-#endif /* __ASM_MACH_MPPARSE_H */
+#endif /* __ASM_NUMAQ_MPPARSE_H */
diff --git a/include/asm-x86/mach-numaq/mach_wakecpu.h b/include/asm-x86/numaq/wakecpu.h
index 00530041a991..c577bda5b1c5 100644
--- a/include/asm-x86/mach-numaq/mach_wakecpu.h
+++ b/include/asm-x86/numaq/wakecpu.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_WAKECPU_H
-#define __ASM_MACH_WAKECPU_H
+#ifndef __ASM_NUMAQ_WAKECPU_H
+#define __ASM_NUMAQ_WAKECPU_H
 
 /* This file copes with machines that wakeup secondary CPUs by NMIs */
 
@@ -40,4 +40,4 @@ static inline void restore_NMI_vector(unsigned short *high, unsigned short *low)
 
 #define inquire_remote_apic(apicid) {}
 
-#endif /* __ASM_MACH_WAKECPU_H */
+#endif /* __ASM_NUMAQ_WAKECPU_H */
diff --git a/include/asm-x86/olpc.h b/include/asm-x86/olpc.h
index 97d47133486f..d7328b1a05c1 100644
--- a/include/asm-x86/olpc.h
+++ b/include/asm-x86/olpc.h
@@ -1,7 +1,7 @@
 /* OLPC machine specific definitions */
 
-#ifndef ASM_OLPC_H_
-#define ASM_OLPC_H_
+#ifndef ASM_X86__OLPC_H
+#define ASM_X86__OLPC_H
 
 #include <asm/geode.h>
 
@@ -129,4 +129,4 @@ extern int olpc_ec_mask_unset(uint8_t bits);
 #define OLPC_GPIO_LID           geode_gpio(26)
 #define OLPC_GPIO_ECSCI         geode_gpio(27)
 
-#endif
+#endif /* ASM_X86__OLPC_H */
diff --git a/include/asm-x86/page.h b/include/asm-x86/page.h
index 49982110e4d9..d4f1d5791fc1 100644
--- a/include/asm-x86/page.h
+++ b/include/asm-x86/page.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PAGE_H
-#define _ASM_X86_PAGE_H
+#ifndef ASM_X86__PAGE_H
+#define ASM_X86__PAGE_H
 
 #include <linux/const.h>
 
@@ -57,6 +57,7 @@ typedef struct { pgdval_t pgd; } pgd_t;
 typedef struct { pgprotval_t pgprot; } pgprot_t;
 
 extern int page_is_ram(unsigned long pagenr);
+extern int pagerange_is_ram(unsigned long start, unsigned long end);
 extern int devmem_is_allowed(unsigned long pagenr);
 extern void map_devmem(unsigned long pfn, unsigned long size,
                        pgprot_t vma_prot);
@@ -178,6 +179,7 @@ static inline pteval_t native_pte_flags(pte_t pte)
 #endif  /* CONFIG_PARAVIRT */
 
 #define __pa(x)         __phys_addr((unsigned long)(x))
+#define __pa_nodebug(x) __phys_addr_nodebug((unsigned long)(x))
 /* __pa_symbol should be used for C visible symbols.
    This seems to be the official gcc blessed way to do such arithmetic. */
 #define __pa_symbol(x)  __pa(__phys_reloc_hide((unsigned long)(x)))
@@ -187,9 +189,14 @@ static inline pteval_t native_pte_flags(pte_t pte)
 #define __boot_va(x)            __va(x)
 #define __boot_pa(x)            __pa(x)
 
+/*
+ * virt_to_page(kaddr) returns a valid pointer if and only if
+ * virt_addr_valid(kaddr) returns true.
+ */
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
 #define pfn_to_kaddr(pfn)      __va((pfn) << PAGE_SHIFT)
-#define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
+extern bool __virt_addr_valid(unsigned long kaddr);
+#define virt_addr_valid(kaddr)  __virt_addr_valid((unsigned long) (kaddr))
 
 #endif  /* __ASSEMBLY__ */
 
@@ -199,4 +206,4 @@ static inline pteval_t native_pte_flags(pte_t pte)
 #define __HAVE_ARCH_GATE_AREA 1
 
 #endif  /* __KERNEL__ */
-#endif  /* _ASM_X86_PAGE_H */
+#endif /* ASM_X86__PAGE_H */
diff --git a/include/asm-x86/page_32.h b/include/asm-x86/page_32.h
index ab8528793f08..bdf5dba4cfb0 100644
--- a/include/asm-x86/page_32.h
+++ b/include/asm-x86/page_32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PAGE_32_H
-#define _ASM_X86_PAGE_32_H
+#ifndef ASM_X86__PAGE_32_H
+#define ASM_X86__PAGE_32_H
 
 /*
  * This handles the memory map.
@@ -20,6 +20,12 @@
 #endif
 #define THREAD_SIZE     (PAGE_SIZE << THREAD_ORDER)
 
+#define STACKFAULT_STACK 0
+#define DOUBLEFAULT_STACK 1
+#define NMI_STACK 0
+#define DEBUG_STACK 0
+#define MCE_STACK 0
+#define N_EXCEPTION_STACKS 1
 
 #ifdef CONFIG_X86_PAE
 /* 44=32+12, the limit we can fit into an unsigned long pfn */
@@ -33,7 +39,6 @@ typedef u64	pmdval_t;
 typedef u64     pudval_t;
 typedef u64     pgdval_t;
 typedef u64     pgprotval_t;
-typedef u64     phys_addr_t;
 
 typedef union {
         struct {
@@ -54,7 +59,6 @@ typedef unsigned long	pmdval_t;
 typedef unsigned long   pudval_t;
 typedef unsigned long   pgdval_t;
 typedef unsigned long   pgprotval_t;
-typedef unsigned long   phys_addr_t;
 
 typedef union {
         pteval_t pte;
@@ -73,7 +77,12 @@ typedef struct page *pgtable_t;
 #endif
 
 #ifndef __ASSEMBLY__
-#define __phys_addr(x)          ((x) - PAGE_OFFSET)
+#define __phys_addr_nodebug(x)  ((x) - PAGE_OFFSET)
+#ifdef CONFIG_DEBUG_VIRTUAL
+extern unsigned long __phys_addr(unsigned long);
+#else
+#define __phys_addr(x)          __phys_addr_nodebug(x)
+#endif
 #define __phys_reloc_hide(x)    RELOC_HIDE((x), 0)
 
 #ifdef CONFIG_FLATMEM
@@ -89,13 +98,11 @@ extern int nx_enabled;
 extern unsigned int __VMALLOC_RESERVE;
 extern int sysctl_legacy_va_layout;
 
-#define VMALLOC_RESERVE         ((unsigned long)__VMALLOC_RESERVE)
-#define MAXMEM                  (-__PAGE_OFFSET - __VMALLOC_RESERVE)
-
 extern void find_low_pfn_range(void);
 extern unsigned long init_memory_mapping(unsigned long start,
                                          unsigned long end);
 extern void initmem_init(unsigned long, unsigned long);
+extern void free_initmem(void);
 extern void setup_bootmem_allocator(void);
 
 
@@ -126,4 +133,4 @@ static inline void copy_page(void *to, void *from)
 #endif  /* CONFIG_X86_3DNOW */
 #endif  /* !__ASSEMBLY__ */
 
-#endif /* _ASM_X86_PAGE_32_H */
+#endif /* ASM_X86__PAGE_32_H */
diff --git a/include/asm-x86/page_64.h b/include/asm-x86/page_64.h
index c6916c83e6b1..49380b8c7e25 100644
--- a/include/asm-x86/page_64.h
+++ b/include/asm-x86/page_64.h
@@ -1,5 +1,5 @@
-#ifndef _X86_64_PAGE_H
-#define _X86_64_PAGE_H
+#ifndef ASM_X86__PAGE_64_H
+#define ASM_X86__PAGE_64_H
 
 #define PAGETABLE_LEVELS        4
 
@@ -79,7 +79,6 @@ typedef unsigned long	pmdval_t;
 typedef unsigned long   pudval_t;
 typedef unsigned long   pgdval_t;
 typedef unsigned long   pgprotval_t;
-typedef unsigned long   phys_addr_t;
 
 typedef struct page *pgtable_t;
 
@@ -91,6 +90,7 @@ extern unsigned long init_memory_mapping(unsigned long start,
                                          unsigned long end);
 
 extern void initmem_init(unsigned long start_pfn, unsigned long end_pfn);
+extern void free_initmem(void);
 
 extern void init_extra_mapping_uc(unsigned long phys, unsigned long size);
 extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
@@ -102,4 +102,4 @@ extern void init_extra_mapping_wb(unsigned long phys, unsigned long size);
 #endif
 
 
-#endif /* _X86_64_PAGE_H */
+#endif /* ASM_X86__PAGE_64_H */
diff --git a/include/asm-x86/param.h b/include/asm-x86/param.h
index 6f0d0422f4ca..0009cfb11a5f 100644
--- a/include/asm-x86/param.h
+++ b/include/asm-x86/param.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PARAM_H
-#define _ASM_X86_PARAM_H
+#ifndef ASM_X86__PARAM_H
+#define ASM_X86__PARAM_H
 
 #ifdef __KERNEL__
 # define HZ             CONFIG_HZ       /* Internal kernel timer frequency */
@@ -19,4 +19,4 @@
 
 #define MAXHOSTNAMELEN  64      /* max length of hostname */
 
-#endif /* _ASM_X86_PARAM_H */
+#endif /* ASM_X86__PARAM_H */
diff --git a/include/asm-x86/paravirt.h b/include/asm-x86/paravirt.h
index fbbde93f12d6..8d6ae2f760d0 100644
--- a/include/asm-x86/paravirt.h
+++ b/include/asm-x86/paravirt.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_PARAVIRT_H
-#define __ASM_PARAVIRT_H
+#ifndef ASM_X86__PARAVIRT_H
+#define ASM_X86__PARAVIRT_H
 /* Various instructions on x86 need to be replaced for
  * para-virtualization: those hooks are defined here. */
 
@@ -124,6 +124,9 @@ struct pv_cpu_ops {
                                 int entrynum, const void *desc, int size);
         void (*write_idt_entry)(gate_desc *,
                                 int entrynum, const gate_desc *gate);
+        void (*alloc_ldt)(struct desc_struct *ldt, unsigned entries);
+        void (*free_ldt)(struct desc_struct *ldt, unsigned entries);
+
         void (*load_sp0)(struct tss_struct *tss, struct thread_struct *t);
 
         void (*set_iopl_mask)(unsigned mask);
@@ -137,6 +140,7 @@ struct pv_cpu_ops {
 
         /* MSR, PMC and TSR operations.
            err = 0/-EFAULT.  wrmsr returns 0/-EFAULT. */
+        u64 (*read_msr_amd)(unsigned int msr, int *err);
         u64 (*read_msr)(unsigned int msr, int *err);
         int (*write_msr)(unsigned int msr, unsigned low, unsigned high);
 
@@ -200,12 +204,6 @@ struct pv_irq_ops {
 
 struct pv_apic_ops {
 #ifdef CONFIG_X86_LOCAL_APIC
-        /*
-         * Direct APIC operations, principally for VMI.  Ideally
-         * these shouldn't be in this interface.
-         */
-        void (*apic_write)(unsigned long reg, u32 v);
-        u32 (*apic_read)(unsigned long reg);
         void (*setup_boot_clock)(void);
         void (*setup_secondary_clock)(void);
 
@@ -257,13 +255,13 @@ struct pv_mmu_ops {
          * Hooks for allocating/releasing pagetable pages when they're
          * attached to a pagetable
          */
-        void (*alloc_pte)(struct mm_struct *mm, u32 pfn);
-        void (*alloc_pmd)(struct mm_struct *mm, u32 pfn);
-        void (*alloc_pmd_clone)(u32 pfn, u32 clonepfn, u32 start, u32 count);
-        void (*alloc_pud)(struct mm_struct *mm, u32 pfn);
-        void (*release_pte)(u32 pfn);
-        void (*release_pmd)(u32 pfn);
-        void (*release_pud)(u32 pfn);
+        void (*alloc_pte)(struct mm_struct *mm, unsigned long pfn);
+        void (*alloc_pmd)(struct mm_struct *mm, unsigned long pfn);
+        void (*alloc_pmd_clone)(unsigned long pfn, unsigned long clonepfn, unsigned long start, unsigned long count);
+        void (*alloc_pud)(struct mm_struct *mm, unsigned long pfn);
+        void (*release_pte)(unsigned long pfn);
+        void (*release_pmd)(unsigned long pfn);
+        void (*release_pud)(unsigned long pfn);
 
         /* Pagetable manipulation functions */
         void (*set_pte)(pte_t *ptep, pte_t pteval);
@@ -330,6 +328,7 @@ struct pv_lock_ops {
         int (*spin_is_locked)(struct raw_spinlock *lock);
         int (*spin_is_contended)(struct raw_spinlock *lock);
         void (*spin_lock)(struct raw_spinlock *lock);
+        void (*spin_lock_flags)(struct raw_spinlock *lock, unsigned long flags);
         int (*spin_trylock)(struct raw_spinlock *lock);
         void (*spin_unlock)(struct raw_spinlock *lock);
 };
@@ -726,6 +725,10 @@ static inline u64 paravirt_read_msr(unsigned msr, int *err)
 {
         return PVOP_CALL2(u64, pv_cpu_ops.read_msr, msr, err);
 }
+static inline u64 paravirt_read_msr_amd(unsigned msr, int *err)
+{
+        return PVOP_CALL2(u64, pv_cpu_ops.read_msr_amd, msr, err);
+}
 static inline int paravirt_write_msr(unsigned msr, unsigned low, unsigned high)
 {
         return PVOP_CALL3(int, pv_cpu_ops.write_msr, msr, low, high);
@@ -771,6 +774,13 @@ static inline int rdmsrl_safe(unsigned msr, unsigned long long *p)
         *p = paravirt_read_msr(msr, &err);
         return err;
 }
+static inline int rdmsrl_amd_safe(unsigned msr, unsigned long long *p)
+{
+        int err;
+
+        *p = paravirt_read_msr_amd(msr, &err);
+        return err;
+}
 
 static inline u64 paravirt_read_tsc(void)
 {
@@ -824,6 +834,16 @@ do {							\
         (aux) = __aux;                                  \
 } while (0)
 
+static inline void paravirt_alloc_ldt(struct desc_struct *ldt, unsigned entries)
+{
+        PVOP_VCALL2(pv_cpu_ops.alloc_ldt, ldt, entries);
+}
+
+static inline void paravirt_free_ldt(struct desc_struct *ldt, unsigned entries)
+{
+        PVOP_VCALL2(pv_cpu_ops.free_ldt, ldt, entries);
+}
+
 static inline void load_TR_desc(void)
 {
         PVOP_VCALL0(pv_cpu_ops.load_tr_desc);
@@ -898,19 +918,6 @@ static inline void slow_down_io(void)
 }
 
 #ifdef CONFIG_X86_LOCAL_APIC
-/*
- * Basic functions accessing APICs.
- */
-static inline void apic_write(unsigned long reg, u32 v)
-{
-        PVOP_VCALL2(pv_apic_ops.apic_write, reg, v);
-}
-
-static inline u32 apic_read(unsigned long reg)
-{
-        return PVOP_CALL1(unsigned long, pv_apic_ops.apic_read, reg);
-}
-
 static inline void setup_boot_clock(void)
 {
         PVOP_VCALL0(pv_apic_ops.setup_boot_clock);
@@ -993,35 +1000,35 @@ static inline void paravirt_pgd_free(struct mm_struct *mm, pgd_t *pgd)
         PVOP_VCALL2(pv_mmu_ops.pgd_free, mm, pgd);
 }
 
-static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned pfn)
+static inline void paravirt_alloc_pte(struct mm_struct *mm, unsigned long pfn)
 {
         PVOP_VCALL2(pv_mmu_ops.alloc_pte, mm, pfn);
 }
-static inline void paravirt_release_pte(unsigned pfn)
+static inline void paravirt_release_pte(unsigned long pfn)
 {
         PVOP_VCALL1(pv_mmu_ops.release_pte, pfn);
 }
 
-static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned pfn)
+static inline void paravirt_alloc_pmd(struct mm_struct *mm, unsigned long pfn)
 {
         PVOP_VCALL2(pv_mmu_ops.alloc_pmd, mm, pfn);
 }
 
-static inline void paravirt_alloc_pmd_clone(unsigned pfn, unsigned clonepfn,
-                                            unsigned start, unsigned count)
+static inline void paravirt_alloc_pmd_clone(unsigned long pfn, unsigned long clonepfn,
+                                            unsigned long start, unsigned long count)
 {
         PVOP_VCALL4(pv_mmu_ops.alloc_pmd_clone, pfn, clonepfn, start, count);
 }
-static inline void paravirt_release_pmd(unsigned pfn)
+static inline void paravirt_release_pmd(unsigned long pfn)
 {
         PVOP_VCALL1(pv_mmu_ops.release_pmd, pfn);
 }
 
-static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned pfn)
+static inline void paravirt_alloc_pud(struct mm_struct *mm, unsigned long pfn)
 {
         PVOP_VCALL2(pv_mmu_ops.alloc_pud, mm, pfn);
 }
-static inline void paravirt_release_pud(unsigned pfn)
+static inline void paravirt_release_pud(unsigned long pfn)
 {
         PVOP_VCALL1(pv_mmu_ops.release_pud, pfn);
 }
@@ -1401,6 +1408,12 @@ static __always_inline void __raw_spin_lock(struct raw_spinlock *lock)
         PVOP_VCALL1(pv_lock_ops.spin_lock, lock);
 }
 
+static __always_inline void __raw_spin_lock_flags(struct raw_spinlock *lock,
+                                                  unsigned long flags)
+{
+        PVOP_VCALL2(pv_lock_ops.spin_lock_flags, lock, flags);
+}
+
 static __always_inline int __raw_spin_trylock(struct raw_spinlock *lock)
 {
         return PVOP_CALL1(int, pv_lock_ops.spin_trylock, lock);
@@ -1634,4 +1647,4 @@ static inline unsigned long __raw_local_irq_save(void)
 
 #endif /* __ASSEMBLY__ */
 #endif /* CONFIG_PARAVIRT */
-#endif  /* __ASM_PARAVIRT_H */
+#endif /* ASM_X86__PARAVIRT_H */
diff --git a/include/asm-x86/parport.h b/include/asm-x86/parport.h
index 3c4ffeb467e9..2e3dda4dc3d9 100644
--- a/include/asm-x86/parport.h
+++ b/include/asm-x86/parport.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PARPORT_H
-#define _ASM_X86_PARPORT_H
+#ifndef ASM_X86__PARPORT_H
+#define ASM_X86__PARPORT_H
 
 static int __devinit parport_pc_find_isa_ports(int autoirq, int autodma);
 static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
@@ -7,4 +7,4 @@ static int __devinit parport_pc_find_nonpci_ports(int autoirq, int autodma)
         return parport_pc_find_isa_ports(autoirq, autodma);
 }
 
-#endif /* _ASM_X86_PARPORT_H */
+#endif /* ASM_X86__PARPORT_H */
diff --git a/include/asm-x86/pat.h b/include/asm-x86/pat.h
index 7edc47307217..482c3e3f9879 100644
--- a/include/asm-x86/pat.h
+++ b/include/asm-x86/pat.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_PAT_H
-#define _ASM_PAT_H
+#ifndef ASM_X86__PAT_H
+#define ASM_X86__PAT_H
 
 #include <linux/types.h>
 
@@ -19,4 +19,4 @@ extern int free_memtype(u64 start, u64 end);
 
 extern void pat_disable(char *reason);
 
-#endif
+#endif /* ASM_X86__PAT_H */
diff --git a/include/asm-x86/pci-direct.h b/include/asm-x86/pci-direct.h
index 80c775d9fe20..da42be07b690 100644
--- a/include/asm-x86/pci-direct.h
+++ b/include/asm-x86/pci-direct.h
@@ -1,5 +1,5 @@
-#ifndef ASM_PCI_DIRECT_H
-#define ASM_PCI_DIRECT_H 1
+#ifndef ASM_X86__PCI_DIRECT_H
+#define ASM_X86__PCI_DIRECT_H
 
 #include <linux/types.h>
 
@@ -18,4 +18,4 @@ extern int early_pci_allowed(void);
 extern unsigned int pci_early_dump_regs;
 extern void early_dump_pci_device(u8 bus, u8 slot, u8 func);
 extern void early_dump_pci_devices(void);
-#endif
+#endif /* ASM_X86__PCI_DIRECT_H */
diff --git a/include/asm-x86/pci.h b/include/asm-x86/pci.h
index 2db14cf17db8..602583192991 100644
--- a/include/asm-x86/pci.h
+++ b/include/asm-x86/pci.h
@@ -1,5 +1,5 @@
-#ifndef __x86_PCI_H
-#define __x86_PCI_H
+#ifndef ASM_X86__PCI_H
+#define ASM_X86__PCI_H
 
 #include <linux/mm.h> /* for struct page */
 #include <linux/types.h>
@@ -111,4 +111,4 @@ static inline cpumask_t __pcibus_to_cpumask(struct pci_bus *bus)
 }
 #endif
 
-#endif
+#endif /* ASM_X86__PCI_H */
diff --git a/include/asm-x86/pci_32.h b/include/asm-x86/pci_32.h
index a50d46851285..3f2288207c0c 100644
--- a/include/asm-x86/pci_32.h
+++ b/include/asm-x86/pci_32.h
@@ -1,5 +1,5 @@
-#ifndef __i386_PCI_H
-#define __i386_PCI_H
+#ifndef ASM_X86__PCI_32_H
+#define ASM_X86__PCI_32_H
 
 
 #ifdef __KERNEL__
@@ -31,4 +31,4 @@ struct pci_dev;
 #endif /* __KERNEL__ */
 
 
-#endif /* __i386_PCI_H */
+#endif /* ASM_X86__PCI_32_H */
diff --git a/include/asm-x86/pci_64.h b/include/asm-x86/pci_64.h
index f330234ffa5c..f72e12d5770e 100644
--- a/include/asm-x86/pci_64.h
+++ b/include/asm-x86/pci_64.h
@@ -1,5 +1,5 @@
-#ifndef __x8664_PCI_H
-#define __x8664_PCI_H
+#ifndef ASM_X86__PCI_64_H
+#define ASM_X86__PCI_64_H
 
 #ifdef __KERNEL__
 
@@ -63,4 +63,4 @@ extern void pci_iommu_alloc(void);
 
 #endif /* __KERNEL__ */
 
-#endif /* __x8664_PCI_H */
+#endif /* ASM_X86__PCI_64_H */
diff --git a/include/asm-x86/pda.h b/include/asm-x86/pda.h
index b34e9a7cc80b..80860afffbdb 100644
--- a/include/asm-x86/pda.h
+++ b/include/asm-x86/pda.h
@@ -1,5 +1,5 @@
-#ifndef X86_64_PDA_H
-#define X86_64_PDA_H
+#ifndef ASM_X86__PDA_H
+#define ASM_X86__PDA_H
 
 #ifndef __ASSEMBLY__
 #include <linux/stddef.h>
@@ -134,4 +134,4 @@ do {									\
 
 #define PDA_STACKOFFSET (5*8)
 
-#endif
+#endif /* ASM_X86__PDA_H */
diff --git a/include/asm-x86/percpu.h b/include/asm-x86/percpu.h
index f643a3a92da0..e10a1d0678cf 100644
--- a/include/asm-x86/percpu.h
+++ b/include/asm-x86/percpu.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PERCPU_H_
-#define _ASM_X86_PERCPU_H_
+#ifndef ASM_X86__PERCPU_H
+#define ASM_X86__PERCPU_H
 
 #ifdef CONFIG_X86_64
 #include <linux/compiler.h>
@@ -215,4 +215,4 @@ do {							\
 
 #endif  /* !CONFIG_SMP */
 
-#endif /* _ASM_X86_PERCPU_H_ */
+#endif /* ASM_X86__PERCPU_H */
diff --git a/include/asm-x86/pgalloc.h b/include/asm-x86/pgalloc.h
index d63ea431cb3b..3cd23adedae8 100644
--- a/include/asm-x86/pgalloc.h
+++ b/include/asm-x86/pgalloc.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PGALLOC_H
-#define _ASM_X86_PGALLOC_H
+#ifndef ASM_X86__PGALLOC_H
+#define ASM_X86__PGALLOC_H
 
 #include <linux/threads.h>
 #include <linux/mm.h>           /* for struct page */
@@ -111,4 +111,4 @@ extern void __pud_free_tlb(struct mmu_gather *tlb, pud_t *pud);
 #endif  /* PAGETABLE_LEVELS > 3 */
 #endif  /* PAGETABLE_LEVELS > 2 */
 
-#endif  /* _ASM_X86_PGALLOC_H */
+#endif /* ASM_X86__PGALLOC_H */
diff --git a/include/asm-x86/pgtable-2level-defs.h b/include/asm-x86/pgtable-2level-defs.h
index 0f71c9f13da4..7ec48f4e5347 100644
--- a/include/asm-x86/pgtable-2level-defs.h
+++ b/include/asm-x86/pgtable-2level-defs.h
@@ -1,5 +1,5 @@
-#ifndef _I386_PGTABLE_2LEVEL_DEFS_H
-#define _I386_PGTABLE_2LEVEL_DEFS_H
+#ifndef ASM_X86__PGTABLE_2LEVEL_DEFS_H
+#define ASM_X86__PGTABLE_2LEVEL_DEFS_H
 
 #define SHARED_KERNEL_PMD       0
 
@@ -17,4 +17,4 @@
 
 #define PTRS_PER_PTE    1024
 
-#endif /* _I386_PGTABLE_2LEVEL_DEFS_H */
+#endif /* ASM_X86__PGTABLE_2LEVEL_DEFS_H */
diff --git a/include/asm-x86/pgtable-2level.h b/include/asm-x86/pgtable-2level.h
index 46bc52c0eae1..81762081dcd8 100644
--- a/include/asm-x86/pgtable-2level.h
+++ b/include/asm-x86/pgtable-2level.h
@@ -1,5 +1,5 @@
-#ifndef _I386_PGTABLE_2LEVEL_H
-#define _I386_PGTABLE_2LEVEL_H
+#ifndef ASM_X86__PGTABLE_2LEVEL_H
+#define ASM_X86__PGTABLE_2LEVEL_H
 
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, (e).pte_low)
@@ -53,9 +53,7 @@ static inline pte_t native_ptep_get_and_clear(pte_t *xp)
 #define native_ptep_get_and_clear(xp) native_local_ptep_get_and_clear(xp)
 #endif
 
-#define pte_page(x)             pfn_to_page(pte_pfn(x))
 #define pte_none(x)             (!(x).pte_low)
-#define pte_pfn(x)              (pte_val(x) >> PAGE_SHIFT)
 
 /*
  * Bits 0, 6 and 7 are taken, split up the 29 bits of offset
@@ -78,4 +76,4 @@ static inline pte_t native_ptep_get_and_clear(pte_t *xp)
 #define __pte_to_swp_entry(pte)         ((swp_entry_t) { (pte).pte_low })
 #define __swp_entry_to_pte(x)           ((pte_t) { .pte = (x).val })
 
-#endif /* _I386_PGTABLE_2LEVEL_H */
+#endif /* ASM_X86__PGTABLE_2LEVEL_H */
diff --git a/include/asm-x86/pgtable-3level-defs.h b/include/asm-x86/pgtable-3level-defs.h
index 448ac9516314..c05fe6ff3720 100644
--- a/include/asm-x86/pgtable-3level-defs.h
+++ b/include/asm-x86/pgtable-3level-defs.h
@@ -1,5 +1,5 @@
-#ifndef _I386_PGTABLE_3LEVEL_DEFS_H
-#define _I386_PGTABLE_3LEVEL_DEFS_H
+#ifndef ASM_X86__PGTABLE_3LEVEL_DEFS_H
+#define ASM_X86__PGTABLE_3LEVEL_DEFS_H
 
 #ifdef CONFIG_PARAVIRT
 #define SHARED_KERNEL_PMD       (pv_info.shared_kernel_pmd)
@@ -25,4 +25,4 @@
  */
 #define PTRS_PER_PTE    512
 
-#endif /* _I386_PGTABLE_3LEVEL_DEFS_H */
+#endif /* ASM_X86__PGTABLE_3LEVEL_DEFS_H */
diff --git a/include/asm-x86/pgtable-3level.h b/include/asm-x86/pgtable-3level.h
index 105057f34032..75f4276b5ddb 100644
--- a/include/asm-x86/pgtable-3level.h
+++ b/include/asm-x86/pgtable-3level.h
@@ -1,5 +1,5 @@
-#ifndef _I386_PGTABLE_3LEVEL_H
-#define _I386_PGTABLE_3LEVEL_H
+#ifndef ASM_X86__PGTABLE_3LEVEL_H
+#define ASM_X86__PGTABLE_3LEVEL_H
 
 /*
  * Intel Physical Address Extension (PAE) Mode - three-level page
@@ -151,18 +151,11 @@ static inline int pte_same(pte_t a, pte_t b)
         return a.pte_low == b.pte_low && a.pte_high == b.pte_high;
 }
 
-#define pte_page(x)     pfn_to_page(pte_pfn(x))
-
 static inline int pte_none(pte_t pte)
 {
         return !pte.pte_low && !pte.pte_high;
 }
 
-static inline unsigned long pte_pfn(pte_t pte)
-{
-        return (pte_val(pte) & PTE_PFN_MASK) >> PAGE_SHIFT;
-}
-
 /*
  * Bits 0, 6 and 7 are taken in the low part of the pte,
  * put the 32 bits of offset into the high part.
@@ -179,4 +172,4 @@ static inline unsigned long pte_pfn(pte_t pte)
 #define __pte_to_swp_entry(pte)         ((swp_entry_t){ (pte).pte_high })
 #define __swp_entry_to_pte(x)           ((pte_t){ { .pte_high = (x).val } })
 
-#endif /* _I386_PGTABLE_3LEVEL_H */
+#endif /* ASM_X86__PGTABLE_3LEVEL_H */
diff --git a/include/asm-x86/pgtable.h b/include/asm-x86/pgtable.h
index 04caa2f544df..88a53b1a17f0 100644
--- a/include/asm-x86/pgtable.h
+++ b/include/asm-x86/pgtable.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PGTABLE_H
-#define _ASM_X86_PGTABLE_H
+#ifndef ASM_X86__PGTABLE_H
+#define ASM_X86__PGTABLE_H
 
 #define FIRST_USER_ADDRESS      0
 
@@ -15,10 +15,11 @@
 #define _PAGE_BIT_PAT           7       /* on 4KB pages */
 #define _PAGE_BIT_GLOBAL        8       /* Global TLB entry PPro+ */
 #define _PAGE_BIT_UNUSED1       9       /* available for programmer */
-#define _PAGE_BIT_UNUSED2       10
+#define _PAGE_BIT_IOMAP         10      /* flag used to indicate IO mapping */
 #define _PAGE_BIT_UNUSED3       11
 #define _PAGE_BIT_PAT_LARGE     12      /* On 2MB or 1GB pages */
 #define _PAGE_BIT_SPECIAL       _PAGE_BIT_UNUSED1
+#define _PAGE_BIT_CPA_TEST      _PAGE_BIT_UNUSED1
 #define _PAGE_BIT_NX           63       /* No execute: only valid after cpuid check */
 
 #define _PAGE_PRESENT   (_AT(pteval_t, 1) << _PAGE_BIT_PRESENT)
@@ -31,11 +32,12 @@
 #define _PAGE_PSE       (_AT(pteval_t, 1) << _PAGE_BIT_PSE)
 #define _PAGE_GLOBAL    (_AT(pteval_t, 1) << _PAGE_BIT_GLOBAL)
 #define _PAGE_UNUSED1   (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED1)
-#define _PAGE_UNUSED2   (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED2)
+#define _PAGE_IOMAP     (_AT(pteval_t, 1) << _PAGE_BIT_IOMAP)
 #define _PAGE_UNUSED3   (_AT(pteval_t, 1) << _PAGE_BIT_UNUSED3)
 #define _PAGE_PAT       (_AT(pteval_t, 1) << _PAGE_BIT_PAT)
 #define _PAGE_PAT_LARGE (_AT(pteval_t, 1) << _PAGE_BIT_PAT_LARGE)
 #define _PAGE_SPECIAL   (_AT(pteval_t, 1) << _PAGE_BIT_SPECIAL)
+#define _PAGE_CPA_TEST  (_AT(pteval_t, 1) << _PAGE_BIT_CPA_TEST)
 #define __HAVE_ARCH_PTE_SPECIAL
 
 #if defined(CONFIG_X86_64) || defined(CONFIG_X86_PAE)
@@ -97,6 +99,11 @@
 #define __PAGE_KERNEL_LARGE_NOCACHE     (__PAGE_KERNEL | _PAGE_CACHE_UC | _PAGE_PSE)
 #define __PAGE_KERNEL_LARGE_EXEC        (__PAGE_KERNEL_EXEC | _PAGE_PSE)
 
+#define __PAGE_KERNEL_IO                (__PAGE_KERNEL | _PAGE_IOMAP)
+#define __PAGE_KERNEL_IO_NOCACHE        (__PAGE_KERNEL_NOCACHE | _PAGE_IOMAP)
+#define __PAGE_KERNEL_IO_UC_MINUS       (__PAGE_KERNEL_UC_MINUS | _PAGE_IOMAP)
+#define __PAGE_KERNEL_IO_WC             (__PAGE_KERNEL_WC | _PAGE_IOMAP)
+
 #define PAGE_KERNEL                     __pgprot(__PAGE_KERNEL)
 #define PAGE_KERNEL_RO                  __pgprot(__PAGE_KERNEL_RO)
 #define PAGE_KERNEL_EXEC                __pgprot(__PAGE_KERNEL_EXEC)
@@ -111,6 +118,11 @@
 #define PAGE_KERNEL_VSYSCALL            __pgprot(__PAGE_KERNEL_VSYSCALL)
 #define PAGE_KERNEL_VSYSCALL_NOCACHE    __pgprot(__PAGE_KERNEL_VSYSCALL_NOCACHE)
 
+#define PAGE_KERNEL_IO                  __pgprot(__PAGE_KERNEL_IO)
+#define PAGE_KERNEL_IO_NOCACHE          __pgprot(__PAGE_KERNEL_IO_NOCACHE)
+#define PAGE_KERNEL_IO_UC_MINUS         __pgprot(__PAGE_KERNEL_IO_UC_MINUS)
+#define PAGE_KERNEL_IO_WC               __pgprot(__PAGE_KERNEL_IO_WC)
+
 /*         xwr */
 #define __P000  PAGE_NONE
 #define __P001  PAGE_READONLY
@@ -130,6 +142,22 @@
 #define __S110  PAGE_SHARED_EXEC
 #define __S111  PAGE_SHARED_EXEC
 
+/*
+ * early identity mapping  pte attrib macros.
+ */
+#ifdef CONFIG_X86_64
+#define __PAGE_KERNEL_IDENT_LARGE_EXEC  __PAGE_KERNEL_LARGE_EXEC
+#else
+/*
+ * For PDE_IDENT_ATTR include USER bit. As the PDE and PTE protection
+ * bits are combined, this will alow user to access the high address mapped
+ * VDSO in the presence of CONFIG_COMPAT_VDSO
+ */
+#define PTE_IDENT_ATTR   0x003          /* PRESENT+RW */
+#define PDE_IDENT_ATTR   0x067          /* PRESENT+RW+USER+DIRTY+ACCESSED */
+#define PGD_IDENT_ATTR   0x001          /* PRESENT (no other attributes) */
+#endif
+
 #ifndef __ASSEMBLY__
 
 /*
@@ -183,9 +211,16 @@ static inline int pte_exec(pte_t pte)
 
 static inline int pte_special(pte_t pte)
 {
-        return pte_val(pte) & _PAGE_SPECIAL;
+        return pte_flags(pte) & _PAGE_SPECIAL;
 }
 
+static inline unsigned long pte_pfn(pte_t pte)
+{
+        return (pte_val(pte) & PTE_PFN_MASK) >> PAGE_SHIFT;
+}
+
+#define pte_page(pte)   pfn_to_page(pte_pfn(pte))
+
 static inline int pmd_large(pmd_t pte)
 {
         return (pmd_val(pte) & (_PAGE_PSE | _PAGE_PRESENT)) ==
@@ -313,6 +348,8 @@ static inline void native_pagetable_setup_start(pgd_t *base) {}
 static inline void native_pagetable_setup_done(pgd_t *base) {}
 #endif
 
+extern int arch_report_meminfo(char *page);
+
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else  /* !CONFIG_PARAVIRT */
@@ -521,4 +558,4 @@ static inline void clone_pgd_range(pgd_t *dst, pgd_t *src, int count)
 #include <asm-generic/pgtable.h>
 #endif  /* __ASSEMBLY__ */
 
-#endif  /* _ASM_X86_PGTABLE_H */
+#endif /* ASM_X86__PGTABLE_H */
diff --git a/include/asm-x86/pgtable_32.h b/include/asm-x86/pgtable_32.h
index 5c3b26567a95..8de702dc7d62 100644
--- a/include/asm-x86/pgtable_32.h
+++ b/include/asm-x86/pgtable_32.h
@@ -1,5 +1,5 @@
-#ifndef _I386_PGTABLE_H
-#define _I386_PGTABLE_H
+#ifndef ASM_X86__PGTABLE_32_H
+#define ASM_X86__PGTABLE_32_H
 
 
 /*
@@ -31,6 +31,7 @@ static inline void pgtable_cache_init(void) { }
 static inline void check_pgt_cache(void) { }
 void paging_init(void);
 
+extern void set_pmd_pfn(unsigned long, unsigned long, pgprot_t);
 
 /*
  * The Linux x86 paging architecture is 'compile-time dual-mode', it
@@ -56,8 +57,7 @@ void paging_init(void);
  * area for the same reason. ;)
  */
 #define VMALLOC_OFFSET  (8 * 1024 * 1024)
-#define VMALLOC_START   (((unsigned long)high_memory + 2 * VMALLOC_OFFSET - 1) \
-                         & ~(VMALLOC_OFFSET - 1))
+#define VMALLOC_START   ((unsigned long)high_memory + VMALLOC_OFFSET)
 #ifdef CONFIG_X86_PAE
 #define LAST_PKMAP 512
 #else
@@ -73,6 +73,8 @@ void paging_init(void);
 # define VMALLOC_END    (FIXADDR_START - 2 * PAGE_SIZE)
 #endif
 
+#define MAXMEM  (VMALLOC_END - PAGE_OFFSET - __VMALLOC_RESERVE)
+
 /*
  * Define this if things work differently on an i386 and an i486:
  * it will (on an i486) warn about kernel memory accesses that are
@@ -186,4 +188,4 @@ do {						\
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
         remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#endif /* _I386_PGTABLE_H */
+#endif /* ASM_X86__PGTABLE_32_H */
diff --git a/include/asm-x86/pgtable_64.h b/include/asm-x86/pgtable_64.h
index 549144d03d99..fde9770e53d1 100644
--- a/include/asm-x86/pgtable_64.h
+++ b/include/asm-x86/pgtable_64.h
@@ -1,5 +1,5 @@
-#ifndef _X86_64_PGTABLE_H
-#define _X86_64_PGTABLE_H
+#ifndef ASM_X86__PGTABLE_64_H
+#define ASM_X86__PGTABLE_64_H
 
 #include <linux/const.h>
 #ifndef __ASSEMBLY__
@@ -175,8 +175,6 @@ static inline int pmd_bad(pmd_t pmd)
 #define pte_present(x)  (pte_val((x)) & (_PAGE_PRESENT | _PAGE_PROTNONE))
 
 #define pages_to_mb(x)  ((x) >> (20 - PAGE_SHIFT))   /* FIXME: is this right? */
-#define pte_page(x)     pfn_to_page(pte_pfn((x)))
-#define pte_pfn(x)      ((pte_val((x)) & __PHYSICAL_MASK) >> PAGE_SHIFT)
 
 /*
  * Macro to mark a page protection value as "uncacheable".
@@ -284,4 +282,4 @@ extern void cleanup_highmap(void);
 #define __HAVE_ARCH_PTE_SAME
 #endif /* !__ASSEMBLY__ */
 
-#endif /* _X86_64_PGTABLE_H */
+#endif /* ASM_X86__PGTABLE_64_H */
diff --git a/include/asm-x86/posix_types_32.h b/include/asm-x86/posix_types_32.h
index b031efda37ec..70cf2bb05939 100644
--- a/include/asm-x86/posix_types_32.h
+++ b/include/asm-x86/posix_types_32.h
@@ -1,5 +1,5 @@
-#ifndef __ARCH_I386_POSIX_TYPES_H
-#define __ARCH_I386_POSIX_TYPES_H
+#ifndef ASM_X86__POSIX_TYPES_32_H
+#define ASM_X86__POSIX_TYPES_32_H
 
 /*
  * This file is generally used by user-level software, so you need to
@@ -82,4 +82,4 @@ do {								\
 
 #endif /* defined(__KERNEL__) */
 
-#endif
+#endif /* ASM_X86__POSIX_TYPES_32_H */
diff --git a/include/asm-x86/posix_types_64.h b/include/asm-x86/posix_types_64.h
index d6624c95854a..388b4e7f4a44 100644
--- a/include/asm-x86/posix_types_64.h
+++ b/include/asm-x86/posix_types_64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_POSIX_TYPES_H
-#define _ASM_X86_64_POSIX_TYPES_H
+#ifndef ASM_X86__POSIX_TYPES_64_H
+#define ASM_X86__POSIX_TYPES_64_H
 
 /*
  * This file is generally used by user-level software, so you need to
@@ -116,4 +116,4 @@ static inline void __FD_ZERO(__kernel_fd_set *p)
 
 #endif /* defined(__KERNEL__) */
 
-#endif
+#endif /* ASM_X86__POSIX_TYPES_64_H */
diff --git a/include/asm-x86/prctl.h b/include/asm-x86/prctl.h
index 52952adef1ca..e7ae34eb4103 100644
--- a/include/asm-x86/prctl.h
+++ b/include/asm-x86/prctl.h
@@ -1,5 +1,5 @@
-#ifndef X86_64_PRCTL_H
-#define X86_64_PRCTL_H 1
+#ifndef ASM_X86__PRCTL_H
+#define ASM_X86__PRCTL_H
 
 #define ARCH_SET_GS 0x1001
 #define ARCH_SET_FS 0x1002
@@ -7,4 +7,4 @@
 #define ARCH_GET_GS 0x1004
 
 
-#endif
+#endif /* ASM_X86__PRCTL_H */
diff --git a/include/asm-x86/processor-cyrix.h b/include/asm-x86/processor-cyrix.h
index 97568ada1f97..1198f2a0e42c 100644
--- a/include/asm-x86/processor-cyrix.h
+++ b/include/asm-x86/processor-cyrix.h
@@ -28,3 +28,11 @@ static inline void setCx86(u8 reg, u8 data)
         outb(reg, 0x22);
         outb(data, 0x23);
 }
+
+#define getCx86_old(reg) ({ outb((reg), 0x22); inb(0x23); })
+
+#define setCx86_old(reg, data) do { \
+        outb((reg), 0x22); \
+        outb((data), 0x23); \
+} while (0)
+
diff --git a/include/asm-x86/processor-flags.h b/include/asm-x86/processor-flags.h
index eff2ecd7fff0..dc5f0712f9fa 100644
--- a/include/asm-x86/processor-flags.h
+++ b/include/asm-x86/processor-flags.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_I386_PROCESSOR_FLAGS_H
-#define __ASM_I386_PROCESSOR_FLAGS_H
+#ifndef ASM_X86__PROCESSOR_FLAGS_H
+#define ASM_X86__PROCESSOR_FLAGS_H
 /* Various flags defined: can be included from assembler. */
 
 /*
@@ -59,6 +59,7 @@
 #define X86_CR4_OSFXSR  0x00000200 /* enable fast FPU save and restore */
 #define X86_CR4_OSXMMEXCPT 0x00000400 /* enable unmasked SSE exceptions */
 #define X86_CR4_VMXE    0x00002000 /* enable VMX virtualization */
+#define X86_CR4_OSXSAVE 0x00040000 /* enable xsave and xrestore */
 
 /*
  * x86-64 Task Priority Register, CR8
@@ -96,4 +97,4 @@
 #endif
 #endif
 
-#endif  /* __ASM_I386_PROCESSOR_FLAGS_H */
+#endif /* ASM_X86__PROCESSOR_FLAGS_H */
diff --git a/include/asm-x86/processor.h b/include/asm-x86/processor.h
index 4df3e2f6fb56..ee7cbb30773a 100644
--- a/include/asm-x86/processor.h
+++ b/include/asm-x86/processor.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_X86_PROCESSOR_H
-#define __ASM_X86_PROCESSOR_H
+#ifndef ASM_X86__PROCESSOR_H
+#define ASM_X86__PROCESSOR_H
 
 #include <asm/processor-flags.h>
 
@@ -20,6 +20,7 @@ struct mm_struct;
 #include <asm/msr.h>
 #include <asm/desc_defs.h>
 #include <asm/nops.h>
+#include <asm/ds.h>
 
 #include <linux/personality.h>
 #include <linux/cpumask.h>
@@ -75,11 +76,11 @@ struct cpuinfo_x86 {
         int                      x86_tlbsize;
         __u8                    x86_virt_bits;
         __u8                    x86_phys_bits;
+#endif
         /* CPUID returned core id bits: */
         __u8                    x86_coreid_bits;
         /* Max extended CPUID function supported: */
         __u32                   extended_cpuid_level;
-#endif
         /* Maximum supported CPUID level, -1=no CPUID: */
         int                     cpuid_level;
         __u32                   x86_capability[NCAPINTS];
@@ -140,6 +141,8 @@ DECLARE_PER_CPU(struct cpuinfo_x86, cpu_info);
 #define current_cpu_data        boot_cpu_data
 #endif
 
+extern const struct seq_operations cpuinfo_op;
+
 static inline int hlt_works(int cpu)
 {
 #ifdef CONFIG_X86_32
@@ -153,6 +156,8 @@ static inline int hlt_works(int cpu)
 
 extern void cpu_detect(struct cpuinfo_x86 *c);
 
+extern struct pt_regs *idle_regs(struct pt_regs *);
+
 extern void early_cpu_init(void);
 extern void identify_boot_cpu(void);
 extern void identify_secondary_cpu(struct cpuinfo_x86 *);
@@ -161,11 +166,8 @@ extern void init_scattered_cpuid_features(struct cpuinfo_x86 *c);
 extern unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c);
 extern unsigned short num_cache_leaves;
 
-#if defined(CONFIG_X86_HT) || defined(CONFIG_X86_64)
+extern void detect_extended_topology(struct cpuinfo_x86 *c);
 extern void detect_ht(struct cpuinfo_x86 *c);
-#else
-static inline void detect_ht(struct cpuinfo_x86 *c) {}
-#endif
 
 static inline void native_cpuid(unsigned int *eax, unsigned int *ebx,
                                 unsigned int *ecx, unsigned int *edx)
@@ -322,7 +324,12 @@ struct i387_fxsave_struct {
         /* 16*16 bytes for each XMM-reg = 256 bytes:                    */
         u32                     xmm_space[64];
 
-        u32                     padding[24];
+        u32                     padding[12];
+
+        union {
+                u32             padding1[12];
+                u32             sw_reserved[12];
+        };
 
 } __attribute__((aligned(16)));
 
@@ -346,10 +353,23 @@ struct i387_soft_struct {
         u32                     entry_eip;
 };
 
+struct xsave_hdr_struct {
+        u64 xstate_bv;
+        u64 reserved1[2];
+        u64 reserved2[5];
+} __attribute__((packed));
+
+struct xsave_struct {
+        struct i387_fxsave_struct i387;
+        struct xsave_hdr_struct xsave_hdr;
+        /* new processor state extensions will go here */
+} __attribute__ ((packed, aligned (64)));
+
 union thread_xstate {
         struct i387_fsave_struct        fsave;
         struct i387_fxsave_struct       fxsave;
         struct i387_soft_struct         soft;
+        struct xsave_struct             xsave;
 };
 
 #ifdef CONFIG_X86_64
@@ -411,9 +431,14 @@ struct thread_struct {
         unsigned                io_bitmap_max;
 /* MSR_IA32_DEBUGCTLMSR value to switch in if TIF_DEBUGCTLMSR is set.  */
         unsigned long   debugctlmsr;
-/* Debug Store - if not 0 points to a DS Save Area configuration;
- *               goes into MSR_IA32_DS_AREA */
-        unsigned long   ds_area_msr;
+#ifdef CONFIG_X86_DS
+/* Debug Store context; see include/asm-x86/ds.h; goes into MSR_IA32_DS_AREA */
+        struct ds_context       *ds_ctx;
+#endif /* CONFIG_X86_DS */
+#ifdef CONFIG_X86_PTRACE_BTS
+/* the signal to send on a bts buffer overflow */
+        unsigned int    bts_ovfl_signal;
+#endif /* CONFIG_X86_PTRACE_BTS */
 };
 
 static inline unsigned long native_get_debugreg(int regno)
@@ -561,41 +586,6 @@ static inline void clear_in_cr4(unsigned long mask)
         write_cr4(cr4);
 }
 
-struct microcode_header {
-        unsigned int            hdrver;
-        unsigned int            rev;
-        unsigned int            date;
-        unsigned int            sig;
-        unsigned int            cksum;
-        unsigned int            ldrver;
-        unsigned int            pf;
-        unsigned int            datasize;
-        unsigned int            totalsize;
-        unsigned int            reserved[3];
-};
-
-struct microcode {
-        struct microcode_header hdr;
-        unsigned int            bits[0];
-};
-
-typedef struct microcode        microcode_t;
-typedef struct microcode_header microcode_header_t;
-
-/* microcode format is extended from prescott processors */
-struct extended_signature {
-        unsigned int            sig;
-        unsigned int            pf;
-        unsigned int            cksum;
-};
-
-struct extended_sigtable {
-        unsigned int            count;
-        unsigned int            cksum;
-        unsigned int            reserved[3];
-        struct extended_signature sigs[0];
-};
-
 typedef struct {
         unsigned long           seg;
 } mm_segment_t;
@@ -943,4 +933,4 @@ extern void start_thread(struct pt_regs *regs, unsigned long new_ip,
 extern int get_tsc_mode(unsigned long adr);
 extern int set_tsc_mode(unsigned int val);
 
-#endif
+#endif /* ASM_X86__PROCESSOR_H */
diff --git a/include/asm-x86/proto.h b/include/asm-x86/proto.h
index 3dd458c385c0..6e89e8b4de0e 100644
--- a/include/asm-x86/proto.h
+++ b/include/asm-x86/proto.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X8664_PROTO_H
-#define _ASM_X8664_PROTO_H 1
+#ifndef ASM_X86__PROTO_H
+#define ASM_X86__PROTO_H
 
 #include <asm/ldt.h>
 
@@ -29,4 +29,4 @@ long do_arch_prctl(struct task_struct *task, int code, unsigned long addr);
 #define round_up(x, y) (((x) + (y) - 1) & ~((y) - 1))
 #define round_down(x, y) ((x) & ~((y) - 1))
 
-#endif
+#endif /* ASM_X86__PROTO_H */
diff --git a/include/asm-x86/ptrace-abi.h b/include/asm-x86/ptrace-abi.h
index 72e7b9db29bb..4298b8882a78 100644
--- a/include/asm-x86/ptrace-abi.h
+++ b/include/asm-x86/ptrace-abi.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PTRACE_ABI_H
-#define _ASM_X86_PTRACE_ABI_H
+#ifndef ASM_X86__PTRACE_ABI_H
+#define ASM_X86__PTRACE_ABI_H
 
 #ifdef __i386__
 
@@ -80,8 +80,9 @@
 
 #define PTRACE_SINGLEBLOCK      33      /* resume execution until next branch */
 
-#ifndef __ASSEMBLY__
+#ifdef CONFIG_X86_PTRACE_BTS
 
+#ifndef __ASSEMBLY__
 #include <asm/types.h>
 
 /* configuration/status structure used in PTRACE_BTS_CONFIG and
@@ -97,20 +98,20 @@ struct ptrace_bts_config {
         /* actual size of bts_struct in bytes */
         __u32 bts_size;
 };
-#endif
+#endif /* __ASSEMBLY__ */
 
 #define PTRACE_BTS_O_TRACE      0x1 /* branch trace */
 #define PTRACE_BTS_O_SCHED      0x2 /* scheduling events w/ jiffies */
 #define PTRACE_BTS_O_SIGNAL     0x4 /* send SIG<signal> on buffer overflow
                                        instead of wrapping around */
-#define PTRACE_BTS_O_CUT_SIZE   0x8 /* cut requested size to max available
-                                       instead of failing */
+#define PTRACE_BTS_O_ALLOC      0x8 /* (re)allocate buffer */
 
 #define PTRACE_BTS_CONFIG       40
 /* Configure branch trace recording.
    ADDR points to a struct ptrace_bts_config.
    DATA gives the size of that buffer.
-   A new buffer is allocated, iff the size changes.
+   A new buffer is allocated, if requested in the flags.
+   An overflow signal may only be requested for new buffers.
    Returns the number of bytes read.
 */
 #define PTRACE_BTS_STATUS       41
@@ -119,7 +120,7 @@ struct ptrace_bts_config {
    Returns the number of bytes written.
 */
 #define PTRACE_BTS_SIZE         42
-/* Return the number of available BTS records.
+/* Return the number of available BTS records for draining.
    DATA and ADDR are ignored.
 */
 #define PTRACE_BTS_GET          43
@@ -139,5 +140,6 @@ struct ptrace_bts_config {
    BTS records are read from oldest to newest.
    Returns number of BTS records drained.
 */
+#endif /* CONFIG_X86_PTRACE_BTS */
 
-#endif
+#endif /* ASM_X86__PTRACE_ABI_H */
diff --git a/include/asm-x86/ptrace.h b/include/asm-x86/ptrace.h
index 8a71db803da6..a2025525a15a 100644
--- a/include/asm-x86/ptrace.h
+++ b/include/asm-x86/ptrace.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PTRACE_H
-#define _ASM_X86_PTRACE_H
+#ifndef ASM_X86__PTRACE_H
+#define ASM_X86__PTRACE_H
 
 #include <linux/compiler.h>     /* For __user */
 #include <asm/ptrace-abi.h>
@@ -127,26 +127,59 @@ struct pt_regs {
 #endif /* __KERNEL__ */
 #endif /* !__i386__ */
 
+
+#ifdef CONFIG_X86_PTRACE_BTS
+/* a branch trace record entry
+ *
+ * In order to unify the interface between various processor versions,
+ * we use the below data structure for all processors.
+ */
+enum bts_qualifier {
+        BTS_INVALID = 0,
+        BTS_BRANCH,
+        BTS_TASK_ARRIVES,
+        BTS_TASK_DEPARTS
+};
+
+struct bts_struct {
+        __u64 qualifier;
+        union {
+                /* BTS_BRANCH */
+                struct {
+                        __u64 from_ip;
+                        __u64 to_ip;
+                } lbr;
+                /* BTS_TASK_ARRIVES or
+                   BTS_TASK_DEPARTS */
+                __u64 jiffies;
+        } variant;
+};
+#endif /* CONFIG_X86_PTRACE_BTS */
+
 #ifdef __KERNEL__
 
-/* the DS BTS struct is used for ptrace as well */
-#include <asm/ds.h>
+#include <linux/init.h>
 
+struct cpuinfo_x86;
 struct task_struct;
 
+#ifdef CONFIG_X86_PTRACE_BTS
+extern void __cpuinit ptrace_bts_init_intel(struct cpuinfo_x86 *);
 extern void ptrace_bts_take_timestamp(struct task_struct *, enum bts_qualifier);
+#else
+#define ptrace_bts_init_intel(config) do {} while (0)
+#endif /* CONFIG_X86_PTRACE_BTS */
 
 extern unsigned long profile_pc(struct pt_regs *regs);
 
 extern unsigned long
 convert_ip_to_linear(struct task_struct *child, struct pt_regs *regs);
-
-#ifdef CONFIG_X86_32
 extern void send_sigtrap(struct task_struct *tsk, struct pt_regs *regs,
-                         int error_code);
-#else
+                         int error_code, int si_code);
 void signal_fault(struct pt_regs *regs, void __user *frame, char *where);
-#endif
+
+extern long syscall_trace_enter(struct pt_regs *);
+extern void syscall_trace_leave(struct pt_regs *);
 
 static inline unsigned long regs_return_value(struct pt_regs *regs)
 {
@@ -213,6 +246,11 @@ static inline unsigned long frame_pointer(struct pt_regs *regs)
         return regs->bp;
 }
 
+static inline unsigned long user_stack_pointer(struct pt_regs *regs)
+{
+        return regs->sp;
+}
+
 /*
  * These are defined as per linux/ptrace.h, which see.
  */
@@ -239,4 +277,4 @@ extern int do_set_thread_area(struct task_struct *p, int idx,
 
 #endif /* !__ASSEMBLY__ */
 
-#endif
+#endif /* ASM_X86__PTRACE_H */
diff --git a/include/asm-x86/pvclock-abi.h b/include/asm-x86/pvclock-abi.h
index 6857f840b243..edb3b4ecfc81 100644
--- a/include/asm-x86/pvclock-abi.h
+++ b/include/asm-x86/pvclock-abi.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_PVCLOCK_ABI_H_
-#define _ASM_X86_PVCLOCK_ABI_H_
+#ifndef ASM_X86__PVCLOCK_ABI_H
+#define ASM_X86__PVCLOCK_ABI_H
 #ifndef __ASSEMBLY__
 
 /*
@@ -39,4 +39,4 @@ struct pvclock_wall_clock {
 } __attribute__((__packed__));
 
 #endif /* __ASSEMBLY__ */
-#endif /* _ASM_X86_PVCLOCK_ABI_H_ */
+#endif /* ASM_X86__PVCLOCK_ABI_H */
diff --git a/include/asm-x86/pvclock.h b/include/asm-x86/pvclock.h
index 85b1bba8e0a3..ad29e277fd6d 100644
--- a/include/asm-x86/pvclock.h
+++ b/include/asm-x86/pvclock.h
@@ -1,13 +1,14 @@
-#ifndef _ASM_X86_PVCLOCK_H_
-#define _ASM_X86_PVCLOCK_H_
+#ifndef ASM_X86__PVCLOCK_H
+#define ASM_X86__PVCLOCK_H
 
 #include <linux/clocksource.h>
 #include <asm/pvclock-abi.h>
 
 /* some helper functions for xen and kvm pv clock sources */
 cycle_t pvclock_clocksource_read(struct pvclock_vcpu_time_info *src);
+unsigned long pvclock_tsc_khz(struct pvclock_vcpu_time_info *src);
 void pvclock_read_wallclock(struct pvclock_wall_clock *wall,
                             struct pvclock_vcpu_time_info *vcpu,
                             struct timespec *ts);
 
-#endif /* _ASM_X86_PVCLOCK_H_ */
+#endif /* ASM_X86__PVCLOCK_H */
diff --git a/include/asm-x86/reboot.h b/include/asm-x86/reboot.h
index 206f355786dc..1c2f0ce9e31e 100644
--- a/include/asm-x86/reboot.h
+++ b/include/asm-x86/reboot.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_REBOOT_H
-#define _ASM_REBOOT_H
+#ifndef ASM_X86__REBOOT_H
+#define ASM_X86__REBOOT_H
 
 struct pt_regs;
 
@@ -18,4 +18,4 @@ void native_machine_crash_shutdown(struct pt_regs *regs);
 void native_machine_shutdown(void);
 void machine_real_restart(const unsigned char *code, int length);
 
-#endif  /* _ASM_REBOOT_H */
+#endif /* ASM_X86__REBOOT_H */
diff --git a/include/asm-x86/reboot_fixups.h b/include/asm-x86/reboot_fixups.h
index 0cb7d87c2b68..2c2987d97570 100644
--- a/include/asm-x86/reboot_fixups.h
+++ b/include/asm-x86/reboot_fixups.h
@@ -1,6 +1,6 @@
-#ifndef _LINUX_REBOOT_FIXUPS_H
-#define _LINUX_REBOOT_FIXUPS_H
+#ifndef ASM_X86__REBOOT_FIXUPS_H
+#define ASM_X86__REBOOT_FIXUPS_H
 
 extern void mach_reboot_fixups(void);
 
-#endif /* _LINUX_REBOOT_FIXUPS_H */
+#endif /* ASM_X86__REBOOT_FIXUPS_H */
diff --git a/include/asm-x86/required-features.h b/include/asm-x86/required-features.h
index adec887dd7cd..a01c4e376331 100644
--- a/include/asm-x86/required-features.h
+++ b/include/asm-x86/required-features.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_REQUIRED_FEATURES_H
-#define _ASM_REQUIRED_FEATURES_H 1
+#ifndef ASM_X86__REQUIRED_FEATURES_H
+#define ASM_X86__REQUIRED_FEATURES_H
 
 /* Define minimum CPUID feature set for kernel These bits are checked
    really early to actually display a visible error message before the
@@ -41,6 +41,12 @@
 # define NEED_3DNOW     0
 #endif
 
+#if defined(CONFIG_X86_P6_NOP) || defined(CONFIG_X86_64)
+# define NEED_NOPL      (1<<(X86_FEATURE_NOPL & 31))
+#else
+# define NEED_NOPL      0
+#endif
+
 #ifdef CONFIG_X86_64
 #define NEED_PSE        0
 #define NEED_MSR        (1<<(X86_FEATURE_MSR & 31))
@@ -67,10 +73,10 @@
 #define REQUIRED_MASK1  (NEED_LM|NEED_3DNOW)
 
 #define REQUIRED_MASK2  0
-#define REQUIRED_MASK3  0
+#define REQUIRED_MASK3  (NEED_NOPL)
 #define REQUIRED_MASK4  0
 #define REQUIRED_MASK5  0
 #define REQUIRED_MASK6  0
 #define REQUIRED_MASK7  0
 
-#endif
+#endif /* ASM_X86__REQUIRED_FEATURES_H */
diff --git a/include/asm-x86/resume-trace.h b/include/asm-x86/resume-trace.h
index 8d9f0b41ee86..e39376d7de50 100644
--- a/include/asm-x86/resume-trace.h
+++ b/include/asm-x86/resume-trace.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_RESUME_TRACE_H
-#define _ASM_X86_RESUME_TRACE_H
+#ifndef ASM_X86__RESUME_TRACE_H
+#define ASM_X86__RESUME_TRACE_H
 
 #include <asm/asm.h>
 
@@ -7,7 +7,7 @@
 do {                                                            \
         if (pm_trace_enabled) {                                 \
                 const void *tracedata;                          \
-                asm volatile(_ASM_MOV_UL " $1f,%0\n"            \
+                asm volatile(_ASM_MOV " $1f,%0\n"               \
                              ".section .tracedata,\"a\"\n"      \
                              "1:\t.word %c1\n\t"                \
                              _ASM_PTR " %c2\n"                  \
@@ -18,4 +18,4 @@ do {								\
         }                                                       \
 } while (0)
 
-#endif
+#endif /* ASM_X86__RESUME_TRACE_H */
diff --git a/include/asm-x86/rio.h b/include/asm-x86/rio.h
index c9448bd8968f..5e1256bdee83 100644
--- a/include/asm-x86/rio.h
+++ b/include/asm-x86/rio.h
@@ -5,8 +5,8 @@
  * Author: Laurent Vivier <Laurent.Vivier@bull.net>
  */
 
-#ifndef __ASM_RIO_H
-#define __ASM_RIO_H
+#ifndef ASM_X86__RIO_H
+#define ASM_X86__RIO_H
 
 #define RIO_TABLE_VERSION       3
 
@@ -60,4 +60,4 @@ enum {
         ALT_CALGARY     = 5,    /* Second Planar Calgary      */
 };
 
-#endif /* __ASM_RIO_H */
+#endif /* ASM_X86__RIO_H */
diff --git a/include/asm-x86/rwlock.h b/include/asm-x86/rwlock.h
index 6a8c0d645108..48a3109e1a7d 100644
--- a/include/asm-x86/rwlock.h
+++ b/include/asm-x86/rwlock.h
@@ -1,8 +1,8 @@
-#ifndef _ASM_X86_RWLOCK_H
-#define _ASM_X86_RWLOCK_H
+#ifndef ASM_X86__RWLOCK_H
+#define ASM_X86__RWLOCK_H
 
 #define RW_LOCK_BIAS             0x01000000
 
 /* Actual code is in asm/spinlock.h or in arch/x86/lib/rwlock.S */
 
-#endif /* _ASM_X86_RWLOCK_H */
+#endif /* ASM_X86__RWLOCK_H */
diff --git a/include/asm-x86/rwsem.h b/include/asm-x86/rwsem.h
index 750f2a3542b3..3ff3015b71a8 100644
--- a/include/asm-x86/rwsem.h
+++ b/include/asm-x86/rwsem.h
@@ -29,8 +29,8 @@
  * front, then they'll all be woken up, but no other readers will be.
  */
 
-#ifndef _I386_RWSEM_H
-#define _I386_RWSEM_H
+#ifndef ASM_X86__RWSEM_H
+#define ASM_X86__RWSEM_H
 
 #ifndef _LINUX_RWSEM_H
 #error "please don't include asm/rwsem.h directly, use linux/rwsem.h instead"
@@ -262,4 +262,4 @@ static inline int rwsem_is_locked(struct rw_semaphore *sem)
 }
 
 #endif /* __KERNEL__ */
-#endif /* _I386_RWSEM_H */
+#endif /* ASM_X86__RWSEM_H */
diff --git a/include/asm-x86/scatterlist.h b/include/asm-x86/scatterlist.h
index c0432061f81a..ee48f880005d 100644
--- a/include/asm-x86/scatterlist.h
+++ b/include/asm-x86/scatterlist.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SCATTERLIST_H
-#define _ASM_X86_SCATTERLIST_H
+#ifndef ASM_X86__SCATTERLIST_H
+#define ASM_X86__SCATTERLIST_H
 
 #include <asm/types.h>
 
@@ -30,4 +30,4 @@ struct scatterlist {
 # define sg_dma_len(sg)         ((sg)->dma_length)
 #endif
 
-#endif
+#endif /* ASM_X86__SCATTERLIST_H */
diff --git a/include/asm-x86/seccomp_32.h b/include/asm-x86/seccomp_32.h
index 36e71c5f306f..cf9ab2dbcef1 100644
--- a/include/asm-x86/seccomp_32.h
+++ b/include/asm-x86/seccomp_32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_SECCOMP_H
-#define _ASM_SECCOMP_H
+#ifndef ASM_X86__SECCOMP_32_H
+#define ASM_X86__SECCOMP_32_H
 
 #include <linux/thread_info.h>
 
@@ -14,4 +14,4 @@
 #define __NR_seccomp_exit __NR_exit
 #define __NR_seccomp_sigreturn __NR_sigreturn
 
-#endif /* _ASM_SECCOMP_H */
+#endif /* ASM_X86__SECCOMP_32_H */
diff --git a/include/asm-x86/seccomp_64.h b/include/asm-x86/seccomp_64.h
index 76cfe69aa63c..03274cea751f 100644
--- a/include/asm-x86/seccomp_64.h
+++ b/include/asm-x86/seccomp_64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_SECCOMP_H
-#define _ASM_SECCOMP_H
+#ifndef ASM_X86__SECCOMP_64_H
+#define ASM_X86__SECCOMP_64_H
 
 #include <linux/thread_info.h>
 
@@ -22,4 +22,4 @@
 #define __NR_seccomp_exit_32 __NR_ia32_exit
 #define __NR_seccomp_sigreturn_32 __NR_ia32_sigreturn
 
-#endif /* _ASM_SECCOMP_H */
+#endif /* ASM_X86__SECCOMP_64_H */
diff --git a/include/asm-x86/segment.h b/include/asm-x86/segment.h
index 646452ea9ea3..5d6e69454891 100644
--- a/include/asm-x86/segment.h
+++ b/include/asm-x86/segment.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SEGMENT_H_
-#define _ASM_X86_SEGMENT_H_
+#ifndef ASM_X86__SEGMENT_H
+#define ASM_X86__SEGMENT_H
 
 /* Constructor for a conventional segment GDT (or LDT) entry */
 /* This is a macro so it can be used in initializers */
@@ -131,12 +131,6 @@
  * Matching rules for certain types of segments.
  */
 
-/* Matches only __KERNEL_CS, ignoring PnP / USER / APM segments */
-#define SEGMENT_IS_KERNEL_CODE(x) (((x) & 0xfc) == GDT_ENTRY_KERNEL_CS * 8)
-
-/* Matches __KERNEL_CS and __USER_CS (they must be 2 entries apart) */
-#define SEGMENT_IS_FLAT_CODE(x)  (((x) & 0xec) == GDT_ENTRY_KERNEL_CS * 8)
-
 /* Matches PNP_CS32 and PNP_CS16 (they must be consecutive) */
 #define SEGMENT_IS_PNP_CODE(x)   (((x) & 0xf4) == GDT_ENTRY_PNPBIOS_BASE * 8)
 
@@ -212,4 +206,4 @@ extern const char early_idt_handlers[NUM_EXCEPTION_VECTORS][10];
 #endif
 #endif
 
-#endif
+#endif /* ASM_X86__SEGMENT_H */
diff --git a/include/asm-x86/sembuf.h b/include/asm-x86/sembuf.h
index ee50c801f7b7..81f06b7e5a3f 100644
--- a/include/asm-x86/sembuf.h
+++ b/include/asm-x86/sembuf.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SEMBUF_H
-#define _ASM_X86_SEMBUF_H
+#ifndef ASM_X86__SEMBUF_H
+#define ASM_X86__SEMBUF_H
 
 /*
  * The semid64_ds structure for x86 architecture.
@@ -21,4 +21,4 @@ struct semid64_ds {
         unsigned long   __unused4;
 };
 
-#endif /* _ASM_X86_SEMBUF_H */
+#endif /* ASM_X86__SEMBUF_H */
diff --git a/include/asm-x86/serial.h b/include/asm-x86/serial.h
index 628c801535ea..303660b671e5 100644
--- a/include/asm-x86/serial.h
+++ b/include/asm-x86/serial.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SERIAL_H
-#define _ASM_X86_SERIAL_H
+#ifndef ASM_X86__SERIAL_H
+#define ASM_X86__SERIAL_H
 
 /*
  * This assumes you have a 1.8432 MHz clock for your UART.
@@ -26,4 +26,4 @@
         { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
         { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
 
-#endif /* _ASM_X86_SERIAL_H */
+#endif /* ASM_X86__SERIAL_H */
diff --git a/include/asm-x86/setup.h b/include/asm-x86/setup.h
index a07c6f1c01e1..11b6cc14b289 100644
--- a/include/asm-x86/setup.h
+++ b/include/asm-x86/setup.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SETUP_H
-#define _ASM_X86_SETUP_H
+#ifndef ASM_X86__SETUP_H
+#define ASM_X86__SETUP_H
 
 #define COMMAND_LINE_SIZE 2048
 
@@ -38,9 +38,11 @@ struct x86_quirks {
         void (*mpc_oem_pci_bus)(struct mpc_config_bus *m);
         void (*smp_read_mpc_oem)(struct mp_config_oemtable *oemtable,
                                     unsigned short oemsize);
+        int (*setup_ioapic_ids)(void);
 };
 
 extern struct x86_quirks *x86_quirks;
+extern unsigned long saved_video_mode;
 
 #ifndef CONFIG_PARAVIRT
 #define paravirt_post_allocator_init()  do {} while (0)
@@ -100,4 +102,4 @@ void __init x86_64_start_reservations(char *real_mode_data);
 #endif /* __ASSEMBLY__ */
 #endif  /*  __KERNEL__  */
 
-#endif /* _ASM_X86_SETUP_H */
+#endif /* ASM_X86__SETUP_H */
diff --git a/include/asm-x86/shmbuf.h b/include/asm-x86/shmbuf.h
index b51413b74971..f51aec2298e9 100644
--- a/include/asm-x86/shmbuf.h
+++ b/include/asm-x86/shmbuf.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SHMBUF_H
-#define _ASM_X86_SHMBUF_H
+#ifndef ASM_X86__SHMBUF_H
+#define ASM_X86__SHMBUF_H
 
 /*
  * The shmid64_ds structure for x86 architecture.
@@ -48,4 +48,4 @@ struct shminfo64 {
         unsigned long   __unused4;
 };
 
-#endif /* _ASM_X86_SHMBUF_H */
+#endif /* ASM_X86__SHMBUF_H */
diff --git a/include/asm-x86/shmparam.h b/include/asm-x86/shmparam.h
index 0880cf0917b9..a83a1fd96a0e 100644
--- a/include/asm-x86/shmparam.h
+++ b/include/asm-x86/shmparam.h
@@ -1,6 +1,6 @@
-#ifndef _ASM_X86_SHMPARAM_H
-#define _ASM_X86_SHMPARAM_H
+#ifndef ASM_X86__SHMPARAM_H
+#define ASM_X86__SHMPARAM_H
 
 #define SHMLBA PAGE_SIZE         /* attach addr a multiple of this */
 
-#endif /* _ASM_X86_SHMPARAM_H */
+#endif /* ASM_X86__SHMPARAM_H */
diff --git a/include/asm-x86/sigcontext.h b/include/asm-x86/sigcontext.h
index 2f9c884d2c0f..ee813f4fe5d5 100644
--- a/include/asm-x86/sigcontext.h
+++ b/include/asm-x86/sigcontext.h
@@ -1,9 +1,43 @@
-#ifndef _ASM_X86_SIGCONTEXT_H
-#define _ASM_X86_SIGCONTEXT_H
+#ifndef ASM_X86__SIGCONTEXT_H
+#define ASM_X86__SIGCONTEXT_H
 
 #include <linux/compiler.h>
 #include <asm/types.h>
 
+#define FP_XSTATE_MAGIC1        0x46505853U
+#define FP_XSTATE_MAGIC2        0x46505845U
+#define FP_XSTATE_MAGIC2_SIZE   sizeof(FP_XSTATE_MAGIC2)
+
+/*
+ * bytes 464..511 in the current 512byte layout of fxsave/fxrstor frame
+ * are reserved for SW usage. On cpu's supporting xsave/xrstor, these bytes
+ * are used to extended the fpstate pointer in the sigcontext, which now
+ * includes the extended state information along with fpstate information.
+ *
+ * Presence of FP_XSTATE_MAGIC1 at the beginning of this SW reserved
+ * area and FP_XSTATE_MAGIC2 at the end of memory layout
+ * (extended_size - FP_XSTATE_MAGIC2_SIZE) indicates the presence of the
+ * extended state information in the memory layout pointed by the fpstate
+ * pointer in sigcontext.
+ */
+struct _fpx_sw_bytes {
+        __u32 magic1;           /* FP_XSTATE_MAGIC1 */
+        __u32 extended_size;    /* total size of the layout referred by
+                                 * fpstate pointer in the sigcontext.
+                                 */
+        __u64 xstate_bv;
+                                /* feature bit mask (including fp/sse/extended
+                                 * state) that is present in the memory
+                                 * layout.
+                                 */
+        __u32 xstate_size;      /* actual xsave state size, based on the
+                                 * features saved in the layout.
+                                 * 'extended_size' will be greater than
+                                 * 'xstate_size'.
+                                 */
+        __u32 padding[7];       /*  for future use. */
+};
+
 #ifdef __i386__
 /*
  * As documented in the iBCS2 standard..
@@ -53,7 +87,13 @@ struct _fpstate {
         unsigned long   reserved;
         struct _fpxreg  _fxsr_st[8];    /* FXSR FPU reg data is ignored */
         struct _xmmreg  _xmm[8];
-        unsigned long   padding[56];
+        unsigned long   padding1[44];
+
+        union {
+                unsigned long   padding2[12];
+                struct _fpx_sw_bytes sw_reserved; /* represents the extended
+                                                   * state info */
+        };
 };
 
 #define X86_FXSR_MAGIC          0x0000
@@ -79,7 +119,15 @@ struct sigcontext {
         unsigned long flags;
         unsigned long sp_at_signal;
         unsigned short ss, __ssh;
-        struct _fpstate __user *fpstate;
+
+        /*
+         * fpstate is really (struct _fpstate *) or (struct _xstate *)
+         * depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
+         * bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end
+         * of extended memory layout. See comments at the defintion of
+         * (struct _fpx_sw_bytes)
+         */
+        void __user *fpstate;           /* zero when no FPU/extended context */
         unsigned long oldmask;
         unsigned long cr2;
 };
@@ -130,7 +178,12 @@ struct _fpstate {
         __u32   mxcsr_mask;
         __u32   st_space[32];   /* 8*16 bytes for each FP-reg */
         __u32   xmm_space[64];  /* 16*16 bytes for each XMM-reg  */
-        __u32   reserved2[24];
+        __u32   reserved2[12];
+        union {
+                __u32   reserved3[12];
+                struct _fpx_sw_bytes sw_reserved; /* represents the extended
+                                                   * state information */
+        };
 };
 
 #ifdef __KERNEL__
@@ -161,7 +214,15 @@ struct sigcontext {
         unsigned long trapno;
         unsigned long oldmask;
         unsigned long cr2;
-        struct _fpstate __user *fpstate;        /* zero when no FPU context */
+
+        /*
+         * fpstate is really (struct _fpstate *) or (struct _xstate *)
+         * depending on the FP_XSTATE_MAGIC1 encoded in the SW reserved
+         * bytes of (struct _fpstate) and FP_XSTATE_MAGIC2 present at the end
+         * of extended memory layout. See comments at the defintion of
+         * (struct _fpx_sw_bytes)
+         */
+        void __user *fpstate;           /* zero when no FPU/extended context */
         unsigned long reserved1[8];
 };
 #else /* __KERNEL__ */
@@ -202,4 +263,22 @@ struct sigcontext {
 
 #endif /* !__i386__ */
 
-#endif
+struct _xsave_hdr {
+        __u64 xstate_bv;
+        __u64 reserved1[2];
+        __u64 reserved2[5];
+};
+
+/*
+ * Extended state pointed by the fpstate pointer in the sigcontext.
+ * In addition to the fpstate, information encoded in the xstate_hdr
+ * indicates the presence of other extended state information
+ * supported by the processor and OS.
+ */
+struct _xstate {
+        struct _fpstate fpstate;
+        struct _xsave_hdr xstate_hdr;
+        /* new processor state extensions go here */
+};
+
+#endif /* ASM_X86__SIGCONTEXT_H */
diff --git a/include/asm-x86/sigcontext32.h b/include/asm-x86/sigcontext32.h
index 57a9686fb491..8c347032c2f2 100644
--- a/include/asm-x86/sigcontext32.h
+++ b/include/asm-x86/sigcontext32.h
@@ -1,5 +1,5 @@
-#ifndef _SIGCONTEXT32_H
-#define _SIGCONTEXT32_H 1
+#ifndef ASM_X86__SIGCONTEXT32_H
+#define ASM_X86__SIGCONTEXT32_H
 
 /* signal context for 32bit programs. */
 
@@ -40,7 +40,11 @@ struct _fpstate_ia32 {
         __u32   reserved;
         struct _fpxreg  _fxsr_st[8];
         struct _xmmreg  _xmm[8];        /* It's actually 16 */
-        __u32   padding[56];
+        __u32   padding[44];
+        union {
+                __u32 padding2[12];
+                struct _fpx_sw_bytes sw_reserved;
+        };
 };
 
 struct sigcontext_ia32 {
@@ -68,4 +72,4 @@ struct sigcontext_ia32 {
        unsigned int cr2;
 };
 
-#endif
+#endif /* ASM_X86__SIGCONTEXT32_H */
diff --git a/include/asm-x86/siginfo.h b/include/asm-x86/siginfo.h
index a477bea0c2a1..808bdfb2958c 100644
--- a/include/asm-x86/siginfo.h
+++ b/include/asm-x86/siginfo.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SIGINFO_H
-#define _ASM_X86_SIGINFO_H
+#ifndef ASM_X86__SIGINFO_H
+#define ASM_X86__SIGINFO_H
 
 #ifdef __x86_64__
 # define __ARCH_SI_PREAMBLE_SIZE        (4 * sizeof(int))
@@ -7,4 +7,4 @@
 
 #include <asm-generic/siginfo.h>
 
-#endif
+#endif /* ASM_X86__SIGINFO_H */
diff --git a/include/asm-x86/signal.h b/include/asm-x86/signal.h
index 6dac49364e95..65acc82d267a 100644
--- a/include/asm-x86/signal.h
+++ b/include/asm-x86/signal.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SIGNAL_H
-#define _ASM_X86_SIGNAL_H
+#ifndef ASM_X86__SIGNAL_H
+#define ASM_X86__SIGNAL_H
 
 #ifndef __ASSEMBLY__
 #include <linux/types.h>
@@ -140,6 +140,9 @@ struct sigaction {
 struct k_sigaction {
         struct sigaction sa;
 };
+
+extern void do_notify_resume(struct pt_regs *, void *, __u32);
+
 # else /* __KERNEL__ */
 /* Here we must cater to libcs that poke about in kernel headers.  */
 
@@ -256,4 +259,4 @@ struct pt_regs;
 #endif /* __KERNEL__ */
 #endif /* __ASSEMBLY__ */
 
-#endif
+#endif /* ASM_X86__SIGNAL_H */
diff --git a/include/asm-x86/smp.h b/include/asm-x86/smp.h
index 3c877f74f279..a6afc29f2dd9 100644
--- a/include/asm-x86/smp.h
+++ b/include/asm-x86/smp.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SMP_H_
-#define _ASM_X86_SMP_H_
+#ifndef ASM_X86__SMP_H
+#define ASM_X86__SMP_H
 #ifndef __ASSEMBLY__
 #include <linux/cpumask.h>
 #include <linux/init.h>
@@ -34,6 +34,9 @@ extern cpumask_t cpu_initialized;
 DECLARE_PER_CPU(cpumask_t, cpu_sibling_map);
 DECLARE_PER_CPU(cpumask_t, cpu_core_map);
 DECLARE_PER_CPU(u16, cpu_llc_id);
+#ifdef CONFIG_X86_32
+DECLARE_PER_CPU(int, cpu_number);
+#endif
 
 DECLARE_EARLY_PER_CPU(u16, x86_cpu_to_apicid);
 DECLARE_EARLY_PER_CPU(u16, x86_bios_cpu_apicid);
@@ -47,12 +50,16 @@ extern struct {
 struct smp_ops {
         void (*smp_prepare_boot_cpu)(void);
         void (*smp_prepare_cpus)(unsigned max_cpus);
-        int (*cpu_up)(unsigned cpu);
         void (*smp_cpus_done)(unsigned max_cpus);
 
         void (*smp_send_stop)(void);
         void (*smp_send_reschedule)(int cpu);
 
+        int (*cpu_up)(unsigned cpu);
+        int (*cpu_disable)(void);
+        void (*cpu_die)(unsigned int cpu);
+        void (*play_dead)(void);
+
         void (*send_call_func_ipi)(cpumask_t mask);
         void (*send_call_func_single_ipi)(int cpu);
 };
@@ -91,6 +98,21 @@ static inline int __cpu_up(unsigned int cpu)
         return smp_ops.cpu_up(cpu);
 }
 
+static inline int __cpu_disable(void)
+{
+        return smp_ops.cpu_disable();
+}
+
+static inline void __cpu_die(unsigned int cpu)
+{
+        smp_ops.cpu_die(cpu);
+}
+
+static inline void play_dead(void)
+{
+        smp_ops.play_dead();
+}
+
 static inline void smp_send_reschedule(int cpu)
 {
         smp_ops.smp_send_reschedule(cpu);
@@ -106,15 +128,20 @@ static inline void arch_send_call_function_ipi(cpumask_t mask)
         smp_ops.send_call_func_ipi(mask);
 }
 
+void cpu_disable_common(void);
 void native_smp_prepare_boot_cpu(void);
 void native_smp_prepare_cpus(unsigned int max_cpus);
 void native_smp_cpus_done(unsigned int max_cpus);
 int native_cpu_up(unsigned int cpunum);
+int native_cpu_disable(void);
+void native_cpu_die(unsigned int cpu);
+void native_play_dead(void);
+void play_dead_common(void);
+
 void native_send_call_func_ipi(cpumask_t mask);
 void native_send_call_func_single_ipi(int cpu);
 
-extern int __cpu_disable(void);
-extern void __cpu_die(unsigned int cpu);
+extern void prefill_possible_map(void);
 
 void smp_store_cpu_info(int id);
 #define cpu_physical_id(cpu)    per_cpu(x86_cpu_to_apicid, cpu)
@@ -124,15 +151,11 @@ static inline int num_booting_cpus(void)
 {
         return cpus_weight(cpu_callout_map);
 }
-#endif /* CONFIG_SMP */
-
-#if defined(CONFIG_SMP) && defined(CONFIG_HOTPLUG_CPU)
-extern void prefill_possible_map(void);
 #else
 static inline void prefill_possible_map(void)
 {
 }
-#endif
+#endif /* CONFIG_SMP */
 
 extern unsigned disabled_cpus __cpuinitdata;
 
@@ -142,7 +165,6 @@ extern unsigned disabled_cpus __cpuinitdata;
  * from the initial startup. We map APIC_BASE very early in page_setup(),
  * so this is correct in the x86 case.
  */
-DECLARE_PER_CPU(int, cpu_number);
 #define raw_smp_processor_id() (x86_read_percpu(cpu_number))
 extern int safe_smp_processor_id(void);
 
@@ -165,30 +187,33 @@ extern int safe_smp_processor_id(void);
 
 #ifdef CONFIG_X86_LOCAL_APIC
 
+#ifndef CONFIG_X86_64
 static inline int logical_smp_processor_id(void)
 {
         /* we don't want to mark this access volatile - bad code generation */
         return GET_APIC_LOGICAL_ID(*(u32 *)(APIC_BASE + APIC_LDR));
 }
 
-#ifndef CONFIG_X86_64
+#include <mach_apicdef.h>
 static inline unsigned int read_apic_id(void)
 {
-        return *(u32 *)(APIC_BASE + APIC_ID);
+        unsigned int reg;
+
+        reg = *(u32 *)(APIC_BASE + APIC_ID);
+
+        return GET_APIC_ID(reg);
 }
-#else
-extern unsigned int read_apic_id(void);
 #endif
 
 
-# ifdef APIC_DEFINITION
+# if defined(APIC_DEFINITION) || defined(CONFIG_X86_64)
 extern int hard_smp_processor_id(void);
 # else
-#  include <mach_apicdef.h>
+#include <mach_apicdef.h>
 static inline int hard_smp_processor_id(void)
 {
         /* we don't want to mark this access volatile - bad code generation */
-        return GET_APIC_ID(read_apic_id());
+        return read_apic_id();
 }
 # endif /* APIC_DEFINITION */
 
@@ -200,9 +225,5 @@ static inline int hard_smp_processor_id(void)
 
 #endif /* CONFIG_X86_LOCAL_APIC */
 
-#ifdef CONFIG_HOTPLUG_CPU
-extern void cpu_uninit(void);
-#endif
-
 #endif /* __ASSEMBLY__ */
-#endif
+#endif /* ASM_X86__SMP_H */
diff --git a/include/asm-x86/socket.h b/include/asm-x86/socket.h
index 80af9c4ccad7..db73274c83c3 100644
--- a/include/asm-x86/socket.h
+++ b/include/asm-x86/socket.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_SOCKET_H
-#define _ASM_SOCKET_H
+#ifndef ASM_X86__SOCKET_H
+#define ASM_X86__SOCKET_H
 
 #include <asm/sockios.h>
 
@@ -54,4 +54,4 @@
 
 #define SO_MARK                 36
 
-#endif /* _ASM_SOCKET_H */
+#endif /* ASM_X86__SOCKET_H */
diff --git a/include/asm-x86/sockios.h b/include/asm-x86/sockios.h
index 49cc72b5d3c9..a006704fdc84 100644
--- a/include/asm-x86/sockios.h
+++ b/include/asm-x86/sockios.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SOCKIOS_H
-#define _ASM_X86_SOCKIOS_H
+#ifndef ASM_X86__SOCKIOS_H
+#define ASM_X86__SOCKIOS_H
 
 /* Socket-level I/O control calls. */
 #define FIOSETOWN       0x8901
@@ -10,4 +10,4 @@
 #define SIOCGSTAMP      0x8906          /* Get stamp (timeval) */
 #define SIOCGSTAMPNS    0x8907          /* Get stamp (timespec) */
 
-#endif /* _ASM_X86_SOCKIOS_H */
+#endif /* ASM_X86__SOCKIOS_H */
diff --git a/include/asm-x86/sparsemem.h b/include/asm-x86/sparsemem.h
index 9bd48b0a534b..38f8e6bc3186 100644
--- a/include/asm-x86/sparsemem.h
+++ b/include/asm-x86/sparsemem.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SPARSEMEM_H
-#define _ASM_X86_SPARSEMEM_H
+#ifndef ASM_X86__SPARSEMEM_H
+#define ASM_X86__SPARSEMEM_H
 
 #ifdef CONFIG_SPARSEMEM
 /*
@@ -31,4 +31,4 @@
 #endif
 
 #endif /* CONFIG_SPARSEMEM */
-#endif
+#endif /* ASM_X86__SPARSEMEM_H */
diff --git a/include/asm-x86/spinlock.h b/include/asm-x86/spinlock.h
index e39c790dbfd2..157ff7fab97a 100644
--- a/include/asm-x86/spinlock.h
+++ b/include/asm-x86/spinlock.h
@@ -1,5 +1,5 @@
-#ifndef _X86_SPINLOCK_H_
-#define _X86_SPINLOCK_H_
+#ifndef ASM_X86__SPINLOCK_H
+#define ASM_X86__SPINLOCK_H
 
 #include <asm/atomic.h>
 #include <asm/rwlock.h>
@@ -21,8 +21,10 @@
 
 #ifdef CONFIG_X86_32
 # define LOCK_PTR_REG "a"
+# define REG_PTR_MODE "k"
 #else
 # define LOCK_PTR_REG "D"
+# define REG_PTR_MODE "q"
 #endif
 
 #if defined(CONFIG_X86_32) && \
@@ -54,19 +56,7 @@
  * much between them in performance though, especially as locks are out of line.
  */
 #if (NR_CPUS < 256)
-static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
-{
-        int tmp = ACCESS_ONCE(lock->slock);
-
-        return (((tmp >> 8) & 0xff) != (tmp & 0xff));
-}
-
-static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
-{
-        int tmp = ACCESS_ONCE(lock->slock);
-
-        return (((tmp >> 8) - tmp) & 0xff) > 1;
-}
+#define TICKET_SHIFT 8
 
 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
 {
@@ -89,19 +79,17 @@ static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
 
 static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
 {
-        int tmp;
-        short new;
+        int tmp, new;
 
-        asm volatile("movw %2,%w0\n\t"
+        asm volatile("movzwl %2, %0\n\t"
                      "cmpb %h0,%b0\n\t"
+                     "leal 0x100(%" REG_PTR_MODE "0), %1\n\t"
                      "jne 1f\n\t"
-                     "movw %w0,%w1\n\t"
-                     "incb %h1\n\t"
-                     "lock ; cmpxchgw %w1,%2\n\t"
+                     LOCK_PREFIX "cmpxchgw %w1,%2\n\t"
                      "1:"
                      "sete %b1\n\t"
                      "movzbl %b1,%0\n\t"
-                     : "=&a" (tmp), "=Q" (new), "+m" (lock->slock)
+                     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
                      :
                      : "memory", "cc");
 
@@ -116,26 +104,14 @@ static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
                      : "memory", "cc");
 }
 #else
-static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
-{
-        int tmp = ACCESS_ONCE(lock->slock);
-
-        return (((tmp >> 16) & 0xffff) != (tmp & 0xffff));
-}
-
-static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
-{
-        int tmp = ACCESS_ONCE(lock->slock);
-
-        return (((tmp >> 16) - tmp) & 0xffff) > 1;
-}
+#define TICKET_SHIFT 16
 
 static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
 {
         int inc = 0x00010000;
         int tmp;
 
-        asm volatile("lock ; xaddl %0, %1\n"
+        asm volatile(LOCK_PREFIX "xaddl %0, %1\n"
                      "movzwl %w0, %2\n\t"
                      "shrl $16, %0\n\t"
                      "1:\t"
@@ -146,7 +122,7 @@ static __always_inline void __ticket_spin_lock(raw_spinlock_t *lock)
                      /* don't need lfence here, because loads are in-order */
                      "jmp 1b\n"
                      "2:"
-                     : "+Q" (inc), "+m" (lock->slock), "=r" (tmp)
+                     : "+r" (inc), "+m" (lock->slock), "=&r" (tmp)
                      :
                      : "memory", "cc");
 }
@@ -160,13 +136,13 @@ static __always_inline int __ticket_spin_trylock(raw_spinlock_t *lock)
                      "movl %0,%1\n\t"
                      "roll $16, %0\n\t"
                      "cmpl %0,%1\n\t"
+                     "leal 0x00010000(%" REG_PTR_MODE "0), %1\n\t"
                      "jne 1f\n\t"
-                     "addl $0x00010000, %1\n\t"
-                     "lock ; cmpxchgl %1,%2\n\t"
+                     LOCK_PREFIX "cmpxchgl %1,%2\n\t"
                      "1:"
                      "sete %b1\n\t"
                      "movzbl %b1,%0\n\t"
-                     : "=&a" (tmp), "=r" (new), "+m" (lock->slock)
+                     : "=&a" (tmp), "=&q" (new), "+m" (lock->slock)
                      :
                      : "memory", "cc");
 
@@ -182,7 +158,19 @@ static __always_inline void __ticket_spin_unlock(raw_spinlock_t *lock)
 }
 #endif
 
-#define __raw_spin_lock_flags(lock, flags) __raw_spin_lock(lock)
+static inline int __ticket_spin_is_locked(raw_spinlock_t *lock)
+{
+        int tmp = ACCESS_ONCE(lock->slock);
+
+        return !!(((tmp >> TICKET_SHIFT) ^ tmp) & ((1 << TICKET_SHIFT) - 1));
+}
+
+static inline int __ticket_spin_is_contended(raw_spinlock_t *lock)
+{
+        int tmp = ACCESS_ONCE(lock->slock);
+
+        return (((tmp >> TICKET_SHIFT) - tmp) & ((1 << TICKET_SHIFT) - 1)) > 1;
+}
 
 #ifdef CONFIG_PARAVIRT
 /*
@@ -272,6 +260,13 @@ static __always_inline void __raw_spin_unlock(raw_spinlock_t *lock)
 {
         __ticket_spin_unlock(lock);
 }
+
+static __always_inline void __raw_spin_lock_flags(raw_spinlock_t *lock,
+                                                  unsigned long flags)
+{
+        __raw_spin_lock(lock);
+}
+
 #endif  /* CONFIG_PARAVIRT */
 
 static inline void __raw_spin_unlock_wait(raw_spinlock_t *lock)
@@ -366,4 +361,4 @@ static inline void __raw_write_unlock(raw_rwlock_t *rw)
 #define _raw_read_relax(lock)   cpu_relax()
 #define _raw_write_relax(lock)  cpu_relax()
 
-#endif
+#endif /* ASM_X86__SPINLOCK_H */
diff --git a/include/asm-x86/spinlock_types.h b/include/asm-x86/spinlock_types.h
index 06c071c9eee9..6aa9b562c508 100644
--- a/include/asm-x86/spinlock_types.h
+++ b/include/asm-x86/spinlock_types.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_SPINLOCK_TYPES_H
-#define __ASM_SPINLOCK_TYPES_H
+#ifndef ASM_X86__SPINLOCK_TYPES_H
+#define ASM_X86__SPINLOCK_TYPES_H
 
 #ifndef __LINUX_SPINLOCK_TYPES_H
 # error "please don't include this file directly"
@@ -17,4 +17,4 @@ typedef struct {
 
 #define __RAW_RW_LOCK_UNLOCKED          { RW_LOCK_BIAS }
 
-#endif
+#endif /* ASM_X86__SPINLOCK_TYPES_H */
diff --git a/include/asm-x86/srat.h b/include/asm-x86/srat.h
index 774c919dc232..5363e4f7e1cd 100644
--- a/include/asm-x86/srat.h
+++ b/include/asm-x86/srat.h
@@ -24,8 +24,8 @@
  * Send feedback to Pat Gaughen <gone@us.ibm.com>
  */
 
-#ifndef _ASM_SRAT_H_
-#define _ASM_SRAT_H_
+#ifndef ASM_X86__SRAT_H
+#define ASM_X86__SRAT_H
 
 #ifdef CONFIG_ACPI_NUMA
 extern int get_memcfg_from_srat(void);
@@ -36,4 +36,4 @@ static inline int get_memcfg_from_srat(void)
 }
 #endif
 
-#endif /* _ASM_SRAT_H_ */
+#endif /* ASM_X86__SRAT_H */
diff --git a/include/asm-x86/stacktrace.h b/include/asm-x86/stacktrace.h
index 30f82526a8e2..f43517e28532 100644
--- a/include/asm-x86/stacktrace.h
+++ b/include/asm-x86/stacktrace.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_STACKTRACE_H
-#define _ASM_STACKTRACE_H 1
+#ifndef ASM_X86__STACKTRACE_H
+#define ASM_X86__STACKTRACE_H
 
 extern int kstack_depth_to_print;
 
@@ -18,4 +18,4 @@ void dump_trace(struct task_struct *tsk, struct pt_regs *regs,
                 unsigned long *stack, unsigned long bp,
                 const struct stacktrace_ops *ops, void *data);
 
-#endif
+#endif /* ASM_X86__STACKTRACE_H */
diff --git a/include/asm-x86/stat.h b/include/asm-x86/stat.h
index 5c22dcb5d17e..1e120f628905 100644
--- a/include/asm-x86/stat.h
+++ b/include/asm-x86/stat.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_STAT_H
-#define _ASM_X86_STAT_H
+#ifndef ASM_X86__STAT_H
+#define ASM_X86__STAT_H
 
 #define STAT_HAVE_NSEC 1
 
@@ -111,4 +111,4 @@ struct __old_kernel_stat {
 #endif
 };
 
-#endif
+#endif /* ASM_X86__STAT_H */
diff --git a/include/asm-x86/statfs.h b/include/asm-x86/statfs.h
index 7c651aa97252..ca5dc19dd461 100644
--- a/include/asm-x86/statfs.h
+++ b/include/asm-x86/statfs.h
@@ -1,63 +1,12 @@
-#ifndef _ASM_X86_STATFS_H
-#define _ASM_X86_STATFS_H
-
-#ifdef __i386__
-#include <asm-generic/statfs.h>
-#else
-
-#ifndef __KERNEL_STRICT_NAMES
-
-#include <linux/types.h>
-
-typedef __kernel_fsid_t fsid_t;
-
-#endif
+#ifndef ASM_X86__STATFS_H
+#define ASM_X86__STATFS_H
 
 /*
- * This is ugly -- we're already 64-bit clean, so just duplicate the
- * definitions.
+ * We need compat_statfs64 to be packed, because the i386 ABI won't
+ * add padding at the end to bring it to a multiple of 8 bytes, but
+ * the x86_64 ABI will.
  */
-struct statfs {
-        long f_type;
-        long f_bsize;
-        long f_blocks;
-        long f_bfree;
-        long f_bavail;
-        long f_files;
-        long f_ffree;
-        __kernel_fsid_t f_fsid;
-        long f_namelen;
-        long f_frsize;
-        long f_spare[5];
-};
-
-struct statfs64 {
-        long f_type;
-        long f_bsize;
-        long f_blocks;
-        long f_bfree;
-        long f_bavail;
-        long f_files;
-        long f_ffree;
-        __kernel_fsid_t f_fsid;
-        long f_namelen;
-        long f_frsize;
-        long f_spare[5];
-};
+#define ARCH_PACK_COMPAT_STATFS64 __attribute__((packed,aligned(4)))
 
-struct compat_statfs64 {
-        __u32 f_type;
-        __u32 f_bsize;
-        __u64 f_blocks;
-        __u64 f_bfree;
-        __u64 f_bavail;
-        __u64 f_files;
-        __u64 f_ffree;
-        __kernel_fsid_t f_fsid;
-        __u32 f_namelen;
-        __u32 f_frsize;
-        __u32 f_spare[5];
-} __attribute__((packed));
-
-#endif /* !__i386__ */
-#endif
+#include <asm-generic/statfs.h>
+#endif /* ASM_X86__STATFS_H */
diff --git a/include/asm-x86/string_32.h b/include/asm-x86/string_32.h
index 193578cd1fd9..487843ed245a 100644
--- a/include/asm-x86/string_32.h
+++ b/include/asm-x86/string_32.h
@@ -1,5 +1,5 @@
-#ifndef _I386_STRING_H_
-#define _I386_STRING_H_
+#ifndef ASM_X86__STRING_32_H
+#define ASM_X86__STRING_32_H
 
 #ifdef __KERNEL__
 
@@ -323,4 +323,4 @@ extern void *memscan(void *addr, int c, size_t size);
 
 #endif /* __KERNEL__ */
 
-#endif
+#endif /* ASM_X86__STRING_32_H */
diff --git a/include/asm-x86/string_64.h b/include/asm-x86/string_64.h
index 52b5ab383395..a2add11d3b66 100644
--- a/include/asm-x86/string_64.h
+++ b/include/asm-x86/string_64.h
@@ -1,5 +1,5 @@
-#ifndef _X86_64_STRING_H_
-#define _X86_64_STRING_H_
+#ifndef ASM_X86__STRING_64_H
+#define ASM_X86__STRING_64_H
 
 #ifdef __KERNEL__
 
@@ -57,4 +57,4 @@ int strcmp(const char *cs, const char *ct);
 
 #endif /* __KERNEL__ */
 
-#endif
+#endif /* ASM_X86__STRING_64_H */
diff --git a/include/asm-x86/mach-summit/mach_apic.h b/include/asm-x86/summit/apic.h
index c47e2ab5c5ca..394b00bb5e72 100644
--- a/include/asm-x86/mach-summit/mach_apic.h
+++ b/include/asm-x86/summit/apic.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_APIC_H
-#define __ASM_MACH_APIC_H
+#ifndef __ASM_SUMMIT_APIC_H
+#define __ASM_SUMMIT_APIC_H
 
 #include <asm/smp.h>
 
@@ -21,7 +21,7 @@ static inline cpumask_t target_cpus(void)
          * Just start on cpu 0.  IRQ balancing will spread load
          */
         return cpumask_of_cpu(0);
-} 
+}
 #define TARGET_CPUS     (target_cpus())
 
 #define INT_DELIVERY_MODE (dest_LowestPrio)
@@ -30,10 +30,10 @@ static inline cpumask_t target_cpus(void)
 static inline unsigned long check_apicid_used(physid_mask_t bitmap, int apicid)
 {
         return 0;
-} 
+}
 
 /* we don't use the phys_cpu_present_map to indicate apicid presence */
-static inline unsigned long check_apicid_present(int bit) 
+static inline unsigned long check_apicid_present(int bit)
 {
         return 1;
 }
@@ -122,7 +122,7 @@ static inline physid_mask_t ioapic_phys_id_map(physid_mask_t phys_id_map)
 
 static inline physid_mask_t apicid_to_cpu_present(int apicid)
 {
-        return physid_mask_of_physid(apicid);
+        return physid_mask_of_physid(0);
 }
 
 static inline void setup_portio_remap(void)
@@ -143,24 +143,24 @@ static inline unsigned int cpu_mask_to_apicid(cpumask_t cpumask)
         int num_bits_set;
         int cpus_found = 0;
         int cpu;
-        int apicid;     
+        int apicid;
 
         num_bits_set = cpus_weight(cpumask);
         /* Return id to all */
         if (num_bits_set == NR_CPUS)
                 return (int) 0xFF;
-        /* 
-         * The cpus in the mask must all be on the apic cluster.  If are not 
-         * on the same apicid cluster return default value of TARGET_CPUS. 
+        /*
+         * The cpus in the mask must all be on the apic cluster.  If are not
+         * on the same apicid cluster return default value of TARGET_CPUS.
          */
         cpu = first_cpu(cpumask);
         apicid = cpu_to_logical_apicid(cpu);
         while (cpus_found < num_bits_set) {
                 if (cpu_isset(cpu, cpumask)) {
                         int new_apicid = cpu_to_logical_apicid(cpu);
-                        if (apicid_cluster(apicid) != 
+                        if (apicid_cluster(apicid) !=
                                         apicid_cluster(new_apicid)){
-                                printk ("%s: Not a valid mask!\n",__FUNCTION__);
+                                printk ("%s: Not a valid mask!\n", __func__);
                                 return 0xFF;
                         }
                         apicid = apicid | new_apicid;
@@ -182,4 +182,4 @@ static inline u32 phys_pkg_id(u32 cpuid_apic, int index_msb)
         return hard_smp_processor_id() >> index_msb;
 }
 
-#endif /* __ASM_MACH_APIC_H */
+#endif /* __ASM_SUMMIT_APIC_H */
diff --git a/include/asm-x86/summit/apicdef.h b/include/asm-x86/summit/apicdef.h
new file mode 100644
index 000000000000..f3fbca1f61c1
--- /dev/null
+++ b/include/asm-x86/summit/apicdef.h
@@ -0,0 +1,13 @@
+#ifndef __ASM_SUMMIT_APICDEF_H
+#define __ASM_SUMMIT_APICDEF_H
+
+#define         APIC_ID_MASK            (0xFF<<24)
+
+static inline unsigned get_apic_id(unsigned long x)
+{
+        return (x>>24)&0xFF;
+}
+
+#define         GET_APIC_ID(x)  get_apic_id(x)
+
+#endif
diff --git a/include/asm-x86/mach-summit/mach_ipi.h b/include/asm-x86/summit/ipi.h
index 9404c535b7ec..53bd1e7bd7b4 100644
--- a/include/asm-x86/mach-summit/mach_ipi.h
+++ b/include/asm-x86/summit/ipi.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_MACH_IPI_H
-#define __ASM_MACH_IPI_H
+#ifndef __ASM_SUMMIT_IPI_H
+#define __ASM_SUMMIT_IPI_H
 
 void send_IPI_mask_sequence(cpumask_t mask, int vector);
 
@@ -22,4 +22,4 @@ static inline void send_IPI_all(int vector)
         send_IPI_mask(cpu_online_map, vector);
 }
 
-#endif /* __ASM_MACH_IPI_H */
+#endif /* __ASM_SUMMIT_IPI_H */
diff --git a/include/asm-x86/mach-summit/irq_vectors_limits.h b/include/asm-x86/summit/irq_vectors_limits.h
index 890ce3f5e09a..890ce3f5e09a 100644
--- a/include/asm-x86/mach-summit/irq_vectors_limits.h
+++ b/include/asm-x86/summit/irq_vectors_limits.h
diff --git a/include/asm-x86/mach-summit/mach_mpparse.h b/include/asm-x86/summit/mpparse.h
index fdf591701339..013ce6fab2d5 100644
--- a/include/asm-x86/mach-summit/mach_mpparse.h
+++ b/include/asm-x86/summit/mpparse.h
@@ -1,7 +1,6 @@
-#ifndef __ASM_MACH_MPPARSE_H
-#define __ASM_MACH_MPPARSE_H
+#ifndef __ASM_SUMMIT_MPPARSE_H
+#define __ASM_SUMMIT_MPPARSE_H
 
-#include <mach_apic.h>
 #include <asm/tsc.h>
 
 extern int use_cyclone;
@@ -12,11 +11,11 @@ extern void setup_summit(void);
 #define setup_summit()  {}
 #endif
 
-static inline int mps_oem_check(struct mp_config_table *mpc, char *oem, 
+static inline int mps_oem_check(struct mp_config_table *mpc, char *oem,
                 char *productid)
 {
-        if (!strncmp(oem, "IBM ENSW", 8) && 
-                        (!strncmp(productid, "VIGIL SMP", 9) 
+        if (!strncmp(oem, "IBM ENSW", 8) &&
+                        (!strncmp(productid, "VIGIL SMP", 9)
                          || !strncmp(productid, "EXA", 3)
                          || !strncmp(productid, "RUTHLESS SMP", 12))){
                 mark_tsc_unstable("Summit based system");
@@ -107,4 +106,4 @@ static inline int is_WPEG(struct rio_detail *rio){
                 rio->type == LookOutAWPEG || rio->type == LookOutBWPEG);
 }
 
-#endif /* __ASM_MACH_MPPARSE_H */
+#endif /* __ASM_SUMMIT_MPPARSE_H */
diff --git a/include/asm-x86/suspend_32.h b/include/asm-x86/suspend_32.h
index 8675c6782a7d..acb6d4d491f4 100644
--- a/include/asm-x86/suspend_32.h
+++ b/include/asm-x86/suspend_32.h
@@ -3,8 +3,8 @@
  * Based on code
  * Copyright 2001 Patrick Mochel <mochel@osdl.org>
  */
-#ifndef __ASM_X86_32_SUSPEND_H
-#define __ASM_X86_32_SUSPEND_H
+#ifndef ASM_X86__SUSPEND_32_H
+#define ASM_X86__SUSPEND_32_H
 
 #include <asm/desc.h>
 #include <asm/i387.h>
@@ -48,4 +48,4 @@ static inline void acpi_save_register_state(unsigned long return_point)
 extern int acpi_save_state_mem(void);
 #endif
 
-#endif /* __ASM_X86_32_SUSPEND_H */
+#endif /* ASM_X86__SUSPEND_32_H */
diff --git a/include/asm-x86/suspend_64.h b/include/asm-x86/suspend_64.h
index dc3262b43072..cf821dd310e8 100644
--- a/include/asm-x86/suspend_64.h
+++ b/include/asm-x86/suspend_64.h
@@ -3,8 +3,8 @@
  * Based on code
  * Copyright 2001 Patrick Mochel <mochel@osdl.org>
  */
-#ifndef __ASM_X86_64_SUSPEND_H
-#define __ASM_X86_64_SUSPEND_H
+#ifndef ASM_X86__SUSPEND_64_H
+#define ASM_X86__SUSPEND_64_H
 
 #include <asm/desc.h>
 #include <asm/i387.h>
@@ -49,4 +49,4 @@ extern int acpi_save_state_mem(void);
 extern char core_restore_code;
 extern char restore_registers;
 
-#endif /* __ASM_X86_64_SUSPEND_H */
+#endif /* ASM_X86__SUSPEND_64_H */
diff --git a/include/asm-x86/swiotlb.h b/include/asm-x86/swiotlb.h
index 2730b351afcf..1e20adbcad4b 100644
--- a/include/asm-x86/swiotlb.h
+++ b/include/asm-x86/swiotlb.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_SWIOTLB_H
-#define _ASM_SWIOTLB_H 1
+#ifndef ASM_X86__SWIOTLB_H
+#define ASM_X86__SWIOTLB_H
 
 #include <asm/dma-mapping.h>
 
@@ -55,4 +55,4 @@ static inline void pci_swiotlb_init(void)
 
 static inline void dma_mark_clean(void *addr, size_t size) {}
 
-#endif /* _ASM_SWIOTLB_H */
+#endif /* ASM_X86__SWIOTLB_H */
diff --git a/include/asm-x86/sync_bitops.h b/include/asm-x86/sync_bitops.h
index b47a1d0b8a83..b689bee71104 100644
--- a/include/asm-x86/sync_bitops.h
+++ b/include/asm-x86/sync_bitops.h
@@ -1,5 +1,5 @@
-#ifndef _I386_SYNC_BITOPS_H
-#define _I386_SYNC_BITOPS_H
+#ifndef ASM_X86__SYNC_BITOPS_H
+#define ASM_X86__SYNC_BITOPS_H
 
 /*
  * Copyright 1992, Linus Torvalds.
@@ -127,4 +127,4 @@ static inline int sync_test_and_change_bit(int nr, volatile unsigned long *addr)
 
 #undef ADDR
 
-#endif /* _I386_SYNC_BITOPS_H */
+#endif /* ASM_X86__SYNC_BITOPS_H */
diff --git a/include/asm-x86/syscall.h b/include/asm-x86/syscall.h
new file mode 100644
index 000000000000..04c47dc5597c
--- /dev/null
+++ b/include/asm-x86/syscall.h
@@ -0,0 +1,211 @@
+/*
+ * Access to user system call parameters and results
+ *
+ * Copyright (C) 2008 Red Hat, Inc.  All rights reserved.
+ *
+ * This copyrighted material is made available to anyone wishing to use,
+ * modify, copy, or redistribute it subject to the terms and conditions
+ * of the GNU General Public License v.2.
+ *
+ * See asm-generic/syscall.h for descriptions of what we must do here.
+ */
+
+#ifndef _ASM_SYSCALL_H
+#define _ASM_SYSCALL_H  1
+
+#include <linux/sched.h>
+#include <linux/err.h>
+
+static inline long syscall_get_nr(struct task_struct *task,
+                                  struct pt_regs *regs)
+{
+        /*
+         * We always sign-extend a -1 value being set here,
+         * so this is always either -1L or a syscall number.
+         */
+        return regs->orig_ax;
+}
+
+static inline void syscall_rollback(struct task_struct *task,
+                                    struct pt_regs *regs)
+{
+        regs->ax = regs->orig_ax;
+}
+
+static inline long syscall_get_error(struct task_struct *task,
+                                     struct pt_regs *regs)
+{
+        unsigned long error = regs->ax;
+#ifdef CONFIG_IA32_EMULATION
+        /*
+         * TS_COMPAT is set for 32-bit syscall entries and then
+         * remains set until we return to user mode.
+         */
+        if (task_thread_info(task)->status & TS_COMPAT)
+                /*
+                 * Sign-extend the value so (int)-EFOO becomes (long)-EFOO
+                 * and will match correctly in comparisons.
+                 */
+                error = (long) (int) error;
+#endif
+        return IS_ERR_VALUE(error) ? error : 0;
+}
+
+static inline long syscall_get_return_value(struct task_struct *task,
+                                            struct pt_regs *regs)
+{
+        return regs->ax;
+}
+
+static inline void syscall_set_return_value(struct task_struct *task,
+                                            struct pt_regs *regs,
+                                            int error, long val)
+{
+        regs->ax = (long) error ?: val;
+}
+
+#ifdef CONFIG_X86_32
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+        memcpy(args, &regs->bx + i, n * sizeof(args[0]));
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+        BUG_ON(i + n > 6);
+        memcpy(&regs->bx + i, args, n * sizeof(args[0]));
+}
+
+#else    /* CONFIG_X86_64 */
+
+static inline void syscall_get_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         unsigned long *args)
+{
+# ifdef CONFIG_IA32_EMULATION
+        if (task_thread_info(task)->status & TS_COMPAT)
+                switch (i + n) {
+                case 6:
+                        if (!n--) break;
+                        *args++ = regs->bp;
+                case 5:
+                        if (!n--) break;
+                        *args++ = regs->di;
+                case 4:
+                        if (!n--) break;
+                        *args++ = regs->si;
+                case 3:
+                        if (!n--) break;
+                        *args++ = regs->dx;
+                case 2:
+                        if (!n--) break;
+                        *args++ = regs->cx;
+                case 1:
+                        if (!n--) break;
+                        *args++ = regs->bx;
+                case 0:
+                        if (!n--) break;
+                default:
+                        BUG();
+                        break;
+                }
+        else
+# endif
+                switch (i + n) {
+                case 6:
+                        if (!n--) break;
+                        *args++ = regs->r9;
+                case 5:
+                        if (!n--) break;
+                        *args++ = regs->r8;
+                case 4:
+                        if (!n--) break;
+                        *args++ = regs->r10;
+                case 3:
+                        if (!n--) break;
+                        *args++ = regs->dx;
+                case 2:
+                        if (!n--) break;
+                        *args++ = regs->si;
+                case 1:
+                        if (!n--) break;
+                        *args++ = regs->di;
+                case 0:
+                        if (!n--) break;
+                default:
+                        BUG();
+                        break;
+                }
+}
+
+static inline void syscall_set_arguments(struct task_struct *task,
+                                         struct pt_regs *regs,
+                                         unsigned int i, unsigned int n,
+                                         const unsigned long *args)
+{
+# ifdef CONFIG_IA32_EMULATION
+        if (task_thread_info(task)->status & TS_COMPAT)
+                switch (i + n) {
+                case 6:
+                        if (!n--) break;
+                        regs->bp = *args++;
+                case 5:
+                        if (!n--) break;
+                        regs->di = *args++;
+                case 4:
+                        if (!n--) break;
+                        regs->si = *args++;
+                case 3:
+                        if (!n--) break;
+                        regs->dx = *args++;
+                case 2:
+                        if (!n--) break;
+                        regs->cx = *args++;
+                case 1:
+                        if (!n--) break;
+                        regs->bx = *args++;
+                case 0:
+                        if (!n--) break;
+                default:
+                        BUG();
+                }
+        else
+# endif
+                switch (i + n) {
+                case 6:
+                        if (!n--) break;
+                        regs->r9 = *args++;
+                case 5:
+                        if (!n--) break;
+                        regs->r8 = *args++;
+                case 4:
+                        if (!n--) break;
+                        regs->r10 = *args++;
+                case 3:
+                        if (!n--) break;
+                        regs->dx = *args++;
+                case 2:
+                        if (!n--) break;
+                        regs->si = *args++;
+                case 1:
+                        if (!n--) break;
+                        regs->di = *args++;
+                case 0:
+                        if (!n--) break;
+                default:
+                        BUG();
+                }
+}
+
+#endif  /* CONFIG_X86_32 */
+
+#endif  /* _ASM_SYSCALL_H */
diff --git a/include/asm-x86/syscalls.h b/include/asm-x86/syscalls.h
new file mode 100644
index 000000000000..87803da44010
--- /dev/null
+++ b/include/asm-x86/syscalls.h
@@ -0,0 +1,93 @@
+/*
+ * syscalls.h - Linux syscall interfaces (arch-specific)
+ *
+ * Copyright (c) 2008 Jaswinder Singh
+ *
+ * This file is released under the GPLv2.
+ * See the file COPYING for more details.
+ */
+
+#ifndef _ASM_X86_SYSCALLS_H
+#define _ASM_X86_SYSCALLS_H
+
+#include <linux/compiler.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+#include <linux/signal.h>
+
+/* Common in X86_32 and X86_64 */
+/* kernel/ioport.c */
+asmlinkage long sys_ioperm(unsigned long, unsigned long, int);
+
+/* X86_32 only */
+#ifdef CONFIG_X86_32
+/* kernel/process_32.c */
+asmlinkage int sys_fork(struct pt_regs);
+asmlinkage int sys_clone(struct pt_regs);
+asmlinkage int sys_vfork(struct pt_regs);
+asmlinkage int sys_execve(struct pt_regs);
+
+/* kernel/signal_32.c */
+asmlinkage int sys_sigsuspend(int, int, old_sigset_t);
+asmlinkage int sys_sigaction(int, const struct old_sigaction __user *,
+                             struct old_sigaction __user *);
+asmlinkage int sys_sigaltstack(unsigned long);
+asmlinkage unsigned long sys_sigreturn(unsigned long);
+asmlinkage int sys_rt_sigreturn(unsigned long);
+
+/* kernel/ioport.c */
+asmlinkage long sys_iopl(unsigned long);
+
+/* kernel/ldt.c */
+asmlinkage int sys_modify_ldt(int, void __user *, unsigned long);
+
+/* kernel/sys_i386_32.c */
+asmlinkage long sys_mmap2(unsigned long, unsigned long, unsigned long,
+                          unsigned long, unsigned long, unsigned long);
+struct mmap_arg_struct;
+asmlinkage int old_mmap(struct mmap_arg_struct __user *);
+struct sel_arg_struct;
+asmlinkage int old_select(struct sel_arg_struct __user *);
+asmlinkage int sys_ipc(uint, int, int, int, void __user *, long);
+struct old_utsname;
+asmlinkage int sys_uname(struct old_utsname __user *);
+struct oldold_utsname;
+asmlinkage int sys_olduname(struct oldold_utsname __user *);
+
+/* kernel/tls.c */
+asmlinkage int sys_set_thread_area(struct user_desc __user *);
+asmlinkage int sys_get_thread_area(struct user_desc __user *);
+
+/* kernel/vm86_32.c */
+asmlinkage int sys_vm86old(struct pt_regs);
+asmlinkage int sys_vm86(struct pt_regs);
+
+#else /* CONFIG_X86_32 */
+
+/* X86_64 only */
+/* kernel/process_64.c */
+asmlinkage long sys_fork(struct pt_regs *);
+asmlinkage long sys_clone(unsigned long, unsigned long,
+                          void __user *, void __user *,
+                          struct pt_regs *);
+asmlinkage long sys_vfork(struct pt_regs *);
+asmlinkage long sys_execve(char __user *, char __user * __user *,
+                           char __user * __user *,
+                           struct pt_regs *);
+
+/* kernel/ioport.c */
+asmlinkage long sys_iopl(unsigned int, struct pt_regs *);
+
+/* kernel/signal_64.c */
+asmlinkage long sys_sigaltstack(const stack_t __user *, stack_t __user *,
+                                struct pt_regs *);
+asmlinkage long sys_rt_sigreturn(struct pt_regs *);
+
+/* kernel/sys_x86_64.c */
+asmlinkage long sys_mmap(unsigned long, unsigned long, unsigned long,
+                         unsigned long, unsigned long, unsigned long);
+struct new_utsname;
+asmlinkage long sys_uname(struct new_utsname __user *);
+
+#endif /* CONFIG_X86_32 */
+#endif /* _ASM_X86_SYSCALLS_H */
diff --git a/include/asm-x86/system.h b/include/asm-x86/system.h
index 983ce37c491f..b20c894660f9 100644
--- a/include/asm-x86/system.h
+++ b/include/asm-x86/system.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_SYSTEM_H_
-#define _ASM_X86_SYSTEM_H_
+#ifndef ASM_X86__SYSTEM_H
+#define ASM_X86__SYSTEM_H
 
 #include <asm/asm.h>
 #include <asm/segment.h>
@@ -64,7 +64,10 @@ do {									\
                                                                         \
                        /* regparm parameters for __switch_to(): */      \
                        [prev]     "a" (prev),                           \
-                       [next]     "d" (next));                          \
+                       [next]     "d" (next)                            \
+                                                                        \
+                     : /* reloaded segment registers */                 \
+                        "memory");                                      \
 } while (0)
 
 /*
@@ -419,4 +422,4 @@ static inline void rdtsc_barrier(void)
         alternative(ASM_NOP3, "lfence", X86_FEATURE_LFENCE_RDTSC);
 }
 
-#endif
+#endif /* ASM_X86__SYSTEM_H */
diff --git a/include/asm-x86/system_64.h b/include/asm-x86/system_64.h
index 97fa251ccb2b..5aedb8bffc5a 100644
--- a/include/asm-x86/system_64.h
+++ b/include/asm-x86/system_64.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_SYSTEM_H
-#define __ASM_SYSTEM_H
+#ifndef ASM_X86__SYSTEM_64_H
+#define ASM_X86__SYSTEM_64_H
 
 #include <asm/segment.h>
 #include <asm/cmpxchg.h>
@@ -19,4 +19,4 @@ static inline void write_cr8(unsigned long val)
 
 #include <linux/irqflags.h>
 
-#endif
+#endif /* ASM_X86__SYSTEM_64_H */
diff --git a/include/asm-x86/tce.h b/include/asm-x86/tce.h
index b1a4ea00df78..e7932d7fbbab 100644
--- a/include/asm-x86/tce.h
+++ b/include/asm-x86/tce.h
@@ -21,8 +21,8 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  */
 
-#ifndef _ASM_X86_64_TCE_H
-#define _ASM_X86_64_TCE_H
+#ifndef ASM_X86__TCE_H
+#define ASM_X86__TCE_H
 
 extern unsigned int specified_table_size;
 struct iommu_table;
@@ -45,4 +45,4 @@ extern void * __init alloc_tce_table(void);
 extern void __init free_tce_table(void *tbl);
 extern int __init build_tce_table(struct pci_dev *dev, void __iomem *bbar);
 
-#endif /* _ASM_X86_64_TCE_H */
+#endif /* ASM_X86__TCE_H */
diff --git a/include/asm-x86/termbits.h b/include/asm-x86/termbits.h
index af1b70ea440f..3d00dc5e0c71 100644
--- a/include/asm-x86/termbits.h
+++ b/include/asm-x86/termbits.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_TERMBITS_H
-#define _ASM_X86_TERMBITS_H
+#ifndef ASM_X86__TERMBITS_H
+#define ASM_X86__TERMBITS_H
 
 #include <linux/posix_types.h>
 
@@ -195,4 +195,4 @@ struct ktermios {
 #define TCSADRAIN       1
 #define TCSAFLUSH       2
 
-#endif /* _ASM_X86_TERMBITS_H */
+#endif /* ASM_X86__TERMBITS_H */
diff --git a/include/asm-x86/termios.h b/include/asm-x86/termios.h
index f72956331c49..e235db248071 100644
--- a/include/asm-x86/termios.h
+++ b/include/asm-x86/termios.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_TERMIOS_H
-#define _ASM_X86_TERMIOS_H
+#ifndef ASM_X86__TERMIOS_H
+#define ASM_X86__TERMIOS_H
 
 #include <asm/termbits.h>
 #include <asm/ioctls.h>
@@ -110,4 +110,4 @@ static inline int kernel_termios_to_user_termios_1(struct termios __user *u,
 
 #endif  /* __KERNEL__ */
 
-#endif /* _ASM_X86_TERMIOS_H */
+#endif /* ASM_X86__TERMIOS_H */
diff --git a/include/asm-x86/therm_throt.h b/include/asm-x86/therm_throt.h
index 399bf6026b16..1c7f57b6b66e 100644
--- a/include/asm-x86/therm_throt.h
+++ b/include/asm-x86/therm_throt.h
@@ -1,9 +1,9 @@
-#ifndef __ASM_I386_THERM_THROT_H__
-#define __ASM_I386_THERM_THROT_H__ 1
+#ifndef ASM_X86__THERM_THROT_H
+#define ASM_X86__THERM_THROT_H
 
 #include <asm/atomic.h>
 
 extern atomic_t therm_throt_en;
 int therm_throt_process(int curr);
 
-#endif /* __ASM_I386_THERM_THROT_H__ */
+#endif /* ASM_X86__THERM_THROT_H */
diff --git a/include/asm-x86/thread_info.h b/include/asm-x86/thread_info.h
index da0a675adf94..3f4e52bb77f5 100644
--- a/include/asm-x86/thread_info.h
+++ b/include/asm-x86/thread_info.h
@@ -4,8 +4,8 @@
  * - Incorporating suggestions made by Linus Torvalds and Dave Miller
  */
 
-#ifndef _ASM_X86_THREAD_INFO_H
-#define _ASM_X86_THREAD_INFO_H
+#ifndef ASM_X86__THREAD_INFO_H
+#define ASM_X86__THREAD_INFO_H
 
 #include <linux/compiler.h>
 #include <asm/page.h>
@@ -71,6 +71,7 @@ struct thread_info {
  * Warning: layout of LSW is hardcoded in entry.S
  */
 #define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* callback before returning to user */
 #define TIF_SIGPENDING          2       /* signal pending */
 #define TIF_NEED_RESCHED        3       /* rescheduling necessary */
 #define TIF_SINGLESTEP          4       /* reenable singlestep on user return*/
@@ -93,6 +94,7 @@ struct thread_info {
 #define TIF_BTS_TRACE_TS        27      /* record scheduling event timestamps */
 
 #define _TIF_SYSCALL_TRACE      (1 << TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1 << TIF_NOTIFY_RESUME)
 #define _TIF_SIGPENDING         (1 << TIF_SIGPENDING)
 #define _TIF_SINGLESTEP         (1 << TIF_SINGLESTEP)
 #define _TIF_NEED_RESCHED       (1 << TIF_NEED_RESCHED)
@@ -133,7 +135,7 @@ struct thread_info {
 
 /* Only used for 64 bit */
 #define _TIF_DO_NOTIFY_MASK                                             \
-        (_TIF_SIGPENDING|_TIF_MCE_NOTIFY)
+        (_TIF_SIGPENDING|_TIF_MCE_NOTIFY|_TIF_NOTIFY_RESUME)
 
 /* flags to check in __switch_to() */
 #define _TIF_WORK_CTXSW                                                 \
@@ -239,6 +241,7 @@ static inline struct thread_info *stack_thread_info(void)
 #define TS_POLLING              0x0004  /* true if in idle loop
                                            and not sleeping */
 #define TS_RESTORE_SIGMASK      0x0008  /* restore signal mask in do_signal() */
+#define TS_XSAVE                0x0010  /* Use xsave/xrstor */
 
 #define tsk_is_polling(t) (task_thread_info(t)->status & TS_POLLING)
 
@@ -258,4 +261,4 @@ extern void free_thread_info(struct thread_info *ti);
 extern int arch_dup_task_struct(struct task_struct *dst, struct task_struct *src);
 #define arch_task_cache_init arch_task_cache_init
 #endif
-#endif /* _ASM_X86_THREAD_INFO_H */
+#endif /* ASM_X86__THREAD_INFO_H */
diff --git a/include/asm-x86/time.h b/include/asm-x86/time.h
index a17fa473e91d..3e724eef7ac4 100644
--- a/include/asm-x86/time.h
+++ b/include/asm-x86/time.h
@@ -1,5 +1,5 @@
-#ifndef _ASMX86_TIME_H
-#define _ASMX86_TIME_H
+#ifndef ASM_X86__TIME_H
+#define ASM_X86__TIME_H
 
 extern void hpet_time_init(void);
 
@@ -46,6 +46,8 @@ static inline int native_set_wallclock(unsigned long nowtime)
 
 #endif
 
+extern void time_init(void);
+
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else /* !CONFIG_PARAVIRT */
@@ -58,4 +60,4 @@ static inline int native_set_wallclock(unsigned long nowtime)
 
 extern unsigned long __init calibrate_cpu(void);
 
-#endif
+#endif /* ASM_X86__TIME_H */
diff --git a/include/asm-x86/timer.h b/include/asm-x86/timer.h
index fb2a4ddddf3d..d0babce4b47a 100644
--- a/include/asm-x86/timer.h
+++ b/include/asm-x86/timer.h
@@ -1,5 +1,5 @@
-#ifndef _ASMi386_TIMER_H
-#define _ASMi386_TIMER_H
+#ifndef ASM_X86__TIMER_H
+#define ASM_X86__TIMER_H
 #include <linux/init.h>
 #include <linux/pm.h>
 #include <linux/percpu.h>
@@ -9,9 +9,12 @@
 unsigned long long native_sched_clock(void);
 unsigned long native_calibrate_tsc(void);
 
+#ifdef CONFIG_X86_32
 extern int timer_ack;
-extern int no_timer_check;
 extern int recalibrate_cpu_khz(void);
+#endif /* CONFIG_X86_32 */
+
+extern int no_timer_check;
 
 #ifndef CONFIG_PARAVIRT
 #define calibrate_tsc() native_calibrate_tsc()
@@ -60,4 +63,4 @@ static inline unsigned long long cycles_2_ns(unsigned long long cyc)
         return ns;
 }
 
-#endif
+#endif /* ASM_X86__TIMER_H */
diff --git a/include/asm-x86/timex.h b/include/asm-x86/timex.h
index 43e5a78500c5..d1ce2416a5da 100644
--- a/include/asm-x86/timex.h
+++ b/include/asm-x86/timex.h
@@ -1,6 +1,6 @@
 /* x86 architecture timex specifications */
-#ifndef _ASM_X86_TIMEX_H
-#define _ASM_X86_TIMEX_H
+#ifndef ASM_X86__TIMEX_H
+#define ASM_X86__TIMEX_H
 
 #include <asm/processor.h>
 #include <asm/tsc.h>
@@ -16,4 +16,4 @@
 
 #define ARCH_HAS_READ_CURRENT_TIMER
 
-#endif
+#endif /* ASM_X86__TIMEX_H */
diff --git a/include/asm-x86/tlb.h b/include/asm-x86/tlb.h
index e4e9e2d07a93..db36e9e89e87 100644
--- a/include/asm-x86/tlb.h
+++ b/include/asm-x86/tlb.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_TLB_H
-#define _ASM_X86_TLB_H
+#ifndef ASM_X86__TLB_H
+#define ASM_X86__TLB_H
 
 #define tlb_start_vma(tlb, vma) do { } while (0)
 #define tlb_end_vma(tlb, vma) do { } while (0)
@@ -8,4 +8,4 @@
 
 #include <asm-generic/tlb.h>
 
-#endif
+#endif /* ASM_X86__TLB_H */
diff --git a/include/asm-x86/tlbflush.h b/include/asm-x86/tlbflush.h
index 35c76ceb9f40..3cdd08b5bdb7 100644
--- a/include/asm-x86/tlbflush.h
+++ b/include/asm-x86/tlbflush.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_TLBFLUSH_H
-#define _ASM_X86_TLBFLUSH_H
+#ifndef ASM_X86__TLBFLUSH_H
+#define ASM_X86__TLBFLUSH_H
 
 #include <linux/mm.h>
 #include <linux/sched.h>
@@ -119,6 +119,10 @@ static inline void native_flush_tlb_others(const cpumask_t *cpumask,
 {
 }
 
+static inline void reset_lazy_tlbstate(void)
+{
+}
+
 #else  /* SMP */
 
 #include <asm/smp.h>
@@ -151,6 +155,12 @@ struct tlb_state {
         char __cacheline_padding[L1_CACHE_BYTES-8];
 };
 DECLARE_PER_CPU(struct tlb_state, cpu_tlbstate);
+
+void reset_lazy_tlbstate(void);
+#else
+static inline void reset_lazy_tlbstate(void)
+{
+}
 #endif
 
 #endif  /* SMP */
@@ -165,4 +175,4 @@ static inline void flush_tlb_kernel_range(unsigned long start,
         flush_tlb_all();
 }
 
-#endif /* _ASM_X86_TLBFLUSH_H */
+#endif /* ASM_X86__TLBFLUSH_H */
diff --git a/include/asm-x86/topology.h b/include/asm-x86/topology.h
index 90ac7718469a..7eca9bc022b2 100644
--- a/include/asm-x86/topology.h
+++ b/include/asm-x86/topology.h
@@ -22,8 +22,8 @@
  *
  * Send feedback to <colpatch@us.ibm.com>
  */
-#ifndef _ASM_X86_TOPOLOGY_H
-#define _ASM_X86_TOPOLOGY_H
+#ifndef ASM_X86__TOPOLOGY_H
+#define ASM_X86__TOPOLOGY_H
 
 #ifdef CONFIG_X86_32
 # ifdef CONFIG_X86_HT
@@ -255,4 +255,4 @@ static inline void set_mp_bus_to_node(int busnum, int node)
 }
 #endif
 
-#endif /* _ASM_X86_TOPOLOGY_H */
+#endif /* ASM_X86__TOPOLOGY_H */
diff --git a/include/asm-x86/trampoline.h b/include/asm-x86/trampoline.h
index b156b08d0131..0406bbd898a9 100644
--- a/include/asm-x86/trampoline.h
+++ b/include/asm-x86/trampoline.h
@@ -1,5 +1,5 @@
-#ifndef __TRAMPOLINE_HEADER
-#define __TRAMPOLINE_HEADER
+#ifndef ASM_X86__TRAMPOLINE_H
+#define ASM_X86__TRAMPOLINE_H
 
 #ifndef __ASSEMBLY__
 
@@ -18,4 +18,4 @@ extern unsigned long setup_trampoline(void);
 
 #endif /* __ASSEMBLY__ */
 
-#endif /* __TRAMPOLINE_HEADER */
+#endif /* ASM_X86__TRAMPOLINE_H */
diff --git a/include/asm-x86/traps.h b/include/asm-x86/traps.h
index a4b65a71bd66..6c3dc2c65751 100644
--- a/include/asm-x86/traps.h
+++ b/include/asm-x86/traps.h
@@ -1,7 +1,14 @@
-#ifndef _ASM_X86_TRAPS_H
-#define _ASM_X86_TRAPS_H
+#ifndef ASM_X86__TRAPS_H
+#define ASM_X86__TRAPS_H
+
+#include <asm/debugreg.h>
+
+#ifdef CONFIG_X86_32
+#define dotraplinkage
+#else
+#define dotraplinkage asmlinkage
+#endif
 
-/* Common in X86_32 and X86_64 */
 asmlinkage void divide_error(void);
 asmlinkage void debug(void);
 asmlinkage void nmi(void);
@@ -10,57 +17,65 @@ asmlinkage void overflow(void);
 asmlinkage void bounds(void);
 asmlinkage void invalid_op(void);
 asmlinkage void device_not_available(void);
+#ifdef CONFIG_X86_64
+asmlinkage void double_fault(void);
+#endif
 asmlinkage void coprocessor_segment_overrun(void);
 asmlinkage void invalid_TSS(void);
 asmlinkage void segment_not_present(void);
 asmlinkage void stack_segment(void);
 asmlinkage void general_protection(void);
 asmlinkage void page_fault(void);
+asmlinkage void spurious_interrupt_bug(void);
 asmlinkage void coprocessor_error(void);
-asmlinkage void simd_coprocessor_error(void);
 asmlinkage void alignment_check(void);
-asmlinkage void spurious_interrupt_bug(void);
 #ifdef CONFIG_X86_MCE
 asmlinkage void machine_check(void);
 #endif /* CONFIG_X86_MCE */
+asmlinkage void simd_coprocessor_error(void);
 
-void do_divide_error(struct pt_regs *, long);
-void do_overflow(struct pt_regs *, long);
-void do_bounds(struct pt_regs *, long);
-void do_coprocessor_segment_overrun(struct pt_regs *, long);
-void do_invalid_TSS(struct pt_regs *, long);
-void do_segment_not_present(struct pt_regs *, long);
-void do_stack_segment(struct pt_regs *, long);
-void do_alignment_check(struct pt_regs *, long);
-void do_invalid_op(struct pt_regs *, long);
-void do_general_protection(struct pt_regs *, long);
-void do_nmi(struct pt_regs *, long);
+dotraplinkage void do_divide_error(struct pt_regs *, long);
+dotraplinkage void do_debug(struct pt_regs *, long);
+dotraplinkage void do_nmi(struct pt_regs *, long);
+dotraplinkage void do_int3(struct pt_regs *, long);
+dotraplinkage void do_overflow(struct pt_regs *, long);
+dotraplinkage void do_bounds(struct pt_regs *, long);
+dotraplinkage void do_invalid_op(struct pt_regs *, long);
+dotraplinkage void do_device_not_available(struct pt_regs *, long);
+dotraplinkage void do_coprocessor_segment_overrun(struct pt_regs *, long);
+dotraplinkage void do_invalid_TSS(struct pt_regs *, long);
+dotraplinkage void do_segment_not_present(struct pt_regs *, long);
+dotraplinkage void do_stack_segment(struct pt_regs *, long);
+dotraplinkage void do_general_protection(struct pt_regs *, long);
+dotraplinkage void do_page_fault(struct pt_regs *, unsigned long);
+dotraplinkage void do_spurious_interrupt_bug(struct pt_regs *, long);
+dotraplinkage void do_coprocessor_error(struct pt_regs *, long);
+dotraplinkage void do_alignment_check(struct pt_regs *, long);
+#ifdef CONFIG_X86_MCE
+dotraplinkage void do_machine_check(struct pt_regs *, long);
+#endif
+dotraplinkage void do_simd_coprocessor_error(struct pt_regs *, long);
+#ifdef CONFIG_X86_32
+dotraplinkage void do_iret_error(struct pt_regs *, long);
+#endif
+
+static inline int get_si_code(unsigned long condition)
+{
+        if (condition & DR_STEP)
+                return TRAP_TRACE;
+        else if (condition & (DR_TRAP0|DR_TRAP1|DR_TRAP2|DR_TRAP3))
+                return TRAP_HWBKPT;
+        else
+                return TRAP_BRKPT;
+}
 
 extern int panic_on_unrecovered_nmi;
 extern int kstack_depth_to_print;
 
 #ifdef CONFIG_X86_32
-
-void do_iret_error(struct pt_regs *, long);
-void do_int3(struct pt_regs *, long);
-void do_debug(struct pt_regs *, long);
 void math_error(void __user *);
-void do_coprocessor_error(struct pt_regs *, long);
-void do_simd_coprocessor_error(struct pt_regs *, long);
-void do_spurious_interrupt_bug(struct pt_regs *, long);
 unsigned long patch_espfix_desc(unsigned long, unsigned long);
 asmlinkage void math_emulate(long);
+#endif
 
-#else /* CONFIG_X86_32 */
-
-asmlinkage void double_fault(void);
-
-asmlinkage void do_int3(struct pt_regs *, long);
-asmlinkage void do_stack_segment(struct pt_regs *, long);
-asmlinkage void do_debug(struct pt_regs *, unsigned long);
-asmlinkage void do_coprocessor_error(struct pt_regs *);
-asmlinkage void do_simd_coprocessor_error(struct pt_regs *);
-asmlinkage void do_spurious_interrupt_bug(struct pt_regs *);
-
-#endif /* CONFIG_X86_32 */
-#endif /* _ASM_X86_TRAPS_H */
+#endif /* ASM_X86__TRAPS_H */
diff --git a/include/asm-x86/tsc.h b/include/asm-x86/tsc.h
index cb6f6ee45b8f..ad0f5c41e78c 100644
--- a/include/asm-x86/tsc.h
+++ b/include/asm-x86/tsc.h
@@ -1,8 +1,8 @@
 /*
  * x86 TSC related functions
  */
-#ifndef _ASM_X86_TSC_H
-#define _ASM_X86_TSC_H
+#ifndef ASM_X86__TSC_H
+#define ASM_X86__TSC_H
 
 #include <asm/processor.h>
 
@@ -59,4 +59,4 @@ extern void check_tsc_sync_target(void);
 
 extern int notsc_setup(char *);
 
-#endif
+#endif /* ASM_X86__TSC_H */
diff --git a/include/asm-x86/types.h b/include/asm-x86/types.h
index 1ac80cd9acf8..e78b52e17444 100644
--- a/include/asm-x86/types.h
+++ b/include/asm-x86/types.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_TYPES_H
-#define _ASM_X86_TYPES_H
+#ifndef ASM_X86__TYPES_H
+#define ASM_X86__TYPES_H
 
 #include <asm-generic/int-ll64.h>
 
@@ -33,4 +33,4 @@ typedef u32 dma_addr_t;
 #endif /* __ASSEMBLY__ */
 #endif /* __KERNEL__ */
 
-#endif
+#endif /* ASM_X86__TYPES_H */
diff --git a/include/asm-x86/uaccess.h b/include/asm-x86/uaccess.h
index 5f702d1d5218..48ebc0ad40ec 100644
--- a/include/asm-x86/uaccess.h
+++ b/include/asm-x86/uaccess.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_UACCES_H_
-#define _ASM_UACCES_H_
+#ifndef ASM_X86__UACCESS_H
+#define ASM_X86__UACCESS_H
 /*
  * User space memory access functions
  */
@@ -450,5 +450,5 @@ extern struct movsl_mask {
 # include "uaccess_64.h"
 #endif
 
-#endif
+#endif /* ASM_X86__UACCESS_H */
 
diff --git a/include/asm-x86/uaccess_32.h b/include/asm-x86/uaccess_32.h
index 6fdef39a0bcb..6b5b57d9c6d1 100644
--- a/include/asm-x86/uaccess_32.h
+++ b/include/asm-x86/uaccess_32.h
@@ -1,5 +1,5 @@
-#ifndef __i386_UACCESS_H
-#define __i386_UACCESS_H
+#ifndef ASM_X86__UACCESS_32_H
+#define ASM_X86__UACCESS_32_H
 
 /*
  * User space memory access functions
@@ -215,4 +215,4 @@ long strnlen_user(const char __user *str, long n);
 unsigned long __must_check clear_user(void __user *mem, unsigned long len);
 unsigned long __must_check __clear_user(void __user *mem, unsigned long len);
 
-#endif /* __i386_UACCESS_H */
+#endif /* ASM_X86__UACCESS_32_H */
diff --git a/include/asm-x86/uaccess_64.h b/include/asm-x86/uaccess_64.h
index 515d4dce96b5..c96c1f5d07a2 100644
--- a/include/asm-x86/uaccess_64.h
+++ b/include/asm-x86/uaccess_64.h
@@ -1,5 +1,5 @@
-#ifndef __X86_64_UACCESS_H
-#define __X86_64_UACCESS_H
+#ifndef ASM_X86__UACCESS_64_H
+#define ASM_X86__UACCESS_64_H
 
 /*
  * User space memory access functions
@@ -7,6 +7,7 @@
 #include <linux/compiler.h>
 #include <linux/errno.h>
 #include <linux/prefetch.h>
+#include <linux/lockdep.h>
 #include <asm/page.h>
 
 /*
@@ -198,4 +199,4 @@ static inline int __copy_from_user_inatomic_nocache(void *dst,
 unsigned long
 copy_user_handle_tail(char *to, char *from, unsigned len, unsigned zerorest);
 
-#endif /* __X86_64_UACCESS_H */
+#endif /* ASM_X86__UACCESS_64_H */
diff --git a/include/asm-x86/ucontext.h b/include/asm-x86/ucontext.h
index 50a79f7fcde9..89eaa5456a7e 100644
--- a/include/asm-x86/ucontext.h
+++ b/include/asm-x86/ucontext.h
@@ -1,5 +1,11 @@
-#ifndef _ASM_X86_UCONTEXT_H
-#define _ASM_X86_UCONTEXT_H
+#ifndef ASM_X86__UCONTEXT_H
+#define ASM_X86__UCONTEXT_H
+
+#define UC_FP_XSTATE    0x1     /* indicates the presence of extended state
+                                 * information in the memory layout pointed
+                                 * by the fpstate pointer in the ucontext's
+                                 * sigcontext struct (uc_mcontext).
+                                 */
 
 struct ucontext {
         unsigned long     uc_flags;
@@ -9,4 +15,4 @@ struct ucontext {
         sigset_t          uc_sigmask;   /* mask last for extensibility */
 };
 
-#endif /* _ASM_X86_UCONTEXT_H */
+#endif /* ASM_X86__UCONTEXT_H */
diff --git a/include/asm-x86/unaligned.h b/include/asm-x86/unaligned.h
index a7bd416b4763..59dcdec37160 100644
--- a/include/asm-x86/unaligned.h
+++ b/include/asm-x86/unaligned.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_UNALIGNED_H
-#define _ASM_X86_UNALIGNED_H
+#ifndef ASM_X86__UNALIGNED_H
+#define ASM_X86__UNALIGNED_H
 
 /*
  * The x86 can do unaligned accesses itself.
@@ -11,4 +11,4 @@
 #define get_unaligned __get_unaligned_le
 #define put_unaligned __put_unaligned_le
 
-#endif /* _ASM_X86_UNALIGNED_H */
+#endif /* ASM_X86__UNALIGNED_H */
diff --git a/include/asm-x86/unistd_32.h b/include/asm-x86/unistd_32.h
index d7394673b772..017f4a87c913 100644
--- a/include/asm-x86/unistd_32.h
+++ b/include/asm-x86/unistd_32.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_I386_UNISTD_H_
-#define _ASM_I386_UNISTD_H_
+#ifndef ASM_X86__UNISTD_32_H
+#define ASM_X86__UNISTD_32_H
 
 /*
  * This file contains the system call numbers.
@@ -376,4 +376,4 @@
 #endif
 
 #endif /* __KERNEL__ */
-#endif /* _ASM_I386_UNISTD_H_ */
+#endif /* ASM_X86__UNISTD_32_H */
diff --git a/include/asm-x86/unistd_64.h b/include/asm-x86/unistd_64.h
index 3a341d791792..ace83f1f6787 100644
--- a/include/asm-x86/unistd_64.h
+++ b/include/asm-x86/unistd_64.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_UNISTD_H_
-#define _ASM_X86_64_UNISTD_H_
+#ifndef ASM_X86__UNISTD_64_H
+#define ASM_X86__UNISTD_64_H
 
 #ifndef __SYSCALL
 #define __SYSCALL(a, b)
@@ -690,4 +690,4 @@ __SYSCALL(__NR_inotify_init1, sys_inotify_init1)
 #define cond_syscall(x) asm(".weak\t" #x "\n\t.set\t" #x ",sys_ni_syscall")
 #endif  /* __KERNEL__ */
 
-#endif /* _ASM_X86_64_UNISTD_H_ */
+#endif /* ASM_X86__UNISTD_64_H */
diff --git a/include/asm-x86/unwind.h b/include/asm-x86/unwind.h
index 8b064bd9c553..a2151567db44 100644
--- a/include/asm-x86/unwind.h
+++ b/include/asm-x86/unwind.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_UNWIND_H
-#define _ASM_X86_UNWIND_H
+#ifndef ASM_X86__UNWIND_H
+#define ASM_X86__UNWIND_H
 
 #define UNW_PC(frame) ((void)(frame), 0UL)
 #define UNW_SP(frame) ((void)(frame), 0UL)
@@ -10,4 +10,4 @@ static inline int arch_unw_user_mode(const void *info)
         return 0;
 }
 
-#endif /* _ASM_X86_UNWIND_H */
+#endif /* ASM_X86__UNWIND_H */
diff --git a/include/asm-x86/user32.h b/include/asm-x86/user32.h
index a3d910047879..aa66c1857f06 100644
--- a/include/asm-x86/user32.h
+++ b/include/asm-x86/user32.h
@@ -1,5 +1,5 @@
-#ifndef USER32_H
-#define USER32_H 1
+#ifndef ASM_X86__USER32_H
+#define ASM_X86__USER32_H
 
 /* IA32 compatible user structures for ptrace.
  * These should be used for 32bit coredumps too. */
@@ -67,4 +67,4 @@ struct user32 {
 };
 
 
-#endif
+#endif /* ASM_X86__USER32_H */
diff --git a/include/asm-x86/user_32.h b/include/asm-x86/user_32.h
index d6e51edc259d..e0fe2f55f1a6 100644
--- a/include/asm-x86/user_32.h
+++ b/include/asm-x86/user_32.h
@@ -1,5 +1,5 @@
-#ifndef _I386_USER_H
-#define _I386_USER_H
+#ifndef ASM_X86__USER_32_H
+#define ASM_X86__USER_32_H
 
 #include <asm/page.h>
 /* Core file format: The core file is written in such a way that gdb
@@ -128,4 +128,4 @@ struct user{
 #define HOST_TEXT_START_ADDR (u.start_code)
 #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
 
-#endif /* _I386_USER_H */
+#endif /* ASM_X86__USER_32_H */
diff --git a/include/asm-x86/user_64.h b/include/asm-x86/user_64.h
index 6037b634c77f..38b5799863b4 100644
--- a/include/asm-x86/user_64.h
+++ b/include/asm-x86/user_64.h
@@ -1,5 +1,5 @@
-#ifndef _X86_64_USER_H
-#define _X86_64_USER_H
+#ifndef ASM_X86__USER_64_H
+#define ASM_X86__USER_64_H
 
 #include <asm/types.h>
 #include <asm/page.h>
@@ -134,4 +134,4 @@ struct user {
 #define HOST_TEXT_START_ADDR (u.start_code)
 #define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
 
-#endif /* _X86_64_USER_H */
+#endif /* ASM_X86__USER_64_H */
diff --git a/include/asm-x86/uv/bios.h b/include/asm-x86/uv/bios.h
index aa73362ff5df..7cd6d7ec1308 100644
--- a/include/asm-x86/uv/bios.h
+++ b/include/asm-x86/uv/bios.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_BIOS_H
-#define _ASM_X86_BIOS_H
+#ifndef ASM_X86__UV__BIOS_H
+#define ASM_X86__UV__BIOS_H
 
 /*
  * BIOS layer definitions.
@@ -65,4 +65,4 @@ x86_bios_freq_base(unsigned long which, unsigned long *ticks_per_second,
                    unsigned long *drift_info);
 extern const char *x86_bios_strerror(long status);
 
-#endif /* _ASM_X86_BIOS_H */
+#endif /* ASM_X86__UV__BIOS_H */
diff --git a/include/asm-x86/uv/uv_bau.h b/include/asm-x86/uv/uv_bau.h
index 91ac0dfb7588..77153fb18f5e 100644
--- a/include/asm-x86/uv/uv_bau.h
+++ b/include/asm-x86/uv/uv_bau.h
@@ -8,8 +8,8 @@
  * Copyright (C) 2008 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef __ASM_X86_UV_BAU__
-#define __ASM_X86_UV_BAU__
+#ifndef ASM_X86__UV__UV_BAU_H
+#define ASM_X86__UV__UV_BAU_H
 
 #include <linux/bitmap.h>
 #define BITSPERBYTE 8
@@ -40,11 +40,6 @@
 #define UV_ACTIVATION_DESCRIPTOR_SIZE   32
 #define UV_DISTRIBUTION_SIZE            256
 #define UV_SW_ACK_NPENDING              8
-#define UV_BAU_MESSAGE                  200
-/*
- * Messaging irq; see irq_64.h and include/asm-x86/hw_irq_64.h
- * To be dynamically allocated in the future
- */
 #define UV_NET_ENDPOINT_INTD            0x38
 #define UV_DESC_BASE_PNODE_SHIFT        49
 #define UV_PAYLOADQ_PNODE_SHIFT         49
@@ -334,4 +329,4 @@ extern int uv_flush_tlb_others(cpumask_t *, struct mm_struct *, unsigned long);
 extern void uv_bau_message_intr1(void);
 extern void uv_bau_timeout_intr1(void);
 
-#endif /* __ASM_X86_UV_BAU__ */
+#endif /* ASM_X86__UV__UV_BAU_H */
diff --git a/include/asm-x86/uv/uv_hub.h b/include/asm-x86/uv/uv_hub.h
index a4ef26e5850b..bdb5b01afbf5 100644
--- a/include/asm-x86/uv/uv_hub.h
+++ b/include/asm-x86/uv/uv_hub.h
@@ -8,8 +8,8 @@
  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef __ASM_X86_UV_HUB_H__
-#define __ASM_X86_UV_HUB_H__
+#ifndef ASM_X86__UV__UV_HUB_H
+#define ASM_X86__UV__UV_HUB_H
 
 #include <linux/numa.h>
 #include <linux/percpu.h>
@@ -350,5 +350,5 @@ static inline int uv_num_possible_blades(void)
         return uv_possible_blades;
 }
 
-#endif /* __ASM_X86_UV_HUB__ */
+#endif /* ASM_X86__UV__UV_HUB_H */
 
diff --git a/include/asm-x86/uv/uv_mmrs.h b/include/asm-x86/uv/uv_mmrs.h
index 151fd7fcb809..8b03d89d2459 100644
--- a/include/asm-x86/uv/uv_mmrs.h
+++ b/include/asm-x86/uv/uv_mmrs.h
@@ -8,8 +8,8 @@
  * Copyright (C) 2007-2008 Silicon Graphics, Inc. All rights reserved.
  */
 
-#ifndef __ASM_X86_UV_MMRS__
-#define __ASM_X86_UV_MMRS__
+#ifndef ASM_X86__UV__UV_MMRS_H
+#define ASM_X86__UV__UV_MMRS_H
 
 #define UV_MMR_ENABLE           (1UL << 63)
 
@@ -1292,4 +1292,4 @@ union uvh_si_alias2_overlay_config_u {
 };
 
 
-#endif /* __ASM_X86_UV_MMRS__ */
+#endif /* ASM_X86__UV__UV_MMRS_H */
diff --git a/include/asm-x86/vdso.h b/include/asm-x86/vdso.h
index 8e18fb80f5e6..4ab320913ea3 100644
--- a/include/asm-x86/vdso.h
+++ b/include/asm-x86/vdso.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_VDSO_H
-#define _ASM_X86_VDSO_H 1
+#ifndef ASM_X86__VDSO_H
+#define ASM_X86__VDSO_H
 
 #ifdef CONFIG_X86_64
 extern const char VDSO64_PRELINK[];
@@ -44,4 +44,4 @@ extern const char vdso32_int80_start, vdso32_int80_end;
 extern const char vdso32_syscall_start, vdso32_syscall_end;
 extern const char vdso32_sysenter_start, vdso32_sysenter_end;
 
-#endif  /* asm-x86/vdso.h */
+#endif /* ASM_X86__VDSO_H */
diff --git a/include/asm-x86/vga.h b/include/asm-x86/vga.h
index 0ccf804377e6..b9e493d07d07 100644
--- a/include/asm-x86/vga.h
+++ b/include/asm-x86/vga.h
@@ -4,8 +4,8 @@
  *      (c) 1998 Martin Mares <mj@ucw.cz>
  */
 
-#ifndef _LINUX_ASM_VGA_H_
-#define _LINUX_ASM_VGA_H_
+#ifndef ASM_X86__VGA_H
+#define ASM_X86__VGA_H
 
 /*
  *      On the PC, we can just recalculate addresses and then
@@ -17,4 +17,4 @@
 #define vga_readb(x) (*(x))
 #define vga_writeb(x, y) (*(y) = (x))
 
-#endif
+#endif /* ASM_X86__VGA_H */
diff --git a/include/asm-x86/vgtod.h b/include/asm-x86/vgtod.h
index 3301f0929342..38fd13364021 100644
--- a/include/asm-x86/vgtod.h
+++ b/include/asm-x86/vgtod.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_VGTOD_H
-#define _ASM_VGTOD_H 1
+#ifndef ASM_X86__VGTOD_H
+#define ASM_X86__VGTOD_H
 
 #include <asm/vsyscall.h>
 #include <linux/clocksource.h>
@@ -26,4 +26,4 @@ extern struct vsyscall_gtod_data __vsyscall_gtod_data
 __section_vsyscall_gtod_data;
 extern struct vsyscall_gtod_data vsyscall_gtod_data;
 
-#endif
+#endif /* ASM_X86__VGTOD_H */
diff --git a/include/asm-x86/visws/cobalt.h b/include/asm-x86/visws/cobalt.h
index 995258831b7f..9627a8fe84e9 100644
--- a/include/asm-x86/visws/cobalt.h
+++ b/include/asm-x86/visws/cobalt.h
@@ -1,5 +1,5 @@
-#ifndef __I386_SGI_COBALT_H
-#define __I386_SGI_COBALT_H
+#ifndef ASM_X86__VISWS__COBALT_H
+#define ASM_X86__VISWS__COBALT_H
 
 #include <asm/fixmap.h>
 
@@ -122,4 +122,4 @@ extern char visws_board_type;
 
 extern char visws_board_rev;
 
-#endif /* __I386_SGI_COBALT_H */
+#endif /* ASM_X86__VISWS__COBALT_H */
diff --git a/include/asm-x86/visws/lithium.h b/include/asm-x86/visws/lithium.h
index dfcd4f07ab85..b36d3b378c63 100644
--- a/include/asm-x86/visws/lithium.h
+++ b/include/asm-x86/visws/lithium.h
@@ -1,5 +1,5 @@
-#ifndef __I386_SGI_LITHIUM_H
-#define __I386_SGI_LITHIUM_H
+#ifndef ASM_X86__VISWS__LITHIUM_H
+#define ASM_X86__VISWS__LITHIUM_H
 
 #include <asm/fixmap.h>
 
@@ -49,5 +49,5 @@ static inline unsigned short li_pcib_read16(unsigned long reg)
         return *((volatile unsigned short *)(LI_PCIB_VADDR+reg));
 }
 
-#endif
+#endif /* ASM_X86__VISWS__LITHIUM_H */
 
diff --git a/include/asm-x86/visws/piix4.h b/include/asm-x86/visws/piix4.h
index 83ea4f46e419..61c938045ec9 100644
--- a/include/asm-x86/visws/piix4.h
+++ b/include/asm-x86/visws/piix4.h
@@ -1,5 +1,5 @@
-#ifndef __I386_SGI_PIIX_H
-#define __I386_SGI_PIIX_H
+#ifndef ASM_X86__VISWS__PIIX4_H
+#define ASM_X86__VISWS__PIIX4_H
 
 /*
  * PIIX4 as used on SGI Visual Workstations
@@ -104,4 +104,4 @@
  */
 #define PIIX_GPI_STPCLK         0x4     // STPCLK signal routed back in
 
-#endif
+#endif /* ASM_X86__VISWS__PIIX4_H */
diff --git a/include/asm-x86/vm86.h b/include/asm-x86/vm86.h
index 5ce351325e01..998bd18eb737 100644
--- a/include/asm-x86/vm86.h
+++ b/include/asm-x86/vm86.h
@@ -1,5 +1,5 @@
-#ifndef _LINUX_VM86_H
-#define _LINUX_VM86_H
+#ifndef ASM_X86__VM86_H
+#define ASM_X86__VM86_H
 
 /*
  * I'm guessing at the VIF/VIP flag usage, but hope that this is how
@@ -205,4 +205,4 @@ static inline int handle_vm86_trap(struct kernel_vm86_regs *a, long b, int c)
 
 #endif /* __KERNEL__ */
 
-#endif
+#endif /* ASM_X86__VM86_H */
diff --git a/include/asm-x86/vmi_time.h b/include/asm-x86/vmi_time.h
index c3118c385156..b2d39e6a08b7 100644
--- a/include/asm-x86/vmi_time.h
+++ b/include/asm-x86/vmi_time.h
@@ -22,8 +22,8 @@
  *
  */
 
-#ifndef __VMI_TIME_H
-#define __VMI_TIME_H
+#ifndef ASM_X86__VMI_TIME_H
+#define ASM_X86__VMI_TIME_H
 
 /*
  * Raw VMI call indices for timer functions
@@ -95,4 +95,4 @@ extern void __devinit vmi_time_ap_init(void);
 
 #define CONFIG_VMI_ALARM_HZ     100
 
-#endif
+#endif /* ASM_X86__VMI_TIME_H */
diff --git a/include/asm-x86/vsyscall.h b/include/asm-x86/vsyscall.h
index 6b66ff905af0..dcd4682413de 100644
--- a/include/asm-x86/vsyscall.h
+++ b/include/asm-x86/vsyscall.h
@@ -1,5 +1,5 @@
-#ifndef _ASM_X86_64_VSYSCALL_H_
-#define _ASM_X86_64_VSYSCALL_H_
+#ifndef ASM_X86__VSYSCALL_H
+#define ASM_X86__VSYSCALL_H
 
 enum vsyscall_num {
         __NR_vgettimeofday,
@@ -41,4 +41,4 @@ extern void map_vsyscall(void);
 
 #endif /* __KERNEL__ */
 
-#endif /* _ASM_X86_64_VSYSCALL_H_ */
+#endif /* ASM_X86__VSYSCALL_H */
diff --git a/include/asm-x86/xcr.h b/include/asm-x86/xcr.h
new file mode 100644
index 000000000000..f2cba4e79a23
--- /dev/null
+++ b/include/asm-x86/xcr.h
@@ -0,0 +1,49 @@
+/* -*- linux-c -*- ------------------------------------------------------- *
+ *
+ *   Copyright 2008 rPath, Inc. - All Rights Reserved
+ *
+ *   This file is part of the Linux kernel, and is made available under
+ *   the terms of the GNU General Public License version 2 or (at your
+ *   option) any later version; incorporated herein by reference.
+ *
+ * ----------------------------------------------------------------------- */
+
+/*
+ * asm-x86/xcr.h
+ *
+ * Definitions for the eXtended Control Register instructions
+ */
+
+#ifndef _ASM_X86_XCR_H
+#define _ASM_X86_XCR_H
+
+#define XCR_XFEATURE_ENABLED_MASK       0x00000000
+
+#ifdef __KERNEL__
+# ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+static inline u64 xgetbv(u32 index)
+{
+        u32 eax, edx;
+
+        asm volatile(".byte 0x0f,0x01,0xd0" /* xgetbv */
+                     : "=a" (eax), "=d" (edx)
+                     : "c" (index));
+        return eax + ((u64)edx << 32);
+}
+
+static inline void xsetbv(u32 index, u64 value)
+{
+        u32 eax = value;
+        u32 edx = value >> 32;
+
+        asm volatile(".byte 0x0f,0x01,0xd1" /* xsetbv */
+                     : : "a" (eax), "d" (edx), "c" (index));
+}
+
+# endif /* __ASSEMBLY__ */
+#endif /* __KERNEL__ */
+
+#endif /* _ASM_X86_XCR_H */
diff --git a/include/asm-x86/xen/events.h b/include/asm-x86/xen/events.h
index 8ded74720024..8151f5b8b6cb 100644
--- a/include/asm-x86/xen/events.h
+++ b/include/asm-x86/xen/events.h
@@ -1,5 +1,5 @@
-#ifndef __XEN_EVENTS_H
-#define __XEN_EVENTS_H
+#ifndef ASM_X86__XEN__EVENTS_H
+#define ASM_X86__XEN__EVENTS_H
 
 enum ipi_vector {
         XEN_RESCHEDULE_VECTOR,
@@ -21,4 +21,4 @@ static inline void xen_do_IRQ(int irq, struct pt_regs *regs)
         do_IRQ(regs);
 }
 
-#endif /* __XEN_EVENTS_H */
+#endif /* ASM_X86__XEN__EVENTS_H */
diff --git a/include/asm-x86/xen/grant_table.h b/include/asm-x86/xen/grant_table.h
index 2444d4593a3b..c4baab4d2b68 100644
--- a/include/asm-x86/xen/grant_table.h
+++ b/include/asm-x86/xen/grant_table.h
@@ -1,7 +1,7 @@
-#ifndef __XEN_GRANT_TABLE_H
-#define __XEN_GRANT_TABLE_H
+#ifndef ASM_X86__XEN__GRANT_TABLE_H
+#define ASM_X86__XEN__GRANT_TABLE_H
 
 #define xen_alloc_vm_area(size) alloc_vm_area(size)
 #define xen_free_vm_area(area)  free_vm_area(area)
 
-#endif /* __XEN_GRANT_TABLE_H */
+#endif /* ASM_X86__XEN__GRANT_TABLE_H */
diff --git a/include/asm-x86/xen/hypercall.h b/include/asm-x86/xen/hypercall.h
index 91cb7fd5c123..44f4259bee3f 100644
--- a/include/asm-x86/xen/hypercall.h
+++ b/include/asm-x86/xen/hypercall.h
@@ -30,8 +30,8 @@
  * IN THE SOFTWARE.
  */
 
-#ifndef __HYPERCALL_H__
-#define __HYPERCALL_H__
+#ifndef ASM_X86__XEN__HYPERCALL_H
+#define ASM_X86__XEN__HYPERCALL_H
 
 #include <linux/errno.h>
 #include <linux/string.h>
@@ -524,4 +524,4 @@ MULTI_stack_switch(struct multicall_entry *mcl,
         mcl->args[1] = esp;
 }
 
-#endif /* __HYPERCALL_H__ */
+#endif /* ASM_X86__XEN__HYPERCALL_H */
diff --git a/include/asm-x86/xen/hypervisor.h b/include/asm-x86/xen/hypervisor.h
index 8e15dd28c91f..445a24759560 100644
--- a/include/asm-x86/xen/hypervisor.h
+++ b/include/asm-x86/xen/hypervisor.h
@@ -30,12 +30,11 @@
  * IN THE SOFTWARE.
  */
 
-#ifndef __HYPERVISOR_H__
-#define __HYPERVISOR_H__
+#ifndef ASM_X86__XEN__HYPERVISOR_H
+#define ASM_X86__XEN__HYPERVISOR_H
 
 #include <linux/types.h>
 #include <linux/kernel.h>
-#include <linux/version.h>
 
 #include <xen/interface/xen.h>
 #include <xen/interface/version.h>
@@ -55,7 +54,6 @@
 /* arch/i386/kernel/setup.c */
 extern struct shared_info *HYPERVISOR_shared_info;
 extern struct start_info *xen_start_info;
-#define is_initial_xendomain() (xen_start_info->flags & SIF_INITDOMAIN)
 
 /* arch/i386/mach-xen/evtchn.c */
 /* Force a proper event-channel callback from Xen. */
@@ -68,6 +66,17 @@ u64 jiffies_to_st(unsigned long jiffies);
 #define MULTI_UVMFLAGS_INDEX 3
 #define MULTI_UVMDOMID_INDEX 4
 
-#define is_running_on_xen()     (xen_start_info ? 1 : 0)
+enum xen_domain_type {
+        XEN_NATIVE,
+        XEN_PV_DOMAIN,
+        XEN_HVM_DOMAIN,
+};
 
-#endif /* __HYPERVISOR_H__ */
+extern enum xen_domain_type xen_domain_type;
+
+#define xen_domain()            (xen_domain_type != XEN_NATIVE)
+#define xen_pv_domain()         (xen_domain_type == XEN_PV_DOMAIN)
+#define xen_initial_domain()    (xen_pv_domain() && xen_start_info->flags & SIF_INITDOMAIN)
+#define xen_hvm_domain()        (xen_domain_type == XEN_HVM_DOMAIN)
+
+#endif /* ASM_X86__XEN__HYPERVISOR_H */
diff --git a/include/asm-x86/xen/interface.h b/include/asm-x86/xen/interface.h
index 9d810f2538a2..d077bba96da9 100644
--- a/include/asm-x86/xen/interface.h
+++ b/include/asm-x86/xen/interface.h
@@ -6,8 +6,8 @@
  * Copyright (c) 2004, K A Fraser
  */
 
-#ifndef __ASM_X86_XEN_INTERFACE_H
-#define __ASM_X86_XEN_INTERFACE_H
+#ifndef ASM_X86__XEN__INTERFACE_H
+#define ASM_X86__XEN__INTERFACE_H
 
 #ifdef __XEN__
 #define __DEFINE_GUEST_HANDLE(name, type) \
@@ -172,4 +172,4 @@ DEFINE_GUEST_HANDLE_STRUCT(vcpu_guest_context);
 #define XEN_CPUID          XEN_EMULATE_PREFIX "cpuid"
 #endif
 
-#endif  /* __ASM_X86_XEN_INTERFACE_H */
+#endif /* ASM_X86__XEN__INTERFACE_H */
diff --git a/include/asm-x86/xen/interface_32.h b/include/asm-x86/xen/interface_32.h
index d8ac41d5db86..08167e19fc66 100644
--- a/include/asm-x86/xen/interface_32.h
+++ b/include/asm-x86/xen/interface_32.h
@@ -6,8 +6,8 @@
  * Copyright (c) 2004, K A Fraser
  */
 
-#ifndef __ASM_X86_XEN_INTERFACE_32_H
-#define __ASM_X86_XEN_INTERFACE_32_H
+#ifndef ASM_X86__XEN__INTERFACE_32_H
+#define ASM_X86__XEN__INTERFACE_32_H
 
 
 /*
@@ -94,4 +94,4 @@ typedef struct xen_callback xen_callback_t;
 #define xen_pfn_to_cr3(pfn) (((unsigned)(pfn) << 12) | ((unsigned)(pfn) >> 20))
 #define xen_cr3_to_pfn(cr3) (((unsigned)(cr3) >> 12) | ((unsigned)(cr3) << 20))
 
-#endif  /* __ASM_X86_XEN_INTERFACE_32_H */
+#endif /* ASM_X86__XEN__INTERFACE_32_H */
diff --git a/include/asm-x86/xen/interface_64.h b/include/asm-x86/xen/interface_64.h
index 842266ce96e6..046c0f1e01d4 100644
--- a/include/asm-x86/xen/interface_64.h
+++ b/include/asm-x86/xen/interface_64.h
@@ -1,5 +1,5 @@
-#ifndef __ASM_X86_XEN_INTERFACE_64_H
-#define __ASM_X86_XEN_INTERFACE_64_H
+#ifndef ASM_X86__XEN__INTERFACE_64_H
+#define ASM_X86__XEN__INTERFACE_64_H
 
 /*
  * 64-bit segment selectors
@@ -156,4 +156,4 @@ typedef unsigned long xen_callback_t;
 #endif /* !__ASSEMBLY__ */
 
 
-#endif  /* __ASM_X86_XEN_INTERFACE_64_H */
+#endif /* ASM_X86__XEN__INTERFACE_64_H */
diff --git a/include/asm-x86/xen/page.h b/include/asm-x86/xen/page.h
index 7b3835d3b77d..d5eada0a48d9 100644
--- a/include/asm-x86/xen/page.h
+++ b/include/asm-x86/xen/page.h
@@ -1,5 +1,5 @@
-#ifndef __XEN_PAGE_H
-#define __XEN_PAGE_H
+#ifndef ASM_X86__XEN__PAGE_H
+#define ASM_X86__XEN__PAGE_H
 
 #include <linux/pfn.h>
 
@@ -76,13 +76,13 @@ static inline unsigned long mfn_to_pfn(unsigned long mfn)
 static inline xmaddr_t phys_to_machine(xpaddr_t phys)
 {
         unsigned offset = phys.paddr & ~PAGE_MASK;
-        return XMADDR(PFN_PHYS((u64)pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
+        return XMADDR(PFN_PHYS(pfn_to_mfn(PFN_DOWN(phys.paddr))) | offset);
 }
 
 static inline xpaddr_t machine_to_phys(xmaddr_t machine)
 {
         unsigned offset = machine.maddr & ~PAGE_MASK;
-        return XPADDR(PFN_PHYS((u64)mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
+        return XPADDR(PFN_PHYS(mfn_to_pfn(PFN_DOWN(machine.maddr))) | offset);
 }
 
 /*
@@ -162,4 +162,4 @@ xmaddr_t arbitrary_virt_to_machine(void *address);
 void make_lowmem_page_readonly(void *vaddr);
 void make_lowmem_page_readwrite(void *vaddr);
 
-#endif /* __XEN_PAGE_H */
+#endif /* ASM_X86__XEN__PAGE_H */
diff --git a/include/asm-x86/xsave.h b/include/asm-x86/xsave.h
new file mode 100644
index 000000000000..08e9a1ac07a9
--- /dev/null
+++ b/include/asm-x86/xsave.h
@@ -0,0 +1,118 @@
+#ifndef __ASM_X86_XSAVE_H
+#define __ASM_X86_XSAVE_H
+
+#include <linux/types.h>
+#include <asm/processor.h>
+#include <asm/i387.h>
+
+#define XSTATE_FP       0x1
+#define XSTATE_SSE      0x2
+
+#define XSTATE_FPSSE    (XSTATE_FP | XSTATE_SSE)
+
+#define FXSAVE_SIZE     512
+
+/*
+ * These are the features that the OS can handle currently.
+ */
+#define XCNTXT_MASK     (XSTATE_FP | XSTATE_SSE)
+
+#ifdef CONFIG_X86_64
+#define REX_PREFIX      "0x48, "
+#else
+#define REX_PREFIX
+#endif
+
+extern unsigned int xstate_size;
+extern u64 pcntxt_mask;
+extern struct xsave_struct *init_xstate_buf;
+
+extern void xsave_cntxt_init(void);
+extern void xsave_init(void);
+extern int init_fpu(struct task_struct *child);
+extern int check_for_xstate(struct i387_fxsave_struct __user *buf,
+                            void __user *fpstate,
+                            struct _fpx_sw_bytes *sw);
+
+static inline int xrstor_checking(struct xsave_struct *fx)
+{
+        int err;
+
+        asm volatile("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
+                     "2:\n"
+                     ".section .fixup,\"ax\"\n"
+                     "3:  movl $-1,%[err]\n"
+                     "    jmp  2b\n"
+                     ".previous\n"
+                     _ASM_EXTABLE(1b, 3b)
+                     : [err] "=r" (err)
+                     : "D" (fx), "m" (*fx), "a" (-1), "d" (-1), "0" (0)
+                     : "memory");
+
+        return err;
+}
+
+static inline int xsave_user(struct xsave_struct __user *buf)
+{
+        int err;
+        __asm__ __volatile__("1: .byte " REX_PREFIX "0x0f,0xae,0x27\n"
+                             "2:\n"
+                             ".section .fixup,\"ax\"\n"
+                             "3:  movl $-1,%[err]\n"
+                             "    jmp  2b\n"
+                             ".previous\n"
+                             ".section __ex_table,\"a\"\n"
+                             _ASM_ALIGN "\n"
+                             _ASM_PTR "1b,3b\n"
+                             ".previous"
+                             : [err] "=r" (err)
+                             : "D" (buf), "a" (-1), "d" (-1), "0" (0)
+                             : "memory");
+        if (unlikely(err) && __clear_user(buf, xstate_size))
+                err = -EFAULT;
+        /* No need to clear here because the caller clears USED_MATH */
+        return err;
+}
+
+static inline int xrestore_user(struct xsave_struct __user *buf, u64 mask)
+{
+        int err;
+        struct xsave_struct *xstate = ((__force struct xsave_struct *)buf);
+        u32 lmask = mask;
+        u32 hmask = mask >> 32;
+
+        __asm__ __volatile__("1: .byte " REX_PREFIX "0x0f,0xae,0x2f\n"
+                             "2:\n"
+                             ".section .fixup,\"ax\"\n"
+                             "3:  movl $-1,%[err]\n"
+                             "    jmp  2b\n"
+                             ".previous\n"
+                             ".section __ex_table,\"a\"\n"
+                             _ASM_ALIGN "\n"
+                             _ASM_PTR "1b,3b\n"
+                             ".previous"
+                             : [err] "=r" (err)
+                             : "D" (xstate), "a" (lmask), "d" (hmask), "0" (0)
+                             : "memory");       /* memory required? */
+        return err;
+}
+
+static inline void xrstor_state(struct xsave_struct *fx, u64 mask)
+{
+        u32 lmask = mask;
+        u32 hmask = mask >> 32;
+
+        asm volatile(".byte " REX_PREFIX "0x0f,0xae,0x2f\n\t"
+                     : : "D" (fx), "m" (*fx), "a" (lmask), "d" (hmask)
+                     :   "memory");
+}
+
+static inline void xsave(struct task_struct *tsk)
+{
+        /* This, however, we can work around by forcing the compiler to select
+           an addressing mode that doesn't require extended registers. */
+        __asm__ __volatile__(".byte " REX_PREFIX "0x0f,0xae,0x27"
+                             : : "D" (&(tsk->thread.xstate->xsave)),
+                                 "a" (-1), "d"(-1) : "memory");
+}
+#endif
diff --git a/include/asm-xtensa/a.out.h b/include/asm-xtensa/a.out.h
deleted file mode 100644
index fdf13702924a..000000000000
--- a/include/asm-xtensa/a.out.h
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * include/asm-xtensa/a.out.h
- *
- * Dummy a.out file. Xtensa does not support the a.out format, but the kernel
- * seems to depend on it.
- *
- * This file is subject to the terms and conditions of the GNU General Public
- * License.  See the file "COPYING" in the main directory of this archive
- * for more details.
- *
- * Copyright (C) 2001 - 2005 Tensilica Inc.
- */
-
-#ifndef _XTENSA_A_OUT_H
-#define _XTENSA_A_OUT_H
-
-struct exec
-{
-  unsigned long a_info;
-  unsigned a_text;
-  unsigned a_data;
-  unsigned a_bss;
-  unsigned a_syms;
-  unsigned a_entry;
-  unsigned a_trsize;
-  unsigned a_drsize;
-};
-
-#endif /* _XTENSA_A_OUT_H */
diff --git a/include/asm-xtensa/elf.h b/include/asm-xtensa/elf.h
index ca6e5101a2cb..c3f53e755ca5 100644
--- a/include/asm-xtensa/elf.h
+++ b/include/asm-xtensa/elf.h
@@ -189,7 +189,7 @@ typedef struct {
 #endif
 } elf_xtregs_t;
 
-#define SET_PERSONALITY(ex, ibcs2) set_personality(PER_LINUX_32BIT)
+#define SET_PERSONALITY(ex) set_personality(PER_LINUX_32BIT)
 
 struct task_struct;
 
diff --git a/include/crypto/internal/rng.h b/include/crypto/internal/rng.h
new file mode 100644
index 000000000000..896973369573
--- /dev/null
+++ b/include/crypto/internal/rng.h
@@ -0,0 +1,26 @@
+/*
+ * RNG: Random Number Generator  algorithms under the crypto API
+ *
+ * Copyright (c) 2008 Neil Horman <nhorman@tuxdriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+
+#ifndef _CRYPTO_INTERNAL_RNG_H
+#define _CRYPTO_INTERNAL_RNG_H
+
+#include <crypto/algapi.h>
+#include <crypto/rng.h>
+
+extern const struct crypto_type crypto_rng_type;
+
+static inline void *crypto_rng_ctx(struct crypto_rng *tfm)
+{
+        return crypto_tfm_ctx(&tfm->base);
+}
+
+#endif
diff --git a/include/crypto/internal/skcipher.h b/include/crypto/internal/skcipher.h
index ccc32bad9a89..2ba42cd7d6aa 100644
--- a/include/crypto/internal/skcipher.h
+++ b/include/crypto/internal/skcipher.h
@@ -15,7 +15,6 @@
 
 #include <crypto/algapi.h>
 #include <crypto/skcipher.h>
-#include <linux/init.h>
 #include <linux/types.h>
 
 struct rtattr;
@@ -65,11 +64,6 @@ void skcipher_geniv_free(struct crypto_instance *inst);
 int skcipher_geniv_init(struct crypto_tfm *tfm);
 void skcipher_geniv_exit(struct crypto_tfm *tfm);
 
-int __init eseqiv_module_init(void);
-void __exit eseqiv_module_exit(void);
-int __init chainiv_module_init(void);
-void chainiv_module_exit(void);
-
 static inline struct crypto_ablkcipher *skcipher_geniv_cipher(
         struct crypto_ablkcipher *geniv)
 {
diff --git a/include/crypto/rng.h b/include/crypto/rng.h
new file mode 100644
index 000000000000..c93f9b917925
--- /dev/null
+++ b/include/crypto/rng.h
@@ -0,0 +1,75 @@
+/*
+ * RNG: Random Number Generator  algorithms under the crypto API
+ *
+ * Copyright (c) 2008 Neil Horman <nhorman@tuxdriver.com>
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the Free
+ * Software Foundation; either version 2 of the License, or (at your option)
+ * any later version.
+ *
+ */
+
+#ifndef _CRYPTO_RNG_H
+#define _CRYPTO_RNG_H
+
+#include <linux/crypto.h>
+
+extern struct crypto_rng *crypto_default_rng;
+
+int crypto_get_default_rng(void);
+void crypto_put_default_rng(void);
+
+static inline struct crypto_rng *__crypto_rng_cast(struct crypto_tfm *tfm)
+{
+        return (struct crypto_rng *)tfm;
+}
+
+static inline struct crypto_rng *crypto_alloc_rng(const char *alg_name,
+                                                  u32 type, u32 mask)
+{
+        type &= ~CRYPTO_ALG_TYPE_MASK;
+        type |= CRYPTO_ALG_TYPE_RNG;
+        mask |= CRYPTO_ALG_TYPE_MASK;
+
+        return __crypto_rng_cast(crypto_alloc_base(alg_name, type, mask));
+}
+
+static inline struct crypto_tfm *crypto_rng_tfm(struct crypto_rng *tfm)
+{
+        return &tfm->base;
+}
+
+static inline struct rng_alg *crypto_rng_alg(struct crypto_rng *tfm)
+{
+        return &crypto_rng_tfm(tfm)->__crt_alg->cra_rng;
+}
+
+static inline struct rng_tfm *crypto_rng_crt(struct crypto_rng *tfm)
+{
+        return &crypto_rng_tfm(tfm)->crt_rng;
+}
+
+static inline void crypto_free_rng(struct crypto_rng *tfm)
+{
+        crypto_free_tfm(crypto_rng_tfm(tfm));
+}
+
+static inline int crypto_rng_get_bytes(struct crypto_rng *tfm,
+                                       u8 *rdata, unsigned int dlen)
+{
+        return crypto_rng_crt(tfm)->rng_gen_random(tfm, rdata, dlen);
+}
+
+static inline int crypto_rng_reset(struct crypto_rng *tfm,
+                                   u8 *seed, unsigned int slen)
+{
+        return crypto_rng_crt(tfm)->rng_reset(tfm, seed, slen);
+}
+
+static inline int crypto_rng_seedsize(struct crypto_rng *tfm)
+{
+        return crypto_rng_alg(tfm)->seedsize;
+}
+
+#endif
diff --git a/include/drm/drm.h b/include/drm/drm.h
index 38d3c6b8276a..f46ba4b57da4 100644
--- a/include/drm/drm.h
+++ b/include/drm/drm.h
@@ -36,7 +36,6 @@
 #ifndef _DRM_H_
 #define _DRM_H_
 
-#if defined(__linux__)
 #if defined(__KERNEL__)
 #endif
 #include <asm/ioctl.h>          /* For _IO* macros */
@@ -46,22 +45,6 @@
 #define DRM_IOC_WRITE           _IOC_WRITE
 #define DRM_IOC_READWRITE       _IOC_READ|_IOC_WRITE
 #define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
-#elif defined(__FreeBSD__) || defined(__NetBSD__) || defined(__OpenBSD__)
-#if defined(__FreeBSD__) && defined(IN_MODULE)
-/* Prevent name collision when including sys/ioccom.h */
-#undef ioctl
-#include <sys/ioccom.h>
-#define ioctl(a,b,c)            xf86ioctl(a,b,c)
-#else
-#include <sys/ioccom.h>
-#endif                          /* __FreeBSD__ && xf86ioctl */
-#define DRM_IOCTL_NR(n)         ((n) & 0xff)
-#define DRM_IOC_VOID            IOC_VOID
-#define DRM_IOC_READ            IOC_OUT
-#define DRM_IOC_WRITE           IOC_IN
-#define DRM_IOC_READWRITE       IOC_INOUT
-#define DRM_IOC(dir, group, nr, size) _IOC(dir, group, nr, size)
-#endif
 
 #define DRM_MAJOR       226
 #define DRM_MAX_MINOR   15
@@ -471,6 +454,7 @@ struct drm_irq_busid {
 enum drm_vblank_seq_type {
         _DRM_VBLANK_ABSOLUTE = 0x0,     /**< Wait for specific vblank sequence number */
         _DRM_VBLANK_RELATIVE = 0x1,     /**< Wait for given number of vblanks */
+        _DRM_VBLANK_FLIP = 0x8000000,   /**< Scheduled buffer swap should flip */
         _DRM_VBLANK_NEXTONMISS = 0x10000000,    /**< If missed, wait for next vblank */
         _DRM_VBLANK_SECONDARY = 0x20000000,     /**< Secondary display controller */
         _DRM_VBLANK_SIGNAL = 0x40000000 /**< Send signal instead of blocking */
@@ -503,6 +487,19 @@ union drm_wait_vblank {
         struct drm_wait_vblank_reply reply;
 };
 
+#define _DRM_PRE_MODESET 1
+#define _DRM_POST_MODESET 2
+
+/**
+ * DRM_IOCTL_MODESET_CTL ioctl argument type
+ *
+ * \sa drmModesetCtl().
+ */
+struct drm_modeset_ctl {
+        uint32_t crtc;
+        uint32_t cmd;
+};
+
 /**
  * DRM_IOCTL_AGP_ENABLE ioctl argument type.
  *
@@ -573,6 +570,34 @@ struct drm_set_version {
         int drm_dd_minor;
 };
 
+/** DRM_IOCTL_GEM_CLOSE ioctl argument type */
+struct drm_gem_close {
+        /** Handle of the object to be closed. */
+        uint32_t handle;
+        uint32_t pad;
+};
+
+/** DRM_IOCTL_GEM_FLINK ioctl argument type */
+struct drm_gem_flink {
+        /** Handle for the object being named */
+        uint32_t handle;
+
+        /** Returned global name */
+        uint32_t name;
+};
+
+/** DRM_IOCTL_GEM_OPEN ioctl argument type */
+struct drm_gem_open {
+        /** Name of object being opened */
+        uint32_t name;
+
+        /** Returned handle for the object */
+        uint32_t handle;
+
+        /** Returned size of the object */
+        uint64_t size;
+};
+
 #define DRM_IOCTL_BASE                  'd'
 #define DRM_IO(nr)                      _IO(DRM_IOCTL_BASE,nr)
 #define DRM_IOR(nr,type)                _IOR(DRM_IOCTL_BASE,nr,type)
@@ -587,6 +612,10 @@ struct drm_set_version {
 #define DRM_IOCTL_GET_CLIENT            DRM_IOWR(0x05, struct drm_client)
 #define DRM_IOCTL_GET_STATS             DRM_IOR( 0x06, struct drm_stats)
 #define DRM_IOCTL_SET_VERSION           DRM_IOWR(0x07, struct drm_set_version)
+#define DRM_IOCTL_MODESET_CTL           DRM_IOW(0x08, struct drm_modeset_ctl)
+#define DRM_IOCTL_GEM_CLOSE             DRM_IOW (0x09, struct drm_gem_close)
+#define DRM_IOCTL_GEM_FLINK             DRM_IOWR(0x0a, struct drm_gem_flink)
+#define DRM_IOCTL_GEM_OPEN              DRM_IOWR(0x0b, struct drm_gem_open)
 
 #define DRM_IOCTL_SET_UNIQUE            DRM_IOW( 0x10, struct drm_unique)
 #define DRM_IOCTL_AUTH_MAGIC            DRM_IOW( 0x11, struct drm_auth)
diff --git a/include/drm/drmP.h b/include/drm/drmP.h
index 1c1b13e29223..59c796b46ee7 100644
--- a/include/drm/drmP.h
+++ b/include/drm/drmP.h
@@ -104,6 +104,7 @@ struct drm_device;
 #define DRIVER_DMA_QUEUE   0x200
 #define DRIVER_FB_DMA      0x400
 #define DRIVER_IRQ_VBL2    0x800
+#define DRIVER_GEM         0x1000
 
 /***********************************************************************/
 /** \name Begin the DRM... */
@@ -387,6 +388,10 @@ struct drm_file {
         struct drm_minor *minor;
         int remove_auth_on_close;
         unsigned long lock_count;
+        /** Mapping of mm object handles to object pointers. */
+        struct idr object_idr;
+        /** Lock for synchronization of access to object_idr. */
+        spinlock_t table_lock;
         struct file *filp;
         void *driver_priv;
 };
@@ -558,6 +563,56 @@ struct drm_ati_pcigart_info {
 };
 
 /**
+ * This structure defines the drm_mm memory object, which will be used by the
+ * DRM for its buffer objects.
+ */
+struct drm_gem_object {
+        /** Reference count of this object */
+        struct kref refcount;
+
+        /** Handle count of this object. Each handle also holds a reference */
+        struct kref handlecount;
+
+        /** Related drm device */
+        struct drm_device *dev;
+
+        /** File representing the shmem storage */
+        struct file *filp;
+
+        /**
+         * Size of the object, in bytes.  Immutable over the object's
+         * lifetime.
+         */
+        size_t size;
+
+        /**
+         * Global name for this object, starts at 1. 0 means unnamed.
+         * Access is covered by the object_name_lock in the related drm_device
+         */
+        int name;
+
+        /**
+         * Memory domains. These monitor which caches contain read/write data
+         * related to the object. When transitioning from one set of domains
+         * to another, the driver is called to ensure that caches are suitably
+         * flushed and invalidated
+         */
+        uint32_t read_domains;
+        uint32_t write_domain;
+
+        /**
+         * While validating an exec operation, the
+         * new read/write domain values are computed here.
+         * They will be transferred to the above values
+         * at the point that any cache flushing occurs
+         */
+        uint32_t pending_read_domains;
+        uint32_t pending_write_domain;
+
+        void *driver_private;
+};
+
+/**
  * DRM driver structure. This structure represent the common code for
  * a family of cards. There will one drm_device for each card present
  * in this family
@@ -580,11 +635,54 @@ struct drm_driver {
         int (*kernel_context_switch) (struct drm_device *dev, int old,
                                       int new);
         void (*kernel_context_switch_unlock) (struct drm_device *dev);
-        int (*vblank_wait) (struct drm_device *dev, unsigned int *sequence);
-        int (*vblank_wait2) (struct drm_device *dev, unsigned int *sequence);
         int (*dri_library_name) (struct drm_device *dev, char *buf);
 
         /**
+         * get_vblank_counter - get raw hardware vblank counter
+         * @dev: DRM device
+         * @crtc: counter to fetch
+         *
+         * Driver callback for fetching a raw hardware vblank counter
+         * for @crtc.  If a device doesn't have a hardware counter, the
+         * driver can simply return the value of drm_vblank_count and
+         * make the enable_vblank() and disable_vblank() hooks into no-ops,
+         * leaving interrupts enabled at all times.
+         *
+         * Wraparound handling and loss of events due to modesetting is dealt
+         * with in the DRM core code.
+         *
+         * RETURNS
+         * Raw vblank counter value.
+         */
+        u32 (*get_vblank_counter) (struct drm_device *dev, int crtc);
+
+        /**
+         * enable_vblank - enable vblank interrupt events
+         * @dev: DRM device
+         * @crtc: which irq to enable
+         *
+         * Enable vblank interrupts for @crtc.  If the device doesn't have
+         * a hardware vblank counter, this routine should be a no-op, since
+         * interrupts will have to stay on to keep the count accurate.
+         *
+         * RETURNS
+         * Zero on success, appropriate errno if the given @crtc's vblank
+         * interrupt cannot be enabled.
+         */
+        int (*enable_vblank) (struct drm_device *dev, int crtc);
+
+        /**
+         * disable_vblank - disable vblank interrupt events
+         * @dev: DRM device
+         * @crtc: which irq to enable
+         *
+         * Disable vblank interrupts for @crtc.  If the device doesn't have
+         * a hardware vblank counter, this routine should be a no-op, since
+         * interrupts will have to stay on to keep the count accurate.
+         */
+        void (*disable_vblank) (struct drm_device *dev, int crtc);
+
+        /**
          * Called by \c drm_device_is_agp.  Typically used to determine if a
          * card is really attached to AGP or not.
          *
@@ -601,7 +699,7 @@ struct drm_driver {
 
         irqreturn_t(*irq_handler) (DRM_IRQ_ARGS);
         void (*irq_preinstall) (struct drm_device *dev);
-        void (*irq_postinstall) (struct drm_device *dev);
+        int (*irq_postinstall) (struct drm_device *dev);
         void (*irq_uninstall) (struct drm_device *dev);
         void (*reclaim_buffers) (struct drm_device *dev,
                                  struct drm_file * file_priv);
@@ -614,6 +712,18 @@ struct drm_driver {
         void (*set_version) (struct drm_device *dev,
                              struct drm_set_version *sv);
 
+        int (*proc_init)(struct drm_minor *minor);
+        void (*proc_cleanup)(struct drm_minor *minor);
+
+        /**
+         * Driver-specific constructor for drm_gem_objects, to set up
+         * obj->driver_private.
+         *
+         * Returns 0 on success.
+         */
+        int (*gem_init_object) (struct drm_gem_object *obj);
+        void (*gem_free_object) (struct drm_gem_object *obj);
+
         int major;
         int minor;
         int patchlevel;
@@ -714,7 +824,6 @@ struct drm_device {
 
         /** \name Context support */
         /*@{ */
-        int irq;                        /**< Interrupt used by board */
         int irq_enabled;                /**< True if irq handler is enabled */
         __volatile__ long context_flag; /**< Context swapping flag */
         __volatile__ long interrupt_flag; /**< Interruption handler flag */
@@ -730,13 +839,28 @@ struct drm_device {
         /** \name VBLANK IRQ support */
         /*@{ */
 
-        wait_queue_head_t vbl_queue;    /**< VBLANK wait queue */
-        atomic_t vbl_received;
-        atomic_t vbl_received2;         /**< number of secondary VBLANK interrupts */
+        /*
+         * At load time, disabling the vblank interrupt won't be allowed since
+         * old clients may not call the modeset ioctl and therefore misbehave.
+         * Once the modeset ioctl *has* been called though, we can safely
+         * disable them when unused.
+         */
+        int vblank_disable_allowed;
+
+        wait_queue_head_t *vbl_queue;   /**< VBLANK wait queue */
+        atomic_t *_vblank_count;        /**< number of VBLANK interrupts (driver must alloc the right number of counters) */
         spinlock_t vbl_lock;
-        struct list_head vbl_sigs;              /**< signal list to send on VBLANK */
-        struct list_head vbl_sigs2;     /**< signals to send on secondary VBLANK */
-        unsigned int vbl_pending;
+        struct list_head *vbl_sigs;     /**< signal list to send on VBLANK */
+        atomic_t vbl_signal_pending;    /* number of signals pending on all crtcs*/
+        atomic_t *vblank_refcount;      /* number of users of vblank interruptsper crtc */
+        u32 *last_vblank;               /* protected by dev->vbl_lock, used */
+                                        /* for wraparound handling */
+        int *vblank_enabled;            /* so we don't call enable more than
+                                           once per disable */
+        int *vblank_inmodeset;          /* Display driver is setting mode */
+        struct timer_list vblank_disable_timer;
+
+        u32 max_vblank_count;           /**< size of vblank counter register */
         spinlock_t tasklet_lock;        /**< For drm_locked_tasklet */
         void (*locked_tasklet_func)(struct drm_device *dev);
 
@@ -757,6 +881,7 @@ struct drm_device {
         struct pci_controller *hose;
 #endif
         struct drm_sg_mem *sg;  /**< Scatter gather memory */
+        int num_crtcs;                  /**< Number of CRTCs on this device */
         void *dev_private;              /**< device private data */
         struct drm_sigdata sigdata;        /**< For block_all_signals */
         sigset_t sigmask;
@@ -771,8 +896,29 @@ struct drm_device {
         spinlock_t drw_lock;
         struct idr drw_idr;
         /*@} */
+
+        /** \name GEM information */
+        /*@{ */
+        spinlock_t object_name_lock;
+        struct idr object_name_idr;
+        atomic_t object_count;
+        atomic_t object_memory;
+        atomic_t pin_count;
+        atomic_t pin_memory;
+        atomic_t gtt_count;
+        atomic_t gtt_memory;
+        uint32_t gtt_total;
+        uint32_t invalidate_domains;    /* domains pending invalidation */
+        uint32_t flush_domains;         /* domains pending flush */
+        /*@} */
+
 };
 
+static inline int drm_dev_to_irq(struct drm_device *dev)
+{
+        return dev->pdev->irq;
+}
+
 static __inline__ int drm_core_check_feature(struct drm_device *dev,
                                              int feature)
 {
@@ -867,6 +1013,11 @@ extern void *drm_realloc(void *oldpt, size_t oldsize, size_t size, int area);
 extern DRM_AGP_MEM *drm_alloc_agp(struct drm_device *dev, int pages, u32 type);
 extern int drm_free_agp(DRM_AGP_MEM * handle, int pages);
 extern int drm_bind_agp(DRM_AGP_MEM * handle, unsigned int start);
+extern DRM_AGP_MEM *drm_agp_bind_pages(struct drm_device *dev,
+                                       struct page **pages,
+                                       unsigned long num_pages,
+                                       uint32_t gtt_offset,
+                                       uint32_t type);
 extern int drm_unbind_agp(DRM_AGP_MEM * handle);
 
                                 /* Misc. IOCTL support (drm_ioctl.h) */
@@ -929,6 +1080,9 @@ extern int drm_getmagic(struct drm_device *dev, void *data,
 extern int drm_authmagic(struct drm_device *dev, void *data,
                          struct drm_file *file_priv);
 
+/* Cache management (drm_cache.c) */
+void drm_clflush_pages(struct page *pages[], unsigned long num_pages);
+
                                 /* Locking IOCTL support (drm_lock.h) */
 extern int drm_lock(struct drm_device *dev, void *data,
                     struct drm_file *file_priv);
@@ -985,15 +1139,25 @@ extern void drm_core_reclaim_buffers(struct drm_device *dev,
 extern int drm_control(struct drm_device *dev, void *data,
                        struct drm_file *file_priv);
 extern irqreturn_t drm_irq_handler(DRM_IRQ_ARGS);
+extern int drm_irq_install(struct drm_device *dev);
 extern int drm_irq_uninstall(struct drm_device *dev);
 extern void drm_driver_irq_preinstall(struct drm_device *dev);
 extern void drm_driver_irq_postinstall(struct drm_device *dev);
 extern void drm_driver_irq_uninstall(struct drm_device *dev);
 
+extern int drm_vblank_init(struct drm_device *dev, int num_crtcs);
 extern int drm_wait_vblank(struct drm_device *dev, void *data,
-                           struct drm_file *file_priv);
+                           struct drm_file *filp);
 extern int drm_vblank_wait(struct drm_device *dev, unsigned int *vbl_seq);
-extern void drm_vbl_send_signals(struct drm_device *dev);
+extern void drm_locked_tasklet(struct drm_device *dev,
+                               void(*func)(struct drm_device *));
+extern u32 drm_vblank_count(struct drm_device *dev, int crtc);
+extern void drm_handle_vblank(struct drm_device *dev, int crtc);
+extern int drm_vblank_get(struct drm_device *dev, int crtc);
+extern void drm_vblank_put(struct drm_device *dev, int crtc);
+/* Modesetting support */
+extern int drm_modeset_ctl(struct drm_device *dev, void *data,
+                           struct drm_file *file_priv);
 extern void drm_locked_tasklet(struct drm_device *dev, void(*func)(struct drm_device*));
 
                                 /* AGP/GART support (drm_agpsupport.h) */
@@ -1026,6 +1190,7 @@ extern DRM_AGP_MEM *drm_agp_allocate_memory(struct agp_bridge_data *bridge, size
 extern int drm_agp_free_memory(DRM_AGP_MEM * handle);
 extern int drm_agp_bind_memory(DRM_AGP_MEM * handle, off_t start);
 extern int drm_agp_unbind_memory(DRM_AGP_MEM * handle);
+extern void drm_agp_chipset_flush(struct drm_device *dev);
 
                                 /* Stub support (drm_stub.h) */
 extern int drm_get_dev(struct pci_dev *pdev, const struct pci_device_id *ent,
@@ -1088,6 +1253,66 @@ extern unsigned long drm_mm_tail_space(struct drm_mm *mm);
 extern int drm_mm_remove_space_from_tail(struct drm_mm *mm, unsigned long size);
 extern int drm_mm_add_space_to_tail(struct drm_mm *mm, unsigned long size);
 
+/* Graphics Execution Manager library functions (drm_gem.c) */
+int drm_gem_init(struct drm_device *dev);
+void drm_gem_object_free(struct kref *kref);
+struct drm_gem_object *drm_gem_object_alloc(struct drm_device *dev,
+                                            size_t size);
+void drm_gem_object_handle_free(struct kref *kref);
+
+static inline void
+drm_gem_object_reference(struct drm_gem_object *obj)
+{
+        kref_get(&obj->refcount);
+}
+
+static inline void
+drm_gem_object_unreference(struct drm_gem_object *obj)
+{
+        if (obj == NULL)
+                return;
+
+        kref_put(&obj->refcount, drm_gem_object_free);
+}
+
+int drm_gem_handle_create(struct drm_file *file_priv,
+                          struct drm_gem_object *obj,
+                          int *handlep);
+
+static inline void
+drm_gem_object_handle_reference(struct drm_gem_object *obj)
+{
+        drm_gem_object_reference(obj);
+        kref_get(&obj->handlecount);
+}
+
+static inline void
+drm_gem_object_handle_unreference(struct drm_gem_object *obj)
+{
+        if (obj == NULL)
+                return;
+
+        /*
+         * Must bump handle count first as this may be the last
+         * ref, in which case the object would disappear before we
+         * checked for a name
+         */
+        kref_put(&obj->handlecount, drm_gem_object_handle_free);
+        drm_gem_object_unreference(obj);
+}
+
+struct drm_gem_object *drm_gem_object_lookup(struct drm_device *dev,
+                                             struct drm_file *filp,
+                                             int handle);
+int drm_gem_close_ioctl(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+int drm_gem_flink_ioctl(struct drm_device *dev, void *data,
+                        struct drm_file *file_priv);
+int drm_gem_open_ioctl(struct drm_device *dev, void *data,
+                       struct drm_file *file_priv);
+void drm_gem_open(struct drm_device *dev, struct drm_file *file_private);
+void drm_gem_release(struct drm_device *dev, struct drm_file *file_private);
+
 extern void drm_core_ioremap(struct drm_map *map, struct drm_device *dev);
 extern void drm_core_ioremap_wc(struct drm_map *map, struct drm_device *dev);
 extern void drm_core_ioremapfree(struct drm_map *map, struct drm_device *dev);
diff --git a/include/drm/drm_pciids.h b/include/drm/drm_pciids.h
index 135bd19499fc..da04109741e8 100644
--- a/include/drm/drm_pciids.h
+++ b/include/drm/drm_pciids.h
@@ -84,18 +84,18 @@
         {0x1002, 0x5462, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
         {0x1002, 0x5464, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_IS_MOBILITY}, \
         {0x1002, 0x5657, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5548, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5549, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554C, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554D, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554E, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x554F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5550, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5551, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5552, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5554, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x564A, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x564B, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x564F, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
@@ -113,8 +113,10 @@
         {0x1002, 0x5964, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5965, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280}, \
         {0x1002, 0x5969, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV100}, \
-        {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
-        {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS480|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a41, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a42, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x5a62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS400|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_IS_IGPGART}, \
         {0x1002, 0x5b60, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5b62, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5b63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
@@ -122,16 +124,16 @@
         {0x1002, 0x5b65, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV380|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5c61, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
         {0x1002, 0x5c63, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV280|RADEON_IS_MOBILITY}, \
-        {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
-        {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R420|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d49, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d4f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d50, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d52, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
+        {0x1002, 0x5d57, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_R423|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5e48, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5e4a, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x5e4b, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RV410|RADEON_NEW_MEMMAP}, \
@@ -237,6 +239,10 @@
         {0x1002, 0x7835, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS300|RADEON_IS_IGP|RADEON_IS_MOBILITY|RADEON_NEW_MEMMAP}, \
         {0x1002, 0x791e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
         {0x1002, 0x791f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS690|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x796c, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x796d, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x796e, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
+        {0x1002, 0x796f, PCI_ANY_ID, PCI_ANY_ID, 0, 0, CHIP_RS740|RADEON_IS_IGP|RADEON_NEW_MEMMAP|RADEON_IS_IGPGART}, \
         {0, 0, 0}
 
 #define r128_PCI_IDS \
diff --git a/include/drm/i915_drm.h b/include/drm/i915_drm.h
index 05c66cf03a9e..eb4b35031a55 100644
--- a/include/drm/i915_drm.h
+++ b/include/drm/i915_drm.h
@@ -143,6 +143,22 @@ typedef struct _drm_i915_sarea {
 #define DRM_I915_GET_VBLANK_PIPE        0x0e
 #define DRM_I915_VBLANK_SWAP    0x0f
 #define DRM_I915_HWS_ADDR       0x11
+#define DRM_I915_GEM_INIT       0x13
+#define DRM_I915_GEM_EXECBUFFER 0x14
+#define DRM_I915_GEM_PIN        0x15
+#define DRM_I915_GEM_UNPIN      0x16
+#define DRM_I915_GEM_BUSY       0x17
+#define DRM_I915_GEM_THROTTLE   0x18
+#define DRM_I915_GEM_ENTERVT    0x19
+#define DRM_I915_GEM_LEAVEVT    0x1a
+#define DRM_I915_GEM_CREATE     0x1b
+#define DRM_I915_GEM_PREAD      0x1c
+#define DRM_I915_GEM_PWRITE     0x1d
+#define DRM_I915_GEM_MMAP       0x1e
+#define DRM_I915_GEM_SET_DOMAIN 0x1f
+#define DRM_I915_GEM_SW_FINISH  0x20
+#define DRM_I915_GEM_SET_TILING 0x21
+#define DRM_I915_GEM_GET_TILING 0x22
 
 #define DRM_IOCTL_I915_INIT             DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t)
 #define DRM_IOCTL_I915_FLUSH            DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH)
@@ -160,6 +176,20 @@ typedef struct _drm_i915_sarea {
 #define DRM_IOCTL_I915_SET_VBLANK_PIPE  DRM_IOW( DRM_COMMAND_BASE + DRM_I915_SET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 #define DRM_IOCTL_I915_GET_VBLANK_PIPE  DRM_IOR( DRM_COMMAND_BASE + DRM_I915_GET_VBLANK_PIPE, drm_i915_vblank_pipe_t)
 #define DRM_IOCTL_I915_VBLANK_SWAP      DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_VBLANK_SWAP, drm_i915_vblank_swap_t)
+#define DRM_IOCTL_I915_GEM_PIN          DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_PIN, struct drm_i915_gem_pin)
+#define DRM_IOCTL_I915_GEM_UNPIN        DRM_IOW(DRM_COMMAND_BASE + DRM_I915_GEM_UNPIN, struct drm_i915_gem_unpin)
+#define DRM_IOCTL_I915_GEM_BUSY         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_BUSY, struct drm_i915_gem_busy)
+#define DRM_IOCTL_I915_GEM_THROTTLE     DRM_IO ( DRM_COMMAND_BASE + DRM_I915_GEM_THROTTLE)
+#define DRM_IOCTL_I915_GEM_ENTERVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_ENTERVT)
+#define DRM_IOCTL_I915_GEM_LEAVEVT      DRM_IO(DRM_COMMAND_BASE + DRM_I915_GEM_LEAVEVT)
+#define DRM_IOCTL_I915_GEM_CREATE       DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_CREATE, struct drm_i915_gem_create)
+#define DRM_IOCTL_I915_GEM_PREAD        DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PREAD, struct drm_i915_gem_pread)
+#define DRM_IOCTL_I915_GEM_PWRITE       DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_PWRITE, struct drm_i915_gem_pwrite)
+#define DRM_IOCTL_I915_GEM_MMAP         DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_GEM_MMAP, struct drm_i915_gem_mmap)
+#define DRM_IOCTL_I915_GEM_SET_DOMAIN   DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SET_DOMAIN, struct drm_i915_gem_set_domain)
+#define DRM_IOCTL_I915_GEM_SW_FINISH    DRM_IOW (DRM_COMMAND_BASE + DRM_I915_GEM_SW_FINISH, struct drm_i915_gem_sw_finish)
+#define DRM_IOCTL_I915_GEM_SET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_SET_TILING, struct drm_i915_gem_set_tiling)
+#define DRM_IOCTL_I915_GEM_GET_TILING   DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_GET_TILING, struct drm_i915_gem_get_tiling)
 
 /* Allow drivers to submit batchbuffers directly to hardware, relying
  * on the security mechanisms provided by hardware.
@@ -200,6 +230,8 @@ typedef struct drm_i915_irq_wait {
 #define I915_PARAM_IRQ_ACTIVE            1
 #define I915_PARAM_ALLOW_BATCHBUFFER     2
 #define I915_PARAM_LAST_DISPATCH         3
+#define I915_PARAM_CHIPSET_ID            4
+#define I915_PARAM_HAS_GEM               5
 
 typedef struct drm_i915_getparam {
         int param;
@@ -267,4 +299,305 @@ typedef struct drm_i915_hws_addr {
         uint64_t addr;
 } drm_i915_hws_addr_t;
 
+struct drm_i915_gem_init {
+        /**
+         * Beginning offset in the GTT to be managed by the DRM memory
+         * manager.
+         */
+        uint64_t gtt_start;
+        /**
+         * Ending offset in the GTT to be managed by the DRM memory
+         * manager.
+         */
+        uint64_t gtt_end;
+};
+
+struct drm_i915_gem_create {
+        /**
+         * Requested size for the object.
+         *
+         * The (page-aligned) allocated size for the object will be returned.
+         */
+        uint64_t size;
+        /**
+         * Returned handle for the object.
+         *
+         * Object handles are nonzero.
+         */
+        uint32_t handle;
+        uint32_t pad;
+};
+
+struct drm_i915_gem_pread {
+        /** Handle for the object being read. */
+        uint32_t handle;
+        uint32_t pad;
+        /** Offset into the object to read from */
+        uint64_t offset;
+        /** Length of data to read */
+        uint64_t size;
+        /**
+         * Pointer to write the data into.
+         *
+         * This is a fixed-size type for 32/64 compatibility.
+         */
+        uint64_t data_ptr;
+};
+
+struct drm_i915_gem_pwrite {
+        /** Handle for the object being written to. */
+        uint32_t handle;
+        uint32_t pad;
+        /** Offset into the object to write to */
+        uint64_t offset;
+        /** Length of data to write */
+        uint64_t size;
+        /**
+         * Pointer to read the data from.
+         *
+         * This is a fixed-size type for 32/64 compatibility.
+         */
+        uint64_t data_ptr;
+};
+
+struct drm_i915_gem_mmap {
+        /** Handle for the object being mapped. */
+        uint32_t handle;
+        uint32_t pad;
+        /** Offset in the object to map. */
+        uint64_t offset;
+        /**
+         * Length of data to map.
+         *
+         * The value will be page-aligned.
+         */
+        uint64_t size;
+        /**
+         * Returned pointer the data was mapped at.
+         *
+         * This is a fixed-size type for 32/64 compatibility.
+         */
+        uint64_t addr_ptr;
+};
+
+struct drm_i915_gem_set_domain {
+        /** Handle for the object */
+        uint32_t handle;
+
+        /** New read domains */
+        uint32_t read_domains;
+
+        /** New write domain */
+        uint32_t write_domain;
+};
+
+struct drm_i915_gem_sw_finish {
+        /** Handle for the object */
+        uint32_t handle;
+};
+
+struct drm_i915_gem_relocation_entry {
+        /**
+         * Handle of the buffer being pointed to by this relocation entry.
+         *
+         * It's appealing to make this be an index into the mm_validate_entry
+         * list to refer to the buffer, but this allows the driver to create
+         * a relocation list for state buffers and not re-write it per
+         * exec using the buffer.
+         */
+        uint32_t target_handle;
+
+        /**
+         * Value to be added to the offset of the target buffer to make up
+         * the relocation entry.
+         */
+        uint32_t delta;
+
+        /** Offset in the buffer the relocation entry will be written into */
+        uint64_t offset;
+
+        /**
+         * Offset value of the target buffer that the relocation entry was last
+         * written as.
+         *
+         * If the buffer has the same offset as last time, we can skip syncing
+         * and writing the relocation.  This value is written back out by
+         * the execbuffer ioctl when the relocation is written.
+         */
+        uint64_t presumed_offset;
+
+        /**
+         * Target memory domains read by this operation.
+         */
+        uint32_t read_domains;
+
+        /**
+         * Target memory domains written by this operation.
+         *
+         * Note that only one domain may be written by the whole
+         * execbuffer operation, so that where there are conflicts,
+         * the application will get -EINVAL back.
+         */
+        uint32_t write_domain;
+};
+
+/** @{
+ * Intel memory domains
+ *
+ * Most of these just align with the various caches in
+ * the system and are used to flush and invalidate as
+ * objects end up cached in different domains.
+ */
+/** CPU cache */
+#define I915_GEM_DOMAIN_CPU             0x00000001
+/** Render cache, used by 2D and 3D drawing */
+#define I915_GEM_DOMAIN_RENDER          0x00000002
+/** Sampler cache, used by texture engine */
+#define I915_GEM_DOMAIN_SAMPLER         0x00000004
+/** Command queue, used to load batch buffers */
+#define I915_GEM_DOMAIN_COMMAND         0x00000008
+/** Instruction cache, used by shader programs */
+#define I915_GEM_DOMAIN_INSTRUCTION     0x00000010
+/** Vertex address cache */
+#define I915_GEM_DOMAIN_VERTEX          0x00000020
+/** GTT domain - aperture and scanout */
+#define I915_GEM_DOMAIN_GTT             0x00000040
+/** @} */
+
+struct drm_i915_gem_exec_object {
+        /**
+         * User's handle for a buffer to be bound into the GTT for this
+         * operation.
+         */
+        uint32_t handle;
+
+        /** Number of relocations to be performed on this buffer */
+        uint32_t relocation_count;
+        /**
+         * Pointer to array of struct drm_i915_gem_relocation_entry containing
+         * the relocations to be performed in this buffer.
+         */
+        uint64_t relocs_ptr;
+
+        /** Required alignment in graphics aperture */
+        uint64_t alignment;
+
+        /**
+         * Returned value of the updated offset of the object, for future
+         * presumed_offset writes.
+         */
+        uint64_t offset;
+};
+
+struct drm_i915_gem_execbuffer {
+        /**
+         * List of buffers to be validated with their relocations to be
+         * performend on them.
+         *
+         * This is a pointer to an array of struct drm_i915_gem_validate_entry.
+         *
+         * These buffers must be listed in an order such that all relocations
+         * a buffer is performing refer to buffers that have already appeared
+         * in the validate list.
+         */
+        uint64_t buffers_ptr;
+        uint32_t buffer_count;
+
+        /** Offset in the batchbuffer to start execution from. */
+        uint32_t batch_start_offset;
+        /** Bytes used in batchbuffer from batch_start_offset */
+        uint32_t batch_len;
+        uint32_t DR1;
+        uint32_t DR4;
+        uint32_t num_cliprects;
+        /** This is a struct drm_clip_rect *cliprects */
+        uint64_t cliprects_ptr;
+};
+
+struct drm_i915_gem_pin {
+        /** Handle of the buffer to be pinned. */
+        uint32_t handle;
+        uint32_t pad;
+
+        /** alignment required within the aperture */
+        uint64_t alignment;
+
+        /** Returned GTT offset of the buffer. */
+        uint64_t offset;
+};
+
+struct drm_i915_gem_unpin {
+        /** Handle of the buffer to be unpinned. */
+        uint32_t handle;
+        uint32_t pad;
+};
+
+struct drm_i915_gem_busy {
+        /** Handle of the buffer to check for busy */
+        uint32_t handle;
+
+        /** Return busy status (1 if busy, 0 if idle) */
+        uint32_t busy;
+};
+
+#define I915_TILING_NONE        0
+#define I915_TILING_X           1
+#define I915_TILING_Y           2
+
+#define I915_BIT_6_SWIZZLE_NONE         0
+#define I915_BIT_6_SWIZZLE_9            1
+#define I915_BIT_6_SWIZZLE_9_10         2
+#define I915_BIT_6_SWIZZLE_9_11         3
+#define I915_BIT_6_SWIZZLE_9_10_11      4
+/* Not seen by userland */
+#define I915_BIT_6_SWIZZLE_UNKNOWN      5
+
+struct drm_i915_gem_set_tiling {
+        /** Handle of the buffer to have its tiling state updated */
+        uint32_t handle;
+
+        /**
+         * Tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+         * I915_TILING_Y).
+         *
+         * This value is to be set on request, and will be updated by the
+         * kernel on successful return with the actual chosen tiling layout.
+         *
+         * The tiling mode may be demoted to I915_TILING_NONE when the system
+         * has bit 6 swizzling that can't be managed correctly by GEM.
+         *
+         * Buffer contents become undefined when changing tiling_mode.
+         */
+        uint32_t tiling_mode;
+
+        /**
+         * Stride in bytes for the object when in I915_TILING_X or
+         * I915_TILING_Y.
+         */
+        uint32_t stride;
+
+        /**
+         * Returned address bit 6 swizzling required for CPU access through
+         * mmap mapping.
+         */
+        uint32_t swizzle_mode;
+};
+
+struct drm_i915_gem_get_tiling {
+        /** Handle of the buffer to get tiling state for. */
+        uint32_t handle;
+
+        /**
+         * Current tiling mode for the object (I915_TILING_NONE, I915_TILING_X,
+         * I915_TILING_Y).
+         */
+        uint32_t tiling_mode;
+
+        /**
+         * Returned address bit 6 swizzling required for CPU access through
+         * mmap mapping.
+         */
+        uint32_t swizzle_mode;
+};
+
 #endif                          /* _I915_DRM_H_ */
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 7d970678f940..bf9aca548f14 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -107,6 +107,7 @@ header-y += keyctl.h
 header-y += limits.h
 header-y += magic.h
 header-y += major.h
+header-y += map_to_7segment.h
 header-y += matroxfb.h
 header-y += meye.h
 header-y += minix_fs.h
@@ -126,6 +127,7 @@ header-y += pci_regs.h
 header-y += pfkeyv2.h
 header-y += pg.h
 header-y += phantom.h
+header-y += phonet.h
 header-y += pkt_cls.h
 header-y += pkt_sched.h
 header-y += posix_types.h
@@ -167,7 +169,8 @@ unifdef-y += acct.h
 unifdef-y += adb.h
 unifdef-y += adfs_fs.h
 unifdef-y += agpgart.h
-ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/a.out.h),)
+ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/a.out.h \
+                  $(srctree)/include/asm-$(SRCARCH)/a.out.h),)
 unifdef-y += a.out.h
 endif
 unifdef-y += apm_bios.h
@@ -179,6 +182,7 @@ unifdef-y += audit.h
 unifdef-y += auto_fs.h
 unifdef-y += auxvec.h
 unifdef-y += binfmts.h
+unifdef-y += blktrace_api.h
 unifdef-y += capability.h
 unifdef-y += capi.h
 unifdef-y += cciss_ioctl.h
@@ -231,6 +235,7 @@ unifdef-y += if_fddi.h
 unifdef-y += if_frad.h
 unifdef-y += if_ltalk.h
 unifdef-y += if_link.h
+unifdef-y += if_phonet.h
 unifdef-y += if_pppol2tp.h
 unifdef-y += if_pppox.h
 unifdef-y += if_tr.h
@@ -258,7 +263,8 @@ unifdef-y += kd.h
 unifdef-y += kernelcapi.h
 unifdef-y += kernel.h
 unifdef-y += keyboard.h
-ifneq ($(wildcard $(srctree)/include/asm-$(SRCARCH)/kvm.h),)
+ifneq ($(wildcard $(srctree)/arch/$(SRCARCH)/include/asm/kvm.h \
+                  $(srctree)/include/asm-$(SRCARCH)/kvm.h),)
 unifdef-y += kvm.h
 endif
 unifdef-y += llc.h
@@ -297,7 +303,6 @@ unifdef-y += parport.h
 unifdef-y += patchkey.h
 unifdef-y += pci.h
 unifdef-y += personality.h
-unifdef-y += pim.h
 unifdef-y += pktcdvd.h
 unifdef-y += pmu.h
 unifdef-y += poll.h
diff --git a/include/linux/aio.h b/include/linux/aio.h
index 09b276c35227..f6b8cf99b596 100644
--- a/include/linux/aio.h
+++ b/include/linux/aio.h
@@ -204,12 +204,21 @@ struct kioctx {
 /* prototypes */
 extern unsigned aio_max_size;
 
+#ifdef CONFIG_AIO
 extern ssize_t wait_on_sync_kiocb(struct kiocb *iocb);
 extern int aio_put_req(struct kiocb *iocb);
 extern void kick_iocb(struct kiocb *iocb);
 extern int aio_complete(struct kiocb *iocb, long res, long res2);
 struct mm_struct;
 extern void exit_aio(struct mm_struct *mm);
+#else
+static inline ssize_t wait_on_sync_kiocb(struct kiocb *iocb) { return 0; }
+static inline int aio_put_req(struct kiocb *iocb) { return 0; }
+static inline void kick_iocb(struct kiocb *iocb) { }
+static inline int aio_complete(struct kiocb *iocb, long res, long res2) { return 0; }
+struct mm_struct;
+static inline void exit_aio(struct mm_struct *mm) { }
+#endif /* CONFIG_AIO */
 
 #define io_wait_to_kiocb(wait) container_of(wait, struct kiocb, ki_wait)
 
diff --git a/include/linux/ata.h b/include/linux/ata.h
index 1ce19c1ef0e9..a53318b8cbd0 100644
--- a/include/linux/ata.h
+++ b/include/linux/ata.h
@@ -30,6 +30,7 @@
 #define __LINUX_ATA_H__
 
 #include <linux/types.h>
+#include <asm/byteorder.h>
 
 /* defines only for the constants which don't work well as enums */
 #define ATA_DMA_BOUNDARY        0xffffUL
@@ -88,6 +89,7 @@ enum {
         ATA_ID_DLF              = 128,
         ATA_ID_CSFO             = 129,
         ATA_ID_CFA_POWER        = 160,
+        ATA_ID_ROT_SPEED        = 217,
         ATA_ID_PIO4             = (1 << 1),
 
         ATA_ID_SERNO_LEN        = 20,
@@ -557,6 +559,15 @@ static inline int ata_id_has_flush(const u16 *id)
         return id[ATA_ID_COMMAND_SET_2] & (1 << 12);
 }
 
+static inline int ata_id_flush_enabled(const u16 *id)
+{
+        if (ata_id_has_flush(id) == 0)
+                return 0;
+        if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
+                return 0;
+        return id[ATA_ID_CFS_ENABLE_2] & (1 << 12);
+}
+
 static inline int ata_id_has_flush_ext(const u16 *id)
 {
         if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
@@ -564,6 +575,19 @@ static inline int ata_id_has_flush_ext(const u16 *id)
         return id[ATA_ID_COMMAND_SET_2] & (1 << 13);
 }
 
+static inline int ata_id_flush_ext_enabled(const u16 *id)
+{
+        if (ata_id_has_flush_ext(id) == 0)
+                return 0;
+        if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
+                return 0;
+        /*
+         * some Maxtor disks have bit 13 defined incorrectly
+         * so check bit 10 too
+         */
+        return (id[ATA_ID_CFS_ENABLE_2] & 0x2400) == 0x2400;
+}
+
 static inline int ata_id_has_lba48(const u16 *id)
 {
         if ((id[ATA_ID_COMMAND_SET_2] & 0xC000) != 0x4000)
@@ -573,6 +597,15 @@ static inline int ata_id_has_lba48(const u16 *id)
         return id[ATA_ID_COMMAND_SET_2] & (1 << 10);
 }
 
+static inline int ata_id_lba48_enabled(const u16 *id)
+{
+        if (ata_id_has_lba48(id) == 0)
+                return 0;
+        if ((id[ATA_ID_CSF_DEFAULT] & 0xC000) != 0x4000)
+                return 0;
+        return id[ATA_ID_CFS_ENABLE_2] & (1 << 10);
+}
+
 static inline int ata_id_hpa_enabled(const u16 *id)
 {
         /* Yes children, word 83 valid bits cover word 82 data */
@@ -644,7 +677,15 @@ static inline unsigned int ata_id_major_version(const u16 *id)
 
 static inline int ata_id_is_sata(const u16 *id)
 {
-        return ata_id_major_version(id) >= 5 && id[ATA_ID_HW_CONFIG] == 0;
+        /*
+         * See if word 93 is 0 AND drive is at least ATA-5 compatible
+         * verifying that word 80 by casting it to a signed type --
+         * this trick allows us to filter out the reserved values of
+         * 0x0000 and 0xffff along with the earlier ATA revisions...
+         */
+        if (id[ATA_ID_HW_CONFIG] == 0 && (short)id[ATA_ID_MAJOR_VER] >= 0x0020)
+                return 1;
+        return 0;
 }
 
 static inline int ata_id_has_tpm(const u16 *id)
@@ -667,6 +708,15 @@ static inline int ata_id_has_dword_io(const u16 *id)
         return 0;
 }
 
+static inline int ata_id_has_unload(const u16 *id)
+{
+        if (ata_id_major_version(id) >= 7 &&
+            (id[ATA_ID_CFSSE] & 0xC000) == 0x4000 &&
+            id[ATA_ID_CFSSE] & (1 << 13))
+                return 1;
+        return 0;
+}
+
 static inline int ata_id_current_chs_valid(const u16 *id)
 {
         /* For ATA-1 devices, if the INITIALIZE DEVICE PARAMETERS command
@@ -691,6 +741,11 @@ static inline int ata_id_is_cfa(const u16 *id)
         return 0;
 }
 
+static inline int ata_id_is_ssd(const u16 *id)
+{
+        return id[ATA_ID_ROT_SPEED] == 0x01;
+}
+
 static inline int ata_drive_40wire(const u16 *dev_id)
 {
         if (ata_id_is_sata(dev_id))
@@ -727,6 +782,76 @@ static inline int atapi_id_dmadir(const u16 *dev_id)
         return ata_id_major_version(dev_id) >= 7 && (dev_id[62] & 0x8000);
 }
 
+/*
+ * ata_id_is_lba_capacity_ok() performs a sanity check on
+ * the claimed LBA capacity value for the device.
+ *
+ * Returns 1 if LBA capacity looks sensible, 0 otherwise.
+ *
+ * It is called only once for each device.
+ */
+static inline int ata_id_is_lba_capacity_ok(u16 *id)
+{
+        unsigned long lba_sects, chs_sects, head, tail;
+
+        /* No non-LBA info .. so valid! */
+        if (id[ATA_ID_CYLS] == 0)
+                return 1;
+
+        lba_sects = ata_id_u32(id, ATA_ID_LBA_CAPACITY);
+
+        /*
+         * The ATA spec tells large drives to return
+         * C/H/S = 16383/16/63 independent of their size.
+         * Some drives can be jumpered to use 15 heads instead of 16.
+         * Some drives can be jumpered to use 4092 cyls instead of 16383.
+         */
+        if ((id[ATA_ID_CYLS] == 16383 ||
+             (id[ATA_ID_CYLS] == 4092 && id[ATA_ID_CUR_CYLS] == 16383)) &&
+            id[ATA_ID_SECTORS] == 63 &&
+            (id[ATA_ID_HEADS] == 15 || id[ATA_ID_HEADS] == 16) &&
+            (lba_sects >= 16383 * 63 * id[ATA_ID_HEADS]))
+                return 1;
+
+        chs_sects = id[ATA_ID_CYLS] * id[ATA_ID_HEADS] * id[ATA_ID_SECTORS];
+
+        /* perform a rough sanity check on lba_sects: within 10% is OK */
+        if (lba_sects - chs_sects < chs_sects/10)
+                return 1;
+
+        /* some drives have the word order reversed */
+        head = (lba_sects >> 16) & 0xffff;
+        tail = lba_sects & 0xffff;
+        lba_sects = head | (tail << 16);
+
+        if (lba_sects - chs_sects < chs_sects/10) {
+                *(__le32 *)&id[ATA_ID_LBA_CAPACITY] = __cpu_to_le32(lba_sects);
+                return 1;       /* LBA capacity is (now) good */
+        }
+
+        return 0;       /* LBA capacity value may be bad */
+}
+
+static inline void ata_id_to_hd_driveid(u16 *id)
+{
+#ifdef __BIG_ENDIAN
+        /* accessed in struct hd_driveid as 8-bit values */
+        id[ATA_ID_MAX_MULTSECT]  = __cpu_to_le16(id[ATA_ID_MAX_MULTSECT]);
+        id[ATA_ID_CAPABILITY]    = __cpu_to_le16(id[ATA_ID_CAPABILITY]);
+        id[ATA_ID_OLD_PIO_MODES] = __cpu_to_le16(id[ATA_ID_OLD_PIO_MODES]);
+        id[ATA_ID_OLD_DMA_MODES] = __cpu_to_le16(id[ATA_ID_OLD_DMA_MODES]);
+        id[ATA_ID_MULTSECT]      = __cpu_to_le16(id[ATA_ID_MULTSECT]);
+
+        /* as 32-bit values */
+        *(u32 *)&id[ATA_ID_LBA_CAPACITY] = ata_id_u32(id, ATA_ID_LBA_CAPACITY);
+        *(u32 *)&id[ATA_ID_SPG]          = ata_id_u32(id, ATA_ID_SPG);
+
+        /* as 64-bit value */
+        *(u64 *)&id[ATA_ID_LBA_CAPACITY_2] =
+                ata_id_u64(id, ATA_ID_LBA_CAPACITY_2);
+#endif
+}
+
 static inline int is_multi_taskfile(struct ata_taskfile *tf)
 {
         return (tf->command == ATA_CMD_READ_MULTI) ||
@@ -745,7 +870,7 @@ static inline int ata_ok(u8 status)
 static inline int lba_28_ok(u64 block, u32 n_block)
 {
         /* check the ending block number */
-        return ((block + n_block - 1) < ((u64)1 << 28)) && (n_block <= 256);
+        return ((block + n_block) < ((u64)1 << 28)) && (n_block <= 256);
 }
 
 static inline int lba_48_ok(u64 block, u32 n_block)
diff --git a/include/linux/auto_dev-ioctl.h b/include/linux/auto_dev-ioctl.h
new file mode 100644
index 000000000000..f4d05ccd731f
--- /dev/null
+++ b/include/linux/auto_dev-ioctl.h
@@ -0,0 +1,157 @@
+/*
+ * Copyright 2008 Red Hat, Inc. All rights reserved.
+ * Copyright 2008 Ian Kent <raven@themaw.net>
+ *
+ * This file is part of the Linux kernel and is made available under
+ * the terms of the GNU General Public License, version 2, or at your
+ * option, any later version, incorporated herein by reference.
+ */
+
+#ifndef _LINUX_AUTO_DEV_IOCTL_H
+#define _LINUX_AUTO_DEV_IOCTL_H
+
+#include <linux/types.h>
+
+#define AUTOFS_DEVICE_NAME              "autofs"
+
+#define AUTOFS_DEV_IOCTL_VERSION_MAJOR  1
+#define AUTOFS_DEV_IOCTL_VERSION_MINOR  0
+
+#define AUTOFS_DEVID_LEN                16
+
+#define AUTOFS_DEV_IOCTL_SIZE           sizeof(struct autofs_dev_ioctl)
+
+/*
+ * An ioctl interface for autofs mount point control.
+ */
+
+/*
+ * All the ioctls use this structure.
+ * When sending a path size must account for the total length
+ * of the chunk of memory otherwise is is the size of the
+ * structure.
+ */
+
+struct autofs_dev_ioctl {
+        __u32 ver_major;
+        __u32 ver_minor;
+        __u32 size;             /* total size of data passed in
+                                 * including this struct */
+        __s32 ioctlfd;          /* automount command fd */
+
+        __u32 arg1;             /* Command parameters */
+        __u32 arg2;
+
+        char path[0];
+};
+
+static inline void init_autofs_dev_ioctl(struct autofs_dev_ioctl *in)
+{
+        in->ver_major = AUTOFS_DEV_IOCTL_VERSION_MAJOR;
+        in->ver_minor = AUTOFS_DEV_IOCTL_VERSION_MINOR;
+        in->size = sizeof(struct autofs_dev_ioctl);
+        in->ioctlfd = -1;
+        in->arg1 = 0;
+        in->arg2 = 0;
+        return;
+}
+
+/*
+ * If you change this make sure you make the corresponding change
+ * to autofs-dev-ioctl.c:lookup_ioctl()
+ */
+enum {
+        /* Get various version info */
+        AUTOFS_DEV_IOCTL_VERSION_CMD = 0x71,
+        AUTOFS_DEV_IOCTL_PROTOVER_CMD,
+        AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD,
+
+        /* Open mount ioctl fd */
+        AUTOFS_DEV_IOCTL_OPENMOUNT_CMD,
+
+        /* Close mount ioctl fd */
+        AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD,
+
+        /* Mount/expire status returns */
+        AUTOFS_DEV_IOCTL_READY_CMD,
+        AUTOFS_DEV_IOCTL_FAIL_CMD,
+
+        /* Activate/deactivate autofs mount */
+        AUTOFS_DEV_IOCTL_SETPIPEFD_CMD,
+        AUTOFS_DEV_IOCTL_CATATONIC_CMD,
+
+        /* Expiry timeout */
+        AUTOFS_DEV_IOCTL_TIMEOUT_CMD,
+
+        /* Get mount last requesting uid and gid */
+        AUTOFS_DEV_IOCTL_REQUESTER_CMD,
+
+        /* Check for eligible expire candidates */
+        AUTOFS_DEV_IOCTL_EXPIRE_CMD,
+
+        /* Request busy status */
+        AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD,
+
+        /* Check if path is a mountpoint */
+        AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD,
+};
+
+#define AUTOFS_IOCTL 0x93
+
+#define AUTOFS_DEV_IOCTL_VERSION \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_VERSION_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_PROTOVER \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_PROTOVER_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_PROTOSUBVER \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_PROTOSUBVER_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_OPENMOUNT \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_OPENMOUNT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_CLOSEMOUNT \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_CLOSEMOUNT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_READY \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_READY_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_FAIL \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_FAIL_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_SETPIPEFD \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_SETPIPEFD_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_CATATONIC \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_CATATONIC_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_TIMEOUT \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_TIMEOUT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_REQUESTER \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_REQUESTER_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_EXPIRE \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_EXPIRE_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_ASKUMOUNT \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_ASKUMOUNT_CMD, struct autofs_dev_ioctl)
+
+#define AUTOFS_DEV_IOCTL_ISMOUNTPOINT \
+        _IOWR(AUTOFS_IOCTL, \
+              AUTOFS_DEV_IOCTL_ISMOUNTPOINT_CMD, struct autofs_dev_ioctl)
+
+#endif  /* _LINUX_AUTO_DEV_IOCTL_H */
diff --git a/include/linux/auto_fs4.h b/include/linux/auto_fs4.h
index b785c6f8644d..2253716d4b92 100644
--- a/include/linux/auto_fs4.h
+++ b/include/linux/auto_fs4.h
@@ -23,12 +23,17 @@
 #define AUTOFS_MIN_PROTO_VERSION        3
 #define AUTOFS_MAX_PROTO_VERSION        5
 
-#define AUTOFS_PROTO_SUBVERSION         0
+#define AUTOFS_PROTO_SUBVERSION         1
 
 /* Mask for expire behaviour */
 #define AUTOFS_EXP_IMMEDIATE            1
 #define AUTOFS_EXP_LEAVES               2
 
+#define AUTOFS_TYPE_ANY                 0x0000
+#define AUTOFS_TYPE_INDIRECT            0x0001
+#define AUTOFS_TYPE_DIRECT              0x0002
+#define AUTOFS_TYPE_OFFSET              0x0004
+
 /* Daemon notification packet types */
 enum autofs_notify {
         NFY_NONE,
diff --git a/include/linux/binfmts.h b/include/linux/binfmts.h
index 826f62350805..7394b5b349ff 100644
--- a/include/linux/binfmts.h
+++ b/include/linux/binfmts.h
@@ -36,6 +36,10 @@ struct linux_binprm{
         unsigned long p; /* current top of mem */
         unsigned int sh_bang:1,
                      misc_bang:1;
+#ifdef __alpha__
+        unsigned int taso:1;
+#endif
+        unsigned int recursion_depth;
         struct file * file;
         int e_uid, e_gid;
         kernel_cap_t cap_post_exec_permitted;
@@ -58,6 +62,7 @@ struct linux_binprm{
 #define BINPRM_FLAGS_EXECFD_BIT 1
 #define BINPRM_FLAGS_EXECFD (1 << BINPRM_FLAGS_EXECFD_BIT)
 
+#define BINPRM_MAX_RECURSION 4
 
 /*
  * This structure defines the functions that are used to load the binary formats that
diff --git a/include/linux/bio.h b/include/linux/bio.h
index 0933a14e6414..1c91a176b9ae 100644
--- a/include/linux/bio.h
+++ b/include/linux/bio.h
@@ -26,21 +26,8 @@
 
 #ifdef CONFIG_BLOCK
 
-/* Platforms may set this to teach the BIO layer about IOMMU hardware. */
 #include <asm/io.h>
 
-#if defined(BIO_VMERGE_MAX_SIZE) && defined(BIO_VMERGE_BOUNDARY)
-#define BIOVEC_VIRT_START_SIZE(x) (bvec_to_phys(x) & (BIO_VMERGE_BOUNDARY - 1))
-#define BIOVEC_VIRT_OVERSIZE(x) ((x) > BIO_VMERGE_MAX_SIZE)
-#else
-#define BIOVEC_VIRT_START_SIZE(x)       0
-#define BIOVEC_VIRT_OVERSIZE(x)         0
-#endif
-
-#ifndef BIO_VMERGE_BOUNDARY
-#define BIO_VMERGE_BOUNDARY     0
-#endif
-
 #define BIO_DEBUG
 
 #ifdef BIO_DEBUG
@@ -88,25 +75,21 @@ struct bio {
         /* Number of segments in this BIO after
          * physical address coalescing is performed.
          */
-        unsigned short          bi_phys_segments;
-
-        /* Number of segments after physical and DMA remapping
-         * hardware coalescing is performed.
-         */
-        unsigned short          bi_hw_segments;
+        unsigned int            bi_phys_segments;
 
         unsigned int            bi_size;        /* residual I/O count */
 
         /*
-         * To keep track of the max hw size, we account for the
-         * sizes of the first and last virtually mergeable segments
-         * in this bio
+         * To keep track of the max segment size, we account for the
+         * sizes of the first and last mergeable segments in this bio.
          */
-        unsigned int            bi_hw_front_size;
-        unsigned int            bi_hw_back_size;
+        unsigned int            bi_seg_front_size;
+        unsigned int            bi_seg_back_size;
 
         unsigned int            bi_max_vecs;    /* max bvl_vecs we can hold */
 
+        unsigned int            bi_comp_cpu;    /* completion CPU */
+
         struct bio_vec          *bi_io_vec;     /* the actual vec list */
 
         bio_end_io_t            *bi_end_io;
@@ -126,11 +109,14 @@ struct bio {
 #define BIO_UPTODATE    0       /* ok after I/O completion */
 #define BIO_RW_BLOCK    1       /* RW_AHEAD set, and read/write would block */
 #define BIO_EOF         2       /* out-out-bounds error */
-#define BIO_SEG_VALID   3       /* nr_hw_seg valid */
+#define BIO_SEG_VALID   3       /* bi_phys_segments valid */
 #define BIO_CLONED      4       /* doesn't own data */
 #define BIO_BOUNCED     5       /* bio is a bounce bio */
 #define BIO_USER_MAPPED 6       /* contains user pages */
 #define BIO_EOPNOTSUPP  7       /* not supported */
+#define BIO_CPU_AFFINE  8       /* complete bio on same CPU as submitted */
+#define BIO_NULL_MAPPED 9       /* contains invalid user pages */
+#define BIO_FS_INTEGRITY 10     /* fs owns integrity data, not block layer */
 #define bio_flagged(bio, flag)  ((bio)->bi_flags & (1 << (flag)))
 
 /*
@@ -144,18 +130,36 @@ struct bio {
 /*
  * bio bi_rw flags
  *
- * bit 0 -- read (not set) or write (set)
+ * bit 0 -- data direction
+ *      If not set, bio is a read from device. If set, it's a write to device.
  * bit 1 -- rw-ahead when set
  * bit 2 -- barrier
- * bit 3 -- fail fast, don't want low level driver retries
- * bit 4 -- synchronous I/O hint: the block layer will unplug immediately
+ *      Insert a serialization point in the IO queue, forcing previously
+ *      submitted IO to be completed before this oen is issued.
+ * bit 3 -- synchronous I/O hint: the block layer will unplug immediately
+ *      Note that this does NOT indicate that the IO itself is sync, just
+ *      that the block layer will not postpone issue of this IO by plugging.
+ * bit 4 -- metadata request
+ *      Used for tracing to differentiate metadata and data IO. May also
+ *      get some preferential treatment in the IO scheduler
+ * bit 5 -- discard sectors
+ *      Informs the lower level device that this range of sectors is no longer
+ *      used by the file system and may thus be freed by the device. Used
+ *      for flash based storage.
+ * bit 6 -- fail fast device errors
+ * bit 7 -- fail fast transport errors
+ * bit 8 -- fail fast driver errors
+ *      Don't want driver retries for any fast fail whatever the reason.
  */
-#define BIO_RW          0
-#define BIO_RW_AHEAD    1
+#define BIO_RW          0       /* Must match RW in req flags (blkdev.h) */
+#define BIO_RW_AHEAD    1       /* Must match FAILFAST in req flags */
 #define BIO_RW_BARRIER  2
-#define BIO_RW_FAILFAST 3
-#define BIO_RW_SYNC     4
-#define BIO_RW_META     5
+#define BIO_RW_SYNC     3
+#define BIO_RW_META     4
+#define BIO_RW_DISCARD  5
+#define BIO_RW_FAILFAST_DEV             6
+#define BIO_RW_FAILFAST_TRANSPORT       7
+#define BIO_RW_FAILFAST_DRIVER          8
 
 /*
  * upper 16 bits of bi_rw define the io priority of this bio
@@ -182,17 +186,21 @@ struct bio {
 #define bio_sectors(bio)        ((bio)->bi_size >> 9)
 #define bio_barrier(bio)        ((bio)->bi_rw & (1 << BIO_RW_BARRIER))
 #define bio_sync(bio)           ((bio)->bi_rw & (1 << BIO_RW_SYNC))
-#define bio_failfast(bio)       ((bio)->bi_rw & (1 << BIO_RW_FAILFAST))
+#define bio_failfast_dev(bio)   ((bio)->bi_rw & (1 << BIO_RW_FAILFAST_DEV))
+#define bio_failfast_transport(bio)     \
+        ((bio)->bi_rw & (1 << BIO_RW_FAILFAST_TRANSPORT))
+#define bio_failfast_driver(bio) ((bio)->bi_rw & (1 << BIO_RW_FAILFAST_DRIVER))
 #define bio_rw_ahead(bio)       ((bio)->bi_rw & (1 << BIO_RW_AHEAD))
 #define bio_rw_meta(bio)        ((bio)->bi_rw & (1 << BIO_RW_META))
-#define bio_empty_barrier(bio)  (bio_barrier(bio) && !(bio)->bi_size)
+#define bio_discard(bio)        ((bio)->bi_rw & (1 << BIO_RW_DISCARD))
+#define bio_empty_barrier(bio)  (bio_barrier(bio) && !bio_has_data(bio) && !bio_discard(bio))
 
 static inline unsigned int bio_cur_sectors(struct bio *bio)
 {
         if (bio->bi_vcnt)
                 return bio_iovec(bio)->bv_len >> 9;
-
-        return 0;
+        else /* dataless requests such as discard */
+                return bio->bi_size >> 9;
 }
 
 static inline void *bio_data(struct bio *bio)
@@ -236,8 +244,6 @@ static inline void *bio_data(struct bio *bio)
         ((bvec_to_phys((vec1)) + (vec1)->bv_len) == bvec_to_phys((vec2)))
 #endif
 
-#define BIOVEC_VIRT_MERGEABLE(vec1, vec2)       \
-        ((((bvec_to_phys((vec1)) + (vec1)->bv_len) | bvec_to_phys((vec2))) & (BIO_VMERGE_BOUNDARY - 1)) == 0)
 #define __BIO_SEG_BOUNDARY(addr1, addr2, mask) \
         (((addr1) | (mask)) == (((addr2) - 1) | (mask)))
 #define BIOVEC_SEG_BOUNDARY(q, b1, b2) \
@@ -319,15 +325,14 @@ struct bio_pair {
         atomic_t                        cnt;
         int                             error;
 };
-extern struct bio_pair *bio_split(struct bio *bi, mempool_t *pool,
-                                  int first_sectors);
-extern mempool_t *bio_split_pool;
+extern struct bio_pair *bio_split(struct bio *bi, int first_sectors);
 extern void bio_pair_release(struct bio_pair *dbio);
 
 extern struct bio_set *bioset_create(int, int);
 extern void bioset_free(struct bio_set *);
 
 extern struct bio *bio_alloc(gfp_t, int);
+extern struct bio *bio_kmalloc(gfp_t, int);
 extern struct bio *bio_alloc_bioset(gfp_t, int, struct bio_set *);
 extern void bio_put(struct bio *);
 extern void bio_free(struct bio *, struct bio_set *);
@@ -335,7 +340,6 @@ extern void bio_free(struct bio *, struct bio_set *);
 extern void bio_endio(struct bio *, int);
 struct request_queue;
 extern int bio_phys_segments(struct request_queue *, struct bio *);
-extern int bio_hw_segments(struct request_queue *, struct bio *);
 
 extern void __bio_clone(struct bio *, struct bio *);
 extern struct bio *bio_clone(struct bio *, gfp_t);
@@ -346,12 +350,14 @@ extern int bio_add_page(struct bio *, struct page *, unsigned int,unsigned int);
 extern int bio_add_pc_page(struct request_queue *, struct bio *, struct page *,
                            unsigned int, unsigned int);
 extern int bio_get_nr_vecs(struct block_device *);
+extern sector_t bio_sector_offset(struct bio *, unsigned short, unsigned int);
 extern struct bio *bio_map_user(struct request_queue *, struct block_device *,
-                                unsigned long, unsigned int, int);
+                                unsigned long, unsigned int, int, gfp_t);
 struct sg_iovec;
+struct rq_map_data;
 extern struct bio *bio_map_user_iov(struct request_queue *,
                                     struct block_device *,
-                                    struct sg_iovec *, int, int);
+                                    struct sg_iovec *, int, int, gfp_t);
 extern void bio_unmap_user(struct bio *);
 extern struct bio *bio_map_kern(struct request_queue *, void *, unsigned int,
                                 gfp_t);
@@ -359,15 +365,25 @@ extern struct bio *bio_copy_kern(struct request_queue *, void *, unsigned int,
                                  gfp_t, int);
 extern void bio_set_pages_dirty(struct bio *bio);
 extern void bio_check_pages_dirty(struct bio *bio);
-extern struct bio *bio_copy_user(struct request_queue *, unsigned long, unsigned int, int);
-extern struct bio *bio_copy_user_iov(struct request_queue *, struct sg_iovec *,
-                                     int, int);
+extern struct bio *bio_copy_user(struct request_queue *, struct rq_map_data *,
+                                 unsigned long, unsigned int, int, gfp_t);
+extern struct bio *bio_copy_user_iov(struct request_queue *,
+                                     struct rq_map_data *, struct sg_iovec *,
+                                     int, int, gfp_t);
 extern int bio_uncopy_user(struct bio *);
 void zero_fill_bio(struct bio *bio);
 extern struct bio_vec *bvec_alloc_bs(gfp_t, int, unsigned long *, struct bio_set *);
 extern unsigned int bvec_nr_vecs(unsigned short idx);
 
 /*
+ * Allow queuer to specify a completion CPU for this bio
+ */
+static inline void bio_set_completion_cpu(struct bio *bio, unsigned int cpu)
+{
+        bio->bi_comp_cpu = cpu;
+}
+
+/*
  * bio_set is used to allow other portions of the IO system to
  * allocate their own private memory pools for bio and iovec structures.
  * These memory pools in turn all allocate from the bio_slab
@@ -445,6 +461,14 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx,
         __bio_kmap_irq((bio), (bio)->bi_idx, (flags))
 #define bio_kunmap_irq(buf,flags)       __bio_kunmap_irq(buf, flags)
 
+/*
+ * Check whether this bio carries any data or not. A NULL bio is allowed.
+ */
+static inline int bio_has_data(struct bio *bio)
+{
+        return bio && bio->bi_io_vec != NULL;
+}
+
 #if defined(CONFIG_BLK_DEV_INTEGRITY)
 
 #define bip_vec_idx(bip, idx)   (&(bip->bip_vec[(idx)]))
@@ -458,14 +482,7 @@ static inline char *__bio_kmap_irq(struct bio *bio, unsigned short idx,
 #define bip_for_each_vec(bvl, bip, i)                                   \
         __bip_for_each_vec(bvl, bip, i, (bip)->bip_idx)
 
-static inline int bio_integrity(struct bio *bio)
-{
-#if defined(CONFIG_BLK_DEV_INTEGRITY)
-        return bio->bi_integrity != NULL;
-#else
-        return 0;
-#endif
-}
+#define bio_integrity(bio) (bio->bi_integrity != NULL)
 
 extern struct bio_integrity_payload *bio_integrity_alloc_bioset(struct bio *, gfp_t, unsigned int, struct bio_set *);
 extern struct bio_integrity_payload *bio_integrity_alloc(struct bio *, gfp_t, unsigned int);
diff --git a/include/linux/blkdev.h b/include/linux/blkdev.h
index e61f22be4d0e..b4fe68fe3a57 100644
--- a/include/linux/blkdev.h
+++ b/include/linux/blkdev.h
@@ -16,7 +16,9 @@
 #include <linux/bio.h>
 #include <linux/module.h>
 #include <linux/stringify.h>
+#include <linux/gfp.h>
 #include <linux/bsg.h>
+#include <linux/smp.h>
 
 #include <asm/scatterlist.h>
 
@@ -54,7 +56,6 @@ enum rq_cmd_type_bits {
         REQ_TYPE_PM_SUSPEND,            /* suspend request */
         REQ_TYPE_PM_RESUME,             /* resume request */
         REQ_TYPE_PM_SHUTDOWN,           /* shutdown request */
-        REQ_TYPE_FLUSH,                 /* flush request */
         REQ_TYPE_SPECIAL,               /* driver defined type */
         REQ_TYPE_LINUX_BLOCK,           /* generic block layer message */
         /*
@@ -76,19 +77,20 @@ enum rq_cmd_type_bits {
  *
  */
 enum {
-        /*
-         * just examples for now
-         */
         REQ_LB_OP_EJECT = 0x40,         /* eject request */
-        REQ_LB_OP_FLUSH = 0x41,         /* flush device */
+        REQ_LB_OP_FLUSH = 0x41,         /* flush request */
+        REQ_LB_OP_DISCARD = 0x42,       /* discard sectors */
 };
 
 /*
- * request type modified bits. first three bits match BIO_RW* bits, important
+ * request type modified bits. first two bits match BIO_RW* bits, important
  */
 enum rq_flag_bits {
         __REQ_RW,               /* not set, read. set, write */
-        __REQ_FAILFAST,         /* no low level driver retries */
+        __REQ_FAILFAST_DEV,     /* no driver retries of device errors */
+        __REQ_FAILFAST_TRANSPORT, /* no driver retries of transport errors */
+        __REQ_FAILFAST_DRIVER,  /* no driver retries of driver errors */
+        __REQ_DISCARD,          /* request to discard sectors */
         __REQ_SORTED,           /* elevator knows about this request */
         __REQ_SOFTBARRIER,      /* may not be passed by ioscheduler */
         __REQ_HARDBARRIER,      /* may not be passed by drive either */
@@ -111,7 +113,10 @@ enum rq_flag_bits {
 };
 
 #define REQ_RW          (1 << __REQ_RW)
-#define REQ_FAILFAST    (1 << __REQ_FAILFAST)
+#define REQ_FAILFAST_DEV        (1 << __REQ_FAILFAST_DEV)
+#define REQ_FAILFAST_TRANSPORT  (1 << __REQ_FAILFAST_TRANSPORT)
+#define REQ_FAILFAST_DRIVER     (1 << __REQ_FAILFAST_DRIVER)
+#define REQ_DISCARD     (1 << __REQ_DISCARD)
 #define REQ_SORTED      (1 << __REQ_SORTED)
 #define REQ_SOFTBARRIER (1 << __REQ_SOFTBARRIER)
 #define REQ_HARDBARRIER (1 << __REQ_HARDBARRIER)
@@ -140,12 +145,14 @@ enum rq_flag_bits {
  */
 struct request {
         struct list_head queuelist;
-        struct list_head donelist;
+        struct call_single_data csd;
+        int cpu;
 
         struct request_queue *q;
 
         unsigned int cmd_flags;
         enum rq_cmd_type_bits cmd_type;
+        unsigned long atomic_flags;
 
         /* Maintain bio traversal state for part by part I/O submission.
          * hard_* are block layer internals, no driver should touch them!
@@ -190,13 +197,6 @@ struct request {
          */
         unsigned short nr_phys_segments;
 
-        /* Number of scatter-gather addr+len pairs after
-         * physical and DMA remapping hardware coalescing is performed.
-         * This is the number of scatter-gather entries the driver
-         * will actually have to deal with after DMA mapping is done.
-         */
-        unsigned short nr_hw_segments;
-
         unsigned short ioprio;
 
         void *special;
@@ -220,6 +220,8 @@ struct request {
         void *data;
         void *sense;
 
+        unsigned long deadline;
+        struct list_head timeout_list;
         unsigned int timeout;
         int retries;
 
@@ -233,6 +235,11 @@ struct request {
         struct request *next_rq;
 };
 
+static inline unsigned short req_get_ioprio(struct request *req)
+{
+        return req->ioprio;
+}
+
 /*
  * State information carried for REQ_TYPE_PM_SUSPEND and REQ_TYPE_PM_RESUME
  * requests. Some step values could eventually be made generic.
@@ -252,6 +259,7 @@ typedef void (request_fn_proc) (struct request_queue *q);
 typedef int (make_request_fn) (struct request_queue *q, struct bio *bio);
 typedef int (prep_rq_fn) (struct request_queue *, struct request *);
 typedef void (unplug_fn) (struct request_queue *);
+typedef int (prepare_discard_fn) (struct request_queue *, struct request *);
 
 struct bio_vec;
 struct bvec_merge_data {
@@ -265,6 +273,15 @@ typedef int (merge_bvec_fn) (struct request_queue *, struct bvec_merge_data *,
 typedef void (prepare_flush_fn) (struct request_queue *, struct request *);
 typedef void (softirq_done_fn)(struct request *);
 typedef int (dma_drain_needed_fn)(struct request *);
+typedef int (lld_busy_fn) (struct request_queue *q);
+
+enum blk_eh_timer_return {
+        BLK_EH_NOT_HANDLED,
+        BLK_EH_HANDLED,
+        BLK_EH_RESET_TIMER,
+};
+
+typedef enum blk_eh_timer_return (rq_timed_out_fn)(struct request *);
 
 enum blk_queue_state {
         Queue_down,
@@ -280,6 +297,15 @@ struct blk_queue_tag {
         atomic_t refcnt;                /* map can be shared */
 };
 
+#define BLK_SCSI_MAX_CMDS       (256)
+#define BLK_SCSI_CMD_PER_LONG   (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
+
+struct blk_cmd_filter {
+        unsigned long read_ok[BLK_SCSI_CMD_PER_LONG];
+        unsigned long write_ok[BLK_SCSI_CMD_PER_LONG];
+        struct kobject kobj;
+};
+
 struct request_queue
 {
         /*
@@ -298,10 +324,13 @@ struct request_queue
         make_request_fn         *make_request_fn;
         prep_rq_fn              *prep_rq_fn;
         unplug_fn               *unplug_fn;
+        prepare_discard_fn      *prepare_discard_fn;
         merge_bvec_fn           *merge_bvec_fn;
         prepare_flush_fn        *prepare_flush_fn;
         softirq_done_fn         *softirq_done_fn;
+        rq_timed_out_fn         *rq_timed_out_fn;
         dma_drain_needed_fn     *dma_drain_needed;
+        lld_busy_fn             *lld_busy_fn;
 
         /*
          * Dispatch queue sorting
@@ -376,6 +405,10 @@ struct request_queue
         unsigned int            nr_sorted;
         unsigned int            in_flight;
 
+        unsigned int            rq_timeout;
+        struct timer_list       timeout;
+        struct list_head        timeout_list;
+
         /*
          * sg stuff
          */
@@ -398,6 +431,7 @@ struct request_queue
 #if defined(CONFIG_BLK_DEV_BSG)
         struct bsg_class_device bsg_dev;
 #endif
+        struct blk_cmd_filter cmd_filter;
 };
 
 #define QUEUE_FLAG_CLUSTER      0       /* cluster several segments into 1 */
@@ -411,6 +445,10 @@ struct request_queue
 #define QUEUE_FLAG_ELVSWITCH    8       /* don't use elevator, just do FIFO */
 #define QUEUE_FLAG_BIDI         9       /* queue supports bidi requests */
 #define QUEUE_FLAG_NOMERGES    10       /* disable merge attempts */
+#define QUEUE_FLAG_SAME_COMP   11       /* force complete on same CPU */
+#define QUEUE_FLAG_FAIL_IO     12       /* fake timeout */
+#define QUEUE_FLAG_STACKABLE   13       /* supports request stacking */
+#define QUEUE_FLAG_NONROT      14       /* non-rotational device (SSD) */
 
 static inline int queue_is_locked(struct request_queue *q)
 {
@@ -516,26 +554,36 @@ enum {
 #define blk_queue_tagged(q)     test_bit(QUEUE_FLAG_QUEUED, &(q)->queue_flags)
 #define blk_queue_stopped(q)    test_bit(QUEUE_FLAG_STOPPED, &(q)->queue_flags)
 #define blk_queue_nomerges(q)   test_bit(QUEUE_FLAG_NOMERGES, &(q)->queue_flags)
+#define blk_queue_nonrot(q)     test_bit(QUEUE_FLAG_NONROT, &(q)->queue_flags)
 #define blk_queue_flushing(q)   ((q)->ordseq)
+#define blk_queue_stackable(q)  \
+        test_bit(QUEUE_FLAG_STACKABLE, &(q)->queue_flags)
 
 #define blk_fs_request(rq)      ((rq)->cmd_type == REQ_TYPE_FS)
 #define blk_pc_request(rq)      ((rq)->cmd_type == REQ_TYPE_BLOCK_PC)
 #define blk_special_request(rq) ((rq)->cmd_type == REQ_TYPE_SPECIAL)
 #define blk_sense_request(rq)   ((rq)->cmd_type == REQ_TYPE_SENSE)
 
-#define blk_noretry_request(rq) ((rq)->cmd_flags & REQ_FAILFAST)
+#define blk_failfast_dev(rq)    ((rq)->cmd_flags & REQ_FAILFAST_DEV)
+#define blk_failfast_transport(rq) ((rq)->cmd_flags & REQ_FAILFAST_TRANSPORT)
+#define blk_failfast_driver(rq) ((rq)->cmd_flags & REQ_FAILFAST_DRIVER)
+#define blk_noretry_request(rq) (blk_failfast_dev(rq) ||        \
+                                 blk_failfast_transport(rq) ||  \
+                                 blk_failfast_driver(rq))
 #define blk_rq_started(rq)      ((rq)->cmd_flags & REQ_STARTED)
 
-#define blk_account_rq(rq)      (blk_rq_started(rq) && blk_fs_request(rq))
+#define blk_account_rq(rq)      (blk_rq_started(rq) && (blk_fs_request(rq) || blk_discard_rq(rq))) 
 
 #define blk_pm_suspend_request(rq)      ((rq)->cmd_type == REQ_TYPE_PM_SUSPEND)
 #define blk_pm_resume_request(rq)       ((rq)->cmd_type == REQ_TYPE_PM_RESUME)
 #define blk_pm_request(rq)      \
         (blk_pm_suspend_request(rq) || blk_pm_resume_request(rq))
 
+#define blk_rq_cpu_valid(rq)    ((rq)->cpu != -1)
 #define blk_sorted_rq(rq)       ((rq)->cmd_flags & REQ_SORTED)
 #define blk_barrier_rq(rq)      ((rq)->cmd_flags & REQ_HARDBARRIER)
 #define blk_fua_rq(rq)          ((rq)->cmd_flags & REQ_FUA)
+#define blk_discard_rq(rq)      ((rq)->cmd_flags & REQ_DISCARD)
 #define blk_bidi_rq(rq)         ((rq)->next_rq != NULL)
 #define blk_empty_barrier(rq)   (blk_barrier_rq(rq) && blk_fs_request(rq) && !(rq)->hard_nr_sectors)
 /* rq->queuelist of dequeued request must be list_empty() */
@@ -582,7 +630,8 @@ static inline void blk_clear_queue_full(struct request_queue *q, int rw)
 #define RQ_NOMERGE_FLAGS        \
         (REQ_NOMERGE | REQ_STARTED | REQ_HARDBARRIER | REQ_SOFTBARRIER)
 #define rq_mergeable(rq)        \
-        (!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && blk_fs_request((rq)))
+        (!((rq)->cmd_flags & RQ_NOMERGE_FLAGS) && \
+         (blk_discard_rq(rq) || blk_fs_request((rq))))
 
 /*
  * q->prep_rq_fn return values
@@ -627,6 +676,12 @@ static inline void blk_queue_bounce(struct request_queue *q, struct bio **bio)
 }
 #endif /* CONFIG_MMU */
 
+struct rq_map_data {
+        struct page **pages;
+        int page_order;
+        int nr_entries;
+};
+
 struct req_iterator {
         int i;
         struct bio *bio;
@@ -654,6 +709,10 @@ extern void __blk_put_request(struct request_queue *, struct request *);
 extern struct request *blk_get_request(struct request_queue *, int, gfp_t);
 extern void blk_insert_request(struct request_queue *, struct request *, int, void *);
 extern void blk_requeue_request(struct request_queue *, struct request *);
+extern int blk_rq_check_limits(struct request_queue *q, struct request *rq);
+extern int blk_lld_busy(struct request_queue *q);
+extern int blk_insert_cloned_request(struct request_queue *q,
+                                     struct request *rq);
 extern void blk_plug_device(struct request_queue *);
 extern void blk_plug_device_unlocked(struct request_queue *);
 extern int blk_remove_plug(struct request_queue *);
@@ -695,11 +754,14 @@ extern void __blk_stop_queue(struct request_queue *q);
 extern void __blk_run_queue(struct request_queue *);
 extern void blk_run_queue(struct request_queue *);
 extern void blk_start_queueing(struct request_queue *);
-extern int blk_rq_map_user(struct request_queue *, struct request *, void __user *, unsigned long);
+extern int blk_rq_map_user(struct request_queue *, struct request *,
+                           struct rq_map_data *, void __user *, unsigned long,
+                           gfp_t);
 extern int blk_rq_unmap_user(struct bio *);
 extern int blk_rq_map_kern(struct request_queue *, struct request *, void *, unsigned int, gfp_t);
 extern int blk_rq_map_user_iov(struct request_queue *, struct request *,
-                               struct sg_iovec *, int, unsigned int);
+                               struct rq_map_data *, struct sg_iovec *, int,
+                               unsigned int, gfp_t);
 extern int blk_execute_rq(struct request_queue *, struct gendisk *,
                           struct request *, int);
 extern void blk_execute_rq_nowait(struct request_queue *, struct gendisk *,
@@ -740,12 +802,15 @@ extern int __blk_end_request(struct request *rq, int error,
 extern int blk_end_bidi_request(struct request *rq, int error,
                                 unsigned int nr_bytes, unsigned int bidi_bytes);
 extern void end_request(struct request *, int);
-extern void end_queued_request(struct request *, int);
-extern void end_dequeued_request(struct request *, int);
 extern int blk_end_request_callback(struct request *rq, int error,
                                 unsigned int nr_bytes,
                                 int (drv_callback)(struct request *));
 extern void blk_complete_request(struct request *);
+extern void __blk_complete_request(struct request *);
+extern void blk_abort_request(struct request *);
+extern void blk_abort_queue(struct request_queue *);
+extern void blk_update_request(struct request *rq, int error,
+                               unsigned int nr_bytes);
 
 /*
  * blk_end_request() takes bytes instead of sectors as a complete size.
@@ -780,12 +845,16 @@ extern void blk_queue_update_dma_pad(struct request_queue *, unsigned int);
 extern int blk_queue_dma_drain(struct request_queue *q,
                                dma_drain_needed_fn *dma_drain_needed,
                                void *buf, unsigned int size);
+extern void blk_queue_lld_busy(struct request_queue *q, lld_busy_fn *fn);
 extern void blk_queue_segment_boundary(struct request_queue *, unsigned long);
 extern void blk_queue_prep_rq(struct request_queue *, prep_rq_fn *pfn);
 extern void blk_queue_merge_bvec(struct request_queue *, merge_bvec_fn *);
 extern void blk_queue_dma_alignment(struct request_queue *, int);
 extern void blk_queue_update_dma_alignment(struct request_queue *, int);
 extern void blk_queue_softirq_done(struct request_queue *, softirq_done_fn *);
+extern void blk_queue_set_discard(struct request_queue *, prepare_discard_fn *);
+extern void blk_queue_rq_timed_out(struct request_queue *, rq_timed_out_fn *);
+extern void blk_queue_rq_timeout(struct request_queue *, unsigned int);
 extern struct backing_dev_info *blk_get_backing_dev_info(struct block_device *bdev);
 extern int blk_queue_ordered(struct request_queue *, unsigned, prepare_flush_fn *);
 extern int blk_do_ordered(struct request_queue *, struct request **);
@@ -796,7 +865,6 @@ extern void blk_ordered_complete_seq(struct request_queue *, unsigned, int);
 extern int blk_rq_map_sg(struct request_queue *, struct request *, struct scatterlist *);
 extern void blk_dump_rq_flags(struct request *, char *);
 extern void generic_unplug_device(struct request_queue *);
-extern void __generic_unplug_device(struct request_queue *);
 extern long nr_blockdev_pages(void);
 
 int blk_get_queue(struct request_queue *);
@@ -807,8 +875,6 @@ extern void blk_put_queue(struct request_queue *);
 /*
  * tag stuff
  */
-#define blk_queue_tag_depth(q)          ((q)->queue_tags->busy)
-#define blk_queue_tag_queue(q)          ((q)->queue_tags->busy < (q)->queue_tags->max_depth)
 #define blk_rq_tagged(rq)               ((rq)->cmd_flags & REQ_QUEUED)
 extern int blk_queue_start_tag(struct request_queue *, struct request *);
 extern struct request *blk_queue_find_tag(struct request_queue *, int);
@@ -829,15 +895,23 @@ static inline struct request *blk_map_queue_find_tag(struct blk_queue_tag *bqt,
 }
 
 extern int blkdev_issue_flush(struct block_device *, sector_t *);
+extern int blkdev_issue_discard(struct block_device *,
+                                sector_t sector, sector_t nr_sects, gfp_t);
+
+static inline int sb_issue_discard(struct super_block *sb,
+                                   sector_t block, sector_t nr_blocks)
+{
+        block <<= (sb->s_blocksize_bits - 9);
+        nr_blocks <<= (sb->s_blocksize_bits - 9);
+        return blkdev_issue_discard(sb->s_bdev, block, nr_blocks, GFP_KERNEL);
+}
 
 /*
 * command filter functions
 */
-extern int blk_verify_command(struct file *file, unsigned char *cmd);
-extern int blk_cmd_filter_verify_command(struct blk_scsi_cmd_filter *filter,
-                                         unsigned char *cmd, mode_t *f_mode);
-extern int blk_register_filter(struct gendisk *disk);
-extern void blk_unregister_filter(struct gendisk *disk);
+extern int blk_verify_command(struct blk_cmd_filter *filter,
+                              unsigned char *cmd, int has_write_perm);
+extern void blk_set_cmd_filter_defaults(struct blk_cmd_filter *filter);
 
 #define MAX_PHYS_SEGMENTS 128
 #define MAX_HW_SEGMENTS 128
@@ -868,6 +942,13 @@ static inline int queue_dma_alignment(struct request_queue *q)
         return q ? q->dma_alignment : 511;
 }
 
+static inline int blk_rq_aligned(struct request_queue *q, void *addr,
+                                 unsigned int len)
+{
+        unsigned int alignment = queue_dma_alignment(q) | q->dma_pad_mask;
+        return !((unsigned long)addr & alignment) && !(len & alignment);
+}
+
 /* assumes size > 256 */
 static inline unsigned int blksize_bits(unsigned int size)
 {
@@ -894,7 +975,7 @@ static inline void put_dev_sector(Sector p)
 }
 
 struct work_struct;
-int kblockd_schedule_work(struct work_struct *work);
+int kblockd_schedule_work(struct request_queue *q, struct work_struct *work);
 void kblockd_flush_work(struct work_struct *work);
 
 #define MODULE_ALIAS_BLOCKDEV(major,minor) \
@@ -939,49 +1020,19 @@ struct blk_integrity {
 
 extern int blk_integrity_register(struct gendisk *, struct blk_integrity *);
 extern void blk_integrity_unregister(struct gendisk *);
-extern int blk_integrity_compare(struct block_device *, struct block_device *);
+extern int blk_integrity_compare(struct gendisk *, struct gendisk *);
 extern int blk_rq_map_integrity_sg(struct request *, struct scatterlist *);
 extern int blk_rq_count_integrity_sg(struct request *);
 
-static inline unsigned short blk_integrity_tuple_size(struct blk_integrity *bi)
-{
-        if (bi)
-                return bi->tuple_size;
-
-        return 0;
-}
-
-static inline struct blk_integrity *bdev_get_integrity(struct block_device *bdev)
+static inline
+struct blk_integrity *bdev_get_integrity(struct block_device *bdev)
 {
         return bdev->bd_disk->integrity;
 }
 
-static inline unsigned int bdev_get_tag_size(struct block_device *bdev)
+static inline struct blk_integrity *blk_get_integrity(struct gendisk *disk)
 {
-        struct blk_integrity *bi = bdev_get_integrity(bdev);
-
-        if (bi)
-                return bi->tag_size;
-
-        return 0;
-}
-
-static inline int bdev_integrity_enabled(struct block_device *bdev, int rw)
-{
-        struct blk_integrity *bi = bdev_get_integrity(bdev);
-
-        if (bi == NULL)
-                return 0;
-
-        if (rw == READ && bi->verify_fn != NULL &&
-            (bi->flags & INTEGRITY_FLAG_READ))
-                return 1;
-
-        if (rw == WRITE && bi->generate_fn != NULL &&
-            (bi->flags & INTEGRITY_FLAG_WRITE))
-                return 1;
-
-        return 0;
+        return disk->integrity;
 }
 
 static inline int blk_integrity_rq(struct request *rq)
@@ -998,7 +1049,7 @@ static inline int blk_integrity_rq(struct request *rq)
 #define blk_rq_count_integrity_sg(a)            (0)
 #define blk_rq_map_integrity_sg(a, b)           (0)
 #define bdev_get_integrity(a)                   (0)
-#define bdev_get_tag_size(a)                    (0)
+#define blk_get_integrity(a)                    (0)
 #define blk_integrity_compare(a, b)             (0)
 #define blk_integrity_register(a, b)            (0)
 #define blk_integrity_unregister(a)             do { } while (0);
diff --git a/include/linux/blktrace_api.h b/include/linux/blktrace_api.h
index d084b8d227a5..bdf505d33e77 100644
--- a/include/linux/blktrace_api.h
+++ b/include/linux/blktrace_api.h
@@ -1,8 +1,10 @@
 #ifndef BLKTRACE_H
 #define BLKTRACE_H
 
+#ifdef __KERNEL__
 #include <linux/blkdev.h>
 #include <linux/relay.h>
+#endif
 
 /*
  * Trace categories
@@ -21,6 +23,8 @@ enum blktrace_cat {
         BLK_TC_NOTIFY   = 1 << 10,      /* special message */
         BLK_TC_AHEAD    = 1 << 11,      /* readahead */
         BLK_TC_META     = 1 << 12,      /* metadata */
+        BLK_TC_DISCARD  = 1 << 13,      /* discard requests */
+        BLK_TC_DRV_DATA = 1 << 14,      /* binary per-driver data */
 
         BLK_TC_END      = 1 << 15,      /* only 16-bits, reminder */
 };
@@ -47,6 +51,8 @@ enum blktrace_act {
         __BLK_TA_SPLIT,                 /* bio was split */
         __BLK_TA_BOUNCE,                /* bio was bounced */
         __BLK_TA_REMAP,                 /* bio was remapped */
+        __BLK_TA_ABORT,                 /* request aborted */
+        __BLK_TA_DRV_DATA,              /* driver-specific binary data */
 };
 
 /*
@@ -77,6 +83,8 @@ enum blktrace_notify {
 #define BLK_TA_SPLIT            (__BLK_TA_SPLIT)
 #define BLK_TA_BOUNCE           (__BLK_TA_BOUNCE)
 #define BLK_TA_REMAP            (__BLK_TA_REMAP | BLK_TC_ACT(BLK_TC_QUEUE))
+#define BLK_TA_ABORT            (__BLK_TA_ABORT | BLK_TC_ACT(BLK_TC_QUEUE))
+#define BLK_TA_DRV_DATA (__BLK_TA_DRV_DATA | BLK_TC_ACT(BLK_TC_DRV_DATA))
 
 #define BLK_TN_PROCESS          (__BLK_TN_PROCESS | BLK_TC_ACT(BLK_TC_NOTIFY))
 #define BLK_TN_TIMESTAMP        (__BLK_TN_TIMESTAMP | BLK_TC_ACT(BLK_TC_NOTIFY))
@@ -89,17 +97,17 @@ enum blktrace_notify {
  * The trace itself
  */
 struct blk_io_trace {
-        u32 magic;              /* MAGIC << 8 | version */
-        u32 sequence;           /* event number */
-        u64 time;               /* in microseconds */
-        u64 sector;             /* disk offset */
-        u32 bytes;              /* transfer length */
-        u32 action;             /* what happened */
-        u32 pid;                /* who did it */
-        u32 device;             /* device number */
-        u32 cpu;                /* on what cpu did it happen */
-        u16 error;              /* completion error */
-        u16 pdu_len;            /* length of data after this trace */
+        __u32 magic;            /* MAGIC << 8 | version */
+        __u32 sequence;         /* event number */
+        __u64 time;             /* in microseconds */
+        __u64 sector;           /* disk offset */
+        __u32 bytes;            /* transfer length */
+        __u32 action;           /* what happened */
+        __u32 pid;              /* who did it */
+        __u32 device;           /* device number */
+        __u32 cpu;              /* on what cpu did it happen */
+        __u16 error;            /* completion error */
+        __u16 pdu_len;          /* length of data after this trace */
 };
 
 /*
@@ -117,6 +125,23 @@ enum {
         Blktrace_stopped,
 };
 
+#define BLKTRACE_BDEV_SIZE      32
+
+/*
+ * User setup structure passed with BLKTRACESTART
+ */
+struct blk_user_trace_setup {
+        char name[BLKTRACE_BDEV_SIZE];  /* output */
+        __u16 act_mask;                 /* input */
+        __u32 buf_size;                 /* input */
+        __u32 buf_nr;                   /* input */
+        __u64 start_lba;
+        __u64 end_lba;
+        __u32 pid;
+};
+
+#ifdef __KERNEL__
+#if defined(CONFIG_BLK_DEV_IO_TRACE)
 struct blk_trace {
         int trace_state;
         struct rchan *rchan;
@@ -133,21 +158,6 @@ struct blk_trace {
         atomic_t dropped;
 };
 
-/*
- * User setup structure passed with BLKTRACESTART
- */
-struct blk_user_trace_setup {
-        char name[BDEVNAME_SIZE];       /* output */
-        u16 act_mask;                   /* input */
-        u32 buf_size;                   /* input */
-        u32 buf_nr;                     /* input */
-        u64 start_lba;
-        u64 end_lba;
-        u32 pid;
-};
-
-#ifdef __KERNEL__
-#if defined(CONFIG_BLK_DEV_IO_TRACE)
 extern int blk_trace_ioctl(struct block_device *, unsigned, char __user *);
 extern void blk_trace_shutdown(struct request_queue *);
 extern void __blk_add_trace(struct blk_trace *, sector_t, int, int, u32, int, int, void *);
@@ -195,6 +205,9 @@ static inline void blk_add_trace_rq(struct request_queue *q, struct request *rq,
         if (likely(!bt))
                 return;
 
+        if (blk_discard_rq(rq))
+                rw |= (1 << BIO_RW_DISCARD);
+
         if (blk_pc_request(rq)) {
                 what |= BLK_TC_ACT(BLK_TC_PC);
                 __blk_add_trace(bt, 0, rq->data_len, rw, what, rq->errors, sizeof(rq->cmd), rq->cmd);
@@ -307,6 +320,34 @@ static inline void blk_add_trace_remap(struct request_queue *q, struct bio *bio,
         __blk_add_trace(bt, from, bio->bi_size, bio->bi_rw, BLK_TA_REMAP, !bio_flagged(bio, BIO_UPTODATE), sizeof(r), &r);
 }
 
+/**
+ * blk_add_driver_data - Add binary message with driver-specific data
+ * @q:          queue the io is for
+ * @rq:         io request
+ * @data:       driver-specific data
+ * @len:        length of driver-specific data
+ *
+ * Description:
+ *     Some drivers might want to write driver-specific data per request.
+ *
+ **/
+static inline void blk_add_driver_data(struct request_queue *q,
+                                       struct request *rq,
+                                       void *data, size_t len)
+{
+        struct blk_trace *bt = q->blk_trace;
+
+        if (likely(!bt))
+                return;
+
+        if (blk_pc_request(rq))
+                __blk_add_trace(bt, 0, rq->data_len, 0, BLK_TA_DRV_DATA,
+                                rq->errors, len, data);
+        else
+                __blk_add_trace(bt, rq->hard_sector, rq->hard_nr_sectors << 9,
+                                0, BLK_TA_DRV_DATA, rq->errors, len, data);
+}
+
 extern int blk_trace_setup(struct request_queue *q, char *name, dev_t dev,
                            char __user *arg);
 extern int blk_trace_startstop(struct request_queue *q, int start);
@@ -320,6 +361,7 @@ extern int blk_trace_remove(struct request_queue *q);
 #define blk_add_trace_generic(q, rq, rw, what)  do { } while (0)
 #define blk_add_trace_pdu_int(q, what, bio, pdu)        do { } while (0)
 #define blk_add_trace_remap(q, bio, dev, f, t)  do {} while (0)
+#define blk_add_driver_data(q, rq, data, len)   do {} while (0)
 #define do_blk_trace_setup(q, name, dev, buts)  (-ENOTTY)
 #define blk_trace_setup(q, name, dev, arg)      (-ENOTTY)
 #define blk_trace_startstop(q, start)           (-ENOTTY)
diff --git a/include/linux/cgroup.h b/include/linux/cgroup.h
index c98dd7cb7076..30934e4bfaab 100644
--- a/include/linux/cgroup.h
+++ b/include/linux/cgroup.h
@@ -326,7 +326,8 @@ struct cgroup_subsys {
          */
         void (*mm_owner_changed)(struct cgroup_subsys *ss,
                                         struct cgroup *old,
-                                        struct cgroup *new);
+                                        struct cgroup *new,
+                                        struct task_struct *p);
         int subsys_id;
         int active;
         int disabled;
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 5ca8c6fddb56..778777316ea4 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -35,6 +35,8 @@ struct clk;
  * clk_get may return different clock producers depending on @dev.)
  *
  * Drivers must assume that the clock source is not enabled.
+ *
+ * clk_get should not be called from within interrupt context.
  */
 struct clk *clk_get(struct device *dev, const char *id);
 
@@ -76,6 +78,8 @@ unsigned long clk_get_rate(struct clk *clk);
  * Note: drivers must ensure that all clk_enable calls made on this
  * clock source are balanced by clk_disable calls prior to calling
  * this function.
+ *
+ * clk_put should not be called from within interrupt context.
  */
 void clk_put(struct clk *clk);
 
diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h
index c33b0dc28e4d..ed3a5d473e52 100644
--- a/include/linux/clockchips.h
+++ b/include/linux/clockchips.h
@@ -127,6 +127,8 @@ extern int clockevents_register_notifier(struct notifier_block *nb);
 extern int clockevents_program_event(struct clock_event_device *dev,
                                      ktime_t expires, ktime_t now);
 
+extern void clockevents_handle_noop(struct clock_event_device *dev);
+
 #ifdef CONFIG_GENERIC_CLOCKEVENTS
 extern void clockevents_notify(unsigned long reason, void *arg);
 #else
diff --git a/include/linux/cnt32_to_63.h b/include/linux/cnt32_to_63.h
new file mode 100644
index 000000000000..8c0f9505b48c
--- /dev/null
+++ b/include/linux/cnt32_to_63.h
@@ -0,0 +1,80 @@
+/*
+ *  Extend a 32-bit counter to 63 bits
+ *
+ *  Author:     Nicolas Pitre
+ *  Created:    December 3, 2006
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2
+ * as published by the Free Software Foundation.
+ */
+
+#ifndef __LINUX_CNT32_TO_63_H__
+#define __LINUX_CNT32_TO_63_H__
+
+#include <linux/compiler.h>
+#include <linux/types.h>
+#include <asm/byteorder.h>
+
+/* this is used only to give gcc a clue about good code generation */
+union cnt32_to_63 {
+        struct {
+#if defined(__LITTLE_ENDIAN)
+                u32 lo, hi;
+#elif defined(__BIG_ENDIAN)
+                u32 hi, lo;
+#endif
+        };
+        u64 val;
+};
+
+
+/**
+ * cnt32_to_63 - Expand a 32-bit counter to a 63-bit counter
+ * @cnt_lo: The low part of the counter
+ *
+ * Many hardware clock counters are only 32 bits wide and therefore have
+ * a relatively short period making wrap-arounds rather frequent.  This
+ * is a problem when implementing sched_clock() for example, where a 64-bit
+ * non-wrapping monotonic value is expected to be returned.
+ *
+ * To overcome that limitation, let's extend a 32-bit counter to 63 bits
+ * in a completely lock free fashion. Bits 0 to 31 of the clock are provided
+ * by the hardware while bits 32 to 62 are stored in memory.  The top bit in
+ * memory is used to synchronize with the hardware clock half-period.  When
+ * the top bit of both counters (hardware and in memory) differ then the
+ * memory is updated with a new value, incrementing it when the hardware
+ * counter wraps around.
+ *
+ * Because a word store in memory is atomic then the incremented value will
+ * always be in synch with the top bit indicating to any potential concurrent
+ * reader if the value in memory is up to date or not with regards to the
+ * needed increment.  And any race in updating the value in memory is harmless
+ * as the same value would simply be stored more than once.
+ *
+ * The only restriction for the algorithm to work properly is that this
+ * code must be executed at least once per each half period of the 32-bit
+ * counter to properly update the state bit in memory. This is usually not a
+ * problem in practice, but if it is then a kernel timer could be scheduled
+ * to manage for this code to be executed often enough.
+ *
+ * Note that the top bit (bit 63) in the returned value should be considered
+ * as garbage.  It is not cleared here because callers are likely to use a
+ * multiplier on the returned value which can get rid of the top bit
+ * implicitly by making the multiplier even, therefore saving on a runtime
+ * clear-bit instruction. Otherwise caller must remember to clear the top
+ * bit explicitly.
+ */
+#define cnt32_to_63(cnt_lo) \
+({ \
+        static volatile u32 __m_cnt_hi; \
+        union cnt32_to_63 __x; \
+        __x.hi = __m_cnt_hi; \
+        __x.lo = (cnt_lo); \
+        if (unlikely((s32)(__x.hi ^ __x.lo) < 0)) \
+                __m_cnt_hi = __x.hi = (__x.hi ^ 0x80000000) + (__x.hi >> 31); \
+        __x.val; \
+})
+
+#endif
diff --git a/include/linux/compat.h b/include/linux/compat.h
index cf8d11cad5ae..f061a1ea1b74 100644
--- a/include/linux/compat.h
+++ b/include/linux/compat.h
@@ -78,7 +78,6 @@ typedef struct {
         compat_sigset_word      sig[_COMPAT_NSIG_WORDS];
 } compat_sigset_t;
 
-extern int cp_compat_stat(struct kstat *, struct compat_stat __user *);
 extern int get_compat_timespec(struct timespec *, const struct compat_timespec __user *);
 extern int put_compat_timespec(const struct timespec *, struct compat_timespec __user *);
 
@@ -235,6 +234,11 @@ extern int get_compat_itimerspec(struct itimerspec *dst,
 extern int put_compat_itimerspec(struct compat_itimerspec __user *dst,
                                  const struct itimerspec *src);
 
+asmlinkage long compat_sys_gettimeofday(struct compat_timeval __user *tv,
+                struct timezone __user *tz);
+asmlinkage long compat_sys_settimeofday(struct compat_timeval __user *tv,
+                struct timezone __user *tz);
+
 asmlinkage long compat_sys_adjtimex(struct compat_timex __user *utp);
 
 extern int compat_printk(const char *fmt, ...);
diff --git a/include/linux/compiler.h b/include/linux/compiler.h
index c8bd2daf95ec..8322141ee480 100644
--- a/include/linux/compiler.h
+++ b/include/linux/compiler.h
@@ -190,7 +190,9 @@ extern void __chk_io_ptr(const volatile void __iomem *);
  * ACCESS_ONCE() in different C statements.
  *
  * This macro does absolutely -nothing- to prevent the CPU from reordering,
- * merging, or refetching absolutely anything at any time.
+ * merging, or refetching absolutely anything at any time.  Its main intended
+ * use is to mediate communication between process-level code and irq/NMI
+ * handlers, all running on the same CPU.
  */
 #define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))
 
diff --git a/include/linux/completion.h b/include/linux/completion.h
index 02ef8835999c..4a6b604ef7e4 100644
--- a/include/linux/completion.h
+++ b/include/linux/completion.h
@@ -10,6 +10,18 @@
 
 #include <linux/wait.h>
 
+/**
+ * struct completion - structure used to maintain state for a "completion"
+ *
+ * This is the opaque structure used to maintain the state for a "completion".
+ * Completions currently use a FIFO to queue threads that have to wait for
+ * the "completion" event.
+ *
+ * See also:  complete(), wait_for_completion() (and friends _timeout,
+ * _interruptible, _interruptible_timeout, and _killable), init_completion(),
+ * and macros DECLARE_COMPLETION(), DECLARE_COMPLETION_ONSTACK(), and
+ * INIT_COMPLETION().
+ */
 struct completion {
         unsigned int done;
         wait_queue_head_t wait;
@@ -21,6 +33,14 @@ struct completion {
 #define COMPLETION_INITIALIZER_ONSTACK(work) \
         ({ init_completion(&work); work; })
 
+/**
+ * DECLARE_COMPLETION: - declare and initialize a completion structure
+ * @work:  identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure. Generally used
+ * for static declarations. You should use the _ONSTACK variant for automatic
+ * variables.
+ */
 #define DECLARE_COMPLETION(work) \
         struct completion work = COMPLETION_INITIALIZER(work)
 
@@ -29,6 +49,13 @@ struct completion {
  * completions - so we use the _ONSTACK() variant for those that
  * are on the kernel stack:
  */
+/**
+ * DECLARE_COMPLETION_ONSTACK: - declare and initialize a completion structure
+ * @work:  identifier for the completion structure
+ *
+ * This macro declares and initializes a completion structure on the kernel
+ * stack.
+ */
 #ifdef CONFIG_LOCKDEP
 # define DECLARE_COMPLETION_ONSTACK(work) \
         struct completion work = COMPLETION_INITIALIZER_ONSTACK(work)
@@ -36,6 +63,13 @@ struct completion {
 # define DECLARE_COMPLETION_ONSTACK(work) DECLARE_COMPLETION(work)
 #endif
 
+/**
+ * init_completion: - Initialize a dynamically allocated completion
+ * @x:  completion structure that is to be initialized
+ *
+ * This inline function will initialize a dynamically created completion
+ * structure.
+ */
 static inline void init_completion(struct completion *x)
 {
         x->done = 0;
@@ -55,6 +89,13 @@ extern bool completion_done(struct completion *x);
 extern void complete(struct completion *);
 extern void complete_all(struct completion *);
 
+/**
+ * INIT_COMPLETION: - reinitialize a completion structure
+ * @x:  completion structure to be reinitialized
+ *
+ * This macro should be used to reinitialize a completion structure so it can
+ * be reused. This is especially important after complete_all() is used.
+ */
 #define INIT_COMPLETION(x)      ((x).done = 0)
 
 
diff --git a/include/linux/console_struct.h b/include/linux/console_struct.h
index b03f80a078be..d71f7c0f931b 100644
--- a/include/linux/console_struct.h
+++ b/include/linux/console_struct.h
@@ -53,7 +53,6 @@ struct vc_data {
         unsigned short  vc_hi_font_mask;        /* [#] Attribute set for upper 256 chars of font or 0 if not supported */
         struct console_font vc_font;            /* Current VC font set */
         unsigned short  vc_video_erase_char;    /* Background erase character */
-        unsigned short  vc_scrl_erase_char;     /* Erase character for scroll */
         /* VT terminal data */
         unsigned int    vc_state;               /* Escape sequence parser state */
         unsigned int    vc_npar,vc_par[NPAR];   /* Parameters of current escape sequence */
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index d7faf8808497..c2747ac2ae43 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -69,6 +69,7 @@ static inline void unregister_cpu_notifier(struct notifier_block *nb)
 #endif
 
 int cpu_up(unsigned int cpu);
+void notify_cpu_starting(unsigned int cpu);
 extern void cpu_hotplug_init(void);
 extern void cpu_maps_update_begin(void);
 extern void cpu_maps_update_done(void);
diff --git a/include/linux/cpufreq.h b/include/linux/cpufreq.h
index 6fd5668aa572..1ee608fd7b77 100644
--- a/include/linux/cpufreq.h
+++ b/include/linux/cpufreq.h
@@ -187,7 +187,8 @@ extern int __cpufreq_driver_target(struct cpufreq_policy *policy,
                                    unsigned int relation);
 
 
-extern int __cpufreq_driver_getavg(struct cpufreq_policy *policy);
+extern int __cpufreq_driver_getavg(struct cpufreq_policy *policy,
+                                   unsigned int cpu);
 
 int cpufreq_register_governor(struct cpufreq_governor *governor);
 void cpufreq_unregister_governor(struct cpufreq_governor *governor);
@@ -226,7 +227,9 @@ struct cpufreq_driver {
         unsigned int    (*get)  (unsigned int cpu);
 
         /* optional */
-        unsigned int (*getavg)  (unsigned int cpu);
+        unsigned int (*getavg)  (struct cpufreq_policy *policy,
+                                 unsigned int cpu);
+
         int     (*exit)         (struct cpufreq_policy *policy);
         int     (*suspend)      (struct cpufreq_policy *policy, pm_message_t pmsg);
         int     (*resume)       (struct cpufreq_policy *policy);
diff --git a/include/linux/cpuset.h b/include/linux/cpuset.h
index e8f450c499b0..2691926fb506 100644
--- a/include/linux/cpuset.h
+++ b/include/linux/cpuset.h
@@ -160,7 +160,7 @@ static inline int current_cpuset_is_being_rebound(void)
 
 static inline void rebuild_sched_domains(void)
 {
-        partition_sched_domains(0, NULL, NULL);
+        partition_sched_domains(1, NULL, NULL);
 }
 
 #endif /* !CONFIG_CPUSETS */
diff --git a/include/linux/crypto.h b/include/linux/crypto.h
index c43dc47fdf75..3d2317e4af2e 100644
--- a/include/linux/crypto.h
+++ b/include/linux/crypto.h
@@ -38,6 +38,7 @@
 #define CRYPTO_ALG_TYPE_DIGEST          0x00000008
 #define CRYPTO_ALG_TYPE_HASH            0x00000009
 #define CRYPTO_ALG_TYPE_AHASH           0x0000000a
+#define CRYPTO_ALG_TYPE_RNG             0x0000000c
 
 #define CRYPTO_ALG_TYPE_HASH_MASK       0x0000000e
 #define CRYPTO_ALG_TYPE_AHASH_MASK      0x0000000c
@@ -61,6 +62,14 @@
 #define CRYPTO_ALG_GENIV                0x00000200
 
 /*
+ * Set if the algorithm has passed automated run-time testing.  Note that
+ * if there is no run-time testing for a given algorithm it is considered
+ * to have passed.
+ */
+
+#define CRYPTO_ALG_TESTED               0x00000400
+
+/*
  * Transform masks and values (for crt_flags).
  */
 #define CRYPTO_TFM_REQ_MASK             0x000fff00
@@ -105,6 +114,7 @@ struct crypto_aead;
 struct crypto_blkcipher;
 struct crypto_hash;
 struct crypto_ahash;
+struct crypto_rng;
 struct crypto_tfm;
 struct crypto_type;
 struct aead_givcrypt_request;
@@ -290,6 +300,15 @@ struct compress_alg {
                               unsigned int slen, u8 *dst, unsigned int *dlen);
 };
 
+struct rng_alg {
+        int (*rng_make_random)(struct crypto_rng *tfm, u8 *rdata,
+                               unsigned int dlen);
+        int (*rng_reset)(struct crypto_rng *tfm, u8 *seed, unsigned int slen);
+
+        unsigned int seedsize;
+};
+
+
 #define cra_ablkcipher  cra_u.ablkcipher
 #define cra_aead        cra_u.aead
 #define cra_blkcipher   cra_u.blkcipher
@@ -298,6 +317,7 @@ struct compress_alg {
 #define cra_hash        cra_u.hash
 #define cra_ahash       cra_u.ahash
 #define cra_compress    cra_u.compress
+#define cra_rng         cra_u.rng
 
 struct crypto_alg {
         struct list_head cra_list;
@@ -325,6 +345,7 @@ struct crypto_alg {
                 struct hash_alg hash;
                 struct ahash_alg ahash;
                 struct compress_alg compress;
+                struct rng_alg rng;
         } cra_u;
 
         int (*cra_init)(struct crypto_tfm *tfm);
@@ -430,6 +451,12 @@ struct compress_tfm {
                               u8 *dst, unsigned int *dlen);
 };
 
+struct rng_tfm {
+        int (*rng_gen_random)(struct crypto_rng *tfm, u8 *rdata,
+                              unsigned int dlen);
+        int (*rng_reset)(struct crypto_rng *tfm, u8 *seed, unsigned int slen);
+};
+
 #define crt_ablkcipher  crt_u.ablkcipher
 #define crt_aead        crt_u.aead
 #define crt_blkcipher   crt_u.blkcipher
@@ -437,6 +464,7 @@ struct compress_tfm {
 #define crt_hash        crt_u.hash
 #define crt_ahash       crt_u.ahash
 #define crt_compress    crt_u.compress
+#define crt_rng         crt_u.rng
 
 struct crypto_tfm {
 
@@ -450,6 +478,7 @@ struct crypto_tfm {
                 struct hash_tfm hash;
                 struct ahash_tfm ahash;
                 struct compress_tfm compress;
+                struct rng_tfm rng;
         } crt_u;
         
         struct crypto_alg *__crt_alg;
@@ -481,6 +510,10 @@ struct crypto_hash {
         struct crypto_tfm base;
 };
 
+struct crypto_rng {
+        struct crypto_tfm base;
+};
+
 enum {
         CRYPTOA_UNSPEC,
         CRYPTOA_ALG,
@@ -515,6 +548,8 @@ struct crypto_tfm *crypto_alloc_tfm(const char *alg_name, u32 tfm_flags);
 struct crypto_tfm *crypto_alloc_base(const char *alg_name, u32 type, u32 mask);
 void crypto_free_tfm(struct crypto_tfm *tfm);
 
+int alg_test(const char *driver, const char *alg, u32 type, u32 mask);
+
 /*
  * Transform helpers which query the underlying algorithm.
  */
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 07aa198f19ed..efba1de629ac 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -230,7 +230,7 @@ extern void d_delete(struct dentry *);
 extern struct dentry * d_alloc(struct dentry *, const struct qstr *);
 extern struct dentry * d_alloc_anon(struct inode *);
 extern struct dentry * d_splice_alias(struct inode *, struct dentry *);
-extern struct dentry * d_add_ci(struct inode *, struct dentry *, struct qstr *);
+extern struct dentry * d_add_ci(struct dentry *, struct inode *, struct qstr *);
 extern void shrink_dcache_sb(struct super_block *);
 extern void shrink_dcache_parent(struct dentry *);
 extern void shrink_dcache_for_umount(struct super_block *);
diff --git a/include/linux/device-mapper.h b/include/linux/device-mapper.h
index a90222e3297d..08d783592b73 100644
--- a/include/linux/device-mapper.h
+++ b/include/linux/device-mapper.h
@@ -13,7 +13,6 @@
 
 struct dm_target;
 struct dm_table;
-struct dm_dev;
 struct mapped_device;
 struct bio_vec;
 
@@ -84,6 +83,12 @@ void dm_error(const char *message);
  */
 void dm_set_device_limits(struct dm_target *ti, struct block_device *bdev);
 
+struct dm_dev {
+        struct block_device *bdev;
+        int mode;
+        char name[16];
+};
+
 /*
  * Constructors should call these functions to ensure destination devices
  * are opened/closed correctly.
@@ -202,6 +207,7 @@ int dm_copy_name_and_uuid(struct mapped_device *md, char *name, char *uuid);
 struct gendisk *dm_disk(struct mapped_device *md);
 int dm_suspended(struct mapped_device *md);
 int dm_noflush_suspending(struct dm_target *ti);
+union map_info *dm_get_mapinfo(struct bio *bio);
 
 /*
  * Geometry functions.
@@ -232,6 +238,11 @@ int dm_table_add_target(struct dm_table *t, const char *type,
 int dm_table_complete(struct dm_table *t);
 
 /*
+ * Unplug all devices in a table.
+ */
+void dm_table_unplug_all(struct dm_table *t);
+
+/*
  * Table reference counting.
  */
 struct dm_table *dm_get_table(struct mapped_device *md);
@@ -256,6 +267,11 @@ void dm_table_event(struct dm_table *t);
  */
 int dm_swap_table(struct mapped_device *md, struct dm_table *t);
 
+/*
+ * A wrapper around vmalloc.
+ */
+void *dm_vcalloc(unsigned long nmemb, unsigned long elem_size);
+
 /*-----------------------------------------------------------------
  * Macros.
  *---------------------------------------------------------------*/
diff --git a/include/linux/device.h b/include/linux/device.h
index d24a47f80f9c..987f5912720a 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -90,6 +90,9 @@ int __must_check bus_for_each_drv(struct bus_type *bus,
                                   struct device_driver *start, void *data,
                                   int (*fn)(struct device_driver *, void *));
 
+void bus_sort_breadthfirst(struct bus_type *bus,
+                           int (*compare)(const struct device *a,
+                                          const struct device *b));
 /*
  * Bus notifiers: Get notified of addition/removal of devices
  * and binding/unbinding of drivers to devices.
@@ -199,6 +202,11 @@ struct class {
         struct class_private *p;
 };
 
+struct class_dev_iter {
+        struct klist_iter               ki;
+        const struct device_type        *type;
+};
+
 extern struct kobject *sysfs_dev_block_kobj;
 extern struct kobject *sysfs_dev_char_kobj;
 extern int __must_check __class_register(struct class *class,
@@ -213,6 +221,13 @@ extern void class_unregister(struct class *class);
         __class_register(class, &__key);        \
 })
 
+extern void class_dev_iter_init(struct class_dev_iter *iter,
+                                struct class *class,
+                                struct device *start,
+                                const struct device_type *type);
+extern struct device *class_dev_iter_next(struct class_dev_iter *iter);
+extern void class_dev_iter_exit(struct class_dev_iter *iter);
+
 extern int class_for_each_device(struct class *class, struct device *start,
                                  void *data,
                                  int (*fn)(struct device *dev, void *data));
@@ -358,6 +373,7 @@ struct device {
 
         struct kobject kobj;
         char    bus_id[BUS_ID_SIZE];    /* position on parent bus */
+        const char              *init_name; /* initial name of the device */
         struct device_type      *type;
         unsigned                uevent_suppress:1;
 
@@ -395,7 +411,7 @@ struct device {
         spinlock_t              devres_lock;
         struct list_head        devres_head;
 
-        struct list_head        node;
+        struct klist_node       knode_class;
         struct class            *class;
         dev_t                   devt;   /* dev_t, creates the sysfs "dev" */
         struct attribute_group  **groups;       /* optional groups */
@@ -406,7 +422,7 @@ struct device {
 /* Get the wakeup routines, which depend on struct device */
 #include <linux/pm_wakeup.h>
 
-static inline const char *dev_name(struct device *dev)
+static inline const char *dev_name(const struct device *dev)
 {
         /* will be changed into kobject_name(&dev->kobj) in the near future */
         return dev->bus_id;
@@ -489,7 +505,6 @@ extern struct device *device_create(struct class *cls, struct device *parent,
                                     dev_t devt, void *drvdata,
                                     const char *fmt, ...)
                                     __attribute__((format(printf, 5, 6)));
-#define device_create_drvdata   device_create
 extern void device_destroy(struct class *cls, dev_t devt);
 
 /*
@@ -518,7 +533,7 @@ extern void device_shutdown(void);
 extern void sysdev_shutdown(void);
 
 /* debugging and troubleshooting/diagnostic helpers. */
-extern const char *dev_driver_string(struct device *dev);
+extern const char *dev_driver_string(const struct device *dev);
 #define dev_printk(level, dev, format, arg...)  \
         printk(level "%s %s: " format , dev_driver_string(dev) , \
                dev_name(dev) , ## arg)
@@ -538,7 +553,11 @@ extern const char *dev_driver_string(struct device *dev);
 #define dev_info(dev, format, arg...)           \
         dev_printk(KERN_INFO , dev , format , ## arg)
 
-#ifdef DEBUG
+#if defined(CONFIG_DYNAMIC_PRINTK_DEBUG)
+#define dev_dbg(dev, format, ...) do { \
+        dynamic_dev_dbg(dev, format, ##__VA_ARGS__); \
+        } while (0)
+#elif defined(DEBUG)
 #define dev_dbg(dev, format, arg...)            \
         dev_printk(KERN_DEBUG , dev , format , ## arg)
 #else
@@ -554,6 +573,14 @@ extern const char *dev_driver_string(struct device *dev);
         ({ if (0) dev_printk(KERN_DEBUG, dev, format, ##arg); 0; })
 #endif
 
+/*
+ * dev_WARN() acts like dev_printk(), but with the key difference
+ * of using a WARN/WARN_ON to get the message out, including the
+ * file/line information and a backtrace.
+ */
+#define dev_WARN(dev, format, arg...) \
+        WARN(1, "Device: %s\n" format, dev_driver_string(dev), ## arg);
+
 /* Create alias, so I can be autoloaded. */
 #define MODULE_ALIAS_CHARDEV(major,minor) \
         MODULE_ALIAS("char-major-" __stringify(major) "-" __stringify(minor))
diff --git a/include/linux/devpts_fs.h b/include/linux/devpts_fs.h
index 154769cad3f3..5ce0e5fd712e 100644
--- a/include/linux/devpts_fs.h
+++ b/include/linux/devpts_fs.h
@@ -17,20 +17,31 @@
 
 #ifdef CONFIG_UNIX98_PTYS
 
-int devpts_new_index(void);
-void devpts_kill_index(int idx);
-int devpts_pty_new(struct tty_struct *tty);      /* mknod in devpts */
-struct tty_struct *devpts_get_tty(int number);   /* get tty structure */
-void devpts_pty_kill(int number);                /* unlink */
+int devpts_new_index(struct inode *ptmx_inode);
+void devpts_kill_index(struct inode *ptmx_inode, int idx);
+/* mknod in devpts */
+int devpts_pty_new(struct inode *ptmx_inode, struct tty_struct *tty);
+/* get tty structure */
+struct tty_struct *devpts_get_tty(struct inode *pts_inode, int number);
+/* unlink */
+void devpts_pty_kill(struct tty_struct *tty);
 
 #else
 
 /* Dummy stubs in the no-pty case */
-static inline int devpts_new_index(void) { return -EINVAL; }
-static inline void devpts_kill_index(int idx) { }
-static inline int devpts_pty_new(struct tty_struct *tty) { return -EINVAL; }
-static inline struct tty_struct *devpts_get_tty(int number) { return NULL; }
-static inline void devpts_pty_kill(int number) { }
+static inline int devpts_new_index(struct inode *ptmx_inode) { return -EINVAL; }
+static inline void devpts_kill_index(struct inode *ptmx_inode, int idx) { }
+static inline int devpts_pty_new(struct inode *ptmx_inode,
+                                struct tty_struct *tty)
+{
+        return -EINVAL;
+}
+static inline struct tty_struct *devpts_get_tty(struct inode *pts_inode,
+                int number)
+{
+        return NULL;
+}
+static inline void devpts_pty_kill(struct tty_struct *tty) { }
 
 #endif
 
diff --git a/include/linux/dlm.h b/include/linux/dlm.h
index 203a025e30e5..b9cd38603fd8 100644
--- a/include/linux/dlm.h
+++ b/include/linux/dlm.h
@@ -2,7 +2,7 @@
 *******************************************************************************
 **
 **  Copyright (C) Sistina Software, Inc.  1997-2003  All rights reserved.
-**  Copyright (C) 2004-2007 Red Hat, Inc.  All rights reserved.
+**  Copyright (C) 2004-2008 Red Hat, Inc.  All rights reserved.
 **
 **  This copyrighted material is made available to anyone wishing to use,
 **  modify, copy, or redistribute it subject to the terms and conditions
@@ -65,9 +65,12 @@ struct dlm_lksb {
         char *   sb_lvbptr;
 };
 
+/* dlm_new_lockspace() flags */
+
 #define DLM_LSFL_NODIR          0x00000001
 #define DLM_LSFL_TIMEWARN       0x00000002
 #define DLM_LSFL_FS             0x00000004
+#define DLM_LSFL_NEWEXCL        0x00000008
 
 #ifdef __KERNEL__
 
diff --git a/include/linux/dlm_device.h b/include/linux/dlm_device.h
index c6034508fed9..3060783c4191 100644
--- a/include/linux/dlm_device.h
+++ b/include/linux/dlm_device.h
@@ -26,7 +26,7 @@
 /* Version of the device interface */
 #define DLM_DEVICE_VERSION_MAJOR 6
 #define DLM_DEVICE_VERSION_MINOR 0
-#define DLM_DEVICE_VERSION_PATCH 0
+#define DLM_DEVICE_VERSION_PATCH 1
 
 /* struct passed to the lock write */
 struct dlm_lock_params {
diff --git a/include/linux/dma-mapping.h b/include/linux/dma-mapping.h
index 952e0f857ac9..ba9114ec5d3a 100644
--- a/include/linux/dma-mapping.h
+++ b/include/linux/dma-mapping.h
@@ -48,6 +48,11 @@ static inline int is_device_dma_capable(struct device *dev)
         return dev->dma_mask != NULL && *dev->dma_mask != DMA_MASK_NONE;
 }
 
+static inline int is_buffer_dma_capable(u64 mask, dma_addr_t addr, size_t size)
+{
+        return addr + size <= mask;
+}
+
 #ifdef CONFIG_HAS_DMA
 #include <asm/dma-mapping.h>
 #else
@@ -58,6 +63,13 @@ static inline int is_device_dma_capable(struct device *dev)
 #define dma_sync_single         dma_sync_single_for_cpu
 #define dma_sync_sg             dma_sync_sg_for_cpu
 
+static inline u64 dma_get_mask(struct device *dev)
+{
+        if (dev && dev->dma_mask && *dev->dma_mask)
+                return *dev->dma_mask;
+        return DMA_32BIT_MASK;
+}
+
 extern u64 dma_get_required_mask(struct device *dev);
 
 static inline unsigned int dma_get_max_seg_size(struct device *dev)
diff --git a/include/linux/dma_remapping.h b/include/linux/dma_remapping.h
new file mode 100644
index 000000000000..bff5c65f81dc
--- /dev/null
+++ b/include/linux/dma_remapping.h
@@ -0,0 +1,157 @@
+#ifndef _DMA_REMAPPING_H
+#define _DMA_REMAPPING_H
+
+/*
+ * We need a fixed PAGE_SIZE of 4K irrespective of
+ * arch PAGE_SIZE for IOMMU page tables.
+ */
+#define PAGE_SHIFT_4K           (12)
+#define PAGE_SIZE_4K            (1UL << PAGE_SHIFT_4K)
+#define PAGE_MASK_4K            (((u64)-1) << PAGE_SHIFT_4K)
+#define PAGE_ALIGN_4K(addr)     (((addr) + PAGE_SIZE_4K - 1) & PAGE_MASK_4K)
+
+#define IOVA_PFN(addr)          ((addr) >> PAGE_SHIFT_4K)
+#define DMA_32BIT_PFN           IOVA_PFN(DMA_32BIT_MASK)
+#define DMA_64BIT_PFN           IOVA_PFN(DMA_64BIT_MASK)
+
+
+/*
+ * 0: Present
+ * 1-11: Reserved
+ * 12-63: Context Ptr (12 - (haw-1))
+ * 64-127: Reserved
+ */
+struct root_entry {
+        u64     val;
+        u64     rsvd1;
+};
+#define ROOT_ENTRY_NR (PAGE_SIZE_4K/sizeof(struct root_entry))
+static inline bool root_present(struct root_entry *root)
+{
+        return (root->val & 1);
+}
+static inline void set_root_present(struct root_entry *root)
+{
+        root->val |= 1;
+}
+static inline void set_root_value(struct root_entry *root, unsigned long value)
+{
+        root->val |= value & PAGE_MASK_4K;
+}
+
+struct context_entry;
+static inline struct context_entry *
+get_context_addr_from_root(struct root_entry *root)
+{
+        return (struct context_entry *)
+                (root_present(root)?phys_to_virt(
+                root->val & PAGE_MASK_4K):
+                NULL);
+}
+
+/*
+ * low 64 bits:
+ * 0: present
+ * 1: fault processing disable
+ * 2-3: translation type
+ * 12-63: address space root
+ * high 64 bits:
+ * 0-2: address width
+ * 3-6: aval
+ * 8-23: domain id
+ */
+struct context_entry {
+        u64 lo;
+        u64 hi;
+};
+#define context_present(c) ((c).lo & 1)
+#define context_fault_disable(c) (((c).lo >> 1) & 1)
+#define context_translation_type(c) (((c).lo >> 2) & 3)
+#define context_address_root(c) ((c).lo & PAGE_MASK_4K)
+#define context_address_width(c) ((c).hi &  7)
+#define context_domain_id(c) (((c).hi >> 8) & ((1 << 16) - 1))
+
+#define context_set_present(c) do {(c).lo |= 1;} while (0)
+#define context_set_fault_enable(c) \
+        do {(c).lo &= (((u64)-1) << 2) | 1;} while (0)
+#define context_set_translation_type(c, val) \
+        do { \
+                (c).lo &= (((u64)-1) << 4) | 3; \
+                (c).lo |= ((val) & 3) << 2; \
+        } while (0)
+#define CONTEXT_TT_MULTI_LEVEL 0
+#define context_set_address_root(c, val) \
+        do {(c).lo |= (val) & PAGE_MASK_4K;} while (0)
+#define context_set_address_width(c, val) do {(c).hi |= (val) & 7;} while (0)
+#define context_set_domain_id(c, val) \
+        do {(c).hi |= ((val) & ((1 << 16) - 1)) << 8;} while (0)
+#define context_clear_entry(c) do {(c).lo = 0; (c).hi = 0;} while (0)
+
+/*
+ * 0: readable
+ * 1: writable
+ * 2-6: reserved
+ * 7: super page
+ * 8-11: available
+ * 12-63: Host physcial address
+ */
+struct dma_pte {
+        u64 val;
+};
+#define dma_clear_pte(p)        do {(p).val = 0;} while (0)
+
+#define DMA_PTE_READ (1)
+#define DMA_PTE_WRITE (2)
+
+#define dma_set_pte_readable(p) do {(p).val |= DMA_PTE_READ;} while (0)
+#define dma_set_pte_writable(p) do {(p).val |= DMA_PTE_WRITE;} while (0)
+#define dma_set_pte_prot(p, prot) \
+                do {(p).val = ((p).val & ~3) | ((prot) & 3); } while (0)
+#define dma_pte_addr(p) ((p).val & PAGE_MASK_4K)
+#define dma_set_pte_addr(p, addr) do {\
+                (p).val |= ((addr) & PAGE_MASK_4K); } while (0)
+#define dma_pte_present(p) (((p).val & 3) != 0)
+
+struct intel_iommu;
+
+struct dmar_domain {
+        int     id;                     /* domain id */
+        struct intel_iommu *iommu;      /* back pointer to owning iommu */
+
+        struct list_head devices;       /* all devices' list */
+        struct iova_domain iovad;       /* iova's that belong to this domain */
+
+        struct dma_pte  *pgd;           /* virtual address */
+        spinlock_t      mapping_lock;   /* page table lock */
+        int             gaw;            /* max guest address width */
+
+        /* adjusted guest address width, 0 is level 2 30-bit */
+        int             agaw;
+
+#define DOMAIN_FLAG_MULTIPLE_DEVICES 1
+        int             flags;
+};
+
+/* PCI domain-device relationship */
+struct device_domain_info {
+        struct list_head link;  /* link to domain siblings */
+        struct list_head global; /* link to global list */
+        u8 bus;                 /* PCI bus numer */
+        u8 devfn;               /* PCI devfn number */
+        struct pci_dev *dev; /* it's NULL for PCIE-to-PCI bridge */
+        struct dmar_domain *domain; /* pointer to domain */
+};
+
+extern int init_dmars(void);
+extern void free_dmar_iommu(struct intel_iommu *iommu);
+
+extern int dmar_disabled;
+
+#ifndef CONFIG_DMAR_GFX_WA
+static inline void iommu_prepare_gfx_mapping(void)
+{
+        return;
+}
+#endif /* !CONFIG_DMAR_GFX_WA */
+
+#endif
diff --git a/include/linux/dmar.h b/include/linux/dmar.h
index 56c73b847551..c360c558e59e 100644
--- a/include/linux/dmar.h
+++ b/include/linux/dmar.h
@@ -25,9 +25,99 @@
 #include <linux/types.h>
 #include <linux/msi.h>
 
-#ifdef CONFIG_DMAR
+#if defined(CONFIG_DMAR) || defined(CONFIG_INTR_REMAP)
 struct intel_iommu;
 
+struct dmar_drhd_unit {
+        struct list_head list;          /* list of drhd units   */
+        struct  acpi_dmar_header *hdr;  /* ACPI header          */
+        u64     reg_base_addr;          /* register base address*/
+        struct  pci_dev **devices;      /* target device array  */
+        int     devices_cnt;            /* target device count  */
+        u8      ignored:1;              /* ignore drhd          */
+        u8      include_all:1;
+        struct intel_iommu *iommu;
+};
+
+extern struct list_head dmar_drhd_units;
+
+#define for_each_drhd_unit(drhd) \
+        list_for_each_entry(drhd, &dmar_drhd_units, list)
+
+extern int dmar_table_init(void);
+extern int early_dmar_detect(void);
+extern int dmar_dev_scope_init(void);
+
+/* Intel IOMMU detection */
+extern void detect_intel_iommu(void);
+
+
+extern int parse_ioapics_under_ir(void);
+extern int alloc_iommu(struct dmar_drhd_unit *);
+#else
+static inline void detect_intel_iommu(void)
+{
+        return;
+}
+
+static inline int dmar_table_init(void)
+{
+        return -ENODEV;
+}
+#endif /* !CONFIG_DMAR && !CONFIG_INTR_REMAP */
+
+#ifdef CONFIG_INTR_REMAP
+extern int intr_remapping_enabled;
+extern int enable_intr_remapping(int);
+
+struct irte {
+        union {
+                struct {
+                        __u64   present         : 1,
+                                fpd             : 1,
+                                dst_mode        : 1,
+                                redir_hint      : 1,
+                                trigger_mode    : 1,
+                                dlvry_mode      : 3,
+                                avail           : 4,
+                                __reserved_1    : 4,
+                                vector          : 8,
+                                __reserved_2    : 8,
+                                dest_id         : 32;
+                };
+                __u64 low;
+        };
+
+        union {
+                struct {
+                        __u64   sid             : 16,
+                                sq              : 2,
+                                svt             : 2,
+                                __reserved_3    : 44;
+                };
+                __u64 high;
+        };
+};
+extern int get_irte(int irq, struct irte *entry);
+extern int modify_irte(int irq, struct irte *irte_modified);
+extern int alloc_irte(struct intel_iommu *iommu, int irq, u16 count);
+extern int set_irte_irq(int irq, struct intel_iommu *iommu, u16 index,
+                        u16 sub_handle);
+extern int map_irq_to_irte_handle(int irq, u16 *sub_handle);
+extern int clear_irte_irq(int irq, struct intel_iommu *iommu, u16 index);
+extern int flush_irte(int irq);
+extern int free_irte(int irq);
+
+extern int irq_remapped(int irq);
+extern struct intel_iommu *map_dev_to_ir(struct pci_dev *dev);
+extern struct intel_iommu *map_ioapic_to_ir(int apic);
+#else
+#define irq_remapped(irq)               (0)
+#define enable_intr_remapping(mode)     (-1)
+#define intr_remapping_enabled          (0)
+#endif
+
+#ifdef CONFIG_DMAR
 extern const char *dmar_get_fault_reason(u8 fault_reason);
 
 /* Can't use the common MSI interrupt functions
@@ -40,47 +130,30 @@ extern void dmar_msi_write(int irq, struct msi_msg *msg);
 extern int dmar_set_interrupt(struct intel_iommu *iommu);
 extern int arch_setup_dmar_msi(unsigned int irq);
 
-/* Intel IOMMU detection and initialization functions */
-extern void detect_intel_iommu(void);
-extern int intel_iommu_init(void);
-
-extern int dmar_table_init(void);
-extern int early_dmar_detect(void);
-
-extern struct list_head dmar_drhd_units;
+extern int iommu_detected, no_iommu;
 extern struct list_head dmar_rmrr_units;
-
-struct dmar_drhd_unit {
-        struct list_head list;          /* list of drhd units   */
-        u64     reg_base_addr;          /* register base address*/
-        struct  pci_dev **devices;      /* target device array  */
-        int     devices_cnt;            /* target device count  */
-        u8      ignored:1;              /* ignore drhd          */
-        u8      include_all:1;
-        struct intel_iommu *iommu;
-};
-
 struct dmar_rmrr_unit {
         struct list_head list;          /* list of rmrr units   */
+        struct acpi_dmar_header *hdr;   /* ACPI header          */
         u64     base_address;           /* reserved base address*/
         u64     end_address;            /* reserved end address */
         struct pci_dev **devices;       /* target devices */
         int     devices_cnt;            /* target device count */
 };
 
-#define for_each_drhd_unit(drhd) \
-        list_for_each_entry(drhd, &dmar_drhd_units, list)
 #define for_each_rmrr_units(rmrr) \
         list_for_each_entry(rmrr, &dmar_rmrr_units, list)
+/* Intel DMAR  initialization functions */
+extern int intel_iommu_init(void);
+extern int dmar_disabled;
 #else
-static inline void detect_intel_iommu(void)
-{
-        return;
-}
 static inline int intel_iommu_init(void)
 {
+#ifdef CONFIG_INTR_REMAP
+        return dmar_dev_scope_init();
+#else
         return -ENODEV;
+#endif
 }
-
 #endif /* !CONFIG_DMAR */
 #endif /* __DMAR_H__ */
diff --git a/include/linux/dmi.h b/include/linux/dmi.h
index 2a063b64133f..e5084eb5943a 100644
--- a/include/linux/dmi.h
+++ b/include/linux/dmi.h
@@ -2,29 +2,9 @@
 #define __DMI_H__
 
 #include <linux/list.h>
+#include <linux/mod_devicetable.h>
 
-enum dmi_field {
-        DMI_NONE,
-        DMI_BIOS_VENDOR,
-        DMI_BIOS_VERSION,
-        DMI_BIOS_DATE,
-        DMI_SYS_VENDOR,
-        DMI_PRODUCT_NAME,
-        DMI_PRODUCT_VERSION,
-        DMI_PRODUCT_SERIAL,
-        DMI_PRODUCT_UUID,
-        DMI_BOARD_VENDOR,
-        DMI_BOARD_NAME,
-        DMI_BOARD_VERSION,
-        DMI_BOARD_SERIAL,
-        DMI_BOARD_ASSET_TAG,
-        DMI_CHASSIS_VENDOR,
-        DMI_CHASSIS_TYPE,
-        DMI_CHASSIS_VERSION,
-        DMI_CHASSIS_SERIAL,
-        DMI_CHASSIS_ASSET_TAG,
-        DMI_STRING_MAX,
-};
+/* enum dmi_field is in mod_devicetable.h */
 
 enum dmi_device_type {
         DMI_DEV_TYPE_ANY = 0,
@@ -48,23 +28,6 @@ struct dmi_header {
         u16 handle;
 };
 
-/*
- *      DMI callbacks for problem boards
- */
-struct dmi_strmatch {
-        u8 slot;
-        char *substr;
-};
-
-struct dmi_system_id {
-        int (*callback)(const struct dmi_system_id *);
-        const char *ident;
-        struct dmi_strmatch matches[4];
-        void *driver_data;
-};
-
-#define DMI_MATCH(a, b) { a, b }
-
 struct dmi_device {
         struct list_head list;
         int type;
diff --git a/include/linux/ds1286.h b/include/linux/ds1286.h
index d8989860e4ce..45ea0aa0aeb9 100644
--- a/include/linux/ds1286.h
+++ b/include/linux/ds1286.h
@@ -8,8 +8,6 @@
 #ifndef __LINUX_DS1286_H
 #define __LINUX_DS1286_H
 
-#include <asm/ds1286.h>
-
 /**********************************************************************
  * register summary
  **********************************************************************/
diff --git a/include/linux/dvb/frontend.h b/include/linux/dvb/frontend.h
index c8cbd90ba375..79a8ed8e6a7d 100644
--- a/include/linux/dvb/frontend.h
+++ b/include/linux/dvb/frontend.h
@@ -62,6 +62,7 @@ typedef enum fe_caps {
         FE_CAN_HIERARCHY_AUTO           = 0x100000,
         FE_CAN_8VSB                     = 0x200000,
         FE_CAN_16VSB                    = 0x400000,
+        FE_HAS_EXTENDED_CAPS            = 0x800000,   // We need more bitspace for newer APIs, indicate this.
         FE_NEEDS_BENDING                = 0x20000000, // not supported anymore, don't use (frontend requires frequency bending)
         FE_CAN_RECOVER                  = 0x40000000, // frontend can recover from a cable unplug automatically
         FE_CAN_MUTE_TS                  = 0x80000000  // frontend can stop spurious TS data output
@@ -147,7 +148,9 @@ typedef enum fe_code_rate {
         FEC_6_7,
         FEC_7_8,
         FEC_8_9,
-        FEC_AUTO
+        FEC_AUTO,
+        FEC_3_5,
+        FEC_9_10,
 } fe_code_rate_t;
 
 
@@ -160,7 +163,11 @@ typedef enum fe_modulation {
         QAM_256,
         QAM_AUTO,
         VSB_8,
-        VSB_16
+        VSB_16,
+        PSK_8,
+        APSK_16,
+        APSK_32,
+        DQPSK,
 } fe_modulation_t;
 
 typedef enum fe_transmit_mode {
@@ -239,6 +246,107 @@ struct dvb_frontend_event {
         struct dvb_frontend_parameters parameters;
 };
 
+/* S2API Commands */
+#define DTV_UNDEFINED           0
+#define DTV_TUNE                1
+#define DTV_CLEAR               2
+#define DTV_FREQUENCY           3
+#define DTV_MODULATION          4
+#define DTV_BANDWIDTH_HZ        5
+#define DTV_INVERSION           6
+#define DTV_DISEQC_MASTER       7
+#define DTV_SYMBOL_RATE         8
+#define DTV_INNER_FEC           9
+#define DTV_VOLTAGE             10
+#define DTV_TONE                11
+#define DTV_PILOT               12
+#define DTV_ROLLOFF             13
+#define DTV_DISEQC_SLAVE_REPLY  14
+
+/* Basic enumeration set for querying unlimited capabilities */
+#define DTV_FE_CAPABILITY_COUNT 15
+#define DTV_FE_CAPABILITY       16
+#define DTV_DELIVERY_SYSTEM     17
+
+#define DTV_API_VERSION                         35
+#define DTV_API_VERSION                         35
+#define DTV_CODE_RATE_HP                        36
+#define DTV_CODE_RATE_LP                        37
+#define DTV_GUARD_INTERVAL                      38
+#define DTV_TRANSMISSION_MODE                   39
+#define DTV_HIERARCHY                           40
+
+#define DTV_MAX_COMMAND                         DTV_HIERARCHY
+
+typedef enum fe_pilot {
+        PILOT_ON,
+        PILOT_OFF,
+        PILOT_AUTO,
+} fe_pilot_t;
+
+typedef enum fe_rolloff {
+        ROLLOFF_35, /* Implied value in DVB-S, default for DVB-S2 */
+        ROLLOFF_20,
+        ROLLOFF_25,
+        ROLLOFF_AUTO,
+} fe_rolloff_t;
+
+typedef enum fe_delivery_system {
+        SYS_UNDEFINED,
+        SYS_DVBC_ANNEX_AC,
+        SYS_DVBC_ANNEX_B,
+        SYS_DVBT,
+        SYS_DSS,
+        SYS_DVBS,
+        SYS_DVBS2,
+        SYS_DVBH,
+        SYS_ISDBT,
+        SYS_ISDBS,
+        SYS_ISDBC,
+        SYS_ATSC,
+        SYS_ATSCMH,
+        SYS_DMBTH,
+        SYS_CMMB,
+        SYS_DAB,
+} fe_delivery_system_t;
+
+struct dtv_cmds_h {
+        char    *name;          /* A display name for debugging purposes */
+
+        __u32   cmd;            /* A unique ID */
+
+        /* Flags */
+        __u32   set:1;          /* Either a set or get property */
+        __u32   buffer:1;       /* Does this property use the buffer? */
+        __u32   reserved:30;    /* Align */
+};
+
+struct dtv_property {
+        __u32 cmd;
+        __u32 reserved[3];
+        union {
+                __u32 data;
+                struct {
+                        __u8 data[32];
+                        __u32 len;
+                        __u32 reserved1[3];
+                        void *reserved2;
+                } buffer;
+        } u;
+        int result;
+} __attribute__ ((packed));
+
+/* num of properties cannot exceed DTV_IOCTL_MAX_MSGS per ioctl */
+#define DTV_IOCTL_MAX_MSGS 64
+
+struct dtv_properties {
+        __u32 num;
+        struct dtv_property *props;
+};
+
+#define FE_SET_PROPERTY            _IOW('o', 82, struct dtv_properties)
+#define FE_GET_PROPERTY            _IOR('o', 83, struct dtv_properties)
+
 
 /**
  * When set, this flag will disable any zigzagging or other "normal" tuning
diff --git a/include/linux/dvb/version.h b/include/linux/dvb/version.h
index 126e0c26cb09..25b823b81734 100644
--- a/include/linux/dvb/version.h
+++ b/include/linux/dvb/version.h
@@ -23,7 +23,7 @@
 #ifndef _DVBVERSION_H_
 #define _DVBVERSION_H_
 
-#define DVB_API_VERSION 3
-#define DVB_API_VERSION_MINOR 2
+#define DVB_API_VERSION 5
+#define DVB_API_VERSION_MINOR 0
 
 #endif /*_DVBVERSION_H_*/
diff --git a/include/linux/dynamic_printk.h b/include/linux/dynamic_printk.h
new file mode 100644
index 000000000000..2d528d009074
--- /dev/null
+++ b/include/linux/dynamic_printk.h
@@ -0,0 +1,93 @@
+#ifndef _DYNAMIC_PRINTK_H
+#define _DYNAMIC_PRINTK_H
+
+#define DYNAMIC_DEBUG_HASH_BITS 6
+#define DEBUG_HASH_TABLE_SIZE (1 << DYNAMIC_DEBUG_HASH_BITS)
+
+#define TYPE_BOOLEAN 1
+
+#define DYNAMIC_ENABLED_ALL 0
+#define DYNAMIC_ENABLED_NONE 1
+#define DYNAMIC_ENABLED_SOME 2
+
+extern int dynamic_enabled;
+
+/* dynamic_printk_enabled, and dynamic_printk_enabled2 are bitmasks in which
+ * bit n is set to 1 if any modname hashes into the bucket n, 0 otherwise. They
+ * use independent hash functions, to reduce the chance of false positives.
+ */
+extern long long dynamic_printk_enabled;
+extern long long dynamic_printk_enabled2;
+
+struct mod_debug {
+        char *modname;
+        char *logical_modname;
+        char *flag_names;
+        int type;
+        int hash;
+        int hash2;
+} __attribute__((aligned(8)));
+
+int register_dynamic_debug_module(char *mod_name, int type, char *share_name,
+                                        char *flags, int hash, int hash2);
+
+#if defined(CONFIG_DYNAMIC_PRINTK_DEBUG)
+extern int unregister_dynamic_debug_module(char *mod_name);
+extern int __dynamic_dbg_enabled_helper(char *modname, int type,
+                                        int value, int hash);
+
+#define __dynamic_dbg_enabled(module, type, value, level, hash)  ({          \
+        int __ret = 0;                                                       \
+        if (unlikely((dynamic_printk_enabled & (1LL << DEBUG_HASH)) &&       \
+                        (dynamic_printk_enabled2 & (1LL << DEBUG_HASH2))))   \
+                        __ret = __dynamic_dbg_enabled_helper(module, type,   \
+                                                                value, hash);\
+        __ret; })
+
+#define dynamic_pr_debug(fmt, ...) do {                                     \
+        static char mod_name[]                                              \
+        __attribute__((section("__verbose_strings")))                       \
+         = KBUILD_MODNAME;                                                  \
+        static struct mod_debug descriptor                                  \
+        __used                                                              \
+        __attribute__((section("__verbose"), aligned(8))) =                 \
+        { mod_name, mod_name, NULL, TYPE_BOOLEAN, DEBUG_HASH, DEBUG_HASH2 };\
+        if (__dynamic_dbg_enabled(KBUILD_MODNAME, TYPE_BOOLEAN,             \
+                                                0, 0, DEBUG_HASH))          \
+                printk(KERN_DEBUG KBUILD_MODNAME ":" fmt,                   \
+                                ##__VA_ARGS__);                             \
+        } while (0)
+
+#define dynamic_dev_dbg(dev, format, ...) do {                              \
+        static char mod_name[]                                              \
+        __attribute__((section("__verbose_strings")))                       \
+         = KBUILD_MODNAME;                                                  \
+        static struct mod_debug descriptor                                  \
+        __used                                                              \
+        __attribute__((section("__verbose"), aligned(8))) =                 \
+        { mod_name, mod_name, NULL, TYPE_BOOLEAN, DEBUG_HASH, DEBUG_HASH2 };\
+        if (__dynamic_dbg_enabled(KBUILD_MODNAME, TYPE_BOOLEAN,             \
+                                                0, 0, DEBUG_HASH))          \
+                        dev_printk(KERN_DEBUG, dev,                         \
+                                        KBUILD_MODNAME ": " format,         \
+                                        ##__VA_ARGS__);                     \
+        } while (0)
+
+#else
+
+static inline int unregister_dynamic_debug_module(const char *mod_name)
+{
+        return 0;
+}
+static inline int __dynamic_dbg_enabled_helper(char *modname, int type,
+                                                int value, int hash)
+{
+        return 0;
+}
+
+#define __dynamic_dbg_enabled(module, type, value, level, hash)  ({ 0; })
+#define dynamic_pr_debug(fmt, ...)  do { } while (0)
+#define dynamic_dev_dbg(dev, format, ...)  do { } while (0)
+#endif
+
+#endif
diff --git a/include/linux/elevator.h b/include/linux/elevator.h
index 639624b55fbe..92f6f634e3e6 100644
--- a/include/linux/elevator.h
+++ b/include/linux/elevator.h
@@ -112,6 +112,7 @@ extern struct request *elv_latter_request(struct request_queue *, struct request
 extern int elv_register_queue(struct request_queue *q);
 extern void elv_unregister_queue(struct request_queue *q);
 extern int elv_may_queue(struct request_queue *, int);
+extern void elv_abort_queue(struct request_queue *);
 extern void elv_completed_request(struct request_queue *, struct request *);
 extern int elv_set_request(struct request_queue *, struct request *, gfp_t);
 extern void elv_put_request(struct request_queue *, struct request *);
@@ -173,15 +174,15 @@ enum {
 #define rb_entry_rq(node)       rb_entry((node), struct request, rb_node)
 
 /*
- * Hack to reuse the donelist list_head as the fifo time holder while
+ * Hack to reuse the csd.list list_head as the fifo time holder while
  * the request is in the io scheduler. Saves an unsigned long in rq.
  */
-#define rq_fifo_time(rq)        ((unsigned long) (rq)->donelist.next)
-#define rq_set_fifo_time(rq,exp)        ((rq)->donelist.next = (void *) (exp))
+#define rq_fifo_time(rq)        ((unsigned long) (rq)->csd.list.next)
+#define rq_set_fifo_time(rq,exp)        ((rq)->csd.list.next = (void *) (exp))
 #define rq_entry_fifo(ptr)      list_entry((ptr), struct request, queuelist)
 #define rq_fifo_clear(rq)       do {            \
         list_del_init(&(rq)->queuelist);        \
-        INIT_LIST_HEAD(&(rq)->donelist);        \
+        INIT_LIST_HEAD(&(rq)->csd.list);        \
         } while (0)
 
 /*
diff --git a/include/linux/elf.h b/include/linux/elf.h
index edc3dac3f02f..0b61ca41a044 100644
--- a/include/linux/elf.h
+++ b/include/linux/elf.h
@@ -360,6 +360,7 @@ typedef struct elf64_shdr {
 #define NT_PPC_SPE      0x101           /* PowerPC SPE/EVR registers */
 #define NT_PPC_VSX      0x102           /* PowerPC VSX registers */
 #define NT_386_TLS      0x200           /* i386 TLS slots (struct user_desc) */
+#define NT_386_IOPERM   0x201           /* x86 io permission bitmap (1=deny) */
 
 
 /* Note header in a PT_NOTE section */
diff --git a/include/linux/ext2_fs.h b/include/linux/ext2_fs.h
index 2efe7b863cff..78c775a83f7c 100644
--- a/include/linux/ext2_fs.h
+++ b/include/linux/ext2_fs.h
@@ -47,7 +47,7 @@
 #ifdef EXT2FS_DEBUG
 #       define ext2_debug(f, a...)      { \
                                         printk ("EXT2-fs DEBUG (%s, %d): %s:", \
-                                                __FILE__, __LINE__, __FUNCTION__); \
+                                                __FILE__, __LINE__, __func__); \
                                         printk (f, ## a); \
                                         }
 #else
diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h
index 80171ee89a22..159d9b476cd7 100644
--- a/include/linux/ext3_fs.h
+++ b/include/linux/ext3_fs.h
@@ -43,7 +43,7 @@
 #define ext3_debug(f, a...)                                             \
         do {                                                            \
                 printk (KERN_DEBUG "EXT3-fs DEBUG (%s, %d): %s:",       \
-                        __FILE__, __LINE__, __FUNCTION__);              \
+                        __FILE__, __LINE__, __func__);          \
                 printk (KERN_DEBUG f, ## a);                            \
         } while (0)
 #else
@@ -837,6 +837,8 @@ extern void ext3_truncate (struct inode *);
 extern void ext3_set_inode_flags(struct inode *);
 extern void ext3_get_inode_flags(struct ext3_inode_info *);
 extern void ext3_set_aops(struct inode *inode);
+extern int ext3_fiemap(struct inode *inode, struct fiemap_extent_info *fieinfo,
+                       u64 start, u64 len);
 
 /* ioctl.c */
 extern int ext3_ioctl (struct inode *, struct file *, unsigned int,
@@ -869,7 +871,7 @@ extern void ext3_update_dynamic_rev (struct super_block *sb);
 #define ext3_std_error(sb, errno)                               \
 do {                                                            \
         if ((errno))                                            \
-                __ext3_std_error((sb), __FUNCTION__, (errno));  \
+                __ext3_std_error((sb), __func__, (errno));      \
 } while (0)
 
 /*
diff --git a/include/linux/ext3_jbd.h b/include/linux/ext3_jbd.h
index 8c43b13a02fe..cf82d519be40 100644
--- a/include/linux/ext3_jbd.h
+++ b/include/linux/ext3_jbd.h
@@ -137,17 +137,17 @@ int __ext3_journal_dirty_metadata(const char *where,
                                 handle_t *handle, struct buffer_head *bh);
 
 #define ext3_journal_get_undo_access(handle, bh) \
-        __ext3_journal_get_undo_access(__FUNCTION__, (handle), (bh))
+        __ext3_journal_get_undo_access(__func__, (handle), (bh))
 #define ext3_journal_get_write_access(handle, bh) \
-        __ext3_journal_get_write_access(__FUNCTION__, (handle), (bh))
+        __ext3_journal_get_write_access(__func__, (handle), (bh))
 #define ext3_journal_revoke(handle, blocknr, bh) \
-        __ext3_journal_revoke(__FUNCTION__, (handle), (blocknr), (bh))
+        __ext3_journal_revoke(__func__, (handle), (blocknr), (bh))
 #define ext3_journal_get_create_access(handle, bh) \
-        __ext3_journal_get_create_access(__FUNCTION__, (handle), (bh))
+        __ext3_journal_get_create_access(__func__, (handle), (bh))
 #define ext3_journal_dirty_metadata(handle, bh) \
-        __ext3_journal_dirty_metadata(__FUNCTION__, (handle), (bh))
+        __ext3_journal_dirty_metadata(__func__, (handle), (bh))
 #define ext3_journal_forget(handle, bh) \
-        __ext3_journal_forget(__FUNCTION__, (handle), (bh))
+        __ext3_journal_forget(__func__, (handle), (bh))
 
 int ext3_journal_dirty_data(handle_t *handle, struct buffer_head *bh);
 
@@ -160,7 +160,7 @@ static inline handle_t *ext3_journal_start(struct inode *inode, int nblocks)
 }
 
 #define ext3_journal_stop(handle) \
-        __ext3_journal_stop(__FUNCTION__, (handle))
+        __ext3_journal_stop(__func__, (handle))
 
 static inline handle_t *ext3_journal_current_handle(void)
 {
diff --git a/include/linux/fd.h b/include/linux/fd.h
index b6bd41d2b460..f5d194af07a8 100644
--- a/include/linux/fd.h
+++ b/include/linux/fd.h
@@ -15,10 +15,16 @@ struct floppy_struct {
                         sect,           /* sectors per track */
                         head,           /* nr of heads */
                         track,          /* nr of tracks */
-                        stretch;        /* !=0 means double track steps */
+                        stretch;        /* bit 0 !=0 means double track steps */
+                                        /* bit 1 != 0 means swap sides */
+                                        /* bits 2..9 give the first sector */
+                                        /*  number (the LSB is flipped) */
 #define FD_STRETCH 1
 #define FD_SWAPSIDES 2
 #define FD_ZEROBASED 4
+#define FD_SECTBASEMASK 0x3FC
+#define FD_MKSECTBASE(s) (((s) ^ 1) << 2)
+#define FD_SECTBASE(floppy) ((((floppy)->stretch & FD_SECTBASEMASK) >> 2) ^ 1)
 
         unsigned char   gap,            /* gap1 size */
 
diff --git a/include/linux/fiemap.h b/include/linux/fiemap.h
new file mode 100644
index 000000000000..671decbd2aeb
--- /dev/null
+++ b/include/linux/fiemap.h
@@ -0,0 +1,64 @@
+/*
+ * FS_IOC_FIEMAP ioctl infrastructure.
+ *
+ * Some portions copyright (C) 2007 Cluster File Systems, Inc
+ *
+ * Authors: Mark Fasheh <mfasheh@suse.com>
+ *          Kalpak Shah <kalpak.shah@sun.com>
+ *          Andreas Dilger <adilger@sun.com>
+ */
+
+#ifndef _LINUX_FIEMAP_H
+#define _LINUX_FIEMAP_H
+
+struct fiemap_extent {
+        __u64 fe_logical;  /* logical offset in bytes for the start of
+                            * the extent from the beginning of the file */
+        __u64 fe_physical; /* physical offset in bytes for the start
+                            * of the extent from the beginning of the disk */
+        __u64 fe_length;   /* length in bytes for this extent */
+        __u64 fe_reserved64[2];
+        __u32 fe_flags;    /* FIEMAP_EXTENT_* flags for this extent */
+        __u32 fe_reserved[3];
+};
+
+struct fiemap {
+        __u64 fm_start;         /* logical offset (inclusive) at
+                                 * which to start mapping (in) */
+        __u64 fm_length;        /* logical length of mapping which
+                                 * userspace wants (in) */
+        __u32 fm_flags;         /* FIEMAP_FLAG_* flags for request (in/out) */
+        __u32 fm_mapped_extents;/* number of extents that were mapped (out) */
+        __u32 fm_extent_count;  /* size of fm_extents array (in) */
+        __u32 fm_reserved;
+        struct fiemap_extent fm_extents[0]; /* array of mapped extents (out) */
+};
+
+#define FIEMAP_MAX_OFFSET       (~0ULL)
+
+#define FIEMAP_FLAG_SYNC        0x00000001 /* sync file data before map */
+#define FIEMAP_FLAG_XATTR       0x00000002 /* map extended attribute tree */
+
+#define FIEMAP_FLAGS_COMPAT     (FIEMAP_FLAG_SYNC | FIEMAP_FLAG_XATTR)
+
+#define FIEMAP_EXTENT_LAST              0x00000001 /* Last extent in file. */
+#define FIEMAP_EXTENT_UNKNOWN           0x00000002 /* Data location unknown. */
+#define FIEMAP_EXTENT_DELALLOC          0x00000004 /* Location still pending.
+                                                    * Sets EXTENT_UNKNOWN. */
+#define FIEMAP_EXTENT_ENCODED           0x00000008 /* Data can not be read
+                                                    * while fs is unmounted */
+#define FIEMAP_EXTENT_DATA_ENCRYPTED    0x00000080 /* Data is encrypted by fs.
+                                                    * Sets EXTENT_NO_BYPASS. */
+#define FIEMAP_EXTENT_NOT_ALIGNED       0x00000100 /* Extent offsets may not be
+                                                    * block aligned. */
+#define FIEMAP_EXTENT_DATA_INLINE       0x00000200 /* Data mixed with metadata.
+                                                    * Sets EXTENT_NOT_ALIGNED.*/
+#define FIEMAP_EXTENT_DATA_TAIL         0x00000400 /* Multiple files in block.
+                                                    * Sets EXTENT_NOT_ALIGNED.*/
+#define FIEMAP_EXTENT_UNWRITTEN         0x00000800 /* Space allocated, but
+                                                    * no data (i.e. zero). */
+#define FIEMAP_EXTENT_MERGED            0x00001000 /* File does not natively
+                                                    * support extents. Result
+                                                    * merged for efficiency. */
+
+#endif /* _LINUX_FIEMAP_H */
diff --git a/include/linux/firewire-cdev.h b/include/linux/firewire-cdev.h
index 0f0e271f97fa..4d078e99c017 100644
--- a/include/linux/firewire-cdev.h
+++ b/include/linux/firewire-cdev.h
@@ -154,8 +154,13 @@ struct fw_cdev_event_iso_interrupt {
  * @request:       Valid if @common.type == %FW_CDEV_EVENT_REQUEST
  * @iso_interrupt: Valid if @common.type == %FW_CDEV_EVENT_ISO_INTERRUPT
  *
- * Convenience union for userspace use.  Events could be read(2) into a char
- * buffer and then cast to this union for further processing.
+ * Convenience union for userspace use.  Events could be read(2) into an
+ * appropriately aligned char buffer and then cast to this union for further
+ * processing.  Note that for a request, response or iso_interrupt event,
+ * the data[] or header[] may make the size of the full event larger than
+ * sizeof(union fw_cdev_event).  Also note that if you attempt to read(2)
+ * an event into a buffer that is not large enough for it, the data that does
+ * not fit will be discarded so that the next read(2) will return a new event.
  */
 union fw_cdev_event {
         struct fw_cdev_event_common common;
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 580b513668fe..a6a625be13fc 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -86,7 +86,9 @@ extern int dir_notify_enable;
 #define READ_META       (READ | (1 << BIO_RW_META))
 #define WRITE_SYNC      (WRITE | (1 << BIO_RW_SYNC))
 #define SWRITE_SYNC     (SWRITE | (1 << BIO_RW_SYNC))
-#define WRITE_BARRIER   ((1 << BIO_RW) | (1 << BIO_RW_BARRIER))
+#define WRITE_BARRIER   (WRITE | (1 << BIO_RW_BARRIER))
+#define DISCARD_NOBARRIER (1 << BIO_RW_DISCARD)
+#define DISCARD_BARRIER ((1 << BIO_RW_DISCARD) | (1 << BIO_RW_BARRIER))
 
 #define SEL_IN          1
 #define SEL_OUT         2
@@ -222,6 +224,7 @@ extern int dir_notify_enable;
 #define BLKTRACESTART _IO(0x12,116)
 #define BLKTRACESTOP _IO(0x12,117)
 #define BLKTRACETEARDOWN _IO(0x12,118)
+#define BLKDISCARD _IO(0x12,119)
 
 #define BMAP_IOCTL 1            /* obsolete - kept for compatibility */
 #define FIBMAP     _IO(0x00,1)  /* bmap access */
@@ -231,6 +234,7 @@ extern int dir_notify_enable;
 #define FS_IOC_SETFLAGS                 _IOW('f', 2, long)
 #define FS_IOC_GETVERSION               _IOR('v', 1, long)
 #define FS_IOC_SETVERSION               _IOW('v', 2, long)
+#define FS_IOC_FIEMAP                   _IOWR('f', 11, struct fiemap)
 #define FS_IOC32_GETFLAGS               _IOR('f', 1, int)
 #define FS_IOC32_SETFLAGS               _IOW('f', 2, int)
 #define FS_IOC32_GETVERSION             _IOR('v', 1, int)
@@ -291,6 +295,7 @@ extern int dir_notify_enable;
 #include <linux/mutex.h>
 #include <linux/capability.h>
 #include <linux/semaphore.h>
+#include <linux/fiemap.h>
 
 #include <asm/atomic.h>
 #include <asm/byteorder.h>
@@ -942,6 +947,14 @@ struct lock_manager_operations {
         int (*fl_change)(struct file_lock **, int);
 };
 
+struct lock_manager {
+        struct list_head list;
+};
+
+void locks_start_grace(struct lock_manager *);
+void locks_end_grace(struct lock_manager *);
+int locks_in_grace(void);
+
 /* that will die - we need it for nfs_lock_info */
 #include <linux/nfs_fs_i.h>
 
@@ -983,6 +996,13 @@ struct file_lock {
 
 #include <linux/fcntl.h>
 
+extern void send_sigio(struct fown_struct *fown, int fd, int band);
+
+/* fs/sync.c */
+extern int do_sync_mapping_range(struct address_space *mapping, loff_t offset,
+                        loff_t endbyte, unsigned int flags);
+
+#ifdef CONFIG_FILE_LOCKING
 extern int fcntl_getlk(struct file *, struct flock __user *);
 extern int fcntl_setlk(unsigned int, struct file *, unsigned int,
                         struct flock __user *);
@@ -993,14 +1013,9 @@ extern int fcntl_setlk64(unsigned int, struct file *, unsigned int,
                         struct flock64 __user *);
 #endif
 
-extern void send_sigio(struct fown_struct *fown, int fd, int band);
 extern int fcntl_setlease(unsigned int fd, struct file *filp, long arg);
 extern int fcntl_getlease(struct file *filp);
 
-/* fs/sync.c */
-extern int do_sync_mapping_range(struct address_space *mapping, loff_t offset,
-                        loff_t endbyte, unsigned int flags);
-
 /* fs/locks.c */
 extern void locks_init_lock(struct file_lock *);
 extern void locks_copy_lock(struct file_lock *, struct file_lock *);
@@ -1023,6 +1038,37 @@ extern int lease_modify(struct file_lock **, int);
 extern int lock_may_read(struct inode *, loff_t start, unsigned long count);
 extern int lock_may_write(struct inode *, loff_t start, unsigned long count);
 extern struct seq_operations locks_seq_operations;
+#else /* !CONFIG_FILE_LOCKING */
+#define fcntl_getlk(a, b) ({ -EINVAL; })
+#define fcntl_setlk(a, b, c, d) ({ -EACCES; })
+#if BITS_PER_LONG == 32
+#define fcntl_getlk64(a, b) ({ -EINVAL; })
+#define fcntl_setlk64(a, b, c, d) ({ -EACCES; })
+#endif
+#define fcntl_setlease(a, b, c) ({ 0; })
+#define fcntl_getlease(a) ({ 0; })
+#define locks_init_lock(a) ({ })
+#define __locks_copy_lock(a, b) ({ })
+#define locks_copy_lock(a, b) ({ })
+#define locks_remove_posix(a, b) ({ })
+#define locks_remove_flock(a) ({ })
+#define posix_test_lock(a, b) ({ 0; })
+#define posix_lock_file(a, b, c) ({ -ENOLCK; })
+#define posix_lock_file_wait(a, b) ({ -ENOLCK; })
+#define posix_unblock_lock(a, b) (-ENOENT)
+#define vfs_test_lock(a, b) ({ 0; })
+#define vfs_lock_file(a, b, c, d) (-ENOLCK)
+#define vfs_cancel_lock(a, b) ({ 0; })
+#define flock_lock_file_wait(a, b) ({ -ENOLCK; })
+#define __break_lease(a, b) ({ 0; })
+#define lease_get_mtime(a, b) ({ })
+#define generic_setlease(a, b, c) ({ -EINVAL; })
+#define vfs_setlease(a, b, c) ({ -EINVAL; })
+#define lease_modify(a, b) ({ -EINVAL; })
+#define lock_may_read(a, b, c) ({ 1; })
+#define lock_may_write(a, b, c) ({ 1; })
+#endif /* !CONFIG_FILE_LOCKING */
+
 
 struct fasync_struct {
         int     magic;
@@ -1179,6 +1225,20 @@ extern void dentry_unhash(struct dentry *dentry);
 extern int file_permission(struct file *, int);
 
 /*
+ * VFS FS_IOC_FIEMAP helper definitions.
+ */
+struct fiemap_extent_info {
+        unsigned int fi_flags;          /* Flags as passed from user */
+        unsigned int fi_extents_mapped; /* Number of mapped extents */
+        unsigned int fi_extents_max;    /* Size of fiemap_extent array */
+        struct fiemap_extent *fi_extents_start; /* Start of fiemap_extent
+                                                 * array */
+};
+int fiemap_fill_next_extent(struct fiemap_extent_info *info, u64 logical,
+                            u64 phys, u64 len, u32 flags);
+int fiemap_check_flags(struct fiemap_extent_info *fieinfo, u32 fs_flags);
+
+/*
  * File types
  *
  * NOTE! These match bits 12..15 of stat.st_mode
@@ -1287,6 +1347,8 @@ struct inode_operations {
         void (*truncate_range)(struct inode *, loff_t, loff_t);
         long (*fallocate)(struct inode *inode, int mode, loff_t offset,
                           loff_t len);
+        int (*fiemap)(struct inode *, struct fiemap_extent_info *, u64 start,
+                      u64 len);
 };
 
 struct seq_file;
@@ -1554,9 +1616,12 @@ extern int vfs_statfs(struct dentry *, struct kstatfs *);
 /* /sys/fs */
 extern struct kobject *fs_kobj;
 
+extern int rw_verify_area(int, struct file *, loff_t *, size_t);
+
 #define FLOCK_VERIFY_READ  1
 #define FLOCK_VERIFY_WRITE 2
 
+#ifdef CONFIG_FILE_LOCKING
 extern int locks_mandatory_locked(struct inode *);
 extern int locks_mandatory_area(int, struct inode *, struct file *, loff_t, size_t);
 
@@ -1587,8 +1652,6 @@ static inline int locks_verify_locked(struct inode *inode)
         return 0;
 }
 
-extern int rw_verify_area(int, struct file *, loff_t *, size_t);
-
 static inline int locks_verify_truncate(struct inode *inode,
                                     struct file *filp,
                                     loff_t size)
@@ -1609,6 +1672,15 @@ static inline int break_lease(struct inode *inode, unsigned int mode)
                 return __break_lease(inode, mode);
         return 0;
 }
+#else /* !CONFIG_FILE_LOCKING */
+#define locks_mandatory_locked(a) ({ 0; })
+#define locks_mandatory_area(a, b, c, d, e) ({ 0; })
+#define __mandatory_lock(a) ({ 0; })
+#define mandatory_lock(a) ({ 0; })
+#define locks_verify_locked(a) ({ 0; })
+#define locks_verify_truncate(a, b, c) ({ 0; })
+#define break_lease(a, b) ({ 0; })
+#endif /* CONFIG_FILE_LOCKING */
 
 /* fs/open.c */
 
@@ -1682,6 +1754,7 @@ extern void chrdev_show(struct seq_file *,off_t);
 
 /* fs/block_dev.c */
 #define BDEVNAME_SIZE   32      /* Largest string for a blockdev identifier */
+#define BDEVT_SIZE      10      /* Largest string for MAJ:MIN for blkdev */
 
 #ifdef CONFIG_BLOCK
 #define BLKDEV_MAJOR_HASH_SIZE  255
@@ -1718,6 +1791,9 @@ extern int fs_may_remount_ro(struct super_block *);
  */
 #define bio_data_dir(bio)       ((bio)->bi_rw & 1)
 
+extern void check_disk_size_change(struct gendisk *disk,
+                                   struct block_device *bdev);
+extern int revalidate_disk(struct gendisk *);
 extern int check_disk_change(struct block_device *);
 extern int __invalidate_device(struct block_device *);
 extern int invalidate_partition(struct gendisk *, int);
@@ -1980,6 +2056,9 @@ extern int vfs_fstat(unsigned int, struct kstat *);
 
 extern int do_vfs_ioctl(struct file *filp, unsigned int fd, unsigned int cmd,
                     unsigned long arg);
+extern int generic_block_fiemap(struct inode *inode,
+                                struct fiemap_extent_info *fieinfo, u64 start,
+                                u64 len, get_block_t *get_block);
 
 extern void get_filesystem(struct file_system_type *fs);
 extern void put_filesystem(struct file_system_type *fs);
diff --git a/include/linux/fs_uart_pd.h b/include/linux/fs_uart_pd.h
index 809bb9ffc788..36b61ff39277 100644
--- a/include/linux/fs_uart_pd.h
+++ b/include/linux/fs_uart_pd.h
@@ -12,7 +12,6 @@
 #ifndef FS_UART_PD_H
 #define FS_UART_PD_H
 
-#include <linux/version.h>
 #include <asm/types.h>
 
 enum fs_uart_id {
diff --git a/include/linux/gameport.h b/include/linux/gameport.h
index f64e29c0ef3f..0cd825f7363a 100644
--- a/include/linux/gameport.h
+++ b/include/linux/gameport.h
@@ -146,10 +146,11 @@ static inline void gameport_unpin_driver(struct gameport *gameport)
         mutex_unlock(&gameport->drv_mutex);
 }
 
-void __gameport_register_driver(struct gameport_driver *drv, struct module *owner);
-static inline void gameport_register_driver(struct gameport_driver *drv)
+int __gameport_register_driver(struct gameport_driver *drv,
+                                struct module *owner, const char *mod_name);
+static inline int __must_check gameport_register_driver(struct gameport_driver *drv)
 {
-        __gameport_register_driver(drv, THIS_MODULE);
+        return __gameport_register_driver(drv, THIS_MODULE, KBUILD_MODNAME);
 }
 
 void gameport_unregister_driver(struct gameport_driver *drv);
diff --git a/include/linux/genhd.h b/include/linux/genhd.h
index 118216f1bd3c..206cdf96c3a7 100644
--- a/include/linux/genhd.h
+++ b/include/linux/genhd.h
@@ -11,12 +11,15 @@
 
 #include <linux/types.h>
 #include <linux/kdev_t.h>
+#include <linux/rcupdate.h>
 
 #ifdef CONFIG_BLOCK
 
-#define kobj_to_dev(k) container_of(k, struct device, kobj)
-#define dev_to_disk(device) container_of(device, struct gendisk, dev)
-#define dev_to_part(device) container_of(device, struct hd_struct, dev)
+#define kobj_to_dev(k)          container_of((k), struct device, kobj)
+#define dev_to_disk(device)     container_of((device), struct gendisk, part0.__dev)
+#define dev_to_part(device)     container_of((device), struct hd_struct, __dev)
+#define disk_to_dev(disk)       (&(disk)->part0.__dev)
+#define part_to_dev(part)       (&((part)->__dev))
 
 extern struct device_type part_type;
 extern struct kobject *block_depr;
@@ -55,6 +58,9 @@ enum {
         UNIXWARE_PARTITION = 0x63,      /* Same as GNU_HURD and SCO Unix */
 };
 
+#define DISK_MAX_PARTS                  256
+#define DISK_NAME_LEN                   32
+
 #include <linux/major.h>
 #include <linux/device.h>
 #include <linux/smp.h>
@@ -87,7 +93,7 @@ struct disk_stats {
 struct hd_struct {
         sector_t start_sect;
         sector_t nr_sects;
-        struct device dev;
+        struct device __dev;
         struct kobject *holder_dir;
         int policy, partno;
 #ifdef CONFIG_FAIL_MAKE_REQUEST
@@ -100,6 +106,7 @@ struct hd_struct {
 #else
         struct disk_stats dkstats;
 #endif
+        struct rcu_head rcu_head;
 };
 
 #define GENHD_FL_REMOVABLE                      1
@@ -108,7 +115,7 @@ struct hd_struct {
 #define GENHD_FL_CD                             8
 #define GENHD_FL_UP                             16
 #define GENHD_FL_SUPPRESS_PARTITION_INFO        32
-#define GENHD_FL_FAIL                           64
+#define GENHD_FL_EXT_DEVT                       64 /* allow extended devt */
 
 #define BLK_SCSI_MAX_CMDS       (256)
 #define BLK_SCSI_CMD_PER_LONG   (BLK_SCSI_MAX_CMDS / (sizeof(long) * 8))
@@ -119,99 +126,137 @@ struct blk_scsi_cmd_filter {
         struct kobject kobj;
 };
 
+struct disk_part_tbl {
+        struct rcu_head rcu_head;
+        int len;
+        struct hd_struct *part[];
+};
+
 struct gendisk {
+        /* major, first_minor and minors are input parameters only,
+         * don't use directly.  Use disk_devt() and disk_max_parts().
+         */
         int major;                      /* major number of driver */
         int first_minor;
         int minors;                     /* maximum number of minors, =1 for
                                          * disks that can't be partitioned. */
-        char disk_name[32];             /* name of major driver */
-        struct hd_struct **part;        /* [indexed by minor] */
+
+        char disk_name[DISK_NAME_LEN];  /* name of major driver */
+
+        /* Array of pointers to partitions indexed by partno.
+         * Protected with matching bdev lock but stat and other
+         * non-critical accesses use RCU.  Always access through
+         * helpers.
+         */
+        struct disk_part_tbl *part_tbl;
+        struct hd_struct part0;
+
         struct block_device_operations *fops;
         struct request_queue *queue;
-        struct blk_scsi_cmd_filter cmd_filter;
         void *private_data;
-        sector_t capacity;
 
         int flags;
         struct device *driverfs_dev;  // FIXME: remove
-        struct device dev;
-        struct kobject *holder_dir;
         struct kobject *slave_dir;
 
         struct timer_rand_state *random;
-        int policy;
 
         atomic_t sync_io;               /* RAID */
-        unsigned long stamp;
-        int in_flight;
-#ifdef  CONFIG_SMP
-        struct disk_stats *dkstats;
-#else
-        struct disk_stats dkstats;
-#endif
         struct work_struct async_notify;
 #ifdef  CONFIG_BLK_DEV_INTEGRITY
         struct blk_integrity *integrity;
 #endif
+        int node_id;
 };
 
-/* 
- * Macros to operate on percpu disk statistics:
- *
- * The __ variants should only be called in critical sections. The full
- * variants disable/enable preemption.
- */
-static inline struct hd_struct *get_part(struct gendisk *gendiskp,
-                                         sector_t sector)
+static inline struct gendisk *part_to_disk(struct hd_struct *part)
 {
-        struct hd_struct *part;
-        int i;
-        for (i = 0; i < gendiskp->minors - 1; i++) {
-                part = gendiskp->part[i];
-                if (part && part->start_sect <= sector
-                    && sector < part->start_sect + part->nr_sects)
-                        return part;
+        if (likely(part)) {
+                if (part->partno)
+                        return dev_to_disk(part_to_dev(part)->parent);
+                else
+                        return dev_to_disk(part_to_dev(part));
         }
         return NULL;
 }
 
-#ifdef  CONFIG_SMP
-#define __disk_stat_add(gendiskp, field, addnd)         \
-        (per_cpu_ptr(gendiskp->dkstats, smp_processor_id())->field += addnd)
+static inline int disk_max_parts(struct gendisk *disk)
+{
+        if (disk->flags & GENHD_FL_EXT_DEVT)
+                return DISK_MAX_PARTS;
+        return disk->minors;
+}
 
-#define disk_stat_read(gendiskp, field)                                 \
-({                                                                      \
-        typeof(gendiskp->dkstats->field) res = 0;                       \
-        int i;                                                          \
-        for_each_possible_cpu(i)                                        \
-                res += per_cpu_ptr(gendiskp->dkstats, i)->field;        \
-        res;                                                            \
-})
+static inline bool disk_partitionable(struct gendisk *disk)
+{
+        return disk_max_parts(disk) > 1;
+}
 
-static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)       {
-        int i;
+static inline dev_t disk_devt(struct gendisk *disk)
+{
+        return disk_to_dev(disk)->devt;
+}
 
-        for_each_possible_cpu(i)
-                memset(per_cpu_ptr(gendiskp->dkstats, i), value,
-                                sizeof(struct disk_stats));
-}               
+static inline dev_t part_devt(struct hd_struct *part)
+{
+        return part_to_dev(part)->devt;
+}
 
-#define __part_stat_add(part, field, addnd)                             \
-        (per_cpu_ptr(part->dkstats, smp_processor_id())->field += addnd)
+extern struct hd_struct *disk_get_part(struct gendisk *disk, int partno);
 
-#define __all_stat_add(gendiskp, part, field, addnd, sector)    \
-({                                                              \
-        if (part)                                               \
-                __part_stat_add(part, field, addnd);            \
-        __disk_stat_add(gendiskp, field, addnd);                \
-})
+static inline void disk_put_part(struct hd_struct *part)
+{
+        if (likely(part))
+                put_device(part_to_dev(part));
+}
+
+/*
+ * Smarter partition iterator without context limits.
+ */
+#define DISK_PITER_REVERSE      (1 << 0) /* iterate in the reverse direction */
+#define DISK_PITER_INCL_EMPTY   (1 << 1) /* include 0-sized parts */
+#define DISK_PITER_INCL_PART0   (1 << 2) /* include partition 0 */
+
+struct disk_part_iter {
+        struct gendisk          *disk;
+        struct hd_struct        *part;
+        int                     idx;
+        unsigned int            flags;
+};
+
+extern void disk_part_iter_init(struct disk_part_iter *piter,
+                                 struct gendisk *disk, unsigned int flags);
+extern struct hd_struct *disk_part_iter_next(struct disk_part_iter *piter);
+extern void disk_part_iter_exit(struct disk_part_iter *piter);
+
+extern struct hd_struct *disk_map_sector_rcu(struct gendisk *disk,
+                                             sector_t sector);
+
+/*
+ * Macros to operate on percpu disk statistics:
+ *
+ * {disk|part|all}_stat_{add|sub|inc|dec}() modify the stat counters
+ * and should be called between disk_stat_lock() and
+ * disk_stat_unlock().
+ *
+ * part_stat_read() can be called at any time.
+ *
+ * part_stat_{add|set_all}() and {init|free}_part_stats are for
+ * internal use only.
+ */
+#ifdef  CONFIG_SMP
+#define part_stat_lock()        ({ rcu_read_lock(); get_cpu(); })
+#define part_stat_unlock()      do { put_cpu(); rcu_read_unlock(); } while (0)
+
+#define __part_stat_add(cpu, part, field, addnd)                        \
+        (per_cpu_ptr((part)->dkstats, (cpu))->field += (addnd))
 
 #define part_stat_read(part, field)                                     \
 ({                                                                      \
-        typeof(part->dkstats->field) res = 0;                           \
+        typeof((part)->dkstats->field) res = 0;                         \
         int i;                                                          \
         for_each_possible_cpu(i)                                        \
-                res += per_cpu_ptr(part->dkstats, i)->field;            \
+                res += per_cpu_ptr((part)->dkstats, i)->field;          \
         res;                                                            \
 })
 
@@ -223,171 +268,107 @@ static inline void part_stat_set_all(struct hd_struct *part, int value)
                 memset(per_cpu_ptr(part->dkstats, i), value,
                                 sizeof(struct disk_stats));
 }
-                                
-#else /* !CONFIG_SMP */
-#define __disk_stat_add(gendiskp, field, addnd) \
-                                (gendiskp->dkstats.field += addnd)
-#define disk_stat_read(gendiskp, field) (gendiskp->dkstats.field)
 
-static inline void disk_stat_set_all(struct gendisk *gendiskp, int value)
+static inline int init_part_stats(struct hd_struct *part)
 {
-        memset(&gendiskp->dkstats, value, sizeof (struct disk_stats));
+        part->dkstats = alloc_percpu(struct disk_stats);
+        if (!part->dkstats)
+                return 0;
+        return 1;
 }
 
-#define __part_stat_add(part, field, addnd) \
-        (part->dkstats.field += addnd)
-
-#define __all_stat_add(gendiskp, part, field, addnd, sector)    \
-({                                                              \
-        if (part)                                               \
-                part->dkstats.field += addnd;                   \
-        __disk_stat_add(gendiskp, field, addnd);                \
-})
-
-#define part_stat_read(part, field)     (part->dkstats.field)
-
-static inline void part_stat_set_all(struct hd_struct *part, int value)
+static inline void free_part_stats(struct hd_struct *part)
 {
-        memset(&part->dkstats, value, sizeof(struct disk_stats));
+        free_percpu(part->dkstats);
 }
 
-#endif /* CONFIG_SMP */
+#else /* !CONFIG_SMP */
+#define part_stat_lock()        ({ rcu_read_lock(); 0; })
+#define part_stat_unlock()      rcu_read_unlock()
 
-#define disk_stat_add(gendiskp, field, addnd)                   \
-        do {                                                    \
-                preempt_disable();                              \
-                __disk_stat_add(gendiskp, field, addnd);        \
-                preempt_enable();                               \
-        } while (0)
-
-#define __disk_stat_dec(gendiskp, field) __disk_stat_add(gendiskp, field, -1)
-#define disk_stat_dec(gendiskp, field) disk_stat_add(gendiskp, field, -1)
-
-#define __disk_stat_inc(gendiskp, field) __disk_stat_add(gendiskp, field, 1)
-#define disk_stat_inc(gendiskp, field) disk_stat_add(gendiskp, field, 1)
-
-#define __disk_stat_sub(gendiskp, field, subnd) \
-                __disk_stat_add(gendiskp, field, -subnd)
-#define disk_stat_sub(gendiskp, field, subnd) \
-                disk_stat_add(gendiskp, field, -subnd)
-
-#define part_stat_add(gendiskp, field, addnd)           \
-        do {                                            \
-                preempt_disable();                      \
-                __part_stat_add(gendiskp, field, addnd);\
-                preempt_enable();                       \
-        } while (0)
-
-#define __part_stat_dec(gendiskp, field) __part_stat_add(gendiskp, field, -1)
-#define part_stat_dec(gendiskp, field) part_stat_add(gendiskp, field, -1)
-
-#define __part_stat_inc(gendiskp, field) __part_stat_add(gendiskp, field, 1)
-#define part_stat_inc(gendiskp, field) part_stat_add(gendiskp, field, 1)
-
-#define __part_stat_sub(gendiskp, field, subnd) \
-                __part_stat_add(gendiskp, field, -subnd)
-#define part_stat_sub(gendiskp, field, subnd) \
-                part_stat_add(gendiskp, field, -subnd)
-
-#define all_stat_add(gendiskp, part, field, addnd, sector)      \
-        do {                                                    \
-                preempt_disable();                              \
-                __all_stat_add(gendiskp, part, field, addnd, sector);   \
-                preempt_enable();                               \
-        } while (0)
-
-#define __all_stat_dec(gendiskp, field, sector) \
-                __all_stat_add(gendiskp, field, -1, sector)
-#define all_stat_dec(gendiskp, field, sector) \
-                all_stat_add(gendiskp, field, -1, sector)
-
-#define __all_stat_inc(gendiskp, part, field, sector) \
-                __all_stat_add(gendiskp, part, field, 1, sector)
-#define all_stat_inc(gendiskp, part, field, sector) \
-                all_stat_add(gendiskp, part, field, 1, sector)
-
-#define __all_stat_sub(gendiskp, part, field, subnd, sector) \
-                __all_stat_add(gendiskp, part, field, -subnd, sector)
-#define all_stat_sub(gendiskp, part, field, subnd, sector) \
-                all_stat_add(gendiskp, part, field, -subnd, sector)
-
-/* Inlines to alloc and free disk stats in struct gendisk */
-#ifdef  CONFIG_SMP
-static inline int init_disk_stats(struct gendisk *disk)
-{
-        disk->dkstats = alloc_percpu(struct disk_stats);
-        if (!disk->dkstats)
-                return 0;
-        return 1;
-}
+#define __part_stat_add(cpu, part, field, addnd)                                \
+        ((part)->dkstats.field += addnd)
+
+#define part_stat_read(part, field)     ((part)->dkstats.field)
 
-static inline void free_disk_stats(struct gendisk *disk)
+static inline void part_stat_set_all(struct hd_struct *part, int value)
 {
-        free_percpu(disk->dkstats);
+        memset(&part->dkstats, value, sizeof(struct disk_stats));
 }
 
 static inline int init_part_stats(struct hd_struct *part)
 {
-        part->dkstats = alloc_percpu(struct disk_stats);
-        if (!part->dkstats)
-                return 0;
         return 1;
 }
 
 static inline void free_part_stats(struct hd_struct *part)
 {
-        free_percpu(part->dkstats);
-}
-
-#else   /* CONFIG_SMP */
-static inline int init_disk_stats(struct gendisk *disk)
-{
-        return 1;
 }
 
-static inline void free_disk_stats(struct gendisk *disk)
-{
-}
+#endif /* CONFIG_SMP */
 
-static inline int init_part_stats(struct hd_struct *part)
+#define part_stat_add(cpu, part, field, addnd)  do {                    \
+        __part_stat_add((cpu), (part), field, addnd);                   \
+        if ((part)->partno)                                             \
+                __part_stat_add((cpu), &part_to_disk((part))->part0,    \
+                                field, addnd);                          \
+} while (0)
+
+#define part_stat_dec(cpu, gendiskp, field)                             \
+        part_stat_add(cpu, gendiskp, field, -1)
+#define part_stat_inc(cpu, gendiskp, field)                             \
+        part_stat_add(cpu, gendiskp, field, 1)
+#define part_stat_sub(cpu, gendiskp, field, subnd)                      \
+        part_stat_add(cpu, gendiskp, field, -subnd)
+
+static inline void part_inc_in_flight(struct hd_struct *part)
 {
-        return 1;
+        part->in_flight++;
+        if (part->partno)
+                part_to_disk(part)->part0.in_flight++;
 }
 
-static inline void free_part_stats(struct hd_struct *part)
+static inline void part_dec_in_flight(struct hd_struct *part)
 {
+        part->in_flight--;
+        if (part->partno)
+                part_to_disk(part)->part0.in_flight--;
 }
-#endif  /* CONFIG_SMP */
 
 /* drivers/block/ll_rw_blk.c */
-extern void disk_round_stats(struct gendisk *disk);
-extern void part_round_stats(struct hd_struct *part);
+extern void part_round_stats(int cpu, struct hd_struct *part);
 
 /* drivers/block/genhd.c */
 extern int get_blkdev_list(char *, int);
 extern void add_disk(struct gendisk *disk);
 extern void del_gendisk(struct gendisk *gp);
 extern void unlink_gendisk(struct gendisk *gp);
-extern struct gendisk *get_gendisk(dev_t dev, int *part);
+extern struct gendisk *get_gendisk(dev_t dev, int *partno);
+extern struct block_device *bdget_disk(struct gendisk *disk, int partno);
 
 extern void set_device_ro(struct block_device *bdev, int flag);
 extern void set_disk_ro(struct gendisk *disk, int flag);
 
+static inline int get_disk_ro(struct gendisk *disk)
+{
+        return disk->part0.policy;
+}
+
 /* drivers/char/random.c */
 extern void add_disk_randomness(struct gendisk *disk);
 extern void rand_initialize_disk(struct gendisk *disk);
 
 static inline sector_t get_start_sect(struct block_device *bdev)
 {
-        return bdev->bd_contains == bdev ? 0 : bdev->bd_part->start_sect;
+        return bdev->bd_part->start_sect;
 }
 static inline sector_t get_capacity(struct gendisk *disk)
 {
-        return disk->capacity;
+        return disk->part0.nr_sects;
 }
 static inline void set_capacity(struct gendisk *disk, sector_t size)
 {
-        disk->capacity = size;
+        disk->part0.nr_sects = size;
 }
 
 #ifdef CONFIG_SOLARIS_X86_PARTITION
@@ -537,9 +518,12 @@ struct unixware_disklabel {
 #define ADDPART_FLAG_RAID       1
 #define ADDPART_FLAG_WHOLEDISK  2
 
-extern dev_t blk_lookup_devt(const char *name, int part);
-extern char *disk_name (struct gendisk *hd, int part, char *buf);
+extern int blk_alloc_devt(struct hd_struct *part, dev_t *devt);
+extern void blk_free_devt(dev_t devt);
+extern dev_t blk_lookup_devt(const char *name, int partno);
+extern char *disk_name (struct gendisk *hd, int partno, char *buf);
 
+extern int disk_expand_part_tbl(struct gendisk *disk, int target);
 extern int rescan_partitions(struct gendisk *disk, struct block_device *bdev);
 extern int __must_check add_partition(struct gendisk *, int, sector_t, sector_t, int);
 extern void delete_partition(struct gendisk *, int);
@@ -556,16 +540,23 @@ extern void blk_register_region(dev_t devt, unsigned long range,
                         void *data);
 extern void blk_unregister_region(dev_t devt, unsigned long range);
 
-static inline struct block_device *bdget_disk(struct gendisk *disk, int index)
-{
-        return bdget(MKDEV(disk->major, disk->first_minor) + index);
-}
+extern ssize_t part_size_show(struct device *dev,
+                              struct device_attribute *attr, char *buf);
+extern ssize_t part_stat_show(struct device *dev,
+                              struct device_attribute *attr, char *buf);
+#ifdef CONFIG_FAIL_MAKE_REQUEST
+extern ssize_t part_fail_show(struct device *dev,
+                              struct device_attribute *attr, char *buf);
+extern ssize_t part_fail_store(struct device *dev,
+                               struct device_attribute *attr,
+                               const char *buf, size_t count);
+#endif /* CONFIG_FAIL_MAKE_REQUEST */
 
 #else /* CONFIG_BLOCK */
 
 static inline void printk_all_partitions(void) { }
 
-static inline dev_t blk_lookup_devt(const char *name, int part)
+static inline dev_t blk_lookup_devt(const char *name, int partno)
 {
         dev_t devt = MKDEV(0, 0);
         return devt;
diff --git a/include/linux/gfs2_ondisk.h b/include/linux/gfs2_ondisk.h
index c3c19f926e6f..14d0df0b5749 100644
--- a/include/linux/gfs2_ondisk.h
+++ b/include/linux/gfs2_ondisk.h
@@ -118,7 +118,11 @@ struct gfs2_sb {
 
         char sb_lockproto[GFS2_LOCKNAME_LEN];
         char sb_locktable[GFS2_LOCKNAME_LEN];
-        /* In gfs1, quota and license dinodes followed */
+
+        struct gfs2_inum __pad3; /* Was quota inode in gfs1 */
+        struct gfs2_inum __pad4; /* Was licence inode in gfs1 */
+#define GFS2_HAS_UUID 1
+        __u8 sb_uuid[16]; /* The UUID, maybe 0 for backwards compat */
 };
 
 /*
diff --git a/include/linux/gpio.h b/include/linux/gpio.h
index 730a20b83576..e10c49a5b96e 100644
--- a/include/linux/gpio.h
+++ b/include/linux/gpio.h
@@ -8,6 +8,7 @@
 
 #else
 
+#include <linux/kernel.h>
 #include <linux/types.h>
 #include <linux/errno.h>
 
@@ -32,6 +33,8 @@ static inline int gpio_request(unsigned gpio, const char *label)
 
 static inline void gpio_free(unsigned gpio)
 {
+        might_sleep();
+
         /* GPIO can never have been requested */
         WARN_ON(1);
 }
diff --git a/include/linux/hid.h b/include/linux/hid.h
index ac4e678a04ed..f13bca2dd53b 100644
--- a/include/linux/hid.h
+++ b/include/linux/hid.h
@@ -67,6 +67,7 @@
 #include <linux/types.h>
 #include <linux/slab.h>
 #include <linux/list.h>
+#include <linux/mod_devicetable.h> /* hid_device_id */
 #include <linux/timer.h>
 #include <linux/workqueue.h>
 #include <linux/input.h>
@@ -246,6 +247,19 @@ struct hid_item {
 #define HID_FEATURE_REPORT      2
 
 /*
+ * HID connect requests
+ */
+
+#define HID_CONNECT_HIDINPUT            0x01
+#define HID_CONNECT_HIDINPUT_FORCE      0x02
+#define HID_CONNECT_HIDRAW              0x04
+#define HID_CONNECT_HIDDEV              0x08
+#define HID_CONNECT_HIDDEV_FORCE        0x10
+#define HID_CONNECT_FF                  0x20
+#define HID_CONNECT_DEFAULT     (HID_CONNECT_HIDINPUT|HID_CONNECT_HIDRAW| \
+                HID_CONNECT_HIDDEV|HID_CONNECT_FF)
+
+/*
  * HID device quirks.
  */
 
@@ -256,48 +270,11 @@ struct hid_item {
 
 #define HID_QUIRK_INVERT                        0x00000001
 #define HID_QUIRK_NOTOUCH                       0x00000002
-#define HID_QUIRK_IGNORE                        0x00000004
 #define HID_QUIRK_NOGET                         0x00000008
-#define HID_QUIRK_HIDDEV                        0x00000010
 #define HID_QUIRK_BADPAD                        0x00000020
 #define HID_QUIRK_MULTI_INPUT                   0x00000040
-#define HID_QUIRK_2WHEEL_MOUSE_HACK_7           0x00000080
-#define HID_QUIRK_2WHEEL_MOUSE_HACK_5           0x00000100
-#define HID_QUIRK_2WHEEL_MOUSE_HACK_ON          0x00000200
-#define HID_QUIRK_MIGHTYMOUSE                   0x00000400
-#define HID_QUIRK_APPLE_HAS_FN                  0x00000800
-#define HID_QUIRK_APPLE_FN_ON                   0x00001000
-#define HID_QUIRK_INVERT_HWHEEL                 0x00002000
-#define HID_QUIRK_APPLE_ISO_KEYBOARD            0x00004000
-#define HID_QUIRK_BAD_RELATIVE_KEYS             0x00008000
 #define HID_QUIRK_SKIP_OUTPUT_REPORTS           0x00010000
-#define HID_QUIRK_IGNORE_MOUSE                  0x00020000
-#define HID_QUIRK_SONY_PS3_CONTROLLER           0x00040000
-#define HID_QUIRK_DUPLICATE_USAGES              0x00080000
-#define HID_QUIRK_RESET_LEDS                    0x00100000
-#define HID_QUIRK_HIDINPUT                      0x00200000
-#define HID_QUIRK_LOGITECH_IGNORE_DOUBLED_WHEEL 0x00400000
-#define HID_QUIRK_LOGITECH_EXPANDED_KEYMAP      0x00800000
-#define HID_QUIRK_IGNORE_HIDINPUT               0x01000000
-#define HID_QUIRK_2WHEEL_MOUSE_HACK_B8          0x02000000
-#define HID_QUIRK_HWHEEL_WHEEL_INVERT           0x04000000
-#define HID_QUIRK_MICROSOFT_KEYS                0x08000000
 #define HID_QUIRK_FULLSPEED_INTERVAL            0x10000000
-#define HID_QUIRK_APPLE_NUMLOCK_EMULATION       0x20000000
-
-/*
- * Separate quirks for runtime report descriptor fixup
- */
-
-#define HID_QUIRK_RDESC_CYMOTION                0x00000001
-#define HID_QUIRK_RDESC_LOGITECH                0x00000002
-#define HID_QUIRK_RDESC_SWAPPED_MIN_MAX         0x00000004
-#define HID_QUIRK_RDESC_PETALYNX                0x00000008
-#define HID_QUIRK_RDESC_MACBOOK_JIS             0x00000010
-#define HID_QUIRK_RDESC_BUTTON_CONSUMER         0x00000020
-#define HID_QUIRK_RDESC_SAMSUNG_REMOTE          0x00000040
-#define HID_QUIRK_RDESC_MICROSOFT_RECV_1028     0x00000080
-#define HID_QUIRK_RDESC_SUNPLUS_WDESKTOP        0x00000100
 
 /*
  * This is the global environment of the parser. This information is
@@ -411,12 +388,21 @@ struct hid_report_enum {
 struct hid_control_fifo {
         unsigned char dir;
         struct hid_report *report;
+        char *raw_report;
+};
+
+struct hid_output_fifo {
+        struct hid_report *report;
+        char *raw_report;
 };
 
 #define HID_CLAIMED_INPUT       1
 #define HID_CLAIMED_HIDDEV      2
 #define HID_CLAIMED_HIDRAW      4
 
+#define HID_STAT_ADDED          1
+#define HID_STAT_PARSED         2
+
 #define HID_CTRL_RUNNING        1
 #define HID_OUT_RUNNING         2
 #define HID_IN_RUNNING          3
@@ -431,22 +417,28 @@ struct hid_input {
         struct input_dev *input;
 };
 
+struct hid_driver;
+struct hid_ll_driver;
+
 struct hid_device {                                                     /* device report descriptor */
-         __u8 *rdesc;
+        __u8 *rdesc;
         unsigned rsize;
         struct hid_collection *collection;                              /* List of HID collections */
         unsigned collection_size;                                       /* Number of allocated hid_collections */
         unsigned maxcollection;                                         /* Number of parsed collections */
         unsigned maxapplication;                                        /* Number of applications */
-        unsigned short bus;                                             /* BUS ID */
-        unsigned short vendor;                                          /* Vendor ID */
-        unsigned short product;                                         /* Product ID */
-        unsigned version;                                               /* HID version */
+        __u16 bus;                                                      /* BUS ID */
+        __u32 vendor;                                                   /* Vendor ID */
+        __u32 product;                                                  /* Product ID */
+        __u32 version;                                                  /* HID version */
         unsigned country;                                               /* HID country */
         struct hid_report_enum report_enum[HID_REPORT_TYPES];
 
-        struct device *dev;                                             /* device */
+        struct device dev;                                              /* device */
+        struct hid_driver *driver;
+        struct hid_ll_driver *ll_driver;
 
+        unsigned int status;                                            /* see STAT flags above */
         unsigned claimed;                                               /* Claimed by hidinput, hiddev? */
         unsigned quirks;                                                /* Various quirks the device can pull on us */
 
@@ -462,26 +454,29 @@ struct hid_device {							/* device report descriptor */
 
         void *driver_data;
 
-        __s32 delayed_value;                                            /* For A4 Tech mice hwheel quirk */
-
-        /* device-specific function pointers */
-        int (*hidinput_input_event) (struct input_dev *, unsigned int, unsigned int, int);
-        int (*hid_open) (struct hid_device *);
-        void (*hid_close) (struct hid_device *);
+        /* temporary hid_ff handling (until moved to the drivers) */
+        int (*ff_init)(struct hid_device *);
 
         /* hiddev event handler */
+        int (*hiddev_connect)(struct hid_device *, unsigned int);
         void (*hiddev_hid_event) (struct hid_device *, struct hid_field *field,
                                   struct hid_usage *, __s32);
         void (*hiddev_report_event) (struct hid_device *, struct hid_report *);
 
         /* handler for raw output data, used by hidraw */
         int (*hid_output_raw_report) (struct hid_device *, __u8 *, size_t);
-#ifdef CONFIG_USB_HIDINPUT_POWERBOOK
-        unsigned long apple_pressed_fn[BITS_TO_LONGS(KEY_CNT)];
-        unsigned long pb_pressed_numlock[BITS_TO_LONGS(KEY_CNT)];
-#endif
 };
 
+static inline void *hid_get_drvdata(struct hid_device *hdev)
+{
+        return dev_get_drvdata(&hdev->dev);
+}
+
+static inline void hid_set_drvdata(struct hid_device *hdev, void *data)
+{
+        dev_set_drvdata(&hdev->dev, data);
+}
+
 #define HID_GLOBAL_STACK_SIZE 4
 #define HID_COLLECTION_STACK_SIZE 4
 
@@ -510,6 +505,107 @@ struct hid_descriptor {
         struct hid_class_descriptor desc[1];
 } __attribute__ ((packed));
 
+#define HID_DEVICE(b, ven, prod) \
+        .bus = (b), \
+        .vendor = (ven), .product = (prod)
+
+#define HID_USB_DEVICE(ven, prod)       HID_DEVICE(BUS_USB, ven, prod)
+#define HID_BLUETOOTH_DEVICE(ven, prod) HID_DEVICE(BUS_BLUETOOTH, ven, prod)
+
+#define HID_REPORT_ID(rep) \
+        .report_type = (rep)
+#define HID_USAGE_ID(uhid, utype, ucode) \
+        .usage_hid = (uhid), .usage_type = (utype), .usage_code = (ucode)
+/* we don't want to catch types and codes equal to 0 */
+#define HID_TERMINATOR          (HID_ANY_ID - 1)
+
+struct hid_report_id {
+        __u32 report_type;
+};
+struct hid_usage_id {
+        __u32 usage_hid;
+        __u32 usage_type;
+        __u32 usage_code;
+};
+
+/**
+ * struct hid_driver
+ * @name: driver name (e.g. "Footech_bar-wheel")
+ * @id_table: which devices is this driver for (must be non-NULL for probe
+ *            to be called)
+ * @probe: new device inserted
+ * @remove: device removed (NULL if not a hot-plug capable driver)
+ * @report_table: on which reports to call raw_event (NULL means all)
+ * @raw_event: if report in report_table, this hook is called (NULL means nop)
+ * @usage_table: on which events to call event (NULL means all)
+ * @event: if usage in usage_table, this hook is called (NULL means nop)
+ * @report_fixup: called before report descriptor parsing (NULL means nop)
+ * @input_mapping: invoked on input registering before mapping an usage
+ * @input_mapped: invoked on input registering after mapping an usage
+ *
+ * raw_event and event should return 0 on no action performed, 1 when no
+ * further processing should be done and negative on error
+ *
+ * input_mapping shall return a negative value to completely ignore this usage
+ * (e.g. doubled or invalid usage), zero to continue with parsing of this
+ * usage by generic code (no special handling needed) or positive to skip
+ * generic parsing (needed special handling which was done in the hook already)
+ * input_mapped shall return negative to inform the layer that this usage
+ * should not be considered for further processing or zero to notify that
+ * no processing was performed and should be done in a generic manner
+ * Both these functions may be NULL which means the same behavior as returning
+ * zero from them.
+ */
+struct hid_driver {
+        char *name;
+        const struct hid_device_id *id_table;
+
+        int (*probe)(struct hid_device *dev, const struct hid_device_id *id);
+        void (*remove)(struct hid_device *dev);
+
+        const struct hid_report_id *report_table;
+        int (*raw_event)(struct hid_device *hdev, struct hid_report *report,
+                        u8 *data, int size);
+        const struct hid_usage_id *usage_table;
+        int (*event)(struct hid_device *hdev, struct hid_field *field,
+                        struct hid_usage *usage, __s32 value);
+
+        void (*report_fixup)(struct hid_device *hdev, __u8 *buf,
+                        unsigned int size);
+
+        int (*input_mapping)(struct hid_device *hdev,
+                        struct hid_input *hidinput, struct hid_field *field,
+                        struct hid_usage *usage, unsigned long **bit, int *max);
+        int (*input_mapped)(struct hid_device *hdev,
+                        struct hid_input *hidinput, struct hid_field *field,
+                        struct hid_usage *usage, unsigned long **bit, int *max);
+/* private: */
+        struct device_driver driver;
+};
+
+/**
+ * hid_ll_driver - low level driver callbacks
+ * @start: called on probe to start the device
+ * @stop: called on remove
+ * @open: called by input layer on open
+ * @close: called by input layer on close
+ * @hidinput_input_event: event input event (e.g. ff or leds)
+ * @parse: this method is called only once to parse the device data,
+ *         shouldn't allocate anything to not leak memory
+ */
+struct hid_ll_driver {
+        int (*start)(struct hid_device *hdev);
+        void (*stop)(struct hid_device *hdev);
+
+        int (*open)(struct hid_device *hdev);
+        void (*close)(struct hid_device *hdev);
+
+        int (*hidinput_input_event) (struct input_dev *idev, unsigned int type,
+                        unsigned int code, int value);
+
+        int (*parse)(struct hid_device *hdev);
+};
+
 /* Applications from HID Usage Tables 4/8/99 Version 1.1 */
 /* We ignore a few input applications that are not widely used */
 #define IS_INPUT_APPLICATION(a) (((a >= 0x00010000) && (a <= 0x00010008)) || (a == 0x00010080) || (a == 0x000c0001) || (a == 0x000d0002))
@@ -520,43 +616,157 @@ struct hid_descriptor {
 extern int hid_debug;
 #endif
 
+extern int hid_add_device(struct hid_device *);
+extern void hid_destroy_device(struct hid_device *);
+
+extern int __must_check __hid_register_driver(struct hid_driver *,
+                struct module *, const char *mod_name);
+static inline int __must_check hid_register_driver(struct hid_driver *driver)
+{
+        return __hid_register_driver(driver, THIS_MODULE, KBUILD_MODNAME);
+}
+extern void hid_unregister_driver(struct hid_driver *);
+
 extern void hidinput_hid_event(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);
 extern void hidinput_report_event(struct hid_device *hid, struct hid_report *report);
-extern int hidinput_connect(struct hid_device *);
+extern int hidinput_connect(struct hid_device *hid, unsigned int force);
 extern void hidinput_disconnect(struct hid_device *);
 
 int hid_set_field(struct hid_field *, unsigned, __s32);
 int hid_input_report(struct hid_device *, int type, u8 *, int, int);
 int hidinput_find_field(struct hid_device *hid, unsigned int type, unsigned int code, struct hid_field **field);
-int hidinput_mapping_quirks(struct hid_usage *, struct input_dev *, unsigned long **, int *);
-int hidinput_event_quirks(struct hid_device *, struct hid_field *, struct hid_usage *, __s32);
-int hidinput_apple_event(struct hid_device *, struct input_dev *, struct hid_usage *, __s32);
 void hid_output_report(struct hid_report *report, __u8 *data);
-void hid_free_device(struct hid_device *device);
-struct hid_device *hid_parse_report(__u8 *start, unsigned size);
+struct hid_device *hid_allocate_device(void);
+int hid_parse_report(struct hid_device *hid, __u8 *start, unsigned size);
+int hid_connect(struct hid_device *hid, unsigned int connect_mask);
+
+/**
+ * hid_map_usage - map usage input bits
+ *
+ * @hidinput: hidinput which we are interested in
+ * @usage: usage to fill in
+ * @bit: pointer to input->{}bit (out parameter)
+ * @max: maximal valid usage->code to consider later (out parameter)
+ * @type: input event type (EV_KEY, EV_REL, ...)
+ * @c: code which corresponds to this usage and type
+ */
+static inline void hid_map_usage(struct hid_input *hidinput,
+                struct hid_usage *usage, unsigned long **bit, int *max,
+                __u8 type, __u16 c)
+{
+        struct input_dev *input = hidinput->input;
+
+        usage->type = type;
+        usage->code = c;
+
+        switch (type) {
+        case EV_ABS:
+                *bit = input->absbit;
+                *max = ABS_MAX;
+                break;
+        case EV_REL:
+                *bit = input->relbit;
+                *max = REL_MAX;
+                break;
+        case EV_KEY:
+                *bit = input->keybit;
+                *max = KEY_MAX;
+                break;
+        case EV_LED:
+                *bit = input->ledbit;
+                *max = LED_MAX;
+                break;
+        }
+}
+
+/**
+ * hid_map_usage_clear - map usage input bits and clear the input bit
+ *
+ * The same as hid_map_usage, except the @c bit is also cleared in supported
+ * bits (@bit).
+ */
+static inline void hid_map_usage_clear(struct hid_input *hidinput,
+                struct hid_usage *usage, unsigned long **bit, int *max,
+                __u8 type, __u16 c)
+{
+        hid_map_usage(hidinput, usage, bit, max, type, c);
+        clear_bit(c, *bit);
+}
+
+/**
+ * hid_parse - parse HW reports
+ *
+ * @hdev: hid device
+ *
+ * Call this from probe after you set up the device (if needed). Your
+ * report_fixup will be called (if non-NULL) after reading raw report from
+ * device before passing it to hid layer for real parsing.
+ */
+static inline int __must_check hid_parse(struct hid_device *hdev)
+{
+        int ret;
+
+        if (hdev->status & HID_STAT_PARSED)
+                return 0;
+
+        ret = hdev->ll_driver->parse(hdev);
+        if (!ret)
+                hdev->status |= HID_STAT_PARSED;
+
+        return ret;
+}
+
+/**
+ * hid_hw_start - start underlaying HW
+ *
+ * @hdev: hid device
+ * @connect_mask: which outputs to connect, see HID_CONNECT_*
+ *
+ * Call this in probe function *after* hid_parse. This will setup HW buffers
+ * and start the device (if not deffered to device open). hid_hw_stop must be
+ * called if this was successfull.
+ */
+static inline int __must_check hid_hw_start(struct hid_device *hdev,
+                unsigned int connect_mask)
+{
+        int ret = hdev->ll_driver->start(hdev);
+        if (ret || !connect_mask)
+                return ret;
+        ret = hid_connect(hdev, connect_mask);
+        if (ret)
+                hdev->ll_driver->stop(hdev);
+        return ret;
+}
+
+/**
+ * hid_hw_stop - stop underlaying HW
+ *
+ * @hdev: hid device
+ *
+ * This is usually called from remove function or from probe when something
+ * failed and hid_hw_start was called already.
+ */
+static inline void hid_hw_stop(struct hid_device *hdev)
+{
+        hdev->ll_driver->stop(hdev);
+}
+
+void hid_report_raw_event(struct hid_device *hid, int type, u8 *data, int size,
+                int interrupt);
+
+extern int hid_generic_init(void);
+extern void hid_generic_exit(void);
 
 /* HID quirks API */
 u32 usbhid_lookup_quirk(const u16 idVendor, const u16 idProduct);
 int usbhid_quirks_init(char **quirks_param);
 void usbhid_quirks_exit(void);
-void usbhid_fixup_report_descriptor(const u16, const u16, char *, unsigned, char **);
-
-#ifdef CONFIG_HID_FF
-int hid_ff_init(struct hid_device *hid);
+void usbhid_set_leds(struct hid_device *hid);
 
-int hid_lgff_init(struct hid_device *hid);
-int hid_lg2ff_init(struct hid_device *hid);
-int hid_plff_init(struct hid_device *hid);
-int hid_tmff_init(struct hid_device *hid);
-int hid_zpff_init(struct hid_device *hid);
 #ifdef CONFIG_HID_PID
 int hid_pidff_init(struct hid_device *hid);
 #else
-static inline int hid_pidff_init(struct hid_device *hid) { return -ENODEV; }
-#endif
-
-#else
-static inline int hid_ff_init(struct hid_device *hid) { return -1; }
+#define hid_pidff_init NULL
 #endif
 
 #ifdef CONFIG_HID_DEBUG
@@ -572,10 +782,23 @@ dbg_hid(const char *fmt, ...)
         return 0;
 }
 #define dbg_hid_line dbg_hid
-#endif
+#endif /* HID_DEBUG */
 
 #define err_hid(format, arg...) printk(KERN_ERR "%s: " format "\n" , \
                 __FILE__ , ## arg)
-#endif
+#endif /* HID_FF */
+
+#ifdef CONFIG_HID_COMPAT
+#define HID_COMPAT_LOAD_DRIVER(name)    \
+void hid_compat_##name(void) { }        \
+EXPORT_SYMBOL(hid_compat_##name)
+#else
+#define HID_COMPAT_LOAD_DRIVER(name)
+#endif /* HID_COMPAT */
+#define HID_COMPAT_CALL_DRIVER(name)    do {    \
+        extern void hid_compat_##name(void);    \
+        hid_compat_##name();                    \
+} while (0)
+
 #endif
 
diff --git a/include/linux/hiddev.h b/include/linux/hiddev.h
index a416b904ba90..c760ae0eb6a1 100644
--- a/include/linux/hiddev.h
+++ b/include/linux/hiddev.h
@@ -182,26 +182,28 @@ struct hiddev_usage_ref_multi {
 /* To traverse the input report descriptor info for a HID device, perform the 
  * following:
  *
- *  rinfo.report_type = HID_REPORT_TYPE_INPUT;
- *  rinfo.report_id = HID_REPORT_ID_FIRST;
- *  ret = ioctl(fd, HIDIOCGREPORTINFO, &rinfo);
+ * rinfo.report_type = HID_REPORT_TYPE_INPUT;
+ * rinfo.report_id = HID_REPORT_ID_FIRST;
+ * ret = ioctl(fd, HIDIOCGREPORTINFO, &rinfo);
  *
- *  while (ret >= 0) {
- *      for (i = 0; i < rinfo.num_fields; i++) { 
- *          finfo.report_type = rinfo.report_type;
- *          finfo.report_id = rinfo.report_id;
- *          finfo.field_index = i;
- *          ioctl(fd, HIDIOCGFIELDINFO, &finfo);
- *          for (j = 0; j < finfo.maxusage; j++) {
- *              uref.field_index = i;
- *              uref.usage_index = j;
- *              ioctl(fd, HIDIOCGUCODE, &uref);
- *              ioctl(fd, HIDIOCGUSAGE, &uref);
- *          }
- *      }
- *      rinfo.report_id |= HID_REPORT_ID_NEXT;
- *      ret = ioctl(fd, HIDIOCGREPORTINFO, &rinfo);
- *  }
+ * while (ret >= 0) {
+ *      for (i = 0; i < rinfo.num_fields; i++) {
+ *              finfo.report_type = rinfo.report_type;
+ *              finfo.report_id = rinfo.report_id;
+ *              finfo.field_index = i;
+ *              ioctl(fd, HIDIOCGFIELDINFO, &finfo);
+ *              for (j = 0; j < finfo.maxusage; j++) {
+ *                      uref.report_type = rinfo.report_type;
+ *                      uref.report_id = rinfo.report_id;
+ *                      uref.field_index = i;
+ *                      uref.usage_index = j;
+ *                      ioctl(fd, HIDIOCGUCODE, &uref);
+ *                      ioctl(fd, HIDIOCGUSAGE, &uref);
+ *              }
+ *      }
+ *      rinfo.report_id |= HID_REPORT_ID_NEXT;
+ *      ret = ioctl(fd, HIDIOCGREPORTINFO, &rinfo);
+ * }
  */
 
 
@@ -217,7 +219,7 @@ struct hid_field;
 struct hid_report;
 
 #ifdef CONFIG_USB_HIDDEV
-int hiddev_connect(struct hid_device *);
+int hiddev_connect(struct hid_device *hid, unsigned int force);
 void hiddev_disconnect(struct hid_device *);
 void hiddev_hid_event(struct hid_device *hid, struct hid_field *field,
                       struct hid_usage *usage, __s32 value);
@@ -225,7 +227,9 @@ void hiddev_report_event(struct hid_device *hid, struct hid_report *report);
 int __init hiddev_init(void);
 void hiddev_exit(void);
 #else
-static inline int hiddev_connect(struct hid_device *hid) { return -1; }
+static inline int hiddev_connect(struct hid_device *hid,
+                unsigned int force)
+{ return -1; }
 static inline void hiddev_disconnect(struct hid_device *hid) { }
 static inline void hiddev_hid_event(struct hid_device *hid, struct hid_field *field,
                       struct hid_usage *usage, __s32 value) { }
diff --git a/include/linux/hpet.h b/include/linux/hpet.h
index 2dc29ce6c8e4..79f63a27bcef 100644
--- a/include/linux/hpet.h
+++ b/include/linux/hpet.h
@@ -37,6 +37,7 @@ struct hpet {
 #define hpet_compare    _u1._hpet_compare
 
 #define HPET_MAX_TIMERS (32)
+#define HPET_MAX_IRQ    (32)
 
 /*
  * HPET general capabilities register
@@ -64,7 +65,7 @@ struct hpet {
  */
 
 #define Tn_INT_ROUTE_CAP_MASK           (0xffffffff00000000ULL)
-#define Tn_INI_ROUTE_CAP_SHIFT          (32UL)
+#define Tn_INT_ROUTE_CAP_SHIFT          (32UL)
 #define Tn_FSB_INT_DELCAP_MASK          (0x8000UL)
 #define Tn_FSB_INT_DELCAP_SHIFT         (15)
 #define Tn_FSB_EN_CNF_MASK              (0x4000UL)
@@ -91,23 +92,14 @@ struct hpet {
  * exported interfaces
  */
 
-struct hpet_task {
-        void (*ht_func) (void *);
-        void *ht_data;
-        void *ht_opaque;
-};
-
 struct hpet_data {
         unsigned long hd_phys_address;
         void __iomem *hd_address;
         unsigned short hd_nirqs;
-        unsigned short hd_flags;
         unsigned int hd_state;  /* timer allocated */
         unsigned int hd_irq[HPET_MAX_TIMERS];
 };
 
-#define HPET_DATA_PLATFORM      0x0001  /* platform call to hpet_alloc */
-
 static inline void hpet_reserve_timer(struct hpet_data *hd, int timer)
 {
         hd->hd_state |= (1 << timer);
@@ -125,7 +117,7 @@ struct hpet_info {
         unsigned short hi_timer;
 };
 
-#define HPET_INFO_PERIODIC      0x0001  /* timer is periodic */
+#define HPET_INFO_PERIODIC      0x0010  /* periodic-capable comparator */
 
 #define HPET_IE_ON      _IO('h', 0x01)  /* interrupt on */
 #define HPET_IE_OFF     _IO('h', 0x02)  /* interrupt off */
diff --git a/include/linux/hrtimer.h b/include/linux/hrtimer.h
index 6d93dce61cbb..9a4e35cd5f79 100644
--- a/include/linux/hrtimer.h
+++ b/include/linux/hrtimer.h
@@ -47,14 +47,22 @@ enum hrtimer_restart {
  *      HRTIMER_CB_IRQSAFE:             Callback may run in hardirq context
  *      HRTIMER_CB_IRQSAFE_NO_RESTART:  Callback may run in hardirq context and
  *                                      does not restart the timer
- *      HRTIMER_CB_IRQSAFE_NO_SOFTIRQ:  Callback must run in hardirq context
- *                                      Special mode for tick emultation
+ *      HRTIMER_CB_IRQSAFE_PERCPU:      Callback must run in hardirq context
+ *                                      Special mode for tick emulation and
+ *                                      scheduler timer. Such timers are per
+ *                                      cpu and not allowed to be migrated on
+ *                                      cpu unplug.
+ *      HRTIMER_CB_IRQSAFE_UNLOCKED:    Callback should run in hardirq context
+ *                                      with timer->base lock unlocked
+ *                                      used for timers which call wakeup to
+ *                                      avoid lock order problems with rq->lock
  */
 enum hrtimer_cb_mode {
         HRTIMER_CB_SOFTIRQ,
         HRTIMER_CB_IRQSAFE,
         HRTIMER_CB_IRQSAFE_NO_RESTART,
-        HRTIMER_CB_IRQSAFE_NO_SOFTIRQ,
+        HRTIMER_CB_IRQSAFE_PERCPU,
+        HRTIMER_CB_IRQSAFE_UNLOCKED,
 };
 
 /*
@@ -67,9 +75,10 @@ enum hrtimer_cb_mode {
  * 0x02         callback function running
  * 0x04         callback pending (high resolution mode)
  *
- * Special case:
+ * Special cases:
  * 0x03         callback function running and enqueued
  *              (was requeued on another CPU)
+ * 0x09         timer was migrated on CPU hotunplug
  * The "callback function running and enqueued" status is only possible on
  * SMP. It happens for example when a posix timer expired and the callback
  * queued a signal. Between dropping the lock which protects the posix timer
@@ -87,6 +96,7 @@ enum hrtimer_cb_mode {
 #define HRTIMER_STATE_ENQUEUED  0x01
 #define HRTIMER_STATE_CALLBACK  0x02
 #define HRTIMER_STATE_PENDING   0x04
+#define HRTIMER_STATE_MIGRATE   0x08
 
 /**
  * struct hrtimer - the basic hrtimer structure
@@ -115,12 +125,12 @@ struct hrtimer {
         enum hrtimer_restart            (*function)(struct hrtimer *);
         struct hrtimer_clock_base       *base;
         unsigned long                   state;
-        enum hrtimer_cb_mode            cb_mode;
         struct list_head                cb_entry;
+        enum hrtimer_cb_mode            cb_mode;
 #ifdef CONFIG_TIMER_STATS
+        int                             start_pid;
         void                            *start_site;
         char                            start_comm[16];
-        int                             start_pid;
 #endif
 };
 
@@ -145,10 +155,8 @@ struct hrtimer_sleeper {
  * @first:              pointer to the timer node which expires first
  * @resolution:         the resolution of the clock, in nanoseconds
  * @get_time:           function to retrieve the current time of the clock
- * @get_softirq_time:   function to retrieve the current time from the softirq
  * @softirq_time:       the time when running the hrtimer queue in the softirq
  * @offset:             offset of this clock to the monotonic base
- * @reprogram:          function to reprogram the timer event
  */
 struct hrtimer_clock_base {
         struct hrtimer_cpu_base *cpu_base;
@@ -157,13 +165,9 @@ struct hrtimer_clock_base {
         struct rb_node          *first;
         ktime_t                 resolution;
         ktime_t                 (*get_time)(void);
-        ktime_t                 (*get_softirq_time)(void);
         ktime_t                 softirq_time;
 #ifdef CONFIG_HIGH_RES_TIMERS
         ktime_t                 offset;
-        int                     (*reprogram)(struct hrtimer *t,
-                                             struct hrtimer_clock_base *b,
-                                             ktime_t n);
 #endif
 };
 
diff --git a/include/linux/i2c-id.h b/include/linux/i2c-id.h
index bf34c5f4c051..01d67ba9e985 100644
--- a/include/linux/i2c-id.h
+++ b/include/linux/i2c-id.h
@@ -41,7 +41,6 @@
 #define I2C_DRIVERID_SAA7110    22      /* video decoder                */
 #define I2C_DRIVERID_SAA5249    24      /* SAA5249 and compatibles      */
 #define I2C_DRIVERID_PCF8583    25      /* real time clock              */
-#define I2C_DRIVERID_SAB3036    26      /* SAB3036 tuner                */
 #define I2C_DRIVERID_TDA7432    27      /* Stereo sound processor       */
 #define I2C_DRIVERID_TVMIXER    28      /* Mixer driver for tv cards    */
 #define I2C_DRIVERID_TVAUDIO    29      /* Generic TV sound driver      */
@@ -61,7 +60,7 @@
 #define I2C_DRIVERID_WM8775     69      /* wm8775 audio processor       */
 #define I2C_DRIVERID_CS53L32A   70      /* cs53l32a audio processor     */
 #define I2C_DRIVERID_CX25840    71      /* cx2584x video encoder        */
-#define I2C_DRIVERID_SAA7127    72      /* saa7124 video encoder        */
+#define I2C_DRIVERID_SAA7127    72      /* saa7127 video encoder        */
 #define I2C_DRIVERID_SAA711X    73      /* saa711x video encoders       */
 #define I2C_DRIVERID_AKITAIOEXP 74      /* IO Expander on Sharp SL-C1000 */
 #define I2C_DRIVERID_INFRARED   75      /* I2C InfraRed on Video boards */
diff --git a/include/linux/i2c.h b/include/linux/i2c.h
index 08be0d21864c..06115128047f 100644
--- a/include/linux/i2c.h
+++ b/include/linux/i2c.h
@@ -97,7 +97,19 @@ extern s32 i2c_smbus_write_i2c_block_data(struct i2c_client * client,
 
 /**
  * struct i2c_driver - represent an I2C device driver
+ * @id: Unique driver ID (optional)
  * @class: What kind of i2c device we instantiate (for detect)
+ * @attach_adapter: Callback for bus addition (for legacy drivers)
+ * @detach_adapter: Callback for bus removal (for legacy drivers)
+ * @detach_client: Callback for device removal (for legacy drivers)
+ * @probe: Callback for device binding (new-style drivers)
+ * @remove: Callback for device unbinding (new-style drivers)
+ * @shutdown: Callback for device shutdown
+ * @suspend: Callback for device suspend
+ * @resume: Callback for device resume
+ * @command: Callback for bus-wide signaling (optional)
+ * @driver: Device driver model driver
+ * @id_table: List of I2C devices supported by this driver
  * @detect: Callback for device detection
  * @address_data: The I2C addresses to probe, ignore or force (for detect)
  * @clients: List of detected clients we created (for i2c-core use only)
diff --git a/include/linux/i2o.h b/include/linux/i2o.h
index 75ae6d8aba4f..4c4e57d1f19d 100644
--- a/include/linux/i2o.h
+++ b/include/linux/i2o.h
@@ -570,7 +570,6 @@ struct i2o_controller {
 #endif
         spinlock_t lock;        /* lock for controller
                                    configuration */
-
         void *driver_data[I2O_MAX_DRIVERS];     /* storage for drivers */
 };
 
@@ -691,289 +690,22 @@ static inline u32 i2o_dma_high(dma_addr_t dma_addr)
 };
 #endif
 
-/**
- *      i2o_sg_tablesize - Calculate the maximum number of elements in a SGL
- *      @c: I2O controller for which the calculation should be done
- *      @body_size: maximum body size used for message in 32-bit words.
- *
- *      Return the maximum number of SG elements in a SG list.
- */
-static inline u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size)
-{
-        i2o_status_block *sb = c->status_block.virt;
-        u16 sg_count =
-            (sb->inbound_frame_size - sizeof(struct i2o_message) / 4) -
-            body_size;
-
-        if (c->pae_support) {
-                /*
-                 * for 64-bit a SG attribute element must be added and each
-                 * SG element needs 12 bytes instead of 8.
-                 */
-                sg_count -= 2;
-                sg_count /= 3;
-        } else
-                sg_count /= 2;
-
-        if (c->short_req && (sg_count > 8))
-                sg_count = 8;
-
-        return sg_count;
-};
-
-/**
- *      i2o_dma_map_single - Map pointer to controller and fill in I2O message.
- *      @c: I2O controller
- *      @ptr: pointer to the data which should be mapped
- *      @size: size of data in bytes
- *      @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
- *      @sg_ptr: pointer to the SG list inside the I2O message
- *
- *      This function does all necessary DMA handling and also writes the I2O
- *      SGL elements into the I2O message. For details on DMA handling see also
- *      dma_map_single(). The pointer sg_ptr will only be set to the end of the
- *      SG list if the allocation was successful.
- *
- *      Returns DMA address which must be checked for failures using
- *      dma_mapping_error().
- */
-static inline dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
+extern u16 i2o_sg_tablesize(struct i2o_controller *c, u16 body_size);
+extern dma_addr_t i2o_dma_map_single(struct i2o_controller *c, void *ptr,
                                             size_t size,
                                             enum dma_data_direction direction,
-                                            u32 ** sg_ptr)
-{
-        u32 sg_flags;
-        u32 *mptr = *sg_ptr;
-        dma_addr_t dma_addr;
-
-        switch (direction) {
-        case DMA_TO_DEVICE:
-                sg_flags = 0xd4000000;
-                break;
-        case DMA_FROM_DEVICE:
-                sg_flags = 0xd0000000;
-                break;
-        default:
-                return 0;
-        }
-
-        dma_addr = dma_map_single(&c->pdev->dev, ptr, size, direction);
-        if (!dma_mapping_error(&c->pdev->dev, dma_addr)) {
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-                if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
-                        *mptr++ = cpu_to_le32(0x7C020002);
-                        *mptr++ = cpu_to_le32(PAGE_SIZE);
-                }
-#endif
-
-                *mptr++ = cpu_to_le32(sg_flags | size);
-                *mptr++ = cpu_to_le32(i2o_dma_low(dma_addr));
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-                if ((sizeof(dma_addr_t) > 4) && c->pae_support)
-                        *mptr++ = cpu_to_le32(i2o_dma_high(dma_addr));
-#endif
-                *sg_ptr = mptr;
-        }
-        return dma_addr;
-};
-
-/**
- *      i2o_dma_map_sg - Map a SG List to controller and fill in I2O message.
- *      @c: I2O controller
- *      @sg: SG list to be mapped
- *      @sg_count: number of elements in the SG list
- *      @direction: DMA_TO_DEVICE / DMA_FROM_DEVICE
- *      @sg_ptr: pointer to the SG list inside the I2O message
- *
- *      This function does all necessary DMA handling and also writes the I2O
- *      SGL elements into the I2O message. For details on DMA handling see also
- *      dma_map_sg(). The pointer sg_ptr will only be set to the end of the SG
- *      list if the allocation was successful.
- *
- *      Returns 0 on failure or 1 on success.
- */
-static inline int i2o_dma_map_sg(struct i2o_controller *c,
+                                            u32 ** sg_ptr);
+extern int i2o_dma_map_sg(struct i2o_controller *c,
                                  struct scatterlist *sg, int sg_count,
                                  enum dma_data_direction direction,
-                                 u32 ** sg_ptr)
-{
-        u32 sg_flags;
-        u32 *mptr = *sg_ptr;
-
-        switch (direction) {
-        case DMA_TO_DEVICE:
-                sg_flags = 0x14000000;
-                break;
-        case DMA_FROM_DEVICE:
-                sg_flags = 0x10000000;
-                break;
-        default:
-                return 0;
-        }
-
-        sg_count = dma_map_sg(&c->pdev->dev, sg, sg_count, direction);
-        if (!sg_count)
-                return 0;
-
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-        if ((sizeof(dma_addr_t) > 4) && c->pae_support) {
-                *mptr++ = cpu_to_le32(0x7C020002);
-                *mptr++ = cpu_to_le32(PAGE_SIZE);
-        }
-#endif
-
-        while (sg_count-- > 0) {
-                if (!sg_count)
-                        sg_flags |= 0xC0000000;
-                *mptr++ = cpu_to_le32(sg_flags | sg_dma_len(sg));
-                *mptr++ = cpu_to_le32(i2o_dma_low(sg_dma_address(sg)));
-#ifdef CONFIG_I2O_EXT_ADAPTEC_DMA64
-                if ((sizeof(dma_addr_t) > 4) && c->pae_support)
-                        *mptr++ = cpu_to_le32(i2o_dma_high(sg_dma_address(sg)));
-#endif
-                sg = sg_next(sg);
-        }
-        *sg_ptr = mptr;
-
-        return 1;
-};
-
-/**
- *      i2o_dma_alloc - Allocate DMA memory
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: i2o_dma struct which should get the DMA buffer
- *      @len: length of the new DMA memory
- *      @gfp_mask: GFP mask
- *
- *      Allocate a coherent DMA memory and write the pointers into addr.
- *
- *      Returns 0 on success or -ENOMEM on failure.
- */
-static inline int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr,
-                                size_t len, gfp_t gfp_mask)
-{
-        struct pci_dev *pdev = to_pci_dev(dev);
-        int dma_64 = 0;
-
-        if ((sizeof(dma_addr_t) > 4) && (pdev->dma_mask == DMA_64BIT_MASK)) {
-                dma_64 = 1;
-                if (pci_set_dma_mask(pdev, DMA_32BIT_MASK))
-                        return -ENOMEM;
-        }
-
-        addr->virt = dma_alloc_coherent(dev, len, &addr->phys, gfp_mask);
-
-        if ((sizeof(dma_addr_t) > 4) && dma_64)
-                if (pci_set_dma_mask(pdev, DMA_64BIT_MASK))
-                        printk(KERN_WARNING "i2o: unable to set 64-bit DMA");
-
-        if (!addr->virt)
-                return -ENOMEM;
-
-        memset(addr->virt, 0, len);
-        addr->len = len;
-
-        return 0;
-};
-
-/**
- *      i2o_dma_free - Free DMA memory
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: i2o_dma struct which contains the DMA buffer
- *
- *      Free a coherent DMA memory and set virtual address of addr to NULL.
- */
-static inline void i2o_dma_free(struct device *dev, struct i2o_dma *addr)
-{
-        if (addr->virt) {
-                if (addr->phys)
-                        dma_free_coherent(dev, addr->len, addr->virt,
-                                          addr->phys);
-                else
-                        kfree(addr->virt);
-                addr->virt = NULL;
-        }
-};
-
-/**
- *      i2o_dma_realloc - Realloc DMA memory
- *      @dev: struct device pointer to the PCI device of the I2O controller
- *      @addr: pointer to a i2o_dma struct DMA buffer
- *      @len: new length of memory
- *      @gfp_mask: GFP mask
- *
- *      If there was something allocated in the addr, free it first. If len > 0
- *      than try to allocate it and write the addresses back to the addr
- *      structure. If len == 0 set the virtual address to NULL.
- *
- *      Returns the 0 on success or negative error code on failure.
- */
-static inline int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
-                                  size_t len, gfp_t gfp_mask)
-{
-        i2o_dma_free(dev, addr);
-
-        if (len)
-                return i2o_dma_alloc(dev, addr, len, gfp_mask);
-
-        return 0;
-};
-
-/*
- *      i2o_pool_alloc - Allocate an slab cache and mempool
- *      @mempool: pointer to struct i2o_pool to write data into.
- *      @name: name which is used to identify cache
- *      @size: size of each object
- *      @min_nr: minimum number of objects
- *
- *      First allocates a slab cache with name and size. Then allocates a
- *      mempool which uses the slab cache for allocation and freeing.
- *
- *      Returns 0 on success or negative error code on failure.
- */
-static inline int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
-                                 size_t size, int min_nr)
-{
-        pool->name = kmalloc(strlen(name) + 1, GFP_KERNEL);
-        if (!pool->name)
-                goto exit;
-        strcpy(pool->name, name);
-
-        pool->slab =
-            kmem_cache_create(pool->name, size, 0, SLAB_HWCACHE_ALIGN, NULL);
-        if (!pool->slab)
-                goto free_name;
-
-        pool->mempool = mempool_create_slab_pool(min_nr, pool->slab);
-        if (!pool->mempool)
-                goto free_slab;
-
-        return 0;
-
-      free_slab:
-        kmem_cache_destroy(pool->slab);
-
-      free_name:
-        kfree(pool->name);
-
-      exit:
-        return -ENOMEM;
-};
-
-/*
- *      i2o_pool_free - Free slab cache and mempool again
- *      @mempool: pointer to struct i2o_pool which should be freed
- *
- *      Note that you have to return all objects to the mempool again before
- *      calling i2o_pool_free().
- */
-static inline void i2o_pool_free(struct i2o_pool *pool)
-{
-        mempool_destroy(pool->mempool);
-        kmem_cache_destroy(pool->slab);
-        kfree(pool->name);
-};
-
+                                 u32 ** sg_ptr);
+extern int i2o_dma_alloc(struct device *dev, struct i2o_dma *addr, size_t len);
+extern void i2o_dma_free(struct device *dev, struct i2o_dma *addr);
+extern int i2o_dma_realloc(struct device *dev, struct i2o_dma *addr,
+                                                                size_t len);
+extern int i2o_pool_alloc(struct i2o_pool *pool, const char *name,
+                                 size_t size, int min_nr);
+extern void i2o_pool_free(struct i2o_pool *pool);
 /* I2O driver (OSM) functions */
 extern int i2o_driver_register(struct i2o_driver *);
 extern void i2o_driver_unregister(struct i2o_driver *);
diff --git a/include/linux/icmpv6.h b/include/linux/icmpv6.h
index 03067443198a..a93a8dd33118 100644
--- a/include/linux/icmpv6.h
+++ b/include/linux/icmpv6.h
@@ -40,16 +40,18 @@ struct icmp6hdr {
                 struct icmpv6_nd_ra {
                         __u8            hop_limit;
 #if defined(__LITTLE_ENDIAN_BITFIELD)
-                        __u8            reserved:4,
+                        __u8            reserved:3,
                                         router_pref:2,
+                                        home_agent:1,
                                         other:1,
                                         managed:1;
 
 #elif defined(__BIG_ENDIAN_BITFIELD)
                         __u8            managed:1,
                                         other:1,
+                                        home_agent:1,
                                         router_pref:2,
-                                        reserved:4;
+                                        reserved:3;
 #else
 #error  "Please fix <asm/byteorder.h>"
 #endif
diff --git a/include/linux/ide.h b/include/linux/ide.h
index 87c12ed96954..c47e371554c1 100644
--- a/include/linux/ide.h
+++ b/include/linux/ide.h
@@ -8,7 +8,7 @@
 
 #include <linux/init.h>
 #include <linux/ioport.h>
-#include <linux/hdreg.h>
+#include <linux/ata.h>
 #include <linux/blkdev.h>
 #include <linux/proc_fs.h>
 #include <linux/interrupt.h>
@@ -17,6 +17,7 @@
 #include <linux/device.h>
 #include <linux/pci.h>
 #include <linux/completion.h>
+#include <linux/pm.h>
 #ifdef CONFIG_BLK_DEV_IDEACPI
 #include <acpi/acpi.h>
 #endif
@@ -47,12 +48,6 @@ typedef unsigned char	byte;	/* used everywhere */
 #define ERROR_RESET     3       /* Reset controller every 4th retry */
 #define ERROR_RECAL     1       /* Recalibrate every 2nd retry */
 
-/*
- * state flags
- */
-
-#define DMA_PIO_RETRY   1       /* retrying in PIO */
-
 #define HWIF(drive)             ((ide_hwif_t *)((drive)->hwif))
 #define HWGROUP(drive)          ((ide_hwgroup_t *)(HWIF(drive)->hwgroup))
 
@@ -87,12 +82,13 @@ struct ide_io_ports {
 };
 
 #define OK_STAT(stat,good,bad)  (((stat)&((good)|(bad)))==(good))
-#define BAD_R_STAT              (BUSY_STAT   | ERR_STAT)
-#define BAD_W_STAT              (BAD_R_STAT  | WRERR_STAT)
-#define BAD_STAT                (BAD_R_STAT  | DRQ_STAT)
-#define DRIVE_READY             (READY_STAT  | SEEK_STAT)
 
-#define BAD_CRC                 (ABRT_ERR    | ICRC_ERR)
+#define BAD_R_STAT      (ATA_BUSY | ATA_ERR)
+#define BAD_W_STAT      (BAD_R_STAT | ATA_DF)
+#define BAD_STAT        (BAD_R_STAT | ATA_DRQ)
+#define DRIVE_READY     (ATA_DRDY | ATA_DSC)
+
+#define BAD_CRC         (ATA_ABORTED | ATA_ICRC)
 
 #define SATA_NR_PORTS           (3)     /* 16 possible ?? */
 
@@ -125,24 +121,43 @@ struct ide_io_ports {
 #define PARTN_BITS      6       /* number of minor dev bits for partitions */
 #define MAX_DRIVES      2       /* per interface; 2 assumed by lots of code */
 #define SECTOR_SIZE     512
-#define SECTOR_WORDS    (SECTOR_SIZE / 4)       /* number of 32bit words per sector */
+
 #define IDE_LARGE_SEEK(b1,b2,t) (((b1) > (b2) + (t)) || ((b2) > (b1) + (t)))
 
 /*
  * Timeouts for various operations:
  */
-#define WAIT_DRQ        (HZ/10)         /* 100msec - spec allows up to 20ms */
-#define WAIT_READY      (5*HZ)          /* 5sec - some laptops are very slow */
-#define WAIT_PIDENTIFY  (10*HZ) /* 10sec  - should be less than 3ms (?), if all ATAPI CD is closed at boot */
-#define WAIT_WORSTCASE  (30*HZ) /* 30sec  - worst case when spinning up */
-#define WAIT_CMD        (10*HZ) /* 10sec  - maximum wait for an IRQ to happen */
-#define WAIT_MIN_SLEEP  (2*HZ/100)      /* 20msec - minimum sleep time */
+enum {
+        /* spec allows up to 20ms */
+        WAIT_DRQ        = HZ / 10,      /* 100ms */
+        /* some laptops are very slow */
+        WAIT_READY      = 5 * HZ,       /* 5s */
+        /* should be less than 3ms (?), if all ATAPI CD is closed at boot */
+        WAIT_PIDENTIFY  = 10 * HZ,      /* 10s */
+        /* worst case when spinning up */
+        WAIT_WORSTCASE  = 30 * HZ,      /* 30s */
+        /* maximum wait for an IRQ to happen */
+        WAIT_CMD        = 10 * HZ,      /* 10s */
+        /* Some drives require a longer IRQ timeout. */
+        WAIT_FLOPPY_CMD = 50 * HZ,      /* 50s */
+        /*
+         * Some drives (for example, Seagate STT3401A Travan) require a very
+         * long timeout, because they don't return an interrupt or clear their
+         * BSY bit until after the command completes (even retension commands).
+         */
+        WAIT_TAPE_CMD   = 900 * HZ,     /* 900s */
+        /* minimum sleep time */
+        WAIT_MIN_SLEEP  = HZ / 50,      /* 20ms */
+};
 
 /*
  * Op codes for special requests to be handled by ide_special_rq().
  * Values should be in the range of 0x20 to 0x3f.
  */
 #define REQ_DRIVE_RESET         0x20
+#define REQ_DEVSET_EXEC         0x21
+#define REQ_PARK_HEADS          0x22
+#define REQ_UNPARK_HEADS        0x23
 
 /*
  * Check for an interrupt and acknowledge the interrupt status
@@ -249,8 +264,6 @@ static inline int __ide_default_irq(unsigned long base)
  * set_geometry : respecify drive geometry
  * recalibrate  : seek to cyl 0
  * set_multmode : set multmode count
- * set_tune     : tune interface for drive
- * serviced     : service command
  * reserved     : unused
  */
 typedef union {
@@ -259,43 +272,11 @@ typedef union {
                 unsigned set_geometry   : 1;
                 unsigned recalibrate    : 1;
                 unsigned set_multmode   : 1;
-                unsigned set_tune       : 1;
-                unsigned serviced       : 1;
-                unsigned reserved       : 3;
+                unsigned reserved       : 5;
         } b;
 } special_t;
 
 /*
- * ATA-IDE Select Register, aka Device-Head
- *
- * head         : always zeros here
- * unit         : drive select number: 0/1
- * bit5         : always 1
- * lba          : using LBA instead of CHS
- * bit7         : always 1
- */
-typedef union {
-        unsigned all                    : 8;
-        struct {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
-                unsigned head           : 4;
-                unsigned unit           : 1;
-                unsigned bit5           : 1;
-                unsigned lba            : 1;
-                unsigned bit7           : 1;
-#elif defined(__BIG_ENDIAN_BITFIELD)
-                unsigned bit7           : 1;
-                unsigned lba            : 1;
-                unsigned bit5           : 1;
-                unsigned unit           : 1;
-                unsigned head           : 4;
-#else
-#error "Please fix <asm/byteorder.h>"
-#endif
-        } b;
-} select_t, ata_select_t;
-
-/*
  * Status returned from various ide_ functions
  */
 typedef enum {
@@ -303,8 +284,177 @@ typedef enum {
         ide_started,    /* a drive operation was started, handler was set */
 } ide_startstop_t;
 
+enum {
+        IDE_TFLAG_LBA48                 = (1 << 0),
+        IDE_TFLAG_FLAGGED               = (1 << 2),
+        IDE_TFLAG_OUT_DATA              = (1 << 3),
+        IDE_TFLAG_OUT_HOB_FEATURE       = (1 << 4),
+        IDE_TFLAG_OUT_HOB_NSECT         = (1 << 5),
+        IDE_TFLAG_OUT_HOB_LBAL          = (1 << 6),
+        IDE_TFLAG_OUT_HOB_LBAM          = (1 << 7),
+        IDE_TFLAG_OUT_HOB_LBAH          = (1 << 8),
+        IDE_TFLAG_OUT_HOB               = IDE_TFLAG_OUT_HOB_FEATURE |
+                                          IDE_TFLAG_OUT_HOB_NSECT |
+                                          IDE_TFLAG_OUT_HOB_LBAL |
+                                          IDE_TFLAG_OUT_HOB_LBAM |
+                                          IDE_TFLAG_OUT_HOB_LBAH,
+        IDE_TFLAG_OUT_FEATURE           = (1 << 9),
+        IDE_TFLAG_OUT_NSECT             = (1 << 10),
+        IDE_TFLAG_OUT_LBAL              = (1 << 11),
+        IDE_TFLAG_OUT_LBAM              = (1 << 12),
+        IDE_TFLAG_OUT_LBAH              = (1 << 13),
+        IDE_TFLAG_OUT_TF                = IDE_TFLAG_OUT_FEATURE |
+                                          IDE_TFLAG_OUT_NSECT |
+                                          IDE_TFLAG_OUT_LBAL |
+                                          IDE_TFLAG_OUT_LBAM |
+                                          IDE_TFLAG_OUT_LBAH,
+        IDE_TFLAG_OUT_DEVICE            = (1 << 14),
+        IDE_TFLAG_WRITE                 = (1 << 15),
+        IDE_TFLAG_FLAGGED_SET_IN_FLAGS  = (1 << 16),
+        IDE_TFLAG_IN_DATA               = (1 << 17),
+        IDE_TFLAG_CUSTOM_HANDLER        = (1 << 18),
+        IDE_TFLAG_DMA_PIO_FALLBACK      = (1 << 19),
+        IDE_TFLAG_IN_HOB_FEATURE        = (1 << 20),
+        IDE_TFLAG_IN_HOB_NSECT          = (1 << 21),
+        IDE_TFLAG_IN_HOB_LBAL           = (1 << 22),
+        IDE_TFLAG_IN_HOB_LBAM           = (1 << 23),
+        IDE_TFLAG_IN_HOB_LBAH           = (1 << 24),
+        IDE_TFLAG_IN_HOB_LBA            = IDE_TFLAG_IN_HOB_LBAL |
+                                          IDE_TFLAG_IN_HOB_LBAM |
+                                          IDE_TFLAG_IN_HOB_LBAH,
+        IDE_TFLAG_IN_HOB                = IDE_TFLAG_IN_HOB_FEATURE |
+                                          IDE_TFLAG_IN_HOB_NSECT |
+                                          IDE_TFLAG_IN_HOB_LBA,
+        IDE_TFLAG_IN_FEATURE            = (1 << 1),
+        IDE_TFLAG_IN_NSECT              = (1 << 25),
+        IDE_TFLAG_IN_LBAL               = (1 << 26),
+        IDE_TFLAG_IN_LBAM               = (1 << 27),
+        IDE_TFLAG_IN_LBAH               = (1 << 28),
+        IDE_TFLAG_IN_LBA                = IDE_TFLAG_IN_LBAL |
+                                          IDE_TFLAG_IN_LBAM |
+                                          IDE_TFLAG_IN_LBAH,
+        IDE_TFLAG_IN_TF                 = IDE_TFLAG_IN_NSECT |
+                                          IDE_TFLAG_IN_LBA,
+        IDE_TFLAG_IN_DEVICE             = (1 << 29),
+        IDE_TFLAG_HOB                   = IDE_TFLAG_OUT_HOB |
+                                          IDE_TFLAG_IN_HOB,
+        IDE_TFLAG_TF                    = IDE_TFLAG_OUT_TF |
+                                          IDE_TFLAG_IN_TF,
+        IDE_TFLAG_DEVICE                = IDE_TFLAG_OUT_DEVICE |
+                                          IDE_TFLAG_IN_DEVICE,
+        /* force 16-bit I/O operations */
+        IDE_TFLAG_IO_16BIT              = (1 << 30),
+        /* ide_task_t was allocated using kmalloc() */
+        IDE_TFLAG_DYN                   = (1 << 31),
+};
+
+struct ide_taskfile {
+        u8      hob_data;       /*  0: high data byte (for TASKFILE IOCTL) */
+
+        u8      hob_feature;    /*  1-5: additional data to support LBA48 */
+        u8      hob_nsect;
+        u8      hob_lbal;
+        u8      hob_lbam;
+        u8      hob_lbah;
+
+        u8      data;           /*  6: low data byte (for TASKFILE IOCTL) */
+
+        union {                 /*  7: */
+                u8 error;       /*   read:  error */
+                u8 feature;     /*  write: feature */
+        };
+
+        u8      nsect;          /*  8: number of sectors */
+        u8      lbal;           /*  9: LBA low */
+        u8      lbam;           /* 10: LBA mid */
+        u8      lbah;           /* 11: LBA high */
+
+        u8      device;         /* 12: device select */
+
+        union {                 /* 13: */
+                u8 status;      /*  read: status  */
+                u8 command;     /* write: command */
+        };
+};
+
+typedef struct ide_task_s {
+        union {
+                struct ide_taskfile     tf;
+                u8                      tf_array[14];
+        };
+        u32                     tf_flags;
+        int                     data_phase;
+        struct request          *rq;            /* copy of request */
+        void                    *special;       /* valid_t generally */
+} ide_task_t;
+
+/* ATAPI packet command flags */
+enum {
+        /* set when an error is considered normal - no retry (ide-tape) */
+        PC_FLAG_ABORT                   = (1 << 0),
+        PC_FLAG_SUPPRESS_ERROR          = (1 << 1),
+        PC_FLAG_WAIT_FOR_DSC            = (1 << 2),
+        PC_FLAG_DMA_OK                  = (1 << 3),
+        PC_FLAG_DMA_IN_PROGRESS         = (1 << 4),
+        PC_FLAG_DMA_ERROR               = (1 << 5),
+        PC_FLAG_WRITING                 = (1 << 6),
+        /* command timed out */
+        PC_FLAG_TIMEDOUT                = (1 << 7),
+};
+
+/*
+ * With each packet command, we allocate a buffer of IDE_PC_BUFFER_SIZE bytes.
+ * This is used for several packet commands (not for READ/WRITE commands).
+ */
+#define IDE_PC_BUFFER_SIZE      256
+
+struct ide_atapi_pc {
+        /* actual packet bytes */
+        u8 c[12];
+        /* incremented on each retry */
+        int retries;
+        int error;
+
+        /* bytes to transfer */
+        int req_xfer;
+        /* bytes actually transferred */
+        int xferred;
+
+        /* data buffer */
+        u8 *buf;
+        /* current buffer position */
+        u8 *cur_pos;
+        int buf_size;
+        /* missing/available data on the current buffer */
+        int b_count;
+
+        /* the corresponding request */
+        struct request *rq;
+
+        unsigned long flags;
+
+        /*
+         * those are more or less driver-specific and some of them are subject
+         * to change/removal later.
+         */
+        u8 pc_buf[IDE_PC_BUFFER_SIZE];
+
+        /* idetape only */
+        struct idetape_bh *bh;
+        char *b_data;
+
+        /* idescsi only for now */
+        struct scatterlist *sg;
+        unsigned int sg_cnt;
+
+        struct scsi_cmnd *scsi_cmd;
+        void (*done) (struct scsi_cmnd *);
+
+        unsigned long timeout;
+};
+
+struct ide_devset;
 struct ide_driver_s;
-struct ide_settings_s;
 
 #ifdef CONFIG_BLK_DEV_IDEACPI
 struct ide_acpi_drive_link;
@@ -315,10 +465,10 @@ struct ide_acpi_hwif_link;
 enum {
         IDE_AFLAG_DRQ_INTERRUPT         = (1 << 0),
         IDE_AFLAG_MEDIA_CHANGED         = (1 << 1),
-
-        /* ide-cd */
         /* Drive cannot lock the door. */
         IDE_AFLAG_NO_DOORLOCK           = (1 << 2),
+
+        /* ide-cd */
         /* Drive cannot eject the disc. */
         IDE_AFLAG_NO_EJECT              = (1 << 3),
         /* Drive is a pre ATAPI 1.2 drive. */
@@ -354,19 +504,81 @@ enum {
         IDE_AFLAG_CLIK_DRIVE            = (1 << 19),
         /* Requires BH algorithm for packets */
         IDE_AFLAG_ZIP_DRIVE             = (1 << 20),
+        /* Write protect */
+        IDE_AFLAG_WP                    = (1 << 21),
+        /* Supports format progress report */
+        IDE_AFLAG_SRFP                  = (1 << 22),
 
         /* ide-tape */
-        IDE_AFLAG_IGNORE_DSC            = (1 << 21),
+        IDE_AFLAG_IGNORE_DSC            = (1 << 23),
         /* 0 When the tape position is unknown */
-        IDE_AFLAG_ADDRESS_VALID         = (1 << 22),
+        IDE_AFLAG_ADDRESS_VALID         = (1 << 24),
         /* Device already opened */
-        IDE_AFLAG_BUSY                  = (1 << 23),
+        IDE_AFLAG_BUSY                  = (1 << 25),
         /* Attempt to auto-detect the current user block size */
-        IDE_AFLAG_DETECT_BS             = (1 << 24),
+        IDE_AFLAG_DETECT_BS             = (1 << 26),
         /* Currently on a filemark */
-        IDE_AFLAG_FILEMARK              = (1 << 25),
+        IDE_AFLAG_FILEMARK              = (1 << 27),
         /* 0 = no tape is loaded, so we don't rewind after ejecting */
-        IDE_AFLAG_MEDIUM_PRESENT        = (1 << 26)
+        IDE_AFLAG_MEDIUM_PRESENT        = (1 << 28),
+
+        IDE_AFLAG_NO_AUTOCLOSE          = (1 << 29),
+};
+
+/* device flags */
+enum {
+        /* restore settings after device reset */
+        IDE_DFLAG_KEEP_SETTINGS         = (1 << 0),
+        /* device is using DMA for read/write */
+        IDE_DFLAG_USING_DMA             = (1 << 1),
+        /* okay to unmask other IRQs */
+        IDE_DFLAG_UNMASK                = (1 << 2),
+        /* don't attempt flushes */
+        IDE_DFLAG_NOFLUSH               = (1 << 3),
+        /* DSC overlap */
+        IDE_DFLAG_DSC_OVERLAP           = (1 << 4),
+        /* give potential excess bandwidth */
+        IDE_DFLAG_NICE1                 = (1 << 5),
+        /* device is physically present */
+        IDE_DFLAG_PRESENT               = (1 << 6),
+        /* device ejected hint */
+        IDE_DFLAG_DEAD                  = (1 << 7),
+        /* id read from device (synthetic if not set) */
+        IDE_DFLAG_ID_READ               = (1 << 8),
+        IDE_DFLAG_NOPROBE               = (1 << 9),
+        /* need to do check_media_change() */
+        IDE_DFLAG_REMOVABLE             = (1 << 10),
+        /* needed for removable devices */
+        IDE_DFLAG_ATTACH                = (1 << 11),
+        IDE_DFLAG_FORCED_GEOM           = (1 << 12),
+        /* disallow setting unmask bit */
+        IDE_DFLAG_NO_UNMASK             = (1 << 13),
+        /* disallow enabling 32-bit I/O */
+        IDE_DFLAG_NO_IO_32BIT           = (1 << 14),
+        /* for removable only: door lock/unlock works */
+        IDE_DFLAG_DOORLOCKING           = (1 << 15),
+        /* disallow DMA */
+        IDE_DFLAG_NODMA                 = (1 << 16),
+        /* powermanagment told us not to do anything, so sleep nicely */
+        IDE_DFLAG_BLOCKED               = (1 << 17),
+        /* ide-scsi emulation */
+        IDE_DFLAG_SCSI                  = (1 << 18),
+        /* sleeping & sleep field valid */
+        IDE_DFLAG_SLEEPING              = (1 << 19),
+        IDE_DFLAG_POST_RESET            = (1 << 20),
+        IDE_DFLAG_UDMA33_WARNED         = (1 << 21),
+        IDE_DFLAG_LBA48                 = (1 << 22),
+        /* status of write cache */
+        IDE_DFLAG_WCACHE                = (1 << 23),
+        /* used for ignoring ATA_DF */
+        IDE_DFLAG_NOWERR                = (1 << 24),
+        /* retrying in PIO */
+        IDE_DFLAG_DMA_PIO_RETRY         = (1 << 25),
+        IDE_DFLAG_LBA                   = (1 << 26),
+        /* don't unload heads */
+        IDE_DFLAG_NO_UNLOAD             = (1 << 27),
+        /* heads unloaded, please don't reset port */
+        IDE_DFLAG_PARKED                = (1 << 28)
 };
 
 struct ide_drive_s {
@@ -378,72 +590,47 @@ struct ide_drive_s {
         struct request          *rq;    /* current request */
         struct ide_drive_s      *next;  /* circular list of hwgroup drives */
         void            *driver_data;   /* extra driver data */
-        struct hd_driveid       *id;    /* drive model identification info */
+        u16                     *id;    /* identification info */
 #ifdef CONFIG_IDE_PROC_FS
         struct proc_dir_entry *proc;    /* /proc/ide/ directory entry */
-        struct ide_settings_s *settings;/* /proc/ide/ drive settings */
+        const struct ide_proc_devset *settings; /* /proc/ide/ drive settings */
 #endif
         struct hwif_s           *hwif;  /* actually (ide_hwif_t *) */
 
+        unsigned long dev_flags;
+
         unsigned long sleep;            /* sleep until this time */
         unsigned long service_start;    /* time we started last request */
         unsigned long service_time;     /* service time of last request */
         unsigned long timeout;          /* max time to wait for irq */
 
         special_t       special;        /* special action flags */
-        select_t        select;         /* basic drive/head select reg value */
 
-        u8      keep_settings;          /* restore settings after drive reset */
-        u8      using_dma;              /* disk is using dma for read/write */
+        u8      select;                 /* basic drive/head select reg value */
         u8      retry_pio;              /* retrying dma capable host in pio */
-        u8      state;                  /* retry state */
         u8      waiting_for_dma;        /* dma currently in progress */
-        u8      unmask;                 /* okay to unmask other irqs */
-        u8      noflush;                /* don't attempt flushes */
-        u8      dsc_overlap;            /* DSC overlap */
-        u8      nice1;                  /* give potential excess bandwidth */
-
-        unsigned present        : 1;    /* drive is physically present */
-        unsigned dead           : 1;    /* device ejected hint */
-        unsigned id_read        : 1;    /* 1=id read from disk 0 = synthetic */
-        unsigned noprobe        : 1;    /* from:  hdx=noprobe */
-        unsigned removable      : 1;    /* 1 if need to do check_media_change */
-        unsigned attach         : 1;    /* needed for removable devices */
-        unsigned forced_geom    : 1;    /* 1 if hdx=c,h,s was given at boot */
-        unsigned no_unmask      : 1;    /* disallow setting unmask bit */
-        unsigned no_io_32bit    : 1;    /* disallow enabling 32bit I/O */
-        unsigned atapi_overlap  : 1;    /* ATAPI overlap (not supported) */
-        unsigned doorlocking    : 1;    /* for removable only: door lock/unlock works */
-        unsigned nodma          : 1;    /* disallow DMA */
-        unsigned remap_0_to_1   : 1;    /* 0=noremap, 1=remap 0->1 (for EZDrive) */
-        unsigned blocked        : 1;    /* 1=powermanagment told us not to do anything, so sleep nicely */
-        unsigned scsi           : 1;    /* 0=default, 1=ide-scsi emulation */
-        unsigned sleeping       : 1;    /* 1=sleeping & sleep field valid */
-        unsigned post_reset     : 1;
-        unsigned udma33_warned  : 1;
-
-        u8      addressing;     /* 0=28-bit, 1=48-bit, 2=48-bit doing 28-bit */
+        u8      dma;                    /* atapi dma flag */
+
         u8      quirk_list;     /* considered quirky, set for a specific host */
         u8      init_speed;     /* transfer rate set at boot */
         u8      current_speed;  /* current transfer rate set */
         u8      desired_speed;  /* desired transfer rate set */
         u8      dn;             /* now wide spread use */
-        u8      wcache;         /* status of write cache */
         u8      acoustic;       /* acoustic management */
         u8      media;          /* disk, cdrom, tape, floppy, ... */
         u8      ready_stat;     /* min status value for drive ready */
         u8      mult_count;     /* current multiple sector setting */
         u8      mult_req;       /* requested multiple sector setting */
-        u8      tune_req;       /* requested drive tuning setting */
         u8      io_32bit;       /* 0=16-bit, 1=32-bit, 2/3=32bit+sync */
-        u8      bad_wstat;      /* used for ignoring WRERR_STAT */
-        u8      nowerr;         /* used for ignoring WRERR_STAT */
-        u8      sect0;          /* offset of first sector for DM6:DDO */
+        u8      bad_wstat;      /* used for ignoring ATA_DF */
         u8      head;           /* "real" number of heads */
         u8      sect;           /* "real" sectors per track */
         u8      bios_head;      /* BIOS/fdisk/LILO number of heads */
         u8      bios_sect;      /* BIOS/fdisk/LILO sectors per track */
 
+        /* delay this long before sending packet command */
+        u8 pc_delay;
+
         unsigned int    bios_cyl;       /* BIOS/fdisk/LILO number of cyls */
         unsigned int    cyl;            /* "real" number of cyls */
         unsigned int    drive_data;     /* used by set_pio_mode/selectproc */
@@ -455,6 +642,9 @@ struct ide_drive_s {
 
         int             lun;            /* logical unit */
         int             crc_count;      /* crc counter to reduce drive speed */
+
+        unsigned long   debug_mask;     /* debugging levels switch */
+
 #ifdef CONFIG_BLK_DEV_IDEACPI
         struct ide_acpi_drive_link *acpidata;
 #endif
@@ -462,21 +652,32 @@ struct ide_drive_s {
         struct device   gendev;
         struct completion gendev_rel_comp;      /* to deal with device release() */
 
+        /* current packet command */
+        struct ide_atapi_pc *pc;
+
         /* callback for packet commands */
-        void (*pc_callback)(struct ide_drive_s *);
+        void (*pc_callback)(struct ide_drive_s *, int);
+
+        void (*pc_update_buffers)(struct ide_drive_s *, struct ide_atapi_pc *);
+        int  (*pc_io_buffers)(struct ide_drive_s *, struct ide_atapi_pc *,
+                              unsigned int, int);
 
         unsigned long atapi_flags;
+
+        struct ide_atapi_pc request_sense_pc;
+        struct request request_sense_rq;
 };
 
 typedef struct ide_drive_s ide_drive_t;
 
-#define to_ide_device(dev)container_of(dev, ide_drive_t, gendev)
+#define to_ide_device(dev)              container_of(dev, ide_drive_t, gendev)
 
-#define IDE_CHIPSET_PCI_MASK    \
-    ((1<<ide_pci)|(1<<ide_cmd646)|(1<<ide_ali14xx))
-#define IDE_CHIPSET_IS_PCI(c)   ((IDE_CHIPSET_PCI_MASK >> (c)) & 1)
+#define to_ide_drv(obj, cont_type)      \
+        container_of(obj, struct cont_type, kref)
+
+#define ide_drv_g(disk, cont_type)      \
+        container_of((disk)->private_data, struct cont_type, driver)
 
-struct ide_task_s;
 struct ide_port_info;
 
 struct ide_tp_ops {
@@ -510,6 +711,7 @@ extern const struct ide_tp_ops default_tp_ops;
  * @resetproc:          routine to reset controller after a disk reset
  * @maskproc:           special host masking for drive selection
  * @quirkproc:          check host's drive quirk list
+ * @clear_irq:          clear IRQ
  *
  * @mdma_filter:        filter MDMA modes
  * @udma_filter:        filter UDMA modes
@@ -526,6 +728,7 @@ struct ide_port_ops {
         void    (*resetproc)(ide_drive_t *);
         void    (*maskproc)(ide_drive_t *, int);
         void    (*quirkproc)(ide_drive_t *);
+        void    (*clear_irq)(ide_drive_t *);
 
         u8      (*mdma_filter)(ide_drive_t *);
         u8      (*udma_filter)(ide_drive_t *);
@@ -565,7 +768,6 @@ typedef struct hwif_s {
         u8 major;       /* our major number */
         u8 index;       /* 0 for ide0; 1 for ide1; ... */
         u8 channel;     /* for dual-port chips: 0=primary, 1=secondary */
-        u8 bus_state;   /* power state of the IDE bus */
 
         u32 host_flags;
 
@@ -589,12 +791,16 @@ typedef struct hwif_s {
         const struct ide_port_ops       *port_ops;
         const struct ide_dma_ops        *dma_ops;
 
-        void (*ide_dma_clear_irq)(ide_drive_t *drive);
-
         /* dma physical region descriptor table (cpu view) */
         unsigned int    *dmatable_cpu;
         /* dma physical region descriptor table (dma view) */
         dma_addr_t      dmatable_dma;
+
+        /* maximum number of PRD table entries */
+        int prd_max_nents;
+        /* PRD entry size in bytes */
+        int prd_ent_size;
+
         /* Scatter-gather list used to build the above */
         struct scatterlist *sg_table;
         int sg_max_nents;               /* Maximum number of entries in it */
@@ -604,6 +810,8 @@ typedef struct hwif_s {
         /* data phase of the active command (currently only valid for PIO/DMA) */
         int             data_phase;
 
+        struct ide_task_s task;         /* current command */
+
         unsigned int nsect;
         unsigned int nleft;
         struct scatterlist *cursg;
@@ -632,17 +840,18 @@ typedef struct hwif_s {
 
         void            *hwif_data;     /* extra hwif data */
 
-        unsigned dma;
-
 #ifdef CONFIG_BLK_DEV_IDEACPI
         struct ide_acpi_hwif_link *acpidata;
 #endif
 } ____cacheline_internodealigned_in_smp ide_hwif_t;
 
+#define MAX_HOST_PORTS 4
+
 struct ide_host {
-        ide_hwif_t      *ports[MAX_HWIFS];
+        ide_hwif_t      *ports[MAX_HOST_PORTS];
         unsigned int    n_ports;
         struct device   *dev[2];
+        unsigned int    (*init_chipset)(struct pci_dev *);
         unsigned long   host_flags;
         void            *host_priv;
 };
@@ -690,102 +899,116 @@ typedef struct ide_driver_s ide_driver_t;
 
 extern struct mutex ide_setting_mtx;
 
-int set_io_32bit(ide_drive_t *, int);
-int set_pio_mode(ide_drive_t *, int);
-int set_using_dma(ide_drive_t *, int);
+/*
+ * configurable drive settings
+ */
 
-/* ATAPI packet command flags */
-enum {
-        /* set when an error is considered normal - no retry (ide-tape) */
-        PC_FLAG_ABORT                   = (1 << 0),
-        PC_FLAG_SUPPRESS_ERROR          = (1 << 1),
-        PC_FLAG_WAIT_FOR_DSC            = (1 << 2),
-        PC_FLAG_DMA_OK                  = (1 << 3),
-        PC_FLAG_DMA_IN_PROGRESS         = (1 << 4),
-        PC_FLAG_DMA_ERROR               = (1 << 5),
-        PC_FLAG_WRITING                 = (1 << 6),
-        /* command timed out */
-        PC_FLAG_TIMEDOUT                = (1 << 7),
+#define DS_SYNC (1 << 0)
+
+struct ide_devset {
+        int             (*get)(ide_drive_t *);
+        int             (*set)(ide_drive_t *, int);
+        unsigned int    flags;
 };
 
-struct ide_atapi_pc {
-        /* actual packet bytes */
-        u8 c[12];
-        /* incremented on each retry */
-        int retries;
-        int error;
+#define __DEVSET(_flags, _get, _set) { \
+        .flags  = _flags, \
+        .get    = _get, \
+        .set    = _set, \
+}
 
-        /* bytes to transfer */
-        int req_xfer;
-        /* bytes actually transferred */
-        int xferred;
+#define ide_devset_get(name, field) \
+static int get_##name(ide_drive_t *drive) \
+{ \
+        return drive->field; \
+}
 
-        /* data buffer */
-        u8 *buf;
-        /* current buffer position */
-        u8 *cur_pos;
-        int buf_size;
-        /* missing/available data on the current buffer */
-        int b_count;
+#define ide_devset_set(name, field) \
+static int set_##name(ide_drive_t *drive, int arg) \
+{ \
+        drive->field = arg; \
+        return 0; \
+}
 
-        /* the corresponding request */
-        struct request *rq;
+#define ide_devset_get_flag(name, flag) \
+static int get_##name(ide_drive_t *drive) \
+{ \
+        return !!(drive->dev_flags & flag); \
+}
 
-        unsigned long flags;
+#define ide_devset_set_flag(name, flag) \
+static int set_##name(ide_drive_t *drive, int arg) \
+{ \
+        if (arg) \
+                drive->dev_flags |= flag; \
+        else \
+                drive->dev_flags &= ~flag; \
+        return 0; \
+}
 
-        /*
-         * those are more or less driver-specific and some of them are subject
-         * to change/removal later.
-         */
-        u8 pc_buf[256];
+#define __IDE_DEVSET(_name, _flags, _get, _set) \
+const struct ide_devset ide_devset_##_name = \
+        __DEVSET(_flags, _get, _set)
 
-        /* idetape only */
-        struct idetape_bh *bh;
-        char *b_data;
+#define IDE_DEVSET(_name, _flags, _get, _set) \
+static __IDE_DEVSET(_name, _flags, _get, _set)
 
-        /* idescsi only for now */
-        struct scatterlist *sg;
-        unsigned int sg_cnt;
+#define ide_devset_rw(_name, _func) \
+IDE_DEVSET(_name, 0, get_##_func, set_##_func)
 
-        struct scsi_cmnd *scsi_cmd;
-        void (*done) (struct scsi_cmnd *);
+#define ide_devset_w(_name, _func) \
+IDE_DEVSET(_name, 0, NULL, set_##_func)
 
-        unsigned long timeout;
-};
+#define ide_ext_devset_rw(_name, _func) \
+__IDE_DEVSET(_name, 0, get_##_func, set_##_func)
+
+#define ide_ext_devset_rw_sync(_name, _func) \
+__IDE_DEVSET(_name, DS_SYNC, get_##_func, set_##_func)
+
+#define ide_decl_devset(_name) \
+extern const struct ide_devset ide_devset_##_name
+
+ide_decl_devset(io_32bit);
+ide_decl_devset(keepsettings);
+ide_decl_devset(pio_mode);
+ide_decl_devset(unmaskirq);
+ide_decl_devset(using_dma);
 
 #ifdef CONFIG_IDE_PROC_FS
 /*
- * configurable drive settings
+ * /proc/ide interface
  */
 
-#define TYPE_INT        0
-#define TYPE_BYTE       1
-#define TYPE_SHORT      2
+#define ide_devset_rw_field(_name, _field) \
+ide_devset_get(_name, _field); \
+ide_devset_set(_name, _field); \
+IDE_DEVSET(_name, DS_SYNC, get_##_name, set_##_name)
+
+#define ide_devset_rw_flag(_name, _field) \
+ide_devset_get_flag(_name, _field); \
+ide_devset_set_flag(_name, _field); \
+IDE_DEVSET(_name, DS_SYNC, get_##_name, set_##_name)
+
+struct ide_proc_devset {
+        const char              *name;
+        const struct ide_devset *setting;
+        int                     min, max;
+        int                     (*mulf)(ide_drive_t *);
+        int                     (*divf)(ide_drive_t *);
+};
 
-#define SETTING_READ    (1 << 0)
-#define SETTING_WRITE   (1 << 1)
-#define SETTING_RW      (SETTING_READ | SETTING_WRITE)
+#define __IDE_PROC_DEVSET(_name, _min, _max, _mulf, _divf) { \
+        .name = __stringify(_name), \
+        .setting = &ide_devset_##_name, \
+        .min = _min, \
+        .max = _max, \
+        .mulf = _mulf, \
+        .divf = _divf, \
+}
 
-typedef int (ide_procset_t)(ide_drive_t *, int);
-typedef struct ide_settings_s {
-        char                    *name;
-        int                     rw;
-        int                     data_type;
-        int                     min;
-        int                     max;
-        int                     mul_factor;
-        int                     div_factor;
-        void                    *data;
-        ide_procset_t           *set;
-        int                     auto_remove;
-        struct ide_settings_s   *next;
-} ide_settings_t;
-
-int ide_add_setting(ide_drive_t *, const char *, int, int, int, int, int, int, void *, ide_procset_t *set);
+#define IDE_PROC_DEVSET(_name, _min, _max) \
+__IDE_PROC_DEVSET(_name, _min, _max, NULL, NULL)
 
-/*
- * /proc/ide interface
- */
 typedef struct {
         const char      *name;
         mode_t          mode;
@@ -802,8 +1025,6 @@ void ide_proc_unregister_port(ide_hwif_t *);
 void ide_proc_register_driver(ide_drive_t *, ide_driver_t *);
 void ide_proc_unregister_driver(ide_drive_t *, ide_driver_t *);
 
-void ide_add_generic_settings(ide_drive_t *);
-
 read_proc_t proc_ide_read_capacity;
 read_proc_t proc_ide_read_geometry;
 
@@ -831,41 +1052,58 @@ static inline void ide_proc_unregister_device(ide_drive_t *drive) { ; }
 static inline void ide_proc_unregister_port(ide_hwif_t *hwif) { ; }
 static inline void ide_proc_register_driver(ide_drive_t *drive, ide_driver_t *driver) { ; }
 static inline void ide_proc_unregister_driver(ide_drive_t *drive, ide_driver_t *driver) { ; }
-static inline void ide_add_generic_settings(ide_drive_t *drive) { ; }
 #define PROC_IDE_READ_RETURN(page,start,off,count,eof,len) return 0;
 #endif
 
+enum {
+        /* enter/exit functions */
+        IDE_DBG_FUNC =                  (1 << 0),
+        /* sense key/asc handling */
+        IDE_DBG_SENSE =                 (1 << 1),
+        /* packet commands handling */
+        IDE_DBG_PC =                    (1 << 2),
+        /* request handling */
+        IDE_DBG_RQ =                    (1 << 3),
+        /* driver probing/setup */
+        IDE_DBG_PROBE =                 (1 << 4),
+};
+
+/* DRV_NAME has to be defined in the driver before using the macro below */
+#define __ide_debug_log(lvl, fmt, args...)                      \
+{                                                               \
+        if (unlikely(drive->debug_mask & lvl))                  \
+                printk(KERN_INFO DRV_NAME ": " fmt, ## args);   \
+}
+
 /*
- * Power Management step value (rq->pm->pm_step).
- *
- * The step value starts at 0 (ide_pm_state_start_suspend) for a
- * suspend operation or 1000 (ide_pm_state_start_resume) for a
- * resume operation.
+ * Power Management state machine (rq->pm->pm_step).
  *
- * For each step, the core calls the subdriver start_power_step() first.
+ * For each step, the core calls ide_start_power_step() first.
  * This can return:
  *      - ide_stopped : In this case, the core calls us back again unless
  *                      step have been set to ide_power_state_completed.
  *      - ide_started : In this case, the channel is left busy until an
  *                      async event (interrupt) occurs.
- * Typically, start_power_step() will issue a taskfile request with
+ * Typically, ide_start_power_step() will issue a taskfile request with
  * do_rw_taskfile().
  *
- * Upon reception of the interrupt, the core will call complete_power_step()
+ * Upon reception of the interrupt, the core will call ide_complete_power_step()
  * with the error code if any. This routine should update the step value
  * and return. It should not start a new request. The core will call
- * start_power_step for the new step value, unless step have been set to
- * ide_power_state_completed.
- *
- * Subdrivers are expected to define their own additional power
- * steps from 1..999 for suspend and from 1001..1999 for resume,
- * other values are reserved for future use.
+ * ide_start_power_step() for the new step value, unless step have been
+ * set to IDE_PM_COMPLETED.
  */
-
 enum {
-        ide_pm_state_completed          = -1,
-        ide_pm_state_start_suspend      = 0,
-        ide_pm_state_start_resume       = 1000,
+        IDE_PM_START_SUSPEND,
+        IDE_PM_FLUSH_CACHE      = IDE_PM_START_SUSPEND,
+        IDE_PM_STANDBY,
+
+        IDE_PM_START_RESUME,
+        IDE_PM_RESTORE_PIO      = IDE_PM_START_RESUME,
+        IDE_PM_IDLE,
+        IDE_PM_RESTORE_DMA,
+
+        IDE_PM_COMPLETED,
 };
 
 /*
@@ -876,8 +1114,6 @@ enum {
  */
 struct ide_driver_s {
         const char                      *version;
-        u8                              media;
-        unsigned supports_dsc_overlap   : 1;
         ide_startstop_t (*do_request)(ide_drive_t *, struct request *, sector_t);
         int             (*end_request)(ide_drive_t *, int, int);
         ide_startstop_t (*error)(ide_drive_t *, struct request *rq, u8, u8);
@@ -887,7 +1123,8 @@ struct ide_driver_s {
         void            (*resume)(ide_drive_t *);
         void            (*shutdown)(ide_drive_t *);
 #ifdef CONFIG_IDE_PROC_FS
-        ide_proc_entry_t        *proc;
+        ide_proc_entry_t                *proc;
+        const struct ide_proc_devset    *settings;
 #endif
 };
 
@@ -896,7 +1133,17 @@ struct ide_driver_s {
 int ide_device_get(ide_drive_t *);
 void ide_device_put(ide_drive_t *);
 
-int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *, unsigned, unsigned long);
+struct ide_ioctl_devset {
+        unsigned int    get_ioctl;
+        unsigned int    set_ioctl;
+        const struct ide_devset *setting;
+};
+
+int ide_setting_ioctl(ide_drive_t *, struct block_device *, unsigned int,
+                      unsigned long, const struct ide_ioctl_devset *);
+
+int generic_ide_ioctl(ide_drive_t *, struct file *, struct block_device *,
+                      unsigned, unsigned long);
 
 extern int ide_vlb_clk;
 extern int ide_pci_clk;
@@ -918,122 +1165,23 @@ ide_startstop_t __ide_error(ide_drive_t *, struct request *, u8, u8);
 
 ide_startstop_t ide_error (ide_drive_t *drive, const char *msg, byte stat);
 
-extern void ide_fix_driveid(struct hd_driveid *);
+void ide_fix_driveid(u16 *);
 
 extern void ide_fixstring(u8 *, const int, const int);
 
+int ide_busy_sleep(ide_hwif_t *, unsigned long, int);
+
 int ide_wait_stat(ide_startstop_t *, ide_drive_t *, u8, u8, unsigned long);
 
 extern ide_startstop_t ide_do_reset (ide_drive_t *);
 
+extern int ide_devset_execute(ide_drive_t *drive,
+                              const struct ide_devset *setting, int arg);
+
 extern void ide_do_drive_cmd(ide_drive_t *, struct request *);
 
 extern void ide_end_drive_cmd(ide_drive_t *, u8, u8);
 
-enum {
-        IDE_TFLAG_LBA48                 = (1 << 0),
-        IDE_TFLAG_FLAGGED               = (1 << 2),
-        IDE_TFLAG_OUT_DATA              = (1 << 3),
-        IDE_TFLAG_OUT_HOB_FEATURE       = (1 << 4),
-        IDE_TFLAG_OUT_HOB_NSECT         = (1 << 5),
-        IDE_TFLAG_OUT_HOB_LBAL          = (1 << 6),
-        IDE_TFLAG_OUT_HOB_LBAM          = (1 << 7),
-        IDE_TFLAG_OUT_HOB_LBAH          = (1 << 8),
-        IDE_TFLAG_OUT_HOB               = IDE_TFLAG_OUT_HOB_FEATURE |
-                                          IDE_TFLAG_OUT_HOB_NSECT |
-                                          IDE_TFLAG_OUT_HOB_LBAL |
-                                          IDE_TFLAG_OUT_HOB_LBAM |
-                                          IDE_TFLAG_OUT_HOB_LBAH,
-        IDE_TFLAG_OUT_FEATURE           = (1 << 9),
-        IDE_TFLAG_OUT_NSECT             = (1 << 10),
-        IDE_TFLAG_OUT_LBAL              = (1 << 11),
-        IDE_TFLAG_OUT_LBAM              = (1 << 12),
-        IDE_TFLAG_OUT_LBAH              = (1 << 13),
-        IDE_TFLAG_OUT_TF                = IDE_TFLAG_OUT_FEATURE |
-                                          IDE_TFLAG_OUT_NSECT |
-                                          IDE_TFLAG_OUT_LBAL |
-                                          IDE_TFLAG_OUT_LBAM |
-                                          IDE_TFLAG_OUT_LBAH,
-        IDE_TFLAG_OUT_DEVICE            = (1 << 14),
-        IDE_TFLAG_WRITE                 = (1 << 15),
-        IDE_TFLAG_FLAGGED_SET_IN_FLAGS  = (1 << 16),
-        IDE_TFLAG_IN_DATA               = (1 << 17),
-        IDE_TFLAG_CUSTOM_HANDLER        = (1 << 18),
-        IDE_TFLAG_DMA_PIO_FALLBACK      = (1 << 19),
-        IDE_TFLAG_IN_HOB_FEATURE        = (1 << 20),
-        IDE_TFLAG_IN_HOB_NSECT          = (1 << 21),
-        IDE_TFLAG_IN_HOB_LBAL           = (1 << 22),
-        IDE_TFLAG_IN_HOB_LBAM           = (1 << 23),
-        IDE_TFLAG_IN_HOB_LBAH           = (1 << 24),
-        IDE_TFLAG_IN_HOB_LBA            = IDE_TFLAG_IN_HOB_LBAL |
-                                          IDE_TFLAG_IN_HOB_LBAM |
-                                          IDE_TFLAG_IN_HOB_LBAH,
-        IDE_TFLAG_IN_HOB                = IDE_TFLAG_IN_HOB_FEATURE |
-                                          IDE_TFLAG_IN_HOB_NSECT |
-                                          IDE_TFLAG_IN_HOB_LBA,
-        IDE_TFLAG_IN_FEATURE            = (1 << 1),
-        IDE_TFLAG_IN_NSECT              = (1 << 25),
-        IDE_TFLAG_IN_LBAL               = (1 << 26),
-        IDE_TFLAG_IN_LBAM               = (1 << 27),
-        IDE_TFLAG_IN_LBAH               = (1 << 28),
-        IDE_TFLAG_IN_LBA                = IDE_TFLAG_IN_LBAL |
-                                          IDE_TFLAG_IN_LBAM |
-                                          IDE_TFLAG_IN_LBAH,
-        IDE_TFLAG_IN_TF                 = IDE_TFLAG_IN_NSECT |
-                                          IDE_TFLAG_IN_LBA,
-        IDE_TFLAG_IN_DEVICE             = (1 << 29),
-        IDE_TFLAG_HOB                   = IDE_TFLAG_OUT_HOB |
-                                          IDE_TFLAG_IN_HOB,
-        IDE_TFLAG_TF                    = IDE_TFLAG_OUT_TF |
-                                          IDE_TFLAG_IN_TF,
-        IDE_TFLAG_DEVICE                = IDE_TFLAG_OUT_DEVICE |
-                                          IDE_TFLAG_IN_DEVICE,
-        /* force 16-bit I/O operations */
-        IDE_TFLAG_IO_16BIT              = (1 << 30),
-        /* ide_task_t was allocated using kmalloc() */
-        IDE_TFLAG_DYN                   = (1 << 31),
-};
-
-struct ide_taskfile {
-        u8      hob_data;       /*  0: high data byte (for TASKFILE IOCTL) */
-
-        u8      hob_feature;    /*  1-5: additional data to support LBA48 */
-        u8      hob_nsect;
-        u8      hob_lbal;
-        u8      hob_lbam;
-        u8      hob_lbah;
-
-        u8      data;           /*  6: low data byte (for TASKFILE IOCTL) */
-
-        union {                 /*  7: */
-                u8 error;       /*   read:  error */
-                u8 feature;     /*  write: feature */
-        };
-
-        u8      nsect;          /*  8: number of sectors */
-        u8      lbal;           /*  9: LBA low */
-        u8      lbam;           /* 10: LBA mid */
-        u8      lbah;           /* 11: LBA high */
-
-        u8      device;         /* 12: device select */
-
-        union {                 /* 13: */
-                u8 status;      /*  read: status  */
-                u8 command;     /* write: command */
-        };
-};
-
-typedef struct ide_task_s {
-        union {
-                struct ide_taskfile     tf;
-                u8                      tf_array[14];
-        };
-        u32                     tf_flags;
-        int                     data_phase;
-        struct request          *rq;            /* copy of request */
-        void                    *special;       /* valid_t generally */
-} ide_task_t;
-
 void ide_tf_dump(const char *, struct ide_taskfile *);
 
 void ide_exec_command(ide_hwif_t *, u8);
@@ -1049,6 +1197,8 @@ void ide_tf_read(ide_drive_t *, ide_task_t *);
 void ide_input_data(ide_drive_t *, struct request *, void *, unsigned int);
 void ide_output_data(ide_drive_t *, struct request *, void *, unsigned int);
 
+int ide_io_buffers(ide_drive_t *, struct ide_atapi_pc *, unsigned int, int);
+
 extern void SELECT_DRIVE(ide_drive_t *);
 void SELECT_MASK(ide_drive_t *, int);
 
@@ -1059,16 +1209,46 @@ extern int drive_is_ready(ide_drive_t *);
 
 void ide_pktcmd_tf_load(ide_drive_t *, u32, u16, u8);
 
-ide_startstop_t ide_pc_intr(ide_drive_t *drive, struct ide_atapi_pc *pc,
-        ide_handler_t *handler, unsigned int timeout, ide_expiry_t *expiry,
-        void (*update_buffers)(ide_drive_t *, struct ide_atapi_pc *),
-        void (*retry_pc)(ide_drive_t *), void (*dsc_handle)(ide_drive_t *),
-        void (*io_buffers)(ide_drive_t *, struct ide_atapi_pc *, unsigned int,
-                           int));
-ide_startstop_t ide_transfer_pc(ide_drive_t *, struct ide_atapi_pc *,
-                                ide_handler_t *, unsigned int, ide_expiry_t *);
-ide_startstop_t ide_issue_pc(ide_drive_t *, struct ide_atapi_pc *,
-                             ide_handler_t *, unsigned int, ide_expiry_t *);
+int ide_check_atapi_device(ide_drive_t *, const char *);
+
+void ide_init_pc(struct ide_atapi_pc *);
+
+/* Disk head parking */
+extern wait_queue_head_t ide_park_wq;
+ssize_t ide_park_show(struct device *dev, struct device_attribute *attr,
+                      char *buf);
+ssize_t ide_park_store(struct device *dev, struct device_attribute *attr,
+                       const char *buf, size_t len);
+
+/*
+ * Special requests for ide-tape block device strategy routine.
+ *
+ * In order to service a character device command, we add special requests to
+ * the tail of our block device request queue and wait for their completion.
+ */
+enum {
+        REQ_IDETAPE_PC1         = (1 << 0), /* packet command (first stage) */
+        REQ_IDETAPE_PC2         = (1 << 1), /* packet command (second stage) */
+        REQ_IDETAPE_READ        = (1 << 2),
+        REQ_IDETAPE_WRITE       = (1 << 3),
+};
+
+int ide_queue_pc_tail(ide_drive_t *, struct gendisk *, struct ide_atapi_pc *);
+
+int ide_do_test_unit_ready(ide_drive_t *, struct gendisk *);
+int ide_do_start_stop(ide_drive_t *, struct gendisk *, int);
+int ide_set_media_lock(ide_drive_t *, struct gendisk *, int);
+void ide_create_request_sense_cmd(ide_drive_t *, struct ide_atapi_pc *);
+void ide_retry_pc(ide_drive_t *, struct gendisk *);
+
+static inline unsigned long ide_scsi_get_timeout(struct ide_atapi_pc *pc)
+{
+        return max_t(unsigned long, WAIT_CMD, pc->timeout - jiffies);
+}
+
+int ide_scsi_expiry(ide_drive_t *);
+
+ide_startstop_t ide_issue_pc(ide_drive_t *, unsigned int, ide_expiry_t *);
 
 ide_startstop_t do_rw_taskfile(ide_drive_t *, ide_task_t *);
 
@@ -1078,8 +1258,6 @@ int ide_raw_taskfile(ide_drive_t *, ide_task_t *, u8 *, u16);
 int ide_no_data_taskfile(ide_drive_t *, ide_task_t *);
 
 int ide_taskfile_ioctl(ide_drive_t *, unsigned int, unsigned long);
-int ide_cmd_ioctl(ide_drive_t *, unsigned int, unsigned long);
-int ide_task_ioctl(ide_drive_t *, unsigned int, unsigned long);
 
 extern int ide_driveid_update(ide_drive_t *);
 extern int ide_config_drive_speed(ide_drive_t *, u8);
@@ -1090,7 +1268,6 @@ extern int ide_wait_not_busy(ide_hwif_t *hwif, unsigned long timeout);
 
 extern void ide_stall_queue(ide_drive_t *drive, unsigned long timeout);
 
-extern int ide_spin_wait_hwgroup(ide_drive_t *);
 extern void ide_timer_expiry(unsigned long);
 extern irqreturn_t ide_intr(int irq, void *dev_id);
 extern void do_ide_request(struct request_queue *);
@@ -1111,7 +1288,6 @@ void ide_setup_pci_noise(struct pci_dev *, const struct ide_port_info *);
 #ifdef CONFIG_BLK_DEV_IDEDMA_PCI
 int ide_pci_set_master(struct pci_dev *, const char *);
 unsigned long ide_pci_dma_base(ide_hwif_t *, const struct ide_port_info *);
-extern const struct ide_dma_ops sff_dma_ops;
 int ide_pci_check_simplex(ide_hwif_t *, const struct ide_port_info *);
 int ide_hwif_setup_dma(ide_hwif_t *, const struct ide_port_info *);
 #else
@@ -1228,6 +1404,14 @@ int ide_pci_init_two(struct pci_dev *, struct pci_dev *,
                      const struct ide_port_info *, void *);
 void ide_pci_remove(struct pci_dev *);
 
+#ifdef CONFIG_PM
+int ide_pci_suspend(struct pci_dev *, pm_message_t);
+int ide_pci_resume(struct pci_dev *);
+#else
+#define ide_pci_suspend NULL
+#define ide_pci_resume NULL
+#endif
+
 void ide_map_sg(ide_drive_t *, struct request *);
 void ide_init_sg_cmd(ide_drive_t *, struct request *);
 
@@ -1239,9 +1423,10 @@ struct drive_list_entry {
         const char *id_firmware;
 };
 
-int ide_in_drive_list(struct hd_driveid *, const struct drive_list_entry *);
+int ide_in_drive_list(u16 *, const struct drive_list_entry *);
 
 #ifdef CONFIG_BLK_DEV_IDEDMA
+int ide_dma_good_drive(ide_drive_t *);
 int __ide_dma_bad_drive(ide_drive_t *);
 int ide_id_dma_bug(ide_drive_t *);
 
@@ -1259,24 +1444,29 @@ int ide_set_dma(ide_drive_t *);
 void ide_check_dma_crc(ide_drive_t *);
 ide_startstop_t ide_dma_intr(ide_drive_t *);
 
+int ide_allocate_dma_engine(ide_hwif_t *);
+void ide_release_dma_engine(ide_hwif_t *);
+
 int ide_build_sglist(ide_drive_t *, struct request *);
 void ide_destroy_dmatable(ide_drive_t *);
 
 #ifdef CONFIG_BLK_DEV_IDEDMA_SFF
+int config_drive_for_dma(ide_drive_t *);
 extern int ide_build_dmatable(ide_drive_t *, struct request *);
-int ide_allocate_dma_engine(ide_hwif_t *);
-void ide_release_dma_engine(ide_hwif_t *);
-
 void ide_dma_host_set(ide_drive_t *, int);
 extern int ide_dma_setup(ide_drive_t *);
 void ide_dma_exec_cmd(ide_drive_t *, u8);
 extern void ide_dma_start(ide_drive_t *);
-extern int __ide_dma_end(ide_drive_t *);
+int ide_dma_end(ide_drive_t *);
 int ide_dma_test_irq(ide_drive_t *);
-extern void ide_dma_lost_irq(ide_drive_t *);
-extern void ide_dma_timeout(ide_drive_t *);
+extern const struct ide_dma_ops sff_dma_ops;
+#else
+static inline int config_drive_for_dma(ide_drive_t *drive) { return 0; }
 #endif /* CONFIG_BLK_DEV_IDEDMA_SFF */
 
+void ide_dma_lost_irq(ide_drive_t *);
+void ide_dma_timeout(ide_drive_t *);
+
 #else
 static inline int ide_id_dma_bug(ide_drive_t *drive) { return 0; }
 static inline u8 ide_find_dma_mode(ide_drive_t *drive, u8 speed) { return 0; }
@@ -1287,11 +1477,8 @@ static inline void ide_dma_on(ide_drive_t *drive) { ; }
 static inline void ide_dma_verbose(ide_drive_t *drive) { ; }
 static inline int ide_set_dma(ide_drive_t *drive) { return 1; }
 static inline void ide_check_dma_crc(ide_drive_t *drive) { ; }
-#endif /* CONFIG_BLK_DEV_IDEDMA */
-
-#ifndef CONFIG_BLK_DEV_IDEDMA_SFF
 static inline void ide_release_dma_engine(ide_hwif_t *hwif) { ; }
-#endif
+#endif /* CONFIG_BLK_DEV_IDEDMA */
 
 #ifdef CONFIG_BLK_DEV_IDEACPI
 extern int ide_acpi_exec_tfs(ide_drive_t *drive);
@@ -1319,7 +1506,6 @@ void ide_undecoded_slave(ide_drive_t *);
 
 void ide_port_apply_params(ide_hwif_t *);
 
-struct ide_host *ide_host_alloc_all(const struct ide_port_info *, hw_regs_t **);
 struct ide_host *ide_host_alloc(const struct ide_port_info *, hw_regs_t **);
 void ide_host_free(struct ide_host *);
 int ide_host_register(struct ide_host *, const struct ide_port_info *,
@@ -1345,24 +1531,6 @@ const char *ide_xfer_verbose(u8 mode);
 extern void ide_toggle_bounce(ide_drive_t *drive, int on);
 extern int ide_set_xfer_rate(ide_drive_t *drive, u8 rate);
 
-static inline int ide_dev_has_iordy(struct hd_driveid *id)
-{
-        return ((id->field_valid & 2) && (id->capability & 8)) ? 1 : 0;
-}
-
-static inline int ide_dev_is_sata(struct hd_driveid *id)
-{
-        /*
-         * See if word 93 is 0 AND drive is at least ATA-5 compatible
-         * verifying that word 80 by casting it to a signed type --
-         * this trick allows us to filter out the reserved values of
-         * 0x0000 and 0xffff along with the earlier ATA revisions...
-         */
-        if (id->hw_config == 0 && (short)id->major_rev_num >= 0x0020)
-                return 1;
-        return 0;
-}
-
 u64 ide_get_lba_addr(struct ide_taskfile *, int);
 u8 ide_dump_status(ide_drive_t *, const char *, u8);
 
@@ -1434,13 +1602,6 @@ extern struct mutex ide_cfg_mtx;
 extern struct bus_type ide_bus_type;
 extern struct class *ide_port_class;
 
-/* check if CACHE FLUSH (EXT) command is supported (bits defined in ATA-6) */
-#define ide_id_has_flush_cache(id)      ((id)->cfs_enable_2 & 0x3000)
-
-/* some Maxtor disks have bit 13 defined incorrectly so check bit 10 too */
-#define ide_id_has_flush_cache_ext(id)  \
-        (((id)->cfs_enable_2 & 0x2400) == 0x2400)
-
 static inline void ide_dump_identify(u8 *id)
 {
         print_hex_dump(KERN_INFO, "", DUMP_PREFIX_NONE, 16, 2, id, 512, 0);
@@ -1448,14 +1609,13 @@ static inline void ide_dump_identify(u8 *id)
 
 static inline int hwif_to_node(ide_hwif_t *hwif)
 {
-        struct pci_dev *dev = to_pci_dev(hwif->dev);
-        return hwif->dev ? pcibus_to_node(dev->bus) : -1;
+        return hwif->dev ? dev_to_node(hwif->dev) : -1;
 }
 
-static inline ide_drive_t *ide_get_paired_drive(ide_drive_t *drive)
+static inline ide_drive_t *ide_get_pair_dev(ide_drive_t *drive)
 {
-        ide_hwif_t *hwif        = HWIF(drive);
+        ide_drive_t *peer = &drive->hwif->drives[(drive->dn ^ 1) & 1];
 
-        return &hwif->drives[(drive->dn ^ 1) & 1];
+        return (peer->dev_flags & IDE_DFLAG_PRESENT) ? peer : NULL;
 }
 #endif /* _IDE_H */
diff --git a/include/linux/ieee80211.h b/include/linux/ieee80211.h
index 7f4df7c7659d..14126bc36641 100644
--- a/include/linux/ieee80211.h
+++ b/include/linux/ieee80211.h
@@ -471,6 +471,11 @@ struct ieee80211s_hdr {
         u8 eaddr3[6];
 } __attribute__ ((packed));
 
+/* Mesh flags */
+#define MESH_FLAGS_AE_A4        0x1
+#define MESH_FLAGS_AE_A5_A6     0x2
+#define MESH_FLAGS_PS_DEEP      0x4
+
 /**
  * struct ieee80211_quiet_ie
  *
@@ -643,6 +648,9 @@ struct ieee80211_mgmt {
         } u;
 } __attribute__ ((packed));
 
+/* mgmt header + 1 byte category code */
+#define IEEE80211_MIN_ACTION_SIZE offsetof(struct ieee80211_mgmt, u.action.u)
+
 
 /* Control frames */
 struct ieee80211_rts {
@@ -708,12 +716,13 @@ struct ieee80211_ht_addt_info {
 
 /* 802.11n HT capabilities masks */
 #define IEEE80211_HT_CAP_SUP_WIDTH              0x0002
-#define IEEE80211_HT_CAP_MIMO_PS                0x000C
+#define IEEE80211_HT_CAP_SM_PS                  0x000C
 #define IEEE80211_HT_CAP_GRN_FLD                0x0010
 #define IEEE80211_HT_CAP_SGI_20                 0x0020
 #define IEEE80211_HT_CAP_SGI_40                 0x0040
 #define IEEE80211_HT_CAP_DELAY_BA               0x0400
 #define IEEE80211_HT_CAP_MAX_AMSDU              0x0800
+#define IEEE80211_HT_CAP_DSSSCCK40              0x1000
 /* 802.11n HT capability AMPDU settings */
 #define IEEE80211_HT_CAP_AMPDU_FACTOR           0x03
 #define IEEE80211_HT_CAP_AMPDU_DENSITY          0x1C
@@ -736,11 +745,26 @@ struct ieee80211_ht_addt_info {
 #define IEEE80211_HT_IE_NON_GF_STA_PRSNT        0x0004
 #define IEEE80211_HT_IE_NON_HT_STA_PRSNT        0x0010
 
-/* MIMO Power Save Modes */
-#define WLAN_HT_CAP_MIMO_PS_STATIC      0
-#define WLAN_HT_CAP_MIMO_PS_DYNAMIC     1
-#define WLAN_HT_CAP_MIMO_PS_INVALID     2
-#define WLAN_HT_CAP_MIMO_PS_DISABLED    3
+/* block-ack parameters */
+#define IEEE80211_ADDBA_PARAM_POLICY_MASK 0x0002
+#define IEEE80211_ADDBA_PARAM_TID_MASK 0x003C
+#define IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK 0xFFA0
+#define IEEE80211_DELBA_PARAM_TID_MASK 0xF000
+#define IEEE80211_DELBA_PARAM_INITIATOR_MASK 0x0800
+
+/*
+ * A-PMDU buffer sizes
+ * According to IEEE802.11n spec size varies from 8K to 64K (in powers of 2)
+ */
+#define IEEE80211_MIN_AMPDU_BUF 0x8
+#define IEEE80211_MAX_AMPDU_BUF 0x40
+
+
+/* Spatial Multiplexing Power Save Modes */
+#define WLAN_HT_CAP_SM_PS_STATIC        0
+#define WLAN_HT_CAP_SM_PS_DYNAMIC       1
+#define WLAN_HT_CAP_SM_PS_INVALID       2
+#define WLAN_HT_CAP_SM_PS_DISABLED      3
 
 /* Authentication algorithms */
 #define WLAN_AUTH_OPEN 0
diff --git a/include/linux/if.h b/include/linux/if.h
index 5c9d1fa93fef..65246846c844 100644
--- a/include/linux/if.h
+++ b/include/linux/if.h
@@ -24,6 +24,7 @@
 #include <linux/compiler.h>             /* for "__user" et al           */
 
 #define IFNAMSIZ        16
+#define IFALIASZ        256
 #include <linux/hdlc/ioctl.h>
 
 /* Standard interface flags (netdevice->flags). */
diff --git a/include/linux/if_ether.h b/include/linux/if_ether.h
index e157c1399b61..7f3c735f422b 100644
--- a/include/linux/if_ether.h
+++ b/include/linux/if_ether.h
@@ -9,7 +9,7 @@
  *
  * Author:      Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Donald Becker, <becker@super.org>
- *              Alan Cox, <alan@redhat.com>
+ *              Alan Cox, <alan@lxorguk.ukuu.org.uk>
  *              Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
  *
  *              This program is free software; you can redistribute it and/or
@@ -56,6 +56,7 @@
 #define ETH_P_DIAG      0x6005          /* DEC Diagnostics              */
 #define ETH_P_CUST      0x6006          /* DEC Customer use             */
 #define ETH_P_SCA       0x6007          /* DEC Systems Comms Arch       */
+#define ETH_P_TEB       0x6558          /* Trans Ether Bridging         */
 #define ETH_P_RARP      0x8035          /* Reverse Addr Res packet      */
 #define ETH_P_ATALK     0x809B          /* Appletalk DDP                */
 #define ETH_P_AARP      0x80F3          /* Appletalk AARP               */
@@ -74,8 +75,10 @@
 #define ETH_P_ATMFATE   0x8884          /* Frame-based ATM Transport
                                          * over Ethernet
                                          */
+#define ETH_P_PAE       0x888E          /* Port Access Entity (IEEE 802.1X) */
 #define ETH_P_AOE       0x88A2          /* ATA over Ethernet            */
 #define ETH_P_TIPC      0x88CA          /* TIPC                         */
+#define ETH_P_EDSA      0xDADA          /* Ethertype DSA [ NOT AN OFFICIALLY REGISTERED ID ] */
 
 /*
  *      Non DIX types. Won't clash for 1500 types.
@@ -99,6 +102,9 @@
 #define ETH_P_ECONET    0x0018          /* Acorn Econet                 */
 #define ETH_P_HDLC      0x0019          /* HDLC frames                  */
 #define ETH_P_ARCNET    0x001A          /* 1A for ArcNet :-)            */
+#define ETH_P_DSA       0x001B          /* Distributed Switch Arch.     */
+#define ETH_P_TRAILER   0x001C          /* Trailer switch tagging       */
+#define ETH_P_PHONET    0x00F5          /* Nokia Phonet frames          */
 
 /*
  *      This is an Ethernet frame header.
diff --git a/include/linux/if_fddi.h b/include/linux/if_fddi.h
index ae77daed6c2f..45de1046dbbf 100644
--- a/include/linux/if_fddi.h
+++ b/include/linux/if_fddi.h
@@ -12,7 +12,7 @@
  *              if_fddi.h is based on previous if_ether.h and if_tr.h work by
  *                      Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *                      Donald Becker, <becker@super.org>
- *                      Alan Cox, <alan@redhat.com>
+ *                      Alan Cox, <alan@lxorguk.ukuu.org.uk>
  *                      Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
  *                      Peter De Schrijver, <stud11@cc4.kuleuven.ac.be>
  *
diff --git a/include/linux/if_hippi.h b/include/linux/if_hippi.h
index 94d31ca7d71a..f0f23516bb59 100644
--- a/include/linux/if_hippi.h
+++ b/include/linux/if_hippi.h
@@ -9,7 +9,7 @@
  *
  * Author:      Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Donald Becker, <becker@super.org>
- *              Alan Cox, <alan@redhat.com>
+ *              Alan Cox, <alan@lxorguk.ukuu.org.uk>
  *              Steve Whitehouse, <gw7rrm@eeshack3.swan.ac.uk>
  *              Jes Sorensen, <Jes.Sorensen@cern.ch>
  *
diff --git a/include/linux/if_link.h b/include/linux/if_link.h
index 84c3492ae5cb..f9032c88716a 100644
--- a/include/linux/if_link.h
+++ b/include/linux/if_link.h
@@ -79,6 +79,7 @@ enum
         IFLA_LINKINFO,
 #define IFLA_LINKINFO IFLA_LINKINFO
         IFLA_NET_NS_PID,
+        IFLA_IFALIAS,
         __IFLA_MAX
 };
 
diff --git a/include/linux/if_phonet.h b/include/linux/if_phonet.h
new file mode 100644
index 000000000000..d70034bcec05
--- /dev/null
+++ b/include/linux/if_phonet.h
@@ -0,0 +1,19 @@
+/*
+ * File: if_phonet.h
+ *
+ * Phonet interface kernel definitions
+ *
+ * Copyright (C) 2008 Nokia Corporation. All rights reserved.
+ */
+#ifndef LINUX_IF_PHONET_H
+#define LINUX_IF_PHONET_H
+
+#define PHONET_MIN_MTU          6       /* pn_length = 0 */
+#define PHONET_MAX_MTU          65541   /* pn_length = 0xffff */
+#define PHONET_DEV_MTU          PHONET_MAX_MTU
+
+#ifdef __KERNEL__
+extern struct header_ops phonet_header_ops;
+#endif
+
+#endif
diff --git a/include/linux/if_tunnel.h b/include/linux/if_tunnel.h
index d4efe4014705..aeab2cb32a9c 100644
--- a/include/linux/if_tunnel.h
+++ b/include/linux/if_tunnel.h
@@ -2,6 +2,7 @@
 #define _IF_TUNNEL_H_
 
 #include <linux/types.h>
+#include <linux/ip.h>
 
 #define SIOCGETTUNNEL   (SIOCDEVPRIVATE + 0)
 #define SIOCADDTUNNEL   (SIOCDEVPRIVATE + 1)
@@ -47,4 +48,22 @@ struct ip_tunnel_prl {
 /* PRL flags */
 #define PRL_DEFAULT             0x0001
 
+enum
+{
+        IFLA_GRE_UNSPEC,
+        IFLA_GRE_LINK,
+        IFLA_GRE_IFLAGS,
+        IFLA_GRE_OFLAGS,
+        IFLA_GRE_IKEY,
+        IFLA_GRE_OKEY,
+        IFLA_GRE_LOCAL,
+        IFLA_GRE_REMOTE,
+        IFLA_GRE_TTL,
+        IFLA_GRE_TOS,
+        IFLA_GRE_PMTUDISC,
+        __IFLA_GRE_MAX,
+};
+
+#define IFLA_GRE_MAX    (__IFLA_GRE_MAX - 1)
+
 #endif /* _IF_TUNNEL_H_ */
diff --git a/include/linux/igmp.h b/include/linux/igmp.h
index 7bb3c095c15b..f734a0ba0698 100644
--- a/include/linux/igmp.h
+++ b/include/linux/igmp.h
@@ -2,7 +2,7 @@
  *      Linux NET3:     Internet Group Management Protocol  [IGMP]
  *
  *      Authors:
- *              Alan Cox <Alan.Cox@linux.org>
+ *              Alan Cox <alan@lxorguk.ukuu.org.uk>
  *
  *      Extended to talk the BSD extended IGMP protocol of mrouted 3.6
  *
diff --git a/include/linux/in.h b/include/linux/in.h
index 4065313cd7ee..db458beef19d 100644
--- a/include/linux/in.h
+++ b/include/linux/in.h
@@ -75,6 +75,7 @@ struct in_addr {
 #define IP_IPSEC_POLICY 16
 #define IP_XFRM_POLICY  17
 #define IP_PASSSEC      18
+#define IP_TRANSPARENT  19
 
 /* BSD compatibility */
 #define IP_RECVRETOPTS  IP_RETOPTS
diff --git a/include/linux/inetdevice.h b/include/linux/inetdevice.h
index c6f51ad52d5b..06fcdb45106b 100644
--- a/include/linux/inetdevice.h
+++ b/include/linux/inetdevice.h
@@ -25,6 +25,7 @@ struct in_device
         struct in_ifaddr        *ifa_list;      /* IP ifaddr chain              */
         rwlock_t                mc_list_lock;
         struct ip_mc_list       *mc_list;       /* IP multicast filter chain    */
+        int                     mc_count;                 /* Number of installed mcasts */
         spinlock_t              mc_tomb_lock;
         struct ip_mc_list       *mc_tomb;
         unsigned long           mr_v1_seen;
diff --git a/include/linux/init.h b/include/linux/init.h
index 93538b696e3d..ad63824460e3 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -233,9 +233,6 @@ struct obs_kernel_param {
                 __attribute__((aligned((sizeof(long)))))        \
                 = { __setup_str_##unique_id, fn, early }
 
-#define __setup_null_param(str, unique_id)                      \
-        __setup_param(str, unique_id, NULL, 0)
-
 #define __setup(str, fn)                                        \
         __setup_param(str, fn, fn, 0)
 
@@ -296,7 +293,6 @@ void __init parse_early_param(void);
         void cleanup_module(void) __attribute__((alias(#exitfn)));
 
 #define __setup_param(str, unique_id, fn)       /* nothing */
-#define __setup_null_param(str, unique_id)      /* nothing */
 #define __setup(str, func)                      /* nothing */
 #endif
 
diff --git a/include/linux/input.h b/include/linux/input.h
index a5802c9c81a4..b86fb5581ce6 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -577,9 +577,22 @@ struct input_absinfo {
 #define KEY_BRL_DOT9            0x1f9
 #define KEY_BRL_DOT10           0x1fa
 
+#define KEY_NUMERIC_0           0x200   /* used by phones, remote controls, */
+#define KEY_NUMERIC_1           0x201   /* and other keypads */
+#define KEY_NUMERIC_2           0x202
+#define KEY_NUMERIC_3           0x203
+#define KEY_NUMERIC_4           0x204
+#define KEY_NUMERIC_5           0x205
+#define KEY_NUMERIC_6           0x206
+#define KEY_NUMERIC_7           0x207
+#define KEY_NUMERIC_8           0x208
+#define KEY_NUMERIC_9           0x209
+#define KEY_NUMERIC_STAR        0x20a
+#define KEY_NUMERIC_POUND       0x20b
+
 /* We avoid low common keys in module aliases so they don't get huge. */
 #define KEY_MIN_INTERESTING     KEY_MUTE
-#define KEY_MAX                 0x1ff
+#define KEY_MAX                 0x2ff
 #define KEY_CNT                 (KEY_MAX+1)
 
 /*
diff --git a/include/linux/intel-iommu.h b/include/linux/intel-iommu.h
new file mode 100644
index 000000000000..2e117f30a76c
--- /dev/null
+++ b/include/linux/intel-iommu.h
@@ -0,0 +1,327 @@
+/*
+ * Copyright (c) 2006, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Copyright (C) 2006-2008 Intel Corporation
+ * Author: Ashok Raj <ashok.raj@intel.com>
+ * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
+ */
+
+#ifndef _INTEL_IOMMU_H_
+#define _INTEL_IOMMU_H_
+
+#include <linux/types.h>
+#include <linux/msi.h>
+#include <linux/sysdev.h>
+#include <linux/iova.h>
+#include <linux/io.h>
+#include <linux/dma_remapping.h>
+#include <asm/cacheflush.h>
+
+/*
+ * Intel IOMMU register specification per version 1.0 public spec.
+ */
+
+#define DMAR_VER_REG    0x0     /* Arch version supported by this IOMMU */
+#define DMAR_CAP_REG    0x8     /* Hardware supported capabilities */
+#define DMAR_ECAP_REG   0x10    /* Extended capabilities supported */
+#define DMAR_GCMD_REG   0x18    /* Global command register */
+#define DMAR_GSTS_REG   0x1c    /* Global status register */
+#define DMAR_RTADDR_REG 0x20    /* Root entry table */
+#define DMAR_CCMD_REG   0x28    /* Context command reg */
+#define DMAR_FSTS_REG   0x34    /* Fault Status register */
+#define DMAR_FECTL_REG  0x38    /* Fault control register */
+#define DMAR_FEDATA_REG 0x3c    /* Fault event interrupt data register */
+#define DMAR_FEADDR_REG 0x40    /* Fault event interrupt addr register */
+#define DMAR_FEUADDR_REG 0x44   /* Upper address register */
+#define DMAR_AFLOG_REG  0x58    /* Advanced Fault control */
+#define DMAR_PMEN_REG   0x64    /* Enable Protected Memory Region */
+#define DMAR_PLMBASE_REG 0x68   /* PMRR Low addr */
+#define DMAR_PLMLIMIT_REG 0x6c  /* PMRR low limit */
+#define DMAR_PHMBASE_REG 0x70   /* pmrr high base addr */
+#define DMAR_PHMLIMIT_REG 0x78  /* pmrr high limit */
+#define DMAR_IQH_REG    0x80    /* Invalidation queue head register */
+#define DMAR_IQT_REG    0x88    /* Invalidation queue tail register */
+#define DMAR_IQA_REG    0x90    /* Invalidation queue addr register */
+#define DMAR_ICS_REG    0x98    /* Invalidation complete status register */
+#define DMAR_IRTA_REG   0xb8    /* Interrupt remapping table addr register */
+
+#define OFFSET_STRIDE           (9)
+/*
+#define dmar_readl(dmar, reg) readl(dmar + reg)
+#define dmar_readq(dmar, reg) ({ \
+                u32 lo, hi; \
+                lo = readl(dmar + reg); \
+                hi = readl(dmar + reg + 4); \
+                (((u64) hi) << 32) + lo; })
+*/
+static inline u64 dmar_readq(void __iomem *addr)
+{
+        u32 lo, hi;
+        lo = readl(addr);
+        hi = readl(addr + 4);
+        return (((u64) hi) << 32) + lo;
+}
+
+static inline void dmar_writeq(void __iomem *addr, u64 val)
+{
+        writel((u32)val, addr);
+        writel((u32)(val >> 32), addr + 4);
+}
+
+#define DMAR_VER_MAJOR(v)               (((v) & 0xf0) >> 4)
+#define DMAR_VER_MINOR(v)               ((v) & 0x0f)
+
+/*
+ * Decoding Capability Register
+ */
+#define cap_read_drain(c)       (((c) >> 55) & 1)
+#define cap_write_drain(c)      (((c) >> 54) & 1)
+#define cap_max_amask_val(c)    (((c) >> 48) & 0x3f)
+#define cap_num_fault_regs(c)   ((((c) >> 40) & 0xff) + 1)
+#define cap_pgsel_inv(c)        (((c) >> 39) & 1)
+
+#define cap_super_page_val(c)   (((c) >> 34) & 0xf)
+#define cap_super_offset(c)     (((find_first_bit(&cap_super_page_val(c), 4)) \
+                                        * OFFSET_STRIDE) + 21)
+
+#define cap_fault_reg_offset(c) ((((c) >> 24) & 0x3ff) * 16)
+#define cap_max_fault_reg_offset(c) \
+        (cap_fault_reg_offset(c) + cap_num_fault_regs(c) * 16)
+
+#define cap_zlr(c)              (((c) >> 22) & 1)
+#define cap_isoch(c)            (((c) >> 23) & 1)
+#define cap_mgaw(c)             ((((c) >> 16) & 0x3f) + 1)
+#define cap_sagaw(c)            (((c) >> 8) & 0x1f)
+#define cap_caching_mode(c)     (((c) >> 7) & 1)
+#define cap_phmr(c)             (((c) >> 6) & 1)
+#define cap_plmr(c)             (((c) >> 5) & 1)
+#define cap_rwbf(c)             (((c) >> 4) & 1)
+#define cap_afl(c)              (((c) >> 3) & 1)
+#define cap_ndoms(c)            (((unsigned long)1) << (4 + 2 * ((c) & 0x7)))
+/*
+ * Extended Capability Register
+ */
+
+#define ecap_niotlb_iunits(e)   ((((e) >> 24) & 0xff) + 1)
+#define ecap_iotlb_offset(e)    ((((e) >> 8) & 0x3ff) * 16)
+#define ecap_max_iotlb_offset(e) \
+        (ecap_iotlb_offset(e) + ecap_niotlb_iunits(e) * 16)
+#define ecap_coherent(e)        ((e) & 0x1)
+#define ecap_qis(e)             ((e) & 0x2)
+#define ecap_eim_support(e)     ((e >> 4) & 0x1)
+#define ecap_ir_support(e)      ((e >> 3) & 0x1)
+#define ecap_max_handle_mask(e) ((e >> 20) & 0xf)
+
+
+/* IOTLB_REG */
+#define DMA_TLB_GLOBAL_FLUSH (((u64)1) << 60)
+#define DMA_TLB_DSI_FLUSH (((u64)2) << 60)
+#define DMA_TLB_PSI_FLUSH (((u64)3) << 60)
+#define DMA_TLB_IIRG(type) ((type >> 60) & 7)
+#define DMA_TLB_IAIG(val) (((val) >> 57) & 7)
+#define DMA_TLB_READ_DRAIN (((u64)1) << 49)
+#define DMA_TLB_WRITE_DRAIN (((u64)1) << 48)
+#define DMA_TLB_DID(id) (((u64)((id) & 0xffff)) << 32)
+#define DMA_TLB_IVT (((u64)1) << 63)
+#define DMA_TLB_IH_NONLEAF (((u64)1) << 6)
+#define DMA_TLB_MAX_SIZE (0x3f)
+
+/* INVALID_DESC */
+#define DMA_ID_TLB_GLOBAL_FLUSH (((u64)1) << 3)
+#define DMA_ID_TLB_DSI_FLUSH    (((u64)2) << 3)
+#define DMA_ID_TLB_PSI_FLUSH    (((u64)3) << 3)
+#define DMA_ID_TLB_READ_DRAIN   (((u64)1) << 7)
+#define DMA_ID_TLB_WRITE_DRAIN  (((u64)1) << 6)
+#define DMA_ID_TLB_DID(id)      (((u64)((id & 0xffff) << 16)))
+#define DMA_ID_TLB_IH_NONLEAF   (((u64)1) << 6)
+#define DMA_ID_TLB_ADDR(addr)   (addr)
+#define DMA_ID_TLB_ADDR_MASK(mask)      (mask)
+
+/* PMEN_REG */
+#define DMA_PMEN_EPM (((u32)1)<<31)
+#define DMA_PMEN_PRS (((u32)1)<<0)
+
+/* GCMD_REG */
+#define DMA_GCMD_TE (((u32)1) << 31)
+#define DMA_GCMD_SRTP (((u32)1) << 30)
+#define DMA_GCMD_SFL (((u32)1) << 29)
+#define DMA_GCMD_EAFL (((u32)1) << 28)
+#define DMA_GCMD_WBF (((u32)1) << 27)
+#define DMA_GCMD_QIE (((u32)1) << 26)
+#define DMA_GCMD_SIRTP (((u32)1) << 24)
+#define DMA_GCMD_IRE (((u32) 1) << 25)
+
+/* GSTS_REG */
+#define DMA_GSTS_TES (((u32)1) << 31)
+#define DMA_GSTS_RTPS (((u32)1) << 30)
+#define DMA_GSTS_FLS (((u32)1) << 29)
+#define DMA_GSTS_AFLS (((u32)1) << 28)
+#define DMA_GSTS_WBFS (((u32)1) << 27)
+#define DMA_GSTS_QIES (((u32)1) << 26)
+#define DMA_GSTS_IRTPS (((u32)1) << 24)
+#define DMA_GSTS_IRES (((u32)1) << 25)
+
+/* CCMD_REG */
+#define DMA_CCMD_ICC (((u64)1) << 63)
+#define DMA_CCMD_GLOBAL_INVL (((u64)1) << 61)
+#define DMA_CCMD_DOMAIN_INVL (((u64)2) << 61)
+#define DMA_CCMD_DEVICE_INVL (((u64)3) << 61)
+#define DMA_CCMD_FM(m) (((u64)((m) & 0x3)) << 32)
+#define DMA_CCMD_MASK_NOBIT 0
+#define DMA_CCMD_MASK_1BIT 1
+#define DMA_CCMD_MASK_2BIT 2
+#define DMA_CCMD_MASK_3BIT 3
+#define DMA_CCMD_SID(s) (((u64)((s) & 0xffff)) << 16)
+#define DMA_CCMD_DID(d) ((u64)((d) & 0xffff))
+
+/* FECTL_REG */
+#define DMA_FECTL_IM (((u32)1) << 31)
+
+/* FSTS_REG */
+#define DMA_FSTS_PPF ((u32)2)
+#define DMA_FSTS_PFO ((u32)1)
+#define dma_fsts_fault_record_index(s) (((s) >> 8) & 0xff)
+
+/* FRCD_REG, 32 bits access */
+#define DMA_FRCD_F (((u32)1) << 31)
+#define dma_frcd_type(d) ((d >> 30) & 1)
+#define dma_frcd_fault_reason(c) (c & 0xff)
+#define dma_frcd_source_id(c) (c & 0xffff)
+#define dma_frcd_page_addr(d) (d & (((u64)-1) << 12)) /* low 64 bit */
+
+#define DMAR_OPERATION_TIMEOUT ((cycles_t) tsc_khz*10*1000) /* 10sec */
+
+#define IOMMU_WAIT_OP(iommu, offset, op, cond, sts) \
+{\
+        cycles_t start_time = get_cycles();\
+        while (1) {\
+                sts = op (iommu->reg + offset);\
+                if (cond)\
+                        break;\
+                if (DMAR_OPERATION_TIMEOUT < (get_cycles() - start_time))\
+                        panic("DMAR hardware is malfunctioning\n");\
+                cpu_relax();\
+        }\
+}
+
+#define QI_LENGTH       256     /* queue length */
+
+enum {
+        QI_FREE,
+        QI_IN_USE,
+        QI_DONE
+};
+
+#define QI_CC_TYPE              0x1
+#define QI_IOTLB_TYPE           0x2
+#define QI_DIOTLB_TYPE          0x3
+#define QI_IEC_TYPE             0x4
+#define QI_IWD_TYPE             0x5
+
+#define QI_IEC_SELECTIVE        (((u64)1) << 4)
+#define QI_IEC_IIDEX(idx)       (((u64)(idx & 0xffff) << 32))
+#define QI_IEC_IM(m)            (((u64)(m & 0x1f) << 27))
+
+#define QI_IWD_STATUS_DATA(d)   (((u64)d) << 32)
+#define QI_IWD_STATUS_WRITE     (((u64)1) << 5)
+
+struct qi_desc {
+        u64 low, high;
+};
+
+struct q_inval {
+        spinlock_t      q_lock;
+        struct qi_desc  *desc;          /* invalidation queue */
+        int             *desc_status;   /* desc status */
+        int             free_head;      /* first free entry */
+        int             free_tail;      /* last free entry */
+        int             free_cnt;
+};
+
+#ifdef CONFIG_INTR_REMAP
+/* 1MB - maximum possible interrupt remapping table size */
+#define INTR_REMAP_PAGE_ORDER   8
+#define INTR_REMAP_TABLE_REG_SIZE       0xf
+
+#define INTR_REMAP_TABLE_ENTRIES        65536
+
+struct ir_table {
+        struct irte *base;
+};
+#endif
+
+struct intel_iommu {
+        void __iomem    *reg; /* Pointer to hardware regs, virtual addr */
+        u64             cap;
+        u64             ecap;
+        int             seg;
+        u32             gcmd; /* Holds TE, EAFL. Don't need SRTP, SFL, WBF */
+        spinlock_t      register_lock; /* protect register handling */
+        int             seq_id; /* sequence id of the iommu */
+
+#ifdef CONFIG_DMAR
+        unsigned long   *domain_ids; /* bitmap of domains */
+        struct dmar_domain **domains; /* ptr to domains */
+        spinlock_t      lock; /* protect context, domain ids */
+        struct root_entry *root_entry; /* virtual address */
+
+        unsigned int irq;
+        unsigned char name[7];    /* Device Name */
+        struct msi_msg saved_msg;
+        struct sys_device sysdev;
+#endif
+        struct q_inval  *qi;            /* Queued invalidation info */
+#ifdef CONFIG_INTR_REMAP
+        struct ir_table *ir_table;      /* Interrupt remapping info */
+#endif
+};
+
+static inline void __iommu_flush_cache(
+        struct intel_iommu *iommu, void *addr, int size)
+{
+        if (!ecap_coherent(iommu->ecap))
+                clflush_cache_range(addr, size);
+}
+
+extern struct dmar_drhd_unit * dmar_find_matched_drhd_unit(struct pci_dev *dev);
+
+extern int alloc_iommu(struct dmar_drhd_unit *drhd);
+extern void free_iommu(struct intel_iommu *iommu);
+extern int dmar_enable_qi(struct intel_iommu *iommu);
+extern void qi_global_iec(struct intel_iommu *iommu);
+
+extern void qi_submit_sync(struct qi_desc *desc, struct intel_iommu *iommu);
+
+void intel_iommu_domain_exit(struct dmar_domain *domain);
+struct dmar_domain *intel_iommu_domain_alloc(struct pci_dev *pdev);
+int intel_iommu_context_mapping(struct dmar_domain *domain,
+                                struct pci_dev *pdev);
+int intel_iommu_page_mapping(struct dmar_domain *domain, dma_addr_t iova,
+                             u64 hpa, size_t size, int prot);
+void intel_iommu_detach_dev(struct dmar_domain *domain, u8 bus, u8 devfn);
+struct dmar_domain *intel_iommu_find_domain(struct pci_dev *pdev);
+u64 intel_iommu_iova_to_pfn(struct dmar_domain *domain, u64 iova);
+
+#ifdef CONFIG_DMAR
+int intel_iommu_found(void);
+#else /* CONFIG_DMAR */
+static inline int intel_iommu_found(void)
+{
+        return 0;
+}
+#endif /* CONFIG_DMAR */
+
+#endif
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index 58ff4e74b2f3..35a61dc60d51 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -11,6 +11,8 @@
 #include <linux/hardirq.h>
 #include <linux/sched.h>
 #include <linux/irqflags.h>
+#include <linux/smp.h>
+#include <linux/percpu.h>
 #include <asm/atomic.h>
 #include <asm/ptrace.h>
 #include <asm/system.h>
@@ -252,6 +254,8 @@ enum
         HRTIMER_SOFTIRQ,
 #endif
         RCU_SOFTIRQ,    /* Preferable RCU should always be the last softirq */
+
+        NR_SOFTIRQS
 };
 
 /* softirq mask and active fields moved to irq_cpustat_t in
@@ -271,6 +275,25 @@ extern void softirq_init(void);
 extern void raise_softirq_irqoff(unsigned int nr);
 extern void raise_softirq(unsigned int nr);
 
+/* This is the worklist that queues up per-cpu softirq work.
+ *
+ * send_remote_sendirq() adds work to these lists, and
+ * the softirq handler itself dequeues from them.  The queues
+ * are protected by disabling local cpu interrupts and they must
+ * only be accessed by the local cpu that they are for.
+ */
+DECLARE_PER_CPU(struct list_head [NR_SOFTIRQS], softirq_work_list);
+
+/* Try to send a softirq to a remote cpu.  If this cannot be done, the
+ * work will be queued to the local cpu.
+ */
+extern void send_remote_softirq(struct call_single_data *cp, int cpu, int softirq);
+
+/* Like send_remote_softirq(), but the caller must disable local cpu interrupts
+ * and compute the current cpu, passed in as 'this_cpu'.
+ */
+extern void __send_remote_softirq(struct call_single_data *cp, int cpu,
+                                  int this_cpu, int softirq);
 
 /* Tasklets --- multithreaded analogue of BHs.
 
diff --git a/include/linux/iommu-helper.h b/include/linux/iommu-helper.h
index c975caf75385..3b068e5b5671 100644
--- a/include/linux/iommu-helper.h
+++ b/include/linux/iommu-helper.h
@@ -1,6 +1,20 @@
+#ifndef _LINUX_IOMMU_HELPER_H
+#define _LINUX_IOMMU_HELPER_H
+
+static inline unsigned long iommu_device_max_index(unsigned long size,
+                                                   unsigned long offset,
+                                                   u64 dma_mask)
+{
+        if (size + offset > dma_mask)
+                return dma_mask - offset + 1;
+        else
+                return size;
+}
+
 extern int iommu_is_span_boundary(unsigned int index, unsigned int nr,
                                   unsigned long shift,
                                   unsigned long boundary_size);
+extern void iommu_area_reserve(unsigned long *map, unsigned long i, int len);
 extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
                                       unsigned long start, unsigned int nr,
                                       unsigned long shift,
@@ -8,3 +22,8 @@ extern unsigned long iommu_area_alloc(unsigned long *map, unsigned long size,
                                       unsigned long align_mask);
 extern void iommu_area_free(unsigned long *map, unsigned long start,
                             unsigned int nr);
+
+extern unsigned long iommu_num_pages(unsigned long addr, unsigned long len,
+                                     unsigned long io_page_size);
+
+#endif
diff --git a/include/linux/ioport.h b/include/linux/ioport.h
index 22d2115458c6..041e95aac2bf 100644
--- a/include/linux/ioport.h
+++ b/include/linux/ioport.h
@@ -34,7 +34,8 @@ struct resource_list {
  */
 #define IORESOURCE_BITS         0x000000ff      /* Bus-specific bits */
 
-#define IORESOURCE_IO           0x00000100      /* Resource type */
+#define IORESOURCE_TYPE_BITS    0x00000f00      /* Resource type */
+#define IORESOURCE_IO           0x00000100
 #define IORESOURCE_MEM          0x00000200
 #define IORESOURCE_IRQ          0x00000400
 #define IORESOURCE_DMA          0x00000800
@@ -108,7 +109,11 @@ extern struct resource iomem_resource;
 
 extern int request_resource(struct resource *root, struct resource *new);
 extern int release_resource(struct resource *new);
+extern void reserve_region_with_split(struct resource *root,
+                             resource_size_t start, resource_size_t end,
+                             const char *name);
 extern int insert_resource(struct resource *parent, struct resource *new);
+extern void insert_resource_expand_to_fit(struct resource *root, struct resource *new);
 extern int allocate_resource(struct resource *root, struct resource *new,
                              resource_size_t size, resource_size_t min,
                              resource_size_t max, resource_size_t align,
@@ -122,6 +127,10 @@ static inline resource_size_t resource_size(struct resource *res)
 {
         return res->end - res->start + 1;
 }
+static inline unsigned long resource_type(struct resource *res)
+{
+        return res->flags & IORESOURCE_TYPE_BITS;
+}
 
 /* Convenience shorthand with allocation */
 #define request_region(start,n,name)    __request_region(&ioport_resource, (start), (n), (name))
@@ -158,13 +167,14 @@ extern struct resource * __devm_request_region(struct device *dev,
                                 struct resource *parent, resource_size_t start,
                                 resource_size_t n, const char *name);
 
-#define devm_release_region(start,n) \
+#define devm_release_region(dev, start, n) \
         __devm_release_region(dev, &ioport_resource, (start), (n))
-#define devm_release_mem_region(start,n) \
+#define devm_release_mem_region(dev, start, n) \
         __devm_release_region(dev, &iomem_resource, (start), (n))
 
 extern void __devm_release_region(struct device *dev, struct resource *parent,
                                   resource_size_t start, resource_size_t n);
+extern int iomem_map_sanity_check(resource_size_t addr, unsigned long size);
 
 #endif /* __ASSEMBLY__ */
 #endif  /* _LINUX_IOPORT_H */
diff --git a/include/linux/iova.h b/include/linux/iova.h
new file mode 100644
index 000000000000..228f6c94b69c
--- /dev/null
+++ b/include/linux/iova.h
@@ -0,0 +1,52 @@
+/*
+ * Copyright (c) 2006, Intel Corporation.
+ *
+ * This file is released under the GPLv2.
+ *
+ * Copyright (C) 2006-2008 Intel Corporation
+ * Author: Anil S Keshavamurthy <anil.s.keshavamurthy@intel.com>
+ *
+ */
+
+#ifndef _IOVA_H_
+#define _IOVA_H_
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/rbtree.h>
+#include <linux/dma-mapping.h>
+
+/* IO virtual address start page frame number */
+#define IOVA_START_PFN          (1)
+
+/* iova structure */
+struct iova {
+        struct rb_node  node;
+        unsigned long   pfn_hi; /* IOMMU dish out addr hi */
+        unsigned long   pfn_lo; /* IOMMU dish out addr lo */
+};
+
+/* holds all the iova translations for a domain */
+struct iova_domain {
+        spinlock_t      iova_alloc_lock;/* Lock to protect iova  allocation */
+        spinlock_t      iova_rbtree_lock; /* Lock to protect update of rbtree */
+        struct rb_root  rbroot;         /* iova domain rbtree root */
+        struct rb_node  *cached32_node; /* Save last alloced node */
+        unsigned long   dma_32bit_pfn;
+};
+
+struct iova *alloc_iova_mem(void);
+void free_iova_mem(struct iova *iova);
+void free_iova(struct iova_domain *iovad, unsigned long pfn);
+void __free_iova(struct iova_domain *iovad, struct iova *iova);
+struct iova *alloc_iova(struct iova_domain *iovad, unsigned long size,
+        unsigned long limit_pfn,
+        bool size_aligned);
+struct iova *reserve_iova(struct iova_domain *iovad, unsigned long pfn_lo,
+        unsigned long pfn_hi);
+void copy_reserved_iova(struct iova_domain *from, struct iova_domain *to);
+void init_iova_domain(struct iova_domain *iovad, unsigned long pfn_32bit);
+struct iova *find_iova(struct iova_domain *iovad, unsigned long pfn);
+void put_iova_domain(struct iova_domain *iovad);
+
+#endif
diff --git a/include/linux/ip_vs.h b/include/linux/ip_vs.h
index ec6eb49af2d8..0f434a28fb58 100644
--- a/include/linux/ip_vs.h
+++ b/include/linux/ip_vs.h
@@ -242,4 +242,164 @@ struct ip_vs_daemon_user {
         int                     syncid;
 };
 
+/*
+ *
+ * IPVS Generic Netlink interface definitions
+ *
+ */
+
+/* Generic Netlink family info */
+
+#define IPVS_GENL_NAME          "IPVS"
+#define IPVS_GENL_VERSION       0x1
+
+struct ip_vs_flags {
+        __be32 flags;
+        __be32 mask;
+};
+
+/* Generic Netlink command attributes */
+enum {
+        IPVS_CMD_UNSPEC = 0,
+
+        IPVS_CMD_NEW_SERVICE,           /* add service */
+        IPVS_CMD_SET_SERVICE,           /* modify service */
+        IPVS_CMD_DEL_SERVICE,           /* delete service */
+        IPVS_CMD_GET_SERVICE,           /* get service info */
+
+        IPVS_CMD_NEW_DEST,              /* add destination */
+        IPVS_CMD_SET_DEST,              /* modify destination */
+        IPVS_CMD_DEL_DEST,              /* delete destination */
+        IPVS_CMD_GET_DEST,              /* get destination info */
+
+        IPVS_CMD_NEW_DAEMON,            /* start sync daemon */
+        IPVS_CMD_DEL_DAEMON,            /* stop sync daemon */
+        IPVS_CMD_GET_DAEMON,            /* get sync daemon status */
+
+        IPVS_CMD_SET_CONFIG,            /* set config settings */
+        IPVS_CMD_GET_CONFIG,            /* get config settings */
+
+        IPVS_CMD_SET_INFO,              /* only used in GET_INFO reply */
+        IPVS_CMD_GET_INFO,              /* get general IPVS info */
+
+        IPVS_CMD_ZERO,                  /* zero all counters and stats */
+        IPVS_CMD_FLUSH,                 /* flush services and dests */
+
+        __IPVS_CMD_MAX,
+};
+
+#define IPVS_CMD_MAX (__IPVS_CMD_MAX - 1)
+
+/* Attributes used in the first level of commands */
+enum {
+        IPVS_CMD_ATTR_UNSPEC = 0,
+        IPVS_CMD_ATTR_SERVICE,          /* nested service attribute */
+        IPVS_CMD_ATTR_DEST,             /* nested destination attribute */
+        IPVS_CMD_ATTR_DAEMON,           /* nested sync daemon attribute */
+        IPVS_CMD_ATTR_TIMEOUT_TCP,      /* TCP connection timeout */
+        IPVS_CMD_ATTR_TIMEOUT_TCP_FIN,  /* TCP FIN wait timeout */
+        IPVS_CMD_ATTR_TIMEOUT_UDP,      /* UDP timeout */
+        __IPVS_CMD_ATTR_MAX,
+};
+
+#define IPVS_CMD_ATTR_MAX (__IPVS_SVC_ATTR_MAX - 1)
+
+/*
+ * Attributes used to describe a service
+ *
+ * Used inside nested attribute IPVS_CMD_ATTR_SERVICE
+ */
+enum {
+        IPVS_SVC_ATTR_UNSPEC = 0,
+        IPVS_SVC_ATTR_AF,               /* address family */
+        IPVS_SVC_ATTR_PROTOCOL,         /* virtual service protocol */
+        IPVS_SVC_ATTR_ADDR,             /* virtual service address */
+        IPVS_SVC_ATTR_PORT,             /* virtual service port */
+        IPVS_SVC_ATTR_FWMARK,           /* firewall mark of service */
+
+        IPVS_SVC_ATTR_SCHED_NAME,       /* name of scheduler */
+        IPVS_SVC_ATTR_FLAGS,            /* virtual service flags */
+        IPVS_SVC_ATTR_TIMEOUT,          /* persistent timeout */
+        IPVS_SVC_ATTR_NETMASK,          /* persistent netmask */
+
+        IPVS_SVC_ATTR_STATS,            /* nested attribute for service stats */
+        __IPVS_SVC_ATTR_MAX,
+};
+
+#define IPVS_SVC_ATTR_MAX (__IPVS_SVC_ATTR_MAX - 1)
+
+/*
+ * Attributes used to describe a destination (real server)
+ *
+ * Used inside nested attribute IPVS_CMD_ATTR_DEST
+ */
+enum {
+        IPVS_DEST_ATTR_UNSPEC = 0,
+        IPVS_DEST_ATTR_ADDR,            /* real server address */
+        IPVS_DEST_ATTR_PORT,            /* real server port */
+
+        IPVS_DEST_ATTR_FWD_METHOD,      /* forwarding method */
+        IPVS_DEST_ATTR_WEIGHT,          /* destination weight */
+
+        IPVS_DEST_ATTR_U_THRESH,        /* upper threshold */
+        IPVS_DEST_ATTR_L_THRESH,        /* lower threshold */
+
+        IPVS_DEST_ATTR_ACTIVE_CONNS,    /* active connections */
+        IPVS_DEST_ATTR_INACT_CONNS,     /* inactive connections */
+        IPVS_DEST_ATTR_PERSIST_CONNS,   /* persistent connections */
+
+        IPVS_DEST_ATTR_STATS,           /* nested attribute for dest stats */
+        __IPVS_DEST_ATTR_MAX,
+};
+
+#define IPVS_DEST_ATTR_MAX (__IPVS_DEST_ATTR_MAX - 1)
+
+/*
+ * Attributes describing a sync daemon
+ *
+ * Used inside nested attribute IPVS_CMD_ATTR_DAEMON
+ */
+enum {
+        IPVS_DAEMON_ATTR_UNSPEC = 0,
+        IPVS_DAEMON_ATTR_STATE,         /* sync daemon state (master/backup) */
+        IPVS_DAEMON_ATTR_MCAST_IFN,     /* multicast interface name */
+        IPVS_DAEMON_ATTR_SYNC_ID,       /* SyncID we belong to */
+        __IPVS_DAEMON_ATTR_MAX,
+};
+
+#define IPVS_DAEMON_ATTR_MAX (__IPVS_DAEMON_ATTR_MAX - 1)
+
+/*
+ * Attributes used to describe service or destination entry statistics
+ *
+ * Used inside nested attributes IPVS_SVC_ATTR_STATS and IPVS_DEST_ATTR_STATS
+ */
+enum {
+        IPVS_STATS_ATTR_UNSPEC = 0,
+        IPVS_STATS_ATTR_CONNS,          /* connections scheduled */
+        IPVS_STATS_ATTR_INPKTS,         /* incoming packets */
+        IPVS_STATS_ATTR_OUTPKTS,        /* outgoing packets */
+        IPVS_STATS_ATTR_INBYTES,        /* incoming bytes */
+        IPVS_STATS_ATTR_OUTBYTES,       /* outgoing bytes */
+
+        IPVS_STATS_ATTR_CPS,            /* current connection rate */
+        IPVS_STATS_ATTR_INPPS,          /* current in packet rate */
+        IPVS_STATS_ATTR_OUTPPS,         /* current out packet rate */
+        IPVS_STATS_ATTR_INBPS,          /* current in byte rate */
+        IPVS_STATS_ATTR_OUTBPS,         /* current out byte rate */
+        __IPVS_STATS_ATTR_MAX,
+};
+
+#define IPVS_STATS_ATTR_MAX (__IPVS_STATS_ATTR_MAX - 1)
+
+/* Attributes used in response to IPVS_CMD_GET_INFO command */
+enum {
+        IPVS_INFO_ATTR_UNSPEC = 0,
+        IPVS_INFO_ATTR_VERSION,         /* IPVS version number */
+        IPVS_INFO_ATTR_CONN_TAB_SIZE,   /* size of connection hash table */
+        __IPVS_INFO_ATTR_MAX,
+};
+
+#define IPVS_INFO_ATTR_MAX (__IPVS_INFO_ATTR_MAX - 1)
+
 #endif  /* _IP_VS_H */
diff --git a/include/linux/irq.h b/include/linux/irq.h
index 8ccb462ea42c..8d9411bc60f6 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -62,6 +62,7 @@ typedef	void (*irq_flow_handler_t)(unsigned int irq,
 #define IRQ_MOVE_PENDING        0x00200000      /* need to re-target IRQ destination */
 #define IRQ_NO_BALANCING        0x00400000      /* IRQ is excluded from balancing */
 #define IRQ_SPURIOUS_DISABLED   0x00800000      /* IRQ was disabled by the spurious trap */
+#define IRQ_MOVE_PCNTXT 0x01000000      /* IRQ migration from process context */
 
 #ifdef CONFIG_IRQ_PER_CPU
 # define CHECK_IRQ_PER_CPU(var) ((var) & IRQ_PER_CPU)
diff --git a/include/linux/isdn_ppp.h b/include/linux/isdn_ppp.h
index 8687a7dc0632..4c218ee7587a 100644
--- a/include/linux/isdn_ppp.h
+++ b/include/linux/isdn_ppp.h
@@ -157,7 +157,7 @@ typedef struct {
 
 typedef struct {
   int mp_mrru;                        /* unused                             */
-  struct sk_buff * frags;       /* fragments sl list -- use skb->next */
+  struct sk_buff_head frags;    /* fragments sl list */
   long frames;                  /* number of frames in the frame list */
   unsigned int seq;             /* last processed packet seq #: any packets
                                  * with smaller seq # will be dropped
diff --git a/include/linux/ivtv.h b/include/linux/ivtv.h
index 17ca64b5a66c..f2720280b9ec 100644
--- a/include/linux/ivtv.h
+++ b/include/linux/ivtv.h
@@ -23,6 +23,7 @@
 
 #include <linux/compiler.h>
 #include <linux/types.h>
+#include <linux/videodev2.h>
 
 /* ivtv knows several distinct output modes: MPEG streaming,
    YUV streaming, YUV updates through user DMA and the passthrough
diff --git a/include/linux/jbd.h b/include/linux/jbd.h
index 07a9b52a2654..7ebbcb1c9ba4 100644
--- a/include/linux/jbd.h
+++ b/include/linux/jbd.h
@@ -61,7 +61,7 @@ extern u8 journal_enable_debug;
         do {                                                            \
                 if ((n) <= journal_enable_debug) {                      \
                         printk (KERN_DEBUG "(%s, %d): %s: ",            \
-                                __FILE__, __LINE__, __FUNCTION__);      \
+                                __FILE__, __LINE__, __func__);  \
                         printk (f, ## a);                               \
                 }                                                       \
         } while (0)
@@ -984,7 +984,7 @@ extern int	cleanup_journal_tail(journal_t *);
 
 #define jbd_ENOSYS() \
 do {                                                                       \
-        printk (KERN_ERR "JBD unimplemented function %s\n", __FUNCTION__); \
+        printk (KERN_ERR "JBD unimplemented function %s\n", __func__); \
         current->state = TASK_UNINTERRUPTIBLE;                             \
         schedule();                                                        \
 } while (1)
diff --git a/include/linux/jbd2.h b/include/linux/jbd2.h
index 3dd209007098..c7d106ef22e2 100644
--- a/include/linux/jbd2.h
+++ b/include/linux/jbd2.h
@@ -61,7 +61,7 @@ extern u8 jbd2_journal_enable_debug;
         do {                                                            \
                 if ((n) <= jbd2_journal_enable_debug) {                 \
                         printk (KERN_DEBUG "(%s, %d): %s: ",            \
-                                __FILE__, __LINE__, __FUNCTION__);      \
+                                __FILE__, __LINE__, __func__);  \
                         printk (f, ## a);                               \
                 }                                                       \
         } while (0)
@@ -641,6 +641,11 @@ struct transaction_s
          */
         int t_handle_count;
 
+        /*
+         * For use by the filesystem to store fs-specific data
+         * structures associated with the transaction
+         */
+        struct list_head        t_private_list;
 };
 
 struct transaction_run_stats_s {
@@ -850,7 +855,8 @@ struct journal_s
          */
         struct block_device     *j_dev;
         int                     j_blocksize;
-        unsigned long long              j_blk_offset;
+        unsigned long long      j_blk_offset;
+        char                    j_devname[BDEVNAME_SIZE+24];
 
         /*
          * Device which holds the client fs.  For internal journal this will be
@@ -934,6 +940,10 @@ struct journal_s
 
         pid_t                   j_last_sync_writer;
 
+        /* This function is called when a transaction is closed */
+        void                    (*j_commit_callback)(journal_t *,
+                                                     transaction_t *);
+
         /*
          * Journal statistics
          */
@@ -966,6 +976,9 @@ struct journal_s
 #define JBD2_FLUSHED    0x008   /* The journal superblock has been flushed */
 #define JBD2_LOADED     0x010   /* The journal superblock has been loaded */
 #define JBD2_BARRIER    0x020   /* Use IDE barriers */
+#define JBD2_ABORT_ON_SYNCDATA_ERR      0x040   /* Abort the journal on file
+                                                 * data write error in ordered
+                                                 * mode */
 
 /*
  * Function declarations for the journaling transaction and buffer
@@ -1059,7 +1072,7 @@ extern void	   jbd2_journal_clear_features
                    (journal_t *, unsigned long, unsigned long, unsigned long);
 extern int         jbd2_journal_create     (journal_t *);
 extern int         jbd2_journal_load       (journal_t *journal);
-extern void        jbd2_journal_destroy    (journal_t *);
+extern int         jbd2_journal_destroy    (journal_t *);
 extern int         jbd2_journal_recover    (journal_t *journal);
 extern int         jbd2_journal_wipe       (journal_t *, int);
 extern int         jbd2_journal_skip_recovery   (journal_t *);
@@ -1139,7 +1152,7 @@ extern int	jbd2_cleanup_journal_tail(journal_t *);
 
 #define jbd_ENOSYS() \
 do {                                                                       \
-        printk (KERN_ERR "JBD unimplemented function %s\n", __FUNCTION__); \
+        printk (KERN_ERR "JBD unimplemented function %s\n", __func__); \
         current->state = TASK_UNINTERRUPTIBLE;                             \
         schedule();                                                        \
 } while (1)
diff --git a/include/linux/journal-head.h b/include/linux/journal-head.h
index 8a62d1e84b9b..bb70ebb6a2d5 100644
--- a/include/linux/journal-head.h
+++ b/include/linux/journal-head.h
@@ -3,7 +3,7 @@
  *
  * buffer_head fields for JBD
  *
- * 27 May 2001 Andrew Morton <akpm@digeo.com>
+ * 27 May 2001 Andrew Morton
  *      Created - pulled out of fs.h
  */
 
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index b96144887444..f3fe34391d8e 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -93,12 +93,10 @@ static inline void print_symbol(const char *fmt, unsigned long addr)
 }
 
 /*
- * Pretty-print a function pointer.
- *
- * ia64 and ppc64 function pointers are really function descriptors,
- * which contain a pointer the real address.
+ * Pretty-print a function pointer.  This function is deprecated.
+ * Please use the "%pF" vsprintf format instead.
  */
-static inline void print_fn_descriptor_symbol(const char *fmt, void *addr)
+static inline void __deprecated print_fn_descriptor_symbol(const char *fmt, void *addr)
 {
 #if defined(CONFIG_IA64) || defined(CONFIG_PPC64)
         addr = *(void **)addr;
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index 2651f805ba6d..5a566b705ca9 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -16,6 +16,7 @@
 #include <linux/log2.h>
 #include <linux/typecheck.h>
 #include <linux/ratelimit.h>
+#include <linux/dynamic_printk.h>
 #include <asm/byteorder.h>
 #include <asm/bug.h>
 
@@ -182,7 +183,7 @@ extern int vsscanf(const char *, const char *, va_list)
 
 extern int get_option(char **str, int *pint);
 extern char *get_options(const char *str, int nints, int *ints);
-extern unsigned long long memparse(char *ptr, char **retptr);
+extern unsigned long long memparse(const char *ptr, char **retptr);
 
 extern int core_kernel_text(unsigned long addr);
 extern int __kernel_text_address(unsigned long addr);
@@ -213,6 +214,9 @@ static inline bool printk_timed_ratelimit(unsigned long *caller_jiffies, \
                 { return false; }
 #endif
 
+extern int printk_needs_cpu(int cpu);
+extern void printk_tick(void);
+
 extern void asmlinkage __attribute__((format(printf, 1, 2)))
         early_printk(const char *fmt, ...);
 
@@ -235,9 +239,10 @@ extern int oops_in_progress;		/* If set, an oops, panic(), BUG() or die() is in
 extern int panic_timeout;
 extern int panic_on_oops;
 extern int panic_on_unrecovered_nmi;
-extern int tainted;
 extern const char *print_tainted(void);
-extern void add_taint(unsigned);
+extern void add_taint(unsigned flag);
+extern int test_taint(unsigned flag);
+extern unsigned long get_taint(void);
 extern int root_mountflags;
 
 /* Values used for system_state */
@@ -250,16 +255,17 @@ extern enum system_states {
         SYSTEM_SUSPEND_DISK,
 } system_state;
 
-#define TAINT_PROPRIETARY_MODULE        (1<<0)
-#define TAINT_FORCED_MODULE             (1<<1)
-#define TAINT_UNSAFE_SMP                (1<<2)
-#define TAINT_FORCED_RMMOD              (1<<3)
-#define TAINT_MACHINE_CHECK             (1<<4)
-#define TAINT_BAD_PAGE                  (1<<5)
-#define TAINT_USER                      (1<<6)
-#define TAINT_DIE                       (1<<7)
-#define TAINT_OVERRIDDEN_ACPI_TABLE     (1<<8)
-#define TAINT_WARN                      (1<<9)
+#define TAINT_PROPRIETARY_MODULE        0
+#define TAINT_FORCED_MODULE             1
+#define TAINT_UNSAFE_SMP                2
+#define TAINT_FORCED_RMMOD              3
+#define TAINT_MACHINE_CHECK             4
+#define TAINT_BAD_PAGE                  5
+#define TAINT_USER                      6
+#define TAINT_DIE                       7
+#define TAINT_OVERRIDDEN_ACPI_TABLE     8
+#define TAINT_WARN                      9
+#define TAINT_CRAP                      10
 
 extern void dump_stack(void) __cold;
 
@@ -303,8 +309,12 @@ static inline char *pack_hex_byte(char *buf, u8 byte)
 #define pr_info(fmt, arg...) \
         printk(KERN_INFO fmt, ##arg)
 
-#ifdef DEBUG
 /* If you are writing a driver, please use dev_dbg instead */
+#if defined(CONFIG_DYNAMIC_PRINTK_DEBUG)
+#define pr_debug(fmt, ...) do { \
+        dynamic_pr_debug(fmt, ##__VA_ARGS__); \
+        } while (0)
+#elif defined(DEBUG)
 #define pr_debug(fmt, arg...) \
         printk(KERN_DEBUG fmt, ##arg)
 #else
diff --git a/include/linux/kernel_stat.h b/include/linux/kernel_stat.h
index cf9f40a91c9c..cac3750cd65e 100644
--- a/include/linux/kernel_stat.h
+++ b/include/linux/kernel_stat.h
@@ -52,6 +52,7 @@ static inline int kstat_irqs(int irq)
         return sum;
 }
 
+extern unsigned long long task_delta_exec(struct task_struct *);
 extern void account_user_time(struct task_struct *, cputime_t);
 extern void account_user_time_scaled(struct task_struct *, cputime_t);
 extern void account_system_time(struct task_struct *, int, cputime_t);
diff --git a/include/linux/key.h b/include/linux/key.h
index c45c962d1cc5..1b70e35a71e3 100644
--- a/include/linux/key.h
+++ b/include/linux/key.h
@@ -299,6 +299,7 @@ extern void key_init(void);
 #define key_validate(k)                 0
 #define key_serial(k)                   0
 #define key_get(k)                      ({ NULL; })
+#define key_revoke(k)                   do { } while(0)
 #define key_put(k)                      do { } while(0)
 #define key_ref_put(k)                  do { } while(0)
 #define make_key_ref(k, p)                      ({ NULL; })
diff --git a/include/linux/klist.h b/include/linux/klist.h
index 06c338ef7f1b..8ea98db223e5 100644
--- a/include/linux/klist.h
+++ b/include/linux/klist.h
@@ -38,7 +38,7 @@ extern void klist_init(struct klist *k, void (*get)(struct klist_node *),
                        void (*put)(struct klist_node *));
 
 struct klist_node {
-        struct klist            *n_klist;
+        void                    *n_klist;       /* never access directly */
         struct list_head        n_node;
         struct kref             n_ref;
         struct completion       n_removed;
@@ -57,7 +57,6 @@ extern int klist_node_attached(struct klist_node *n);
 
 struct klist_iter {
         struct klist            *i_klist;
-        struct list_head        *i_head;
         struct klist_node       *i_cur;
 };
 
diff --git a/include/linux/kmod.h b/include/linux/kmod.h
index a1a91577813c..92213a9194e1 100644
--- a/include/linux/kmod.h
+++ b/include/linux/kmod.h
@@ -99,4 +99,7 @@ struct file;
 extern int call_usermodehelper_pipe(char *path, char *argv[], char *envp[],
                                     struct file **filp);
 
+extern int usermodehelper_disable(void);
+extern void usermodehelper_enable(void);
+
 #endif /* __LINUX_KMOD_H__ */
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 69511f74f912..797fcd781242 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -311,21 +311,32 @@ struct kvm_s390_interrupt {
 
 /* This structure represents a single trace buffer record. */
 struct kvm_trace_rec {
-        __u32 event:28;
-        __u32 extra_u32:3;
-        __u32 cycle_in:1;
+        /* variable rec_val
+         * is split into:
+         * bits 0 - 27  -> event id
+         * bits 28 -30  -> number of extra data args of size u32
+         * bits 31      -> binary indicator for if tsc is in record
+         */
+        __u32 rec_val;
         __u32 pid;
         __u32 vcpu_id;
         union {
                 struct {
-                        __u64 cycle_u64;
+                        __u64 timestamp;
                         __u32 extra_u32[KVM_TRC_EXTRA_MAX];
-                } cycle;
+                } __attribute__((packed)) timestamp;
                 struct {
                         __u32 extra_u32[KVM_TRC_EXTRA_MAX];
-                } nocycle;
+                } notimestamp;
         } u;
-} __attribute__((packed));
+};
+
+#define TRACE_REC_EVENT_ID(val) \
+                (0x0fffffff & (val))
+#define TRACE_REC_NUM_DATA_ARGS(val) \
+                (0x70000000 & ((val) << 28))
+#define TRACE_REC_TCS(val) \
+                (0x80000000 & ((val) << 31))
 
 #define KVMIO 0xAE
 
@@ -372,6 +383,10 @@ struct kvm_trace_rec {
 #define KVM_CAP_MP_STATE 14
 #define KVM_CAP_COALESCED_MMIO 15
 #define KVM_CAP_SYNC_MMU 16  /* Changes to host mmap are reflected in guest */
+#if defined(CONFIG_X86)||defined(CONFIG_IA64)
+#define KVM_CAP_DEVICE_ASSIGNMENT 17
+#endif
+#define KVM_CAP_IOMMU 18
 
 /*
  * ioctls for VM fds
@@ -401,6 +416,10 @@ struct kvm_trace_rec {
                         _IOW(KVMIO,  0x67, struct kvm_coalesced_mmio_zone)
 #define KVM_UNREGISTER_COALESCED_MMIO \
                         _IOW(KVMIO,  0x68, struct kvm_coalesced_mmio_zone)
+#define KVM_ASSIGN_PCI_DEVICE _IOR(KVMIO, 0x69, \
+                                   struct kvm_assigned_pci_dev)
+#define KVM_ASSIGN_IRQ _IOR(KVMIO, 0x70, \
+                            struct kvm_assigned_irq)
 
 /*
  * ioctls for vcpu fds
@@ -440,4 +459,45 @@ struct kvm_trace_rec {
 #define KVM_GET_MP_STATE          _IOR(KVMIO,  0x98, struct kvm_mp_state)
 #define KVM_SET_MP_STATE          _IOW(KVMIO,  0x99, struct kvm_mp_state)
 
+#define KVM_TRC_INJ_VIRQ         (KVM_TRC_HANDLER + 0x02)
+#define KVM_TRC_REDELIVER_EVT    (KVM_TRC_HANDLER + 0x03)
+#define KVM_TRC_PEND_INTR        (KVM_TRC_HANDLER + 0x04)
+#define KVM_TRC_IO_READ          (KVM_TRC_HANDLER + 0x05)
+#define KVM_TRC_IO_WRITE         (KVM_TRC_HANDLER + 0x06)
+#define KVM_TRC_CR_READ          (KVM_TRC_HANDLER + 0x07)
+#define KVM_TRC_CR_WRITE         (KVM_TRC_HANDLER + 0x08)
+#define KVM_TRC_DR_READ          (KVM_TRC_HANDLER + 0x09)
+#define KVM_TRC_DR_WRITE         (KVM_TRC_HANDLER + 0x0A)
+#define KVM_TRC_MSR_READ         (KVM_TRC_HANDLER + 0x0B)
+#define KVM_TRC_MSR_WRITE        (KVM_TRC_HANDLER + 0x0C)
+#define KVM_TRC_CPUID            (KVM_TRC_HANDLER + 0x0D)
+#define KVM_TRC_INTR             (KVM_TRC_HANDLER + 0x0E)
+#define KVM_TRC_NMI              (KVM_TRC_HANDLER + 0x0F)
+#define KVM_TRC_VMMCALL          (KVM_TRC_HANDLER + 0x10)
+#define KVM_TRC_HLT              (KVM_TRC_HANDLER + 0x11)
+#define KVM_TRC_CLTS             (KVM_TRC_HANDLER + 0x12)
+#define KVM_TRC_LMSW             (KVM_TRC_HANDLER + 0x13)
+#define KVM_TRC_APIC_ACCESS      (KVM_TRC_HANDLER + 0x14)
+#define KVM_TRC_TDP_FAULT        (KVM_TRC_HANDLER + 0x15)
+#define KVM_TRC_GTLB_WRITE       (KVM_TRC_HANDLER + 0x16)
+#define KVM_TRC_STLB_WRITE       (KVM_TRC_HANDLER + 0x17)
+#define KVM_TRC_STLB_INVAL       (KVM_TRC_HANDLER + 0x18)
+#define KVM_TRC_PPC_INSTR        (KVM_TRC_HANDLER + 0x19)
+
+struct kvm_assigned_pci_dev {
+        __u32 assigned_dev_id;
+        __u32 busnr;
+        __u32 devfn;
+        __u32 flags;
+};
+
+struct kvm_assigned_irq {
+        __u32 assigned_dev_id;
+        __u32 host_irq;
+        __u32 guest_irq;
+        __u32 flags;
+};
+
+#define KVM_DEV_ASSIGN_ENABLE_IOMMU     (1 << 0)
+
 #endif
diff --git a/include/linux/kvm_host.h b/include/linux/kvm_host.h
index 8525afc53107..3833c48fae3a 100644
--- a/include/linux/kvm_host.h
+++ b/include/linux/kvm_host.h
@@ -34,6 +34,8 @@
 #define KVM_REQ_MMU_RELOAD         3
 #define KVM_REQ_TRIPLE_FAULT       4
 #define KVM_REQ_PENDING_TIMER      5
+#define KVM_REQ_UNHALT             6
+#define KVM_REQ_MMU_SYNC           7
 
 struct kvm_vcpu;
 extern struct kmem_cache *kvm_vcpu_cache;
@@ -279,12 +281,68 @@ void kvm_free_physmem(struct kvm *kvm);
 
 struct  kvm *kvm_arch_create_vm(void);
 void kvm_arch_destroy_vm(struct kvm *kvm);
+void kvm_free_all_assigned_devices(struct kvm *kvm);
 
 int kvm_cpu_get_interrupt(struct kvm_vcpu *v);
 int kvm_cpu_has_interrupt(struct kvm_vcpu *v);
 int kvm_cpu_has_pending_timer(struct kvm_vcpu *vcpu);
 void kvm_vcpu_kick(struct kvm_vcpu *vcpu);
 
+int kvm_is_mmio_pfn(pfn_t pfn);
+
+struct kvm_irq_ack_notifier {
+        struct hlist_node link;
+        unsigned gsi;
+        void (*irq_acked)(struct kvm_irq_ack_notifier *kian);
+};
+
+struct kvm_assigned_dev_kernel {
+        struct kvm_irq_ack_notifier ack_notifier;
+        struct work_struct interrupt_work;
+        struct list_head list;
+        int assigned_dev_id;
+        int host_busnr;
+        int host_devfn;
+        int host_irq;
+        int guest_irq;
+        int irq_requested;
+        struct pci_dev *dev;
+        struct kvm *kvm;
+};
+void kvm_set_irq(struct kvm *kvm, int irq, int level);
+void kvm_notify_acked_irq(struct kvm *kvm, unsigned gsi);
+void kvm_register_irq_ack_notifier(struct kvm *kvm,
+                                   struct kvm_irq_ack_notifier *kian);
+void kvm_unregister_irq_ack_notifier(struct kvm *kvm,
+                                     struct kvm_irq_ack_notifier *kian);
+
+#ifdef CONFIG_DMAR
+int kvm_iommu_map_pages(struct kvm *kvm, gfn_t base_gfn,
+                        unsigned long npages);
+int kvm_iommu_map_guest(struct kvm *kvm,
+                        struct kvm_assigned_dev_kernel *assigned_dev);
+int kvm_iommu_unmap_guest(struct kvm *kvm);
+#else /* CONFIG_DMAR */
+static inline int kvm_iommu_map_pages(struct kvm *kvm,
+                                      gfn_t base_gfn,
+                                      unsigned long npages)
+{
+        return 0;
+}
+
+static inline int kvm_iommu_map_guest(struct kvm *kvm,
+                                      struct kvm_assigned_dev_kernel
+                                      *assigned_dev)
+{
+        return -ENODEV;
+}
+
+static inline int kvm_iommu_unmap_guest(struct kvm *kvm)
+{
+        return 0;
+}
+#endif /* CONFIG_DMAR */
+
 static inline void kvm_guest_enter(void)
 {
         account_system_vtime(current);
@@ -307,6 +365,11 @@ static inline gpa_t gfn_to_gpa(gfn_t gfn)
         return (gpa_t)gfn << PAGE_SHIFT;
 }
 
+static inline hpa_t pfn_to_hpa(pfn_t pfn)
+{
+        return (hpa_t)pfn << PAGE_SHIFT;
+}
+
 static inline void kvm_migrate_timers(struct kvm_vcpu *vcpu)
 {
         set_bit(KVM_REQ_MIGRATE_TIMER, &vcpu->requests);
@@ -326,6 +389,25 @@ struct kvm_stats_debugfs_item {
 extern struct kvm_stats_debugfs_item debugfs_entries[];
 extern struct dentry *kvm_debugfs_dir;
 
+#define KVMTRACE_5D(evt, vcpu, d1, d2, d3, d4, d5, name) \
+        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+                                                vcpu, 5, d1, d2, d3, d4, d5)
+#define KVMTRACE_4D(evt, vcpu, d1, d2, d3, d4, name) \
+        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+                                                vcpu, 4, d1, d2, d3, d4, 0)
+#define KVMTRACE_3D(evt, vcpu, d1, d2, d3, name) \
+        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+                                                vcpu, 3, d1, d2, d3, 0, 0)
+#define KVMTRACE_2D(evt, vcpu, d1, d2, name) \
+        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+                                                vcpu, 2, d1, d2, 0, 0, 0)
+#define KVMTRACE_1D(evt, vcpu, d1, name) \
+        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+                                                vcpu, 1, d1, 0, 0, 0, 0)
+#define KVMTRACE_0D(evt, vcpu, name) \
+        trace_mark(kvm_trace_##name, "%u %p %u %u %u %u %u %u", KVM_TRC_##evt, \
+                                                vcpu, 0, 0, 0, 0, 0, 0)
+
 #ifdef CONFIG_KVM_TRACE
 int kvm_trace_ioctl(unsigned int ioctl, unsigned long arg);
 void kvm_trace_cleanup(void);
diff --git a/include/linux/lcd.h b/include/linux/lcd.h
index 173febac6656..c67fecafff90 100644
--- a/include/linux/lcd.h
+++ b/include/linux/lcd.h
@@ -11,6 +11,7 @@
 #include <linux/device.h>
 #include <linux/mutex.h>
 #include <linux/notifier.h>
+#include <linux/fb.h>
 
 /* Notes on locking:
  *
@@ -45,6 +46,8 @@ struct lcd_ops {
         int (*get_contrast)(struct lcd_device *);
         /* Set LCD panel contrast */
         int (*set_contrast)(struct lcd_device *, int contrast);
+        /* Set LCD panel mode (resolutions ...) */
+        int (*set_mode)(struct lcd_device *, struct fb_videomode *);
         /* Check if given framebuffer device is the one LCD is bound to;
            return 0 if not, !=0 if it is. If NULL, lcd always matches the fb. */
         int (*check_fb)(struct lcd_device *, struct fb_info *);
diff --git a/include/linux/libata.h b/include/linux/libata.h
index 06b80337303b..947cf84e555d 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -146,6 +146,7 @@ enum {
         ATA_DFLAG_SPUNDOWN      = (1 << 14), /* XXX: for spindown_compat */
         ATA_DFLAG_SLEEPING      = (1 << 15), /* device is sleeping */
         ATA_DFLAG_DUBIOUS_XFER  = (1 << 16), /* data transfer not verified */
+        ATA_DFLAG_NO_UNLOAD     = (1 << 17), /* device doesn't support unload */
         ATA_DFLAG_INIT_MASK     = (1 << 24) - 1,
 
         ATA_DFLAG_DETACH        = (1 << 24),
@@ -163,6 +164,7 @@ enum {
         ATA_DEV_NONE            = 9,    /* no device */
 
         /* struct ata_link flags */
+        ATA_LFLAG_NO_HRST       = (1 << 1), /* avoid hardreset */
         ATA_LFLAG_NO_SRST       = (1 << 2), /* avoid softreset */
         ATA_LFLAG_ASSUME_ATA    = (1 << 3), /* assume ATA class */
         ATA_LFLAG_ASSUME_SEMB   = (1 << 4), /* assume SEMB class */
@@ -243,6 +245,7 @@ enum {
         ATA_TMOUT_BOOT          = 30000,        /* heuristic */
         ATA_TMOUT_BOOT_QUICK    =  7000,        /* heuristic */
         ATA_TMOUT_INTERNAL_QUICK = 5000,
+        ATA_TMOUT_MAX_PARK      = 30000,
 
         /* FIXME: GoVault needs 2s but we can't afford that without
          * parallel probing.  800ms is enough for iVDR disk
@@ -318,8 +321,11 @@ enum {
         ATA_EH_RESET            = ATA_EH_SOFTRESET | ATA_EH_HARDRESET,
         ATA_EH_ENABLE_LINK      = (1 << 3),
         ATA_EH_LPM              = (1 << 4),  /* link power management action */
+        ATA_EH_PARK             = (1 << 5), /* unload heads and stop I/O */
 
-        ATA_EH_PERDEV_MASK      = ATA_EH_REVALIDATE,
+        ATA_EH_PERDEV_MASK      = ATA_EH_REVALIDATE | ATA_EH_PARK,
+        ATA_EH_ALL_ACTIONS      = ATA_EH_REVALIDATE | ATA_EH_RESET |
+                                  ATA_EH_ENABLE_LINK | ATA_EH_LPM,
 
         /* ata_eh_info->flags */
         ATA_EHI_HOTPLUGGED      = (1 << 0),  /* could have been hotplugged */
@@ -451,6 +457,7 @@ enum link_pm {
         MEDIUM_POWER,
 };
 extern struct device_attribute dev_attr_link_power_management_policy;
+extern struct device_attribute dev_attr_unload_heads;
 extern struct device_attribute dev_attr_em_message_type;
 extern struct device_attribute dev_attr_em_message;
 extern struct device_attribute dev_attr_sw_activity;
@@ -553,8 +560,8 @@ struct ata_ering {
 struct ata_device {
         struct ata_link         *link;
         unsigned int            devno;          /* 0 or 1 */
-        unsigned long           flags;          /* ATA_DFLAG_xxx */
         unsigned int            horkage;        /* List of broken features */
+        unsigned long           flags;          /* ATA_DFLAG_xxx */
         struct scsi_device      *sdev;          /* attached SCSI device */
 #ifdef CONFIG_ATA_ACPI
         acpi_handle             acpi_handle;
@@ -563,6 +570,7 @@ struct ata_device {
         /* n_sector is used as CLEAR_OFFSET, read comment above CLEAR_OFFSET */
         u64                     n_sectors;      /* size of device, if ATA */
         unsigned int            class;          /* ATA_DEV_xxx */
+        unsigned long           unpark_deadline;
 
         u8                      pio_mode;
         u8                      dma_mode;
@@ -620,6 +628,7 @@ struct ata_eh_context {
                                                [ATA_EH_CMD_TIMEOUT_TABLE_SIZE];
         unsigned int            classes[ATA_MAX_DEVICES];
         unsigned int            did_probe_mask;
+        unsigned int            unloaded_mask;
         unsigned int            saved_ncq_enabled;
         u8                      saved_xfer_mode[ATA_MAX_DEVICES];
         /* timestamp for the last reset attempt or success */
@@ -646,6 +655,7 @@ struct ata_link {
 
         unsigned int            flags;          /* ATA_LFLAG_xxx */
 
+        u32                     saved_scontrol; /* SControl on probe */
         unsigned int            hw_sata_spd_limit;
         unsigned int            sata_spd_limit;
         unsigned int            sata_spd;       /* current SATA PHY speed */
@@ -686,7 +696,8 @@ struct ata_port {
         unsigned int            qc_active;
         int                     nr_active_links; /* #links with active qcs */
 
-        struct ata_link         link;   /* host default link */
+        struct ata_link         link;           /* host default link */
+        struct ata_link         *slave_link;    /* see ata_slave_link_init() */
 
         int                     nr_pmp_links;   /* nr of available PMP links */
         struct ata_link         *pmp_link;      /* array of PMP links */
@@ -707,6 +718,7 @@ struct ata_port {
         struct list_head        eh_done_q;
         wait_queue_head_t       eh_wait_q;
         int                     eh_tries;
+        struct completion       park_req_pending;
 
         pm_message_t            pm_mesg;
         int                     *pm_result;
@@ -770,8 +782,8 @@ struct ata_port_operations {
         /*
          * Optional features
          */
-        int  (*scr_read)(struct ata_port *ap, unsigned int sc_reg, u32 *val);
-        int  (*scr_write)(struct ata_port *ap, unsigned int sc_reg, u32 val);
+        int  (*scr_read)(struct ata_link *link, unsigned int sc_reg, u32 *val);
+        int  (*scr_write)(struct ata_link *link, unsigned int sc_reg, u32 val);
         void (*pmp_attach)(struct ata_port *ap);
         void (*pmp_detach)(struct ata_port *ap);
         int  (*enable_pm)(struct ata_port *ap, enum link_pm policy);
@@ -893,6 +905,7 @@ extern void ata_port_disable(struct ata_port *);
 extern struct ata_host *ata_host_alloc(struct device *dev, int max_ports);
 extern struct ata_host *ata_host_alloc_pinfo(struct device *dev,
                         const struct ata_port_info * const * ppi, int n_ports);
+extern int ata_slave_link_init(struct ata_port *ap);
 extern int ata_host_start(struct ata_host *host);
 extern int ata_host_register(struct ata_host *host,
                              struct scsi_host_template *sht);
@@ -918,8 +931,8 @@ extern int sata_scr_valid(struct ata_link *link);
 extern int sata_scr_read(struct ata_link *link, int reg, u32 *val);
 extern int sata_scr_write(struct ata_link *link, int reg, u32 val);
 extern int sata_scr_write_flush(struct ata_link *link, int reg, u32 val);
-extern int ata_link_online(struct ata_link *link);
-extern int ata_link_offline(struct ata_link *link);
+extern bool ata_link_online(struct ata_link *link);
+extern bool ata_link_offline(struct ata_link *link);
 #ifdef CONFIG_PM
 extern int ata_host_suspend(struct ata_host *host, pm_message_t mesg);
 extern void ata_host_resume(struct ata_host *host);
@@ -1096,6 +1109,7 @@ extern void ata_std_error_handler(struct ata_port *ap);
  */
 extern const struct ata_port_operations ata_base_port_ops;
 extern const struct ata_port_operations sata_port_ops;
+extern struct device_attribute *ata_common_sdev_attrs[];
 
 #define ATA_BASE_SHT(drv_name)                                  \
         .module                 = THIS_MODULE,                  \
@@ -1110,7 +1124,8 @@ extern const struct ata_port_operations sata_port_ops;
         .proc_name              = drv_name,                     \
         .slave_configure        = ata_scsi_slave_config,        \
         .slave_destroy          = ata_scsi_slave_destroy,       \
-        .bios_param             = ata_std_bios_param
+        .bios_param             = ata_std_bios_param,           \
+        .sdev_attrs             = ata_common_sdev_attrs
 
 #define ATA_NCQ_SHT(drv_name)                                   \
         ATA_BASE_SHT(drv_name),                                 \
@@ -1132,7 +1147,7 @@ static inline bool sata_pmp_attached(struct ata_port *ap)
 
 static inline int ata_is_host_link(const struct ata_link *link)
 {
-        return link == &link->ap->link;
+        return link == &link->ap->link || link == link->ap->slave_link;
 }
 #else /* CONFIG_SATA_PMP */
 static inline bool sata_pmp_supported(struct ata_port *ap)
@@ -1165,7 +1180,7 @@ static inline int sata_srst_pmp(struct ata_link *link)
         printk("%sata%u: "fmt, lv, (ap)->print_id , ##args)
 
 #define ata_link_printk(link, lv, fmt, args...) do { \
-        if (sata_pmp_attached((link)->ap)) \
+        if (sata_pmp_attached((link)->ap) || (link)->ap->slave_link)    \
                 printk("%sata%u.%02u: "fmt, lv, (link)->ap->print_id,   \
                        (link)->pmp , ##args); \
         else \
@@ -1263,34 +1278,17 @@ static inline int ata_link_active(struct ata_link *link)
         return ata_tag_valid(link->active_tag) || link->sactive;
 }
 
-static inline struct ata_link *ata_port_first_link(struct ata_port *ap)
-{
-        if (sata_pmp_attached(ap))
-                return ap->pmp_link;
-        return &ap->link;
-}
-
-static inline struct ata_link *ata_port_next_link(struct ata_link *link)
-{
-        struct ata_port *ap = link->ap;
-
-        if (ata_is_host_link(link)) {
-                if (!sata_pmp_attached(ap))
-                        return NULL;
-                return ap->pmp_link;
-        }
-
-        if (++link < ap->nr_pmp_links + ap->pmp_link)
-                return link;
-        return NULL;
-}
+extern struct ata_link *__ata_port_next_link(struct ata_port *ap,
+                                             struct ata_link *link,
+                                             bool dev_only);
 
-#define __ata_port_for_each_link(lk, ap) \
-        for ((lk) = &(ap)->link; (lk); (lk) = ata_port_next_link(lk))
+#define __ata_port_for_each_link(link, ap) \
+        for ((link) = __ata_port_next_link((ap), NULL, false); (link); \
+             (link) = __ata_port_next_link((ap), (link), false))
 
 #define ata_port_for_each_link(link, ap) \
-        for ((link) = ata_port_first_link(ap); (link); \
-             (link) = ata_port_next_link(link))
+        for ((link) = __ata_port_next_link((ap), NULL, true); (link); \
+             (link) = __ata_port_next_link((ap), (link), true))
 
 #define ata_link_for_each_dev(dev, link) \
         for ((dev) = (link)->device; \
@@ -1427,6 +1425,28 @@ static inline unsigned long ata_deadline(unsigned long from_jiffies,
         return from_jiffies + msecs_to_jiffies(timeout_msecs);
 }
 
+/* Don't open code these in drivers as there are traps. Firstly the range may
+   change in future hardware and specs, secondly 0xFF means 'no DMA' but is
+   > UDMA_0. Dyma ddreigiau */
+
+static inline int ata_using_mwdma(struct ata_device *adev)
+{
+        if (adev->dma_mode >= XFER_MW_DMA_0 && adev->dma_mode <= XFER_MW_DMA_4)
+                return 1;
+        return 0;
+}
+
+static inline int ata_using_udma(struct ata_device *adev)
+{
+        if (adev->dma_mode >= XFER_UDMA_0 && adev->dma_mode <= XFER_UDMA_7)
+                return 1;
+        return 0;
+}
+
+static inline int ata_dma_enabled(struct ata_device *adev)
+{
+        return (adev->dma_mode == 0xFF ? 0 : 1);
+}
 
 /**************************************************************************
  * PMP - drivers/ata/libata-pmp.c
diff --git a/include/linux/list.h b/include/linux/list.h
index db35ef02e745..969f6e92d089 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -619,6 +619,19 @@ static inline void hlist_add_after(struct hlist_node *n,
                 next->next->pprev  = &next->next;
 }
 
+/*
+ * Move a list from one list head to another. Fixup the pprev
+ * reference of the first entry if it exists.
+ */
+static inline void hlist_move_list(struct hlist_head *old,
+                                   struct hlist_head *new)
+{
+        new->first = old->first;
+        if (new->first)
+                new->first->pprev = &new->first;
+        old->first = NULL;
+}
+
 #define hlist_entry(ptr, type, member) container_of(ptr,type,member)
 
 #define hlist_for_each(pos, head) \
diff --git a/include/linux/lockd/bind.h b/include/linux/lockd/bind.h
index 3d25bcd139d1..e5872dc994c0 100644
--- a/include/linux/lockd/bind.h
+++ b/include/linux/lockd/bind.h
@@ -27,7 +27,6 @@ struct nlmsvc_binding {
                                                 struct nfs_fh *,
                                                 struct file **);
         void                    (*fclose)(struct file *);
-        unsigned long           (*get_grace_period)(void);
 };
 
 extern struct nlmsvc_binding *  nlmsvc_ops;
@@ -53,15 +52,7 @@ extern void	nlmclnt_done(struct nlm_host *host);
 
 extern int      nlmclnt_proc(struct nlm_host *host, int cmd,
                                         struct file_lock *fl);
-extern int      lockd_up(int proto);
+extern int      lockd_up(void);
 extern void     lockd_down(void);
 
-unsigned long get_nfs_grace_period(void);
-
-#ifdef CONFIG_NFSD_V4
-unsigned long get_nfs4_grace_period(void);
-#else
-static inline unsigned long get_nfs4_grace_period(void) {return 0;}
-#endif
-
 #endif /* LINUX_LOCKD_BIND_H */
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h
index dbb87ab282e8..b56d5aa9b194 100644
--- a/include/linux/lockd/lockd.h
+++ b/include/linux/lockd/lockd.h
@@ -12,6 +12,8 @@
 #ifdef __KERNEL__
 
 #include <linux/in.h>
+#include <linux/in6.h>
+#include <net/ipv6.h>
 #include <linux/fs.h>
 #include <linux/kref.h>
 #include <linux/utsname.h>
@@ -38,8 +40,9 @@
  */
 struct nlm_host {
         struct hlist_node       h_hash;         /* doubly linked list */
-        struct sockaddr_in      h_addr;         /* peer address */
-        struct sockaddr_in      h_saddr;        /* our address (optional) */
+        struct sockaddr_storage h_addr;         /* peer address */
+        size_t                  h_addrlen;
+        struct sockaddr_storage h_srcaddr;      /* our address (optional) */
         struct rpc_clnt *       h_rpcclnt;      /* RPC client to talk to peer */
         char *                  h_name;         /* remote hostname */
         u32                     h_version;      /* interface version */
@@ -61,18 +64,56 @@ struct nlm_host {
         struct list_head        h_granted;      /* Locks in GRANTED state */
         struct list_head        h_reclaim;      /* Locks in RECLAIM state */
         struct nsm_handle *     h_nsmhandle;    /* NSM status handle */
+
+        char                    h_addrbuf[48],  /* address eyecatchers */
+                                h_srcaddrbuf[48];
 };
 
 struct nsm_handle {
         struct list_head        sm_link;
         atomic_t                sm_count;
         char *                  sm_name;
-        struct sockaddr_in      sm_addr;
+        struct sockaddr_storage sm_addr;
+        size_t                  sm_addrlen;
         unsigned int            sm_monitored : 1,
                                 sm_sticky : 1;  /* don't unmonitor */
+        char                    sm_addrbuf[48]; /* address eyecatcher */
 };
 
 /*
+ * Rigorous type checking on sockaddr type conversions
+ */
+static inline struct sockaddr_in *nlm_addr_in(const struct nlm_host *host)
+{
+        return (struct sockaddr_in *)&host->h_addr;
+}
+
+static inline struct sockaddr *nlm_addr(const struct nlm_host *host)
+{
+        return (struct sockaddr *)&host->h_addr;
+}
+
+static inline struct sockaddr_in *nlm_srcaddr_in(const struct nlm_host *host)
+{
+        return (struct sockaddr_in *)&host->h_srcaddr;
+}
+
+static inline struct sockaddr *nlm_srcaddr(const struct nlm_host *host)
+{
+        return (struct sockaddr *)&host->h_srcaddr;
+}
+
+static inline struct sockaddr_in *nsm_addr_in(const struct nsm_handle *handle)
+{
+        return (struct sockaddr_in *)&handle->sm_addr;
+}
+
+static inline struct sockaddr *nsm_addr(const struct nsm_handle *handle)
+{
+        return (struct sockaddr *)&handle->sm_addr;
+}
+
+/*
  * Map an fl_owner_t into a unique 32-bit "pid"
  */
 struct nlm_lockowner {
@@ -166,7 +207,8 @@ int		  nlm_async_reply(struct nlm_rqst *, u32, const struct rpc_call_ops *);
 struct nlm_wait * nlmclnt_prepare_block(struct nlm_host *host, struct file_lock *fl);
 void              nlmclnt_finish_block(struct nlm_wait *block);
 int               nlmclnt_block(struct nlm_wait *block, struct nlm_rqst *req, long timeout);
-__be32            nlmclnt_grant(const struct sockaddr_in *addr, const struct nlm_lock *);
+__be32            nlmclnt_grant(const struct sockaddr *addr,
+                                const struct nlm_lock *lock);
 void              nlmclnt_recovery(struct nlm_host *);
 int               nlmclnt_reclaim(struct nlm_host *, struct file_lock *);
 void              nlmclnt_next_cookie(struct nlm_cookie *);
@@ -174,12 +216,14 @@ void		  nlmclnt_next_cookie(struct nlm_cookie *);
 /*
  * Host cache
  */
-struct nlm_host  *nlmclnt_lookup_host(const struct sockaddr_in *sin,
-                                        int proto, u32 version,
+struct nlm_host  *nlmclnt_lookup_host(const struct sockaddr *sap,
+                                        const size_t salen,
+                                        const unsigned short protocol,
+                                        const u32 version,
+                                        const char *hostname);
+struct nlm_host  *nlmsvc_lookup_host(const struct svc_rqst *rqstp,
                                         const char *hostname,
-                                        unsigned int hostname_len);
-struct nlm_host  *nlmsvc_lookup_host(struct svc_rqst *, const char *,
-                                        unsigned int);
+                                        const size_t hostname_len);
 struct rpc_clnt * nlm_bind_host(struct nlm_host *);
 void              nlm_rebind_host(struct nlm_host *);
 struct nlm_host * nlm_get_host(struct nlm_host *);
@@ -201,7 +245,7 @@ typedef int	  (*nlm_host_match_fn_t)(void *cur, struct nlm_host *ref);
  */
 __be32            nlmsvc_lock(struct svc_rqst *, struct nlm_file *,
                               struct nlm_host *, struct nlm_lock *, int,
-                              struct nlm_cookie *);
+                              struct nlm_cookie *, int);
 __be32            nlmsvc_unlock(struct nlm_file *, struct nlm_lock *);
 __be32            nlmsvc_testlock(struct svc_rqst *, struct nlm_file *,
                         struct nlm_host *, struct nlm_lock *,
@@ -233,15 +277,82 @@ static inline struct inode *nlmsvc_file_inode(struct nlm_file *file)
         return file->f_file->f_path.dentry->d_inode;
 }
 
+static inline int __nlm_privileged_request4(const struct sockaddr *sap)
+{
+        const struct sockaddr_in *sin = (struct sockaddr_in *)sap;
+        return (sin->sin_addr.s_addr == htonl(INADDR_LOOPBACK)) &&
+                        (ntohs(sin->sin_port) < 1024);
+}
+
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+static inline int __nlm_privileged_request6(const struct sockaddr *sap)
+{
+        const struct sockaddr_in6 *sin6 = (struct sockaddr_in6 *)sap;
+        return (ipv6_addr_type(&sin6->sin6_addr) & IPV6_ADDR_LOOPBACK) &&
+                        (ntohs(sin6->sin6_port) < 1024);
+}
+#else   /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */
+static inline int __nlm_privileged_request6(const struct sockaddr *sap)
+{
+        return 0;
+}
+#endif  /* defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE) */
+
 /*
- * Compare two host addresses (needs modifying for ipv6)
+ * Ensure incoming requests are from local privileged callers.
+ *
+ * Return TRUE if sender is local and is connecting via a privileged port;
+ * otherwise return FALSE.
  */
-static inline int nlm_cmp_addr(const struct sockaddr_in *sin1,
-                               const struct sockaddr_in *sin2)
+static inline int nlm_privileged_requester(const struct svc_rqst *rqstp)
 {
+        const struct sockaddr *sap = svc_addr(rqstp);
+
+        switch (sap->sa_family) {
+        case AF_INET:
+                return __nlm_privileged_request4(sap);
+        case AF_INET6:
+                return __nlm_privileged_request6(sap);
+        default:
+                return 0;
+        }
+}
+
+static inline int __nlm_cmp_addr4(const struct sockaddr *sap1,
+                                  const struct sockaddr *sap2)
+{
+        const struct sockaddr_in *sin1 = (const struct sockaddr_in *)sap1;
+        const struct sockaddr_in *sin2 = (const struct sockaddr_in *)sap2;
         return sin1->sin_addr.s_addr == sin2->sin_addr.s_addr;
 }
 
+static inline int __nlm_cmp_addr6(const struct sockaddr *sap1,
+                                  const struct sockaddr *sap2)
+{
+        const struct sockaddr_in6 *sin1 = (const struct sockaddr_in6 *)sap1;
+        const struct sockaddr_in6 *sin2 = (const struct sockaddr_in6 *)sap2;
+        return ipv6_addr_equal(&sin1->sin6_addr, &sin2->sin6_addr);
+}
+
+/*
+ * Compare two host addresses
+ *
+ * Return TRUE if the addresses are the same; otherwise FALSE.
+ */
+static inline int nlm_cmp_addr(const struct sockaddr *sap1,
+                               const struct sockaddr *sap2)
+{
+        if (sap1->sa_family == sap2->sa_family) {
+                switch (sap1->sa_family) {
+                case AF_INET:
+                        return __nlm_cmp_addr4(sap1, sap2);
+                case AF_INET6:
+                        return __nlm_cmp_addr6(sap1, sap2);
+                }
+        }
+        return 0;
+}
+
 /*
  * Compare two NLM locks.
  * When the second lock is of type F_UNLCK, this acts like a wildcard.
diff --git a/include/linux/lockd/xdr.h b/include/linux/lockd/xdr.h
index df18fa053bcd..d6b3a802c046 100644
--- a/include/linux/lockd/xdr.h
+++ b/include/linux/lockd/xdr.h
@@ -81,8 +81,6 @@ struct nlm_reboot {
         unsigned int    len;
         u32             state;
         __be32          addr;
-        __be32          vers;
-        __be32          proto;
 };
 
 /*
diff --git a/include/linux/magic.h b/include/linux/magic.h
index 1fa0c2ce4dec..f7f3fdddbef0 100644
--- a/include/linux/magic.h
+++ b/include/linux/magic.h
@@ -6,6 +6,10 @@
 #define AFS_SUPER_MAGIC                0x5346414F
 #define AUTOFS_SUPER_MAGIC      0x0187
 #define CODA_SUPER_MAGIC        0x73757245
+#define DEBUGFS_MAGIC          0x64626720
+#define SYSFS_MAGIC             0x62656572
+#define SECURITYFS_MAGIC        0x73636673
+#define TMPFS_MAGIC             0x01021994
 #define EFS_SUPER_MAGIC         0x414A53
 #define EXT2_SUPER_MAGIC        0xEF53
 #define EXT3_SUPER_MAGIC        0xEF53
diff --git a/include/linux/major.h b/include/linux/major.h
index 53d5fafd85c3..88249452b935 100644
--- a/include/linux/major.h
+++ b/include/linux/major.h
@@ -170,4 +170,6 @@
 
 #define VIOTAPE_MAJOR           230
 
+#define BLOCK_EXT_MAJOR         259
+
 #endif
diff --git a/include/linux/map_to_7segment.h b/include/linux/map_to_7segment.h
new file mode 100644
index 000000000000..7df8432c4402
--- /dev/null
+++ b/include/linux/map_to_7segment.h
@@ -0,0 +1,187 @@
+/*
+ * Copyright (c) 2005 Henk Vergonet <Henk.Vergonet@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ */
+
+#ifndef MAP_TO_7SEGMENT_H
+#define MAP_TO_7SEGMENT_H
+
+/* This file provides translation primitives and tables for the conversion
+ * of (ASCII) characters to a 7-segments notation.
+ *
+ * The 7 segment's wikipedia notation below is used as standard.
+ * See: http://en.wikipedia.org/wiki/Seven_segment_display
+ *
+ * Notation:    +-a-+
+ *              f   b
+ *              +-g-+
+ *              e   c
+ *              +-d-+
+ *
+ * Usage:
+ *
+ *   Register a map variable, and fill it with a character set:
+ *      static SEG7_DEFAULT_MAP(map_seg7);
+ *
+ *
+ *   Then use for conversion:
+ *      seg7 = map_to_seg7(&map_seg7, some_char);
+ *      ...
+ *
+ * In device drivers it is recommended, if required, to make the char map
+ * accessible via the sysfs interface using the following scheme:
+ *
+ * static ssize_t show_map(struct device *dev, char *buf) {
+ *      memcpy(buf, &map_seg7, sizeof(map_seg7));
+ *      return sizeof(map_seg7);
+ * }
+ * static ssize_t store_map(struct device *dev, const char *buf, size_t cnt) {
+ *      if(cnt != sizeof(map_seg7))
+ *              return -EINVAL;
+ *      memcpy(&map_seg7, buf, cnt);
+ *      return cnt;
+ * }
+ * static DEVICE_ATTR(map_seg7, PERMS_RW, show_map, store_map);
+ *
+ * History:
+ * 2005-05-31   RFC linux-kernel@vger.kernel.org
+ */
+#include <linux/errno.h>
+
+
+#define BIT_SEG7_A              0
+#define BIT_SEG7_B              1
+#define BIT_SEG7_C              2
+#define BIT_SEG7_D              3
+#define BIT_SEG7_E              4
+#define BIT_SEG7_F              5
+#define BIT_SEG7_G              6
+#define BIT_SEG7_RESERVED       7
+
+struct seg7_conversion_map {
+        unsigned char   table[128];
+};
+
+static inline int map_to_seg7(struct seg7_conversion_map *map, int c)
+{
+        return c >= 0 && c < sizeof(map->table) ? map->table[c] : -EINVAL;
+}
+
+#define SEG7_CONVERSION_MAP(_name, _map)        \
+        struct seg7_conversion_map _name = { .table = { _map } }
+
+/*
+ * It is recommended to use a facility that allows user space to redefine
+ * custom character sets for LCD devices. Please use a sysfs interface
+ * as described above.
+ */
+#define MAP_TO_SEG7_SYSFS_FILE  "map_seg7"
+
+/*******************************************************************************
+ * ASCII conversion table
+ ******************************************************************************/
+
+#define _SEG7(l,a,b,c,d,e,f,g)  \
+      ( a<<BIT_SEG7_A | b<<BIT_SEG7_B | c<<BIT_SEG7_C | d<<BIT_SEG7_D | \
+        e<<BIT_SEG7_E | f<<BIT_SEG7_F | g<<BIT_SEG7_G )
+
+#define _MAP_0_32_ASCII_SEG7_NON_PRINTABLE      \
+        0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,
+
+#define _MAP_33_47_ASCII_SEG7_SYMBOL            \
+ _SEG7('!',0,0,0,0,1,1,0), _SEG7('"',0,1,0,0,0,1,0), _SEG7('#',0,1,1,0,1,1,0),\
+ _SEG7('$',1,0,1,1,0,1,1), _SEG7('%',0,0,1,0,0,1,0), _SEG7('&',1,0,1,1,1,1,1),\
+ _SEG7('\'',0,0,0,0,0,1,0),_SEG7('(',1,0,0,1,1,1,0), _SEG7(')',1,1,1,1,0,0,0),\
+ _SEG7('*',0,1,1,0,1,1,1), _SEG7('+',0,1,1,0,0,0,1), _SEG7(',',0,0,0,0,1,0,0),\
+ _SEG7('-',0,0,0,0,0,0,1), _SEG7('.',0,0,0,0,1,0,0), _SEG7('/',0,1,0,0,1,0,1),
+
+#define _MAP_48_57_ASCII_SEG7_NUMERIC           \
+ _SEG7('0',1,1,1,1,1,1,0), _SEG7('1',0,1,1,0,0,0,0), _SEG7('2',1,1,0,1,1,0,1),\
+ _SEG7('3',1,1,1,1,0,0,1), _SEG7('4',0,1,1,0,0,1,1), _SEG7('5',1,0,1,1,0,1,1),\
+ _SEG7('6',1,0,1,1,1,1,1), _SEG7('7',1,1,1,0,0,0,0), _SEG7('8',1,1,1,1,1,1,1),\
+ _SEG7('9',1,1,1,1,0,1,1),
+
+#define _MAP_58_64_ASCII_SEG7_SYMBOL            \
+ _SEG7(':',0,0,0,1,0,0,1), _SEG7(';',0,0,0,1,0,0,1), _SEG7('<',1,0,0,0,0,1,1),\
+ _SEG7('=',0,0,0,1,0,0,1), _SEG7('>',1,1,0,0,0,0,1), _SEG7('?',1,1,1,0,0,1,0),\
+ _SEG7('@',1,1,0,1,1,1,1),
+
+#define _MAP_65_90_ASCII_SEG7_ALPHA_UPPR        \
+ _SEG7('A',1,1,1,0,1,1,1), _SEG7('B',1,1,1,1,1,1,1), _SEG7('C',1,0,0,1,1,1,0),\
+ _SEG7('D',1,1,1,1,1,1,0), _SEG7('E',1,0,0,1,1,1,1), _SEG7('F',1,0,0,0,1,1,1),\
+ _SEG7('G',1,1,1,1,0,1,1), _SEG7('H',0,1,1,0,1,1,1), _SEG7('I',0,1,1,0,0,0,0),\
+ _SEG7('J',0,1,1,1,0,0,0), _SEG7('K',0,1,1,0,1,1,1), _SEG7('L',0,0,0,1,1,1,0),\
+ _SEG7('M',1,1,1,0,1,1,0), _SEG7('N',1,1,1,0,1,1,0), _SEG7('O',1,1,1,1,1,1,0),\
+ _SEG7('P',1,1,0,0,1,1,1), _SEG7('Q',1,1,1,1,1,1,0), _SEG7('R',1,1,1,0,1,1,1),\
+ _SEG7('S',1,0,1,1,0,1,1), _SEG7('T',0,0,0,1,1,1,1), _SEG7('U',0,1,1,1,1,1,0),\
+ _SEG7('V',0,1,1,1,1,1,0), _SEG7('W',0,1,1,1,1,1,1), _SEG7('X',0,1,1,0,1,1,1),\
+ _SEG7('Y',0,1,1,0,0,1,1), _SEG7('Z',1,1,0,1,1,0,1),
+
+#define _MAP_91_96_ASCII_SEG7_SYMBOL            \
+ _SEG7('[',1,0,0,1,1,1,0), _SEG7('\\',0,0,1,0,0,1,1),_SEG7(']',1,1,1,1,0,0,0),\
+ _SEG7('^',1,1,0,0,0,1,0), _SEG7('_',0,0,0,1,0,0,0), _SEG7('`',0,1,0,0,0,0,0),
+
+#define _MAP_97_122_ASCII_SEG7_ALPHA_LOWER      \
+ _SEG7('A',1,1,1,0,1,1,1), _SEG7('b',0,0,1,1,1,1,1), _SEG7('c',0,0,0,1,1,0,1),\
+ _SEG7('d',0,1,1,1,1,0,1), _SEG7('E',1,0,0,1,1,1,1), _SEG7('F',1,0,0,0,1,1,1),\
+ _SEG7('G',1,1,1,1,0,1,1), _SEG7('h',0,0,1,0,1,1,1), _SEG7('i',0,0,1,0,0,0,0),\
+ _SEG7('j',0,0,1,1,0,0,0), _SEG7('k',0,0,1,0,1,1,1), _SEG7('L',0,0,0,1,1,1,0),\
+ _SEG7('M',1,1,1,0,1,1,0), _SEG7('n',0,0,1,0,1,0,1), _SEG7('o',0,0,1,1,1,0,1),\
+ _SEG7('P',1,1,0,0,1,1,1), _SEG7('q',1,1,1,0,0,1,1), _SEG7('r',0,0,0,0,1,0,1),\
+ _SEG7('S',1,0,1,1,0,1,1), _SEG7('T',0,0,0,1,1,1,1), _SEG7('u',0,0,1,1,1,0,0),\
+ _SEG7('v',0,0,1,1,1,0,0), _SEG7('W',0,1,1,1,1,1,1), _SEG7('X',0,1,1,0,1,1,1),\
+ _SEG7('y',0,1,1,1,0,1,1), _SEG7('Z',1,1,0,1,1,0,1),
+
+#define _MAP_123_126_ASCII_SEG7_SYMBOL          \
+ _SEG7('{',1,0,0,1,1,1,0), _SEG7('|',0,0,0,0,1,1,0), _SEG7('}',1,1,1,1,0,0,0),\
+ _SEG7('~',1,0,0,0,0,0,0),
+
+/* Maps */
+
+/* This set tries to map as close as possible to the visible characteristics
+ * of the ASCII symbol, lowercase and uppercase letters may differ in
+ * presentation on the display.
+ */
+#define MAP_ASCII7SEG_ALPHANUM                  \
+        _MAP_0_32_ASCII_SEG7_NON_PRINTABLE      \
+        _MAP_33_47_ASCII_SEG7_SYMBOL            \
+        _MAP_48_57_ASCII_SEG7_NUMERIC           \
+        _MAP_58_64_ASCII_SEG7_SYMBOL            \
+        _MAP_65_90_ASCII_SEG7_ALPHA_UPPR        \
+        _MAP_91_96_ASCII_SEG7_SYMBOL            \
+        _MAP_97_122_ASCII_SEG7_ALPHA_LOWER      \
+        _MAP_123_126_ASCII_SEG7_SYMBOL
+
+/* This set tries to map as close as possible to the symbolic characteristics
+ * of the ASCII character for maximum discrimination.
+ * For now this means all alpha chars are in lower case representations.
+ * (This for example facilitates the use of hex numbers with uppercase input.)
+ */
+#define MAP_ASCII7SEG_ALPHANUM_LC                       \
+        _MAP_0_32_ASCII_SEG7_NON_PRINTABLE      \
+        _MAP_33_47_ASCII_SEG7_SYMBOL            \
+        _MAP_48_57_ASCII_SEG7_NUMERIC           \
+        _MAP_58_64_ASCII_SEG7_SYMBOL            \
+        _MAP_97_122_ASCII_SEG7_ALPHA_LOWER      \
+        _MAP_91_96_ASCII_SEG7_SYMBOL            \
+        _MAP_97_122_ASCII_SEG7_ALPHA_LOWER      \
+        _MAP_123_126_ASCII_SEG7_SYMBOL
+
+#define SEG7_DEFAULT_MAP(_name)         \
+        SEG7_CONVERSION_MAP(_name,MAP_ASCII7SEG_ALPHANUM)
+
+#endif  /* MAP_TO_7SEGMENT_H */
+
diff --git a/include/linux/memstick.h b/include/linux/memstick.h
index a9f998a3f48b..d0c37e682234 100644
--- a/include/linux/memstick.h
+++ b/include/linux/memstick.h
@@ -21,30 +21,30 @@
 struct ms_status_register {
         unsigned char reserved;
         unsigned char interrupt;
-#define MEMSTICK_INT_CMDNAK             0x0001
-#define MEMSTICK_INT_IOREQ              0x0008
-#define MEMSTICK_INT_IOBREQ             0x0010
-#define MEMSTICK_INT_BREQ               0x0020
-#define MEMSTICK_INT_ERR                0x0040
-#define MEMSTICK_INT_CED                0x0080
+#define MEMSTICK_INT_CMDNAK 0x01
+#define MEMSTICK_INT_IOREQ  0x08
+#define MEMSTICK_INT_IOBREQ 0x10
+#define MEMSTICK_INT_BREQ   0x20
+#define MEMSTICK_INT_ERR    0x40
+#define MEMSTICK_INT_CED    0x80
 
         unsigned char status0;
-#define MEMSTICK_STATUS0_WP             0x0001
-#define MEMSTICK_STATUS0_SL             0x0002
-#define MEMSTICK_STATUS0_BF             0x0010
-#define MEMSTICK_STATUS0_BE             0x0020
-#define MEMSTICK_STATUS0_FB0            0x0040
-#define MEMSTICK_STATUS0_MB             0x0080
+#define MEMSTICK_STATUS0_WP  0x01
+#define MEMSTICK_STATUS0_SL  0x02
+#define MEMSTICK_STATUS0_BF  0x10
+#define MEMSTICK_STATUS0_BE  0x20
+#define MEMSTICK_STATUS0_FB0 0x40
+#define MEMSTICK_STATUS0_MB  0x80
 
         unsigned char status1;
-#define MEMSTICK_STATUS1_UCFG           0x0001
-#define MEMSTICK_STATUS1_FGER           0x0002
-#define MEMSTICK_STATUS1_UCEX           0x0004
-#define MEMSTICK_STATUS1_EXER           0x0008
-#define MEMSTICK_STATUS1_UCDT           0x0010
-#define MEMSTICK_STATUS1_DTER           0x0020
-#define MEMSTICK_STATUS1_FBI            0x0040
-#define MEMSTICK_STATUS1_MB             0x0080
+#define MEMSTICK_STATUS1_UCFG 0x01
+#define MEMSTICK_STATUS1_FGER 0x02
+#define MEMSTICK_STATUS1_UCEX 0x04
+#define MEMSTICK_STATUS1_EXER 0x08
+#define MEMSTICK_STATUS1_UCDT 0x10
+#define MEMSTICK_STATUS1_DTER 0x20
+#define MEMSTICK_STATUS1_FB1  0x40
+#define MEMSTICK_STATUS1_MB   0x80
 } __attribute__((packed));
 
 struct ms_id_register {
@@ -56,32 +56,32 @@ struct ms_id_register {
 
 struct ms_param_register {
         unsigned char system;
-#define MEMSTICK_SYS_ATEN 0xc0
-#define MEMSTICK_SYS_BAMD 0x80
 #define MEMSTICK_SYS_PAM  0x08
+#define MEMSTICK_SYS_BAMD 0x80
 
         unsigned char block_address_msb;
         unsigned short block_address;
         unsigned char cp;
-#define MEMSTICK_CP_BLOCK               0x0000
-#define MEMSTICK_CP_PAGE                0x0020
-#define MEMSTICK_CP_EXTRA               0x0040
-#define MEMSTICK_CP_OVERWRITE           0x0080
+#define MEMSTICK_CP_BLOCK     0x00
+#define MEMSTICK_CP_PAGE      0x20
+#define MEMSTICK_CP_EXTRA     0x40
+#define MEMSTICK_CP_OVERWRITE 0x80
 
         unsigned char page_address;
 } __attribute__((packed));
 
 struct ms_extra_data_register {
         unsigned char  overwrite_flag;
-#define MEMSTICK_OVERWRITE_UPDATA       0x0010
-#define MEMSTICK_OVERWRITE_PAGE         0x0060
-#define MEMSTICK_OVERWRITE_BLOCK        0x0080
+#define MEMSTICK_OVERWRITE_UDST  0x10
+#define MEMSTICK_OVERWRITE_PGST1 0x20
+#define MEMSTICK_OVERWRITE_PGST0 0x40
+#define MEMSTICK_OVERWRITE_BKST  0x80
 
         unsigned char  management_flag;
-#define MEMSTICK_MANAGEMENT_SYSTEM      0x0004
-#define MEMSTICK_MANAGEMENT_TRANS_TABLE 0x0008
-#define MEMSTICK_MANAGEMENT_COPY        0x0010
-#define MEMSTICK_MANAGEMENT_ACCESS      0x0020
+#define MEMSTICK_MANAGEMENT_SYSFLG 0x04
+#define MEMSTICK_MANAGEMENT_ATFLG  0x08
+#define MEMSTICK_MANAGEMENT_SCMS1  0x10
+#define MEMSTICK_MANAGEMENT_SCMS0  0x20
 
         unsigned short logical_address;
 } __attribute__((packed));
@@ -96,9 +96,9 @@ struct ms_register {
 
 struct mspro_param_register {
         unsigned char  system;
-#define MEMSTICK_SYS_SERIAL 0x80
 #define MEMSTICK_SYS_PAR4   0x00
 #define MEMSTICK_SYS_PAR8   0x40
+#define MEMSTICK_SYS_SERIAL 0x80
 
         unsigned short data_count;
         unsigned int   data_address;
@@ -147,7 +147,7 @@ struct ms_register_addr {
         unsigned char w_length;
 } __attribute__((packed));
 
-enum {
+enum memstick_tpc {
         MS_TPC_READ_MG_STATUS   = 0x01,
         MS_TPC_READ_LONG_DATA   = 0x02,
         MS_TPC_READ_SHORT_DATA  = 0x03,
@@ -167,7 +167,7 @@ enum {
         MS_TPC_SET_CMD          = 0x0e
 };
 
-enum {
+enum memstick_command {
         MS_CMD_BLOCK_END       = 0x33,
         MS_CMD_RESET           = 0x3c,
         MS_CMD_BLOCK_WRITE     = 0x55,
@@ -201,8 +201,6 @@ enum {
 
 /*** Driver structures and functions ***/
 
-#define MEMSTICK_PART_SHIFT 3
-
 enum memstick_param { MEMSTICK_POWER = 1, MEMSTICK_INTERFACE };
 
 #define MEMSTICK_POWER_OFF 0
@@ -215,24 +213,27 @@ enum memstick_param { MEMSTICK_POWER = 1, MEMSTICK_INTERFACE };
 struct memstick_host;
 struct memstick_driver;
 
+struct memstick_device_id {
+        unsigned char match_flags;
 #define MEMSTICK_MATCH_ALL            0x01
 
+        unsigned char type;
 #define MEMSTICK_TYPE_LEGACY          0xff
 #define MEMSTICK_TYPE_DUO             0x00
 #define MEMSTICK_TYPE_PRO             0x01
 
+        unsigned char category;
 #define MEMSTICK_CATEGORY_STORAGE     0xff
 #define MEMSTICK_CATEGORY_STORAGE_DUO 0x00
+#define MEMSTICK_CATEGORY_IO          0x01
+#define MEMSTICK_CATEGORY_IO_PRO      0x10
 
-#define MEMSTICK_CLASS_GENERIC        0xff
-#define MEMSTICK_CLASS_GENERIC_DUO    0x00
-
-
-struct memstick_device_id {
-        unsigned char match_flags;
-        unsigned char type;
-        unsigned char category;
         unsigned char class;
+#define MEMSTICK_CLASS_FLASH          0xff
+#define MEMSTICK_CLASS_DUO            0x00
+#define MEMSTICK_CLASS_ROM            0x01
+#define MEMSTICK_CLASS_RO             0x02
+#define MEMSTICK_CLASS_WP             0x03
 };
 
 struct memstick_request {
@@ -319,9 +320,9 @@ void memstick_suspend_host(struct memstick_host *host);
 void memstick_resume_host(struct memstick_host *host);
 
 void memstick_init_req_sg(struct memstick_request *mrq, unsigned char tpc,
-                          struct scatterlist *sg);
+                          const struct scatterlist *sg);
 void memstick_init_req(struct memstick_request *mrq, unsigned char tpc,
-                       void *buf, size_t length);
+                       const void *buf, size_t length);
 int memstick_next_req(struct memstick_host *host,
                       struct memstick_request **mrq);
 void memstick_new_req(struct memstick_host *host);
diff --git a/include/linux/mfd/tmio.h b/include/linux/mfd/tmio.h
index ec612e66391c..516d955ab8a1 100644
--- a/include/linux/mfd/tmio.h
+++ b/include/linux/mfd/tmio.h
@@ -1,6 +1,8 @@
 #ifndef MFD_TMIO_H
 #define MFD_TMIO_H
 
+#include <linux/fb.h>
+
 #define tmio_ioread8(addr) readb(addr)
 #define tmio_ioread16(addr) readw(addr)
 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
@@ -25,4 +27,21 @@ struct tmio_nand_data {
         unsigned int            num_partitions;
 };
 
+#define FBIO_TMIO_ACC_WRITE     0x7C639300
+#define FBIO_TMIO_ACC_SYNC      0x7C639301
+
+struct tmio_fb_data {
+        int                     (*lcd_set_power)(struct platform_device *fb_dev,
+                                                                bool on);
+        int                     (*lcd_mode)(struct platform_device *fb_dev,
+                                        const struct fb_videomode *mode);
+        int                     num_modes;
+        struct fb_videomode     *modes;
+
+        /* in mm: size of screen */
+        int                     height;
+        int                     width;
+};
+
+
 #endif
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
new file mode 100644
index 000000000000..217bb22ebb8e
--- /dev/null
+++ b/include/linux/mfd/wm8350/audio.h
@@ -0,0 +1,598 @@
+/*
+ * audio.h  --  Audio Driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_WM8350_AUDIO_H_
+#define __LINUX_MFD_WM8350_AUDIO_H_
+
+#include <linux/platform_device.h>
+
+#define WM8350_CLOCK_CONTROL_1                  0x28
+#define WM8350_CLOCK_CONTROL_2                  0x29
+#define WM8350_FLL_CONTROL_1                    0x2A
+#define WM8350_FLL_CONTROL_2                    0x2B
+#define WM8350_FLL_CONTROL_3                    0x2C
+#define WM8350_FLL_CONTROL_4                    0x2D
+#define WM8350_DAC_CONTROL                      0x30
+#define WM8350_DAC_DIGITAL_VOLUME_L             0x32
+#define WM8350_DAC_DIGITAL_VOLUME_R             0x33
+#define WM8350_DAC_LR_RATE                      0x35
+#define WM8350_DAC_CLOCK_CONTROL                0x36
+#define WM8350_DAC_MUTE                         0x3A
+#define WM8350_DAC_MUTE_VOLUME                  0x3B
+#define WM8350_DAC_SIDE                         0x3C
+#define WM8350_ADC_CONTROL                      0x40
+#define WM8350_ADC_DIGITAL_VOLUME_L             0x42
+#define WM8350_ADC_DIGITAL_VOLUME_R             0x43
+#define WM8350_ADC_DIVIDER                      0x44
+#define WM8350_ADC_LR_RATE                      0x46
+#define WM8350_INPUT_CONTROL                    0x48
+#define WM8350_IN3_INPUT_CONTROL                0x49
+#define WM8350_MIC_BIAS_CONTROL                 0x4A
+#define WM8350_OUTPUT_CONTROL                   0x4C
+#define WM8350_JACK_DETECT                      0x4D
+#define WM8350_ANTI_POP_CONTROL                 0x4E
+#define WM8350_LEFT_INPUT_VOLUME                0x50
+#define WM8350_RIGHT_INPUT_VOLUME               0x51
+#define WM8350_LEFT_MIXER_CONTROL               0x58
+#define WM8350_RIGHT_MIXER_CONTROL              0x59
+#define WM8350_OUT3_MIXER_CONTROL               0x5C
+#define WM8350_OUT4_MIXER_CONTROL               0x5D
+#define WM8350_OUTPUT_LEFT_MIXER_VOLUME         0x60
+#define WM8350_OUTPUT_RIGHT_MIXER_VOLUME        0x61
+#define WM8350_INPUT_MIXER_VOLUME_L             0x62
+#define WM8350_INPUT_MIXER_VOLUME_R             0x63
+#define WM8350_INPUT_MIXER_VOLUME               0x64
+#define WM8350_LOUT1_VOLUME                     0x68
+#define WM8350_ROUT1_VOLUME                     0x69
+#define WM8350_LOUT2_VOLUME                     0x6A
+#define WM8350_ROUT2_VOLUME                     0x6B
+#define WM8350_BEEP_VOLUME                      0x6F
+#define WM8350_AI_FORMATING                     0x70
+#define WM8350_ADC_DAC_COMP                     0x71
+#define WM8350_AI_ADC_CONTROL                   0x72
+#define WM8350_AI_DAC_CONTROL                   0x73
+#define WM8350_AIF_TEST                         0x74
+#define WM8350_JACK_PIN_STATUS                  0xE7
+
+/* Bit values for R08 (0x08) */
+#define WM8350_CODEC_ISEL_1_5                   0       /* x1.5 */
+#define WM8350_CODEC_ISEL_1_0                   1       /* x1.0 */
+#define WM8350_CODEC_ISEL_0_75                  2       /* x0.75 */
+#define WM8350_CODEC_ISEL_0_5                   3       /* x0.5 */
+
+#define WM8350_VMID_OFF                         0
+#define WM8350_VMID_500K                        1
+#define WM8350_VMID_100K                        2
+#define WM8350_VMID_10K                         3
+
+/*
+ * R40 (0x28) - Clock Control 1
+ */
+#define WM8350_TOCLK_RATE                       0x4000
+#define WM8350_MCLK_SEL                         0x0800
+#define WM8350_MCLK_DIV_MASK                    0x0100
+#define WM8350_BCLK_DIV_MASK                    0x00F0
+#define WM8350_OPCLK_DIV_MASK                   0x0007
+
+/*
+ * R41 (0x29) - Clock Control 2
+ */
+#define WM8350_LRC_ADC_SEL                      0x8000
+#define WM8350_MCLK_DIR                         0x0001
+
+/*
+ * R42 (0x2A) - FLL Control 1
+ */
+#define WM8350_FLL_DITHER_WIDTH_MASK            0x3000
+#define WM8350_FLL_DITHER_HP                    0x0800
+#define WM8350_FLL_OUTDIV_MASK                  0x0700
+#define WM8350_FLL_RSP_RATE_MASK                0x00F0
+#define WM8350_FLL_RATE_MASK                    0x0007
+
+/*
+ * R43 (0x2B) - FLL Control 2
+ */
+#define WM8350_FLL_RATIO_MASK                   0xF800
+#define WM8350_FLL_N_MASK                       0x03FF
+
+/*
+ * R44 (0x2C) - FLL Control 3
+ */
+#define WM8350_FLL_K_MASK                       0xFFFF
+
+/*
+ * R45 (0x2D) - FLL Control 4
+ */
+#define WM8350_FLL_FRAC                         0x0020
+#define WM8350_FLL_SLOW_LOCK_REF                0x0010
+#define WM8350_FLL_CLK_SRC_MASK                 0x0003
+
+/*
+ * R48 (0x30) - DAC Control
+ */
+#define WM8350_DAC_MONO                         0x2000
+#define WM8350_AIF_LRCLKRATE                    0x1000
+#define WM8350_DEEMP_MASK                       0x0030
+#define WM8350_DACL_DATINV                      0x0002
+#define WM8350_DACR_DATINV                      0x0001
+
+/*
+ * R50 (0x32) - DAC Digital Volume L
+ */
+#define WM8350_DAC_VU                           0x0100
+#define WM8350_DACL_VOL_MASK                    0x00FF
+
+/*
+ * R51 (0x33) - DAC Digital Volume R
+ */
+#define WM8350_DAC_VU                           0x0100
+#define WM8350_DACR_VOL_MASK                    0x00FF
+
+/*
+ * R53 (0x35) - DAC LR Rate
+ */
+#define WM8350_DACLRC_ENA                       0x0800
+#define WM8350_DACLRC_RATE_MASK                 0x07FF
+
+/*
+ * R54 (0x36) - DAC Clock Control
+ */
+#define WM8350_DACCLK_POL                       0x0010
+#define WM8350_DAC_CLKDIV_MASK                  0x0007
+
+/*
+ * R58 (0x3A) - DAC Mute
+ */
+#define WM8350_DAC_MUTE_ENA                     0x4000
+
+/*
+ * R59 (0x3B) - DAC Mute Volume
+ */
+#define WM8350_DAC_MUTEMODE                     0x4000
+#define WM8350_DAC_MUTERATE                     0x2000
+#define WM8350_DAC_SB_FILT                      0x1000
+
+/*
+ * R60 (0x3C) - DAC Side
+ */
+#define WM8350_ADC_TO_DACL_MASK                 0x3000
+#define WM8350_ADC_TO_DACR_MASK                 0x0C00
+
+/*
+ * R64 (0x40) - ADC Control
+ */
+#define WM8350_ADC_HPF_CUT_MASK                 0x0300
+#define WM8350_ADCL_DATINV                      0x0002
+#define WM8350_ADCR_DATINV                      0x0001
+
+/*
+ * R66 (0x42) - ADC Digital Volume L
+ */
+#define WM8350_ADC_VU                           0x0100
+#define WM8350_ADCL_VOL_MASK                    0x00FF
+
+/*
+ * R67 (0x43) - ADC Digital Volume R
+ */
+#define WM8350_ADC_VU                           0x0100
+#define WM8350_ADCR_VOL_MASK                    0x00FF
+
+/*
+ * R68 (0x44) - ADC Divider
+ */
+#define WM8350_ADCL_DAC_SVOL_MASK               0x0F00
+#define WM8350_ADCR_DAC_SVOL_MASK               0x00F0
+#define WM8350_ADCCLK_POL                       0x0008
+#define WM8350_ADC_CLKDIV_MASK                  0x0007
+
+/*
+ * R70 (0x46) - ADC LR Rate
+ */
+#define WM8350_ADCLRC_ENA                       0x0800
+#define WM8350_ADCLRC_RATE_MASK                 0x07FF
+
+/*
+ * R72 (0x48) - Input Control
+ */
+#define WM8350_IN2R_ENA                         0x0400
+#define WM8350_IN1RN_ENA                        0x0200
+#define WM8350_IN1RP_ENA                        0x0100
+#define WM8350_IN2L_ENA                         0x0004
+#define WM8350_IN1LN_ENA                        0x0002
+#define WM8350_IN1LP_ENA                        0x0001
+
+/*
+ * R73 (0x49) - IN3 Input Control
+ */
+#define WM8350_IN3R_SHORT                       0x4000
+#define WM8350_IN3L_SHORT                       0x0040
+
+/*
+ * R74 (0x4A) - Mic Bias Control
+ */
+#define WM8350_MICBSEL                          0x4000
+#define WM8350_MCDTHR_MASK                      0x001C
+#define WM8350_MCDSCTHR_MASK                    0x0003
+
+/*
+ * R76 (0x4C) - Output Control
+ */
+#define WM8350_OUT4_VROI                        0x0800
+#define WM8350_OUT3_VROI                        0x0400
+#define WM8350_OUT2_VROI                        0x0200
+#define WM8350_OUT1_VROI                        0x0100
+#define WM8350_OUT2_FB                          0x0004
+#define WM8350_OUT1_FB                          0x0001
+
+/*
+ * R77 (0x4D) - Jack Detect
+ */
+#define WM8350_JDL_ENA                          0x8000
+#define WM8350_JDR_ENA                          0x4000
+
+/*
+ * R78 (0x4E) - Anti Pop Control
+ */
+#define WM8350_ANTI_POP_MASK                    0x0300
+#define WM8350_DIS_OP_LN4_MASK                  0x00C0
+#define WM8350_DIS_OP_LN3_MASK                  0x0030
+#define WM8350_DIS_OP_OUT2_MASK                 0x000C
+#define WM8350_DIS_OP_OUT1_MASK                 0x0003
+
+/*
+ * R80 (0x50) - Left Input Volume
+ */
+#define WM8350_INL_MUTE                         0x4000
+#define WM8350_INL_ZC                           0x2000
+#define WM8350_IN_VU                            0x0100
+#define WM8350_INL_VOL_MASK                     0x00FC
+
+/*
+ * R81 (0x51) - Right Input Volume
+ */
+#define WM8350_INR_MUTE                         0x4000
+#define WM8350_INR_ZC                           0x2000
+#define WM8350_IN_VU                            0x0100
+#define WM8350_INR_VOL_MASK                     0x00FC
+
+/*
+ * R88 (0x58) - Left Mixer Control
+ */
+#define WM8350_DACR_TO_MIXOUTL                  0x1000
+#define WM8350_DACL_TO_MIXOUTL                  0x0800
+#define WM8350_IN3L_TO_MIXOUTL                  0x0004
+#define WM8350_INR_TO_MIXOUTL                   0x0002
+#define WM8350_INL_TO_MIXOUTL                   0x0001
+
+/*
+ * R89 (0x59) - Right Mixer Control
+ */
+#define WM8350_DACR_TO_MIXOUTR                  0x1000
+#define WM8350_DACL_TO_MIXOUTR                  0x0800
+#define WM8350_IN3R_TO_MIXOUTR                  0x0008
+#define WM8350_INR_TO_MIXOUTR                   0x0002
+#define WM8350_INL_TO_MIXOUTR                   0x0001
+
+/*
+ * R92 (0x5C) - OUT3 Mixer Control
+ */
+#define WM8350_DACL_TO_OUT3                     0x0800
+#define WM8350_MIXINL_TO_OUT3                   0x0100
+#define WM8350_OUT4_TO_OUT3                     0x0008
+#define WM8350_MIXOUTL_TO_OUT3                  0x0001
+
+/*
+ * R93 (0x5D) - OUT4 Mixer Control
+ */
+#define WM8350_DACR_TO_OUT4                     0x1000
+#define WM8350_DACL_TO_OUT4                     0x0800
+#define WM8350_OUT4_ATTN                        0x0400
+#define WM8350_MIXINR_TO_OUT4                   0x0200
+#define WM8350_OUT3_TO_OUT4                     0x0004
+#define WM8350_MIXOUTR_TO_OUT4                  0x0002
+#define WM8350_MIXOUTL_TO_OUT4                  0x0001
+
+/*
+ * R96 (0x60) - Output Left Mixer Volume
+ */
+#define WM8350_IN3L_MIXOUTL_VOL_MASK            0x0E00
+#define WM8350_IN3L_MIXOUTL_VOL_SHIFT                9
+#define WM8350_INR_MIXOUTL_VOL_MASK             0x00E0
+#define WM8350_INR_MIXOUTL_VOL_SHIFT                 5
+#define WM8350_INL_MIXOUTL_VOL_MASK             0x000E
+#define WM8350_INL_MIXOUTL_VOL_SHIFT                 1
+
+/* Bit values for R96 (0x60) */
+#define WM8350_IN3L_MIXOUTL_VOL_OFF                  0
+#define WM8350_IN3L_MIXOUTL_VOL_M12DB                1
+#define WM8350_IN3L_MIXOUTL_VOL_M9DB                 2
+#define WM8350_IN3L_MIXOUTL_VOL_M6DB                 3
+#define WM8350_IN3L_MIXOUTL_VOL_M3DB                 4
+#define WM8350_IN3L_MIXOUTL_VOL_0DB                  5
+#define WM8350_IN3L_MIXOUTL_VOL_3DB                  6
+#define WM8350_IN3L_MIXOUTL_VOL_6DB                  7
+
+#define WM8350_INR_MIXOUTL_VOL_OFF                   0
+#define WM8350_INR_MIXOUTL_VOL_M12DB                 1
+#define WM8350_INR_MIXOUTL_VOL_M9DB                  2
+#define WM8350_INR_MIXOUTL_VOL_M6DB                  3
+#define WM8350_INR_MIXOUTL_VOL_M3DB                  4
+#define WM8350_INR_MIXOUTL_VOL_0DB                   5
+#define WM8350_INR_MIXOUTL_VOL_3DB                   6
+#define WM8350_INR_MIXOUTL_VOL_6DB                   7
+
+#define WM8350_INL_MIXOUTL_VOL_OFF                   0
+#define WM8350_INL_MIXOUTL_VOL_M12DB                 1
+#define WM8350_INL_MIXOUTL_VOL_M9DB                  2
+#define WM8350_INL_MIXOUTL_VOL_M6DB                  3
+#define WM8350_INL_MIXOUTL_VOL_M3DB                  4
+#define WM8350_INL_MIXOUTL_VOL_0DB                   5
+#define WM8350_INL_MIXOUTL_VOL_3DB                   6
+#define WM8350_INL_MIXOUTL_VOL_6DB                   7
+
+/*
+ * R97 (0x61) - Output Right Mixer Volume
+ */
+#define WM8350_IN3R_MIXOUTR_VOL_MASK            0xE000
+#define WM8350_IN3R_MIXOUTR_VOL_SHIFT               13
+#define WM8350_INR_MIXOUTR_VOL_MASK             0x00E0
+#define WM8350_INR_MIXOUTR_VOL_SHIFT                 5
+#define WM8350_INL_MIXOUTR_VOL_MASK             0x000E
+#define WM8350_INL_MIXOUTR_VOL_SHIFT                 1
+
+/* Bit values for R96 (0x60) */
+#define WM8350_IN3R_MIXOUTR_VOL_OFF                  0
+#define WM8350_IN3R_MIXOUTR_VOL_M12DB                1
+#define WM8350_IN3R_MIXOUTR_VOL_M9DB                 2
+#define WM8350_IN3R_MIXOUTR_VOL_M6DB                 3
+#define WM8350_IN3R_MIXOUTR_VOL_M3DB                 4
+#define WM8350_IN3R_MIXOUTR_VOL_0DB                  5
+#define WM8350_IN3R_MIXOUTR_VOL_3DB                  6
+#define WM8350_IN3R_MIXOUTR_VOL_6DB                  7
+
+#define WM8350_INR_MIXOUTR_VOL_OFF                   0
+#define WM8350_INR_MIXOUTR_VOL_M12DB                 1
+#define WM8350_INR_MIXOUTR_VOL_M9DB                  2
+#define WM8350_INR_MIXOUTR_VOL_M6DB                  3
+#define WM8350_INR_MIXOUTR_VOL_M3DB                  4
+#define WM8350_INR_MIXOUTR_VOL_0DB                   5
+#define WM8350_INR_MIXOUTR_VOL_3DB                   6
+#define WM8350_INR_MIXOUTR_VOL_6DB                   7
+
+#define WM8350_INL_MIXOUTR_VOL_OFF                   0
+#define WM8350_INL_MIXOUTR_VOL_M12DB                 1
+#define WM8350_INL_MIXOUTR_VOL_M9DB                  2
+#define WM8350_INL_MIXOUTR_VOL_M6DB                  3
+#define WM8350_INL_MIXOUTR_VOL_M3DB                  4
+#define WM8350_INL_MIXOUTR_VOL_0DB                   5
+#define WM8350_INL_MIXOUTR_VOL_3DB                   6
+#define WM8350_INL_MIXOUTR_VOL_6DB                   7
+
+/*
+ * R98 (0x62) - Input Mixer Volume L
+ */
+#define WM8350_IN3L_MIXINL_VOL_MASK             0x0E00
+#define WM8350_IN2L_MIXINL_VOL_MASK             0x000E
+#define WM8350_INL_MIXINL_VOL                   0x0001
+
+/*
+ * R99 (0x63) - Input Mixer Volume R
+ */
+#define WM8350_IN3R_MIXINR_VOL_MASK             0xE000
+#define WM8350_IN2R_MIXINR_VOL_MASK             0x00E0
+#define WM8350_INR_MIXINR_VOL                   0x0001
+
+/*
+ * R100 (0x64) - Input Mixer Volume
+ */
+#define WM8350_OUT4_MIXIN_DST                   0x8000
+#define WM8350_OUT4_MIXIN_VOL_MASK              0x000E
+
+/*
+ * R104 (0x68) - LOUT1 Volume
+ */
+#define WM8350_OUT1L_MUTE                       0x4000
+#define WM8350_OUT1L_ZC                         0x2000
+#define WM8350_OUT1_VU                          0x0100
+#define WM8350_OUT1L_VOL_MASK                   0x00FC
+#define WM8350_OUT1L_VOL_SHIFT                       2
+
+/*
+ * R105 (0x69) - ROUT1 Volume
+ */
+#define WM8350_OUT1R_MUTE                       0x4000
+#define WM8350_OUT1R_ZC                         0x2000
+#define WM8350_OUT1_VU                          0x0100
+#define WM8350_OUT1R_VOL_MASK                   0x00FC
+#define WM8350_OUT1R_VOL_SHIFT                       2
+
+/*
+ * R106 (0x6A) - LOUT2 Volume
+ */
+#define WM8350_OUT2L_MUTE                       0x4000
+#define WM8350_OUT2L_ZC                         0x2000
+#define WM8350_OUT2_VU                          0x0100
+#define WM8350_OUT2L_VOL_MASK                   0x00FC
+
+/*
+ * R107 (0x6B) - ROUT2 Volume
+ */
+#define WM8350_OUT2R_MUTE                       0x4000
+#define WM8350_OUT2R_ZC                         0x2000
+#define WM8350_OUT2R_INV                        0x0400
+#define WM8350_OUT2R_INV_MUTE                   0x0200
+#define WM8350_OUT2_VU                          0x0100
+#define WM8350_OUT2R_VOL_MASK                   0x00FC
+
+/*
+ * R111 (0x6F) - BEEP Volume
+ */
+#define WM8350_IN3R_OUT2R_VOL_MASK              0x00E0
+
+/*
+ * R112 (0x70) - AI Formating
+ */
+#define WM8350_AIF_BCLK_INV                     0x8000
+#define WM8350_AIF_TRI                          0x2000
+#define WM8350_AIF_LRCLK_INV                    0x1000
+#define WM8350_AIF_WL_MASK                      0x0C00
+#define WM8350_AIF_FMT_MASK                     0x0300
+
+/*
+ * R113 (0x71) - ADC DAC COMP
+ */
+#define WM8350_DAC_COMP                         0x0080
+#define WM8350_DAC_COMPMODE                     0x0040
+#define WM8350_ADC_COMP                         0x0020
+#define WM8350_ADC_COMPMODE                     0x0010
+#define WM8350_LOOPBACK                         0x0001
+
+/*
+ * R114 (0x72) - AI ADC Control
+ */
+#define WM8350_AIFADC_PD                        0x0080
+#define WM8350_AIFADCL_SRC                      0x0040
+#define WM8350_AIFADCR_SRC                      0x0020
+#define WM8350_AIFADC_TDM_CHAN                  0x0010
+#define WM8350_AIFADC_TDM                       0x0008
+
+/*
+ * R115 (0x73) - AI DAC Control
+ */
+#define WM8350_BCLK_MSTR                        0x4000
+#define WM8350_AIFDAC_PD                        0x0080
+#define WM8350_DACL_SRC                         0x0040
+#define WM8350_DACR_SRC                         0x0020
+#define WM8350_AIFDAC_TDM_CHAN                  0x0010
+#define WM8350_AIFDAC_TDM                       0x0008
+#define WM8350_DAC_BOOST_MASK                   0x0003
+
+/*
+ * R116 (0x74) - AIF Test
+ */
+#define WM8350_CODEC_BYP                        0x4000
+#define WM8350_AIFADC_WR_TST                    0x2000
+#define WM8350_AIFADC_RD_TST                    0x1000
+#define WM8350_AIFDAC_WR_TST                    0x0800
+#define WM8350_AIFDAC_RD_TST                    0x0400
+#define WM8350_AIFADC_ASYN                      0x0020
+#define WM8350_AIFDAC_ASYN                      0x0010
+
+/*
+ * R231 (0xE7) - Jack Status
+ */
+#define WM8350_JACK_R_LVL                       0x0400
+
+/*
+ * WM8350 Platform setup
+ */
+#define WM8350_S_CURVE_NONE                     0x0
+#define WM8350_S_CURVE_FAST                     0x1
+#define WM8350_S_CURVE_MEDIUM                   0x2
+#define WM8350_S_CURVE_SLOW                     0x3
+
+#define WM8350_DISCHARGE_OFF                    0x0
+#define WM8350_DISCHARGE_FAST                   0x1
+#define WM8350_DISCHARGE_MEDIUM                 0x2
+#define WM8350_DISCHARGE_SLOW                   0x3
+
+#define WM8350_TIE_OFF_500R                     0x0
+#define WM8350_TIE_OFF_30K                      0x1
+
+/*
+ * Clock sources & directions
+ */
+#define WM8350_SYSCLK                           0
+
+#define WM8350_MCLK_SEL_PLL_MCLK                0
+#define WM8350_MCLK_SEL_PLL_DAC                 1
+#define WM8350_MCLK_SEL_PLL_ADC                 2
+#define WM8350_MCLK_SEL_PLL_32K                 3
+#define WM8350_MCLK_SEL_MCLK                    5
+
+#define WM8350_MCLK_DIR_OUT                     0
+#define WM8350_MCLK_DIR_IN                      1
+
+/* clock divider id's */
+#define WM8350_ADC_CLKDIV                       0
+#define WM8350_DAC_CLKDIV                       1
+#define WM8350_BCLK_CLKDIV                      2
+#define WM8350_OPCLK_CLKDIV                     3
+#define WM8350_TO_CLKDIV                        4
+#define WM8350_SYS_CLKDIV                       5
+#define WM8350_DACLR_CLKDIV                     6
+#define WM8350_ADCLR_CLKDIV                     7
+
+/* ADC clock dividers */
+#define WM8350_ADCDIV_1                         0x0
+#define WM8350_ADCDIV_1_5                       0x1
+#define WM8350_ADCDIV_2                         0x2
+#define WM8350_ADCDIV_3                         0x3
+#define WM8350_ADCDIV_4                         0x4
+#define WM8350_ADCDIV_5_5                       0x5
+#define WM8350_ADCDIV_6                         0x6
+
+/* ADC clock dividers */
+#define WM8350_DACDIV_1                         0x0
+#define WM8350_DACDIV_1_5                       0x1
+#define WM8350_DACDIV_2                         0x2
+#define WM8350_DACDIV_3                         0x3
+#define WM8350_DACDIV_4                         0x4
+#define WM8350_DACDIV_5_5                       0x5
+#define WM8350_DACDIV_6                         0x6
+
+/* BCLK clock dividers */
+#define WM8350_BCLK_DIV_1                       (0x0 << 4)
+#define WM8350_BCLK_DIV_1_5                     (0x1 << 4)
+#define WM8350_BCLK_DIV_2                       (0x2 << 4)
+#define WM8350_BCLK_DIV_3                       (0x3 << 4)
+#define WM8350_BCLK_DIV_4                       (0x4 << 4)
+#define WM8350_BCLK_DIV_5_5                     (0x5 << 4)
+#define WM8350_BCLK_DIV_6                       (0x6 << 4)
+#define WM8350_BCLK_DIV_8                       (0x7 << 4)
+#define WM8350_BCLK_DIV_11                      (0x8 << 4)
+#define WM8350_BCLK_DIV_12                      (0x9 << 4)
+#define WM8350_BCLK_DIV_16                      (0xa << 4)
+#define WM8350_BCLK_DIV_22                      (0xb << 4)
+#define WM8350_BCLK_DIV_24                      (0xc << 4)
+#define WM8350_BCLK_DIV_32                      (0xd << 4)
+#define WM8350_BCLK_DIV_44                      (0xe << 4)
+#define WM8350_BCLK_DIV_48                      (0xf << 4)
+
+/* Sys (MCLK) clock dividers */
+#define WM8350_MCLK_DIV_1                       (0x0 << 8)
+#define WM8350_MCLK_DIV_2                       (0x1 << 8)
+
+/* OP clock dividers */
+#define WM8350_OPCLK_DIV_1                      0x0
+#define WM8350_OPCLK_DIV_2                      0x1
+#define WM8350_OPCLK_DIV_3                      0x2
+#define WM8350_OPCLK_DIV_4                      0x3
+#define WM8350_OPCLK_DIV_5_5                    0x4
+#define WM8350_OPCLK_DIV_6                      0x5
+
+/* DAI ID */
+#define WM8350_HIFI_DAI                         0
+
+/*
+ * Audio interrupts.
+ */
+#define WM8350_IRQ_CODEC_JCK_DET_L              39
+#define WM8350_IRQ_CODEC_JCK_DET_R              40
+#define WM8350_IRQ_CODEC_MICSCD                 41
+#define WM8350_IRQ_CODEC_MICD                   42
+
+struct wm8350_codec {
+        struct platform_device *pdev;
+};
+
+#endif
diff --git a/include/linux/mfd/wm8350/comparator.h b/include/linux/mfd/wm8350/comparator.h
new file mode 100644
index 000000000000..053788649452
--- /dev/null
+++ b/include/linux/mfd/wm8350/comparator.h
@@ -0,0 +1,167 @@
+/*
+ * comparator.h  --  Comparator Aux ADC for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __LINUX_MFD_WM8350_COMPARATOR_H_
+#define __LINUX_MFD_WM8350_COMPARATOR_H_
+
+/*
+ * Registers
+ */
+
+#define WM8350_DIGITISER_CONTROL_1              0x90
+#define WM8350_DIGITISER_CONTROL_2              0x91
+#define WM8350_AUX1_READBACK                    0x98
+#define WM8350_AUX2_READBACK                    0x99
+#define WM8350_AUX3_READBACK                    0x9A
+#define WM8350_AUX4_READBACK                    0x9B
+#define WM8350_CHIP_TEMP_READBACK               0x9F
+#define WM8350_GENERIC_COMPARATOR_CONTROL       0xA3
+#define WM8350_GENERIC_COMPARATOR_1             0xA4
+#define WM8350_GENERIC_COMPARATOR_2             0xA5
+#define WM8350_GENERIC_COMPARATOR_3             0xA6
+#define WM8350_GENERIC_COMPARATOR_4             0xA7
+
+/*
+ * R144 (0x90) - Digitiser Control (1)
+ */
+#define WM8350_AUXADC_CTC                       0x4000
+#define WM8350_AUXADC_POLL                      0x2000
+#define WM8350_AUXADC_HIB_MODE                  0x1000
+#define WM8350_AUXADC_SEL8                      0x0080
+#define WM8350_AUXADC_SEL7                      0x0040
+#define WM8350_AUXADC_SEL6                      0x0020
+#define WM8350_AUXADC_SEL5                      0x0010
+#define WM8350_AUXADC_SEL4                      0x0008
+#define WM8350_AUXADC_SEL3                      0x0004
+#define WM8350_AUXADC_SEL2                      0x0002
+#define WM8350_AUXADC_SEL1                      0x0001
+
+/*
+ * R145 (0x91) - Digitiser Control (2)
+ */
+#define WM8350_AUXADC_MASKMODE_MASK             0x3000
+#define WM8350_AUXADC_CRATE_MASK                0x0700
+#define WM8350_AUXADC_CAL                       0x0004
+#define WM8350_AUX_RBMODE                       0x0002
+#define WM8350_AUXADC_WAIT                      0x0001
+
+/*
+ * R152 (0x98) - AUX1 Readback
+ */
+#define WM8350_AUXADC_SCALE1_MASK               0x6000
+#define WM8350_AUXADC_REF1                      0x1000
+#define WM8350_AUXADC_DATA1_MASK                0x0FFF
+
+/*
+ * R153 (0x99) - AUX2 Readback
+ */
+#define WM8350_AUXADC_SCALE2_MASK               0x6000
+#define WM8350_AUXADC_REF2                      0x1000
+#define WM8350_AUXADC_DATA2_MASK                0x0FFF
+
+/*
+ * R154 (0x9A) - AUX3 Readback
+ */
+#define WM8350_AUXADC_SCALE3_MASK               0x6000
+#define WM8350_AUXADC_REF3                      0x1000
+#define WM8350_AUXADC_DATA3_MASK                0x0FFF
+
+/*
+ * R155 (0x9B) - AUX4 Readback
+ */
+#define WM8350_AUXADC_SCALE4_MASK               0x6000
+#define WM8350_AUXADC_REF4                      0x1000
+#define WM8350_AUXADC_DATA4_MASK                0x0FFF
+
+/*
+ * R156 (0x9C) - USB Voltage Readback
+ */
+#define WM8350_AUXADC_DATA_USB_MASK             0x0FFF
+
+/*
+ * R157 (0x9D) - LINE Voltage Readback
+ */
+#define WM8350_AUXADC_DATA_LINE_MASK            0x0FFF
+
+/*
+ * R158 (0x9E) - BATT Voltage Readback
+ */
+#define WM8350_AUXADC_DATA_BATT_MASK            0x0FFF
+
+/*
+ * R159 (0x9F) - Chip Temp Readback
+ */
+#define WM8350_AUXADC_DATA_CHIPTEMP_MASK        0x0FFF
+
+/*
+ * R163 (0xA3) - Generic Comparator Control
+ */
+#define WM8350_DCMP4_ENA                        0x0008
+#define WM8350_DCMP3_ENA                        0x0004
+#define WM8350_DCMP2_ENA                        0x0002
+#define WM8350_DCMP1_ENA                        0x0001
+
+/*
+ * R164 (0xA4) - Generic comparator 1
+ */
+#define WM8350_DCMP1_SRCSEL_MASK                0xE000
+#define WM8350_DCMP1_GT                         0x1000
+#define WM8350_DCMP1_THR_MASK                   0x0FFF
+
+/*
+ * R165 (0xA5) - Generic comparator 2
+ */
+#define WM8350_DCMP2_SRCSEL_MASK                0xE000
+#define WM8350_DCMP2_GT                         0x1000
+#define WM8350_DCMP2_THR_MASK                   0x0FFF
+
+/*
+ * R166 (0xA6) - Generic comparator 3
+ */
+#define WM8350_DCMP3_SRCSEL_MASK                0xE000
+#define WM8350_DCMP3_GT                         0x1000
+#define WM8350_DCMP3_THR_MASK                   0x0FFF
+
+/*
+ * R167 (0xA7) - Generic comparator 4
+ */
+#define WM8350_DCMP4_SRCSEL_MASK                0xE000
+#define WM8350_DCMP4_GT                         0x1000
+#define WM8350_DCMP4_THR_MASK                   0x0FFF
+
+/*
+ * Interrupts.
+ */
+#define WM8350_IRQ_AUXADC_DATARDY               16
+#define WM8350_IRQ_AUXADC_DCOMP4                17
+#define WM8350_IRQ_AUXADC_DCOMP3                18
+#define WM8350_IRQ_AUXADC_DCOMP2                19
+#define WM8350_IRQ_AUXADC_DCOMP1                20
+#define WM8350_IRQ_SYS_HYST_COMP_FAIL           21
+#define WM8350_IRQ_SYS_CHIP_GT115               22
+#define WM8350_IRQ_SYS_CHIP_GT140               23
+
+/*
+ * USB/2, LINE & BATT = ((VRTC * 2) / 4095)) * 10e6 uV
+ * Where VRTC = 2.7 V
+ */
+#define WM8350_AUX_COEFF                        1319
+
+#define WM8350_AUXADC_AUX1                      0
+#define WM8350_AUXADC_AUX2                      1
+#define WM8350_AUXADC_AUX3                      2
+#define WM8350_AUXADC_AUX4                      3
+#define WM8350_AUXADC_USB                       4
+#define WM8350_AUXADC_LINE                      5
+#define WM8350_AUXADC_BATT                      6
+#define WM8350_AUXADC_TEMP                      7
+
+#endif
diff --git a/include/linux/mfd/wm8350/core.h b/include/linux/mfd/wm8350/core.h
new file mode 100644
index 000000000000..6ebf97f2a475
--- /dev/null
+++ b/include/linux/mfd/wm8350/core.h
@@ -0,0 +1,631 @@
+/*
+ * core.h  --  Core Driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_WM8350_CORE_H_
+#define __LINUX_MFD_WM8350_CORE_H_
+
+#include <linux/kernel.h>
+#include <linux/mutex.h>
+#include <linux/workqueue.h>
+
+#include <linux/mfd/wm8350/audio.h>
+#include <linux/mfd/wm8350/gpio.h>
+#include <linux/mfd/wm8350/pmic.h>
+#include <linux/mfd/wm8350/rtc.h>
+#include <linux/mfd/wm8350/supply.h>
+#include <linux/mfd/wm8350/wdt.h>
+
+/*
+ * Register values.
+ */
+#define WM8350_RESET_ID                         0x00
+#define WM8350_ID                               0x01
+#define WM8350_SYSTEM_CONTROL_1                 0x03
+#define WM8350_SYSTEM_CONTROL_2                 0x04
+#define WM8350_SYSTEM_HIBERNATE                 0x05
+#define WM8350_INTERFACE_CONTROL                0x06
+#define WM8350_POWER_MGMT_1                     0x08
+#define WM8350_POWER_MGMT_2                     0x09
+#define WM8350_POWER_MGMT_3                     0x0A
+#define WM8350_POWER_MGMT_4                     0x0B
+#define WM8350_POWER_MGMT_5                     0x0C
+#define WM8350_POWER_MGMT_6                     0x0D
+#define WM8350_POWER_MGMT_7                     0x0E
+
+#define WM8350_SYSTEM_INTERRUPTS                0x18
+#define WM8350_INT_STATUS_1                     0x19
+#define WM8350_INT_STATUS_2                     0x1A
+#define WM8350_POWER_UP_INT_STATUS              0x1B
+#define WM8350_UNDER_VOLTAGE_INT_STATUS         0x1C
+#define WM8350_OVER_CURRENT_INT_STATUS          0x1D
+#define WM8350_GPIO_INT_STATUS                  0x1E
+#define WM8350_COMPARATOR_INT_STATUS            0x1F
+#define WM8350_SYSTEM_INTERRUPTS_MASK           0x20
+#define WM8350_INT_STATUS_1_MASK                0x21
+#define WM8350_INT_STATUS_2_MASK                0x22
+#define WM8350_POWER_UP_INT_STATUS_MASK         0x23
+#define WM8350_UNDER_VOLTAGE_INT_STATUS_MASK    0x24
+#define WM8350_OVER_CURRENT_INT_STATUS_MASK     0x25
+#define WM8350_GPIO_INT_STATUS_MASK             0x26
+#define WM8350_COMPARATOR_INT_STATUS_MASK       0x27
+
+#define WM8350_MAX_REGISTER                     0xFF
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Reset/ID
+ */
+#define WM8350_SW_RESET_CHIP_ID_MASK            0xFFFF
+
+/*
+ * R1 (0x01) - ID
+ */
+#define WM8350_CHIP_REV_MASK                    0x7000
+#define WM8350_CONF_STS_MASK                    0x0C00
+#define WM8350_CUST_ID_MASK                     0x00FF
+
+/*
+ * R3 (0x03) - System Control 1
+ */
+#define WM8350_CHIP_ON                          0x8000
+#define WM8350_POWERCYCLE                       0x2000
+#define WM8350_VCC_FAULT_OV                     0x1000
+#define WM8350_REG_RSTB_TIME_MASK               0x0C00
+#define WM8350_BG_SLEEP                         0x0200
+#define WM8350_MEM_VALID                        0x0020
+#define WM8350_CHIP_SET_UP                      0x0010
+#define WM8350_ON_DEB_T                         0x0008
+#define WM8350_ON_POL                           0x0002
+#define WM8350_IRQ_POL                          0x0001
+
+/*
+ * R4 (0x04) - System Control 2
+ */
+#define WM8350_USB_SUSPEND_8MA                  0x8000
+#define WM8350_USB_SUSPEND                      0x4000
+#define WM8350_USB_MSTR                         0x2000
+#define WM8350_USB_MSTR_SRC                     0x1000
+#define WM8350_USB_500MA                        0x0800
+#define WM8350_USB_NOLIM                        0x0400
+
+/*
+ * R5 (0x05) - System Hibernate
+ */
+#define WM8350_HIBERNATE                        0x8000
+#define WM8350_WDOG_HIB_MODE                    0x0080
+#define WM8350_REG_HIB_STARTUP_SEQ              0x0040
+#define WM8350_REG_RESET_HIB_MODE               0x0020
+#define WM8350_RST_HIB_MODE                     0x0010
+#define WM8350_IRQ_HIB_MODE                     0x0008
+#define WM8350_MEMRST_HIB_MODE                  0x0004
+#define WM8350_PCCOMP_HIB_MODE                  0x0002
+#define WM8350_TEMPMON_HIB_MODE                 0x0001
+
+/*
+ * R6 (0x06) - Interface Control
+ */
+#define WM8350_USE_DEV_PINS                     0x8000
+#define WM8350_USE_DEV_PINS_MASK                0x8000
+#define WM8350_USE_DEV_PINS_SHIFT                   15
+#define WM8350_DEV_ADDR_MASK                    0x6000
+#define WM8350_DEV_ADDR_SHIFT                       13
+#define WM8350_CONFIG_DONE                      0x1000
+#define WM8350_CONFIG_DONE_MASK                 0x1000
+#define WM8350_CONFIG_DONE_SHIFT                    12
+#define WM8350_RECONFIG_AT_ON                   0x0800
+#define WM8350_RECONFIG_AT_ON_MASK              0x0800
+#define WM8350_RECONFIG_AT_ON_SHIFT                 11
+#define WM8350_AUTOINC                          0x0200
+#define WM8350_AUTOINC_MASK                     0x0200
+#define WM8350_AUTOINC_SHIFT                         9
+#define WM8350_ARA                              0x0100
+#define WM8350_ARA_MASK                         0x0100
+#define WM8350_ARA_SHIFT                             8
+#define WM8350_SPI_CFG                          0x0008
+#define WM8350_SPI_CFG_MASK                     0x0008
+#define WM8350_SPI_CFG_SHIFT                         3
+#define WM8350_SPI_4WIRE                        0x0004
+#define WM8350_SPI_4WIRE_MASK                   0x0004
+#define WM8350_SPI_4WIRE_SHIFT                       2
+#define WM8350_SPI_3WIRE                        0x0002
+#define WM8350_SPI_3WIRE_MASK                   0x0002
+#define WM8350_SPI_3WIRE_SHIFT                       1
+
+/* Bit values for R06 (0x06) */
+#define WM8350_USE_DEV_PINS_PRIMARY                  0
+#define WM8350_USE_DEV_PINS_DEV                      1
+
+#define WM8350_DEV_ADDR_34                           0
+#define WM8350_DEV_ADDR_36                           1
+#define WM8350_DEV_ADDR_3C                           2
+#define WM8350_DEV_ADDR_3E                           3
+
+#define WM8350_CONFIG_DONE_OFF                       0
+#define WM8350_CONFIG_DONE_DONE                      1
+
+#define WM8350_RECONFIG_AT_ON_OFF                    0
+#define WM8350_RECONFIG_AT_ON_ON                     1
+
+#define WM8350_AUTOINC_OFF                           0
+#define WM8350_AUTOINC_ON                            1
+
+#define WM8350_ARA_OFF                               0
+#define WM8350_ARA_ON                                1
+
+#define WM8350_SPI_CFG_CMOS                          0
+#define WM8350_SPI_CFG_OD                            1
+
+#define WM8350_SPI_4WIRE_3WIRE                       0
+#define WM8350_SPI_4WIRE_4WIRE                       1
+
+#define WM8350_SPI_3WIRE_I2C                         0
+#define WM8350_SPI_3WIRE_SPI                         1
+
+/*
+ * R8 (0x08) - Power mgmt (1)
+ */
+#define WM8350_CODEC_ISEL_MASK                  0xC000
+#define WM8350_VBUFEN                           0x2000
+#define WM8350_OUTPUT_DRAIN_EN                  0x0400
+#define WM8350_MIC_DET_ENA                      0x0100
+#define WM8350_BIASEN                           0x0020
+#define WM8350_MICBEN                           0x0010
+#define WM8350_VMIDEN                           0x0004
+#define WM8350_VMID_MASK                        0x0003
+#define WM8350_VMID_SHIFT                            0
+
+/*
+ * R9 (0x09) - Power mgmt (2)
+ */
+#define WM8350_IN3R_ENA                         0x0800
+#define WM8350_IN3L_ENA                         0x0400
+#define WM8350_INR_ENA                          0x0200
+#define WM8350_INL_ENA                          0x0100
+#define WM8350_MIXINR_ENA                       0x0080
+#define WM8350_MIXINL_ENA                       0x0040
+#define WM8350_OUT4_ENA                         0x0020
+#define WM8350_OUT3_ENA                         0x0010
+#define WM8350_MIXOUTR_ENA                      0x0002
+#define WM8350_MIXOUTL_ENA                      0x0001
+
+/*
+ * R10 (0x0A) - Power mgmt (3)
+ */
+#define WM8350_IN3R_TO_OUT2R                    0x0080
+#define WM8350_OUT2R_ENA                        0x0008
+#define WM8350_OUT2L_ENA                        0x0004
+#define WM8350_OUT1R_ENA                        0x0002
+#define WM8350_OUT1L_ENA                        0x0001
+
+/*
+ * R11 (0x0B) - Power mgmt (4)
+ */
+#define WM8350_SYSCLK_ENA                       0x4000
+#define WM8350_ADC_HPF_ENA                      0x2000
+#define WM8350_FLL_ENA                          0x0800
+#define WM8350_FLL_OSC_ENA                      0x0400
+#define WM8350_TOCLK_ENA                        0x0100
+#define WM8350_DACR_ENA                         0x0020
+#define WM8350_DACL_ENA                         0x0010
+#define WM8350_ADCR_ENA                         0x0008
+#define WM8350_ADCL_ENA                         0x0004
+
+/*
+ * R12 (0x0C) - Power mgmt (5)
+ */
+#define WM8350_CODEC_ENA                        0x1000
+#define WM8350_RTC_TICK_ENA                     0x0800
+#define WM8350_OSC32K_ENA                       0x0400
+#define WM8350_CHG_ENA                          0x0200
+#define WM8350_ACC_DET_ENA                      0x0100
+#define WM8350_AUXADC_ENA                       0x0080
+#define WM8350_DCMP4_ENA                        0x0008
+#define WM8350_DCMP3_ENA                        0x0004
+#define WM8350_DCMP2_ENA                        0x0002
+#define WM8350_DCMP1_ENA                        0x0001
+
+/*
+ * R13 (0x0D) - Power mgmt (6)
+ */
+#define WM8350_LS_ENA                           0x8000
+#define WM8350_LDO4_ENA                         0x0800
+#define WM8350_LDO3_ENA                         0x0400
+#define WM8350_LDO2_ENA                         0x0200
+#define WM8350_LDO1_ENA                         0x0100
+#define WM8350_DC6_ENA                          0x0020
+#define WM8350_DC5_ENA                          0x0010
+#define WM8350_DC4_ENA                          0x0008
+#define WM8350_DC3_ENA                          0x0004
+#define WM8350_DC2_ENA                          0x0002
+#define WM8350_DC1_ENA                          0x0001
+
+/*
+ * R14 (0x0E) - Power mgmt (7)
+ */
+#define WM8350_CS2_ENA                          0x0002
+#define WM8350_CS1_ENA                          0x0001
+
+/*
+ * R24 (0x18) - System Interrupts
+ */
+#define WM8350_OC_INT                           0x2000
+#define WM8350_UV_INT                           0x1000
+#define WM8350_PUTO_INT                         0x0800
+#define WM8350_CS_INT                           0x0200
+#define WM8350_EXT_INT                          0x0100
+#define WM8350_CODEC_INT                        0x0080
+#define WM8350_GP_INT                           0x0040
+#define WM8350_AUXADC_INT                       0x0020
+#define WM8350_RTC_INT                          0x0010
+#define WM8350_SYS_INT                          0x0008
+#define WM8350_CHG_INT                          0x0004
+#define WM8350_USB_INT                          0x0002
+#define WM8350_WKUP_INT                         0x0001
+
+/*
+ * R25 (0x19) - Interrupt Status 1
+ */
+#define WM8350_CHG_BAT_HOT_EINT                 0x8000
+#define WM8350_CHG_BAT_COLD_EINT                0x4000
+#define WM8350_CHG_BAT_FAIL_EINT                0x2000
+#define WM8350_CHG_TO_EINT                      0x1000
+#define WM8350_CHG_END_EINT                     0x0800
+#define WM8350_CHG_START_EINT                   0x0400
+#define WM8350_CHG_FAST_RDY_EINT                0x0200
+#define WM8350_RTC_PER_EINT                     0x0080
+#define WM8350_RTC_SEC_EINT                     0x0040
+#define WM8350_RTC_ALM_EINT                     0x0020
+#define WM8350_CHG_VBATT_LT_3P9_EINT            0x0004
+#define WM8350_CHG_VBATT_LT_3P1_EINT            0x0002
+#define WM8350_CHG_VBATT_LT_2P85_EINT           0x0001
+
+/*
+ * R26 (0x1A) - Interrupt Status 2
+ */
+#define WM8350_CS1_EINT                         0x2000
+#define WM8350_CS2_EINT                         0x1000
+#define WM8350_USB_LIMIT_EINT                   0x0400
+#define WM8350_AUXADC_DATARDY_EINT              0x0100
+#define WM8350_AUXADC_DCOMP4_EINT               0x0080
+#define WM8350_AUXADC_DCOMP3_EINT               0x0040
+#define WM8350_AUXADC_DCOMP2_EINT               0x0020
+#define WM8350_AUXADC_DCOMP1_EINT               0x0010
+#define WM8350_SYS_HYST_COMP_FAIL_EINT          0x0008
+#define WM8350_SYS_CHIP_GT115_EINT              0x0004
+#define WM8350_SYS_CHIP_GT140_EINT              0x0002
+#define WM8350_SYS_WDOG_TO_EINT                 0x0001
+
+/*
+ * R27 (0x1B) - Power Up Interrupt Status
+ */
+#define WM8350_PUTO_LDO4_EINT                   0x0800
+#define WM8350_PUTO_LDO3_EINT                   0x0400
+#define WM8350_PUTO_LDO2_EINT                   0x0200
+#define WM8350_PUTO_LDO1_EINT                   0x0100
+#define WM8350_PUTO_DC6_EINT                    0x0020
+#define WM8350_PUTO_DC5_EINT                    0x0010
+#define WM8350_PUTO_DC4_EINT                    0x0008
+#define WM8350_PUTO_DC3_EINT                    0x0004
+#define WM8350_PUTO_DC2_EINT                    0x0002
+#define WM8350_PUTO_DC1_EINT                    0x0001
+
+/*
+ * R28 (0x1C) - Under Voltage Interrupt status
+ */
+#define WM8350_UV_LDO4_EINT                     0x0800
+#define WM8350_UV_LDO3_EINT                     0x0400
+#define WM8350_UV_LDO2_EINT                     0x0200
+#define WM8350_UV_LDO1_EINT                     0x0100
+#define WM8350_UV_DC6_EINT                      0x0020
+#define WM8350_UV_DC5_EINT                      0x0010
+#define WM8350_UV_DC4_EINT                      0x0008
+#define WM8350_UV_DC3_EINT                      0x0004
+#define WM8350_UV_DC2_EINT                      0x0002
+#define WM8350_UV_DC1_EINT                      0x0001
+
+/*
+ * R29 (0x1D) - Over Current Interrupt status
+ */
+#define WM8350_OC_LS_EINT                       0x8000
+
+/*
+ * R30 (0x1E) - GPIO Interrupt Status
+ */
+#define WM8350_GP12_EINT                        0x1000
+#define WM8350_GP11_EINT                        0x0800
+#define WM8350_GP10_EINT                        0x0400
+#define WM8350_GP9_EINT                         0x0200
+#define WM8350_GP8_EINT                         0x0100
+#define WM8350_GP7_EINT                         0x0080
+#define WM8350_GP6_EINT                         0x0040
+#define WM8350_GP5_EINT                         0x0020
+#define WM8350_GP4_EINT                         0x0010
+#define WM8350_GP3_EINT                         0x0008
+#define WM8350_GP2_EINT                         0x0004
+#define WM8350_GP1_EINT                         0x0002
+#define WM8350_GP0_EINT                         0x0001
+
+/*
+ * R31 (0x1F) - Comparator Interrupt Status
+ */
+#define WM8350_EXT_USB_FB_EINT                  0x8000
+#define WM8350_EXT_WALL_FB_EINT                 0x4000
+#define WM8350_EXT_BAT_FB_EINT                  0x2000
+#define WM8350_CODEC_JCK_DET_L_EINT             0x0800
+#define WM8350_CODEC_JCK_DET_R_EINT             0x0400
+#define WM8350_CODEC_MICSCD_EINT                0x0200
+#define WM8350_CODEC_MICD_EINT                  0x0100
+#define WM8350_WKUP_OFF_STATE_EINT              0x0040
+#define WM8350_WKUP_HIB_STATE_EINT              0x0020
+#define WM8350_WKUP_CONV_FAULT_EINT             0x0010
+#define WM8350_WKUP_WDOG_RST_EINT               0x0008
+#define WM8350_WKUP_GP_PWR_ON_EINT              0x0004
+#define WM8350_WKUP_ONKEY_EINT                  0x0002
+#define WM8350_WKUP_GP_WAKEUP_EINT              0x0001
+
+/*
+ * R32 (0x20) - System Interrupts Mask
+ */
+#define WM8350_IM_OC_INT                        0x2000
+#define WM8350_IM_UV_INT                        0x1000
+#define WM8350_IM_PUTO_INT                      0x0800
+#define WM8350_IM_SPARE_INT                     0x0400
+#define WM8350_IM_CS_INT                        0x0200
+#define WM8350_IM_EXT_INT                       0x0100
+#define WM8350_IM_CODEC_INT                     0x0080
+#define WM8350_IM_GP_INT                        0x0040
+#define WM8350_IM_AUXADC_INT                    0x0020
+#define WM8350_IM_RTC_INT                       0x0010
+#define WM8350_IM_SYS_INT                       0x0008
+#define WM8350_IM_CHG_INT                       0x0004
+#define WM8350_IM_USB_INT                       0x0002
+#define WM8350_IM_WKUP_INT                      0x0001
+
+/*
+ * R33 (0x21) - Interrupt Status 1 Mask
+ */
+#define WM8350_IM_CHG_BAT_HOT_EINT              0x8000
+#define WM8350_IM_CHG_BAT_COLD_EINT             0x4000
+#define WM8350_IM_CHG_BAT_FAIL_EINT             0x2000
+#define WM8350_IM_CHG_TO_EINT                   0x1000
+#define WM8350_IM_CHG_END_EINT                  0x0800
+#define WM8350_IM_CHG_START_EINT                0x0400
+#define WM8350_IM_CHG_FAST_RDY_EINT             0x0200
+#define WM8350_IM_RTC_PER_EINT                  0x0080
+#define WM8350_IM_RTC_SEC_EINT                  0x0040
+#define WM8350_IM_RTC_ALM_EINT                  0x0020
+#define WM8350_IM_CHG_VBATT_LT_3P9_EINT         0x0004
+#define WM8350_IM_CHG_VBATT_LT_3P1_EINT         0x0002
+#define WM8350_IM_CHG_VBATT_LT_2P85_EINT        0x0001
+
+/*
+ * R34 (0x22) - Interrupt Status 2 Mask
+ */
+#define WM8350_IM_SPARE2_EINT                   0x8000
+#define WM8350_IM_SPARE1_EINT                   0x4000
+#define WM8350_IM_CS1_EINT                      0x2000
+#define WM8350_IM_CS2_EINT                      0x1000
+#define WM8350_IM_USB_LIMIT_EINT                0x0400
+#define WM8350_IM_AUXADC_DATARDY_EINT           0x0100
+#define WM8350_IM_AUXADC_DCOMP4_EINT            0x0080
+#define WM8350_IM_AUXADC_DCOMP3_EINT            0x0040
+#define WM8350_IM_AUXADC_DCOMP2_EINT            0x0020
+#define WM8350_IM_AUXADC_DCOMP1_EINT            0x0010
+#define WM8350_IM_SYS_HYST_COMP_FAIL_EINT       0x0008
+#define WM8350_IM_SYS_CHIP_GT115_EINT           0x0004
+#define WM8350_IM_SYS_CHIP_GT140_EINT           0x0002
+#define WM8350_IM_SYS_WDOG_TO_EINT              0x0001
+
+/*
+ * R35 (0x23) - Power Up Interrupt Status Mask
+ */
+#define WM8350_IM_PUTO_LDO4_EINT                0x0800
+#define WM8350_IM_PUTO_LDO3_EINT                0x0400
+#define WM8350_IM_PUTO_LDO2_EINT                0x0200
+#define WM8350_IM_PUTO_LDO1_EINT                0x0100
+#define WM8350_IM_PUTO_DC6_EINT                 0x0020
+#define WM8350_IM_PUTO_DC5_EINT                 0x0010
+#define WM8350_IM_PUTO_DC4_EINT                 0x0008
+#define WM8350_IM_PUTO_DC3_EINT                 0x0004
+#define WM8350_IM_PUTO_DC2_EINT                 0x0002
+#define WM8350_IM_PUTO_DC1_EINT                 0x0001
+
+/*
+ * R36 (0x24) - Under Voltage Interrupt status Mask
+ */
+#define WM8350_IM_UV_LDO4_EINT                  0x0800
+#define WM8350_IM_UV_LDO3_EINT                  0x0400
+#define WM8350_IM_UV_LDO2_EINT                  0x0200
+#define WM8350_IM_UV_LDO1_EINT                  0x0100
+#define WM8350_IM_UV_DC6_EINT                   0x0020
+#define WM8350_IM_UV_DC5_EINT                   0x0010
+#define WM8350_IM_UV_DC4_EINT                   0x0008
+#define WM8350_IM_UV_DC3_EINT                   0x0004
+#define WM8350_IM_UV_DC2_EINT                   0x0002
+#define WM8350_IM_UV_DC1_EINT                   0x0001
+
+/*
+ * R37 (0x25) - Over Current Interrupt status Mask
+ */
+#define WM8350_IM_OC_LS_EINT                    0x8000
+
+/*
+ * R38 (0x26) - GPIO Interrupt Status Mask
+ */
+#define WM8350_IM_GP12_EINT                     0x1000
+#define WM8350_IM_GP11_EINT                     0x0800
+#define WM8350_IM_GP10_EINT                     0x0400
+#define WM8350_IM_GP9_EINT                      0x0200
+#define WM8350_IM_GP8_EINT                      0x0100
+#define WM8350_IM_GP7_EINT                      0x0080
+#define WM8350_IM_GP6_EINT                      0x0040
+#define WM8350_IM_GP5_EINT                      0x0020
+#define WM8350_IM_GP4_EINT                      0x0010
+#define WM8350_IM_GP3_EINT                      0x0008
+#define WM8350_IM_GP2_EINT                      0x0004
+#define WM8350_IM_GP1_EINT                      0x0002
+#define WM8350_IM_GP0_EINT                      0x0001
+
+/*
+ * R39 (0x27) - Comparator Interrupt Status Mask
+ */
+#define WM8350_IM_EXT_USB_FB_EINT               0x8000
+#define WM8350_IM_EXT_WALL_FB_EINT              0x4000
+#define WM8350_IM_EXT_BAT_FB_EINT               0x2000
+#define WM8350_IM_CODEC_JCK_DET_L_EINT          0x0800
+#define WM8350_IM_CODEC_JCK_DET_R_EINT          0x0400
+#define WM8350_IM_CODEC_MICSCD_EINT             0x0200
+#define WM8350_IM_CODEC_MICD_EINT               0x0100
+#define WM8350_IM_WKUP_OFF_STATE_EINT           0x0040
+#define WM8350_IM_WKUP_HIB_STATE_EINT           0x0020
+#define WM8350_IM_WKUP_CONV_FAULT_EINT          0x0010
+#define WM8350_IM_WKUP_WDOG_RST_EINT            0x0008
+#define WM8350_IM_WKUP_GP_PWR_ON_EINT           0x0004
+#define WM8350_IM_WKUP_ONKEY_EINT               0x0002
+#define WM8350_IM_WKUP_GP_WAKEUP_EINT           0x0001
+
+/*
+ * R220 (0xDC) - RAM BIST 1
+ */
+#define WM8350_READ_STATUS                      0x0800
+#define WM8350_TSTRAM_CLK                       0x0100
+#define WM8350_TSTRAM_CLK_ENA                   0x0080
+#define WM8350_STARTSEQ                         0x0040
+#define WM8350_READ_SRC                         0x0020
+#define WM8350_COUNT_DIR                        0x0010
+#define WM8350_TSTRAM_MODE_MASK                 0x000E
+#define WM8350_TSTRAM_ENA                       0x0001
+
+/*
+ * R225 (0xE1) - DCDC/LDO status
+ */
+#define WM8350_LS_STS                           0x8000
+#define WM8350_LDO4_STS                         0x0800
+#define WM8350_LDO3_STS                         0x0400
+#define WM8350_LDO2_STS                         0x0200
+#define WM8350_LDO1_STS                         0x0100
+#define WM8350_DC6_STS                          0x0020
+#define WM8350_DC5_STS                          0x0010
+#define WM8350_DC4_STS                          0x0008
+#define WM8350_DC3_STS                          0x0004
+#define WM8350_DC2_STS                          0x0002
+#define WM8350_DC1_STS                          0x0001
+
+/* WM8350 wake up conditions */
+#define WM8350_IRQ_WKUP_OFF_STATE               43
+#define WM8350_IRQ_WKUP_HIB_STATE               44
+#define WM8350_IRQ_WKUP_CONV_FAULT              45
+#define WM8350_IRQ_WKUP_WDOG_RST                46
+#define WM8350_IRQ_WKUP_GP_PWR_ON               47
+#define WM8350_IRQ_WKUP_ONKEY                   48
+#define WM8350_IRQ_WKUP_GP_WAKEUP               49
+
+/* wm8350 chip revisions */
+#define WM8350_REV_E                            0x4
+#define WM8350_REV_F                            0x5
+#define WM8350_REV_G                            0x6
+
+#define WM8350_NUM_IRQ                          63
+
+struct wm8350_reg_access {
+        u16 readable;           /* Mask of readable bits */
+        u16 writable;           /* Mask of writable bits */
+        u16 vol;                /* Mask of volatile bits */
+};
+extern const struct wm8350_reg_access wm8350_reg_io_map[];
+extern const u16 wm8350_mode0_defaults[];
+extern const u16 wm8350_mode1_defaults[];
+extern const u16 wm8350_mode2_defaults[];
+extern const u16 wm8350_mode3_defaults[];
+
+struct wm8350;
+
+struct wm8350_irq {
+        void (*handler) (struct wm8350 *, int, void *);
+        void *data;
+};
+
+struct wm8350 {
+        int rev;                /* chip revision */
+
+        struct device *dev;
+
+        /* device IO */
+        union {
+                struct i2c_client *i2c_client;
+                struct spi_device *spi_device;
+        };
+        int (*read_dev)(struct wm8350 *wm8350, char reg, int size, void *dest);
+        int (*write_dev)(struct wm8350 *wm8350, char reg, int size,
+                         void *src);
+        u16 *reg_cache;
+
+        /* Interrupt handling */
+        struct work_struct irq_work;
+        struct mutex irq_mutex; /* IRQ table mutex */
+        struct wm8350_irq irq[WM8350_NUM_IRQ];
+        int chip_irq;
+
+        /* Client devices */
+        struct wm8350_codec codec;
+        struct wm8350_gpio gpio;
+        struct wm8350_pmic pmic;
+        struct wm8350_power power;
+        struct wm8350_rtc rtc;
+        struct wm8350_wdt wdt;
+};
+
+/**
+ * Data to be supplied by the platform to initialise the WM8350.
+ *
+ * @init: Function called during driver initialisation.  Should be
+ *        used by the platform to configure GPIO functions and similar.
+ */
+struct wm8350_platform_data {
+        int (*init)(struct wm8350 *wm8350);
+};
+
+
+/*
+ * WM8350 device initialisation and exit.
+ */
+int wm8350_device_init(struct wm8350 *wm8350, int irq,
+                       struct wm8350_platform_data *pdata);
+void wm8350_device_exit(struct wm8350 *wm8350);
+
+/*
+ * WM8350 device IO
+ */
+int wm8350_clear_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
+int wm8350_set_bits(struct wm8350 *wm8350, u16 reg, u16 mask);
+u16 wm8350_reg_read(struct wm8350 *wm8350, int reg);
+int wm8350_reg_write(struct wm8350 *wm8350, int reg, u16 val);
+int wm8350_reg_lock(struct wm8350 *wm8350);
+int wm8350_reg_unlock(struct wm8350 *wm8350);
+int wm8350_block_read(struct wm8350 *wm8350, int reg, int size, u16 *dest);
+int wm8350_block_write(struct wm8350 *wm8350, int reg, int size, u16 *src);
+
+/*
+ * WM8350 internal interrupts
+ */
+int wm8350_register_irq(struct wm8350 *wm8350, int irq,
+                        void (*handler) (struct wm8350 *, int, void *),
+                        void *data);
+int wm8350_free_irq(struct wm8350 *wm8350, int irq);
+int wm8350_mask_irq(struct wm8350 *wm8350, int irq);
+int wm8350_unmask_irq(struct wm8350 *wm8350, int irq);
+
+
+#endif
diff --git a/include/linux/mfd/wm8350/gpio.h b/include/linux/mfd/wm8350/gpio.h
new file mode 100644
index 000000000000..ed91e8f5d298
--- /dev/null
+++ b/include/linux/mfd/wm8350/gpio.h
@@ -0,0 +1,342 @@
+/*
+ * gpio.h  --  GPIO Driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_WM8350_GPIO_H_
+#define __LINUX_MFD_WM8350_GPIO_H_
+
+#include <linux/platform_device.h>
+
+/*
+ * GPIO Registers.
+ */
+#define WM8350_GPIO_DEBOUNCE                    0x80
+#define WM8350_GPIO_PIN_PULL_UP_CONTROL         0x81
+#define WM8350_GPIO_PULL_DOWN_CONTROL           0x82
+#define WM8350_GPIO_INT_MODE                    0x83
+#define WM8350_GPIO_CONTROL                     0x85
+#define WM8350_GPIO_CONFIGURATION_I_O           0x86
+#define WM8350_GPIO_PIN_POLARITY_TYPE           0x87
+#define WM8350_GPIO_FUNCTION_SELECT_1           0x8C
+#define WM8350_GPIO_FUNCTION_SELECT_2           0x8D
+#define WM8350_GPIO_FUNCTION_SELECT_3           0x8E
+#define WM8350_GPIO_FUNCTION_SELECT_4           0x8F
+
+/*
+ * GPIO Functions
+ */
+#define WM8350_GPIO0_GPIO_IN                    0x0
+#define WM8350_GPIO0_GPIO_OUT                   0x0
+#define WM8350_GPIO0_PWR_ON_IN                  0x1
+#define WM8350_GPIO0_PWR_ON_OUT                 0x1
+#define WM8350_GPIO0_LDO_EN_IN                  0x2
+#define WM8350_GPIO0_VRTC_OUT                   0x2
+#define WM8350_GPIO0_LPWR1_IN                   0x3
+#define WM8350_GPIO0_POR_B_OUT                  0x3
+
+#define WM8350_GPIO1_GPIO_IN                    0x0
+#define WM8350_GPIO1_GPIO_OUT                   0x0
+#define WM8350_GPIO1_PWR_ON_IN                  0x1
+#define WM8350_GPIO1_DO_CONF_OUT                0x1
+#define WM8350_GPIO1_LDO_EN_IN                  0x2
+#define WM8350_GPIO1_RESET_OUT                  0x2
+#define WM8350_GPIO1_LPWR2_IN                   0x3
+#define WM8350_GPIO1_MEMRST_OUT                 0x3
+
+#define WM8350_GPIO2_GPIO_IN                    0x0
+#define WM8350_GPIO2_GPIO_OUT                   0x0
+#define WM8350_GPIO2_PWR_ON_IN                  0x1
+#define WM8350_GPIO2_PWR_ON_OUT                 0x1
+#define WM8350_GPIO2_WAKE_UP_IN                 0x2
+#define WM8350_GPIO2_VRTC_OUT                   0x2
+#define WM8350_GPIO2_32KHZ_IN                   0x3
+#define WM8350_GPIO2_32KHZ_OUT                  0x3
+
+#define WM8350_GPIO3_GPIO_IN                    0x0
+#define WM8350_GPIO3_GPIO_OUT                   0x0
+#define WM8350_GPIO3_PWR_ON_IN                  0x1
+#define WM8350_GPIO3_P_CLK_OUT                  0x1
+#define WM8350_GPIO3_LDO_EN_IN                  0x2
+#define WM8350_GPIO3_VRTC_OUT                   0x2
+#define WM8350_GPIO3_PWR_OFF_IN                 0x3
+#define WM8350_GPIO3_32KHZ_OUT                  0x3
+
+#define WM8350_GPIO4_GPIO_IN                    0x0
+#define WM8350_GPIO4_GPIO_OUT                   0x0
+#define WM8350_GPIO4_MR_IN                      0x1
+#define WM8350_GPIO4_MEM_RST_OUT                0x1
+#define WM8350_GPIO4_FLASH_IN                   0x2
+#define WM8350_GPIO4_ADA_OUT                    0x2
+#define WM8350_GPIO4_HIBERNATE_IN               0x3
+#define WM8350_GPIO4_FLASH_OUT                  0x3
+#define WM8350_GPIO4_MICDET_OUT                 0x4
+#define WM8350_GPIO4_MICSHT_OUT                 0x5
+
+#define WM8350_GPIO5_GPIO_IN                    0x0
+#define WM8350_GPIO5_GPIO_OUT                   0x0
+#define WM8350_GPIO5_LPWR1_IN                   0x1
+#define WM8350_GPIO5_P_CLK_OUT                  0x1
+#define WM8350_GPIO5_ADCLRCLK_IN                0x2
+#define WM8350_GPIO5_ADCLRCLK_OUT               0x2
+#define WM8350_GPIO5_HIBERNATE_IN               0x3
+#define WM8350_GPIO5_32KHZ_OUT                  0x3
+#define WM8350_GPIO5_MICDET_OUT                 0x4
+#define WM8350_GPIO5_MICSHT_OUT                 0x5
+#define WM8350_GPIO5_ADA_OUT                    0x6
+#define WM8350_GPIO5_OPCLK_OUT                  0x7
+
+#define WM8350_GPIO6_GPIO_IN                    0x0
+#define WM8350_GPIO6_GPIO_OUT                   0x0
+#define WM8350_GPIO6_LPWR2_IN                   0x1
+#define WM8350_GPIO6_MEMRST_OUT                 0x1
+#define WM8350_GPIO6_FLASH_IN                   0x2
+#define WM8350_GPIO6_ADA_OUT                    0x2
+#define WM8350_GPIO6_HIBERNATE_IN               0x3
+#define WM8350_GPIO6_RTC_OUT                    0x3
+#define WM8350_GPIO6_MICDET_OUT                 0x4
+#define WM8350_GPIO6_MICSHT_OUT                 0x5
+#define WM8350_GPIO6_ADCLRCLKB_OUT              0x6
+#define WM8350_GPIO6_SDOUT_OUT                  0x7
+
+#define WM8350_GPIO7_GPIO_IN                    0x0
+#define WM8350_GPIO7_GPIO_OUT                   0x0
+#define WM8350_GPIO7_LPWR3_IN                   0x1
+#define WM8350_GPIO7_P_CLK_OUT                  0x1
+#define WM8350_GPIO7_MASK_IN                    0x2
+#define WM8350_GPIO7_VCC_FAULT_OUT              0x2
+#define WM8350_GPIO7_HIBERNATE_IN               0x3
+#define WM8350_GPIO7_BATT_FAULT_OUT             0x3
+#define WM8350_GPIO7_MICDET_OUT                 0x4
+#define WM8350_GPIO7_MICSHT_OUT                 0x5
+#define WM8350_GPIO7_ADA_OUT                    0x6
+#define WM8350_GPIO7_CSB_IN                     0x7
+
+#define WM8350_GPIO8_GPIO_IN                    0x0
+#define WM8350_GPIO8_GPIO_OUT                   0x0
+#define WM8350_GPIO8_MR_IN                      0x1
+#define WM8350_GPIO8_VCC_FAULT_OUT              0x1
+#define WM8350_GPIO8_ADCBCLK_IN                 0x2
+#define WM8350_GPIO8_ADCBCLK_OUT                0x2
+#define WM8350_GPIO8_PWR_OFF_IN                 0x3
+#define WM8350_GPIO8_BATT_FAULT_OUT             0x3
+#define WM8350_GPIO8_ALTSCL_IN                  0xf
+
+#define WM8350_GPIO9_GPIO_IN                    0x0
+#define WM8350_GPIO9_GPIO_OUT                   0x0
+#define WM8350_GPIO9_HEARTBEAT_IN               0x1
+#define WM8350_GPIO9_VCC_FAULT_OUT              0x1
+#define WM8350_GPIO9_MASK_IN                    0x2
+#define WM8350_GPIO9_LINE_GT_BATT_OUT           0x2
+#define WM8350_GPIO9_PWR_OFF_IN                 0x3
+#define WM8350_GPIO9_BATT_FAULT_OUT             0x3
+#define WM8350_GPIO9_ALTSDA_OUT                 0xf
+
+#define WM8350_GPIO10_GPIO_IN                   0x0
+#define WM8350_GPIO10_GPIO_OUT                  0x0
+#define WM8350_GPIO10_ISINKC_OUT                0x1
+#define WM8350_GPIO10_PWR_OFF_IN                0x2
+#define WM8350_GPIO10_LINE_GT_BATT_OUT          0x2
+#define WM8350_GPIO10_CHD_IND_IN                0x3
+
+#define WM8350_GPIO11_GPIO_IN                   0x0
+#define WM8350_GPIO11_GPIO_OUT                  0x0
+#define WM8350_GPIO11_ISINKD_OUT                0x1
+#define WM8350_GPIO11_WAKEUP_IN                 0x2
+#define WM8350_GPIO11_LINE_GT_BATT_OUT          0x2
+#define WM8350_GPIO11_CHD_IND_IN                0x3
+
+#define WM8350_GPIO12_GPIO_IN                   0x0
+#define WM8350_GPIO12_GPIO_OUT                  0x0
+#define WM8350_GPIO12_ISINKE_OUT                0x1
+#define WM8350_GPIO12_LINE_GT_BATT_OUT          0x2
+#define WM8350_GPIO12_LINE_EN_OUT               0x3
+#define WM8350_GPIO12_32KHZ_OUT                 0x4
+
+#define WM8350_GPIO_DIR_IN                      0
+#define WM8350_GPIO_DIR_OUT                     1
+#define WM8350_GPIO_ACTIVE_LOW                  0
+#define WM8350_GPIO_ACTIVE_HIGH                 1
+#define WM8350_GPIO_PULL_NONE                   0
+#define WM8350_GPIO_PULL_UP                     1
+#define WM8350_GPIO_PULL_DOWN                   2
+#define WM8350_GPIO_INVERT_OFF                  0
+#define WM8350_GPIO_INVERT_ON                   1
+#define WM8350_GPIO_DEBOUNCE_OFF                0
+#define WM8350_GPIO_DEBOUNCE_ON                 1
+
+/*
+ * R128 (0x80) - GPIO Debounce
+ */
+#define WM8350_GP12_DB                          0x1000
+#define WM8350_GP11_DB                          0x0800
+#define WM8350_GP10_DB                          0x0400
+#define WM8350_GP9_DB                           0x0200
+#define WM8350_GP8_DB                           0x0100
+#define WM8350_GP7_DB                           0x0080
+#define WM8350_GP6_DB                           0x0040
+#define WM8350_GP5_DB                           0x0020
+#define WM8350_GP4_DB                           0x0010
+#define WM8350_GP3_DB                           0x0008
+#define WM8350_GP2_DB                           0x0004
+#define WM8350_GP1_DB                           0x0002
+#define WM8350_GP0_DB                           0x0001
+
+/*
+ * R129 (0x81) - GPIO Pin pull up Control
+ */
+#define WM8350_GP12_PU                          0x1000
+#define WM8350_GP11_PU                          0x0800
+#define WM8350_GP10_PU                          0x0400
+#define WM8350_GP9_PU                           0x0200
+#define WM8350_GP8_PU                           0x0100
+#define WM8350_GP7_PU                           0x0080
+#define WM8350_GP6_PU                           0x0040
+#define WM8350_GP5_PU                           0x0020
+#define WM8350_GP4_PU                           0x0010
+#define WM8350_GP3_PU                           0x0008
+#define WM8350_GP2_PU                           0x0004
+#define WM8350_GP1_PU                           0x0002
+#define WM8350_GP0_PU                           0x0001
+
+/*
+ * R130 (0x82) - GPIO Pull down Control
+ */
+#define WM8350_GP12_PD                          0x1000
+#define WM8350_GP11_PD                          0x0800
+#define WM8350_GP10_PD                          0x0400
+#define WM8350_GP9_PD                           0x0200
+#define WM8350_GP8_PD                           0x0100
+#define WM8350_GP7_PD                           0x0080
+#define WM8350_GP6_PD                           0x0040
+#define WM8350_GP5_PD                           0x0020
+#define WM8350_GP4_PD                           0x0010
+#define WM8350_GP3_PD                           0x0008
+#define WM8350_GP2_PD                           0x0004
+#define WM8350_GP1_PD                           0x0002
+#define WM8350_GP0_PD                           0x0001
+
+/*
+ * R131 (0x83) - GPIO Interrupt Mode
+ */
+#define WM8350_GP12_INTMODE                     0x1000
+#define WM8350_GP11_INTMODE                     0x0800
+#define WM8350_GP10_INTMODE                     0x0400
+#define WM8350_GP9_INTMODE                      0x0200
+#define WM8350_GP8_INTMODE                      0x0100
+#define WM8350_GP7_INTMODE                      0x0080
+#define WM8350_GP6_INTMODE                      0x0040
+#define WM8350_GP5_INTMODE                      0x0020
+#define WM8350_GP4_INTMODE                      0x0010
+#define WM8350_GP3_INTMODE                      0x0008
+#define WM8350_GP2_INTMODE                      0x0004
+#define WM8350_GP1_INTMODE                      0x0002
+#define WM8350_GP0_INTMODE                      0x0001
+
+/*
+ * R133 (0x85) - GPIO Control
+ */
+#define WM8350_GP_DBTIME_MASK                   0x00C0
+
+/*
+ * R134 (0x86) - GPIO Configuration (i/o)
+ */
+#define WM8350_GP12_DIR                         0x1000
+#define WM8350_GP11_DIR                         0x0800
+#define WM8350_GP10_DIR                         0x0400
+#define WM8350_GP9_DIR                          0x0200
+#define WM8350_GP8_DIR                          0x0100
+#define WM8350_GP7_DIR                          0x0080
+#define WM8350_GP6_DIR                          0x0040
+#define WM8350_GP5_DIR                          0x0020
+#define WM8350_GP4_DIR                          0x0010
+#define WM8350_GP3_DIR                          0x0008
+#define WM8350_GP2_DIR                          0x0004
+#define WM8350_GP1_DIR                          0x0002
+#define WM8350_GP0_DIR                          0x0001
+
+/*
+ * R135 (0x87) - GPIO Pin Polarity / Type
+ */
+#define WM8350_GP12_CFG                         0x1000
+#define WM8350_GP11_CFG                         0x0800
+#define WM8350_GP10_CFG                         0x0400
+#define WM8350_GP9_CFG                          0x0200
+#define WM8350_GP8_CFG                          0x0100
+#define WM8350_GP7_CFG                          0x0080
+#define WM8350_GP6_CFG                          0x0040
+#define WM8350_GP5_CFG                          0x0020
+#define WM8350_GP4_CFG                          0x0010
+#define WM8350_GP3_CFG                          0x0008
+#define WM8350_GP2_CFG                          0x0004
+#define WM8350_GP1_CFG                          0x0002
+#define WM8350_GP0_CFG                          0x0001
+
+/*
+ * R140 (0x8C) - GPIO Function Select 1
+ */
+#define WM8350_GP3_FN_MASK                      0xF000
+#define WM8350_GP2_FN_MASK                      0x0F00
+#define WM8350_GP1_FN_MASK                      0x00F0
+#define WM8350_GP0_FN_MASK                      0x000F
+
+/*
+ * R141 (0x8D) - GPIO Function Select 2
+ */
+#define WM8350_GP7_FN_MASK                      0xF000
+#define WM8350_GP6_FN_MASK                      0x0F00
+#define WM8350_GP5_FN_MASK                      0x00F0
+#define WM8350_GP4_FN_MASK                      0x000F
+
+/*
+ * R142 (0x8E) - GPIO Function Select 3
+ */
+#define WM8350_GP11_FN_MASK                     0xF000
+#define WM8350_GP10_FN_MASK                     0x0F00
+#define WM8350_GP9_FN_MASK                      0x00F0
+#define WM8350_GP8_FN_MASK                      0x000F
+
+/*
+ * R143 (0x8F) - GPIO Function Select 4
+ */
+#define WM8350_GP12_FN_MASK                     0x000F
+
+/*
+ * R230 (0xE6) - GPIO Pin Status
+ */
+#define WM8350_GP12_LVL                         0x1000
+#define WM8350_GP11_LVL                         0x0800
+#define WM8350_GP10_LVL                         0x0400
+#define WM8350_GP9_LVL                          0x0200
+#define WM8350_GP8_LVL                          0x0100
+#define WM8350_GP7_LVL                          0x0080
+#define WM8350_GP6_LVL                          0x0040
+#define WM8350_GP5_LVL                          0x0020
+#define WM8350_GP4_LVL                          0x0010
+#define WM8350_GP3_LVL                          0x0008
+#define WM8350_GP2_LVL                          0x0004
+#define WM8350_GP1_LVL                          0x0002
+#define WM8350_GP0_LVL                          0x0001
+
+struct wm8350;
+
+int wm8350_gpio_config(struct wm8350 *wm8350, int gpio, int dir, int func,
+                       int pol, int pull, int invert, int debounce);
+
+struct wm8350_gpio {
+        struct platform_device *pdev;
+};
+
+/*
+ * GPIO Interrupts
+ */
+#define WM8350_IRQ_GPIO(x)                      (50 + x)
+
+#endif
diff --git a/include/linux/mfd/wm8350/pmic.h b/include/linux/mfd/wm8350/pmic.h
new file mode 100644
index 000000000000..69b69e07f62f
--- /dev/null
+++ b/include/linux/mfd/wm8350/pmic.h
@@ -0,0 +1,741 @@
+/*
+ * pmic.h  --  Power Managment Driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_WM8350_PMIC_H
+#define __LINUX_MFD_WM8350_PMIC_H
+
+/*
+ * Register values.
+ */
+
+#define WM8350_CURRENT_SINK_DRIVER_A            0xAC
+#define WM8350_CSA_FLASH_CONTROL                0xAD
+#define WM8350_CURRENT_SINK_DRIVER_B            0xAE
+#define WM8350_CSB_FLASH_CONTROL                0xAF
+#define WM8350_DCDC_LDO_REQUESTED               0xB0
+#define WM8350_DCDC_ACTIVE_OPTIONS              0xB1
+#define WM8350_DCDC_SLEEP_OPTIONS               0xB2
+#define WM8350_POWER_CHECK_COMPARATOR           0xB3
+#define WM8350_DCDC1_CONTROL                    0xB4
+#define WM8350_DCDC1_TIMEOUTS                   0xB5
+#define WM8350_DCDC1_LOW_POWER                  0xB6
+#define WM8350_DCDC2_CONTROL                    0xB7
+#define WM8350_DCDC2_TIMEOUTS                   0xB8
+#define WM8350_DCDC3_CONTROL                    0xBA
+#define WM8350_DCDC3_TIMEOUTS                   0xBB
+#define WM8350_DCDC3_LOW_POWER                  0xBC
+#define WM8350_DCDC4_CONTROL                    0xBD
+#define WM8350_DCDC4_TIMEOUTS                   0xBE
+#define WM8350_DCDC4_LOW_POWER                  0xBF
+#define WM8350_DCDC5_CONTROL                    0xC0
+#define WM8350_DCDC5_TIMEOUTS                   0xC1
+#define WM8350_DCDC6_CONTROL                    0xC3
+#define WM8350_DCDC6_TIMEOUTS                   0xC4
+#define WM8350_DCDC6_LOW_POWER                  0xC5
+#define WM8350_LIMIT_SWITCH_CONTROL             0xC7
+#define WM8350_LDO1_CONTROL                     0xC8
+#define WM8350_LDO1_TIMEOUTS                    0xC9
+#define WM8350_LDO1_LOW_POWER                   0xCA
+#define WM8350_LDO2_CONTROL                     0xCB
+#define WM8350_LDO2_TIMEOUTS                    0xCC
+#define WM8350_LDO2_LOW_POWER                   0xCD
+#define WM8350_LDO3_CONTROL                     0xCE
+#define WM8350_LDO3_TIMEOUTS                    0xCF
+#define WM8350_LDO3_LOW_POWER                   0xD0
+#define WM8350_LDO4_CONTROL                     0xD1
+#define WM8350_LDO4_TIMEOUTS                    0xD2
+#define WM8350_LDO4_LOW_POWER                   0xD3
+#define WM8350_VCC_FAULT_MASKS                  0xD7
+#define WM8350_MAIN_BANDGAP_CONTROL             0xD8
+#define WM8350_OSC_CONTROL                      0xD9
+#define WM8350_RTC_TICK_CONTROL                 0xDA
+#define WM8350_SECURITY                         0xDB
+#define WM8350_RAM_BIST_1                       0xDC
+#define WM8350_DCDC_LDO_STATUS                  0xE1
+#define WM8350_GPIO_PIN_STATUS                  0xE6
+
+#define WM8350_DCDC1_FORCE_PWM                  0xF8
+#define WM8350_DCDC3_FORCE_PWM                  0xFA
+#define WM8350_DCDC4_FORCE_PWM                  0xFB
+#define WM8350_DCDC6_FORCE_PWM                  0xFD
+
+/*
+ * R172 (0xAC) - Current Sink Driver A
+ */
+#define WM8350_CS1_HIB_MODE                     0x1000
+#define WM8350_CS1_HIB_MODE_MASK                0x1000
+#define WM8350_CS1_HIB_MODE_SHIFT                   12
+#define WM8350_CS1_ISEL_MASK                    0x003F
+#define WM8350_CS1_ISEL_SHIFT                        0
+
+/* Bit values for R172 (0xAC) */
+#define WM8350_CS1_HIB_MODE_DISABLE                  0
+#define WM8350_CS1_HIB_MODE_LEAVE                    1
+
+#define WM8350_CS1_ISEL_220M                      0x3F
+
+/*
+ * R173 (0xAD) - CSA Flash control
+ */
+#define WM8350_CS1_FLASH_MODE                   0x8000
+#define WM8350_CS1_TRIGSRC                      0x4000
+#define WM8350_CS1_DRIVE                        0x2000
+#define WM8350_CS1_FLASH_DUR_MASK               0x0300
+#define WM8350_CS1_OFF_RAMP_MASK                0x0030
+#define WM8350_CS1_ON_RAMP_MASK                 0x0003
+
+/*
+ * R174 (0xAE) - Current Sink Driver B
+ */
+#define WM8350_CS2_HIB_MODE                     0x1000
+#define WM8350_CS2_ISEL_MASK                    0x003F
+
+/*
+ * R175 (0xAF) - CSB Flash control
+ */
+#define WM8350_CS2_FLASH_MODE                   0x8000
+#define WM8350_CS2_TRIGSRC                      0x4000
+#define WM8350_CS2_DRIVE                        0x2000
+#define WM8350_CS2_FLASH_DUR_MASK               0x0300
+#define WM8350_CS2_OFF_RAMP_MASK                0x0030
+#define WM8350_CS2_ON_RAMP_MASK                 0x0003
+
+/*
+ * R176 (0xB0) - DCDC/LDO requested
+ */
+#define WM8350_LS_ENA                           0x8000
+#define WM8350_LDO4_ENA                         0x0800
+#define WM8350_LDO3_ENA                         0x0400
+#define WM8350_LDO2_ENA                         0x0200
+#define WM8350_LDO1_ENA                         0x0100
+#define WM8350_DC6_ENA                          0x0020
+#define WM8350_DC5_ENA                          0x0010
+#define WM8350_DC4_ENA                          0x0008
+#define WM8350_DC3_ENA                          0x0004
+#define WM8350_DC2_ENA                          0x0002
+#define WM8350_DC1_ENA                          0x0001
+
+/*
+ * R177 (0xB1) - DCDC Active options
+ */
+#define WM8350_PUTO_MASK                        0x3000
+#define WM8350_PWRUP_DELAY_MASK                 0x0300
+#define WM8350_DC6_ACTIVE                       0x0020
+#define WM8350_DC4_ACTIVE                       0x0008
+#define WM8350_DC3_ACTIVE                       0x0004
+#define WM8350_DC1_ACTIVE                       0x0001
+
+/*
+ * R178 (0xB2) - DCDC Sleep options
+ */
+#define WM8350_DC6_SLEEP                        0x0020
+#define WM8350_DC4_SLEEP                        0x0008
+#define WM8350_DC3_SLEEP                        0x0004
+#define WM8350_DC1_SLEEP                        0x0001
+
+/*
+ * R179 (0xB3) - Power-check comparator
+ */
+#define WM8350_PCCMP_ERRACT                     0x4000
+#define WM8350_PCCMP_RAIL                       0x0100
+#define WM8350_PCCMP_OFF_THR_MASK               0x0070
+#define WM8350_PCCMP_ON_THR_MASK                0x0007
+
+/*
+ * R180 (0xB4) - DCDC1 Control
+ */
+#define WM8350_DC1_OPFLT                        0x0400
+#define WM8350_DC1_VSEL_MASK                    0x007F
+#define WM8350_DC1_VSEL_SHIFT                        0
+
+/*
+ * R181 (0xB5) - DCDC1 Timeouts
+ */
+#define WM8350_DC1_ERRACT_MASK                  0xC000
+#define WM8350_DC1_ERRACT_SHIFT                     14
+#define WM8350_DC1_ENSLOT_MASK                  0x3C00
+#define WM8350_DC1_ENSLOT_SHIFT                     10
+#define WM8350_DC1_SDSLOT_MASK                  0x03C0
+#define WM8350_DC1_UVTO_MASK                    0x0030
+#define WM8350_DC1_SDSLOT_SHIFT                      6
+
+/* Bit values for R181 (0xB5) */
+#define WM8350_DC1_ERRACT_NONE                       0
+#define WM8350_DC1_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_DC1_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R182 (0xB6) - DCDC1 Low Power
+ */
+#define WM8350_DC1_HIB_MODE_MASK                0x7000
+#define WM8350_DC1_HIB_TRIG_MASK                0x0300
+#define WM8350_DC1_VIMG_MASK                    0x007F
+
+/*
+ * R183 (0xB7) - DCDC2 Control
+ */
+#define WM8350_DC2_MODE                         0x4000
+#define WM8350_DC2_MODE_MASK                    0x4000
+#define WM8350_DC2_MODE_SHIFT                       14
+#define WM8350_DC2_HIB_MODE                     0x1000
+#define WM8350_DC2_HIB_MODE_MASK                0x1000
+#define WM8350_DC2_HIB_MODE_SHIFT                   12
+#define WM8350_DC2_HIB_TRIG_MASK                0x0300
+#define WM8350_DC2_HIB_TRIG_SHIFT                    8
+#define WM8350_DC2_ILIM                         0x0040
+#define WM8350_DC2_ILIM_MASK                    0x0040
+#define WM8350_DC2_ILIM_SHIFT                        6
+#define WM8350_DC2_RMP_MASK                     0x0018
+#define WM8350_DC2_RMP_SHIFT                         3
+#define WM8350_DC2_FBSRC_MASK                   0x0003
+#define WM8350_DC2_FBSRC_SHIFT                       0
+
+/* Bit values for R183 (0xB7) */
+#define WM8350_DC2_MODE_BOOST                        0
+#define WM8350_DC2_MODE_SWITCH                       1
+
+#define WM8350_DC2_HIB_MODE_ACTIVE                   1
+#define WM8350_DC2_HIB_MODE_DISABLE                  0
+
+#define WM8350_DC2_HIB_TRIG_NONE                     0
+#define WM8350_DC2_HIB_TRIG_LPWR1                    1
+#define WM8350_DC2_HIB_TRIG_LPWR2                    2
+#define WM8350_DC2_HIB_TRIG_LPWR3                    3
+
+#define WM8350_DC2_ILIM_HIGH                         0
+#define WM8350_DC2_ILIM_LOW                          1
+
+#define WM8350_DC2_RMP_30V                           0
+#define WM8350_DC2_RMP_20V                           1
+#define WM8350_DC2_RMP_10V                           2
+#define WM8350_DC2_RMP_5V                            3
+
+#define WM8350_DC2_FBSRC_FB2                         0
+#define WM8350_DC2_FBSRC_ISINKA                      1
+#define WM8350_DC2_FBSRC_ISINKB                      2
+#define WM8350_DC2_FBSRC_USB                         3
+
+/*
+ * R184 (0xB8) - DCDC2 Timeouts
+ */
+#define WM8350_DC2_ERRACT_MASK                  0xC000
+#define WM8350_DC2_ERRACT_SHIFT                     14
+#define WM8350_DC2_ENSLOT_MASK                  0x3C00
+#define WM8350_DC2_ENSLOT_SHIFT                     10
+#define WM8350_DC2_SDSLOT_MASK                  0x03C0
+#define WM8350_DC2_UVTO_MASK                    0x0030
+
+/* Bit values for R184 (0xB8) */
+#define WM8350_DC2_ERRACT_NONE                       0
+#define WM8350_DC2_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_DC2_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R186 (0xBA) - DCDC3 Control
+ */
+#define WM8350_DC3_OPFLT                        0x0400
+#define WM8350_DC3_VSEL_MASK                    0x007F
+#define WM8350_DC3_VSEL_SHIFT                        0
+
+/*
+ * R187 (0xBB) - DCDC3 Timeouts
+ */
+#define WM8350_DC3_ERRACT_MASK                  0xC000
+#define WM8350_DC3_ERRACT_SHIFT                     14
+#define WM8350_DC3_ENSLOT_MASK                  0x3C00
+#define WM8350_DC3_ENSLOT_SHIFT                     10
+#define WM8350_DC3_SDSLOT_MASK                  0x03C0
+#define WM8350_DC3_UVTO_MASK                    0x0030
+#define WM8350_DC3_SDSLOT_SHIFT                      6
+
+/* Bit values for R187 (0xBB) */
+#define WM8350_DC3_ERRACT_NONE                       0
+#define WM8350_DC3_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_DC3_ERRACT_SHUTDOWN_SYS               2
+/*
+ * R188 (0xBC) - DCDC3 Low Power
+ */
+#define WM8350_DC3_HIB_MODE_MASK                0x7000
+#define WM8350_DC3_HIB_TRIG_MASK                0x0300
+#define WM8350_DC3_VIMG_MASK                    0x007F
+
+/*
+ * R189 (0xBD) - DCDC4 Control
+ */
+#define WM8350_DC4_OPFLT                        0x0400
+#define WM8350_DC4_VSEL_MASK                    0x007F
+#define WM8350_DC4_VSEL_SHIFT                        0
+
+/*
+ * R190 (0xBE) - DCDC4 Timeouts
+ */
+#define WM8350_DC4_ERRACT_MASK                  0xC000
+#define WM8350_DC4_ERRACT_SHIFT                     14
+#define WM8350_DC4_ENSLOT_MASK                  0x3C00
+#define WM8350_DC4_ENSLOT_SHIFT                     10
+#define WM8350_DC4_SDSLOT_MASK                  0x03C0
+#define WM8350_DC4_UVTO_MASK                    0x0030
+#define WM8350_DC4_SDSLOT_SHIFT                      6
+
+/* Bit values for R190 (0xBE) */
+#define WM8350_DC4_ERRACT_NONE                       0
+#define WM8350_DC4_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_DC4_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R191 (0xBF) - DCDC4 Low Power
+ */
+#define WM8350_DC4_HIB_MODE_MASK                0x7000
+#define WM8350_DC4_HIB_TRIG_MASK                0x0300
+#define WM8350_DC4_VIMG_MASK                    0x007F
+
+/*
+ * R192 (0xC0) - DCDC5 Control
+ */
+#define WM8350_DC5_MODE                         0x4000
+#define WM8350_DC5_MODE_MASK                    0x4000
+#define WM8350_DC5_MODE_SHIFT                       14
+#define WM8350_DC5_HIB_MODE                     0x1000
+#define WM8350_DC5_HIB_MODE_MASK                0x1000
+#define WM8350_DC5_HIB_MODE_SHIFT                   12
+#define WM8350_DC5_HIB_TRIG_MASK                0x0300
+#define WM8350_DC5_HIB_TRIG_SHIFT                    8
+#define WM8350_DC5_ILIM                         0x0040
+#define WM8350_DC5_ILIM_MASK                    0x0040
+#define WM8350_DC5_ILIM_SHIFT                        6
+#define WM8350_DC5_RMP_MASK                     0x0018
+#define WM8350_DC5_RMP_SHIFT                         3
+#define WM8350_DC5_FBSRC_MASK                   0x0003
+#define WM8350_DC5_FBSRC_SHIFT                       0
+
+/* Bit values for R192 (0xC0) */
+#define WM8350_DC5_MODE_BOOST                        0
+#define WM8350_DC5_MODE_SWITCH                       1
+
+#define WM8350_DC5_HIB_MODE_ACTIVE                   1
+#define WM8350_DC5_HIB_MODE_DISABLE                  0
+
+#define WM8350_DC5_HIB_TRIG_NONE                     0
+#define WM8350_DC5_HIB_TRIG_LPWR1                    1
+#define WM8350_DC5_HIB_TRIG_LPWR2                    2
+#define WM8350_DC5_HIB_TRIG_LPWR3                    3
+
+#define WM8350_DC5_ILIM_HIGH                         0
+#define WM8350_DC5_ILIM_LOW                          1
+
+#define WM8350_DC5_RMP_30V                           0
+#define WM8350_DC5_RMP_20V                           1
+#define WM8350_DC5_RMP_10V                           2
+#define WM8350_DC5_RMP_5V                            3
+
+#define WM8350_DC5_FBSRC_FB2                         0
+#define WM8350_DC5_FBSRC_ISINKA                      1
+#define WM8350_DC5_FBSRC_ISINKB                      2
+#define WM8350_DC5_FBSRC_USB                         3
+
+/*
+ * R193 (0xC1) - DCDC5 Timeouts
+ */
+#define WM8350_DC5_ERRACT_MASK                  0xC000
+#define WM8350_DC5_ERRACT_SHIFT                     14
+#define WM8350_DC5_ENSLOT_MASK                  0x3C00
+#define WM8350_DC5_ENSLOT_SHIFT                     10
+#define WM8350_DC5_SDSLOT_MASK                  0x03C0
+#define WM8350_DC5_UVTO_MASK                    0x0030
+#define WM8350_DC5_SDSLOT_SHIFT                      6
+
+/* Bit values for R193 (0xC1) */
+#define WM8350_DC5_ERRACT_NONE                       0
+#define WM8350_DC5_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_DC5_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R195 (0xC3) - DCDC6 Control
+ */
+#define WM8350_DC6_OPFLT                        0x0400
+#define WM8350_DC6_VSEL_MASK                    0x007F
+#define WM8350_DC6_VSEL_SHIFT                        0
+
+/*
+ * R196 (0xC4) - DCDC6 Timeouts
+ */
+#define WM8350_DC6_ERRACT_MASK                  0xC000
+#define WM8350_DC6_ERRACT_SHIFT                     14
+#define WM8350_DC6_ENSLOT_MASK                  0x3C00
+#define WM8350_DC6_ENSLOT_SHIFT                     10
+#define WM8350_DC6_SDSLOT_MASK                  0x03C0
+#define WM8350_DC6_UVTO_MASK                    0x0030
+#define WM8350_DC6_SDSLOT_SHIFT                      6
+
+/* Bit values for R196 (0xC4) */
+#define WM8350_DC6_ERRACT_NONE                       0
+#define WM8350_DC6_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_DC6_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R197 (0xC5) - DCDC6 Low Power
+ */
+#define WM8350_DC6_HIB_MODE_MASK                0x7000
+#define WM8350_DC6_HIB_TRIG_MASK                0x0300
+#define WM8350_DC6_VIMG_MASK                    0x007F
+
+/*
+ * R199 (0xC7) - Limit Switch Control
+ */
+#define WM8350_LS_ERRACT_MASK                   0xC000
+#define WM8350_LS_ERRACT_SHIFT                      14
+#define WM8350_LS_ENSLOT_MASK                   0x3C00
+#define WM8350_LS_ENSLOT_SHIFT                      10
+#define WM8350_LS_SDSLOT_MASK                   0x03C0
+#define WM8350_LS_SDSLOT_SHIFT                       6
+#define WM8350_LS_HIB_MODE                      0x0010
+#define WM8350_LS_HIB_MODE_MASK                 0x0010
+#define WM8350_LS_HIB_MODE_SHIFT                     4
+#define WM8350_LS_HIB_PROT                      0x0002
+#define WM8350_LS_HIB_PROT_MASK                 0x0002
+#define WM8350_LS_HIB_PROT_SHIFT                     1
+#define WM8350_LS_PROT                          0x0001
+#define WM8350_LS_PROT_MASK                     0x0001
+#define WM8350_LS_PROT_SHIFT                         0
+
+/* Bit values for R199 (0xC7) */
+#define WM8350_LS_ERRACT_NONE                       0
+#define WM8350_LS_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_LS_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R200 (0xC8) - LDO1 Control
+ */
+#define WM8350_LDO1_SWI                         0x4000
+#define WM8350_LDO1_OPFLT                       0x0400
+#define WM8350_LDO1_VSEL_MASK                   0x001F
+#define WM8350_LDO1_VSEL_SHIFT                       0
+
+/*
+ * R201 (0xC9) - LDO1 Timeouts
+ */
+#define WM8350_LDO1_ERRACT_MASK                 0xC000
+#define WM8350_LDO1_ERRACT_SHIFT                    14
+#define WM8350_LDO1_ENSLOT_MASK                 0x3C00
+#define WM8350_LDO1_ENSLOT_SHIFT                    10
+#define WM8350_LDO1_SDSLOT_MASK                 0x03C0
+#define WM8350_LDO1_UVTO_MASK                   0x0030
+#define WM8350_LDO1_SDSLOT_SHIFT                     6
+
+/* Bit values for R201 (0xC9) */
+#define WM8350_LDO1_ERRACT_NONE                       0
+#define WM8350_LDO1_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_LDO1_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R202 (0xCA) - LDO1 Low Power
+ */
+#define WM8350_LDO1_HIB_MODE_MASK               0x3000
+#define WM8350_LDO1_HIB_TRIG_MASK               0x0300
+#define WM8350_LDO1_VIMG_MASK                   0x001F
+#define WM8350_LDO1_HIB_MODE_DIS                (0x1 << 12)
+
+
+/*
+ * R203 (0xCB) - LDO2 Control
+ */
+#define WM8350_LDO2_SWI                         0x4000
+#define WM8350_LDO2_OPFLT                       0x0400
+#define WM8350_LDO2_VSEL_MASK                   0x001F
+#define WM8350_LDO2_VSEL_SHIFT                       0
+
+/*
+ * R204 (0xCC) - LDO2 Timeouts
+ */
+#define WM8350_LDO2_ERRACT_MASK                 0xC000
+#define WM8350_LDO2_ERRACT_SHIFT                    14
+#define WM8350_LDO2_ENSLOT_MASK                 0x3C00
+#define WM8350_LDO2_ENSLOT_SHIFT                    10
+#define WM8350_LDO2_SDSLOT_MASK                 0x03C0
+#define WM8350_LDO2_SDSLOT_SHIFT                     6
+
+/* Bit values for R204 (0xCC) */
+#define WM8350_LDO2_ERRACT_NONE                       0
+#define WM8350_LDO2_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_LDO2_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R205 (0xCD) - LDO2 Low Power
+ */
+#define WM8350_LDO2_HIB_MODE_MASK               0x3000
+#define WM8350_LDO2_HIB_TRIG_MASK               0x0300
+#define WM8350_LDO2_VIMG_MASK                   0x001F
+
+/*
+ * R206 (0xCE) - LDO3 Control
+ */
+#define WM8350_LDO3_SWI                         0x4000
+#define WM8350_LDO3_OPFLT                       0x0400
+#define WM8350_LDO3_VSEL_MASK                   0x001F
+#define WM8350_LDO3_VSEL_SHIFT                       0
+
+/*
+ * R207 (0xCF) - LDO3 Timeouts
+ */
+#define WM8350_LDO3_ERRACT_MASK                 0xC000
+#define WM8350_LDO3_ERRACT_SHIFT                    14
+#define WM8350_LDO3_ENSLOT_MASK                 0x3C00
+#define WM8350_LDO3_ENSLOT_SHIFT                    10
+#define WM8350_LDO3_SDSLOT_MASK                 0x03C0
+#define WM8350_LDO3_UVTO_MASK                   0x0030
+#define WM8350_LDO3_SDSLOT_SHIFT                     6
+
+/* Bit values for R207 (0xCF) */
+#define WM8350_LDO3_ERRACT_NONE                       0
+#define WM8350_LDO3_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_LDO3_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R208 (0xD0) - LDO3 Low Power
+ */
+#define WM8350_LDO3_HIB_MODE_MASK               0x3000
+#define WM8350_LDO3_HIB_TRIG_MASK               0x0300
+#define WM8350_LDO3_VIMG_MASK                   0x001F
+
+/*
+ * R209 (0xD1) - LDO4 Control
+ */
+#define WM8350_LDO4_SWI                         0x4000
+#define WM8350_LDO4_OPFLT                       0x0400
+#define WM8350_LDO4_VSEL_MASK                   0x001F
+#define WM8350_LDO4_VSEL_SHIFT                       0
+
+/*
+ * R210 (0xD2) - LDO4 Timeouts
+ */
+#define WM8350_LDO4_ERRACT_MASK                 0xC000
+#define WM8350_LDO4_ERRACT_SHIFT                    14
+#define WM8350_LDO4_ENSLOT_MASK                 0x3C00
+#define WM8350_LDO4_ENSLOT_SHIFT                    10
+#define WM8350_LDO4_SDSLOT_MASK                 0x03C0
+#define WM8350_LDO4_UVTO_MASK                   0x0030
+#define WM8350_LDO4_SDSLOT_SHIFT                     6
+
+/* Bit values for R210 (0xD2) */
+#define WM8350_LDO4_ERRACT_NONE                       0
+#define WM8350_LDO4_ERRACT_SHUTDOWN_CONV              1
+#define WM8350_LDO4_ERRACT_SHUTDOWN_SYS               2
+
+/*
+ * R211 (0xD3) - LDO4 Low Power
+ */
+#define WM8350_LDO4_HIB_MODE_MASK               0x3000
+#define WM8350_LDO4_HIB_TRIG_MASK               0x0300
+#define WM8350_LDO4_VIMG_MASK                   0x001F
+
+/*
+ * R215 (0xD7) - VCC_FAULT Masks
+ */
+#define WM8350_LS_FAULT                         0x8000
+#define WM8350_LDO4_FAULT                       0x0800
+#define WM8350_LDO3_FAULT                       0x0400
+#define WM8350_LDO2_FAULT                       0x0200
+#define WM8350_LDO1_FAULT                       0x0100
+#define WM8350_DC6_FAULT                        0x0020
+#define WM8350_DC5_FAULT                        0x0010
+#define WM8350_DC4_FAULT                        0x0008
+#define WM8350_DC3_FAULT                        0x0004
+#define WM8350_DC2_FAULT                        0x0002
+#define WM8350_DC1_FAULT                        0x0001
+
+/*
+ * R216 (0xD8) - Main Bandgap Control
+ */
+#define WM8350_MBG_LOAD_FUSES                   0x8000
+#define WM8350_MBG_FUSE_WPREP                   0x4000
+#define WM8350_MBG_FUSE_WRITE                   0x2000
+#define WM8350_MBG_FUSE_TRIM_MASK               0x1F00
+#define WM8350_MBG_TRIM_SRC                     0x0020
+#define WM8350_MBG_USER_TRIM_MASK               0x001F
+
+/*
+ * R217 (0xD9) - OSC Control
+ */
+#define WM8350_OSC_LOAD_FUSES                   0x8000
+#define WM8350_OSC_FUSE_WPREP                   0x4000
+#define WM8350_OSC_FUSE_WRITE                   0x2000
+#define WM8350_OSC_FUSE_TRIM_MASK               0x0F00
+#define WM8350_OSC_TRIM_SRC                     0x0020
+#define WM8350_OSC_USER_TRIM_MASK               0x000F
+
+/*
+ * R248 (0xF8) - DCDC1 Force PWM
+ */
+#define WM8350_DCDC1_FORCE_PWM_ENA              0x0010
+
+/*
+ * R250 (0xFA) - DCDC3 Force PWM
+ */
+#define WM8350_DCDC3_FORCE_PWM_ENA              0x0010
+
+/*
+ * R251 (0xFB) - DCDC4 Force PWM
+ */
+#define WM8350_DCDC4_FORCE_PWM_ENA              0x0010
+
+/*
+ * R253 (0xFD) - DCDC1 Force PWM
+ */
+#define WM8350_DCDC6_FORCE_PWM_ENA              0x0010
+
+/*
+ * DCDC's
+ */
+#define WM8350_DCDC_1                           0
+#define WM8350_DCDC_2                           1
+#define WM8350_DCDC_3                           2
+#define WM8350_DCDC_4                           3
+#define WM8350_DCDC_5                           4
+#define WM8350_DCDC_6                           5
+
+/* DCDC modes */
+#define WM8350_DCDC_ACTIVE_STANDBY              0
+#define WM8350_DCDC_ACTIVE_PULSE                1
+#define WM8350_DCDC_SLEEP_NORMAL                0
+#define WM8350_DCDC_SLEEP_LOW                   1
+
+/* DCDC Low power (Hibernate) mode */
+#define WM8350_DCDC_HIB_MODE_CUR                (0 << 12)
+#define WM8350_DCDC_HIB_MODE_IMAGE              (1 << 12)
+#define WM8350_DCDC_HIB_MODE_STANDBY            (2 << 12)
+#define WM8350_DCDC_HIB_MODE_LDO                (4 << 12)
+#define WM8350_DCDC_HIB_MODE_LDO_IM             (5 << 12)
+#define WM8350_DCDC_HIB_MODE_DIS                (7 << 12)
+#define WM8350_DCDC_HIB_MODE_MASK               (7 << 12)
+
+/* DCDC Low Power (Hibernate) signal */
+#define WM8350_DCDC_HIB_SIG_REG                 (0 << 8)
+#define WM8350_DCDC_HIB_SIG_LPWR1               (1 << 8)
+#define WM8350_DCDC_HIB_SIG_LPWR2               (2 << 8)
+#define WM8350_DCDC_HIB_SIG_LPWR3               (3 << 8)
+
+/* LDO Low power (Hibernate) mode */
+#define WM8350_LDO_HIB_MODE_IMAGE               (0 << 0)
+#define WM8350_LDO_HIB_MODE_DIS                 (1 << 0)
+
+/* LDO Low Power (Hibernate) signal */
+#define WM8350_LDO_HIB_SIG_REG                  (0 << 8)
+#define WM8350_LDO_HIB_SIG_LPWR1                (1 << 8)
+#define WM8350_LDO_HIB_SIG_LPWR2                (2 << 8)
+#define WM8350_LDO_HIB_SIG_LPWR3                (3 << 8)
+
+/*
+ * LDOs
+ */
+#define WM8350_LDO_1                            6
+#define WM8350_LDO_2                            7
+#define WM8350_LDO_3                            8
+#define WM8350_LDO_4                            9
+
+/*
+ * ISINKs
+ */
+#define WM8350_ISINK_A                          10
+#define WM8350_ISINK_B                          11
+
+#define WM8350_ISINK_MODE_BOOST                 0
+#define WM8350_ISINK_MODE_SWITCH                1
+#define WM8350_ISINK_ILIM_NORMAL                0
+#define WM8350_ISINK_ILIM_LOW                   1
+
+#define WM8350_ISINK_FLASH_DISABLE              0
+#define WM8350_ISINK_FLASH_ENABLE               1
+#define WM8350_ISINK_FLASH_TRIG_BIT             0
+#define WM8350_ISINK_FLASH_TRIG_GPIO            1
+#define WM8350_ISINK_FLASH_MODE_EN              (1 << 13)
+#define WM8350_ISINK_FLASH_MODE_DIS             (0 << 13)
+#define WM8350_ISINK_FLASH_DUR_32MS             (0 << 8)
+#define WM8350_ISINK_FLASH_DUR_64MS             (1 << 8)
+#define WM8350_ISINK_FLASH_DUR_96MS             (2 << 8)
+#define WM8350_ISINK_FLASH_DUR_1024MS           (3 << 8)
+#define WM8350_ISINK_FLASH_ON_INSTANT           (0 << 4)
+#define WM8350_ISINK_FLASH_ON_0_25S             (1 << 4)
+#define WM8350_ISINK_FLASH_ON_0_50S             (2 << 4)
+#define WM8350_ISINK_FLASH_ON_1_00S             (3 << 4)
+#define WM8350_ISINK_FLASH_ON_1_95S             (1 << 4)
+#define WM8350_ISINK_FLASH_ON_3_91S             (2 << 4)
+#define WM8350_ISINK_FLASH_ON_7_80S             (3 << 4)
+#define WM8350_ISINK_FLASH_OFF_INSTANT          (0 << 0)
+#define WM8350_ISINK_FLASH_OFF_0_25S            (1 << 0)
+#define WM8350_ISINK_FLASH_OFF_0_50S            (2 << 0)
+#define WM8350_ISINK_FLASH_OFF_1_00S            (3 << 0)
+#define WM8350_ISINK_FLASH_OFF_1_95S            (1 << 0)
+#define WM8350_ISINK_FLASH_OFF_3_91S            (2 << 0)
+#define WM8350_ISINK_FLASH_OFF_7_80S            (3 << 0)
+
+/*
+ * Regulator Interrupts.
+ */
+#define WM8350_IRQ_CS1                          13
+#define WM8350_IRQ_CS2                          14
+#define WM8350_IRQ_UV_LDO4                      25
+#define WM8350_IRQ_UV_LDO3                      26
+#define WM8350_IRQ_UV_LDO2                      27
+#define WM8350_IRQ_UV_LDO1                      28
+#define WM8350_IRQ_UV_DC6                       29
+#define WM8350_IRQ_UV_DC5                       30
+#define WM8350_IRQ_UV_DC4                       31
+#define WM8350_IRQ_UV_DC3                       32
+#define WM8350_IRQ_UV_DC2                       33
+#define WM8350_IRQ_UV_DC1                       34
+#define WM8350_IRQ_OC_LS                        35
+
+#define NUM_WM8350_REGULATORS                   12
+
+struct wm8350;
+struct platform_device;
+struct regulator_init_data;
+
+struct wm8350_pmic {
+        /* ISINK to DCDC mapping */
+        int isink_A_dcdc;
+        int isink_B_dcdc;
+
+        /* hibernate configs */
+        u16 dcdc1_hib_mode;
+        u16 dcdc3_hib_mode;
+        u16 dcdc4_hib_mode;
+        u16 dcdc6_hib_mode;
+
+        /* regulator devices */
+        struct platform_device *pdev[NUM_WM8350_REGULATORS];
+};
+
+int wm8350_register_regulator(struct wm8350 *wm8350, int reg,
+                              struct regulator_init_data *initdata);
+
+/*
+ * Additional DCDC control not supported via regulator API
+ */
+int wm8350_dcdc_set_slot(struct wm8350 *wm8350, int dcdc, u16 start,
+                         u16 stop, u16 fault);
+int wm8350_dcdc25_set_mode(struct wm8350 *wm8350, int dcdc, u16 mode,
+                           u16 ilim, u16 ramp, u16 feedback);
+
+/*
+ * Additional LDO control not supported via regulator API
+ */
+int wm8350_ldo_set_slot(struct wm8350 *wm8350, int ldo, u16 start, u16 stop);
+
+/*
+ * Additional ISINK control not supported via regulator API
+ */
+int wm8350_isink_set_flash(struct wm8350 *wm8350, int isink, u16 mode,
+                           u16 trigger, u16 duration, u16 on_ramp,
+                           u16 off_ramp, u16 drive);
+
+#endif
diff --git a/include/linux/mfd/wm8350/rtc.h b/include/linux/mfd/wm8350/rtc.h
new file mode 100644
index 000000000000..dfda69e9f440
--- /dev/null
+++ b/include/linux/mfd/wm8350/rtc.h
@@ -0,0 +1,266 @@
+/*
+ * rtc.h  --  RTC driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __LINUX_MFD_WM8350_RTC_H
+#define __LINUX_MFD_WM8350_RTC_H
+
+#include <linux/platform_device.h>
+
+/*
+ * Register values.
+ */
+#define WM8350_RTC_SECONDS_MINUTES              0x10
+#define WM8350_RTC_HOURS_DAY                    0x11
+#define WM8350_RTC_DATE_MONTH                   0x12
+#define WM8350_RTC_YEAR                         0x13
+#define WM8350_ALARM_SECONDS_MINUTES            0x14
+#define WM8350_ALARM_HOURS_DAY                  0x15
+#define WM8350_ALARM_DATE_MONTH                 0x16
+#define WM8350_RTC_TIME_CONTROL                 0x17
+
+/*
+ * R16 (0x10) - RTC Seconds/Minutes
+ */
+#define WM8350_RTC_MINS_MASK                    0x7F00
+#define WM8350_RTC_MINS_SHIFT                        8
+#define WM8350_RTC_SECS_MASK                    0x007F
+#define WM8350_RTC_SECS_SHIFT                        0
+
+/*
+ * R17 (0x11) - RTC Hours/Day
+ */
+#define WM8350_RTC_DAY_MASK                     0x0700
+#define WM8350_RTC_DAY_SHIFT                         8
+#define WM8350_RTC_HPM_MASK                     0x0020
+#define WM8350_RTC_HPM_SHIFT                         5
+#define WM8350_RTC_HRS_MASK                     0x001F
+#define WM8350_RTC_HRS_SHIFT                         0
+
+/* Bit values for R21 (0x15) */
+#define WM8350_RTC_DAY_SUN                           1
+#define WM8350_RTC_DAY_MON                           2
+#define WM8350_RTC_DAY_TUE                           3
+#define WM8350_RTC_DAY_WED                           4
+#define WM8350_RTC_DAY_THU                           5
+#define WM8350_RTC_DAY_FRI                           6
+#define WM8350_RTC_DAY_SAT                           7
+
+#define WM8350_RTC_HPM_AM                            0
+#define WM8350_RTC_HPM_PM                            1
+
+/*
+ * R18 (0x12) - RTC Date/Month
+ */
+#define WM8350_RTC_MTH_MASK                     0x1F00
+#define WM8350_RTC_MTH_SHIFT                         8
+#define WM8350_RTC_DATE_MASK                    0x003F
+#define WM8350_RTC_DATE_SHIFT                        0
+
+/* Bit values for R22 (0x16) */
+#define WM8350_RTC_MTH_JAN                           1
+#define WM8350_RTC_MTH_FEB                           2
+#define WM8350_RTC_MTH_MAR                           3
+#define WM8350_RTC_MTH_APR                           4
+#define WM8350_RTC_MTH_MAY                           5
+#define WM8350_RTC_MTH_JUN                           6
+#define WM8350_RTC_MTH_JUL                           7
+#define WM8350_RTC_MTH_AUG                           8
+#define WM8350_RTC_MTH_SEP                           9
+#define WM8350_RTC_MTH_OCT                          10
+#define WM8350_RTC_MTH_NOV                          11
+#define WM8350_RTC_MTH_DEC                          12
+#define WM8350_RTC_MTH_JAN_BCD                    0x01
+#define WM8350_RTC_MTH_FEB_BCD                    0x02
+#define WM8350_RTC_MTH_MAR_BCD                    0x03
+#define WM8350_RTC_MTH_APR_BCD                    0x04
+#define WM8350_RTC_MTH_MAY_BCD                    0x05
+#define WM8350_RTC_MTH_JUN_BCD                    0x06
+#define WM8350_RTC_MTH_JUL_BCD                    0x07
+#define WM8350_RTC_MTH_AUG_BCD                    0x08
+#define WM8350_RTC_MTH_SEP_BCD                    0x09
+#define WM8350_RTC_MTH_OCT_BCD                    0x10
+#define WM8350_RTC_MTH_NOV_BCD                    0x11
+#define WM8350_RTC_MTH_DEC_BCD                    0x12
+
+/*
+ * R19 (0x13) - RTC Year
+ */
+#define WM8350_RTC_YHUNDREDS_MASK               0x3F00
+#define WM8350_RTC_YHUNDREDS_SHIFT                   8
+#define WM8350_RTC_YUNITS_MASK                  0x00FF
+#define WM8350_RTC_YUNITS_SHIFT                      0
+
+/*
+ * R20 (0x14) - Alarm Seconds/Minutes
+ */
+#define WM8350_RTC_ALMMINS_MASK                 0x7F00
+#define WM8350_RTC_ALMMINS_SHIFT                     8
+#define WM8350_RTC_ALMSECS_MASK                 0x007F
+#define WM8350_RTC_ALMSECS_SHIFT                     0
+
+/* Bit values for R20 (0x14) */
+#define WM8350_RTC_ALMMINS_DONT_CARE                -1
+#define WM8350_RTC_ALMSECS_DONT_CARE                -1
+
+/*
+ * R21 (0x15) - Alarm Hours/Day
+ */
+#define WM8350_RTC_ALMDAY_MASK                  0x0F00
+#define WM8350_RTC_ALMDAY_SHIFT                      8
+#define WM8350_RTC_ALMHPM_MASK                  0x0020
+#define WM8350_RTC_ALMHPM_SHIFT                      5
+#define WM8350_RTC_ALMHRS_MASK                  0x001F
+#define WM8350_RTC_ALMHRS_SHIFT                      0
+
+/* Bit values for R21 (0x15) */
+#define WM8350_RTC_ALMDAY_DONT_CARE                 -1
+#define WM8350_RTC_ALMDAY_SUN                        1
+#define WM8350_RTC_ALMDAY_MON                        2
+#define WM8350_RTC_ALMDAY_TUE                        3
+#define WM8350_RTC_ALMDAY_WED                        4
+#define WM8350_RTC_ALMDAY_THU                        5
+#define WM8350_RTC_ALMDAY_FRI                        6
+#define WM8350_RTC_ALMDAY_SAT                        7
+
+#define WM8350_RTC_ALMHPM_AM                         0
+#define WM8350_RTC_ALMHPM_PM                         1
+
+#define WM8350_RTC_ALMHRS_DONT_CARE                 -1
+
+/*
+ * R22 (0x16) - Alarm Date/Month
+ */
+#define WM8350_RTC_ALMMTH_MASK                  0x1F00
+#define WM8350_RTC_ALMMTH_SHIFT                      8
+#define WM8350_RTC_ALMDATE_MASK                 0x003F
+#define WM8350_RTC_ALMDATE_SHIFT                     0
+
+/* Bit values for R22 (0x16) */
+#define WM8350_RTC_ALMDATE_DONT_CARE                -1
+
+#define WM8350_RTC_ALMMTH_DONT_CARE                 -1
+#define WM8350_RTC_ALMMTH_JAN                        1
+#define WM8350_RTC_ALMMTH_FEB                        2
+#define WM8350_RTC_ALMMTH_MAR                        3
+#define WM8350_RTC_ALMMTH_APR                        4
+#define WM8350_RTC_ALMMTH_MAY                        5
+#define WM8350_RTC_ALMMTH_JUN                        6
+#define WM8350_RTC_ALMMTH_JUL                        7
+#define WM8350_RTC_ALMMTH_AUG                        8
+#define WM8350_RTC_ALMMTH_SEP                        9
+#define WM8350_RTC_ALMMTH_OCT                       10
+#define WM8350_RTC_ALMMTH_NOV                       11
+#define WM8350_RTC_ALMMTH_DEC                       12
+#define WM8350_RTC_ALMMTH_JAN_BCD                 0x01
+#define WM8350_RTC_ALMMTH_FEB_BCD                 0x02
+#define WM8350_RTC_ALMMTH_MAR_BCD                 0x03
+#define WM8350_RTC_ALMMTH_APR_BCD                 0x04
+#define WM8350_RTC_ALMMTH_MAY_BCD                 0x05
+#define WM8350_RTC_ALMMTH_JUN_BCD                 0x06
+#define WM8350_RTC_ALMMTH_JUL_BCD                 0x07
+#define WM8350_RTC_ALMMTH_AUG_BCD                 0x08
+#define WM8350_RTC_ALMMTH_SEP_BCD                 0x09
+#define WM8350_RTC_ALMMTH_OCT_BCD                 0x10
+#define WM8350_RTC_ALMMTH_NOV_BCD                 0x11
+#define WM8350_RTC_ALMMTH_DEC_BCD                 0x12
+
+/*
+ * R23 (0x17) - RTC Time Control
+ */
+#define WM8350_RTC_BCD                          0x8000
+#define WM8350_RTC_BCD_MASK                     0x8000
+#define WM8350_RTC_BCD_SHIFT                        15
+#define WM8350_RTC_12HR                         0x4000
+#define WM8350_RTC_12HR_MASK                    0x4000
+#define WM8350_RTC_12HR_SHIFT                       14
+#define WM8350_RTC_DST                          0x2000
+#define WM8350_RTC_DST_MASK                     0x2000
+#define WM8350_RTC_DST_SHIFT                        13
+#define WM8350_RTC_SET                          0x0800
+#define WM8350_RTC_SET_MASK                     0x0800
+#define WM8350_RTC_SET_SHIFT                        11
+#define WM8350_RTC_STS                          0x0400
+#define WM8350_RTC_STS_MASK                     0x0400
+#define WM8350_RTC_STS_SHIFT                        10
+#define WM8350_RTC_ALMSET                       0x0200
+#define WM8350_RTC_ALMSET_MASK                  0x0200
+#define WM8350_RTC_ALMSET_SHIFT                      9
+#define WM8350_RTC_ALMSTS                       0x0100
+#define WM8350_RTC_ALMSTS_MASK                  0x0100
+#define WM8350_RTC_ALMSTS_SHIFT                      8
+#define WM8350_RTC_PINT                         0x0070
+#define WM8350_RTC_PINT_MASK                    0x0070
+#define WM8350_RTC_PINT_SHIFT                        4
+#define WM8350_RTC_DSW                          0x000F
+#define WM8350_RTC_DSW_MASK                     0x000F
+#define WM8350_RTC_DSW_SHIFT                         0
+
+/* Bit values for R23 (0x17) */
+#define WM8350_RTC_BCD_BINARY                        0
+#define WM8350_RTC_BCD_BCD                           1
+
+#define WM8350_RTC_12HR_24HR                         0
+#define WM8350_RTC_12HR_12HR                         1
+
+#define WM8350_RTC_DST_DISABLED                      0
+#define WM8350_RTC_DST_ENABLED                       1
+
+#define WM8350_RTC_SET_RUN                           0
+#define WM8350_RTC_SET_SET                           1
+
+#define WM8350_RTC_STS_RUNNING                       0
+#define WM8350_RTC_STS_STOPPED                       1
+
+#define WM8350_RTC_ALMSET_RUN                        0
+#define WM8350_RTC_ALMSET_SET                        1
+
+#define WM8350_RTC_ALMSTS_RUNNING                    0
+#define WM8350_RTC_ALMSTS_STOPPED                    1
+
+#define WM8350_RTC_PINT_DISABLED                     0
+#define WM8350_RTC_PINT_SECS                         1
+#define WM8350_RTC_PINT_MINS                         2
+#define WM8350_RTC_PINT_HRS                          3
+#define WM8350_RTC_PINT_DAYS                         4
+#define WM8350_RTC_PINT_MTHS                         5
+
+#define WM8350_RTC_DSW_DISABLED                      0
+#define WM8350_RTC_DSW_1HZ                           1
+#define WM8350_RTC_DSW_2HZ                           2
+#define WM8350_RTC_DSW_4HZ                           3
+#define WM8350_RTC_DSW_8HZ                           4
+#define WM8350_RTC_DSW_16HZ                          5
+#define WM8350_RTC_DSW_32HZ                          6
+#define WM8350_RTC_DSW_64HZ                          7
+#define WM8350_RTC_DSW_128HZ                         8
+#define WM8350_RTC_DSW_256HZ                         9
+#define WM8350_RTC_DSW_512HZ                        10
+#define WM8350_RTC_DSW_1024HZ                       11
+
+/*
+ * R218 (0xDA) - RTC Tick Control
+ */
+#define WM8350_RTC_TICKSTS                      0x4000
+#define WM8350_RTC_CLKSRC                       0x2000
+#define WM8350_RTC_TRIM_MASK                    0x03FF
+
+/*
+ * RTC Interrupts.
+ */
+#define WM8350_IRQ_RTC_PER                      7
+#define WM8350_IRQ_RTC_SEC                      8
+#define WM8350_IRQ_RTC_ALM                      9
+
+struct wm8350_rtc {
+        struct platform_device *pdev;
+};
+
+#endif
diff --git a/include/linux/mfd/wm8350/supply.h b/include/linux/mfd/wm8350/supply.h
new file mode 100644
index 000000000000..1c8f3cde79b0
--- /dev/null
+++ b/include/linux/mfd/wm8350/supply.h
@@ -0,0 +1,111 @@
+/*
+ * supply.h  --  Power Supply Driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ *
+ */
+
+#ifndef __LINUX_MFD_WM8350_SUPPLY_H_
+#define __LINUX_MFD_WM8350_SUPPLY_H_
+
+#include <linux/platform_device.h>
+
+/*
+ * Charger registers
+ */
+#define WM8350_BATTERY_CHARGER_CONTROL_1        0xA8
+#define WM8350_BATTERY_CHARGER_CONTROL_2        0xA9
+#define WM8350_BATTERY_CHARGER_CONTROL_3        0xAA
+
+/*
+ * R168 (0xA8) - Battery Charger Control 1
+ */
+#define WM8350_CHG_ENA_R168                     0x8000
+#define WM8350_CHG_THR                          0x2000
+#define WM8350_CHG_EOC_SEL_MASK                 0x1C00
+#define WM8350_CHG_TRICKLE_TEMP_CHOKE           0x0200
+#define WM8350_CHG_TRICKLE_USB_CHOKE            0x0100
+#define WM8350_CHG_RECOVER_T                    0x0080
+#define WM8350_CHG_END_ACT                      0x0040
+#define WM8350_CHG_FAST                         0x0020
+#define WM8350_CHG_FAST_USB_THROTTLE            0x0010
+#define WM8350_CHG_NTC_MON                      0x0008
+#define WM8350_CHG_BATT_HOT_MON                 0x0004
+#define WM8350_CHG_BATT_COLD_MON                0x0002
+#define WM8350_CHG_CHIP_TEMP_MON                0x0001
+
+/*
+ * R169 (0xA9) - Battery Charger Control 2
+ */
+#define WM8350_CHG_ACTIVE                       0x8000
+#define WM8350_CHG_PAUSE                        0x4000
+#define WM8350_CHG_STS_MASK                     0x3000
+#define WM8350_CHG_TIME_MASK                    0x0F00
+#define WM8350_CHG_MASK_WALL_FB                 0x0080
+#define WM8350_CHG_TRICKLE_SEL                  0x0040
+#define WM8350_CHG_VSEL_MASK                    0x0030
+#define WM8350_CHG_ISEL_MASK                    0x000F
+#define WM8350_CHG_STS_OFF                      0x0000
+#define WM8350_CHG_STS_TRICKLE                  0x1000
+#define WM8350_CHG_STS_FAST                     0x2000
+
+/*
+ * R170 (0xAA) - Battery Charger Control 3
+ */
+#define WM8350_CHG_THROTTLE_T_MASK              0x0060
+#define WM8350_CHG_SMART                        0x0010
+#define WM8350_CHG_TIMER_ADJT_MASK              0x000F
+
+/*
+ * Charger Interrupts
+ */
+#define WM8350_IRQ_CHG_BAT_HOT                  0
+#define WM8350_IRQ_CHG_BAT_COLD                 1
+#define WM8350_IRQ_CHG_BAT_FAIL                 2
+#define WM8350_IRQ_CHG_TO                       3
+#define WM8350_IRQ_CHG_END                      4
+#define WM8350_IRQ_CHG_START                    5
+#define WM8350_IRQ_CHG_FAST_RDY                 6
+#define WM8350_IRQ_CHG_VBATT_LT_3P9             10
+#define WM8350_IRQ_CHG_VBATT_LT_3P1             11
+#define WM8350_IRQ_CHG_VBATT_LT_2P85            12
+
+/*
+ * Charger Policy
+ */
+#define WM8350_CHG_TRICKLE_50mA                 (0 << 6)
+#define WM8350_CHG_TRICKLE_100mA                (1 << 6)
+#define WM8350_CHG_4_05V                        (0 << 4)
+#define WM8350_CHG_4_10V                        (1 << 4)
+#define WM8350_CHG_4_15V                        (2 << 4)
+#define WM8350_CHG_4_20V                        (3 << 4)
+#define WM8350_CHG_FAST_LIMIT_mA(x)             ((x / 50) & 0xf)
+#define WM8350_CHG_EOC_mA(x)                    (((x - 10) & 0x7) << 10)
+#define WM8350_CHG_TRICKLE_3_1V                 (0 << 13)
+#define WM8350_CHG_TRICKLE_3_9V                 (1 << 13)
+
+/*
+ * Supply Registers.
+ */
+#define WM8350_USB_VOLTAGE_READBACK             0x9C
+#define WM8350_LINE_VOLTAGE_READBACK            0x9D
+#define WM8350_BATT_VOLTAGE_READBACK            0x9E
+
+/*
+ * Supply Interrupts.
+ */
+#define WM8350_IRQ_USB_LIMIT                    15
+#define WM8350_IRQ_EXT_USB_FB                   36
+#define WM8350_IRQ_EXT_WALL_FB                  37
+#define WM8350_IRQ_EXT_BAT_FB                   38
+
+struct wm8350_power {
+        struct platform_device *pdev;
+};
+
+#endif
diff --git a/include/linux/mfd/wm8350/wdt.h b/include/linux/mfd/wm8350/wdt.h
new file mode 100644
index 000000000000..f6135b5e5ef4
--- /dev/null
+++ b/include/linux/mfd/wm8350/wdt.h
@@ -0,0 +1,28 @@
+/*
+ * wdt.h  --  Watchdog Driver for Wolfson WM8350 PMIC
+ *
+ * Copyright 2007, 2008 Wolfson Microelectronics PLC
+ *
+ *  This program is free software; you can redistribute  it and/or modify it
+ *  under  the terms of  the GNU General  Public License as published by the
+ *  Free Software Foundation;  either version 2 of the  License, or (at your
+ *  option) any later version.
+ */
+
+#ifndef __LINUX_MFD_WM8350_WDT_H_
+#define __LINUX_MFD_WM8350_WDT_H_
+
+#include <linux/platform_device.h>
+
+#define WM8350_WDOG_HIB_MODE                    0x0080
+#define WM8350_WDOG_DEBUG                       0x0040
+#define WM8350_WDOG_MODE_MASK                   0x0030
+#define WM8350_WDOG_TO_MASK                     0x0007
+
+#define WM8350_IRQ_SYS_WDOG_TO                  24
+
+struct wm8350_wdt {
+        struct platform_device *pdev;
+};
+
+#endif
diff --git a/include/linux/mfd/wm8400-audio.h b/include/linux/mfd/wm8400-audio.h
new file mode 100644
index 000000000000..b6640e018046
--- /dev/null
+++ b/include/linux/mfd/wm8400-audio.h
@@ -0,0 +1,1186 @@
+/*
+ * wm8400 private definitions for audio
+ *
+ * Copyright 2008 Wolfson Microelectronics plc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_MFD_WM8400_AUDIO_H
+#define __LINUX_MFD_WM8400_AUDIO_H
+
+#include <linux/mfd/wm8400-audio.h>
+
+/*
+ * R2 (0x02) - Power Management (1)
+ */
+#define WM8400_CODEC_ENA                        0x8000  /* CODEC_ENA */
+#define WM8400_CODEC_ENA_MASK                   0x8000  /* CODEC_ENA */
+#define WM8400_CODEC_ENA_SHIFT                      15  /* CODEC_ENA */
+#define WM8400_CODEC_ENA_WIDTH                       1  /* CODEC_ENA */
+#define WM8400_SYSCLK_ENA                       0x4000  /* SYSCLK_ENA */
+#define WM8400_SYSCLK_ENA_MASK                  0x4000  /* SYSCLK_ENA */
+#define WM8400_SYSCLK_ENA_SHIFT                     14  /* SYSCLK_ENA */
+#define WM8400_SYSCLK_ENA_WIDTH                      1  /* SYSCLK_ENA */
+#define WM8400_SPK_MIX_ENA                      0x2000  /* SPK_MIX_ENA */
+#define WM8400_SPK_MIX_ENA_MASK                 0x2000  /* SPK_MIX_ENA */
+#define WM8400_SPK_MIX_ENA_SHIFT                    13  /* SPK_MIX_ENA */
+#define WM8400_SPK_MIX_ENA_WIDTH                     1  /* SPK_MIX_ENA */
+#define WM8400_SPK_ENA                          0x1000  /* SPK_ENA */
+#define WM8400_SPK_ENA_MASK                     0x1000  /* SPK_ENA */
+#define WM8400_SPK_ENA_SHIFT                        12  /* SPK_ENA */
+#define WM8400_SPK_ENA_WIDTH                         1  /* SPK_ENA */
+#define WM8400_OUT3_ENA                         0x0800  /* OUT3_ENA */
+#define WM8400_OUT3_ENA_MASK                    0x0800  /* OUT3_ENA */
+#define WM8400_OUT3_ENA_SHIFT                       11  /* OUT3_ENA */
+#define WM8400_OUT3_ENA_WIDTH                        1  /* OUT3_ENA */
+#define WM8400_OUT4_ENA                         0x0400  /* OUT4_ENA */
+#define WM8400_OUT4_ENA_MASK                    0x0400  /* OUT4_ENA */
+#define WM8400_OUT4_ENA_SHIFT                       10  /* OUT4_ENA */
+#define WM8400_OUT4_ENA_WIDTH                        1  /* OUT4_ENA */
+#define WM8400_LOUT_ENA                         0x0200  /* LOUT_ENA */
+#define WM8400_LOUT_ENA_MASK                    0x0200  /* LOUT_ENA */
+#define WM8400_LOUT_ENA_SHIFT                        9  /* LOUT_ENA */
+#define WM8400_LOUT_ENA_WIDTH                        1  /* LOUT_ENA */
+#define WM8400_ROUT_ENA                         0x0100  /* ROUT_ENA */
+#define WM8400_ROUT_ENA_MASK                    0x0100  /* ROUT_ENA */
+#define WM8400_ROUT_ENA_SHIFT                        8  /* ROUT_ENA */
+#define WM8400_ROUT_ENA_WIDTH                        1  /* ROUT_ENA */
+#define WM8400_MIC1BIAS_ENA                     0x0010  /* MIC1BIAS_ENA */
+#define WM8400_MIC1BIAS_ENA_MASK                0x0010  /* MIC1BIAS_ENA */
+#define WM8400_MIC1BIAS_ENA_SHIFT                    4  /* MIC1BIAS_ENA */
+#define WM8400_MIC1BIAS_ENA_WIDTH                    1  /* MIC1BIAS_ENA */
+#define WM8400_VMID_MODE_MASK                   0x0006  /* VMID_MODE - [2:1] */
+#define WM8400_VMID_MODE_SHIFT                       1  /* VMID_MODE - [2:1] */
+#define WM8400_VMID_MODE_WIDTH                       2  /* VMID_MODE - [2:1] */
+#define WM8400_VREF_ENA                         0x0001  /* VREF_ENA */
+#define WM8400_VREF_ENA_MASK                    0x0001  /* VREF_ENA */
+#define WM8400_VREF_ENA_SHIFT                        0  /* VREF_ENA */
+#define WM8400_VREF_ENA_WIDTH                        1  /* VREF_ENA */
+
+/*
+ * R3 (0x03) - Power Management (2)
+ */
+#define WM8400_FLL_ENA                          0x8000  /* FLL_ENA */
+#define WM8400_FLL_ENA_MASK                     0x8000  /* FLL_ENA */
+#define WM8400_FLL_ENA_SHIFT                        15  /* FLL_ENA */
+#define WM8400_FLL_ENA_WIDTH                         1  /* FLL_ENA */
+#define WM8400_TSHUT_ENA                        0x4000  /* TSHUT_ENA */
+#define WM8400_TSHUT_ENA_MASK                   0x4000  /* TSHUT_ENA */
+#define WM8400_TSHUT_ENA_SHIFT                      14  /* TSHUT_ENA */
+#define WM8400_TSHUT_ENA_WIDTH                       1  /* TSHUT_ENA */
+#define WM8400_TSHUT_OPDIS                      0x2000  /* TSHUT_OPDIS */
+#define WM8400_TSHUT_OPDIS_MASK                 0x2000  /* TSHUT_OPDIS */
+#define WM8400_TSHUT_OPDIS_SHIFT                    13  /* TSHUT_OPDIS */
+#define WM8400_TSHUT_OPDIS_WIDTH                     1  /* TSHUT_OPDIS */
+#define WM8400_OPCLK_ENA                        0x0800  /* OPCLK_ENA */
+#define WM8400_OPCLK_ENA_MASK                   0x0800  /* OPCLK_ENA */
+#define WM8400_OPCLK_ENA_SHIFT                      11  /* OPCLK_ENA */
+#define WM8400_OPCLK_ENA_WIDTH                       1  /* OPCLK_ENA */
+#define WM8400_AINL_ENA                         0x0200  /* AINL_ENA */
+#define WM8400_AINL_ENA_MASK                    0x0200  /* AINL_ENA */
+#define WM8400_AINL_ENA_SHIFT                        9  /* AINL_ENA */
+#define WM8400_AINL_ENA_WIDTH                        1  /* AINL_ENA */
+#define WM8400_AINR_ENA                         0x0100  /* AINR_ENA */
+#define WM8400_AINR_ENA_MASK                    0x0100  /* AINR_ENA */
+#define WM8400_AINR_ENA_SHIFT                        8  /* AINR_ENA */
+#define WM8400_AINR_ENA_WIDTH                        1  /* AINR_ENA */
+#define WM8400_LIN34_ENA                        0x0080  /* LIN34_ENA */
+#define WM8400_LIN34_ENA_MASK                   0x0080  /* LIN34_ENA */
+#define WM8400_LIN34_ENA_SHIFT                       7  /* LIN34_ENA */
+#define WM8400_LIN34_ENA_WIDTH                       1  /* LIN34_ENA */
+#define WM8400_LIN12_ENA                        0x0040  /* LIN12_ENA */
+#define WM8400_LIN12_ENA_MASK                   0x0040  /* LIN12_ENA */
+#define WM8400_LIN12_ENA_SHIFT                       6  /* LIN12_ENA */
+#define WM8400_LIN12_ENA_WIDTH                       1  /* LIN12_ENA */
+#define WM8400_RIN34_ENA                        0x0020  /* RIN34_ENA */
+#define WM8400_RIN34_ENA_MASK                   0x0020  /* RIN34_ENA */
+#define WM8400_RIN34_ENA_SHIFT                       5  /* RIN34_ENA */
+#define WM8400_RIN34_ENA_WIDTH                       1  /* RIN34_ENA */
+#define WM8400_RIN12_ENA                        0x0010  /* RIN12_ENA */
+#define WM8400_RIN12_ENA_MASK                   0x0010  /* RIN12_ENA */
+#define WM8400_RIN12_ENA_SHIFT                       4  /* RIN12_ENA */
+#define WM8400_RIN12_ENA_WIDTH                       1  /* RIN12_ENA */
+#define WM8400_ADCL_ENA                         0x0002  /* ADCL_ENA */
+#define WM8400_ADCL_ENA_MASK                    0x0002  /* ADCL_ENA */
+#define WM8400_ADCL_ENA_SHIFT                        1  /* ADCL_ENA */
+#define WM8400_ADCL_ENA_WIDTH                        1  /* ADCL_ENA */
+#define WM8400_ADCR_ENA                         0x0001  /* ADCR_ENA */
+#define WM8400_ADCR_ENA_MASK                    0x0001  /* ADCR_ENA */
+#define WM8400_ADCR_ENA_SHIFT                        0  /* ADCR_ENA */
+#define WM8400_ADCR_ENA_WIDTH                        1  /* ADCR_ENA */
+
+/*
+ * R4 (0x04) - Power Management (3)
+ */
+#define WM8400_LON_ENA                          0x2000  /* LON_ENA */
+#define WM8400_LON_ENA_MASK                     0x2000  /* LON_ENA */
+#define WM8400_LON_ENA_SHIFT                        13  /* LON_ENA */
+#define WM8400_LON_ENA_WIDTH                         1  /* LON_ENA */
+#define WM8400_LOP_ENA                          0x1000  /* LOP_ENA */
+#define WM8400_LOP_ENA_MASK                     0x1000  /* LOP_ENA */
+#define WM8400_LOP_ENA_SHIFT                        12  /* LOP_ENA */
+#define WM8400_LOP_ENA_WIDTH                         1  /* LOP_ENA */
+#define WM8400_RON_ENA                          0x0800  /* RON_ENA */
+#define WM8400_RON_ENA_MASK                     0x0800  /* RON_ENA */
+#define WM8400_RON_ENA_SHIFT                        11  /* RON_ENA */
+#define WM8400_RON_ENA_WIDTH                         1  /* RON_ENA */
+#define WM8400_ROP_ENA                          0x0400  /* ROP_ENA */
+#define WM8400_ROP_ENA_MASK                     0x0400  /* ROP_ENA */
+#define WM8400_ROP_ENA_SHIFT                        10  /* ROP_ENA */
+#define WM8400_ROP_ENA_WIDTH                         1  /* ROP_ENA */
+#define WM8400_LOPGA_ENA                        0x0080  /* LOPGA_ENA */
+#define WM8400_LOPGA_ENA_MASK                   0x0080  /* LOPGA_ENA */
+#define WM8400_LOPGA_ENA_SHIFT                       7  /* LOPGA_ENA */
+#define WM8400_LOPGA_ENA_WIDTH                       1  /* LOPGA_ENA */
+#define WM8400_ROPGA_ENA                        0x0040  /* ROPGA_ENA */
+#define WM8400_ROPGA_ENA_MASK                   0x0040  /* ROPGA_ENA */
+#define WM8400_ROPGA_ENA_SHIFT                       6  /* ROPGA_ENA */
+#define WM8400_ROPGA_ENA_WIDTH                       1  /* ROPGA_ENA */
+#define WM8400_LOMIX_ENA                        0x0020  /* LOMIX_ENA */
+#define WM8400_LOMIX_ENA_MASK                   0x0020  /* LOMIX_ENA */
+#define WM8400_LOMIX_ENA_SHIFT                       5  /* LOMIX_ENA */
+#define WM8400_LOMIX_ENA_WIDTH                       1  /* LOMIX_ENA */
+#define WM8400_ROMIX_ENA                        0x0010  /* ROMIX_ENA */
+#define WM8400_ROMIX_ENA_MASK                   0x0010  /* ROMIX_ENA */
+#define WM8400_ROMIX_ENA_SHIFT                       4  /* ROMIX_ENA */
+#define WM8400_ROMIX_ENA_WIDTH                       1  /* ROMIX_ENA */
+#define WM8400_DACL_ENA                         0x0002  /* DACL_ENA */
+#define WM8400_DACL_ENA_MASK                    0x0002  /* DACL_ENA */
+#define WM8400_DACL_ENA_SHIFT                        1  /* DACL_ENA */
+#define WM8400_DACL_ENA_WIDTH                        1  /* DACL_ENA */
+#define WM8400_DACR_ENA                         0x0001  /* DACR_ENA */
+#define WM8400_DACR_ENA_MASK                    0x0001  /* DACR_ENA */
+#define WM8400_DACR_ENA_SHIFT                        0  /* DACR_ENA */
+#define WM8400_DACR_ENA_WIDTH                        1  /* DACR_ENA */
+
+/*
+ * R5 (0x05) - Audio Interface (1)
+ */
+#define WM8400_AIFADCL_SRC                      0x8000  /* AIFADCL_SRC */
+#define WM8400_AIFADCL_SRC_MASK                 0x8000  /* AIFADCL_SRC */
+#define WM8400_AIFADCL_SRC_SHIFT                    15  /* AIFADCL_SRC */
+#define WM8400_AIFADCL_SRC_WIDTH                     1  /* AIFADCL_SRC */
+#define WM8400_AIFADCR_SRC                      0x4000  /* AIFADCR_SRC */
+#define WM8400_AIFADCR_SRC_MASK                 0x4000  /* AIFADCR_SRC */
+#define WM8400_AIFADCR_SRC_SHIFT                    14  /* AIFADCR_SRC */
+#define WM8400_AIFADCR_SRC_WIDTH                     1  /* AIFADCR_SRC */
+#define WM8400_AIFADC_TDM                       0x2000  /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_MASK                  0x2000  /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_SHIFT                     13  /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_WIDTH                      1  /* AIFADC_TDM */
+#define WM8400_AIFADC_TDM_CHAN                  0x1000  /* AIFADC_TDM_CHAN */
+#define WM8400_AIFADC_TDM_CHAN_MASK             0x1000  /* AIFADC_TDM_CHAN */
+#define WM8400_AIFADC_TDM_CHAN_SHIFT                12  /* AIFADC_TDM_CHAN */
+#define WM8400_AIFADC_TDM_CHAN_WIDTH                 1  /* AIFADC_TDM_CHAN */
+#define WM8400_AIF_BCLK_INV                     0x0100  /* AIF_BCLK_INV */
+#define WM8400_AIF_BCLK_INV_MASK                0x0100  /* AIF_BCLK_INV */
+#define WM8400_AIF_BCLK_INV_SHIFT                    8  /* AIF_BCLK_INV */
+#define WM8400_AIF_BCLK_INV_WIDTH                    1  /* AIF_BCLK_INV */
+#define WM8400_AIF_LRCLK_INV                    0x0080  /* AIF_LRCLK_INV */
+#define WM8400_AIF_LRCLK_INV_MASK               0x0080  /* AIF_LRCLK_INV */
+#define WM8400_AIF_LRCLK_INV_SHIFT                   7  /* AIF_LRCLK_INV */
+#define WM8400_AIF_LRCLK_INV_WIDTH                   1  /* AIF_LRCLK_INV */
+#define WM8400_AIF_WL_MASK                      0x0060  /* AIF_WL - [6:5] */
+#define WM8400_AIF_WL_SHIFT                          5  /* AIF_WL - [6:5] */
+#define WM8400_AIF_WL_WIDTH                          2  /* AIF_WL - [6:5] */
+#define WM8400_AIF_WL_16BITS                    (0 << 5)
+#define WM8400_AIF_WL_20BITS                    (1 << 5)
+#define WM8400_AIF_WL_24BITS                    (2 << 5)
+#define WM8400_AIF_WL_32BITS                    (3 << 5)
+#define WM8400_AIF_FMT_MASK                     0x0018  /* AIF_FMT - [4:3] */
+#define WM8400_AIF_FMT_SHIFT                         3  /* AIF_FMT - [4:3] */
+#define WM8400_AIF_FMT_WIDTH                         2  /* AIF_FMT - [4:3] */
+#define WM8400_AIF_FMT_RIGHTJ                   (0 << 3)
+#define WM8400_AIF_FMT_LEFTJ                    (1 << 3)
+#define WM8400_AIF_FMT_I2S                      (2 << 3)
+#define WM8400_AIF_FMT_DSP                      (3 << 3)
+
+/*
+ * R6 (0x06) - Audio Interface (2)
+ */
+#define WM8400_DACL_SRC                         0x8000  /* DACL_SRC */
+#define WM8400_DACL_SRC_MASK                    0x8000  /* DACL_SRC */
+#define WM8400_DACL_SRC_SHIFT                       15  /* DACL_SRC */
+#define WM8400_DACL_SRC_WIDTH                        1  /* DACL_SRC */
+#define WM8400_DACR_SRC                         0x4000  /* DACR_SRC */
+#define WM8400_DACR_SRC_MASK                    0x4000  /* DACR_SRC */
+#define WM8400_DACR_SRC_SHIFT                       14  /* DACR_SRC */
+#define WM8400_DACR_SRC_WIDTH                        1  /* DACR_SRC */
+#define WM8400_AIFDAC_TDM                       0x2000  /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_MASK                  0x2000  /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_SHIFT                     13  /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_WIDTH                      1  /* AIFDAC_TDM */
+#define WM8400_AIFDAC_TDM_CHAN                  0x1000  /* AIFDAC_TDM_CHAN */
+#define WM8400_AIFDAC_TDM_CHAN_MASK             0x1000  /* AIFDAC_TDM_CHAN */
+#define WM8400_AIFDAC_TDM_CHAN_SHIFT                12  /* AIFDAC_TDM_CHAN */
+#define WM8400_AIFDAC_TDM_CHAN_WIDTH                 1  /* AIFDAC_TDM_CHAN */
+#define WM8400_DAC_BOOST_MASK                   0x0C00  /* DAC_BOOST - [11:10] */
+#define WM8400_DAC_BOOST_SHIFT                      10  /* DAC_BOOST - [11:10] */
+#define WM8400_DAC_BOOST_WIDTH                       2  /* DAC_BOOST - [11:10] */
+#define WM8400_DAC_COMP                         0x0010  /* DAC_COMP */
+#define WM8400_DAC_COMP_MASK                    0x0010  /* DAC_COMP */
+#define WM8400_DAC_COMP_SHIFT                        4  /* DAC_COMP */
+#define WM8400_DAC_COMP_WIDTH                        1  /* DAC_COMP */
+#define WM8400_DAC_COMPMODE                     0x0008  /* DAC_COMPMODE */
+#define WM8400_DAC_COMPMODE_MASK                0x0008  /* DAC_COMPMODE */
+#define WM8400_DAC_COMPMODE_SHIFT                    3  /* DAC_COMPMODE */
+#define WM8400_DAC_COMPMODE_WIDTH                    1  /* DAC_COMPMODE */
+#define WM8400_ADC_COMP                         0x0004  /* ADC_COMP */
+#define WM8400_ADC_COMP_MASK                    0x0004  /* ADC_COMP */
+#define WM8400_ADC_COMP_SHIFT                        2  /* ADC_COMP */
+#define WM8400_ADC_COMP_WIDTH                        1  /* ADC_COMP */
+#define WM8400_ADC_COMPMODE                     0x0002  /* ADC_COMPMODE */
+#define WM8400_ADC_COMPMODE_MASK                0x0002  /* ADC_COMPMODE */
+#define WM8400_ADC_COMPMODE_SHIFT                    1  /* ADC_COMPMODE */
+#define WM8400_ADC_COMPMODE_WIDTH                    1  /* ADC_COMPMODE */
+#define WM8400_LOOPBACK                         0x0001  /* LOOPBACK */
+#define WM8400_LOOPBACK_MASK                    0x0001  /* LOOPBACK */
+#define WM8400_LOOPBACK_SHIFT                        0  /* LOOPBACK */
+#define WM8400_LOOPBACK_WIDTH                        1  /* LOOPBACK */
+
+/*
+ * R7 (0x07) - Clocking (1)
+ */
+#define WM8400_TOCLK_RATE                       0x8000  /* TOCLK_RATE */
+#define WM8400_TOCLK_RATE_MASK                  0x8000  /* TOCLK_RATE */
+#define WM8400_TOCLK_RATE_SHIFT                     15  /* TOCLK_RATE */
+#define WM8400_TOCLK_RATE_WIDTH                      1  /* TOCLK_RATE */
+#define WM8400_TOCLK_ENA                        0x4000  /* TOCLK_ENA */
+#define WM8400_TOCLK_ENA_MASK                   0x4000  /* TOCLK_ENA */
+#define WM8400_TOCLK_ENA_SHIFT                      14  /* TOCLK_ENA */
+#define WM8400_TOCLK_ENA_WIDTH                       1  /* TOCLK_ENA */
+#define WM8400_OPCLKDIV_MASK                    0x1E00  /* OPCLKDIV - [12:9] */
+#define WM8400_OPCLKDIV_SHIFT                        9  /* OPCLKDIV - [12:9] */
+#define WM8400_OPCLKDIV_WIDTH                        4  /* OPCLKDIV - [12:9] */
+#define WM8400_DCLKDIV_MASK                     0x01C0  /* DCLKDIV - [8:6] */
+#define WM8400_DCLKDIV_SHIFT                         6  /* DCLKDIV - [8:6] */
+#define WM8400_DCLKDIV_WIDTH                         3  /* DCLKDIV - [8:6] */
+#define WM8400_BCLK_DIV_MASK                    0x001E  /* BCLK_DIV - [4:1] */
+#define WM8400_BCLK_DIV_SHIFT                        1  /* BCLK_DIV - [4:1] */
+#define WM8400_BCLK_DIV_WIDTH                        4  /* BCLK_DIV - [4:1] */
+
+/*
+ * R8 (0x08) - Clocking (2)
+ */
+#define WM8400_MCLK_SRC                         0x8000  /* MCLK_SRC */
+#define WM8400_MCLK_SRC_MASK                    0x8000  /* MCLK_SRC */
+#define WM8400_MCLK_SRC_SHIFT                       15  /* MCLK_SRC */
+#define WM8400_MCLK_SRC_WIDTH                        1  /* MCLK_SRC */
+#define WM8400_SYSCLK_SRC                       0x4000  /* SYSCLK_SRC */
+#define WM8400_SYSCLK_SRC_MASK                  0x4000  /* SYSCLK_SRC */
+#define WM8400_SYSCLK_SRC_SHIFT                     14  /* SYSCLK_SRC */
+#define WM8400_SYSCLK_SRC_WIDTH                      1  /* SYSCLK_SRC */
+#define WM8400_CLK_FORCE                        0x2000  /* CLK_FORCE */
+#define WM8400_CLK_FORCE_MASK                   0x2000  /* CLK_FORCE */
+#define WM8400_CLK_FORCE_SHIFT                      13  /* CLK_FORCE */
+#define WM8400_CLK_FORCE_WIDTH                       1  /* CLK_FORCE */
+#define WM8400_MCLK_DIV_MASK                    0x1800  /* MCLK_DIV - [12:11] */
+#define WM8400_MCLK_DIV_SHIFT                       11  /* MCLK_DIV - [12:11] */
+#define WM8400_MCLK_DIV_WIDTH                        2  /* MCLK_DIV - [12:11] */
+#define WM8400_MCLK_INV                         0x0400  /* MCLK_INV */
+#define WM8400_MCLK_INV_MASK                    0x0400  /* MCLK_INV */
+#define WM8400_MCLK_INV_SHIFT                       10  /* MCLK_INV */
+#define WM8400_MCLK_INV_WIDTH                        1  /* MCLK_INV */
+#define WM8400_ADC_CLKDIV_MASK                  0x00E0  /* ADC_CLKDIV - [7:5] */
+#define WM8400_ADC_CLKDIV_SHIFT                      5  /* ADC_CLKDIV - [7:5] */
+#define WM8400_ADC_CLKDIV_WIDTH                      3  /* ADC_CLKDIV - [7:5] */
+#define WM8400_DAC_CLKDIV_MASK                  0x001C  /* DAC_CLKDIV - [4:2] */
+#define WM8400_DAC_CLKDIV_SHIFT                      2  /* DAC_CLKDIV - [4:2] */
+#define WM8400_DAC_CLKDIV_WIDTH                      3  /* DAC_CLKDIV - [4:2] */
+
+/*
+ * R9 (0x09) - Audio Interface (3)
+ */
+#define WM8400_AIF_MSTR1                        0x8000  /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR1_MASK                   0x8000  /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR1_SHIFT                      15  /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR1_WIDTH                       1  /* AIF_MSTR1 */
+#define WM8400_AIF_MSTR2                        0x4000  /* AIF_MSTR2 */
+#define WM8400_AIF_MSTR2_MASK                   0x4000  /* AIF_MSTR2 */
+#define WM8400_AIF_MSTR2_SHIFT                      14  /* AIF_MSTR2 */
+#define WM8400_AIF_MSTR2_WIDTH                       1  /* AIF_MSTR2 */
+#define WM8400_AIF_SEL                          0x2000  /* AIF_SEL */
+#define WM8400_AIF_SEL_MASK                     0x2000  /* AIF_SEL */
+#define WM8400_AIF_SEL_SHIFT                        13  /* AIF_SEL */
+#define WM8400_AIF_SEL_WIDTH                         1  /* AIF_SEL */
+#define WM8400_ADCLRC_DIR                       0x0800  /* ADCLRC_DIR */
+#define WM8400_ADCLRC_DIR_MASK                  0x0800  /* ADCLRC_DIR */
+#define WM8400_ADCLRC_DIR_SHIFT                     11  /* ADCLRC_DIR */
+#define WM8400_ADCLRC_DIR_WIDTH                      1  /* ADCLRC_DIR */
+#define WM8400_ADCLRC_RATE_MASK                 0x07FF  /* ADCLRC_RATE - [10:0] */
+#define WM8400_ADCLRC_RATE_SHIFT                     0  /* ADCLRC_RATE - [10:0] */
+#define WM8400_ADCLRC_RATE_WIDTH                    11  /* ADCLRC_RATE - [10:0] */
+
+/*
+ * R10 (0x0A) - Audio Interface (4)
+ */
+#define WM8400_ALRCGPIO1                        0x8000  /* ALRCGPIO1 */
+#define WM8400_ALRCGPIO1_MASK                   0x8000  /* ALRCGPIO1 */
+#define WM8400_ALRCGPIO1_SHIFT                      15  /* ALRCGPIO1 */
+#define WM8400_ALRCGPIO1_WIDTH                       1  /* ALRCGPIO1 */
+#define WM8400_ALRCBGPIO6                       0x4000  /* ALRCBGPIO6 */
+#define WM8400_ALRCBGPIO6_MASK                  0x4000  /* ALRCBGPIO6 */
+#define WM8400_ALRCBGPIO6_SHIFT                     14  /* ALRCBGPIO6 */
+#define WM8400_ALRCBGPIO6_WIDTH                      1  /* ALRCBGPIO6 */
+#define WM8400_AIF_TRIS                         0x2000  /* AIF_TRIS */
+#define WM8400_AIF_TRIS_MASK                    0x2000  /* AIF_TRIS */
+#define WM8400_AIF_TRIS_SHIFT                       13  /* AIF_TRIS */
+#define WM8400_AIF_TRIS_WIDTH                        1  /* AIF_TRIS */
+#define WM8400_DACLRC_DIR                       0x0800  /* DACLRC_DIR */
+#define WM8400_DACLRC_DIR_MASK                  0x0800  /* DACLRC_DIR */
+#define WM8400_DACLRC_DIR_SHIFT                     11  /* DACLRC_DIR */
+#define WM8400_DACLRC_DIR_WIDTH                      1  /* DACLRC_DIR */
+#define WM8400_DACLRC_RATE_MASK                 0x07FF  /* DACLRC_RATE - [10:0] */
+#define WM8400_DACLRC_RATE_SHIFT                     0  /* DACLRC_RATE - [10:0] */
+#define WM8400_DACLRC_RATE_WIDTH                    11  /* DACLRC_RATE - [10:0] */
+
+/*
+ * R11 (0x0B) - DAC CTRL
+ */
+#define WM8400_DAC_SDMCLK_RATE                  0x2000  /* DAC_SDMCLK_RATE */
+#define WM8400_DAC_SDMCLK_RATE_MASK             0x2000  /* DAC_SDMCLK_RATE */
+#define WM8400_DAC_SDMCLK_RATE_SHIFT                13  /* DAC_SDMCLK_RATE */
+#define WM8400_DAC_SDMCLK_RATE_WIDTH                 1  /* DAC_SDMCLK_RATE */
+#define WM8400_AIF_LRCLKRATE                    0x0400  /* AIF_LRCLKRATE */
+#define WM8400_AIF_LRCLKRATE_MASK               0x0400  /* AIF_LRCLKRATE */
+#define WM8400_AIF_LRCLKRATE_SHIFT                  10  /* AIF_LRCLKRATE */
+#define WM8400_AIF_LRCLKRATE_WIDTH                   1  /* AIF_LRCLKRATE */
+#define WM8400_DAC_MONO                         0x0200  /* DAC_MONO */
+#define WM8400_DAC_MONO_MASK                    0x0200  /* DAC_MONO */
+#define WM8400_DAC_MONO_SHIFT                        9  /* DAC_MONO */
+#define WM8400_DAC_MONO_WIDTH                        1  /* DAC_MONO */
+#define WM8400_DAC_SB_FILT                      0x0100  /* DAC_SB_FILT */
+#define WM8400_DAC_SB_FILT_MASK                 0x0100  /* DAC_SB_FILT */
+#define WM8400_DAC_SB_FILT_SHIFT                     8  /* DAC_SB_FILT */
+#define WM8400_DAC_SB_FILT_WIDTH                     1  /* DAC_SB_FILT */
+#define WM8400_DAC_MUTERATE                     0x0080  /* DAC_MUTERATE */
+#define WM8400_DAC_MUTERATE_MASK                0x0080  /* DAC_MUTERATE */
+#define WM8400_DAC_MUTERATE_SHIFT                    7  /* DAC_MUTERATE */
+#define WM8400_DAC_MUTERATE_WIDTH                    1  /* DAC_MUTERATE */
+#define WM8400_DAC_MUTEMODE                     0x0040  /* DAC_MUTEMODE */
+#define WM8400_DAC_MUTEMODE_MASK                0x0040  /* DAC_MUTEMODE */
+#define WM8400_DAC_MUTEMODE_SHIFT                    6  /* DAC_MUTEMODE */
+#define WM8400_DAC_MUTEMODE_WIDTH                    1  /* DAC_MUTEMODE */
+#define WM8400_DEEMP_MASK                       0x0030  /* DEEMP - [5:4] */
+#define WM8400_DEEMP_SHIFT                           4  /* DEEMP - [5:4] */
+#define WM8400_DEEMP_WIDTH                           2  /* DEEMP - [5:4] */
+#define WM8400_DAC_MUTE                         0x0004  /* DAC_MUTE */
+#define WM8400_DAC_MUTE_MASK                    0x0004  /* DAC_MUTE */
+#define WM8400_DAC_MUTE_SHIFT                        2  /* DAC_MUTE */
+#define WM8400_DAC_MUTE_WIDTH                        1  /* DAC_MUTE */
+#define WM8400_DACL_DATINV                      0x0002  /* DACL_DATINV */
+#define WM8400_DACL_DATINV_MASK                 0x0002  /* DACL_DATINV */
+#define WM8400_DACL_DATINV_SHIFT                     1  /* DACL_DATINV */
+#define WM8400_DACL_DATINV_WIDTH                     1  /* DACL_DATINV */
+#define WM8400_DACR_DATINV                      0x0001  /* DACR_DATINV */
+#define WM8400_DACR_DATINV_MASK                 0x0001  /* DACR_DATINV */
+#define WM8400_DACR_DATINV_SHIFT                     0  /* DACR_DATINV */
+#define WM8400_DACR_DATINV_WIDTH                     1  /* DACR_DATINV */
+
+/*
+ * R12 (0x0C) - Left DAC Digital Volume
+ */
+#define WM8400_DAC_VU                           0x0100  /* DAC_VU */
+#define WM8400_DAC_VU_MASK                      0x0100  /* DAC_VU */
+#define WM8400_DAC_VU_SHIFT                          8  /* DAC_VU */
+#define WM8400_DAC_VU_WIDTH                          1  /* DAC_VU */
+#define WM8400_DACL_VOL_MASK                    0x00FF  /* DACL_VOL - [7:0] */
+#define WM8400_DACL_VOL_SHIFT                        0  /* DACL_VOL - [7:0] */
+#define WM8400_DACL_VOL_WIDTH                        8  /* DACL_VOL - [7:0] */
+
+/*
+ * R13 (0x0D) - Right DAC Digital Volume
+ */
+#define WM8400_DAC_VU                           0x0100  /* DAC_VU */
+#define WM8400_DAC_VU_MASK                      0x0100  /* DAC_VU */
+#define WM8400_DAC_VU_SHIFT                          8  /* DAC_VU */
+#define WM8400_DAC_VU_WIDTH                          1  /* DAC_VU */
+#define WM8400_DACR_VOL_MASK                    0x00FF  /* DACR_VOL - [7:0] */
+#define WM8400_DACR_VOL_SHIFT                        0  /* DACR_VOL - [7:0] */
+#define WM8400_DACR_VOL_WIDTH                        8  /* DACR_VOL - [7:0] */
+
+/*
+ * R14 (0x0E) - Digital Side Tone
+ */
+#define WM8400_ADCL_DAC_SVOL_MASK               0x1E00  /*   ADCL_DAC_SVOL - [12:9] */
+#define WM8400_ADCL_DAC_SVOL_SHIFT                   9  /*   ADCL_DAC_SVOL - [12:9] */
+#define WM8400_ADCL_DAC_SVOL_WIDTH                   4  /*   ADCL_DAC_SVOL - [12:9] */
+#define WM8400_ADCR_DAC_SVOL_MASK               0x01E0  /* ADCR_DAC_SVOL - [8:5] */
+#define WM8400_ADCR_DAC_SVOL_SHIFT                   5  /* ADCR_DAC_SVOL - [8:5] */
+#define WM8400_ADCR_DAC_SVOL_WIDTH                   4  /* ADCR_DAC_SVOL - [8:5] */
+#define WM8400_ADC_TO_DACL_MASK                 0x000C  /* ADC_TO_DACL - [3:2] */
+#define WM8400_ADC_TO_DACL_SHIFT                     2  /* ADC_TO_DACL - [3:2] */
+#define WM8400_ADC_TO_DACL_WIDTH                     2  /* ADC_TO_DACL - [3:2] */
+#define WM8400_ADC_TO_DACR_MASK                 0x0003  /* ADC_TO_DACR - [1:0] */
+#define WM8400_ADC_TO_DACR_SHIFT                     0  /* ADC_TO_DACR - [1:0] */
+#define WM8400_ADC_TO_DACR_WIDTH                     2  /* ADC_TO_DACR - [1:0] */
+
+/*
+ * R15 (0x0F) - ADC CTRL
+ */
+#define WM8400_ADC_HPF_ENA                      0x0100  /* ADC_HPF_ENA */
+#define WM8400_ADC_HPF_ENA_MASK                 0x0100  /* ADC_HPF_ENA */
+#define WM8400_ADC_HPF_ENA_SHIFT                     8  /* ADC_HPF_ENA */
+#define WM8400_ADC_HPF_ENA_WIDTH                     1  /* ADC_HPF_ENA */
+#define WM8400_ADC_HPF_CUT_MASK                 0x0060  /* ADC_HPF_CUT - [6:5] */
+#define WM8400_ADC_HPF_CUT_SHIFT                     5  /* ADC_HPF_CUT - [6:5] */
+#define WM8400_ADC_HPF_CUT_WIDTH                     2  /* ADC_HPF_CUT - [6:5] */
+#define WM8400_ADCL_DATINV                      0x0002  /* ADCL_DATINV */
+#define WM8400_ADCL_DATINV_MASK                 0x0002  /* ADCL_DATINV */
+#define WM8400_ADCL_DATINV_SHIFT                     1  /* ADCL_DATINV */
+#define WM8400_ADCL_DATINV_WIDTH                     1  /* ADCL_DATINV */
+#define WM8400_ADCR_DATINV                      0x0001  /* ADCR_DATINV */
+#define WM8400_ADCR_DATINV_MASK                 0x0001  /* ADCR_DATINV */
+#define WM8400_ADCR_DATINV_SHIFT                     0  /* ADCR_DATINV */
+#define WM8400_ADCR_DATINV_WIDTH                     1  /* ADCR_DATINV */
+
+/*
+ * R16 (0x10) - Left ADC Digital Volume
+ */
+#define WM8400_ADC_VU                           0x0100  /* ADC_VU */
+#define WM8400_ADC_VU_MASK                      0x0100  /* ADC_VU */
+#define WM8400_ADC_VU_SHIFT                          8  /* ADC_VU */
+#define WM8400_ADC_VU_WIDTH                          1  /* ADC_VU */
+#define WM8400_ADCL_VOL_MASK                    0x00FF  /* ADCL_VOL - [7:0] */
+#define WM8400_ADCL_VOL_SHIFT                        0  /* ADCL_VOL - [7:0] */
+#define WM8400_ADCL_VOL_WIDTH                        8  /* ADCL_VOL - [7:0] */
+
+/*
+ * R17 (0x11) - Right ADC Digital Volume
+ */
+#define WM8400_ADC_VU                           0x0100  /* ADC_VU */
+#define WM8400_ADC_VU_MASK                      0x0100  /* ADC_VU */
+#define WM8400_ADC_VU_SHIFT                          8  /* ADC_VU */
+#define WM8400_ADC_VU_WIDTH                          1  /* ADC_VU */
+#define WM8400_ADCR_VOL_MASK                    0x00FF  /* ADCR_VOL - [7:0] */
+#define WM8400_ADCR_VOL_SHIFT                        0  /* ADCR_VOL - [7:0] */
+#define WM8400_ADCR_VOL_WIDTH                        8  /* ADCR_VOL - [7:0] */
+
+/*
+ * R24 (0x18) - Left Line Input 1&2 Volume
+ */
+#define WM8400_IPVU                             0x0100  /* IPVU */
+#define WM8400_IPVU_MASK                        0x0100  /* IPVU */
+#define WM8400_IPVU_SHIFT                            8  /* IPVU */
+#define WM8400_IPVU_WIDTH                            1  /* IPVU */
+#define WM8400_LI12MUTE                         0x0080  /* LI12MUTE */
+#define WM8400_LI12MUTE_MASK                    0x0080  /* LI12MUTE */
+#define WM8400_LI12MUTE_SHIFT                        7  /* LI12MUTE */
+#define WM8400_LI12MUTE_WIDTH                        1  /* LI12MUTE */
+#define WM8400_LI12ZC                           0x0040  /* LI12ZC */
+#define WM8400_LI12ZC_MASK                      0x0040  /* LI12ZC */
+#define WM8400_LI12ZC_SHIFT                          6  /* LI12ZC */
+#define WM8400_LI12ZC_WIDTH                          1  /* LI12ZC */
+#define WM8400_LIN12VOL_MASK                    0x001F  /* LIN12VOL - [4:0] */
+#define WM8400_LIN12VOL_SHIFT                        0  /* LIN12VOL - [4:0] */
+#define WM8400_LIN12VOL_WIDTH                        5  /* LIN12VOL - [4:0] */
+
+/*
+ * R25 (0x19) - Left Line Input 3&4 Volume
+ */
+#define WM8400_IPVU                             0x0100  /* IPVU */
+#define WM8400_IPVU_MASK                        0x0100  /* IPVU */
+#define WM8400_IPVU_SHIFT                            8  /* IPVU */
+#define WM8400_IPVU_WIDTH                            1  /* IPVU */
+#define WM8400_LI34MUTE                         0x0080  /* LI34MUTE */
+#define WM8400_LI34MUTE_MASK                    0x0080  /* LI34MUTE */
+#define WM8400_LI34MUTE_SHIFT                        7  /* LI34MUTE */
+#define WM8400_LI34MUTE_WIDTH                        1  /* LI34MUTE */
+#define WM8400_LI34ZC                           0x0040  /* LI34ZC */
+#define WM8400_LI34ZC_MASK                      0x0040  /* LI34ZC */
+#define WM8400_LI34ZC_SHIFT                          6  /* LI34ZC */
+#define WM8400_LI34ZC_WIDTH                          1  /* LI34ZC */
+#define WM8400_LIN34VOL_MASK                    0x001F  /* LIN34VOL - [4:0] */
+#define WM8400_LIN34VOL_SHIFT                        0  /* LIN34VOL - [4:0] */
+#define WM8400_LIN34VOL_WIDTH                        5  /* LIN34VOL - [4:0] */
+
+/*
+ * R26 (0x1A) - Right Line Input 1&2 Volume
+ */
+#define WM8400_IPVU                             0x0100  /* IPVU */
+#define WM8400_IPVU_MASK                        0x0100  /* IPVU */
+#define WM8400_IPVU_SHIFT                            8  /* IPVU */
+#define WM8400_IPVU_WIDTH                            1  /* IPVU */
+#define WM8400_RI12MUTE                         0x0080  /* RI12MUTE */
+#define WM8400_RI12MUTE_MASK                    0x0080  /* RI12MUTE */
+#define WM8400_RI12MUTE_SHIFT                        7  /* RI12MUTE */
+#define WM8400_RI12MUTE_WIDTH                        1  /* RI12MUTE */
+#define WM8400_RI12ZC                           0x0040  /* RI12ZC */
+#define WM8400_RI12ZC_MASK                      0x0040  /* RI12ZC */
+#define WM8400_RI12ZC_SHIFT                          6  /* RI12ZC */
+#define WM8400_RI12ZC_WIDTH                          1  /* RI12ZC */
+#define WM8400_RIN12VOL_MASK                    0x001F  /* RIN12VOL - [4:0] */
+#define WM8400_RIN12VOL_SHIFT                        0  /* RIN12VOL - [4:0] */
+#define WM8400_RIN12VOL_WIDTH                        5  /* RIN12VOL - [4:0] */
+
+/*
+ * R27 (0x1B) - Right Line Input 3&4 Volume
+ */
+#define WM8400_IPVU                             0x0100  /* IPVU */
+#define WM8400_IPVU_MASK                        0x0100  /* IPVU */
+#define WM8400_IPVU_SHIFT                            8  /* IPVU */
+#define WM8400_IPVU_WIDTH                            1  /* IPVU */
+#define WM8400_RI34MUTE                         0x0080  /* RI34MUTE */
+#define WM8400_RI34MUTE_MASK                    0x0080  /* RI34MUTE */
+#define WM8400_RI34MUTE_SHIFT                        7  /* RI34MUTE */
+#define WM8400_RI34MUTE_WIDTH                        1  /* RI34MUTE */
+#define WM8400_RI34ZC                           0x0040  /* RI34ZC */
+#define WM8400_RI34ZC_MASK                      0x0040  /* RI34ZC */
+#define WM8400_RI34ZC_SHIFT                          6  /* RI34ZC */
+#define WM8400_RI34ZC_WIDTH                          1  /* RI34ZC */
+#define WM8400_RIN34VOL_MASK                    0x001F  /* RIN34VOL - [4:0] */
+#define WM8400_RIN34VOL_SHIFT                        0  /* RIN34VOL - [4:0] */
+#define WM8400_RIN34VOL_WIDTH                        5  /* RIN34VOL - [4:0] */
+
+/*
+ * R28 (0x1C) - Left Output Volume
+ */
+#define WM8400_OPVU                             0x0100  /* OPVU */
+#define WM8400_OPVU_MASK                        0x0100  /* OPVU */
+#define WM8400_OPVU_SHIFT                            8  /* OPVU */
+#define WM8400_OPVU_WIDTH                            1  /* OPVU */
+#define WM8400_LOZC                             0x0080  /* LOZC */
+#define WM8400_LOZC_MASK                        0x0080  /* LOZC */
+#define WM8400_LOZC_SHIFT                            7  /* LOZC */
+#define WM8400_LOZC_WIDTH                            1  /* LOZC */
+#define WM8400_LOUTVOL_MASK                     0x007F  /* LOUTVOL - [6:0] */
+#define WM8400_LOUTVOL_SHIFT                         0  /* LOUTVOL - [6:0] */
+#define WM8400_LOUTVOL_WIDTH                         7  /* LOUTVOL - [6:0] */
+
+/*
+ * R29 (0x1D) - Right Output Volume
+ */
+#define WM8400_OPVU                             0x0100  /* OPVU */
+#define WM8400_OPVU_MASK                        0x0100  /* OPVU */
+#define WM8400_OPVU_SHIFT                            8  /* OPVU */
+#define WM8400_OPVU_WIDTH                            1  /* OPVU */
+#define WM8400_ROZC                             0x0080  /* ROZC */
+#define WM8400_ROZC_MASK                        0x0080  /* ROZC */
+#define WM8400_ROZC_SHIFT                            7  /* ROZC */
+#define WM8400_ROZC_WIDTH                            1  /* ROZC */
+#define WM8400_ROUTVOL_MASK                     0x007F  /* ROUTVOL - [6:0] */
+#define WM8400_ROUTVOL_SHIFT                         0  /* ROUTVOL - [6:0] */
+#define WM8400_ROUTVOL_WIDTH                         7  /* ROUTVOL - [6:0] */
+
+/*
+ * R30 (0x1E) - Line Outputs Volume
+ */
+#define WM8400_LONMUTE                          0x0040  /* LONMUTE */
+#define WM8400_LONMUTE_MASK                     0x0040  /* LONMUTE */
+#define WM8400_LONMUTE_SHIFT                         6  /* LONMUTE */
+#define WM8400_LONMUTE_WIDTH                         1  /* LONMUTE */
+#define WM8400_LOPMUTE                          0x0020  /* LOPMUTE */
+#define WM8400_LOPMUTE_MASK                     0x0020  /* LOPMUTE */
+#define WM8400_LOPMUTE_SHIFT                         5  /* LOPMUTE */
+#define WM8400_LOPMUTE_WIDTH                         1  /* LOPMUTE */
+#define WM8400_LOATTN                           0x0010  /* LOATTN */
+#define WM8400_LOATTN_MASK                      0x0010  /* LOATTN */
+#define WM8400_LOATTN_SHIFT                          4  /* LOATTN */
+#define WM8400_LOATTN_WIDTH                          1  /* LOATTN */
+#define WM8400_RONMUTE                          0x0004  /* RONMUTE */
+#define WM8400_RONMUTE_MASK                     0x0004  /* RONMUTE */
+#define WM8400_RONMUTE_SHIFT                         2  /* RONMUTE */
+#define WM8400_RONMUTE_WIDTH                         1  /* RONMUTE */
+#define WM8400_ROPMUTE                          0x0002  /* ROPMUTE */
+#define WM8400_ROPMUTE_MASK                     0x0002  /* ROPMUTE */
+#define WM8400_ROPMUTE_SHIFT                         1  /* ROPMUTE */
+#define WM8400_ROPMUTE_WIDTH                         1  /* ROPMUTE */
+#define WM8400_ROATTN                           0x0001  /* ROATTN */
+#define WM8400_ROATTN_MASK                      0x0001  /* ROATTN */
+#define WM8400_ROATTN_SHIFT                          0  /* ROATTN */
+#define WM8400_ROATTN_WIDTH                          1  /* ROATTN */
+
+/*
+ * R31 (0x1F) - Out3/4 Volume
+ */
+#define WM8400_OUT3MUTE                         0x0020  /* OUT3MUTE */
+#define WM8400_OUT3MUTE_MASK                    0x0020  /* OUT3MUTE */
+#define WM8400_OUT3MUTE_SHIFT                        5  /* OUT3MUTE */
+#define WM8400_OUT3MUTE_WIDTH                        1  /* OUT3MUTE */
+#define WM8400_OUT3ATTN                         0x0010  /* OUT3ATTN */
+#define WM8400_OUT3ATTN_MASK                    0x0010  /* OUT3ATTN */
+#define WM8400_OUT3ATTN_SHIFT                        4  /* OUT3ATTN */
+#define WM8400_OUT3ATTN_WIDTH                        1  /* OUT3ATTN */
+#define WM8400_OUT4MUTE                         0x0002  /* OUT4MUTE */
+#define WM8400_OUT4MUTE_MASK                    0x0002  /* OUT4MUTE */
+#define WM8400_OUT4MUTE_SHIFT                        1  /* OUT4MUTE */
+#define WM8400_OUT4MUTE_WIDTH                        1  /* OUT4MUTE */
+#define WM8400_OUT4ATTN                         0x0001  /* OUT4ATTN */
+#define WM8400_OUT4ATTN_MASK                    0x0001  /* OUT4ATTN */
+#define WM8400_OUT4ATTN_SHIFT                        0  /* OUT4ATTN */
+#define WM8400_OUT4ATTN_WIDTH                        1  /* OUT4ATTN */
+
+/*
+ * R32 (0x20) - Left OPGA Volume
+ */
+#define WM8400_OPVU                             0x0100  /* OPVU */
+#define WM8400_OPVU_MASK                        0x0100  /* OPVU */
+#define WM8400_OPVU_SHIFT                            8  /* OPVU */
+#define WM8400_OPVU_WIDTH                            1  /* OPVU */
+#define WM8400_LOPGAZC                          0x0080  /* LOPGAZC */
+#define WM8400_LOPGAZC_MASK                     0x0080  /* LOPGAZC */
+#define WM8400_LOPGAZC_SHIFT                         7  /* LOPGAZC */
+#define WM8400_LOPGAZC_WIDTH                         1  /* LOPGAZC */
+#define WM8400_LOPGAVOL_MASK                    0x007F  /* LOPGAVOL - [6:0] */
+#define WM8400_LOPGAVOL_SHIFT                        0  /* LOPGAVOL - [6:0] */
+#define WM8400_LOPGAVOL_WIDTH                        7  /* LOPGAVOL - [6:0] */
+
+/*
+ * R33 (0x21) - Right OPGA Volume
+ */
+#define WM8400_OPVU                             0x0100  /* OPVU */
+#define WM8400_OPVU_MASK                        0x0100  /* OPVU */
+#define WM8400_OPVU_SHIFT                            8  /* OPVU */
+#define WM8400_OPVU_WIDTH                            1  /* OPVU */
+#define WM8400_ROPGAZC                          0x0080  /* ROPGAZC */
+#define WM8400_ROPGAZC_MASK                     0x0080  /* ROPGAZC */
+#define WM8400_ROPGAZC_SHIFT                         7  /* ROPGAZC */
+#define WM8400_ROPGAZC_WIDTH                         1  /* ROPGAZC */
+#define WM8400_ROPGAVOL_MASK                    0x007F  /* ROPGAVOL - [6:0] */
+#define WM8400_ROPGAVOL_SHIFT                        0  /* ROPGAVOL - [6:0] */
+#define WM8400_ROPGAVOL_WIDTH                        7  /* ROPGAVOL - [6:0] */
+
+/*
+ * R34 (0x22) - Speaker Volume
+ */
+#define WM8400_SPKATTN_MASK                     0x0003  /* SPKATTN - [1:0] */
+#define WM8400_SPKATTN_SHIFT                         0  /* SPKATTN - [1:0] */
+#define WM8400_SPKATTN_WIDTH                         2  /* SPKATTN - [1:0] */
+
+/*
+ * R35 (0x23) - ClassD1
+ */
+#define WM8400_CDMODE                           0x0100  /* CDMODE */
+#define WM8400_CDMODE_MASK                      0x0100  /* CDMODE */
+#define WM8400_CDMODE_SHIFT                          8  /* CDMODE */
+#define WM8400_CDMODE_WIDTH                          1  /* CDMODE */
+#define WM8400_CLASSD_CLK_SEL                   0x0080  /* CLASSD_CLK_SEL */
+#define WM8400_CLASSD_CLK_SEL_MASK              0x0080  /* CLASSD_CLK_SEL */
+#define WM8400_CLASSD_CLK_SEL_SHIFT                  7  /* CLASSD_CLK_SEL */
+#define WM8400_CLASSD_CLK_SEL_WIDTH                  1  /* CLASSD_CLK_SEL */
+#define WM8400_CD_SRCTRL                        0x0040  /* CD_SRCTRL */
+#define WM8400_CD_SRCTRL_MASK                   0x0040  /* CD_SRCTRL */
+#define WM8400_CD_SRCTRL_SHIFT                       6  /* CD_SRCTRL */
+#define WM8400_CD_SRCTRL_WIDTH                       1  /* CD_SRCTRL */
+#define WM8400_SPKNOPOP                         0x0020  /* SPKNOPOP */
+#define WM8400_SPKNOPOP_MASK                    0x0020  /* SPKNOPOP */
+#define WM8400_SPKNOPOP_SHIFT                        5  /* SPKNOPOP */
+#define WM8400_SPKNOPOP_WIDTH                        1  /* SPKNOPOP */
+#define WM8400_DBLERATE                         0x0010  /* DBLERATE */
+#define WM8400_DBLERATE_MASK                    0x0010  /* DBLERATE */
+#define WM8400_DBLERATE_SHIFT                        4  /* DBLERATE */
+#define WM8400_DBLERATE_WIDTH                        1  /* DBLERATE */
+#define WM8400_LOOPTEST                         0x0008  /* LOOPTEST */
+#define WM8400_LOOPTEST_MASK                    0x0008  /* LOOPTEST */
+#define WM8400_LOOPTEST_SHIFT                        3  /* LOOPTEST */
+#define WM8400_LOOPTEST_WIDTH                        1  /* LOOPTEST */
+#define WM8400_HALFABBIAS                       0x0004  /* HALFABBIAS */
+#define WM8400_HALFABBIAS_MASK                  0x0004  /* HALFABBIAS */
+#define WM8400_HALFABBIAS_SHIFT                      2  /* HALFABBIAS */
+#define WM8400_HALFABBIAS_WIDTH                      1  /* HALFABBIAS */
+#define WM8400_TRIDEL_MASK                      0x0003  /* TRIDEL - [1:0] */
+#define WM8400_TRIDEL_SHIFT                          0  /* TRIDEL - [1:0] */
+#define WM8400_TRIDEL_WIDTH                          2  /* TRIDEL - [1:0] */
+
+/*
+ * R37 (0x25) - ClassD3
+ */
+#define WM8400_DCGAIN_MASK                      0x0038  /* DCGAIN - [5:3] */
+#define WM8400_DCGAIN_SHIFT                          3  /* DCGAIN - [5:3] */
+#define WM8400_DCGAIN_WIDTH                          3  /* DCGAIN - [5:3] */
+#define WM8400_ACGAIN_MASK                      0x0007  /* ACGAIN - [2:0] */
+#define WM8400_ACGAIN_SHIFT                          0  /* ACGAIN - [2:0] */
+#define WM8400_ACGAIN_WIDTH                          3  /* ACGAIN - [2:0] */
+
+/*
+ * R39 (0x27) - Input Mixer1
+ */
+#define WM8400_AINLMODE_MASK                    0x000C  /* AINLMODE - [3:2] */
+#define WM8400_AINLMODE_SHIFT                        2  /* AINLMODE - [3:2] */
+#define WM8400_AINLMODE_WIDTH                        2  /* AINLMODE - [3:2] */
+#define WM8400_AINRMODE_MASK                    0x0003  /* AINRMODE - [1:0] */
+#define WM8400_AINRMODE_SHIFT                        0  /* AINRMODE - [1:0] */
+#define WM8400_AINRMODE_WIDTH                        2  /* AINRMODE - [1:0] */
+
+/*
+ * R40 (0x28) - Input Mixer2
+ */
+#define WM8400_LMP4                             0x0080  /* LMP4 */
+#define WM8400_LMP4_MASK                        0x0080  /* LMP4 */
+#define WM8400_LMP4_SHIFT                            7  /* LMP4 */
+#define WM8400_LMP4_WIDTH                            1  /* LMP4 */
+#define WM8400_LMN3                             0x0040  /* LMN3 */
+#define WM8400_LMN3_MASK                        0x0040  /* LMN3 */
+#define WM8400_LMN3_SHIFT                            6  /* LMN3 */
+#define WM8400_LMN3_WIDTH                            1  /* LMN3 */
+#define WM8400_LMP2                             0x0020  /* LMP2 */
+#define WM8400_LMP2_MASK                        0x0020  /* LMP2 */
+#define WM8400_LMP2_SHIFT                            5  /* LMP2 */
+#define WM8400_LMP2_WIDTH                            1  /* LMP2 */
+#define WM8400_LMN1                             0x0010  /* LMN1 */
+#define WM8400_LMN1_MASK                        0x0010  /* LMN1 */
+#define WM8400_LMN1_SHIFT                            4  /* LMN1 */
+#define WM8400_LMN1_WIDTH                            1  /* LMN1 */
+#define WM8400_RMP4                             0x0008  /* RMP4 */
+#define WM8400_RMP4_MASK                        0x0008  /* RMP4 */
+#define WM8400_RMP4_SHIFT                            3  /* RMP4 */
+#define WM8400_RMP4_WIDTH                            1  /* RMP4 */
+#define WM8400_RMN3                             0x0004  /* RMN3 */
+#define WM8400_RMN3_MASK                        0x0004  /* RMN3 */
+#define WM8400_RMN3_SHIFT                            2  /* RMN3 */
+#define WM8400_RMN3_WIDTH                            1  /* RMN3 */
+#define WM8400_RMP2                             0x0002  /* RMP2 */
+#define WM8400_RMP2_MASK                        0x0002  /* RMP2 */
+#define WM8400_RMP2_SHIFT                            1  /* RMP2 */
+#define WM8400_RMP2_WIDTH                            1  /* RMP2 */
+#define WM8400_RMN1                             0x0001  /* RMN1 */
+#define WM8400_RMN1_MASK                        0x0001  /* RMN1 */
+#define WM8400_RMN1_SHIFT                            0  /* RMN1 */
+#define WM8400_RMN1_WIDTH                            1  /* RMN1 */
+
+/*
+ * R41 (0x29) - Input Mixer3
+ */
+#define WM8400_L34MNB                           0x0100  /* L34MNB */
+#define WM8400_L34MNB_MASK                      0x0100  /* L34MNB */
+#define WM8400_L34MNB_SHIFT                          8  /* L34MNB */
+#define WM8400_L34MNB_WIDTH                          1  /* L34MNB */
+#define WM8400_L34MNBST                         0x0080  /* L34MNBST */
+#define WM8400_L34MNBST_MASK                    0x0080  /* L34MNBST */
+#define WM8400_L34MNBST_SHIFT                        7  /* L34MNBST */
+#define WM8400_L34MNBST_WIDTH                        1  /* L34MNBST */
+#define WM8400_L12MNB                           0x0020  /* L12MNB */
+#define WM8400_L12MNB_MASK                      0x0020  /* L12MNB */
+#define WM8400_L12MNB_SHIFT                          5  /* L12MNB */
+#define WM8400_L12MNB_WIDTH                          1  /* L12MNB */
+#define WM8400_L12MNBST                         0x0010  /* L12MNBST */
+#define WM8400_L12MNBST_MASK                    0x0010  /* L12MNBST */
+#define WM8400_L12MNBST_SHIFT                        4  /* L12MNBST */
+#define WM8400_L12MNBST_WIDTH                        1  /* L12MNBST */
+#define WM8400_LDBVOL_MASK                      0x0007  /* LDBVOL - [2:0] */
+#define WM8400_LDBVOL_SHIFT                          0  /* LDBVOL - [2:0] */
+#define WM8400_LDBVOL_WIDTH                          3  /* LDBVOL - [2:0] */
+
+/*
+ * R42 (0x2A) - Input Mixer4
+ */
+#define WM8400_R34MNB                           0x0100  /* R34MNB */
+#define WM8400_R34MNB_MASK                      0x0100  /* R34MNB */
+#define WM8400_R34MNB_SHIFT                          8  /* R34MNB */
+#define WM8400_R34MNB_WIDTH                          1  /* R34MNB */
+#define WM8400_R34MNBST                         0x0080  /* R34MNBST */
+#define WM8400_R34MNBST_MASK                    0x0080  /* R34MNBST */
+#define WM8400_R34MNBST_SHIFT                        7  /* R34MNBST */
+#define WM8400_R34MNBST_WIDTH                        1  /* R34MNBST */
+#define WM8400_R12MNB                           0x0020  /* R12MNB */
+#define WM8400_R12MNB_MASK                      0x0020  /* R12MNB */
+#define WM8400_R12MNB_SHIFT                          5  /* R12MNB */
+#define WM8400_R12MNB_WIDTH                          1  /* R12MNB */
+#define WM8400_R12MNBST                         0x0010  /* R12MNBST */
+#define WM8400_R12MNBST_MASK                    0x0010  /* R12MNBST */
+#define WM8400_R12MNBST_SHIFT                        4  /* R12MNBST */
+#define WM8400_R12MNBST_WIDTH                        1  /* R12MNBST */
+#define WM8400_RDBVOL_MASK                      0x0007  /* RDBVOL - [2:0] */
+#define WM8400_RDBVOL_SHIFT                          0  /* RDBVOL - [2:0] */
+#define WM8400_RDBVOL_WIDTH                          3  /* RDBVOL - [2:0] */
+
+/*
+ * R43 (0x2B) - Input Mixer5
+ */
+#define WM8400_LI2BVOL_MASK                     0x01C0  /* LI2BVOL - [8:6] */
+#define WM8400_LI2BVOL_SHIFT                         6  /* LI2BVOL - [8:6] */
+#define WM8400_LI2BVOL_WIDTH                         3  /* LI2BVOL - [8:6] */
+#define WM8400_LR4BVOL_MASK                     0x0038  /* LR4BVOL - [5:3] */
+#define WM8400_LR4BVOL_SHIFT                         3  /* LR4BVOL - [5:3] */
+#define WM8400_LR4BVOL_WIDTH                         3  /* LR4BVOL - [5:3] */
+#define WM8400_LL4BVOL_MASK                     0x0007  /* LL4BVOL - [2:0] */
+#define WM8400_LL4BVOL_SHIFT                         0  /* LL4BVOL - [2:0] */
+#define WM8400_LL4BVOL_WIDTH                         3  /* LL4BVOL - [2:0] */
+
+/*
+ * R44 (0x2C) - Input Mixer6
+ */
+#define WM8400_RI2BVOL_MASK                     0x01C0  /* RI2BVOL - [8:6] */
+#define WM8400_RI2BVOL_SHIFT                         6  /* RI2BVOL - [8:6] */
+#define WM8400_RI2BVOL_WIDTH                         3  /* RI2BVOL - [8:6] */
+#define WM8400_RL4BVOL_MASK                     0x0038  /* RL4BVOL - [5:3] */
+#define WM8400_RL4BVOL_SHIFT                         3  /* RL4BVOL - [5:3] */
+#define WM8400_RL4BVOL_WIDTH                         3  /* RL4BVOL - [5:3] */
+#define WM8400_RR4BVOL_MASK                     0x0007  /* RR4BVOL - [2:0] */
+#define WM8400_RR4BVOL_SHIFT                         0  /* RR4BVOL - [2:0] */
+#define WM8400_RR4BVOL_WIDTH                         3  /* RR4BVOL - [2:0] */
+
+/*
+ * R45 (0x2D) - Output Mixer1
+ */
+#define WM8400_LRBLO                            0x0080  /* LRBLO */
+#define WM8400_LRBLO_MASK                       0x0080  /* LRBLO */
+#define WM8400_LRBLO_SHIFT                           7  /* LRBLO */
+#define WM8400_LRBLO_WIDTH                           1  /* LRBLO */
+#define WM8400_LLBLO                            0x0040  /* LLBLO */
+#define WM8400_LLBLO_MASK                       0x0040  /* LLBLO */
+#define WM8400_LLBLO_SHIFT                           6  /* LLBLO */
+#define WM8400_LLBLO_WIDTH                           1  /* LLBLO */
+#define WM8400_LRI3LO                           0x0020  /* LRI3LO */
+#define WM8400_LRI3LO_MASK                      0x0020  /* LRI3LO */
+#define WM8400_LRI3LO_SHIFT                          5  /* LRI3LO */
+#define WM8400_LRI3LO_WIDTH                          1  /* LRI3LO */
+#define WM8400_LLI3LO                           0x0010  /* LLI3LO */
+#define WM8400_LLI3LO_MASK                      0x0010  /* LLI3LO */
+#define WM8400_LLI3LO_SHIFT                          4  /* LLI3LO */
+#define WM8400_LLI3LO_WIDTH                          1  /* LLI3LO */
+#define WM8400_LR12LO                           0x0008  /* LR12LO */
+#define WM8400_LR12LO_MASK                      0x0008  /* LR12LO */
+#define WM8400_LR12LO_SHIFT                          3  /* LR12LO */
+#define WM8400_LR12LO_WIDTH                          1  /* LR12LO */
+#define WM8400_LL12LO                           0x0004  /* LL12LO */
+#define WM8400_LL12LO_MASK                      0x0004  /* LL12LO */
+#define WM8400_LL12LO_SHIFT                          2  /* LL12LO */
+#define WM8400_LL12LO_WIDTH                          1  /* LL12LO */
+#define WM8400_LDLO                             0x0001  /* LDLO */
+#define WM8400_LDLO_MASK                        0x0001  /* LDLO */
+#define WM8400_LDLO_SHIFT                            0  /* LDLO */
+#define WM8400_LDLO_WIDTH                            1  /* LDLO */
+
+/*
+ * R46 (0x2E) - Output Mixer2
+ */
+#define WM8400_RLBRO                            0x0080  /* RLBRO */
+#define WM8400_RLBRO_MASK                       0x0080  /* RLBRO */
+#define WM8400_RLBRO_SHIFT                           7  /* RLBRO */
+#define WM8400_RLBRO_WIDTH                           1  /* RLBRO */
+#define WM8400_RRBRO                            0x0040  /* RRBRO */
+#define WM8400_RRBRO_MASK                       0x0040  /* RRBRO */
+#define WM8400_RRBRO_SHIFT                           6  /* RRBRO */
+#define WM8400_RRBRO_WIDTH                           1  /* RRBRO */
+#define WM8400_RLI3RO                           0x0020  /* RLI3RO */
+#define WM8400_RLI3RO_MASK                      0x0020  /* RLI3RO */
+#define WM8400_RLI3RO_SHIFT                          5  /* RLI3RO */
+#define WM8400_RLI3RO_WIDTH                          1  /* RLI3RO */
+#define WM8400_RRI3RO                           0x0010  /* RRI3RO */
+#define WM8400_RRI3RO_MASK                      0x0010  /* RRI3RO */
+#define WM8400_RRI3RO_SHIFT                          4  /* RRI3RO */
+#define WM8400_RRI3RO_WIDTH                          1  /* RRI3RO */
+#define WM8400_RL12RO                           0x0008  /* RL12RO */
+#define WM8400_RL12RO_MASK                      0x0008  /* RL12RO */
+#define WM8400_RL12RO_SHIFT                          3  /* RL12RO */
+#define WM8400_RL12RO_WIDTH                          1  /* RL12RO */
+#define WM8400_RR12RO                           0x0004  /* RR12RO */
+#define WM8400_RR12RO_MASK                      0x0004  /* RR12RO */
+#define WM8400_RR12RO_SHIFT                          2  /* RR12RO */
+#define WM8400_RR12RO_WIDTH                          1  /* RR12RO */
+#define WM8400_RDRO                             0x0001  /* RDRO */
+#define WM8400_RDRO_MASK                        0x0001  /* RDRO */
+#define WM8400_RDRO_SHIFT                            0  /* RDRO */
+#define WM8400_RDRO_WIDTH                            1  /* RDRO */
+
+/*
+ * R47 (0x2F) - Output Mixer3
+ */
+#define WM8400_LLI3LOVOL_MASK                   0x01C0  /* LLI3LOVOL - [8:6] */
+#define WM8400_LLI3LOVOL_SHIFT                       6  /* LLI3LOVOL - [8:6] */
+#define WM8400_LLI3LOVOL_WIDTH                       3  /* LLI3LOVOL - [8:6] */
+#define WM8400_LR12LOVOL_MASK                   0x0038  /* LR12LOVOL - [5:3] */
+#define WM8400_LR12LOVOL_SHIFT                       3  /* LR12LOVOL - [5:3] */
+#define WM8400_LR12LOVOL_WIDTH                       3  /* LR12LOVOL - [5:3] */
+#define WM8400_LL12LOVOL_MASK                   0x0007  /* LL12LOVOL - [2:0] */
+#define WM8400_LL12LOVOL_SHIFT                       0  /* LL12LOVOL - [2:0] */
+#define WM8400_LL12LOVOL_WIDTH                       3  /* LL12LOVOL - [2:0] */
+
+/*
+ * R48 (0x30) - Output Mixer4
+ */
+#define WM8400_RRI3ROVOL_MASK                   0x01C0  /* RRI3ROVOL - [8:6] */
+#define WM8400_RRI3ROVOL_SHIFT                       6  /* RRI3ROVOL - [8:6] */
+#define WM8400_RRI3ROVOL_WIDTH                       3  /* RRI3ROVOL - [8:6] */
+#define WM8400_RL12ROVOL_MASK                   0x0038  /* RL12ROVOL - [5:3] */
+#define WM8400_RL12ROVOL_SHIFT                       3  /* RL12ROVOL - [5:3] */
+#define WM8400_RL12ROVOL_WIDTH                       3  /* RL12ROVOL - [5:3] */
+#define WM8400_RR12ROVOL_MASK                   0x0007  /* RR12ROVOL - [2:0] */
+#define WM8400_RR12ROVOL_SHIFT                       0  /* RR12ROVOL - [2:0] */
+#define WM8400_RR12ROVOL_WIDTH                       3  /* RR12ROVOL - [2:0] */
+
+/*
+ * R49 (0x31) - Output Mixer5
+ */
+#define WM8400_LRI3LOVOL_MASK                   0x01C0  /* LRI3LOVOL - [8:6] */
+#define WM8400_LRI3LOVOL_SHIFT                       6  /* LRI3LOVOL - [8:6] */
+#define WM8400_LRI3LOVOL_WIDTH                       3  /* LRI3LOVOL - [8:6] */
+#define WM8400_LRBLOVOL_MASK                    0x0038  /* LRBLOVOL - [5:3] */
+#define WM8400_LRBLOVOL_SHIFT                        3  /* LRBLOVOL - [5:3] */
+#define WM8400_LRBLOVOL_WIDTH                        3  /* LRBLOVOL - [5:3] */
+#define WM8400_LLBLOVOL_MASK                    0x0007  /* LLBLOVOL - [2:0] */
+#define WM8400_LLBLOVOL_SHIFT                        0  /* LLBLOVOL - [2:0] */
+#define WM8400_LLBLOVOL_WIDTH                        3  /* LLBLOVOL - [2:0] */
+
+/*
+ * R50 (0x32) - Output Mixer6
+ */
+#define WM8400_RLI3ROVOL_MASK                   0x01C0  /* RLI3ROVOL - [8:6] */
+#define WM8400_RLI3ROVOL_SHIFT                       6  /* RLI3ROVOL - [8:6] */
+#define WM8400_RLI3ROVOL_WIDTH                       3  /* RLI3ROVOL - [8:6] */
+#define WM8400_RLBROVOL_MASK                    0x0038  /* RLBROVOL - [5:3] */
+#define WM8400_RLBROVOL_SHIFT                        3  /* RLBROVOL - [5:3] */
+#define WM8400_RLBROVOL_WIDTH                        3  /* RLBROVOL - [5:3] */
+#define WM8400_RRBROVOL_MASK                    0x0007  /* RRBROVOL - [2:0] */
+#define WM8400_RRBROVOL_SHIFT                        0  /* RRBROVOL - [2:0] */
+#define WM8400_RRBROVOL_WIDTH                        3  /* RRBROVOL - [2:0] */
+
+/*
+ * R51 (0x33) - Out3/4 Mixer
+ */
+#define WM8400_VSEL_MASK                        0x0180  /* VSEL - [8:7] */
+#define WM8400_VSEL_SHIFT                            7  /* VSEL - [8:7] */
+#define WM8400_VSEL_WIDTH                            2  /* VSEL - [8:7] */
+#define WM8400_LI4O3                            0x0020  /* LI4O3 */
+#define WM8400_LI4O3_MASK                       0x0020  /* LI4O3 */
+#define WM8400_LI4O3_SHIFT                           5  /* LI4O3 */
+#define WM8400_LI4O3_WIDTH                           1  /* LI4O3 */
+#define WM8400_LPGAO3                           0x0010  /* LPGAO3 */
+#define WM8400_LPGAO3_MASK                      0x0010  /* LPGAO3 */
+#define WM8400_LPGAO3_SHIFT                          4  /* LPGAO3 */
+#define WM8400_LPGAO3_WIDTH                          1  /* LPGAO3 */
+#define WM8400_RI4O4                            0x0002  /* RI4O4 */
+#define WM8400_RI4O4_MASK                       0x0002  /* RI4O4 */
+#define WM8400_RI4O4_SHIFT                           1  /* RI4O4 */
+#define WM8400_RI4O4_WIDTH                           1  /* RI4O4 */
+#define WM8400_RPGAO4                           0x0001  /* RPGAO4 */
+#define WM8400_RPGAO4_MASK                      0x0001  /* RPGAO4 */
+#define WM8400_RPGAO4_SHIFT                          0  /* RPGAO4 */
+#define WM8400_RPGAO4_WIDTH                          1  /* RPGAO4 */
+
+/*
+ * R52 (0x34) - Line Mixer1
+ */
+#define WM8400_LLOPGALON                        0x0040  /* LLOPGALON */
+#define WM8400_LLOPGALON_MASK                   0x0040  /* LLOPGALON */
+#define WM8400_LLOPGALON_SHIFT                       6  /* LLOPGALON */
+#define WM8400_LLOPGALON_WIDTH                       1  /* LLOPGALON */
+#define WM8400_LROPGALON                        0x0020  /* LROPGALON */
+#define WM8400_LROPGALON_MASK                   0x0020  /* LROPGALON */
+#define WM8400_LROPGALON_SHIFT                       5  /* LROPGALON */
+#define WM8400_LROPGALON_WIDTH                       1  /* LROPGALON */
+#define WM8400_LOPLON                           0x0010  /* LOPLON */
+#define WM8400_LOPLON_MASK                      0x0010  /* LOPLON */
+#define WM8400_LOPLON_SHIFT                          4  /* LOPLON */
+#define WM8400_LOPLON_WIDTH                          1  /* LOPLON */
+#define WM8400_LR12LOP                          0x0004  /* LR12LOP */
+#define WM8400_LR12LOP_MASK                     0x0004  /* LR12LOP */
+#define WM8400_LR12LOP_SHIFT                         2  /* LR12LOP */
+#define WM8400_LR12LOP_WIDTH                         1  /* LR12LOP */
+#define WM8400_LL12LOP                          0x0002  /* LL12LOP */
+#define WM8400_LL12LOP_MASK                     0x0002  /* LL12LOP */
+#define WM8400_LL12LOP_SHIFT                         1  /* LL12LOP */
+#define WM8400_LL12LOP_WIDTH                         1  /* LL12LOP */
+#define WM8400_LLOPGALOP                        0x0001  /* LLOPGALOP */
+#define WM8400_LLOPGALOP_MASK                   0x0001  /* LLOPGALOP */
+#define WM8400_LLOPGALOP_SHIFT                       0  /* LLOPGALOP */
+#define WM8400_LLOPGALOP_WIDTH                       1  /* LLOPGALOP */
+
+/*
+ * R53 (0x35) - Line Mixer2
+ */
+#define WM8400_RROPGARON                        0x0040  /* RROPGARON */
+#define WM8400_RROPGARON_MASK                   0x0040  /* RROPGARON */
+#define WM8400_RROPGARON_SHIFT                       6  /* RROPGARON */
+#define WM8400_RROPGARON_WIDTH                       1  /* RROPGARON */
+#define WM8400_RLOPGARON                        0x0020  /* RLOPGARON */
+#define WM8400_RLOPGARON_MASK                   0x0020  /* RLOPGARON */
+#define WM8400_RLOPGARON_SHIFT                       5  /* RLOPGARON */
+#define WM8400_RLOPGARON_WIDTH                       1  /* RLOPGARON */
+#define WM8400_ROPRON                           0x0010  /* ROPRON */
+#define WM8400_ROPRON_MASK                      0x0010  /* ROPRON */
+#define WM8400_ROPRON_SHIFT                          4  /* ROPRON */
+#define WM8400_ROPRON_WIDTH                          1  /* ROPRON */
+#define WM8400_RL12ROP                          0x0004  /* RL12ROP */
+#define WM8400_RL12ROP_MASK                     0x0004  /* RL12ROP */
+#define WM8400_RL12ROP_SHIFT                         2  /* RL12ROP */
+#define WM8400_RL12ROP_WIDTH                         1  /* RL12ROP */
+#define WM8400_RR12ROP                          0x0002  /* RR12ROP */
+#define WM8400_RR12ROP_MASK                     0x0002  /* RR12ROP */
+#define WM8400_RR12ROP_SHIFT                         1  /* RR12ROP */
+#define WM8400_RR12ROP_WIDTH                         1  /* RR12ROP */
+#define WM8400_RROPGAROP                        0x0001  /* RROPGAROP */
+#define WM8400_RROPGAROP_MASK                   0x0001  /* RROPGAROP */
+#define WM8400_RROPGAROP_SHIFT                       0  /* RROPGAROP */
+#define WM8400_RROPGAROP_WIDTH                       1  /* RROPGAROP */
+
+/*
+ * R54 (0x36) - Speaker Mixer
+ */
+#define WM8400_LB2SPK                           0x0080  /* LB2SPK */
+#define WM8400_LB2SPK_MASK                      0x0080  /* LB2SPK */
+#define WM8400_LB2SPK_SHIFT                          7  /* LB2SPK */
+#define WM8400_LB2SPK_WIDTH                          1  /* LB2SPK */
+#define WM8400_RB2SPK                           0x0040  /* RB2SPK */
+#define WM8400_RB2SPK_MASK                      0x0040  /* RB2SPK */
+#define WM8400_RB2SPK_SHIFT                          6  /* RB2SPK */
+#define WM8400_RB2SPK_WIDTH                          1  /* RB2SPK */
+#define WM8400_LI2SPK                           0x0020  /* LI2SPK */
+#define WM8400_LI2SPK_MASK                      0x0020  /* LI2SPK */
+#define WM8400_LI2SPK_SHIFT                          5  /* LI2SPK */
+#define WM8400_LI2SPK_WIDTH                          1  /* LI2SPK */
+#define WM8400_RI2SPK                           0x0010  /* RI2SPK */
+#define WM8400_RI2SPK_MASK                      0x0010  /* RI2SPK */
+#define WM8400_RI2SPK_SHIFT                          4  /* RI2SPK */
+#define WM8400_RI2SPK_WIDTH                          1  /* RI2SPK */
+#define WM8400_LOPGASPK                         0x0008  /* LOPGASPK */
+#define WM8400_LOPGASPK_MASK                    0x0008  /* LOPGASPK */
+#define WM8400_LOPGASPK_SHIFT                        3  /* LOPGASPK */
+#define WM8400_LOPGASPK_WIDTH                        1  /* LOPGASPK */
+#define WM8400_ROPGASPK                         0x0004  /* ROPGASPK */
+#define WM8400_ROPGASPK_MASK                    0x0004  /* ROPGASPK */
+#define WM8400_ROPGASPK_SHIFT                        2  /* ROPGASPK */
+#define WM8400_ROPGASPK_WIDTH                        1  /* ROPGASPK */
+#define WM8400_LDSPK                            0x0002  /* LDSPK */
+#define WM8400_LDSPK_MASK                       0x0002  /* LDSPK */
+#define WM8400_LDSPK_SHIFT                           1  /* LDSPK */
+#define WM8400_LDSPK_WIDTH                           1  /* LDSPK */
+#define WM8400_RDSPK                            0x0001  /* RDSPK */
+#define WM8400_RDSPK_MASK                       0x0001  /* RDSPK */
+#define WM8400_RDSPK_SHIFT                           0  /* RDSPK */
+#define WM8400_RDSPK_WIDTH                           1  /* RDSPK */
+
+/*
+ * R55 (0x37) - Additional Control
+ */
+#define WM8400_VROI                             0x0001  /* VROI */
+#define WM8400_VROI_MASK                        0x0001  /* VROI */
+#define WM8400_VROI_SHIFT                            0  /* VROI */
+#define WM8400_VROI_WIDTH                            1  /* VROI */
+
+/*
+ * R56 (0x38) - AntiPOP1
+ */
+#define WM8400_DIS_LLINE                        0x0020  /* DIS_LLINE */
+#define WM8400_DIS_LLINE_MASK                   0x0020  /* DIS_LLINE */
+#define WM8400_DIS_LLINE_SHIFT                       5  /* DIS_LLINE */
+#define WM8400_DIS_LLINE_WIDTH                       1  /* DIS_LLINE */
+#define WM8400_DIS_RLINE                        0x0010  /* DIS_RLINE */
+#define WM8400_DIS_RLINE_MASK                   0x0010  /* DIS_RLINE */
+#define WM8400_DIS_RLINE_SHIFT                       4  /* DIS_RLINE */
+#define WM8400_DIS_RLINE_WIDTH                       1  /* DIS_RLINE */
+#define WM8400_DIS_OUT3                         0x0008  /* DIS_OUT3 */
+#define WM8400_DIS_OUT3_MASK                    0x0008  /* DIS_OUT3 */
+#define WM8400_DIS_OUT3_SHIFT                        3  /* DIS_OUT3 */
+#define WM8400_DIS_OUT3_WIDTH                        1  /* DIS_OUT3 */
+#define WM8400_DIS_OUT4                         0x0004  /* DIS_OUT4 */
+#define WM8400_DIS_OUT4_MASK                    0x0004  /* DIS_OUT4 */
+#define WM8400_DIS_OUT4_SHIFT                        2  /* DIS_OUT4 */
+#define WM8400_DIS_OUT4_WIDTH                        1  /* DIS_OUT4 */
+#define WM8400_DIS_LOUT                         0x0002  /* DIS_LOUT */
+#define WM8400_DIS_LOUT_MASK                    0x0002  /* DIS_LOUT */
+#define WM8400_DIS_LOUT_SHIFT                        1  /* DIS_LOUT */
+#define WM8400_DIS_LOUT_WIDTH                        1  /* DIS_LOUT */
+#define WM8400_DIS_ROUT                         0x0001  /* DIS_ROUT */
+#define WM8400_DIS_ROUT_MASK                    0x0001  /* DIS_ROUT */
+#define WM8400_DIS_ROUT_SHIFT                        0  /* DIS_ROUT */
+#define WM8400_DIS_ROUT_WIDTH                        1  /* DIS_ROUT */
+
+/*
+ * R57 (0x39) - AntiPOP2
+ */
+#define WM8400_SOFTST                           0x0040  /* SOFTST */
+#define WM8400_SOFTST_MASK                      0x0040  /* SOFTST */
+#define WM8400_SOFTST_SHIFT                          6  /* SOFTST */
+#define WM8400_SOFTST_WIDTH                          1  /* SOFTST */
+#define WM8400_BUFIOEN                          0x0008  /* BUFIOEN */
+#define WM8400_BUFIOEN_MASK                     0x0008  /* BUFIOEN */
+#define WM8400_BUFIOEN_SHIFT                         3  /* BUFIOEN */
+#define WM8400_BUFIOEN_WIDTH                         1  /* BUFIOEN */
+#define WM8400_BUFDCOPEN                        0x0004  /* BUFDCOPEN */
+#define WM8400_BUFDCOPEN_MASK                   0x0004  /* BUFDCOPEN */
+#define WM8400_BUFDCOPEN_SHIFT                       2  /* BUFDCOPEN */
+#define WM8400_BUFDCOPEN_WIDTH                       1  /* BUFDCOPEN */
+#define WM8400_POBCTRL                          0x0002  /* POBCTRL */
+#define WM8400_POBCTRL_MASK                     0x0002  /* POBCTRL */
+#define WM8400_POBCTRL_SHIFT                         1  /* POBCTRL */
+#define WM8400_POBCTRL_WIDTH                         1  /* POBCTRL */
+#define WM8400_VMIDTOG                          0x0001  /* VMIDTOG */
+#define WM8400_VMIDTOG_MASK                     0x0001  /* VMIDTOG */
+#define WM8400_VMIDTOG_SHIFT                         0  /* VMIDTOG */
+#define WM8400_VMIDTOG_WIDTH                         1  /* VMIDTOG */
+
+/*
+ * R58 (0x3A) - MICBIAS
+ */
+#define WM8400_MCDSCTH_MASK                     0x00C0  /* MCDSCTH - [7:6] */
+#define WM8400_MCDSCTH_SHIFT                         6  /* MCDSCTH - [7:6] */
+#define WM8400_MCDSCTH_WIDTH                         2  /* MCDSCTH - [7:6] */
+#define WM8400_MCDTHR_MASK                      0x0038  /* MCDTHR - [5:3] */
+#define WM8400_MCDTHR_SHIFT                          3  /* MCDTHR - [5:3] */
+#define WM8400_MCDTHR_WIDTH                          3  /* MCDTHR - [5:3] */
+#define WM8400_MCD                              0x0004  /* MCD */
+#define WM8400_MCD_MASK                         0x0004  /* MCD */
+#define WM8400_MCD_SHIFT                             2  /* MCD */
+#define WM8400_MCD_WIDTH                             1  /* MCD */
+#define WM8400_MBSEL                            0x0001  /* MBSEL */
+#define WM8400_MBSEL_MASK                       0x0001  /* MBSEL */
+#define WM8400_MBSEL_SHIFT                           0  /* MBSEL */
+#define WM8400_MBSEL_WIDTH                           1  /* MBSEL */
+
+/*
+ * R60 (0x3C) - FLL Control 1
+ */
+#define WM8400_FLL_REF_FREQ                     0x1000  /* FLL_REF_FREQ */
+#define WM8400_FLL_REF_FREQ_MASK                0x1000  /* FLL_REF_FREQ */
+#define WM8400_FLL_REF_FREQ_SHIFT                   12  /* FLL_REF_FREQ */
+#define WM8400_FLL_REF_FREQ_WIDTH                    1  /* FLL_REF_FREQ */
+#define WM8400_FLL_CLK_SRC_MASK                 0x0C00  /* FLL_CLK_SRC - [11:10] */
+#define WM8400_FLL_CLK_SRC_SHIFT                    10  /* FLL_CLK_SRC - [11:10] */
+#define WM8400_FLL_CLK_SRC_WIDTH                     2  /* FLL_CLK_SRC - [11:10] */
+#define WM8400_FLL_FRAC                         0x0200  /* FLL_FRAC */
+#define WM8400_FLL_FRAC_MASK                    0x0200  /* FLL_FRAC */
+#define WM8400_FLL_FRAC_SHIFT                        9  /* FLL_FRAC */
+#define WM8400_FLL_FRAC_WIDTH                        1  /* FLL_FRAC */
+#define WM8400_FLL_OSC_ENA                      0x0100  /* FLL_OSC_ENA */
+#define WM8400_FLL_OSC_ENA_MASK                 0x0100  /* FLL_OSC_ENA */
+#define WM8400_FLL_OSC_ENA_SHIFT                     8  /* FLL_OSC_ENA */
+#define WM8400_FLL_OSC_ENA_WIDTH                     1  /* FLL_OSC_ENA */
+#define WM8400_FLL_CTRL_RATE_MASK               0x00E0  /* FLL_CTRL_RATE - [7:5] */
+#define WM8400_FLL_CTRL_RATE_SHIFT                   5  /* FLL_CTRL_RATE - [7:5] */
+#define WM8400_FLL_CTRL_RATE_WIDTH                   3  /* FLL_CTRL_RATE - [7:5] */
+#define WM8400_FLL_FRATIO_MASK                  0x001F  /* FLL_FRATIO - [4:0] */
+#define WM8400_FLL_FRATIO_SHIFT                      0  /* FLL_FRATIO - [4:0] */
+#define WM8400_FLL_FRATIO_WIDTH                      5  /* FLL_FRATIO - [4:0] */
+
+/*
+ * R61 (0x3D) - FLL Control 2
+ */
+#define WM8400_FLL_K_MASK                       0xFFFF  /* FLL_K - [15:0] */
+#define WM8400_FLL_K_SHIFT                           0  /* FLL_K - [15:0] */
+#define WM8400_FLL_K_WIDTH                          16  /* FLL_K - [15:0] */
+
+/*
+ * R62 (0x3E) - FLL Control 3
+ */
+#define WM8400_FLL_N_MASK                       0x03FF  /* FLL_N - [9:0] */
+#define WM8400_FLL_N_SHIFT                           0  /* FLL_N - [9:0] */
+#define WM8400_FLL_N_WIDTH                          10  /* FLL_N - [9:0] */
+
+/*
+ * R63 (0x3F) - FLL Control 4
+ */
+#define WM8400_FLL_TRK_GAIN_MASK                0x0078  /* FLL_TRK_GAIN - [6:3] */
+#define WM8400_FLL_TRK_GAIN_SHIFT                    3  /* FLL_TRK_GAIN - [6:3] */
+#define WM8400_FLL_TRK_GAIN_WIDTH                    4  /* FLL_TRK_GAIN - [6:3] */
+#define WM8400_FLL_OUTDIV_MASK                  0x0007  /* FLL_OUTDIV - [2:0] */
+#define WM8400_FLL_OUTDIV_SHIFT                      0  /* FLL_OUTDIV - [2:0] */
+#define WM8400_FLL_OUTDIV_WIDTH                      3  /* FLL_OUTDIV - [2:0] */
+
+void wm8400_reset_codec_reg_cache(struct wm8400 *wm8400);
+
+#endif
diff --git a/include/linux/mfd/wm8400-private.h b/include/linux/mfd/wm8400-private.h
new file mode 100644
index 000000000000..2aab4e93a5c9
--- /dev/null
+++ b/include/linux/mfd/wm8400-private.h
@@ -0,0 +1,936 @@
+/*
+ * wm8400 private definitions.
+ *
+ * Copyright 2008 Wolfson Microelectronics plc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_MFD_WM8400_PRIV_H
+#define __LINUX_MFD_WM8400_PRIV_H
+
+#include <linux/mfd/wm8400.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+#define WM8400_REGISTER_COUNT 0x55
+
+struct wm8400 {
+        struct device *dev;
+
+        int (*read_dev)(void *data, char reg, int count, u16 *dst);
+        int (*write_dev)(void *data, char reg, int count, const u16 *src);
+
+        struct mutex io_lock;
+        void *io_data;
+
+        u16 reg_cache[WM8400_REGISTER_COUNT];
+
+        struct platform_device regulators[6];
+};
+
+/*
+ * Register values.
+ */
+#define WM8400_RESET_ID                         0x00
+#define WM8400_ID                               0x01
+#define WM8400_POWER_MANAGEMENT_1               0x02
+#define WM8400_POWER_MANAGEMENT_2               0x03
+#define WM8400_POWER_MANAGEMENT_3               0x04
+#define WM8400_AUDIO_INTERFACE_1                0x05
+#define WM8400_AUDIO_INTERFACE_2                0x06
+#define WM8400_CLOCKING_1                       0x07
+#define WM8400_CLOCKING_2                       0x08
+#define WM8400_AUDIO_INTERFACE_3                0x09
+#define WM8400_AUDIO_INTERFACE_4                0x0A
+#define WM8400_DAC_CTRL                         0x0B
+#define WM8400_LEFT_DAC_DIGITAL_VOLUME          0x0C
+#define WM8400_RIGHT_DAC_DIGITAL_VOLUME         0x0D
+#define WM8400_DIGITAL_SIDE_TONE                0x0E
+#define WM8400_ADC_CTRL                         0x0F
+#define WM8400_LEFT_ADC_DIGITAL_VOLUME          0x10
+#define WM8400_RIGHT_ADC_DIGITAL_VOLUME         0x11
+#define WM8400_GPIO_CTRL_1                      0x12
+#define WM8400_GPIO1_GPIO2                      0x13
+#define WM8400_GPIO3_GPIO4                      0x14
+#define WM8400_GPIO5_GPIO6                      0x15
+#define WM8400_GPIOCTRL_2                       0x16
+#define WM8400_GPIO_POL                         0x17
+#define WM8400_LEFT_LINE_INPUT_1_2_VOLUME       0x18
+#define WM8400_LEFT_LINE_INPUT_3_4_VOLUME       0x19
+#define WM8400_RIGHT_LINE_INPUT_1_2_VOLUME      0x1A
+#define WM8400_RIGHT_LINE_INPUT_3_4_VOLUME      0x1B
+#define WM8400_LEFT_OUTPUT_VOLUME               0x1C
+#define WM8400_RIGHT_OUTPUT_VOLUME              0x1D
+#define WM8400_LINE_OUTPUTS_VOLUME              0x1E
+#define WM8400_OUT3_4_VOLUME                    0x1F
+#define WM8400_LEFT_OPGA_VOLUME                 0x20
+#define WM8400_RIGHT_OPGA_VOLUME                0x21
+#define WM8400_SPEAKER_VOLUME                   0x22
+#define WM8400_CLASSD1                          0x23
+#define WM8400_CLASSD3                          0x25
+#define WM8400_INPUT_MIXER1                     0x27
+#define WM8400_INPUT_MIXER2                     0x28
+#define WM8400_INPUT_MIXER3                     0x29
+#define WM8400_INPUT_MIXER4                     0x2A
+#define WM8400_INPUT_MIXER5                     0x2B
+#define WM8400_INPUT_MIXER6                     0x2C
+#define WM8400_OUTPUT_MIXER1                    0x2D
+#define WM8400_OUTPUT_MIXER2                    0x2E
+#define WM8400_OUTPUT_MIXER3                    0x2F
+#define WM8400_OUTPUT_MIXER4                    0x30
+#define WM8400_OUTPUT_MIXER5                    0x31
+#define WM8400_OUTPUT_MIXER6                    0x32
+#define WM8400_OUT3_4_MIXER                     0x33
+#define WM8400_LINE_MIXER1                      0x34
+#define WM8400_LINE_MIXER2                      0x35
+#define WM8400_SPEAKER_MIXER                    0x36
+#define WM8400_ADDITIONAL_CONTROL               0x37
+#define WM8400_ANTIPOP1                         0x38
+#define WM8400_ANTIPOP2                         0x39
+#define WM8400_MICBIAS                          0x3A
+#define WM8400_FLL_CONTROL_1                    0x3C
+#define WM8400_FLL_CONTROL_2                    0x3D
+#define WM8400_FLL_CONTROL_3                    0x3E
+#define WM8400_FLL_CONTROL_4                    0x3F
+#define WM8400_LDO1_CONTROL                     0x41
+#define WM8400_LDO2_CONTROL                     0x42
+#define WM8400_LDO3_CONTROL                     0x43
+#define WM8400_LDO4_CONTROL                     0x44
+#define WM8400_DCDC1_CONTROL_1                  0x46
+#define WM8400_DCDC1_CONTROL_2                  0x47
+#define WM8400_DCDC2_CONTROL_1                  0x48
+#define WM8400_DCDC2_CONTROL_2                  0x49
+#define WM8400_INTERFACE                        0x4B
+#define WM8400_PM_GENERAL                       0x4C
+#define WM8400_PM_SHUTDOWN_CONTROL              0x4E
+#define WM8400_INTERRUPT_STATUS_1               0x4F
+#define WM8400_INTERRUPT_STATUS_1_MASK          0x50
+#define WM8400_INTERRUPT_LEVELS                 0x51
+#define WM8400_SHUTDOWN_REASON                  0x52
+#define WM8400_LINE_CIRCUITS                    0x54
+
+/*
+ * Field Definitions.
+ */
+
+/*
+ * R0 (0x00) - Reset/ID
+ */
+#define WM8400_SW_RESET_CHIP_ID_MASK            0xFFFF  /* SW_RESET/CHIP_ID - [15:0] */
+#define WM8400_SW_RESET_CHIP_ID_SHIFT                0  /* SW_RESET/CHIP_ID - [15:0] */
+#define WM8400_SW_RESET_CHIP_ID_WIDTH               16  /* SW_RESET/CHIP_ID - [15:0] */
+
+/*
+ * R1 (0x01) - ID
+ */
+#define WM8400_CHIP_REV_MASK                    0x7000  /* CHIP_REV - [14:12] */
+#define WM8400_CHIP_REV_SHIFT                       12  /* CHIP_REV - [14:12] */
+#define WM8400_CHIP_REV_WIDTH                        3  /* CHIP_REV - [14:12] */
+
+/*
+ * R18 (0x12) - GPIO CTRL 1
+ */
+#define WM8400_IRQ                              0x1000  /* IRQ */
+#define WM8400_IRQ_MASK                         0x1000  /* IRQ */
+#define WM8400_IRQ_SHIFT                            12  /* IRQ */
+#define WM8400_IRQ_WIDTH                             1  /* IRQ */
+#define WM8400_TEMPOK                           0x0800  /* TEMPOK */
+#define WM8400_TEMPOK_MASK                      0x0800  /* TEMPOK */
+#define WM8400_TEMPOK_SHIFT                         11  /* TEMPOK */
+#define WM8400_TEMPOK_WIDTH                          1  /* TEMPOK */
+#define WM8400_MIC1SHRT                         0x0400  /* MIC1SHRT */
+#define WM8400_MIC1SHRT_MASK                    0x0400  /* MIC1SHRT */
+#define WM8400_MIC1SHRT_SHIFT                       10  /* MIC1SHRT */
+#define WM8400_MIC1SHRT_WIDTH                        1  /* MIC1SHRT */
+#define WM8400_MIC1DET                          0x0200  /* MIC1DET */
+#define WM8400_MIC1DET_MASK                     0x0200  /* MIC1DET */
+#define WM8400_MIC1DET_SHIFT                         9  /* MIC1DET */
+#define WM8400_MIC1DET_WIDTH                         1  /* MIC1DET */
+#define WM8400_FLL_LCK                          0x0100  /* FLL_LCK */
+#define WM8400_FLL_LCK_MASK                     0x0100  /* FLL_LCK */
+#define WM8400_FLL_LCK_SHIFT                         8  /* FLL_LCK */
+#define WM8400_FLL_LCK_WIDTH                         1  /* FLL_LCK */
+#define WM8400_GPIO_STATUS_MASK                 0x00FF  /* GPIO_STATUS - [7:0] */
+#define WM8400_GPIO_STATUS_SHIFT                     0  /* GPIO_STATUS - [7:0] */
+#define WM8400_GPIO_STATUS_WIDTH                     8  /* GPIO_STATUS - [7:0] */
+
+/*
+ * R19 (0x13) - GPIO1 & GPIO2
+ */
+#define WM8400_GPIO2_DEB_ENA                    0x8000  /* GPIO2_DEB_ENA */
+#define WM8400_GPIO2_DEB_ENA_MASK               0x8000  /* GPIO2_DEB_ENA */
+#define WM8400_GPIO2_DEB_ENA_SHIFT                  15  /* GPIO2_DEB_ENA */
+#define WM8400_GPIO2_DEB_ENA_WIDTH                   1  /* GPIO2_DEB_ENA */
+#define WM8400_GPIO2_IRQ_ENA                    0x4000  /* GPIO2_IRQ_ENA */
+#define WM8400_GPIO2_IRQ_ENA_MASK               0x4000  /* GPIO2_IRQ_ENA */
+#define WM8400_GPIO2_IRQ_ENA_SHIFT                  14  /* GPIO2_IRQ_ENA */
+#define WM8400_GPIO2_IRQ_ENA_WIDTH                   1  /* GPIO2_IRQ_ENA */
+#define WM8400_GPIO2_PU                         0x2000  /* GPIO2_PU */
+#define WM8400_GPIO2_PU_MASK                    0x2000  /* GPIO2_PU */
+#define WM8400_GPIO2_PU_SHIFT                       13  /* GPIO2_PU */
+#define WM8400_GPIO2_PU_WIDTH                        1  /* GPIO2_PU */
+#define WM8400_GPIO2_PD                         0x1000  /* GPIO2_PD */
+#define WM8400_GPIO2_PD_MASK                    0x1000  /* GPIO2_PD */
+#define WM8400_GPIO2_PD_SHIFT                       12  /* GPIO2_PD */
+#define WM8400_GPIO2_PD_WIDTH                        1  /* GPIO2_PD */
+#define WM8400_GPIO2_SEL_MASK                   0x0F00  /* GPIO2_SEL - [11:8] */
+#define WM8400_GPIO2_SEL_SHIFT                       8  /* GPIO2_SEL - [11:8] */
+#define WM8400_GPIO2_SEL_WIDTH                       4  /* GPIO2_SEL - [11:8] */
+#define WM8400_GPIO1_DEB_ENA                    0x0080  /* GPIO1_DEB_ENA */
+#define WM8400_GPIO1_DEB_ENA_MASK               0x0080  /* GPIO1_DEB_ENA */
+#define WM8400_GPIO1_DEB_ENA_SHIFT                   7  /* GPIO1_DEB_ENA */
+#define WM8400_GPIO1_DEB_ENA_WIDTH                   1  /* GPIO1_DEB_ENA */
+#define WM8400_GPIO1_IRQ_ENA                    0x0040  /* GPIO1_IRQ_ENA */
+#define WM8400_GPIO1_IRQ_ENA_MASK               0x0040  /* GPIO1_IRQ_ENA */
+#define WM8400_GPIO1_IRQ_ENA_SHIFT                   6  /* GPIO1_IRQ_ENA */
+#define WM8400_GPIO1_IRQ_ENA_WIDTH                   1  /* GPIO1_IRQ_ENA */
+#define WM8400_GPIO1_PU                         0x0020  /* GPIO1_PU */
+#define WM8400_GPIO1_PU_MASK                    0x0020  /* GPIO1_PU */
+#define WM8400_GPIO1_PU_SHIFT                        5  /* GPIO1_PU */
+#define WM8400_GPIO1_PU_WIDTH                        1  /* GPIO1_PU */
+#define WM8400_GPIO1_PD                         0x0010  /* GPIO1_PD */
+#define WM8400_GPIO1_PD_MASK                    0x0010  /* GPIO1_PD */
+#define WM8400_GPIO1_PD_SHIFT                        4  /* GPIO1_PD */
+#define WM8400_GPIO1_PD_WIDTH                        1  /* GPIO1_PD */
+#define WM8400_GPIO1_SEL_MASK                   0x000F  /* GPIO1_SEL - [3:0] */
+#define WM8400_GPIO1_SEL_SHIFT                       0  /* GPIO1_SEL - [3:0] */
+#define WM8400_GPIO1_SEL_WIDTH                       4  /* GPIO1_SEL - [3:0] */
+
+/*
+ * R20 (0x14) - GPIO3 & GPIO4
+ */
+#define WM8400_GPIO4_DEB_ENA                    0x8000  /* GPIO4_DEB_ENA */
+#define WM8400_GPIO4_DEB_ENA_MASK               0x8000  /* GPIO4_DEB_ENA */
+#define WM8400_GPIO4_DEB_ENA_SHIFT                  15  /* GPIO4_DEB_ENA */
+#define WM8400_GPIO4_DEB_ENA_WIDTH                   1  /* GPIO4_DEB_ENA */
+#define WM8400_GPIO4_IRQ_ENA                    0x4000  /* GPIO4_IRQ_ENA */
+#define WM8400_GPIO4_IRQ_ENA_MASK               0x4000  /* GPIO4_IRQ_ENA */
+#define WM8400_GPIO4_IRQ_ENA_SHIFT                  14  /* GPIO4_IRQ_ENA */
+#define WM8400_GPIO4_IRQ_ENA_WIDTH                   1  /* GPIO4_IRQ_ENA */
+#define WM8400_GPIO4_PU                         0x2000  /* GPIO4_PU */
+#define WM8400_GPIO4_PU_MASK                    0x2000  /* GPIO4_PU */
+#define WM8400_GPIO4_PU_SHIFT                       13  /* GPIO4_PU */
+#define WM8400_GPIO4_PU_WIDTH                        1  /* GPIO4_PU */
+#define WM8400_GPIO4_PD                         0x1000  /* GPIO4_PD */
+#define WM8400_GPIO4_PD_MASK                    0x1000  /* GPIO4_PD */
+#define WM8400_GPIO4_PD_SHIFT                       12  /* GPIO4_PD */
+#define WM8400_GPIO4_PD_WIDTH                        1  /* GPIO4_PD */
+#define WM8400_GPIO4_SEL_MASK                   0x0F00  /* GPIO4_SEL - [11:8] */
+#define WM8400_GPIO4_SEL_SHIFT                       8  /* GPIO4_SEL - [11:8] */
+#define WM8400_GPIO4_SEL_WIDTH                       4  /* GPIO4_SEL - [11:8] */
+#define WM8400_GPIO3_DEB_ENA                    0x0080  /* GPIO3_DEB_ENA */
+#define WM8400_GPIO3_DEB_ENA_MASK               0x0080  /* GPIO3_DEB_ENA */
+#define WM8400_GPIO3_DEB_ENA_SHIFT                   7  /* GPIO3_DEB_ENA */
+#define WM8400_GPIO3_DEB_ENA_WIDTH                   1  /* GPIO3_DEB_ENA */
+#define WM8400_GPIO3_IRQ_ENA                    0x0040  /* GPIO3_IRQ_ENA */
+#define WM8400_GPIO3_IRQ_ENA_MASK               0x0040  /* GPIO3_IRQ_ENA */
+#define WM8400_GPIO3_IRQ_ENA_SHIFT                   6  /* GPIO3_IRQ_ENA */
+#define WM8400_GPIO3_IRQ_ENA_WIDTH                   1  /* GPIO3_IRQ_ENA */
+#define WM8400_GPIO3_PU                         0x0020  /* GPIO3_PU */
+#define WM8400_GPIO3_PU_MASK                    0x0020  /* GPIO3_PU */
+#define WM8400_GPIO3_PU_SHIFT                        5  /* GPIO3_PU */
+#define WM8400_GPIO3_PU_WIDTH                        1  /* GPIO3_PU */
+#define WM8400_GPIO3_PD                         0x0010  /* GPIO3_PD */
+#define WM8400_GPIO3_PD_MASK                    0x0010  /* GPIO3_PD */
+#define WM8400_GPIO3_PD_SHIFT                        4  /* GPIO3_PD */
+#define WM8400_GPIO3_PD_WIDTH                        1  /* GPIO3_PD */
+#define WM8400_GPIO3_SEL_MASK                   0x000F  /* GPIO3_SEL - [3:0] */
+#define WM8400_GPIO3_SEL_SHIFT                       0  /* GPIO3_SEL - [3:0] */
+#define WM8400_GPIO3_SEL_WIDTH                       4  /* GPIO3_SEL - [3:0] */
+
+/*
+ * R21 (0x15) - GPIO5 & GPIO6
+ */
+#define WM8400_GPIO6_DEB_ENA                    0x8000  /* GPIO6_DEB_ENA */
+#define WM8400_GPIO6_DEB_ENA_MASK               0x8000  /* GPIO6_DEB_ENA */
+#define WM8400_GPIO6_DEB_ENA_SHIFT                  15  /* GPIO6_DEB_ENA */
+#define WM8400_GPIO6_DEB_ENA_WIDTH                   1  /* GPIO6_DEB_ENA */
+#define WM8400_GPIO6_IRQ_ENA                    0x4000  /* GPIO6_IRQ_ENA */
+#define WM8400_GPIO6_IRQ_ENA_MASK               0x4000  /* GPIO6_IRQ_ENA */
+#define WM8400_GPIO6_IRQ_ENA_SHIFT                  14  /* GPIO6_IRQ_ENA */
+#define WM8400_GPIO6_IRQ_ENA_WIDTH                   1  /* GPIO6_IRQ_ENA */
+#define WM8400_GPIO6_PU                         0x2000  /* GPIO6_PU */
+#define WM8400_GPIO6_PU_MASK                    0x2000  /* GPIO6_PU */
+#define WM8400_GPIO6_PU_SHIFT                       13  /* GPIO6_PU */
+#define WM8400_GPIO6_PU_WIDTH                        1  /* GPIO6_PU */
+#define WM8400_GPIO6_PD                         0x1000  /* GPIO6_PD */
+#define WM8400_GPIO6_PD_MASK                    0x1000  /* GPIO6_PD */
+#define WM8400_GPIO6_PD_SHIFT                       12  /* GPIO6_PD */
+#define WM8400_GPIO6_PD_WIDTH                        1  /* GPIO6_PD */
+#define WM8400_GPIO6_SEL_MASK                   0x0F00  /* GPIO6_SEL - [11:8] */
+#define WM8400_GPIO6_SEL_SHIFT                       8  /* GPIO6_SEL - [11:8] */
+#define WM8400_GPIO6_SEL_WIDTH                       4  /* GPIO6_SEL - [11:8] */
+#define WM8400_GPIO5_DEB_ENA                    0x0080  /* GPIO5_DEB_ENA */
+#define WM8400_GPIO5_DEB_ENA_MASK               0x0080  /* GPIO5_DEB_ENA */
+#define WM8400_GPIO5_DEB_ENA_SHIFT                   7  /* GPIO5_DEB_ENA */
+#define WM8400_GPIO5_DEB_ENA_WIDTH                   1  /* GPIO5_DEB_ENA */
+#define WM8400_GPIO5_IRQ_ENA                    0x0040  /* GPIO5_IRQ_ENA */
+#define WM8400_GPIO5_IRQ_ENA_MASK               0x0040  /* GPIO5_IRQ_ENA */
+#define WM8400_GPIO5_IRQ_ENA_SHIFT                   6  /* GPIO5_IRQ_ENA */
+#define WM8400_GPIO5_IRQ_ENA_WIDTH                   1  /* GPIO5_IRQ_ENA */
+#define WM8400_GPIO5_PU                         0x0020  /* GPIO5_PU */
+#define WM8400_GPIO5_PU_MASK                    0x0020  /* GPIO5_PU */
+#define WM8400_GPIO5_PU_SHIFT                        5  /* GPIO5_PU */
+#define WM8400_GPIO5_PU_WIDTH                        1  /* GPIO5_PU */
+#define WM8400_GPIO5_PD                         0x0010  /* GPIO5_PD */
+#define WM8400_GPIO5_PD_MASK                    0x0010  /* GPIO5_PD */
+#define WM8400_GPIO5_PD_SHIFT                        4  /* GPIO5_PD */
+#define WM8400_GPIO5_PD_WIDTH                        1  /* GPIO5_PD */
+#define WM8400_GPIO5_SEL_MASK                   0x000F  /* GPIO5_SEL - [3:0] */
+#define WM8400_GPIO5_SEL_SHIFT                       0  /* GPIO5_SEL - [3:0] */
+#define WM8400_GPIO5_SEL_WIDTH                       4  /* GPIO5_SEL - [3:0] */
+
+/*
+ * R22 (0x16) - GPIOCTRL 2
+ */
+#define WM8400_TEMPOK_IRQ_ENA                   0x0800  /* TEMPOK_IRQ_ENA */
+#define WM8400_TEMPOK_IRQ_ENA_MASK              0x0800  /* TEMPOK_IRQ_ENA */
+#define WM8400_TEMPOK_IRQ_ENA_SHIFT                 11  /* TEMPOK_IRQ_ENA */
+#define WM8400_TEMPOK_IRQ_ENA_WIDTH                  1  /* TEMPOK_IRQ_ENA */
+#define WM8400_MIC1SHRT_IRQ_ENA                 0x0400  /* MIC1SHRT_IRQ_ENA */
+#define WM8400_MIC1SHRT_IRQ_ENA_MASK            0x0400  /* MIC1SHRT_IRQ_ENA */
+#define WM8400_MIC1SHRT_IRQ_ENA_SHIFT               10  /* MIC1SHRT_IRQ_ENA */
+#define WM8400_MIC1SHRT_IRQ_ENA_WIDTH                1  /* MIC1SHRT_IRQ_ENA */
+#define WM8400_MIC1DET_IRQ_ENA                  0x0200  /* MIC1DET_IRQ_ENA */
+#define WM8400_MIC1DET_IRQ_ENA_MASK             0x0200  /* MIC1DET_IRQ_ENA */
+#define WM8400_MIC1DET_IRQ_ENA_SHIFT                 9  /* MIC1DET_IRQ_ENA */
+#define WM8400_MIC1DET_IRQ_ENA_WIDTH                 1  /* MIC1DET_IRQ_ENA */
+#define WM8400_FLL_LCK_IRQ_ENA                  0x0100  /* FLL_LCK_IRQ_ENA */
+#define WM8400_FLL_LCK_IRQ_ENA_MASK             0x0100  /* FLL_LCK_IRQ_ENA */
+#define WM8400_FLL_LCK_IRQ_ENA_SHIFT                 8  /* FLL_LCK_IRQ_ENA */
+#define WM8400_FLL_LCK_IRQ_ENA_WIDTH                 1  /* FLL_LCK_IRQ_ENA */
+#define WM8400_GPI8_DEB_ENA                     0x0080  /* GPI8_DEB_ENA */
+#define WM8400_GPI8_DEB_ENA_MASK                0x0080  /* GPI8_DEB_ENA */
+#define WM8400_GPI8_DEB_ENA_SHIFT                    7  /* GPI8_DEB_ENA */
+#define WM8400_GPI8_DEB_ENA_WIDTH                    1  /* GPI8_DEB_ENA */
+#define WM8400_GPI8_IRQ_ENA                     0x0040  /* GPI8_IRQ_ENA */
+#define WM8400_GPI8_IRQ_ENA_MASK                0x0040  /* GPI8_IRQ_ENA */
+#define WM8400_GPI8_IRQ_ENA_SHIFT                    6  /* GPI8_IRQ_ENA */
+#define WM8400_GPI8_IRQ_ENA_WIDTH                    1  /* GPI8_IRQ_ENA */
+#define WM8400_GPI8_ENA                         0x0010  /* GPI8_ENA */
+#define WM8400_GPI8_ENA_MASK                    0x0010  /* GPI8_ENA */
+#define WM8400_GPI8_ENA_SHIFT                        4  /* GPI8_ENA */
+#define WM8400_GPI8_ENA_WIDTH                        1  /* GPI8_ENA */
+#define WM8400_GPI7_DEB_ENA                     0x0008  /* GPI7_DEB_ENA */
+#define WM8400_GPI7_DEB_ENA_MASK                0x0008  /* GPI7_DEB_ENA */
+#define WM8400_GPI7_DEB_ENA_SHIFT                    3  /* GPI7_DEB_ENA */
+#define WM8400_GPI7_DEB_ENA_WIDTH                    1  /* GPI7_DEB_ENA */
+#define WM8400_GPI7_IRQ_ENA                     0x0004  /* GPI7_IRQ_ENA */
+#define WM8400_GPI7_IRQ_ENA_MASK                0x0004  /* GPI7_IRQ_ENA */
+#define WM8400_GPI7_IRQ_ENA_SHIFT                    2  /* GPI7_IRQ_ENA */
+#define WM8400_GPI7_IRQ_ENA_WIDTH                    1  /* GPI7_IRQ_ENA */
+#define WM8400_GPI7_ENA                         0x0001  /* GPI7_ENA */
+#define WM8400_GPI7_ENA_MASK                    0x0001  /* GPI7_ENA */
+#define WM8400_GPI7_ENA_SHIFT                        0  /* GPI7_ENA */
+#define WM8400_GPI7_ENA_WIDTH                        1  /* GPI7_ENA */
+
+/*
+ * R23 (0x17) - GPIO_POL
+ */
+#define WM8400_IRQ_INV                          0x1000  /* IRQ_INV */
+#define WM8400_IRQ_INV_MASK                     0x1000  /* IRQ_INV */
+#define WM8400_IRQ_INV_SHIFT                        12  /* IRQ_INV */
+#define WM8400_IRQ_INV_WIDTH                         1  /* IRQ_INV */
+#define WM8400_TEMPOK_POL                       0x0800  /* TEMPOK_POL */
+#define WM8400_TEMPOK_POL_MASK                  0x0800  /* TEMPOK_POL */
+#define WM8400_TEMPOK_POL_SHIFT                     11  /* TEMPOK_POL */
+#define WM8400_TEMPOK_POL_WIDTH                      1  /* TEMPOK_POL */
+#define WM8400_MIC1SHRT_POL                     0x0400  /* MIC1SHRT_POL */
+#define WM8400_MIC1SHRT_POL_MASK                0x0400  /* MIC1SHRT_POL */
+#define WM8400_MIC1SHRT_POL_SHIFT                   10  /* MIC1SHRT_POL */
+#define WM8400_MIC1SHRT_POL_WIDTH                    1  /* MIC1SHRT_POL */
+#define WM8400_MIC1DET_POL                      0x0200  /* MIC1DET_POL */
+#define WM8400_MIC1DET_POL_MASK                 0x0200  /* MIC1DET_POL */
+#define WM8400_MIC1DET_POL_SHIFT                     9  /* MIC1DET_POL */
+#define WM8400_MIC1DET_POL_WIDTH                     1  /* MIC1DET_POL */
+#define WM8400_FLL_LCK_POL                      0x0100  /* FLL_LCK_POL */
+#define WM8400_FLL_LCK_POL_MASK                 0x0100  /* FLL_LCK_POL */
+#define WM8400_FLL_LCK_POL_SHIFT                     8  /* FLL_LCK_POL */
+#define WM8400_FLL_LCK_POL_WIDTH                     1  /* FLL_LCK_POL */
+#define WM8400_GPIO_POL_MASK                    0x00FF  /* GPIO_POL - [7:0] */
+#define WM8400_GPIO_POL_SHIFT                        0  /* GPIO_POL - [7:0] */
+#define WM8400_GPIO_POL_WIDTH                        8  /* GPIO_POL - [7:0] */
+
+/*
+ * R65 (0x41) - LDO 1 Control
+ */
+#define WM8400_LDO1_ENA                         0x8000  /* LDO1_ENA */
+#define WM8400_LDO1_ENA_MASK                    0x8000  /* LDO1_ENA */
+#define WM8400_LDO1_ENA_SHIFT                       15  /* LDO1_ENA */
+#define WM8400_LDO1_ENA_WIDTH                        1  /* LDO1_ENA */
+#define WM8400_LDO1_SWI                         0x4000  /* LDO1_SWI */
+#define WM8400_LDO1_SWI_MASK                    0x4000  /* LDO1_SWI */
+#define WM8400_LDO1_SWI_SHIFT                       14  /* LDO1_SWI */
+#define WM8400_LDO1_SWI_WIDTH                        1  /* LDO1_SWI */
+#define WM8400_LDO1_OPFLT                       0x1000  /* LDO1_OPFLT */
+#define WM8400_LDO1_OPFLT_MASK                  0x1000  /* LDO1_OPFLT */
+#define WM8400_LDO1_OPFLT_SHIFT                     12  /* LDO1_OPFLT */
+#define WM8400_LDO1_OPFLT_WIDTH                      1  /* LDO1_OPFLT */
+#define WM8400_LDO1_ERRACT                      0x0800  /* LDO1_ERRACT */
+#define WM8400_LDO1_ERRACT_MASK                 0x0800  /* LDO1_ERRACT */
+#define WM8400_LDO1_ERRACT_SHIFT                    11  /* LDO1_ERRACT */
+#define WM8400_LDO1_ERRACT_WIDTH                     1  /* LDO1_ERRACT */
+#define WM8400_LDO1_HIB_MODE                    0x0400  /* LDO1_HIB_MODE */
+#define WM8400_LDO1_HIB_MODE_MASK               0x0400  /* LDO1_HIB_MODE */
+#define WM8400_LDO1_HIB_MODE_SHIFT                  10  /* LDO1_HIB_MODE */
+#define WM8400_LDO1_HIB_MODE_WIDTH                   1  /* LDO1_HIB_MODE */
+#define WM8400_LDO1_VIMG_MASK                   0x03E0  /* LDO1_VIMG - [9:5] */
+#define WM8400_LDO1_VIMG_SHIFT                       5  /* LDO1_VIMG - [9:5] */
+#define WM8400_LDO1_VIMG_WIDTH                       5  /* LDO1_VIMG - [9:5] */
+#define WM8400_LDO1_VSEL_MASK                   0x001F  /* LDO1_VSEL - [4:0] */
+#define WM8400_LDO1_VSEL_SHIFT                       0  /* LDO1_VSEL - [4:0] */
+#define WM8400_LDO1_VSEL_WIDTH                       5  /* LDO1_VSEL - [4:0] */
+
+/*
+ * R66 (0x42) - LDO 2 Control
+ */
+#define WM8400_LDO2_ENA                         0x8000  /* LDO2_ENA */
+#define WM8400_LDO2_ENA_MASK                    0x8000  /* LDO2_ENA */
+#define WM8400_LDO2_ENA_SHIFT                       15  /* LDO2_ENA */
+#define WM8400_LDO2_ENA_WIDTH                        1  /* LDO2_ENA */
+#define WM8400_LDO2_SWI                         0x4000  /* LDO2_SWI */
+#define WM8400_LDO2_SWI_MASK                    0x4000  /* LDO2_SWI */
+#define WM8400_LDO2_SWI_SHIFT                       14  /* LDO2_SWI */
+#define WM8400_LDO2_SWI_WIDTH                        1  /* LDO2_SWI */
+#define WM8400_LDO2_OPFLT                       0x1000  /* LDO2_OPFLT */
+#define WM8400_LDO2_OPFLT_MASK                  0x1000  /* LDO2_OPFLT */
+#define WM8400_LDO2_OPFLT_SHIFT                     12  /* LDO2_OPFLT */
+#define WM8400_LDO2_OPFLT_WIDTH                      1  /* LDO2_OPFLT */
+#define WM8400_LDO2_ERRACT                      0x0800  /* LDO2_ERRACT */
+#define WM8400_LDO2_ERRACT_MASK                 0x0800  /* LDO2_ERRACT */
+#define WM8400_LDO2_ERRACT_SHIFT                    11  /* LDO2_ERRACT */
+#define WM8400_LDO2_ERRACT_WIDTH                     1  /* LDO2_ERRACT */
+#define WM8400_LDO2_HIB_MODE                    0x0400  /* LDO2_HIB_MODE */
+#define WM8400_LDO2_HIB_MODE_MASK               0x0400  /* LDO2_HIB_MODE */
+#define WM8400_LDO2_HIB_MODE_SHIFT                  10  /* LDO2_HIB_MODE */
+#define WM8400_LDO2_HIB_MODE_WIDTH                   1  /* LDO2_HIB_MODE */
+#define WM8400_LDO2_VIMG_MASK                   0x03E0  /* LDO2_VIMG - [9:5] */
+#define WM8400_LDO2_VIMG_SHIFT                       5  /* LDO2_VIMG - [9:5] */
+#define WM8400_LDO2_VIMG_WIDTH                       5  /* LDO2_VIMG - [9:5] */
+#define WM8400_LDO2_VSEL_MASK                   0x001F  /* LDO2_VSEL - [4:0] */
+#define WM8400_LDO2_VSEL_SHIFT                       0  /* LDO2_VSEL - [4:0] */
+#define WM8400_LDO2_VSEL_WIDTH                       5  /* LDO2_VSEL - [4:0] */
+
+/*
+ * R67 (0x43) - LDO 3 Control
+ */
+#define WM8400_LDO3_ENA                         0x8000  /* LDO3_ENA */
+#define WM8400_LDO3_ENA_MASK                    0x8000  /* LDO3_ENA */
+#define WM8400_LDO3_ENA_SHIFT                       15  /* LDO3_ENA */
+#define WM8400_LDO3_ENA_WIDTH                        1  /* LDO3_ENA */
+#define WM8400_LDO3_SWI                         0x4000  /* LDO3_SWI */
+#define WM8400_LDO3_SWI_MASK                    0x4000  /* LDO3_SWI */
+#define WM8400_LDO3_SWI_SHIFT                       14  /* LDO3_SWI */
+#define WM8400_LDO3_SWI_WIDTH                        1  /* LDO3_SWI */
+#define WM8400_LDO3_OPFLT                       0x1000  /* LDO3_OPFLT */
+#define WM8400_LDO3_OPFLT_MASK                  0x1000  /* LDO3_OPFLT */
+#define WM8400_LDO3_OPFLT_SHIFT                     12  /* LDO3_OPFLT */
+#define WM8400_LDO3_OPFLT_WIDTH                      1  /* LDO3_OPFLT */
+#define WM8400_LDO3_ERRACT                      0x0800  /* LDO3_ERRACT */
+#define WM8400_LDO3_ERRACT_MASK                 0x0800  /* LDO3_ERRACT */
+#define WM8400_LDO3_ERRACT_SHIFT                    11  /* LDO3_ERRACT */
+#define WM8400_LDO3_ERRACT_WIDTH                     1  /* LDO3_ERRACT */
+#define WM8400_LDO3_HIB_MODE                    0x0400  /* LDO3_HIB_MODE */
+#define WM8400_LDO3_HIB_MODE_MASK               0x0400  /* LDO3_HIB_MODE */
+#define WM8400_LDO3_HIB_MODE_SHIFT                  10  /* LDO3_HIB_MODE */
+#define WM8400_LDO3_HIB_MODE_WIDTH                   1  /* LDO3_HIB_MODE */
+#define WM8400_LDO3_VIMG_MASK                   0x03E0  /* LDO3_VIMG - [9:5] */
+#define WM8400_LDO3_VIMG_SHIFT                       5  /* LDO3_VIMG - [9:5] */
+#define WM8400_LDO3_VIMG_WIDTH                       5  /* LDO3_VIMG - [9:5] */
+#define WM8400_LDO3_VSEL_MASK                   0x001F  /* LDO3_VSEL - [4:0] */
+#define WM8400_LDO3_VSEL_SHIFT                       0  /* LDO3_VSEL - [4:0] */
+#define WM8400_LDO3_VSEL_WIDTH                       5  /* LDO3_VSEL - [4:0] */
+
+/*
+ * R68 (0x44) - LDO 4 Control
+ */
+#define WM8400_LDO4_ENA                         0x8000  /* LDO4_ENA */
+#define WM8400_LDO4_ENA_MASK                    0x8000  /* LDO4_ENA */
+#define WM8400_LDO4_ENA_SHIFT                       15  /* LDO4_ENA */
+#define WM8400_LDO4_ENA_WIDTH                        1  /* LDO4_ENA */
+#define WM8400_LDO4_SWI                         0x4000  /* LDO4_SWI */
+#define WM8400_LDO4_SWI_MASK                    0x4000  /* LDO4_SWI */
+#define WM8400_LDO4_SWI_SHIFT                       14  /* LDO4_SWI */
+#define WM8400_LDO4_SWI_WIDTH                        1  /* LDO4_SWI */
+#define WM8400_LDO4_OPFLT                       0x1000  /* LDO4_OPFLT */
+#define WM8400_LDO4_OPFLT_MASK                  0x1000  /* LDO4_OPFLT */
+#define WM8400_LDO4_OPFLT_SHIFT                     12  /* LDO4_OPFLT */
+#define WM8400_LDO4_OPFLT_WIDTH                      1  /* LDO4_OPFLT */
+#define WM8400_LDO4_ERRACT                      0x0800  /* LDO4_ERRACT */
+#define WM8400_LDO4_ERRACT_MASK                 0x0800  /* LDO4_ERRACT */
+#define WM8400_LDO4_ERRACT_SHIFT                    11  /* LDO4_ERRACT */
+#define WM8400_LDO4_ERRACT_WIDTH                     1  /* LDO4_ERRACT */
+#define WM8400_LDO4_HIB_MODE                    0x0400  /* LDO4_HIB_MODE */
+#define WM8400_LDO4_HIB_MODE_MASK               0x0400  /* LDO4_HIB_MODE */
+#define WM8400_LDO4_HIB_MODE_SHIFT                  10  /* LDO4_HIB_MODE */
+#define WM8400_LDO4_HIB_MODE_WIDTH                   1  /* LDO4_HIB_MODE */
+#define WM8400_LDO4_VIMG_MASK                   0x03E0  /* LDO4_VIMG - [9:5] */
+#define WM8400_LDO4_VIMG_SHIFT                       5  /* LDO4_VIMG - [9:5] */
+#define WM8400_LDO4_VIMG_WIDTH                       5  /* LDO4_VIMG - [9:5] */
+#define WM8400_LDO4_VSEL_MASK                   0x001F  /* LDO4_VSEL - [4:0] */
+#define WM8400_LDO4_VSEL_SHIFT                       0  /* LDO4_VSEL - [4:0] */
+#define WM8400_LDO4_VSEL_WIDTH                       5  /* LDO4_VSEL - [4:0] */
+
+/*
+ * R70 (0x46) - DCDC1 Control 1
+ */
+#define WM8400_DC1_ENA                          0x8000  /* DC1_ENA */
+#define WM8400_DC1_ENA_MASK                     0x8000  /* DC1_ENA */
+#define WM8400_DC1_ENA_SHIFT                        15  /* DC1_ENA */
+#define WM8400_DC1_ENA_WIDTH                         1  /* DC1_ENA */
+#define WM8400_DC1_ACTIVE                       0x4000  /* DC1_ACTIVE */
+#define WM8400_DC1_ACTIVE_MASK                  0x4000  /* DC1_ACTIVE */
+#define WM8400_DC1_ACTIVE_SHIFT                     14  /* DC1_ACTIVE */
+#define WM8400_DC1_ACTIVE_WIDTH                      1  /* DC1_ACTIVE */
+#define WM8400_DC1_SLEEP                        0x2000  /* DC1_SLEEP */
+#define WM8400_DC1_SLEEP_MASK                   0x2000  /* DC1_SLEEP */
+#define WM8400_DC1_SLEEP_SHIFT                      13  /* DC1_SLEEP */
+#define WM8400_DC1_SLEEP_WIDTH                       1  /* DC1_SLEEP */
+#define WM8400_DC1_OPFLT                        0x1000  /* DC1_OPFLT */
+#define WM8400_DC1_OPFLT_MASK                   0x1000  /* DC1_OPFLT */
+#define WM8400_DC1_OPFLT_SHIFT                      12  /* DC1_OPFLT */
+#define WM8400_DC1_OPFLT_WIDTH                       1  /* DC1_OPFLT */
+#define WM8400_DC1_ERRACT                       0x0800  /* DC1_ERRACT */
+#define WM8400_DC1_ERRACT_MASK                  0x0800  /* DC1_ERRACT */
+#define WM8400_DC1_ERRACT_SHIFT                     11  /* DC1_ERRACT */
+#define WM8400_DC1_ERRACT_WIDTH                      1  /* DC1_ERRACT */
+#define WM8400_DC1_HIB_MODE                     0x0400  /* DC1_HIB_MODE */
+#define WM8400_DC1_HIB_MODE_MASK                0x0400  /* DC1_HIB_MODE */
+#define WM8400_DC1_HIB_MODE_SHIFT                   10  /* DC1_HIB_MODE */
+#define WM8400_DC1_HIB_MODE_WIDTH                    1  /* DC1_HIB_MODE */
+#define WM8400_DC1_SOFTST_MASK                  0x0300  /* DC1_SOFTST - [9:8] */
+#define WM8400_DC1_SOFTST_SHIFT                      8  /* DC1_SOFTST - [9:8] */
+#define WM8400_DC1_SOFTST_WIDTH                      2  /* DC1_SOFTST - [9:8] */
+#define WM8400_DC1_OV_PROT                      0x0080  /* DC1_OV_PROT */
+#define WM8400_DC1_OV_PROT_MASK                 0x0080  /* DC1_OV_PROT */
+#define WM8400_DC1_OV_PROT_SHIFT                     7  /* DC1_OV_PROT */
+#define WM8400_DC1_OV_PROT_WIDTH                     1  /* DC1_OV_PROT */
+#define WM8400_DC1_VSEL_MASK                    0x007F  /* DC1_VSEL - [6:0] */
+#define WM8400_DC1_VSEL_SHIFT                        0  /* DC1_VSEL - [6:0] */
+#define WM8400_DC1_VSEL_WIDTH                        7  /* DC1_VSEL - [6:0] */
+
+/*
+ * R71 (0x47) - DCDC1 Control 2
+ */
+#define WM8400_DC1_FRC_PWM                      0x2000  /* DC1_FRC_PWM */
+#define WM8400_DC1_FRC_PWM_MASK                 0x2000  /* DC1_FRC_PWM */
+#define WM8400_DC1_FRC_PWM_SHIFT                    13  /* DC1_FRC_PWM */
+#define WM8400_DC1_FRC_PWM_WIDTH                     1  /* DC1_FRC_PWM */
+#define WM8400_DC1_STBY_LIM_MASK                0x0300  /* DC1_STBY_LIM - [9:8] */
+#define WM8400_DC1_STBY_LIM_SHIFT                    8  /* DC1_STBY_LIM - [9:8] */
+#define WM8400_DC1_STBY_LIM_WIDTH                    2  /* DC1_STBY_LIM - [9:8] */
+#define WM8400_DC1_ACT_LIM                      0x0080  /* DC1_ACT_LIM */
+#define WM8400_DC1_ACT_LIM_MASK                 0x0080  /* DC1_ACT_LIM */
+#define WM8400_DC1_ACT_LIM_SHIFT                     7  /* DC1_ACT_LIM */
+#define WM8400_DC1_ACT_LIM_WIDTH                     1  /* DC1_ACT_LIM */
+#define WM8400_DC1_VIMG_MASK                    0x007F  /* DC1_VIMG - [6:0] */
+#define WM8400_DC1_VIMG_SHIFT                        0  /* DC1_VIMG - [6:0] */
+#define WM8400_DC1_VIMG_WIDTH                        7  /* DC1_VIMG - [6:0] */
+
+/*
+ * R72 (0x48) - DCDC2 Control 1
+ */
+#define WM8400_DC2_ENA                          0x8000  /* DC2_ENA */
+#define WM8400_DC2_ENA_MASK                     0x8000  /* DC2_ENA */
+#define WM8400_DC2_ENA_SHIFT                        15  /* DC2_ENA */
+#define WM8400_DC2_ENA_WIDTH                         1  /* DC2_ENA */
+#define WM8400_DC2_ACTIVE                       0x4000  /* DC2_ACTIVE */
+#define WM8400_DC2_ACTIVE_MASK                  0x4000  /* DC2_ACTIVE */
+#define WM8400_DC2_ACTIVE_SHIFT                     14  /* DC2_ACTIVE */
+#define WM8400_DC2_ACTIVE_WIDTH                      1  /* DC2_ACTIVE */
+#define WM8400_DC2_SLEEP                        0x2000  /* DC2_SLEEP */
+#define WM8400_DC2_SLEEP_MASK                   0x2000  /* DC2_SLEEP */
+#define WM8400_DC2_SLEEP_SHIFT                      13  /* DC2_SLEEP */
+#define WM8400_DC2_SLEEP_WIDTH                       1  /* DC2_SLEEP */
+#define WM8400_DC2_OPFLT                        0x1000  /* DC2_OPFLT */
+#define WM8400_DC2_OPFLT_MASK                   0x1000  /* DC2_OPFLT */
+#define WM8400_DC2_OPFLT_SHIFT                      12  /* DC2_OPFLT */
+#define WM8400_DC2_OPFLT_WIDTH                       1  /* DC2_OPFLT */
+#define WM8400_DC2_ERRACT                       0x0800  /* DC2_ERRACT */
+#define WM8400_DC2_ERRACT_MASK                  0x0800  /* DC2_ERRACT */
+#define WM8400_DC2_ERRACT_SHIFT                     11  /* DC2_ERRACT */
+#define WM8400_DC2_ERRACT_WIDTH                      1  /* DC2_ERRACT */
+#define WM8400_DC2_HIB_MODE                     0x0400  /* DC2_HIB_MODE */
+#define WM8400_DC2_HIB_MODE_MASK                0x0400  /* DC2_HIB_MODE */
+#define WM8400_DC2_HIB_MODE_SHIFT                   10  /* DC2_HIB_MODE */
+#define WM8400_DC2_HIB_MODE_WIDTH                    1  /* DC2_HIB_MODE */
+#define WM8400_DC2_SOFTST_MASK                  0x0300  /* DC2_SOFTST - [9:8] */
+#define WM8400_DC2_SOFTST_SHIFT                      8  /* DC2_SOFTST - [9:8] */
+#define WM8400_DC2_SOFTST_WIDTH                      2  /* DC2_SOFTST - [9:8] */
+#define WM8400_DC2_OV_PROT                      0x0080  /* DC2_OV_PROT */
+#define WM8400_DC2_OV_PROT_MASK                 0x0080  /* DC2_OV_PROT */
+#define WM8400_DC2_OV_PROT_SHIFT                     7  /* DC2_OV_PROT */
+#define WM8400_DC2_OV_PROT_WIDTH                     1  /* DC2_OV_PROT */
+#define WM8400_DC2_VSEL_MASK                    0x007F  /* DC2_VSEL - [6:0] */
+#define WM8400_DC2_VSEL_SHIFT                        0  /* DC2_VSEL - [6:0] */
+#define WM8400_DC2_VSEL_WIDTH                        7  /* DC2_VSEL - [6:0] */
+
+/*
+ * R73 (0x49) - DCDC2 Control 2
+ */
+#define WM8400_DC2_FRC_PWM                      0x2000  /* DC2_FRC_PWM */
+#define WM8400_DC2_FRC_PWM_MASK                 0x2000  /* DC2_FRC_PWM */
+#define WM8400_DC2_FRC_PWM_SHIFT                    13  /* DC2_FRC_PWM */
+#define WM8400_DC2_FRC_PWM_WIDTH                     1  /* DC2_FRC_PWM */
+#define WM8400_DC2_STBY_LIM_MASK                0x0300  /* DC2_STBY_LIM - [9:8] */
+#define WM8400_DC2_STBY_LIM_SHIFT                    8  /* DC2_STBY_LIM - [9:8] */
+#define WM8400_DC2_STBY_LIM_WIDTH                    2  /* DC2_STBY_LIM - [9:8] */
+#define WM8400_DC2_ACT_LIM                      0x0080  /* DC2_ACT_LIM */
+#define WM8400_DC2_ACT_LIM_MASK                 0x0080  /* DC2_ACT_LIM */
+#define WM8400_DC2_ACT_LIM_SHIFT                     7  /* DC2_ACT_LIM */
+#define WM8400_DC2_ACT_LIM_WIDTH                     1  /* DC2_ACT_LIM */
+#define WM8400_DC2_VIMG_MASK                    0x007F  /* DC2_VIMG - [6:0] */
+#define WM8400_DC2_VIMG_SHIFT                        0  /* DC2_VIMG - [6:0] */
+#define WM8400_DC2_VIMG_WIDTH                        7  /* DC2_VIMG - [6:0] */
+
+/*
+ * R75 (0x4B) - Interface
+ */
+#define WM8400_AUTOINC                          0x0008  /* AUTOINC */
+#define WM8400_AUTOINC_MASK                     0x0008  /* AUTOINC */
+#define WM8400_AUTOINC_SHIFT                         3  /* AUTOINC */
+#define WM8400_AUTOINC_WIDTH                         1  /* AUTOINC */
+#define WM8400_ARA_ENA                          0x0004  /* ARA_ENA */
+#define WM8400_ARA_ENA_MASK                     0x0004  /* ARA_ENA */
+#define WM8400_ARA_ENA_SHIFT                         2  /* ARA_ENA */
+#define WM8400_ARA_ENA_WIDTH                         1  /* ARA_ENA */
+#define WM8400_SPI_CFG                          0x0002  /* SPI_CFG */
+#define WM8400_SPI_CFG_MASK                     0x0002  /* SPI_CFG */
+#define WM8400_SPI_CFG_SHIFT                         1  /* SPI_CFG */
+#define WM8400_SPI_CFG_WIDTH                         1  /* SPI_CFG */
+
+/*
+ * R76 (0x4C) - PM GENERAL
+ */
+#define WM8400_CODEC_SOFTST                     0x8000  /* CODEC_SOFTST */
+#define WM8400_CODEC_SOFTST_MASK                0x8000  /* CODEC_SOFTST */
+#define WM8400_CODEC_SOFTST_SHIFT                   15  /* CODEC_SOFTST */
+#define WM8400_CODEC_SOFTST_WIDTH                    1  /* CODEC_SOFTST */
+#define WM8400_CODEC_SOFTSD                     0x4000  /* CODEC_SOFTSD */
+#define WM8400_CODEC_SOFTSD_MASK                0x4000  /* CODEC_SOFTSD */
+#define WM8400_CODEC_SOFTSD_SHIFT                   14  /* CODEC_SOFTSD */
+#define WM8400_CODEC_SOFTSD_WIDTH                    1  /* CODEC_SOFTSD */
+#define WM8400_CHIP_SOFTSD                      0x2000  /* CHIP_SOFTSD */
+#define WM8400_CHIP_SOFTSD_MASK                 0x2000  /* CHIP_SOFTSD */
+#define WM8400_CHIP_SOFTSD_SHIFT                    13  /* CHIP_SOFTSD */
+#define WM8400_CHIP_SOFTSD_WIDTH                     1  /* CHIP_SOFTSD */
+#define WM8400_DSLEEP1_POL                      0x0008  /* DSLEEP1_POL */
+#define WM8400_DSLEEP1_POL_MASK                 0x0008  /* DSLEEP1_POL */
+#define WM8400_DSLEEP1_POL_SHIFT                     3  /* DSLEEP1_POL */
+#define WM8400_DSLEEP1_POL_WIDTH                     1  /* DSLEEP1_POL */
+#define WM8400_DSLEEP2_POL                      0x0004  /* DSLEEP2_POL */
+#define WM8400_DSLEEP2_POL_MASK                 0x0004  /* DSLEEP2_POL */
+#define WM8400_DSLEEP2_POL_SHIFT                     2  /* DSLEEP2_POL */
+#define WM8400_DSLEEP2_POL_WIDTH                     1  /* DSLEEP2_POL */
+#define WM8400_PWR_STATE_MASK                   0x0003  /* PWR_STATE - [1:0] */
+#define WM8400_PWR_STATE_SHIFT                       0  /* PWR_STATE - [1:0] */
+#define WM8400_PWR_STATE_WIDTH                       2  /* PWR_STATE - [1:0] */
+
+/*
+ * R78 (0x4E) - PM Shutdown Control
+ */
+#define WM8400_CHIP_GT150_ERRACT                0x0200  /* CHIP_GT150_ERRACT */
+#define WM8400_CHIP_GT150_ERRACT_MASK           0x0200  /* CHIP_GT150_ERRACT */
+#define WM8400_CHIP_GT150_ERRACT_SHIFT               9  /* CHIP_GT150_ERRACT */
+#define WM8400_CHIP_GT150_ERRACT_WIDTH               1  /* CHIP_GT150_ERRACT */
+#define WM8400_CHIP_GT115_ERRACT                0x0100  /* CHIP_GT115_ERRACT */
+#define WM8400_CHIP_GT115_ERRACT_MASK           0x0100  /* CHIP_GT115_ERRACT */
+#define WM8400_CHIP_GT115_ERRACT_SHIFT               8  /* CHIP_GT115_ERRACT */
+#define WM8400_CHIP_GT115_ERRACT_WIDTH               1  /* CHIP_GT115_ERRACT */
+#define WM8400_LINE_CMP_ERRACT                  0x0080  /* LINE_CMP_ERRACT */
+#define WM8400_LINE_CMP_ERRACT_MASK             0x0080  /* LINE_CMP_ERRACT */
+#define WM8400_LINE_CMP_ERRACT_SHIFT                 7  /* LINE_CMP_ERRACT */
+#define WM8400_LINE_CMP_ERRACT_WIDTH                 1  /* LINE_CMP_ERRACT */
+#define WM8400_UVLO_ERRACT                      0x0040  /* UVLO_ERRACT */
+#define WM8400_UVLO_ERRACT_MASK                 0x0040  /* UVLO_ERRACT */
+#define WM8400_UVLO_ERRACT_SHIFT                     6  /* UVLO_ERRACT */
+#define WM8400_UVLO_ERRACT_WIDTH                     1  /* UVLO_ERRACT */
+
+/*
+ * R79 (0x4F) - Interrupt Status 1
+ */
+#define WM8400_MICD_CINT                        0x8000  /* MICD_CINT */
+#define WM8400_MICD_CINT_MASK                   0x8000  /* MICD_CINT */
+#define WM8400_MICD_CINT_SHIFT                      15  /* MICD_CINT */
+#define WM8400_MICD_CINT_WIDTH                       1  /* MICD_CINT */
+#define WM8400_MICSCD_CINT                      0x4000  /* MICSCD_CINT */
+#define WM8400_MICSCD_CINT_MASK                 0x4000  /* MICSCD_CINT */
+#define WM8400_MICSCD_CINT_SHIFT                    14  /* MICSCD_CINT */
+#define WM8400_MICSCD_CINT_WIDTH                     1  /* MICSCD_CINT */
+#define WM8400_JDL_CINT                         0x2000  /* JDL_CINT */
+#define WM8400_JDL_CINT_MASK                    0x2000  /* JDL_CINT */
+#define WM8400_JDL_CINT_SHIFT                       13  /* JDL_CINT */
+#define WM8400_JDL_CINT_WIDTH                        1  /* JDL_CINT */
+#define WM8400_JDR_CINT                         0x1000  /* JDR_CINT */
+#define WM8400_JDR_CINT_MASK                    0x1000  /* JDR_CINT */
+#define WM8400_JDR_CINT_SHIFT                       12  /* JDR_CINT */
+#define WM8400_JDR_CINT_WIDTH                        1  /* JDR_CINT */
+#define WM8400_CODEC_SEQ_END_EINT               0x0800  /* CODEC_SEQ_END_EINT */
+#define WM8400_CODEC_SEQ_END_EINT_MASK          0x0800  /* CODEC_SEQ_END_EINT */
+#define WM8400_CODEC_SEQ_END_EINT_SHIFT             11  /* CODEC_SEQ_END_EINT */
+#define WM8400_CODEC_SEQ_END_EINT_WIDTH              1  /* CODEC_SEQ_END_EINT */
+#define WM8400_CDEL_TO_EINT                     0x0400  /* CDEL_TO_EINT */
+#define WM8400_CDEL_TO_EINT_MASK                0x0400  /* CDEL_TO_EINT */
+#define WM8400_CDEL_TO_EINT_SHIFT                   10  /* CDEL_TO_EINT */
+#define WM8400_CDEL_TO_EINT_WIDTH                    1  /* CDEL_TO_EINT */
+#define WM8400_CHIP_GT150_EINT                  0x0200  /* CHIP_GT150_EINT */
+#define WM8400_CHIP_GT150_EINT_MASK             0x0200  /* CHIP_GT150_EINT */
+#define WM8400_CHIP_GT150_EINT_SHIFT                 9  /* CHIP_GT150_EINT */
+#define WM8400_CHIP_GT150_EINT_WIDTH                 1  /* CHIP_GT150_EINT */
+#define WM8400_CHIP_GT115_EINT                  0x0100  /* CHIP_GT115_EINT */
+#define WM8400_CHIP_GT115_EINT_MASK             0x0100  /* CHIP_GT115_EINT */
+#define WM8400_CHIP_GT115_EINT_SHIFT                 8  /* CHIP_GT115_EINT */
+#define WM8400_CHIP_GT115_EINT_WIDTH                 1  /* CHIP_GT115_EINT */
+#define WM8400_LINE_CMP_EINT                    0x0080  /* LINE_CMP_EINT */
+#define WM8400_LINE_CMP_EINT_MASK               0x0080  /* LINE_CMP_EINT */
+#define WM8400_LINE_CMP_EINT_SHIFT                   7  /* LINE_CMP_EINT */
+#define WM8400_LINE_CMP_EINT_WIDTH                   1  /* LINE_CMP_EINT */
+#define WM8400_UVLO_EINT                        0x0040  /* UVLO_EINT */
+#define WM8400_UVLO_EINT_MASK                   0x0040  /* UVLO_EINT */
+#define WM8400_UVLO_EINT_SHIFT                       6  /* UVLO_EINT */
+#define WM8400_UVLO_EINT_WIDTH                       1  /* UVLO_EINT */
+#define WM8400_DC2_UV_EINT                      0x0020  /* DC2_UV_EINT */
+#define WM8400_DC2_UV_EINT_MASK                 0x0020  /* DC2_UV_EINT */
+#define WM8400_DC2_UV_EINT_SHIFT                     5  /* DC2_UV_EINT */
+#define WM8400_DC2_UV_EINT_WIDTH                     1  /* DC2_UV_EINT */
+#define WM8400_DC1_UV_EINT                      0x0010  /* DC1_UV_EINT */
+#define WM8400_DC1_UV_EINT_MASK                 0x0010  /* DC1_UV_EINT */
+#define WM8400_DC1_UV_EINT_SHIFT                     4  /* DC1_UV_EINT */
+#define WM8400_DC1_UV_EINT_WIDTH                     1  /* DC1_UV_EINT */
+#define WM8400_LDO4_UV_EINT                     0x0008  /* LDO4_UV_EINT */
+#define WM8400_LDO4_UV_EINT_MASK                0x0008  /* LDO4_UV_EINT */
+#define WM8400_LDO4_UV_EINT_SHIFT                    3  /* LDO4_UV_EINT */
+#define WM8400_LDO4_UV_EINT_WIDTH                    1  /* LDO4_UV_EINT */
+#define WM8400_LDO3_UV_EINT                     0x0004  /* LDO3_UV_EINT */
+#define WM8400_LDO3_UV_EINT_MASK                0x0004  /* LDO3_UV_EINT */
+#define WM8400_LDO3_UV_EINT_SHIFT                    2  /* LDO3_UV_EINT */
+#define WM8400_LDO3_UV_EINT_WIDTH                    1  /* LDO3_UV_EINT */
+#define WM8400_LDO2_UV_EINT                     0x0002  /* LDO2_UV_EINT */
+#define WM8400_LDO2_UV_EINT_MASK                0x0002  /* LDO2_UV_EINT */
+#define WM8400_LDO2_UV_EINT_SHIFT                    1  /* LDO2_UV_EINT */
+#define WM8400_LDO2_UV_EINT_WIDTH                    1  /* LDO2_UV_EINT */
+#define WM8400_LDO1_UV_EINT                     0x0001  /* LDO1_UV_EINT */
+#define WM8400_LDO1_UV_EINT_MASK                0x0001  /* LDO1_UV_EINT */
+#define WM8400_LDO1_UV_EINT_SHIFT                    0  /* LDO1_UV_EINT */
+#define WM8400_LDO1_UV_EINT_WIDTH                    1  /* LDO1_UV_EINT */
+
+/*
+ * R80 (0x50) - Interrupt Status 1 Mask
+ */
+#define WM8400_IM_MICD_CINT                     0x8000  /* IM_MICD_CINT */
+#define WM8400_IM_MICD_CINT_MASK                0x8000  /* IM_MICD_CINT */
+#define WM8400_IM_MICD_CINT_SHIFT                   15  /* IM_MICD_CINT */
+#define WM8400_IM_MICD_CINT_WIDTH                    1  /* IM_MICD_CINT */
+#define WM8400_IM_MICSCD_CINT                   0x4000  /* IM_MICSCD_CINT */
+#define WM8400_IM_MICSCD_CINT_MASK              0x4000  /* IM_MICSCD_CINT */
+#define WM8400_IM_MICSCD_CINT_SHIFT                 14  /* IM_MICSCD_CINT */
+#define WM8400_IM_MICSCD_CINT_WIDTH                  1  /* IM_MICSCD_CINT */
+#define WM8400_IM_JDL_CINT                      0x2000  /* IM_JDL_CINT */
+#define WM8400_IM_JDL_CINT_MASK                 0x2000  /* IM_JDL_CINT */
+#define WM8400_IM_JDL_CINT_SHIFT                    13  /* IM_JDL_CINT */
+#define WM8400_IM_JDL_CINT_WIDTH                     1  /* IM_JDL_CINT */
+#define WM8400_IM_JDR_CINT                      0x1000  /* IM_JDR_CINT */
+#define WM8400_IM_JDR_CINT_MASK                 0x1000  /* IM_JDR_CINT */
+#define WM8400_IM_JDR_CINT_SHIFT                    12  /* IM_JDR_CINT */
+#define WM8400_IM_JDR_CINT_WIDTH                     1  /* IM_JDR_CINT */
+#define WM8400_IM_CODEC_SEQ_END_EINT            0x0800  /* IM_CODEC_SEQ_END_EINT */
+#define WM8400_IM_CODEC_SEQ_END_EINT_MASK       0x0800  /* IM_CODEC_SEQ_END_EINT */
+#define WM8400_IM_CODEC_SEQ_END_EINT_SHIFT          11  /* IM_CODEC_SEQ_END_EINT */
+#define WM8400_IM_CODEC_SEQ_END_EINT_WIDTH           1  /* IM_CODEC_SEQ_END_EINT */
+#define WM8400_IM_CDEL_TO_EINT                  0x0400  /* IM_CDEL_TO_EINT */
+#define WM8400_IM_CDEL_TO_EINT_MASK             0x0400  /* IM_CDEL_TO_EINT */
+#define WM8400_IM_CDEL_TO_EINT_SHIFT                10  /* IM_CDEL_TO_EINT */
+#define WM8400_IM_CDEL_TO_EINT_WIDTH                 1  /* IM_CDEL_TO_EINT */
+#define WM8400_IM_CHIP_GT150_EINT               0x0200  /* IM_CHIP_GT150_EINT */
+#define WM8400_IM_CHIP_GT150_EINT_MASK          0x0200  /* IM_CHIP_GT150_EINT */
+#define WM8400_IM_CHIP_GT150_EINT_SHIFT              9  /* IM_CHIP_GT150_EINT */
+#define WM8400_IM_CHIP_GT150_EINT_WIDTH              1  /* IM_CHIP_GT150_EINT */
+#define WM8400_IM_CHIP_GT115_EINT               0x0100  /* IM_CHIP_GT115_EINT */
+#define WM8400_IM_CHIP_GT115_EINT_MASK          0x0100  /* IM_CHIP_GT115_EINT */
+#define WM8400_IM_CHIP_GT115_EINT_SHIFT              8  /* IM_CHIP_GT115_EINT */
+#define WM8400_IM_CHIP_GT115_EINT_WIDTH              1  /* IM_CHIP_GT115_EINT */
+#define WM8400_IM_LINE_CMP_EINT                 0x0080  /* IM_LINE_CMP_EINT */
+#define WM8400_IM_LINE_CMP_EINT_MASK            0x0080  /* IM_LINE_CMP_EINT */
+#define WM8400_IM_LINE_CMP_EINT_SHIFT                7  /* IM_LINE_CMP_EINT */
+#define WM8400_IM_LINE_CMP_EINT_WIDTH                1  /* IM_LINE_CMP_EINT */
+#define WM8400_IM_UVLO_EINT                     0x0040  /* IM_UVLO_EINT */
+#define WM8400_IM_UVLO_EINT_MASK                0x0040  /* IM_UVLO_EINT */
+#define WM8400_IM_UVLO_EINT_SHIFT                    6  /* IM_UVLO_EINT */
+#define WM8400_IM_UVLO_EINT_WIDTH                    1  /* IM_UVLO_EINT */
+#define WM8400_IM_DC2_UV_EINT                   0x0020  /* IM_DC2_UV_EINT */
+#define WM8400_IM_DC2_UV_EINT_MASK              0x0020  /* IM_DC2_UV_EINT */
+#define WM8400_IM_DC2_UV_EINT_SHIFT                  5  /* IM_DC2_UV_EINT */
+#define WM8400_IM_DC2_UV_EINT_WIDTH                  1  /* IM_DC2_UV_EINT */
+#define WM8400_IM_DC1_UV_EINT                   0x0010  /* IM_DC1_UV_EINT */
+#define WM8400_IM_DC1_UV_EINT_MASK              0x0010  /* IM_DC1_UV_EINT */
+#define WM8400_IM_DC1_UV_EINT_SHIFT                  4  /* IM_DC1_UV_EINT */
+#define WM8400_IM_DC1_UV_EINT_WIDTH                  1  /* IM_DC1_UV_EINT */
+#define WM8400_IM_LDO4_UV_EINT                  0x0008  /* IM_LDO4_UV_EINT */
+#define WM8400_IM_LDO4_UV_EINT_MASK             0x0008  /* IM_LDO4_UV_EINT */
+#define WM8400_IM_LDO4_UV_EINT_SHIFT                 3  /* IM_LDO4_UV_EINT */
+#define WM8400_IM_LDO4_UV_EINT_WIDTH                 1  /* IM_LDO4_UV_EINT */
+#define WM8400_IM_LDO3_UV_EINT                  0x0004  /* IM_LDO3_UV_EINT */
+#define WM8400_IM_LDO3_UV_EINT_MASK             0x0004  /* IM_LDO3_UV_EINT */
+#define WM8400_IM_LDO3_UV_EINT_SHIFT                 2  /* IM_LDO3_UV_EINT */
+#define WM8400_IM_LDO3_UV_EINT_WIDTH                 1  /* IM_LDO3_UV_EINT */
+#define WM8400_IM_LDO2_UV_EINT                  0x0002  /* IM_LDO2_UV_EINT */
+#define WM8400_IM_LDO2_UV_EINT_MASK             0x0002  /* IM_LDO2_UV_EINT */
+#define WM8400_IM_LDO2_UV_EINT_SHIFT                 1  /* IM_LDO2_UV_EINT */
+#define WM8400_IM_LDO2_UV_EINT_WIDTH                 1  /* IM_LDO2_UV_EINT */
+#define WM8400_IM_LDO1_UV_EINT                  0x0001  /* IM_LDO1_UV_EINT */
+#define WM8400_IM_LDO1_UV_EINT_MASK             0x0001  /* IM_LDO1_UV_EINT */
+#define WM8400_IM_LDO1_UV_EINT_SHIFT                 0  /* IM_LDO1_UV_EINT */
+#define WM8400_IM_LDO1_UV_EINT_WIDTH                 1  /* IM_LDO1_UV_EINT */
+
+/*
+ * R81 (0x51) - Interrupt Levels
+ */
+#define WM8400_MICD_LVL                         0x8000  /* MICD_LVL */
+#define WM8400_MICD_LVL_MASK                    0x8000  /* MICD_LVL */
+#define WM8400_MICD_LVL_SHIFT                       15  /* MICD_LVL */
+#define WM8400_MICD_LVL_WIDTH                        1  /* MICD_LVL */
+#define WM8400_MICSCD_LVL                       0x4000  /* MICSCD_LVL */
+#define WM8400_MICSCD_LVL_MASK                  0x4000  /* MICSCD_LVL */
+#define WM8400_MICSCD_LVL_SHIFT                     14  /* MICSCD_LVL */
+#define WM8400_MICSCD_LVL_WIDTH                      1  /* MICSCD_LVL */
+#define WM8400_JDL_LVL                          0x2000  /* JDL_LVL */
+#define WM8400_JDL_LVL_MASK                     0x2000  /* JDL_LVL */
+#define WM8400_JDL_LVL_SHIFT                        13  /* JDL_LVL */
+#define WM8400_JDL_LVL_WIDTH                         1  /* JDL_LVL */
+#define WM8400_JDR_LVL                          0x1000  /* JDR_LVL */
+#define WM8400_JDR_LVL_MASK                     0x1000  /* JDR_LVL */
+#define WM8400_JDR_LVL_SHIFT                        12  /* JDR_LVL */
+#define WM8400_JDR_LVL_WIDTH                         1  /* JDR_LVL */
+#define WM8400_CODEC_SEQ_END_LVL                0x0800  /* CODEC_SEQ_END_LVL */
+#define WM8400_CODEC_SEQ_END_LVL_MASK           0x0800  /* CODEC_SEQ_END_LVL */
+#define WM8400_CODEC_SEQ_END_LVL_SHIFT              11  /* CODEC_SEQ_END_LVL */
+#define WM8400_CODEC_SEQ_END_LVL_WIDTH               1  /* CODEC_SEQ_END_LVL */
+#define WM8400_CDEL_TO_LVL                      0x0400  /* CDEL_TO_LVL */
+#define WM8400_CDEL_TO_LVL_MASK                 0x0400  /* CDEL_TO_LVL */
+#define WM8400_CDEL_TO_LVL_SHIFT                    10  /* CDEL_TO_LVL */
+#define WM8400_CDEL_TO_LVL_WIDTH                     1  /* CDEL_TO_LVL */
+#define WM8400_CHIP_GT150_LVL                   0x0200  /* CHIP_GT150_LVL */
+#define WM8400_CHIP_GT150_LVL_MASK              0x0200  /* CHIP_GT150_LVL */
+#define WM8400_CHIP_GT150_LVL_SHIFT                  9  /* CHIP_GT150_LVL */
+#define WM8400_CHIP_GT150_LVL_WIDTH                  1  /* CHIP_GT150_LVL */
+#define WM8400_CHIP_GT115_LVL                   0x0100  /* CHIP_GT115_LVL */
+#define WM8400_CHIP_GT115_LVL_MASK              0x0100  /* CHIP_GT115_LVL */
+#define WM8400_CHIP_GT115_LVL_SHIFT                  8  /* CHIP_GT115_LVL */
+#define WM8400_CHIP_GT115_LVL_WIDTH                  1  /* CHIP_GT115_LVL */
+#define WM8400_LINE_CMP_LVL                     0x0080  /* LINE_CMP_LVL */
+#define WM8400_LINE_CMP_LVL_MASK                0x0080  /* LINE_CMP_LVL */
+#define WM8400_LINE_CMP_LVL_SHIFT                    7  /* LINE_CMP_LVL */
+#define WM8400_LINE_CMP_LVL_WIDTH                    1  /* LINE_CMP_LVL */
+#define WM8400_UVLO_LVL                         0x0040  /* UVLO_LVL */
+#define WM8400_UVLO_LVL_MASK                    0x0040  /* UVLO_LVL */
+#define WM8400_UVLO_LVL_SHIFT                        6  /* UVLO_LVL */
+#define WM8400_UVLO_LVL_WIDTH                        1  /* UVLO_LVL */
+#define WM8400_DC2_UV_LVL                       0x0020  /* DC2_UV_LVL */
+#define WM8400_DC2_UV_LVL_MASK                  0x0020  /* DC2_UV_LVL */
+#define WM8400_DC2_UV_LVL_SHIFT                      5  /* DC2_UV_LVL */
+#define WM8400_DC2_UV_LVL_WIDTH                      1  /* DC2_UV_LVL */
+#define WM8400_DC1_UV_LVL                       0x0010  /* DC1_UV_LVL */
+#define WM8400_DC1_UV_LVL_MASK                  0x0010  /* DC1_UV_LVL */
+#define WM8400_DC1_UV_LVL_SHIFT                      4  /* DC1_UV_LVL */
+#define WM8400_DC1_UV_LVL_WIDTH                      1  /* DC1_UV_LVL */
+#define WM8400_LDO4_UV_LVL                      0x0008  /* LDO4_UV_LVL */
+#define WM8400_LDO4_UV_LVL_MASK                 0x0008  /* LDO4_UV_LVL */
+#define WM8400_LDO4_UV_LVL_SHIFT                     3  /* LDO4_UV_LVL */
+#define WM8400_LDO4_UV_LVL_WIDTH                     1  /* LDO4_UV_LVL */
+#define WM8400_LDO3_UV_LVL                      0x0004  /* LDO3_UV_LVL */
+#define WM8400_LDO3_UV_LVL_MASK                 0x0004  /* LDO3_UV_LVL */
+#define WM8400_LDO3_UV_LVL_SHIFT                     2  /* LDO3_UV_LVL */
+#define WM8400_LDO3_UV_LVL_WIDTH                     1  /* LDO3_UV_LVL */
+#define WM8400_LDO2_UV_LVL                      0x0002  /* LDO2_UV_LVL */
+#define WM8400_LDO2_UV_LVL_MASK                 0x0002  /* LDO2_UV_LVL */
+#define WM8400_LDO2_UV_LVL_SHIFT                     1  /* LDO2_UV_LVL */
+#define WM8400_LDO2_UV_LVL_WIDTH                     1  /* LDO2_UV_LVL */
+#define WM8400_LDO1_UV_LVL                      0x0001  /* LDO1_UV_LVL */
+#define WM8400_LDO1_UV_LVL_MASK                 0x0001  /* LDO1_UV_LVL */
+#define WM8400_LDO1_UV_LVL_SHIFT                     0  /* LDO1_UV_LVL */
+#define WM8400_LDO1_UV_LVL_WIDTH                     1  /* LDO1_UV_LVL */
+
+/*
+ * R82 (0x52) - Shutdown Reason
+ */
+#define WM8400_SDR_CHIP_SOFTSD                  0x2000  /* SDR_CHIP_SOFTSD */
+#define WM8400_SDR_CHIP_SOFTSD_MASK             0x2000  /* SDR_CHIP_SOFTSD */
+#define WM8400_SDR_CHIP_SOFTSD_SHIFT                13  /* SDR_CHIP_SOFTSD */
+#define WM8400_SDR_CHIP_SOFTSD_WIDTH                 1  /* SDR_CHIP_SOFTSD */
+#define WM8400_SDR_NPDN                         0x0800  /* SDR_NPDN */
+#define WM8400_SDR_NPDN_MASK                    0x0800  /* SDR_NPDN */
+#define WM8400_SDR_NPDN_SHIFT                       11  /* SDR_NPDN */
+#define WM8400_SDR_NPDN_WIDTH                        1  /* SDR_NPDN */
+#define WM8400_SDR_CHIP_GT150                   0x0200  /* SDR_CHIP_GT150 */
+#define WM8400_SDR_CHIP_GT150_MASK              0x0200  /* SDR_CHIP_GT150 */
+#define WM8400_SDR_CHIP_GT150_SHIFT                  9  /* SDR_CHIP_GT150 */
+#define WM8400_SDR_CHIP_GT150_WIDTH                  1  /* SDR_CHIP_GT150 */
+#define WM8400_SDR_CHIP_GT115                   0x0100  /* SDR_CHIP_GT115 */
+#define WM8400_SDR_CHIP_GT115_MASK              0x0100  /* SDR_CHIP_GT115 */
+#define WM8400_SDR_CHIP_GT115_SHIFT                  8  /* SDR_CHIP_GT115 */
+#define WM8400_SDR_CHIP_GT115_WIDTH                  1  /* SDR_CHIP_GT115 */
+#define WM8400_SDR_LINE_CMP                     0x0080  /* SDR_LINE_CMP */
+#define WM8400_SDR_LINE_CMP_MASK                0x0080  /* SDR_LINE_CMP */
+#define WM8400_SDR_LINE_CMP_SHIFT                    7  /* SDR_LINE_CMP */
+#define WM8400_SDR_LINE_CMP_WIDTH                    1  /* SDR_LINE_CMP */
+#define WM8400_SDR_UVLO                         0x0040  /* SDR_UVLO */
+#define WM8400_SDR_UVLO_MASK                    0x0040  /* SDR_UVLO */
+#define WM8400_SDR_UVLO_SHIFT                        6  /* SDR_UVLO */
+#define WM8400_SDR_UVLO_WIDTH                        1  /* SDR_UVLO */
+#define WM8400_SDR_DC2_UV                       0x0020  /* SDR_DC2_UV */
+#define WM8400_SDR_DC2_UV_MASK                  0x0020  /* SDR_DC2_UV */
+#define WM8400_SDR_DC2_UV_SHIFT                      5  /* SDR_DC2_UV */
+#define WM8400_SDR_DC2_UV_WIDTH                      1  /* SDR_DC2_UV */
+#define WM8400_SDR_DC1_UV                       0x0010  /* SDR_DC1_UV */
+#define WM8400_SDR_DC1_UV_MASK                  0x0010  /* SDR_DC1_UV */
+#define WM8400_SDR_DC1_UV_SHIFT                      4  /* SDR_DC1_UV */
+#define WM8400_SDR_DC1_UV_WIDTH                      1  /* SDR_DC1_UV */
+#define WM8400_SDR_LDO4_UV                      0x0008  /* SDR_LDO4_UV */
+#define WM8400_SDR_LDO4_UV_MASK                 0x0008  /* SDR_LDO4_UV */
+#define WM8400_SDR_LDO4_UV_SHIFT                     3  /* SDR_LDO4_UV */
+#define WM8400_SDR_LDO4_UV_WIDTH                     1  /* SDR_LDO4_UV */
+#define WM8400_SDR_LDO3_UV                      0x0004  /* SDR_LDO3_UV */
+#define WM8400_SDR_LDO3_UV_MASK                 0x0004  /* SDR_LDO3_UV */
+#define WM8400_SDR_LDO3_UV_SHIFT                     2  /* SDR_LDO3_UV */
+#define WM8400_SDR_LDO3_UV_WIDTH                     1  /* SDR_LDO3_UV */
+#define WM8400_SDR_LDO2_UV                      0x0002  /* SDR_LDO2_UV */
+#define WM8400_SDR_LDO2_UV_MASK                 0x0002  /* SDR_LDO2_UV */
+#define WM8400_SDR_LDO2_UV_SHIFT                     1  /* SDR_LDO2_UV */
+#define WM8400_SDR_LDO2_UV_WIDTH                     1  /* SDR_LDO2_UV */
+#define WM8400_SDR_LDO1_UV                      0x0001  /* SDR_LDO1_UV */
+#define WM8400_SDR_LDO1_UV_MASK                 0x0001  /* SDR_LDO1_UV */
+#define WM8400_SDR_LDO1_UV_SHIFT                     0  /* SDR_LDO1_UV */
+#define WM8400_SDR_LDO1_UV_WIDTH                     1  /* SDR_LDO1_UV */
+
+/*
+ * R84 (0x54) - Line Circuits
+ */
+#define WM8400_BG_LINE_COMP                     0x8000  /* BG_LINE_COMP */
+#define WM8400_BG_LINE_COMP_MASK                0x8000  /* BG_LINE_COMP */
+#define WM8400_BG_LINE_COMP_SHIFT                   15  /* BG_LINE_COMP */
+#define WM8400_BG_LINE_COMP_WIDTH                    1  /* BG_LINE_COMP */
+#define WM8400_LINE_CMP_VTHI_MASK               0x00F0  /* LINE_CMP_VTHI - [7:4] */
+#define WM8400_LINE_CMP_VTHI_SHIFT                   4  /* LINE_CMP_VTHI - [7:4] */
+#define WM8400_LINE_CMP_VTHI_WIDTH                   4  /* LINE_CMP_VTHI - [7:4] */
+#define WM8400_LINE_CMP_VTHD_MASK               0x000F  /* LINE_CMP_VTHD - [3:0] */
+#define WM8400_LINE_CMP_VTHD_SHIFT                   0  /* LINE_CMP_VTHD - [3:0] */
+#define WM8400_LINE_CMP_VTHD_WIDTH                   4  /* LINE_CMP_VTHD - [3:0] */
+
+u16 wm8400_reg_read(struct wm8400 *wm8400, u8 reg);
+int wm8400_block_read(struct wm8400 *wm8400, u8 reg, int count, u16 *data);
+int wm8400_set_bits(struct wm8400 *wm8400, u8 reg, u16 mask, u16 val);
+
+#endif
diff --git a/include/linux/mfd/wm8400.h b/include/linux/mfd/wm8400.h
new file mode 100644
index 000000000000..b46b566ac1ac
--- /dev/null
+++ b/include/linux/mfd/wm8400.h
@@ -0,0 +1,40 @@
+/*
+ * wm8400 client interface
+ *
+ * Copyright 2008 Wolfson Microelectronics plc
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_MFD_WM8400_H
+#define __LINUX_MFD_WM8400_H
+
+#include <linux/regulator/machine.h>
+
+#define WM8400_LDO1  0
+#define WM8400_LDO2  1
+#define WM8400_LDO3  2
+#define WM8400_LDO4  3
+#define WM8400_DCDC1 4
+#define WM8400_DCDC2 5
+
+struct wm8400_platform_data {
+        int (*platform_init)(struct device *dev);
+};
+
+int wm8400_register_regulator(struct device *dev, int reg,
+                              struct regulator_init_data *initdata);
+
+#endif
diff --git a/include/linux/mlx4/device.h b/include/linux/mlx4/device.h
index 655ea0d1ee14..b2f944468313 100644
--- a/include/linux/mlx4/device.h
+++ b/include/linux/mlx4/device.h
@@ -141,6 +141,10 @@ enum {
         MLX4_STAT_RATE_OFFSET   = 5
 };
 
+enum {
+        MLX4_MTT_FLAG_PRESENT           = 1
+};
+
 static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor)
 {
         return (major << 32) | (minor << 16) | subminor;
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 72a15dc26bbf..c61ba10768ea 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -7,6 +7,7 @@
 
 #include <linux/gfp.h>
 #include <linux/list.h>
+#include <linux/mmdebug.h>
 #include <linux/mmzone.h>
 #include <linux/rbtree.h>
 #include <linux/prio_tree.h>
@@ -219,12 +220,6 @@ struct inode;
  */
 #include <linux/page-flags.h>
 
-#ifdef CONFIG_DEBUG_VM
-#define VM_BUG_ON(cond) BUG_ON(cond)
-#else
-#define VM_BUG_ON(condition) do { } while(0)
-#endif
-
 /*
  * Methods to modify the page usage count.
  *
@@ -919,7 +914,7 @@ static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long a
 }
 #endif /* CONFIG_MMU && !__ARCH_HAS_4LEVEL_HACK */
 
-#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+#if USE_SPLIT_PTLOCKS
 /*
  * We tuck a spinlock to guard each pagetable page into its struct page,
  * at page->private, with BUILD_BUG_ON to make sure that this will not
@@ -932,14 +927,14 @@ static inline pmd_t *pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long a
 } while (0)
 #define pte_lock_deinit(page)   ((page)->mapping = NULL)
 #define pte_lockptr(mm, pmd)    ({(void)(mm); __pte_lockptr(pmd_page(*(pmd)));})
-#else
+#else   /* !USE_SPLIT_PTLOCKS */
 /*
  * We use mm->page_table_lock to guard all pagetable pages of the mm.
  */
 #define pte_lock_init(page)     do {} while (0)
 #define pte_lock_deinit(page)   do {} while (0)
 #define pte_lockptr(mm, pmd)    ({(void)(pmd); &(mm)->page_table_lock;})
-#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#endif /* USE_SPLIT_PTLOCKS */
 
 static inline void pgtable_page_ctor(struct page *page)
 {
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index bf334138c7c1..9d49fa36bbef 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -21,11 +21,13 @@
 
 struct address_space;
 
-#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+#define USE_SPLIT_PTLOCKS       (NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS)
+
+#if USE_SPLIT_PTLOCKS
 typedef atomic_long_t mm_counter_t;
-#else  /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#else  /* !USE_SPLIT_PTLOCKS */
 typedef unsigned long mm_counter_t;
-#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#endif /* !USE_SPLIT_PTLOCKS */
 
 /*
  * Each physical page in the system has a struct page associated with
@@ -65,7 +67,7 @@ struct page {
                                                  * see PAGE_MAPPING_ANON below.
                                                  */
             };
-#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+#if USE_SPLIT_PTLOCKS
             spinlock_t ptl;
 #endif
             struct kmem_cache *slab;    /* SLUB: Pointer to slab */
diff --git a/include/linux/mmc/host.h b/include/linux/mmc/host.h
index 9c288c909878..bde891f64591 100644
--- a/include/linux/mmc/host.h
+++ b/include/linux/mmc/host.h
@@ -65,7 +65,7 @@ struct mmc_host_ops {
          *   -ENOSYS when not supported (equal to NULL callback)
          *   or a negative errno value when something bad happened
          *
-         * Return values for the get_ro callback should be:
+         * Return values for the get_cd callback should be:
          *   0 for a absent card
          *   1 for a present card
          *   -ENOSYS when not supported (equal to NULL callback)
diff --git a/include/linux/mmdebug.h b/include/linux/mmdebug.h
new file mode 100644
index 000000000000..8a5509877192
--- /dev/null
+++ b/include/linux/mmdebug.h
@@ -0,0 +1,18 @@
+#ifndef LINUX_MM_DEBUG_H
+#define LINUX_MM_DEBUG_H 1
+
+#include <linux/autoconf.h>
+
+#ifdef CONFIG_DEBUG_VM
+#define VM_BUG_ON(cond) BUG_ON(cond)
+#else
+#define VM_BUG_ON(cond) do { } while (0)
+#endif
+
+#ifdef CONFIG_DEBUG_VIRTUAL
+#define VIRTUAL_BUG_ON(cond) BUG_ON(cond)
+#else
+#define VIRTUAL_BUG_ON(cond) do { } while (0)
+#endif
+
+#endif
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index 443bc7cd8c62..428328a05fa1 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -751,8 +751,9 @@ static inline int zonelist_node_idx(struct zoneref *zoneref)
  *
  * This function returns the next zone at or below a given zone index that is
  * within the allowed nodemask using a cursor as the starting point for the
- * search. The zoneref returned is a cursor that is used as the next starting
- * point for future calls to next_zones_zonelist().
+ * search. The zoneref returned is a cursor that represents the current zone
+ * being examined. It should be advanced by one before calling
+ * next_zones_zonelist again.
  */
 struct zoneref *next_zones_zonelist(struct zoneref *z,
                                         enum zone_type highest_zoneidx,
@@ -768,9 +769,8 @@ struct zoneref *next_zones_zonelist(struct zoneref *z,
  *
  * This function returns the first zone at or below a given zone index that is
  * within the allowed nodemask. The zoneref returned is a cursor that can be
- * used to iterate the zonelist with next_zones_zonelist. The cursor should
- * not be used by the caller as it does not match the value of the zone
- * returned.
+ * used to iterate the zonelist with next_zones_zonelist by advancing it by
+ * one before calling.
  */
 static inline struct zoneref *first_zones_zonelist(struct zonelist *zonelist,
                                         enum zone_type highest_zoneidx,
@@ -795,7 +795,7 @@ static inline struct zoneref *first_zones_zonelist(struct zonelist *zonelist,
 #define for_each_zone_zonelist_nodemask(zone, z, zlist, highidx, nodemask) \
         for (z = first_zones_zonelist(zlist, highidx, nodemask, &zone); \
                 zone;                                                   \
-                z = next_zones_zonelist(z, highidx, nodemask, &zone))   \
+                z = next_zones_zonelist(++z, highidx, nodemask, &zone)) \
 
 /**
  * for_each_zone_zonelist - helper macro to iterate over valid zones in a zonelist at or below a given zone index
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index c4db5827963d..eb71b45fdf5a 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -131,6 +131,16 @@ struct usb_device_id {
 #define USB_DEVICE_ID_MATCH_INT_SUBCLASS        0x0100
 #define USB_DEVICE_ID_MATCH_INT_PROTOCOL        0x0200
 
+#define HID_ANY_ID                              (~0)
+
+struct hid_device_id {
+        __u16 bus;
+        __u32 vendor;
+        __u32 product;
+        kernel_ulong_t driver_data
+                __attribute__((aligned(sizeof(kernel_ulong_t))));
+};
+
 /* s390 CCW devices */
 struct ccw_device_id {
         __u16   match_flags;    /* which fields to match against */
@@ -274,7 +284,7 @@ struct pcmcia_device_id {
 /* Input */
 #define INPUT_DEVICE_ID_EV_MAX          0x1f
 #define INPUT_DEVICE_ID_KEY_MIN_INTERESTING     0x71
-#define INPUT_DEVICE_ID_KEY_MAX         0x1ff
+#define INPUT_DEVICE_ID_KEY_MAX         0x2ff
 #define INPUT_DEVICE_ID_REL_MAX         0x0f
 #define INPUT_DEVICE_ID_ABS_MAX         0x3f
 #define INPUT_DEVICE_ID_MSC_MAX         0x07
@@ -388,5 +398,52 @@ struct i2c_device_id {
                         __attribute__((aligned(sizeof(kernel_ulong_t))));
 };
 
+/* dmi */
+enum dmi_field {
+        DMI_NONE,
+        DMI_BIOS_VENDOR,
+        DMI_BIOS_VERSION,
+        DMI_BIOS_DATE,
+        DMI_SYS_VENDOR,
+        DMI_PRODUCT_NAME,
+        DMI_PRODUCT_VERSION,
+        DMI_PRODUCT_SERIAL,
+        DMI_PRODUCT_UUID,
+        DMI_BOARD_VENDOR,
+        DMI_BOARD_NAME,
+        DMI_BOARD_VERSION,
+        DMI_BOARD_SERIAL,
+        DMI_BOARD_ASSET_TAG,
+        DMI_CHASSIS_VENDOR,
+        DMI_CHASSIS_TYPE,
+        DMI_CHASSIS_VERSION,
+        DMI_CHASSIS_SERIAL,
+        DMI_CHASSIS_ASSET_TAG,
+        DMI_STRING_MAX,
+};
+
+struct dmi_strmatch {
+        unsigned char slot;
+        char substr[79];
+};
+
+#ifndef __KERNEL__
+struct dmi_system_id {
+        kernel_ulong_t callback;
+        kernel_ulong_t ident;
+        struct dmi_strmatch matches[4];
+        kernel_ulong_t driver_data
+                        __attribute__((aligned(sizeof(kernel_ulong_t))));
+};
+#else
+struct dmi_system_id {
+        int (*callback)(const struct dmi_system_id *);
+        const char *ident;
+        struct dmi_strmatch matches[4];
+        void *driver_data;
+};
+#endif
+
+#define DMI_MATCH(a, b) { a, b }
 
 #endif /* LINUX_MOD_DEVICETABLE_H */
diff --git a/include/linux/module.h b/include/linux/module.h
index 68e09557c951..a41555cbe00a 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -345,7 +345,6 @@ struct module
         /* Reference counts */
         struct module_ref ref[NR_CPUS];
 #endif
-
 };
 #ifndef MODULE_ARCH_INIT
 #define MODULE_ARCH_INIT {}
diff --git a/include/linux/mount.h b/include/linux/mount.h
index 30a1d63b6fb5..cab2a85e2ee8 100644
--- a/include/linux/mount.h
+++ b/include/linux/mount.h
@@ -5,8 +5,6 @@
  *
  * Author:  Marco van Wieringen <mvw@planets.elm.net>
  *
- * Version: $Id: mount.h,v 2.0 1996/11/17 16:48:14 mvw Exp mvw $
- *
  */
 #ifndef _LINUX_MOUNT_H
 #define _LINUX_MOUNT_H
diff --git a/include/linux/mroute.h b/include/linux/mroute.h
index 07112ee9293a..8a455694d682 100644
--- a/include/linux/mroute.h
+++ b/include/linux/mroute.h
@@ -6,7 +6,6 @@
 #ifdef __KERNEL__
 #include <linux/in.h>
 #endif
-#include <linux/pim.h>
 
 /*
  *      Based on the MROUTING 3.5 defines primarily to keep
@@ -130,6 +129,7 @@ struct igmpmsg
  */
 
 #ifdef __KERNEL__
+#include <linux/pim.h>
 #include <net/sock.h>
 
 #ifdef CONFIG_IP_MROUTE
diff --git a/include/linux/mroute6.h b/include/linux/mroute6.h
index 5cf50473a10f..6f4c180179e2 100644
--- a/include/linux/mroute6.h
+++ b/include/linux/mroute6.h
@@ -115,6 +115,7 @@ struct sioc_mif_req6
 
 #ifdef __KERNEL__
 
+#include <linux/pim.h>
 #include <linux/skbuff.h>       /* for struct sk_buff_head */
 
 #ifdef CONFIG_IPV6_MROUTE
diff --git a/include/linux/mtd/blktrans.h b/include/linux/mtd/blktrans.h
index 310e61606415..8b4aa0523db7 100644
--- a/include/linux/mtd/blktrans.h
+++ b/include/linux/mtd/blktrans.h
@@ -41,6 +41,8 @@ struct mtd_blktrans_ops {
                     unsigned long block, char *buffer);
         int (*writesect)(struct mtd_blktrans_dev *dev,
                      unsigned long block, char *buffer);
+        int (*discard)(struct mtd_blktrans_dev *dev,
+                       unsigned long block, unsigned nr_blocks);
 
         /* Block layer ioctls */
         int (*getgeo)(struct mtd_blktrans_dev *dev, struct hd_geometry *geo);
diff --git a/include/linux/mv643xx_eth.h b/include/linux/mv643xx_eth.h
index 12078577aef6..cbbbe9bfecad 100644
--- a/include/linux/mv643xx_eth.h
+++ b/include/linux/mv643xx_eth.h
@@ -17,9 +17,14 @@
 
 struct mv643xx_eth_shared_platform_data {
         struct mbus_dram_target_info    *dram;
+        struct platform_device  *shared_smi;
         unsigned int            t_clk;
 };
 
+#define MV643XX_ETH_PHY_ADDR_DEFAULT    0
+#define MV643XX_ETH_PHY_ADDR(x)         (0x80 | (x))
+#define MV643XX_ETH_PHY_NONE            0xff
+
 struct mv643xx_eth_platform_data {
         /*
          * Pointer back to our parent instance, and our port number.
@@ -30,8 +35,6 @@ struct mv643xx_eth_platform_data {
         /*
          * Whether a PHY is present, and if yes, at which address.
          */
-        struct platform_device  *shared_smi;
-        int                     force_phy_addr;
         int                     phy_addr;
 
         /*
@@ -49,10 +52,10 @@ struct mv643xx_eth_platform_data {
         int                     duplex;
 
         /*
-         * Which RX/TX queues to use.
+         * How many RX/TX queues to use.
          */
-        int                     rx_queue_mask;
-        int                     tx_queue_mask;
+        int                     rx_queue_count;
+        int                     tx_queue_count;
 
         /*
          * Override default RX/TX queue sizes if nonzero.
diff --git a/include/linux/net.h b/include/linux/net.h
index 4a9a30f2d68f..6dc14a240042 100644
--- a/include/linux/net.h
+++ b/include/linux/net.h
@@ -18,16 +18,9 @@
 #ifndef _LINUX_NET_H
 #define _LINUX_NET_H
 
-#include <linux/wait.h>
 #include <linux/socket.h>
-#include <linux/fcntl.h>        /* For O_CLOEXEC and O_NONBLOCK */
 #include <asm/socket.h>
 
-struct poll_table_struct;
-struct pipe_inode_info;
-struct inode;
-struct net;
-
 #define NPROTO          AF_MAX
 
 #define SYS_SOCKET      1               /* sys_socket(2)                */
@@ -62,6 +55,13 @@ typedef enum {
 #ifdef __KERNEL__
 #include <linux/stringify.h>
 #include <linux/random.h>
+#include <linux/wait.h>
+#include <linux/fcntl.h>        /* For O_CLOEXEC and O_NONBLOCK */
+
+struct poll_table_struct;
+struct pipe_inode_info;
+struct inode;
+struct net;
 
 #define SOCK_ASYNC_NOSPACE      0
 #define SOCK_ASYNC_WAITDATA     1
diff --git a/include/linux/netdevice.h b/include/linux/netdevice.h
index 488c56e649b5..64875859d654 100644
--- a/include/linux/netdevice.h
+++ b/include/linux/netdevice.h
@@ -11,7 +11,7 @@
  *              Fred N. van Kempen, <waltje@uWalt.NL.Mugnet.ORG>
  *              Corey Minyard <wf-rch!minyard@relay.EU.net>
  *              Donald J. Becker, <becker@cesdis.gsfc.nasa.gov>
- *              Alan Cox, <Alan.Cox@linux.org>
+ *              Alan Cox, <alan@lxorguk.ukuu.org.uk>
  *              Bjorn Ekwall. <bj0rn@blox.se>
  *              Pekka Riikonen <priikone@poseidon.pspt.fi>
  *
@@ -42,6 +42,7 @@
 #include <linux/workqueue.h>
 
 #include <net/net_namespace.h>
+#include <net/dsa.h>
 
 struct vlan_group;
 struct ethtool_ops;
@@ -471,6 +472,8 @@ struct net_device
         char                    name[IFNAMSIZ];
         /* device name hash chain */
         struct hlist_node       name_hlist;
+        /* snmp alias */
+        char                    *ifalias;
 
         /*
          *      I/O specific fields
@@ -605,6 +608,9 @@ struct net_device
 
         /* Protocol specific pointers */
         
+#ifdef CONFIG_NET_DSA
+        void                    *dsa_ptr;       /* dsa specific data */
+#endif
         void                    *atalk_ptr;     /* AppleTalk link       */
         void                    *ip_ptr;        /* IPv4 specific data   */  
         void                    *dn_ptr;        /* DECnet specific data */
@@ -796,6 +802,26 @@ void dev_net_set(struct net_device *dev, struct net *net)
 #endif
 }
 
+static inline bool netdev_uses_dsa_tags(struct net_device *dev)
+{
+#ifdef CONFIG_NET_DSA_TAG_DSA
+        if (dev->dsa_ptr != NULL)
+                return dsa_uses_dsa_tags(dev->dsa_ptr);
+#endif
+
+        return 0;
+}
+
+static inline bool netdev_uses_trailer_tags(struct net_device *dev)
+{
+#ifdef CONFIG_NET_DSA_TAG_TRAILER
+        if (dev->dsa_ptr != NULL)
+                return dsa_uses_trailer_tags(dev->dsa_ptr);
+#endif
+
+        return 0;
+}
+
 /**
  *      netdev_priv - access network device private data
  *      @dev: network device
@@ -1223,7 +1249,8 @@ extern int		dev_ioctl(struct net *net, unsigned int cmd, void __user *);
 extern int              dev_ethtool(struct net *net, struct ifreq *);
 extern unsigned         dev_get_flags(const struct net_device *);
 extern int              dev_change_flags(struct net_device *, unsigned);
-extern int              dev_change_name(struct net_device *, char *);
+extern int              dev_change_name(struct net_device *, const char *);
+extern int              dev_set_alias(struct net_device *, const char *, size_t);
 extern int              dev_change_net_namespace(struct net_device *,
                                                  struct net *, const char *);
 extern int              dev_set_mtu(struct net_device *, int);
@@ -1667,7 +1694,7 @@ extern void dev_seq_stop(struct seq_file *seq, void *v);
 extern int netdev_class_create_file(struct class_attribute *class_attr);
 extern void netdev_class_remove_file(struct class_attribute *class_attr);
 
-extern char *netdev_drivername(struct net_device *dev, char *buffer, int len);
+extern char *netdev_drivername(const struct net_device *dev, char *buffer, int len);
 
 extern void linkwatch_run_queue(void);
 
diff --git a/include/linux/netfilter.h b/include/linux/netfilter.h
index 0c5eb7ed8b3f..48cfe51bfddc 100644
--- a/include/linux/netfilter.h
+++ b/include/linux/netfilter.h
@@ -5,13 +5,11 @@
 #include <linux/init.h>
 #include <linux/skbuff.h>
 #include <linux/net.h>
-#include <linux/netdevice.h>
 #include <linux/if.h>
 #include <linux/in.h>
 #include <linux/in6.h>
 #include <linux/wait.h>
 #include <linux/list.h>
-#include <net/net_namespace.h>
 #endif
 #include <linux/types.h>
 #include <linux/compiler.h>
@@ -52,6 +50,16 @@ enum nf_inet_hooks {
         NF_INET_NUMHOOKS
 };
 
+enum {
+        NFPROTO_UNSPEC =  0,
+        NFPROTO_IPV4   =  2,
+        NFPROTO_ARP    =  3,
+        NFPROTO_BRIDGE =  7,
+        NFPROTO_IPV6   = 10,
+        NFPROTO_DECNET = 12,
+        NFPROTO_NUMPROTO,
+};
+
 union nf_inet_addr {
         __u32           all[4];
         __be32          ip;
@@ -92,8 +100,8 @@ struct nf_hook_ops
         /* User fills in from here down. */
         nf_hookfn *hook;
         struct module *owner;
-        int pf;
-        int hooknum;
+        u_int8_t pf;
+        unsigned int hooknum;
         /* Hooks are ordered in ascending priority. */
         int priority;
 };
@@ -102,7 +110,7 @@ struct nf_sockopt_ops
 {
         struct list_head list;
 
-        int pf;
+        u_int8_t pf;
 
         /* Non-inclusive ranges: use 0/0/NULL to never get called. */
         int set_optmin;
@@ -138,9 +146,9 @@ extern struct ctl_path nf_net_netfilter_sysctl_path[];
 extern struct ctl_path nf_net_ipv4_netfilter_sysctl_path[];
 #endif /* CONFIG_SYSCTL */
 
-extern struct list_head nf_hooks[NPROTO][NF_MAX_HOOKS];
+extern struct list_head nf_hooks[NFPROTO_NUMPROTO][NF_MAX_HOOKS];
 
-int nf_hook_slow(int pf, unsigned int hook, struct sk_buff *skb,
+int nf_hook_slow(u_int8_t pf, unsigned int hook, struct sk_buff *skb,
                  struct net_device *indev, struct net_device *outdev,
                  int (*okfn)(struct sk_buff *), int thresh);
 
@@ -151,7 +159,7 @@ int nf_hook_slow(int pf, unsigned int hook, struct sk_buff *skb,
  *      okfn must be invoked by the caller in this case.  Any other return
  *      value indicates the packet has been consumed by the hook.
  */
-static inline int nf_hook_thresh(int pf, unsigned int hook,
+static inline int nf_hook_thresh(u_int8_t pf, unsigned int hook,
                                  struct sk_buff *skb,
                                  struct net_device *indev,
                                  struct net_device *outdev,
@@ -167,7 +175,7 @@ static inline int nf_hook_thresh(int pf, unsigned int hook,
         return nf_hook_slow(pf, hook, skb, indev, outdev, okfn, thresh);
 }
 
-static inline int nf_hook(int pf, unsigned int hook, struct sk_buff *skb,
+static inline int nf_hook(u_int8_t pf, unsigned int hook, struct sk_buff *skb,
                           struct net_device *indev, struct net_device *outdev,
                           int (*okfn)(struct sk_buff *))
 {
@@ -212,14 +220,14 @@ __ret;})
         NF_HOOK_THRESH(pf, hook, skb, indev, outdev, okfn, INT_MIN)
 
 /* Call setsockopt() */
-int nf_setsockopt(struct sock *sk, int pf, int optval, char __user *opt, 
+int nf_setsockopt(struct sock *sk, u_int8_t pf, int optval, char __user *opt,
                   int len);
-int nf_getsockopt(struct sock *sk, int pf, int optval, char __user *opt,
+int nf_getsockopt(struct sock *sk, u_int8_t pf, int optval, char __user *opt,
                   int *len);
 
-int compat_nf_setsockopt(struct sock *sk, int pf, int optval,
+int compat_nf_setsockopt(struct sock *sk, u_int8_t pf, int optval,
                 char __user *opt, int len);
-int compat_nf_getsockopt(struct sock *sk, int pf, int optval,
+int compat_nf_getsockopt(struct sock *sk, u_int8_t pf, int optval,
                 char __user *opt, int *len);
 
 /* Call this before modifying an existing packet: ensures it is
@@ -247,7 +255,7 @@ struct nf_afinfo {
         int             route_key_size;
 };
 
-extern const struct nf_afinfo *nf_afinfo[NPROTO];
+extern const struct nf_afinfo *nf_afinfo[NFPROTO_NUMPROTO];
 static inline const struct nf_afinfo *nf_get_afinfo(unsigned short family)
 {
         return rcu_dereference(nf_afinfo[family]);
@@ -292,7 +300,7 @@ extern void nf_unregister_afinfo(const struct nf_afinfo *afinfo);
 extern void (*ip_nat_decode_session)(struct sk_buff *, struct flowi *);
 
 static inline void
-nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, int family)
+nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, u_int8_t family)
 {
 #ifdef CONFIG_NF_NAT_NEEDED
         void (*decodefn)(struct sk_buff *, struct flowi *);
@@ -315,7 +323,7 @@ extern struct proc_dir_entry *proc_net_netfilter;
 #else /* !CONFIG_NETFILTER */
 #define NF_HOOK(pf, hook, skb, indev, outdev, okfn) (okfn)(skb)
 #define NF_HOOK_COND(pf, hook, skb, indev, outdev, okfn, cond) (okfn)(skb)
-static inline int nf_hook_thresh(int pf, unsigned int hook,
+static inline int nf_hook_thresh(u_int8_t pf, unsigned int hook,
                                  struct sk_buff *skb,
                                  struct net_device *indev,
                                  struct net_device *outdev,
@@ -324,7 +332,7 @@ static inline int nf_hook_thresh(int pf, unsigned int hook,
 {
         return okfn(skb);
 }
-static inline int nf_hook(int pf, unsigned int hook, struct sk_buff *skb,
+static inline int nf_hook(u_int8_t pf, unsigned int hook, struct sk_buff *skb,
                           struct net_device *indev, struct net_device *outdev,
                           int (*okfn)(struct sk_buff *))
 {
@@ -332,7 +340,9 @@ static inline int nf_hook(int pf, unsigned int hook, struct sk_buff *skb,
 }
 struct flowi;
 static inline void
-nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, int family) {}
+nf_nat_decode_session(struct sk_buff *skb, struct flowi *fl, u_int8_t family)
+{
+}
 #endif /*CONFIG_NETFILTER*/
 
 #if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
@@ -343,56 +353,5 @@ extern void (*nf_ct_destroy)(struct nf_conntrack *);
 static inline void nf_ct_attach(struct sk_buff *new, struct sk_buff *skb) {}
 #endif
 
-static inline struct net *nf_pre_routing_net(const struct net_device *in,
-                                             const struct net_device *out)
-{
-#ifdef CONFIG_NET_NS
-        return in->nd_net;
-#else
-        return &init_net;
-#endif
-}
-
-static inline struct net *nf_local_in_net(const struct net_device *in,
-                                          const struct net_device *out)
-{
-#ifdef CONFIG_NET_NS
-        return in->nd_net;
-#else
-        return &init_net;
-#endif
-}
-
-static inline struct net *nf_forward_net(const struct net_device *in,
-                                         const struct net_device *out)
-{
-#ifdef CONFIG_NET_NS
-        BUG_ON(in->nd_net != out->nd_net);
-        return in->nd_net;
-#else
-        return &init_net;
-#endif
-}
-
-static inline struct net *nf_local_out_net(const struct net_device *in,
-                                           const struct net_device *out)
-{
-#ifdef CONFIG_NET_NS
-        return out->nd_net;
-#else
-        return &init_net;
-#endif
-}
-
-static inline struct net *nf_post_routing_net(const struct net_device *in,
-                                              const struct net_device *out)
-{
-#ifdef CONFIG_NET_NS
-        return out->nd_net;
-#else
-        return &init_net;
-#endif
-}
-
 #endif /*__KERNEL__*/
 #endif /*__LINUX_NETFILTER_H*/
diff --git a/include/linux/netfilter/Kbuild b/include/linux/netfilter/Kbuild
index 3aff513d12c8..5a8af875bce2 100644
--- a/include/linux/netfilter/Kbuild
+++ b/include/linux/netfilter/Kbuild
@@ -32,6 +32,7 @@ header-y += xt_owner.h
 header-y += xt_pkttype.h
 header-y += xt_rateest.h
 header-y += xt_realm.h
+header-y += xt_recent.h
 header-y += xt_sctp.h
 header-y += xt_state.h
 header-y += xt_statistic.h
diff --git a/include/linux/netfilter/nf_conntrack_proto_gre.h b/include/linux/netfilter/nf_conntrack_proto_gre.h
index 535e4219d2bb..2a10efda17fb 100644
--- a/include/linux/netfilter/nf_conntrack_proto_gre.h
+++ b/include/linux/netfilter/nf_conntrack_proto_gre.h
@@ -87,7 +87,7 @@ int nf_ct_gre_keymap_add(struct nf_conn *ct, enum ip_conntrack_dir dir,
 /* delete keymap entries */
 void nf_ct_gre_keymap_destroy(struct nf_conn *ct);
 
-extern void nf_ct_gre_keymap_flush(void);
+extern void nf_ct_gre_keymap_flush(struct net *net);
 extern void nf_nat_need_gre(void);
 
 #endif /* __KERNEL__ */
diff --git a/include/linux/netfilter/nfnetlink.h b/include/linux/netfilter/nfnetlink.h
index 0d8424f76899..7d8e0455ccac 100644
--- a/include/linux/netfilter/nfnetlink.h
+++ b/include/linux/netfilter/nfnetlink.h
@@ -78,6 +78,9 @@ extern int nfnetlink_send(struct sk_buff *skb, u32 pid, unsigned group,
                           int echo);
 extern int nfnetlink_unicast(struct sk_buff *skb, u_int32_t pid, int flags);
 
+extern void nfnl_lock(void);
+extern void nfnl_unlock(void);
+
 #define MODULE_ALIAS_NFNL_SUBSYS(subsys) \
         MODULE_ALIAS("nfnetlink-subsys-" __stringify(subsys))
 
diff --git a/include/linux/netfilter/x_tables.h b/include/linux/netfilter/x_tables.h
index 2326296b6f25..be41b609c88f 100644
--- a/include/linux/netfilter/x_tables.h
+++ b/include/linux/netfilter/x_tables.h
@@ -173,6 +173,98 @@ struct xt_counters_info
 
 #include <linux/netdevice.h>
 
+/**
+ * struct xt_match_param - parameters for match extensions' match functions
+ *
+ * @in:         input netdevice
+ * @out:        output netdevice
+ * @match:      struct xt_match through which this function was invoked
+ * @matchinfo:  per-match data
+ * @fragoff:    packet is a fragment, this is the data offset
+ * @thoff:      position of transport header relative to skb->data
+ * @hotdrop:    drop packet if we had inspection problems
+ * @family:     Actual NFPROTO_* through which the function is invoked
+ *              (helpful when match->family == NFPROTO_UNSPEC)
+ */
+struct xt_match_param {
+        const struct net_device *in, *out;
+        const struct xt_match *match;
+        const void *matchinfo;
+        int fragoff;
+        unsigned int thoff;
+        bool *hotdrop;
+        u_int8_t family;
+};
+
+/**
+ * struct xt_mtchk_param - parameters for match extensions'
+ * checkentry functions
+ *
+ * @table:      table the rule is tried to be inserted into
+ * @entryinfo:  the family-specific rule data
+ *              (struct ipt_ip, ip6t_ip, ebt_entry)
+ * @match:      struct xt_match through which this function was invoked
+ * @matchinfo:  per-match data
+ * @hook_mask:  via which hooks the new rule is reachable
+ */
+struct xt_mtchk_param {
+        const char *table;
+        const void *entryinfo;
+        const struct xt_match *match;
+        void *matchinfo;
+        unsigned int hook_mask;
+        u_int8_t family;
+};
+
+/* Match destructor parameters */
+struct xt_mtdtor_param {
+        const struct xt_match *match;
+        void *matchinfo;
+        u_int8_t family;
+};
+
+/**
+ * struct xt_target_param - parameters for target extensions' target functions
+ *
+ * @hooknum:    hook through which this target was invoked
+ * @target:     struct xt_target through which this function was invoked
+ * @targinfo:   per-target data
+ *
+ * Other fields see above.
+ */
+struct xt_target_param {
+        const struct net_device *in, *out;
+        unsigned int hooknum;
+        const struct xt_target *target;
+        const void *targinfo;
+        u_int8_t family;
+};
+
+/**
+ * struct xt_tgchk_param - parameters for target extensions'
+ * checkentry functions
+ *
+ * @entryinfo:  the family-specific rule data
+ *              (struct ipt_entry, ip6t_entry, arpt_entry, ebt_entry)
+ *
+ * Other fields see above.
+ */
+struct xt_tgchk_param {
+        const char *table;
+        void *entryinfo;
+        const struct xt_target *target;
+        void *targinfo;
+        unsigned int hook_mask;
+        u_int8_t family;
+};
+
+/* Target destructor parameters */
+struct xt_tgdtor_param {
+        const struct xt_target *target;
+        void *targinfo;
+        u_int8_t family;
+};
+
 struct xt_match
 {
         struct list_head list;
@@ -185,24 +277,13 @@ struct xt_match
            non-linear skb, using skb_header_pointer and
            skb_ip_make_writable. */
         bool (*match)(const struct sk_buff *skb,
-                      const struct net_device *in,
-                      const struct net_device *out,
-                      const struct xt_match *match,
-                      const void *matchinfo,
-                      int offset,
-                      unsigned int protoff,
-                      bool *hotdrop);
+                      const struct xt_match_param *);
 
         /* Called when user tries to insert an entry of this type. */
-        /* Should return true or false. */
-        bool (*checkentry)(const char *tablename,
-                           const void *ip,
-                           const struct xt_match *match,
-                           void *matchinfo,
-                           unsigned int hook_mask);
+        bool (*checkentry)(const struct xt_mtchk_param *);
 
         /* Called when entry of this type deleted. */
-        void (*destroy)(const struct xt_match *match, void *matchinfo);
+        void (*destroy)(const struct xt_mtdtor_param *);
 
         /* Called when userspace align differs from kernel space one */
         void (*compat_from_user)(void *dst, void *src);
@@ -235,24 +316,16 @@ struct xt_target
            must now handle non-linear skbs, using skb_copy_bits and
            skb_ip_make_writable. */
         unsigned int (*target)(struct sk_buff *skb,
-                               const struct net_device *in,
-                               const struct net_device *out,
-                               unsigned int hooknum,
-                               const struct xt_target *target,
-                               const void *targinfo);
+                               const struct xt_target_param *);
 
         /* Called when user tries to insert an entry of this type:
            hook_mask is a bitmask of hooks from which it can be
            called. */
         /* Should return true or false. */
-        bool (*checkentry)(const char *tablename,
-                           const void *entry,
-                           const struct xt_target *target,
-                           void *targinfo,
-                           unsigned int hook_mask);
+        bool (*checkentry)(const struct xt_tgchk_param *);
 
         /* Called when entry of this type deleted. */
-        void (*destroy)(const struct xt_target *target, void *targinfo);
+        void (*destroy)(const struct xt_tgdtor_param *);
 
         /* Called when userspace align differs from kernel space one */
         void (*compat_from_user)(void *dst, void *src);
@@ -292,7 +365,7 @@ struct xt_table
         /* Set this to THIS_MODULE if you are a module, otherwise NULL */
         struct module *me;
 
-        int af;         /* address/protocol family */
+        u_int8_t af;            /* address/protocol family */
 };
 
 #include <linux/netfilter_ipv4.h>
@@ -328,12 +401,10 @@ extern void xt_unregister_match(struct xt_match *target);
 extern int xt_register_matches(struct xt_match *match, unsigned int n);
 extern void xt_unregister_matches(struct xt_match *match, unsigned int n);
 
-extern int xt_check_match(const struct xt_match *match, unsigned short family,
-                          unsigned int size, const char *table, unsigned int hook,
-                          unsigned short proto, int inv_proto);
-extern int xt_check_target(const struct xt_target *target, unsigned short family,
-                           unsigned int size, const char *table, unsigned int hook,
-                           unsigned short proto, int inv_proto);
+extern int xt_check_match(struct xt_mtchk_param *,
+                          unsigned int size, u_int8_t proto, bool inv_proto);
+extern int xt_check_target(struct xt_tgchk_param *,
+                           unsigned int size, u_int8_t proto, bool inv_proto);
 
 extern struct xt_table *xt_register_table(struct net *net,
                                           struct xt_table *table,
@@ -346,19 +417,19 @@ extern struct xt_table_info *xt_replace_table(struct xt_table *table,
                                               struct xt_table_info *newinfo,
                                               int *error);
 
-extern struct xt_match *xt_find_match(int af, const char *name, u8 revision);
-extern struct xt_target *xt_find_target(int af, const char *name, u8 revision);
-extern struct xt_target *xt_request_find_target(int af, const char *name, 
+extern struct xt_match *xt_find_match(u8 af, const char *name, u8 revision);
+extern struct xt_target *xt_find_target(u8 af, const char *name, u8 revision);
+extern struct xt_target *xt_request_find_target(u8 af, const char *name,
                                                 u8 revision);
-extern int xt_find_revision(int af, const char *name, u8 revision, int target,
-                            int *err);
+extern int xt_find_revision(u8 af, const char *name, u8 revision,
+                            int target, int *err);
 
-extern struct xt_table *xt_find_table_lock(struct net *net, int af,
+extern struct xt_table *xt_find_table_lock(struct net *net, u_int8_t af,
                                            const char *name);
 extern void xt_table_unlock(struct xt_table *t);
 
-extern int xt_proto_init(struct net *net, int af);
-extern void xt_proto_fini(struct net *net, int af);
+extern int xt_proto_init(struct net *net, u_int8_t af);
+extern void xt_proto_fini(struct net *net, u_int8_t af);
 
 extern struct xt_table_info *xt_alloc_table_info(unsigned int size);
 extern void xt_free_table_info(struct xt_table_info *info);
@@ -423,12 +494,12 @@ struct compat_xt_counters_info
 #define COMPAT_XT_ALIGN(s) (((s) + (__alignof__(struct compat_xt_counters)-1)) \
                 & ~(__alignof__(struct compat_xt_counters)-1))
 
-extern void xt_compat_lock(int af);
-extern void xt_compat_unlock(int af);
+extern void xt_compat_lock(u_int8_t af);
+extern void xt_compat_unlock(u_int8_t af);
 
-extern int xt_compat_add_offset(int af, unsigned int offset, short delta);
-extern void xt_compat_flush_offsets(int af);
-extern short xt_compat_calc_jump(int af, unsigned int offset);
+extern int xt_compat_add_offset(u_int8_t af, unsigned int offset, short delta);
+extern void xt_compat_flush_offsets(u_int8_t af);
+extern short xt_compat_calc_jump(u_int8_t af, unsigned int offset);
 
 extern int xt_compat_match_offset(const struct xt_match *match);
 extern int xt_compat_match_from_user(struct xt_entry_match *m,
diff --git a/include/linux/netfilter/xt_TPROXY.h b/include/linux/netfilter/xt_TPROXY.h
new file mode 100644
index 000000000000..152e8f97132b
--- /dev/null
+++ b/include/linux/netfilter/xt_TPROXY.h
@@ -0,0 +1,14 @@
+#ifndef _XT_TPROXY_H_target
+#define _XT_TPROXY_H_target
+
+/* TPROXY target is capable of marking the packet to perform
+ * redirection. We can get rid of that whenever we get support for
+ * mutliple targets in the same rule. */
+struct xt_tproxy_target_info {
+        u_int32_t mark_mask;
+        u_int32_t mark_value;
+        __be32 laddr;
+        __be16 lport;
+};
+
+#endif /* _XT_TPROXY_H_target */
diff --git a/include/linux/netfilter/xt_recent.h b/include/linux/netfilter/xt_recent.h
new file mode 100644
index 000000000000..5cfeb81c6794
--- /dev/null
+++ b/include/linux/netfilter/xt_recent.h
@@ -0,0 +1,26 @@
+#ifndef _LINUX_NETFILTER_XT_RECENT_H
+#define _LINUX_NETFILTER_XT_RECENT_H 1
+
+enum {
+        XT_RECENT_CHECK    = 1 << 0,
+        XT_RECENT_SET      = 1 << 1,
+        XT_RECENT_UPDATE   = 1 << 2,
+        XT_RECENT_REMOVE   = 1 << 3,
+        XT_RECENT_TTL      = 1 << 4,
+
+        XT_RECENT_SOURCE   = 0,
+        XT_RECENT_DEST     = 1,
+
+        XT_RECENT_NAME_LEN = 200,
+};
+
+struct xt_recent_mtinfo {
+        u_int32_t seconds;
+        u_int32_t hit_count;
+        u_int8_t check_set;
+        u_int8_t invert;
+        char name[XT_RECENT_NAME_LEN];
+        u_int8_t side;
+};
+
+#endif /* _LINUX_NETFILTER_XT_RECENT_H */
diff --git a/include/linux/netfilter_bridge/ebtables.h b/include/linux/netfilter_bridge/ebtables.h
index 892f5b7771c7..d45e29cd1cfb 100644
--- a/include/linux/netfilter_bridge/ebtables.h
+++ b/include/linux/netfilter_bridge/ebtables.h
@@ -31,6 +31,9 @@
  * The 4 lsb are more than enough to store the verdict. */
 #define EBT_VERDICT_BITS 0x0000000F
 
+struct xt_match;
+struct xt_target;
+
 struct ebt_counter
 {
         uint64_t pcnt;
@@ -121,7 +124,7 @@ struct ebt_entry_match
 {
         union {
                 char name[EBT_FUNCTION_MAXNAMELEN];
-                struct ebt_match *match;
+                struct xt_match *match;
         } u;
         /* size of data */
         unsigned int match_size;
@@ -132,7 +135,7 @@ struct ebt_entry_watcher
 {
         union {
                 char name[EBT_FUNCTION_MAXNAMELEN];
-                struct ebt_watcher *watcher;
+                struct xt_target *watcher;
         } u;
         /* size of data */
         unsigned int watcher_size;
@@ -143,7 +146,7 @@ struct ebt_entry_target
 {
         union {
                 char name[EBT_FUNCTION_MAXNAMELEN];
-                struct ebt_target *target;
+                struct xt_target *target;
         } u;
         /* size of data */
         unsigned int target_size;
@@ -207,14 +210,17 @@ struct ebt_match
 {
         struct list_head list;
         const char name[EBT_FUNCTION_MAXNAMELEN];
-        /* 0 == it matches */
-        int (*match)(const struct sk_buff *skb, const struct net_device *in,
-           const struct net_device *out, const void *matchdata,
-           unsigned int datalen);
-        /* 0 == let it in */
-        int (*check)(const char *tablename, unsigned int hookmask,
-           const struct ebt_entry *e, void *matchdata, unsigned int datalen);
-        void (*destroy)(void *matchdata, unsigned int datalen);
+        bool (*match)(const struct sk_buff *skb, const struct net_device *in,
+                const struct net_device *out, const struct xt_match *match,
+                const void *matchinfo, int offset, unsigned int protoff,
+                bool *hotdrop);
+        bool (*checkentry)(const char *table, const void *entry,
+                const struct xt_match *match, void *matchinfo,
+                unsigned int hook_mask);
+        void (*destroy)(const struct xt_match *match, void *matchinfo);
+        unsigned int matchsize;
+        u_int8_t revision;
+        u_int8_t family;
         struct module *me;
 };
 
@@ -222,13 +228,17 @@ struct ebt_watcher
 {
         struct list_head list;
         const char name[EBT_FUNCTION_MAXNAMELEN];
-        void (*watcher)(const struct sk_buff *skb, unsigned int hooknr,
-           const struct net_device *in, const struct net_device *out,
-           const void *watcherdata, unsigned int datalen);
-        /* 0 == let it in */
-        int (*check)(const char *tablename, unsigned int hookmask,
-           const struct ebt_entry *e, void *watcherdata, unsigned int datalen);
-        void (*destroy)(void *watcherdata, unsigned int datalen);
+        unsigned int (*target)(struct sk_buff *skb,
+                const struct net_device *in, const struct net_device *out,
+                unsigned int hook_num, const struct xt_target *target,
+                const void *targinfo);
+        bool (*checkentry)(const char *table, const void *entry,
+                const struct xt_target *target, void *targinfo,
+                unsigned int hook_mask);
+        void (*destroy)(const struct xt_target *target, void *targinfo);
+        unsigned int targetsize;
+        u_int8_t revision;
+        u_int8_t family;
         struct module *me;
 };
 
@@ -236,14 +246,18 @@ struct ebt_target
 {
         struct list_head list;
         const char name[EBT_FUNCTION_MAXNAMELEN];
-        /* returns one of the standard verdicts */
-        int (*target)(struct sk_buff *skb, unsigned int hooknr,
-           const struct net_device *in, const struct net_device *out,
-           const void *targetdata, unsigned int datalen);
-        /* 0 == let it in */
-        int (*check)(const char *tablename, unsigned int hookmask,
-           const struct ebt_entry *e, void *targetdata, unsigned int datalen);
-        void (*destroy)(void *targetdata, unsigned int datalen);
+        /* returns one of the standard EBT_* verdicts */
+        unsigned int (*target)(struct sk_buff *skb,
+                const struct net_device *in, const struct net_device *out,
+                unsigned int hook_num, const struct xt_target *target,
+                const void *targinfo);
+        bool (*checkentry)(const char *table, const void *entry,
+                const struct xt_target *target, void *targinfo,
+                unsigned int hook_mask);
+        void (*destroy)(const struct xt_target *target, void *targinfo);
+        unsigned int targetsize;
+        u_int8_t revision;
+        u_int8_t family;
         struct module *me;
 };
 
@@ -288,12 +302,6 @@ struct ebt_table
                      ~(__alignof__(struct ebt_replace)-1))
 extern int ebt_register_table(struct ebt_table *table);
 extern void ebt_unregister_table(struct ebt_table *table);
-extern int ebt_register_match(struct ebt_match *match);
-extern void ebt_unregister_match(struct ebt_match *match);
-extern int ebt_register_watcher(struct ebt_watcher *watcher);
-extern void ebt_unregister_watcher(struct ebt_watcher *watcher);
-extern int ebt_register_target(struct ebt_target *target);
-extern void ebt_unregister_target(struct ebt_target *target);
 extern unsigned int ebt_do_table(unsigned int hook, struct sk_buff *skb,
    const struct net_device *in, const struct net_device *out,
    struct ebt_table *table);
@@ -302,9 +310,9 @@ extern unsigned int ebt_do_table(unsigned int hook, struct sk_buff *skb,
 #define FWINV(bool,invflg) ((bool) ^ !!(info->invflags & invflg))
 /* True if the hook mask denotes that the rule is in a base chain,
  * used in the check() functions */
-#define BASE_CHAIN (hookmask & (1 << NF_BR_NUMHOOKS))
+#define BASE_CHAIN (par->hook_mask & (1 << NF_BR_NUMHOOKS))
 /* Clear the bit in the hook mask that tells if the rule is on a base chain */
-#define CLEAR_BASE_CHAIN_BIT (hookmask &= ~(1 << NF_BR_NUMHOOKS))
+#define CLEAR_BASE_CHAIN_BIT (par->hook_mask &= ~(1 << NF_BR_NUMHOOKS))
 /* True if the target is not a standard target */
 #define INVALID_TARGET (info->target < -NUM_STANDARD_TARGETS || info->target >= 0)
 
diff --git a/include/linux/netfilter_ipv4/ipt_recent.h b/include/linux/netfilter_ipv4/ipt_recent.h
index 6508a4592651..d636cca133c2 100644
--- a/include/linux/netfilter_ipv4/ipt_recent.h
+++ b/include/linux/netfilter_ipv4/ipt_recent.h
@@ -1,27 +1,21 @@
 #ifndef _IPT_RECENT_H
 #define _IPT_RECENT_H
 
-#define RECENT_NAME     "ipt_recent"
-#define RECENT_VER      "v0.3.1"
+#include <linux/netfilter/xt_recent.h>
 
-#define IPT_RECENT_CHECK  1
-#define IPT_RECENT_SET    2
-#define IPT_RECENT_UPDATE 4
-#define IPT_RECENT_REMOVE 8
-#define IPT_RECENT_TTL   16
+#define ipt_recent_info xt_recent_mtinfo
 
-#define IPT_RECENT_SOURCE 0
-#define IPT_RECENT_DEST   1
+enum {
+        IPT_RECENT_CHECK    = XT_RECENT_CHECK,
+        IPT_RECENT_SET      = XT_RECENT_SET,
+        IPT_RECENT_UPDATE   = XT_RECENT_UPDATE,
+        IPT_RECENT_REMOVE   = XT_RECENT_REMOVE,
+        IPT_RECENT_TTL      = XT_RECENT_TTL,
 
-#define IPT_RECENT_NAME_LEN 200
+        IPT_RECENT_SOURCE   = XT_RECENT_SOURCE,
+        IPT_RECENT_DEST     = XT_RECENT_DEST,
 
-struct ipt_recent_info {
-        u_int32_t   seconds;
-        u_int32_t   hit_count;
-        u_int8_t    check_set;
-        u_int8_t    invert;
-        char        name[IPT_RECENT_NAME_LEN];
-        u_int8_t    side;
+        IPT_RECENT_NAME_LEN = XT_RECENT_NAME_LEN,
 };
 
 #endif /*_IPT_RECENT_H*/
diff --git a/include/linux/nfs_fs.h b/include/linux/nfs_fs.h
index 78a5922a2f11..ac8d0233b05c 100644
--- a/include/linux/nfs_fs.h
+++ b/include/linux/nfs_fs.h
@@ -137,7 +137,7 @@ struct nfs_inode {
         unsigned long           attrtimeo_timestamp;
         __u64                   change_attr;            /* v4 only */
 
-        unsigned long           last_updated;
+        unsigned long           attr_gencount;
         /* "Generation counter" for the attribute cache. This is
          * bumped whenever we update the metadata on the
          * server.
@@ -200,11 +200,10 @@ struct nfs_inode {
 /*
  * Bit offsets in flags field
  */
-#define NFS_INO_REVALIDATING    (0)             /* revalidating attrs */
-#define NFS_INO_ADVISE_RDPLUS   (1)             /* advise readdirplus */
-#define NFS_INO_STALE           (2)             /* possible stale inode */
-#define NFS_INO_ACL_LRU_SET     (3)             /* Inode is on the LRU list */
-#define NFS_INO_MOUNTPOINT      (4)             /* inode is remote mountpoint */
+#define NFS_INO_ADVISE_RDPLUS   (0)             /* advise readdirplus */
+#define NFS_INO_STALE           (1)             /* possible stale inode */
+#define NFS_INO_ACL_LRU_SET     (2)             /* Inode is on the LRU list */
+#define NFS_INO_MOUNTPOINT      (3)             /* inode is remote mountpoint */
 
 static inline struct nfs_inode *NFS_I(const struct inode *inode)
 {
@@ -345,15 +344,11 @@ extern struct nfs_open_context *get_nfs_open_context(struct nfs_open_context *ct
 extern void put_nfs_open_context(struct nfs_open_context *ctx);
 extern struct nfs_open_context *nfs_find_open_context(struct inode *inode, struct rpc_cred *cred, int mode);
 extern u64 nfs_compat_user_ino64(u64 fileid);
+extern void nfs_fattr_init(struct nfs_fattr *fattr);
 
 /* linux/net/ipv4/ipconfig.c: trims ip addr off front of name, too. */
 extern __be32 root_nfs_parse_addr(char *name); /*__init*/
-
-static inline void nfs_fattr_init(struct nfs_fattr *fattr)
-{
-        fattr->valid = 0;
-        fattr->time_start = jiffies;
-}
+extern unsigned long nfs_inc_attr_generation_counter(void);
 
 /*
  * linux/fs/nfs/file.c
diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
index c9beacd16c00..4e477ae58699 100644
--- a/include/linux/nfs_fs_sb.h
+++ b/include/linux/nfs_fs_sb.h
@@ -119,7 +119,6 @@ struct nfs_server {
         void (*destroy)(struct nfs_server *);
 
         atomic_t active; /* Keep trace of any activity to this server */
-        wait_queue_head_t active_wq;  /* Wait for any activity to stop  */
 
         /* mountd-related mount options */
         struct sockaddr_storage mountd_address;
diff --git a/include/linux/nfs_mount.h b/include/linux/nfs_mount.h
index df7c6b7a7ebb..6549a06ac16e 100644
--- a/include/linux/nfs_mount.h
+++ b/include/linux/nfs_mount.h
@@ -65,4 +65,8 @@ struct nfs_mount_data {
 #define NFS_MOUNT_UNSHARED      0x8000  /* 5 */
 #define NFS_MOUNT_FLAGMASK      0xFFFF
 
+/* The following are for internal use only */
+#define NFS_MOUNT_LOOKUP_CACHE_NONEG    0x10000
+#define NFS_MOUNT_LOOKUP_CACHE_NONE     0x20000
+
 #endif
diff --git a/include/linux/nfs_xdr.h b/include/linux/nfs_xdr.h
index 8c77c11224d1..c1c31acb8a2b 100644
--- a/include/linux/nfs_xdr.h
+++ b/include/linux/nfs_xdr.h
@@ -36,6 +36,7 @@ struct nfs_fattr {
         __u32                   nlink;
         __u32                   uid;
         __u32                   gid;
+        dev_t                   rdev;
         __u64                   size;
         union {
                 struct {
@@ -46,7 +47,6 @@ struct nfs_fattr {
                         __u64   used;
                 } nfs3;
         } du;
-        dev_t                   rdev;
         struct nfs_fsid         fsid;
         __u64                   fileid;
         struct timespec         atime;
@@ -56,6 +56,7 @@ struct nfs_fattr {
         __u64                   change_attr;    /* NFSv4 change attribute */
         __u64                   pre_change_attr;/* pre-op NFSv4 change attribute */
         unsigned long           time_start;
+        unsigned long           gencount;
 };
 
 #define NFS_ATTR_WCC            0x0001          /* pre-op WCC data    */
@@ -672,16 +673,16 @@ struct nfs4_rename_res {
         struct nfs_fattr *              new_fattr;
 };
 
-#define NFS4_SETCLIENTID_NAMELEN        (56)
+#define NFS4_SETCLIENTID_NAMELEN        (127)
 struct nfs4_setclientid {
         const nfs4_verifier *           sc_verifier;
         unsigned int                    sc_name_len;
-        char                            sc_name[NFS4_SETCLIENTID_NAMELEN];
+        char                            sc_name[NFS4_SETCLIENTID_NAMELEN + 1];
         u32                             sc_prog;
         unsigned int                    sc_netid_len;
-        char                            sc_netid[RPCBIND_MAXNETIDLEN];
+        char                            sc_netid[RPCBIND_MAXNETIDLEN + 1];
         unsigned int                    sc_uaddr_len;
-        char                            sc_uaddr[RPCBIND_MAXUADDRLEN];
+        char                            sc_uaddr[RPCBIND_MAXUADDRLEN + 1];
         u32                             sc_cb_ident;
 };
 
diff --git a/include/linux/nfsd/nfsd.h b/include/linux/nfsd/nfsd.h
index 108f47e5fd95..21269405ffe2 100644
--- a/include/linux/nfsd/nfsd.h
+++ b/include/linux/nfsd/nfsd.h
@@ -38,6 +38,7 @@
 #define NFSD_MAY_LOCK           32
 #define NFSD_MAY_OWNER_OVERRIDE 64
 #define NFSD_MAY_LOCAL_ACCESS   128 /* IRIX doing local access check on device special file*/
+#define NFSD_MAY_BYPASS_GSS_ON_ROOT 256
 
 #define NFSD_MAY_CREATE         (NFSD_MAY_EXEC|NFSD_MAY_WRITE)
 #define NFSD_MAY_REMOVE         (NFSD_MAY_EXEC|NFSD_MAY_WRITE|NFSD_MAY_TRUNC)
@@ -125,7 +126,7 @@ int		nfsd_truncate(struct svc_rqst *, struct svc_fh *,
 __be32          nfsd_readdir(struct svc_rqst *, struct svc_fh *,
                              loff_t *, struct readdir_cd *, filldir_t);
 __be32          nfsd_statfs(struct svc_rqst *, struct svc_fh *,
-                                struct kstatfs *);
+                                struct kstatfs *, int access);
 
 int             nfsd_notify_change(struct inode *, struct iattr *);
 __be32          nfsd_permission(struct svc_rqst *, struct svc_export *,
diff --git a/include/linux/nl80211.h b/include/linux/nl80211.h
index 2be7c63bc0f2..9bad65400fba 100644
--- a/include/linux/nl80211.h
+++ b/include/linux/nl80211.h
@@ -89,6 +89,22 @@
  * @NL80211_CMD_DEL_PATH: Remove a mesh path identified by %NL80211_ATTR_MAC
  *      or, if no MAC address given, all mesh paths, on the interface identified
  *      by %NL80211_ATTR_IFINDEX.
+ * @NL80211_CMD_SET_BSS: Set BSS attributes for BSS identified by
+ *      %NL80211_ATTR_IFINDEX.
+ *
+ * @NL80211_CMD_SET_REG: Set current regulatory domain. CRDA sends this command
+ *      after being queried by the kernel. CRDA replies by sending a regulatory
+ *      domain structure which consists of %NL80211_ATTR_REG_ALPHA set to our
+ *      current alpha2 if it found a match. It also provides
+ *      NL80211_ATTR_REG_RULE_FLAGS, and a set of regulatory rules. Each
+ *      regulatory rule is a nested set of attributes  given by
+ *      %NL80211_ATTR_REG_RULE_FREQ_[START|END] and
+ *      %NL80211_ATTR_FREQ_RANGE_MAX_BW with an attached power rule given by
+ *      %NL80211_ATTR_REG_RULE_POWER_MAX_ANT_GAIN and
+ *      %NL80211_ATTR_REG_RULE_POWER_MAX_EIRP.
+ * @NL80211_CMD_REQ_SET_REG: ask the wireless core to set the regulatory domain
+ *      to the the specified ISO/IEC 3166-1 alpha2 country code. The core will
+ *      store this as a valid request and then query userspace for it.
  *
  * @NL80211_CMD_MAX: highest used command number
  * @__NL80211_CMD_AFTER_LAST: internal use
@@ -127,13 +143,23 @@ enum nl80211_commands {
         NL80211_CMD_NEW_MPATH,
         NL80211_CMD_DEL_MPATH,
 
-        /* add commands here */
+        NL80211_CMD_SET_BSS,
+
+        NL80211_CMD_SET_REG,
+        NL80211_CMD_REQ_SET_REG,
+
+        /* add new commands above here */
 
         /* used to define NL80211_CMD_MAX below */
         __NL80211_CMD_AFTER_LAST,
         NL80211_CMD_MAX = __NL80211_CMD_AFTER_LAST - 1
 };
 
+/*
+ * Allow user space programs to use #ifdef on new commands by defining them
+ * here
+ */
+#define NL80211_CMD_SET_BSS NL80211_CMD_SET_BSS
 
 /**
  * enum nl80211_attrs - nl80211 netlink attributes
@@ -188,10 +214,34 @@ enum nl80211_commands {
  *      info given for %NL80211_CMD_GET_MPATH, nested attribute described at
  *      &enum nl80211_mpath_info.
  *
- *
  * @NL80211_ATTR_MNTR_FLAGS: flags, nested element with NLA_FLAG attributes of
  *      &enum nl80211_mntr_flags.
  *
+ * @NL80211_ATTR_REG_ALPHA2: an ISO-3166-alpha2 country code for which the
+ *      current regulatory domain should be set to or is already set to.
+ *      For example, 'CR', for Costa Rica. This attribute is used by the kernel
+ *      to query the CRDA to retrieve one regulatory domain. This attribute can
+ *      also be used by userspace to query the kernel for the currently set
+ *      regulatory domain. We chose an alpha2 as that is also used by the
+ *      IEEE-802.11d country information element to identify a country.
+ *      Users can also simply ask the wireless core to set regulatory domain
+ *      to a specific alpha2.
+ * @NL80211_ATTR_REG_RULES: a nested array of regulatory domain regulatory
+ *      rules.
+ *
+ * @NL80211_ATTR_BSS_CTS_PROT: whether CTS protection is enabled (u8, 0 or 1)
+ * @NL80211_ATTR_BSS_SHORT_PREAMBLE: whether short preamble is enabled
+ *      (u8, 0 or 1)
+ * @NL80211_ATTR_BSS_SHORT_SLOT_TIME: whether short slot time enabled
+ *      (u8, 0 or 1)
+ *
+ * @NL80211_ATTR_HT_CAPABILITY: HT Capability information element (from
+ *      association request when used with NL80211_CMD_NEW_STATION)
+ *
+ * @NL80211_ATTR_SUPPORTED_IFTYPES: nested attribute containing all
+ *      supported interface types, each a flag attribute with the number
+ *      of the interface mode.
+ *
  * @NL80211_ATTR_MAX: highest attribute number currently defined
  * @__NL80211_ATTR_AFTER_LAST: internal use
  */
@@ -235,16 +285,35 @@ enum nl80211_attrs {
         NL80211_ATTR_MPATH_NEXT_HOP,
         NL80211_ATTR_MPATH_INFO,
 
+        NL80211_ATTR_BSS_CTS_PROT,
+        NL80211_ATTR_BSS_SHORT_PREAMBLE,
+        NL80211_ATTR_BSS_SHORT_SLOT_TIME,
+
+        NL80211_ATTR_HT_CAPABILITY,
+
+        NL80211_ATTR_SUPPORTED_IFTYPES,
+
+        NL80211_ATTR_REG_ALPHA2,
+        NL80211_ATTR_REG_RULES,
+
         /* add attributes here, update the policy in nl80211.c */
 
         __NL80211_ATTR_AFTER_LAST,
         NL80211_ATTR_MAX = __NL80211_ATTR_AFTER_LAST - 1
 };
 
+/*
+ * Allow user space programs to use #ifdef on new attributes by defining them
+ * here
+ */
+#define NL80211_ATTR_HT_CAPABILITY NL80211_ATTR_HT_CAPABILITY
+
 #define NL80211_MAX_SUPP_RATES                  32
+#define NL80211_MAX_SUPP_REG_RULES              32
 #define NL80211_TKIP_DATA_OFFSET_ENCR_KEY       0
 #define NL80211_TKIP_DATA_OFFSET_TX_MIC_KEY     16
 #define NL80211_TKIP_DATA_OFFSET_RX_MIC_KEY     24
+#define NL80211_HT_CAPABILITY_LEN               26
 
 /**
  * enum nl80211_iftype - (virtual) interface types
@@ -436,6 +505,66 @@ enum nl80211_bitrate_attr {
 };
 
 /**
+ * enum nl80211_reg_rule_attr - regulatory rule attributes
+ * @NL80211_ATTR_REG_RULE_FLAGS: a set of flags which specify additional
+ *      considerations for a given frequency range. These are the
+ *      &enum nl80211_reg_rule_flags.
+ * @NL80211_ATTR_FREQ_RANGE_START: starting frequencry for the regulatory
+ *      rule in KHz. This is not a center of frequency but an actual regulatory
+ *      band edge.
+ * @NL80211_ATTR_FREQ_RANGE_END: ending frequency for the regulatory rule
+ *      in KHz. This is not a center a frequency but an actual regulatory
+ *      band edge.
+ * @NL80211_ATTR_FREQ_RANGE_MAX_BW: maximum allowed bandwidth for this
+ *      frequency range, in KHz.
+ * @NL80211_ATTR_POWER_RULE_MAX_ANT_GAIN: the maximum allowed antenna gain
+ *      for a given frequency range. The value is in mBi (100 * dBi).
+ *      If you don't have one then don't send this.
+ * @NL80211_ATTR_POWER_RULE_MAX_EIRP: the maximum allowed EIRP for
+ *      a given frequency range. The value is in mBm (100 * dBm).
+ */
+enum nl80211_reg_rule_attr {
+        __NL80211_REG_RULE_ATTR_INVALID,
+        NL80211_ATTR_REG_RULE_FLAGS,
+
+        NL80211_ATTR_FREQ_RANGE_START,
+        NL80211_ATTR_FREQ_RANGE_END,
+        NL80211_ATTR_FREQ_RANGE_MAX_BW,
+
+        NL80211_ATTR_POWER_RULE_MAX_ANT_GAIN,
+        NL80211_ATTR_POWER_RULE_MAX_EIRP,
+
+        /* keep last */
+        __NL80211_REG_RULE_ATTR_AFTER_LAST,
+        NL80211_REG_RULE_ATTR_MAX = __NL80211_REG_RULE_ATTR_AFTER_LAST - 1
+};
+
+/**
+ * enum nl80211_reg_rule_flags - regulatory rule flags
+ *
+ * @NL80211_RRF_NO_OFDM: OFDM modulation not allowed
+ * @NL80211_RRF_NO_CCK: CCK modulation not allowed
+ * @NL80211_RRF_NO_INDOOR: indoor operation not allowed
+ * @NL80211_RRF_NO_OUTDOOR: outdoor operation not allowed
+ * @NL80211_RRF_DFS: DFS support is required to be used
+ * @NL80211_RRF_PTP_ONLY: this is only for Point To Point links
+ * @NL80211_RRF_PTMP_ONLY: this is only for Point To Multi Point links
+ * @NL80211_RRF_PASSIVE_SCAN: passive scan is required
+ * @NL80211_RRF_NO_IBSS: no IBSS is allowed
+ */
+enum nl80211_reg_rule_flags {
+        NL80211_RRF_NO_OFDM             = 1<<0,
+        NL80211_RRF_NO_CCK              = 1<<1,
+        NL80211_RRF_NO_INDOOR           = 1<<2,
+        NL80211_RRF_NO_OUTDOOR          = 1<<3,
+        NL80211_RRF_DFS                 = 1<<4,
+        NL80211_RRF_PTP_ONLY            = 1<<5,
+        NL80211_RRF_PTMP_ONLY           = 1<<6,
+        NL80211_RRF_PASSIVE_SCAN        = 1<<7,
+        NL80211_RRF_NO_IBSS             = 1<<8,
+};
+
+/**
  * enum nl80211_mntr_flags - monitor configuration flags
  *
  * Monitor configuration flags.
diff --git a/include/linux/notifier.h b/include/linux/notifier.h
index da2698b0fdd1..b86fa2ffca0c 100644
--- a/include/linux/notifier.h
+++ b/include/linux/notifier.h
@@ -213,9 +213,16 @@ static inline int notifier_to_errno(int ret)
 #define CPU_DOWN_FAILED         0x0006 /* CPU (unsigned)v NOT going down */
 #define CPU_DEAD                0x0007 /* CPU (unsigned)v dead */
 #define CPU_DYING               0x0008 /* CPU (unsigned)v not running any task,
-                                        * not handling interrupts, soon dead */
+                                        * not handling interrupts, soon dead.
+                                        * Called on the dying cpu, interrupts
+                                        * are already disabled. Must not
+                                        * sleep, must not fail */
 #define CPU_POST_DEAD           0x0009 /* CPU (unsigned)v dead, cpu_hotplug
                                         * lock is dropped */
+#define CPU_STARTING            0x000A /* CPU (unsigned)v soon running.
+                                        * Called on the new cpu, just before
+                                        * enabling interrupts. Must not sleep,
+                                        * must not fail */
 
 /* Used for CPU hotplug events occuring while tasks are frozen due to a suspend
  * operation in progress
@@ -229,6 +236,7 @@ static inline int notifier_to_errno(int ret)
 #define CPU_DOWN_FAILED_FROZEN  (CPU_DOWN_FAILED | CPU_TASKS_FROZEN)
 #define CPU_DEAD_FROZEN         (CPU_DEAD | CPU_TASKS_FROZEN)
 #define CPU_DYING_FROZEN        (CPU_DYING | CPU_TASKS_FROZEN)
+#define CPU_STARTING_FROZEN     (CPU_STARTING | CPU_TASKS_FROZEN)
 
 /* Hibernation and suspend events */
 #define PM_HIBERNATION_PREPARE  0x0001 /* Going to hibernate */
diff --git a/include/linux/of.h b/include/linux/of.h
index 79886ade070f..e2488f5e7cb2 100644
--- a/include/linux/of.h
+++ b/include/linux/of.h
@@ -71,5 +71,8 @@ extern int of_n_size_cells(struct device_node *np);
 extern const struct of_device_id *of_match_node(
         const struct of_device_id *matches, const struct device_node *node);
 extern int of_modalias_node(struct device_node *node, char *modalias, int len);
+extern int of_parse_phandles_with_args(struct device_node *np,
+        const char *list_name, const char *cells_name, int index,
+        struct device_node **out_node, const void **out_args);
 
 #endif /* _LINUX_OF_H */
diff --git a/include/linux/oprofile.h b/include/linux/oprofile.h
index 041bb31100f4..bcb8f725427c 100644
--- a/include/linux/oprofile.h
+++ b/include/linux/oprofile.h
@@ -36,6 +36,8 @@
 #define XEN_ENTER_SWITCH_CODE           10
 #define SPU_PROFILING_CODE              11
 #define SPU_CTX_SWITCH_CODE             12
+#define IBS_FETCH_CODE                  13
+#define IBS_OP_CODE                     14
 
 struct super_block;
 struct dentry;
diff --git a/include/linux/parport.h b/include/linux/parport.h
index 6a0d7cdb5774..e1f83c5065c5 100644
--- a/include/linux/parport.h
+++ b/include/linux/parport.h
@@ -1,5 +1,3 @@
-/* $Id: parport.h,v 1.1 1998/05/17 10:57:52 andrea Exp andrea $ */
-
 /*
  * Any part of this program may be used in documents licensed under
  * the GNU Free Documentation License, Version 1.1 or any later version
diff --git a/include/linux/parser.h b/include/linux/parser.h
index 7dcd05075756..ea2281e726f6 100644
--- a/include/linux/parser.h
+++ b/include/linux/parser.h
@@ -25,7 +25,7 @@ typedef struct {
         char *to;
 } substring_t;
 
-int match_token(char *, match_table_t table, substring_t args[]);
+int match_token(char *, const match_table_t table, substring_t args[]);
 int match_int(substring_t *, int *result);
 int match_octal(substring_t *, int *result);
 int match_hex(substring_t *, int *result);
diff --git a/include/linux/pci.h b/include/linux/pci.h
index c0e14008a3c2..98dc6243a706 100644
--- a/include/linux/pci.h
+++ b/include/linux/pci.h
@@ -534,7 +534,7 @@ extern void pci_sort_breadthfirst(void);
 #ifdef CONFIG_PCI_LEGACY
 struct pci_dev __deprecated *pci_find_device(unsigned int vendor,
                                              unsigned int device,
-                                             const struct pci_dev *from);
+                                             struct pci_dev *from);
 struct pci_dev __deprecated *pci_find_slot(unsigned int bus,
                                            unsigned int devfn);
 #endif /* CONFIG_PCI_LEGACY */
@@ -550,7 +550,7 @@ struct pci_dev *pci_get_device(unsigned int vendor, unsigned int device,
                                 struct pci_dev *from);
 struct pci_dev *pci_get_subsys(unsigned int vendor, unsigned int device,
                                 unsigned int ss_vendor, unsigned int ss_device,
-                                const struct pci_dev *from);
+                                struct pci_dev *from);
 struct pci_dev *pci_get_slot(struct pci_bus *bus, unsigned int devfn);
 struct pci_dev *pci_get_bus_and_slot(unsigned int bus, unsigned int devfn);
 struct pci_dev *pci_get_class(unsigned int class, struct pci_dev *from);
@@ -816,7 +816,7 @@ _PCI_NOP_ALL(write,)
 
 static inline struct pci_dev *pci_find_device(unsigned int vendor,
                                               unsigned int device,
-                                              const struct pci_dev *from)
+                                              struct pci_dev *from)
 {
         return NULL;
 }
@@ -838,7 +838,7 @@ static inline struct pci_dev *pci_get_subsys(unsigned int vendor,
                                              unsigned int device,
                                              unsigned int ss_vendor,
                                              unsigned int ss_device,
-                                             const struct pci_dev *from)
+                                             struct pci_dev *from)
 {
         return NULL;
 }
diff --git a/include/linux/pci_ids.h b/include/linux/pci_ids.h
index f1624b396754..8edddc240e4f 100644
--- a/include/linux/pci_ids.h
+++ b/include/linux/pci_ids.h
@@ -497,6 +497,16 @@
 #define PCI_DEVICE_ID_AMD_K8_NB_ADDRMAP 0x1101
 #define PCI_DEVICE_ID_AMD_K8_NB_MEMCTL  0x1102
 #define PCI_DEVICE_ID_AMD_K8_NB_MISC    0x1103
+#define PCI_DEVICE_ID_AMD_10H_NB_HT     0x1200
+#define PCI_DEVICE_ID_AMD_10H_NB_MAP    0x1201
+#define PCI_DEVICE_ID_AMD_10H_NB_DRAM   0x1202
+#define PCI_DEVICE_ID_AMD_10H_NB_MISC   0x1203
+#define PCI_DEVICE_ID_AMD_10H_NB_LINK   0x1204
+#define PCI_DEVICE_ID_AMD_11H_NB_HT     0x1300
+#define PCI_DEVICE_ID_AMD_11H_NB_MAP    0x1301
+#define PCI_DEVICE_ID_AMD_11H_NB_DRAM   0x1302
+#define PCI_DEVICE_ID_AMD_11H_NB_MISC   0x1303
+#define PCI_DEVICE_ID_AMD_11H_NB_LINK   0x1304
 #define PCI_DEVICE_ID_AMD_LANCE         0x2000
 #define PCI_DEVICE_ID_AMD_LANCE_HOME    0x2001
 #define PCI_DEVICE_ID_AMD_SCSI          0x2020
@@ -577,6 +587,7 @@
 #define PCI_DEVICE_ID_MATROX_G200_PCI   0x0520
 #define PCI_DEVICE_ID_MATROX_G200_AGP   0x0521
 #define PCI_DEVICE_ID_MATROX_G400       0x0525
+#define PCI_DEVICE_ID_MATROX_G200EV_PCI 0x0530
 #define PCI_DEVICE_ID_MATROX_G550       0x2527
 #define PCI_DEVICE_ID_MATROX_VIA        0x4536
 
@@ -1411,6 +1422,8 @@
 #define PCI_DEVICE_ID_EICON_MAESTRAQ_U  0xe013
 #define PCI_DEVICE_ID_EICON_MAESTRAP    0xe014
 
+#define PCI_VENDOR_ID_CISCO             0x1137
+
 #define PCI_VENDOR_ID_ZIATECH           0x1138
 #define PCI_DEVICE_ID_ZIATECH_5550_HC   0x5550
  
@@ -1521,7 +1534,9 @@
 #define PCI_DEVICE_ID_MARVELL_GT64260   0x6430
 #define PCI_DEVICE_ID_MARVELL_MV64360   0x6460
 #define PCI_DEVICE_ID_MARVELL_MV64460   0x6480
-#define PCI_DEVICE_ID_MARVELL_CAFE_SD   0x4101
+#define PCI_DEVICE_ID_MARVELL_88ALP01_NAND      0x4100
+#define PCI_DEVICE_ID_MARVELL_88ALP01_SD        0x4101
+#define PCI_DEVICE_ID_MARVELL_88ALP01_CCIC      0x4102
 
 #define PCI_VENDOR_ID_V3                0x11b0
 #define PCI_DEVICE_ID_V3_V960           0x0001
@@ -2213,6 +2228,7 @@
 
 #define PCI_VENDOR_ID_ATTANSIC          0x1969
 #define PCI_DEVICE_ID_ATTANSIC_L1       0x1048
+#define PCI_DEVICE_ID_ATTANSIC_L2       0x2048
 
 #define PCI_VENDOR_ID_JMICRON           0x197B
 #define PCI_DEVICE_ID_JMICRON_JMB360    0x2360
@@ -2244,6 +2260,16 @@
 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2  0x0007
 #define PCI_DEVICE_ID_3DLABS_PERMEDIA2V 0x0009
 
+#define PCI_VENDOR_ID_NETXEN            0x4040
+#define PCI_DEVICE_ID_NX2031_10GXSR     0x0001
+#define PCI_DEVICE_ID_NX2031_10GCX4     0x0002
+#define PCI_DEVICE_ID_NX2031_4GCU       0x0003
+#define PCI_DEVICE_ID_NX2031_IMEZ       0x0004
+#define PCI_DEVICE_ID_NX2031_HMEZ       0x0005
+#define PCI_DEVICE_ID_NX2031_XG_MGMT    0x0024
+#define PCI_DEVICE_ID_NX2031_XG_MGMT2   0x0025
+#define PCI_DEVICE_ID_NX3031            0x0100
+
 #define PCI_VENDOR_ID_AKS               0x416c
 #define PCI_DEVICE_ID_AKS_ALADDINCARD   0x0100
 
diff --git a/include/linux/percpu.h b/include/linux/percpu.h
index fac3337547eb..9f2a3751873a 100644
--- a/include/linux/percpu.h
+++ b/include/linux/percpu.h
@@ -23,12 +23,19 @@
         __attribute__((__section__(SHARED_ALIGNED_SECTION)))            \
         PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name             \
         ____cacheline_aligned_in_smp
+
+#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name)                 \
+        __attribute__((__section__(".data.percpu.page_aligned")))       \
+        PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
 #else
 #define DEFINE_PER_CPU(type, name)                                      \
         PER_CPU_ATTRIBUTES __typeof__(type) per_cpu__##name
 
 #define DEFINE_PER_CPU_SHARED_ALIGNED(type, name)                     \
         DEFINE_PER_CPU(type, name)
+
+#define DEFINE_PER_CPU_PAGE_ALIGNED(type, name)               \
+        DEFINE_PER_CPU(type, name)
 #endif
 
 #define EXPORT_PER_CPU_SYMBOL(var) EXPORT_SYMBOL(per_cpu__##var)
diff --git a/include/linux/percpu_counter.h b/include/linux/percpu_counter.h
index 208388835357..9007ccdfc112 100644
--- a/include/linux/percpu_counter.h
+++ b/include/linux/percpu_counter.h
@@ -35,7 +35,7 @@ int percpu_counter_init_irq(struct percpu_counter *fbc, s64 amount);
 void percpu_counter_destroy(struct percpu_counter *fbc);
 void percpu_counter_set(struct percpu_counter *fbc, s64 amount);
 void __percpu_counter_add(struct percpu_counter *fbc, s64 amount, s32 batch);
-s64 __percpu_counter_sum(struct percpu_counter *fbc, int set);
+s64 __percpu_counter_sum(struct percpu_counter *fbc);
 
 static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount)
 {
@@ -44,19 +44,13 @@ static inline void percpu_counter_add(struct percpu_counter *fbc, s64 amount)
 
 static inline s64 percpu_counter_sum_positive(struct percpu_counter *fbc)
 {
-        s64 ret = __percpu_counter_sum(fbc, 0);
+        s64 ret = __percpu_counter_sum(fbc);
         return ret < 0 ? 0 : ret;
 }
 
-static inline s64 percpu_counter_sum_and_set(struct percpu_counter *fbc)
-{
-        return __percpu_counter_sum(fbc, 1);
-}
-
-
 static inline s64 percpu_counter_sum(struct percpu_counter *fbc)
 {
-        return __percpu_counter_sum(fbc, 0);
+        return __percpu_counter_sum(fbc);
 }
 
 static inline s64 percpu_counter_read(struct percpu_counter *fbc)
diff --git a/include/linux/pfkeyv2.h b/include/linux/pfkeyv2.h
index 700725ddcaae..01b262959f2e 100644
--- a/include/linux/pfkeyv2.h
+++ b/include/linux/pfkeyv2.h
@@ -226,6 +226,15 @@ struct sadb_x_sec_ctx {
 } __attribute__((packed));
 /* sizeof(struct sadb_sec_ctx) = 8 */
 
+/* Used by MIGRATE to pass addresses IKE will use to perform
+ * negotiation with the peer */
+struct sadb_x_kmaddress {
+        uint16_t        sadb_x_kmaddress_len;
+        uint16_t        sadb_x_kmaddress_exttype;
+        uint32_t        sadb_x_kmaddress_reserved;
+} __attribute__((packed));
+/* sizeof(struct sadb_x_kmaddress) == 8 */
+
 /* Message types */
 #define SADB_RESERVED           0
 #define SADB_GETSPI             1
@@ -346,7 +355,9 @@ struct sadb_x_sec_ctx {
 #define SADB_X_EXT_NAT_T_DPORT          22
 #define SADB_X_EXT_NAT_T_OA             23
 #define SADB_X_EXT_SEC_CTX              24
-#define SADB_EXT_MAX                    24
+/* Used with MIGRATE to pass @ to IKE for negotiation */
+#define SADB_X_EXT_KMADDRESS            25
+#define SADB_EXT_MAX                    25
 
 /* Identity Extension values */
 #define SADB_IDENTTYPE_RESERVED 0
diff --git a/include/linux/pfn.h b/include/linux/pfn.h
index bb01f8b92b56..7646637221f3 100644
--- a/include/linux/pfn.h
+++ b/include/linux/pfn.h
@@ -1,9 +1,13 @@
 #ifndef _LINUX_PFN_H_
 #define _LINUX_PFN_H_
 
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+
 #define PFN_ALIGN(x)    (((unsigned long)(x) + (PAGE_SIZE - 1)) & PAGE_MASK)
 #define PFN_UP(x)       (((x) + PAGE_SIZE-1) >> PAGE_SHIFT)
 #define PFN_DOWN(x)     ((x) >> PAGE_SHIFT)
-#define PFN_PHYS(x)     ((x) << PAGE_SHIFT)
+#define PFN_PHYS(x)     ((phys_addr_t)(x) << PAGE_SHIFT)
 
 #endif
diff --git a/include/linux/phonet.h b/include/linux/phonet.h
new file mode 100644
index 000000000000..c9609f9aedac
--- /dev/null
+++ b/include/linux/phonet.h
@@ -0,0 +1,170 @@
+/**
+ * file phonet.h
+ *
+ * Phonet sockets kernel interface
+ *
+ * Copyright (C) 2008 Nokia Corporation. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef LINUX_PHONET_H
+#define LINUX_PHONET_H
+
+/* Automatic protocol selection */
+#define PN_PROTO_TRANSPORT      0
+/* Phonet datagram socket */
+#define PN_PROTO_PHONET         1
+/* Phonet pipe */
+#define PN_PROTO_PIPE           2
+#define PHONET_NPROTO           3
+
+/* Socket options for SOL_PNPIPE level */
+#define PNPIPE_ENCAP            1
+#define PNPIPE_IFINDEX          2
+
+#define PNADDR_ANY              0
+#define PNPORT_RESOURCE_ROUTING 0
+
+/* Values for PNPIPE_ENCAP option */
+#define PNPIPE_ENCAP_NONE       0
+#define PNPIPE_ENCAP_IP         1
+
+/* ioctls */
+#define SIOCPNGETOBJECT         (SIOCPROTOPRIVATE + 0)
+
+/* Phonet protocol header */
+struct phonethdr {
+        __u8    pn_rdev;
+        __u8    pn_sdev;
+        __u8    pn_res;
+        __be16  pn_length;
+        __u8    pn_robj;
+        __u8    pn_sobj;
+} __attribute__((packed));
+
+/* Common Phonet payload header */
+struct phonetmsg {
+        __u8    pn_trans_id;    /* transaction ID */
+        __u8    pn_msg_id;      /* message type */
+        union {
+                struct {
+                        __u8    pn_submsg_id;   /* message subtype */
+                        __u8    pn_data[5];
+                } base;
+                struct {
+                        __u16   pn_e_res_id;    /* extended resource ID */
+                        __u8    pn_e_submsg_id; /* message subtype */
+                        __u8    pn_e_data[3];
+                } ext;
+        } pn_msg_u;
+};
+#define PN_COMMON_MESSAGE       0xF0
+#define PN_PREFIX               0xE0 /* resource for extended messages */
+#define pn_submsg_id            pn_msg_u.base.pn_submsg_id
+#define pn_e_submsg_id          pn_msg_u.ext.pn_e_submsg_id
+#define pn_e_res_id             pn_msg_u.ext.pn_e_res_id
+#define pn_data                 pn_msg_u.base.pn_data
+#define pn_e_data               pn_msg_u.ext.pn_e_data
+
+/* data for unreachable errors */
+#define PN_COMM_SERVICE_NOT_IDENTIFIED_RESP     0x01
+#define PN_COMM_ISA_ENTITY_NOT_REACHABLE_RESP   0x14
+#define pn_orig_msg_id          pn_data[0]
+#define pn_status               pn_data[1]
+#define pn_e_orig_msg_id        pn_e_data[0]
+#define pn_e_status             pn_e_data[1]
+
+/* Phonet socket address structure */
+struct sockaddr_pn {
+        sa_family_t spn_family;
+        __u8 spn_obj;
+        __u8 spn_dev;
+        __u8 spn_resource;
+        __u8 spn_zero[sizeof(struct sockaddr) - sizeof(sa_family_t) - 3];
+} __attribute__ ((packed));
+
+static inline __u16 pn_object(__u8 addr, __u16 port)
+{
+        return (addr << 8) | (port & 0x3ff);
+}
+
+static inline __u8 pn_obj(__u16 handle)
+{
+        return handle & 0xff;
+}
+
+static inline __u8 pn_dev(__u16 handle)
+{
+        return handle >> 8;
+}
+
+static inline __u16 pn_port(__u16 handle)
+{
+        return handle & 0x3ff;
+}
+
+static inline __u8 pn_addr(__u16 handle)
+{
+        return (handle >> 8) & 0xfc;
+}
+
+static inline void pn_sockaddr_set_addr(struct sockaddr_pn *spn, __u8 addr)
+{
+        spn->spn_dev &= 0x03;
+        spn->spn_dev |= addr & 0xfc;
+}
+
+static inline void pn_sockaddr_set_port(struct sockaddr_pn *spn, __u16 port)
+{
+        spn->spn_dev &= 0xfc;
+        spn->spn_dev |= (port >> 8) & 0x03;
+        spn->spn_obj = port & 0xff;
+}
+
+static inline void pn_sockaddr_set_object(struct sockaddr_pn *spn,
+                                                __u16 handle)
+{
+        spn->spn_dev = pn_dev(handle);
+        spn->spn_obj = pn_obj(handle);
+}
+
+static inline void pn_sockaddr_set_resource(struct sockaddr_pn *spn,
+                                                __u8 resource)
+{
+        spn->spn_resource = resource;
+}
+
+static inline __u8 pn_sockaddr_get_addr(const struct sockaddr_pn *spn)
+{
+        return spn->spn_dev & 0xfc;
+}
+
+static inline __u16 pn_sockaddr_get_port(const struct sockaddr_pn *spn)
+{
+        return ((spn->spn_dev & 0x03) << 8) | spn->spn_obj;
+}
+
+static inline __u16 pn_sockaddr_get_object(const struct sockaddr_pn *spn)
+{
+        return pn_object(spn->spn_dev, spn->spn_obj);
+}
+
+static inline __u8 pn_sockaddr_get_resource(const struct sockaddr_pn *spn)
+{
+        return spn->spn_resource;
+}
+
+#endif
diff --git a/include/linux/phy.h b/include/linux/phy.h
index 7224c4099a28..77c4ed60b982 100644
--- a/include/linux/phy.h
+++ b/include/linux/phy.h
@@ -99,7 +99,14 @@ struct mii_bus {
          */
         struct mutex mdio_lock;
 
-        struct device *dev;
+        struct device *parent;
+        enum {
+                MDIOBUS_ALLOCATED = 1,
+                MDIOBUS_REGISTERED,
+                MDIOBUS_UNREGISTERED,
+                MDIOBUS_RELEASED,
+        } state;
+        struct device dev;
 
         /* list of all PHYs on bus */
         struct phy_device *phy_map[PHY_MAX_ADDR];
@@ -113,6 +120,16 @@ struct mii_bus {
          */
         int *irq;
 };
+#define to_mii_bus(d) container_of(d, struct mii_bus, dev)
+
+struct mii_bus *mdiobus_alloc(void);
+int mdiobus_register(struct mii_bus *bus);
+void mdiobus_unregister(struct mii_bus *bus);
+void mdiobus_free(struct mii_bus *bus);
+struct phy_device *mdiobus_scan(struct mii_bus *bus, int addr);
+int mdiobus_read(struct mii_bus *bus, int addr, u16 regnum);
+int mdiobus_write(struct mii_bus *bus, int addr, u16 regnum, u16 val);
+
 
 #define PHY_INTERRUPT_DISABLED  0x0
 #define PHY_INTERRUPT_ENABLED   0x80000000
@@ -391,8 +408,35 @@ struct phy_fixup {
         int (*run)(struct phy_device *phydev);
 };
 
-int phy_read(struct phy_device *phydev, u16 regnum);
-int phy_write(struct phy_device *phydev, u16 regnum, u16 val);
+/**
+ * phy_read - Convenience function for reading a given PHY register
+ * @phydev: the phy_device struct
+ * @regnum: register number to read
+ *
+ * NOTE: MUST NOT be called from interrupt context,
+ * because the bus read/write functions may wait for an interrupt
+ * to conclude the operation.
+ */
+static inline int phy_read(struct phy_device *phydev, u16 regnum)
+{
+        return mdiobus_read(phydev->bus, phydev->addr, regnum);
+}
+
+/**
+ * phy_write - Convenience function for writing a given PHY register
+ * @phydev: the phy_device struct
+ * @regnum: register number to write
+ * @val: value to write to @regnum
+ *
+ * NOTE: MUST NOT be called from interrupt context,
+ * because the bus read/write functions may wait for an interrupt
+ * to conclude the operation.
+ */
+static inline int phy_write(struct phy_device *phydev, u16 regnum, u16 val)
+{
+        return mdiobus_write(phydev->bus, phydev->addr, regnum, val);
+}
+
 int get_phy_id(struct mii_bus *bus, int addr, u32 *phy_id);
 struct phy_device* get_phy_device(struct mii_bus *bus, int addr);
 int phy_clear_interrupt(struct phy_device *phydev);
@@ -408,8 +452,6 @@ void phy_start(struct phy_device *phydev);
 void phy_stop(struct phy_device *phydev);
 int phy_start_aneg(struct phy_device *phydev);
 
-int mdiobus_register(struct mii_bus *bus);
-void mdiobus_unregister(struct mii_bus *bus);
 void phy_sanitize_settings(struct phy_device *phydev);
 int phy_stop_interrupts(struct phy_device *phydev);
 int phy_enable_interrupts(struct phy_device *phydev);
diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h
index 1af82c4e17d4..d82fe825d62f 100644
--- a/include/linux/pid_namespace.h
+++ b/include/linux/pid_namespace.h
@@ -84,12 +84,6 @@ static inline struct pid_namespace *task_active_pid_ns(struct task_struct *tsk)
         return tsk->nsproxy->pid_ns;
 }
 
-static inline struct task_struct *task_child_reaper(struct task_struct *tsk)
-{
-        BUG_ON(tsk != current);
-        return tsk->nsproxy->pid_ns->child_reaper;
-}
-
 void pidhash_init(void);
 void pidmap_init(void);
 
diff --git a/include/linux/pim.h b/include/linux/pim.h
index 236ffd317394..1ba0661561a4 100644
--- a/include/linux/pim.h
+++ b/include/linux/pim.h
@@ -3,22 +3,6 @@
 
 #include <asm/byteorder.h>
 
-#ifndef __KERNEL__
-struct pim {
-#if defined(__LITTLE_ENDIAN_BITFIELD)
-        __u8    pim_type:4,             /* PIM message type */
-                pim_ver:4;              /* PIM version */
-#elif defined(__BIG_ENDIAN_BITFIELD)
-        __u8    pim_ver:4;              /* PIM version */
-                pim_type:4;             /* PIM message type */
-#endif
-        __u8    pim_rsv;                /* Reserved */
-        __be16  pim_cksum;              /* Checksum */
-};
-
-#define PIM_MINLEN              8
-#endif
-
 /* Message types - V1 */
 #define PIM_V1_VERSION          __constant_htonl(0x10000000)
 #define PIM_V1_REGISTER         1
@@ -27,7 +11,6 @@ struct pim {
 #define PIM_VERSION             2
 #define PIM_REGISTER            1
 
-#if defined(__KERNEL__)
 #define PIM_NULL_REGISTER       __constant_htonl(0x40000000)
 
 /* PIMv2 register message header layout (ietf-draft-idmr-pimvsm-v2-00.ps */
@@ -42,4 +25,3 @@ struct pimreghdr
 struct sk_buff;
 extern int pim_rcv_v1(struct sk_buff *);
 #endif
-#endif
diff --git a/include/linux/pkt_sched.h b/include/linux/pkt_sched.h
index e5de421ac7b4..5d921fa91a5b 100644
--- a/include/linux/pkt_sched.h
+++ b/include/linux/pkt_sched.h
@@ -123,6 +123,13 @@ struct tc_prio_qopt
         __u8    priomap[TC_PRIO_MAX+1]; /* Map: logical priority -> PRIO band */
 };
 
+/* MULTIQ section */
+
+struct tc_multiq_qopt {
+        __u16   bands;                  /* Number of bands */
+        __u16   max_bands;              /* Maximum number of queues */
+};
+
 /* TBF section */
 
 struct tc_tbf_qopt
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 95ac21ab3a09..4b8cc6a32479 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -37,6 +37,8 @@ extern int platform_add_devices(struct platform_device **, int);
 
 extern struct platform_device *platform_device_register_simple(const char *, int id,
                                         struct resource *, unsigned int);
+extern struct platform_device *platform_device_register_data(struct device *,
+                const char *, int, const void *, size_t);
 
 extern struct platform_device *platform_device_alloc(const char *name, int id);
 extern int platform_device_add_resources(struct platform_device *pdev, struct resource *res, unsigned int num);
diff --git a/include/linux/pm.h b/include/linux/pm.h
index 4dcce54b6d76..42de4003c4ee 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -419,7 +419,7 @@ extern void __suspend_report_result(const char *function, void *fn, int ret);
 
 #define suspend_report_result(fn, ret)                                  \
         do {                                                            \
-                __suspend_report_result(__FUNCTION__, fn, ret);         \
+                __suspend_report_result(__func__, fn, ret);             \
         } while (0)
 
 #else /* !CONFIG_PM_SLEEP */
diff --git a/include/linux/pnp.h b/include/linux/pnp.h
index 1ce54b63085d..53b70fd1d9a5 100644
--- a/include/linux/pnp.h
+++ b/include/linux/pnp.h
@@ -21,7 +21,16 @@ struct pnp_dev;
 /*
  * Resource Management
  */
-struct resource *pnp_get_resource(struct pnp_dev *, unsigned int, unsigned int);
+#ifdef CONFIG_PNP
+struct resource *pnp_get_resource(struct pnp_dev *dev, unsigned long type,
+                                unsigned int num);
+#else
+static inline struct resource *pnp_get_resource(struct pnp_dev *dev,
+                        unsigned long type, unsigned int num)
+{
+        return NULL;
+}
+#endif
 
 static inline int pnp_resource_valid(struct resource *res)
 {
diff --git a/include/linux/posix-timers.h b/include/linux/posix-timers.h
index a7dd38f30ade..a7c721355549 100644
--- a/include/linux/posix-timers.h
+++ b/include/linux/posix-timers.h
@@ -45,8 +45,6 @@ struct k_itimer {
         int it_requeue_pending;         /* waiting to requeue this timer */
 #define REQUEUE_PENDING 1
         int it_sigev_notify;            /* notify word of sigevent struct */
-        int it_sigev_signo;             /* signo word of sigevent struct */
-        sigval_t it_sigev_value;        /* value word of sigevent struct */
         struct task_struct *it_process; /* process to send signal to */
         struct sigqueue *sigq;          /* signal queue entry. */
         union {
@@ -115,4 +113,6 @@ void set_process_cpu_timer(struct task_struct *task, unsigned int clock_idx,
 
 long clock_nanosleep_restart(struct restart_block *restart_block);
 
+void update_rlimit_cpu(unsigned long rlim_new);
+
 #endif
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h
index fb61850d1cfc..27d534f4470d 100644
--- a/include/linux/proc_fs.h
+++ b/include/linux/proc_fs.h
@@ -139,7 +139,6 @@ extern int proc_readdir(struct file *, void *, filldir_t);
 extern struct dentry *proc_lookup(struct inode *, struct dentry *, struct nameidata *);
 
 extern const struct file_operations proc_kcore_operations;
-extern const struct file_operations ppc_htab_operations;
 
 extern int pid_ns_prepare_proc(struct pid_namespace *ns);
 extern void pid_ns_release_proc(struct pid_namespace *ns);
diff --git a/include/linux/profile.h b/include/linux/profile.h
index 7e7087239af5..570045053ce9 100644
--- a/include/linux/profile.h
+++ b/include/linux/profile.h
@@ -35,7 +35,9 @@ enum profile_type {
 extern int prof_on __read_mostly;
 
 /* init basic kernel profiler */
-void __init profile_init(void);
+int profile_init(void);
+int profile_setup(char *str);
+int create_proc_profile(void);
 void profile_tick(int type);
 
 /*
@@ -84,9 +86,9 @@ struct pt_regs;
 
 #define prof_on 0
 
-static inline void profile_init(void)
+static inline int profile_init(void)
 {
-        return;
+        return 0;
 }
 
 static inline void profile_tick(int type)
diff --git a/include/linux/proportions.h b/include/linux/proportions.h
index 5afc1b23346d..cf793bbbd05e 100644
--- a/include/linux/proportions.h
+++ b/include/linux/proportions.h
@@ -104,8 +104,8 @@ struct prop_local_single {
          * snapshot of the last seen global state
          * and a lock protecting this state
          */
-        int shift;
         unsigned long period;
+        int shift;
         spinlock_t lock;                /* protect the snapshot state */
 };
 
diff --git a/include/linux/quicklist.h b/include/linux/quicklist.h
index 39b66713a0bb..bd466439c588 100644
--- a/include/linux/quicklist.h
+++ b/include/linux/quicklist.h
@@ -80,6 +80,13 @@ void quicklist_trim(int nr, void (*dtor)(void *),
 
 unsigned long quicklist_total_size(void);
 
+#else
+
+static inline unsigned long quicklist_total_size(void)
+{
+        return 0;
+}
+
 #endif
 
 #endif /* LINUX_QUICKLIST_H */
diff --git a/include/linux/quota.h b/include/linux/quota.h
index 376a05048bc5..40401b554484 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -28,8 +28,6 @@
  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
  * SUCH DAMAGE.
- *
- * Version: $Id: quota.h,v 2.0 1996/11/17 16:48:14 mvw Exp mvw $
  */
 
 #ifndef _LINUX_QUOTA_
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index ca6b9b5c8d52..a558a4c1d35a 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -3,9 +3,6 @@
  * macros expand to the right source-code.
  *
  * Author:  Marco van Wieringen <mvw@planets.elm.net>
- *
- * Version: $Id: quotaops.h,v 1.2 1998/01/15 16:22:26 ecd Exp $
- *
  */
 #ifndef _LINUX_QUOTAOPS_
 #define _LINUX_QUOTAOPS_
diff --git a/include/linux/raid/linear.h b/include/linux/raid/linear.h
index 7e375111d007..f38b9c586afb 100644
--- a/include/linux/raid/linear.h
+++ b/include/linux/raid/linear.h
@@ -5,8 +5,8 @@
 
 struct dev_info {
         mdk_rdev_t      *rdev;
-        sector_t        size;
-        sector_t        offset;
+        sector_t        num_sectors;
+        sector_t        start_sector;
 };
 
 typedef struct dev_info dev_info_t;
@@ -15,9 +15,11 @@ struct linear_private_data
 {
         struct linear_private_data *prev;       /* earlier version */
         dev_info_t              **hash_table;
-        sector_t                hash_spacing;
+        sector_t                spacing;
         sector_t                array_sectors;
-        int                     preshift; /* shift before dividing by hash_spacing */
+        int                     sector_shift;   /* shift before dividing
+                                                 * by spacing
+                                                 */
         dev_info_t              disks[0];
 };
 
diff --git a/include/linux/raid/md.h b/include/linux/raid/md.h
index dc0e3fcb9f28..82bea14cae1a 100644
--- a/include/linux/raid/md.h
+++ b/include/linux/raid/md.h
@@ -19,27 +19,7 @@
 #define _MD_H
 
 #include <linux/blkdev.h>
-#include <linux/major.h>
-#include <linux/ioctl.h>
-#include <linux/types.h>
-#include <linux/bitops.h>
-#include <linux/module.h>
-#include <linux/hdreg.h>
-#include <linux/proc_fs.h>
 #include <linux/seq_file.h>
-#include <linux/smp_lock.h>
-#include <linux/delay.h>
-#include <net/checksum.h>
-#include <linux/random.h>
-#include <linux/kernel_stat.h>
-#include <asm/io.h>
-#include <linux/completion.h>
-#include <linux/mempool.h>
-#include <linux/list.h>
-#include <linux/reboot.h>
-#include <linux/vmalloc.h>
-#include <linux/blkpg.h>
-#include <linux/bio.h>
 
 /*
  * 'md_p.h' holds the 'physical' layout of RAID devices
@@ -74,19 +54,17 @@
 
 extern int mdp_major;
 
-extern int register_md_personality (struct mdk_personality *p);
-extern int unregister_md_personality (struct mdk_personality *p);
-extern mdk_thread_t * md_register_thread (void (*run) (mddev_t *mddev),
+extern int register_md_personality(struct mdk_personality *p);
+extern int unregister_md_personality(struct mdk_personality *p);
+extern mdk_thread_t * md_register_thread(void (*run) (mddev_t *mddev),
                                 mddev_t *mddev, const char *name);
-extern void md_unregister_thread (mdk_thread_t *thread);
+extern void md_unregister_thread(mdk_thread_t *thread);
 extern void md_wakeup_thread(mdk_thread_t *thread);
 extern void md_check_recovery(mddev_t *mddev);
 extern void md_write_start(mddev_t *mddev, struct bio *bi);
 extern void md_write_end(mddev_t *mddev);
-extern void md_handle_safemode(mddev_t *mddev);
 extern void md_done_sync(mddev_t *mddev, int blocks, int ok);
-extern void md_error (mddev_t *mddev, mdk_rdev_t *rdev);
-extern void md_unplug_mddev(mddev_t *mddev);
+extern void md_error(mddev_t *mddev, mdk_rdev_t *rdev);
 
 extern void md_super_write(mddev_t *mddev, mdk_rdev_t *rdev,
                            sector_t sector, int size, struct page *page);
diff --git a/include/linux/ramfs.h b/include/linux/ramfs.h
index b160fb18e8d6..37aaf2b39863 100644
--- a/include/linux/ramfs.h
+++ b/include/linux/ramfs.h
@@ -6,6 +6,7 @@ extern int ramfs_get_sb(struct file_system_type *fs_type,
          int flags, const char *dev_name, void *data, struct vfsmount *mnt);
 
 #ifndef CONFIG_MMU
+extern int ramfs_nommu_expand_for_mapping(struct inode *inode, size_t newsize);
 extern unsigned long ramfs_nommu_get_unmapped_area(struct file *file,
                                                    unsigned long addr,
                                                    unsigned long len,
diff --git a/include/linux/rcuclassic.h b/include/linux/rcuclassic.h
index 4ab843622727..5f89b62e6983 100644
--- a/include/linux/rcuclassic.h
+++ b/include/linux/rcuclassic.h
@@ -40,12 +40,21 @@
 #include <linux/cpumask.h>
 #include <linux/seqlock.h>
 
+#ifdef CONFIG_RCU_CPU_STALL_DETECTOR
+#define RCU_SECONDS_TILL_STALL_CHECK    ( 3 * HZ) /* for rcp->jiffies_stall */
+#define RCU_SECONDS_TILL_STALL_RECHECK  (30 * HZ) /* for rcp->jiffies_stall */
+#endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */
 
 /* Global control variables for rcupdate callback mechanism. */
 struct rcu_ctrlblk {
         long    cur;            /* Current batch number.                      */
         long    completed;      /* Number of the last completed batch         */
-        int     next_pending;   /* Is the next batch already waiting?         */
+        long    pending;        /* Number of the last pending batch           */
+#ifdef CONFIG_RCU_CPU_STALL_DETECTOR
+        unsigned long gp_start; /* Time at which GP started in jiffies. */
+        unsigned long jiffies_stall;
+                                /* Time at which to check for CPU stalls. */
+#endif /* #ifdef CONFIG_RCU_CPU_STALL_DETECTOR */
 
         int     signaled;
 
@@ -66,11 +75,7 @@ static inline int rcu_batch_after(long a, long b)
         return (a - b) > 0;
 }
 
-/*
- * Per-CPU data for Read-Copy UPdate.
- * nxtlist - new callbacks are added here
- * curlist - current batch for which quiescent cycle started if any
- */
+/* Per-CPU data for Read-Copy UPdate. */
 struct rcu_data {
         /* 1) quiescent state handling : */
         long            quiescbatch;     /* Batch # for grace period */
@@ -78,12 +83,24 @@ struct rcu_data {
         int             qs_pending;      /* core waits for quiesc state */
 
         /* 2) batch handling */
-        long            batch;           /* Batch # for current RCU batch */
+        /*
+         * if nxtlist is not NULL, then:
+         * batch:
+         *      The batch # for the last entry of nxtlist
+         * [*nxttail[1], NULL = *nxttail[2]):
+         *      Entries that batch # <= batch
+         * [*nxttail[0], *nxttail[1]):
+         *      Entries that batch # <= batch - 1
+         * [nxtlist, *nxttail[0]):
+         *      Entries that batch # <= batch - 2
+         *      The grace period for these entries has completed, and
+         *      the other grace-period-completed entries may be moved
+         *      here temporarily in rcu_process_callbacks().
+         */
+        long            batch;
         struct rcu_head *nxtlist;
-        struct rcu_head **nxttail;
+        struct rcu_head **nxttail[3];
         long            qlen;            /* # of queued callbacks */
-        struct rcu_head *curlist;
-        struct rcu_head **curtail;
         struct rcu_head *donelist;
         struct rcu_head **donetail;
         long            blimit;          /* Upper limit on a processed batch */
diff --git a/include/linux/rculist.h b/include/linux/rculist.h
index eb4443c7e05b..e649bd3f2c97 100644
--- a/include/linux/rculist.h
+++ b/include/linux/rculist.h
@@ -198,20 +198,6 @@ static inline void list_splice_init_rcu(struct list_head *list,
         at->prev = last;
 }
 
-/**
- * list_for_each_rcu    -       iterate over an rcu-protected list
- * @pos:        the &struct list_head to use as a loop cursor.
- * @head:       the head for your list.
- *
- * This list-traversal primitive may safely run concurrently with
- * the _rcu list-mutation primitives such as list_add_rcu()
- * as long as the traversal is guarded by rcu_read_lock().
- */
-#define list_for_each_rcu(pos, head) \
-        for (pos = rcu_dereference((head)->next); \
-                prefetch(pos->next), pos != (head); \
-                pos = rcu_dereference(pos->next))
-
 #define __list_for_each_rcu(pos, head) \
         for (pos = rcu_dereference((head)->next); \
                 pos != (head); \
diff --git a/include/linux/rcupdate.h b/include/linux/rcupdate.h
index e8b4039cfb2f..86f1f5e43e33 100644
--- a/include/linux/rcupdate.h
+++ b/include/linux/rcupdate.h
@@ -133,6 +133,26 @@ struct rcu_head {
 #define rcu_read_unlock_bh() __rcu_read_unlock_bh()
 
 /**
+ * rcu_read_lock_sched - mark the beginning of a RCU-classic critical section
+ *
+ * Should be used with either
+ * - synchronize_sched()
+ * or
+ * - call_rcu_sched() and rcu_barrier_sched()
+ * on the write-side to insure proper synchronization.
+ */
+#define rcu_read_lock_sched() preempt_disable()
+
+/*
+ * rcu_read_unlock_sched - marks the end of a RCU-classic critical section
+ *
+ * See rcu_read_lock_sched for more information.
+ */
+#define rcu_read_unlock_sched() preempt_enable()
+
+
+
+/**
  * rcu_dereference - fetch an RCU-protected pointer in an
  * RCU read-side critical section.  This pointer may later
  * be safely dereferenced.
diff --git a/include/linux/rcupreempt.h b/include/linux/rcupreempt.h
index 0967f03b0705..3e05c09b54a2 100644
--- a/include/linux/rcupreempt.h
+++ b/include/linux/rcupreempt.h
@@ -57,7 +57,13 @@ static inline void rcu_qsctr_inc(int cpu)
         rdssp->sched_qs++;
 }
 #define rcu_bh_qsctr_inc(cpu)
-#define call_rcu_bh(head, rcu) call_rcu(head, rcu)
+
+/*
+ * Someone might want to pass call_rcu_bh as a function pointer.
+ * So this needs to just be a rename and not a macro function.
+ *  (no parentheses)
+ */
+#define call_rcu_bh             call_rcu
 
 /**
  * call_rcu_sched - Queue RCU callback for invocation after sched grace period.
@@ -111,7 +117,6 @@ extern struct rcupreempt_trace *rcupreempt_trace_cpu(int cpu);
 struct softirq_action;
 
 #ifdef CONFIG_NO_HZ
-DECLARE_PER_CPU(struct rcu_dyntick_sched, rcu_dyntick_sched);
 
 static inline void rcu_enter_nohz(void)
 {
@@ -126,8 +131,8 @@ static inline void rcu_exit_nohz(void)
 {
         static DEFINE_RATELIMIT_STATE(rs, 10 * HZ, 1);
 
-        smp_mb(); /* CPUs seeing ++ must see later RCU read-side crit sects */
         __get_cpu_var(rcu_dyntick_sched).dynticks++;
+        smp_mb(); /* CPUs seeing ++ must see later RCU read-side crit sects */
         WARN_ON_RATELIMIT(!(__get_cpu_var(rcu_dyntick_sched).dynticks & 0x1),
                                 &rs);
 }
diff --git a/include/linux/regulator/driver.h b/include/linux/regulator/driver.h
index 1d712c7172a2..e37d80561985 100644
--- a/include/linux/regulator/driver.h
+++ b/include/linux/regulator/driver.h
@@ -18,8 +18,8 @@
 #include <linux/device.h>
 #include <linux/regulator/consumer.h>
 
-struct regulator_constraints;
 struct regulator_dev;
+struct regulator_init_data;
 
 /**
  * struct regulator_ops - regulator operations.
@@ -51,7 +51,7 @@ struct regulator_ops {
                                           int output_uV, int load_uA);
 
         /* the operations below are for configuration of regulator state when
-         * it's parent PMIC enters a global STANBY/HIBERNATE state */
+         * its parent PMIC enters a global STANDBY/HIBERNATE state */
 
         /* set regulator suspend voltage */
         int (*set_suspend_voltage) (struct regulator_dev *, int uV);
@@ -85,15 +85,17 @@ struct regulator_desc {
         struct module *owner;
 };
 
-
 struct regulator_dev *regulator_register(struct regulator_desc *regulator_desc,
-                                          void *reg_data);
+        struct device *dev, void *driver_data);
 void regulator_unregister(struct regulator_dev *rdev);
 
 int regulator_notifier_call_chain(struct regulator_dev *rdev,
                                   unsigned long event, void *data);
 
 void *rdev_get_drvdata(struct regulator_dev *rdev);
+struct device *rdev_get_dev(struct regulator_dev *rdev);
 int rdev_get_id(struct regulator_dev *rdev);
 
+void *regulator_get_init_drvdata(struct regulator_init_data *reg_init_data);
+
 #endif
diff --git a/include/linux/regulator/machine.h b/include/linux/regulator/machine.h
index 11e737dbfcf2..c6d69331a81e 100644
--- a/include/linux/regulator/machine.h
+++ b/include/linux/regulator/machine.h
@@ -89,15 +89,33 @@ struct regulation_constraints {
         unsigned apply_uV:1;    /* apply uV constraint iff min == max */
 };
 
-int regulator_set_supply(const char *regulator, const char *regulator_supply);
+/**
+ * struct regulator_consumer_supply - supply -> device mapping
+ *
+ * This maps a supply name to a device.
+ */
+struct regulator_consumer_supply {
+        struct device *dev;     /* consumer */
+        const char *supply;     /* consumer supply - e.g. "vcc" */
+};
 
-const char *regulator_get_supply(const char *regulator);
+/**
+ * struct regulator_init_data - regulator platform initialisation data.
+ *
+ * Initialisation constraints, our supply and consumers supplies.
+ */
+struct regulator_init_data {
+        struct device *supply_regulator_dev; /* or NULL for LINE */
 
-int regulator_set_machine_constraints(const char *regulator,
-        struct regulation_constraints *constraints);
+        struct regulation_constraints constraints;
 
-int regulator_set_device_supply(const char *regulator, struct device *dev,
-                                const char *supply);
+        int num_consumer_supplies;
+        struct regulator_consumer_supply *consumer_supplies;
+
+        /* optional regulator machine specific init */
+        int (*regulator_init)(void *driver_data);
+        void *driver_data;      /* core does not touch this */
+};
 
 int regulator_suspend_prepare(suspend_state_t state);
 
diff --git a/include/linux/reiserfs_fs.h b/include/linux/reiserfs_fs.h
index e9963af16cda..bc5114d35e99 100644
--- a/include/linux/reiserfs_fs.h
+++ b/include/linux/reiserfs_fs.h
@@ -87,7 +87,7 @@ void reiserfs_warning(struct super_block *s, const char *fmt, ...);
 if( !( cond ) )                                                                 \
   reiserfs_panic( NULL, "reiserfs[%i]: assertion " scond " failed at "  \
                   __FILE__ ":%i:%s: " format "\n",              \
-                  in_interrupt() ? -1 : task_pid_nr(current), __LINE__ , __FUNCTION__ , ##args )
+                  in_interrupt() ? -1 : task_pid_nr(current), __LINE__ , __func__ , ##args )
 
 #define RASSERT(cond, format, args...) __RASSERT(cond, #cond, format, ##args)
 
diff --git a/include/linux/res_counter.h b/include/linux/res_counter.h
index fdeadd9740dc..271c1c2c9f6f 100644
--- a/include/linux/res_counter.h
+++ b/include/linux/res_counter.h
@@ -166,7 +166,7 @@ static inline int res_counter_set_limit(struct res_counter *cnt,
         int ret = -EBUSY;
 
         spin_lock_irqsave(&cnt->lock, flags);
-        if (cnt->usage < limit) {
+        if (cnt->usage <= limit) {
                 cnt->limit = limit;
                 ret = 0;
         }
diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h
index 741d1a62cc3f..4cd64b0d9825 100644
--- a/include/linux/rfkill.h
+++ b/include/linux/rfkill.h
@@ -49,6 +49,7 @@ enum rfkill_state {
         RFKILL_STATE_SOFT_BLOCKED = 0,  /* Radio output blocked */
         RFKILL_STATE_UNBLOCKED    = 1,  /* Radio output allowed */
         RFKILL_STATE_HARD_BLOCKED = 2,  /* Output blocked, non-overrideable */
+        RFKILL_STATE_MAX,               /* marker for last valid state */
 };
 
 /*
@@ -110,12 +111,14 @@ struct rfkill {
 };
 #define to_rfkill(d)    container_of(d, struct rfkill, dev)
 
-struct rfkill *rfkill_allocate(struct device *parent, enum rfkill_type type);
+struct rfkill * __must_check rfkill_allocate(struct device *parent,
+                                             enum rfkill_type type);
 void rfkill_free(struct rfkill *rfkill);
-int rfkill_register(struct rfkill *rfkill);
+int __must_check rfkill_register(struct rfkill *rfkill);
 void rfkill_unregister(struct rfkill *rfkill);
 
 int rfkill_force_state(struct rfkill *rfkill, enum rfkill_state state);
+int rfkill_set_default(enum rfkill_type type, enum rfkill_state state);
 
 /**
  * rfkill_state_complement - return complementar state
diff --git a/include/linux/rtc/m48t59.h b/include/linux/rtc/m48t59.h
index e8c7c21ceb1f..6fc961459b4a 100644
--- a/include/linux/rtc/m48t59.h
+++ b/include/linux/rtc/m48t59.h
@@ -18,40 +18,47 @@
 /*
  * M48T59 Register Offset
  */
-#define M48T59_YEAR             0x1fff
-#define M48T59_MONTH            0x1ffe
-#define M48T59_MDAY             0x1ffd  /* Day of Month */
-#define M48T59_WDAY             0x1ffc  /* Day of Week */
+#define M48T59_YEAR             0xf
+#define M48T59_MONTH            0xe
+#define M48T59_MDAY             0xd     /* Day of Month */
+#define M48T59_WDAY             0xc     /* Day of Week */
 #define M48T59_WDAY_CB                  0x20    /* Century Bit */
 #define M48T59_WDAY_CEB                 0x10    /* Century Enable Bit */
-#define M48T59_HOUR             0x1ffb
-#define M48T59_MIN              0x1ffa
-#define M48T59_SEC              0x1ff9
-#define M48T59_CNTL             0x1ff8
+#define M48T59_HOUR             0xb
+#define M48T59_MIN              0xa
+#define M48T59_SEC              0x9
+#define M48T59_CNTL             0x8
 #define M48T59_CNTL_READ                0x40
 #define M48T59_CNTL_WRITE               0x80
-#define M48T59_WATCHDOG         0x1ff7
-#define M48T59_INTR             0x1ff6
+#define M48T59_WATCHDOG         0x7
+#define M48T59_INTR             0x6
 #define M48T59_INTR_AFE                 0x80    /* Alarm Interrupt Enable */
 #define M48T59_INTR_ABE                 0x20
-#define M48T59_ALARM_DATE       0x1ff5
-#define M48T59_ALARM_HOUR       0x1ff4
-#define M48T59_ALARM_MIN        0x1ff3
-#define M48T59_ALARM_SEC        0x1ff2
-#define M48T59_UNUSED           0x1ff1
-#define M48T59_FLAGS            0x1ff0
+#define M48T59_ALARM_DATE       0x5
+#define M48T59_ALARM_HOUR       0x4
+#define M48T59_ALARM_MIN        0x3
+#define M48T59_ALARM_SEC        0x2
+#define M48T59_UNUSED           0x1
+#define M48T59_FLAGS            0x0
 #define M48T59_FLAGS_WDT                0x80    /* watchdog timer expired */
 #define M48T59_FLAGS_AF                 0x40    /* alarm */
 #define M48T59_FLAGS_BF                 0x10    /* low battery */
 
-#define M48T59_NVRAM_SIZE       0x1ff0
+#define M48T59RTC_TYPE_M48T59   0 /* to keep compatibility */
+#define M48T59RTC_TYPE_M48T02   1
+#define M48T59RTC_TYPE_M48T08   2
 
 struct m48t59_plat_data {
-        /* The method to access M48T59 registers,
-         * NOTE: The 'ofs' should be 0x00~0x1fff
-         */
+        /* The method to access M48T59 registers */
         void (*write_byte)(struct device *dev, u32 ofs, u8 val);
         unsigned char (*read_byte)(struct device *dev, u32 ofs);
+
+        int type; /* RTC model */
+
+        /* ioaddr mapped externally */
+        void __iomem *ioaddr;
+        /* offset to RTC registers, automatically set according to the type */
+        unsigned int offset;
 };
 
 #endif /* _LINUX_RTC_M48T59_H_ */
diff --git a/include/linux/rtmutex.h b/include/linux/rtmutex.h
index 382bb7951166..f19b00b7d530 100644
--- a/include/linux/rtmutex.h
+++ b/include/linux/rtmutex.h
@@ -54,7 +54,7 @@ struct hrtimer_sleeper;
 #ifdef CONFIG_DEBUG_RT_MUTEXES
 # define __DEBUG_RT_MUTEX_INITIALIZER(mutexname) \
         , .name = #mutexname, .file = __FILE__, .line = __LINE__
-# define rt_mutex_init(mutex)                   __rt_mutex_init(mutex, __FUNCTION__)
+# define rt_mutex_init(mutex)                   __rt_mutex_init(mutex, __func__)
  extern void rt_mutex_debug_task_free(struct task_struct *tsk);
 #else
 # define __DEBUG_RT_MUTEX_INITIALIZER(mutexname)
diff --git a/include/linux/rtnetlink.h b/include/linux/rtnetlink.h
index ca643b13b026..2b3d51c6ec9c 100644
--- a/include/linux/rtnetlink.h
+++ b/include/linux/rtnetlink.h
@@ -582,6 +582,10 @@ enum rtnetlink_groups {
 #define RTNLGRP_IPV6_RULE       RTNLGRP_IPV6_RULE
         RTNLGRP_ND_USEROPT,
 #define RTNLGRP_ND_USEROPT      RTNLGRP_ND_USEROPT
+        RTNLGRP_PHONET_IFADDR,
+#define RTNLGRP_PHONET_IFADDR   RTNLGRP_PHONET_IFADDR
+        RTNLGRP_PHONET_ROUTE,
+#define RTNLGRP_PHONET_ROUTE    RTNLGRP_PHONET_ROUTE
         __RTNLGRP_MAX
 };
 #define RTNLGRP_MAX     (__RTNLGRP_MAX - 1)
diff --git a/include/linux/sched.h b/include/linux/sched.h
index cfb0d87b99fc..81c68fef4431 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -352,7 +352,7 @@ arch_get_unmapped_area_topdown(struct file *filp, unsigned long addr,
 extern void arch_unmap_area(struct mm_struct *, unsigned long);
 extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 
-#if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
+#if USE_SPLIT_PTLOCKS
 /*
  * The mm counters are not protected by its page_table_lock,
  * so must be incremented atomically.
@@ -363,7 +363,7 @@ extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 #define inc_mm_counter(mm, member) atomic_long_inc(&(mm)->_##member)
 #define dec_mm_counter(mm, member) atomic_long_dec(&(mm)->_##member)
 
-#else  /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#else  /* !USE_SPLIT_PTLOCKS */
 /*
  * The mm counters are protected by its page_table_lock,
  * so can be incremented directly.
@@ -374,7 +374,7 @@ extern void arch_unmap_area_topdown(struct mm_struct *, unsigned long);
 #define inc_mm_counter(mm, member) (mm)->_##member++
 #define dec_mm_counter(mm, member) (mm)->_##member--
 
-#endif /* NR_CPUS < CONFIG_SPLIT_PTLOCK_CPUS */
+#endif /* !USE_SPLIT_PTLOCKS */
 
 #define get_mm_rss(mm)                                  \
         (get_mm_counter(mm, file_rss) + get_mm_counter(mm, anon_rss))
@@ -425,6 +425,39 @@ struct pacct_struct {
         unsigned long           ac_minflt, ac_majflt;
 };
 
+/**
+ * struct task_cputime - collected CPU time counts
+ * @utime:              time spent in user mode, in &cputime_t units
+ * @stime:              time spent in kernel mode, in &cputime_t units
+ * @sum_exec_runtime:   total time spent on the CPU, in nanoseconds
+ *
+ * This structure groups together three kinds of CPU time that are
+ * tracked for threads and thread groups.  Most things considering
+ * CPU time want to group these counts together and treat all three
+ * of them in parallel.
+ */
+struct task_cputime {
+        cputime_t utime;
+        cputime_t stime;
+        unsigned long long sum_exec_runtime;
+};
+/* Alternate field names when used to cache expirations. */
+#define prof_exp        stime
+#define virt_exp        utime
+#define sched_exp       sum_exec_runtime
+
+/**
+ * struct thread_group_cputime - thread group interval timer counts
+ * @totals:             thread group interval timers; substructure for
+ *                      uniprocessor kernel, per-cpu for SMP kernel.
+ *
+ * This structure contains the version of task_cputime, above, that is
+ * used for thread group CPU clock calculations.
+ */
+struct thread_group_cputime {
+        struct task_cputime *totals;
+};
+
 /*
  * NOTE! "signal_struct" does not have it's own
  * locking, because a shared signal_struct always
@@ -451,8 +484,8 @@ struct signal_struct {
          * - everyone except group_exit_task is stopped during signal delivery
          *   of fatal signals, group_exit_task processes the signal.
          */
-        struct task_struct      *group_exit_task;
         int                     notify_count;
+        struct task_struct      *group_exit_task;
 
         /* thread group stop support, overloads group_exit_code too */
         int                     group_stop_count;
@@ -470,6 +503,17 @@ struct signal_struct {
         cputime_t it_prof_expires, it_virt_expires;
         cputime_t it_prof_incr, it_virt_incr;
 
+        /*
+         * Thread group totals for process CPU clocks.
+         * See thread_group_cputime(), et al, for details.
+         */
+        struct thread_group_cputime cputime;
+
+        /* Earliest-expiration cache. */
+        struct task_cputime cputime_expires;
+
+        struct list_head cpu_timers[3];
+
         /* job control IDs */
 
         /*
@@ -500,7 +544,7 @@ struct signal_struct {
          * Live threads maintain their own counters and add to these
          * in __exit_signal, except for the group leader.
          */
-        cputime_t utime, stime, cutime, cstime;
+        cputime_t cutime, cstime;
         cputime_t gtime;
         cputime_t cgtime;
         unsigned long nvcsw, nivcsw, cnvcsw, cnivcsw;
@@ -509,14 +553,6 @@ struct signal_struct {
         struct task_io_accounting ioac;
 
         /*
-         * Cumulative ns of scheduled CPU time for dead threads in the
-         * group, not including a zombie group leader.  (This only differs
-         * from jiffies_to_ns(utime + stime) if sched_clock uses something
-         * other than jiffies.)
-         */
-        unsigned long long sum_sched_runtime;
-
-        /*
          * We don't bother to synchronize most readers of this at all,
          * because there is no reader checking a limit that actually needs
          * to get both rlim_cur and rlim_max atomically, and either one
@@ -527,8 +563,6 @@ struct signal_struct {
          */
         struct rlimit rlim[RLIM_NLIMITS];
 
-        struct list_head cpu_timers[3];
-
         /* keep the process-shared keyrings here so that they do the right
          * thing in threads created with CLONE_THREAD */
 #ifdef CONFIG_KEYS
@@ -824,6 +858,9 @@ struct sched_domain {
         unsigned int ttwu_move_affine;
         unsigned int ttwu_move_balance;
 #endif
+#ifdef CONFIG_SCHED_DEBUG
+        char *name;
+#endif
 };
 
 extern void partition_sched_domains(int ndoms_new, cpumask_t *doms_new,
@@ -897,7 +934,7 @@ struct sched_class {
         void (*yield_task) (struct rq *rq);
         int  (*select_task_rq)(struct task_struct *p, int sync);
 
-        void (*check_preempt_curr) (struct rq *rq, struct task_struct *p);
+        void (*check_preempt_curr) (struct rq *rq, struct task_struct *p, int sync);
 
         struct task_struct * (*pick_next_task) (struct rq *rq);
         void (*put_prev_task) (struct rq *rq, struct task_struct *p);
@@ -1010,8 +1047,8 @@ struct sched_entity {
 
 struct sched_rt_entity {
         struct list_head run_list;
-        unsigned int time_slice;
         unsigned long timeout;
+        unsigned int time_slice;
         int nr_cpus_allowed;
 
         struct sched_rt_entity *back;
@@ -1134,8 +1171,7 @@ struct task_struct {
 /* mm fault and swap info: this can arguably be seen as either mm-specific or thread-specific */
         unsigned long min_flt, maj_flt;
 
-        cputime_t it_prof_expires, it_virt_expires;
-        unsigned long long it_sched_expires;
+        struct task_cputime cputime_expires;
         struct list_head cpu_timers[3];
 
 /* process credentials */
@@ -1475,6 +1511,10 @@ static inline void put_task_struct(struct task_struct *t)
                 __put_task_struct(t);
 }
 
+extern cputime_t task_utime(struct task_struct *p);
+extern cputime_t task_stime(struct task_struct *p);
+extern cputime_t task_gtime(struct task_struct *p);
+
 /*
  * Per process flags
  */
@@ -1581,6 +1621,7 @@ extern unsigned long long cpu_clock(int cpu);
 
 extern unsigned long long
 task_sched_runtime(struct task_struct *task);
+extern unsigned long long thread_group_sched_runtime(struct task_struct *task);
 
 /* sched_exec is called by processes performing an exec */
 #ifdef CONFIG_SMP
@@ -2078,6 +2119,30 @@ static inline int spin_needbreak(spinlock_t *lock)
 }
 
 /*
+ * Thread group CPU time accounting.
+ */
+
+extern int thread_group_cputime_alloc(struct task_struct *);
+extern void thread_group_cputime(struct task_struct *, struct task_cputime *);
+
+static inline void thread_group_cputime_init(struct signal_struct *sig)
+{
+        sig->cputime.totals = NULL;
+}
+
+static inline int thread_group_cputime_clone_thread(struct task_struct *curr)
+{
+        if (curr->signal->cputime.totals)
+                return 0;
+        return thread_group_cputime_alloc(curr);
+}
+
+static inline void thread_group_cputime_free(struct signal_struct *sig)
+{
+        free_percpu(sig->cputime.totals);
+}
+
+/*
  * Reevaluate whether the task has signals pending delivery.
  * Wake the task if so.
  * This is required every time the blocked sigset_t changes.
diff --git a/include/linux/security.h b/include/linux/security.h
index 80c4d002864c..f5c4a51eb42e 100644
--- a/include/linux/security.h
+++ b/include/linux/security.h
@@ -1560,11 +1560,6 @@ struct security_operations {
 extern int security_init(void);
 extern int security_module_enable(struct security_operations *ops);
 extern int register_security(struct security_operations *ops);
-extern struct dentry *securityfs_create_file(const char *name, mode_t mode,
-                                             struct dentry *parent, void *data,
-                                             const struct file_operations *fops);
-extern struct dentry *securityfs_create_dir(const char *name, struct dentry *parent);
-extern void securityfs_remove(struct dentry *dentry);
 
 /* Security operations */
 int security_ptrace_may_access(struct task_struct *child, unsigned int mode);
@@ -2424,25 +2419,6 @@ static inline int security_netlink_recv(struct sk_buff *skb, int cap)
         return cap_netlink_recv(skb, cap);
 }
 
-static inline struct dentry *securityfs_create_dir(const char *name,
-                                        struct dentry *parent)
-{
-        return ERR_PTR(-ENODEV);
-}
-
-static inline struct dentry *securityfs_create_file(const char *name,
-                                                mode_t mode,
-                                                struct dentry *parent,
-                                                void *data,
-                                                const struct file_operations *fops)
-{
-        return ERR_PTR(-ENODEV);
-}
-
-static inline void securityfs_remove(struct dentry *dentry)
-{
-}
-
 static inline int security_secid_to_secctx(u32 secid, char **secdata, u32 *seclen)
 {
         return -EOPNOTSUPP;
@@ -2806,5 +2782,35 @@ static inline void security_audit_rule_free(void *lsmrule)
 #endif /* CONFIG_SECURITY */
 #endif /* CONFIG_AUDIT */
 
+#ifdef CONFIG_SECURITYFS
+
+extern struct dentry *securityfs_create_file(const char *name, mode_t mode,
+                                             struct dentry *parent, void *data,
+                                             const struct file_operations *fops);
+extern struct dentry *securityfs_create_dir(const char *name, struct dentry *parent);
+extern void securityfs_remove(struct dentry *dentry);
+
+#else /* CONFIG_SECURITYFS */
+
+static inline struct dentry *securityfs_create_dir(const char *name,
+                                                   struct dentry *parent)
+{
+        return ERR_PTR(-ENODEV);
+}
+
+static inline struct dentry *securityfs_create_file(const char *name,
+                                                    mode_t mode,
+                                                    struct dentry *parent,
+                                                    void *data,
+                                                    const struct file_operations *fops)
+{
+        return ERR_PTR(-ENODEV);
+}
+
+static inline void securityfs_remove(struct dentry *dentry)
+{}
+
+#endif
+
 #endif /* ! __LINUX_SECURITY_H */
 
diff --git a/include/linux/serial.h b/include/linux/serial.h
index deb714314fb1..1ea8d9265bf6 100644
--- a/include/linux/serial.h
+++ b/include/linux/serial.h
@@ -173,6 +173,22 @@ struct serial_icounter_struct {
         int reserved[9];
 };
 
+/*
+ * Serial interface for controlling RS485 settings on chips with suitable
+ * support. Set with TIOCSRS485 and get with TIOCGRS485 if supported by your
+ * platform. The set function returns the new state, with any unsupported bits
+ * reverted appropriately.
+ */
+
+struct serial_rs485 {
+        __u32   flags;                  /* RS485 feature flags */
+#define SER_RS485_ENABLED               (1 << 0)
+#define SER_RS485_RTS_ON_SEND           (1 << 1)
+#define SER_RS485_RTS_AFTER_SEND        (1 << 2)
+        __u32   delay_rts_before_send;  /* Milliseconds */
+        __u32   padding[6];             /* Memory is cheap, new structs
+                                           are a royal PITA .. */
+};
 
 #ifdef __KERNEL__
 #include <linux/compiler.h>
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 3b2f6c04855e..e27f216361fc 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -241,7 +241,7 @@ typedef unsigned int __bitwise__ upf_t;
 
 struct uart_port {
         spinlock_t              lock;                   /* port lock */
-        unsigned int            iobase;                 /* in/out[bwl] */
+        unsigned long           iobase;                 /* in/out[bwl] */
         unsigned char __iomem   *membase;               /* read/write[bwl] */
         unsigned int            irq;                    /* irq number */
         unsigned int            uartclk;                /* base uart clock */
diff --git a/include/linux/skbuff.h b/include/linux/skbuff.h
index 909923717830..2725f4e5a9bf 100644
--- a/include/linux/skbuff.h
+++ b/include/linux/skbuff.h
@@ -146,8 +146,14 @@ struct skb_shared_info {
         unsigned short  gso_segs;
         unsigned short  gso_type;
         __be32          ip6_frag_id;
+#ifdef CONFIG_HAS_DMA
+        unsigned int    num_dma_maps;
+#endif
         struct sk_buff  *frag_list;
         skb_frag_t      frags[MAX_SKB_FRAGS];
+#ifdef CONFIG_HAS_DMA
+        dma_addr_t      dma_maps[MAX_SKB_FRAGS + 1];
+#endif
 };
 
 /* We divide dataref into two halves.  The higher 16 bits hold references
@@ -353,6 +359,14 @@ struct sk_buff {
 
 #include <asm/system.h>
 
+#ifdef CONFIG_HAS_DMA
+#include <linux/dma-mapping.h>
+extern int skb_dma_map(struct device *dev, struct sk_buff *skb,
+                       enum dma_data_direction dir);
+extern void skb_dma_unmap(struct device *dev, struct sk_buff *skb,
+                          enum dma_data_direction dir);
+#endif
+
 extern void kfree_skb(struct sk_buff *skb);
 extern void            __kfree_skb(struct sk_buff *skb);
 extern struct sk_buff *__alloc_skb(unsigned int size,
@@ -369,6 +383,8 @@ static inline struct sk_buff *alloc_skb_fclone(unsigned int size,
         return __alloc_skb(size, priority, 1, -1);
 }
 
+extern int skb_recycle_check(struct sk_buff *skb, int skb_size);
+
 extern struct sk_buff *skb_morph(struct sk_buff *dst, struct sk_buff *src);
 extern struct sk_buff *skb_clone(struct sk_buff *skb,
                                  gfp_t priority);
@@ -459,6 +475,37 @@ static inline int skb_queue_empty(const struct sk_buff_head *list)
 }
 
 /**
+ *      skb_queue_is_last - check if skb is the last entry in the queue
+ *      @list: queue head
+ *      @skb: buffer
+ *
+ *      Returns true if @skb is the last buffer on the list.
+ */
+static inline bool skb_queue_is_last(const struct sk_buff_head *list,
+                                     const struct sk_buff *skb)
+{
+        return (skb->next == (struct sk_buff *) list);
+}
+
+/**
+ *      skb_queue_next - return the next packet in the queue
+ *      @list: queue head
+ *      @skb: current buffer
+ *
+ *      Return the next packet in @list after @skb.  It is only valid to
+ *      call this if skb_queue_is_last() evaluates to false.
+ */
+static inline struct sk_buff *skb_queue_next(const struct sk_buff_head *list,
+                                             const struct sk_buff *skb)
+{
+        /* This BUG_ON may seem severe, but if we just return then we
+         * are going to dereference garbage.
+         */
+        BUG_ON(skb_queue_is_last(list, skb));
+        return skb->next;
+}
+
+/**
  *      skb_get - reference buffer
  *      @skb: buffer to reference
  *
@@ -646,6 +693,22 @@ static inline __u32 skb_queue_len(const struct sk_buff_head *list_)
         return list_->qlen;
 }
 
+/**
+ *      __skb_queue_head_init - initialize non-spinlock portions of sk_buff_head
+ *      @list: queue to initialize
+ *
+ *      This initializes only the list and queue length aspects of
+ *      an sk_buff_head object.  This allows to initialize the list
+ *      aspects of an sk_buff_head without reinitializing things like
+ *      the spinlock.  It can also be used for on-stack sk_buff_head
+ *      objects where the spinlock is known to not be used.
+ */
+static inline void __skb_queue_head_init(struct sk_buff_head *list)
+{
+        list->prev = list->next = (struct sk_buff *)list;
+        list->qlen = 0;
+}
+
 /*
  * This function creates a split out lock class for each invocation;
  * this is needed for now since a whole lot of users of the skb-queue
@@ -657,8 +720,7 @@ static inline __u32 skb_queue_len(const struct sk_buff_head *list_)
 static inline void skb_queue_head_init(struct sk_buff_head *list)
 {
         spin_lock_init(&list->lock);
-        list->prev = list->next = (struct sk_buff *)list;
-        list->qlen = 0;
+        __skb_queue_head_init(list);
 }
 
 static inline void skb_queue_head_init_class(struct sk_buff_head *list,
@@ -685,6 +747,83 @@ static inline void __skb_insert(struct sk_buff *newsk,
         list->qlen++;
 }
 
+static inline void __skb_queue_splice(const struct sk_buff_head *list,
+                                      struct sk_buff *prev,
+                                      struct sk_buff *next)
+{
+        struct sk_buff *first = list->next;
+        struct sk_buff *last = list->prev;
+
+        first->prev = prev;
+        prev->next = first;
+
+        last->next = next;
+        next->prev = last;
+}
+
+/**
+ *      skb_queue_splice - join two skb lists, this is designed for stacks
+ *      @list: the new list to add
+ *      @head: the place to add it in the first list
+ */
+static inline void skb_queue_splice(const struct sk_buff_head *list,
+                                    struct sk_buff_head *head)
+{
+        if (!skb_queue_empty(list)) {
+                __skb_queue_splice(list, (struct sk_buff *) head, head->next);
+                head->qlen += list->qlen;
+        }
+}
+
+/**
+ *      skb_queue_splice - join two skb lists and reinitialise the emptied list
+ *      @list: the new list to add
+ *      @head: the place to add it in the first list
+ *
+ *      The list at @list is reinitialised
+ */
+static inline void skb_queue_splice_init(struct sk_buff_head *list,
+                                         struct sk_buff_head *head)
+{
+        if (!skb_queue_empty(list)) {
+                __skb_queue_splice(list, (struct sk_buff *) head, head->next);
+                head->qlen += list->qlen;
+                __skb_queue_head_init(list);
+        }
+}
+
+/**
+ *      skb_queue_splice_tail - join two skb lists, each list being a queue
+ *      @list: the new list to add
+ *      @head: the place to add it in the first list
+ */
+static inline void skb_queue_splice_tail(const struct sk_buff_head *list,
+                                         struct sk_buff_head *head)
+{
+        if (!skb_queue_empty(list)) {
+                __skb_queue_splice(list, head->prev, (struct sk_buff *) head);
+                head->qlen += list->qlen;
+        }
+}
+
+/**
+ *      skb_queue_splice_tail - join two skb lists and reinitialise the emptied list
+ *      @list: the new list to add
+ *      @head: the place to add it in the first list
+ *
+ *      Each of the lists is a queue.
+ *      The list at @list is reinitialised
+ */
+static inline void skb_queue_splice_tail_init(struct sk_buff_head *list,
+                                              struct sk_buff_head *head)
+{
+        if (!skb_queue_empty(list)) {
+                __skb_queue_splice(list, head->prev, (struct sk_buff *) head);
+                head->qlen += list->qlen;
+                __skb_queue_head_init(list);
+        }
+}
+
 /**
  *      __skb_queue_after - queue a buffer at the list head
  *      @list: list to use
@@ -829,6 +968,9 @@ static inline void skb_fill_page_desc(struct sk_buff *skb, int i,
         skb_shinfo(skb)->nr_frags = i + 1;
 }
 
+extern void skb_add_rx_frag(struct sk_buff *skb, int i, struct page *page,
+                            int off, int size);
+
 #define SKB_PAGE_ASSERT(skb)    BUG_ON(skb_shinfo(skb)->nr_frags)
 #define SKB_FRAG_ASSERT(skb)    BUG_ON(skb_shinfo(skb)->frag_list)
 #define SKB_LINEAR_ASSERT(skb)  BUG_ON(skb_is_nonlinear(skb))
@@ -1243,6 +1385,26 @@ static inline struct sk_buff *netdev_alloc_skb(struct net_device *dev,
         return __netdev_alloc_skb(dev, length, GFP_ATOMIC);
 }
 
+extern struct page *__netdev_alloc_page(struct net_device *dev, gfp_t gfp_mask);
+
+/**
+ *      netdev_alloc_page - allocate a page for ps-rx on a specific device
+ *      @dev: network device to receive on
+ *
+ *      Allocate a new page node local to the specified device.
+ *
+ *      %NULL is returned if there is no free memory.
+ */
+static inline struct page *netdev_alloc_page(struct net_device *dev)
+{
+        return __netdev_alloc_page(dev, GFP_ATOMIC);
+}
+
+static inline void netdev_free_page(struct net_device *dev, struct page *page)
+{
+        __free_page(page);
+}
+
 /**
  *      skb_clone_writable - is the header of a clone writable
  *      @skb: buffer to check
@@ -1434,6 +1596,15 @@ static inline int pskb_trim_rcsum(struct sk_buff *skb, unsigned int len)
                      skb != (struct sk_buff *)(queue);                          \
                      skb = tmp, tmp = skb->next)
 
+#define skb_queue_walk_from(queue, skb)                                         \
+                for (; prefetch(skb->next), (skb != (struct sk_buff *)(queue)); \
+                     skb = skb->next)
+
+#define skb_queue_walk_from_safe(queue, skb, tmp)                               \
+                for (tmp = skb->next;                                           \
+                     skb != (struct sk_buff *)(queue);                          \
+                     skb = tmp, tmp = skb->next)
+
 #define skb_queue_reverse_walk(queue, skb) \
                 for (skb = (queue)->prev;                                       \
                      prefetch(skb->prev), (skb != (struct sk_buff *)(queue));   \
diff --git a/include/linux/smb.h b/include/linux/smb.h
index caa43b2370cb..82fefddc5987 100644
--- a/include/linux/smb.h
+++ b/include/linux/smb.h
@@ -11,7 +11,9 @@
 
 #include <linux/types.h>
 #include <linux/magic.h>
+#ifdef __KERNEL__
 #include <linux/time.h>
+#endif
 
 enum smb_protocol { 
         SMB_PROTOCOL_NONE, 
diff --git a/include/linux/smc91x.h b/include/linux/smc91x.h
index 3827b922ba1f..bc21db598c06 100644
--- a/include/linux/smc91x.h
+++ b/include/linux/smc91x.h
@@ -16,8 +16,19 @@
 
 #define SMC91X_USE_DMA          (1 << 6)
 
+#define RPC_LED_100_10  (0x00)  /* LED = 100Mbps OR's with 10Mbps link detect */
+#define RPC_LED_RES     (0x01)  /* LED = Reserved */
+#define RPC_LED_10      (0x02)  /* LED = 10Mbps link detect */
+#define RPC_LED_FD      (0x03)  /* LED = Full Duplex Mode */
+#define RPC_LED_TX_RX   (0x04)  /* LED = TX or RX packet occurred */
+#define RPC_LED_100     (0x05)  /* LED = 100Mbps link dectect */
+#define RPC_LED_TX      (0x06)  /* LED = TX packet occurred */
+#define RPC_LED_RX      (0x07)  /* LED = RX packet occurred */
+
 struct smc91x_platdata {
         unsigned long flags;
+        unsigned char leda;
+        unsigned char ledb;
 };
 
 #endif /* __SMC91X_H__ */
diff --git a/include/linux/smp.h b/include/linux/smp.h
index 66484d4a8459..2e4d58b26c06 100644
--- a/include/linux/smp.h
+++ b/include/linux/smp.h
@@ -7,6 +7,7 @@
  */
 
 #include <linux/errno.h>
+#include <linux/types.h>
 #include <linux/list.h>
 #include <linux/cpumask.h>
 
@@ -16,7 +17,8 @@ struct call_single_data {
         struct list_head list;
         void (*func) (void *info);
         void *info;
-        unsigned int flags;
+        u16 flags;
+        u16 priv;
 };
 
 #ifdef CONFIG_SMP
diff --git a/include/linux/socket.h b/include/linux/socket.h
index dc5086fe7736..20fc4bbfca42 100644
--- a/include/linux/socket.h
+++ b/include/linux/socket.h
@@ -190,7 +190,8 @@ struct ucred {
 #define AF_IUCV         32      /* IUCV sockets                 */
 #define AF_RXRPC        33      /* RxRPC sockets                */
 #define AF_ISDN         34      /* mISDN sockets                */
-#define AF_MAX          35      /* For now.. */
+#define AF_PHONET       35      /* Phonet sockets               */
+#define AF_MAX          36      /* For now.. */
 
 /* Protocol families, same as address families. */
 #define PF_UNSPEC       AF_UNSPEC
@@ -227,6 +228,7 @@ struct ucred {
 #define PF_IUCV         AF_IUCV
 #define PF_RXRPC        AF_RXRPC
 #define PF_ISDN         AF_ISDN
+#define PF_PHONET       AF_PHONET
 #define PF_MAX          AF_MAX
 
 /* Maximum queue length specifiable by listen.  */
@@ -295,6 +297,7 @@ struct ucred {
 #define SOL_RXRPC       272
 #define SOL_PPPOL2TP    273
 #define SOL_BLUETOOTH   274
+#define SOL_PNPIPE      275
 
 /* IPX options */
 #define IPX_TYPE        1
diff --git a/include/linux/spi/ads7846.h b/include/linux/spi/ads7846.h
index daf744017a31..05eab2f11e63 100644
--- a/include/linux/spi/ads7846.h
+++ b/include/linux/spi/ads7846.h
@@ -43,6 +43,9 @@ struct ads7846_platform_data {
         u16     debounce_tol;           /* tolerance used for filtering */
         u16     debounce_rep;           /* additional consecutive good readings
                                          * required after the first two */
+        int     gpio_pendown;           /* the GPIO used to decide the pendown
+                                         * state if get_pendown_state == NULL
+                                         */
         int     (*get_pendown_state)(void);
         int     (*filter_init)  (struct ads7846_platform_data *pdata,
                                  void **filter_data);
diff --git a/include/linux/spi/corgi_lcd.h b/include/linux/spi/corgi_lcd.h
new file mode 100644
index 000000000000..6692b3418ccf
--- /dev/null
+++ b/include/linux/spi/corgi_lcd.h
@@ -0,0 +1,20 @@
+#ifndef __LINUX_SPI_CORGI_LCD_H
+#define __LINUX_SPI_CORGI_LCD_H
+
+#define CORGI_LCD_MODE_QVGA     1
+#define CORGI_LCD_MODE_VGA      2
+
+struct corgi_lcd_platform_data {
+        int     init_mode;
+        int     max_intensity;
+        int     default_intensity;
+        int     limit_mask;
+
+        int     gpio_backlight_on;      /* -1 if n/a */
+        int     gpio_backlight_cont;    /* -1 if n/a */
+
+        void (*notify)(int intensity);
+        void (*kick_battery)(void);
+};
+
+#endif /* __LINUX_SPI_CORGI_LCD_H */
diff --git a/include/linux/spi/orion_spi.h b/include/linux/spi/orion_spi.h
index b4d9fa6f797c..decf6d8c77b7 100644
--- a/include/linux/spi/orion_spi.h
+++ b/include/linux/spi/orion_spi.h
@@ -11,6 +11,7 @@
 
 struct orion_spi_info {
         u32     tclk;           /* no <linux/clk.h> support yet */
+        u32     enable_clock_fix;
 };
 
 
diff --git a/include/linux/ssb/ssb_regs.h b/include/linux/ssb/ssb_regs.h
index ebad0bac9801..99a0f991e850 100644
--- a/include/linux/ssb/ssb_regs.h
+++ b/include/linux/ssb/ssb_regs.h
@@ -245,8 +245,6 @@
 
 /* SPROM Revision 3 (inherits most data from rev 2) */
 #define SSB_SPROM3_IL0MAC               0x104A  /* 6 bytes MAC address for 802.11b/g */
-#define SSB_SPROM3_ET0MAC               0x1050  /* 6 bytes MAC address for Ethernet ?? */
-#define SSB_SPROM3_ET1MAC               0x1050  /* 6 bytes MAC address for 802.11a ?? */
 #define SSB_SPROM3_OFDMAPO              0x102C  /* A-PHY OFDM Mid Power Offset (4 bytes, BigEndian) */
 #define SSB_SPROM3_OFDMALPO             0x1030  /* A-PHY OFDM Low Power Offset (4 bytes, BigEndian) */
 #define SSB_SPROM3_OFDMAHPO             0x1034  /* A-PHY OFDM High Power Offset (4 bytes, BigEndian) */
@@ -267,8 +265,6 @@
 
 /* SPROM Revision 4 */
 #define SSB_SPROM4_IL0MAC               0x104C  /* 6 byte MAC address for a/b/g/n */
-#define SSB_SPROM4_ET0MAC               0x1018  /* 6 bytes MAC address for Ethernet ?? */
-#define SSB_SPROM4_ET1MAC               0x1018  /* 6 bytes MAC address for 802.11a ?? */
 #define SSB_SPROM4_ETHPHY               0x105A  /* Ethernet PHY settings ?? */
 #define  SSB_SPROM4_ETHPHY_ET0A         0x001F  /* MII Address for enet0 */
 #define  SSB_SPROM4_ETHPHY_ET1A         0x03E0  /* MII Address for enet1 */
@@ -316,6 +312,21 @@
 #define SSB_SPROM4_PA1B1                0x1090
 #define SSB_SPROM4_PA1B2                0x1092
 
+/* SPROM Revision 5 (inherits most data from rev 4) */
+#define SSB_SPROM5_BFLLO                0x104A  /* Boardflags (low 16 bits) */
+#define SSB_SPROM5_BFLHI                0x104C  /* Board Flags Hi */
+#define SSB_SPROM5_IL0MAC               0x1052  /* 6 byte MAC address for a/b/g/n */
+#define SSB_SPROM5_CCODE                0x1044  /* Country Code (2 bytes) */
+#define SSB_SPROM5_GPIOA                0x1076  /* Gen. Purpose IO # 0 and 1 */
+#define  SSB_SPROM5_GPIOA_P0            0x00FF  /* Pin 0 */
+#define  SSB_SPROM5_GPIOA_P1            0xFF00  /* Pin 1 */
+#define  SSB_SPROM5_GPIOA_P1_SHIFT      8
+#define SSB_SPROM5_GPIOB                0x1078  /* Gen. Purpose IO # 2 and 3 */
+#define  SSB_SPROM5_GPIOB_P2            0x00FF  /* Pin 2 */
+#define  SSB_SPROM5_GPIOB_P3            0xFF00  /* Pin 3 */
+#define  SSB_SPROM5_GPIOB_P3_SHIFT      8
+
+
 /* Values for SSB_SPROM1_BINF_CCODE */
 enum {
         SSB_SPROM1CCODE_WORLD = 0,
diff --git a/include/linux/stacktrace.h b/include/linux/stacktrace.h
index 5da9794b2d78..b106fd8e0d5c 100644
--- a/include/linux/stacktrace.h
+++ b/include/linux/stacktrace.h
@@ -1,6 +1,8 @@
 #ifndef __LINUX_STACKTRACE_H
 #define __LINUX_STACKTRACE_H
 
+struct task_struct;
+
 #ifdef CONFIG_STACKTRACE
 struct stack_trace {
         unsigned int nr_entries, max_entries;
diff --git a/include/linux/stop_machine.h b/include/linux/stop_machine.h
index f1cb0ba6d715..faf1519b5adc 100644
--- a/include/linux/stop_machine.h
+++ b/include/linux/stop_machine.h
@@ -3,16 +3,13 @@
 /* "Bogolock": stop the entire machine, disable interrupts.  This is a
    very heavy lock, which is equivalent to grabbing every spinlock
    (and more).  So the "read" side to such a lock is anything which
-   diables preeempt. */
+   disables preeempt. */
 #include <linux/cpu.h>
 #include <linux/cpumask.h>
 #include <asm/system.h>
 
 #if defined(CONFIG_STOP_MACHINE) && defined(CONFIG_SMP)
 
-/* Deprecated, but useful for transition. */
-#define ALL_CPUS ~0U
-
 /**
  * stop_machine: freeze the machine on all CPUs and run this function
  * @fn: the function to run
@@ -50,18 +47,4 @@ static inline int stop_machine(int (*fn)(void *), void *data,
         return ret;
 }
 #endif /* CONFIG_SMP */
-
-static inline int __deprecated stop_machine_run(int (*fn)(void *), void *data,
-                                                unsigned int cpu)
-{
-        /* If they don't care which cpu fn runs on, just pick one. */
-        if (cpu == NR_CPUS)
-                return stop_machine(fn, data, NULL);
-        else if (cpu == ~0U)
-                return stop_machine(fn, data, &cpu_possible_map);
-        else {
-                cpumask_t cpus = cpumask_of_cpu(cpu);
-                return stop_machine(fn, data, &cpus);
-        }
-}
 #endif /* _LINUX_STOP_MACHINE */
diff --git a/include/linux/string_helpers.h b/include/linux/string_helpers.h
new file mode 100644
index 000000000000..a3eb2f65b656
--- /dev/null
+++ b/include/linux/string_helpers.h
@@ -0,0 +1,16 @@
+#ifndef _LINUX_STRING_HELPERS_H_
+#define _LINUX_STRING_HELPERS_H_
+
+#include <linux/types.h>
+
+/* Descriptions of the types of units to
+ * print in */
+enum string_size_units {
+        STRING_UNITS_10,        /* use powers of 10^3 (standard SI) */
+        STRING_UNITS_2,         /* use binary powers of 2^10 */
+};
+
+int string_get_size(u64 size, enum string_size_units units,
+                    char *buf, int len);
+
+#endif
diff --git a/include/linux/sunrpc/clnt.h b/include/linux/sunrpc/clnt.h
index e5bfe01ee305..6f0ee1b84a4f 100644
--- a/include/linux/sunrpc/clnt.h
+++ b/include/linux/sunrpc/clnt.h
@@ -104,6 +104,7 @@ struct rpc_create_args {
         const struct rpc_timeout *timeout;
         char                    *servername;
         struct rpc_program      *program;
+        u32                     prognumber;     /* overrides program->number */
         u32                     version;
         rpc_authflavor_t        authflavor;
         unsigned long           flags;
@@ -124,10 +125,10 @@ struct rpc_clnt *rpc_clone_client(struct rpc_clnt *);
 void            rpc_shutdown_client(struct rpc_clnt *);
 void            rpc_release_client(struct rpc_clnt *);
 
-int             rpcb_register(u32, u32, int, unsigned short, int *);
+int             rpcb_register(u32, u32, int, unsigned short);
 int             rpcb_v4_register(const u32 program, const u32 version,
                                  const struct sockaddr *address,
-                                 const char *netid, int *result);
+                                 const char *netid);
 int             rpcb_getport_sync(struct sockaddr_in *, u32, u32, int);
 void            rpcb_getport_async(struct rpc_task *);
 
diff --git a/include/linux/sunrpc/svc.h b/include/linux/sunrpc/svc.h
index dc69068d94c7..3afe7fb403b2 100644
--- a/include/linux/sunrpc/svc.h
+++ b/include/linux/sunrpc/svc.h
@@ -66,6 +66,7 @@ struct svc_serv {
         struct list_head        sv_tempsocks;   /* all temporary sockets */
         int                     sv_tmpcnt;      /* count of temporary sockets */
         struct timer_list       sv_temptimer;   /* timer for aging temporary sockets */
+        sa_family_t             sv_family;      /* listener's address family */
 
         char *                  sv_name;        /* service name */
 
@@ -265,17 +266,17 @@ struct svc_rqst {
 /*
  * Rigorous type checking on sockaddr type conversions
  */
-static inline struct sockaddr_in *svc_addr_in(struct svc_rqst *rqst)
+static inline struct sockaddr_in *svc_addr_in(const struct svc_rqst *rqst)
 {
         return (struct sockaddr_in *) &rqst->rq_addr;
 }
 
-static inline struct sockaddr_in6 *svc_addr_in6(struct svc_rqst *rqst)
+static inline struct sockaddr_in6 *svc_addr_in6(const struct svc_rqst *rqst)
 {
         return (struct sockaddr_in6 *) &rqst->rq_addr;
 }
 
-static inline struct sockaddr *svc_addr(struct svc_rqst *rqst)
+static inline struct sockaddr *svc_addr(const struct svc_rqst *rqst)
 {
         return (struct sockaddr *) &rqst->rq_addr;
 }
@@ -381,18 +382,20 @@ struct svc_procedure {
 /*
  * Function prototypes.
  */
-struct svc_serv *  svc_create(struct svc_program *, unsigned int,
-                              void (*shutdown)(struct svc_serv*));
+struct svc_serv *svc_create(struct svc_program *, unsigned int, sa_family_t,
+                            void (*shutdown)(struct svc_serv *));
 struct svc_rqst *svc_prepare_thread(struct svc_serv *serv,
                                         struct svc_pool *pool);
 void               svc_exit_thread(struct svc_rqst *);
 struct svc_serv *  svc_create_pooled(struct svc_program *, unsigned int,
-                        void (*shutdown)(struct svc_serv*), svc_thread_fn,
-                        struct module *);
+                        sa_family_t, void (*shutdown)(struct svc_serv *),
+                        svc_thread_fn, struct module *);
 int                svc_set_num_threads(struct svc_serv *, struct svc_pool *, int);
 void               svc_destroy(struct svc_serv *);
 int                svc_process(struct svc_rqst *);
-int                svc_register(struct svc_serv *, int, unsigned short);
+int                svc_register(const struct svc_serv *, const unsigned short,
+                                const unsigned short);
+
 void               svc_wake_up(struct svc_serv *);
 void               svc_reserve(struct svc_rqst *rqstp, int space);
 struct svc_pool *  svc_pool_for_cpu(struct svc_serv *serv, int cpu);
diff --git a/include/linux/sunrpc/svc_rdma.h b/include/linux/sunrpc/svc_rdma.h
index ef2e3a20bf3b..c14fe86dac59 100644
--- a/include/linux/sunrpc/svc_rdma.h
+++ b/include/linux/sunrpc/svc_rdma.h
@@ -72,6 +72,7 @@ extern atomic_t rdma_stat_sq_prod;
  */
 struct svc_rdma_op_ctxt {
         struct svc_rdma_op_ctxt *read_hdr;
+        struct svc_rdma_fastreg_mr *frmr;
         int hdr_count;
         struct xdr_buf arg;
         struct list_head dto_q;
@@ -103,16 +104,30 @@ struct svc_rdma_chunk_sge {
         int start;              /* sge no for this chunk */
         int count;              /* sge count for this chunk */
 };
+struct svc_rdma_fastreg_mr {
+        struct ib_mr *mr;
+        void *kva;
+        struct ib_fast_reg_page_list *page_list;
+        int page_list_len;
+        unsigned long access_flags;
+        unsigned long map_len;
+        enum dma_data_direction direction;
+        struct list_head frmr_list;
+};
 struct svc_rdma_req_map {
+        struct svc_rdma_fastreg_mr *frmr;
         unsigned long count;
         union {
                 struct kvec sge[RPCSVC_MAXPAGES];
                 struct svc_rdma_chunk_sge ch[RPCSVC_MAXPAGES];
         };
 };
-
+#define RDMACTXT_F_FAST_UNREG   1
 #define RDMACTXT_F_LAST_CTXT    2
 
+#define SVCRDMA_DEVCAP_FAST_REG         1       /* fast mr registration */
+#define SVCRDMA_DEVCAP_READ_W_INV       2       /* read w/ invalidate */
+
 struct svcxprt_rdma {
         struct svc_xprt      sc_xprt;           /* SVC transport structure */
         struct rdma_cm_id    *sc_cm_id;         /* RDMA connection id */
@@ -136,6 +151,11 @@ struct svcxprt_rdma {
         struct ib_cq         *sc_rq_cq;
         struct ib_cq         *sc_sq_cq;
         struct ib_mr         *sc_phys_mr;       /* MR for server memory */
+        u32                  sc_dev_caps;       /* distilled device caps */
+        u32                  sc_dma_lkey;       /* local dma key */
+        unsigned int         sc_frmr_pg_list_len;
+        struct list_head     sc_frmr_q;
+        spinlock_t           sc_frmr_q_lock;
 
         spinlock_t           sc_lock;           /* transport lock */
 
@@ -143,7 +163,6 @@ struct svcxprt_rdma {
         unsigned long        sc_flags;
         struct list_head     sc_dto_q;          /* DTO tasklet I/O pending Q */
         struct list_head     sc_read_complete_q;
-        spinlock_t           sc_read_complete_lock;
         struct work_struct   sc_work;
 };
 /* sc_flags */
@@ -193,8 +212,13 @@ extern int svc_rdma_post_recv(struct svcxprt_rdma *);
 extern int svc_rdma_create_listen(struct svc_serv *, int, struct sockaddr *);
 extern struct svc_rdma_op_ctxt *svc_rdma_get_context(struct svcxprt_rdma *);
 extern void svc_rdma_put_context(struct svc_rdma_op_ctxt *, int);
+extern void svc_rdma_unmap_dma(struct svc_rdma_op_ctxt *ctxt);
 extern struct svc_rdma_req_map *svc_rdma_get_req_map(void);
 extern void svc_rdma_put_req_map(struct svc_rdma_req_map *);
+extern int svc_rdma_fastreg(struct svcxprt_rdma *, struct svc_rdma_fastreg_mr *);
+extern struct svc_rdma_fastreg_mr *svc_rdma_get_frmr(struct svcxprt_rdma *);
+extern void svc_rdma_put_frmr(struct svcxprt_rdma *,
+                              struct svc_rdma_fastreg_mr *);
 extern void svc_sq_reap(struct svcxprt_rdma *);
 extern void svc_rq_reap(struct svcxprt_rdma *);
 extern struct svc_xprt_class svc_rdma_class;
diff --git a/include/linux/sunrpc/svcsock.h b/include/linux/sunrpc/svcsock.h
index 8cff696dedf5..483e10380aae 100644
--- a/include/linux/sunrpc/svcsock.h
+++ b/include/linux/sunrpc/svcsock.h
@@ -39,10 +39,7 @@ int		svc_send(struct svc_rqst *);
 void            svc_drop(struct svc_rqst *);
 void            svc_sock_update_bufs(struct svc_serv *serv);
 int             svc_sock_names(char *buf, struct svc_serv *serv, char *toclose);
-int             svc_addsock(struct svc_serv *serv,
-                            int fd,
-                            char *name_return,
-                            int *proto);
+int             svc_addsock(struct svc_serv *serv, int fd, char *name_return);
 void            svc_init_xprt_sock(void);
 void            svc_cleanup_xprt_sock(void);
 
diff --git a/include/linux/sunrpc/xprtrdma.h b/include/linux/sunrpc/xprtrdma.h
index 4de56b1d372b..54a379c9e8eb 100644
--- a/include/linux/sunrpc/xprtrdma.h
+++ b/include/linux/sunrpc/xprtrdma.h
@@ -66,9 +66,6 @@
 
 #define RPCRDMA_INLINE_PAD_THRESH  (512)/* payload threshold to pad (bytes) */
 
-#define RDMA_RESOLVE_TIMEOUT    (5*HZ)  /* TBD 5 seconds */
-#define RDMA_CONNECT_RETRY_MAX  (2)     /* retries if no listener backlog */
-
 /* memory registration strategies */
 #define RPCRDMA_PERSISTENT_REGISTRATION (1)
 
@@ -78,6 +75,7 @@ enum rpcrdma_memreg {
         RPCRDMA_MEMWINDOWS,
         RPCRDMA_MEMWINDOWS_ASYNC,
         RPCRDMA_MTHCAFMR,
+        RPCRDMA_FRMR,
         RPCRDMA_ALLPHYSICAL,
         RPCRDMA_LAST
 };
diff --git a/include/linux/swiotlb.h b/include/linux/swiotlb.h
new file mode 100644
index 000000000000..b18ec5533e8c
--- /dev/null
+++ b/include/linux/swiotlb.h
@@ -0,0 +1,83 @@
+#ifndef __LINUX_SWIOTLB_H
+#define __LINUX_SWIOTLB_H
+
+#include <linux/types.h>
+
+struct device;
+struct dma_attrs;
+struct scatterlist;
+
+extern void
+swiotlb_init(void);
+
+extern void
+*swiotlb_alloc_coherent(struct device *hwdev, size_t size,
+                        dma_addr_t *dma_handle, gfp_t flags);
+
+extern void
+swiotlb_free_coherent(struct device *hwdev, size_t size,
+                      void *vaddr, dma_addr_t dma_handle);
+
+extern dma_addr_t
+swiotlb_map_single(struct device *hwdev, void *ptr, size_t size, int dir);
+
+extern void
+swiotlb_unmap_single(struct device *hwdev, dma_addr_t dev_addr,
+                     size_t size, int dir);
+
+extern dma_addr_t
+swiotlb_map_single_attrs(struct device *hwdev, void *ptr, size_t size,
+                         int dir, struct dma_attrs *attrs);
+
+extern void
+swiotlb_unmap_single_attrs(struct device *hwdev, dma_addr_t dev_addr,
+                           size_t size, int dir, struct dma_attrs *attrs);
+
+extern int
+swiotlb_map_sg(struct device *hwdev, struct scatterlist *sg, int nents,
+               int direction);
+
+extern void
+swiotlb_unmap_sg(struct device *hwdev, struct scatterlist *sg, int nents,
+                 int direction);
+
+extern int
+swiotlb_map_sg_attrs(struct device *hwdev, struct scatterlist *sgl, int nelems,
+                     int dir, struct dma_attrs *attrs);
+
+extern void
+swiotlb_unmap_sg_attrs(struct device *hwdev, struct scatterlist *sgl,
+                       int nelems, int dir, struct dma_attrs *attrs);
+
+extern void
+swiotlb_sync_single_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
+                            size_t size, int dir);
+
+extern void
+swiotlb_sync_sg_for_cpu(struct device *hwdev, struct scatterlist *sg,
+                        int nelems, int dir);
+
+extern void
+swiotlb_sync_single_for_device(struct device *hwdev, dma_addr_t dev_addr,
+                               size_t size, int dir);
+
+extern void
+swiotlb_sync_sg_for_device(struct device *hwdev, struct scatterlist *sg,
+                           int nelems, int dir);
+
+extern void
+swiotlb_sync_single_range_for_cpu(struct device *hwdev, dma_addr_t dev_addr,
+                                  unsigned long offset, size_t size, int dir);
+
+extern void
+swiotlb_sync_single_range_for_device(struct device *hwdev, dma_addr_t dev_addr,
+                                     unsigned long offset, size_t size,
+                                     int dir);
+
+extern int
+swiotlb_dma_mapping_error(struct device *hwdev, dma_addr_t dma_addr);
+
+extern int
+swiotlb_dma_supported(struct device *hwdev, u64 mask);
+
+#endif /* __LINUX_SWIOTLB_H */
diff --git a/include/linux/sysctl.h b/include/linux/sysctl.h
index d0437f36921f..39d471d1163b 100644
--- a/include/linux/sysctl.h
+++ b/include/linux/sysctl.h
@@ -972,7 +972,7 @@ extern int sysctl_perm(struct ctl_table_root *root,
 
 typedef struct ctl_table ctl_table;
 
-typedef int ctl_handler (struct ctl_table *table, int __user *name, int nlen,
+typedef int ctl_handler (struct ctl_table *table,
                          void __user *oldval, size_t __user *oldlenp,
                          void __user *newval, size_t newlen);
 
diff --git a/include/linux/sysfs.h b/include/linux/sysfs.h
index 37fa24152bd8..b330e289d71f 100644
--- a/include/linux/sysfs.h
+++ b/include/linux/sysfs.h
@@ -78,6 +78,8 @@ struct sysfs_ops {
         ssize_t (*store)(struct kobject *,struct attribute *,const char *, size_t);
 };
 
+struct sysfs_dirent;
+
 #ifdef CONFIG_SYSFS
 
 int sysfs_schedule_callback(struct kobject *kobj, void (*func)(void *),
@@ -117,9 +119,14 @@ int sysfs_add_file_to_group(struct kobject *kobj,
 void sysfs_remove_file_from_group(struct kobject *kobj,
                         const struct attribute *attr, const char *group);
 
-void sysfs_notify(struct kobject *kobj, char *dir, char *attr);
-
-extern int __must_check sysfs_init(void);
+void sysfs_notify(struct kobject *kobj, const char *dir, const char *attr);
+void sysfs_notify_dirent(struct sysfs_dirent *sd);
+struct sysfs_dirent *sysfs_get_dirent(struct sysfs_dirent *parent_sd,
+                                      const unsigned char *name);
+struct sysfs_dirent *sysfs_get(struct sysfs_dirent *sd);
+void sysfs_put(struct sysfs_dirent *sd);
+void sysfs_printk_last_file(void);
+int __must_check sysfs_init(void);
 
 #else /* CONFIG_SYSFS */
 
@@ -222,7 +229,24 @@ static inline void sysfs_remove_file_from_group(struct kobject *kobj,
 {
 }
 
-static inline void sysfs_notify(struct kobject *kobj, char *dir, char *attr)
+static inline void sysfs_notify(struct kobject *kobj, const char *dir,
+                                const char *attr)
+{
+}
+static inline void sysfs_notify_dirent(struct sysfs_dirent *sd)
+{
+}
+static inline
+struct sysfs_dirent *sysfs_get_dirent(struct sysfs_dirent *parent_sd,
+                                      const unsigned char *name)
+{
+        return NULL;
+}
+static inline struct sysfs_dirent *sysfs_get(struct sysfs_dirent *sd)
+{
+        return NULL;
+}
+static inline void sysfs_put(struct sysfs_dirent *sd)
 {
 }
 
@@ -231,6 +255,10 @@ static inline int __must_check sysfs_init(void)
         return 0;
 }
 
+static inline void sysfs_printk_last_file(void)
+{
+}
+
 #endif /* CONFIG_SYSFS */
 
 #endif /* _SYSFS_H_ */
diff --git a/include/linux/task_io_accounting.h b/include/linux/task_io_accounting.h
index 5e88afc9a2fb..bdf855c2856f 100644
--- a/include/linux/task_io_accounting.h
+++ b/include/linux/task_io_accounting.h
@@ -5,7 +5,7 @@
  * Don't include this header file directly - it is designed to be dragged in via
  * sched.h.
  *
- * Blame akpm@osdl.org for all this.
+ * Blame Andrew Morton for all this.
  */
 
 struct task_io_accounting {
diff --git a/include/linux/tc_act/Kbuild b/include/linux/tc_act/Kbuild
index 6dac0d7365cc..76990937f4c9 100644
--- a/include/linux/tc_act/Kbuild
+++ b/include/linux/tc_act/Kbuild
@@ -3,3 +3,4 @@ header-y += tc_ipt.h
 header-y += tc_mirred.h
 header-y += tc_pedit.h
 header-y += tc_nat.h
+header-y += tc_skbedit.h
diff --git a/include/linux/tc_act/tc_skbedit.h b/include/linux/tc_act/tc_skbedit.h
new file mode 100644
index 000000000000..a14e461a7af7
--- /dev/null
+++ b/include/linux/tc_act/tc_skbedit.h
@@ -0,0 +1,44 @@
+/*
+ * Copyright (c) 2008, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Author: Alexander Duyck <alexander.h.duyck@intel.com>
+ */
+
+#ifndef __LINUX_TC_SKBEDIT_H
+#define __LINUX_TC_SKBEDIT_H
+
+#include <linux/pkt_cls.h>
+
+#define TCA_ACT_SKBEDIT 11
+
+#define SKBEDIT_F_PRIORITY              0x1
+#define SKBEDIT_F_QUEUE_MAPPING         0x2
+
+struct tc_skbedit {
+        tc_gen;
+};
+
+enum {
+        TCA_SKBEDIT_UNSPEC,
+        TCA_SKBEDIT_TM,
+        TCA_SKBEDIT_PARMS,
+        TCA_SKBEDIT_PRIORITY,
+        TCA_SKBEDIT_QUEUE_MAPPING,
+        __TCA_SKBEDIT_MAX
+};
+#define TCA_SKBEDIT_MAX (__TCA_SKBEDIT_MAX - 1)
+
+#endif
diff --git a/include/linux/tcp.h b/include/linux/tcp.h
index 2e2557388e36..fe77e1499ab7 100644
--- a/include/linux/tcp.h
+++ b/include/linux/tcp.h
@@ -312,8 +312,11 @@ struct tcp_sock {
         u32     retrans_out;    /* Retransmitted packets out            */
 
         u16     urg_data;       /* Saved octet of OOB data and control flags */
-        u8      urg_mode;       /* In urgent mode               */
         u8      ecn_flags;      /* ECN status bits.                     */
+        u8      reordering;     /* Packet reordering metric.            */
+        u32     snd_up;         /* Urgent pointer               */
+
+        u8      keepalive_probes; /* num of allowed keep alive probes   */
 /*
  *      Options received (usually on last packet, some only on SYN packets).
  */
@@ -342,7 +345,6 @@ struct tcp_sock {
         struct sk_buff* lost_skb_hint;
         struct sk_buff *scoreboard_skb_hint;
         struct sk_buff *retransmit_skb_hint;
-        struct sk_buff *forward_skb_hint;
 
         struct sk_buff_head     out_of_order_queue; /* Out of order segments go here */
 
@@ -358,12 +360,10 @@ struct tcp_sock {
                                          */
 
         int     lost_cnt_hint;
-        int     retransmit_cnt_hint;
+        u32     retransmit_high;        /* L-bits may be on up to this seqno */
 
         u32     lost_retrans_low;       /* Sent seq after any rxmit (lowest) */
 
-        u8      reordering;     /* Packet reordering metric.            */
-        u8      keepalive_probes; /* num of allowed keep alive probes   */
         u32     prior_ssthresh; /* ssthresh saved at recovery start     */
         u32     high_seq;       /* snd_nxt at onset of congestion       */
 
@@ -375,8 +375,6 @@ struct tcp_sock {
         u32     total_retrans;  /* Total retransmits for entire connection */
 
         u32     urg_seq;        /* Seq of received urgent pointer */
-        u32     snd_up;         /* Urgent pointer               */
-
         unsigned int            keepalive_time;   /* time before keep alive takes place */
         unsigned int            keepalive_intvl;  /* time interval between keep alive probes */
 
diff --git a/include/linux/telephony.h b/include/linux/telephony.h
index 0d0cf2a1e7bc..5b2b6261f193 100644
--- a/include/linux/telephony.h
+++ b/include/linux/telephony.h
@@ -28,10 +28,6 @@
  * ON AN "AS IS" BASIS, AND QUICKNET TECHNOLOGIES, INC. HAS NO OBLIGATION
  * TO PROVIDE MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  *
- * Version:       $Revision: 4.2 $
- *
- * $Id: telephony.h,v 4.2 2001/08/06 07:09:43 craigs Exp $
- *
  *****************************************************************************/
 
 #ifndef TELEPHONY_H
diff --git a/include/linux/termios.h b/include/linux/termios.h
index 478662889f48..2acd0c1f8a2a 100644
--- a/include/linux/termios.h
+++ b/include/linux/termios.h
@@ -4,4 +4,19 @@
 #include <linux/types.h>
 #include <asm/termios.h>
 
+#define NFF     5
+
+struct termiox
+{
+        __u16   x_hflag;
+        __u16   x_cflag;
+        __u16   x_rflag[NFF];
+        __u16   x_sflag;
+};
+
+#define RTSXOFF         0x0001          /* RTS flow control on input */
+#define CTSXON          0x0002          /* CTS flow control on output */
+#define DTRXOFF         0x0004          /* DTR flow control on input */
+#define DSRXON          0x0008          /* DCD flow control on output */
+
 #endif
diff --git a/include/linux/tick.h b/include/linux/tick.h
index d3c02695dc5d..b6ec8189ac0c 100644
--- a/include/linux/tick.h
+++ b/include/linux/tick.h
@@ -74,10 +74,13 @@ extern struct tick_device *tick_get_device(int cpu);
 extern int tick_init_highres(void);
 extern int tick_program_event(ktime_t expires, int force);
 extern void tick_setup_sched_timer(void);
+# endif
+
+# if defined CONFIG_NO_HZ || defined CONFIG_HIGH_RES_TIMERS
 extern void tick_cancel_sched_timer(int cpu);
 # else
 static inline void tick_cancel_sched_timer(int cpu) { }
-# endif /* HIGHRES */
+# endif
 
 # ifdef CONFIG_GENERIC_CLOCKEVENTS_BROADCAST
 extern struct tick_device *tick_get_broadcast_device(void);
@@ -93,9 +96,11 @@ extern cpumask_t *tick_get_broadcast_oneshot_mask(void);
 extern void tick_clock_notify(void);
 extern int tick_check_oneshot_change(int allow_nohz);
 extern struct tick_sched *tick_get_tick_sched(int cpu);
+extern void tick_check_idle(int cpu);
 # else
 static inline void tick_clock_notify(void) { }
 static inline int tick_check_oneshot_change(int allow_nohz) { return 0; }
+static inline void tick_check_idle(int cpu) { }
 # endif
 
 #else /* CONFIG_GENERIC_CLOCKEVENTS */
@@ -103,27 +108,24 @@ static inline void tick_init(void) { }
 static inline void tick_cancel_sched_timer(int cpu) { }
 static inline void tick_clock_notify(void) { }
 static inline int tick_check_oneshot_change(int allow_nohz) { return 0; }
+static inline void tick_check_idle(int cpu) { }
 #endif /* !CONFIG_GENERIC_CLOCKEVENTS */
 
 # ifdef CONFIG_NO_HZ
 extern void tick_nohz_stop_sched_tick(int inidle);
 extern void tick_nohz_restart_sched_tick(void);
-extern void tick_nohz_update_jiffies(void);
 extern ktime_t tick_nohz_get_sleep_length(void);
-extern void tick_nohz_stop_idle(int cpu);
 extern u64 get_cpu_idle_time_us(int cpu, u64 *last_update_time);
 # else
 static inline void tick_nohz_stop_sched_tick(int inidle) { }
 static inline void tick_nohz_restart_sched_tick(void) { }
-static inline void tick_nohz_update_jiffies(void) { }
 static inline ktime_t tick_nohz_get_sleep_length(void)
 {
         ktime_t len = { .tv64 = NSEC_PER_SEC/HZ };
 
         return len;
 }
-static inline void tick_nohz_stop_idle(int cpu) { }
-static inline u64 get_cpu_idle_time_us(int cpu, u64 *unused) { return 0; }
+static inline u64 get_cpu_idle_time_us(int cpu, u64 *unused) { return -1; }
 # endif /* !NO_HZ */
 
 #endif
diff --git a/include/linux/time.h b/include/linux/time.h
index 205f974b9ebf..4f1c9db57707 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -29,6 +29,8 @@ struct timezone {
 
 #ifdef __KERNEL__
 
+extern struct timezone sys_tz;
+
 /* Parameters used to convert the timespec values: */
 #define MSEC_PER_SEC    1000L
 #define USEC_PER_MSEC   1000L
@@ -126,6 +128,9 @@ extern int timekeeping_valid_for_hres(void);
 extern void update_wall_time(void);
 extern void update_xtime_cache(u64 nsec);
 
+struct tms;
+extern void do_sys_times(struct tms *);
+
 /**
  * timespec_to_ns - Convert timespec to nanoseconds
  * @ts:         pointer to the timespec variable to be converted
diff --git a/include/linux/timex.h b/include/linux/timex.h
index fc6035d29d56..9007313b5b71 100644
--- a/include/linux/timex.h
+++ b/include/linux/timex.h
@@ -82,7 +82,7 @@
  */
 #define SHIFT_USEC 16           /* frequency offset scale (shift) */
 #define PPM_SCALE (NSEC_PER_USEC << (NTP_SCALE_SHIFT - SHIFT_USEC))
-#define PPM_SCALE_INV_SHIFT 20
+#define PPM_SCALE_INV_SHIFT 19
 #define PPM_SCALE_INV ((1ll << (PPM_SCALE_INV_SHIFT + NTP_SCALE_SHIFT)) / \
                        PPM_SCALE + 1)
 
@@ -141,8 +141,15 @@ struct timex {
 #define ADJ_MICRO               0x1000  /* select microsecond resolution */
 #define ADJ_NANO                0x2000  /* select nanosecond resolution */
 #define ADJ_TICK                0x4000  /* tick value */
+
+#ifdef __KERNEL__
+#define ADJ_ADJTIME             0x8000  /* switch between adjtime/adjtimex modes */
+#define ADJ_OFFSET_SINGLESHOT   0x0001  /* old-fashioned adjtime */
+#define ADJ_OFFSET_READONLY     0x2000  /* read-only adjtime */
+#else
 #define ADJ_OFFSET_SINGLESHOT   0x8001  /* old-fashioned adjtime */
-#define ADJ_OFFSET_SS_READ      0xa001  /* read-only adjtime */
+#define ADJ_OFFSET_SS_READ      0xa001  /* read-only adjtime */
+#endif
 
 /* xntp 3.4 compatibility names */
 #define MOD_OFFSET      ADJ_OFFSET
diff --git a/include/linux/tracehook.h b/include/linux/tracehook.h
index b48d81969574..6186a789d6c7 100644
--- a/include/linux/tracehook.h
+++ b/include/linux/tracehook.h
@@ -272,7 +272,7 @@ static inline void tracehook_finish_clone(struct task_struct *child,
  * tracehook_report_clone_complete().  This must prevent the child from
  * self-reaping if tracehook_report_clone_complete() uses the @child
  * pointer; otherwise it might have died and been released by the time
- * tracehook_report_report_clone_complete() is called.
+ * tracehook_report_clone_complete() is called.
  *
  * Called with no locks held, but the child cannot run until this returns.
  */
diff --git a/include/linux/tty.h b/include/linux/tty.h
index 0cbec74ec086..3b8121d4e36f 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -23,7 +23,7 @@
  */
 #define NR_UNIX98_PTY_DEFAULT   4096      /* Default maximum for Unix98 ptys */
 #define NR_UNIX98_PTY_MAX       (1 << MINORBITS) /* Absolute limit */
-#define NR_LDISCS               18
+#define NR_LDISCS               19
 
 /* line disciplines */
 #define N_TTY           0
@@ -45,6 +45,7 @@
 #define N_HCI           15      /* Bluetooth HCI UART */
 #define N_GIGASET_M101  16      /* Siemens Gigaset M101 serial DECT adapter */
 #define N_SLCAN         17      /* Serial / USB serial CAN Adaptors */
+#define N_PPS           18      /* Pulse per Second */
 
 /*
  * This character is the same as _POSIX_VDISABLE: it cannot be used as
@@ -181,6 +182,7 @@ struct signal_struct;
 
 struct tty_port {
         struct tty_struct       *tty;           /* Back pointer */
+        spinlock_t              lock;           /* Lock protecting tty field */
         int                     blocked_open;   /* Waiting to open */
         int                     count;          /* Usage count */
         wait_queue_head_t       open_wait;      /* Open waiters */
@@ -208,6 +210,7 @@ struct tty_operations;
 
 struct tty_struct {
         int     magic;
+        struct kref kref;
         struct tty_driver *driver;
         const struct tty_operations *ops;
         int index;
@@ -217,6 +220,7 @@ struct tty_struct {
         spinlock_t ctrl_lock;
         /* Termios values are protected by the termios mutex */
         struct ktermios *termios, *termios_locked;
+        struct termiox *termiox;        /* May be NULL for unsupported */
         char name[64];
         struct pid *pgrp;               /* Protected by ctrl lock */
         struct pid *session;
@@ -310,6 +314,25 @@ extern int kmsg_redirect;
 extern void console_init(void);
 extern int vcs_init(void);
 
+extern struct class *tty_class;
+
+/**
+ *      tty_kref_get            -       get a tty reference
+ *      @tty: tty device
+ *
+ *      Return a new reference to a tty object. The caller must hold
+ *      sufficient locks/counts to ensure that their existing reference cannot
+ *      go away
+ */
+
+extern inline struct tty_struct *tty_kref_get(struct tty_struct *tty)
+{
+        if (tty)
+                kref_get(&tty->kref);
+        return tty;
+}
+extern void tty_kref_put(struct tty_struct *tty);
+
 extern int tty_paranoia_check(struct tty_struct *tty, struct inode *inode,
                               const char *routine);
 extern char *tty_name(struct tty_struct *tty, char *buf);
@@ -333,13 +356,15 @@ extern void tty_throttle(struct tty_struct *tty);
 extern void tty_unthrottle(struct tty_struct *tty);
 extern int tty_do_resize(struct tty_struct *tty, struct tty_struct *real_tty,
                                                 struct winsize *ws);
-
+extern void tty_shutdown(struct tty_struct *tty);
+extern void tty_free_termios(struct tty_struct *tty);
 extern int is_current_pgrp_orphaned(void);
 extern struct pid *tty_get_pgrp(struct tty_struct *tty);
 extern int is_ignored(int sig);
 extern int tty_signal(int sig, struct tty_struct *tty);
 extern void tty_hangup(struct tty_struct *tty);
 extern void tty_vhangup(struct tty_struct *tty);
+extern void tty_vhangup_self(void);
 extern void tty_unhangup(struct file *filp);
 extern int tty_hung_up_p(struct file *filp);
 extern void do_SAK(struct tty_struct *tty);
@@ -347,6 +372,9 @@ extern void __do_SAK(struct tty_struct *tty);
 extern void disassociate_ctty(int priv);
 extern void no_tty(void);
 extern void tty_flip_buffer_push(struct tty_struct *tty);
+extern void tty_buffer_free_all(struct tty_struct *tty);
+extern void tty_buffer_flush(struct tty_struct *tty);
+extern void tty_buffer_init(struct tty_struct *tty);
 extern speed_t tty_get_baud_rate(struct tty_struct *tty);
 extern speed_t tty_termios_baud_rate(struct ktermios *termios);
 extern speed_t tty_termios_input_baud_rate(struct ktermios *termios);
@@ -372,6 +400,15 @@ extern int tty_perform_flush(struct tty_struct *tty, unsigned long arg);
 extern dev_t tty_devnum(struct tty_struct *tty);
 extern void proc_clear_tty(struct task_struct *p);
 extern struct tty_struct *get_current_tty(void);
+extern void tty_default_fops(struct file_operations *fops);
+extern struct tty_struct *alloc_tty_struct(void);
+extern void free_tty_struct(struct tty_struct *tty);
+extern void initialize_tty_struct(struct tty_struct *tty,
+                struct tty_driver *driver, int idx);
+extern struct tty_struct *tty_init_dev(struct tty_driver *driver, int idx,
+                                                                int first_ok);
+extern void tty_release_dev(struct file *filp);
+extern int tty_init_termios(struct tty_struct *tty);
 
 extern struct mutex tty_mutex;
 
@@ -382,6 +419,8 @@ extern int tty_write_lock(struct tty_struct *tty, int ndelay);
 extern void tty_port_init(struct tty_port *port);
 extern int tty_port_alloc_xmit_buf(struct tty_port *port);
 extern void tty_port_free_xmit_buf(struct tty_port *port);
+extern struct tty_struct *tty_port_tty_get(struct tty_port *port);
+extern void tty_port_tty_set(struct tty_port *port, struct tty_struct *tty);
 
 extern int tty_register_ldisc(int disc, struct tty_ldisc_ops *new_ldisc);
 extern int tty_unregister_ldisc(int disc);
@@ -427,7 +466,7 @@ static inline void tty_audit_push_task(struct task_struct *tsk,
 #endif
 
 /* tty_ioctl.c */
-extern int n_tty_ioctl(struct tty_struct *tty, struct file *file,
+extern int n_tty_ioctl_helper(struct tty_struct *tty, struct file *file,
                        unsigned int cmd, unsigned long arg);
 
 /* serial.c */
diff --git a/include/linux/tty_driver.h b/include/linux/tty_driver.h
index 16d27944c321..78416b901589 100644
--- a/include/linux/tty_driver.h
+++ b/include/linux/tty_driver.h
@@ -7,6 +7,28 @@
  * defined; unless noted otherwise, they are optional, and can be
  * filled in with a null pointer.
  *
+ * struct tty_struct * (*lookup)(struct tty_driver *self, int idx)
+ *
+ *      Return the tty device corresponding to idx, NULL if there is not
+ *      one currently in use and an ERR_PTR value on error. Called under
+ *      tty_mutex (for now!)
+ *
+ *      Optional method. Default behaviour is to use the ttys array
+ *
+ * int (*install)(struct tty_driver *self, struct tty_struct *tty)
+ *
+ *      Install a new tty into the tty driver internal tables. Used in
+ *      conjunction with lookup and remove methods.
+ *
+ *      Optional method. Default behaviour is to use the ttys array
+ *
+ * void (*remove)(struct tty_driver *self, struct tty_struct *tty)
+ *
+ *      Remove a closed tty from the tty driver internal tables. Used in
+ *      conjunction with lookup and remove methods.
+ *
+ *      Optional method. Default behaviour is to use the ttys array
+ *
  * int  (*open)(struct tty_struct * tty, struct file * filp);
  *
  *      This routine is called when a particular tty device is opened.
@@ -21,6 +43,11 @@
  *
  *      Required method.
  *
+ * void (*shutdown)(struct tty_struct * tty);
+ *
+ *      This routine is called when a particular tty device is closed for
+ *      the last time freeing up the resources.
+ *
  * int (*write)(struct tty_struct * tty,
  *               const unsigned char *buf, int count);
  *
@@ -180,6 +207,14 @@
  *      not force errors here if they are not resizable objects (eg a serial
  *      line). See tty_do_resize() if you need to wrap the standard method
  *      in your own logic - the usual case.
+ *
+ * void (*set_termiox)(struct tty_struct *tty, struct termiox *new);
+ *
+ *      Called when the device receives a termiox based ioctl. Passes down
+ *      the requested data from user space. This method will not be invoked
+ *      unless the tty also has a valid tty->termiox pointer.
+ *
+ *      Optional: Called under the termios lock
  */
 
 #include <linux/fs.h>
@@ -190,8 +225,13 @@ struct tty_struct;
 struct tty_driver;
 
 struct tty_operations {
+        struct tty_struct * (*lookup)(struct tty_driver *driver,
+                        struct inode *inode, int idx);
+        int  (*install)(struct tty_driver *driver, struct tty_struct *tty);
+        void (*remove)(struct tty_driver *driver, struct tty_struct *tty);
         int  (*open)(struct tty_struct * tty, struct file * filp);
         void (*close)(struct tty_struct * tty, struct file * filp);
+        void (*shutdown)(struct tty_struct *tty);
         int  (*write)(struct tty_struct * tty,
                       const unsigned char *buf, int count);
         int  (*put_char)(struct tty_struct *tty, unsigned char ch);
@@ -220,6 +260,7 @@ struct tty_operations {
                         unsigned int set, unsigned int clear);
         int (*resize)(struct tty_struct *tty, struct tty_struct *real_tty,
                                 struct winsize *ws);
+        int (*set_termiox)(struct tty_struct *tty, struct termiox *tnew);
 #ifdef CONFIG_CONSOLE_POLL
         int (*poll_init)(struct tty_driver *driver, int line, char *options);
         int (*poll_get_char)(struct tty_driver *driver, int line);
@@ -229,6 +270,7 @@ struct tty_operations {
 
 struct tty_driver {
         int     magic;          /* magic number for this structure */
+        struct kref kref;       /* Reference management */
         struct cdev cdev;
         struct module   *owner;
         const char      *driver_name;
@@ -242,7 +284,6 @@ struct tty_driver {
         short   subtype;        /* subtype of tty driver */
         struct ktermios init_termios; /* Initial termios */
         int     flags;          /* tty driver flags */
-        int     refcount;       /* for loadable tty drivers */
         struct proc_dir_entry *proc_entry; /* /proc fs entry */
         struct tty_driver *other; /* only used for the PTY driver */
 
@@ -264,12 +305,19 @@ struct tty_driver {
 
 extern struct list_head tty_drivers;
 
-struct tty_driver *alloc_tty_driver(int lines);
-void put_tty_driver(struct tty_driver *driver);
-void tty_set_operations(struct tty_driver *driver,
+extern struct tty_driver *alloc_tty_driver(int lines);
+extern void put_tty_driver(struct tty_driver *driver);
+extern void tty_set_operations(struct tty_driver *driver,
                         const struct tty_operations *op);
 extern struct tty_driver *tty_find_polling_driver(char *name, int *line);
 
+extern void tty_driver_kref_put(struct tty_driver *driver);
+extern inline struct tty_driver *tty_driver_kref_get(struct tty_driver *d)
+{
+        kref_get(&d->kref);
+        return d;
+}
+
 /* tty driver magic number */
 #define TTY_DRIVER_MAGIC                0x5402
 
diff --git a/include/linux/types.h b/include/linux/types.h
index d4a9ce6e2760..f24f7beb47df 100644
--- a/include/linux/types.h
+++ b/include/linux/types.h
@@ -191,12 +191,14 @@ typedef __u32 __bitwise __wsum;
 #ifdef __KERNEL__
 typedef unsigned __bitwise__ gfp_t;
 
-#ifdef CONFIG_RESOURCES_64BIT
-typedef u64 resource_size_t;
+#ifdef CONFIG_PHYS_ADDR_T_64BIT
+typedef u64 phys_addr_t;
 #else
-typedef u32 resource_size_t;
+typedef u32 phys_addr_t;
 #endif
 
+typedef phys_addr_t resource_size_t;
+
 struct ustat {
         __kernel_daddr_t        f_tfree;
         __kernel_ino_t          f_tinode;
diff --git a/include/linux/ucb1400.h b/include/linux/ucb1400.h
new file mode 100644
index 000000000000..970473bf8d5a
--- /dev/null
+++ b/include/linux/ucb1400.h
@@ -0,0 +1,161 @@
+/*
+ * Register definitions and functions for:
+ *  Philips UCB1400 driver
+ *
+ * Based on ucb1400_ts:
+ *  Author:     Nicolas Pitre
+ *  Created:    September 25, 2006
+ *  Copyright:  MontaVista Software, Inc.
+ *
+ * Spliting done by: Marek Vasut <marek.vasut@gmail.com>
+ * If something doesnt work and it worked before spliting, e-mail me,
+ * dont bother Nicolas please ;-)
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This code is heavily based on ucb1x00-*.c copyrighted by Russell King
+ * covering the UCB1100, UCB1200 and UCB1300..  Support for the UCB1400 has
+ * been made separate from ucb1x00-core/ucb1x00-ts on Russell's request.
+ */
+
+#ifndef _LINUX__UCB1400_H
+#define _LINUX__UCB1400_H
+
+#include <sound/ac97_codec.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+
+/*
+ * UCB1400 AC-link registers
+ */
+
+#define UCB_IO_DATA             0x5a
+#define UCB_IO_DIR              0x5c
+#define UCB_IE_RIS              0x5e
+#define UCB_IE_FAL              0x60
+#define UCB_IE_STATUS           0x62
+#define UCB_IE_CLEAR            0x62
+#define UCB_IE_ADC              (1 << 11)
+#define UCB_IE_TSPX             (1 << 12)
+
+#define UCB_TS_CR               0x64
+#define UCB_TS_CR_TSMX_POW      (1 << 0)
+#define UCB_TS_CR_TSPX_POW      (1 << 1)
+#define UCB_TS_CR_TSMY_POW      (1 << 2)
+#define UCB_TS_CR_TSPY_POW      (1 << 3)
+#define UCB_TS_CR_TSMX_GND      (1 << 4)
+#define UCB_TS_CR_TSPX_GND      (1 << 5)
+#define UCB_TS_CR_TSMY_GND      (1 << 6)
+#define UCB_TS_CR_TSPY_GND      (1 << 7)
+#define UCB_TS_CR_MODE_INT      (0 << 8)
+#define UCB_TS_CR_MODE_PRES     (1 << 8)
+#define UCB_TS_CR_MODE_POS      (2 << 8)
+#define UCB_TS_CR_BIAS_ENA      (1 << 11)
+#define UCB_TS_CR_TSPX_LOW      (1 << 12)
+#define UCB_TS_CR_TSMX_LOW      (1 << 13)
+
+#define UCB_ADC_CR              0x66
+#define UCB_ADC_SYNC_ENA        (1 << 0)
+#define UCB_ADC_VREFBYP_CON     (1 << 1)
+#define UCB_ADC_INP_TSPX        (0 << 2)
+#define UCB_ADC_INP_TSMX        (1 << 2)
+#define UCB_ADC_INP_TSPY        (2 << 2)
+#define UCB_ADC_INP_TSMY        (3 << 2)
+#define UCB_ADC_INP_AD0         (4 << 2)
+#define UCB_ADC_INP_AD1         (5 << 2)
+#define UCB_ADC_INP_AD2         (6 << 2)
+#define UCB_ADC_INP_AD3         (7 << 2)
+#define UCB_ADC_EXT_REF         (1 << 5)
+#define UCB_ADC_START           (1 << 7)
+#define UCB_ADC_ENA             (1 << 15)
+
+#define UCB_ADC_DATA            0x68
+#define UCB_ADC_DAT_VALID       (1 << 15)
+#define UCB_ADC_DAT_MASK        0x3ff
+
+#define UCB_ID                  0x7e
+#define UCB_ID_1400             0x4304
+
+struct ucb1400_ts {
+        struct input_dev        *ts_idev;
+        struct task_struct      *ts_task;
+        int                     id;
+        wait_queue_head_t       ts_wait;
+        unsigned int            ts_restart:1;
+        int                     irq;
+        unsigned int            irq_pending;    /* not bit field shared */
+        struct snd_ac97         *ac97;
+};
+
+struct ucb1400 {
+        struct platform_device  *ucb1400_ts;
+};
+
+static inline u16 ucb1400_reg_read(struct snd_ac97 *ac97, u16 reg)
+{
+        return ac97->bus->ops->read(ac97, reg);
+}
+
+static inline void ucb1400_reg_write(struct snd_ac97 *ac97, u16 reg, u16 val)
+{
+        ac97->bus->ops->write(ac97, reg, val);
+}
+
+static inline u16 ucb1400_gpio_get_value(struct snd_ac97 *ac97, u16 gpio)
+{
+        return ucb1400_reg_read(ac97, UCB_IO_DATA) & (1 << gpio);
+}
+
+static inline void ucb1400_gpio_set_value(struct snd_ac97 *ac97, u16 gpio,
+                                                u16 val)
+{
+        ucb1400_reg_write(ac97, UCB_IO_DATA, val ?
+                        ucb1400_reg_read(ac97, UCB_IO_DATA) | (1 << gpio) :
+                        ucb1400_reg_read(ac97, UCB_IO_DATA) & ~(1 << gpio));
+}
+
+static inline u16 ucb1400_gpio_get_direction(struct snd_ac97 *ac97, u16 gpio)
+{
+        return ucb1400_reg_read(ac97, UCB_IO_DIR) & (1 << gpio);
+}
+
+static inline void ucb1400_gpio_set_direction(struct snd_ac97 *ac97, u16 gpio,
+                                                u16 dir)
+{
+        ucb1400_reg_write(ac97, UCB_IO_DIR, dir ?
+                        ucb1400_reg_read(ac97, UCB_IO_DIR) | (1 << gpio) :
+                        ucb1400_reg_read(ac97, UCB_IO_DIR) & ~(1 << gpio));
+}
+
+static inline void ucb1400_adc_enable(struct snd_ac97 *ac97)
+{
+        ucb1400_reg_write(ac97, UCB_ADC_CR, UCB_ADC_ENA);
+}
+
+static unsigned int ucb1400_adc_read(struct snd_ac97 *ac97, u16 adc_channel,
+                                        int adcsync)
+{
+        unsigned int val;
+
+        if (adcsync)
+                adc_channel |= UCB_ADC_SYNC_ENA;
+
+        ucb1400_reg_write(ac97, UCB_ADC_CR, UCB_ADC_ENA | adc_channel);
+        ucb1400_reg_write(ac97, UCB_ADC_CR, UCB_ADC_ENA | adc_channel |
+                                UCB_ADC_START);
+
+        while (!((val = ucb1400_reg_read(ac97, UCB_ADC_DATA))
+                        & UCB_ADC_DAT_VALID))
+                schedule_timeout_uninterruptible(1);
+
+        return val & UCB_ADC_DAT_MASK;
+}
+
+static inline void ucb1400_adc_disable(struct snd_ac97 *ac97)
+{
+        ucb1400_reg_write(ac97, UCB_ADC_CR, 0);
+}
+
+#endif
diff --git a/include/linux/usb.h b/include/linux/usb.h
index 0924cd9c30f6..8fa973bede5e 100644
--- a/include/linux/usb.h
+++ b/include/linux/usb.h
@@ -110,6 +110,8 @@ enum usb_interface_condition {
  * @sysfs_files_created: sysfs attributes exist
  * @needs_remote_wakeup: flag set when the driver requires remote-wakeup
  *      capability during autosuspend.
+ * @needs_altsetting0: flag set when a set-interface request for altsetting 0
+ *      has been deferred.
  * @needs_binding: flag set when the driver should be re-probed or unbound
  *      following a reset or suspend operation it doesn't support.
  * @dev: driver model's view of this device
@@ -162,6 +164,7 @@ struct usb_interface {
         unsigned is_active:1;           /* the interface is not suspended */
         unsigned sysfs_files_created:1; /* the sysfs attributes exist */
         unsigned needs_remote_wakeup:1; /* driver requires remote wakeup */
+        unsigned needs_altsetting0:1;   /* switch to altsetting 0 is pending */
         unsigned needs_binding:1;       /* needs delayed unbind/rebind */
 
         struct device dev;              /* interface specific device info */
@@ -1132,6 +1135,7 @@ struct usb_anchor {
         struct list_head urb_list;
         wait_queue_head_t wait;
         spinlock_t lock;
+        unsigned int poisoned:1;
 };
 
 static inline void init_usb_anchor(struct usb_anchor *anchor)
@@ -1456,12 +1460,18 @@ extern struct urb *usb_get_urb(struct urb *urb);
 extern int usb_submit_urb(struct urb *urb, gfp_t mem_flags);
 extern int usb_unlink_urb(struct urb *urb);
 extern void usb_kill_urb(struct urb *urb);
+extern void usb_poison_urb(struct urb *urb);
+extern void usb_unpoison_urb(struct urb *urb);
 extern void usb_kill_anchored_urbs(struct usb_anchor *anchor);
+extern void usb_poison_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_unlink_anchored_urbs(struct usb_anchor *anchor);
 extern void usb_anchor_urb(struct urb *urb, struct usb_anchor *anchor);
 extern void usb_unanchor_urb(struct urb *urb);
 extern int usb_wait_anchor_empty_timeout(struct usb_anchor *anchor,
                                          unsigned int timeout);
+extern struct urb *usb_get_from_anchor(struct usb_anchor *anchor);
+extern void usb_scuttle_anchored_urbs(struct usb_anchor *anchor);
+extern int usb_anchor_empty(struct usb_anchor *anchor);
 
 /**
  * usb_urb_dir_in - check if an URB describes an IN transfer
diff --git a/include/linux/usb/Kbuild b/include/linux/usb/Kbuild
index 42e84fc315e3..54c446309a2a 100644
--- a/include/linux/usb/Kbuild
+++ b/include/linux/usb/Kbuild
@@ -4,4 +4,5 @@ header-y += ch9.h
 header-y += gadgetfs.h
 header-y += midi.h
 header-y += g_printer.h
-
+header-y += tmc.h
+header-y += vstusb.h
diff --git a/include/linux/usb/cdc.h b/include/linux/usb/cdc.h
index ca228bb94218..18a729343ffa 100644
--- a/include/linux/usb/cdc.h
+++ b/include/linux/usb/cdc.h
@@ -160,6 +160,15 @@ struct usb_cdc_mdlm_detail_desc {
         __u8    bDetailData[0];
 } __attribute__ ((packed));
 
+/* "OBEX Control Model Functional Descriptor" */
+struct usb_cdc_obex_desc {
+        __u8    bLength;
+        __u8    bDescriptorType;
+        __u8    bDescriptorSubType;
+
+        __le16  bcdVersion;
+} __attribute__ ((packed));
+
 /*-------------------------------------------------------------------------*/
 
 /*
diff --git a/include/linux/usb/composite.h b/include/linux/usb/composite.h
index c932390c6da0..935c380ffe47 100644
--- a/include/linux/usb/composite.h
+++ b/include/linux/usb/composite.h
@@ -130,6 +130,9 @@ struct usb_function {
 
 int usb_add_function(struct usb_configuration *, struct usb_function *);
 
+int usb_function_deactivate(struct usb_function *);
+int usb_function_activate(struct usb_function *);
+
 int usb_interface_id(struct usb_configuration *, struct usb_function *);
 
 /**
@@ -316,9 +319,13 @@ struct usb_composite_dev {
         struct usb_composite_driver     *driver;
         u8                              next_string_id;
 
-        spinlock_t                      lock;
+        /* the gadget driver won't enable the data pullup
+         * while the deactivation count is nonzero.
+         */
+        unsigned                        deactivations;
 
-        /* REVISIT use and existence of lock ... */
+        /* protects at least deactivation count */
+        spinlock_t                      lock;
 };
 
 extern int usb_string_id(struct usb_composite_dev *c);
diff --git a/include/linux/usb/ehci_def.h b/include/linux/usb/ehci_def.h
new file mode 100644
index 000000000000..5b88e36c9103
--- /dev/null
+++ b/include/linux/usb/ehci_def.h
@@ -0,0 +1,160 @@
+/*
+ * Copyright (c) 2001-2002 by David Brownell
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
+ * or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software Foundation,
+ * Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#ifndef __LINUX_USB_EHCI_DEF_H
+#define __LINUX_USB_EHCI_DEF_H
+
+/* EHCI register interface, corresponds to EHCI Revision 0.95 specification */
+
+/* Section 2.2 Host Controller Capability Registers */
+struct ehci_caps {
+        /* these fields are specified as 8 and 16 bit registers,
+         * but some hosts can't perform 8 or 16 bit PCI accesses.
+         */
+        u32             hc_capbase;
+#define HC_LENGTH(p)            (((p)>>00)&0x00ff)      /* bits 7:0 */
+#define HC_VERSION(p)           (((p)>>16)&0xffff)      /* bits 31:16 */
+        u32             hcs_params;     /* HCSPARAMS - offset 0x4 */
+#define HCS_DEBUG_PORT(p)       (((p)>>20)&0xf) /* bits 23:20, debug port? */
+#define HCS_INDICATOR(p)        ((p)&(1 << 16)) /* true: has port indicators */
+#define HCS_N_CC(p)             (((p)>>12)&0xf) /* bits 15:12, #companion HCs */
+#define HCS_N_PCC(p)            (((p)>>8)&0xf)  /* bits 11:8, ports per CC */
+#define HCS_PORTROUTED(p)       ((p)&(1 << 7))  /* true: port routing */
+#define HCS_PPC(p)              ((p)&(1 << 4))  /* true: port power control */
+#define HCS_N_PORTS(p)          (((p)>>0)&0xf)  /* bits 3:0, ports on HC */
+
+        u32             hcc_params;      /* HCCPARAMS - offset 0x8 */
+#define HCC_EXT_CAPS(p)         (((p)>>8)&0xff) /* for pci extended caps */
+#define HCC_ISOC_CACHE(p)       ((p)&(1 << 7))  /* true: can cache isoc frame */
+#define HCC_ISOC_THRES(p)       (((p)>>4)&0x7)  /* bits 6:4, uframes cached */
+#define HCC_CANPARK(p)          ((p)&(1 << 2))  /* true: can park on async qh */
+#define HCC_PGM_FRAMELISTLEN(p) ((p)&(1 << 1))  /* true: periodic_size changes*/
+#define HCC_64BIT_ADDR(p)       ((p)&(1))       /* true: can use 64-bit addr */
+        u8              portroute [8];   /* nibbles for routing - offset 0xC */
+} __attribute__ ((packed));
+
+
+/* Section 2.3 Host Controller Operational Registers */
+struct ehci_regs {
+
+        /* USBCMD: offset 0x00 */
+        u32             command;
+/* 23:16 is r/w intr rate, in microframes; default "8" == 1/msec */
+#define CMD_PARK        (1<<11)         /* enable "park" on async qh */
+#define CMD_PARK_CNT(c) (((c)>>8)&3)    /* how many transfers to park for */
+#define CMD_LRESET      (1<<7)          /* partial reset (no ports, etc) */
+#define CMD_IAAD        (1<<6)          /* "doorbell" interrupt async advance */
+#define CMD_ASE         (1<<5)          /* async schedule enable */
+#define CMD_PSE         (1<<4)          /* periodic schedule enable */
+/* 3:2 is periodic frame list size */
+#define CMD_RESET       (1<<1)          /* reset HC not bus */
+#define CMD_RUN         (1<<0)          /* start/stop HC */
+
+        /* USBSTS: offset 0x04 */
+        u32             status;
+#define STS_ASS         (1<<15)         /* Async Schedule Status */
+#define STS_PSS         (1<<14)         /* Periodic Schedule Status */
+#define STS_RECL        (1<<13)         /* Reclamation */
+#define STS_HALT        (1<<12)         /* Not running (any reason) */
+/* some bits reserved */
+        /* these STS_* flags are also intr_enable bits (USBINTR) */
+#define STS_IAA         (1<<5)          /* Interrupted on async advance */
+#define STS_FATAL       (1<<4)          /* such as some PCI access errors */
+#define STS_FLR         (1<<3)          /* frame list rolled over */
+#define STS_PCD         (1<<2)          /* port change detect */
+#define STS_ERR         (1<<1)          /* "error" completion (overflow, ...) */
+#define STS_INT         (1<<0)          /* "normal" completion (short, ...) */
+
+        /* USBINTR: offset 0x08 */
+        u32             intr_enable;
+
+        /* FRINDEX: offset 0x0C */
+        u32             frame_index;    /* current microframe number */
+        /* CTRLDSSEGMENT: offset 0x10 */
+        u32             segment;        /* address bits 63:32 if needed */
+        /* PERIODICLISTBASE: offset 0x14 */
+        u32             frame_list;     /* points to periodic list */
+        /* ASYNCLISTADDR: offset 0x18 */
+        u32             async_next;     /* address of next async queue head */
+
+        u32             reserved [9];
+
+        /* CONFIGFLAG: offset 0x40 */
+        u32             configured_flag;
+#define FLAG_CF         (1<<0)          /* true: we'll support "high speed" */
+
+        /* PORTSC: offset 0x44 */
+        u32             port_status [0];        /* up to N_PORTS */
+/* 31:23 reserved */
+#define PORT_WKOC_E     (1<<22)         /* wake on overcurrent (enable) */
+#define PORT_WKDISC_E   (1<<21)         /* wake on disconnect (enable) */
+#define PORT_WKCONN_E   (1<<20)         /* wake on connect (enable) */
+/* 19:16 for port testing */
+#define PORT_LED_OFF    (0<<14)
+#define PORT_LED_AMBER  (1<<14)
+#define PORT_LED_GREEN  (2<<14)
+#define PORT_LED_MASK   (3<<14)
+#define PORT_OWNER      (1<<13)         /* true: companion hc owns this port */
+#define PORT_POWER      (1<<12)         /* true: has power (see PPC) */
+#define PORT_USB11(x) (((x)&(3<<10)) == (1<<10))        /* USB 1.1 device */
+/* 11:10 for detecting lowspeed devices (reset vs release ownership) */
+/* 9 reserved */
+#define PORT_RESET      (1<<8)          /* reset port */
+#define PORT_SUSPEND    (1<<7)          /* suspend port */
+#define PORT_RESUME     (1<<6)          /* resume it */
+#define PORT_OCC        (1<<5)          /* over current change */
+#define PORT_OC         (1<<4)          /* over current active */
+#define PORT_PEC        (1<<3)          /* port enable change */
+#define PORT_PE         (1<<2)          /* port enable */
+#define PORT_CSC        (1<<1)          /* connect status change */
+#define PORT_CONNECT    (1<<0)          /* device connected */
+#define PORT_RWC_BITS   (PORT_CSC | PORT_PEC | PORT_OCC)
+} __attribute__ ((packed));
+
+#define USBMODE         0x68            /* USB Device mode */
+#define USBMODE_SDIS    (1<<3)          /* Stream disable */
+#define USBMODE_BE      (1<<2)          /* BE/LE endianness select */
+#define USBMODE_CM_HC   (3<<0)          /* host controller mode */
+#define USBMODE_CM_IDLE (0<<0)          /* idle state */
+
+/* Appendix C, Debug port ... intended for use with special "debug devices"
+ * that can help if there's no serial console.  (nonstandard enumeration.)
+ */
+struct ehci_dbg_port {
+        u32     control;
+#define DBGP_OWNER      (1<<30)
+#define DBGP_ENABLED    (1<<28)
+#define DBGP_DONE       (1<<16)
+#define DBGP_INUSE      (1<<10)
+#define DBGP_ERRCODE(x) (((x)>>7)&0x07)
+#       define DBGP_ERR_BAD     1
+#       define DBGP_ERR_SIGNAL  2
+#define DBGP_ERROR      (1<<6)
+#define DBGP_GO         (1<<5)
+#define DBGP_OUT        (1<<4)
+#define DBGP_LEN(x)     (((x)>>0)&0x0f)
+        u32     pids;
+#define DBGP_PID_GET(x)         (((x)>>16)&0xff)
+#define DBGP_PID_SET(data, tok) (((data)<<8)|(tok))
+        u32     data03;
+        u32     data47;
+        u32     address;
+#define DBGP_EPADDR(dev, ep)    (((dev)<<8)|(ep))
+} __attribute__ ((packed));
+
+#endif /* __LINUX_USB_EHCI_DEF_H */
diff --git a/include/linux/usb/serial.h b/include/linux/usb/serial.h
index 655341d0f534..0b8617a9176d 100644
--- a/include/linux/usb/serial.h
+++ b/include/linux/usb/serial.h
@@ -192,7 +192,7 @@ static inline void usb_set_serial_data(struct usb_serial *serial, void *data)
  * The driver.owner field should be set to the module owner of this driver.
  * The driver.name field should be set to the name of this driver (remember
  * it will show up in sysfs, so it needs to be short and to the point.
- * Useing the module name is a good idea.)
+ * Using the module name is a good idea.)
  */
 struct usb_serial_driver {
         const char *description;
diff --git a/include/linux/usb/tmc.h b/include/linux/usb/tmc.h
new file mode 100644
index 000000000000..c045ae12556c
--- /dev/null
+++ b/include/linux/usb/tmc.h
@@ -0,0 +1,43 @@
+/*
+ * Copyright (C) 2007 Stefan Kopp, Gechingen, Germany
+ * Copyright (C) 2008 Novell, Inc.
+ * Copyright (C) 2008 Greg Kroah-Hartman <gregkh@suse.de>
+ *
+ * This file holds USB constants defined by the USB Device Class
+ * Definition for Test and Measurement devices published by the USB-IF.
+ *
+ * It also has the ioctl definitions for the usbtmc kernel driver that
+ * userspace needs to know about.
+ */
+
+#ifndef __LINUX_USB_TMC_H
+#define __LINUX_USB_TMC_H
+
+/* USB TMC status values */
+#define USBTMC_STATUS_SUCCESS                           0x01
+#define USBTMC_STATUS_PENDING                           0x02
+#define USBTMC_STATUS_FAILED                            0x80
+#define USBTMC_STATUS_TRANSFER_NOT_IN_PROGRESS          0x81
+#define USBTMC_STATUS_SPLIT_NOT_IN_PROGRESS             0x82
+#define USBTMC_STATUS_SPLIT_IN_PROGRESS                 0x83
+
+/* USB TMC requests values */
+#define USBTMC_REQUEST_INITIATE_ABORT_BULK_OUT          1
+#define USBTMC_REQUEST_CHECK_ABORT_BULK_OUT_STATUS      2
+#define USBTMC_REQUEST_INITIATE_ABORT_BULK_IN           3
+#define USBTMC_REQUEST_CHECK_ABORT_BULK_IN_STATUS       4
+#define USBTMC_REQUEST_INITIATE_CLEAR                   5
+#define USBTMC_REQUEST_CHECK_CLEAR_STATUS               6
+#define USBTMC_REQUEST_GET_CAPABILITIES                 7
+#define USBTMC_REQUEST_INDICATOR_PULSE                  64
+
+/* Request values for USBTMC driver's ioctl entry point */
+#define USBTMC_IOC_NR                   91
+#define USBTMC_IOCTL_INDICATOR_PULSE    _IO(USBTMC_IOC_NR, 1)
+#define USBTMC_IOCTL_CLEAR              _IO(USBTMC_IOC_NR, 2)
+#define USBTMC_IOCTL_ABORT_BULK_OUT     _IO(USBTMC_IOC_NR, 3)
+#define USBTMC_IOCTL_ABORT_BULK_IN      _IO(USBTMC_IOC_NR, 4)
+#define USBTMC_IOCTL_CLEAR_OUT_HALT     _IO(USBTMC_IOC_NR, 6)
+#define USBTMC_IOCTL_CLEAR_IN_HALT      _IO(USBTMC_IOC_NR, 7)
+
+#endif
diff --git a/include/linux/usb/vstusb.h b/include/linux/usb/vstusb.h
new file mode 100644
index 000000000000..1cfac67191ff
--- /dev/null
+++ b/include/linux/usb/vstusb.h
@@ -0,0 +1,71 @@
+/*****************************************************************************
+ *  File: drivers/usb/misc/vstusb.h
+ *
+ *  Purpose: Support for the bulk USB Vernier Spectrophotometers
+ *
+ *  Author:     EQware Engineering, Inc.
+ *              Oregon City, OR, USA 97045
+ *
+ *  Copyright:  2007, 2008
+ *              Vernier Software & Technology
+ *              Beaverton, OR, USA 97005
+ *
+ *  Web:        www.vernier.com
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License version 2 as
+ *  published by the Free Software Foundation.
+ *
+ *****************************************************************************/
+/*****************************************************************************
+ *
+ *  The vstusb module is a standard usb 'client' driver running on top of the
+ *  standard usb host controller stack.
+ *
+ *  In general, vstusb supports standard bulk usb pipes.  It supports multiple
+ *  devices and multiple pipes per device.
+ *
+ *  The vstusb driver supports two interfaces:
+ *  1 - ioctl SEND_PIPE/RECV_PIPE - a general bulk write/read msg
+ *      interface to any pipe with timeout support;
+ *  2 - standard read/write with ioctl config - offers standard read/write
+ *      interface with ioctl configured pipes and timeouts.
+ *
+ *  Both interfaces can be signal from other process and will abort its i/o
+ *  operation.
+ *
+ *  A timeout of 0 means NO timeout.  The user can still terminate the read via
+ *  signal.
+ *
+ *  If using multiple threads with this driver, the user should ensure that
+ *  any reads, writes, or ioctls are complete before closing the device.
+ *  Changing read/write timeouts or pipes takes effect on next read/write.
+ *
+ *****************************************************************************/
+
+struct vstusb_args {
+        union {
+                /* this struct is used for IOCTL_VSTUSB_SEND_PIPE,      *
+                 * IOCTL_VSTUSB_RECV_PIPE, and read()/write() fops      */
+                struct {
+                        void __user     *buffer;
+                        size_t          count;
+                        unsigned int    timeout_ms;
+                        int             pipe;
+                };
+
+                /* this one is used for IOCTL_VSTUSB_CONFIG_RW          */
+                struct {
+                        int rd_pipe;
+                        int rd_timeout_ms;
+                        int wr_pipe;
+                        int wr_timeout_ms;
+                };
+        };
+};
+
+#define VST_IOC_MAGIC 'L'
+#define VST_IOC_FIRST 0x20
+#define IOCTL_VSTUSB_SEND_PIPE  _IO(VST_IOC_MAGIC, VST_IOC_FIRST)
+#define IOCTL_VSTUSB_RECV_PIPE  _IO(VST_IOC_MAGIC, VST_IOC_FIRST + 1)
+#define IOCTL_VSTUSB_CONFIG_RW  _IO(VST_IOC_MAGIC, VST_IOC_FIRST + 2)
diff --git a/include/linux/videodev2.h b/include/linux/videodev2.h
index e65a6bed4e3e..d4b03034ee73 100644
--- a/include/linux/videodev2.h
+++ b/include/linux/videodev2.h
@@ -334,6 +334,8 @@ struct v4l2_pix_format {
 #define V4L2_PIX_FMT_SPCA508  v4l2_fourcc('S', '5', '0', '8') /* YUVY per line */
 #define V4L2_PIX_FMT_SPCA561  v4l2_fourcc('S', '5', '6', '1') /* compressed GBRG bayer */
 #define V4L2_PIX_FMT_PAC207   v4l2_fourcc('P', '2', '0', '7') /* compressed BGGR bayer */
+#define V4L2_PIX_FMT_PJPG     v4l2_fourcc('P', 'J', 'P', 'G') /* Pixart 73xx JPEG */
+#define V4L2_PIX_FMT_YVYU    v4l2_fourcc('Y', 'V', 'Y', 'U') /* 16  YVU 4:2:2     */
 
 /*
  *      F O R M A T   E N U M E R A T I O N
@@ -908,6 +910,8 @@ enum v4l2_mpeg_audio_encoding {
         V4L2_MPEG_AUDIO_ENCODING_LAYER_1 = 0,
         V4L2_MPEG_AUDIO_ENCODING_LAYER_2 = 1,
         V4L2_MPEG_AUDIO_ENCODING_LAYER_3 = 2,
+        V4L2_MPEG_AUDIO_ENCODING_AAC     = 3,
+        V4L2_MPEG_AUDIO_ENCODING_AC3     = 4,
 };
 #define V4L2_CID_MPEG_AUDIO_L1_BITRATE          (V4L2_CID_MPEG_BASE+102)
 enum v4l2_mpeg_audio_l1_bitrate {
@@ -986,12 +990,36 @@ enum v4l2_mpeg_audio_crc {
         V4L2_MPEG_AUDIO_CRC_CRC16 = 1,
 };
 #define V4L2_CID_MPEG_AUDIO_MUTE                (V4L2_CID_MPEG_BASE+109)
+#define V4L2_CID_MPEG_AUDIO_AAC_BITRATE         (V4L2_CID_MPEG_BASE+110)
+#define V4L2_CID_MPEG_AUDIO_AC3_BITRATE         (V4L2_CID_MPEG_BASE+111)
+enum v4l2_mpeg_audio_ac3_bitrate {
+        V4L2_MPEG_AUDIO_AC3_BITRATE_32K  = 0,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_40K  = 1,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_48K  = 2,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_56K  = 3,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_64K  = 4,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_80K  = 5,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_96K  = 6,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_112K = 7,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_128K = 8,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_160K = 9,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_192K = 10,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_224K = 11,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_256K = 12,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_320K = 13,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_384K = 14,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_448K = 15,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_512K = 16,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_576K = 17,
+        V4L2_MPEG_AUDIO_AC3_BITRATE_640K = 18,
+};
 
 /*  MPEG video */
 #define V4L2_CID_MPEG_VIDEO_ENCODING            (V4L2_CID_MPEG_BASE+200)
 enum v4l2_mpeg_video_encoding {
-        V4L2_MPEG_VIDEO_ENCODING_MPEG_1 = 0,
-        V4L2_MPEG_VIDEO_ENCODING_MPEG_2 = 1,
+        V4L2_MPEG_VIDEO_ENCODING_MPEG_1     = 0,
+        V4L2_MPEG_VIDEO_ENCODING_MPEG_2     = 1,
+        V4L2_MPEG_VIDEO_ENCODING_MPEG_4_AVC = 2,
 };
 #define V4L2_CID_MPEG_VIDEO_ASPECT              (V4L2_CID_MPEG_BASE+201)
 enum v4l2_mpeg_video_aspect {
diff --git a/include/linux/vt_kern.h b/include/linux/vt_kern.h
index 1cbd0a7db4e6..2f1113467f70 100644
--- a/include/linux/vt_kern.h
+++ b/include/linux/vt_kern.h
@@ -96,7 +96,7 @@ void change_console(struct vc_data *new_vc);
 void reset_vc(struct vc_data *vc);
 extern int unbind_con_driver(const struct consw *csw, int first, int last,
                              int deflt);
-int vty_init(void);
+int vty_init(const struct file_operations *console_fops);
 
 /*
  * vc_screen.c shares this temporary buffer with the console write code so that
diff --git a/include/linux/wait.h b/include/linux/wait.h
index 0081147a9fe8..ef609f842fac 100644
--- a/include/linux/wait.h
+++ b/include/linux/wait.h
@@ -108,15 +108,6 @@ static inline int waitqueue_active(wait_queue_head_t *q)
         return !list_empty(&q->task_list);
 }
 
-/*
- * Used to distinguish between sync and async io wait context:
- * sync i/o typically specifies a NULL wait queue entry or a wait
- * queue entry bound to a task (current task) to wake up.
- * aio specifies a wait queue entry with an async notification
- * callback routine, not associated with any task.
- */
-#define is_sync_wait(wait)      (!(wait) || ((wait)->private))
-
 extern void add_wait_queue(wait_queue_head_t *q, wait_queue_t *wait);
 extern void add_wait_queue_exclusive(wait_queue_head_t *q, wait_queue_t *wait);
 extern void remove_wait_queue(wait_queue_head_t *q, wait_queue_t *wait);
diff --git a/include/linux/wm97xx_batt.h b/include/linux/wm97xx_batt.h
new file mode 100644
index 000000000000..9681d1ab0e4f
--- /dev/null
+++ b/include/linux/wm97xx_batt.h
@@ -0,0 +1,26 @@
+#ifndef _LINUX_WM97XX_BAT_H
+#define _LINUX_WM97XX_BAT_H
+
+#include <linux/wm97xx.h>
+
+struct wm97xx_batt_info {
+        int     batt_aux;
+        int     temp_aux;
+        int     charge_gpio;
+        int     min_voltage;
+        int     max_voltage;
+        int     batt_div;
+        int     batt_mult;
+        int     temp_div;
+        int     temp_mult;
+        int     batt_tech;
+        char    *batt_name;
+};
+
+#ifdef CONFIG_BATTERY_WM97XX
+void __init wm97xx_bat_set_pdata(struct wm97xx_batt_info *data);
+#else
+static inline void wm97xx_bat_set_pdata(struct wm97xx_batt_info *data) {}
+#endif
+
+#endif
diff --git a/include/linux/writeback.h b/include/linux/writeback.h
index 12b15c561a1f..e585657e9831 100644
--- a/include/linux/writeback.h
+++ b/include/linux/writeback.h
@@ -63,7 +63,15 @@ struct writeback_control {
         unsigned for_writepages:1;      /* This is a writepages() call */
         unsigned range_cyclic:1;        /* range_start is cyclic */
         unsigned more_io:1;             /* more io to be dispatched */
-        unsigned range_cont:1;
+        /*
+         * write_cache_pages() won't update wbc->nr_to_write and
+         * mapping->writeback_index if no_nrwrite_index_update
+         * is set.  write_cache_pages() may write more than we
+         * requested and we want to make sure nr_to_write and
+         * writeback_index are updated in a consistent manner
+         * so we use a single control to update them
+         */
+        unsigned no_nrwrite_index_update:1;
 };
 
 /*
diff --git a/include/linux/xfrm.h b/include/linux/xfrm.h
index fb0c215a3051..4bc1e6b86cb2 100644
--- a/include/linux/xfrm.h
+++ b/include/linux/xfrm.h
@@ -279,6 +279,7 @@ enum xfrm_attr_type_t {
         XFRMA_POLICY_TYPE,      /* struct xfrm_userpolicy_type */
         XFRMA_MIGRATE,
         XFRMA_ALG_AEAD,         /* struct xfrm_algo_aead */
+        XFRMA_KMADDRESS,        /* struct xfrm_user_kmaddress */
         __XFRMA_MAX
 
 #define XFRMA_MAX (__XFRMA_MAX - 1)
@@ -415,6 +416,15 @@ struct xfrm_user_report {
         struct xfrm_selector            sel;
 };
 
+/* Used by MIGRATE to pass addresses IKE should use to perform
+ * SA negotiation with the peer */
+struct xfrm_user_kmaddress {
+        xfrm_address_t                  local;
+        xfrm_address_t                  remote;
+        __u32                           reserved;
+        __u16                           family;
+};
+
 struct xfrm_user_migrate {
         xfrm_address_t                  old_daddr;
         xfrm_address_t                  old_saddr;
diff --git a/include/math-emu/op-2.h b/include/math-emu/op-2.h
index e193fb08fd55..4f26ecc1411b 100644
--- a/include/math-emu/op-2.h
+++ b/include/math-emu/op-2.h
@@ -25,7 +25,7 @@
 #ifndef __MATH_EMU_OP_2_H__
 #define __MATH_EMU_OP_2_H__
 
-#define _FP_FRAC_DECL_2(X)      _FP_W_TYPE X##_f0, X##_f1
+#define _FP_FRAC_DECL_2(X)      _FP_W_TYPE X##_f0 = 0, X##_f1 = 0
 #define _FP_FRAC_COPY_2(D,S)    (D##_f0 = S##_f0, D##_f1 = S##_f1)
 #define _FP_FRAC_SET_2(X,I)     __FP_FRAC_SET_2(X, I)
 #define _FP_FRAC_HIGH_2(X)      (X##_f1)
diff --git a/include/math-emu/op-common.h b/include/math-emu/op-common.h
index bb46e7645d53..cc1ec396f8d6 100644
--- a/include/math-emu/op-common.h
+++ b/include/math-emu/op-common.h
@@ -73,7 +73,7 @@ do {									\
         X##_c = FP_CLS_NAN;                                             \
         /* Check for signaling NaN */                                   \
         if (!(_FP_FRAC_HIGH_RAW_##fs(X) & _FP_QNANBIT_##fs))            \
-          FP_SET_EXCEPTION(FP_EX_INVALID);                              \
+          FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_SNAN);         \
       }                                                                 \
     break;                                                              \
   }                                                                     \
@@ -324,7 +324,7 @@ do {									     \
         _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);                              \
         R##_s = _FP_NANSIGN_##fs;                                            \
         R##_c = FP_CLS_NAN;                                                  \
-        FP_SET_EXCEPTION(FP_EX_INVALID);                                     \
+        FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_ISI);                 \
         break;                                                               \
       }                                                                      \
     /* FALLTHRU */                                                           \
@@ -431,7 +431,7 @@ do {							\
     R##_s = _FP_NANSIGN_##fs;                           \
     R##_c = FP_CLS_NAN;                                 \
     _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);             \
-    FP_SET_EXCEPTION(FP_EX_INVALID);                    \
+    FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_IMZ);\
     break;                                              \
                                                         \
   default:                                              \
@@ -490,11 +490,15 @@ do {							\
     break;                                              \
                                                         \
   case _FP_CLS_COMBINE(FP_CLS_INF,FP_CLS_INF):          \
+    R##_s = _FP_NANSIGN_##fs;                           \
+    R##_c = FP_CLS_NAN;                                 \
+    _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);             \
+    FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_IDI);\
   case _FP_CLS_COMBINE(FP_CLS_ZERO,FP_CLS_ZERO):        \
     R##_s = _FP_NANSIGN_##fs;                           \
     R##_c = FP_CLS_NAN;                                 \
     _FP_FRAC_SET_##wc(R, _FP_NANFRAC_##fs);             \
-    FP_SET_EXCEPTION(FP_EX_INVALID);                    \
+    FP_SET_EXCEPTION(FP_EX_INVALID | FP_EX_INVALID_ZDZ);\
     break;                                              \
                                                         \
   default:                                              \
diff --git a/include/math-emu/soft-fp.h b/include/math-emu/soft-fp.h
index a6f873b45f98..3f284bc03180 100644
--- a/include/math-emu/soft-fp.h
+++ b/include/math-emu/soft-fp.h
@@ -51,6 +51,25 @@
 #ifndef FP_EX_INVALID
 #define FP_EX_INVALID           0
 #endif
+#ifndef FP_EX_INVALID_SNAN
+#define FP_EX_INVALID_SNAN      0
+#endif
+/* inf - inf */
+#ifndef FP_EX_INVALID_ISI
+#define FP_EX_INVALID_ISI       0
+#endif
+/* inf / inf */
+#ifndef FP_EX_INVALID_IDI
+#define FP_EX_INVALID_IDI       0
+#endif
+/* 0 / 0 */
+#ifndef FP_EX_INVALID_ZDZ
+#define FP_EX_INVALID_ZDZ       0
+#endif
+/* inf * 0 */
+#ifndef FP_EX_INVALID_IMZ
+#define FP_EX_INVALID_IMZ       0
+#endif
 #ifndef FP_EX_OVERFLOW
 #define FP_EX_OVERFLOW          0
 #endif
diff --git a/include/media/ir-common.h b/include/media/ir-common.h
index b8e8aa91905a..38f2d93c3957 100644
--- a/include/media/ir-common.h
+++ b/include/media/ir-common.h
@@ -25,6 +25,7 @@
 
 #include <linux/input.h>
 #include <linux/workqueue.h>
+#include <linux/interrupt.h>
 
 #define IR_TYPE_RC5     1
 #define IR_TYPE_PD      2 /* Pulse distance encoded IR */
@@ -85,6 +86,10 @@ struct card_ir {
         u32 code;                       /* raw code under construction */
         struct timeval base_time;       /* time of last seen code */
         int active;                     /* building raw code */
+
+        /* NEC decoding */
+        u32                     nec_gpio;
+        struct tasklet_struct   tlet;
 };
 
 void ir_input_init(struct input_dev *dev, struct ir_input_state *ir,
@@ -105,6 +110,7 @@ void ir_rc5_timer_keyup(unsigned long data);
 extern IR_KEYTAB_TYPE ir_codes_empty[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_avermedia[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_avermedia_dvbt[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_avermedia_m135a[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_apac_viewcomp[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_pixelview[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_pixelview_new[IR_KEYTAB_SIZE];
@@ -139,6 +145,7 @@ extern IR_KEYTAB_TYPE ir_codes_proteus_2309[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_budget_ci_old[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_asus_pc39[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_encore_enltv[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_encore_enltv2[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_tt_1500[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_fusionhdtv_mce[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_behold[IR_KEYTAB_SIZE];
@@ -147,7 +154,9 @@ extern IR_KEYTAB_TYPE ir_codes_pinnacle_pctv_hd[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_genius_tvgo_a11mce[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_powercolor_real_angel[IR_KEYTAB_SIZE];
 extern IR_KEYTAB_TYPE ir_codes_avermedia_a16d[IR_KEYTAB_SIZE];
-
+extern IR_KEYTAB_TYPE ir_codes_encore_enltv_fm53[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_real_audio_220_32_keys[IR_KEYTAB_SIZE];
+extern IR_KEYTAB_TYPE ir_codes_msi_tvanywhere_plus[IR_KEYTAB_SIZE];
 #endif
 
 /*
diff --git a/include/media/saa7115.h b/include/media/saa7115.h
index f677dfb9d373..bab212719591 100644
--- a/include/media/saa7115.h
+++ b/include/media/saa7115.h
@@ -1,5 +1,5 @@
 /*
-    saa7115.h - definition for saa7113/4/5 inputs and frequency flags
+    saa7115.h - definition for saa7111/3/4/5 inputs and frequency flags
 
     Copyright (C) 2006 Hans Verkuil (hverkuil@xs4all.nl)
 
@@ -21,13 +21,13 @@
 #ifndef _SAA7115_H_
 #define _SAA7115_H_
 
-/* SAA7113/4/5 HW inputs */
+/* SAA7111/3/4/5 HW inputs */
 #define SAA7115_COMPOSITE0 0
 #define SAA7115_COMPOSITE1 1
 #define SAA7115_COMPOSITE2 2
 #define SAA7115_COMPOSITE3 3
-#define SAA7115_COMPOSITE4 4 /* not available for the saa7113 */
-#define SAA7115_COMPOSITE5 5 /* not available for the saa7113 */
+#define SAA7115_COMPOSITE4 4 /* not available for the saa7111/3 */
+#define SAA7115_COMPOSITE5 5 /* not available for the saa7111/3 */
 #define SAA7115_SVIDEO0    6
 #define SAA7115_SVIDEO1    7
 #define SAA7115_SVIDEO2    8
@@ -42,8 +42,15 @@
 #define SAA7115_FREQ_FL_CGCDIV (1 << 1)    /* SA 3A[6], CGCDIV, SAA7115 only */
 #define SAA7115_FREQ_FL_APLL   (1 << 2)    /* SA 3A[3], APLL, SAA7114/5 only */
 
-#define SAA7115_IPORT_ON    1
-#define SAA7115_IPORT_OFF   0
+#define SAA7115_IPORT_ON        1
+#define SAA7115_IPORT_OFF       0
+
+/* SAA7111 specific output flags */
+#define SAA7111_VBI_BYPASS      2
+#define SAA7111_FMT_YUV422      0x00
+#define SAA7111_FMT_RGB         0x40
+#define SAA7111_FMT_CCIR        0x80
+#define SAA7111_FMT_YUV411      0xc0
 
 #endif
 
diff --git a/include/media/saa7146.h b/include/media/saa7146.h
index 2f68f4cd0037..c5a6e22a4b37 100644
--- a/include/media/saa7146.h
+++ b/include/media/saa7146.h
@@ -24,13 +24,13 @@
 
 extern unsigned int saa7146_debug;
 
-//#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),KBUILD_MODNAME,__FUNCTION__)
+//#define DEBUG_PROLOG printk("(0x%08x)(0x%08x) %s: %s(): ",(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,RPS_ADDR0))),(dev==0?-1:(dev->mem==0?-1:saa7146_read(dev,IER))),KBUILD_MODNAME,__func__)
 
 #ifndef DEBUG_VARIABLE
         #define DEBUG_VARIABLE saa7146_debug
 #endif
 
-#define DEBUG_PROLOG printk("%s: %s(): ",KBUILD_MODNAME,__FUNCTION__)
+#define DEBUG_PROLOG printk("%s: %s(): ",KBUILD_MODNAME, __func__)
 #define INFO(x) { printk("%s: ",KBUILD_MODNAME); printk x; }
 
 #define ERR(x) { DEBUG_PROLOG; printk x; }
diff --git a/include/media/sh_mobile_ceu.h b/include/media/sh_mobile_ceu.h
index 234a4711d2ec..b5dbefea3740 100644
--- a/include/media/sh_mobile_ceu.h
+++ b/include/media/sh_mobile_ceu.h
@@ -5,8 +5,6 @@
 
 struct sh_mobile_ceu_info {
         unsigned long flags; /* SOCAM_... */
-        void (*enable_camera)(void);
-        void (*disable_camera)(void);
 };
 
 #endif /* __ASM_SH_MOBILE_CEU_H__ */
diff --git a/include/media/soc_camera.h b/include/media/soc_camera.h
index d548de326722..c5de7bb19fda 100644
--- a/include/media/soc_camera.h
+++ b/include/media/soc_camera.h
@@ -83,6 +83,9 @@ struct soc_camera_link {
         int bus_id;
         /* GPIO number to switch between 8 and 10 bit modes */
         unsigned int gpio;
+        /* Optional callbacks to power on or off and reset the sensor */
+        int (*power)(struct device *, int);
+        int (*reset)(struct device *);
 };
 
 static inline struct soc_camera_device *to_soc_camera_dev(struct device *dev)
diff --git a/include/media/soc_camera_platform.h b/include/media/soc_camera_platform.h
index 851f18220984..1d092b4678aa 100644
--- a/include/media/soc_camera_platform.h
+++ b/include/media/soc_camera_platform.h
@@ -1,3 +1,13 @@
+/*
+ * Generic Platform Camera Driver Header
+ *
+ * Copyright (C) 2008 Magnus Damm
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ */
+
 #ifndef __SOC_CAMERA_H__
 #define __SOC_CAMERA_H__
 
@@ -9,6 +19,7 @@ struct soc_camera_platform_info {
         unsigned long format_depth;
         struct v4l2_pix_format format;
         unsigned long bus_param;
+        void (*power)(int);
         int (*set_capture)(struct soc_camera_platform_info *info, int enable);
 };
 
diff --git a/include/media/tuner.h b/include/media/tuner.h
index 77068fcc86bd..7d4e2db78076 100644
--- a/include/media/tuner.h
+++ b/include/media/tuner.h
@@ -122,6 +122,8 @@
 #define TUNER_TDA9887                   74      /* This tuner should be used only internally */
 #define TUNER_TEA5761                   75      /* Only FM Radio Tuner */
 #define TUNER_XC5000                    76      /* Xceive Silicon Tuner */
+#define TUNER_TCL_MF02GIP_5N            77      /* TCL MF02GIP_5N */
+#define TUNER_PHILIPS_FMD1216MEX_MK3    78
 
 /* tv card specific */
 #define TDA9887_PRESENT                 (1<<0)
@@ -178,7 +180,7 @@ struct tuner_setup {
         unsigned int    type;   /* Tuner type */
         unsigned int    mode_mask;  /* Allowed tuner modes */
         unsigned int    config; /* configuraion for more complex tuners */
-        int (*tuner_callback) (void *dev, int command,int arg);
+        int (*tuner_callback) (void *dev, int component, int cmd, int arg);
 };
 
 #endif /* __KERNEL__ */
diff --git a/include/media/v4l2-chip-ident.h b/include/media/v4l2-chip-ident.h
index 41b509babf3f..d73a8e9028a5 100644
--- a/include/media/v4l2-chip-ident.h
+++ b/include/media/v4l2-chip-ident.h
@@ -72,6 +72,10 @@ enum {
         /* module cs5345: just ident 5345 */
         V4L2_IDENT_CS5345 = 5345,
 
+        /* module saa6752hs: reserved range 6750-6759 */
+        V4L2_IDENT_SAA6752HS = 6752,
+        V4L2_IDENT_SAA6752HS_AC3 = 6753,
+
         /* module wm8739: just ident 8739 */
         V4L2_IDENT_WM8739 = 8739,
 
@@ -161,6 +165,7 @@ enum {
         /* Micron CMOS sensor chips: 45000-45099 */
         V4L2_IDENT_MT9M001C12ST         = 45000,
         V4L2_IDENT_MT9M001C12STM        = 45005,
+        V4L2_IDENT_MT9M111              = 45007,
         V4L2_IDENT_MT9V022IX7ATC        = 45010, /* No way to detect "normal" I77ATx */
         V4L2_IDENT_MT9V022IX7ATM        = 45015, /* and "lead free" IA7ATx chips */
 };
diff --git a/include/media/v4l2-common.h b/include/media/v4l2-common.h
index 07d3a9a575d1..2f8719abf5cb 100644
--- a/include/media/v4l2-common.h
+++ b/include/media/v4l2-common.h
@@ -76,11 +76,14 @@ int v4l2_prio_check(struct v4l2_prio_state *global, enum v4l2_priority *local);
 
 int v4l2_ctrl_check(struct v4l2_ext_control *ctrl, struct v4l2_queryctrl *qctrl,
                 const char **menu_items);
+const char *v4l2_ctrl_get_name(u32 id);
 const char **v4l2_ctrl_get_menu(u32 id);
 int v4l2_ctrl_query_fill(struct v4l2_queryctrl *qctrl, s32 min, s32 max, s32 step, s32 def);
 int v4l2_ctrl_query_fill_std(struct v4l2_queryctrl *qctrl);
 int v4l2_ctrl_query_menu(struct v4l2_querymenu *qmenu,
                 struct v4l2_queryctrl *qctrl, const char **menu_items);
+#define V4L2_CTRL_MENU_IDS_END (0xffffffff)
+int v4l2_ctrl_query_menu_valid_items(struct v4l2_querymenu *qmenu, const u32 *ids);
 u32 v4l2_ctrl_next(const u32 * const *ctrl_classes, u32 id);
 
 /* ------------------------------------------------------------------------- */
@@ -222,18 +225,22 @@ struct v4l2_crystal_freq {
    An extra flags field allows device specific configuration regarding
    clock frequency dividers, etc. If not used, then set flags to 0.
    If the frequency is not supported, then -EINVAL is returned. */
-#define VIDIOC_INT_S_CRYSTAL_FREQ       _IOW ('d', 113, struct v4l2_crystal_freq)
+#define VIDIOC_INT_S_CRYSTAL_FREQ       _IOW('d', 113, struct v4l2_crystal_freq)
 
 /* Initialize the sensor registors to some sort of reasonable
    default values. */
-#define VIDIOC_INT_INIT                 _IOW ('d', 114, u32)
+#define VIDIOC_INT_INIT                 _IOW('d', 114, u32)
 
 /* Set v4l2_std_id for video OUTPUT devices. This is ignored by
    video input devices. */
-#define VIDIOC_INT_S_STD_OUTPUT         _IOW  ('d', 115, v4l2_std_id)
+#define VIDIOC_INT_S_STD_OUTPUT         _IOW('d', 115, v4l2_std_id)
 
 /* Get v4l2_std_id for video OUTPUT devices. This is ignored by
    video input devices. */
-#define VIDIOC_INT_G_STD_OUTPUT         _IOW  ('d', 116, v4l2_std_id)
+#define VIDIOC_INT_G_STD_OUTPUT         _IOW('d', 116, v4l2_std_id)
+
+/* Set GPIO pins. Very simple right now, might need to be extended with
+   a v4l2_gpio struct if a direction is also needed. */
+#define VIDIOC_INT_S_GPIO               _IOW('d', 117, u32)
 
 #endif /* V4L2_COMMON_H_ */
diff --git a/include/media/v4l2-dev.h b/include/media/v4l2-dev.h
index 2745e1afc722..a0a6b41c5e09 100644
--- a/include/media/v4l2-dev.h
+++ b/include/media/v4l2-dev.h
@@ -9,30 +9,20 @@
 #ifndef _V4L2_DEV_H
 #define _V4L2_DEV_H
 
-#define OBSOLETE_DEVDATA 1 /* to be removed soon */
-
 #include <linux/poll.h>
 #include <linux/fs.h>
 #include <linux/device.h>
+#include <linux/cdev.h>
 #include <linux/mutex.h>
-#include <linux/compiler.h> /* need __user */
 #include <linux/videodev2.h>
 
 #define VIDEO_MAJOR     81
-/* Minor device allocation */
-#define MINOR_VFL_TYPE_GRABBER_MIN   0
-#define MINOR_VFL_TYPE_GRABBER_MAX  63
-#define MINOR_VFL_TYPE_RADIO_MIN    64
-#define MINOR_VFL_TYPE_RADIO_MAX   127
-#define MINOR_VFL_TYPE_VTX_MIN     192
-#define MINOR_VFL_TYPE_VTX_MAX     223
-#define MINOR_VFL_TYPE_VBI_MIN     224
-#define MINOR_VFL_TYPE_VBI_MAX     255
 
 #define VFL_TYPE_GRABBER        0
 #define VFL_TYPE_VBI            1
 #define VFL_TYPE_RADIO          2
 #define VFL_TYPE_VTX            3
+#define VFL_TYPE_MAX            4
 
 struct v4l2_ioctl_callbacks;
 
@@ -49,12 +39,15 @@ struct video_device
 
         /* sysfs */
         struct device dev;              /* v4l device */
+        struct cdev cdev;               /* character device */
+        void (*cdev_release)(struct kobject *kobj);
         struct device *parent;          /* device parent */
 
         /* device info */
         char name[32];
         int vfl_type;
         int minor;
+        u16 num;
         /* attribute to differentiate multiple indices on one physical device */
         int index;
 
@@ -69,50 +62,50 @@ struct video_device
 
         /* ioctl callbacks */
         const struct v4l2_ioctl_ops *ioctl_ops;
-
-#ifdef OBSOLETE_DEVDATA /* to be removed soon */
-        /* dev->driver_data will be used instead some day.
-         * Use the video_{get|set}_drvdata() helper functions,
-         * so the switch over will be transparent for you.
-         * Or use {pci|usb}_{get|set}_drvdata() directly. */
-        void *priv;
-#endif
-
-        /* for videodev.c internal usage -- please don't touch */
-        int users;                     /* video_exclusive_{open|close} ... */
-        struct mutex lock;             /* ... helper function uses these   */
 };
 
-/* Class-dev to video-device */
+/* dev to video-device */
 #define to_video_device(cd) container_of(cd, struct video_device, dev)
 
-/* Version 2 functions */
-extern int video_register_device(struct video_device *vfd, int type, int nr);
-int video_register_device_index(struct video_device *vfd, int type, int nr,
-                                        int index);
-void video_unregister_device(struct video_device *);
+/* Register and unregister devices. Note that if video_register_device fails,
+   the release() callback of the video_device structure is *not* called, so
+   the caller is responsible for freeing any data. Usually that means that
+   you call video_device_release() on failure. */
+int __must_check video_register_device(struct video_device *vfd, int type, int nr);
+int __must_check video_register_device_index(struct video_device *vfd,
+                                                int type, int nr, int index);
+void video_unregister_device(struct video_device *vfd);
 
-/* helper functions to alloc / release struct video_device, the
-   later can be used for video_device->release() */
-struct video_device *video_device_alloc(void);
+/* helper functions to alloc/release struct video_device, the
+   latter can also be used for video_device->release(). */
+struct video_device * __must_check video_device_alloc(void);
+
+/* this release function frees the vfd pointer */
 void video_device_release(struct video_device *vfd);
 
-#ifdef OBSOLETE_DEVDATA /* to be removed soon */
+/* this release function does nothing, use when the video_device is a
+   static global struct. Note that having a static video_device is
+   a dubious construction at best. */
+void video_device_release_empty(struct video_device *vfd);
+
 /* helper functions to access driver private data. */
 static inline void *video_get_drvdata(struct video_device *dev)
 {
-        return dev->priv;
+        return dev_get_drvdata(&dev->dev);
 }
 
 static inline void video_set_drvdata(struct video_device *dev, void *data)
 {
-        dev->priv = data;
+        dev_set_drvdata(&dev->dev, data);
 }
 
-/* Obsolete stuff - Still needed for radio devices and obsolete drivers */
-extern struct video_device* video_devdata(struct file*);
-extern int video_exclusive_open(struct inode *inode, struct file *file);
-extern int video_exclusive_release(struct inode *inode, struct file *file);
-#endif
+struct video_device *video_devdata(struct file *file);
+
+/* Combine video_get_drvdata and video_devdata as this is
+   used very often. */
+static inline void *video_drvdata(struct file *file)
+{
+        return video_get_drvdata(video_devdata(file));
+}
 
 #endif /* _V4L2_DEV_H */
diff --git a/include/media/v4l2-i2c-drv-legacy.h b/include/media/v4l2-i2c-drv-legacy.h
index 975ffbf4e2c5..e65dd9d84e8b 100644
--- a/include/media/v4l2-i2c-drv-legacy.h
+++ b/include/media/v4l2-i2c-drv-legacy.h
@@ -21,6 +21,17 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+/* NOTE: the full version of this header is in the v4l-dvb repository
+ * and allows v4l i2c drivers to be compiled on older kernels as well.
+ * The version of this header as it appears in the kernel is a stripped
+ * version (without all the backwards compatibility stuff) and so it
+ * looks a bit odd.
+ *
+ * If you look at the full version then you will understand the reason
+ * for introducing this header since you really don't want to have all
+ * the tricky backwards compatibility code in each and every i2c driver.
+ */
+
 struct v4l2_i2c_driver_data {
         const char * const name;
         int driverid;
diff --git a/include/media/v4l2-i2c-drv.h b/include/media/v4l2-i2c-drv.h
index 40ecef29801d..efdc8bf27f87 100644
--- a/include/media/v4l2-i2c-drv.h
+++ b/include/media/v4l2-i2c-drv.h
@@ -21,6 +21,17 @@
  * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  */
 
+/* NOTE: the full version of this header is in the v4l-dvb repository
+ * and allows v4l i2c drivers to be compiled on older kernels as well.
+ * The version of this header as it appears in the kernel is a stripped
+ * version (without all the backwards compatibility stuff) and so it
+ * looks a bit odd.
+ *
+ * If you look at the full version then you will understand the reason
+ * for introducing this header since you really don't want to have all
+ * the tricky backwards compatibility code in each and every i2c driver.
+ */
+
 #ifndef __V4L2_I2C_DRV_H__
 #define __V4L2_I2C_DRV_H__
 
diff --git a/include/media/v4l2-ioctl.h b/include/media/v4l2-ioctl.h
index dc6404618555..0bef03add796 100644
--- a/include/media/v4l2-ioctl.h
+++ b/include/media/v4l2-ioctl.h
@@ -39,11 +39,6 @@ struct v4l2_ioctl_ops {
                                             struct v4l2_fmtdesc *f);
         int (*vidioc_enum_fmt_vid_out)     (struct file *file, void *fh,
                                             struct v4l2_fmtdesc *f);
-#if 1
-        /* deprecated, will be removed in 2.6.28 */
-        int (*vidioc_enum_fmt_vbi_cap)     (struct file *file, void *fh,
-                                            struct v4l2_fmtdesc *f);
-#endif
         int (*vidioc_enum_fmt_type_private)(struct file *file, void *fh,
                                             struct v4l2_fmtdesc *f);
 
diff --git a/include/media/videobuf-dvb.h b/include/media/videobuf-dvb.h
index b77748696329..80471c2b6343 100644
--- a/include/media/videobuf-dvb.h
+++ b/include/media/videobuf-dvb.h
@@ -16,7 +16,6 @@ struct videobuf_dvb {
         int                        nfeeds;
 
         /* videobuf_dvb_(un)register manges this */
-        struct dvb_adapter         adapter;
         struct dvb_demux           demux;
         struct dmxdev              dmxdev;
         struct dmx_frontend        fe_hw;
@@ -24,12 +23,34 @@ struct videobuf_dvb {
         struct dvb_net             net;
 };
 
-int videobuf_dvb_register(struct videobuf_dvb *dvb,
+struct videobuf_dvb_frontend {
+        struct list_head felist;
+        int id;
+        struct videobuf_dvb dvb;
+};
+
+struct videobuf_dvb_frontends {
+        struct list_head felist;
+        struct mutex lock;
+        struct dvb_adapter adapter;
+        int active_fe_id; /* Indicates which frontend in the felist is in use */
+        int gate; /* Frontend with gate control 0=!MFE,1=fe0,2=fe1 etc */
+};
+
+int videobuf_dvb_register_bus(struct videobuf_dvb_frontends *f,
                           struct module *module,
                           void *adapter_priv,
                           struct device *device,
-                          short *adapter_nr);
-void videobuf_dvb_unregister(struct videobuf_dvb *dvb);
+                          short *adapter_nr,
+                          int mfe_shared);
+
+void videobuf_dvb_unregister_bus(struct videobuf_dvb_frontends *f);
+
+struct videobuf_dvb_frontend * videobuf_dvb_alloc_frontend(struct videobuf_dvb_frontends *f, int id);
+
+struct videobuf_dvb_frontend * videobuf_dvb_get_frontend(struct videobuf_dvb_frontends *f, int id);
+int videobuf_dvb_find_frontend(struct videobuf_dvb_frontends *f, struct dvb_frontend *p);
+
 
 /*
  * Local variables:
diff --git a/include/net/9p/9p.h b/include/net/9p/9p.h
index b3d3e27c6299..fb163e2e0de6 100644
--- a/include/net/9p/9p.h
+++ b/include/net/9p/9p.h
@@ -61,7 +61,7 @@ extern unsigned int p9_debug_level;
 do {  \
         if ((p9_debug_level & level) == level) \
                 printk(KERN_NOTICE "-- %s (%d): " \
-                format , __FUNCTION__, task_pid_nr(current) , ## arg); \
+                format , __func__, task_pid_nr(current) , ## arg); \
 } while (0)
 
 #define PRINT_FCALL_ERROR(s, fcall) P9_DPRINTK(P9_DEBUG_ERROR,   \
@@ -76,7 +76,7 @@ do {  \
 #define P9_EPRINTK(level, format, arg...) \
 do { \
         printk(level "9p: %s (%d): " \
-                format , __FUNCTION__, task_pid_nr(current), ## arg); \
+                format , __func__, task_pid_nr(current), ## arg); \
 } while (0)
 
 /**
@@ -596,4 +596,5 @@ int p9_idpool_check(int id, struct p9_idpool *p);
 int p9_error_init(void);
 int p9_errstr2errno(char *, int);
 int p9_trans_fd_init(void);
+void p9_trans_fd_exit(void);
 #endif /* NET_9P_H */
diff --git a/include/net/9p/transport.h b/include/net/9p/transport.h
index 0db3a4038dc0..3ca737120a90 100644
--- a/include/net/9p/transport.h
+++ b/include/net/9p/transport.h
@@ -26,6 +26,8 @@
 #ifndef NET_9P_TRANSPORT_H
 #define NET_9P_TRANSPORT_H
 
+#include <linux/module.h>
+
 /**
  * enum p9_trans_status - different states of underlying transports
  * @Connected: transport is connected and healthy
@@ -91,9 +93,12 @@ struct p9_trans_module {
         int maxsize;            /* max message size of transport */
         int def;                /* this transport should be default */
         struct p9_trans * (*create)(const char *, char *, int, unsigned char);
+        struct module *owner;
 };
 
 void v9fs_register_trans(struct p9_trans_module *m);
-struct p9_trans_module *v9fs_match_trans(const substring_t *name);
-struct p9_trans_module *v9fs_default_trans(void);
+void v9fs_unregister_trans(struct p9_trans_module *m);
+struct p9_trans_module *v9fs_get_trans_by_name(const substring_t *name);
+struct p9_trans_module *v9fs_get_default_trans(void);
+void v9fs_put_trans(struct p9_trans_module *m);
 #endif /* NET_9P_TRANSPORT_H */
diff --git a/include/net/bluetooth/bluetooth.h b/include/net/bluetooth/bluetooth.h
index 6f8418bf4241..996d12df7594 100644
--- a/include/net/bluetooth/bluetooth.h
+++ b/include/net/bluetooth/bluetooth.h
@@ -54,8 +54,8 @@
 #define SOL_RFCOMM      18
 
 #define BT_INFO(fmt, arg...) printk(KERN_INFO "Bluetooth: " fmt "\n" , ## arg)
-#define BT_DBG(fmt, arg...)  printk(KERN_INFO "%s: " fmt "\n" , __FUNCTION__ , ## arg)
-#define BT_ERR(fmt, arg...)  printk(KERN_ERR  "%s: " fmt "\n" , __FUNCTION__ , ## arg)
+#define BT_DBG(fmt, arg...)  printk(KERN_INFO "%s: " fmt "\n" , __func__ , ## arg)
+#define BT_ERR(fmt, arg...)  printk(KERN_ERR  "%s: " fmt "\n" , __func__ , ## arg)
 
 /* Connection and socket states */
 enum {
diff --git a/include/net/bluetooth/hci_core.h b/include/net/bluetooth/hci_core.h
index cbf751094688..46a43b721dd6 100644
--- a/include/net/bluetooth/hci_core.h
+++ b/include/net/bluetooth/hci_core.h
@@ -325,7 +325,8 @@ int hci_conn_del(struct hci_conn *conn);
 void hci_conn_hash_flush(struct hci_dev *hdev);
 void hci_conn_check_pending(struct hci_dev *hdev);
 
-struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *src);
+struct hci_conn *hci_connect(struct hci_dev *hdev, int type, bdaddr_t *dst, __u8 auth_type);
+int hci_conn_check_link_mode(struct hci_conn *conn);
 int hci_conn_auth(struct hci_conn *conn);
 int hci_conn_encrypt(struct hci_conn *conn);
 int hci_conn_change_link_key(struct hci_conn *conn);
diff --git a/include/net/cfg80211.h b/include/net/cfg80211.h
index e00750836ba5..0e85ec39b638 100644
--- a/include/net/cfg80211.h
+++ b/include/net/cfg80211.h
@@ -152,6 +152,7 @@ struct station_parameters {
         u16 aid;
         u8 supported_rates_len;
         u8 plink_action;
+        struct ieee80211_ht_cap *ht_capa;
 };
 
 /**
@@ -268,6 +269,83 @@ struct mpath_info {
         u8 flags;
 };
 
+/**
+ * struct bss_parameters - BSS parameters
+ *
+ * Used to change BSS parameters (mainly for AP mode).
+ *
+ * @use_cts_prot: Whether to use CTS protection
+ *      (0 = no, 1 = yes, -1 = do not change)
+ * @use_short_preamble: Whether the use of short preambles is allowed
+ *      (0 = no, 1 = yes, -1 = do not change)
+ * @use_short_slot_time: Whether the use of short slot time is allowed
+ *      (0 = no, 1 = yes, -1 = do not change)
+ */
+struct bss_parameters {
+        int use_cts_prot;
+        int use_short_preamble;
+        int use_short_slot_time;
+};
+
+/**
+ * enum reg_set_by - Indicates who is trying to set the regulatory domain
+ * @REGDOM_SET_BY_INIT: regulatory domain was set by initialization. We will be
+ *      using a static world regulatory domain by default.
+ * @REGDOM_SET_BY_CORE: Core queried CRDA for a dynamic world regulatory domain.
+ * @REGDOM_SET_BY_USER: User asked the wireless core to set the
+ *      regulatory domain.
+ * @REGDOM_SET_BY_DRIVER: a wireless drivers has hinted to the wireless core
+ *      it thinks its knows the regulatory domain we should be in.
+ * @REGDOM_SET_BY_COUNTRY_IE: the wireless core has received an 802.11 country
+ *      information element with regulatory information it thinks we
+ *      should consider.
+ */
+enum reg_set_by {
+        REGDOM_SET_BY_INIT,
+        REGDOM_SET_BY_CORE,
+        REGDOM_SET_BY_USER,
+        REGDOM_SET_BY_DRIVER,
+        REGDOM_SET_BY_COUNTRY_IE,
+};
+
+struct ieee80211_freq_range {
+        u32 start_freq_khz;
+        u32 end_freq_khz;
+        u32 max_bandwidth_khz;
+};
+
+struct ieee80211_power_rule {
+        u32 max_antenna_gain;
+        u32 max_eirp;
+};
+
+struct ieee80211_reg_rule {
+        struct ieee80211_freq_range freq_range;
+        struct ieee80211_power_rule power_rule;
+        u32 flags;
+};
+
+struct ieee80211_regdomain {
+        u32 n_reg_rules;
+        char alpha2[2];
+        struct ieee80211_reg_rule reg_rules[];
+};
+
+#define MHZ_TO_KHZ(freq) (freq * 1000)
+#define KHZ_TO_MHZ(freq) (freq / 1000)
+#define DBI_TO_MBI(gain) (gain * 100)
+#define MBI_TO_DBI(gain) (gain / 100)
+#define DBM_TO_MBM(gain) (gain * 100)
+#define MBM_TO_DBM(gain) (gain / 100)
+
+#define REG_RULE(start, end, bw, gain, eirp, reg_flags) { \
+        .freq_range.start_freq_khz = (start) * 1000, \
+        .freq_range.end_freq_khz = (end) * 1000, \
+        .freq_range.max_bandwidth_khz = (bw) * 1000, \
+        .power_rule.max_antenna_gain = (gain) * 100, \
+        .power_rule.max_eirp = (eirp) * 100, \
+        .flags = reg_flags, \
+        }
 
 /* from net/wireless.h */
 struct wiphy;
@@ -285,11 +363,13 @@ struct wiphy;
  * wireless extensions but this is subject to reevaluation as soon as this
  * code is used more widely and we have a first user without wext.
  *
- * @add_virtual_intf: create a new virtual interface with the given name
+ * @add_virtual_intf: create a new virtual interface with the given name,
+ *      must set the struct wireless_dev's iftype.
  *
  * @del_virtual_intf: remove the virtual interface determined by ifindex.
  *
- * @change_virtual_intf: change type of virtual interface
+ * @change_virtual_intf: change type/configuration of virtual interface,
+ *      keep the struct wireless_dev's iftype updated.
  *
  * @add_key: add a key with the given parameters. @mac_addr will be %NULL
  *      when adding a group key.
@@ -318,6 +398,8 @@ struct wiphy;
  * @change_station: Modify a given station.
  *
  * @set_mesh_cfg: set mesh parameters (by now, just mesh id)
+ *
+ * @change_bss: Modify parameters for a given BSS.
  */
 struct cfg80211_ops {
         int     (*add_virtual_intf)(struct wiphy *wiphy, char *name,
@@ -370,6 +452,9 @@ struct cfg80211_ops {
         int     (*dump_mpath)(struct wiphy *wiphy, struct net_device *dev,
                                int idx, u8 *dst, u8 *next_hop,
                                struct mpath_info *pinfo);
+
+        int     (*change_bss)(struct wiphy *wiphy, struct net_device *dev,
+                              struct bss_parameters *params);
 };
 
 #endif /* __NET_CFG80211_H */
diff --git a/include/net/cipso_ipv4.h b/include/net/cipso_ipv4.h
index a6bb94530cfd..9909774eb998 100644
--- a/include/net/cipso_ipv4.h
+++ b/include/net/cipso_ipv4.h
@@ -40,11 +40,12 @@
 #include <linux/net.h>
 #include <linux/skbuff.h>
 #include <net/netlabel.h>
+#include <asm/atomic.h>
 
 /* known doi values */
 #define CIPSO_V4_DOI_UNKNOWN          0x00000000
 
-/* tag types */
+/* standard tag types */
 #define CIPSO_V4_TAG_INVALID          0
 #define CIPSO_V4_TAG_RBITMAP          1
 #define CIPSO_V4_TAG_ENUM             2
@@ -52,10 +53,14 @@
 #define CIPSO_V4_TAG_PBITMAP          6
 #define CIPSO_V4_TAG_FREEFORM         7
 
+/* non-standard tag types (tags > 127) */
+#define CIPSO_V4_TAG_LOCAL            128
+
 /* doi mapping types */
 #define CIPSO_V4_MAP_UNKNOWN          0
-#define CIPSO_V4_MAP_STD              1
+#define CIPSO_V4_MAP_TRANS            1
 #define CIPSO_V4_MAP_PASS             2
+#define CIPSO_V4_MAP_LOCAL            3
 
 /* limits */
 #define CIPSO_V4_MAX_REM_LVLS         255
@@ -79,10 +84,9 @@ struct cipso_v4_doi {
         } map;
         u8 tags[CIPSO_V4_TAG_MAXCNT];
 
-        u32 valid;
+        atomic_t refcount;
         struct list_head list;
         struct rcu_head rcu;
-        struct list_head dom_list;
 };
 
 /* Standard CIPSO mapping table */
@@ -128,25 +132,26 @@ extern int cipso_v4_rbm_strictvalid;
 
 #ifdef CONFIG_NETLABEL
 int cipso_v4_doi_add(struct cipso_v4_doi *doi_def);
-int cipso_v4_doi_remove(u32 doi,
-                        struct netlbl_audit *audit_info,
-                        void (*callback) (struct rcu_head * head));
+void cipso_v4_doi_free(struct cipso_v4_doi *doi_def);
+int cipso_v4_doi_remove(u32 doi, struct netlbl_audit *audit_info);
 struct cipso_v4_doi *cipso_v4_doi_getdef(u32 doi);
+void cipso_v4_doi_putdef(struct cipso_v4_doi *doi_def);
 int cipso_v4_doi_walk(u32 *skip_cnt,
                      int (*callback) (struct cipso_v4_doi *doi_def, void *arg),
                      void *cb_arg);
-int cipso_v4_doi_domhsh_add(struct cipso_v4_doi *doi_def, const char *domain);
-int cipso_v4_doi_domhsh_remove(struct cipso_v4_doi *doi_def,
-                               const char *domain);
 #else
 static inline int cipso_v4_doi_add(struct cipso_v4_doi *doi_def)
 {
         return -ENOSYS;
 }
 
+static inline void cipso_v4_doi_free(struct cipso_v4_doi *doi_def)
+{
+        return;
+}
+
 static inline int cipso_v4_doi_remove(u32 doi,
-                                    struct netlbl_audit *audit_info,
-                                    void (*callback) (struct rcu_head * head))
+                                      struct netlbl_audit *audit_info)
 {
         return 0;
 }
@@ -206,10 +211,15 @@ void cipso_v4_error(struct sk_buff *skb, int error, u32 gateway);
 int cipso_v4_sock_setattr(struct sock *sk,
                           const struct cipso_v4_doi *doi_def,
                           const struct netlbl_lsm_secattr *secattr);
+void cipso_v4_sock_delattr(struct sock *sk);
 int cipso_v4_sock_getattr(struct sock *sk, struct netlbl_lsm_secattr *secattr);
+int cipso_v4_skbuff_setattr(struct sk_buff *skb,
+                            const struct cipso_v4_doi *doi_def,
+                            const struct netlbl_lsm_secattr *secattr);
+int cipso_v4_skbuff_delattr(struct sk_buff *skb);
 int cipso_v4_skbuff_getattr(const struct sk_buff *skb,
                             struct netlbl_lsm_secattr *secattr);
-int cipso_v4_validate(unsigned char **option);
+int cipso_v4_validate(const struct sk_buff *skb, unsigned char **option);
 #else
 static inline void cipso_v4_error(struct sk_buff *skb,
                                   int error,
@@ -225,19 +235,36 @@ static inline int cipso_v4_sock_setattr(struct sock *sk,
         return -ENOSYS;
 }
 
+static inline void cipso_v4_sock_delattr(struct sock *sk)
+{
+}
+
 static inline int cipso_v4_sock_getattr(struct sock *sk,
                                         struct netlbl_lsm_secattr *secattr)
 {
         return -ENOSYS;
 }
 
+static inline int cipso_v4_skbuff_setattr(struct sk_buff *skb,
+                                      const struct cipso_v4_doi *doi_def,
+                                      const struct netlbl_lsm_secattr *secattr)
+{
+        return -ENOSYS;
+}
+
+static inline int cipso_v4_skbuff_delattr(struct sk_buff *skb)
+{
+        return -ENOSYS;
+}
+
 static inline int cipso_v4_skbuff_getattr(const struct sk_buff *skb,
                                           struct netlbl_lsm_secattr *secattr)
 {
         return -ENOSYS;
 }
 
-static inline int cipso_v4_validate(unsigned char **option)
+static inline int cipso_v4_validate(const struct sk_buff *skb,
+                                    unsigned char **option)
 {
         return -ENOSYS;
 }
diff --git a/include/net/dsa.h b/include/net/dsa.h
new file mode 100644
index 000000000000..52e97bfca5a1
--- /dev/null
+++ b/include/net/dsa.h
@@ -0,0 +1,37 @@
+/*
+ * include/net/dsa.h - Driver for Distributed Switch Architecture switch chips
+ * Copyright (c) 2008 Marvell Semiconductor
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef __LINUX_NET_DSA_H
+#define __LINUX_NET_DSA_H
+
+#define DSA_MAX_PORTS   12
+
+struct dsa_platform_data {
+        /*
+         * Reference to a Linux network interface that connects
+         * to the switch chip.
+         */
+        struct device   *netdev;
+
+        /*
+         * How to access the switch configuration registers, and
+         * the names of the switch ports (use "cpu" to designate
+         * the switch port that the cpu is connected to).
+         */
+        struct device   *mii_bus;
+        int             sw_addr;
+        char            *port_names[DSA_MAX_PORTS];
+};
+
+extern bool dsa_uses_dsa_tags(void *dsa_ptr);
+extern bool dsa_uses_trailer_tags(void *dsa_ptr);
+
+
+#endif
diff --git a/include/net/flow.h b/include/net/flow.h
index 228b2477ceec..b45a5e4fcadd 100644
--- a/include/net/flow.h
+++ b/include/net/flow.h
@@ -47,6 +47,8 @@ struct flowi {
 #define fl4_scope       nl_u.ip4_u.scope
 
         __u8    proto;
+        __u8    flags;
+#define FLOWI_FLAG_ANYSRC 0x01
         union {
                 struct {
                         __be16  sport;
diff --git a/include/net/ieee80211.h b/include/net/ieee80211.h
index b31399e1fd83..93a56de3594b 100644
--- a/include/net/ieee80211.h
+++ b/include/net/ieee80211.h
@@ -114,7 +114,7 @@ extern u32 ieee80211_debug_level;
 #define IEEE80211_DEBUG(level, fmt, args...) \
 do { if (ieee80211_debug_level & (level)) \
   printk(KERN_DEBUG "ieee80211: %c %s " fmt, \
-         in_interrupt() ? 'I' : 'U', __FUNCTION__ , ## args); } while (0)
+         in_interrupt() ? 'I' : 'U', __func__ , ## args); } while (0)
 static inline bool ieee80211_ratelimit_debug(u32 level)
 {
         return (ieee80211_debug_level & level) && net_ratelimit();
@@ -190,10 +190,6 @@ const char *escape_essid(const char *essid, u8 essid_len);
 #endif
 #include <net/iw_handler.h>     /* new driver API */
 
-#ifndef ETH_P_PAE
-#define ETH_P_PAE 0x888E        /* Port Access Entity (IEEE 802.1X) */
-#endif                          /* ETH_P_PAE */
-
 #define ETH_P_PREAUTH 0x88C7    /* IEEE 802.11i pre-authentication */
 
 #ifndef ETH_P_80211_RAW
diff --git a/include/net/inet6_hashtables.h b/include/net/inet6_hashtables.h
index e48989f04c24..f74665d7bea8 100644
--- a/include/net/inet6_hashtables.h
+++ b/include/net/inet6_hashtables.h
@@ -91,6 +91,21 @@ static inline struct sock *__inet6_lookup(struct net *net,
         return inet6_lookup_listener(net, hashinfo, daddr, hnum, dif);
 }
 
+static inline struct sock *__inet6_lookup_skb(struct inet_hashinfo *hashinfo,
+                                              struct sk_buff *skb,
+                                              const __be16 sport,
+                                              const __be16 dport)
+{
+        struct sock *sk;
+
+        if (unlikely(sk = skb_steal_sock(skb)))
+                return sk;
+        else return __inet6_lookup(dev_net(skb->dst->dev), hashinfo,
+                                   &ipv6_hdr(skb)->saddr, sport,
+                                   &ipv6_hdr(skb)->daddr, ntohs(dport),
+                                   inet6_iif(skb));
+}
+
 extern struct sock *inet6_lookup(struct net *net, struct inet_hashinfo *hashinfo,
                                  const struct in6_addr *saddr, const __be16 sport,
                                  const struct in6_addr *daddr, const __be16 dport,
diff --git a/include/net/inet_connection_sock.h b/include/net/inet_connection_sock.h
index 2ff545a56fb5..03cffd9f64e3 100644
--- a/include/net/inet_connection_sock.h
+++ b/include/net/inet_connection_sock.h
@@ -51,12 +51,14 @@ struct inet_connection_sock_af_ops {
                                   char __user *optval, int optlen);
         int         (*getsockopt)(struct sock *sk, int level, int optname, 
                                   char __user *optval, int __user *optlen);
+#ifdef CONFIG_COMPAT
         int         (*compat_setsockopt)(struct sock *sk,
                                 int level, int optname,
                                 char __user *optval, int optlen);
         int         (*compat_getsockopt)(struct sock *sk,
                                 int level, int optname,
                                 char __user *optval, int __user *optlen);
+#endif
         void        (*addr2sockaddr)(struct sock *sk, struct sockaddr *);
         int         (*bind_conflict)(const struct sock *sk,
                                      const struct inet_bind_bucket *tb);
diff --git a/include/net/inet_hashtables.h b/include/net/inet_hashtables.h
index bb619d80f2e2..5cc182f9ecae 100644
--- a/include/net/inet_hashtables.h
+++ b/include/net/inet_hashtables.h
@@ -16,6 +16,7 @@
 
 
 #include <linux/interrupt.h>
+#include <linux/ip.h>
 #include <linux/ipv6.h>
 #include <linux/list.h>
 #include <linux/slab.h>
@@ -28,6 +29,7 @@
 #include <net/inet_connection_sock.h>
 #include <net/inet_sock.h>
 #include <net/sock.h>
+#include <net/route.h>
 #include <net/tcp_states.h>
 #include <net/netns/hash.h>
 
@@ -371,6 +373,22 @@ static inline struct sock *inet_lookup(struct net *net,
         return sk;
 }
 
+static inline struct sock *__inet_lookup_skb(struct inet_hashinfo *hashinfo,
+                                             struct sk_buff *skb,
+                                             const __be16 sport,
+                                             const __be16 dport)
+{
+        struct sock *sk;
+        const struct iphdr *iph = ip_hdr(skb);
+
+        if (unlikely(sk = skb_steal_sock(skb)))
+                return sk;
+        else
+                return __inet_lookup(dev_net(skb->dst->dev), hashinfo,
+                                     iph->saddr, sport,
+                                     iph->daddr, dport, inet_iif(skb));
+}
+
 extern int __inet_hash_connect(struct inet_timewait_death_row *death_row,
                 struct sock *sk, u32 port_offset,
                 int (*check_established)(struct inet_timewait_death_row *,
diff --git a/include/net/inet_sock.h b/include/net/inet_sock.h
index 643e26be058e..de0ecc71cf03 100644
--- a/include/net/inet_sock.h
+++ b/include/net/inet_sock.h
@@ -24,7 +24,6 @@
 #include <net/flow.h>
 #include <net/sock.h>
 #include <net/request_sock.h>
-#include <net/route.h>
 #include <net/netns/hash.h>
 
 /** struct ip_options - IP Options
@@ -62,8 +61,8 @@ struct inet_request_sock {
         struct request_sock     req;
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
         u16                     inet6_rsk_offset;
-        /* 2 bytes hole, try to pack */
 #endif
+        __be16                  loc_port;
         __be32                  loc_addr;
         __be32                  rmt_addr;
         __be16                  rmt_port;
@@ -73,7 +72,8 @@ struct inet_request_sock {
                                 sack_ok    : 1,
                                 wscale_ok  : 1,
                                 ecn_ok     : 1,
-                                acked      : 1;
+                                acked      : 1,
+                                no_srccheck: 1;
         struct ip_options       *opt;
 };
 
@@ -129,7 +129,8 @@ struct inet_sock {
                                 is_icsk:1,
                                 freebind:1,
                                 hdrincl:1,
-                                mc_loop:1;
+                                mc_loop:1,
+                                transparent:1;
         int                     mc_index;
         __be32                  mc_addr;
         struct ip_mc_socklist   *mc_list;
@@ -194,12 +195,6 @@ static inline int inet_sk_ehashfn(const struct sock *sk)
         return inet_ehashfn(net, laddr, lport, faddr, fport);
 }
 
-
-static inline int inet_iif(const struct sk_buff *skb)
-{
-        return skb->rtable->rt_iif;
-}
-
 static inline struct request_sock *inet_reqsk_alloc(struct request_sock_ops *ops)
 {
         struct request_sock *req = reqsk_alloc(ops);
@@ -210,4 +205,9 @@ static inline struct request_sock *inet_reqsk_alloc(struct request_sock_ops *ops
         return req;
 }
 
+static inline __u8 inet_sk_flowi_flags(const struct sock *sk)
+{
+        return inet_sk(sk)->transparent ? FLOWI_FLAG_ANYSRC : 0;
+}
+
 #endif  /* _INET_SOCK_H */
diff --git a/include/net/inet_timewait_sock.h b/include/net/inet_timewait_sock.h
index 95c660c9719b..80e4977631b8 100644
--- a/include/net/inet_timewait_sock.h
+++ b/include/net/inet_timewait_sock.h
@@ -128,7 +128,8 @@ struct inet_timewait_sock {
         __be16                  tw_dport;
         __u16                   tw_num;
         /* And these are ours. */
-        __u8                    tw_ipv6only:1;
+        __u8                    tw_ipv6only:1,
+                                tw_transparent:1;
         /* 15 bits hole, try to pack */
         __u16                   tw_ipv6_offset;
         unsigned long           tw_ttd;
@@ -208,6 +209,9 @@ extern void inet_twsk_schedule(struct inet_timewait_sock *tw,
 extern void inet_twsk_deschedule(struct inet_timewait_sock *tw,
                                  struct inet_timewait_death_row *twdr);
 
+extern void inet_twsk_purge(struct net *net, struct inet_hashinfo *hashinfo,
+                            struct inet_timewait_death_row *twdr, int family);
+
 static inline
 struct net *twsk_net(const struct inet_timewait_sock *twsk)
 {
diff --git a/include/net/ip.h b/include/net/ip.h
index 250e6ef025a4..bc026ecb513f 100644
--- a/include/net/ip.h
+++ b/include/net/ip.h
@@ -29,6 +29,7 @@
 
 #include <net/inet_sock.h>
 #include <net/snmp.h>
+#include <net/flow.h>
 
 struct sock;
 
@@ -140,12 +141,20 @@ static inline void ip_tr_mc_map(__be32 addr, char *buf)
 
 struct ip_reply_arg {
         struct kvec iov[1];   
+        int         flags;
         __wsum      csum;
         int         csumoffset; /* u16 offset of csum in iov[0].iov_base */
                                 /* -1 if not needed */ 
         int         bound_dev_if;
 }; 
 
+#define IP_REPLY_ARG_NOSRCCHECK 1
+
+static inline __u8 ip_reply_arg_flowi_flags(const struct ip_reply_arg *arg)
+{
+        return (arg->flags & IP_REPLY_ARG_NOSRCCHECK) ? FLOWI_FLAG_ANYSRC : 0;
+}
+
 void ip_send_reply(struct sock *sk, struct sk_buff *skb, struct ip_reply_arg *arg,
                    unsigned int len); 
 
@@ -169,6 +178,10 @@ extern unsigned long snmp_fold_field(void *mib[], int offt);
 extern int snmp_mib_init(void *ptr[2], size_t mibsize);
 extern void snmp_mib_free(void *ptr[2]);
 
+extern struct local_ports {
+        seqlock_t       lock;
+        int             range[2];
+} sysctl_local_ports;
 extern void inet_get_local_port_range(int *low, int *high);
 
 extern int sysctl_ip_default_ttl;
@@ -383,7 +396,7 @@ extern void	ip_local_error(struct sock *sk, int err, __be32 daddr, __be16 dport,
 int ipv4_doint_and_flush(ctl_table *ctl, int write,
                          struct file* filp, void __user *buffer,
                          size_t *lenp, loff_t *ppos);
-int ipv4_doint_and_flush_strategy(ctl_table *table, int __user *name, int nlen,
+int ipv4_doint_and_flush_strategy(ctl_table *table,
                                   void __user *oldval, size_t __user *oldlenp,
                                   void __user *newval, size_t newlen);
 #ifdef CONFIG_PROC_FS
diff --git a/include/net/ip_vs.h b/include/net/ip_vs.h
index 7312c3dd309f..fe9fcf73c85e 100644
--- a/include/net/ip_vs.h
+++ b/include/net/ip_vs.h
@@ -21,11 +21,104 @@
 #include <linux/timer.h>
 
 #include <net/checksum.h>
+#include <linux/netfilter.h>            /* for union nf_inet_addr */
+#include <linux/ip.h>
+#include <linux/ipv6.h>                 /* for struct ipv6hdr */
+#include <net/ipv6.h>                   /* for ipv6_addr_copy */
+
+struct ip_vs_iphdr {
+        int len;
+        __u8 protocol;
+        union nf_inet_addr saddr;
+        union nf_inet_addr daddr;
+};
+
+static inline void
+ip_vs_fill_iphdr(int af, const void *nh, struct ip_vs_iphdr *iphdr)
+{
+#ifdef CONFIG_IP_VS_IPV6
+        if (af == AF_INET6) {
+                const struct ipv6hdr *iph = nh;
+                iphdr->len = sizeof(struct ipv6hdr);
+                iphdr->protocol = iph->nexthdr;
+                ipv6_addr_copy(&iphdr->saddr.in6, &iph->saddr);
+                ipv6_addr_copy(&iphdr->daddr.in6, &iph->daddr);
+        } else
+#endif
+        {
+                const struct iphdr *iph = nh;
+                iphdr->len = iph->ihl * 4;
+                iphdr->protocol = iph->protocol;
+                iphdr->saddr.ip = iph->saddr;
+                iphdr->daddr.ip = iph->daddr;
+        }
+}
+
+static inline void ip_vs_addr_copy(int af, union nf_inet_addr *dst,
+                                   const union nf_inet_addr *src)
+{
+#ifdef CONFIG_IP_VS_IPV6
+        if (af == AF_INET6)
+                ipv6_addr_copy(&dst->in6, &src->in6);
+        else
+#endif
+        dst->ip = src->ip;
+}
+
+static inline int ip_vs_addr_equal(int af, const union nf_inet_addr *a,
+                                   const union nf_inet_addr *b)
+{
+#ifdef CONFIG_IP_VS_IPV6
+        if (af == AF_INET6)
+                return ipv6_addr_equal(&a->in6, &b->in6);
+#endif
+        return a->ip == b->ip;
+}
 
 #ifdef CONFIG_IP_VS_DEBUG
 #include <linux/net.h>
 
 extern int ip_vs_get_debug_level(void);
+
+static inline const char *ip_vs_dbg_addr(int af, char *buf, size_t buf_len,
+                                         const union nf_inet_addr *addr,
+                                         int *idx)
+{
+        int len;
+#ifdef CONFIG_IP_VS_IPV6
+        if (af == AF_INET6)
+                len = snprintf(&buf[*idx], buf_len - *idx, "[" NIP6_FMT "]",
+                               NIP6(addr->in6)) + 1;
+        else
+#endif
+                len = snprintf(&buf[*idx], buf_len - *idx, NIPQUAD_FMT,
+                               NIPQUAD(addr->ip)) + 1;
+
+        *idx += len;
+        BUG_ON(*idx > buf_len + 1);
+        return &buf[*idx - len];
+}
+
+#define IP_VS_DBG_BUF(level, msg...)                    \
+    do {                                                \
+            char ip_vs_dbg_buf[160];                    \
+            int ip_vs_dbg_idx = 0;                      \
+            if (level <= ip_vs_get_debug_level())       \
+                    printk(KERN_DEBUG "IPVS: " msg);    \
+    } while (0)
+#define IP_VS_ERR_BUF(msg...)                           \
+    do {                                                \
+            char ip_vs_dbg_buf[160];                    \
+            int ip_vs_dbg_idx = 0;                      \
+            printk(KERN_ERR "IPVS: " msg);              \
+    } while (0)
+
+/* Only use from within IP_VS_DBG_BUF() or IP_VS_ERR_BUF macros */
+#define IP_VS_DBG_ADDR(af, addr)                        \
+    ip_vs_dbg_addr(af, ip_vs_dbg_buf,                   \
+                   sizeof(ip_vs_dbg_buf), addr,         \
+                   &ip_vs_dbg_idx)
+
 #define IP_VS_DBG(level, msg...)                        \
     do {                                                \
             if (level <= ip_vs_get_debug_level())       \
@@ -48,6 +141,8 @@ extern int ip_vs_get_debug_level(void);
                 pp->debug_packet(pp, skb, ofs, msg);    \
     } while (0)
 #else   /* NO DEBUGGING at ALL */
+#define IP_VS_DBG_BUF(level, msg...)  do {} while (0)
+#define IP_VS_ERR_BUF(msg...)  do {} while (0)
 #define IP_VS_DBG(level, msg...)  do {} while (0)
 #define IP_VS_DBG_RL(msg...)  do {} while (0)
 #define IP_VS_DBG_PKT(level, pp, skb, ofs, msg)         do {} while (0)
@@ -70,13 +165,13 @@ extern int ip_vs_get_debug_level(void);
     do {                                                                \
             if (level <= ip_vs_get_debug_level())                       \
                     printk(KERN_DEBUG "Enter: %s, %s line %i\n",        \
-                           __FUNCTION__, __FILE__, __LINE__);           \
+                           __func__, __FILE__, __LINE__);               \
     } while (0)
 #define LeaveFunction(level)                                            \
     do {                                                                \
             if (level <= ip_vs_get_debug_level())                       \
                         printk(KERN_DEBUG "Leave: %s, %s line %i\n",    \
-                               __FUNCTION__, __FILE__, __LINE__);       \
+                               __func__, __FILE__, __LINE__);       \
     } while (0)
 #else
 #define EnterFunction(level)   do {} while (0)
@@ -160,27 +255,10 @@ struct ip_vs_estimator {
 
 struct ip_vs_stats
 {
-        __u32                   conns;          /* connections scheduled */
-        __u32                   inpkts;         /* incoming packets */
-        __u32                   outpkts;        /* outgoing packets */
-        __u64                   inbytes;        /* incoming bytes */
-        __u64                   outbytes;       /* outgoing bytes */
-
-        __u32                   cps;            /* current connection rate */
-        __u32                   inpps;          /* current in packet rate */
-        __u32                   outpps;         /* current out packet rate */
-        __u32                   inbps;          /* current in byte rate */
-        __u32                   outbps;         /* current out byte rate */
-
-        /*
-         * Don't add anything before the lock, because we use memcpy() to copy
-         * the members before the lock to struct ip_vs_stats_user in
-         * ip_vs_ctl.c.
-         */
+        struct ip_vs_stats_user ustats;         /* statistics */
+        struct ip_vs_estimator  est;            /* estimator */
 
         spinlock_t              lock;           /* spin lock */
-
-        struct ip_vs_estimator  est;            /* estimator */
 };
 
 struct dst_entry;
@@ -202,21 +280,23 @@ struct ip_vs_protocol {
 
         void (*exit)(struct ip_vs_protocol *pp);
 
-        int (*conn_schedule)(struct sk_buff *skb,
+        int (*conn_schedule)(int af, struct sk_buff *skb,
                              struct ip_vs_protocol *pp,
                              int *verdict, struct ip_vs_conn **cpp);
 
         struct ip_vs_conn *
-        (*conn_in_get)(const struct sk_buff *skb,
+        (*conn_in_get)(int af,
+                       const struct sk_buff *skb,
                        struct ip_vs_protocol *pp,
-                       const struct iphdr *iph,
+                       const struct ip_vs_iphdr *iph,
                        unsigned int proto_off,
                        int inverse);
 
         struct ip_vs_conn *
-        (*conn_out_get)(const struct sk_buff *skb,
+        (*conn_out_get)(int af,
+                        const struct sk_buff *skb,
                         struct ip_vs_protocol *pp,
-                        const struct iphdr *iph,
+                        const struct ip_vs_iphdr *iph,
                         unsigned int proto_off,
                         int inverse);
 
@@ -226,7 +306,8 @@ struct ip_vs_protocol {
         int (*dnat_handler)(struct sk_buff *skb,
                             struct ip_vs_protocol *pp, struct ip_vs_conn *cp);
 
-        int (*csum_check)(struct sk_buff *skb, struct ip_vs_protocol *pp);
+        int (*csum_check)(int af, struct sk_buff *skb,
+                          struct ip_vs_protocol *pp);
 
         const char *(*state_name)(int state);
 
@@ -259,9 +340,10 @@ struct ip_vs_conn {
         struct list_head        c_list;         /* hashed list heads */
 
         /* Protocol, addresses and port numbers */
-        __be32                   caddr;          /* client address */
-        __be32                   vaddr;          /* virtual address */
-        __be32                   daddr;          /* destination address */
+        u16                      af;            /* address family */
+        union nf_inet_addr       caddr;          /* client address */
+        union nf_inet_addr       vaddr;          /* virtual address */
+        union nf_inet_addr       daddr;          /* destination address */
         __be16                   cport;
         __be16                   vport;
         __be16                   dport;
@@ -305,6 +387,45 @@ struct ip_vs_conn {
 
 
 /*
+ *      Extended internal versions of struct ip_vs_service_user and
+ *      ip_vs_dest_user for IPv6 support.
+ *
+ *      We need these to conveniently pass around service and destination
+ *      options, but unfortunately, we also need to keep the old definitions to
+ *      maintain userspace backwards compatibility for the setsockopt interface.
+ */
+struct ip_vs_service_user_kern {
+        /* virtual service addresses */
+        u16                     af;
+        u16                     protocol;
+        union nf_inet_addr      addr;           /* virtual ip address */
+        u16                     port;
+        u32                     fwmark;         /* firwall mark of service */
+
+        /* virtual service options */
+        char                    *sched_name;
+        unsigned                flags;          /* virtual service flags */
+        unsigned                timeout;        /* persistent timeout in sec */
+        u32                     netmask;        /* persistent netmask */
+};
+
+
+struct ip_vs_dest_user_kern {
+        /* destination server address */
+        union nf_inet_addr      addr;
+        u16                     port;
+
+        /* real server options */
+        unsigned                conn_flags;     /* connection flags */
+        int                     weight;         /* destination weight */
+
+        /* thresholds for active connections */
+        u32                     u_threshold;    /* upper threshold */
+        u32                     l_threshold;    /* lower threshold */
+};
+
+
+/*
  *      The information about the virtual service offered to the net
  *      and the forwarding entries
  */
@@ -314,8 +435,9 @@ struct ip_vs_service {
         atomic_t                refcnt;   /* reference counter */
         atomic_t                usecnt;   /* use counter */
 
+        u16                     af;       /* address family */
         __u16                   protocol; /* which protocol (TCP/UDP) */
-        __be32                  addr;     /* IP address for virtual service */
+        union nf_inet_addr      addr;     /* IP address for virtual service */
         __be16                  port;     /* port number for the service */
         __u32                   fwmark;   /* firewall mark of the service */
         unsigned                flags;    /* service status flags */
@@ -342,7 +464,8 @@ struct ip_vs_dest {
         struct list_head        n_list;   /* for the dests in the service */
         struct list_head        d_list;   /* for table with all the dests */
 
-        __be32                  addr;           /* IP address of the server */
+        u16                     af;             /* address family */
+        union nf_inet_addr      addr;           /* IP address of the server */
         __be16                  port;           /* port number of the server */
         volatile unsigned       flags;          /* dest status flags */
         atomic_t                conn_flags;     /* flags to copy to conn */
@@ -366,7 +489,7 @@ struct ip_vs_dest {
         /* for virtual service */
         struct ip_vs_service    *svc;           /* service it belongs to */
         __u16                   protocol;       /* which protocol (TCP/UDP) */
-        __be32                  vaddr;          /* virtual IP address */
+        union nf_inet_addr      vaddr;          /* virtual IP address */
         __be16                  vport;          /* virtual port number */
         __u32                   vfwmark;        /* firewall mark of service */
 };
@@ -380,6 +503,9 @@ struct ip_vs_scheduler {
         char                    *name;          /* scheduler name */
         atomic_t                refcnt;         /* reference counter */
         struct module           *module;        /* THIS_MODULE/NULL */
+#ifdef CONFIG_IP_VS_IPV6
+        int                     supports_ipv6;  /* scheduler has IPv6 support */
+#endif
 
         /* scheduler initializing service */
         int (*init_service)(struct ip_vs_service *svc);
@@ -479,16 +605,8 @@ extern void ip_vs_init_hash_table(struct list_head *table, int rows);
 #ifndef CONFIG_IP_VS_TAB_BITS
 #define CONFIG_IP_VS_TAB_BITS   12
 #endif
-/* make sure that IP_VS_CONN_TAB_BITS is located in [8, 20] */
-#if CONFIG_IP_VS_TAB_BITS < 8
-#define IP_VS_CONN_TAB_BITS     8
-#endif
-#if CONFIG_IP_VS_TAB_BITS > 20
-#define IP_VS_CONN_TAB_BITS     20
-#endif
-#if 8 <= CONFIG_IP_VS_TAB_BITS && CONFIG_IP_VS_TAB_BITS <= 20
+
 #define IP_VS_CONN_TAB_BITS     CONFIG_IP_VS_TAB_BITS
-#endif
 #define IP_VS_CONN_TAB_SIZE     (1 << IP_VS_CONN_TAB_BITS)
 #define IP_VS_CONN_TAB_MASK     (IP_VS_CONN_TAB_SIZE - 1)
 
@@ -500,11 +618,16 @@ enum {
 };
 
 extern struct ip_vs_conn *ip_vs_conn_in_get
-(int protocol, __be32 s_addr, __be16 s_port, __be32 d_addr, __be16 d_port);
+(int af, int protocol, const union nf_inet_addr *s_addr, __be16 s_port,
+ const union nf_inet_addr *d_addr, __be16 d_port);
+
 extern struct ip_vs_conn *ip_vs_ct_in_get
-(int protocol, __be32 s_addr, __be16 s_port, __be32 d_addr, __be16 d_port);
+(int af, int protocol, const union nf_inet_addr *s_addr, __be16 s_port,
+ const union nf_inet_addr *d_addr, __be16 d_port);
+
 extern struct ip_vs_conn *ip_vs_conn_out_get
-(int protocol, __be32 s_addr, __be16 s_port, __be32 d_addr, __be16 d_port);
+(int af, int protocol, const union nf_inet_addr *s_addr, __be16 s_port,
+ const union nf_inet_addr *d_addr, __be16 d_port);
 
 /* put back the conn without restarting its timer */
 static inline void __ip_vs_conn_put(struct ip_vs_conn *cp)
@@ -515,8 +638,9 @@ extern void ip_vs_conn_put(struct ip_vs_conn *cp);
 extern void ip_vs_conn_fill_cport(struct ip_vs_conn *cp, __be16 cport);
 
 extern struct ip_vs_conn *
-ip_vs_conn_new(int proto, __be32 caddr, __be16 cport, __be32 vaddr, __be16 vport,
-               __be32 daddr, __be16 dport, unsigned flags,
+ip_vs_conn_new(int af, int proto, const union nf_inet_addr *caddr, __be16 cport,
+               const union nf_inet_addr *vaddr, __be16 vport,
+               const union nf_inet_addr *daddr, __be16 dport, unsigned flags,
                struct ip_vs_dest *dest);
 extern void ip_vs_conn_expire_now(struct ip_vs_conn *cp);
 
@@ -532,24 +656,32 @@ static inline void ip_vs_control_del(struct ip_vs_conn *cp)
 {
         struct ip_vs_conn *ctl_cp = cp->control;
         if (!ctl_cp) {
-                IP_VS_ERR("request control DEL for uncontrolled: "
-                          "%d.%d.%d.%d:%d to %d.%d.%d.%d:%d\n",
-                          NIPQUAD(cp->caddr),ntohs(cp->cport),
-                          NIPQUAD(cp->vaddr),ntohs(cp->vport));
+                IP_VS_ERR_BUF("request control DEL for uncontrolled: "
+                              "%s:%d to %s:%d\n",
+                              IP_VS_DBG_ADDR(cp->af, &cp->caddr),
+                              ntohs(cp->cport),
+                              IP_VS_DBG_ADDR(cp->af, &cp->vaddr),
+                              ntohs(cp->vport));
+
                 return;
         }
 
-        IP_VS_DBG(7, "DELeting control for: "
-                  "cp.dst=%d.%d.%d.%d:%d ctl_cp.dst=%d.%d.%d.%d:%d\n",
-                  NIPQUAD(cp->caddr),ntohs(cp->cport),
-                  NIPQUAD(ctl_cp->caddr),ntohs(ctl_cp->cport));
+        IP_VS_DBG_BUF(7, "DELeting control for: "
+                      "cp.dst=%s:%d ctl_cp.dst=%s:%d\n",
+                      IP_VS_DBG_ADDR(cp->af, &cp->caddr),
+                      ntohs(cp->cport),
+                      IP_VS_DBG_ADDR(cp->af, &ctl_cp->caddr),
+                      ntohs(ctl_cp->cport));
 
         cp->control = NULL;
         if (atomic_read(&ctl_cp->n_control) == 0) {
-                IP_VS_ERR("BUG control DEL with n=0 : "
-                          "%d.%d.%d.%d:%d to %d.%d.%d.%d:%d\n",
-                          NIPQUAD(cp->caddr),ntohs(cp->cport),
-                          NIPQUAD(cp->vaddr),ntohs(cp->vport));
+                IP_VS_ERR_BUF("BUG control DEL with n=0 : "
+                              "%s:%d to %s:%d\n",
+                              IP_VS_DBG_ADDR(cp->af, &cp->caddr),
+                              ntohs(cp->cport),
+                              IP_VS_DBG_ADDR(cp->af, &cp->vaddr),
+                              ntohs(cp->vport));
+
                 return;
         }
         atomic_dec(&ctl_cp->n_control);
@@ -559,17 +691,22 @@ static inline void
 ip_vs_control_add(struct ip_vs_conn *cp, struct ip_vs_conn *ctl_cp)
 {
         if (cp->control) {
-                IP_VS_ERR("request control ADD for already controlled: "
-                          "%d.%d.%d.%d:%d to %d.%d.%d.%d:%d\n",
-                          NIPQUAD(cp->caddr),ntohs(cp->cport),
-                          NIPQUAD(cp->vaddr),ntohs(cp->vport));
+                IP_VS_ERR_BUF("request control ADD for already controlled: "
+                              "%s:%d to %s:%d\n",
+                              IP_VS_DBG_ADDR(cp->af, &cp->caddr),
+                              ntohs(cp->cport),
+                              IP_VS_DBG_ADDR(cp->af, &cp->vaddr),
+                              ntohs(cp->vport));
+
                 ip_vs_control_del(cp);
         }
 
-        IP_VS_DBG(7, "ADDing control for: "
-                  "cp.dst=%d.%d.%d.%d:%d ctl_cp.dst=%d.%d.%d.%d:%d\n",
-                  NIPQUAD(cp->caddr),ntohs(cp->cport),
-                  NIPQUAD(ctl_cp->caddr),ntohs(ctl_cp->cport));
+        IP_VS_DBG_BUF(7, "ADDing control for: "
+                      "cp.dst=%s:%d ctl_cp.dst=%s:%d\n",
+                      IP_VS_DBG_ADDR(cp->af, &cp->caddr),
+                      ntohs(cp->cport),
+                      IP_VS_DBG_ADDR(cp->af, &ctl_cp->caddr),
+                      ntohs(ctl_cp->cport));
 
         cp->control = ctl_cp;
         atomic_inc(&ctl_cp->n_control);
@@ -647,7 +784,8 @@ extern struct ip_vs_stats ip_vs_stats;
 extern const struct ctl_path net_vs_ctl_path[];
 
 extern struct ip_vs_service *
-ip_vs_service_get(__u32 fwmark, __u16 protocol, __be32 vaddr, __be16 vport);
+ip_vs_service_get(int af, __u32 fwmark, __u16 protocol,
+                  const union nf_inet_addr *vaddr, __be16 vport);
 
 static inline void ip_vs_service_put(struct ip_vs_service *svc)
 {
@@ -655,14 +793,16 @@ static inline void ip_vs_service_put(struct ip_vs_service *svc)
 }
 
 extern struct ip_vs_dest *
-ip_vs_lookup_real_service(__u16 protocol, __be32 daddr, __be16 dport);
+ip_vs_lookup_real_service(int af, __u16 protocol,
+                          const union nf_inet_addr *daddr, __be16 dport);
+
 extern int ip_vs_use_count_inc(void);
 extern void ip_vs_use_count_dec(void);
 extern int ip_vs_control_init(void);
 extern void ip_vs_control_cleanup(void);
 extern struct ip_vs_dest *
-ip_vs_find_dest(__be32 daddr, __be16 dport,
-                 __be32 vaddr, __be16 vport, __u16 protocol);
+ip_vs_find_dest(int af, const union nf_inet_addr *daddr, __be16 dport,
+                const union nf_inet_addr *vaddr, __be16 vport, __u16 protocol);
 extern struct ip_vs_dest *ip_vs_try_bind_dest(struct ip_vs_conn *cp);
 
 
@@ -683,6 +823,8 @@ extern void ip_vs_sync_conn(struct ip_vs_conn *cp);
 /*
  *      IPVS rate estimator prototypes (from ip_vs_est.c)
  */
+extern int ip_vs_estimator_init(void);
+extern void ip_vs_estimator_cleanup(void);
 extern void ip_vs_new_estimator(struct ip_vs_stats *stats);
 extern void ip_vs_kill_estimator(struct ip_vs_stats *stats);
 extern void ip_vs_zero_estimator(struct ip_vs_stats *stats);
@@ -704,6 +846,19 @@ extern int ip_vs_icmp_xmit
 (struct sk_buff *skb, struct ip_vs_conn *cp, struct ip_vs_protocol *pp, int offset);
 extern void ip_vs_dst_reset(struct ip_vs_dest *dest);
 
+#ifdef CONFIG_IP_VS_IPV6
+extern int ip_vs_bypass_xmit_v6
+(struct sk_buff *skb, struct ip_vs_conn *cp, struct ip_vs_protocol *pp);
+extern int ip_vs_nat_xmit_v6
+(struct sk_buff *skb, struct ip_vs_conn *cp, struct ip_vs_protocol *pp);
+extern int ip_vs_tunnel_xmit_v6
+(struct sk_buff *skb, struct ip_vs_conn *cp, struct ip_vs_protocol *pp);
+extern int ip_vs_dr_xmit_v6
+(struct sk_buff *skb, struct ip_vs_conn *cp, struct ip_vs_protocol *pp);
+extern int ip_vs_icmp_xmit_v6
+(struct sk_buff *skb, struct ip_vs_conn *cp, struct ip_vs_protocol *pp,
+ int offset);
+#endif
 
 /*
  *      This is a simple mechanism to ignore packets when
@@ -748,7 +903,12 @@ static inline char ip_vs_fwd_tag(struct ip_vs_conn *cp)
 }
 
 extern void ip_vs_nat_icmp(struct sk_buff *skb, struct ip_vs_protocol *pp,
-                struct ip_vs_conn *cp, int dir);
+                           struct ip_vs_conn *cp, int dir);
+
+#ifdef CONFIG_IP_VS_IPV6
+extern void ip_vs_nat_icmp_v6(struct sk_buff *skb, struct ip_vs_protocol *pp,
+                              struct ip_vs_conn *cp, int dir);
+#endif
 
 extern __sum16 ip_vs_checksum_complete(struct sk_buff *skb, int offset);
 
@@ -759,6 +919,17 @@ static inline __wsum ip_vs_check_diff4(__be32 old, __be32 new, __wsum oldsum)
         return csum_partial((char *) diff, sizeof(diff), oldsum);
 }
 
+#ifdef CONFIG_IP_VS_IPV6
+static inline __wsum ip_vs_check_diff16(const __be32 *old, const __be32 *new,
+                                        __wsum oldsum)
+{
+        __be32 diff[8] = { ~old[3], ~old[2], ~old[1], ~old[0],
+                            new[3],  new[2],  new[1],  new[0] };
+
+        return csum_partial((char *) diff, sizeof(diff), oldsum);
+}
+#endif
+
 static inline __wsum ip_vs_check_diff2(__be16 old, __be16 new, __wsum oldsum)
 {
         __be16 diff[2] = { ~old, new };
diff --git a/include/net/ipip.h b/include/net/ipip.h
index a85bda64b852..fdf9bd743705 100644
--- a/include/net/ipip.h
+++ b/include/net/ipip.h
@@ -37,7 +37,7 @@ struct ip_tunnel_prl_entry
 
 #define IPTUNNEL_XMIT() do {                                            \
         int err;                                                        \
-        int pkt_len = skb->len;                                         \
+        int pkt_len = skb->len - skb_transport_offset(skb);             \
                                                                         \
         skb->ip_summed = CHECKSUM_NONE;                                 \
         ip_select_ident(iph, &rt->u.dst, NULL);                         \
diff --git a/include/net/ipv6.h b/include/net/ipv6.h
index 113028fb8f66..6d5b58a1c743 100644
--- a/include/net/ipv6.h
+++ b/include/net/ipv6.h
@@ -110,43 +110,42 @@ struct frag_hdr {
 extern int sysctl_mld_max_msf;
 extern struct ctl_path net_ipv6_ctl_path[];
 
-#define _DEVINC(statname, modifier, idev, field)                        \
+#define _DEVINC(net, statname, modifier, idev, field)                   \
 ({                                                                      \
         struct inet6_dev *_idev = (idev);                               \
         if (likely(_idev != NULL))                                      \
                 SNMP_INC_STATS##modifier((_idev)->stats.statname, (field)); \
-        SNMP_INC_STATS##modifier(statname##_statistics, (field));       \
+        SNMP_INC_STATS##modifier((net)->mib.statname##_statistics, (field));\
 })
 
-#define _DEVADD(statname, modifier, idev, field, val)                   \
+#define _DEVADD(net, statname, modifier, idev, field, val)              \
 ({                                                                      \
         struct inet6_dev *_idev = (idev);                               \
         if (likely(_idev != NULL))                                      \
                 SNMP_ADD_STATS##modifier((_idev)->stats.statname, (field), (val)); \
-        SNMP_ADD_STATS##modifier(statname##_statistics, (field), (val));\
+        SNMP_ADD_STATS##modifier((net)->mib.statname##_statistics, (field), (val));\
 })
 
 /* MIBs */
-DECLARE_SNMP_STAT(struct ipstats_mib, ipv6_statistics);
 
-#define IP6_INC_STATS(idev,field)       _DEVINC(ipv6, , idev, field)
-#define IP6_INC_STATS_BH(idev,field)    _DEVINC(ipv6, _BH, idev, field)
-#define IP6_ADD_STATS_BH(idev,field,val) _DEVADD(ipv6, _BH, idev, field, val)
-
-DECLARE_SNMP_STAT(struct icmpv6_mib, icmpv6_statistics);
-DECLARE_SNMP_STAT(struct icmpv6msg_mib, icmpv6msg_statistics);
-
-#define ICMP6_INC_STATS(idev, field)    _DEVINC(icmpv6, , idev, field)
-#define ICMP6_INC_STATS_BH(idev, field) _DEVINC(icmpv6, _BH, idev, field)
-
-#define ICMP6MSGOUT_INC_STATS(idev, field) \
-        _DEVINC(icmpv6msg, , idev, field +256)
-#define ICMP6MSGOUT_INC_STATS_BH(idev, field) \
-        _DEVINC(icmpv6msg, _BH, idev, field +256)
-#define ICMP6MSGIN_INC_STATS(idev, field) \
-         _DEVINC(icmpv6msg, , idev, field)
-#define ICMP6MSGIN_INC_STATS_BH(idev, field) \
-        _DEVINC(icmpv6msg, _BH, idev, field)
+#define IP6_INC_STATS(net, idev,field)          \
+                _DEVINC(net, ipv6, , idev, field)
+#define IP6_INC_STATS_BH(net, idev,field)       \
+                _DEVINC(net, ipv6, _BH, idev, field)
+#define IP6_ADD_STATS_BH(net, idev,field,val)   \
+                _DEVADD(net, ipv6, _BH, idev, field, val)
+
+#define ICMP6_INC_STATS(net, idev, field)       \
+                _DEVINC(net, icmpv6, , idev, field)
+#define ICMP6_INC_STATS_BH(net, idev, field)    \
+                _DEVINC(net, icmpv6, _BH, idev, field)
+
+#define ICMP6MSGOUT_INC_STATS(net, idev, field)         \
+        _DEVINC(net, icmpv6msg, , idev, field +256)
+#define ICMP6MSGOUT_INC_STATS_BH(net, idev, field)      \
+        _DEVINC(net, icmpv6msg, _BH, idev, field +256)
+#define ICMP6MSGIN_INC_STATS_BH(net, idev, field)       \
+        _DEVINC(net, icmpv6msg, _BH, idev, field)
 
 struct ip6_ra_chain
 {
@@ -576,6 +575,8 @@ extern int ip6_mc_msfilter(struct sock *sk, struct group_filter *gsf);
 extern int ip6_mc_msfget(struct sock *sk, struct group_filter *gsf,
                          struct group_filter __user *optval,
                          int __user *optlen);
+extern unsigned int inet6_hash_frag(__be32 id, const struct in6_addr *saddr,
+                                    const struct in6_addr *daddr, u32 rnd);
 
 #ifdef CONFIG_PROC_FS
 extern int  ac6_proc_init(struct net *net);
diff --git a/include/net/irda/irda.h b/include/net/irda/irda.h
index 08387553b57e..7e582061b230 100644
--- a/include/net/irda/irda.h
+++ b/include/net/irda/irda.h
@@ -72,7 +72,7 @@ do {	if (irda_debug >= (n)) \
 #define IRDA_ASSERT(expr, func) \
 do { if(!(expr)) { \
         printk( "Assertion failed! %s:%s:%d %s\n", \
-                __FILE__,__FUNCTION__,__LINE__,(#expr) ); \
+                __FILE__,__func__,__LINE__,(#expr) ); \
         func } } while (0)
 #define IRDA_ASSERT_LABEL(label)        label
 #else
diff --git a/include/net/mac80211.h b/include/net/mac80211.h
index ff137fd7714f..d861197f83c7 100644
--- a/include/net/mac80211.h
+++ b/include/net/mac80211.h
@@ -158,13 +158,17 @@ struct ieee80211_low_level_stats {
  *      also implies a change in the AID.
  * @BSS_CHANGED_ERP_CTS_PROT: CTS protection changed
  * @BSS_CHANGED_ERP_PREAMBLE: preamble changed
+ * @BSS_CHANGED_ERP_SLOT: slot timing changed
  * @BSS_CHANGED_HT: 802.11n parameters changed
+ * @BSS_CHANGED_BASIC_RATES: Basic rateset changed
  */
 enum ieee80211_bss_change {
         BSS_CHANGED_ASSOC               = 1<<0,
         BSS_CHANGED_ERP_CTS_PROT        = 1<<1,
         BSS_CHANGED_ERP_PREAMBLE        = 1<<2,
+        BSS_CHANGED_ERP_SLOT            = 1<<3,
         BSS_CHANGED_HT                  = 1<<4,
+        BSS_CHANGED_BASIC_RATES         = 1<<5,
 };
 
 /**
@@ -177,6 +181,7 @@ enum ieee80211_bss_change {
  * @aid: association ID number, valid only when @assoc is true
  * @use_cts_prot: use CTS protection
  * @use_short_preamble: use 802.11b short preamble
+ * @use_short_slot: use short slot time (only relevant for ERP)
  * @dtim_period: num of beacons before the next DTIM, for PSM
  * @timestamp: beacon timestamp
  * @beacon_int: beacon interval
@@ -184,6 +189,9 @@ enum ieee80211_bss_change {
  * @assoc_ht: association in HT mode
  * @ht_conf: ht capabilities
  * @ht_bss_conf: ht extended capabilities
+ * @basic_rates: bitmap of basic rates, each bit stands for an
+ *      index into the rate table configured by the driver in
+ *      the current band.
  */
 struct ieee80211_bss_conf {
         /* association related data */
@@ -192,10 +200,12 @@ struct ieee80211_bss_conf {
         /* erp related data */
         bool use_cts_prot;
         bool use_short_preamble;
+        bool use_short_slot;
         u8 dtim_period;
         u16 beacon_int;
         u16 assoc_capability;
         u64 timestamp;
+        u64 basic_rates;
         /* ht related data */
         bool assoc_ht;
         struct ieee80211_ht_info *ht_conf;
@@ -282,6 +292,20 @@ enum mac80211_tx_control_flags {
 #define IEEE80211_TX_INFO_DRIVER_DATA_PTRS \
         (IEEE80211_TX_INFO_DRIVER_DATA_SIZE / sizeof(void *))
 
+/* maximum number of alternate rate retry stages */
+#define IEEE80211_TX_MAX_ALTRATE        3
+
+/**
+ * struct ieee80211_tx_altrate - alternate rate selection/status
+ *
+ * @rate_idx: rate index to attempt to send with
+ * @limit: number of retries before fallback
+ */
+struct ieee80211_tx_altrate {
+        s8 rate_idx;
+        u8 limit;
+};
+
 /**
  * struct ieee80211_tx_info - skb transmit information
  *
@@ -290,6 +314,9 @@ enum mac80211_tx_control_flags {
  *  (2) driver internal use (if applicable)
  *  (3) TX status information - driver tells mac80211 what happened
  *
+ * The TX control's sta pointer is only valid during the ->tx call,
+ * it may be NULL.
+ *
  * @flags: transmit info flags, defined above
  * @band: TBD
  * @tx_rate_idx: TBD
@@ -317,18 +344,19 @@ struct ieee80211_tx_info {
 
         union {
                 struct {
+                        /* NB: vif can be NULL for injected frames */
                         struct ieee80211_vif *vif;
                         struct ieee80211_key_conf *hw_key;
+                        struct ieee80211_sta *sta;
                         unsigned long jiffies;
-                        u16 aid;
-                        s8 rts_cts_rate_idx, alt_retry_rate_idx;
+                        s8 rts_cts_rate_idx;
                         u8 retry_limit;
-                        u8 icv_len;
-                        u8 iv_len;
+                        struct ieee80211_tx_altrate retries[IEEE80211_TX_MAX_ALTRATE];
                 } control;
                 struct {
                         u64 ampdu_ack_map;
                         int ack_signal;
+                        struct ieee80211_tx_altrate retries[IEEE80211_TX_MAX_ALTRATE + 1];
                         u8 retry_count;
                         bool excessive_retries;
                         u8 ampdu_ack_len;
@@ -363,6 +391,7 @@ static inline struct ieee80211_tx_info *IEEE80211_SKB_CB(struct sk_buff *skb)
  * @RX_FLAG_TSFT: The timestamp passed in the RX status (@mactime field)
  *      is valid. This is useful in monitor mode and necessary for beacon frames
  *      to enable IBSS merging.
+ * @RX_FLAG_SHORTPRE: Short preamble was used for this frame
  */
 enum mac80211_rx_flags {
         RX_FLAG_MMIC_ERROR      = 1<<0,
@@ -373,6 +402,7 @@ enum mac80211_rx_flags {
         RX_FLAG_FAILED_FCS_CRC  = 1<<5,
         RX_FLAG_FAILED_PLCP_CRC = 1<<6,
         RX_FLAG_TSFT            = 1<<7,
+        RX_FLAG_SHORTPRE        = 1<<8
 };
 
 /**
@@ -418,6 +448,11 @@ struct ieee80211_rx_status {
  * @IEEE80211_CONF_PS: Enable 802.11 power save mode
  */
 enum ieee80211_conf_flags {
+        /*
+         * TODO: IEEE80211_CONF_SHORT_SLOT_TIME will be removed once drivers
+         * have been converted to use bss_info_changed() for slot time
+         * configuration
+         */
         IEEE80211_CONF_SHORT_SLOT_TIME  = (1<<0),
         IEEE80211_CONF_RADIOTAP         = (1<<1),
         IEEE80211_CONF_SUPPORT_HT_MODE  = (1<<2),
@@ -461,33 +496,6 @@ struct ieee80211_conf {
 };
 
 /**
- * enum ieee80211_if_types - types of 802.11 network interfaces
- *
- * @IEEE80211_IF_TYPE_INVALID: invalid interface type, not used
- *      by mac80211 itself
- * @IEEE80211_IF_TYPE_AP: interface in AP mode.
- * @IEEE80211_IF_TYPE_MGMT: special interface for communication with hostap
- *      daemon. Drivers should never see this type.
- * @IEEE80211_IF_TYPE_STA: interface in STA (client) mode.
- * @IEEE80211_IF_TYPE_IBSS: interface in IBSS (ad-hoc) mode.
- * @IEEE80211_IF_TYPE_MNTR: interface in monitor (rfmon) mode.
- * @IEEE80211_IF_TYPE_WDS: interface in WDS mode.
- * @IEEE80211_IF_TYPE_VLAN: VLAN interface bound to an AP, drivers
- *      will never see this type.
- * @IEEE80211_IF_TYPE_MESH_POINT: 802.11s mesh point
- */
-enum ieee80211_if_types {
-        IEEE80211_IF_TYPE_INVALID,
-        IEEE80211_IF_TYPE_AP,
-        IEEE80211_IF_TYPE_STA,
-        IEEE80211_IF_TYPE_IBSS,
-        IEEE80211_IF_TYPE_MESH_POINT,
-        IEEE80211_IF_TYPE_MNTR,
-        IEEE80211_IF_TYPE_WDS,
-        IEEE80211_IF_TYPE_VLAN,
-};
-
-/**
  * struct ieee80211_vif - per-interface data
  *
  * Data in this structure is continually present for driver
@@ -498,7 +506,7 @@ enum ieee80211_if_types {
  *      sizeof(void *).
  */
 struct ieee80211_vif {
-        enum ieee80211_if_types type;
+        enum nl80211_iftype type;
         /* must be last */
         u8 drv_priv[0] __attribute__((__aligned__(sizeof(void *))));
 };
@@ -506,7 +514,7 @@ struct ieee80211_vif {
 static inline bool ieee80211_vif_is_mesh(struct ieee80211_vif *vif)
 {
 #ifdef CONFIG_MAC80211_MESH
-        return vif->type == IEEE80211_IF_TYPE_MESH_POINT;
+        return vif->type == NL80211_IFTYPE_MESH_POINT;
 #endif
         return false;
 }
@@ -517,7 +525,7 @@ static inline bool ieee80211_vif_is_mesh(struct ieee80211_vif *vif)
  * @vif: pointer to a driver-use per-interface structure. The pointer
  *      itself is also used for various functions including
  *      ieee80211_beacon_get() and ieee80211_get_buffered_bc().
- * @type: one of &enum ieee80211_if_types constants. Determines the type of
+ * @type: one of &enum nl80211_iftype constants. Determines the type of
  *      added/removed interface.
  * @mac_addr: pointer to MAC address of the interface. This pointer is valid
  *      until the interface is removed (i.e. it cannot be used after
@@ -533,7 +541,7 @@ static inline bool ieee80211_vif_is_mesh(struct ieee80211_vif *vif)
  * in pure monitor mode.
  */
 struct ieee80211_if_init_conf {
-        enum ieee80211_if_types type;
+        enum nl80211_iftype type;
         struct ieee80211_vif *vif;
         void *mac_addr;
 };
@@ -637,10 +645,13 @@ enum ieee80211_key_flags {
  *      - Temporal Encryption Key (128 bits)
  *      - Temporal Authenticator Tx MIC Key (64 bits)
  *      - Temporal Authenticator Rx MIC Key (64 bits)
- *
+ * @icv_len: FIXME
+ * @iv_len: FIXME
  */
 struct ieee80211_key_conf {
         enum ieee80211_key_alg alg;
+        u8 icv_len;
+        u8 iv_len;
         u8 hw_key_idx;
         u8 flags;
         s8 keyidx;
@@ -662,6 +673,33 @@ enum set_key_cmd {
 };
 
 /**
+ * struct ieee80211_sta - station table entry
+ *
+ * A station table entry represents a station we are possibly
+ * communicating with. Since stations are RCU-managed in
+ * mac80211, any ieee80211_sta pointer you get access to must
+ * either be protected by rcu_read_lock() explicitly or implicitly,
+ * or you must take good care to not use such a pointer after a
+ * call to your sta_notify callback that removed it.
+ *
+ * @addr: MAC address
+ * @aid: AID we assigned to the station if we're an AP
+ * @supp_rates: Bitmap of supported rates (per band)
+ * @ht_info: HT capabilities of this STA
+ * @drv_priv: data area for driver use, will always be aligned to
+ *      sizeof(void *), size is determined in hw information.
+ */
+struct ieee80211_sta {
+        u64 supp_rates[IEEE80211_NUM_BANDS];
+        u8 addr[ETH_ALEN];
+        u16 aid;
+        struct ieee80211_ht_info ht_info;
+
+        /* must be last */
+        u8 drv_priv[0] __attribute__((__aligned__(sizeof(void *))));
+};
+
+/**
  * enum sta_notify_cmd - sta notify command
  *
  * Used with the sta_notify() callback in &struct ieee80211_ops, this
@@ -805,6 +843,11 @@ enum ieee80211_hw_flags {
  *
  * @vif_data_size: size (in bytes) of the drv_priv data area
  *      within &struct ieee80211_vif.
+ * @sta_data_size: size (in bytes) of the drv_priv data area
+ *      within &struct ieee80211_sta.
+ *
+ * @max_altrates: maximum number of alternate rate retry stages
+ * @max_altrate_tries: maximum number of tries for each stage
  */
 struct ieee80211_hw {
         struct ieee80211_conf conf;
@@ -816,12 +859,17 @@ struct ieee80211_hw {
         unsigned int extra_tx_headroom;
         int channel_change_time;
         int vif_data_size;
+        int sta_data_size;
         u16 queues;
         u16 ampdu_queues;
         u16 max_listen_interval;
         s8 max_signal;
+        u8 max_altrates;
+        u8 max_altrate_tries;
 };
 
+struct ieee80211_hw *wiphy_to_hw(struct wiphy *wiphy);
+
 /**
  * SET_IEEE80211_DEV - set device for 802.11 hardware
  *
@@ -874,11 +922,11 @@ ieee80211_get_rts_cts_rate(const struct ieee80211_hw *hw,
 
 static inline struct ieee80211_rate *
 ieee80211_get_alt_retry_rate(const struct ieee80211_hw *hw,
-                             const struct ieee80211_tx_info *c)
+                             const struct ieee80211_tx_info *c, int idx)
 {
-        if (c->control.alt_retry_rate_idx < 0)
+        if (c->control.retries[idx].rate_idx < 0)
                 return NULL;
-        return &hw->wiphy->bands[c->band]->bitrates[c->control.alt_retry_rate_idx];
+        return &hw->wiphy->bands[c->band]->bitrates[c->control.retries[idx].rate_idx];
 }
 
 /**
@@ -1097,7 +1145,7 @@ enum ieee80211_ampdu_mlme_action {
  *      This callback must be implemented and atomic.
  *
  * @set_tim: Set TIM bit. mac80211 calls this function when a TIM bit
- *      must be set or cleared for a given AID. Must be atomic.
+ *      must be set or cleared for a given STA. Must be atomic.
  *
  * @set_key: See the section "Hardware crypto acceleration"
  *      This callback can sleep, and is only called between add_interface
@@ -1111,7 +1159,9 @@ enum ieee80211_ampdu_mlme_action {
  * @hw_scan: Ask the hardware to service the scan request, no need to start
  *      the scan state machine in stack. The scan must honour the channel
  *      configuration done by the regulatory agent in the wiphy's registered
- *      bands.
+ *      bands. When the scan finishes, ieee80211_scan_completed() must be
+ *      called; note that it also must be called when the scan cannot finish
+ *      because the hardware is turned off! Anything else is a bug!
  *
  * @get_stats: return low-level statistics
  *
@@ -1131,7 +1181,7 @@ enum ieee80211_ampdu_mlme_action {
  *      of assocaited station or AP.
  *
  * @conf_tx: Configure TX queue parameters (EDCF (aifs, cw_min, cw_max),
- *      bursting) for a hardware TX queue. Must be atomic.
+ *      bursting) for a hardware TX queue.
  *
  * @get_tx_stats: Get statistics of the current TX queue status. This is used
  *      to get number of currently queued packets (queue length), maximum queue
@@ -1181,7 +1231,8 @@ struct ieee80211_ops {
                                  unsigned int changed_flags,
                                  unsigned int *total_flags,
                                  int mc_count, struct dev_addr_list *mc_list);
-        int (*set_tim)(struct ieee80211_hw *hw, int aid, int set);
+        int (*set_tim)(struct ieee80211_hw *hw, struct ieee80211_sta *sta,
+                       bool set);
         int (*set_key)(struct ieee80211_hw *hw, enum set_key_cmd cmd,
                        const u8 *local_address, const u8 *address,
                        struct ieee80211_key_conf *key);
@@ -1198,7 +1249,7 @@ struct ieee80211_ops {
         int (*set_retry_limit)(struct ieee80211_hw *hw,
                                u32 short_retry, u32 long_retr);
         void (*sta_notify)(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
-                        enum sta_notify_cmd, const u8 *addr);
+                        enum sta_notify_cmd, struct ieee80211_sta *sta);
         int (*conf_tx)(struct ieee80211_hw *hw, u16 queue,
                        const struct ieee80211_tx_queue_params *params);
         int (*get_tx_stats)(struct ieee80211_hw *hw,
@@ -1208,7 +1259,7 @@ struct ieee80211_ops {
         int (*tx_last_beacon)(struct ieee80211_hw *hw);
         int (*ampdu_action)(struct ieee80211_hw *hw,
                             enum ieee80211_ampdu_mlme_action action,
-                            const u8 *addr, u16 tid, u16 *ssn);
+                            struct ieee80211_sta *sta, u16 tid, u16 *ssn);
 };
 
 /**
@@ -1557,16 +1608,6 @@ ieee80211_get_buffered_bc(struct ieee80211_hw *hw, struct ieee80211_vif *vif);
 unsigned int ieee80211_get_hdrlen_from_skb(const struct sk_buff *skb);
 
 /**
- * ieee80211_get_hdrlen - get header length from frame control
- *
- * This function returns the 802.11 header length in bytes (not including
- * encryption headers.)
- *
- * @fc: the frame control field (in CPU endianness)
- */
-int ieee80211_get_hdrlen(u16 fc);
-
-/**
  * ieee80211_hdrlen - get header length in bytes from frame control
  * @fc: frame control field in little-endian format
  */
@@ -1608,6 +1649,16 @@ void ieee80211_wake_queue(struct ieee80211_hw *hw, int queue);
 void ieee80211_stop_queue(struct ieee80211_hw *hw, int queue);
 
 /**
+ * ieee80211_queue_stopped - test status of the queue
+ * @hw: pointer as obtained from ieee80211_alloc_hw().
+ * @queue: queue number (counted from zero).
+ *
+ * Drivers should use this function instead of netif_stop_queue.
+ */
+
+int ieee80211_queue_stopped(struct ieee80211_hw *hw, int queue);
+
+/**
  * ieee80211_stop_queues - stop all queues
  * @hw: pointer as obtained from ieee80211_alloc_hw().
  *
@@ -1758,4 +1809,85 @@ void ieee80211_stop_tx_ba_cb_irqsafe(struct ieee80211_hw *hw, const u8 *ra,
  */
 void ieee80211_notify_mac(struct ieee80211_hw *hw,
                           enum ieee80211_notification_types  notif_type);
+
+/**
+ * ieee80211_find_sta - find a station
+ *
+ * @hw: pointer as obtained from ieee80211_alloc_hw()
+ * @addr: station's address
+ *
+ * This function must be called under RCU lock and the
+ * resulting pointer is only valid under RCU lock as well.
+ */
+struct ieee80211_sta *ieee80211_find_sta(struct ieee80211_hw *hw,
+                                         const u8 *addr);
+
+
+/* Rate control API */
+/**
+ * struct rate_selection - rate information for/from rate control algorithms
+ *
+ * @rate_idx: selected transmission rate index
+ * @nonerp_idx: Non-ERP rate to use instead if ERP cannot be used
+ * @probe_idx: rate for probing (or -1)
+ * @max_rate_idx: maximum rate index that can be used, this is
+ *      input to the algorithm and will be enforced
+ */
+struct rate_selection {
+        s8 rate_idx, nonerp_idx, probe_idx, max_rate_idx;
+};
+
+struct rate_control_ops {
+        struct module *module;
+        const char *name;
+        void *(*alloc)(struct ieee80211_hw *hw, struct dentry *debugfsdir);
+        void (*clear)(void *priv);
+        void (*free)(void *priv);
+
+        void *(*alloc_sta)(void *priv, struct ieee80211_sta *sta, gfp_t gfp);
+        void (*rate_init)(void *priv, struct ieee80211_supported_band *sband,
+                          struct ieee80211_sta *sta, void *priv_sta);
+        void (*free_sta)(void *priv, struct ieee80211_sta *sta,
+                         void *priv_sta);
+
+        void (*tx_status)(void *priv, struct ieee80211_supported_band *sband,
+                          struct ieee80211_sta *sta, void *priv_sta,
+                          struct sk_buff *skb);
+        void (*get_rate)(void *priv, struct ieee80211_supported_band *sband,
+                         struct ieee80211_sta *sta, void *priv_sta,
+                         struct sk_buff *skb,
+                         struct rate_selection *sel);
+
+        void (*add_sta_debugfs)(void *priv, void *priv_sta,
+                                struct dentry *dir);
+        void (*remove_sta_debugfs)(void *priv, void *priv_sta);
+};
+
+static inline int rate_supported(struct ieee80211_sta *sta,
+                                 enum ieee80211_band band,
+                                 int index)
+{
+        return (sta == NULL || sta->supp_rates[band] & BIT(index));
+}
+
+static inline s8
+rate_lowest_index(struct ieee80211_supported_band *sband,
+                  struct ieee80211_sta *sta)
+{
+        int i;
+
+        for (i = 0; i < sband->n_bitrates; i++)
+                if (rate_supported(sta, sband->band, i))
+                        return i;
+
+        /* warn when we cannot find a rate. */
+        WARN_ON(1);
+
+        return 0;
+}
+
+
+int ieee80211_rate_control_register(struct rate_control_ops *ops);
+void ieee80211_rate_control_unregister(struct rate_control_ops *ops);
+
 #endif /* MAC80211_H */
diff --git a/include/net/ndisc.h b/include/net/ndisc.h
index a01b7c4dc763..11dd0137c6a5 100644
--- a/include/net/ndisc.h
+++ b/include/net/ndisc.h
@@ -129,9 +129,8 @@ extern int 			ndisc_ifinfo_sysctl_change(struct ctl_table *ctl,
                                                            void __user *buffer,
                                                            size_t *lenp,
                                                            loff_t *ppos);
-int ndisc_ifinfo_sysctl_strategy(ctl_table *ctl, int __user *name,
-                                 int nlen, void __user *oldval,
-                                 size_t __user *oldlenp,
+int ndisc_ifinfo_sysctl_strategy(ctl_table *ctl,
+                                 void __user *oldval, size_t __user *oldlenp,
                                  void __user *newval, size_t newlen);
 #endif
 
diff --git a/include/net/net_namespace.h b/include/net/net_namespace.h
index a8eb43cf0c7e..708009be88b6 100644
--- a/include/net/net_namespace.h
+++ b/include/net/net_namespace.h
@@ -16,6 +16,9 @@
 #include <net/netns/ipv6.h>
 #include <net/netns/dccp.h>
 #include <net/netns/x_tables.h>
+#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
+#include <net/netns/conntrack.h>
+#endif
 
 struct proc_dir_entry;
 struct net_device;
@@ -67,6 +70,9 @@ struct net {
 #endif
 #ifdef CONFIG_NETFILTER
         struct netns_xt         xt;
+#if defined(CONFIG_NF_CONNTRACK) || defined(CONFIG_NF_CONNTRACK_MODULE)
+        struct netns_ct         ct;
+#endif
 #endif
         struct net_generic      *gen;
 };
diff --git a/include/net/netfilter/ipv4/nf_defrag_ipv4.h b/include/net/netfilter/ipv4/nf_defrag_ipv4.h
new file mode 100644
index 000000000000..6b00ea38546b
--- /dev/null
+++ b/include/net/netfilter/ipv4/nf_defrag_ipv4.h
@@ -0,0 +1,6 @@
+#ifndef _NF_DEFRAG_IPV4_H
+#define _NF_DEFRAG_IPV4_H
+
+extern void nf_defrag_ipv4_enable(void);
+
+#endif /* _NF_DEFRAG_IPV4_H */
diff --git a/include/net/netfilter/nf_conntrack.h b/include/net/netfilter/nf_conntrack.h
index 0741ad592da0..b76a8685b5b5 100644
--- a/include/net/netfilter/nf_conntrack.h
+++ b/include/net/netfilter/nf_conntrack.h
@@ -123,7 +123,9 @@ struct nf_conn
 
         /* Extensions */
         struct nf_ct_ext *ext;
-
+#ifdef CONFIG_NET_NS
+        struct net *ct_net;
+#endif
         struct rcu_head rcu;
 };
 
@@ -147,6 +149,17 @@ static inline u_int8_t nf_ct_protonum(const struct nf_conn *ct)
 /* get master conntrack via master expectation */
 #define master_ct(conntr) (conntr->master)
 
+extern struct net init_net;
+
+static inline struct net *nf_ct_net(const struct nf_conn *ct)
+{
+#ifdef CONFIG_NET_NS
+        return ct->ct_net;
+#else
+        return &init_net;
+#endif
+}
+
 /* Alter reply tuple (maybe alter helper). */
 extern void
 nf_conntrack_alter_reply(struct nf_conn *ct,
@@ -182,11 +195,11 @@ extern void nf_ct_free_hashtable(struct hlist_head *hash, int vmalloced,
                                  unsigned int size);
 
 extern struct nf_conntrack_tuple_hash *
-__nf_conntrack_find(const struct nf_conntrack_tuple *tuple);
+__nf_conntrack_find(struct net *net, const struct nf_conntrack_tuple *tuple);
 
 extern void nf_conntrack_hash_insert(struct nf_conn *ct);
 
-extern void nf_conntrack_flush(void);
+extern void nf_conntrack_flush(struct net *net);
 
 extern bool nf_ct_get_tuplepr(const struct sk_buff *skb,
                               unsigned int nhoff, u_int16_t l3num,
@@ -248,10 +261,11 @@ extern struct nf_conn nf_conntrack_untracked;
 
 /* Iterate over all conntracks: if iter returns true, it's deleted. */
 extern void
-nf_ct_iterate_cleanup(int (*iter)(struct nf_conn *i, void *data), void *data);
+nf_ct_iterate_cleanup(struct net *net, int (*iter)(struct nf_conn *i, void *data), void *data);
 extern void nf_conntrack_free(struct nf_conn *ct);
 extern struct nf_conn *
-nf_conntrack_alloc(const struct nf_conntrack_tuple *orig,
+nf_conntrack_alloc(struct net *net,
+                   const struct nf_conntrack_tuple *orig,
                    const struct nf_conntrack_tuple *repl,
                    gfp_t gfp);
 
@@ -273,16 +287,14 @@ static inline int nf_ct_is_untracked(const struct sk_buff *skb)
 
 extern int nf_conntrack_set_hashsize(const char *val, struct kernel_param *kp);
 extern unsigned int nf_conntrack_htable_size;
-extern int nf_conntrack_checksum;
-extern atomic_t nf_conntrack_count;
 extern int nf_conntrack_max;
 
-DECLARE_PER_CPU(struct ip_conntrack_stat, nf_conntrack_stat);
-#define NF_CT_STAT_INC(count) (__get_cpu_var(nf_conntrack_stat).count++)
-#define NF_CT_STAT_INC_ATOMIC(count)                    \
+#define NF_CT_STAT_INC(net, count)      \
+        (per_cpu_ptr((net)->ct.stat, raw_smp_processor_id())->count++)
+#define NF_CT_STAT_INC_ATOMIC(net, count)               \
 do {                                                    \
         local_bh_disable();                             \
-        __get_cpu_var(nf_conntrack_stat).count++;       \
+        per_cpu_ptr((net)->ct.stat, raw_smp_processor_id())->count++;   \
         local_bh_enable();                              \
 } while (0)
 
diff --git a/include/net/netfilter/nf_conntrack_acct.h b/include/net/netfilter/nf_conntrack_acct.h
index 5d5ae55d54c4..03e218f0be43 100644
--- a/include/net/netfilter/nf_conntrack_acct.h
+++ b/include/net/netfilter/nf_conntrack_acct.h
@@ -8,6 +8,7 @@
 
 #ifndef _NF_CONNTRACK_ACCT_H
 #define _NF_CONNTRACK_ACCT_H
+#include <net/net_namespace.h>
 #include <linux/netfilter/nf_conntrack_common.h>
 #include <linux/netfilter/nf_conntrack_tuple_common.h>
 #include <net/netfilter/nf_conntrack.h>
@@ -18,8 +19,6 @@ struct nf_conn_counter {
         u_int64_t bytes;
 };
 
-extern int nf_ct_acct;
-
 static inline
 struct nf_conn_counter *nf_conn_acct_find(const struct nf_conn *ct)
 {
@@ -29,9 +28,10 @@ struct nf_conn_counter *nf_conn_acct_find(const struct nf_conn *ct)
 static inline
 struct nf_conn_counter *nf_ct_acct_ext_add(struct nf_conn *ct, gfp_t gfp)
 {
+        struct net *net = nf_ct_net(ct);
         struct nf_conn_counter *acct;
 
-        if (!nf_ct_acct)
+        if (!net->ct.sysctl_acct)
                 return NULL;
 
         acct = nf_ct_ext_add(ct, NF_CT_EXT_ACCT, gfp);
@@ -45,7 +45,7 @@ struct nf_conn_counter *nf_ct_acct_ext_add(struct nf_conn *ct, gfp_t gfp)
 extern unsigned int
 seq_print_acct(struct seq_file *s, const struct nf_conn *ct, int dir);
 
-extern int nf_conntrack_acct_init(void);
-extern void nf_conntrack_acct_fini(void);
+extern int nf_conntrack_acct_init(struct net *net);
+extern void nf_conntrack_acct_fini(struct net *net);
 
 #endif /* _NF_CONNTRACK_ACCT_H */
diff --git a/include/net/netfilter/nf_conntrack_core.h b/include/net/netfilter/nf_conntrack_core.h
index a81771210934..e78afe7f28e3 100644
--- a/include/net/netfilter/nf_conntrack_core.h
+++ b/include/net/netfilter/nf_conntrack_core.h
@@ -20,12 +20,13 @@
 /* This header is used to share core functionality between the
    standalone connection tracking module, and the compatibility layer's use
    of connection tracking. */
-extern unsigned int nf_conntrack_in(int pf,
+extern unsigned int nf_conntrack_in(struct net *net,
+                                    u_int8_t pf,
                                     unsigned int hooknum,
                                     struct sk_buff *skb);
 
-extern int nf_conntrack_init(void);
-extern void nf_conntrack_cleanup(void);
+extern int nf_conntrack_init(struct net *net);
+extern void nf_conntrack_cleanup(struct net *net);
 
 extern int nf_conntrack_proto_init(void);
 extern void nf_conntrack_proto_fini(void);
@@ -48,7 +49,7 @@ nf_ct_invert_tuple(struct nf_conntrack_tuple *inverse,
 
 /* Find a connection corresponding to a tuple. */
 extern struct nf_conntrack_tuple_hash *
-nf_conntrack_find_get(const struct nf_conntrack_tuple *tuple);
+nf_conntrack_find_get(struct net *net, const struct nf_conntrack_tuple *tuple);
 
 extern int __nf_conntrack_confirm(struct sk_buff *skb);
 
@@ -71,8 +72,6 @@ print_tuple(struct seq_file *s, const struct nf_conntrack_tuple *tuple,
             const struct nf_conntrack_l3proto *l3proto,
             const struct nf_conntrack_l4proto *proto);
 
-extern struct hlist_head *nf_conntrack_hash;
 extern spinlock_t nf_conntrack_lock ;
-extern struct hlist_head unconfirmed;
 
 #endif /* _NF_CONNTRACK_CORE_H */
diff --git a/include/net/netfilter/nf_conntrack_ecache.h b/include/net/netfilter/nf_conntrack_ecache.h
index f0b9078235c9..1285ff26a014 100644
--- a/include/net/netfilter/nf_conntrack_ecache.h
+++ b/include/net/netfilter/nf_conntrack_ecache.h
@@ -8,6 +8,7 @@
 
 #include <linux/notifier.h>
 #include <linux/interrupt.h>
+#include <net/net_namespace.h>
 #include <net/netfilter/nf_conntrack_expect.h>
 
 #ifdef CONFIG_NF_CONNTRACK_EVENTS
@@ -15,9 +16,6 @@ struct nf_conntrack_ecache {
         struct nf_conn *ct;
         unsigned int events;
 };
-DECLARE_PER_CPU(struct nf_conntrack_ecache, nf_conntrack_ecache);
-
-#define CONNTRACK_ECACHE(x)     (__get_cpu_var(nf_conntrack_ecache).x)
 
 extern struct atomic_notifier_head nf_conntrack_chain;
 extern int nf_conntrack_register_notifier(struct notifier_block *nb);
@@ -25,17 +23,16 @@ extern int nf_conntrack_unregister_notifier(struct notifier_block *nb);
 
 extern void nf_ct_deliver_cached_events(const struct nf_conn *ct);
 extern void __nf_ct_event_cache_init(struct nf_conn *ct);
-extern void nf_ct_event_cache_flush(void);
+extern void nf_ct_event_cache_flush(struct net *net);
 
 static inline void
-nf_conntrack_event_cache(enum ip_conntrack_events event,
-                         const struct sk_buff *skb)
+nf_conntrack_event_cache(enum ip_conntrack_events event, struct nf_conn *ct)
 {
-        struct nf_conn *ct = (struct nf_conn *)skb->nfct;
+        struct net *net = nf_ct_net(ct);
         struct nf_conntrack_ecache *ecache;
 
         local_bh_disable();
-        ecache = &__get_cpu_var(nf_conntrack_ecache);
+        ecache = per_cpu_ptr(net->ct.ecache, raw_smp_processor_id());
         if (ct != ecache->ct)
                 __nf_ct_event_cache_init(ct);
         ecache->events |= event;
@@ -60,16 +57,28 @@ nf_ct_expect_event(enum ip_conntrack_expect_events event,
         atomic_notifier_call_chain(&nf_ct_expect_chain, event, exp);
 }
 
+extern int nf_conntrack_ecache_init(struct net *net);
+extern void nf_conntrack_ecache_fini(struct net *net);
+
 #else /* CONFIG_NF_CONNTRACK_EVENTS */
 
 static inline void nf_conntrack_event_cache(enum ip_conntrack_events event,
-                                            const struct sk_buff *skb) {}
+                                            struct nf_conn *ct) {}
 static inline void nf_conntrack_event(enum ip_conntrack_events event,
                                       struct nf_conn *ct) {}
 static inline void nf_ct_deliver_cached_events(const struct nf_conn *ct) {}
 static inline void nf_ct_expect_event(enum ip_conntrack_expect_events event,
                                       struct nf_conntrack_expect *exp) {}
-static inline void nf_ct_event_cache_flush(void) {}
+static inline void nf_ct_event_cache_flush(struct net *net) {}
+
+static inline int nf_conntrack_ecache_init(struct net *net)
+{
+        return 0;
+}
+
+static inline void nf_conntrack_ecache_fini(struct net *net)
+{
+}
 #endif /* CONFIG_NF_CONNTRACK_EVENTS */
 
 #endif /*_NF_CONNTRACK_ECACHE_H*/
diff --git a/include/net/netfilter/nf_conntrack_expect.h b/include/net/netfilter/nf_conntrack_expect.h
index dfdf4b459475..37a7fc1164b0 100644
--- a/include/net/netfilter/nf_conntrack_expect.h
+++ b/include/net/netfilter/nf_conntrack_expect.h
@@ -6,7 +6,6 @@
 #define _NF_CONNTRACK_EXPECT_H
 #include <net/netfilter/nf_conntrack.h>
 
-extern struct hlist_head *nf_ct_expect_hash;
 extern unsigned int nf_ct_expect_hsize;
 extern unsigned int nf_ct_expect_max;
 
@@ -56,6 +55,15 @@ struct nf_conntrack_expect
         struct rcu_head rcu;
 };
 
+static inline struct net *nf_ct_exp_net(struct nf_conntrack_expect *exp)
+{
+#ifdef CONFIG_NET_NS
+        return exp->master->ct_net;     /* by definition */
+#else
+        return &init_net;
+#endif
+}
+
 struct nf_conntrack_expect_policy
 {
         unsigned int    max_expected;
@@ -67,17 +75,17 @@ struct nf_conntrack_expect_policy
 #define NF_CT_EXPECT_PERMANENT  0x1
 #define NF_CT_EXPECT_INACTIVE   0x2
 
-int nf_conntrack_expect_init(void);
-void nf_conntrack_expect_fini(void);
+int nf_conntrack_expect_init(struct net *net);
+void nf_conntrack_expect_fini(struct net *net);
 
 struct nf_conntrack_expect *
-__nf_ct_expect_find(const struct nf_conntrack_tuple *tuple);
+__nf_ct_expect_find(struct net *net, const struct nf_conntrack_tuple *tuple);
 
 struct nf_conntrack_expect *
-nf_ct_expect_find_get(const struct nf_conntrack_tuple *tuple);
+nf_ct_expect_find_get(struct net *net, const struct nf_conntrack_tuple *tuple);
 
 struct nf_conntrack_expect *
-nf_ct_find_expectation(const struct nf_conntrack_tuple *tuple);
+nf_ct_find_expectation(struct net *net, const struct nf_conntrack_tuple *tuple);
 
 void nf_ct_unlink_expect(struct nf_conntrack_expect *exp);
 void nf_ct_remove_expectations(struct nf_conn *ct);
@@ -86,7 +94,7 @@ void nf_ct_unexpect_related(struct nf_conntrack_expect *exp);
 /* Allocate space for an expectation: this is mandatory before calling
    nf_ct_expect_related.  You will have to call put afterwards. */
 struct nf_conntrack_expect *nf_ct_expect_alloc(struct nf_conn *me);
-void nf_ct_expect_init(struct nf_conntrack_expect *, unsigned int, int,
+void nf_ct_expect_init(struct nf_conntrack_expect *, unsigned int, u_int8_t,
                        const union nf_inet_addr *,
                        const union nf_inet_addr *,
                        u_int8_t, const __be16 *, const __be16 *);
diff --git a/include/net/netfilter/nf_conntrack_l4proto.h b/include/net/netfilter/nf_conntrack_l4proto.h
index 723df9d1cc35..7f2f43c77284 100644
--- a/include/net/netfilter/nf_conntrack_l4proto.h
+++ b/include/net/netfilter/nf_conntrack_l4proto.h
@@ -39,7 +39,7 @@ struct nf_conntrack_l4proto
                       const struct sk_buff *skb,
                       unsigned int dataoff,
                       enum ip_conntrack_info ctinfo,
-                      int pf,
+                      u_int8_t pf,
                       unsigned int hooknum);
 
         /* Called when a new connection for this protocol found;
@@ -50,9 +50,9 @@ struct nf_conntrack_l4proto
         /* Called when a conntrack entry is destroyed */
         void (*destroy)(struct nf_conn *ct);
 
-        int (*error)(struct sk_buff *skb, unsigned int dataoff,
+        int (*error)(struct net *net, struct sk_buff *skb, unsigned int dataoff,
                      enum ip_conntrack_info *ctinfo,
-                     int pf, unsigned int hooknum);
+                     u_int8_t pf, unsigned int hooknum);
 
         /* Print out the per-protocol part of the tuple. Return like seq_* */
         int (*print_tuple)(struct seq_file *s,
@@ -117,20 +117,19 @@ extern int nf_ct_port_nlattr_to_tuple(struct nlattr *tb[],
                                       struct nf_conntrack_tuple *t);
 extern const struct nla_policy nf_ct_port_nla_policy[];
 
-/* Log invalid packets */
-extern unsigned int nf_ct_log_invalid;
-
 #ifdef CONFIG_SYSCTL
 #ifdef DEBUG_INVALID_PACKETS
-#define LOG_INVALID(proto) \
-        (nf_ct_log_invalid == (proto) || nf_ct_log_invalid == IPPROTO_RAW)
+#define LOG_INVALID(net, proto)                         \
+        ((net)->ct.sysctl_log_invalid == (proto) ||     \
+         (net)->ct.sysctl_log_invalid == IPPROTO_RAW)
 #else
-#define LOG_INVALID(proto) \
-        ((nf_ct_log_invalid == (proto) || nf_ct_log_invalid == IPPROTO_RAW) \
+#define LOG_INVALID(net, proto)                         \
+        (((net)->ct.sysctl_log_invalid == (proto) ||    \
+          (net)->ct.sysctl_log_invalid == IPPROTO_RAW)  \
          && net_ratelimit())
 #endif
 #else
-#define LOG_INVALID(proto) 0
+#define LOG_INVALID(net, proto) 0
 #endif /* CONFIG_SYSCTL */
 
 #endif /*_NF_CONNTRACK_PROTOCOL_H*/
diff --git a/include/net/netfilter/nf_log.h b/include/net/netfilter/nf_log.h
index 8c6b5ae45534..7182c06974f4 100644
--- a/include/net/netfilter/nf_log.h
+++ b/include/net/netfilter/nf_log.h
@@ -28,7 +28,7 @@ struct nf_loginfo {
         } u;
 };
 
-typedef void nf_logfn(unsigned int pf,
+typedef void nf_logfn(u_int8_t pf,
                       unsigned int hooknum,
                       const struct sk_buff *skb,
                       const struct net_device *in,
@@ -43,12 +43,12 @@ struct nf_logger {
 };
 
 /* Function to register/unregister log function. */
-int nf_log_register(int pf, const struct nf_logger *logger);
+int nf_log_register(u_int8_t pf, const struct nf_logger *logger);
 void nf_log_unregister(const struct nf_logger *logger);
-void nf_log_unregister_pf(int pf);
+void nf_log_unregister_pf(u_int8_t pf);
 
 /* Calls the registered backend logging function */
-void nf_log_packet(int pf,
+void nf_log_packet(u_int8_t pf,
                    unsigned int hooknum,
                    const struct sk_buff *skb,
                    const struct net_device *in,
diff --git a/include/net/netfilter/nf_nat_core.h b/include/net/netfilter/nf_nat_core.h
index f29eeb9777e0..58684066388c 100644
--- a/include/net/netfilter/nf_nat_core.h
+++ b/include/net/netfilter/nf_nat_core.h
@@ -25,4 +25,12 @@ static inline int nf_nat_initialized(struct nf_conn *ct,
         else
                 return test_bit(IPS_DST_NAT_DONE_BIT, &ct->status);
 }
+
+struct nlattr;
+
+extern int
+(*nfnetlink_parse_nat_setup_hook)(struct nf_conn *ct,
+                                  enum nf_nat_manip_type manip,
+                                  struct nlattr *attr);
+
 #endif /* _NF_NAT_CORE_H */
diff --git a/include/net/netfilter/nf_queue.h b/include/net/netfilter/nf_queue.h
index d030044e9235..252fd1010b77 100644
--- a/include/net/netfilter/nf_queue.h
+++ b/include/net/netfilter/nf_queue.h
@@ -8,7 +8,7 @@ struct nf_queue_entry {
         unsigned int            id;
 
         struct nf_hook_ops      *elem;
-        int                     pf;
+        u_int8_t                pf;
         unsigned int            hook;
         struct net_device       *indev;
         struct net_device       *outdev;
@@ -24,9 +24,9 @@ struct nf_queue_handler {
         char                    *name;
 };
 
-extern int nf_register_queue_handler(int pf,
+extern int nf_register_queue_handler(u_int8_t pf,
                                      const struct nf_queue_handler *qh);
-extern int nf_unregister_queue_handler(int pf,
+extern int nf_unregister_queue_handler(u_int8_t pf,
                                        const struct nf_queue_handler *qh);
 extern void nf_unregister_queue_handlers(const struct nf_queue_handler *qh);
 extern void nf_reinject(struct nf_queue_entry *entry, unsigned int verdict);
diff --git a/include/net/netfilter/nf_tproxy_core.h b/include/net/netfilter/nf_tproxy_core.h
new file mode 100644
index 000000000000..208b46f4d6d2
--- /dev/null
+++ b/include/net/netfilter/nf_tproxy_core.h
@@ -0,0 +1,32 @@
+#ifndef _NF_TPROXY_CORE_H
+#define _NF_TPROXY_CORE_H
+
+#include <linux/types.h>
+#include <linux/in.h>
+#include <linux/skbuff.h>
+#include <net/sock.h>
+#include <net/inet_sock.h>
+#include <net/tcp.h>
+
+/* look up and get a reference to a matching socket */
+extern struct sock *
+nf_tproxy_get_sock_v4(struct net *net, const u8 protocol,
+                      const __be32 saddr, const __be32 daddr,
+                      const __be16 sport, const __be16 dport,
+                      const struct net_device *in, bool listening);
+
+static inline void
+nf_tproxy_put_sock(struct sock *sk)
+{
+        /* TIME_WAIT inet sockets have to be handled differently */
+        if ((sk->sk_protocol == IPPROTO_TCP) && (sk->sk_state == TCP_TIME_WAIT))
+                inet_twsk_put(inet_twsk(sk));
+        else
+                sock_put(sk);
+}
+
+/* assign a socket to the skb -- consumes sk */
+int
+nf_tproxy_assign_sock(struct sk_buff *skb, struct sock *sk);
+
+#endif
diff --git a/include/net/netlabel.h b/include/net/netlabel.h
index e4d2d6baa983..17c442a4514e 100644
--- a/include/net/netlabel.h
+++ b/include/net/netlabel.h
@@ -9,7 +9,7 @@
  */
 
 /*
- * (c) Copyright Hewlett-Packard Development Company, L.P., 2006
+ * (c) Copyright Hewlett-Packard Development Company, L.P., 2006, 2008
  *
  * This program is free software;  you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -72,8 +72,10 @@ struct cipso_v4_doi;
 /* NetLabel NETLINK protocol version
  *  1: initial version
  *  2: added static labels for unlabeled connections
+ *  3: network selectors added to the NetLabel/LSM domain mapping and the
+ *     CIPSO_V4_MAP_LOCAL CIPSO mapping was added
  */
-#define NETLBL_PROTO_VERSION            2
+#define NETLBL_PROTO_VERSION            3
 
 /* NetLabel NETLINK types/families */
 #define NETLBL_NLTYPE_NONE              0
@@ -87,6 +89,8 @@ struct cipso_v4_doi;
 #define NETLBL_NLTYPE_CIPSOV6_NAME      "NLBL_CIPSOv6"
 #define NETLBL_NLTYPE_UNLABELED         5
 #define NETLBL_NLTYPE_UNLABELED_NAME    "NLBL_UNLBL"
+#define NETLBL_NLTYPE_ADDRSELECT        6
+#define NETLBL_NLTYPE_ADDRSELECT_NAME   "NLBL_ADRSEL"
 
 /*
  * NetLabel - Kernel API for accessing the network packet label mappings.
@@ -200,7 +204,7 @@ struct netlbl_lsm_secattr {
         u32 type;
         char *domain;
         struct netlbl_lsm_cache *cache;
-        union {
+        struct {
                 struct {
                         struct netlbl_lsm_secattr_catmap *cat;
                         u32 lvl;
@@ -352,12 +356,9 @@ static inline void netlbl_secattr_free(struct netlbl_lsm_secattr *secattr)
 int netlbl_cfg_map_del(const char *domain, struct netlbl_audit *audit_info);
 int netlbl_cfg_unlbl_add_map(const char *domain,
                              struct netlbl_audit *audit_info);
-int netlbl_cfg_cipsov4_add(struct cipso_v4_doi *doi_def,
-                           struct netlbl_audit *audit_info);
 int netlbl_cfg_cipsov4_add_map(struct cipso_v4_doi *doi_def,
                                const char *domain,
                                struct netlbl_audit *audit_info);
-int netlbl_cfg_cipsov4_del(u32 doi, struct netlbl_audit *audit_info);
 
 /*
  * LSM security attribute operations
@@ -380,12 +381,19 @@ int netlbl_secattr_catmap_setrng(struct netlbl_lsm_secattr_catmap *catmap,
 int netlbl_enabled(void);
 int netlbl_sock_setattr(struct sock *sk,
                         const struct netlbl_lsm_secattr *secattr);
+void netlbl_sock_delattr(struct sock *sk);
 int netlbl_sock_getattr(struct sock *sk,
                         struct netlbl_lsm_secattr *secattr);
+int netlbl_conn_setattr(struct sock *sk,
+                        struct sockaddr *addr,
+                        const struct netlbl_lsm_secattr *secattr);
+int netlbl_skbuff_setattr(struct sk_buff *skb,
+                          u16 family,
+                          const struct netlbl_lsm_secattr *secattr);
 int netlbl_skbuff_getattr(const struct sk_buff *skb,
                           u16 family,
                           struct netlbl_lsm_secattr *secattr);
-void netlbl_skbuff_err(struct sk_buff *skb, int error);
+void netlbl_skbuff_err(struct sk_buff *skb, int error, int gateway);
 
 /*
  * LSM label mapping cache operations
@@ -404,22 +412,12 @@ static inline int netlbl_cfg_unlbl_add_map(const char *domain,
 {
         return -ENOSYS;
 }
-static inline int netlbl_cfg_cipsov4_add(struct cipso_v4_doi *doi_def,
-                                         struct netlbl_audit *audit_info)
-{
-        return -ENOSYS;
-}
 static inline int netlbl_cfg_cipsov4_add_map(struct cipso_v4_doi *doi_def,
                                              const char *domain,
                                              struct netlbl_audit *audit_info)
 {
         return -ENOSYS;
 }
-static inline int netlbl_cfg_cipsov4_del(u32 doi,
-                                         struct netlbl_audit *audit_info)
-{
-        return -ENOSYS;
-}
 static inline int netlbl_secattr_catmap_walk(
                                       struct netlbl_lsm_secattr_catmap *catmap,
                                       u32 offset)
@@ -456,18 +454,35 @@ static inline int netlbl_sock_setattr(struct sock *sk,
 {
         return -ENOSYS;
 }
+static inline void netlbl_sock_delattr(struct sock *sk)
+{
+}
 static inline int netlbl_sock_getattr(struct sock *sk,
                                       struct netlbl_lsm_secattr *secattr)
 {
         return -ENOSYS;
 }
+static inline int netlbl_conn_setattr(struct sock *sk,
+                                      struct sockaddr *addr,
+                                      const struct netlbl_lsm_secattr *secattr)
+{
+        return -ENOSYS;
+}
+static inline int netlbl_skbuff_setattr(struct sk_buff *skb,
+                                      u16 family,
+                                      const struct netlbl_lsm_secattr *secattr)
+{
+        return -ENOSYS;
+}
 static inline int netlbl_skbuff_getattr(const struct sk_buff *skb,
                                         u16 family,
                                         struct netlbl_lsm_secattr *secattr)
 {
         return -ENOSYS;
 }
-static inline void netlbl_skbuff_err(struct sk_buff *skb, int error)
+static inline void netlbl_skbuff_err(struct sk_buff *skb,
+                                     int error,
+                                     int gateway)
 {
         return;
 }
diff --git a/include/net/netlink.h b/include/net/netlink.h
index 18024b8cecb8..3643bbb8e585 100644
--- a/include/net/netlink.h
+++ b/include/net/netlink.h
@@ -119,9 +119,6 @@
  * Nested Attributes Construction:
  *   nla_nest_start(skb, type)          start a nested attribute
  *   nla_nest_end(skb, nla)             finalize a nested attribute
- *   nla_nest_compat_start(skb, type,   start a nested compat attribute
- *                         len, data)
- *   nla_nest_compat_end(skb, type)     finalize a nested compat attribute
  *   nla_nest_cancel(skb, nla)          cancel nested attribute construction
  *
  * Attribute Length Calculations:
@@ -156,7 +153,6 @@
  *   nla_find_nested()                  find attribute in nested attributes
  *   nla_parse()                        parse and validate stream of attrs
  *   nla_parse_nested()                 parse nested attribuets
- *   nla_parse_nested_compat()          parse nested compat attributes
  *   nla_for_each_attr()                loop over all attributes
  *   nla_for_each_nested()              loop over the nested attributes
  *=========================================================================
@@ -702,7 +698,7 @@ static inline int nla_len(const struct nlattr *nla)
  */
 static inline int nla_ok(const struct nlattr *nla, int remaining)
 {
-        return remaining >= sizeof(*nla) &&
+        return remaining >= (int) sizeof(*nla) &&
                nla->nla_len >= sizeof(*nla) &&
                nla->nla_len <= remaining;
 }
@@ -752,39 +748,6 @@ static inline int nla_parse_nested(struct nlattr *tb[], int maxtype,
 }
 
 /**
- * nla_parse_nested_compat - parse nested compat attributes
- * @tb: destination array with maxtype+1 elements
- * @maxtype: maximum attribute type to be expected
- * @nla: attribute containing the nested attributes
- * @data: pointer to point to contained structure
- * @len: length of contained structure
- * @policy: validation policy
- *
- * Parse a nested compat attribute. The compat attribute contains a structure
- * and optionally a set of nested attributes. On success the data pointer
- * points to the nested data and tb contains the parsed attributes
- * (see nla_parse).
- */
-static inline int __nla_parse_nested_compat(struct nlattr *tb[], int maxtype,
-                                            struct nlattr *nla,
-                                            const struct nla_policy *policy,
-                                            int len)
-{
-        int nested_len = nla_len(nla) - NLA_ALIGN(len);
-
-        if (nested_len < 0)
-                return -EINVAL;
-        if (nested_len >= nla_attr_size(0))
-                return nla_parse(tb, maxtype, nla_data(nla) + NLA_ALIGN(len),
-                                 nested_len, policy);
-        memset(tb, 0, sizeof(struct nlattr *) * (maxtype + 1));
-        return 0;
-}
-
-#define nla_parse_nested_compat(tb, maxtype, nla, policy, data, len) \
-({      data = nla_len(nla) >= len ? nla_data(nla) : NULL; \
-        __nla_parse_nested_compat(tb, maxtype, nla, policy, len); })
-/**
  * nla_put_u8 - Add a u8 netlink attribute to a socket buffer
  * @skb: socket buffer to add attribute to
  * @attrtype: attribute type
@@ -1031,51 +994,6 @@ static inline int nla_nest_end(struct sk_buff *skb, struct nlattr *start)
 }
 
 /**
- * nla_nest_compat_start - Start a new level of nested compat attributes
- * @skb: socket buffer to add attributes to
- * @attrtype: attribute type of container
- * @attrlen: length of structure
- * @data: pointer to structure
- *
- * Start a nested compat attribute that contains both a structure and
- * a set of nested attributes.
- *
- * Returns the container attribute
- */
-static inline struct nlattr *nla_nest_compat_start(struct sk_buff *skb,
-                                                   int attrtype, int attrlen,
-                                                   const void *data)
-{
-        struct nlattr *start = (struct nlattr *)skb_tail_pointer(skb);
-
-        if (nla_put(skb, attrtype, attrlen, data) < 0)
-                return NULL;
-        if (nla_nest_start(skb, attrtype) == NULL) {
-                nlmsg_trim(skb, start);
-                return NULL;
-        }
-        return start;
-}
-
-/**
- * nla_nest_compat_end - Finalize nesting of compat attributes
- * @skb: socket buffer the attributes are stored in
- * @start: container attribute
- *
- * Corrects the container attribute header to include the all
- * appeneded attributes.
- *
- * Returns the total data length of the skb.
- */
-static inline int nla_nest_compat_end(struct sk_buff *skb, struct nlattr *start)
-{
-        struct nlattr *nest = (void *)start + NLMSG_ALIGN(start->nla_len);
-
-        start->nla_len = skb_tail_pointer(skb) - (unsigned char *)start;
-        return nla_nest_end(skb, nest);
-}
-
-/**
  * nla_nest_cancel - Cancel nesting of attributes
  * @skb: socket buffer the message is stored in
  * @start: container attribute
diff --git a/include/net/netns/conntrack.h b/include/net/netns/conntrack.h
new file mode 100644
index 000000000000..f4498a62881b
--- /dev/null
+++ b/include/net/netns/conntrack.h
@@ -0,0 +1,30 @@
+#ifndef __NETNS_CONNTRACK_H
+#define __NETNS_CONNTRACK_H
+
+#include <linux/list.h>
+#include <asm/atomic.h>
+
+struct ctl_table_header;
+struct nf_conntrack_ecache;
+
+struct netns_ct {
+        atomic_t                count;
+        unsigned int            expect_count;
+        struct hlist_head       *hash;
+        struct hlist_head       *expect_hash;
+        struct hlist_head       unconfirmed;
+        struct ip_conntrack_stat *stat;
+#ifdef CONFIG_NF_CONNTRACK_EVENTS
+        struct nf_conntrack_ecache *ecache;
+#endif
+        int                     sysctl_acct;
+        int                     sysctl_checksum;
+        unsigned int            sysctl_log_invalid; /* Log invalid packets */
+#ifdef CONFIG_SYSCTL
+        struct ctl_table_header *sysctl_header;
+        struct ctl_table_header *acct_sysctl_header;
+#endif
+        int                     hash_vmalloc;
+        int                     expect_vmalloc;
+};
+#endif
diff --git a/include/net/netns/ipv4.h b/include/net/netns/ipv4.h
index a6ed83853dcc..ece1c926b5d1 100644
--- a/include/net/netns/ipv4.h
+++ b/include/net/netns/ipv4.h
@@ -38,6 +38,9 @@ struct netns_ipv4 {
         struct xt_table         *iptable_raw;
         struct xt_table         *arptable_filter;
         struct xt_table         *iptable_security;
+        struct xt_table         *nat_table;
+        struct hlist_head       *nat_bysource;
+        int                     nat_vmalloced;
 #endif
 
         int sysctl_icmp_echo_ignore_all;
diff --git a/include/net/netns/mib.h b/include/net/netns/mib.h
index 449147604642..10cb7c336de5 100644
--- a/include/net/netns/mib.h
+++ b/include/net/netns/mib.h
@@ -11,6 +11,15 @@ struct netns_mib {
         DEFINE_SNMP_STAT(struct udp_mib, udplite_statistics);
         DEFINE_SNMP_STAT(struct icmp_mib, icmp_statistics);
         DEFINE_SNMP_STAT(struct icmpmsg_mib, icmpmsg_statistics);
+
+#if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
+        struct proc_dir_entry *proc_net_devsnmp6;
+        DEFINE_SNMP_STAT(struct udp_mib, udp_stats_in6);
+        DEFINE_SNMP_STAT(struct udp_mib, udplite_stats_in6);
+        DEFINE_SNMP_STAT(struct ipstats_mib, ipv6_statistics);
+        DEFINE_SNMP_STAT(struct icmpv6_mib, icmpv6_statistics);
+        DEFINE_SNMP_STAT(struct icmpv6msg_mib, icmpv6msg_statistics);
+#endif
 };
 
 #endif
diff --git a/include/net/phonet/gprs.h b/include/net/phonet/gprs.h
new file mode 100644
index 000000000000..928daf595beb
--- /dev/null
+++ b/include/net/phonet/gprs.h
@@ -0,0 +1,38 @@
+/*
+ * File: pep_gprs.h
+ *
+ * GPRS over Phonet pipe end point socket
+ *
+ * Copyright (C) 2008 Nokia Corporation.
+ *
+ * Author: Rémi Denis-Courmont <remi.denis-courmont@nokia.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef NET_PHONET_GPRS_H
+#define NET_PHONET_GPRS_H
+
+struct sock;
+struct sk_buff;
+
+int pep_writeable(struct sock *sk);
+int pep_write(struct sock *sk, struct sk_buff *skb);
+struct sk_buff *pep_read(struct sock *sk);
+
+int gprs_attach(struct sock *sk);
+void gprs_detach(struct sock *sk);
+
+#endif
diff --git a/include/net/phonet/pep.h b/include/net/phonet/pep.h
new file mode 100644
index 000000000000..fcd793030e4d
--- /dev/null
+++ b/include/net/phonet/pep.h
@@ -0,0 +1,160 @@
+/*
+ * File: pep.h
+ *
+ * Phonet Pipe End Point sockets definitions
+ *
+ * Copyright (C) 2008 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef NET_PHONET_PEP_H
+#define NET_PHONET_PEP_H
+
+struct pep_sock {
+        struct pn_sock          pn_sk;
+
+        /* XXX: union-ify listening vs connected stuff ? */
+        /* Listening socket stuff: */
+        struct hlist_head       ackq;
+        struct hlist_head       hlist;
+
+        /* Connected socket stuff: */
+        struct sock             *listener;
+        struct sk_buff_head     ctrlreq_queue;
+#define PNPIPE_CTRLREQ_MAX      10
+        int                     ifindex;
+        u16                     peer_type;      /* peer type/subtype */
+        u8                      pipe_handle;
+
+        u8                      rx_credits;
+        u8                      tx_credits;
+        u8                      rx_fc;  /* RX flow control */
+        u8                      tx_fc;  /* TX flow control */
+        u8                      init_enable;    /* auto-enable at creation */
+};
+
+static inline struct pep_sock *pep_sk(struct sock *sk)
+{
+        return (struct pep_sock *)sk;
+}
+
+extern const struct proto_ops phonet_stream_ops;
+
+/* Pipe protocol definitions */
+struct pnpipehdr {
+        u8                      utid; /* transaction ID */
+        u8                      message_id;
+        u8                      pipe_handle;
+        union {
+                u8              state_after_connect;    /* connect request */
+                u8              state_after_reset;      /* reset request */
+                u8              error_code;             /* any response */
+                u8              pep_type;               /* status indication */
+                u8              data[1];
+        };
+};
+#define other_pep_type          data[1]
+
+static inline struct pnpipehdr *pnp_hdr(struct sk_buff *skb)
+{
+        return (struct pnpipehdr *)skb_transport_header(skb);
+}
+
+#define MAX_PNPIPE_HEADER (MAX_PHONET_HEADER + 4)
+
+enum {
+        PNS_PIPE_DATA = 0x20,
+
+        PNS_PEP_CONNECT_REQ = 0x40,
+        PNS_PEP_CONNECT_RESP,
+        PNS_PEP_DISCONNECT_REQ,
+        PNS_PEP_DISCONNECT_RESP,
+        PNS_PEP_RESET_REQ,
+        PNS_PEP_RESET_RESP,
+        PNS_PEP_ENABLE_REQ,
+        PNS_PEP_ENABLE_RESP,
+        PNS_PEP_CTRL_REQ,
+        PNS_PEP_CTRL_RESP,
+        PNS_PEP_DISABLE_REQ = 0x4C,
+        PNS_PEP_DISABLE_RESP,
+
+        PNS_PEP_STATUS_IND = 0x60,
+        PNS_PIPE_CREATED_IND,
+        PNS_PIPE_RESET_IND = 0x63,
+        PNS_PIPE_ENABLED_IND,
+        PNS_PIPE_REDIRECTED_IND,
+        PNS_PIPE_DISABLED_IND = 0x66,
+};
+
+#define PN_PIPE_INVALID_HANDLE  0xff
+#define PN_PEP_TYPE_COMMON      0x00
+
+/* Phonet pipe status indication */
+enum {
+        PN_PEP_IND_FLOW_CONTROL,
+        PN_PEP_IND_ID_MCFC_GRANT_CREDITS,
+};
+
+/* Phonet pipe error codes */
+enum {
+        PN_PIPE_NO_ERROR,
+        PN_PIPE_ERR_INVALID_PARAM,
+        PN_PIPE_ERR_INVALID_HANDLE,
+        PN_PIPE_ERR_INVALID_CTRL_ID,
+        PN_PIPE_ERR_NOT_ALLOWED,
+        PN_PIPE_ERR_PEP_IN_USE,
+        PN_PIPE_ERR_OVERLOAD,
+        PN_PIPE_ERR_DEV_DISCONNECTED,
+        PN_PIPE_ERR_TIMEOUT,
+        PN_PIPE_ERR_ALL_PIPES_IN_USE,
+        PN_PIPE_ERR_GENERAL,
+        PN_PIPE_ERR_NOT_SUPPORTED,
+};
+
+/* Phonet pipe states */
+enum {
+        PN_PIPE_DISABLE,
+        PN_PIPE_ENABLE,
+};
+
+/* Phonet pipe sub-block types */
+enum {
+        PN_PIPE_SB_CREATE_REQ_PEP_SUB_TYPE,
+        PN_PIPE_SB_CONNECT_REQ_PEP_SUB_TYPE,
+        PN_PIPE_SB_REDIRECT_REQ_PEP_SUB_TYPE,
+        PN_PIPE_SB_NEGOTIATED_FC,
+        PN_PIPE_SB_REQUIRED_FC_TX,
+        PN_PIPE_SB_PREFERRED_FC_RX,
+};
+
+/* Phonet pipe flow control models */
+enum {
+        PN_NO_FLOW_CONTROL,
+        PN_LEGACY_FLOW_CONTROL,
+        PN_ONE_CREDIT_FLOW_CONTROL,
+        PN_MULTI_CREDIT_FLOW_CONTROL,
+};
+
+#define pn_flow_safe(fc) ((fc) >> 1)
+
+/* Phonet pipe flow control states */
+enum {
+        PEP_IND_EMPTY,
+        PEP_IND_BUSY,
+        PEP_IND_READY,
+};
+
+#endif
diff --git a/include/net/phonet/phonet.h b/include/net/phonet/phonet.h
new file mode 100644
index 000000000000..d4e72508e145
--- /dev/null
+++ b/include/net/phonet/phonet.h
@@ -0,0 +1,112 @@
+/*
+ * File: af_phonet.h
+ *
+ * Phonet sockets kernel definitions
+ *
+ * Copyright (C) 2008 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef AF_PHONET_H
+#define AF_PHONET_H
+
+/*
+ * The lower layers may not require more space, ever. Make sure it's
+ * enough.
+ */
+#define MAX_PHONET_HEADER       8
+
+/*
+ * Every Phonet* socket has this structure first in its
+ * protocol-specific structure under name c.
+ */
+struct pn_sock {
+        struct sock     sk;
+        u16             sobject;
+        u8              resource;
+};
+
+static inline struct pn_sock *pn_sk(struct sock *sk)
+{
+        return (struct pn_sock *)sk;
+}
+
+extern const struct proto_ops phonet_dgram_ops;
+
+struct sock *pn_find_sock_by_sa(const struct sockaddr_pn *sa);
+void phonet_get_local_port_range(int *min, int *max);
+void pn_sock_hash(struct sock *sk);
+void pn_sock_unhash(struct sock *sk);
+int pn_sock_get_port(struct sock *sk, unsigned short sport);
+
+int pn_skb_send(struct sock *sk, struct sk_buff *skb,
+                const struct sockaddr_pn *target);
+
+static inline struct phonethdr *pn_hdr(struct sk_buff *skb)
+{
+        return (struct phonethdr *)skb_network_header(skb);
+}
+
+static inline struct phonetmsg *pn_msg(struct sk_buff *skb)
+{
+        return (struct phonetmsg *)skb_transport_header(skb);
+}
+
+/*
+ * Get the other party's sockaddr from received skb. The skb begins
+ * with a Phonet header.
+ */
+static inline
+void pn_skb_get_src_sockaddr(struct sk_buff *skb, struct sockaddr_pn *sa)
+{
+        struct phonethdr *ph = pn_hdr(skb);
+        u16 obj = pn_object(ph->pn_sdev, ph->pn_sobj);
+
+        sa->spn_family = AF_PHONET;
+        pn_sockaddr_set_object(sa, obj);
+        pn_sockaddr_set_resource(sa, ph->pn_res);
+        memset(sa->spn_zero, 0, sizeof(sa->spn_zero));
+}
+
+static inline
+void pn_skb_get_dst_sockaddr(struct sk_buff *skb, struct sockaddr_pn *sa)
+{
+        struct phonethdr *ph = pn_hdr(skb);
+        u16 obj = pn_object(ph->pn_rdev, ph->pn_robj);
+
+        sa->spn_family = AF_PHONET;
+        pn_sockaddr_set_object(sa, obj);
+        pn_sockaddr_set_resource(sa, ph->pn_res);
+        memset(sa->spn_zero, 0, sizeof(sa->spn_zero));
+}
+
+/* Protocols in Phonet protocol family. */
+struct phonet_protocol {
+        const struct proto_ops  *ops;
+        struct proto            *prot;
+        int                     sock_type;
+};
+
+int phonet_proto_register(int protocol, struct phonet_protocol *pp);
+void phonet_proto_unregister(int protocol, struct phonet_protocol *pp);
+
+int phonet_sysctl_init(void);
+void phonet_sysctl_exit(void);
+void phonet_netlink_register(void);
+int isi_register(void);
+void isi_unregister(void);
+
+#endif
diff --git a/include/net/phonet/pn_dev.h b/include/net/phonet/pn_dev.h
new file mode 100644
index 000000000000..bbd2a836e04c
--- /dev/null
+++ b/include/net/phonet/pn_dev.h
@@ -0,0 +1,50 @@
+/*
+ * File: pn_dev.h
+ *
+ * Phonet network device
+ *
+ * Copyright (C) 2008 Nokia Corporation.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * version 2 as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful, but
+ * WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA
+ * 02110-1301 USA
+ */
+
+#ifndef PN_DEV_H
+#define PN_DEV_H
+
+struct phonet_device_list {
+        struct list_head list;
+        spinlock_t lock;
+};
+
+extern struct phonet_device_list pndevs;
+
+struct phonet_device {
+        struct list_head list;
+        struct net_device *netdev;
+        DECLARE_BITMAP(addrs, 64);
+};
+
+void phonet_device_init(void);
+void phonet_device_exit(void);
+struct net_device *phonet_device_get(struct net *net);
+
+int phonet_address_add(struct net_device *dev, u8 addr);
+int phonet_address_del(struct net_device *dev, u8 addr);
+u8 phonet_address_get(struct net_device *dev, u8 addr);
+int phonet_address_lookup(u8 addr);
+
+#define PN_NO_ADDR      0xff
+
+#endif
diff --git a/include/net/pkt_sched.h b/include/net/pkt_sched.h
index 853fe83d9f37..4082f39f5079 100644
--- a/include/net/pkt_sched.h
+++ b/include/net/pkt_sched.h
@@ -78,6 +78,7 @@ extern struct Qdisc *fifo_create_dflt(struct Qdisc *sch, struct Qdisc_ops *ops,
 
 extern int register_qdisc(struct Qdisc_ops *qops);
 extern int unregister_qdisc(struct Qdisc_ops *qops);
+extern void qdisc_list_del(struct Qdisc *q);
 extern struct Qdisc *qdisc_lookup(struct net_device *dev, u32 handle);
 extern struct Qdisc *qdisc_lookup_class(struct net_device *dev, u32 handle);
 extern struct qdisc_rate_table *qdisc_get_rtab(struct tc_ratespec *r,
@@ -89,10 +90,7 @@ extern void __qdisc_run(struct Qdisc *q);
 
 static inline void qdisc_run(struct Qdisc *q)
 {
-        struct netdev_queue *txq = q->dev_queue;
-
-        if (!netif_tx_queue_stopped(txq) &&
-            !test_and_set_bit(__QDISC_STATE_RUNNING, &q->state))
+        if (!test_and_set_bit(__QDISC_STATE_RUNNING, &q->state))
                 __qdisc_run(q);
 }
 
diff --git a/include/net/route.h b/include/net/route.h
index 4f0d8c14736c..4e8cae0e5841 100644
--- a/include/net/route.h
+++ b/include/net/route.h
@@ -27,7 +27,7 @@
 #include <net/dst.h>
 #include <net/inetpeer.h>
 #include <net/flow.h>
-#include <net/sock.h>
+#include <net/inet_sock.h>
 #include <linux/in_route.h>
 #include <linux/rtnetlink.h>
 #include <linux/route.h>
@@ -161,6 +161,10 @@ static inline int ip_route_connect(struct rtable **rp, __be32 dst,
 
         int err;
         struct net *net = sock_net(sk);
+
+        if (inet_sk(sk)->transparent)
+                fl.flags |= FLOWI_FLAG_ANYSRC;
+
         if (!dst || !src) {
                 err = __ip_route_output_key(net, rp, &fl);
                 if (err)
@@ -204,4 +208,9 @@ static inline struct inet_peer *rt_get_peer(struct rtable *rt)
         return rt->peer;
 }
 
+static inline int inet_iif(const struct sk_buff *skb)
+{
+        return skb->rtable->rt_iif;
+}
+
 #endif  /* _ROUTE_H */
diff --git a/include/net/sch_generic.h b/include/net/sch_generic.h
index 84d25f2e6188..3fe49d808957 100644
--- a/include/net/sch_generic.h
+++ b/include/net/sch_generic.h
@@ -53,6 +53,7 @@ struct Qdisc
         atomic_t                refcnt;
         unsigned long           state;
         struct sk_buff          *gso_skb;
+        struct sk_buff_head     requeue;
         struct sk_buff_head     q;
         struct netdev_queue     *dev_queue;
         struct Qdisc            *next_sched;
@@ -193,6 +194,11 @@ static inline struct Qdisc *qdisc_root(struct Qdisc *qdisc)
         return qdisc->dev_queue->qdisc;
 }
 
+static inline struct Qdisc *qdisc_root_sleeping(struct Qdisc *qdisc)
+{
+        return qdisc->dev_queue->qdisc_sleeping;
+}
+
 /* The qdisc root lock is a mechanism by which to top level
  * of a qdisc tree can be locked from any qdisc node in the
  * forest.  This allows changing the configuration of some
@@ -212,6 +218,14 @@ static inline spinlock_t *qdisc_root_lock(struct Qdisc *qdisc)
         return qdisc_lock(root);
 }
 
+static inline spinlock_t *qdisc_root_sleeping_lock(struct Qdisc *qdisc)
+{
+        struct Qdisc *root = qdisc_root_sleeping(qdisc);
+
+        ASSERT_RTNL();
+        return qdisc_lock(root);
+}
+
 static inline struct net_device *qdisc_dev(struct Qdisc *qdisc)
 {
         return qdisc->dev_queue->dev;
@@ -219,12 +233,12 @@ static inline struct net_device *qdisc_dev(struct Qdisc *qdisc)
 
 static inline void sch_tree_lock(struct Qdisc *q)
 {
-        spin_lock_bh(qdisc_root_lock(q));
+        spin_lock_bh(qdisc_root_sleeping_lock(q));
 }
 
 static inline void sch_tree_unlock(struct Qdisc *q)
 {
-        spin_unlock_bh(qdisc_root_lock(q));
+        spin_unlock_bh(qdisc_root_sleeping_lock(q));
 }
 
 #define tcf_tree_lock(tp)       sch_tree_lock((tp)->q)
diff --git a/include/net/sctp/constants.h b/include/net/sctp/constants.h
index c32ddf0279c8..b05b0557211f 100644
--- a/include/net/sctp/constants.h
+++ b/include/net/sctp/constants.h
@@ -261,7 +261,9 @@ enum { SCTP_ARBITRARY_COOKIE_ECHO_LEN = 200 };
  * must be less than 65535 (2^16 - 1), or we will have overflow
  * problems creating SACK's.
  */
-#define SCTP_TSN_MAP_SIZE 2048
+#define SCTP_TSN_MAP_INITIAL BITS_PER_LONG
+#define SCTP_TSN_MAP_INCREMENT SCTP_TSN_MAP_INITIAL
+#define SCTP_TSN_MAP_SIZE 4096
 #define SCTP_TSN_MAX_GAP  65535
 
 /* We will not record more than this many duplicate TSNs between two
diff --git a/include/net/sctp/sctp.h b/include/net/sctp/sctp.h
index 17b932b8a55a..ed71b110edf7 100644
--- a/include/net/sctp/sctp.h
+++ b/include/net/sctp/sctp.h
@@ -303,7 +303,7 @@ extern int sctp_debug_flag;
 #define SCTP_ASSERT(expr, str, func) \
         if (!(expr)) { \
                 SCTP_DEBUG_PRINTK("Assertion Failed: %s(%s) at %s:%s:%d\n", \
-                        str, (#expr), __FILE__, __FUNCTION__, __LINE__); \
+                        str, (#expr), __FILE__, __func__, __LINE__); \
                 func; \
         }
 
@@ -406,10 +406,7 @@ struct sctp_association *sctp_id2assoc(struct sock *sk, sctp_assoc_t id);
 
 /* A macro to walk a list of skbs.  */
 #define sctp_skb_for_each(pos, head, tmp) \
-for (pos = (head)->next;\
-     tmp = (pos)->next, pos != ((struct sk_buff *)(head));\
-     pos = tmp)
-
+        skb_queue_walk_safe(head, pos, tmp)
 
 /* A helper to append an entire skb list (list) to another (head). */
 static inline void sctp_skb_list_tail(struct sk_buff_head *list,
@@ -420,10 +417,7 @@ static inline void sctp_skb_list_tail(struct sk_buff_head *list,
         sctp_spin_lock_irqsave(&head->lock, flags);
         sctp_spin_lock(&list->lock);
 
-        list_splice((struct list_head *)list, (struct list_head *)head->prev);
-
-        head->qlen += list->qlen;
-        list->qlen = 0;
+        skb_queue_splice_tail_init(list, head);
 
         sctp_spin_unlock(&list->lock);
         sctp_spin_unlock_irqrestore(&head->lock, flags);
diff --git a/include/net/sctp/sm.h b/include/net/sctp/sm.h
index 24811732bdb2..029a54a02396 100644
--- a/include/net/sctp/sm.h
+++ b/include/net/sctp/sm.h
@@ -227,6 +227,9 @@ struct sctp_chunk *sctp_make_abort_violation(const struct sctp_association *,
                                    const struct sctp_chunk *,
                                    const __u8 *,
                                    const size_t );
+struct sctp_chunk *sctp_make_violation_paramlen(const struct sctp_association *,
+                                   const struct sctp_chunk *,
+                                   struct sctp_paramhdr *);
 struct sctp_chunk *sctp_make_heartbeat(const struct sctp_association *,
                                   const struct sctp_transport *,
                                   const void *payload,
diff --git a/include/net/sctp/structs.h b/include/net/sctp/structs.h
index ab1c472ea753..9661d7b765f0 100644
--- a/include/net/sctp/structs.h
+++ b/include/net/sctp/structs.h
@@ -731,20 +731,23 @@ struct sctp_chunk {
          */
         struct sk_buff *auth_chunk;
 
-        __u8 rtt_in_progress;   /* Is this chunk used for RTT calculation? */
-        __u8 resent;            /* Has this chunk ever been retransmitted. */
-        __u8 has_tsn;           /* Does this chunk have a TSN yet? */
-        __u8 has_ssn;           /* Does this chunk have a SSN yet? */
-        __u8 singleton;         /* Was this the only chunk in the packet? */
-        __u8 end_of_packet;     /* Was this the last chunk in the packet? */
-        __u8 ecn_ce_done;       /* Have we processed the ECN CE bit? */
-        __u8 pdiscard;          /* Discard the whole packet now? */
-        __u8 tsn_gap_acked;     /* Is this chunk acked by a GAP ACK? */
-        __s8 fast_retransmit;    /* Is this chunk fast retransmitted? */
-        __u8 tsn_missing_report; /* Data chunk missing counter. */
-        __u8 data_accepted;     /* At least 1 chunk in this packet accepted */
-        __u8 auth;              /* IN: was auth'ed | OUT: needs auth */
-        __u8 has_asconf;        /* IN: have seen an asconf before */
+#define SCTP_CAN_FRTX 0x0
+#define SCTP_NEED_FRTX 0x1
+#define SCTP_DONT_FRTX 0x2
+        __u16   rtt_in_progress:1,      /* This chunk used for RTT calc? */
+                resent:1,               /* Has this chunk ever been resent. */
+                has_tsn:1,              /* Does this chunk have a TSN yet? */
+                has_ssn:1,              /* Does this chunk have a SSN yet? */
+                singleton:1,            /* Only chunk in the packet? */
+                end_of_packet:1,        /* Last chunk in the packet? */
+                ecn_ce_done:1,          /* Have we processed the ECN CE bit? */
+                pdiscard:1,             /* Discard the whole packet now? */
+                tsn_gap_acked:1,        /* Is this chunk acked by a GAP ACK? */
+                data_accepted:1,        /* At least 1 chunk accepted */
+                auth:1,                 /* IN: was auth'ed | OUT: needs auth */
+                has_asconf:1,           /* IN: have seen an asconf before */
+                tsn_missing_report:2,   /* Data chunk missing counter. */
+                fast_retransmit:2;      /* Is this chunk fast retransmitted? */
 };
 
 void sctp_chunk_hold(struct sctp_chunk *);
@@ -1225,7 +1228,7 @@ int sctp_raw_to_bind_addrs(struct sctp_bind_addr *bp, __u8 *raw, int len,
 
 sctp_scope_t sctp_scope(const union sctp_addr *);
 int sctp_in_scope(const union sctp_addr *addr, const sctp_scope_t scope);
-int sctp_is_any(const union sctp_addr *addr);
+int sctp_is_any(struct sock *sk, const union sctp_addr *addr);
 int sctp_addr_is_valid(const union sctp_addr *addr);
 
 
@@ -1542,7 +1545,6 @@ struct sctp_association {
                  * in tsn_map--we get it by calling sctp_tsnmap_get_ctsn().
                  */
                 struct sctp_tsnmap tsn_map;
-                __u8 _map[sctp_tsnmap_storage_size(SCTP_TSN_MAP_SIZE)];
 
                 /* Ack State   : This flag indicates if the next received
                  *             : packet is to be responded to with a
diff --git a/include/net/sctp/tsnmap.h b/include/net/sctp/tsnmap.h
index 099211bf998d..4aabc5a96cf6 100644
--- a/include/net/sctp/tsnmap.h
+++ b/include/net/sctp/tsnmap.h
@@ -60,18 +60,7 @@ struct sctp_tsnmap {
          * It points at one of the two buffers with which we will
          * ping-pong between.
          */
-        __u8 *tsn_map;
-
-        /* This marks the tsn which overflows the tsn_map, when the
-         * cumulative ack point reaches this point we know we can switch
-         * maps (tsn_map and overflow_map swap).
-         */
-        __u32 overflow_tsn;
-
-        /* This is the overflow array for tsn_map.
-         * It points at one of the other ping-pong buffers.
-         */
-        __u8 *overflow_map;
+        unsigned long *tsn_map;
 
         /* This is the TSN at tsn_map[0].  */
         __u32 base_tsn;
@@ -89,15 +78,15 @@ struct sctp_tsnmap {
          */
         __u32 cumulative_tsn_ack_point;
 
+        /* This is the highest TSN we've marked.  */
+        __u32 max_tsn_seen;
+
         /* This is the minimum number of TSNs we can track.  This corresponds
          * to the size of tsn_map.   Note: the overflow_map allows us to
          * potentially track more than this quantity.
          */
         __u16 len;
 
-        /* This is the highest TSN we've marked.  */
-        __u32 max_tsn_seen;
-
         /* Data chunks pending receipt. used by SCTP_STATUS sockopt */
         __u16 pending_data;
 
@@ -105,29 +94,19 @@ struct sctp_tsnmap {
          * every SACK.  Store up to SCTP_MAX_DUP_TSNS worth of
          * information.
          */
-        __be32 dup_tsns[SCTP_MAX_DUP_TSNS];
         __u16 num_dup_tsns;
-
-        /* Record gap ack block information here.  */
-        struct sctp_gap_ack_block gabs[SCTP_MAX_GABS];
-
-        int malloced;
-
-        __u8 raw_map[0];
+        __be32 dup_tsns[SCTP_MAX_DUP_TSNS];
 };
 
 struct sctp_tsnmap_iter {
         __u32 start;
 };
 
-/* This macro assists in creation of external storage for variable length
- * internal buffers.  We double allocate so the overflow map works.
- */
-#define sctp_tsnmap_storage_size(count) (sizeof(__u8) * (count) * 2)
-
 /* Initialize a block of memory as a tsnmap.  */
 struct sctp_tsnmap *sctp_tsnmap_init(struct sctp_tsnmap *, __u16 len,
-                                     __u32 initial_tsn);
+                                     __u32 initial_tsn, gfp_t gfp);
+
+void sctp_tsnmap_free(struct sctp_tsnmap *map);
 
 /* Test the tracking state of this TSN.
  * Returns:
@@ -138,7 +117,7 @@ struct sctp_tsnmap *sctp_tsnmap_init(struct sctp_tsnmap *, __u16 len,
 int sctp_tsnmap_check(const struct sctp_tsnmap *, __u32 tsn);
 
 /* Mark this TSN as seen.  */
-void sctp_tsnmap_mark(struct sctp_tsnmap *, __u32 tsn);
+int sctp_tsnmap_mark(struct sctp_tsnmap *, __u32 tsn);
 
 /* Mark this TSN and all lower as seen. */
 void sctp_tsnmap_skip(struct sctp_tsnmap *map, __u32 tsn);
@@ -169,24 +148,16 @@ static inline __be32 *sctp_tsnmap_get_dups(struct sctp_tsnmap *map)
 }
 
 /* How many gap ack blocks do we have recorded? */
-__u16 sctp_tsnmap_num_gabs(struct sctp_tsnmap *map);
+__u16 sctp_tsnmap_num_gabs(struct sctp_tsnmap *map,
+                           struct sctp_gap_ack_block *gabs);
 
 /* Refresh the count on pending data. */
 __u16 sctp_tsnmap_pending(struct sctp_tsnmap *map);
 
-/* Return pointer to gap ack blocks as needed by SACK. */
-static inline struct sctp_gap_ack_block *sctp_tsnmap_get_gabs(struct sctp_tsnmap *map)
-{
-        return map->gabs;
-}
-
 /* Is there a gap in the TSN map?  */
 static inline int sctp_tsnmap_has_gap(const struct sctp_tsnmap *map)
 {
-        int has_gap;
-
-        has_gap = (map->cumulative_tsn_ack_point != map->max_tsn_seen);
-        return has_gap;
+        return (map->cumulative_tsn_ack_point != map->max_tsn_seen);
 }
 
 /* Mark a duplicate TSN.  Note:  limit the storage of duplicate TSN
diff --git a/include/net/sock.h b/include/net/sock.h
index 06c5259aff30..ada50c04d09f 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -482,6 +482,11 @@ static inline void sk_add_backlog(struct sock *sk, struct sk_buff *skb)
         skb->next = NULL;
 }
 
+static inline int sk_backlog_rcv(struct sock *sk, struct sk_buff *skb)
+{
+        return sk->sk_backlog_rcv(sk, skb);
+}
+
 #define sk_wait_event(__sk, __timeo, __condition)                       \
         ({      int __rc;                                               \
                 release_sock(__sk);                                     \
@@ -532,6 +537,7 @@ struct proto {
         int                     (*getsockopt)(struct sock *sk, int level, 
                                         int optname, char __user *optval, 
                                         int __user *option);     
+#ifdef CONFIG_COMPAT
         int                     (*compat_setsockopt)(struct sock *sk,
                                         int level,
                                         int optname, char __user *optval,
@@ -540,6 +546,7 @@ struct proto {
                                         int level,
                                         int optname, char __user *optval,
                                         int __user *option);
+#endif
         int                     (*sendmsg)(struct kiocb *iocb, struct sock *sk,
                                            struct msghdr *msg, size_t len);
         int                     (*recvmsg)(struct kiocb *iocb, struct sock *sk,
@@ -1322,6 +1329,18 @@ static inline void sk_change_net(struct sock *sk, struct net *net)
         sock_net_set(sk, hold_net(net));
 }
 
+static inline struct sock *skb_steal_sock(struct sk_buff *skb)
+{
+        if (unlikely(skb->sk)) {
+                struct sock *sk = skb->sk;
+
+                skb->destructor = NULL;
+                skb->sk = NULL;
+                return sk;
+        }
+        return NULL;
+}
+
 extern void sock_enable_timestamp(struct sock *sk);
 extern int sock_get_timestamp(struct sock *, struct timeval __user *);
 extern int sock_get_timestampns(struct sock *, struct timespec __user *);
diff --git a/include/net/tc_act/tc_skbedit.h b/include/net/tc_act/tc_skbedit.h
new file mode 100644
index 000000000000..6abb3ed3ebf7
--- /dev/null
+++ b/include/net/tc_act/tc_skbedit.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2008, Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms and conditions of the GNU General Public License,
+ * version 2, as published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
+ * more details.
+ *
+ * You should have received a copy of the GNU General Public License along with
+ * this program; if not, write to the Free Software Foundation, Inc., 59 Temple
+ * Place - Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * Author: Alexander Duyck <alexander.h.duyck@intel.com>
+ */
+
+#ifndef __NET_TC_SKBEDIT_H
+#define __NET_TC_SKBEDIT_H
+
+#include <net/act_api.h>
+
+struct tcf_skbedit {
+        struct tcf_common       common;
+        u32                     flags;
+        u32                     priority;
+        u16                     queue_mapping;
+};
+#define to_skbedit(pc) \
+        container_of(pc, struct tcf_skbedit, common)
+
+#endif /* __NET_TC_SKBEDIT_H */
diff --git a/include/net/tcp.h b/include/net/tcp.h
index 8983386356a5..438014d57610 100644
--- a/include/net/tcp.h
+++ b/include/net/tcp.h
@@ -472,6 +472,8 @@ extern void tcp_send_delayed_ack(struct sock *sk);
 
 /* tcp_input.c */
 extern void tcp_cwnd_application_limited(struct sock *sk);
+extern void tcp_skb_mark_lost_uncond_verify(struct tcp_sock *tp,
+                                            struct sk_buff *skb);
 
 /* tcp_timer.c */
 extern void tcp_init_xmit_timers(struct sock *);
@@ -894,7 +896,7 @@ static inline int tcp_prequeue(struct sock *sk, struct sk_buff *skb)
                         BUG_ON(sock_owned_by_user(sk));
 
                         while ((skb1 = __skb_dequeue(&tp->ucopy.prequeue)) != NULL) {
-                                sk->sk_backlog_rcv(sk, skb1);
+                                sk_backlog_rcv(sk, skb1);
                                 NET_INC_STATS_BH(sock_net(sk), LINUX_MIB_TCPPREQUEUEDROPPED);
                         }
 
@@ -974,6 +976,7 @@ static inline void tcp_openreq_init(struct request_sock *req,
         ireq->acked = 0;
         ireq->ecn_ok = 0;
         ireq->rmt_port = tcp_hdr(skb)->source;
+        ireq->loc_port = tcp_hdr(skb)->dest;
 }
 
 extern void tcp_enter_memory_pressure(struct sock *sk);
@@ -1039,13 +1042,12 @@ static inline void tcp_clear_retrans_hints_partial(struct tcp_sock *tp)
 {
         tp->lost_skb_hint = NULL;
         tp->scoreboard_skb_hint = NULL;
-        tp->retransmit_skb_hint = NULL;
-        tp->forward_skb_hint = NULL;
 }
 
 static inline void tcp_clear_all_retrans_hints(struct tcp_sock *tp)
 {
         tcp_clear_retrans_hints_partial(tp);
+        tp->retransmit_skb_hint = NULL;
 }
 
 /* MD5 Signature */
@@ -1180,49 +1182,45 @@ static inline void tcp_write_queue_purge(struct sock *sk)
 
 static inline struct sk_buff *tcp_write_queue_head(struct sock *sk)
 {
-        struct sk_buff *skb = sk->sk_write_queue.next;
-        if (skb == (struct sk_buff *) &sk->sk_write_queue)
-                return NULL;
-        return skb;
+        return skb_peek(&sk->sk_write_queue);
 }
 
 static inline struct sk_buff *tcp_write_queue_tail(struct sock *sk)
 {
-        struct sk_buff *skb = sk->sk_write_queue.prev;
-        if (skb == (struct sk_buff *) &sk->sk_write_queue)
-                return NULL;
-        return skb;
+        return skb_peek_tail(&sk->sk_write_queue);
 }
 
 static inline struct sk_buff *tcp_write_queue_next(struct sock *sk, struct sk_buff *skb)
 {
-        return skb->next;
+        return skb_queue_next(&sk->sk_write_queue, skb);
 }
 
 #define tcp_for_write_queue(skb, sk)                                    \
-                for (skb = (sk)->sk_write_queue.next;                   \
-                     (skb != (struct sk_buff *)&(sk)->sk_write_queue);  \
-                     skb = skb->next)
+        skb_queue_walk(&(sk)->sk_write_queue, skb)
 
 #define tcp_for_write_queue_from(skb, sk)                               \
-                for (; (skb != (struct sk_buff *)&(sk)->sk_write_queue);\
-                     skb = skb->next)
+        skb_queue_walk_from(&(sk)->sk_write_queue, skb)
 
 #define tcp_for_write_queue_from_safe(skb, tmp, sk)                     \
-                for (tmp = skb->next;                                   \
-                     (skb != (struct sk_buff *)&(sk)->sk_write_queue);  \
-                     skb = tmp, tmp = skb->next)
+        skb_queue_walk_from_safe(&(sk)->sk_write_queue, skb, tmp)
 
 static inline struct sk_buff *tcp_send_head(struct sock *sk)
 {
         return sk->sk_send_head;
 }
 
+static inline bool tcp_skb_is_last(const struct sock *sk,
+                                   const struct sk_buff *skb)
+{
+        return skb_queue_is_last(&sk->sk_write_queue, skb);
+}
+
 static inline void tcp_advance_send_head(struct sock *sk, struct sk_buff *skb)
 {
-        sk->sk_send_head = skb->next;
-        if (sk->sk_send_head == (struct sk_buff *)&sk->sk_write_queue)
+        if (tcp_skb_is_last(sk, skb))
                 sk->sk_send_head = NULL;
+        else
+                sk->sk_send_head = tcp_write_queue_next(sk, skb);
 }
 
 static inline void tcp_check_send_head(struct sock *sk, struct sk_buff *skb_unlinked)
@@ -1267,12 +1265,12 @@ static inline void tcp_insert_write_queue_after(struct sk_buff *skb,
         __skb_queue_after(&sk->sk_write_queue, skb, buff);
 }
 
-/* Insert skb between prev and next on the write queue of sk.  */
+/* Insert new before skb on the write queue of sk.  */
 static inline void tcp_insert_write_queue_before(struct sk_buff *new,
                                                   struct sk_buff *skb,
                                                   struct sock *sk)
 {
-        __skb_insert(new, skb->prev, skb, &sk->sk_write_queue);
+        __skb_queue_before(&sk->sk_write_queue, skb, new);
 
         if (sk->sk_send_head == skb)
                 sk->sk_send_head = new;
@@ -1283,12 +1281,6 @@ static inline void tcp_unlink_write_queue(struct sk_buff *skb, struct sock *sk)
         __skb_unlink(skb, &sk->sk_write_queue);
 }
 
-static inline int tcp_skb_is_last(const struct sock *sk,
-                                  const struct sk_buff *skb)
-{
-        return skb->next == (struct sk_buff *)&sk->sk_write_queue;
-}
-
 static inline int tcp_write_queue_empty(struct sock *sk)
 {
         return skb_queue_empty(&sk->sk_write_queue);
diff --git a/include/net/udp.h b/include/net/udp.h
index addcdc67234c..1e205095ea68 100644
--- a/include/net/udp.h
+++ b/include/net/udp.h
@@ -148,10 +148,9 @@ extern int 	udp_lib_setsockopt(struct sock *sk, int level, int optname,
                                    char __user *optval, int optlen,
                                    int (*push_pending_frames)(struct sock *));
 
-DECLARE_SNMP_STAT(struct udp_mib, udp_stats_in6);
-
-/* UDP-Lite does not have a standardized MIB yet, so we inherit from UDP */
-DECLARE_SNMP_STAT(struct udp_mib, udplite_stats_in6);
+extern struct sock *udp4_lib_lookup(struct net *net, __be32 saddr, __be16 sport,
+                                    __be32 daddr, __be16 dport,
+                                    int dif);
 
 /*
  *      SNMP statistics for UDP and UDP-Lite
@@ -163,12 +162,14 @@ DECLARE_SNMP_STAT(struct udp_mib, udplite_stats_in6);
         if (is_udplite) SNMP_INC_STATS_BH((net)->mib.udplite_statistics, field);         \
         else            SNMP_INC_STATS_BH((net)->mib.udp_statistics, field);    }  while(0)
 
-#define UDP6_INC_STATS_BH(net, field, is_udplite)           do { (void)net;  \
-        if (is_udplite) SNMP_INC_STATS_BH(udplite_stats_in6, field);         \
-        else            SNMP_INC_STATS_BH(udp_stats_in6, field);    } while(0)
-#define UDP6_INC_STATS_USER(net, field, is_udplite)         do { (void)net;    \
-        if (is_udplite) SNMP_INC_STATS_USER(udplite_stats_in6, field);         \
-        else            SNMP_INC_STATS_USER(udp_stats_in6, field);    } while(0)
+#define UDP6_INC_STATS_BH(net, field, is_udplite)           do { \
+        if (is_udplite) SNMP_INC_STATS_BH((net)->mib.udplite_stats_in6, field);\
+        else            SNMP_INC_STATS_BH((net)->mib.udp_stats_in6, field);  \
+} while(0)
+#define UDP6_INC_STATS_USER(net, field, __lite)             do { \
+        if (__lite) SNMP_INC_STATS_USER((net)->mib.udplite_stats_in6, field);  \
+        else        SNMP_INC_STATS_USER((net)->mib.udp_stats_in6, field);      \
+} while(0)
 
 #if defined(CONFIG_IPV6) || defined(CONFIG_IPV6_MODULE)
 #define UDPX_INC_STATS_BH(sk, field) \
diff --git a/include/net/wireless.h b/include/net/wireless.h
index 9324f8dd183e..721efb363db7 100644
--- a/include/net/wireless.h
+++ b/include/net/wireless.h
@@ -60,6 +60,7 @@ enum ieee80211_channel_flags {
  * with cfg80211.
  *
  * @center_freq: center frequency in MHz
+ * @max_bandwidth: maximum allowed bandwidth for this channel, in MHz
  * @hw_value: hardware-specific value for the channel
  * @flags: channel flags from &enum ieee80211_channel_flags.
  * @orig_flags: channel flags at registration time, used by regulatory
@@ -73,6 +74,7 @@ enum ieee80211_channel_flags {
 struct ieee80211_channel {
         enum ieee80211_band band;
         u16 center_freq;
+        u8 max_bandwidth;
         u16 hw_value;
         u32 flags;
         int max_antenna_gain;
@@ -178,6 +180,7 @@ struct ieee80211_supported_band {
  * struct wiphy - wireless hardware description
  * @idx: the wiphy index assigned to this item
  * @class_dev: the class device representing /sys/class/ieee80211/<wiphy-name>
+ * @reg_notifier: the driver's regulatory notification callback
  */
 struct wiphy {
         /* assign these fields before you register the wiphy */
@@ -185,6 +188,9 @@ struct wiphy {
         /* permanent MAC address */
         u8 perm_addr[ETH_ALEN];
 
+        /* Supported interface modes, OR together BIT(NL80211_IFTYPE_...) */
+        u16 interface_modes;
+
         /* If multiple wiphys are registered and you're handed e.g.
          * a regular netdev with assigned ieee80211_ptr, you won't
          * know whether it points to a wiphy your driver has registered
@@ -194,6 +200,9 @@ struct wiphy {
 
         struct ieee80211_supported_band *bands[IEEE80211_NUM_BANDS];
 
+        /* Lets us get back the wiphy on the callback */
+        int (*reg_notifier)(struct wiphy *wiphy, enum reg_set_by setby);
+
         /* fields below are read-only, assigned by cfg80211 */
 
         /* the item in /sys/class/ieee80211/ points to this,
@@ -214,9 +223,11 @@ struct wiphy {
  * the netdev.)
  *
  * @wiphy: pointer to hardware description
+ * @iftype: interface type
  */
 struct wireless_dev {
         struct wiphy *wiphy;
+        enum nl80211_iftype iftype;
 
         /* private to the generic wireless code */
         struct list_head list;
@@ -319,7 +330,6 @@ extern int ieee80211_frequency_to_channel(int freq);
  */
 extern struct ieee80211_channel *__ieee80211_get_channel(struct wiphy *wiphy,
                                                          int freq);
-
 /**
  * ieee80211_get_channel - get channel struct from wiphy for specified frequency
  */
@@ -328,4 +338,57 @@ ieee80211_get_channel(struct wiphy *wiphy, int freq)
 {
         return __ieee80211_get_channel(wiphy, freq);
 }
+
+/**
+ * __regulatory_hint - hint to the wireless core a regulatory domain
+ * @wiphy: if a driver is providing the hint this is the driver's very
+ *      own &struct wiphy
+ * @alpha2: the ISO/IEC 3166 alpha2 being claimed the regulatory domain
+ *      should be in. If @rd is set this should be NULL
+ * @rd: a complete regulatory domain, if passed the caller need not worry
+ *      about freeing it
+ *
+ * The Wireless subsystem can use this function to hint to the wireless core
+ * what it believes should be the current regulatory domain by
+ * giving it an ISO/IEC 3166 alpha2 country code it knows its regulatory
+ * domain should be in or by providing a completely build regulatory domain.
+ *
+ * Returns -EALREADY if *a regulatory domain* has already been set. Note that
+ * this could be by another driver. It is safe for drivers to continue if
+ * -EALREADY is returned, if drivers are not capable of world roaming they
+ * should not register more channels than they support. Right now we only
+ * support listening to the first driver hint. If the driver is capable
+ * of world roaming but wants to respect its own EEPROM mappings for
+ * specific regulatory domains it should register the @reg_notifier callback
+ * on the &struct wiphy. Returns 0 if the hint went through fine or through an
+ * intersection operation. Otherwise a standard error code is returned.
+ *
+ */
+extern int __regulatory_hint(struct wiphy *wiphy, enum reg_set_by set_by,
+                const char *alpha2, struct ieee80211_regdomain *rd);
+/**
+ * regulatory_hint - driver hint to the wireless core a regulatory domain
+ * @wiphy: the driver's very own &struct wiphy
+ * @alpha2: the ISO/IEC 3166 alpha2 the driver claims its regulatory domain
+ *      should be in. If @rd is set this should be NULL. Note that if you
+ *      set this to NULL you should still set rd->alpha2 to some accepted
+ *      alpha2.
+ * @rd: a complete regulatory domain provided by the driver. If passed
+ *      the driver does not need to worry about freeing it.
+ *
+ * Wireless drivers can use this function to hint to the wireless core
+ * what it believes should be the current regulatory domain by
+ * giving it an ISO/IEC 3166 alpha2 country code it knows its regulatory
+ * domain should be in or by providing a completely build regulatory domain.
+ * If the driver provides an ISO/IEC 3166 alpha2 userspace will be queried
+ * for a regulatory domain structure for the respective country. If
+ * a regulatory domain is build and passed you should set the alpha2
+ * if possible, otherwise set it to the special value of "99" which tells
+ * the wireless core it is unknown. If you pass a built regulatory domain
+ * and we return non zero you are in charge of kfree()'ing the structure.
+ *
+ * See __regulatory_hint() documentation for possible return values.
+ */
+extern int regulatory_hint(struct wiphy *wiphy,
+                const char *alpha2, struct ieee80211_regdomain *rd);
 #endif /* __NET_WIRELESS_H */
diff --git a/include/net/xfrm.h b/include/net/xfrm.h
index 2933d7474a79..11c890ad8ebb 100644
--- a/include/net/xfrm.h
+++ b/include/net/xfrm.h
@@ -117,12 +117,23 @@ extern struct mutex xfrm_cfg_mutex;
       metrics. Plus, it will be made via sk->sk_dst_cache. Solved.
  */
 
+struct xfrm_state_walk {
+        struct list_head        all;
+        u8                      state;
+        union {
+                u8              dying;
+                u8              proto;
+        };
+        u32                     seq;
+};
+
 /* Full description of state of transformer. */
 struct xfrm_state
 {
-        /* Note: bydst is re-used during gc */
-        struct list_head        all;
-        struct hlist_node       bydst;
+        union {
+                struct hlist_node       gclist;
+                struct hlist_node       bydst;
+        };
         struct hlist_node       bysrc;
         struct hlist_node       byspi;
 
@@ -134,12 +145,8 @@ struct xfrm_state
 
         u32                     genid;
 
-        /* Key manger bits */
-        struct {
-                u8              state;
-                u8              dying;
-                u32             seq;
-        } km;
+        /* Key manager bits */
+        struct xfrm_state_walk  km;
 
         /* Parameters of this state. */
         struct {
@@ -447,10 +454,20 @@ struct xfrm_tmpl
 
 #define XFRM_MAX_DEPTH          6
 
+struct xfrm_policy_walk_entry {
+        struct list_head        all;
+        u8                      dead;
+};
+
+struct xfrm_policy_walk {
+        struct xfrm_policy_walk_entry walk;
+        u8 type;
+        u32 seq;
+};
+
 struct xfrm_policy
 {
         struct xfrm_policy      *next;
-        struct list_head        bytype;
         struct hlist_node       bydst;
         struct hlist_node       byidx;
 
@@ -465,17 +482,23 @@ struct xfrm_policy
         struct xfrm_lifetime_cfg lft;
         struct xfrm_lifetime_cur curlft;
         struct dst_entry       *bundles;
-        u16                     family;
+        struct xfrm_policy_walk_entry walk;
         u8                      type;
         u8                      action;
         u8                      flags;
-        u8                      dead;
         u8                      xfrm_nr;
-        /* XXX 1 byte hole, try to pack */
+        u16                     family;
         struct xfrm_sec_ctx     *security;
         struct xfrm_tmpl        xfrm_vec[XFRM_MAX_DEPTH];
 };
 
+struct xfrm_kmaddress {
+        xfrm_address_t          local;
+        xfrm_address_t          remote;
+        u32                     reserved;
+        u16                     family;
+};
+
 struct xfrm_migrate {
         xfrm_address_t          old_daddr;
         xfrm_address_t          old_saddr;
@@ -515,7 +538,7 @@ struct xfrm_mgr
         int                     (*new_mapping)(struct xfrm_state *x, xfrm_address_t *ipaddr, __be16 sport);
         int                     (*notify_policy)(struct xfrm_policy *x, int dir, struct km_event *c);
         int                     (*report)(u8 proto, struct xfrm_selector *sel, xfrm_address_t *addr);
-        int                     (*migrate)(struct xfrm_selector *sel, u8 dir, u8 type, struct xfrm_migrate *m, int num_bundles);
+        int                     (*migrate)(struct xfrm_selector *sel, u8 dir, u8 type, struct xfrm_migrate *m, int num_bundles, struct xfrm_kmaddress *k);
 };
 
 extern int xfrm_register_km(struct xfrm_mgr *km);
@@ -1243,18 +1266,6 @@ struct xfrm6_tunnel {
         int priority;
 };
 
-struct xfrm_state_walk {
-        struct xfrm_state *state;
-        int count;
-        u8 proto;
-};
-
-struct xfrm_policy_walk {
-        struct xfrm_policy *policy;
-        int count;
-        u8 type, cur_type;
-};
-
 extern void xfrm_init(void);
 extern void xfrm4_init(void);
 extern void xfrm_state_init(void);
@@ -1279,23 +1290,10 @@ static inline void xfrm6_fini(void)
 extern int xfrm_proc_init(void);
 #endif
 
-static inline void xfrm_state_walk_init(struct xfrm_state_walk *walk, u8 proto)
-{
-        walk->proto = proto;
-        walk->state = NULL;
-        walk->count = 0;
-}
-
-static inline void xfrm_state_walk_done(struct xfrm_state_walk *walk)
-{
-        if (walk->state != NULL) {
-                xfrm_state_put(walk->state);
-                walk->state = NULL;
-        }
-}
-
+extern void xfrm_state_walk_init(struct xfrm_state_walk *walk, u8 proto);
 extern int xfrm_state_walk(struct xfrm_state_walk *walk,
                            int (*func)(struct xfrm_state *, int, void*), void *);
+extern void xfrm_state_walk_done(struct xfrm_state_walk *walk);
 extern struct xfrm_state *xfrm_state_alloc(void);
 extern struct xfrm_state *xfrm_state_find(xfrm_address_t *daddr, xfrm_address_t *saddr, 
                                           struct flowi *fl, struct xfrm_tmpl *tmpl,
@@ -1419,24 +1417,10 @@ static inline int xfrm4_udp_encap_rcv(struct sock *sk, struct sk_buff *skb)
 
 struct xfrm_policy *xfrm_policy_alloc(gfp_t gfp);
 
-static inline void xfrm_policy_walk_init(struct xfrm_policy_walk *walk, u8 type)
-{
-        walk->cur_type = XFRM_POLICY_TYPE_MAIN;
-        walk->type = type;
-        walk->policy = NULL;
-        walk->count = 0;
-}
-
-static inline void xfrm_policy_walk_done(struct xfrm_policy_walk *walk)
-{
-        if (walk->policy != NULL) {
-                xfrm_pol_put(walk->policy);
-                walk->policy = NULL;
-        }
-}
-
+extern void xfrm_policy_walk_init(struct xfrm_policy_walk *walk, u8 type);
 extern int xfrm_policy_walk(struct xfrm_policy_walk *walk,
         int (*func)(struct xfrm_policy *, int, int, void*), void *);
+extern void xfrm_policy_walk_done(struct xfrm_policy_walk *walk);
 int xfrm_policy_insert(int dir, struct xfrm_policy *policy, int excl);
 struct xfrm_policy *xfrm_policy_bysel_ctx(u8 type, int dir,
                                           struct xfrm_selector *sel,
@@ -1455,12 +1439,14 @@ extern int xfrm_bundle_ok(struct xfrm_policy *pol, struct xfrm_dst *xdst,
 
 #ifdef CONFIG_XFRM_MIGRATE
 extern int km_migrate(struct xfrm_selector *sel, u8 dir, u8 type,
-                      struct xfrm_migrate *m, int num_bundles);
+                      struct xfrm_migrate *m, int num_bundles,
+                      struct xfrm_kmaddress *k);
 extern struct xfrm_state * xfrm_migrate_state_find(struct xfrm_migrate *m);
 extern struct xfrm_state * xfrm_state_migrate(struct xfrm_state *x,
                                               struct xfrm_migrate *m);
 extern int xfrm_migrate(struct xfrm_selector *sel, u8 dir, u8 type,
-                        struct xfrm_migrate *m, int num_bundles);
+                        struct xfrm_migrate *m, int num_bundles,
+                        struct xfrm_kmaddress *k);
 #endif
 
 extern wait_queue_head_t km_waitq;
diff --git a/include/pcmcia/ciscode.h b/include/pcmcia/ciscode.h
index ad6e278ba7f2..b417985708f2 100644
--- a/include/pcmcia/ciscode.h
+++ b/include/pcmcia/ciscode.h
@@ -119,7 +119,7 @@
 
 #define MANFID_TOSHIBA                  0x0098
 
-#define MANFID_UNGERMANN 0x02c0
+#define MANFID_UNGERMANN                0x02c0
 
 #define MANFID_XIRCOM                   0x0105
 
diff --git a/include/pcmcia/cistpl.h b/include/pcmcia/cistpl.h
index e2e10c1e9a06..cfdd5af77dcc 100644
--- a/include/pcmcia/cistpl.h
+++ b/include/pcmcia/cistpl.h
@@ -573,44 +573,6 @@ typedef struct tuple_t {
 #define TUPLE_RETURN_LINK       0x01
 #define TUPLE_RETURN_COMMON     0x02
 
-/* For ValidateCIS */
-typedef struct cisinfo_t {
-    u_int       Chains;
-} cisinfo_t;
-
 #define CISTPL_MAX_CIS_SIZE     0x200
 
-/* For ReplaceCIS */
-typedef struct cisdump_t {
-    u_int       Length;
-    cisdata_t   Data[CISTPL_MAX_CIS_SIZE];
-} cisdump_t;
-
-
-int pcmcia_replace_cis(struct pcmcia_socket *s, cisdump_t *cis);
-
-/* don't use outside of PCMCIA core yet */
-int pccard_get_next_tuple(struct pcmcia_socket *s, unsigned int func, tuple_t *tuple);
-int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function, tuple_t *tuple);
-int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple);
-int pccard_parse_tuple(tuple_t *tuple, cisparse_t *parse);
-
-int pccard_validate_cis(struct pcmcia_socket *s, unsigned int function, unsigned int *count);
-
-/* ... but use these wrappers instead */
-#define pcmcia_get_first_tuple(p_dev, tuple) \
-                pccard_get_first_tuple(p_dev->socket, p_dev->func, tuple)
-
-#define pcmcia_get_next_tuple(p_dev, tuple) \
-                pccard_get_next_tuple(p_dev->socket, p_dev->func, tuple)
-
-#define pcmcia_get_tuple_data(p_dev, tuple) \
-                pccard_get_tuple_data(p_dev->socket, tuple)
-
-#define pcmcia_parse_tuple(p_dev, tuple, parse) \
-                pccard_parse_tuple(tuple, parse)
-
-#define pcmcia_validate_cis(p_dev, info) \
-                pccard_validate_cis(p_dev->socket, p_dev->func, info)
-
 #endif /* LINUX_CISTPL_H */
diff --git a/include/pcmcia/cs.h b/include/pcmcia/cs.h
index 45d84b275789..904468a191ef 100644
--- a/include/pcmcia/cs.h
+++ b/include/pcmcia/cs.h
@@ -28,72 +28,16 @@ typedef struct conf_reg_t {
 #define CS_WRITE        2
 
 /* for AdjustResourceInfo */
-typedef struct adjust_t {
-    u_int       Action;
-    u_int       Resource;
-    u_int       Attributes;
-    union {
-        struct memory {
-            u_long      Base;
-            u_long      Size;
-        } memory;
-        struct io {
-            ioaddr_t    BasePort;
-            ioaddr_t    NumPorts;
-            u_int       IOAddrLines;
-        } io;
-        struct irq {
-            u_int       IRQ;
-        } irq;
-    } resource;
-} adjust_t;
-
 /* Action field */
 #define REMOVE_MANAGED_RESOURCE         1
 #define ADD_MANAGED_RESOURCE            2
-#define GET_FIRST_MANAGED_RESOURCE      3
-#define GET_NEXT_MANAGED_RESOURCE       4
-/* Resource field */
-#define RES_MEMORY_RANGE                1
-#define RES_IO_RANGE                    2
-#define RES_IRQ                         3
-/* Attribute field */
-#define RES_IRQ_TYPE                    0x03
-#define RES_IRQ_TYPE_EXCLUSIVE          0
-#define RES_IRQ_TYPE_TIME               1
-#define RES_IRQ_TYPE_DYNAMIC            2
-#define RES_IRQ_CSC                     0x04
-#define RES_SHARED                      0x08
-#define RES_RESERVED                    0x10
-#define RES_ALLOCATED                   0x20
-#define RES_REMOVED                     0x40
+
 
 typedef struct event_callback_args_t {
         struct pcmcia_device    *client_handle;
         void                    *client_data;
 } event_callback_args_t;
 
-/* for GetConfigurationInfo */
-typedef struct config_info_t {
-    u_char      Function;
-    u_int       Attributes;
-    u_int       Vcc, Vpp1, Vpp2;
-    u_int       IntType;
-    u_int       ConfigBase;
-    u_char      Status, Pin, Copy, Option, ExtStatus;
-    u_int       Present;
-    u_int       CardValues;
-    u_int       AssignedIRQ;
-    u_int       IRQAttributes;
-    ioaddr_t    BasePort1;
-    ioaddr_t    NumPorts1;
-    u_int       Attributes1;
-    ioaddr_t    BasePort2;
-    ioaddr_t    NumPorts2;
-    u_int       Attributes2;
-    u_int       IOAddrLines;
-} config_info_t;
-
 /* For CardValues field */
 #define CV_OPTION_VALUE         0x01
 #define CV_STATUS_VALUE         0x02
@@ -257,22 +201,6 @@ typedef struct win_req_t {
 #define WIN_BAR_MASK            0xe000
 #define WIN_BAR_SHIFT           13
 
-/* Attributes for RegisterClient -- UNUSED -- */
-#define INFO_MASTER_CLIENT      0x01
-#define INFO_IO_CLIENT          0x02
-#define INFO_MTD_CLIENT         0x04
-#define INFO_MEM_CLIENT         0x08
-#define MAX_NUM_CLIENTS         3
-
-#define INFO_CARD_SHARE         0x10
-#define INFO_CARD_EXCL          0x20
-
-typedef struct cs_status_t {
-    u_char      Function;
-    event_t     CardState;
-    event_t     SocketState;
-} cs_status_t;
-
 typedef struct error_info_t {
     int         func;
     int         retcode;
@@ -308,95 +236,4 @@ typedef struct error_info_t {
 #define CS_EVENT_3VCARD                 0x200000
 #define CS_EVENT_XVCARD                 0x400000
 
-/* Return codes */
-#define CS_SUCCESS              0x00
-#define CS_BAD_ADAPTER          0x01
-#define CS_BAD_ATTRIBUTE        0x02
-#define CS_BAD_BASE             0x03
-#define CS_BAD_EDC              0x04
-#define CS_BAD_IRQ              0x06
-#define CS_BAD_OFFSET           0x07
-#define CS_BAD_PAGE             0x08
-#define CS_READ_FAILURE         0x09
-#define CS_BAD_SIZE             0x0a
-#define CS_BAD_SOCKET           0x0b
-#define CS_BAD_TYPE             0x0d
-#define CS_BAD_VCC              0x0e
-#define CS_BAD_VPP              0x0f
-#define CS_BAD_WINDOW           0x11
-#define CS_WRITE_FAILURE        0x12
-#define CS_NO_CARD              0x14
-#define CS_UNSUPPORTED_FUNCTION 0x15
-#define CS_UNSUPPORTED_MODE     0x16
-#define CS_BAD_SPEED            0x17
-#define CS_BUSY                 0x18
-#define CS_GENERAL_FAILURE      0x19
-#define CS_WRITE_PROTECTED      0x1a
-#define CS_BAD_ARG_LENGTH       0x1b
-#define CS_BAD_ARGS             0x1c
-#define CS_CONFIGURATION_LOCKED 0x1d
-#define CS_IN_USE               0x1e
-#define CS_NO_MORE_ITEMS        0x1f
-#define CS_OUT_OF_RESOURCE      0x20
-#define CS_BAD_HANDLE           0x21
-
-#define CS_BAD_TUPLE            0x40
-
-#ifdef __KERNEL__
-
-/*
- *  The main Card Services entry point
- */
-
-enum service {
-    AccessConfigurationRegister, AddSocketServices,
-    AdjustResourceInfo, CheckEraseQueue, CloseMemory, CopyMemory,
-    DeregisterClient, DeregisterEraseQueue, GetCardServicesInfo,
-    GetClientInfo, GetConfigurationInfo, GetEventMask,
-    GetFirstClient, GetFirstPartion, GetFirstRegion, GetFirstTuple,
-    GetNextClient, GetNextPartition, GetNextRegion, GetNextTuple,
-    GetStatus, GetTupleData, MapLogSocket, MapLogWindow, MapMemPage,
-    MapPhySocket, MapPhyWindow, ModifyConfiguration, ModifyWindow,
-    OpenMemory, ParseTuple, ReadMemory, RegisterClient,
-    RegisterEraseQueue, RegisterMTD, RegisterTimer,
-    ReleaseConfiguration, ReleaseExclusive, ReleaseIO, ReleaseIRQ,
-    ReleaseSocketMask, ReleaseWindow, ReplaceSocketServices,
-    RequestConfiguration, RequestExclusive, RequestIO, RequestIRQ,
-    RequestSocketMask, RequestWindow, ResetCard, ReturnSSEntry,
-    SetEventMask, SetRegion, ValidateCIS, VendorSpecific,
-    WriteMemory, BindDevice, BindMTD, ReportError,
-    SuspendCard, ResumeCard, EjectCard, InsertCard, ReplaceCIS,
-    GetFirstWindow, GetNextWindow, GetMemPage
-};
-
-struct pcmcia_socket;
-
-int pcmcia_access_configuration_register(struct pcmcia_device *p_dev, conf_reg_t *reg);
-int pcmcia_get_configuration_info(struct pcmcia_device *p_dev, config_info_t *config);
-int pcmcia_get_mem_page(window_handle_t win, memreq_t *req);
-int pcmcia_map_mem_page(window_handle_t win, memreq_t *req);
-int pcmcia_modify_configuration(struct pcmcia_device *p_dev, modconf_t *mod);
-int pcmcia_release_window(window_handle_t win);
-int pcmcia_request_configuration(struct pcmcia_device *p_dev, config_req_t *req);
-int pcmcia_request_io(struct pcmcia_device *p_dev, io_req_t *req);
-int pcmcia_request_irq(struct pcmcia_device *p_dev, irq_req_t *req);
-int pcmcia_request_window(struct pcmcia_device **p_dev, win_req_t *req, window_handle_t *wh);
-int pcmcia_suspend_card(struct pcmcia_socket *skt);
-int pcmcia_resume_card(struct pcmcia_socket *skt);
-int pcmcia_eject_card(struct pcmcia_socket *skt);
-int pcmcia_insert_card(struct pcmcia_socket *skt);
-int pccard_reset_card(struct pcmcia_socket *skt);
-
-struct pcmcia_device * pcmcia_dev_present(struct pcmcia_device *p_dev);
-void pcmcia_disable_device(struct pcmcia_device *p_dev);
-
-struct pcmcia_socket * pcmcia_get_socket(struct pcmcia_socket *skt);
-void pcmcia_put_socket(struct pcmcia_socket *skt);
-
-/* compatibility functions */
-#define pcmcia_reset_card(p_dev, req) \
-                pccard_reset_card(p_dev->socket)
-
-#endif /* __KERNEL__ */
-
 #endif /* _LINUX_CS_H */
diff --git a/include/pcmcia/cs_types.h b/include/pcmcia/cs_types.h
index f402a0f435b4..315965a37930 100644
--- a/include/pcmcia/cs_types.h
+++ b/include/pcmcia/cs_types.h
@@ -21,14 +21,6 @@
 #include <sys/types.h>
 #endif
 
-#if defined(__arm__) || defined(__mips__) || defined(__avr32__) || \
-        defined(__bfin__)
-/* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */
-typedef u_int   ioaddr_t;
-#else
-typedef u_short ioaddr_t;
-#endif
-
 typedef u_short socket_t;
 typedef u_int   event_t;
 typedef u_char  cisdata_t;
diff --git a/include/pcmcia/device_id.h b/include/pcmcia/device_id.h
index e04e0b0d9a25..c33ea08352b8 100644
--- a/include/pcmcia/device_id.h
+++ b/include/pcmcia/device_id.h
@@ -1,10 +1,19 @@
 /*
- * Copyright (2003-2004)        Dominik Brodowski <linux@brodo.de>
- *                              David Woodhouse
+ * device_id.h -- PCMCIA driver matching helpers
  *
- * License: GPL v2
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * (C) 2003 - 2004      David Woodhouse
+ * (C) 2003 - 2004      Dominik Brodowski
  */
 
+#ifndef _LINUX_PCMCIA_DEVICE_ID_H
+#define _LINUX_PCMCIA_DEVICE_ID_H
+
+#ifdef __KERNEL__
+
 #define PCMCIA_DEVICE_MANF_CARD(manf, card) { \
         .match_flags = PCMCIA_DEV_ID_MATCH_MANF_ID| \
                         PCMCIA_DEV_ID_MATCH_CARD_ID, \
@@ -256,3 +265,6 @@
 
 
 #define PCMCIA_DEVICE_NULL { .match_flags = 0, }
+
+#endif /* __KERNEL__ */
+#endif /* _LINUX_PCMCIA_DEVICE_ID_H */
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index b316027c853d..a2be80b9a095 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -10,7 +10,7 @@
  * are Copyright (C) 1999 David A. Hinds.  All Rights Reserved.
  *
  * (C) 1999             David A. Hinds
- * (C) 2003 - 2004      Dominik Brodowski
+ * (C) 2003 - 2008      Dominik Brodowski
  */
 
 #ifndef _LINUX_DS_H
@@ -23,108 +23,21 @@
 #include <pcmcia/cs_types.h>
 #include <pcmcia/device_id.h>
 
-typedef struct tuple_parse_t {
-    tuple_t             tuple;
-    cisdata_t           data[255];
-    cisparse_t          parse;
-} tuple_parse_t;
-
-typedef struct win_info_t {
-    window_handle_t     handle;
-    win_req_t           window;
-    memreq_t            map;
-} win_info_t;
-    
-typedef struct bind_info_t {
-    dev_info_t          dev_info;
-    u_char              function;
-    struct pcmcia_device *instance;
-    char                name[DEV_NAME_LEN];
-    u_short             major, minor;
-    void                *next;
-} bind_info_t;
-
-typedef struct mtd_info_t {
-    dev_info_t          dev_info;
-    u_int               Attributes;
-    u_int               CardOffset;
-} mtd_info_t;
-
-typedef struct region_info_t {
-    u_int               Attributes;
-    u_int               CardOffset;
-    u_int               RegionSize;
-    u_int               AccessSpeed;
-    u_int               BlockSize;
-    u_int               PartMultiple;
-    u_char              JedecMfr, JedecInfo;
-    memory_handle_t     next;
-} region_info_t;
-#define REGION_TYPE             0x0001
-#define REGION_TYPE_CM          0x0000
-#define REGION_TYPE_AM          0x0001
-#define REGION_PREFETCH         0x0008
-#define REGION_CACHEABLE        0x0010
-#define REGION_BAR_MASK         0xe000
-#define REGION_BAR_SHIFT        13
-
-typedef union ds_ioctl_arg_t {
-    adjust_t            adjust;
-    config_info_t       config;
-    tuple_t             tuple;
-    tuple_parse_t       tuple_parse;
-    client_req_t        client_req;
-    cs_status_t         status;
-    conf_reg_t          conf_reg;
-    cisinfo_t           cisinfo;
-    region_info_t       region;
-    bind_info_t         bind_info;
-    mtd_info_t          mtd_info;
-    win_info_t          win_info;
-    cisdump_t           cisdump;
-} ds_ioctl_arg_t;
-
-#define DS_ADJUST_RESOURCE_INFO         _IOWR('d', 2, adjust_t)
-#define DS_GET_CONFIGURATION_INFO       _IOWR('d', 3, config_info_t)
-#define DS_GET_FIRST_TUPLE              _IOWR('d', 4, tuple_t)
-#define DS_GET_NEXT_TUPLE               _IOWR('d', 5, tuple_t)
-#define DS_GET_TUPLE_DATA               _IOWR('d', 6, tuple_parse_t)
-#define DS_PARSE_TUPLE                  _IOWR('d', 7, tuple_parse_t)
-#define DS_RESET_CARD                   _IO  ('d', 8)
-#define DS_GET_STATUS                   _IOWR('d', 9, cs_status_t)
-#define DS_ACCESS_CONFIGURATION_REGISTER _IOWR('d', 10, conf_reg_t)
-#define DS_VALIDATE_CIS                 _IOR ('d', 11, cisinfo_t)
-#define DS_SUSPEND_CARD                 _IO  ('d', 12)
-#define DS_RESUME_CARD                  _IO  ('d', 13)
-#define DS_EJECT_CARD                   _IO  ('d', 14)
-#define DS_INSERT_CARD                  _IO  ('d', 15)
-#define DS_GET_FIRST_REGION             _IOWR('d', 16, region_info_t)
-#define DS_GET_NEXT_REGION              _IOWR('d', 17, region_info_t)
-#define DS_REPLACE_CIS                  _IOWR('d', 18, cisdump_t)
-#define DS_GET_FIRST_WINDOW             _IOR ('d', 19, win_info_t)
-#define DS_GET_NEXT_WINDOW              _IOWR('d', 20, win_info_t)
-#define DS_GET_MEM_PAGE                 _IOWR('d', 21, win_info_t)
-
-#define DS_BIND_REQUEST                 _IOWR('d', 60, bind_info_t)
-#define DS_GET_DEVICE_INFO              _IOWR('d', 61, bind_info_t) 
-#define DS_GET_NEXT_DEVICE              _IOWR('d', 62, bind_info_t) 
-#define DS_UNBIND_REQUEST               _IOW ('d', 63, bind_info_t)
-#define DS_BIND_MTD                     _IOWR('d', 64, mtd_info_t)
-
 #ifdef __KERNEL__
 #include <linux/device.h>
 #include <pcmcia/ss.h>
 
-typedef struct dev_node_t {
-    char                dev_name[DEV_NAME_LEN];
-    u_short             major, minor;
-    struct dev_node_t   *next;
-} dev_node_t;
-
-
+/*
+ * PCMCIA device drivers (16-bit cards only; 32-bit cards require CardBus
+ * a.k.a. PCI drivers
+ */
 struct pcmcia_socket;
+struct pcmcia_device;
 struct config_t;
 
+/* dynamic device IDs for PCMCIA device drivers. See
+ * Documentation/pcmcia/driver.txt for details.
+*/
 struct pcmcia_dynids {
         spinlock_t              lock;
         struct list_head        list;
@@ -147,6 +60,14 @@ struct pcmcia_driver {
 int pcmcia_register_driver(struct pcmcia_driver *driver);
 void pcmcia_unregister_driver(struct pcmcia_driver *driver);
 
+/* Some drivers use dev_node_t to store char or block device information.
+ * Don't use this in new drivers, though.
+ */
+typedef struct dev_node_t {
+        char                    dev_name[DEV_NAME_LEN];
+        u_short                 major, minor;
+        struct dev_node_t       *next;
+} dev_node_t;
 
 struct pcmcia_device {
         /* the socket and the device_no [for multifunction devices]
@@ -216,10 +137,304 @@ struct pcmcia_device {
 #define to_pcmcia_dev(n) container_of(n, struct pcmcia_device, dev)
 #define to_pcmcia_drv(n) container_of(n, struct pcmcia_driver, drv)
 
+/* deprecated -- don't use! */
 #define handle_to_dev(handle) (handle->dev)
 
-/* error reporting */
-void cs_error(struct pcmcia_device *handle, int func, int ret);
+
+/* (deprecated) error reporting by PCMCIA devices. Use dev_printk()
+ * or dev_dbg() directly in the driver, without referring to pcmcia_error_func()
+ * and/or pcmcia_error_ret() for those functions will go away soon.
+ */
+enum service {
+    AccessConfigurationRegister, AddSocketServices,
+    AdjustResourceInfo, CheckEraseQueue, CloseMemory, CopyMemory,
+    DeregisterClient, DeregisterEraseQueue, GetCardServicesInfo,
+    GetClientInfo, GetConfigurationInfo, GetEventMask,
+    GetFirstClient, GetFirstPartion, GetFirstRegion, GetFirstTuple,
+    GetNextClient, GetNextPartition, GetNextRegion, GetNextTuple,
+    GetStatus, GetTupleData, MapLogSocket, MapLogWindow, MapMemPage,
+    MapPhySocket, MapPhyWindow, ModifyConfiguration, ModifyWindow,
+    OpenMemory, ParseTuple, ReadMemory, RegisterClient,
+    RegisterEraseQueue, RegisterMTD, RegisterTimer,
+    ReleaseConfiguration, ReleaseExclusive, ReleaseIO, ReleaseIRQ,
+    ReleaseSocketMask, ReleaseWindow, ReplaceSocketServices,
+    RequestConfiguration, RequestExclusive, RequestIO, RequestIRQ,
+    RequestSocketMask, RequestWindow, ResetCard, ReturnSSEntry,
+    SetEventMask, SetRegion, ValidateCIS, VendorSpecific,
+    WriteMemory, BindDevice, BindMTD, ReportError,
+    SuspendCard, ResumeCard, EjectCard, InsertCard, ReplaceCIS,
+    GetFirstWindow, GetNextWindow, GetMemPage
+};
+const char *pcmcia_error_func(int func);
+const char *pcmcia_error_ret(int ret);
+
+#define cs_error(p_dev, func, ret)                      \
+        {                                               \
+                dev_printk(KERN_NOTICE, &p_dev->dev,    \
+                           "%s : %s\n",                 \
+                           pcmcia_error_func(func),     \
+                           pcmcia_error_ret(ret));      \
+        }
+
+/* CIS access.
+ * Use the pcmcia_* versions in PCMCIA drivers
+ */
+int pcmcia_parse_tuple(tuple_t *tuple, cisparse_t *parse);
+
+int pccard_get_first_tuple(struct pcmcia_socket *s, unsigned int function,
+                           tuple_t *tuple);
+#define pcmcia_get_first_tuple(p_dev, tuple) \
+                pccard_get_first_tuple(p_dev->socket, p_dev->func, tuple)
+
+int pccard_get_next_tuple(struct pcmcia_socket *s, unsigned int function,
+                          tuple_t *tuple);
+#define pcmcia_get_next_tuple(p_dev, tuple) \
+                pccard_get_next_tuple(p_dev->socket, p_dev->func, tuple)
+
+int pccard_get_tuple_data(struct pcmcia_socket *s, tuple_t *tuple);
+#define pcmcia_get_tuple_data(p_dev, tuple) \
+                pccard_get_tuple_data(p_dev->socket, tuple)
+
+
+/* loop CIS entries for valid configuration */
+int pcmcia_loop_config(struct pcmcia_device *p_dev,
+                       int      (*conf_check)   (struct pcmcia_device *p_dev,
+                                                 cistpl_cftable_entry_t *cf,
+                                                 cistpl_cftable_entry_t *dflt,
+                                                 unsigned int vcc,
+                                                 void *priv_data),
+                       void *priv_data);
+
+/* is the device still there? */
+struct pcmcia_device *pcmcia_dev_present(struct pcmcia_device *p_dev);
+
+/* low-level interface reset */
+int pcmcia_reset_card(struct pcmcia_socket *skt);
+
+/* CIS config */
+int pcmcia_access_configuration_register(struct pcmcia_device *p_dev,
+                                         conf_reg_t *reg);
+
+/* device configuration */
+int pcmcia_request_io(struct pcmcia_device *p_dev, io_req_t *req);
+int pcmcia_request_irq(struct pcmcia_device *p_dev, irq_req_t *req);
+int pcmcia_request_configuration(struct pcmcia_device *p_dev,
+                                 config_req_t *req);
+
+int pcmcia_request_window(struct pcmcia_device **p_dev, win_req_t *req,
+                          window_handle_t *wh);
+int pcmcia_release_window(window_handle_t win);
+
+int pcmcia_get_mem_page(window_handle_t win, memreq_t *req);
+int pcmcia_map_mem_page(window_handle_t win, memreq_t *req);
+
+int pcmcia_modify_configuration(struct pcmcia_device *p_dev, modconf_t *mod);
+void pcmcia_disable_device(struct pcmcia_device *p_dev);
 
 #endif /* __KERNEL__ */
+
+
+
+/* Below, there are only definitions which are used by
+ * - the PCMCIA ioctl
+ * - deprecated PCMCIA userspace tools only
+ *
+ * here be dragons ... here be dragons ... here be dragons ... here be drag
+ */
+
+#if defined(CONFIG_PCMCIA_IOCTL) || !defined(__KERNEL__)
+
+#if defined(__arm__) || defined(__mips__) || defined(__avr32__) || \
+        defined(__bfin__)
+/* This (ioaddr_t) is exposed to userspace & hence cannot be changed. */
+typedef u_int   ioaddr_t;
+#else
+typedef u_short ioaddr_t;
+#endif
+
+/* for AdjustResourceInfo */
+typedef struct adjust_t {
+        u_int                   Action;
+        u_int                   Resource;
+        u_int                   Attributes;
+        union {
+                struct memory {
+                        u_long          Base;
+                        u_long          Size;
+                } memory;
+                struct io {
+                        ioaddr_t        BasePort;
+                        ioaddr_t        NumPorts;
+                        u_int           IOAddrLines;
+                } io;
+                struct irq {
+                        u_int           IRQ;
+                } irq;
+        } resource;
+} adjust_t;
+
+/* Action field */
+#define REMOVE_MANAGED_RESOURCE         1
+#define ADD_MANAGED_RESOURCE            2
+#define GET_FIRST_MANAGED_RESOURCE      3
+#define GET_NEXT_MANAGED_RESOURCE       4
+/* Resource field */
+#define RES_MEMORY_RANGE                1
+#define RES_IO_RANGE                    2
+#define RES_IRQ                         3
+/* Attribute field */
+#define RES_IRQ_TYPE                    0x03
+#define RES_IRQ_TYPE_EXCLUSIVE          0
+#define RES_IRQ_TYPE_TIME               1
+#define RES_IRQ_TYPE_DYNAMIC            2
+#define RES_IRQ_CSC                     0x04
+#define RES_SHARED                      0x08
+#define RES_RESERVED                    0x10
+#define RES_ALLOCATED                   0x20
+#define RES_REMOVED                     0x40
+
+
+typedef struct tuple_parse_t {
+        tuple_t                 tuple;
+        cisdata_t               data[255];
+        cisparse_t              parse;
+} tuple_parse_t;
+
+typedef struct win_info_t {
+        window_handle_t         handle;
+        win_req_t               window;
+        memreq_t                map;
+} win_info_t;
+
+typedef struct bind_info_t {
+        dev_info_t              dev_info;
+        u_char                  function;
+        struct pcmcia_device    *instance;
+        char                    name[DEV_NAME_LEN];
+        u_short                 major, minor;
+        void                    *next;
+} bind_info_t;
+
+typedef struct mtd_info_t {
+        dev_info_t              dev_info;
+        u_int                   Attributes;
+        u_int                   CardOffset;
+} mtd_info_t;
+
+typedef struct region_info_t {
+        u_int                   Attributes;
+        u_int                   CardOffset;
+        u_int                   RegionSize;
+        u_int                   AccessSpeed;
+        u_int                   BlockSize;
+        u_int                   PartMultiple;
+        u_char                  JedecMfr, JedecInfo;
+        memory_handle_t         next;
+} region_info_t;
+
+#define REGION_TYPE             0x0001
+#define REGION_TYPE_CM          0x0000
+#define REGION_TYPE_AM          0x0001
+#define REGION_PREFETCH         0x0008
+#define REGION_CACHEABLE        0x0010
+#define REGION_BAR_MASK         0xe000
+#define REGION_BAR_SHIFT        13
+
+/* For ReplaceCIS */
+typedef struct cisdump_t {
+        u_int                   Length;
+        cisdata_t               Data[CISTPL_MAX_CIS_SIZE];
+} cisdump_t;
+
+/* for GetConfigurationInfo */
+typedef struct config_info_t {
+        u_char                  Function;
+        u_int                   Attributes;
+        u_int                   Vcc, Vpp1, Vpp2;
+        u_int                   IntType;
+        u_int                   ConfigBase;
+        u_char                  Status, Pin, Copy, Option, ExtStatus;
+        u_int                   Present;
+        u_int                   CardValues;
+        u_int                   AssignedIRQ;
+        u_int                   IRQAttributes;
+        ioaddr_t                BasePort1;
+        ioaddr_t                NumPorts1;
+        u_int                   Attributes1;
+        ioaddr_t                BasePort2;
+        ioaddr_t                NumPorts2;
+        u_int                   Attributes2;
+        u_int                   IOAddrLines;
+} config_info_t;
+
+/* For ValidateCIS */
+typedef struct cisinfo_t {
+        u_int                   Chains;
+} cisinfo_t;
+
+typedef struct cs_status_t {
+        u_char                  Function;
+        event_t                 CardState;
+        event_t                 SocketState;
+} cs_status_t;
+
+typedef union ds_ioctl_arg_t {
+        adjust_t                adjust;
+        config_info_t           config;
+        tuple_t                 tuple;
+        tuple_parse_t           tuple_parse;
+        client_req_t            client_req;
+        cs_status_t             status;
+        conf_reg_t              conf_reg;
+        cisinfo_t               cisinfo;
+        region_info_t           region;
+        bind_info_t             bind_info;
+        mtd_info_t              mtd_info;
+        win_info_t              win_info;
+        cisdump_t               cisdump;
+} ds_ioctl_arg_t;
+
+#define DS_ADJUST_RESOURCE_INFO                 _IOWR('d',  2, adjust_t)
+#define DS_GET_CONFIGURATION_INFO               _IOWR('d',  3, config_info_t)
+#define DS_GET_FIRST_TUPLE                      _IOWR('d',  4, tuple_t)
+#define DS_GET_NEXT_TUPLE                       _IOWR('d',  5, tuple_t)
+#define DS_GET_TUPLE_DATA                       _IOWR('d',  6, tuple_parse_t)
+#define DS_PARSE_TUPLE                          _IOWR('d',  7, tuple_parse_t)
+#define DS_RESET_CARD                           _IO  ('d',  8)
+#define DS_GET_STATUS                           _IOWR('d',  9, cs_status_t)
+#define DS_ACCESS_CONFIGURATION_REGISTER        _IOWR('d', 10, conf_reg_t)
+#define DS_VALIDATE_CIS                         _IOR ('d', 11, cisinfo_t)
+#define DS_SUSPEND_CARD                         _IO  ('d', 12)
+#define DS_RESUME_CARD                          _IO  ('d', 13)
+#define DS_EJECT_CARD                           _IO  ('d', 14)
+#define DS_INSERT_CARD                          _IO  ('d', 15)
+#define DS_GET_FIRST_REGION                     _IOWR('d', 16, region_info_t)
+#define DS_GET_NEXT_REGION                      _IOWR('d', 17, region_info_t)
+#define DS_REPLACE_CIS                          _IOWR('d', 18, cisdump_t)
+#define DS_GET_FIRST_WINDOW                     _IOR ('d', 19, win_info_t)
+#define DS_GET_NEXT_WINDOW                      _IOWR('d', 20, win_info_t)
+#define DS_GET_MEM_PAGE                         _IOWR('d', 21, win_info_t)
+
+#define DS_BIND_REQUEST                         _IOWR('d', 60, bind_info_t)
+#define DS_GET_DEVICE_INFO                      _IOWR('d', 61, bind_info_t)
+#define DS_GET_NEXT_DEVICE                      _IOWR('d', 62, bind_info_t)
+#define DS_UNBIND_REQUEST                       _IOW ('d', 63, bind_info_t)
+#define DS_BIND_MTD                             _IOWR('d', 64, mtd_info_t)
+
+
+/* used in userspace only */
+#define CS_IN_USE                       0x1e
+
+#define INFO_MASTER_CLIENT      0x01
+#define INFO_IO_CLIENT          0x02
+#define INFO_MTD_CLIENT         0x04
+#define INFO_MEM_CLIENT         0x08
+#define MAX_NUM_CLIENTS         3
+
+#define INFO_CARD_SHARE         0x10
+#define INFO_CARD_EXCL          0x20
+
+
+#endif /* !defined(__KERNEL__) || defined(CONFIG_PCMCIA_IOCTL) */
+
 #endif /* _LINUX_DS_H */
diff --git a/include/pcmcia/ss.h b/include/pcmcia/ss.h
index ed919dd9bb5c..9b4ac9385f5d 100644
--- a/include/pcmcia/ss.h
+++ b/include/pcmcia/ss.h
@@ -53,10 +53,10 @@
 
 /* for GetSocket, SetSocket */
 typedef struct socket_state_t {
-    u_int       flags;
-    u_int       csc_mask;
-    u_char      Vcc, Vpp;
-    u_char      io_irq;
+        u_int   flags;
+        u_int   csc_mask;
+        u_char  Vcc, Vpp;
+        u_char  io_irq;
 } socket_state_t;
 
 extern socket_state_t dead_socket;
@@ -86,79 +86,22 @@ extern socket_state_t dead_socket;
 #define HOOK_POWER_PRE  0x01
 #define HOOK_POWER_POST 0x02
 
-
 typedef struct pccard_io_map {
-    u_char      map;
-    u_char      flags;
-    u_short     speed;
-    u_int       start, stop;
+        u_char  map;
+        u_char  flags;
+        u_short speed;
+        u_int   start, stop;
 } pccard_io_map;
 
 typedef struct pccard_mem_map {
-    u_char      map;
-    u_char      flags;
-    u_short     speed;
-    u_long      static_start;
-    u_int       card_start;
-    struct resource *res;
+        u_char          map;
+        u_char          flags;
+        u_short         speed;
+        u_long          static_start;
+        u_int           card_start;
+        struct resource *res;
 } pccard_mem_map;
 
-typedef struct cb_bridge_map {
-    u_char      map;
-    u_char      flags;
-    u_int       start, stop;
-} cb_bridge_map;
-
-/*
- * Socket operations.
- */
-struct pcmcia_socket;
-
-struct pccard_operations {
-        int (*init)(struct pcmcia_socket *sock);
-        int (*suspend)(struct pcmcia_socket *sock);
-        int (*get_status)(struct pcmcia_socket *sock, u_int *value);
-        int (*set_socket)(struct pcmcia_socket *sock, socket_state_t *state);
-        int (*set_io_map)(struct pcmcia_socket *sock, struct pccard_io_map *io);
-        int (*set_mem_map)(struct pcmcia_socket *sock, struct pccard_mem_map *mem);
-};
-
-struct pccard_resource_ops {
-        int     (*validate_mem)         (struct pcmcia_socket *s);
-        int     (*adjust_io_region)     (struct resource *res,
-                                         unsigned long r_start,
-                                         unsigned long r_end,
-                                         struct pcmcia_socket *s);
-        struct resource* (*find_io)     (unsigned long base, int num,
-                                         unsigned long align,
-                                         struct pcmcia_socket *s);
-        struct resource* (*find_mem)    (unsigned long base, unsigned long num,
-                                         unsigned long align, int low,
-                                         struct pcmcia_socket *s);
-        int     (*add_io)               (struct pcmcia_socket *s,
-                                         unsigned int action,
-                                         unsigned long r_start,
-                                         unsigned long r_end);
-        int     (*add_mem)              (struct pcmcia_socket *s,
-                                         unsigned int action,
-                                         unsigned long r_start,
-                                         unsigned long r_end);
-        int     (*init)                 (struct pcmcia_socket *s);
-        void    (*exit)                 (struct pcmcia_socket *s);
-};
-/* SS_CAP_STATIC_MAP */
-extern struct pccard_resource_ops pccard_static_ops;
-/* !SS_CAP_STATIC_MAP */
-extern struct pccard_resource_ops pccard_nonstatic_ops;
-
-/* static mem, dynamic IO sockets */
-extern struct pccard_resource_ops pccard_iodyn_ops;
-
-/*
- *  Calls to set up low-level "Socket Services" drivers
- */
-struct pcmcia_socket;
-
 typedef struct io_window_t {
         u_int                   InUse, Config;
         struct resource         *res;
@@ -179,10 +122,25 @@ typedef struct window_t {
 /* Maximum number of memory windows per socket */
 #define MAX_WIN 4
 
+
+/*
+ * Socket operations.
+ */
+struct pcmcia_socket;
+struct pccard_resource_ops;
 struct config_t;
 struct pcmcia_callback;
 struct user_info_t;
 
+struct pccard_operations {
+        int (*init)(struct pcmcia_socket *s);
+        int (*suspend)(struct pcmcia_socket *s);
+        int (*get_status)(struct pcmcia_socket *s, u_int *value);
+        int (*set_socket)(struct pcmcia_socket *s, socket_state_t *state);
+        int (*set_io_map)(struct pcmcia_socket *s, struct pccard_io_map *io);
+        int (*set_mem_map)(struct pcmcia_socket *s, struct pccard_mem_map *mem);
+};
+
 struct pcmcia_socket {
         struct module                   *owner;
         spinlock_t                      lock;
@@ -199,8 +157,8 @@ struct pcmcia_socket {
         io_window_t                     io[MAX_IO_WIN];
         window_t                        win[MAX_WIN];
         struct list_head                cis_cache;
-        u_int                           fake_cis_len;
-        char                            *fake_cis;
+        size_t                          fake_cis_len;
+        u8                              *fake_cis;
 
         struct list_head                socket_list;
         struct completion               socket_released;
@@ -218,12 +176,12 @@ struct pcmcia_socket {
         struct pci_dev *                cb_dev;
 
 
-        /* socket setup is done so resources should be able to be allocated. Only
-         * if set to 1, calls to find_{io,mem}_region are handled, and insertion
-         * events are actually managed by the PCMCIA layer.*/
+        /* socket setup is done so resources should be able to be allocated.
+         * Only if set to 1, calls to find_{io,mem}_region are handled, and
+         * insertio events are actually managed by the PCMCIA layer.*/
         u8                              resource_setup_done:1;
 
-        /* is set to one if resource setup is done using adjust_resource_info() */
+        /* It's old if resource setup is done using adjust_resource_info() */
         u8                              resource_setup_old:1;
         u8                              resource_setup_new:1;
 
@@ -236,75 +194,101 @@ struct pcmcia_socket {
 
         /* Zoom video behaviour is so chip specific its not worth adding
            this to _ops */
-        void                            (*zoom_video)(struct pcmcia_socket *, int);
+        void                            (*zoom_video)(struct pcmcia_socket *,
+                                                      int);
 
         /* so is power hook */
         int (*power_hook)(struct pcmcia_socket *sock, int operation);
-#ifdef CONFIG_CARDBUS
+
         /* allows tuning the CB bridge before loading driver for the CB card */
+#ifdef CONFIG_CARDBUS
         void (*tune_bridge)(struct pcmcia_socket *sock, struct pci_bus *bus);
 #endif
 
         /* state thread */
-        struct mutex                    skt_mutex;      /* protects socket h/w state */
-
         struct task_struct              *thread;
         struct completion               thread_done;
-        spinlock_t                      thread_lock;    /* protects thread_events */
         unsigned int                    thread_events;
+        /* protects socket h/w state */
+        struct mutex                    skt_mutex;
+        /* protects thread_events */
+        spinlock_t                      thread_lock;
 
         /* pcmcia (16-bit) */
         struct pcmcia_callback          *callback;
 
 #if defined(CONFIG_PCMCIA) || defined(CONFIG_PCMCIA_MODULE)
-        struct list_head                devices_list;   /*  PCMCIA devices */
-        u8                              device_count;   /* the number of devices, used
-                                                         * only internally and subject
-                                                         * to incorrectness and change */
+        /* The following elements refer to 16-bit PCMCIA devices inserted
+         * into the socket */
+        struct list_head                devices_list;
+
+        /* the number of devices, used only internally and subject to
+         * incorrectness and change */
+        u8                              device_count;
 
+        /* 16-bit state: */
         struct {
-                u8                      present:1,      /* PCMCIA card is present in socket */
-                                        busy:1,         /* "master" ioctl is used */
-                                        dead:1,         /* pcmcia module is being unloaded */
-                                        device_add_pending:1, /* a multifunction-device
-                                                               * add event is pending */
-                                        mfc_pfc:1,      /* the pending event adds a mfc (1) or pfc (0) */
-                                        reserved:3;
-        }                               pcmcia_state;
-
-        struct work_struct              device_add;     /* for adding further pseudo-multifunction
-                                                         * devices */
+                /* PCMCIA card is present in socket */
+                u8                      present:1;
+                /* "master" ioctl is used */
+                u8                      busy:1;
+                /* pcmcia module is being unloaded */
+                u8                      dead:1;
+                /* a multifunction-device add event is pending */
+                u8                      device_add_pending:1;
+                /* the pending event adds a mfc (1) or pfc (0) */
+                u8                      mfc_pfc:1;
+
+                u8                      reserved:3;
+        } pcmcia_state;
+
+
+        /* for adding further pseudo-multifunction devices */
+        struct work_struct              device_add;
 
 #ifdef CONFIG_PCMCIA_IOCTL
         struct user_info_t              *user;
         wait_queue_head_t               queue;
-#endif
-#endif
+#endif /* CONFIG_PCMCIA_IOCTL */
+#endif /* CONFIG_PCMCIA */
 
         /* cardbus (32-bit) */
 #ifdef CONFIG_CARDBUS
         struct resource *               cb_cis_res;
         void __iomem                    *cb_cis_virt;
-#endif
+#endif /* CONFIG_CARDBUS */
 
         /* socket device */
         struct device                   dev;
-        void                            *driver_data;   /* data internal to the socket driver */
-
+        /* data internal to the socket driver */
+        void                            *driver_data;
 };
 
-struct pcmcia_socket * pcmcia_get_socket_by_nr(unsigned int nr);
 
+/* socket drivers must define the resource operations type they use. There
+ * are three options:
+ * - pccard_static_ops          iomem and ioport areas are assigned statically
+ * - pccard_iodyn_ops           iomem areas is assigned statically, ioport
+ *                              areas dynamically
+ * - pccard_nonstatic_ops       iomem and ioport areas are assigned dynamically.
+ *                              If this option is selected, use
+ *                              "select PCCARD_NONSTATIC" in Kconfig.
+ */
+extern struct pccard_resource_ops pccard_static_ops;
+extern struct pccard_resource_ops pccard_iodyn_ops;
+extern struct pccard_resource_ops pccard_nonstatic_ops;
 
+/* socket drivers are expected to use these callbacks in their .drv struct */
+extern int pcmcia_socket_dev_suspend(struct device *dev, pm_message_t state);
+extern int pcmcia_socket_dev_resume(struct device *dev);
+
+/* socket drivers use this callback in their IRQ handler */
+extern void pcmcia_parse_events(struct pcmcia_socket *socket,
+                                unsigned int events);
 
-extern void pcmcia_parse_events(struct pcmcia_socket *socket, unsigned int events);
+/* to register and unregister a socket */
 extern int pcmcia_register_socket(struct pcmcia_socket *socket);
 extern void pcmcia_unregister_socket(struct pcmcia_socket *socket);
 
-extern struct class pcmcia_socket_class;
-
-/* socket drivers are expected to use these callbacks in their .drv struct */
-extern int pcmcia_socket_dev_suspend(struct device *dev, pm_message_t state);
-extern int pcmcia_socket_dev_resume(struct device *dev);
 
 #endif /* _LINUX_SS_H */
diff --git a/include/scsi/iscsi_if.h b/include/scsi/iscsi_if.h
index 16be12f1cbe8..0c9514de5df7 100644
--- a/include/scsi/iscsi_if.h
+++ b/include/scsi/iscsi_if.h
@@ -213,6 +213,8 @@ enum iscsi_err {
         ISCSI_ERR_DATA_DGST             = ISCSI_ERR_BASE + 15,
         ISCSI_ERR_PARAM_NOT_FOUND       = ISCSI_ERR_BASE + 16,
         ISCSI_ERR_NO_SCSI_CMD           = ISCSI_ERR_BASE + 17,
+        ISCSI_ERR_INVALID_HOST          = ISCSI_ERR_BASE + 18,
+        ISCSI_ERR_XMIT_FAILED           = ISCSI_ERR_BASE + 19,
 };
 
 /*
diff --git a/include/scsi/libiscsi.h b/include/scsi/libiscsi.h
index 5e75bb7f311c..61e53f14f7e1 100644
--- a/include/scsi/libiscsi.h
+++ b/include/scsi/libiscsi.h
@@ -287,6 +287,11 @@ struct iscsi_session {
         struct iscsi_pool       cmdpool;        /* PDU's pool */
 };
 
+enum {
+        ISCSI_HOST_SETUP,
+        ISCSI_HOST_REMOVED,
+};
+
 struct iscsi_host {
         char                    *initiatorname;
         /* hw address or netdev iscsi connection is bound to */
@@ -295,6 +300,12 @@ struct iscsi_host {
         /* local address */
         int                     local_port;
         char                    local_address[ISCSI_ADDRESS_BUF_LEN];
+
+        wait_queue_head_t       session_removal_wq;
+        /* protects sessions and state */
+        spinlock_t              lock;
+        int                     num_sessions;
+        int                     state;
 };
 
 /*
@@ -302,7 +313,7 @@ struct iscsi_host {
  */
 extern int iscsi_change_queue_depth(struct scsi_device *sdev, int depth);
 extern int iscsi_eh_abort(struct scsi_cmnd *sc);
-extern int iscsi_eh_host_reset(struct scsi_cmnd *sc);
+extern int iscsi_eh_target_reset(struct scsi_cmnd *sc);
 extern int iscsi_eh_device_reset(struct scsi_cmnd *sc);
 extern int iscsi_queuecommand(struct scsi_cmnd *sc,
                               void (*done)(struct scsi_cmnd *));
@@ -351,6 +362,8 @@ extern void iscsi_conn_stop(struct iscsi_cls_conn *, int);
 extern int iscsi_conn_bind(struct iscsi_cls_session *, struct iscsi_cls_conn *,
                            int);
 extern void iscsi_conn_failure(struct iscsi_conn *conn, enum iscsi_err err);
+extern void iscsi_session_failure(struct iscsi_cls_session *cls_session,
+                                  enum iscsi_err err);
 extern int iscsi_conn_get_param(struct iscsi_cls_conn *cls_conn,
                                 enum iscsi_param param, char *buf);
 extern void iscsi_suspend_tx(struct iscsi_conn *conn);
diff --git a/include/scsi/scsi.h b/include/scsi/scsi.h
index 5c40cc537d4c..a109165714d6 100644
--- a/include/scsi/scsi.h
+++ b/include/scsi/scsi.h
@@ -309,6 +309,20 @@ struct scsi_lun {
 };
 
 /*
+ * The Well Known LUNS (SAM-3) in our int representation of a LUN
+ */
+#define SCSI_W_LUN_BASE 0xc100
+#define SCSI_W_LUN_REPORT_LUNS (SCSI_W_LUN_BASE + 1)
+#define SCSI_W_LUN_ACCESS_CONTROL (SCSI_W_LUN_BASE + 2)
+#define SCSI_W_LUN_TARGET_LOG_PAGE (SCSI_W_LUN_BASE + 3)
+
+static inline int scsi_is_wlun(unsigned int lun)
+{
+        return (lun & 0xff00) == SCSI_W_LUN_BASE;
+}
+
+
+/*
  *  MESSAGE CODES
  */
 
@@ -367,6 +381,11 @@ struct scsi_lun {
 #define DID_IMM_RETRY   0x0c    /* Retry without decrementing retry count  */
 #define DID_REQUEUE     0x0d    /* Requeue command (no immediate retry) also
                                  * without decrementing the retry count    */
+#define DID_TRANSPORT_DISRUPTED 0x0e /* Transport error disrupted execution
+                                      * and the driver blocked the port to
+                                      * recover the link. Transport class will
+                                      * retry or fail IO */
+#define DID_TRANSPORT_FAILFAST  0x0f /* Transport class fastfailed the io */
 #define DRIVER_OK       0x00    /* Driver status                           */
 
 /*
@@ -412,6 +431,7 @@ struct scsi_lun {
 #define SCSI_MLQUEUE_HOST_BUSY   0x1055
 #define SCSI_MLQUEUE_DEVICE_BUSY 0x1056
 #define SCSI_MLQUEUE_EH_RETRY    0x1057
+#define SCSI_MLQUEUE_TARGET_BUSY 0x1058
 
 /*
  *  Use these to separate status msg and our bytes
diff --git a/include/scsi/scsi_cmnd.h b/include/scsi/scsi_cmnd.h
index f9f6e793575c..855bf95963e7 100644
--- a/include/scsi/scsi_cmnd.h
+++ b/include/scsi/scsi_cmnd.h
@@ -75,7 +75,6 @@ struct scsi_cmnd {
 
         int retries;
         int allowed;
-        int timeout_per_command;
 
         unsigned char prot_op;
         unsigned char prot_type;
@@ -86,7 +85,6 @@ struct scsi_cmnd {
         /* These elements define the operation we are about to perform */
         unsigned char *cmnd;
 
-        struct timer_list eh_timeout;   /* Used to time out the command. */
 
         /* These elements define the operation we ultimately want to perform */
         struct scsi_data_buffer sdb;
@@ -139,7 +137,6 @@ extern void scsi_put_command(struct scsi_cmnd *);
 extern void __scsi_put_command(struct Scsi_Host *, struct scsi_cmnd *,
                                struct device *);
 extern void scsi_finish_command(struct scsi_cmnd *cmd);
-extern void scsi_req_abort_cmd(struct scsi_cmnd *cmd);
 
 extern void *scsi_kmap_atomic_sg(struct scatterlist *sg, int sg_count,
                                  size_t *offset, size_t *len);
diff --git a/include/scsi/scsi_device.h b/include/scsi/scsi_device.h
index 80b2e93c2936..a37a8148a310 100644
--- a/include/scsi/scsi_device.h
+++ b/include/scsi/scsi_device.h
@@ -42,9 +42,11 @@ enum scsi_device_state {
                                  * originate in the mid-layer) */
         SDEV_OFFLINE,           /* Device offlined (by error handling or
                                  * user request */
-        SDEV_BLOCK,             /* Device blocked by scsi lld.  No scsi 
-                                 * commands from user or midlayer should be issued
-                                 * to the scsi lld. */
+        SDEV_BLOCK,             /* Device blocked by scsi lld.  No
+                                 * scsi commands from user or midlayer
+                                 * should be issued to the scsi
+                                 * lld. */
+        SDEV_CREATED_BLOCK,     /* same as above but for created devices */
 };
 
 enum scsi_device_event {
@@ -236,6 +238,16 @@ struct scsi_target {
                                                  * for the device at a time. */
         unsigned int            pdt_1f_for_no_lun;      /* PDT = 0x1f */
                                                 /* means no lun present */
+        /* commands actually active on LLD. protected by host lock. */
+        unsigned int            target_busy;
+        /*
+         * LLDs should set this in the slave_alloc host template callout.
+         * If set to zero then there is not limit.
+         */
+        unsigned int            can_queue;
+        unsigned int            target_blocked;
+        unsigned int            max_target_blocked;
+#define SCSI_DEFAULT_TARGET_BLOCKED     3
 
         char                    scsi_level;
         struct execute_work     ew;
@@ -384,10 +396,23 @@ static inline unsigned int sdev_id(struct scsi_device *sdev)
 #define scmd_id(scmd) sdev_id((scmd)->device)
 #define scmd_channel(scmd) sdev_channel((scmd)->device)
 
+/*
+ * checks for positions of the SCSI state machine
+ */
 static inline int scsi_device_online(struct scsi_device *sdev)
 {
         return sdev->sdev_state != SDEV_OFFLINE;
 }
+static inline int scsi_device_blocked(struct scsi_device *sdev)
+{
+        return sdev->sdev_state == SDEV_BLOCK ||
+                sdev->sdev_state == SDEV_CREATED_BLOCK;
+}
+static inline int scsi_device_created(struct scsi_device *sdev)
+{
+        return sdev->sdev_state == SDEV_CREATED ||
+                sdev->sdev_state == SDEV_CREATED_BLOCK;
+}
 
 /* accessor functions for the SCSI parameters */
 static inline int scsi_device_sync(struct scsi_device *sdev)
diff --git a/include/scsi/scsi_host.h b/include/scsi/scsi_host.h
index 44a55d1bf530..d123ca84e732 100644
--- a/include/scsi/scsi_host.h
+++ b/include/scsi/scsi_host.h
@@ -43,13 +43,6 @@ struct blk_queue_tags;
 #define DISABLE_CLUSTERING 0
 #define ENABLE_CLUSTERING 1
 
-enum scsi_eh_timer_return {
-        EH_NOT_HANDLED,
-        EH_HANDLED,
-        EH_RESET_TIMER,
-};
-
-
 struct scsi_host_template {
         struct module *module;
         const char *name;
@@ -347,7 +340,7 @@ struct scsi_host_template {
          *
          * Status: OPTIONAL
          */
-        enum scsi_eh_timer_return (* eh_timed_out)(struct scsi_cmnd *);
+        enum blk_eh_timer_return (*eh_timed_out)(struct scsi_cmnd *);
 
         /*
          * Name of proc directory
diff --git a/include/scsi/scsi_netlink.h b/include/scsi/scsi_netlink.h
index 8c1470cc8209..536752c40d41 100644
--- a/include/scsi/scsi_netlink.h
+++ b/include/scsi/scsi_netlink.h
@@ -22,6 +22,9 @@
 #ifndef SCSI_NETLINK_H
 #define SCSI_NETLINK_H
 
+#include <linux/netlink.h>
+
+
 /*
  * This file intended to be included by both kernel and user space
  */
@@ -55,7 +58,41 @@ struct scsi_nl_hdr {
 #define SCSI_NL_TRANSPORT_FC                    1
 #define SCSI_NL_MAX_TRANSPORTS                  2
 
-/* scsi_nl_hdr->msgtype values are defined in each transport */
+/* Transport-based scsi_nl_hdr->msgtype values are defined in each transport */
+
+/*
+ * GENERIC SCSI scsi_nl_hdr->msgtype Values
+ */
+        /* kernel -> user */
+#define SCSI_NL_SHOST_VENDOR                    0x0001
+        /* user -> kernel */
+/* SCSI_NL_SHOST_VENDOR msgtype is kernel->user and user->kernel */
+
+
+/*
+ * Message Structures :
+ */
+
+/* macro to round up message lengths to 8byte boundary */
+#define SCSI_NL_MSGALIGN(len)           (((len) + 7) & ~7)
+
+
+/*
+ * SCSI HOST Vendor Unique messages :
+ *   SCSI_NL_SHOST_VENDOR
+ *
+ * Note: The Vendor Unique message payload will begin directly after
+ *       this structure, with the length of the payload per vmsg_datalen.
+ *
+ * Note: When specifying vendor_id, be sure to read the Vendor Type and ID
+ *   formatting requirements specified below
+ */
+struct scsi_nl_host_vendor_msg {
+        struct scsi_nl_hdr snlh;                /* must be 1st element ! */
+        uint64_t vendor_id;
+        uint16_t host_no;
+        uint16_t vmsg_datalen;
+} __attribute__((aligned(sizeof(uint64_t))));
 
 
 /*
@@ -83,5 +120,28 @@ struct scsi_nl_hdr {
         }
 
 
+#ifdef __KERNEL__
+
+#include <scsi/scsi_host.h>
+
+/* Exported Kernel Interfaces */
+int scsi_nl_add_transport(u8 tport,
+         int (*msg_handler)(struct sk_buff *),
+        void (*event_handler)(struct notifier_block *, unsigned long, void *));
+void scsi_nl_remove_transport(u8 tport);
+
+int scsi_nl_add_driver(u64 vendor_id, struct scsi_host_template *hostt,
+        int (*nlmsg_handler)(struct Scsi_Host *shost, void *payload,
+                                 u32 len, u32 pid),
+        void (*nlevt_handler)(struct notifier_block *nb,
+                                 unsigned long event, void *notify_ptr));
+void scsi_nl_remove_driver(u64 vendor_id);
+
+void scsi_nl_send_transport_msg(u32 pid, struct scsi_nl_hdr *hdr);
+int scsi_nl_send_vendor_msg(u32 pid, unsigned short host_no, u64 vendor_id,
+                         char *data_buf, u32 data_len);
+
+#endif /* __KERNEL__ */
+
 #endif /* SCSI_NETLINK_H */
 
diff --git a/include/scsi/scsi_transport.h b/include/scsi/scsi_transport.h
index 490bd13a634c..0de32cd4e8a7 100644
--- a/include/scsi/scsi_transport.h
+++ b/include/scsi/scsi_transport.h
@@ -21,6 +21,7 @@
 #define SCSI_TRANSPORT_H
 
 #include <linux/transport_class.h>
+#include <linux/blkdev.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_device.h>
 
@@ -64,7 +65,7 @@ struct scsi_transport_template {
          *                      begin counting again
          * EH_NOT_HANDLED       Begin normal error recovery
          */
-        enum scsi_eh_timer_return (* eh_timed_out)(struct scsi_cmnd *);
+        enum blk_eh_timer_return (*eh_timed_out)(struct scsi_cmnd *);
 
         /*
          * Used as callback for the completion of i_t_nexus request
diff --git a/include/scsi/scsi_transport_fc.h b/include/scsi/scsi_transport_fc.h
index 878373c32ef7..49d8913c4f86 100644
--- a/include/scsi/scsi_transport_fc.h
+++ b/include/scsi/scsi_transport_fc.h
@@ -167,6 +167,26 @@ enum fc_tgtid_binding_type  {
 struct device_attribute dev_attr_vport_##_name =        \
         __ATTR(_name,_mode,_show,_store)
 
+/*
+ * fc_vport_identifiers: This set of data contains all elements
+ * to uniquely identify and instantiate a FC virtual port.
+ *
+ * Notes:
+ *   symbolic_name: The driver is to append the symbolic_name string data
+ *      to the symbolic_node_name data that it generates by default.
+ *      the resulting combination should then be registered with the switch.
+ *      It is expected that things like Xen may stuff a VM title into
+ *      this field.
+ */
+#define FC_VPORT_SYMBOLIC_NAMELEN               64
+struct fc_vport_identifiers {
+        u64 node_name;
+        u64 port_name;
+        u32 roles;
+        bool disable;
+        enum fc_port_type vport_type;   /* only FC_PORTTYPE_NPIV allowed */
+        char symbolic_name[FC_VPORT_SYMBOLIC_NAMELEN];
+};
 
 /*
  * FC Virtual Port Attributes
@@ -197,7 +217,6 @@ struct device_attribute dev_attr_vport_##_name = 	\
  * managed by the transport w/o driver interaction.
  */
 
-#define FC_VPORT_SYMBOLIC_NAMELEN               64
 struct fc_vport {
         /* Fixed Attributes */
 
@@ -338,6 +357,7 @@ struct fc_rport {	/* aka fc_starget_attrs */
 /* bit field values for struct fc_rport "flags" field: */
 #define FC_RPORT_DEVLOSS_PENDING        0x01
 #define FC_RPORT_SCAN_PENDING           0x02
+#define FC_RPORT_FAST_FAIL_TIMEDOUT     0x03
 
 #define dev_to_rport(d)                         \
         container_of(d, struct fc_rport, dev)
@@ -659,12 +679,15 @@ fc_remote_port_chkready(struct fc_rport *rport)
                 if (rport->roles & FC_PORT_ROLE_FCP_TARGET)
                         result = 0;
                 else if (rport->flags & FC_RPORT_DEVLOSS_PENDING)
-                        result = DID_IMM_RETRY << 16;
+                        result = DID_TRANSPORT_DISRUPTED << 16;
                 else
                         result = DID_NO_CONNECT << 16;
                 break;
         case FC_PORTSTATE_BLOCKED:
-                result = DID_IMM_RETRY << 16;
+                if (rport->flags & FC_RPORT_FAST_FAIL_TIMEDOUT)
+                        result = DID_TRANSPORT_FAILFAST << 16;
+                else
+                        result = DID_TRANSPORT_DISRUPTED << 16;
                 break;
         default:
                 result = DID_NO_CONNECT << 16;
@@ -732,6 +755,8 @@ void fc_host_post_vendor_event(struct Scsi_Host *shost, u32 event_number,
          *   be sure to read the Vendor Type and ID formatting requirements
          *   specified in scsi_netlink.h
          */
+struct fc_vport *fc_vport_create(struct Scsi_Host *shost, int channel,
+                struct fc_vport_identifiers *);
 int fc_vport_terminate(struct fc_vport *vport);
 
 #endif /* SCSI_TRANSPORT_FC_H */
diff --git a/include/scsi/scsi_transport_iscsi.h b/include/scsi/scsi_transport_iscsi.h
index 8b6c91df4c7a..c667cc396545 100644
--- a/include/scsi/scsi_transport_iscsi.h
+++ b/include/scsi/scsi_transport_iscsi.h
@@ -135,7 +135,8 @@ extern int iscsi_unregister_transport(struct iscsi_transport *tt);
 /*
  * control plane upcalls
  */
-extern void iscsi_conn_error(struct iscsi_cls_conn *conn, enum iscsi_err error);
+extern void iscsi_conn_error_event(struct iscsi_cls_conn *conn,
+                                   enum iscsi_err error);
 extern int iscsi_recv_pdu(struct iscsi_cls_conn *conn, struct iscsi_hdr *hdr,
                           char *data, uint32_t data_size);
 
@@ -207,7 +208,7 @@ extern void iscsi_host_for_each_session(struct Scsi_Host *shost,
 struct iscsi_endpoint {
         void *dd_data;                  /* LLD private data */
         struct device dev;
-        unsigned int id;
+        uint64_t id;
 };
 
 /*
diff --git a/include/sound/ad1848.h b/include/sound/ad1848.h
deleted file mode 100644
index d9aebdf6db63..000000000000
--- a/include/sound/ad1848.h
+++ /dev/null
@@ -1,218 +0,0 @@
-#ifndef __SOUND_AD1848_H
-#define __SOUND_AD1848_H
-
-/*
- *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
- *  Definitions for AD1847/AD1848/CS4248 chips
- *
- *
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- */
-
-#include "pcm.h"
-#include <linux/interrupt.h>
-
-/* IO ports */
-
-#define AD1848P( chip, x ) ( (chip) -> port + c_d_c_AD1848##x )
-
-#define c_d_c_AD1848REGSEL      0
-#define c_d_c_AD1848REG         1
-#define c_d_c_AD1848STATUS      2
-#define c_d_c_AD1848PIO         3
-
-/* codec registers */
-
-#define AD1848_LEFT_INPUT       0x00    /* left input control */
-#define AD1848_RIGHT_INPUT      0x01    /* right input control */
-#define AD1848_AUX1_LEFT_INPUT  0x02    /* left AUX1 input control */
-#define AD1848_AUX1_RIGHT_INPUT 0x03    /* right AUX1 input control */
-#define AD1848_AUX2_LEFT_INPUT  0x04    /* left AUX2 input control */
-#define AD1848_AUX2_RIGHT_INPUT 0x05    /* right AUX2 input control */
-#define AD1848_LEFT_OUTPUT      0x06    /* left output control register */
-#define AD1848_RIGHT_OUTPUT     0x07    /* right output control register */
-#define AD1848_DATA_FORMAT      0x08    /* clock and data format - playback/capture - bits 7-0 MCE */
-#define AD1848_IFACE_CTRL       0x09    /* interface control - bits 7-2 MCE */
-#define AD1848_PIN_CTRL         0x0a    /* pin control */
-#define AD1848_TEST_INIT        0x0b    /* test and initialization */
-#define AD1848_MISC_INFO        0x0c    /* miscellaneous information */
-#define AD1848_LOOPBACK         0x0d    /* loopback control */
-#define AD1848_DATA_UPR_CNT     0x0e    /* playback/capture upper base count */
-#define AD1848_DATA_LWR_CNT     0x0f    /* playback/capture lower base count */
-
-/* definitions for codec register select port - CODECP( REGSEL ) */
-
-#define AD1848_INIT             0x80    /* CODEC is initializing */
-#define AD1848_MCE              0x40    /* mode change enable */
-#define AD1848_TRD              0x20    /* transfer request disable */
-
-/* definitions for codec status register - CODECP( STATUS ) */
-
-#define AD1848_GLOBALIRQ        0x01    /* IRQ is active */
-
-/* definitions for AD1848_LEFT_INPUT and AD1848_RIGHT_INPUT registers */
-
-#define AD1848_ENABLE_MIC_GAIN  0x20
-
-#define AD1848_MIXS_LINE1       0x00
-#define AD1848_MIXS_AUX1        0x40
-#define AD1848_MIXS_LINE2       0x80
-#define AD1848_MIXS_ALL         0xc0
-
-/* definitions for clock and data format register - AD1848_PLAYBK_FORMAT */
-
-#define AD1848_LINEAR_8         0x00    /* 8-bit unsigned data */
-#define AD1848_ALAW_8           0x60    /* 8-bit A-law companded */
-#define AD1848_ULAW_8           0x20    /* 8-bit U-law companded */
-#define AD1848_LINEAR_16        0x40    /* 16-bit twos complement data - little endian */
-#define AD1848_STEREO           0x10    /* stereo mode */
-/* bits 3-1 define frequency divisor */
-#define AD1848_XTAL1            0x00    /* 24.576 crystal */
-#define AD1848_XTAL2            0x01    /* 16.9344 crystal */
-
-/* definitions for interface control register - AD1848_IFACE_CTRL */
-
-#define AD1848_CAPTURE_PIO      0x80    /* capture PIO enable */
-#define AD1848_PLAYBACK_PIO     0x40    /* playback PIO enable */
-#define AD1848_CALIB_MODE       0x18    /* calibration mode bits */
-#define AD1848_AUTOCALIB        0x08    /* auto calibrate */
-#define AD1848_SINGLE_DMA       0x04    /* use single DMA channel */
-#define AD1848_CAPTURE_ENABLE   0x02    /* capture enable */
-#define AD1848_PLAYBACK_ENABLE  0x01    /* playback enable */
-
-/* definitions for pin control register - AD1848_PIN_CTRL */
-
-#define AD1848_IRQ_ENABLE       0x02    /* enable IRQ */
-#define AD1848_XCTL1            0x40    /* external control #1 */
-#define AD1848_XCTL0            0x80    /* external control #0 */
-
-/* definitions for test and init register - AD1848_TEST_INIT */
-
-#define AD1848_CALIB_IN_PROGRESS 0x20   /* auto calibrate in progress */
-#define AD1848_DMA_REQUEST      0x10    /* DMA request in progress */
-
-/* defines for codec.mode */
-
-#define AD1848_MODE_NONE        0x0000
-#define AD1848_MODE_PLAY        0x0001
-#define AD1848_MODE_CAPTURE     0x0002
-#define AD1848_MODE_TIMER       0x0004
-#define AD1848_MODE_OPEN        (AD1848_MODE_PLAY|AD1848_MODE_CAPTURE|AD1848_MODE_TIMER)
-#define AD1848_MODE_RUNNING     0x0010
-
-/* defines for codec.hardware */
-
-#define AD1848_HW_DETECT        0x0000  /* let AD1848 driver detect chip */
-#define AD1848_HW_AD1847        0x0001  /* AD1847 chip */
-#define AD1848_HW_AD1848        0x0002  /* AD1848 chip */
-#define AD1848_HW_CS4248        0x0003  /* CS4248 chip */
-#define AD1848_HW_CMI8330       0x0004  /* CMI8330 chip */
-#define AD1848_HW_THINKPAD      0x0005  /* Thinkpad 360/750/755 */
-
-/* IBM Thinkpad specific stuff */
-#define AD1848_THINKPAD_CTL_PORT1               0x15e8
-#define AD1848_THINKPAD_CTL_PORT2               0x15e9
-#define AD1848_THINKPAD_CS4248_ENABLE_BIT       0x02
-
-struct snd_ad1848 {
-        unsigned long port;             /* i/o port */
-        struct resource *res_port;
-        int irq;                        /* IRQ line */
-        int dma;                        /* data DMA */
-        unsigned short version;         /* version of CODEC chip */
-        unsigned short mode;            /* see to AD1848_MODE_XXXX */
-        unsigned short hardware;        /* see to AD1848_HW_XXXX */
-        unsigned short single_dma:1;    /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
-
-        struct snd_pcm *pcm;
-        struct snd_pcm_substream *playback_substream;
-        struct snd_pcm_substream *capture_substream;
-        struct snd_card *card;
-
-        unsigned char image[32];        /* SGalaxy needs an access to extended registers */
-        int mce_bit;
-        int calibrate_mute;
-        int dma_size;
-        int thinkpad_flag;              /* Thinkpad CS4248 needs some extra help */
-
-#ifdef CONFIG_PM
-        void (*suspend)(struct snd_ad1848 *chip);
-        void (*resume)(struct snd_ad1848 *chip);
-#endif
-
-        spinlock_t reg_lock;
-};
-
-/* exported functions */
-
-void snd_ad1848_out(struct snd_ad1848 *chip, unsigned char reg, unsigned char value);
-
-int snd_ad1848_create(struct snd_card *card,
-                      unsigned long port,
-                      int irq, int dma,
-                      unsigned short hardware,
-                      struct snd_ad1848 ** chip);
-
-int snd_ad1848_pcm(struct snd_ad1848 * chip, int device, struct snd_pcm **rpcm);
-const struct snd_pcm_ops *snd_ad1848_get_pcm_ops(int direction);
-int snd_ad1848_mixer(struct snd_ad1848 * chip);
-
-/* exported mixer stuffs */
-enum { AD1848_MIX_SINGLE, AD1848_MIX_DOUBLE, AD1848_MIX_CAPTURE };
-
-#define AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) \
-        ((reg) | ((shift) << 8) | ((mask) << 16) | ((invert) << 24))
-#define AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) \
-        ((left_reg) | ((right_reg) << 8) | ((shift_left) << 16) | ((shift_right) << 19) | ((mask) << 24) | ((invert) << 22))
-
-/* for ease of use */
-struct ad1848_mix_elem {
-        const char *name;
-        int index;
-        int type;
-        unsigned long private_value;
-        const unsigned int *tlv;
-};
-
-#define AD1848_SINGLE(xname, xindex, reg, shift, mask, invert) \
-{ .name = xname, \
-  .index = xindex, \
-  .type = AD1848_MIX_SINGLE, \
-  .private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert) }
-
-#define AD1848_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
-{ .name = xname, \
-  .index = xindex, \
-  .type = AD1848_MIX_SINGLE, \
-  .private_value = AD1848_MIXVAL_SINGLE(reg, shift, mask, invert), \
-  .tlv = xtlv }
-
-#define AD1848_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
-{ .name = xname, \
-  .index = xindex, \
-  .type = AD1848_MIX_DOUBLE, \
-  .private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert) }
-
-#define AD1848_DOUBLE_TLV(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert, xtlv) \
-{ .name = xname, \
-  .index = xindex, \
-  .type = AD1848_MIX_DOUBLE, \
-  .private_value = AD1848_MIXVAL_DOUBLE(left_reg, right_reg, shift_left, shift_right, mask, invert), \
-  .tlv = xtlv }
-
-int snd_ad1848_add_ctl_elem(struct snd_ad1848 *chip, const struct ad1848_mix_elem *c);
-
-#endif /* __SOUND_AD1848_H */
diff --git a/include/sound/asound.h b/include/sound/asound.h
index 3eaf155b850d..2c4dc908a54a 100644
--- a/include/sound/asound.h
+++ b/include/sound/asound.h
@@ -93,9 +93,10 @@ enum {
         SNDRV_HWDEP_IFACE_PCXHR,        /* Digigram PCXHR */
         SNDRV_HWDEP_IFACE_SB_RC,        /* SB Extigy/Audigy2NX remote control */
         SNDRV_HWDEP_IFACE_HDA,          /* HD-audio */
+        SNDRV_HWDEP_IFACE_USB_STREAM,   /* direct access to usb stream */
 
         /* Don't forget to change the following: */
-        SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_HDA
+        SNDRV_HWDEP_IFACE_LAST = SNDRV_HWDEP_IFACE_USB_STREAM
 };
 
 struct snd_hwdep_info {
@@ -296,29 +297,39 @@ struct snd_pcm_info {
         unsigned char reserved[64];     /* reserved for future... */
 };
 
-typedef int __bitwise snd_pcm_hw_param_t;
-#define SNDRV_PCM_HW_PARAM_ACCESS       ((__force snd_pcm_hw_param_t) 0) /* Access type */
-#define SNDRV_PCM_HW_PARAM_FORMAT       ((__force snd_pcm_hw_param_t) 1) /* Format */
-#define SNDRV_PCM_HW_PARAM_SUBFORMAT    ((__force snd_pcm_hw_param_t) 2) /* Subformat */
+typedef int snd_pcm_hw_param_t;
+#define SNDRV_PCM_HW_PARAM_ACCESS       0       /* Access type */
+#define SNDRV_PCM_HW_PARAM_FORMAT       1       /* Format */
+#define SNDRV_PCM_HW_PARAM_SUBFORMAT    2       /* Subformat */
 #define SNDRV_PCM_HW_PARAM_FIRST_MASK   SNDRV_PCM_HW_PARAM_ACCESS
 #define SNDRV_PCM_HW_PARAM_LAST_MASK    SNDRV_PCM_HW_PARAM_SUBFORMAT
 
-#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS  ((__force snd_pcm_hw_param_t) 8) /* Bits per sample */
-#define SNDRV_PCM_HW_PARAM_FRAME_BITS   ((__force snd_pcm_hw_param_t) 9) /* Bits per frame */
-#define SNDRV_PCM_HW_PARAM_CHANNELS     ((__force snd_pcm_hw_param_t) 10) /* Channels */
-#define SNDRV_PCM_HW_PARAM_RATE         ((__force snd_pcm_hw_param_t) 11) /* Approx rate */
-#define SNDRV_PCM_HW_PARAM_PERIOD_TIME  ((__force snd_pcm_hw_param_t) 12) /* Approx distance between interrupts in us */
-#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE  ((__force snd_pcm_hw_param_t) 13) /* Approx frames between interrupts */
-#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES ((__force snd_pcm_hw_param_t) 14) /* Approx bytes between interrupts */
-#define SNDRV_PCM_HW_PARAM_PERIODS      ((__force snd_pcm_hw_param_t) 15) /* Approx interrupts per buffer */
-#define SNDRV_PCM_HW_PARAM_BUFFER_TIME  ((__force snd_pcm_hw_param_t) 16) /* Approx duration of buffer in us */
-#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE  ((__force snd_pcm_hw_param_t) 17) /* Size of buffer in frames */
-#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES ((__force snd_pcm_hw_param_t) 18) /* Size of buffer in bytes */
-#define SNDRV_PCM_HW_PARAM_TICK_TIME    ((__force snd_pcm_hw_param_t) 19) /* Approx tick duration in us */
+#define SNDRV_PCM_HW_PARAM_SAMPLE_BITS  8       /* Bits per sample */
+#define SNDRV_PCM_HW_PARAM_FRAME_BITS   9       /* Bits per frame */
+#define SNDRV_PCM_HW_PARAM_CHANNELS     10      /* Channels */
+#define SNDRV_PCM_HW_PARAM_RATE         11      /* Approx rate */
+#define SNDRV_PCM_HW_PARAM_PERIOD_TIME  12      /* Approx distance between
+                                                 * interrupts in us
+                                                 */
+#define SNDRV_PCM_HW_PARAM_PERIOD_SIZE  13      /* Approx frames between
+                                                 * interrupts
+                                                 */
+#define SNDRV_PCM_HW_PARAM_PERIOD_BYTES 14      /* Approx bytes between
+                                                 * interrupts
+                                                 */
+#define SNDRV_PCM_HW_PARAM_PERIODS      15      /* Approx interrupts per
+                                                 * buffer
+                                                 */
+#define SNDRV_PCM_HW_PARAM_BUFFER_TIME  16      /* Approx duration of buffer
+                                                 * in us
+                                                 */
+#define SNDRV_PCM_HW_PARAM_BUFFER_SIZE  17      /* Size of buffer in frames */
+#define SNDRV_PCM_HW_PARAM_BUFFER_BYTES 18      /* Size of buffer in bytes */
+#define SNDRV_PCM_HW_PARAM_TICK_TIME    19      /* Approx tick duration in us */
 #define SNDRV_PCM_HW_PARAM_FIRST_INTERVAL       SNDRV_PCM_HW_PARAM_SAMPLE_BITS
 #define SNDRV_PCM_HW_PARAM_LAST_INTERVAL        SNDRV_PCM_HW_PARAM_TICK_TIME
 
-#define SNDRV_PCM_HW_PARAMS_NORESAMPLE          (1<<0)  /* avoid rate resampling */
+#define SNDRV_PCM_HW_PARAMS_NORESAMPLE  (1<<0)  /* avoid rate resampling */
 
 struct snd_interval {
         unsigned int min, max;
@@ -696,7 +707,7 @@ struct snd_timer_tread {
  *                                                                          *
  ****************************************************************************/
 
-#define SNDRV_CTL_VERSION               SNDRV_PROTOCOL_VERSION(2, 0, 5)
+#define SNDRV_CTL_VERSION               SNDRV_PROTOCOL_VERSION(2, 0, 6)
 
 struct snd_ctl_card_info {
         int card;                       /* card number */
@@ -707,8 +718,7 @@ struct snd_ctl_card_info {
         unsigned char longname[80];     /* name + info text about soundcard */
         unsigned char reserved_[16];    /* reserved for future (was ID of mixer) */
         unsigned char mixername[80];    /* visual mixer identification */
-        unsigned char components[80];   /* card components / fine identification, delimited with one space (AC97 etc..) */
-        unsigned char reserved[48];     /* reserved for future */
+        unsigned char components[128];  /* card components / fine identification, delimited with one space (AC97 etc..) */
 };
 
 typedef int __bitwise snd_ctl_elem_type_t;
diff --git a/include/sound/asoundef.h b/include/sound/asoundef.h
index a6e0facf8a37..20ebf3298eba 100644
--- a/include/sound/asoundef.h
+++ b/include/sound/asoundef.h
@@ -60,35 +60,56 @@
 #define IEC958_AES1_PRO_USERBITS_UDEF   (12<<4) /* user defined application */
 #define IEC958_AES1_CON_CATEGORY        0x7f
 #define IEC958_AES1_CON_GENERAL         0x00
-#define IEC958_AES1_CON_EXPERIMENTAL    0x40
-#define IEC958_AES1_CON_SOLIDMEM_MASK   0x0f
-#define IEC958_AES1_CON_SOLIDMEM_ID     0x08
-#define IEC958_AES1_CON_BROADCAST1_MASK 0x07
-#define IEC958_AES1_CON_BROADCAST1_ID   0x04
-#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07
-#define IEC958_AES1_CON_DIGDIGCONV_ID   0x02
-#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f
-#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x06
-#define IEC958_AES1_CON_ADC_MASK        0x1f
-#define IEC958_AES1_CON_ADC_ID          0x16
-#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f
-#define IEC958_AES1_CON_BROADCAST2_ID   0x0e
 #define IEC958_AES1_CON_LASEROPT_MASK   0x07
 #define IEC958_AES1_CON_LASEROPT_ID     0x01
-#define IEC958_AES1_CON_MUSICAL_MASK    0x07
-#define IEC958_AES1_CON_MUSICAL_ID      0x05
-#define IEC958_AES1_CON_MAGNETIC_MASK   0x07
-#define IEC958_AES1_CON_MAGNETIC_ID     0x03
 #define IEC958_AES1_CON_IEC908_CD       (IEC958_AES1_CON_LASEROPT_ID|0x00)
 #define IEC958_AES1_CON_NON_IEC908_CD   (IEC958_AES1_CON_LASEROPT_ID|0x08)
+#define IEC958_AES1_CON_MINI_DISC       (IEC958_AES1_CON_LASEROPT_ID|0x48)
+#define IEC958_AES1_CON_DVD             (IEC958_AES1_CON_LASEROPT_ID|0x18)
+#define IEC958_AES1_CON_LASTEROPT_OTHER (IEC958_AES1_CON_LASEROPT_ID|0x78)
+#define IEC958_AES1_CON_DIGDIGCONV_MASK 0x07
+#define IEC958_AES1_CON_DIGDIGCONV_ID   0x02
 #define IEC958_AES1_CON_PCM_CODER       (IEC958_AES1_CON_DIGDIGCONV_ID|0x00)
-#define IEC958_AES1_CON_SAMPLER         (IEC958_AES1_CON_DIGDIGCONV_ID|0x20)
 #define IEC958_AES1_CON_MIXER           (IEC958_AES1_CON_DIGDIGCONV_ID|0x10)
 #define IEC958_AES1_CON_RATE_CONVERTER  (IEC958_AES1_CON_DIGDIGCONV_ID|0x18)
-#define IEC958_AES1_CON_SYNTHESIZER     (IEC958_AES1_CON_MUSICAL_ID|0x00)
-#define IEC958_AES1_CON_MICROPHONE      (IEC958_AES1_CON_MUSICAL_ID|0x08)
+#define IEC958_AES1_CON_SAMPLER         (IEC958_AES1_CON_DIGDIGCONV_ID|0x20)
+#define IEC958_AES1_CON_DSP             (IEC958_AES1_CON_DIGDIGCONV_ID|0x28)
+#define IEC958_AES1_CON_DIGDIGCONV_OTHER (IEC958_AES1_CON_DIGDIGCONV_ID|0x78)
+#define IEC958_AES1_CON_MAGNETIC_MASK   0x07
+#define IEC958_AES1_CON_MAGNETIC_ID     0x03
 #define IEC958_AES1_CON_DAT             (IEC958_AES1_CON_MAGNETIC_ID|0x00)
 #define IEC958_AES1_CON_VCR             (IEC958_AES1_CON_MAGNETIC_ID|0x08)
+#define IEC958_AES1_CON_DCC             (IEC958_AES1_CON_MAGNETIC_ID|0x40)
+#define IEC958_AES1_CON_MAGNETIC_DISC   (IEC958_AES1_CON_MAGNETIC_ID|0x18)
+#define IEC958_AES1_CON_MAGNETIC_OTHER  (IEC958_AES1_CON_MAGNETIC_ID|0x78)
+#define IEC958_AES1_CON_BROADCAST1_MASK 0x07
+#define IEC958_AES1_CON_BROADCAST1_ID   0x04
+#define IEC958_AES1_CON_DAB_JAPAN       (IEC958_AES1_CON_BROADCAST1_ID|0x00)
+#define IEC958_AES1_CON_DAB_EUROPE      (IEC958_AES1_CON_BROADCAST1_ID|0x08)
+#define IEC958_AES1_CON_DAB_USA         (IEC958_AES1_CON_BROADCAST1_ID|0x60)
+#define IEC958_AES1_CON_SOFTWARE        (IEC958_AES1_CON_BROADCAST1_ID|0x40)
+#define IEC958_AES1_CON_IEC62105        (IEC958_AES1_CON_BROADCAST1_ID|0x20)
+#define IEC958_AES1_CON_BROADCAST1_OTHER (IEC958_AES1_CON_BROADCAST1_ID|0x78)
+#define IEC958_AES1_CON_BROADCAST2_MASK 0x0f
+#define IEC958_AES1_CON_BROADCAST2_ID   0x0e
+#define IEC958_AES1_CON_MUSICAL_MASK    0x07
+#define IEC958_AES1_CON_MUSICAL_ID      0x05
+#define IEC958_AES1_CON_SYNTHESIZER     (IEC958_AES1_CON_MUSICAL_ID|0x00)
+#define IEC958_AES1_CON_MICROPHONE      (IEC958_AES1_CON_MUSICAL_ID|0x08)
+#define IEC958_AES1_CON_MUSICAL_OTHER   (IEC958_AES1_CON_MUSICAL_ID|0x78)
+#define IEC958_AES1_CON_ADC_MASK        0x1f
+#define IEC958_AES1_CON_ADC_ID          0x06
+#define IEC958_AES1_CON_ADC             (IEC958_AES1_CON_ADC_ID|0x00)
+#define IEC958_AES1_CON_ADC_OTHER       (IEC958_AES1_CON_ADC_ID|0x60)
+#define IEC958_AES1_CON_ADC_COPYRIGHT_MASK 0x1f
+#define IEC958_AES1_CON_ADC_COPYRIGHT_ID 0x16
+#define IEC958_AES1_CON_ADC_COPYRIGHT   (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x00)
+#define IEC958_AES1_CON_ADC_COPYRIGHT_OTHER (IEC958_AES1_CON_ADC_COPYRIGHT_ID|0x60)
+#define IEC958_AES1_CON_SOLIDMEM_MASK   0x0f
+#define IEC958_AES1_CON_SOLIDMEM_ID     0x08
+#define IEC958_AES1_CON_SOLIDMEM_DIGITAL_RECORDER_PLAYER (IEC958_AES1_CON_SOLIDMEM_ID|0x00)
+#define IEC958_AES1_CON_SOLIDMEM_OTHER  (IEC958_AES1_CON_SOLIDMEM_ID|0x70)
+#define IEC958_AES1_CON_EXPERIMENTAL    0x40
 #define IEC958_AES1_CON_ORIGINAL        (1<<7)  /* this bits depends on the category code */
 #define IEC958_AES2_PRO_SBITS           (7<<0)  /* mask - sample bits */
 #define IEC958_AES2_PRO_SBITS_20        (2<<0)  /* 20-bit - coordination */
@@ -106,8 +127,16 @@
 #define IEC958_AES2_CON_CHANNEL_UNSPEC  (0<<4)  /* unspecified */
 #define IEC958_AES3_CON_FS              (15<<0) /* mask - sample frequency */
 #define IEC958_AES3_CON_FS_44100        (0<<0)  /* 44.1kHz */
+#define IEC958_AES3_CON_FS_NOTID        (1<<0)  /* non indicated */
 #define IEC958_AES3_CON_FS_48000        (2<<0)  /* 48kHz */
 #define IEC958_AES3_CON_FS_32000        (3<<0)  /* 32kHz */
+#define IEC958_AES3_CON_FS_22050        (4<<0)  /* 22.05kHz */
+#define IEC958_AES3_CON_FS_24000        (6<<0)  /* 24kHz */
+#define IEC958_AES3_CON_FS_88200        (8<<0)  /* 88.2kHz */
+#define IEC958_AES3_CON_FS_768000       (9<<0)  /* 768kHz */
+#define IEC958_AES3_CON_FS_96000        (10<<0) /* 96kHz */
+#define IEC958_AES3_CON_FS_176400       (12<<0) /* 176.4kHz */
+#define IEC958_AES3_CON_FS_192000       (14<<0) /* 192kHz */
 #define IEC958_AES3_CON_CLOCK           (3<<4)  /* mask - clock accuracy */
 #define IEC958_AES3_CON_CLOCK_1000PPM   (0<<4)  /* 1000 ppm */
 #define IEC958_AES3_CON_CLOCK_50PPM     (1<<4)  /* 50 ppm */
@@ -120,6 +149,26 @@
 #define IEC958_AES4_CON_WORDLEN_23_19   (4<<1)  /* 23-bit or 19-bit */
 #define IEC958_AES4_CON_WORDLEN_24_20   (5<<1)  /* 24-bit or 20-bit */
 #define IEC958_AES4_CON_WORDLEN_21_17   (6<<1)  /* 21-bit or 17-bit */
+#define IEC958_AES4_CON_ORIGFS          (15<<4) /* mask - original sample frequency */
+#define IEC958_AES4_CON_ORIGFS_NOTID    (0<<4)  /* not indicated */
+#define IEC958_AES4_CON_ORIGFS_192000   (1<<4)  /* 192kHz */
+#define IEC958_AES4_CON_ORIGFS_12000    (2<<4)  /* 12kHz */
+#define IEC958_AES4_CON_ORIGFS_176400   (3<<4)  /* 176.4kHz */
+#define IEC958_AES4_CON_ORIGFS_96000    (5<<4)  /* 96kHz */
+#define IEC958_AES4_CON_ORIGFS_8000     (6<<4)  /* 8kHz */
+#define IEC958_AES4_CON_ORIGFS_88200    (7<<4)  /* 88.2kHz */
+#define IEC958_AES4_CON_ORIGFS_16000    (8<<4)  /* 16kHz */
+#define IEC958_AES4_CON_ORIGFS_24000    (9<<4)  /* 24kHz */
+#define IEC958_AES4_CON_ORIGFS_11025    (10<<4) /* 11.025kHz */
+#define IEC958_AES4_CON_ORIGFS_22050    (11<<4) /* 22.05kHz */
+#define IEC958_AES4_CON_ORIGFS_32000    (12<<4) /* 32kHz */
+#define IEC958_AES4_CON_ORIGFS_48000    (13<<4) /* 48kHz */
+#define IEC958_AES4_CON_ORIGFS_44100    (15<<4) /* 44.1kHz */
+#define IEC958_AES5_CON_CGMSA           (3<<0)  /* mask - CGMS-A */
+#define IEC958_AES5_CON_CGMSA_COPYFREELY (0<<0) /* copying is permitted without restriction */
+#define IEC958_AES5_CON_CGMSA_COPYONCE  (1<<0)  /* one generation of copies may be made */
+#define IEC958_AES5_CON_CGMSA_COPYNOMORE (2<<0) /* condition not be used */
+#define IEC958_AES5_CON_CGMSA_COPYNEVER (3<<0)  /* no copying is permitted */
 
 /*****************************************************************************
  *                                                                           *
diff --git a/include/sound/core.h b/include/sound/core.h
index 558b96284bd2..35424a971b7a 100644
--- a/include/sound/core.h
+++ b/include/sound/core.h
@@ -28,6 +28,7 @@
 #include <linux/rwsem.h>                /* struct rw_semaphore */
 #include <linux/pm.h>                   /* pm_message_t */
 #include <linux/device.h>
+#include <linux/stringify.h>
 
 /* number of supported soundcards */
 #ifdef CONFIG_SND_DYNAMIC_MINORS
@@ -42,9 +43,6 @@
 #ifdef CONFIG_PCI
 struct pci_dev;
 #endif
-#ifdef CONFIG_SBUS
-struct sbus_dev;
-#endif
 
 /* device allocation stuff */
 
@@ -63,6 +61,7 @@ typedef int __bitwise snd_device_type_t;
 #define SNDRV_DEV_INFO          ((__force snd_device_type_t) 0x1006)
 #define SNDRV_DEV_BUS           ((__force snd_device_type_t) 0x1007)
 #define SNDRV_DEV_CODEC         ((__force snd_device_type_t) 0x1008)
+#define SNDRV_DEV_JACK          ((__force snd_device_type_t) 0x1009)
 #define SNDRV_DEV_LOWLEVEL      ((__force snd_device_type_t) 0x2000)
 
 typedef int __bitwise snd_device_state_t;
@@ -114,7 +113,7 @@ struct snd_card {
         char shortname[32];             /* short name of this soundcard */
         char longname[80];              /* name of this soundcard */
         char mixername[80];             /* mixer name */
-        char components[80];            /* card components delimited with
+        char components[128];           /* card components delimited with
                                                                 space */
         struct module *module;          /* top-level module */
 
@@ -366,8 +365,6 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
 
 #ifdef CONFIG_SND_DEBUG
 
-#define __ASTRING__(x) #x
-
 #ifdef CONFIG_SND_VERBOSE_PRINTK
 /**
  * snd_printd - debug printk
@@ -382,33 +379,15 @@ void snd_verbose_printd(const char *file, int line, const char *format, ...)
 #define snd_printd(fmt, args...) \
         printk(fmt ,##args)
 #endif
-/**
- * snd_assert - run-time assertion macro
- * @expr: expression
- *
- * This macro checks the expression in run-time and invokes the commands
- * given in the rest arguments if the assertion is failed.
- * When CONFIG_SND_DEBUG is not set, the expression is executed but
- * not checked.
- */
-#define snd_assert(expr, args...) do {                                  \
-        if (unlikely(!(expr))) {                                        \
-                snd_printk(KERN_ERR "BUG? (%s)\n", __ASTRING__(expr));  \
-                dump_stack();                                           \
-                args;                                                   \
-        }                                                               \
-} while (0)
-
-#define snd_BUG() do {                          \
-        snd_printk(KERN_ERR "BUG?\n");          \
-        dump_stack();                           \
-} while (0)
+
+#define snd_BUG()               WARN(1, "BUG?\n")
+#define snd_BUG_ON(cond)        WARN((cond), "BUG? (%s)\n", __stringify(cond))
 
 #else /* !CONFIG_SND_DEBUG */
 
 #define snd_printd(fmt, args...)        /* nothing */
-#define snd_assert(expr, args...)       (void)(expr)
 #define snd_BUG()                       /* nothing */
+#define snd_BUG_ON(cond)        ({/*(void)(cond);*/ 0;})  /* always false */
 
 #endif /* CONFIG_SND_DEBUG */
 
diff --git a/include/sound/cs4231.h b/include/sound/cs4231.h
deleted file mode 100644
index f0785f9f4ae4..000000000000
--- a/include/sound/cs4231.h
+++ /dev/null
@@ -1,175 +0,0 @@
-#ifndef __SOUND_CS4231_H
-#define __SOUND_CS4231_H
-
-/*
- *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
- *  Definitions for CS4231 & InterWave chips & compatible chips
- *
- *
- *   This program is free software; you can redistribute it and/or modify
- *   it under the terms of the GNU General Public License as published by
- *   the Free Software Foundation; either version 2 of the License, or
- *   (at your option) any later version.
- *
- *   This program is distributed in the hope that it will be useful,
- *   but WITHOUT ANY WARRANTY; without even the implied warranty of
- *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *   GNU General Public License for more details.
- *
- *   You should have received a copy of the GNU General Public License
- *   along with this program; if not, write to the Free Software
- *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
- *
- */
-
-#include "control.h"
-#include "pcm.h"
-#include "timer.h"
-
-#include "cs4231-regs.h"
-
-/* defines for codec.mode */
-
-#define CS4231_MODE_NONE        0x0000
-#define CS4231_MODE_PLAY        0x0001
-#define CS4231_MODE_RECORD      0x0002
-#define CS4231_MODE_TIMER       0x0004
-#define CS4231_MODE_OPEN        (CS4231_MODE_PLAY|CS4231_MODE_RECORD|CS4231_MODE_TIMER)
-
-/* defines for codec.hardware */
-
-#define CS4231_HW_DETECT        0x0000  /* let CS4231 driver detect chip */
-#define CS4231_HW_DETECT3       0x0001  /* allow mode 3 */
-#define CS4231_HW_TYPE_MASK     0xff00  /* type mask */
-#define CS4231_HW_CS4231_MASK   0x0100  /* CS4231 serie */
-#define CS4231_HW_CS4231        0x0100  /* CS4231 chip */
-#define CS4231_HW_CS4231A       0x0101  /* CS4231A chip */
-#define CS4231_HW_AD1845        0x0102  /* AD1845 chip */
-#define CS4231_HW_CS4232_MASK   0x0200  /* CS4232 serie (has control ports) */
-#define CS4231_HW_CS4232        0x0200  /* CS4232 */
-#define CS4231_HW_CS4232A       0x0201  /* CS4232A */
-#define CS4231_HW_CS4236        0x0202  /* CS4236 */
-#define CS4231_HW_CS4236B_MASK  0x0400  /* CS4236B serie (has extended control regs) */
-#define CS4231_HW_CS4235        0x0400  /* CS4235 - Crystal Clear (tm) stereo enhancement */
-#define CS4231_HW_CS4236B       0x0401  /* CS4236B */
-#define CS4231_HW_CS4237B       0x0402  /* CS4237B - SRS 3D */
-#define CS4231_HW_CS4238B       0x0403  /* CS4238B - QSOUND 3D */
-#define CS4231_HW_CS4239        0x0404  /* CS4239 - Crystal Clear (tm) stereo enhancement */
-/* compatible, but clones */
-#define CS4231_HW_INTERWAVE     0x1000  /* InterWave chip */
-#define CS4231_HW_OPL3SA2       0x1101  /* OPL3-SA2 chip, similar to cs4231 */
-#define CS4231_HW_OPTI93X       0x1102  /* Opti 930/931/933 */
-
-/* defines for codec.hwshare */
-#define CS4231_HWSHARE_IRQ      (1<<0)
-#define CS4231_HWSHARE_DMA1     (1<<1)
-#define CS4231_HWSHARE_DMA2     (1<<2)
-
-struct snd_cs4231 {
-        unsigned long port;             /* base i/o port */
-        struct resource *res_port;
-        unsigned long cport;            /* control base i/o port (CS4236) */
-        struct resource *res_cport;
-        int irq;                        /* IRQ line */
-        int dma1;                       /* playback DMA */
-        int dma2;                       /* record DMA */
-        unsigned short version;         /* version of CODEC chip */
-        unsigned short mode;            /* see to CS4231_MODE_XXXX */
-        unsigned short hardware;        /* see to CS4231_HW_XXXX */
-        unsigned short hwshare;         /* shared resources */
-        unsigned short single_dma:1,    /* forced single DMA mode (GUS 16-bit daughter board) or dma1 == dma2 */
-                       ebus_flag:1;     /* SPARC: EBUS present */
-
-        struct snd_card *card;
-        struct snd_pcm *pcm;
-        struct snd_pcm_substream *playback_substream;
-        struct snd_pcm_substream *capture_substream;
-        struct snd_timer *timer;
-
-        unsigned char image[32];        /* registers image */
-        unsigned char eimage[32];       /* extended registers image */
-        unsigned char cimage[16];       /* control registers image */
-        int mce_bit;
-        int calibrate_mute;
-        int sw_3d_bit;
-        unsigned int p_dma_size;
-        unsigned int c_dma_size;
-
-        spinlock_t reg_lock;
-        struct mutex mce_mutex;
-        struct mutex open_mutex;
-
-        int (*rate_constraint) (struct snd_pcm_runtime *runtime);
-        void (*set_playback_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char pdfr);
-        void (*set_capture_format) (struct snd_cs4231 *chip, struct snd_pcm_hw_params *hw_params, unsigned char cdfr);
-        void (*trigger) (struct snd_cs4231 *chip, unsigned int what, int start);
-#ifdef CONFIG_PM
-        void (*suspend) (struct snd_cs4231 *chip);
-        void (*resume) (struct snd_cs4231 *chip);
-#endif
-        void *dma_private_data;
-        int (*claim_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma);
-        int (*release_dma) (struct snd_cs4231 *chip, void *dma_private_data, int dma);
-};
-
-/* exported functions */
-
-void snd_cs4231_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val);
-unsigned char snd_cs4231_in(struct snd_cs4231 *chip, unsigned char reg);
-void snd_cs4236_ext_out(struct snd_cs4231 *chip, unsigned char reg, unsigned char val);
-unsigned char snd_cs4236_ext_in(struct snd_cs4231 *chip, unsigned char reg);
-void snd_cs4231_mce_up(struct snd_cs4231 *chip);
-void snd_cs4231_mce_down(struct snd_cs4231 *chip);
-
-void snd_cs4231_overrange(struct snd_cs4231 *chip);
-
-irqreturn_t snd_cs4231_interrupt(int irq, void *dev_id);
-
-const char *snd_cs4231_chip_id(struct snd_cs4231 *chip);
-
-int snd_cs4231_create(struct snd_card *card,
-                      unsigned long port,
-                      unsigned long cport,
-                      int irq, int dma1, int dma2,
-                      unsigned short hardware,
-                      unsigned short hwshare,
-                      struct snd_cs4231 ** rchip);
-int snd_cs4231_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm);
-int snd_cs4231_timer(struct snd_cs4231 * chip, int device, struct snd_timer **rtimer);
-int snd_cs4231_mixer(struct snd_cs4231 * chip);
-
-int snd_cs4236_create(struct snd_card *card,
-                      unsigned long port,
-                      unsigned long cport,
-                      int irq, int dma1, int dma2,
-                      unsigned short hardware,
-                      unsigned short hwshare,
-                      struct snd_cs4231 ** rchip);
-int snd_cs4236_pcm(struct snd_cs4231 * chip, int device, struct snd_pcm **rpcm);
-int snd_cs4236_mixer(struct snd_cs4231 * chip);
-
-/*
- *  mixer library
- */
-
-#define CS4231_SINGLE(xname, xindex, reg, shift, mask, invert) \
-{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
-  .info = snd_cs4231_info_single, \
-  .get = snd_cs4231_get_single, .put = snd_cs4231_put_single, \
-  .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
-
-int snd_cs4231_info_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
-int snd_cs4231_get_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
-int snd_cs4231_put_single(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
-
-#define CS4231_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
-{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, .index = xindex, \
-  .info = snd_cs4231_info_double, \
-  .get = snd_cs4231_get_double, .put = snd_cs4231_put_double, \
-  .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | (shift_right << 19) | (mask << 24) | (invert << 22) }
-
-int snd_cs4231_info_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_info *uinfo);
-int snd_cs4231_get_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
-int snd_cs4231_put_double(struct snd_kcontrol *kcontrol, struct snd_ctl_elem_value *ucontrol);
-
-#endif /* __SOUND_CS4231_H */
diff --git a/include/sound/jack.h b/include/sound/jack.h
new file mode 100644
index 000000000000..b1b2b8b59adb
--- /dev/null
+++ b/include/sound/jack.h
@@ -0,0 +1,75 @@
+#ifndef __SOUND_JACK_H
+#define __SOUND_JACK_H
+
+/*
+ *  Jack abstraction layer
+ *
+ *  Copyright 2008 Wolfson Microelectronics plc
+ *
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include <sound/core.h>
+
+struct input_dev;
+
+/**
+ * Jack types which can be reported.  These values are used as a
+ * bitmask.
+ */
+enum snd_jack_types {
+        SND_JACK_HEADPHONE      = 0x0001,
+        SND_JACK_MICROPHONE     = 0x0002,
+        SND_JACK_HEADSET        = SND_JACK_HEADPHONE | SND_JACK_MICROPHONE,
+};
+
+struct snd_jack {
+        struct input_dev *input_dev;
+        int registered;
+        int type;
+        const char *id;
+        char name[100];
+};
+
+#ifdef CONFIG_SND_JACK
+
+int snd_jack_new(struct snd_card *card, const char *id, int type,
+                 struct snd_jack **jack);
+void snd_jack_set_parent(struct snd_jack *jack, struct device *parent);
+
+void snd_jack_report(struct snd_jack *jack, int status);
+
+#else
+
+static inline int snd_jack_new(struct snd_card *card, const char *id, int type,
+                               struct snd_jack **jack)
+{
+        return 0;
+}
+
+static inline void snd_jack_set_parent(struct snd_jack *jack,
+                                       struct device *parent)
+{
+}
+
+static inline void snd_jack_report(struct snd_jack *jack, int status)
+{
+}
+
+#endif
+
+#endif
diff --git a/include/sound/memalloc.h b/include/sound/memalloc.h
index ae2921d9ddcc..7ccce94a5255 100644
--- a/include/sound/memalloc.h
+++ b/include/sound/memalloc.h
@@ -37,7 +37,6 @@ struct snd_dma_device {
 #ifndef snd_dma_pci_data
 #define snd_dma_pci_data(pci)   (&(pci)->dev)
 #define snd_dma_isa_data()      NULL
-#define snd_dma_sbus_data(sbus) ((struct device *)(sbus))
 #define snd_dma_continuous_data(x)      ((struct device *)(unsigned long)(x))
 #endif
 
@@ -49,7 +48,6 @@ struct snd_dma_device {
 #define SNDRV_DMA_TYPE_CONTINUOUS       1       /* continuous no-DMA memory */
 #define SNDRV_DMA_TYPE_DEV              2       /* generic device continuous */
 #define SNDRV_DMA_TYPE_DEV_SG           3       /* generic device SG-buffer */
-#define SNDRV_DMA_TYPE_SBUS             4       /* SBUS continuous */
 
 /*
  * info for buffer allocation
@@ -65,6 +63,11 @@ struct snd_dma_buffer {
 /*
  * Scatter-Gather generic device pages
  */
+void *snd_malloc_sgbuf_pages(struct device *device,
+                             size_t size, struct snd_dma_buffer *dmab,
+                             size_t *res_size);
+int snd_free_sgbuf_pages(struct snd_dma_buffer *dmab);
+
 struct snd_sg_page {
         void *buf;
         dma_addr_t addr;
@@ -92,9 +95,18 @@ static inline unsigned int snd_sgbuf_aligned_pages(size_t size)
  */
 static inline dma_addr_t snd_sgbuf_get_addr(struct snd_sg_buf *sgbuf, size_t offset)
 {
-        return sgbuf->table[offset >> PAGE_SHIFT].addr + offset % PAGE_SIZE;
+        dma_addr_t addr = sgbuf->table[offset >> PAGE_SHIFT].addr;
+        addr &= PAGE_MASK;
+        return addr + offset % PAGE_SIZE;
 }
 
+/*
+ * return the virtual address at the corresponding offset
+ */
+static inline void *snd_sgbuf_get_ptr(struct snd_sg_buf *sgbuf, size_t offset)
+{
+        return sgbuf->table[offset >> PAGE_SHIFT].buf + offset % PAGE_SIZE;
+}
 
 /* allocate/release a buffer */
 int snd_dma_alloc_pages(int type, struct device *dev, size_t size,
diff --git a/include/sound/minors.h b/include/sound/minors.h
index 46bcd2023ed8..a81798ab73ed 100644
--- a/include/sound/minors.h
+++ b/include/sound/minors.h
@@ -21,6 +21,8 @@
  *
  */
 
+#define SNDRV_OS_MINORS                 256
+
 #define SNDRV_MINOR_DEVICES             32
 #define SNDRV_MINOR_CARD(minor)         ((minor) >> 5)
 #define SNDRV_MINOR_DEVICE(minor)       ((minor) & 0x001f)
diff --git a/include/sound/pcm.h b/include/sound/pcm.h
index 51d58ccda2d8..40c5a6fa6bcd 100644
--- a/include/sound/pcm.h
+++ b/include/sound/pcm.h
@@ -25,6 +25,7 @@
 
 #include <sound/asound.h>
 #include <sound/memalloc.h>
+#include <sound/minors.h>
 #include <linux/poll.h>
 #include <linux/mm.h>
 #include <linux/bitops.h>
@@ -84,7 +85,11 @@ struct snd_pcm_ops {
  *
  */
 
-#define SNDRV_PCM_DEVICES               8
+#if defined(CONFIG_SND_DYNAMIC_MINORS)
+#define SNDRV_PCM_DEVICES       (SNDRV_OS_MINORS-2)
+#else
+#define SNDRV_PCM_DEVICES       8
+#endif
 
 #define SNDRV_PCM_IOCTL1_FALSE          ((void *)0)
 #define SNDRV_PCM_IOCTL1_TRUE           ((void *)1)
@@ -416,7 +421,7 @@ struct snd_pcm_str {
 struct snd_pcm {
         struct snd_card *card;
         struct list_head list;
-        unsigned int device;    /* device number */
+        int device; /* device number */
         unsigned int info_flags;
         unsigned short dev_class;
         unsigned short dev_subclass;
@@ -969,10 +974,30 @@ int snd_pcm_lib_preallocate_pages_for_all(struct snd_pcm *pcm,
 int snd_pcm_lib_malloc_pages(struct snd_pcm_substream *substream, size_t size);
 int snd_pcm_lib_free_pages(struct snd_pcm_substream *substream);
 
-#define snd_pcm_substream_sgbuf(substream) ((substream)->runtime->dma_buffer_p->private_data)
-#define snd_pcm_sgbuf_pages(size) snd_sgbuf_aligned_pages(size)
-#define snd_pcm_sgbuf_get_addr(sgbuf,ofs) snd_sgbuf_get_addr(sgbuf,ofs)
-struct page *snd_pcm_sgbuf_ops_page(struct snd_pcm_substream *substream, unsigned long offset);
+/*
+ * SG-buffer handling
+ */
+#define snd_pcm_substream_sgbuf(substream) \
+        ((substream)->runtime->dma_buffer_p->private_data)
+
+static inline dma_addr_t
+snd_pcm_sgbuf_get_addr(struct snd_pcm_substream *substream, unsigned int ofs)
+{
+        struct snd_sg_buf *sg = snd_pcm_substream_sgbuf(substream);
+        return snd_sgbuf_get_addr(sg, ofs);
+}
+
+static inline void *
+snd_pcm_sgbuf_get_ptr(struct snd_pcm_substream *substream, unsigned int ofs)
+{
+        struct snd_sg_buf *sg = snd_pcm_substream_sgbuf(substream);
+        return snd_sgbuf_get_ptr(sg, ofs);
+}
+
+struct page *snd_pcm_sgbuf_ops_page(struct snd_pcm_substream *substream,
+                                    unsigned long offset);
+unsigned int snd_pcm_sgbuf_get_chunk_size(struct snd_pcm_substream *substream,
+                                          unsigned int ofs, unsigned int size);
 
 /* handle mmap counter - PCM mmap callback should handle this counter properly */
 static inline void snd_pcm_mmap_data_open(struct vm_area_struct *area)
@@ -1010,4 +1035,6 @@ static inline void snd_pcm_limit_isa_dma_size(int dma, size_t *max)
                                          (IEC958_AES1_CON_PCM_CODER<<8)|\
                                          (IEC958_AES3_CON_FS_48000<<24))
 
+#define PCM_RUNTIME_CHECK(sub) snd_BUG_ON(!(sub) || !(sub)->runtime)
+
 #endif /* __SOUND_PCM_H */
diff --git a/include/sound/pxa2xx-lib.h b/include/sound/pxa2xx-lib.h
new file mode 100644
index 000000000000..2fd3d251d9a5
--- /dev/null
+++ b/include/sound/pxa2xx-lib.h
@@ -0,0 +1,45 @@
+#ifndef PXA2XX_LIB_H
+#define PXA2XX_LIB_H
+
+#include <linux/platform_device.h>
+#include <sound/ac97_codec.h>
+
+/* PCM */
+
+struct pxa2xx_pcm_dma_params {
+        char *name;                     /* stream identifier */
+        u32 dcmd;                       /* DMA descriptor dcmd field */
+        volatile u32 *drcmr;            /* the DMA request channel to use */
+        u32 dev_addr;                   /* device physical address for DMA */
+};
+
+extern int __pxa2xx_pcm_hw_params(struct snd_pcm_substream *substream,
+                                struct snd_pcm_hw_params *params);
+extern int __pxa2xx_pcm_hw_free(struct snd_pcm_substream *substream);
+extern int pxa2xx_pcm_trigger(struct snd_pcm_substream *substream, int cmd);
+extern snd_pcm_uframes_t pxa2xx_pcm_pointer(struct snd_pcm_substream *substream);
+extern int __pxa2xx_pcm_prepare(struct snd_pcm_substream *substream);
+extern void pxa2xx_pcm_dma_irq(int dma_ch, void *dev_id);
+extern int __pxa2xx_pcm_open(struct snd_pcm_substream *substream);
+extern int __pxa2xx_pcm_close(struct snd_pcm_substream *substream);
+extern int pxa2xx_pcm_mmap(struct snd_pcm_substream *substream,
+        struct vm_area_struct *vma);
+extern int pxa2xx_pcm_preallocate_dma_buffer(struct snd_pcm *pcm, int stream);
+extern void pxa2xx_pcm_free_dma_buffers(struct snd_pcm *pcm);
+
+/* AC97 */
+
+extern unsigned short pxa2xx_ac97_read(struct snd_ac97 *ac97, unsigned short reg);
+extern void pxa2xx_ac97_write(struct snd_ac97 *ac97, unsigned short reg, unsigned short val);
+
+extern bool pxa2xx_ac97_try_warm_reset(struct snd_ac97 *ac97);
+extern bool pxa2xx_ac97_try_cold_reset(struct snd_ac97 *ac97);
+extern void pxa2xx_ac97_finish_reset(struct snd_ac97 *ac97);
+
+extern int pxa2xx_ac97_hw_suspend(void);
+extern int pxa2xx_ac97_hw_resume(void);
+
+extern int pxa2xx_ac97_hw_probe(struct platform_device *dev);
+extern void pxa2xx_ac97_hw_remove(struct platform_device *dev);
+
+#endif
diff --git a/include/sound/sb.h b/include/sound/sb.h
index d0c9ed3546c8..85f93c5fe1e4 100644
--- a/include/sound/sb.h
+++ b/include/sound/sb.h
@@ -240,11 +240,15 @@ struct snd_sb {
 #define SB_DT019X_CAP_MAIN      0x07
 
 #define SB_ALS4000_MONO_IO_CTRL 0x4b
+#define SB_ALS4000_OUT_MIXER_CTRL_2     0x4c
 #define SB_ALS4000_MIC_IN_GAIN  0x4d
+#define SB_ALS4000_ANALOG_REFRNC_VOLT_CTRL 0x4e
 #define SB_ALS4000_FMDAC        0x4f
 #define SB_ALS4000_3D_SND_FX    0x50
 #define SB_ALS4000_3D_TIME_DELAY        0x51
 #define SB_ALS4000_3D_AUTO_MUTE 0x52
+#define SB_ALS4000_ANALOG_BLOCK_CTRL 0x53
+#define SB_ALS4000_3D_DELAYLINE_PATTERN 0x54
 #define SB_ALS4000_QSOUND       0xdb
 
 /* IRQ setting bitmap */
@@ -257,6 +261,7 @@ struct snd_sb {
 #define SB_IRQTYPE_8BIT         0x01
 #define SB_IRQTYPE_16BIT        0x02
 #define SB_IRQTYPE_MPUIN        0x04
+#define ALS4K_IRQTYPE_CR1E_DMA  0x20
 
 /* DMA setting bitmap */
 #define SB_DMASETUP_DMA0        0x01
diff --git a/include/sound/snd_wavefront.h b/include/sound/snd_wavefront.h
index 9688d4be918e..fa149ca77e4b 100644
--- a/include/sound/snd_wavefront.h
+++ b/include/sound/snd_wavefront.h
@@ -1,7 +1,6 @@
 #ifndef __SOUND_SND_WAVEFRONT_H__
 #define __SOUND_SND_WAVEFRONT_H__
 
-#include "cs4231.h"
 #include "mpu401.h"
 #include "hwdep.h"
 #include "rawmidi.h"
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index c1b26fcc0b5c..ca699a3017f3 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -240,6 +240,7 @@ int snd_soc_dapm_sys_add(struct device *dev);
 /* dapm audio pin control and status */
 int snd_soc_dapm_enable_pin(struct snd_soc_codec *codec, char *pin);
 int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, char *pin);
+int snd_soc_dapm_nc_pin(struct snd_soc_codec *codec, char *pin);
 int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, char *pin);
 int snd_soc_dapm_sync(struct snd_soc_codec *codec);
 
diff --git a/include/sound/soc-of-simple.h b/include/sound/soc-of-simple.h
new file mode 100644
index 000000000000..a064e1934a56
--- /dev/null
+++ b/include/sound/soc-of-simple.h
@@ -0,0 +1,25 @@
+/*
+ * OF helpers for ALSA SoC
+ *
+ * Copyright (C) 2008, Secret Lab Technologies Ltd.
+ */
+
+#ifndef _INCLUDE_SOC_OF_H_
+#define _INCLUDE_SOC_OF_H_
+
+#if defined(CONFIG_SND_SOC_OF_SIMPLE) || defined(CONFIG_SND_SOC_OF_SIMPLE_MODULE)
+
+#include <linux/of.h>
+#include <sound/soc.h>
+
+int of_snd_soc_register_codec(struct snd_soc_codec_device *codec_dev,
+                              void *codec_data, struct snd_soc_dai *dai,
+                              struct device_node *node);
+
+int of_snd_soc_register_platform(struct snd_soc_platform *platform,
+                                 struct device_node *node,
+                                 struct snd_soc_dai *cpu_dai);
+
+#endif
+
+#endif /* _INCLUDE_SOC_OF_H_ */
diff --git a/include/sound/soc.h b/include/sound/soc.h
index 1890d87c5204..a1e0357a84d7 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -26,10 +26,12 @@
 /*
  * Convenience kcontrol builders
  */
-#define SOC_SINGLE_VALUE(reg, shift, max, invert) ((reg) | ((shift) << 8) |\
-        ((shift) << 12) | ((max) << 16) | ((invert) << 24))
-#define SOC_SINGLE_VALUE_EXT(reg, max, invert) ((reg) | ((max) << 16) |\
-        ((invert) << 31))
+#define SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert) \
+        ((unsigned long)&(struct soc_mixer_control) \
+        {.reg = xreg, .shift = xshift, .max = xmax, .invert = xinvert})
+#define SOC_SINGLE_VALUE_EXT(xreg, xmax, xinvert) \
+        ((unsigned long)&(struct soc_mixer_control) \
+        {.reg = xreg, .max = xmax, .invert = xinvert})
 #define SOC_SINGLE(xname, reg, shift, max, invert) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
@@ -43,64 +45,68 @@
         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw,\
         .put = snd_soc_put_volsw, \
         .private_value =  SOC_SINGLE_VALUE(reg, shift, max, invert) }
-#define SOC_DOUBLE(xname, reg, shift_left, shift_right, max, invert) \
+#define SOC_DOUBLE(xname, xreg, shift_left, shift_right, xmax, xinvert) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \
         .put = snd_soc_put_volsw, \
-        .private_value = (reg) | ((shift_left) << 8) | \
-                ((shift_right) << 12) | ((max) << 16) | ((invert) << 24) }
-#define SOC_DOUBLE_R(xname, reg_left, reg_right, shift, max, invert) \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = xreg, .shift = shift_left, .rshift = shift_right, \
+                 .max = xmax, .invert = xinvert} }
+#define SOC_DOUBLE_R(xname, reg_left, reg_right, xshift, xmax, xinvert) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
         .info = snd_soc_info_volsw_2r, \
         .get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \
-        .private_value = (reg_left) | ((shift) << 8)  | \
-                ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
-#define SOC_DOUBLE_TLV(xname, reg, shift_left, shift_right, max, invert, tlv_array) \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
+                .max = xmax, .invert = xinvert} }
+#define SOC_DOUBLE_TLV(xname, xreg, shift_left, shift_right, xmax, xinvert, tlv_array) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
         .tlv.p = (tlv_array), \
         .info = snd_soc_info_volsw, .get = snd_soc_get_volsw, \
         .put = snd_soc_put_volsw, \
-        .private_value = (reg) | ((shift_left) << 8) | \
-                ((shift_right) << 12) | ((max) << 16) | ((invert) << 24) }
-#define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, shift, max, invert, tlv_array) \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = xreg, .shift = shift_left, .rshift = shift_right,\
+                 .max = xmax, .invert = xinvert} }
+#define SOC_DOUBLE_R_TLV(xname, reg_left, reg_right, xshift, xmax, xinvert, tlv_array) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname),\
         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
                  SNDRV_CTL_ELEM_ACCESS_READWRITE,\
         .tlv.p = (tlv_array), \
         .info = snd_soc_info_volsw_2r, \
         .get = snd_soc_get_volsw_2r, .put = snd_soc_put_volsw_2r, \
-        .private_value = (reg_left) | ((shift) << 8)  | \
-                ((max) << 12) | ((invert) << 20) | ((reg_right) << 24) }
-#define SOC_DOUBLE_S8_TLV(xname, reg, min, max, tlv_array) \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = reg_left, .rreg = reg_right, .shift = xshift, \
+                .max = xmax, .invert = xinvert} }
+#define SOC_DOUBLE_S8_TLV(xname, xreg, xmin, xmax, tlv_array) \
 {       .iface  = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ | \
                   SNDRV_CTL_ELEM_ACCESS_READWRITE, \
         .tlv.p  = (tlv_array), \
         .info   = snd_soc_info_volsw_s8, .get = snd_soc_get_volsw_s8, \
         .put    = snd_soc_put_volsw_s8, \
-        .private_value = (reg) | (((signed char)max) << 16) | \
-                         (((signed char)min) << 24) }
-#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmask, xtexts) \
+        .private_value = (unsigned long)&(struct soc_mixer_control) \
+                {.reg = xreg, .min = xmin, .max = xmax} }
+#define SOC_ENUM_DOUBLE(xreg, xshift_l, xshift_r, xmax, xtexts) \
 {       .reg = xreg, .shift_l = xshift_l, .shift_r = xshift_r, \
-        .mask = xmask, .texts = xtexts }
-#define SOC_ENUM_SINGLE(xreg, xshift, xmask, xtexts) \
-        SOC_ENUM_DOUBLE(xreg, xshift, xshift, xmask, xtexts)
-#define SOC_ENUM_SINGLE_EXT(xmask, xtexts) \
-{       .mask = xmask, .texts = xtexts }
+        .max = xmax, .texts = xtexts }
+#define SOC_ENUM_SINGLE(xreg, xshift, xmax, xtexts) \
+        SOC_ENUM_DOUBLE(xreg, xshift, xshift, xmax, xtexts)
+#define SOC_ENUM_SINGLE_EXT(xmax, xtexts) \
+{       .max = xmax, .texts = xtexts }
 #define SOC_ENUM(xname, xenum) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname,\
         .info = snd_soc_info_enum_double, \
         .get = snd_soc_get_enum_double, .put = snd_soc_put_enum_double, \
         .private_value = (unsigned long)&xenum }
-#define SOC_SINGLE_EXT(xname, xreg, xshift, xmask, xinvert,\
+#define SOC_SINGLE_EXT(xname, xreg, xshift, xmax, xinvert,\
          xhandler_get, xhandler_put) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
         .info = snd_soc_info_volsw, \
         .get = xhandler_get, .put = xhandler_put, \
-        .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) }
-#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmask, xinvert,\
+        .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert) }
+#define SOC_SINGLE_EXT_TLV(xname, xreg, xshift, xmax, xinvert,\
          xhandler_get, xhandler_put, tlv_array) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
         .access = SNDRV_CTL_ELEM_ACCESS_TLV_READ |\
@@ -108,7 +114,7 @@
         .tlv.p = (tlv_array), \
         .info = snd_soc_info_volsw, \
         .get = xhandler_get, .put = xhandler_put, \
-        .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmask, xinvert) }
+        .private_value = SOC_SINGLE_VALUE(xreg, xshift, xmax, xinvert) }
 #define SOC_SINGLE_BOOL_EXT(xname, xdata, xhandler_get, xhandler_put) \
 {       .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = xname, \
         .info = snd_soc_info_bool_ext, \
@@ -410,6 +416,8 @@ struct snd_soc_codec {
         void *control_data; /* codec control (i2c/3wire) data */
         unsigned int (*read)(struct snd_soc_codec *, unsigned int);
         int (*write)(struct snd_soc_codec *, unsigned int, unsigned int);
+        int (*display_register)(struct snd_soc_codec *, char *,
+                                size_t, unsigned int);
         hw_write_t hw_write;
         hw_read_t hw_read;
         void *reg_cache;
@@ -516,13 +524,19 @@ struct snd_soc_pcm_runtime {
         struct snd_soc_device *socdev;
 };
 
+/* mixer control */
+struct soc_mixer_control {
+        int min, max;
+        unsigned int reg, rreg, shift, rshift, invert;
+};
+
 /* enumerated kcontrol */
 struct soc_enum {
         unsigned short reg;
         unsigned short reg2;
         unsigned char shift_l;
         unsigned char shift_r;
-        unsigned int mask;
+        unsigned int max;
         const char **texts;
         void *dapm;
 };
diff --git a/include/sound/tea575x-tuner.h b/include/sound/tea575x-tuner.h
index b62ce3e077f9..b6870cbaf2b3 100644
--- a/include/sound/tea575x-tuner.h
+++ b/include/sound/tea575x-tuner.h
@@ -43,6 +43,7 @@ struct snd_tea575x {
         unsigned int freq_fixup;        /* crystal onboard */
         unsigned int val;               /* hw value */
         unsigned long freq;             /* frequency */
+        unsigned long in_use;           /* set if the device is in use */
         struct snd_tea575x_ops *ops;
         void *private_data;
 };
diff --git a/include/sound/version.h b/include/sound/version.h
index 6b78aff273a8..4aafeda88634 100644
--- a/include/sound/version.h
+++ b/include/sound/version.h
@@ -1,3 +1,3 @@
 /* include/version.h */
-#define CONFIG_SND_VERSION "1.0.17"
+#define CONFIG_SND_VERSION "1.0.18rc3"
 #define CONFIG_SND_DATE ""
diff --git a/include/sound/vx_core.h b/include/sound/vx_core.h
index 4830651cc4cf..5456343ebe4c 100644
--- a/include/sound/vx_core.h
+++ b/include/sound/vx_core.h
@@ -235,37 +235,31 @@ irqreturn_t snd_vx_irq_handler(int irq, void *dev);
  */
 static inline int vx_test_and_ack(struct vx_core *chip)
 {
-        snd_assert(chip->ops->test_and_ack, return -ENXIO);
         return chip->ops->test_and_ack(chip);
 }
 
 static inline void vx_validate_irq(struct vx_core *chip, int enable)
 {
-        snd_assert(chip->ops->validate_irq, return);
         chip->ops->validate_irq(chip, enable);
 }
 
 static inline unsigned char snd_vx_inb(struct vx_core *chip, int reg)
 {
-        snd_assert(chip->ops->in8, return 0);
         return chip->ops->in8(chip, reg);
 }
 
 static inline unsigned int snd_vx_inl(struct vx_core *chip, int reg)
 {
-        snd_assert(chip->ops->in32, return 0);
         return chip->ops->in32(chip, reg);
 }
 
 static inline void snd_vx_outb(struct vx_core *chip, int reg, unsigned char val)
 {
-        snd_assert(chip->ops->out8, return);
         chip->ops->out8(chip, reg, val);
 }
 
 static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
 {
-        snd_assert(chip->ops->out32, return);
         chip->ops->out32(chip, reg, val);
 }
 
@@ -276,7 +270,6 @@ static inline void snd_vx_outl(struct vx_core *chip, int reg, unsigned int val)
 
 static inline void vx_reset_dsp(struct vx_core *chip)
 {
-        snd_assert(chip->ops->reset_dsp, return);
         chip->ops->reset_dsp(chip);
 }
 
@@ -304,14 +297,12 @@ int snd_vx_check_reg_bit(struct vx_core *chip, int reg, int mask, int bit, int t
 static inline void vx_pseudo_dma_write(struct vx_core *chip, struct snd_pcm_runtime *runtime,
                                        struct vx_pipe *pipe, int count)
 {
-        snd_assert(chip->ops->dma_write, return);
         chip->ops->dma_write(chip, runtime, pipe, count);
 }
 
 static inline void vx_pseudo_dma_read(struct vx_core *chip, struct snd_pcm_runtime *runtime,
                                       struct vx_pipe *pipe, int count)
 {
-        snd_assert(chip->ops->dma_read, return);
         chip->ops->dma_read(chip, runtime, pipe, count);
 }
 
diff --git a/include/sound/wss.h b/include/sound/wss.h
new file mode 100644
index 000000000000..fd01f22825cd
--- /dev/null
+++ b/include/sound/wss.h
@@ -0,0 +1,235 @@
+#ifndef __SOUND_WSS_H
+#define __SOUND_WSS_H
+
+/*
+ *  Copyright (c) by Jaroslav Kysela <perex@perex.cz>
+ *  Definitions for CS4231 & InterWave chips & compatible chips
+ *
+ *
+ *   This program is free software; you can redistribute it and/or modify
+ *   it under the terms of the GNU General Public License as published by
+ *   the Free Software Foundation; either version 2 of the License, or
+ *   (at your option) any later version.
+ *
+ *   This program is distributed in the hope that it will be useful,
+ *   but WITHOUT ANY WARRANTY; without even the implied warranty of
+ *   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ *   GNU General Public License for more details.
+ *
+ *   You should have received a copy of the GNU General Public License
+ *   along with this program; if not, write to the Free Software
+ *   Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
+ *
+ */
+
+#include "control.h"
+#include "pcm.h"
+#include "timer.h"
+
+#include "cs4231-regs.h"
+
+/* defines for codec.mode */
+
+#define WSS_MODE_NONE   0x0000
+#define WSS_MODE_PLAY   0x0001
+#define WSS_MODE_RECORD 0x0002
+#define WSS_MODE_TIMER  0x0004
+#define WSS_MODE_OPEN   (WSS_MODE_PLAY|WSS_MODE_RECORD|WSS_MODE_TIMER)
+
+/* defines for codec.hardware */
+
+#define WSS_HW_DETECT        0x0000     /* let CS4231 driver detect chip */
+#define WSS_HW_DETECT3  0x0001  /* allow mode 3 */
+#define WSS_HW_TYPE_MASK        0xff00  /* type mask */
+#define WSS_HW_CS4231_MASK   0x0100     /* CS4231 serie */
+#define WSS_HW_CS4231        0x0100     /* CS4231 chip */
+#define WSS_HW_CS4231A       0x0101     /* CS4231A chip */
+#define WSS_HW_AD1845   0x0102  /* AD1845 chip */
+#define WSS_HW_CS4232_MASK   0x0200     /* CS4232 serie (has control ports) */
+#define WSS_HW_CS4232        0x0200     /* CS4232 */
+#define WSS_HW_CS4232A       0x0201     /* CS4232A */
+#define WSS_HW_CS4236   0x0202  /* CS4236 */
+#define WSS_HW_CS4236B_MASK     0x0400  /* CS4236B serie (has extended control regs) */
+#define WSS_HW_CS4235   0x0400  /* CS4235 - Crystal Clear (tm) stereo enhancement */
+#define WSS_HW_CS4236B       0x0401     /* CS4236B */
+#define WSS_HW_CS4237B       0x0402     /* CS4237B - SRS 3D */
+#define WSS_HW_CS4238B  0x0403  /* CS4238B - QSOUND 3D */
+#define WSS_HW_CS4239   0x0404  /* CS4239 - Crystal Clear (tm) stereo enhancement */
+#define WSS_HW_AD1848_MASK      0x0800  /* AD1848 serie (half duplex) */
+#define WSS_HW_AD1847           0x0801  /* AD1847 chip */
+#define WSS_HW_AD1848           0x0802  /* AD1848 chip */
+#define WSS_HW_CS4248           0x0803  /* CS4248 chip */
+#define WSS_HW_CMI8330          0x0804  /* CMI8330 chip */
+#define WSS_HW_THINKPAD         0x0805  /* Thinkpad 360/750/755 */
+/* compatible, but clones */
+#define WSS_HW_INTERWAVE     0x1000     /* InterWave chip */
+#define WSS_HW_OPL3SA2       0x1101     /* OPL3-SA2 chip, similar to cs4231 */
+#define WSS_HW_OPTI93X  0x1102  /* Opti 930/931/933 */
+
+/* defines for codec.hwshare */
+#define WSS_HWSHARE_IRQ (1<<0)
+#define WSS_HWSHARE_DMA1        (1<<1)
+#define WSS_HWSHARE_DMA2        (1<<2)
+
+/* IBM Thinkpad specific stuff */
+#define AD1848_THINKPAD_CTL_PORT1               0x15e8
+#define AD1848_THINKPAD_CTL_PORT2               0x15e9
+#define AD1848_THINKPAD_CS4248_ENABLE_BIT       0x02
+
+struct snd_wss {
+        unsigned long port;             /* base i/o port */
+        struct resource *res_port;
+        unsigned long cport;            /* control base i/o port (CS4236) */
+        struct resource *res_cport;
+        int irq;                        /* IRQ line */
+        int dma1;                       /* playback DMA */
+        int dma2;                       /* record DMA */
+        unsigned short version;         /* version of CODEC chip */
+        unsigned short mode;            /* see to WSS_MODE_XXXX */
+        unsigned short hardware;        /* see to WSS_HW_XXXX */
+        unsigned short hwshare;         /* shared resources */
+        unsigned short single_dma:1,    /* forced single DMA mode (GUS 16-bit */
+                                        /* daughter board) or dma1 == dma2 */
+                       ebus_flag:1,     /* SPARC: EBUS present */
+                       thinkpad_flag:1; /* Thinkpad CS4248 needs extra help */
+
+        struct snd_card *card;
+        struct snd_pcm *pcm;
+        struct snd_pcm_substream *playback_substream;
+        struct snd_pcm_substream *capture_substream;
+        struct snd_timer *timer;
+
+        unsigned char image[32];        /* registers image */
+        unsigned char eimage[32];       /* extended registers image */
+        unsigned char cimage[16];       /* control registers image */
+        int mce_bit;
+        int calibrate_mute;
+        int sw_3d_bit;
+        unsigned int p_dma_size;
+        unsigned int c_dma_size;
+
+        spinlock_t reg_lock;
+        struct mutex mce_mutex;
+        struct mutex open_mutex;
+
+        int (*rate_constraint) (struct snd_pcm_runtime *runtime);
+        void (*set_playback_format) (struct snd_wss *chip,
+                                     struct snd_pcm_hw_params *hw_params,
+                                     unsigned char pdfr);
+        void (*set_capture_format) (struct snd_wss *chip,
+                                    struct snd_pcm_hw_params *hw_params,
+                                    unsigned char cdfr);
+        void (*trigger) (struct snd_wss *chip, unsigned int what, int start);
+#ifdef CONFIG_PM
+        void (*suspend) (struct snd_wss *chip);
+        void (*resume) (struct snd_wss *chip);
+#endif
+        void *dma_private_data;
+        int (*claim_dma) (struct snd_wss *chip,
+                          void *dma_private_data, int dma);
+        int (*release_dma) (struct snd_wss *chip,
+                            void *dma_private_data, int dma);
+};
+
+/* exported functions */
+
+void snd_wss_out(struct snd_wss *chip, unsigned char reg, unsigned char val);
+unsigned char snd_wss_in(struct snd_wss *chip, unsigned char reg);
+void snd_cs4236_ext_out(struct snd_wss *chip,
+                        unsigned char reg, unsigned char val);
+unsigned char snd_cs4236_ext_in(struct snd_wss *chip, unsigned char reg);
+void snd_wss_mce_up(struct snd_wss *chip);
+void snd_wss_mce_down(struct snd_wss *chip);
+
+void snd_wss_overrange(struct snd_wss *chip);
+
+irqreturn_t snd_wss_interrupt(int irq, void *dev_id);
+
+const char *snd_wss_chip_id(struct snd_wss *chip);
+
+int snd_wss_create(struct snd_card *card,
+                      unsigned long port,
+                      unsigned long cport,
+                      int irq, int dma1, int dma2,
+                      unsigned short hardware,
+                      unsigned short hwshare,
+                      struct snd_wss **rchip);
+int snd_wss_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm);
+int snd_wss_timer(struct snd_wss *chip, int device, struct snd_timer **rtimer);
+int snd_wss_mixer(struct snd_wss *chip);
+
+const struct snd_pcm_ops *snd_wss_get_pcm_ops(int direction);
+
+int snd_cs4236_create(struct snd_card *card,
+                      unsigned long port,
+                      unsigned long cport,
+                      int irq, int dma1, int dma2,
+                      unsigned short hardware,
+                      unsigned short hwshare,
+                      struct snd_wss **rchip);
+int snd_cs4236_pcm(struct snd_wss *chip, int device, struct snd_pcm **rpcm);
+int snd_cs4236_mixer(struct snd_wss *chip);
+
+/*
+ *  mixer library
+ */
+
+#define WSS_SINGLE(xname, xindex, reg, shift, mask, invert) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .name = xname, \
+  .index = xindex, \
+  .info = snd_wss_info_single, \
+  .get = snd_wss_get_single, \
+  .put = snd_wss_put_single, \
+  .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24) }
+
+int snd_wss_info_single(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_info *uinfo);
+int snd_wss_get_single(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol);
+int snd_wss_put_single(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol);
+
+#define WSS_DOUBLE(xname, xindex, left_reg, right_reg, shift_left, shift_right, mask, invert) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .name = xname, \
+  .index = xindex, \
+  .info = snd_wss_info_double, \
+  .get = snd_wss_get_double, \
+  .put = snd_wss_put_double, \
+  .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
+                   (shift_right << 19) | (mask << 24) | (invert << 22) }
+
+#define WSS_SINGLE_TLV(xname, xindex, reg, shift, mask, invert, xtlv) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
+  .name = xname, \
+  .index = xindex, \
+  .info = snd_wss_info_single, \
+  .get = snd_wss_get_single, \
+  .put = snd_wss_put_single, \
+  .private_value = reg | (shift << 8) | (mask << 16) | (invert << 24), \
+  .tlv = { .p = (xtlv) } }
+
+#define WSS_DOUBLE_TLV(xname, xindex, left_reg, right_reg, \
+                        shift_left, shift_right, mask, invert, xtlv) \
+{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, \
+  .access = SNDRV_CTL_ELEM_ACCESS_READWRITE | SNDRV_CTL_ELEM_ACCESS_TLV_READ, \
+  .name = xname, \
+  .index = xindex, \
+  .info = snd_wss_info_double, \
+  .get = snd_wss_get_double, \
+  .put = snd_wss_put_double, \
+  .private_value = left_reg | (right_reg << 8) | (shift_left << 16) | \
+                   (shift_right << 19) | (mask << 24) | (invert << 22), \
+  .tlv = { .p = (xtlv) } }
+
+
+int snd_wss_info_double(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_info *uinfo);
+int snd_wss_get_double(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol);
+int snd_wss_put_double(struct snd_kcontrol *kcontrol,
+                        struct snd_ctl_elem_value *ucontrol);
+
+#endif /* __SOUND_WSS_H */
diff --git a/include/video/atmel_lcdc.h b/include/video/atmel_lcdc.h
index 920c4e9cb93d..6ad87f485992 100644
--- a/include/video/atmel_lcdc.h
+++ b/include/video/atmel_lcdc.h
@@ -30,6 +30,7 @@
  */
 #define ATMEL_LCDC_WIRING_BGR   0
 #define ATMEL_LCDC_WIRING_RGB   1
+#define ATMEL_LCDC_WIRING_RGB555        2
 
 
  /* LCD Controller info data structure, stored in device platform_data */
diff --git a/include/video/cyblafb.h b/include/video/cyblafb.h
index 717440575380..d3c1d4e2c8e3 100644
--- a/include/video/cyblafb.h
+++ b/include/video/cyblafb.h
@@ -4,7 +4,7 @@
 #endif
 
 #if CYBLAFB_DEBUG
-#define debug(f,a...)   printk("%s:" f,  __FUNCTION__ , ## a);
+#define debug(f,a...)   printk("%s:" f,  __func__ , ## a);
 #else
 #define debug(f,a...)
 #endif
diff --git a/include/video/metronomefb.h b/include/video/metronomefb.h
index dab04b4fad7f..9863f4b6d418 100644
--- a/include/video/metronomefb.h
+++ b/include/video/metronomefb.h
@@ -12,14 +12,6 @@
 #ifndef _LINUX_METRONOMEFB_H_
 #define _LINUX_METRONOMEFB_H_
 
-/* address and control descriptors used by metronome controller */
-struct metromem_desc {
-        u32 mFDADR0;
-        u32 mFSADR0;
-        u32 mFIDR0;
-        u32 mLDCMD0;
-};
-
 /* command structure used by metronome controller */
 struct metromem_cmd {
         u16 opcode;
@@ -29,34 +21,37 @@ struct metromem_cmd {
 
 /* struct used by metronome. board specific stuff comes from *board */
 struct metronomefb_par {
-        unsigned char *metromem;
-        struct metromem_desc *metromem_desc;
         struct metromem_cmd *metromem_cmd;
         unsigned char *metromem_wfm;
         unsigned char *metromem_img;
         u16 *metromem_img_csum;
         u16 *csum_table;
-        int metromemsize;
         dma_addr_t metromem_dma;
-        dma_addr_t metromem_desc_dma;
         struct fb_info *info;
         struct metronome_board *board;
         wait_queue_head_t waitq;
         u8 frame_count;
+        int extra_size;
+        int dt;
 };
 
-/* board specific routines */
+/* board specific routines and data */
 struct metronome_board {
-        struct module *owner;
-        void (*free_irq)(struct fb_info *);
-        void (*init_gpio_regs)(struct metronomefb_par *);
-        void (*init_lcdc_regs)(struct metronomefb_par *);
-        void (*post_dma_setup)(struct metronomefb_par *);
+        struct module *owner; /* the platform device */
         void (*set_rst)(struct metronomefb_par *, int);
         void (*set_stdby)(struct metronomefb_par *, int);
+        void (*cleanup)(struct metronomefb_par *);
         int (*met_wait_event)(struct metronomefb_par *);
         int (*met_wait_event_intr)(struct metronomefb_par *);
         int (*setup_irq)(struct fb_info *);
+        int (*setup_fb)(struct metronomefb_par *);
+        int (*setup_io)(struct metronomefb_par *);
+        int (*get_panel_type)(void);
+        unsigned char *metromem;
+        int fw;
+        int fh;
+        int wfm_size;
+        struct fb_info *host_fbinfo; /* the host LCD controller's fbi */
 };
 
 #endif
diff --git a/include/video/neomagic.h b/include/video/neomagic.h
index 38910da0ae59..08b663782956 100644
--- a/include/video/neomagic.h
+++ b/include/video/neomagic.h
@@ -123,7 +123,6 @@ typedef volatile struct {
 
 struct neofb_par {
         struct vgastate state;
-        struct mutex open_lock;
         unsigned int ref_count;
 
         unsigned char MiscOutReg;       /* Misc */
diff --git a/include/video/radeon.h b/include/video/radeon.h
index 099ffa5e5bee..d5dcaf154ba4 100644
--- a/include/video/radeon.h
+++ b/include/video/radeon.h
@@ -386,7 +386,7 @@
 #define SC_BOTTOM_RIGHT                        0x16F0  
 #define SRC_SC_BOTTOM_RIGHT                    0x16F4  
 #define RB2D_DSTCACHE_MODE                     0x3428
-#define RB2D_DSTCACHE_CTLSTAT                  0x342C
+#define RB2D_DSTCACHE_CTLSTAT_broken           0x342C /* do not use */
 #define LVDS_GEN_CNTL                          0x02d0
 #define LVDS_PLL_CNTL                          0x02d4
 #define FP2_GEN_CNTL                           0x0288
@@ -525,6 +525,9 @@
 #define CRTC_DISPLAY_DIS                           (1 << 10)
 #define CRTC_CRT_ON                                (1 << 15)
 
+/* DSTCACHE_MODE bits constants */
+#define RB2D_DC_AUTOFLUSH_ENABLE                   (1 << 8)
+#define RB2D_DC_DC_DISABLE_IGNORE_PE               (1 << 17)
 
 /* DSTCACHE_CTLSTAT bit constants */
 #define RB2D_DC_FLUSH_2D                           (1 << 0)
@@ -532,6 +535,9 @@
 #define RB2D_DC_FLUSH_ALL                          (RB2D_DC_FLUSH_2D | RB2D_DC_FREE_2D)
 #define RB2D_DC_BUSY                               (1 << 31)
 
+/* DSTCACHE_MODE bits constants */
+#define RB2D_DC_AUTOFLUSH_ENABLE                   (1 << 8)
+#define RB2D_DC_DC_DISABLE_IGNORE_PE               (1 << 17)
 
 /* CRTC_GEN_CNTL bit constants */
 #define CRTC_DBL_SCAN_EN                           0x00000001
@@ -863,15 +869,10 @@
 #define GMC_DST_16BPP_YVYU422                      0x00000c00
 #define GMC_DST_32BPP_AYUV444                      0x00000e00
 #define GMC_DST_16BPP_ARGB4444                     0x00000f00
-#define GMC_SRC_MONO                               0x00000000
-#define GMC_SRC_MONO_LBKGD                         0x00001000
-#define GMC_SRC_DSTCOLOR                           0x00003000
 #define GMC_BYTE_ORDER_MSB_TO_LSB                  0x00000000
 #define GMC_BYTE_ORDER_LSB_TO_MSB                  0x00004000
 #define GMC_DP_CONVERSION_TEMP_9300                0x00008000
 #define GMC_DP_CONVERSION_TEMP_6500                0x00000000
-#define GMC_DP_SRC_RECT                            0x02000000
-#define GMC_DP_SRC_HOST                            0x03000000
 #define GMC_DP_SRC_HOST_BYTEALIGN                  0x04000000
 #define GMC_3D_FCN_EN_CLR                          0x00000000
 #define GMC_3D_FCN_EN_SET                          0x08000000
@@ -882,6 +883,9 @@
 #define GMC_WRITE_MASK_LEAVE                       0x00000000
 #define GMC_WRITE_MASK_SET                         0x40000000
 #define GMC_CLR_CMP_CNTL_DIS                       (1 << 28)
+#define GMC_SRC_DATATYPE_MASK                      (3 << 12)
+#define GMC_SRC_DATATYPE_MONO_FG_BG                (0 << 12)
+#define GMC_SRC_DATATYPE_MONO_FG_LA                (1 << 12)
 #define GMC_SRC_DATATYPE_COLOR                     (3 << 12)
 #define ROP3_S                                     0x00cc0000
 #define ROP3_SRCCOPY                               0x00cc0000
@@ -890,6 +894,7 @@
 #define DP_SRC_SOURCE_MASK                         (7    << 24)
 #define GMC_BRUSH_NONE                             (15   <<  4)
 #define DP_SRC_SOURCE_MEMORY                       (2    << 24)
+#define DP_SRC_SOURCE_HOST_DATA                    (3    << 24)
 #define GMC_BRUSH_SOLIDCOLOR                       0x000000d0
 
 /* DP_MIX bit constants */
@@ -975,6 +980,12 @@
 #define DISP_PWR_MAN_TV_ENABLE_RST                 (1 << 25)
 #define DISP_PWR_MAN_AUTO_PWRUP_EN                 (1 << 26)
 
+/* RBBM_GUICNTL constants */
+#define RBBM_GUICNTL_HOST_DATA_SWAP_NONE           (0 << 0)
+#define RBBM_GUICNTL_HOST_DATA_SWAP_16BIT          (1 << 0)
+#define RBBM_GUICNTL_HOST_DATA_SWAP_32BIT          (2 << 0)
+#define RBBM_GUICNTL_HOST_DATA_SWAP_HDW            (3 << 0)
+
 /* masks */
 
 #define CONFIG_MEMSIZE_MASK             0x1f000000
diff --git a/include/video/s1d13xxxfb.h b/include/video/s1d13xxxfb.h
index c99d261df8f7..fe41b8407946 100644
--- a/include/video/s1d13xxxfb.h
+++ b/include/video/s1d13xxxfb.h
@@ -14,7 +14,8 @@
 #define S1D13XXXFB_H
 
 #define S1D_PALETTE_SIZE                256
-#define S1D_CHIP_REV                    7       /* expected chip revision number for s1d13806 */
+#define S1D13506_CHIP_REV               4       /* expected chip revision number for s1d13506 */
+#define S1D13806_CHIP_REV               7       /* expected chip revision number for s1d13806 */
 #define S1D_FBID                        "S1D13806"
 #define S1D_DEVICENAME                  "s1d13806fb"
 
diff --git a/include/xen/balloon.h b/include/xen/balloon.h
deleted file mode 100644
index fe43b0f3c86a..000000000000
--- a/include/xen/balloon.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/******************************************************************************
- * balloon.h
- *
- * Xen balloon driver - enables returning/claiming memory to/from Xen.
- *
- * Copyright (c) 2003, B Dragovic
- * Copyright (c) 2003-2004, M Williamson, K Fraser
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License version 2
- * as published by the Free Software Foundation; or, when distributed
- * separately from the Linux kernel or incorporated into other
- * software packages, subject to the following license:
- *
- * Permission is hereby granted, free of charge, to any person obtaining a copy
- * of this source file (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy, modify,
- * merge, publish, distribute, sublicense, and/or sell copies of the Software,
- * and to permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
- * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
- * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
- * IN THE SOFTWARE.
- */
-
-#ifndef __XEN_BALLOON_H__
-#define __XEN_BALLOON_H__
-
-#include <linux/spinlock.h>
-
-#if 0
-/*
- * Inform the balloon driver that it should allow some slop for device-driver
- * memory activities.
- */
-void balloon_update_driver_allowance(long delta);
-
-/* Allocate/free a set of empty pages in low memory (i.e., no RAM mapped). */
-struct page **alloc_empty_pages_and_pagevec(int nr_pages);
-void free_empty_pages_and_pagevec(struct page **pagevec, int nr_pages);
-
-void balloon_release_driver_page(struct page *page);
-
-/*
- * Prevent the balloon driver from changing the memory reservation during
- * a driver critical region.
- */
-extern spinlock_t balloon_lock;
-#define balloon_lock(__flags)   spin_lock_irqsave(&balloon_lock, __flags)
-#define balloon_unlock(__flags) spin_unlock_irqrestore(&balloon_lock, __flags)
-#endif
-
-#endif /* __XEN_BALLOON_H__ */
diff --git a/include/xen/events.h b/include/xen/events.h
index 4680ff3fbc91..0d5f1adc0363 100644
--- a/include/xen/events.h
+++ b/include/xen/events.h
@@ -46,6 +46,8 @@ extern void xen_irq_resume(void);
 
 /* Clear an irq's pending state, in preparation for polling on it */
 void xen_clear_irq_pending(int irq);
+void xen_set_irq_pending(int irq);
+bool xen_test_irq_pending(int irq);
 
 /* Poll waiting for an irq to become pending.  In the usual case, the
    irq will be disabled so it won't deliver an interrupt. */