diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/linux/amba/pl08x.h | 99 | ||||
-rw-r--r-- | include/linux/dmaengine.h | 2 |
2 files changed, 51 insertions, 50 deletions
diff --git a/include/linux/amba/pl08x.h b/include/linux/amba/pl08x.h index 521a0f8974ac..3111385b8ca7 100644 --- a/include/linux/amba/pl08x.h +++ b/include/linux/amba/pl08x.h | |||
@@ -12,7 +12,6 @@ | |||
12 | * | 12 | * |
13 | * Please credit ARM.com | 13 | * Please credit ARM.com |
14 | * Documentation: ARM DDI 0196D | 14 | * Documentation: ARM DDI 0196D |
15 | * | ||
16 | */ | 15 | */ |
17 | 16 | ||
18 | #ifndef AMBA_PL08X_H | 17 | #ifndef AMBA_PL08X_H |
@@ -22,6 +21,15 @@ | |||
22 | #include <linux/dmaengine.h> | 21 | #include <linux/dmaengine.h> |
23 | #include <linux/interrupt.h> | 22 | #include <linux/interrupt.h> |
24 | 23 | ||
24 | struct pl08x_lli; | ||
25 | struct pl08x_driver_data; | ||
26 | |||
27 | /* Bitmasks for selecting AHB ports for DMA transfers */ | ||
28 | enum { | ||
29 | PL08X_AHB1 = (1 << 0), | ||
30 | PL08X_AHB2 = (1 << 1) | ||
31 | }; | ||
32 | |||
25 | /** | 33 | /** |
26 | * struct pl08x_channel_data - data structure to pass info between | 34 | * struct pl08x_channel_data - data structure to pass info between |
27 | * platform and PL08x driver regarding channel configuration | 35 | * platform and PL08x driver regarding channel configuration |
@@ -46,8 +54,10 @@ | |||
46 | * @circular_buffer: whether the buffer passed in is circular and | 54 | * @circular_buffer: whether the buffer passed in is circular and |
47 | * shall simply be looped round round (like a record baby round | 55 | * shall simply be looped round round (like a record baby round |
48 | * round round round) | 56 | * round round round) |
49 | * @single: the device connected to this channel will request single | 57 | * @single: the device connected to this channel will request single DMA |
50 | * DMA transfers, not bursts. (Bursts are default.) | 58 | * transfers, not bursts. (Bursts are default.) |
59 | * @periph_buses: the device connected to this channel is accessible via | ||
60 | * these buses (use PL08X_AHB1 | PL08X_AHB2). | ||
51 | */ | 61 | */ |
52 | struct pl08x_channel_data { | 62 | struct pl08x_channel_data { |
53 | char *bus_id; | 63 | char *bus_id; |
@@ -55,10 +65,10 @@ struct pl08x_channel_data { | |||
55 | int max_signal; | 65 | int max_signal; |
56 | u32 muxval; | 66 | u32 muxval; |
57 | u32 cctl; | 67 | u32 cctl; |
58 | u32 ccfg; | ||
59 | dma_addr_t addr; | 68 | dma_addr_t addr; |
60 | bool circular_buffer; | 69 | bool circular_buffer; |
61 | bool single; | 70 | bool single; |
71 | u8 periph_buses; | ||
62 | }; | 72 | }; |
63 | 73 | ||
64 | /** | 74 | /** |
@@ -67,24 +77,23 @@ struct pl08x_channel_data { | |||
67 | * @addr: current address | 77 | * @addr: current address |
68 | * @maxwidth: the maximum width of a transfer on this bus | 78 | * @maxwidth: the maximum width of a transfer on this bus |
69 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 | 79 | * @buswidth: the width of this bus in bytes: 1, 2 or 4 |
70 | * @fill_bytes: bytes required to fill to the next bus memory | 80 | * @fill_bytes: bytes required to fill to the next bus memory boundary |
71 | * boundary | ||
72 | */ | 81 | */ |
73 | struct pl08x_bus_data { | 82 | struct pl08x_bus_data { |
74 | dma_addr_t addr; | 83 | dma_addr_t addr; |
75 | u8 maxwidth; | 84 | u8 maxwidth; |
76 | u8 buswidth; | 85 | u8 buswidth; |
77 | u32 fill_bytes; | 86 | size_t fill_bytes; |
78 | }; | 87 | }; |
79 | 88 | ||
80 | /** | 89 | /** |
81 | * struct pl08x_phy_chan - holder for the physical channels | 90 | * struct pl08x_phy_chan - holder for the physical channels |
82 | * @id: physical index to this channel | 91 | * @id: physical index to this channel |
83 | * @lock: a lock to use when altering an instance of this struct | 92 | * @lock: a lock to use when altering an instance of this struct |
84 | * @signal: the physical signal (aka channel) serving this | 93 | * @signal: the physical signal (aka channel) serving this physical channel |
85 | * physical channel right now | 94 | * right now |
86 | * @serving: the virtual channel currently being served by this | 95 | * @serving: the virtual channel currently being served by this physical |
87 | * physical channel | 96 | * channel |
88 | */ | 97 | */ |
89 | struct pl08x_phy_chan { | 98 | struct pl08x_phy_chan { |
90 | unsigned int id; | 99 | unsigned int id; |
@@ -92,11 +101,6 @@ struct pl08x_phy_chan { | |||
92 | spinlock_t lock; | 101 | spinlock_t lock; |
93 | int signal; | 102 | int signal; |
94 | struct pl08x_dma_chan *serving; | 103 | struct pl08x_dma_chan *serving; |
95 | u32 csrc; | ||
96 | u32 cdst; | ||
97 | u32 clli; | ||
98 | u32 cctl; | ||
99 | u32 ccfg; | ||
100 | }; | 104 | }; |
101 | 105 | ||
102 | /** | 106 | /** |
@@ -108,26 +112,23 @@ struct pl08x_txd { | |||
108 | struct dma_async_tx_descriptor tx; | 112 | struct dma_async_tx_descriptor tx; |
109 | struct list_head node; | 113 | struct list_head node; |
110 | enum dma_data_direction direction; | 114 | enum dma_data_direction direction; |
111 | struct pl08x_bus_data srcbus; | 115 | dma_addr_t src_addr; |
112 | struct pl08x_bus_data dstbus; | 116 | dma_addr_t dst_addr; |
113 | int len; | 117 | size_t len; |
114 | dma_addr_t llis_bus; | 118 | dma_addr_t llis_bus; |
115 | void *llis_va; | 119 | struct pl08x_lli *llis_va; |
116 | struct pl08x_channel_data *cd; | 120 | /* Default cctl value for LLIs */ |
117 | bool active; | 121 | u32 cctl; |
118 | /* | 122 | /* |
119 | * Settings to be put into the physical channel when we | 123 | * Settings to be put into the physical channel when we |
120 | * trigger this txd | 124 | * trigger this txd. Other registers are in llis_va[0]. |
121 | */ | 125 | */ |
122 | u32 csrc; | 126 | u32 ccfg; |
123 | u32 cdst; | ||
124 | u32 clli; | ||
125 | u32 cctl; | ||
126 | }; | 127 | }; |
127 | 128 | ||
128 | /** | 129 | /** |
129 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual | 130 | * struct pl08x_dma_chan_state - holds the PL08x specific virtual channel |
130 | * channel states | 131 | * states |
131 | * @PL08X_CHAN_IDLE: the channel is idle | 132 | * @PL08X_CHAN_IDLE: the channel is idle |
132 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport | 133 | * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport |
133 | * channel and is running a transfer on it | 134 | * channel and is running a transfer on it |
@@ -147,6 +148,8 @@ enum pl08x_dma_chan_state { | |||
147 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel | 148 | * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel |
148 | * @chan: wrappped abstract channel | 149 | * @chan: wrappped abstract channel |
149 | * @phychan: the physical channel utilized by this channel, if there is one | 150 | * @phychan: the physical channel utilized by this channel, if there is one |
151 | * @phychan_hold: if non-zero, hold on to the physical channel even if we | ||
152 | * have no pending entries | ||
150 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc | 153 | * @tasklet: tasklet scheduled by the IRQ to handle actual work etc |
151 | * @name: name of channel | 154 | * @name: name of channel |
152 | * @cd: channel platform data | 155 | * @cd: channel platform data |
@@ -154,53 +157,49 @@ enum pl08x_dma_chan_state { | |||
154 | * @runtime_direction: current direction of this channel according to | 157 | * @runtime_direction: current direction of this channel according to |
155 | * runtime config | 158 | * runtime config |
156 | * @lc: last completed transaction on this channel | 159 | * @lc: last completed transaction on this channel |
157 | * @desc_list: queued transactions pending on this channel | 160 | * @pend_list: queued transactions pending on this channel |
158 | * @at: active transaction on this channel | 161 | * @at: active transaction on this channel |
159 | * @lockflags: sometimes we let a lock last between two function calls, | ||
160 | * especially prep/submit, and then we need to store the IRQ flags | ||
161 | * in the channel state, here | ||
162 | * @lock: a lock for this channel data | 162 | * @lock: a lock for this channel data |
163 | * @host: a pointer to the host (internal use) | 163 | * @host: a pointer to the host (internal use) |
164 | * @state: whether the channel is idle, paused, running etc | 164 | * @state: whether the channel is idle, paused, running etc |
165 | * @slave: whether this channel is a device (slave) or for memcpy | 165 | * @slave: whether this channel is a device (slave) or for memcpy |
166 | * @waiting: a TX descriptor on this channel which is waiting for | 166 | * @waiting: a TX descriptor on this channel which is waiting for a physical |
167 | * a physical channel to become available | 167 | * channel to become available |
168 | */ | 168 | */ |
169 | struct pl08x_dma_chan { | 169 | struct pl08x_dma_chan { |
170 | struct dma_chan chan; | 170 | struct dma_chan chan; |
171 | struct pl08x_phy_chan *phychan; | 171 | struct pl08x_phy_chan *phychan; |
172 | int phychan_hold; | ||
172 | struct tasklet_struct tasklet; | 173 | struct tasklet_struct tasklet; |
173 | char *name; | 174 | char *name; |
174 | struct pl08x_channel_data *cd; | 175 | struct pl08x_channel_data *cd; |
175 | dma_addr_t runtime_addr; | 176 | dma_addr_t runtime_addr; |
176 | enum dma_data_direction runtime_direction; | 177 | enum dma_data_direction runtime_direction; |
177 | atomic_t last_issued; | ||
178 | dma_cookie_t lc; | 178 | dma_cookie_t lc; |
179 | struct list_head desc_list; | 179 | struct list_head pend_list; |
180 | struct pl08x_txd *at; | 180 | struct pl08x_txd *at; |
181 | unsigned long lockflags; | ||
182 | spinlock_t lock; | 181 | spinlock_t lock; |
183 | void *host; | 182 | struct pl08x_driver_data *host; |
184 | enum pl08x_dma_chan_state state; | 183 | enum pl08x_dma_chan_state state; |
185 | bool slave; | 184 | bool slave; |
186 | struct pl08x_txd *waiting; | 185 | struct pl08x_txd *waiting; |
187 | }; | 186 | }; |
188 | 187 | ||
189 | /** | 188 | /** |
190 | * struct pl08x_platform_data - the platform configuration for the | 189 | * struct pl08x_platform_data - the platform configuration for the PL08x |
191 | * PL08x PrimeCells. | 190 | * PrimeCells. |
192 | * @slave_channels: the channels defined for the different devices on the | 191 | * @slave_channels: the channels defined for the different devices on the |
193 | * platform, all inclusive, including multiplexed channels. The available | 192 | * platform, all inclusive, including multiplexed channels. The available |
194 | * physical channels will be multiplexed around these signals as they | 193 | * physical channels will be multiplexed around these signals as they are |
195 | * are requested, just enumerate all possible channels. | 194 | * requested, just enumerate all possible channels. |
196 | * @get_signal: request a physical signal to be used for a DMA | 195 | * @get_signal: request a physical signal to be used for a DMA transfer |
197 | * transfer immediately: if there is some multiplexing or similar blocking | 196 | * immediately: if there is some multiplexing or similar blocking the use |
198 | * the use of the channel the transfer can be denied by returning | 197 | * of the channel the transfer can be denied by returning less than zero, |
199 | * less than zero, else it returns the allocated signal number | 198 | * else it returns the allocated signal number |
200 | * @put_signal: indicate to the platform that this physical signal is not | 199 | * @put_signal: indicate to the platform that this physical signal is not |
201 | * running any DMA transfer and multiplexing can be recycled | 200 | * running any DMA transfer and multiplexing can be recycled |
202 | * @bus_bit_lli: Bit[0] of the address indicated which AHB bus master the | 201 | * @lli_buses: buses which LLIs can be fetched from: PL08X_AHB1 | PL08X_AHB2 |
203 | * LLI addresses are on 0/1 Master 1/2. | 202 | * @mem_buses: buses which memory can be accessed from: PL08X_AHB1 | PL08X_AHB2 |
204 | */ | 203 | */ |
205 | struct pl08x_platform_data { | 204 | struct pl08x_platform_data { |
206 | struct pl08x_channel_data *slave_channels; | 205 | struct pl08x_channel_data *slave_channels; |
@@ -208,6 +207,8 @@ struct pl08x_platform_data { | |||
208 | struct pl08x_channel_data memcpy_channel; | 207 | struct pl08x_channel_data memcpy_channel; |
209 | int (*get_signal)(struct pl08x_dma_chan *); | 208 | int (*get_signal)(struct pl08x_dma_chan *); |
210 | void (*put_signal)(struct pl08x_dma_chan *); | 209 | void (*put_signal)(struct pl08x_dma_chan *); |
210 | u8 lli_buses; | ||
211 | u8 mem_buses; | ||
211 | }; | 212 | }; |
212 | 213 | ||
213 | #ifdef CONFIG_AMBA_PL08X | 214 | #ifdef CONFIG_AMBA_PL08X |
diff --git a/include/linux/dmaengine.h b/include/linux/dmaengine.h index 8cd00ad98d37..9bebd7f16ef1 100644 --- a/include/linux/dmaengine.h +++ b/include/linux/dmaengine.h | |||
@@ -532,7 +532,7 @@ static inline int dmaengine_resume(struct dma_chan *chan) | |||
532 | return dmaengine_device_control(chan, DMA_RESUME, 0); | 532 | return dmaengine_device_control(chan, DMA_RESUME, 0); |
533 | } | 533 | } |
534 | 534 | ||
535 | static inline int dmaengine_submit(struct dma_async_tx_descriptor *desc) | 535 | static inline dma_cookie_t dmaengine_submit(struct dma_async_tx_descriptor *desc) |
536 | { | 536 | { |
537 | return desc->tx_submit(desc); | 537 | return desc->tx_submit(desc); |
538 | } | 538 | } |