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-rw-r--r--include/asm-arm/pgalloc.h5
-rw-r--r--include/asm-arm/pgtable-hwdef.h88
-rw-r--r--include/asm-arm/pgtable.h80
-rw-r--r--include/asm-arm/tlb.h9
-rw-r--r--include/asm-arm/tlbflush.h9
5 files changed, 111 insertions, 80 deletions
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
index bc18ff405181..c4ac2e67768d 100644
--- a/include/asm-arm/pgalloc.h
+++ b/include/asm-arm/pgalloc.h
@@ -10,10 +10,15 @@
10#ifndef _ASMARM_PGALLOC_H 10#ifndef _ASMARM_PGALLOC_H
11#define _ASMARM_PGALLOC_H 11#define _ASMARM_PGALLOC_H
12 12
13#include <asm/domain.h>
14#include <asm/pgtable-hwdef.h>
13#include <asm/processor.h> 15#include <asm/processor.h>
14#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
15#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
16 18
19#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
20#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
21
17/* 22/*
18 * Since we have only two-level page tables, these are trivial 23 * Since we have only two-level page tables, these are trivial
19 */ 24 */
diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h
new file mode 100644
index 000000000000..1d033495cc75
--- /dev/null
+++ b/include/asm-arm/pgtable-hwdef.h
@@ -0,0 +1,88 @@
1/*
2 * linux/include/asm-arm/pgtable-hwdef.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_PGTABLE_HWDEF_H
11#define _ASMARM_PGTABLE_HWDEF_H
12
13/*
14 * Hardware page table definitions.
15 *
16 * + Level 1 descriptor (PMD)
17 * - common
18 */
19#define PMD_TYPE_MASK (3 << 0)
20#define PMD_TYPE_FAULT (0 << 0)
21#define PMD_TYPE_TABLE (1 << 0)
22#define PMD_TYPE_SECT (2 << 0)
23#define PMD_BIT4 (1 << 4)
24#define PMD_DOMAIN(x) ((x) << 5)
25#define PMD_PROTECTION (1 << 9) /* v5 */
26/*
27 * - section
28 */
29#define PMD_SECT_BUFFERABLE (1 << 2)
30#define PMD_SECT_CACHEABLE (1 << 3)
31#define PMD_SECT_AP_WRITE (1 << 10)
32#define PMD_SECT_AP_READ (1 << 11)
33#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
34#define PMD_SECT_APX (1 << 15) /* v6 */
35#define PMD_SECT_S (1 << 16) /* v6 */
36#define PMD_SECT_nG (1 << 17) /* v6 */
37#define PMD_SECT_SUPER (1 << 18) /* v6 */
38
39#define PMD_SECT_UNCACHED (0)
40#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
41#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
42#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
43#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
44#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
45#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
46
47/*
48 * - coarse table (not used)
49 */
50
51/*
52 * + Level 2 descriptor (PTE)
53 * - common
54 */
55#define PTE_TYPE_MASK (3 << 0)
56#define PTE_TYPE_FAULT (0 << 0)
57#define PTE_TYPE_LARGE (1 << 0)
58#define PTE_TYPE_SMALL (2 << 0)
59#define PTE_TYPE_EXT (3 << 0) /* v5 */
60#define PTE_BUFFERABLE (1 << 2)
61#define PTE_CACHEABLE (1 << 3)
62
63/*
64 * - extended small page/tiny page
65 */
66#define PTE_EXT_XN (1 << 0) /* v6 */
67#define PTE_EXT_AP_MASK (3 << 4)
68#define PTE_EXT_AP0 (1 << 4)
69#define PTE_EXT_AP1 (2 << 4)
70#define PTE_EXT_AP_UNO_SRO (0 << 4)
71#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
72#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
73#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
74#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
75#define PTE_EXT_APX (1 << 9) /* v6 */
76#define PTE_EXT_SHARED (1 << 10) /* v6 */
77#define PTE_EXT_NG (1 << 11) /* v6 */
78
79/*
80 * - small page
81 */
82#define PTE_SMALL_AP_MASK (0xff << 4)
83#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
84#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
85#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
86#define PTE_SMALL_AP_URW_SRW (0xff << 4)
87
88#endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 70e00d08345e..e595ae24efe2 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -137,81 +137,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
137#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) 137#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
138 138
139/* 139/*
140 * Hardware page table definitions.
141 *
142 * + Level 1 descriptor (PMD)
143 * - common
144 */
145#define PMD_TYPE_MASK (3 << 0)
146#define PMD_TYPE_FAULT (0 << 0)
147#define PMD_TYPE_TABLE (1 << 0)
148#define PMD_TYPE_SECT (2 << 0)
149#define PMD_BIT4 (1 << 4)
150#define PMD_DOMAIN(x) ((x) << 5)
151#define PMD_PROTECTION (1 << 9) /* v5 */
152/*
153 * - section
154 */
155#define PMD_SECT_BUFFERABLE (1 << 2)
156#define PMD_SECT_CACHEABLE (1 << 3)
157#define PMD_SECT_AP_WRITE (1 << 10)
158#define PMD_SECT_AP_READ (1 << 11)
159#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
160#define PMD_SECT_APX (1 << 15) /* v6 */
161#define PMD_SECT_S (1 << 16) /* v6 */
162#define PMD_SECT_nG (1 << 17) /* v6 */
163#define PMD_SECT_SUPER (1 << 18) /* v6 */
164
165#define PMD_SECT_UNCACHED (0)
166#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
167#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
168#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
169#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
170#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
171#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
172
173/*
174 * - coarse table (not used)
175 */
176
177/*
178 * + Level 2 descriptor (PTE)
179 * - common
180 */
181#define PTE_TYPE_MASK (3 << 0)
182#define PTE_TYPE_FAULT (0 << 0)
183#define PTE_TYPE_LARGE (1 << 0)
184#define PTE_TYPE_SMALL (2 << 0)
185#define PTE_TYPE_EXT (3 << 0) /* v5 */
186#define PTE_BUFFERABLE (1 << 2)
187#define PTE_CACHEABLE (1 << 3)
188
189/*
190 * - extended small page/tiny page
191 */
192#define PTE_EXT_XN (1 << 0) /* v6 */
193#define PTE_EXT_AP_MASK (3 << 4)
194#define PTE_EXT_AP0 (1 << 4)
195#define PTE_EXT_AP1 (2 << 4)
196#define PTE_EXT_AP_UNO_SRO (0 << 4)
197#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
198#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
199#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
200#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
201#define PTE_EXT_APX (1 << 9) /* v6 */
202#define PTE_EXT_SHARED (1 << 10) /* v6 */
203#define PTE_EXT_NG (1 << 11) /* v6 */
204
205/*
206 * - small page
207 */
208#define PTE_SMALL_AP_MASK (0xff << 4)
209#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
210#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
211#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
212#define PTE_SMALL_AP_URW_SRW (0xff << 4)
213
214/*
215 * "Linux" PTE definitions. 140 * "Linux" PTE definitions.
216 * 141 *
217 * We keep two sets of PTEs - the hardware and the linux version. 142 * We keep two sets of PTEs - the hardware and the linux version.
@@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
236 161
237#ifndef __ASSEMBLY__ 162#ifndef __ASSEMBLY__
238 163
239#include <asm/domain.h>
240
241#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
242#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
243
244/* 164/*
245 * The following macros handle the cache and bufferable bits... 165 * The following macros handle the cache and bufferable bits...
246 */ 166 */
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index f49bfb78c221..cb740025d413 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -19,6 +19,14 @@
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22
23#ifndef CONFIG_MMU
24
25#include <linux/pagemap.h>
26#include <asm-generic/tlb.h>
27
28#else /* !CONFIG_MMU */
29
22#include <asm/pgalloc.h> 30#include <asm/pgalloc.h>
23 31
24/* 32/*
@@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
82 90
83#define tlb_migrate_finish(mm) do { } while (0) 91#define tlb_migrate_finish(mm) do { } while (0)
84 92
93#endif /* CONFIG_MMU */
85#endif 94#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 0c2acc944a0a..728992451dd1 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -11,6 +11,13 @@
11#define _ASMARM_TLBFLUSH_H 11#define _ASMARM_TLBFLUSH_H
12 12
13#include <linux/config.h> 13#include <linux/config.h>
14
15#ifndef CONFIG_MMU
16
17#define tlb_flush(tlb) ((void) tlb)
18
19#else /* CONFIG_MMU */
20
14#include <asm/glue.h> 21#include <asm/glue.h>
15 22
16#define TLB_V3_PAGE (1 << 0) 23#define TLB_V3_PAGE (1 << 0)
@@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte
423 430
424#endif 431#endif
425 432
433#endif /* CONFIG_MMU */
434
426#endif 435#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-28 05:17:09 -0500