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-rw-r--r--include/linux/i2c/twl.h6
-rw-r--r--include/linux/mfd/davinci_voicecodec.h126
-rw-r--r--include/linux/mfd/wm8350/audio.h2
-rw-r--r--include/linux/mfd/wm8994/core.h53
-rw-r--r--include/linux/mfd/wm8994/pdata.h1
-rw-r--r--include/sound/jack.h8
-rw-r--r--include/sound/soc-dai.h7
-rw-r--r--include/sound/soc-dapm.h5
-rw-r--r--include/sound/soc.h20
-rw-r--r--include/sound/tlv320dac33-plat.h1
-rw-r--r--include/sound/wm8903.h249
-rw-r--r--include/sound/wm8904.h110
-rw-r--r--include/sound/wm8960.h24
13 files changed, 600 insertions, 12 deletions
diff --git a/include/linux/i2c/twl.h b/include/linux/i2c/twl.h
index fb6784e86d5f..ebd90ce58ca2 100644
--- a/include/linux/i2c/twl.h
+++ b/include/linux/i2c/twl.h
@@ -569,9 +569,9 @@ struct twl4030_codec_data {
569 struct twl4030_codec_audio_data *audio; 569 struct twl4030_codec_audio_data *audio;
570 struct twl4030_codec_vibra_data *vibra; 570 struct twl4030_codec_vibra_data *vibra;
571 571
572 /* twl6030 */ 572 /* twl6040 */
573 int audpwron_gpio; /* audio power-on gpio */ 573 int audpwron_gpio; /* audio power-on gpio */
574 int naudint_irq; /* audio interrupt */ 574 int naudint_irq; /* audio interrupt */
575}; 575};
576 576
577struct twl4030_platform_data { 577struct twl4030_platform_data {
diff --git a/include/linux/mfd/davinci_voicecodec.h b/include/linux/mfd/davinci_voicecodec.h
new file mode 100644
index 000000000000..0ab61320ffa8
--- /dev/null
+++ b/include/linux/mfd/davinci_voicecodec.h
@@ -0,0 +1,126 @@
1/*
2 * DaVinci Voice Codec Core Interface for TI platforms
3 *
4 * Copyright (C) 2010 Texas Instruments, Inc
5 *
6 * Author: Miguel Aguilar <miguel.aguilar@ridgerun.com>
7 *
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License as published by
10 * the Free Software Foundation; either version 2 of the License, or
11 * (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21 */
22
23#ifndef __LINUX_MFD_DAVINCI_VOICECODEC_H_
24#define __LINUX_MFD_DAVINIC_VOICECODEC_H_
25
26#include <linux/kernel.h>
27#include <linux/platform_device.h>
28#include <linux/mfd/core.h>
29
30#include <mach/edma.h>
31
32/*
33 * Register values.
34 */
35#define DAVINCI_VC_PID 0x00
36#define DAVINCI_VC_CTRL 0x04
37#define DAVINCI_VC_INTEN 0x08
38#define DAVINCI_VC_INTSTATUS 0x0c
39#define DAVINCI_VC_INTCLR 0x10
40#define DAVINCI_VC_EMUL_CTRL 0x14
41#define DAVINCI_VC_RFIFO 0x20
42#define DAVINCI_VC_WFIFO 0x24
43#define DAVINCI_VC_FIFOSTAT 0x28
44#define DAVINCI_VC_TST_CTRL 0x2C
45#define DAVINCI_VC_REG05 0x94
46#define DAVINCI_VC_REG09 0xA4
47#define DAVINCI_VC_REG12 0xB0
48
49/* DAVINCI_VC_CTRL bit fields */
50#define DAVINCI_VC_CTRL_MASK 0x5500
51#define DAVINCI_VC_CTRL_RSTADC BIT(0)
52#define DAVINCI_VC_CTRL_RSTDAC BIT(1)
53#define DAVINCI_VC_CTRL_RD_BITS_8 BIT(4)
54#define DAVINCI_VC_CTRL_RD_UNSIGNED BIT(5)
55#define DAVINCI_VC_CTRL_WD_BITS_8 BIT(6)
56#define DAVINCI_VC_CTRL_WD_UNSIGNED BIT(7)
57#define DAVINCI_VC_CTRL_RFIFOEN BIT(8)
58#define DAVINCI_VC_CTRL_RFIFOCL BIT(9)
59#define DAVINCI_VC_CTRL_RFIFOMD_WORD_1 BIT(10)
60#define DAVINCI_VC_CTRL_WFIFOEN BIT(12)
61#define DAVINCI_VC_CTRL_WFIFOCL BIT(13)
62#define DAVINCI_VC_CTRL_WFIFOMD_WORD_1 BIT(14)
63
64/* DAVINCI_VC_INT bit fields */
65#define DAVINCI_VC_INT_MASK 0x3F
66#define DAVINCI_VC_INT_RDRDY_MASK BIT(0)
67#define DAVINCI_VC_INT_RERROVF_MASK BIT(1)
68#define DAVINCI_VC_INT_RERRUDR_MASK BIT(2)
69#define DAVINCI_VC_INT_WDREQ_MASK BIT(3)
70#define DAVINCI_VC_INT_WERROVF_MASKBIT BIT(4)
71#define DAVINCI_VC_INT_WERRUDR_MASK BIT(5)
72
73/* DAVINCI_VC_REG05 bit fields */
74#define DAVINCI_VC_REG05_PGA_GAIN 0x07
75
76/* DAVINCI_VC_REG09 bit fields */
77#define DAVINCI_VC_REG09_MUTE 0x40
78#define DAVINCI_VC_REG09_DIG_ATTEN 0x3F
79
80/* DAVINCI_VC_REG12 bit fields */
81#define DAVINCI_VC_REG12_POWER_ALL_ON 0xFD
82#define DAVINCI_VC_REG12_POWER_ALL_OFF 0x00
83
84#define DAVINCI_VC_CELLS 2
85
86enum davinci_vc_cells {
87 DAVINCI_VC_VCIF_CELL,
88 DAVINCI_VC_CQ93VC_CELL,
89};
90
91struct davinci_vcif {
92 struct platform_device *pdev;
93 u32 dma_tx_channel;
94 u32 dma_rx_channel;
95 dma_addr_t dma_tx_addr;
96 dma_addr_t dma_rx_addr;
97};
98
99struct cq93vc {
100 struct platform_device *pdev;
101 struct snd_soc_codec *codec;
102 u32 sysclk;
103};
104
105struct davinci_vc;
106
107struct davinci_vc {
108 /* Device data */
109 struct device *dev;
110 struct platform_device *pdev;
111 struct clk *clk;
112
113 /* Memory resources */
114 void __iomem *base;
115 resource_size_t pbase;
116 size_t base_size;
117
118 /* MFD cells */
119 struct mfd_cell cells[DAVINCI_VC_CELLS];
120
121 /* Client devices */
122 struct davinci_vcif davinci_vcif;
123 struct cq93vc cq93vc;
124};
125
126#endif
diff --git a/include/linux/mfd/wm8350/audio.h b/include/linux/mfd/wm8350/audio.h
index d899dc0223ba..a95141eafce3 100644
--- a/include/linux/mfd/wm8350/audio.h
+++ b/include/linux/mfd/wm8350/audio.h
@@ -492,6 +492,8 @@
492 */ 492 */
493#define WM8350_JACK_L_LVL 0x0800 493#define WM8350_JACK_L_LVL 0x0800
494#define WM8350_JACK_R_LVL 0x0400 494#define WM8350_JACK_R_LVL 0x0400
495#define WM8350_JACK_MICSCD_LVL 0x0200
496#define WM8350_JACK_MICSD_LVL 0x0100
495 497
496/* 498/*
497 * WM8350 Platform setup 499 * WM8350 Platform setup
diff --git a/include/linux/mfd/wm8994/core.h b/include/linux/mfd/wm8994/core.h
index b06ff2846748..de79baee4925 100644
--- a/include/linux/mfd/wm8994/core.h
+++ b/include/linux/mfd/wm8994/core.h
@@ -15,14 +15,38 @@
15#ifndef __MFD_WM8994_CORE_H__ 15#ifndef __MFD_WM8994_CORE_H__
16#define __MFD_WM8994_CORE_H__ 16#define __MFD_WM8994_CORE_H__
17 17
18#include <linux/interrupt.h>
19
18struct regulator_dev; 20struct regulator_dev;
19struct regulator_bulk_data; 21struct regulator_bulk_data;
20 22
21#define WM8994_NUM_GPIO_REGS 11 23#define WM8994_NUM_GPIO_REGS 11
22#define WM8994_NUM_LDO_REGS 2 24#define WM8994_NUM_LDO_REGS 2
25#define WM8994_NUM_IRQ_REGS 2
26
27#define WM8994_IRQ_TEMP_SHUT 0
28#define WM8994_IRQ_MIC1_DET 1
29#define WM8994_IRQ_MIC1_SHRT 2
30#define WM8994_IRQ_MIC2_DET 3
31#define WM8994_IRQ_MIC2_SHRT 4
32#define WM8994_IRQ_FLL1_LOCK 5
33#define WM8994_IRQ_FLL2_LOCK 6
34#define WM8994_IRQ_SRC1_LOCK 7
35#define WM8994_IRQ_SRC2_LOCK 8
36#define WM8994_IRQ_AIF1DRC1_SIG_DET 9
37#define WM8994_IRQ_AIF1DRC2_SIG_DET 10
38#define WM8994_IRQ_AIF2DRC_SIG_DET 11
39#define WM8994_IRQ_FIFOS_ERR 12
40#define WM8994_IRQ_WSEQ_DONE 13
41#define WM8994_IRQ_DCS_DONE 14
42#define WM8994_IRQ_TEMP_WARN 15
43
44/* GPIOs in the chip are numbered from 1-11 */
45#define WM8994_IRQ_GPIO(x) (x + WM8994_IRQ_TEMP_WARN)
23 46
24struct wm8994 { 47struct wm8994 {
25 struct mutex io_lock; 48 struct mutex io_lock;
49 struct mutex irq_lock;
26 50
27 struct device *dev; 51 struct device *dev;
28 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg, 52 int (*read_dev)(struct wm8994 *wm8994, unsigned short reg,
@@ -33,6 +57,11 @@ struct wm8994 {
33 void *control_data; 57 void *control_data;
34 58
35 int gpio_base; 59 int gpio_base;
60 int irq_base;
61
62 int irq;
63 u16 irq_masks_cur[WM8994_NUM_IRQ_REGS];
64 u16 irq_masks_cache[WM8994_NUM_IRQ_REGS];
36 65
37 /* Used over suspend/resume */ 66 /* Used over suspend/resume */
38 u16 ldo_regs[WM8994_NUM_LDO_REGS]; 67 u16 ldo_regs[WM8994_NUM_LDO_REGS];
@@ -51,4 +80,26 @@ int wm8994_set_bits(struct wm8994 *wm8994, unsigned short reg,
51int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg, 80int wm8994_bulk_read(struct wm8994 *wm8994, unsigned short reg,
52 int count, u16 *buf); 81 int count, u16 *buf);
53 82
83
84/* Helper to save on boilerplate */
85static inline int wm8994_request_irq(struct wm8994 *wm8994, int irq,
86 irq_handler_t handler, const char *name,
87 void *data)
88{
89 if (!wm8994->irq_base)
90 return -EINVAL;
91 return request_threaded_irq(wm8994->irq_base + irq, NULL, handler,
92 IRQF_TRIGGER_RISING, name,
93 data);
94}
95static inline void wm8994_free_irq(struct wm8994 *wm8994, int irq, void *data)
96{
97 if (!wm8994->irq_base)
98 return;
99 free_irq(wm8994->irq_base + irq, data);
100}
101
102int wm8994_irq_init(struct wm8994 *wm8994);
103void wm8994_irq_exit(struct wm8994 *wm8994);
104
54#endif 105#endif
diff --git a/include/linux/mfd/wm8994/pdata.h b/include/linux/mfd/wm8994/pdata.h
index 70d6a8687dc5..5c51f367c061 100644
--- a/include/linux/mfd/wm8994/pdata.h
+++ b/include/linux/mfd/wm8994/pdata.h
@@ -70,6 +70,7 @@ struct wm8994_pdata {
70 70
71 struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO]; 71 struct wm8994_ldo_pdata ldo[WM8994_NUM_LDO];
72 72
73 int irq_base; /** Base IRQ number for WM8994, required for IRQs */
73 74
74 int num_drc_cfgs; 75 int num_drc_cfgs;
75 struct wm8994_drc_cfg *drc_cfgs; 76 struct wm8994_drc_cfg *drc_cfgs;
diff --git a/include/sound/jack.h b/include/sound/jack.h
index f236e426a706..d90b9fa32707 100644
--- a/include/sound/jack.h
+++ b/include/sound/jack.h
@@ -42,6 +42,11 @@ enum snd_jack_types {
42 SND_JACK_MECHANICAL = 0x0008, /* If detected separately */ 42 SND_JACK_MECHANICAL = 0x0008, /* If detected separately */
43 SND_JACK_VIDEOOUT = 0x0010, 43 SND_JACK_VIDEOOUT = 0x0010,
44 SND_JACK_AVOUT = SND_JACK_LINEOUT | SND_JACK_VIDEOOUT, 44 SND_JACK_AVOUT = SND_JACK_LINEOUT | SND_JACK_VIDEOOUT,
45
46 /* Kept separate from switches to facilitate implementation */
47 SND_JACK_BTN_0 = 0x4000,
48 SND_JACK_BTN_1 = 0x2000,
49 SND_JACK_BTN_2 = 0x1000,
45}; 50};
46 51
47struct snd_jack { 52struct snd_jack {
@@ -50,6 +55,7 @@ struct snd_jack {
50 int type; 55 int type;
51 const char *id; 56 const char *id;
52 char name[100]; 57 char name[100];
58 unsigned int key[3]; /* Keep in sync with definitions above */
53 void *private_data; 59 void *private_data;
54 void (*private_free)(struct snd_jack *); 60 void (*private_free)(struct snd_jack *);
55}; 61};
@@ -59,6 +65,8 @@ struct snd_jack {
59int snd_jack_new(struct snd_card *card, const char *id, int type, 65int snd_jack_new(struct snd_card *card, const char *id, int type,
60 struct snd_jack **jack); 66 struct snd_jack **jack);
61void snd_jack_set_parent(struct snd_jack *jack, struct device *parent); 67void snd_jack_set_parent(struct snd_jack *jack, struct device *parent);
68int snd_jack_set_key(struct snd_jack *jack, enum snd_jack_types type,
69 int keytype);
62 70
63void snd_jack_report(struct snd_jack *jack, int status); 71void snd_jack_report(struct snd_jack *jack, int status);
64 72
diff --git a/include/sound/soc-dai.h b/include/sound/soc-dai.h
index 0a0b019d41ad..377693a14385 100644
--- a/include/sound/soc-dai.h
+++ b/include/sound/soc-dai.h
@@ -182,6 +182,12 @@ struct snd_soc_dai_ops {
182 struct snd_soc_dai *); 182 struct snd_soc_dai *);
183 int (*trigger)(struct snd_pcm_substream *, int, 183 int (*trigger)(struct snd_pcm_substream *, int,
184 struct snd_soc_dai *); 184 struct snd_soc_dai *);
185 /*
186 * For hardware based FIFO caused delay reporting.
187 * Optional.
188 */
189 snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *,
190 struct snd_soc_dai *);
185}; 191};
186 192
187/* 193/*
@@ -215,7 +221,6 @@ struct snd_soc_dai {
215 unsigned int symmetric_rates:1; 221 unsigned int symmetric_rates:1;
216 222
217 /* DAI runtime info */ 223 /* DAI runtime info */
218 struct snd_pcm_runtime *runtime;
219 struct snd_soc_codec *codec; 224 struct snd_soc_codec *codec;
220 unsigned int active; 225 unsigned int active;
221 unsigned char pop_wait:1; 226 unsigned char pop_wait:1;
diff --git a/include/sound/soc-dapm.h b/include/sound/soc-dapm.h
index c0922a034223..d5d6ba862dfe 100644
--- a/include/sound/soc-dapm.h
+++ b/include/sound/soc-dapm.h
@@ -339,6 +339,8 @@ int snd_soc_dapm_disable_pin(struct snd_soc_codec *codec, const char *pin);
339int snd_soc_dapm_nc_pin(struct snd_soc_codec *codec, const char *pin); 339int snd_soc_dapm_nc_pin(struct snd_soc_codec *codec, const char *pin);
340int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, const char *pin); 340int snd_soc_dapm_get_pin_status(struct snd_soc_codec *codec, const char *pin);
341int snd_soc_dapm_sync(struct snd_soc_codec *codec); 341int snd_soc_dapm_sync(struct snd_soc_codec *codec);
342int snd_soc_dapm_force_enable_pin(struct snd_soc_codec *codec,
343 const char *pin);
342 344
343/* dapm widget types */ 345/* dapm widget types */
344enum snd_soc_dapm_type { 346enum snd_soc_dapm_type {
@@ -425,9 +427,8 @@ struct snd_soc_dapm_widget {
425 unsigned char connected:1; /* connected codec pin */ 427 unsigned char connected:1; /* connected codec pin */
426 unsigned char new:1; /* cnew complete */ 428 unsigned char new:1; /* cnew complete */
427 unsigned char ext:1; /* has external widgets */ 429 unsigned char ext:1; /* has external widgets */
428 unsigned char muted:1; /* muted for pop reduction */
429 unsigned char suspend:1; /* was active before suspend */ 430 unsigned char suspend:1; /* was active before suspend */
430 unsigned char pmdown:1; /* waiting for timeout */ 431 unsigned char force:1; /* force state */
431 432
432 int (*power_check)(struct snd_soc_dapm_widget *w); 433 int (*power_check)(struct snd_soc_dapm_widget *w);
433 434
diff --git a/include/sound/soc.h b/include/sound/soc.h
index a57fbfcd4c8f..4ab3dad4a9c9 100644
--- a/include/sound/soc.h
+++ b/include/sound/soc.h
@@ -15,6 +15,7 @@
15 15
16#include <linux/platform_device.h> 16#include <linux/platform_device.h>
17#include <linux/types.h> 17#include <linux/types.h>
18#include <linux/notifier.h>
18#include <linux/workqueue.h> 19#include <linux/workqueue.h>
19#include <linux/interrupt.h> 20#include <linux/interrupt.h>
20#include <linux/kernel.h> 21#include <linux/kernel.h>
@@ -212,6 +213,7 @@ struct snd_soc_dai_mode;
212struct snd_soc_pcm_runtime; 213struct snd_soc_pcm_runtime;
213struct snd_soc_dai; 214struct snd_soc_dai;
214struct snd_soc_platform; 215struct snd_soc_platform;
216struct snd_soc_dai_link;
215struct snd_soc_codec; 217struct snd_soc_codec;
216struct soc_enum; 218struct soc_enum;
217struct snd_soc_ac97_ops; 219struct snd_soc_ac97_ops;
@@ -260,6 +262,10 @@ int snd_soc_jack_new(struct snd_soc_card *card, const char *id, int type,
260void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask); 262void snd_soc_jack_report(struct snd_soc_jack *jack, int status, int mask);
261int snd_soc_jack_add_pins(struct snd_soc_jack *jack, int count, 263int snd_soc_jack_add_pins(struct snd_soc_jack *jack, int count,
262 struct snd_soc_jack_pin *pins); 264 struct snd_soc_jack_pin *pins);
265void snd_soc_jack_notifier_register(struct snd_soc_jack *jack,
266 struct notifier_block *nb);
267void snd_soc_jack_notifier_unregister(struct snd_soc_jack *jack,
268 struct notifier_block *nb);
263#ifdef CONFIG_GPIOLIB 269#ifdef CONFIG_GPIOLIB
264int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count, 270int snd_soc_jack_add_gpios(struct snd_soc_jack *jack, int count,
265 struct snd_soc_jack_gpio *gpios); 271 struct snd_soc_jack_gpio *gpios);
@@ -363,6 +369,7 @@ struct snd_soc_jack {
363 struct snd_soc_card *card; 369 struct snd_soc_card *card;
364 struct list_head pins; 370 struct list_head pins;
365 int status; 371 int status;
372 struct blocking_notifier_head notifier;
366}; 373};
367 374
368/* SoC PCM stream information */ 375/* SoC PCM stream information */
@@ -374,7 +381,7 @@ struct snd_soc_pcm_stream {
374 unsigned int rate_max; /* max rate */ 381 unsigned int rate_max; /* max rate */
375 unsigned int channels_min; /* min channels */ 382 unsigned int channels_min; /* min channels */
376 unsigned int channels_max; /* max channels */ 383 unsigned int channels_max; /* max channels */
377 unsigned int active:1; /* stream is in use */ 384 unsigned int active; /* stream is in use */
378 void *dma_data; /* used by platform code */ 385 void *dma_data; /* used by platform code */
379}; 386};
380 387
@@ -462,14 +469,21 @@ struct snd_soc_platform {
462 469
463 int (*probe)(struct platform_device *pdev); 470 int (*probe)(struct platform_device *pdev);
464 int (*remove)(struct platform_device *pdev); 471 int (*remove)(struct platform_device *pdev);
465 int (*suspend)(struct snd_soc_dai *dai); 472 int (*suspend)(struct snd_soc_dai_link *dai_link);
466 int (*resume)(struct snd_soc_dai *dai); 473 int (*resume)(struct snd_soc_dai_link *dai_link);
467 474
468 /* pcm creation and destruction */ 475 /* pcm creation and destruction */
469 int (*pcm_new)(struct snd_card *, struct snd_soc_dai *, 476 int (*pcm_new)(struct snd_card *, struct snd_soc_dai *,
470 struct snd_pcm *); 477 struct snd_pcm *);
471 void (*pcm_free)(struct snd_pcm *); 478 void (*pcm_free)(struct snd_pcm *);
472 479
480 /*
481 * For platform caused delay reporting.
482 * Optional.
483 */
484 snd_pcm_sframes_t (*delay)(struct snd_pcm_substream *,
485 struct snd_soc_dai *);
486
473 /* platform stream ops */ 487 /* platform stream ops */
474 struct snd_pcm_ops *pcm_ops; 488 struct snd_pcm_ops *pcm_ops;
475}; 489};
diff --git a/include/sound/tlv320dac33-plat.h b/include/sound/tlv320dac33-plat.h
index ac0665264bdf..3f428d53195b 100644
--- a/include/sound/tlv320dac33-plat.h
+++ b/include/sound/tlv320dac33-plat.h
@@ -15,6 +15,7 @@
15 15
16struct tlv320dac33_platform_data { 16struct tlv320dac33_platform_data {
17 int power_gpio; 17 int power_gpio;
18 int keep_bclk; /* Keep the BCLK running in FIFO modes */
18 u8 burst_bclkdiv; 19 u8 burst_bclkdiv;
19}; 20};
20 21
diff --git a/include/sound/wm8903.h b/include/sound/wm8903.h
new file mode 100644
index 000000000000..b4a0db2307ef
--- /dev/null
+++ b/include/sound/wm8903.h
@@ -0,0 +1,249 @@
1/*
2 * linux/sound/wm8903.h -- Platform data for WM8903
3 *
4 * Copyright 2010 Wolfson Microelectronics. PLC.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10
11#ifndef __LINUX_SND_WM8903_H
12#define __LINUX_SND_WM8903_H
13
14/* Used to enable configuration of a GPIO to all zeros */
15#define WM8903_GPIO_NO_CONFIG 0x8000
16
17/*
18 * R6 (0x06) - Mic Bias Control 0
19 */
20#define WM8903_MICDET_HYST_ENA 0x0080 /* MICDET_HYST_ENA */
21#define WM8903_MICDET_HYST_ENA_MASK 0x0080 /* MICDET_HYST_ENA */
22#define WM8903_MICDET_HYST_ENA_SHIFT 7 /* MICDET_HYST_ENA */
23#define WM8903_MICDET_HYST_ENA_WIDTH 1 /* MICDET_HYST_ENA */
24#define WM8903_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
25#define WM8903_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
26#define WM8903_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
27#define WM8903_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
28#define WM8903_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
29#define WM8903_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
30#define WM8903_MICDET_ENA 0x0002 /* MICDET_ENA */
31#define WM8903_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
32#define WM8903_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
33#define WM8903_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
34#define WM8903_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
35#define WM8903_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
36#define WM8903_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
37#define WM8903_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
38
39/*
40 * R116 (0x74) - GPIO Control 1
41 */
42#define WM8903_GP1_FN_MASK 0x1F00 /* GP1_FN - [12:8] */
43#define WM8903_GP1_FN_SHIFT 8 /* GP1_FN - [12:8] */
44#define WM8903_GP1_FN_WIDTH 5 /* GP1_FN - [12:8] */
45#define WM8903_GP1_DIR 0x0080 /* GP1_DIR */
46#define WM8903_GP1_DIR_MASK 0x0080 /* GP1_DIR */
47#define WM8903_GP1_DIR_SHIFT 7 /* GP1_DIR */
48#define WM8903_GP1_DIR_WIDTH 1 /* GP1_DIR */
49#define WM8903_GP1_OP_CFG 0x0040 /* GP1_OP_CFG */
50#define WM8903_GP1_OP_CFG_MASK 0x0040 /* GP1_OP_CFG */
51#define WM8903_GP1_OP_CFG_SHIFT 6 /* GP1_OP_CFG */
52#define WM8903_GP1_OP_CFG_WIDTH 1 /* GP1_OP_CFG */
53#define WM8903_GP1_IP_CFG 0x0020 /* GP1_IP_CFG */
54#define WM8903_GP1_IP_CFG_MASK 0x0020 /* GP1_IP_CFG */
55#define WM8903_GP1_IP_CFG_SHIFT 5 /* GP1_IP_CFG */
56#define WM8903_GP1_IP_CFG_WIDTH 1 /* GP1_IP_CFG */
57#define WM8903_GP1_LVL 0x0010 /* GP1_LVL */
58#define WM8903_GP1_LVL_MASK 0x0010 /* GP1_LVL */
59#define WM8903_GP1_LVL_SHIFT 4 /* GP1_LVL */
60#define WM8903_GP1_LVL_WIDTH 1 /* GP1_LVL */
61#define WM8903_GP1_PD 0x0008 /* GP1_PD */
62#define WM8903_GP1_PD_MASK 0x0008 /* GP1_PD */
63#define WM8903_GP1_PD_SHIFT 3 /* GP1_PD */
64#define WM8903_GP1_PD_WIDTH 1 /* GP1_PD */
65#define WM8903_GP1_PU 0x0004 /* GP1_PU */
66#define WM8903_GP1_PU_MASK 0x0004 /* GP1_PU */
67#define WM8903_GP1_PU_SHIFT 2 /* GP1_PU */
68#define WM8903_GP1_PU_WIDTH 1 /* GP1_PU */
69#define WM8903_GP1_INTMODE 0x0002 /* GP1_INTMODE */
70#define WM8903_GP1_INTMODE_MASK 0x0002 /* GP1_INTMODE */
71#define WM8903_GP1_INTMODE_SHIFT 1 /* GP1_INTMODE */
72#define WM8903_GP1_INTMODE_WIDTH 1 /* GP1_INTMODE */
73#define WM8903_GP1_DB 0x0001 /* GP1_DB */
74#define WM8903_GP1_DB_MASK 0x0001 /* GP1_DB */
75#define WM8903_GP1_DB_SHIFT 0 /* GP1_DB */
76#define WM8903_GP1_DB_WIDTH 1 /* GP1_DB */
77
78/*
79 * R117 (0x75) - GPIO Control 2
80 */
81#define WM8903_GP2_FN_MASK 0x1F00 /* GP2_FN - [12:8] */
82#define WM8903_GP2_FN_SHIFT 8 /* GP2_FN - [12:8] */
83#define WM8903_GP2_FN_WIDTH 5 /* GP2_FN - [12:8] */
84#define WM8903_GP2_DIR 0x0080 /* GP2_DIR */
85#define WM8903_GP2_DIR_MASK 0x0080 /* GP2_DIR */
86#define WM8903_GP2_DIR_SHIFT 7 /* GP2_DIR */
87#define WM8903_GP2_DIR_WIDTH 1 /* GP2_DIR */
88#define WM8903_GP2_OP_CFG 0x0040 /* GP2_OP_CFG */
89#define WM8903_GP2_OP_CFG_MASK 0x0040 /* GP2_OP_CFG */
90#define WM8903_GP2_OP_CFG_SHIFT 6 /* GP2_OP_CFG */
91#define WM8903_GP2_OP_CFG_WIDTH 1 /* GP2_OP_CFG */
92#define WM8903_GP2_IP_CFG 0x0020 /* GP2_IP_CFG */
93#define WM8903_GP2_IP_CFG_MASK 0x0020 /* GP2_IP_CFG */
94#define WM8903_GP2_IP_CFG_SHIFT 5 /* GP2_IP_CFG */
95#define WM8903_GP2_IP_CFG_WIDTH 1 /* GP2_IP_CFG */
96#define WM8903_GP2_LVL 0x0010 /* GP2_LVL */
97#define WM8903_GP2_LVL_MASK 0x0010 /* GP2_LVL */
98#define WM8903_GP2_LVL_SHIFT 4 /* GP2_LVL */
99#define WM8903_GP2_LVL_WIDTH 1 /* GP2_LVL */
100#define WM8903_GP2_PD 0x0008 /* GP2_PD */
101#define WM8903_GP2_PD_MASK 0x0008 /* GP2_PD */
102#define WM8903_GP2_PD_SHIFT 3 /* GP2_PD */
103#define WM8903_GP2_PD_WIDTH 1 /* GP2_PD */
104#define WM8903_GP2_PU 0x0004 /* GP2_PU */
105#define WM8903_GP2_PU_MASK 0x0004 /* GP2_PU */
106#define WM8903_GP2_PU_SHIFT 2 /* GP2_PU */
107#define WM8903_GP2_PU_WIDTH 1 /* GP2_PU */
108#define WM8903_GP2_INTMODE 0x0002 /* GP2_INTMODE */
109#define WM8903_GP2_INTMODE_MASK 0x0002 /* GP2_INTMODE */
110#define WM8903_GP2_INTMODE_SHIFT 1 /* GP2_INTMODE */
111#define WM8903_GP2_INTMODE_WIDTH 1 /* GP2_INTMODE */
112#define WM8903_GP2_DB 0x0001 /* GP2_DB */
113#define WM8903_GP2_DB_MASK 0x0001 /* GP2_DB */
114#define WM8903_GP2_DB_SHIFT 0 /* GP2_DB */
115#define WM8903_GP2_DB_WIDTH 1 /* GP2_DB */
116
117/*
118 * R118 (0x76) - GPIO Control 3
119 */
120#define WM8903_GP3_FN_MASK 0x1F00 /* GP3_FN - [12:8] */
121#define WM8903_GP3_FN_SHIFT 8 /* GP3_FN - [12:8] */
122#define WM8903_GP3_FN_WIDTH 5 /* GP3_FN - [12:8] */
123#define WM8903_GP3_DIR 0x0080 /* GP3_DIR */
124#define WM8903_GP3_DIR_MASK 0x0080 /* GP3_DIR */
125#define WM8903_GP3_DIR_SHIFT 7 /* GP3_DIR */
126#define WM8903_GP3_DIR_WIDTH 1 /* GP3_DIR */
127#define WM8903_GP3_OP_CFG 0x0040 /* GP3_OP_CFG */
128#define WM8903_GP3_OP_CFG_MASK 0x0040 /* GP3_OP_CFG */
129#define WM8903_GP3_OP_CFG_SHIFT 6 /* GP3_OP_CFG */
130#define WM8903_GP3_OP_CFG_WIDTH 1 /* GP3_OP_CFG */
131#define WM8903_GP3_IP_CFG 0x0020 /* GP3_IP_CFG */
132#define WM8903_GP3_IP_CFG_MASK 0x0020 /* GP3_IP_CFG */
133#define WM8903_GP3_IP_CFG_SHIFT 5 /* GP3_IP_CFG */
134#define WM8903_GP3_IP_CFG_WIDTH 1 /* GP3_IP_CFG */
135#define WM8903_GP3_LVL 0x0010 /* GP3_LVL */
136#define WM8903_GP3_LVL_MASK 0x0010 /* GP3_LVL */
137#define WM8903_GP3_LVL_SHIFT 4 /* GP3_LVL */
138#define WM8903_GP3_LVL_WIDTH 1 /* GP3_LVL */
139#define WM8903_GP3_PD 0x0008 /* GP3_PD */
140#define WM8903_GP3_PD_MASK 0x0008 /* GP3_PD */
141#define WM8903_GP3_PD_SHIFT 3 /* GP3_PD */
142#define WM8903_GP3_PD_WIDTH 1 /* GP3_PD */
143#define WM8903_GP3_PU 0x0004 /* GP3_PU */
144#define WM8903_GP3_PU_MASK 0x0004 /* GP3_PU */
145#define WM8903_GP3_PU_SHIFT 2 /* GP3_PU */
146#define WM8903_GP3_PU_WIDTH 1 /* GP3_PU */
147#define WM8903_GP3_INTMODE 0x0002 /* GP3_INTMODE */
148#define WM8903_GP3_INTMODE_MASK 0x0002 /* GP3_INTMODE */
149#define WM8903_GP3_INTMODE_SHIFT 1 /* GP3_INTMODE */
150#define WM8903_GP3_INTMODE_WIDTH 1 /* GP3_INTMODE */
151#define WM8903_GP3_DB 0x0001 /* GP3_DB */
152#define WM8903_GP3_DB_MASK 0x0001 /* GP3_DB */
153#define WM8903_GP3_DB_SHIFT 0 /* GP3_DB */
154#define WM8903_GP3_DB_WIDTH 1 /* GP3_DB */
155
156/*
157 * R119 (0x77) - GPIO Control 4
158 */
159#define WM8903_GP4_FN_MASK 0x1F00 /* GP4_FN - [12:8] */
160#define WM8903_GP4_FN_SHIFT 8 /* GP4_FN - [12:8] */
161#define WM8903_GP4_FN_WIDTH 5 /* GP4_FN - [12:8] */
162#define WM8903_GP4_DIR 0x0080 /* GP4_DIR */
163#define WM8903_GP4_DIR_MASK 0x0080 /* GP4_DIR */
164#define WM8903_GP4_DIR_SHIFT 7 /* GP4_DIR */
165#define WM8903_GP4_DIR_WIDTH 1 /* GP4_DIR */
166#define WM8903_GP4_OP_CFG 0x0040 /* GP4_OP_CFG */
167#define WM8903_GP4_OP_CFG_MASK 0x0040 /* GP4_OP_CFG */
168#define WM8903_GP4_OP_CFG_SHIFT 6 /* GP4_OP_CFG */
169#define WM8903_GP4_OP_CFG_WIDTH 1 /* GP4_OP_CFG */
170#define WM8903_GP4_IP_CFG 0x0020 /* GP4_IP_CFG */
171#define WM8903_GP4_IP_CFG_MASK 0x0020 /* GP4_IP_CFG */
172#define WM8903_GP4_IP_CFG_SHIFT 5 /* GP4_IP_CFG */
173#define WM8903_GP4_IP_CFG_WIDTH 1 /* GP4_IP_CFG */
174#define WM8903_GP4_LVL 0x0010 /* GP4_LVL */
175#define WM8903_GP4_LVL_MASK 0x0010 /* GP4_LVL */
176#define WM8903_GP4_LVL_SHIFT 4 /* GP4_LVL */
177#define WM8903_GP4_LVL_WIDTH 1 /* GP4_LVL */
178#define WM8903_GP4_PD 0x0008 /* GP4_PD */
179#define WM8903_GP4_PD_MASK 0x0008 /* GP4_PD */
180#define WM8903_GP4_PD_SHIFT 3 /* GP4_PD */
181#define WM8903_GP4_PD_WIDTH 1 /* GP4_PD */
182#define WM8903_GP4_PU 0x0004 /* GP4_PU */
183#define WM8903_GP4_PU_MASK 0x0004 /* GP4_PU */
184#define WM8903_GP4_PU_SHIFT 2 /* GP4_PU */
185#define WM8903_GP4_PU_WIDTH 1 /* GP4_PU */
186#define WM8903_GP4_INTMODE 0x0002 /* GP4_INTMODE */
187#define WM8903_GP4_INTMODE_MASK 0x0002 /* GP4_INTMODE */
188#define WM8903_GP4_INTMODE_SHIFT 1 /* GP4_INTMODE */
189#define WM8903_GP4_INTMODE_WIDTH 1 /* GP4_INTMODE */
190#define WM8903_GP4_DB 0x0001 /* GP4_DB */
191#define WM8903_GP4_DB_MASK 0x0001 /* GP4_DB */
192#define WM8903_GP4_DB_SHIFT 0 /* GP4_DB */
193#define WM8903_GP4_DB_WIDTH 1 /* GP4_DB */
194
195/*
196 * R120 (0x78) - GPIO Control 5
197 */
198#define WM8903_GP5_FN_MASK 0x1F00 /* GP5_FN - [12:8] */
199#define WM8903_GP5_FN_SHIFT 8 /* GP5_FN - [12:8] */
200#define WM8903_GP5_FN_WIDTH 5 /* GP5_FN - [12:8] */
201#define WM8903_GP5_DIR 0x0080 /* GP5_DIR */
202#define WM8903_GP5_DIR_MASK 0x0080 /* GP5_DIR */
203#define WM8903_GP5_DIR_SHIFT 7 /* GP5_DIR */
204#define WM8903_GP5_DIR_WIDTH 1 /* GP5_DIR */
205#define WM8903_GP5_OP_CFG 0x0040 /* GP5_OP_CFG */
206#define WM8903_GP5_OP_CFG_MASK 0x0040 /* GP5_OP_CFG */
207#define WM8903_GP5_OP_CFG_SHIFT 6 /* GP5_OP_CFG */
208#define WM8903_GP5_OP_CFG_WIDTH 1 /* GP5_OP_CFG */
209#define WM8903_GP5_IP_CFG 0x0020 /* GP5_IP_CFG */
210#define WM8903_GP5_IP_CFG_MASK 0x0020 /* GP5_IP_CFG */
211#define WM8903_GP5_IP_CFG_SHIFT 5 /* GP5_IP_CFG */
212#define WM8903_GP5_IP_CFG_WIDTH 1 /* GP5_IP_CFG */
213#define WM8903_GP5_LVL 0x0010 /* GP5_LVL */
214#define WM8903_GP5_LVL_MASK 0x0010 /* GP5_LVL */
215#define WM8903_GP5_LVL_SHIFT 4 /* GP5_LVL */
216#define WM8903_GP5_LVL_WIDTH 1 /* GP5_LVL */
217#define WM8903_GP5_PD 0x0008 /* GP5_PD */
218#define WM8903_GP5_PD_MASK 0x0008 /* GP5_PD */
219#define WM8903_GP5_PD_SHIFT 3 /* GP5_PD */
220#define WM8903_GP5_PD_WIDTH 1 /* GP5_PD */
221#define WM8903_GP5_PU 0x0004 /* GP5_PU */
222#define WM8903_GP5_PU_MASK 0x0004 /* GP5_PU */
223#define WM8903_GP5_PU_SHIFT 2 /* GP5_PU */
224#define WM8903_GP5_PU_WIDTH 1 /* GP5_PU */
225#define WM8903_GP5_INTMODE 0x0002 /* GP5_INTMODE */
226#define WM8903_GP5_INTMODE_MASK 0x0002 /* GP5_INTMODE */
227#define WM8903_GP5_INTMODE_SHIFT 1 /* GP5_INTMODE */
228#define WM8903_GP5_INTMODE_WIDTH 1 /* GP5_INTMODE */
229#define WM8903_GP5_DB 0x0001 /* GP5_DB */
230#define WM8903_GP5_DB_MASK 0x0001 /* GP5_DB */
231#define WM8903_GP5_DB_SHIFT 0 /* GP5_DB */
232#define WM8903_GP5_DB_WIDTH 1 /* GP5_DB */
233
234struct wm8903_platform_data {
235 bool irq_active_low; /* Set if IRQ active low, default high */
236
237 /* Default register value for R6 (Mic bias), used to configure
238 * microphone detection. In conjunction with gpio_cfg this
239 * can be used to route the microphone status signals out onto
240 * the GPIOs for use with snd_soc_jack_add_gpios().
241 */
242 u16 micdet_cfg;
243
244 int micdet_delay; /* Delay after microphone detection (ms) */
245
246 u32 gpio_cfg[5]; /* Default register values for GPIO pin mux */
247};
248
249#endif
diff --git a/include/sound/wm8904.h b/include/sound/wm8904.h
index d66575a601be..898be3a8db9a 100644
--- a/include/sound/wm8904.h
+++ b/include/sound/wm8904.h
@@ -15,8 +15,111 @@
15#ifndef __MFD_WM8994_PDATA_H__ 15#ifndef __MFD_WM8994_PDATA_H__
16#define __MFD_WM8994_PDATA_H__ 16#define __MFD_WM8994_PDATA_H__
17 17
18#define WM8904_DRC_REGS 4 18/* Used to enable configuration of a GPIO to all zeros */
19#define WM8904_EQ_REGS 25 19#define WM8904_GPIO_NO_CONFIG 0x8000
20
21/*
22 * R6 (0x06) - Mic Bias Control 0
23 */
24#define WM8904_MICDET_THR_MASK 0x0070 /* MICDET_THR - [6:4] */
25#define WM8904_MICDET_THR_SHIFT 4 /* MICDET_THR - [6:4] */
26#define WM8904_MICDET_THR_WIDTH 3 /* MICDET_THR - [6:4] */
27#define WM8904_MICSHORT_THR_MASK 0x000C /* MICSHORT_THR - [3:2] */
28#define WM8904_MICSHORT_THR_SHIFT 2 /* MICSHORT_THR - [3:2] */
29#define WM8904_MICSHORT_THR_WIDTH 2 /* MICSHORT_THR - [3:2] */
30#define WM8904_MICDET_ENA 0x0002 /* MICDET_ENA */
31#define WM8904_MICDET_ENA_MASK 0x0002 /* MICDET_ENA */
32#define WM8904_MICDET_ENA_SHIFT 1 /* MICDET_ENA */
33#define WM8904_MICDET_ENA_WIDTH 1 /* MICDET_ENA */
34#define WM8904_MICBIAS_ENA 0x0001 /* MICBIAS_ENA */
35#define WM8904_MICBIAS_ENA_MASK 0x0001 /* MICBIAS_ENA */
36#define WM8904_MICBIAS_ENA_SHIFT 0 /* MICBIAS_ENA */
37#define WM8904_MICBIAS_ENA_WIDTH 1 /* MICBIAS_ENA */
38
39/*
40 * R7 (0x07) - Mic Bias Control 1
41 */
42#define WM8904_MIC_DET_FILTER_ENA 0x8000 /* MIC_DET_FILTER_ENA */
43#define WM8904_MIC_DET_FILTER_ENA_MASK 0x8000 /* MIC_DET_FILTER_ENA */
44#define WM8904_MIC_DET_FILTER_ENA_SHIFT 15 /* MIC_DET_FILTER_ENA */
45#define WM8904_MIC_DET_FILTER_ENA_WIDTH 1 /* MIC_DET_FILTER_ENA */
46#define WM8904_MIC_SHORT_FILTER_ENA 0x4000 /* MIC_SHORT_FILTER_ENA */
47#define WM8904_MIC_SHORT_FILTER_ENA_MASK 0x4000 /* MIC_SHORT_FILTER_ENA */
48#define WM8904_MIC_SHORT_FILTER_ENA_SHIFT 14 /* MIC_SHORT_FILTER_ENA */
49#define WM8904_MIC_SHORT_FILTER_ENA_WIDTH 1 /* MIC_SHORT_FILTER_ENA */
50#define WM8904_MICBIAS_SEL_MASK 0x0007 /* MICBIAS_SEL - [2:0] */
51#define WM8904_MICBIAS_SEL_SHIFT 0 /* MICBIAS_SEL - [2:0] */
52#define WM8904_MICBIAS_SEL_WIDTH 3 /* MICBIAS_SEL - [2:0] */
53
54
55/*
56 * R121 (0x79) - GPIO Control 1
57 */
58#define WM8904_GPIO1_PU 0x0020 /* GPIO1_PU */
59#define WM8904_GPIO1_PU_MASK 0x0020 /* GPIO1_PU */
60#define WM8904_GPIO1_PU_SHIFT 5 /* GPIO1_PU */
61#define WM8904_GPIO1_PU_WIDTH 1 /* GPIO1_PU */
62#define WM8904_GPIO1_PD 0x0010 /* GPIO1_PD */
63#define WM8904_GPIO1_PD_MASK 0x0010 /* GPIO1_PD */
64#define WM8904_GPIO1_PD_SHIFT 4 /* GPIO1_PD */
65#define WM8904_GPIO1_PD_WIDTH 1 /* GPIO1_PD */
66#define WM8904_GPIO1_SEL_MASK 0x000F /* GPIO1_SEL - [3:0] */
67#define WM8904_GPIO1_SEL_SHIFT 0 /* GPIO1_SEL - [3:0] */
68#define WM8904_GPIO1_SEL_WIDTH 4 /* GPIO1_SEL - [3:0] */
69
70/*
71 * R122 (0x7A) - GPIO Control 2
72 */
73#define WM8904_GPIO2_PU 0x0020 /* GPIO2_PU */
74#define WM8904_GPIO2_PU_MASK 0x0020 /* GPIO2_PU */
75#define WM8904_GPIO2_PU_SHIFT 5 /* GPIO2_PU */
76#define WM8904_GPIO2_PU_WIDTH 1 /* GPIO2_PU */
77#define WM8904_GPIO2_PD 0x0010 /* GPIO2_PD */
78#define WM8904_GPIO2_PD_MASK 0x0010 /* GPIO2_PD */
79#define WM8904_GPIO2_PD_SHIFT 4 /* GPIO2_PD */
80#define WM8904_GPIO2_PD_WIDTH 1 /* GPIO2_PD */
81#define WM8904_GPIO2_SEL_MASK 0x000F /* GPIO2_SEL - [3:0] */
82#define WM8904_GPIO2_SEL_SHIFT 0 /* GPIO2_SEL - [3:0] */
83#define WM8904_GPIO2_SEL_WIDTH 4 /* GPIO2_SEL - [3:0] */
84
85/*
86 * R123 (0x7B) - GPIO Control 3
87 */
88#define WM8904_GPIO3_PU 0x0020 /* GPIO3_PU */
89#define WM8904_GPIO3_PU_MASK 0x0020 /* GPIO3_PU */
90#define WM8904_GPIO3_PU_SHIFT 5 /* GPIO3_PU */
91#define WM8904_GPIO3_PU_WIDTH 1 /* GPIO3_PU */
92#define WM8904_GPIO3_PD 0x0010 /* GPIO3_PD */
93#define WM8904_GPIO3_PD_MASK 0x0010 /* GPIO3_PD */
94#define WM8904_GPIO3_PD_SHIFT 4 /* GPIO3_PD */
95#define WM8904_GPIO3_PD_WIDTH 1 /* GPIO3_PD */
96#define WM8904_GPIO3_SEL_MASK 0x000F /* GPIO3_SEL - [3:0] */
97#define WM8904_GPIO3_SEL_SHIFT 0 /* GPIO3_SEL - [3:0] */
98#define WM8904_GPIO3_SEL_WIDTH 4 /* GPIO3_SEL - [3:0] */
99
100/*
101 * R124 (0x7C) - GPIO Control 4
102 */
103#define WM8904_GPI7_ENA 0x0200 /* GPI7_ENA */
104#define WM8904_GPI7_ENA_MASK 0x0200 /* GPI7_ENA */
105#define WM8904_GPI7_ENA_SHIFT 9 /* GPI7_ENA */
106#define WM8904_GPI7_ENA_WIDTH 1 /* GPI7_ENA */
107#define WM8904_GPI8_ENA 0x0100 /* GPI8_ENA */
108#define WM8904_GPI8_ENA_MASK 0x0100 /* GPI8_ENA */
109#define WM8904_GPI8_ENA_SHIFT 8 /* GPI8_ENA */
110#define WM8904_GPI8_ENA_WIDTH 1 /* GPI8_ENA */
111#define WM8904_GPIO_BCLK_MODE_ENA 0x0080 /* GPIO_BCLK_MODE_ENA */
112#define WM8904_GPIO_BCLK_MODE_ENA_MASK 0x0080 /* GPIO_BCLK_MODE_ENA */
113#define WM8904_GPIO_BCLK_MODE_ENA_SHIFT 7 /* GPIO_BCLK_MODE_ENA */
114#define WM8904_GPIO_BCLK_MODE_ENA_WIDTH 1 /* GPIO_BCLK_MODE_ENA */
115#define WM8904_GPIO_BCLK_SEL_MASK 0x000F /* GPIO_BCLK_SEL - [3:0] */
116#define WM8904_GPIO_BCLK_SEL_SHIFT 0 /* GPIO_BCLK_SEL - [3:0] */
117#define WM8904_GPIO_BCLK_SEL_WIDTH 4 /* GPIO_BCLK_SEL - [3:0] */
118
119#define WM8904_MIC_REGS 2
120#define WM8904_GPIO_REGS 4
121#define WM8904_DRC_REGS 4
122#define WM8904_EQ_REGS 25
20 123
21/** 124/**
22 * DRC configurations are specified with a label and a set of register 125 * DRC configurations are specified with a label and a set of register
@@ -52,6 +155,9 @@ struct wm8904_pdata {
52 155
53 int num_retune_mobile_cfgs; 156 int num_retune_mobile_cfgs;
54 struct wm8904_retune_mobile_cfg *retune_mobile_cfgs; 157 struct wm8904_retune_mobile_cfg *retune_mobile_cfgs;
158
159 u32 gpio_cfg[WM8904_GPIO_REGS];
160 u32 mic_cfg[WM8904_MIC_REGS];
55}; 161};
56 162
57#endif 163#endif
diff --git a/include/sound/wm8960.h b/include/sound/wm8960.h
new file mode 100644
index 000000000000..74e9a95529c5
--- /dev/null
+++ b/include/sound/wm8960.h
@@ -0,0 +1,24 @@
1/*
2 * wm8960.h -- WM8960 Soc Audio driver platform data
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _WM8960_PDATA_H
10#define _WM8960_PDATA_H
11
12#define WM8960_DRES_400R 0
13#define WM8960_DRES_200R 1
14#define WM8960_DRES_600R 2
15#define WM8960_DRES_150R 3
16#define WM8960_DRES_MAX 3
17
18struct wm8960_data {
19 bool capless; /* Headphone outputs configured in capless mode */
20
21 int dres; /* Discharge resistance for headphone outputs */
22};
23
24#endif
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 12:01:12 -0500