478 files changed, 30631 insertions, 4756 deletions

diff --git a/include/acpi/acpi_bus.h b/include/acpi/acpi_bus.h
index 16c3c441256e..9cfd5b1a48eb 100644
--- a/include/acpi/acpi_bus.h
+++ b/include/acpi/acpi_bus.h
@@ -303,6 +303,9 @@ struct acpi_device {
 #define to_acpi_device(d)       container_of(d, struct acpi_device, dev)
 #define to_acpi_driver(d)       container_of(d, struct acpi_driver, drv)
 
+/* acpi_device.dev.bus == &acpi_bus_type */
+extern struct bus_type acpi_bus_type;
+
 /*
  * Events
  * ------
diff --git a/include/asm-alpha/atomic.h b/include/asm-alpha/atomic.h
index fc77f7413083..f5cb7b878af2 100644
--- a/include/asm-alpha/atomic.h
+++ b/include/asm-alpha/atomic.h
@@ -2,6 +2,7 @@
 #define _ALPHA_ATOMIC_H
 
 #include <asm/barrier.h>
+#include <asm/system.h>
 
 /*
  * Atomic operations that C can't guarantee us.  Useful for
@@ -175,19 +176,64 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t * v)
         return result;
 }
 
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+/**
+ * atomic_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
 #define atomic_add_negative(a, v) (atomic_add_return((a), (v)) < 0)
 #define atomic64_add_negative(a, v) (atomic64_add_return((a), (v)) < 0)
 
diff --git a/include/asm-alpha/kdebug.h b/include/asm-alpha/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-alpha/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-alpha/local.h b/include/asm-alpha/local.h
index 90a510fa358e..6ad3ea696421 100644
--- a/include/asm-alpha/local.h
+++ b/include/asm-alpha/local.h
@@ -4,37 +4,115 @@
 #include <linux/percpu.h>
 #include <asm/atomic.h>
 
-typedef atomic64_t local_t;
+typedef struct
+{
+        atomic_long_t a;
+} local_t;
 
-#define LOCAL_INIT(i)   ATOMIC64_INIT(i)
-#define local_read(v)   atomic64_read(v)
-#define local_set(v,i)  atomic64_set(v,i)
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
+#define local_inc(l)    atomic_long_inc(&(l)->a)
+#define local_dec(l)    atomic_long_dec(&(l)->a)
+#define local_add(i,l)  atomic_long_add((i),(&(l)->a))
+#define local_sub(i,l)  atomic_long_sub((i),(&(l)->a))
 
-#define local_inc(v)    atomic64_inc(v)
-#define local_dec(v)    atomic64_dec(v)
-#define local_add(i, v) atomic64_add(i, v)
-#define local_sub(i, v) atomic64_sub(i, v)
+static __inline__ long local_add_return(long i, local_t * l)
+{
+        long temp, result;
+        __asm__ __volatile__(
+        "1:     ldq_l %0,%1\n"
+        "       addq %0,%3,%2\n"
+        "       addq %0,%3,%0\n"
+        "       stq_c %0,%1\n"
+        "       beq %0,2f\n"
+        ".subsection 2\n"
+        "2:     br 1b\n"
+        ".previous"
+        :"=&r" (temp), "=m" (l->a.counter), "=&r" (result)
+        :"Ir" (i), "m" (l->a.counter) : "memory");
+        return result;
+}
 
-#define __local_inc(v)          ((v)->counter++)
-#define __local_dec(v)          ((v)->counter++)
-#define __local_add(i,v)        ((v)->counter+=(i))
-#define __local_sub(i,v)        ((v)->counter-=(i))
+static __inline__ long local_sub_return(long i, local_t * l)
+{
+        long temp, result;
+        __asm__ __volatile__(
+        "1:     ldq_l %0,%1\n"
+        "       subq %0,%3,%2\n"
+        "       subq %0,%3,%0\n"
+        "       stq_c %0,%1\n"
+        "       beq %0,2f\n"
+        ".subsection 2\n"
+        "2:     br 1b\n"
+        ".previous"
+        :"=&r" (temp), "=m" (l->a.counter), "=&r" (result)
+        :"Ir" (i), "m" (l->a.counter) : "memory");
+        return result;
+}
+
+#define local_cmpxchg(l, o, n) \
+        (cmpxchg_local(&((l)->a.counter), (o), (n)))
+#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to l...
+ * @u: ...unless l is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+#define local_add_unless(l, a, u)                               \
+({                                                              \
+        long c, old;                                            \
+        c = local_read(l);                                      \
+        for (;;) {                                              \
+                if (unlikely(c == (u)))                         \
+                        break;                                  \
+                old = local_cmpxchg((l), c, c + (a));   \
+                if (likely(old == c))                           \
+                        break;                                  \
+                c = old;                                        \
+        }                                                       \
+        c != (u);                                               \
+})
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
+#define local_add_negative(a, l) (local_add_return((a), (l)) < 0)
+
+#define local_dec_return(l) local_sub_return(1,(l))
+
+#define local_inc_return(l) local_add_return(1,(l))
+
+#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0)
+
+#define local_inc_and_test(l) (local_add_return(1, (l)) == 0)
+
+#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
+
+/* Verify if faster than atomic ops */
+#define __local_inc(l)          ((l)->a.counter++)
+#define __local_dec(l)          ((l)->a.counter++)
+#define __local_add(i,l)        ((l)->a.counter+=(i))
+#define __local_sub(i,l)        ((l)->a.counter-=(i))
 
 /* Use these for per-cpu local_t variables: on some archs they are
  * much more efficient than these naive implementations.  Note they take
  * a variable, not an address.
  */
-#define cpu_local_read(v)       local_read(&__get_cpu_var(v))
-#define cpu_local_set(v, i)     local_set(&__get_cpu_var(v), (i))
-
-#define cpu_local_inc(v)        local_inc(&__get_cpu_var(v))
-#define cpu_local_dec(v)        local_dec(&__get_cpu_var(v))
-#define cpu_local_add(i, v)     local_add((i), &__get_cpu_var(v))
-#define cpu_local_sub(i, v)     local_sub((i), &__get_cpu_var(v))
-
-#define __cpu_local_inc(v)      __local_inc(&__get_cpu_var(v))
-#define __cpu_local_dec(v)      __local_dec(&__get_cpu_var(v))
-#define __cpu_local_add(i, v)   __local_add((i), &__get_cpu_var(v))
-#define __cpu_local_sub(i, v)   __local_sub((i), &__get_cpu_var(v))
+#define cpu_local_read(l)       local_read(&__get_cpu_var(l))
+#define cpu_local_set(l, i)     local_set(&__get_cpu_var(l), (i))
+
+#define cpu_local_inc(l)        local_inc(&__get_cpu_var(l))
+#define cpu_local_dec(l)        local_dec(&__get_cpu_var(l))
+#define cpu_local_add(i, l)     local_add((i), &__get_cpu_var(l))
+#define cpu_local_sub(i, l)     local_sub((i), &__get_cpu_var(l))
+
+#define __cpu_local_inc(l)      __local_inc(&__get_cpu_var(l))
+#define __cpu_local_dec(l)      __local_dec(&__get_cpu_var(l))
+#define __cpu_local_add(i, l)   __local_add((i), &__get_cpu_var(l))
+#define __cpu_local_sub(i, l)   __local_sub((i), &__get_cpu_var(l))
 
 #endif /* _ALPHA_LOCAL_H */
diff --git a/include/asm-alpha/pgtable.h b/include/asm-alpha/pgtable.h
index 49ac9bee7ced..616d20662ff3 100644
--- a/include/asm-alpha/pgtable.h
+++ b/include/asm-alpha/pgtable.h
@@ -345,10 +345,6 @@ extern inline pte_t mk_swap_pte(unsigned long type, unsigned long offset)
 #define io_remap_pfn_range(vma, start, pfn, size, prot) \
                 remap_pfn_range(vma, start, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #define pte_ERROR(e) \
         printk("%s:%d: bad pte %016lx.\n", __FILE__, __LINE__, pte_val(e))
 #define pmd_ERROR(e) \
diff --git a/include/asm-alpha/system.h b/include/asm-alpha/system.h
index 03e9c0e5ed74..cf1021a97b2e 100644
--- a/include/asm-alpha/system.h
+++ b/include/asm-alpha/system.h
@@ -443,8 +443,110 @@ extern void __xchg_called_with_bad_pointer(void);
      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
   })
 
-#define tas(ptr) (xchg((ptr),1))
+static inline unsigned long
+__xchg_u8_local(volatile char *m, unsigned long val)
+{
+        unsigned long ret, tmp, addr64;
+
+        __asm__ __volatile__(
+        "       andnot  %4,7,%3\n"
+        "       insbl   %1,%4,%1\n"
+        "1:     ldq_l   %2,0(%3)\n"
+        "       extbl   %2,%4,%0\n"
+        "       mskbl   %2,%4,%2\n"
+        "       or      %1,%2,%2\n"
+        "       stq_c   %2,0(%3)\n"
+        "       beq     %2,2f\n"
+        ".subsection 2\n"
+        "2:     br      1b\n"
+        ".previous"
+        : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
+        : "r" ((long)m), "1" (val) : "memory");
 
+        return ret;
+}
+
+static inline unsigned long
+__xchg_u16_local(volatile short *m, unsigned long val)
+{
+        unsigned long ret, tmp, addr64;
+
+        __asm__ __volatile__(
+        "       andnot  %4,7,%3\n"
+        "       inswl   %1,%4,%1\n"
+        "1:     ldq_l   %2,0(%3)\n"
+        "       extwl   %2,%4,%0\n"
+        "       mskwl   %2,%4,%2\n"
+        "       or      %1,%2,%2\n"
+        "       stq_c   %2,0(%3)\n"
+        "       beq     %2,2f\n"
+        ".subsection 2\n"
+        "2:     br      1b\n"
+        ".previous"
+        : "=&r" (ret), "=&r" (val), "=&r" (tmp), "=&r" (addr64)
+        : "r" ((long)m), "1" (val) : "memory");
+
+        return ret;
+}
+
+static inline unsigned long
+__xchg_u32_local(volatile int *m, unsigned long val)
+{
+        unsigned long dummy;
+
+        __asm__ __volatile__(
+        "1:     ldl_l %0,%4\n"
+        "       bis $31,%3,%1\n"
+        "       stl_c %1,%2\n"
+        "       beq %1,2f\n"
+        ".subsection 2\n"
+        "2:     br 1b\n"
+        ".previous"
+        : "=&r" (val), "=&r" (dummy), "=m" (*m)
+        : "rI" (val), "m" (*m) : "memory");
+
+        return val;
+}
+
+static inline unsigned long
+__xchg_u64_local(volatile long *m, unsigned long val)
+{
+        unsigned long dummy;
+
+        __asm__ __volatile__(
+        "1:     ldq_l %0,%4\n"
+        "       bis $31,%3,%1\n"
+        "       stq_c %1,%2\n"
+        "       beq %1,2f\n"
+        ".subsection 2\n"
+        "2:     br 1b\n"
+        ".previous"
+        : "=&r" (val), "=&r" (dummy), "=m" (*m)
+        : "rI" (val), "m" (*m) : "memory");
+
+        return val;
+}
+
+#define __xchg_local(ptr, x, size) \
+({ \
+        unsigned long __xchg__res; \
+        volatile void *__xchg__ptr = (ptr); \
+        switch (size) { \
+                case 1: __xchg__res = __xchg_u8_local(__xchg__ptr, x); break; \
+                case 2: __xchg__res = __xchg_u16_local(__xchg__ptr, x); break; \
+                case 4: __xchg__res = __xchg_u32_local(__xchg__ptr, x); break; \
+                case 8: __xchg__res = __xchg_u64_local(__xchg__ptr, x); break; \
+                default: __xchg_called_with_bad_pointer(); __xchg__res = x; \
+        } \
+        __xchg__res; \
+})
+
+#define xchg_local(ptr,x)                                                    \
+  ({                                                                         \
+     __typeof__(*(ptr)) _x_ = (x);                                           \
+     (__typeof__(*(ptr))) __xchg_local((ptr), (unsigned long)_x_,            \
+                sizeof(*(ptr))); \
+  })
 
 /* 
  * Atomic compare and exchange.  Compare OLD with MEM, if identical,
@@ -596,6 +698,128 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new, int size)
                                     (unsigned long)_n_, sizeof(*(ptr))); \
   })
 
+static inline unsigned long
+__cmpxchg_u8_local(volatile char *m, long old, long new)
+{
+        unsigned long prev, tmp, cmp, addr64;
+
+        __asm__ __volatile__(
+        "       andnot  %5,7,%4\n"
+        "       insbl   %1,%5,%1\n"
+        "1:     ldq_l   %2,0(%4)\n"
+        "       extbl   %2,%5,%0\n"
+        "       cmpeq   %0,%6,%3\n"
+        "       beq     %3,2f\n"
+        "       mskbl   %2,%5,%2\n"
+        "       or      %1,%2,%2\n"
+        "       stq_c   %2,0(%4)\n"
+        "       beq     %2,3f\n"
+        "2:\n"
+        ".subsection 2\n"
+        "3:     br      1b\n"
+        ".previous"
+        : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
+        : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
+
+        return prev;
+}
+
+static inline unsigned long
+__cmpxchg_u16_local(volatile short *m, long old, long new)
+{
+        unsigned long prev, tmp, cmp, addr64;
+
+        __asm__ __volatile__(
+        "       andnot  %5,7,%4\n"
+        "       inswl   %1,%5,%1\n"
+        "1:     ldq_l   %2,0(%4)\n"
+        "       extwl   %2,%5,%0\n"
+        "       cmpeq   %0,%6,%3\n"
+        "       beq     %3,2f\n"
+        "       mskwl   %2,%5,%2\n"
+        "       or      %1,%2,%2\n"
+        "       stq_c   %2,0(%4)\n"
+        "       beq     %2,3f\n"
+        "2:\n"
+        ".subsection 2\n"
+        "3:     br      1b\n"
+        ".previous"
+        : "=&r" (prev), "=&r" (new), "=&r" (tmp), "=&r" (cmp), "=&r" (addr64)
+        : "r" ((long)m), "Ir" (old), "1" (new) : "memory");
+
+        return prev;
+}
+
+static inline unsigned long
+__cmpxchg_u32_local(volatile int *m, int old, int new)
+{
+        unsigned long prev, cmp;
+
+        __asm__ __volatile__(
+        "1:     ldl_l %0,%5\n"
+        "       cmpeq %0,%3,%1\n"
+        "       beq %1,2f\n"
+        "       mov %4,%1\n"
+        "       stl_c %1,%2\n"
+        "       beq %1,3f\n"
+        "2:\n"
+        ".subsection 2\n"
+        "3:     br 1b\n"
+        ".previous"
+        : "=&r"(prev), "=&r"(cmp), "=m"(*m)
+        : "r"((long) old), "r"(new), "m"(*m) : "memory");
+
+        return prev;
+}
+
+static inline unsigned long
+__cmpxchg_u64_local(volatile long *m, unsigned long old, unsigned long new)
+{
+        unsigned long prev, cmp;
+
+        __asm__ __volatile__(
+        "1:     ldq_l %0,%5\n"
+        "       cmpeq %0,%3,%1\n"
+        "       beq %1,2f\n"
+        "       mov %4,%1\n"
+        "       stq_c %1,%2\n"
+        "       beq %1,3f\n"
+        "2:\n"
+        ".subsection 2\n"
+        "3:     br 1b\n"
+        ".previous"
+        : "=&r"(prev), "=&r"(cmp), "=m"(*m)
+        : "r"((long) old), "r"(new), "m"(*m) : "memory");
+
+        return prev;
+}
+
+static __always_inline unsigned long
+__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
+                int size)
+{
+        switch (size) {
+                case 1:
+                        return __cmpxchg_u8_local(ptr, old, new);
+                case 2:
+                        return __cmpxchg_u16_local(ptr, old, new);
+                case 4:
+                        return __cmpxchg_u32_local(ptr, old, new);
+                case 8:
+                        return __cmpxchg_u64_local(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg_local(ptr,o,n)                                           \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
 #endif /* __ASSEMBLY__ */
 
 #define arch_align_stack(x) (x)
diff --git a/include/asm-alpha/thread_info.h b/include/asm-alpha/thread_info.h
index 69ffd93f8e22..eeb3bef91e11 100644
--- a/include/asm-alpha/thread_info.h
+++ b/include/asm-alpha/thread_info.h
@@ -92,5 +92,27 @@ register struct thread_info *__current_thread_info __asm__("$8");
 #define _TIF_ALLWORK_MASK       (_TIF_WORK_MASK         \
                                  | _TIF_SYSCALL_TRACE)
 
+#define ALPHA_UAC_SHIFT         6
+#define ALPHA_UAC_MASK          (1 << TIF_UAC_NOPRINT | 1 << TIF_UAC_NOFIX | \
+                                 1 << TIF_UAC_SIGBUS)
+
+#define SET_UNALIGN_CTL(task,value)     ({                                   \
+        (task)->thread_info->flags = (((task)->thread_info->flags &          \
+                ~ALPHA_UAC_MASK)                                             \
+                | (((value) << ALPHA_UAC_SHIFT)       & (1<<TIF_UAC_NOPRINT))\
+                | (((value) << (ALPHA_UAC_SHIFT + 1)) & (1<<TIF_UAC_SIGBUS)) \
+                | (((value) << (ALPHA_UAC_SHIFT - 1)) & (1<<TIF_UAC_NOFIX)));\
+        0; })
+
+#define GET_UNALIGN_CTL(task,value)     ({                              \
+        put_user(((task)->thread_info->flags & (1 << TIF_UAC_NOPRINT))  \
+                  >> ALPHA_UAC_SHIFT                                    \
+                 | ((task)->thread_info->flags & (1 << TIF_UAC_SIGBUS)) \
+                 >> (ALPHA_UAC_SHIFT + 1)                               \
+                 | ((task)->thread_info->flags & (1 << TIF_UAC_NOFIX))  \
+                 >> (ALPHA_UAC_SHIFT - 1),                              \
+                 (int __user *)(value));                                \
+        })
+
 #endif /* __KERNEL__ */
 #endif /* _ALPHA_THREAD_INFO_H */
diff --git a/include/asm-arm/arch-at91/at91_adc.h b/include/asm-arm/arch-at91/at91_adc.h
new file mode 100644
index 000000000000..1ed66eaaf83a
--- /dev/null
+++ b/include/asm-arm/arch-at91/at91_adc.h
@@ -0,0 +1,61 @@
+/*
+ * include/asm-arm/arch-at91/at91_adc.h
+ *
+ * Copyright (C) SAN People
+ *
+ * Analog-to-Digital Converter (ADC) registers.
+ * Based on AT91SAM9260 datasheet revision D.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ */
+
+#ifndef AT91_ADC_H
+#define AT91_ADC_H
+
+#define AT91_ADC_CR             0x00            /* Control Register */
+#define         AT91_ADC_SWRST          (1 << 0)        /* Software Reset */
+#define         AT91_ADC_START          (1 << 1)        /* Start Conversion */
+
+#define AT91_ADC_MR             0x04            /* Mode Register */
+#define         AT91_ADC_TRGEN          (1 << 0)        /* Trigger Enable */
+#define         AT91_ADC_TRGSEL         (7 << 1)        /* Trigger Selection */
+#define                 AT91_ADC_TRGSEL_TC0             (0 << 1)
+#define                 AT91_ADC_TRGSEL_TC1             (1 << 1)
+#define                 AT91_ADC_TRGSEL_TC2             (2 << 1)
+#define                 AT91_ADC_TRGSEL_EXTERNAL        (6 << 1)
+#define         AT91_ADC_LOWRES         (1 << 4)        /* Low Resolution */
+#define         AT91_ADC_SLEEP          (1 << 5)        /* Sleep Mode */
+#define         AT91_ADC_PRESCAL        (0x3f << 8)     /* Prescalar Rate Selection */
+#define                 AT91_ADC_PRESCAL_(x)    ((x) << 8)
+#define         AT91_ADC_STARTUP        (0x1f << 16)    /* Startup Up Time */
+#define                 AT91_ADC_STARTUP_(x)    ((x) << 16)
+#define         AT91_ADC_SHTIM          (0xf  << 24)    /* Sample & Hold Time */
+#define                 AT91_ADC_SHTIM_(x)      ((x) << 24)
+
+#define AT91_ADC_CHER           0x10            /* Channel Enable Register */
+#define AT91_ADC_CHDR           0x14            /* Channel Disable Register */
+#define AT91_ADC_CHSR           0x18            /* Channel Status Register */
+#define         AT91_ADC_CH(n)          (1 << (n))      /* Channel Number */
+
+#define AT91_ADC_SR             0x1C            /* Status Register */
+#define         AT91_ADC_EOC(n)         (1 << (n))      /* End of Conversion on Channel N */
+#define         AT91_ADC_OVRE(n)        (1 << ((n) + 8))/* Overrun Error on Channel N */
+#define         AT91_ADC_DRDY           (1 << 16)       /* Data Ready */
+#define         AT91_ADC_GOVRE          (1 << 17)       /* General Overrun Error */
+#define         AT91_ADC_ENDRX          (1 << 18)       /* End of RX Buffer */
+#define         AT91_ADC_RXFUFF         (1 << 19)       /* RX Buffer Full */
+
+#define AT91_ADC_LCDR           0x20            /* Last Converted Data Register */
+#define         AT91_ADC_LDATA          (0x3ff)
+
+#define AT91_ADC_IER            0x24            /* Interrupt Enable Register */
+#define AT91_ADC_IDR            0x28            /* Interrupt Disable Register */
+#define AT91_ADC_IMR            0x2C            /* Interrupt Mask Register */
+
+#define AT91_ADC_CHR(n)         (0x30 + ((n) * 4)       /* Channel Data Register N */
+#define         AT91_ADC_DATA           (0x3ff)
+
+#endif
diff --git a/include/asm-arm/arch-at91/board.h b/include/asm-arm/arch-at91/board.h
index 7b9903c2c447..7a34a5b1fed0 100644
--- a/include/asm-arm/arch-at91/board.h
+++ b/include/asm-arm/arch-at91/board.h
@@ -62,7 +62,7 @@ struct at91_mmc_data {
 };
 extern void __init at91_add_device_mmc(short mmc_id, struct at91_mmc_data *data);
 
- /* Ethernet */
+ /* Ethernet (EMAC & MACB) */
 struct at91_eth_data {
         u8              phy_irq_pin;    /* PHY IRQ */
         u8              is_rmii;        /* using RMII interface? */
@@ -114,6 +114,16 @@ struct atmel_uart_data {
 };
 extern void __init at91_add_device_serial(void);
 
+ /* LCD Controller */
+struct atmel_lcdfb_info;
+extern void __init at91_add_device_lcdc(struct atmel_lcdfb_info *data);
+
+ /* AC97 */
+struct atmel_ac97_data {
+        u8              reset_pin;      /* reset */
+}
+extern void __init at91_add_device_ac97(struct atmel_ac97_data *data);
+
  /* LEDs */
 extern u8 at91_leds_cpu;
 extern u8 at91_leds_timer;
diff --git a/include/asm-arm/arch-ebsa110/io.h b/include/asm-arm/arch-ebsa110/io.h
index 722c5e086285..44a4001de807 100644
--- a/include/asm-arm/arch-ebsa110/io.h
+++ b/include/asm-arm/arch-ebsa110/io.h
@@ -81,4 +81,12 @@ extern void outsb(unsigned int port, const void *buf, int sz);
 extern void outsw(unsigned int port, const void *buf, int sz);
 extern void outsl(unsigned int port, const void *buf, int sz);
 
+/* can't support writesb atm */
+extern void writesw(void __iomem *addr, const void *data, int wordlen);
+extern void writesl(void __iomem *addr, const void *data, int longlen);
+
+/* can't support readsb atm */
+extern void readsw(const void __iomem *addr, void *data, int wordlen);
+extern void readsl(const void __iomem *addr, void *data, int longlen);
+
 #endif
diff --git a/include/asm-arm/arch-imx/imx-regs.h b/include/asm-arm/arch-imx/imx-regs.h
index e56a4e247d62..de6494a4dc6b 100644
--- a/include/asm-arm/arch-imx/imx-regs.h
+++ b/include/asm-arm/arch-imx/imx-regs.h
@@ -477,122 +477,4 @@
 #define LCDISR_EOF     (1<<1)
 #define LCDISR_BOF     (1<<0)
 
-/*
- *  UART Module. Takes the UART base address as argument
- */
-#define URXD0(x) __REG( 0x0 + (x)) /* Receiver Register */
-#define URTX0(x) __REG( 0x40 + (x)) /* Transmitter Register */
-#define UCR1(x)  __REG( 0x80 + (x)) /* Control Register 1 */
-#define UCR2(x)  __REG( 0x84 + (x)) /* Control Register 2 */
-#define UCR3(x)  __REG( 0x88 + (x)) /* Control Register 3 */
-#define UCR4(x)  __REG( 0x8c + (x)) /* Control Register 4 */
-#define UFCR(x)  __REG( 0x90 + (x)) /* FIFO Control Register */
-#define USR1(x)  __REG( 0x94 + (x)) /* Status Register 1 */
-#define USR2(x)  __REG( 0x98 + (x)) /* Status Register 2 */
-#define UESC(x)  __REG( 0x9c + (x)) /* Escape Character Register */
-#define UTIM(x)  __REG( 0xa0 + (x)) /* Escape Timer Register */
-#define UBIR(x)  __REG( 0xa4 + (x)) /* BRM Incremental Register */
-#define UBMR(x)  __REG( 0xa8 + (x)) /* BRM Modulator Register */
-#define UBRC(x)  __REG( 0xac + (x)) /* Baud Rate Count Register */
-#define BIPR1(x) __REG( 0xb0 + (x)) /* Incremental Preset Register 1 */
-#define BIPR2(x) __REG( 0xb4 + (x)) /* Incremental Preset Register 2 */
-#define BIPR3(x) __REG( 0xb8 + (x)) /* Incremental Preset Register 3 */
-#define BIPR4(x) __REG( 0xbc + (x)) /* Incremental Preset Register 4 */
-#define BMPR1(x) __REG( 0xc0 + (x)) /* BRM Modulator Register 1 */
-#define BMPR2(x) __REG( 0xc4 + (x)) /* BRM Modulator Register 2 */
-#define BMPR3(x) __REG( 0xc8 + (x)) /* BRM Modulator Register 3 */
-#define BMPR4(x) __REG( 0xcc + (x)) /* BRM Modulator Register 4 */
-#define UTS(x)   __REG( 0xd0 + (x)) /* UART Test Register */
-
-/* UART Control Register Bit Fields.*/
-#define  URXD_CHARRDY    (1<<15)
-#define  URXD_ERR        (1<<14)
-#define  URXD_OVRRUN     (1<<13)
-#define  URXD_FRMERR     (1<<12)
-#define  URXD_BRK        (1<<11)
-#define  URXD_PRERR      (1<<10)
-#define  UCR1_ADEN       (1<<15) /* Auto dectect interrupt */
-#define  UCR1_ADBR       (1<<14) /* Auto detect baud rate */
-#define  UCR1_TRDYEN     (1<<13) /* Transmitter ready interrupt enable */
-#define  UCR1_IDEN       (1<<12) /* Idle condition interrupt */
-#define  UCR1_RRDYEN     (1<<9)  /* Recv ready interrupt enable */
-#define  UCR1_RDMAEN     (1<<8)  /* Recv ready DMA enable */
-#define  UCR1_IREN       (1<<7)  /* Infrared interface enable */
-#define  UCR1_TXMPTYEN   (1<<6)  /* Transimitter empty interrupt enable */
-#define  UCR1_RTSDEN     (1<<5)  /* RTS delta interrupt enable */
-#define  UCR1_SNDBRK     (1<<4)  /* Send break */
-#define  UCR1_TDMAEN     (1<<3)  /* Transmitter ready DMA enable */
-#define  UCR1_UARTCLKEN  (1<<2)  /* UART clock enabled */
-#define  UCR1_DOZE       (1<<1)  /* Doze */
-#define  UCR1_UARTEN     (1<<0)  /* UART enabled */
-#define  UCR2_ESCI       (1<<15) /* Escape seq interrupt enable */
-#define  UCR2_IRTS       (1<<14) /* Ignore RTS pin */
-#define  UCR2_CTSC       (1<<13) /* CTS pin control */
-#define  UCR2_CTS        (1<<12) /* Clear to send */
-#define  UCR2_ESCEN      (1<<11) /* Escape enable */
-#define  UCR2_PREN       (1<<8)  /* Parity enable */
-#define  UCR2_PROE       (1<<7)  /* Parity odd/even */
-#define  UCR2_STPB       (1<<6)  /* Stop */
-#define  UCR2_WS         (1<<5)  /* Word size */
-#define  UCR2_RTSEN      (1<<4)  /* Request to send interrupt enable */
-#define  UCR2_TXEN       (1<<2)  /* Transmitter enabled */
-#define  UCR2_RXEN       (1<<1)  /* Receiver enabled */
-#define  UCR2_SRST       (1<<0)  /* SW reset */
-#define  UCR3_DTREN      (1<<13) /* DTR interrupt enable */
-#define  UCR3_PARERREN   (1<<12) /* Parity enable */
-#define  UCR3_FRAERREN   (1<<11) /* Frame error interrupt enable */
-#define  UCR3_DSR        (1<<10) /* Data set ready */
-#define  UCR3_DCD        (1<<9)  /* Data carrier detect */
-#define  UCR3_RI         (1<<8)  /* Ring indicator */
-#define  UCR3_TIMEOUTEN  (1<<7)  /* Timeout interrupt enable */
-#define  UCR3_RXDSEN     (1<<6)  /* Receive status interrupt enable */
-#define  UCR3_AIRINTEN   (1<<5)  /* Async IR wake interrupt enable */
-#define  UCR3_AWAKEN     (1<<4)  /* Async wake interrupt enable */
-#define  UCR3_REF25      (1<<3)  /* Ref freq 25 MHz */
-#define  UCR3_REF30      (1<<2)  /* Ref Freq 30 MHz */
-#define  UCR3_INVT       (1<<1)  /* Inverted Infrared transmission */
-#define  UCR3_BPEN       (1<<0)  /* Preset registers enable */
-#define  UCR4_CTSTL_32   (32<<10) /* CTS trigger level (32 chars) */
-#define  UCR4_INVR       (1<<9)  /* Inverted infrared reception */
-#define  UCR4_ENIRI      (1<<8)  /* Serial infrared interrupt enable */
-#define  UCR4_WKEN       (1<<7)  /* Wake interrupt enable */
-#define  UCR4_REF16      (1<<6)  /* Ref freq 16 MHz */
-#define  UCR4_IRSC       (1<<5)  /* IR special case */
-#define  UCR4_TCEN       (1<<3)  /* Transmit complete interrupt enable */
-#define  UCR4_BKEN       (1<<2)  /* Break condition interrupt enable */
-#define  UCR4_OREN       (1<<1)  /* Receiver overrun interrupt enable */
-#define  UCR4_DREN       (1<<0)  /* Recv data ready interrupt enable */
-#define  UFCR_RXTL_SHF   0       /* Receiver trigger level shift */
-#define  UFCR_RFDIV      (7<<7)  /* Reference freq divider mask */
-#define  UFCR_TXTL_SHF   10      /* Transmitter trigger level shift */
-#define  USR1_PARITYERR  (1<<15) /* Parity error interrupt flag */
-#define  USR1_RTSS       (1<<14) /* RTS pin status */
-#define  USR1_TRDY       (1<<13) /* Transmitter ready interrupt/dma flag */
-#define  USR1_RTSD       (1<<12) /* RTS delta */
-#define  USR1_ESCF       (1<<11) /* Escape seq interrupt flag */
-#define  USR1_FRAMERR    (1<<10) /* Frame error interrupt flag */
-#define  USR1_RRDY       (1<<9)  /* Receiver ready interrupt/dma flag */
-#define  USR1_TIMEOUT    (1<<7)  /* Receive timeout interrupt status */
-#define  USR1_RXDS       (1<<6)  /* Receiver idle interrupt flag */
-#define  USR1_AIRINT     (1<<5)  /* Async IR wake interrupt flag */
-#define  USR1_AWAKE      (1<<4)  /* Aysnc wake interrupt flag */
-#define  USR2_ADET       (1<<15) /* Auto baud rate detect complete */
-#define  USR2_TXFE       (1<<14) /* Transmit buffer FIFO empty */
-#define  USR2_DTRF       (1<<13) /* DTR edge interrupt flag */
-#define  USR2_IDLE       (1<<12) /* Idle condition */
-#define  USR2_IRINT      (1<<8)  /* Serial infrared interrupt flag */
-#define  USR2_WAKE       (1<<7)  /* Wake */
-#define  USR2_RTSF       (1<<4)  /* RTS edge interrupt flag */
-#define  USR2_TXDC       (1<<3)  /* Transmitter complete */
-#define  USR2_BRCD       (1<<2)  /* Break condition */
-#define  USR2_ORE        (1<<1)  /* Overrun error */
-#define  USR2_RDR        (1<<0)  /* Recv data ready */
-#define  UTS_FRCPERR     (1<<13) /* Force parity error */
-#define  UTS_LOOP        (1<<12) /* Loop tx and rx */
-#define  UTS_TXEMPTY     (1<<6)  /* TxFIFO empty */
-#define  UTS_RXEMPTY     (1<<5)  /* RxFIFO empty */
-#define  UTS_TXFULL      (1<<4)  /* TxFIFO full */
-#define  UTS_RXFULL      (1<<3)  /* RxFIFO full */
-#define  UTS_SOFTRST     (1<<0)  /* Software reset */
-
 #endif                          // _IMX_REGS_H
diff --git a/include/asm-arm/arch-iop13xx/io.h b/include/asm-arm/arch-iop13xx/io.h
index 5a7bdb526606..7dfff4ad82b3 100644
--- a/include/asm-arm/arch-iop13xx/io.h
+++ b/include/asm-arm/arch-iop13xx/io.h
@@ -26,7 +26,6 @@
 #define __mem_isa(a) (a)
 
 extern void __iomem * __iop13xx_io(unsigned long io_addr);
-extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
 extern void __iomem *__iop13xx_ioremap(unsigned long cookie, size_t size,
         unsigned long flags);
 extern void __iop13xx_iounmap(void __iomem *addr);
diff --git a/include/asm-arm/arch-iop13xx/iop13xx.h b/include/asm-arm/arch-iop13xx/iop13xx.h
index d26b755a9879..85707e9c3325 100644
--- a/include/asm-arm/arch-iop13xx/iop13xx.h
+++ b/include/asm-arm/arch-iop13xx/iop13xx.h
@@ -8,6 +8,7 @@ extern u32 iop13xx_atue_pmmr_offset;
 void iop13xx_init_irq(void);
 void iop13xx_map_io(void);
 void iop13xx_platform_init(void);
+void iop13xx_add_tpmi_devices(void);
 void iop13xx_init_irq(void);
 
 /* CPUID CP6 R0 Page 0 */
@@ -27,19 +28,24 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PCI_OFFSET       IOP13XX_MAX_RAM_SIZE
 
 /* PCI MAP
- * 0x0000.0000 - 0x8000.0000           1:1 mapping with Physical RAM
- * 0x8000.0000 - 0x8800.0000           PCIX/PCIE memory window (128MB)
-*/
+ * bus range            cpu phys        cpu virt        note
+ * 0x0000.0000 + 2GB    (n/a)           (n/a)           inbound, 1:1 mapping with Physical RAM
+ * 0x8000.0000 + 928M   0x1.8000.0000   (ioremap)       PCIX outbound memory window
+ * 0x8000.0000 + 928M   0x2.8000.0000   (ioremap)       PCIE outbound memory window
+ *
+ * IO MAP
+ * 0x1000 + 64K 0x0.fffb.1000   0xfec6.1000     PCIX outbound i/o window
+ * 0x1000 + 64K 0x0.fffd.1000   0xfed7.1000     PCIE outbound i/o window
+ */
 #define IOP13XX_PCIX_IO_WINDOW_SIZE   0x10000UL
 #define IOP13XX_PCIX_LOWER_IO_PA      0xfffb0000UL
 #define IOP13XX_PCIX_LOWER_IO_VA      0xfec60000UL
-#define IOP13XX_PCIX_LOWER_IO_BA      0x0fff0000UL
+#define IOP13XX_PCIX_LOWER_IO_BA      0x0UL /* OIOTVR */
+#define IOP13XX_PCIX_IO_BUS_OFFSET    0x1000UL
 #define IOP13XX_PCIX_UPPER_IO_PA      (IOP13XX_PCIX_LOWER_IO_PA +\
                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
 #define IOP13XX_PCIX_UPPER_IO_VA      (IOP13XX_PCIX_LOWER_IO_VA +\
                                        IOP13XX_PCIX_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIX_IO_OFFSET        (IOP13XX_PCIX_LOWER_IO_VA -\
-                                       IOP13XX_PCIX_LOWER_IO_BA)
 #define IOP13XX_PCIX_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
                                            (IOP13XX_PCIX_LOWER_IO_PA\
                                            - IOP13XX_PCIX_LOWER_IO_VA))
@@ -65,15 +71,14 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PCIE_IO_WINDOW_SIZE      0x10000UL
 #define IOP13XX_PCIE_LOWER_IO_PA         0xfffd0000UL
 #define IOP13XX_PCIE_LOWER_IO_VA         0xfed70000UL
-#define IOP13XX_PCIE_LOWER_IO_BA         0x0fff0000UL
+#define IOP13XX_PCIE_LOWER_IO_BA         0x0UL  /* OIOTVR */
+#define IOP13XX_PCIE_IO_BUS_OFFSET       0x1000UL
 #define IOP13XX_PCIE_UPPER_IO_PA         (IOP13XX_PCIE_LOWER_IO_PA +\
                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 #define IOP13XX_PCIE_UPPER_IO_VA         (IOP13XX_PCIE_LOWER_IO_VA +\
                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
 #define IOP13XX_PCIE_UPPER_IO_BA         (IOP13XX_PCIE_LOWER_IO_BA +\
                                          IOP13XX_PCIE_IO_WINDOW_SIZE - 1)
-#define IOP13XX_PCIE_IO_OFFSET           (IOP13XX_PCIE_LOWER_IO_VA -\
-                                         IOP13XX_PCIE_LOWER_IO_BA)
 #define IOP13XX_PCIE_IO_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
                                            (IOP13XX_PCIE_LOWER_IO_PA\
                                            - IOP13XX_PCIE_LOWER_IO_VA))
@@ -451,4 +456,5 @@ static inline int iop13xx_cpu_id(void)
 #define IOP13XX_PBI_BAR1                IOP13XX_PBI_OFFSET(0x10)
 #define IOP13XX_PBI_LR1                 IOP13XX_PBI_OFFSET(0x14)
 
+#define IOP13XX_PROCESSOR_FREQ          IOP13XX_REG_ADDR32(0x2180)
 #endif /* _IOP13XX_HW_H_ */
diff --git a/include/asm-arm/arch-iop13xx/time.h b/include/asm-arm/arch-iop13xx/time.h
index 77a837a02dec..49213d9d7cad 100644
--- a/include/asm-arm/arch-iop13xx/time.h
+++ b/include/asm-arm/arch-iop13xx/time.h
@@ -7,9 +7,65 @@
 #define IOP_TMR_PRIVILEGED 0x08
 #define IOP_TMR_RATIO_1_1  0x00
 
+#define IOP13XX_XSI_FREQ_RATIO_MASK     (3 << 19)
+#define IOP13XX_XSI_FREQ_RATIO_2        (0 << 19)
+#define IOP13XX_XSI_FREQ_RATIO_3        (1 << 19)
+#define IOP13XX_XSI_FREQ_RATIO_4        (2 << 19)
+#define IOP13XX_CORE_FREQ_MASK          (7 << 16)
+#define IOP13XX_CORE_FREQ_600           (0 << 16)
+#define IOP13XX_CORE_FREQ_667           (1 << 16)
+#define IOP13XX_CORE_FREQ_800           (2 << 16)
+#define IOP13XX_CORE_FREQ_933           (3 << 16)
+#define IOP13XX_CORE_FREQ_1000          (4 << 16)
+#define IOP13XX_CORE_FREQ_1200          (5 << 16)
+
 void iop_init_time(unsigned long tickrate);
 unsigned long iop_gettimeoffset(void);
 
+static inline unsigned long iop13xx_core_freq(void)
+{
+        unsigned long freq = __raw_readl(IOP13XX_PROCESSOR_FREQ);
+        freq &= IOP13XX_CORE_FREQ_MASK;
+        switch (freq) {
+        case IOP13XX_CORE_FREQ_600:
+                return 600000000;
+        case IOP13XX_CORE_FREQ_667:
+                return 667000000;
+        case IOP13XX_CORE_FREQ_800:
+                return 800000000;
+        case IOP13XX_CORE_FREQ_933:
+                return 933000000;
+        case IOP13XX_CORE_FREQ_1000:
+                return 1000000000;
+        case IOP13XX_CORE_FREQ_1200:
+                return 1200000000;
+        default:
+                printk("%s: warning unknown frequency, defaulting to 800Mhz\n",
+                        __FUNCTION__);
+        }
+
+        return 800000000;
+}
+
+static inline unsigned long iop13xx_xsi_bus_ratio(void)
+{
+        unsigned long  ratio = __raw_readl(IOP13XX_PROCESSOR_FREQ);
+        ratio &= IOP13XX_XSI_FREQ_RATIO_MASK;
+        switch (ratio) {
+        case IOP13XX_XSI_FREQ_RATIO_2:
+                return 2;
+        case IOP13XX_XSI_FREQ_RATIO_3:
+                return 3;
+        case IOP13XX_XSI_FREQ_RATIO_4:
+                return 4;
+        default:
+                printk("%s: warning unknown ratio, defaulting to 2\n",
+                        __FUNCTION__);
+        }
+
+        return 2;
+}
+
 static inline void write_tmr0(u32 val)
 {
         asm volatile("mcr p6, 0, %0, c0, c9, 0" : : "r" (val));
diff --git a/include/asm-arm/arch-iop32x/io.h b/include/asm-arm/arch-iop32x/io.h
index 5f570a598a37..994f16af5057 100644
--- a/include/asm-arm/arch-iop32x/io.h
+++ b/include/asm-arm/arch-iop32x/io.h
@@ -13,7 +13,6 @@
 
 #include <asm/hardware.h>
 
-extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
 extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
         unsigned long flags);
 extern void __iop3xx_iounmap(void __iomem *addr);
diff --git a/include/asm-arm/arch-iop32x/iop32x.h b/include/asm-arm/arch-iop32x/iop32x.h
index 2e9469047eb1..0d8af57221a1 100644
--- a/include/asm-arm/arch-iop32x/iop32x.h
+++ b/include/asm-arm/arch-iop32x/iop32x.h
@@ -24,5 +24,14 @@
 
 #include <asm/hardware/iop3xx.h>
 
+/* ATU Parameters
+ * set up a 1:1 bus to physical ram relationship
+ * w/ physical ram on top of pci in the memory map
+ */
+#define IOP32X_MAX_RAM_SIZE            0x40000000UL
+#define IOP3XX_MAX_RAM_SIZE            IOP32X_MAX_RAM_SIZE
+#define IOP3XX_PCI_LOWER_MEM_BA        0x80000000
+#define IOP32X_PCI_MEM_WINDOW_SIZE     0x04000000
+#define IOP3XX_PCI_MEM_WINDOW_SIZE     IOP32X_PCI_MEM_WINDOW_SIZE
 
 #endif
diff --git a/include/asm-arm/arch-iop32x/memory.h b/include/asm-arm/arch-iop32x/memory.h
index 764cd3f0d416..c51072af214e 100644
--- a/include/asm-arm/arch-iop32x/memory.h
+++ b/include/asm-arm/arch-iop32x/memory.h
@@ -19,8 +19,8 @@
  * bus_to_virt: Used to convert an address for DMA operations
  *              to an address that the kernel can use.
  */
-#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
-#define __bus_to_virt(x)        (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)        (__phys_to_virt(x))
 
 
 #endif
diff --git a/include/asm-arm/arch-iop33x/io.h b/include/asm-arm/arch-iop33x/io.h
index 1bb5071e1fa8..993f7589b29f 100644
--- a/include/asm-arm/arch-iop33x/io.h
+++ b/include/asm-arm/arch-iop33x/io.h
@@ -13,7 +13,6 @@
 
 #include <asm/hardware.h>
 
-extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
 extern void __iomem *__iop3xx_ioremap(unsigned long cookie, size_t size,
         unsigned long flags);
 extern void __iop3xx_iounmap(void __iomem *addr);
diff --git a/include/asm-arm/arch-iop33x/iop33x.h b/include/asm-arm/arch-iop33x/iop33x.h
index 7ac6e93db5ff..766985b9a723 100644
--- a/include/asm-arm/arch-iop33x/iop33x.h
+++ b/include/asm-arm/arch-iop33x/iop33x.h
@@ -29,5 +29,15 @@
 #define IOP33X_UART1_PHYS       (IOP3XX_PERIPHERAL_PHYS_BASE + 0x1740)
 #define IOP33X_UART1_VIRT       (IOP3XX_PERIPHERAL_VIRT_BASE + 0x1740)
 
+/* ATU Parameters
+ * set up a 1:1 bus to physical ram relationship
+ * w/ pci on top of physical ram in memory map
+ */
+#define IOP33X_MAX_RAM_SIZE             0x80000000UL
+#define IOP3XX_MAX_RAM_SIZE             IOP33X_MAX_RAM_SIZE
+#define IOP3XX_PCI_LOWER_MEM_BA (PHYS_OFFSET + IOP33X_MAX_RAM_SIZE)
+#define IOP33X_PCI_MEM_WINDOW_SIZE      0x08000000
+#define IOP3XX_PCI_MEM_WINDOW_SIZE      IOP33X_PCI_MEM_WINDOW_SIZE
+
 
 #endif
diff --git a/include/asm-arm/arch-iop33x/memory.h b/include/asm-arm/arch-iop33x/memory.h
index 0d39139b241e..c8749127d6ab 100644
--- a/include/asm-arm/arch-iop33x/memory.h
+++ b/include/asm-arm/arch-iop33x/memory.h
@@ -19,8 +19,8 @@
  * bus_to_virt: Used to convert an address for DMA operations
  *              to an address that the kernel can use.
  */
-#define __virt_to_bus(x)        (((__virt_to_phys(x)) & ~(*IOP3XX_IATVR2)) | ((*IOP3XX_IABAR2) & 0xfffffff0))
-#define __bus_to_virt(x)        (__phys_to_virt(((x) & ~(*IOP3XX_IALR2)) | ( *IOP3XX_IATVR2)))
+#define __virt_to_bus(x)        (__virt_to_phys(x))
+#define __bus_to_virt(x)        (__phys_to_virt(x))
 
 
 #endif
diff --git a/include/asm-arm/arch-ixp23xx/io.h b/include/asm-arm/arch-ixp23xx/io.h
index 18415a81ac74..66f5bafc315c 100644
--- a/include/asm-arm/arch-ixp23xx/io.h
+++ b/include/asm-arm/arch-ixp23xx/io.h
@@ -23,7 +23,7 @@
 #include <linux/kernel.h>       /* For BUG */
 
 static inline void __iomem *
-ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags)
+ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned int mtype)
 {
         if (addr >= IXP23XX_PCI_MEM_START &&
                 addr <= IXP23XX_PCI_MEM_START + IXP23XX_PCI_MEM_SIZE) {
@@ -34,7 +34,7 @@ ixp23xx_ioremap(unsigned long addr, unsigned long size, unsigned long flags)
                         ((addr - IXP23XX_PCI_MEM_START) + IXP23XX_PCI_MEM_VIRT);
         }
 
-        return __ioremap(addr, size, flags);
+        return __arm_ioremap(addr, size, mtype);
 }
 
 static inline void
diff --git a/include/asm-arm/arch-ixp4xx/cpu.h b/include/asm-arm/arch-ixp4xx/cpu.h
new file mode 100644
index 000000000000..d2523b326c6c
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/cpu.h
@@ -0,0 +1,31 @@
+/*
+ * include/asm-arm/arch-ixp4xx/cpu.h
+ *
+ * IXP4XX cpu type detection
+ *
+ * Copyright (C) 2007 MontaVista Software, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ */
+
+#ifndef __ASM_ARCH_CPU_H__
+#define __ASM_ARCH_CPU_H__
+
+extern unsigned int processor_id;
+/* Processor id value in CP15 Register 0 */
+#define IXP425_PROCESSOR_ID_VALUE       0x690541c0
+#define IXP435_PROCESSOR_ID_VALUE       0x69054040
+#define IXP465_PROCESSOR_ID_VALUE       0x69054200
+#define IXP4XX_PROCESSOR_ID_MASK        0xfffffff0
+
+#define cpu_is_ixp42x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+                          IXP425_PROCESSOR_ID_VALUE)
+#define cpu_is_ixp43x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+                          IXP435_PROCESSOR_ID_VALUE)
+#define cpu_is_ixp46x() ((processor_id & IXP4XX_PROCESSOR_ID_MASK) == \
+                          IXP465_PROCESSOR_ID_VALUE)
+
+#endif  /* _ASM_ARCH_CPU_H */
diff --git a/include/asm-arm/arch-ixp4xx/dsmg600.h b/include/asm-arm/arch-ixp4xx/dsmg600.h
new file mode 100644
index 000000000000..a19605ad240d
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/dsmg600.h
@@ -0,0 +1,57 @@
+/*
+ * DSM-G600 platform specific definitions
+ *
+ * Copyright (C) 2006 Tower Technologies
+ * Author: Alessandro Zummo <a.zummo@towertech.it>
+ *
+ * based on ixdp425.h:
+ *      Copyright 2004 (C) MontaVista, Software, Inc.
+ *
+ * This file is licensed under  the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __ASM_ARCH_HARDWARE_H__
+#error "Do not include this directly, instead #include <asm/hardware.h>"
+#endif
+
+#define DSMG600_SDA_PIN         5
+#define DSMG600_SCL_PIN         4
+
+/*
+ * DSMG600 PCI IRQs
+ */
+#define DSMG600_PCI_MAX_DEV     4
+#define DSMG600_PCI_IRQ_LINES   3
+
+
+/* PCI controller GPIO to IRQ pin mappings */
+#define DSMG600_PCI_INTA_PIN    11
+#define DSMG600_PCI_INTB_PIN    10
+#define DSMG600_PCI_INTC_PIN    9
+#define DSMG600_PCI_INTD_PIN    8
+#define DSMG600_PCI_INTE_PIN    7
+#define DSMG600_PCI_INTF_PIN    6
+
+/* DSM-G600 Timer Setting */
+#define DSMG600_FREQ 66000000
+
+/* Buttons */
+
+#define DSMG600_PB_GPIO         15      /* power button */
+#define DSMG600_PB_BM           (1L << DSMG600_PB_GPIO)
+
+#define DSMG600_RB_GPIO         3       /* reset button */
+
+#define DSMG600_RB_IRQ          IRQ_IXP4XX_GPIO3
+
+#define DSMG600_PO_GPIO         2       /* power off */
+
+/* LEDs */
+
+#define DSMG600_LED_PWR_GPIO    0
+#define DSMG600_LED_PWR_BM      (1L << DSMG600_LED_PWR_GPIO)
+
+#define DSMG600_LED_WLAN_GPIO   14
+#define DSMG600_LED_WLAN_BM     (1L << DSMG600_LED_WLAN_GPIO)
diff --git a/include/asm-arm/arch-ixp4xx/entry-macro.S b/include/asm-arm/arch-ixp4xx/entry-macro.S
index dadb568b7ef0..f144a005ed95 100644
--- a/include/asm-arm/arch-ixp4xx/entry-macro.S
+++ b/include/asm-arm/arch-ixp4xx/entry-macro.S
@@ -31,9 +31,9 @@
 
 1001:
                 /*
-                 * IXP465 has an upper IRQ status register
+                 * IXP465/IXP435 has an upper IRQ status register
                  */
-#if defined(CONFIG_CPU_IXP46X)
+#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
                 ldr     \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
                 ldr     \irqstat, [\irqstat]            @ get upper interrupts
                 mov     \irqnr, #63
diff --git a/include/asm-arm/arch-ixp4xx/gpio.h b/include/asm-arm/arch-ixp4xx/gpio.h
new file mode 100644
index 000000000000..3a4c5b8ae9e1
--- /dev/null
+++ b/include/asm-arm/arch-ixp4xx/gpio.h
@@ -0,0 +1,73 @@
+/*
+ * linux/include/asm-arm/arch-ixp4xx/gpio.h
+ *
+ * IXP4XX GPIO wrappers for arch-neutral GPIO calls
+ *
+ * Written by Milan Svoboda <msvoboda@ra.rockwell.com>
+ * Based on PXA implementation by Philipp Zabel <philipp.zabel@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
+ *
+ */
+
+#ifndef __ASM_ARCH_IXP4XX_GPIO_H
+#define __ASM_ARCH_IXP4XX_GPIO_H
+
+#include <asm/hardware.h>
+
+static inline int gpio_request(unsigned gpio, const char *label)
+{
+        return 0;
+}
+
+static inline void gpio_free(unsigned gpio)
+{
+        return;
+}
+
+static inline int gpio_direction_input(unsigned gpio)
+{
+        gpio_line_config(gpio, IXP4XX_GPIO_IN);
+        return 0;
+}
+
+static inline int gpio_direction_output(unsigned gpio, int level)
+{
+        gpio_line_set(gpio, level);
+        gpio_line_config(gpio, IXP4XX_GPIO_OUT);
+        return 0;
+}
+
+static inline int gpio_get_value(unsigned gpio)
+{
+        int value;
+
+        gpio_line_get(gpio, &value);
+
+        return value;
+}
+
+static inline void gpio_set_value(unsigned gpio, int value)
+{
+        gpio_line_set(gpio, value);
+}
+
+#include <asm-generic/gpio.h>                   /* cansleep wrappers */
+
+extern int gpio_to_irq(int gpio);
+extern int irq_to_gpio(int gpio);
+
+#endif
+
diff --git a/include/asm-arm/arch-ixp4xx/hardware.h b/include/asm-arm/arch-ixp4xx/hardware.h
index 88fd0877dcc1..297ceda08b61 100644
--- a/include/asm-arm/arch-ixp4xx/hardware.h
+++ b/include/asm-arm/arch-ixp4xx/hardware.h
@@ -17,8 +17,8 @@
 #ifndef __ASM_ARCH_HARDWARE_H__
 #define __ASM_ARCH_HARDWARE_H__
 
-#define PCIBIOS_MIN_IO                  0x00001000
-#define PCIBIOS_MIN_MEM                 0x48000000
+#define PCIBIOS_MIN_IO          0x00001000
+#define PCIBIOS_MIN_MEM         (cpu_is_ixp43x() ? 0x40000000 : 0x48000000)
 
 /*
  * We override the standard dma-mask routines for bouncing.
@@ -27,11 +27,8 @@
 
 #define pcibios_assign_all_busses()     1
 
-#if defined(CONFIG_CPU_IXP46X) && !defined(__ASSEMBLY__)
-extern unsigned int processor_id;
-#define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200)
-#else
-#define cpu_is_ixp465() (0)
+#ifndef __ASSEMBLER__
+#include <asm/arch/cpu.h>
 #endif
 
 /* Register locations and bits */
@@ -47,5 +44,6 @@ extern unsigned int processor_id;
 #include "prpmc1100.h"
 #include "nslu2.h"
 #include "nas100d.h"
+#include "dsmg600.h"
 
 #endif  /* _ASM_ARCH_HARDWARE_H */
diff --git a/include/asm-arm/arch-ixp4xx/io.h b/include/asm-arm/arch-ixp4xx/io.h
index a41ba229c564..c72f9d79417c 100644
--- a/include/asm-arm/arch-ixp4xx/io.h
+++ b/include/asm-arm/arch-ixp4xx/io.h
@@ -59,10 +59,10 @@ extern int ixp4xx_pci_write(u32 addr, u32 cmd, u32 data);
  * fallback to the default.
  */
 static inline void __iomem *
-__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned long flags)
+__ixp4xx_ioremap(unsigned long addr, size_t size, unsigned int mtype)
 {
-        if((addr < 0x48000000) || (addr > 0x4fffffff))
-                return __ioremap(addr, size, flags);
+        if((addr < PCIBIOS_MIN_MEM) || (addr > 0x4fffffff))
+                return __arm_ioremap(addr, size, mtype);
 
         return (void *)addr;
 }
diff --git a/include/asm-arm/arch-ixp4xx/irqs.h b/include/asm-arm/arch-ixp4xx/irqs.h
index e44a563d00ff..11801605047b 100644
--- a/include/asm-arm/arch-ixp4xx/irqs.h
+++ b/include/asm-arm/arch-ixp4xx/irqs.h
@@ -62,10 +62,10 @@
 /*
  * Only first 32 sources are valid if running on IXP42x systems
  */
-#ifndef CONFIG_CPU_IXP46X
-#define NR_IRQS                 32
-#else
+#if defined(CONFIG_CPU_IXP46X) || defined(CONFIG_CPU_IXP43X)
 #define NR_IRQS                 64
+#else
+#define NR_IRQS                 32
 #endif
 
 #define XSCALE_PMU_IRQ          (IRQ_IXP4XX_XSCALE_PMU)
@@ -118,4 +118,14 @@
 #define        IRQ_NAS100D_PCI_INTD    IRQ_IXP4XX_GPIO8
 #define        IRQ_NAS100D_PCI_INTE    IRQ_IXP4XX_GPIO7
 
+/*
+ * D-Link DSM-G600 RevA board IRQs
+ */
+#define        IRQ_DSMG600_PCI_INTA    IRQ_IXP4XX_GPIO11
+#define        IRQ_DSMG600_PCI_INTB    IRQ_IXP4XX_GPIO10
+#define        IRQ_DSMG600_PCI_INTC    IRQ_IXP4XX_GPIO9
+#define        IRQ_DSMG600_PCI_INTD    IRQ_IXP4XX_GPIO8
+#define        IRQ_DSMG600_PCI_INTE    IRQ_IXP4XX_GPIO7
+#define        IRQ_DSMG600_PCI_INTF    IRQ_IXP4XX_GPIO6
+
 #endif
diff --git a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
index ed35e5c94f40..5d949d763a91 100644
--- a/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
+++ b/include/asm-arm/arch-ixp4xx/ixp4xx-regs.h
@@ -607,19 +607,4 @@
 
 #define DCMD_LENGTH     0x01fff         /* length mask (max = 8K - 1) */
 
-#ifndef __ASSEMBLY__
-static inline int cpu_is_ixp46x(void)
-{
-#ifdef CONFIG_CPU_IXP46X
-        unsigned int processor_id;
-
-        asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
-
-        if ((processor_id & 0xffffff00) == 0x69054200)
-                return 1;
-#endif
-        return 0;
-}
-#endif
-
 #endif
diff --git a/include/asm-arm/arch-netx/netx-regs.h b/include/asm-arm/arch-netx/netx-regs.h
index 8ab45bea83ca..fc9aa21f360c 100644
--- a/include/asm-arm/arch-netx/netx-regs.h
+++ b/include/asm-arm/arch-netx/netx-regs.h
@@ -121,8 +121,8 @@
 #define NETX_SYSTEM_IOC_MR          NETX_SYSTEM_REG(0x08)
 
 /* FIXME: Docs are not consistent */
-#define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x08)
-/* #define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x0c) */
+/* #define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x08) */
+#define NETX_SYSTEM_RES_CR          NETX_SYSTEM_REG(0x0c)
 
 #define NETX_SYSTEM_PHY_CONTROL     NETX_SYSTEM_REG(0x10)
 #define NETX_SYSTEM_REV             NETX_SYSTEM_REG(0x34)
diff --git a/include/asm-arm/arch-ns9xxx/board.h b/include/asm-arm/arch-ns9xxx/board.h
index 91dc8fb1027f..716f34fdb716 100644
--- a/include/asm-arm/arch-ns9xxx/board.h
+++ b/include/asm-arm/arch-ns9xxx/board.h
@@ -15,4 +15,6 @@
 
 #define board_is_a9m9750dev()   (machine_is_cc9p9360dev())
 
+#define board_is_jscc9p9360()   (machine_is_cc9p9360js())
+
 #endif /* ifndef __ASM_ARCH_BOARD_H */
diff --git a/include/asm-arm/arch-ns9xxx/clock.h b/include/asm-arm/arch-ns9xxx/clock.h
index a7c5ab3d9011..bf30cbdcc2bf 100644
--- a/include/asm-arm/arch-ns9xxx/clock.h
+++ b/include/asm-arm/arch-ns9xxx/clock.h
@@ -11,13 +11,43 @@
 #ifndef __ASM_ARCH_CLOCK_H
 #define __ASM_ARCH_CLOCK_H
 
+#include <asm/arch-ns9xxx/regs-sys.h>
+
+#define CRYSTAL 29491200 /* Hz */
+
+/* The HRM calls this value f_vco */
 static inline u32 ns9xxx_systemclock(void) __attribute__((const));
 static inline u32 ns9xxx_systemclock(void)
 {
+        u32 pll = SYS_PLL;
+
         /*
-         * This should be a multiple of HZ * TIMERCLOCKSELECT (in time.c)
+         * The system clock should be a multiple of HZ * TIMERCLOCKSELECT (in
+         * time.c).
+         *
+         * The following values are given:
+         *   - TIMERCLOCKSELECT == 2^i for an i in {0 .. 6}
+         *   - CRYSTAL == 29491200 == 2^17 * 3^2 * 5^2
+         *   - ND in {0 .. 31}
+         *   - FS in {0 .. 3}
+         *
+         * Assuming the worst, we consider:
+         *   - TIMERCLOCKSELECT == 64
+         *   - ND == 0
+         *   - FS == 3
+         *
+         * So HZ should be a divisor of:
+         *      (CRYSTAL * (ND + 1) >> FS) / TIMERCLOCKSELECT
+         *   == (2^17 * 3^2 * 5^2 * 1 >> 3) / 64
+         *   == 2^8 * 3^2 * 5^2
+         *   == 57600
+         *
+         * Currently HZ is defined to be 100 for this platform.
+         *
+         * Fine.
          */
-        return 353894400;
+        return CRYSTAL * (REGGET(pll, SYS_PLL, ND) + 1)
+                >> REGGET(pll, SYS_PLL, FS);
 }
 
 static inline u32 ns9xxx_cpuclock(void) __attribute__((const));
diff --git a/include/asm-arm/arch-ns9xxx/hardware.h b/include/asm-arm/arch-ns9xxx/hardware.h
index 6819da7c48d4..25600554c4fe 100644
--- a/include/asm-arm/arch-ns9xxx/hardware.h
+++ b/include/asm-arm/arch-ns9xxx/hardware.h
@@ -51,8 +51,9 @@
                        ~(__REGVAL(reg ## _ ## field, value))))          \
                   | (__REGVAL(reg ## _ ## field, value))))
 
-#  define REGGET(reg, field)                                            \
-        ((reg & (reg ## _ ## field)) / (field & (-field)))
+#  define REGGET(var, reg, field)                                       \
+        ((var & (reg ## _ ## field)) /                                  \
+         ((reg ## _ ## field) & (-(reg ## _ ## field))))
 
 #else
 
diff --git a/include/asm-arm/arch-ns9xxx/processor.h b/include/asm-arm/arch-ns9xxx/processor.h
index 716c106ac0bf..223e51b8e104 100644
--- a/include/asm-arm/arch-ns9xxx/processor.h
+++ b/include/asm-arm/arch-ns9xxx/processor.h
@@ -13,6 +13,7 @@
 
 #include <asm/mach-types.h>
 
-#define processor_is_ns9360()   (machine_is_cc9p9360dev())
+#define processor_is_ns9360()   (machine_is_cc9p9360dev()               \
+                || machine_is_cc9p9360js())
 
 #endif /* ifndef __ASM_ARCH_PROCESSOR_H */
diff --git a/include/asm-arm/arch-ns9xxx/regs-sys.h b/include/asm-arm/arch-ns9xxx/regs-sys.h
index 8162a50bb273..a42546aeb92a 100644
--- a/include/asm-arm/arch-ns9xxx/regs-sys.h
+++ b/include/asm-arm/arch-ns9xxx/regs-sys.h
@@ -48,6 +48,12 @@
 /* PLL Configuration register */
 #define SYS_PLL         __REG(0xa0900188)
 
+/* PLL FS status */
+#define SYS_PLL_FS              __REGBITS(24, 23)
+
+/* PLL ND status */
+#define SYS_PLL_ND              __REGBITS(20, 16)
+
 /* PLL Configuration register: PLL SW change */
 #define SYS_PLL_SWC             __REGBIT(15)
 #define SYS_PLL_SWC_NO                  __REGVAL(SYS_PLL_SWC, 0)
diff --git a/include/asm-arm/arch-pxa/i2c.h b/include/asm-arm/arch-pxa/i2c.h
index 46ec2243974a..e404b233d8a8 100644
--- a/include/asm-arm/arch-pxa/i2c.h
+++ b/include/asm-arm/arch-pxa/i2c.h
@@ -64,6 +64,7 @@ struct i2c_slave_client;
 struct i2c_pxa_platform_data {
         unsigned int            slave_addr;
         struct i2c_slave_client *slave;
+        unsigned int            class;
 };
 
 extern void pxa_set_i2c_info(struct i2c_pxa_platform_data *info);
diff --git a/include/asm-arm/arch-pxa/pxa-regs.h b/include/asm-arm/arch-pxa/pxa-regs.h
index 139c9d954818..dbcc9298b0c8 100644
--- a/include/asm-arm/arch-pxa/pxa-regs.h
+++ b/include/asm-arm/arch-pxa/pxa-regs.h
@@ -1801,35 +1801,35 @@
 #define CCCR_M_MASK     0x0060          /* Memory Frequency to Run Mode Frequency Multiplier */
 #define CCCR_L_MASK     0x001f          /* Crystal Frequency to Memory Frequency Multiplier */
 
-#define CKEN24_CAMERA   (1 << 24)       /* Camera Interface Clock Enable */
-#define CKEN23_SSP1     (1 << 23)       /* SSP1 Unit Clock Enable */
-#define CKEN22_MEMC     (1 << 22)       /* Memory Controller Clock Enable */
-#define CKEN21_MEMSTK   (1 << 21)       /* Memory Stick Host Controller */
-#define CKEN20_IM       (1 << 20)       /* Internal Memory Clock Enable */
-#define CKEN19_KEYPAD   (1 << 19)       /* Keypad Interface Clock Enable */
-#define CKEN18_USIM     (1 << 18)       /* USIM Unit Clock Enable */
-#define CKEN17_MSL      (1 << 17)       /* MSL Unit Clock Enable */
-#define CKEN16_LCD      (1 << 16)       /* LCD Unit Clock Enable */
-#define CKEN15_PWRI2C   (1 << 15)       /* PWR I2C Unit Clock Enable */
-#define CKEN14_I2C      (1 << 14)       /* I2C Unit Clock Enable */
-#define CKEN13_FICP     (1 << 13)       /* FICP Unit Clock Enable */
-#define CKEN12_MMC      (1 << 12)       /* MMC Unit Clock Enable */
-#define CKEN11_USB      (1 << 11)       /* USB Unit Clock Enable */
-#define CKEN10_ASSP     (1 << 10)       /* ASSP (SSP3) Clock Enable */
-#define CKEN10_USBHOST  (1 << 10)       /* USB Host Unit Clock Enable */
-#define CKEN9_OSTIMER   (1 << 9)        /* OS Timer Unit Clock Enable */
-#define CKEN9_NSSP      (1 << 9)        /* NSSP (SSP2) Clock Enable */
-#define CKEN8_I2S       (1 << 8)        /* I2S Unit Clock Enable */
-#define CKEN7_BTUART    (1 << 7)        /* BTUART Unit Clock Enable */
-#define CKEN6_FFUART    (1 << 6)        /* FFUART Unit Clock Enable */
-#define CKEN5_STUART    (1 << 5)        /* STUART Unit Clock Enable */
-#define CKEN4_HWUART    (1 << 4)        /* HWUART Unit Clock Enable */
-#define CKEN4_SSP3      (1 << 4)        /* SSP3 Unit Clock Enable */
-#define CKEN3_SSP       (1 << 3)        /* SSP Unit Clock Enable */
-#define CKEN3_SSP2      (1 << 3)        /* SSP2 Unit Clock Enable */
-#define CKEN2_AC97      (1 << 2)        /* AC97 Unit Clock Enable */
-#define CKEN1_PWM1      (1 << 1)        /* PWM1 Clock Enable */
-#define CKEN0_PWM0      (1 << 0)        /* PWM0 Clock Enable */
+#define CKEN_CAMERA     (24)    /* Camera Interface Clock Enable */
+#define CKEN_SSP1       (23)    /* SSP1 Unit Clock Enable */
+#define CKEN_MEMC       (22)    /* Memory Controller Clock Enable */
+#define CKEN_MEMSTK     (21)    /* Memory Stick Host Controller */
+#define CKEN_IM         (20)    /* Internal Memory Clock Enable */
+#define CKEN_KEYPAD     (19)    /* Keypad Interface Clock Enable */
+#define CKEN_USIM       (18)    /* USIM Unit Clock Enable */
+#define CKEN_MSL        (17)    /* MSL Unit Clock Enable */
+#define CKEN_LCD        (16)    /* LCD Unit Clock Enable */
+#define CKEN_PWRI2C     (15)    /* PWR I2C Unit Clock Enable */
+#define CKEN_I2C        (14)    /* I2C Unit Clock Enable */
+#define CKEN_FICP       (13)    /* FICP Unit Clock Enable */
+#define CKEN_MMC        (12)    /* MMC Unit Clock Enable */
+#define CKEN_USB        (11)    /* USB Unit Clock Enable */
+#define CKEN_ASSP       (10)    /* ASSP (SSP3) Clock Enable */
+#define CKEN_USBHOST    (10)    /* USB Host Unit Clock Enable */
+#define CKEN_OSTIMER    (9)     /* OS Timer Unit Clock Enable */
+#define CKEN_NSSP       (9)     /* NSSP (SSP2) Clock Enable */
+#define CKEN_I2S        (8)     /* I2S Unit Clock Enable */
+#define CKEN_BTUART     (7)     /* BTUART Unit Clock Enable */
+#define CKEN_FFUART     (6)     /* FFUART Unit Clock Enable */
+#define CKEN_STUART     (5)     /* STUART Unit Clock Enable */
+#define CKEN_HWUART     (4)     /* HWUART Unit Clock Enable */
+#define CKEN_SSP3       (4)     /* SSP3 Unit Clock Enable */
+#define CKEN_SSP        (3)     /* SSP Unit Clock Enable */
+#define CKEN_SSP2       (3)     /* SSP2 Unit Clock Enable */
+#define CKEN_AC97       (2)     /* AC97 Unit Clock Enable */
+#define CKEN_PWM1       (1)     /* PWM1 Clock Enable */
+#define CKEN_PWM0       (0)     /* PWM0 Clock Enable */
 
 #define OSCC_OON        (1 << 1)        /* 32.768kHz OON (write-once only bit) */
 #define OSCC_OOK        (1 << 0)        /* 32.768kHz OOK (read-only bit) */
diff --git a/include/asm-arm/arch-s3c2410/regs-ac97.h b/include/asm-arm/arch-s3c2410/regs-ac97.h
index bdd6a4f93d7f..b004dee6bcaf 100644
--- a/include/asm-arm/arch-s3c2410/regs-ac97.h
+++ b/include/asm-arm/arch-s3c2410/regs-ac97.h
@@ -13,11 +13,55 @@
 #ifndef __ASM_ARCH_REGS_AC97_H
 #define __ASM_ARCH_REGS_AC97_H __FILE__
 
-#define S3C_AC97_GLBCTRL        (0x00)
-#define S3C_AC97_GLBSTAT        (0x04)
-#define S3C_AC97_CODEC_CMD      (0x08)
-#define S3C_AC97_PCM_ADDR       (0x10)
-#define S3C_AC97_PCM_DATA       (0x18)
-#define S3C_AC97_MIC_DATA       (0x1C)
+#define S3C_AC97_GLBCTRL                                (0x00)
+
+#define S3C_AC97_GLBCTRL_CODECREADYIE                   (1<<22)
+#define S3C_AC97_GLBCTRL_PCMOUTURIE                     (1<<21)
+#define S3C_AC97_GLBCTRL_PCMINORIE                      (1<<20)
+#define S3C_AC97_GLBCTRL_MICINORIE                      (1<<19)
+#define S3C_AC97_GLBCTRL_PCMOUTTIE                      (1<<18)
+#define S3C_AC97_GLBCTRL_PCMINTIE                       (1<<17)
+#define S3C_AC97_GLBCTRL_MICINTIE                       (1<<16)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_OFF                   (0<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_PIO                   (1<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_DMA                   (2<<12)
+#define S3C_AC97_GLBCTRL_PCMOUTTM_MASK                  (3<<12)
+#define S3C_AC97_GLBCTRL_PCMINTM_OFF                    (0<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_PIO                    (1<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_DMA                    (2<<10)
+#define S3C_AC97_GLBCTRL_PCMINTM_MASK                   (3<<10)
+#define S3C_AC97_GLBCTRL_MICINTM_OFF                    (0<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_PIO                    (1<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_DMA                    (2<<8)
+#define S3C_AC97_GLBCTRL_MICINTM_MASK                   (3<<8)
+#define S3C_AC97_GLBCTRL_TRANSFERDATAENABLE             (1<<3)
+#define S3C_AC97_GLBCTRL_ACLINKON                       (1<<2)
+#define S3C_AC97_GLBCTRL_WARMRESET                      (1<<1)
+#define S3C_AC97_GLBCTRL_COLDRESET                      (1<<0)
+
+#define S3C_AC97_GLBSTAT                                (0x04)
+
+#define S3C_AC97_GLBSTAT_CODECREADY                     (1<<22)
+#define S3C_AC97_GLBSTAT_PCMOUTUR                       (1<<21)
+#define S3C_AC97_GLBSTAT_PCMINORI                       (1<<20)
+#define S3C_AC97_GLBSTAT_MICINORI                       (1<<19)
+#define S3C_AC97_GLBSTAT_PCMOUTTI                       (1<<18)
+#define S3C_AC97_GLBSTAT_PCMINTI                        (1<<17)
+#define S3C_AC97_GLBSTAT_MICINTI                        (1<<16)
+#define S3C_AC97_GLBSTAT_MAINSTATE_IDLE                 (0<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_INIT                 (1<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_READY                (2<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_ACTIVE               (3<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_LP                   (4<<0)
+#define S3C_AC97_GLBSTAT_MAINSTATE_WARM                 (5<<0)
+
+#define S3C_AC97_CODEC_CMD                              (0x08)
+
+#define S3C_AC97_CODEC_CMD_READ                         (1<<23)
+
+#define S3C_AC97_STAT                                   (0x0c)
+#define S3C_AC97_PCM_ADDR                               (0x10)
+#define S3C_AC97_PCM_DATA                               (0x18)
+#define S3C_AC97_MIC_DATA                               (0x1C)
 
 #endif /* __ASM_ARCH_REGS_AC97_H */
diff --git a/include/asm-arm/arch-s3c2410/regs-udc.h b/include/asm-arm/arch-s3c2410/regs-udc.h
index 3c8354619b60..e1e9805d2d9a 100644
--- a/include/asm-arm/arch-s3c2410/regs-udc.h
+++ b/include/asm-arm/arch-s3c2410/regs-udc.h
@@ -75,7 +75,7 @@
 #define S3C2410_UDC_OUT_FIFO_CNT1_REG   S3C2410_USBDREG(0x0198)
 #define S3C2410_UDC_OUT_FIFO_CNT2_REG   S3C2410_USBDREG(0x019c)
 
-
+#define S3C2410_UDC_FUNCADDR_UPDATE     (1<<7)
 
 #define S3C2410_UDC_PWR_ISOUP           (1<<7) // R/W
 #define S3C2410_UDC_PWR_RESET           (1<<3) // R
@@ -135,10 +135,6 @@
 #define S3C2410_UDC_OCSR2_ISO           (1<<6) // R/W
 #define S3C2410_UDC_OCSR2_DMAIEN        (1<<5) // R/W
 
-#define S3C2410_UDC_SETIX(base,x)           \
-        writel(S3C2410_UDC_INDEX_ ## x, base+S3C2410_UDC_INDEX_REG);
-
-
 #define S3C2410_UDC_EP0_CSR_OPKRDY      (1<<0)
 #define S3C2410_UDC_EP0_CSR_IPKRDY      (1<<1)
 #define S3C2410_UDC_EP0_CSR_SENTSTL     (1<<2)
diff --git a/include/asm-arm/atomic.h b/include/asm-arm/atomic.h
index f266c2795124..3b59f94b5a3d 100644
--- a/include/asm-arm/atomic.h
+++ b/include/asm-arm/atomic.h
@@ -12,6 +12,7 @@
 #define __ASM_ARM_ATOMIC_H
 
 #include <linux/compiler.h>
+#include <asm/system.h>
 
 typedef struct { volatile int counter; } atomic_t;
 
diff --git a/include/asm-arm/ecard.h b/include/asm-arm/ecard.h
index a0ae2b954d29..3a6d3eb27622 100644
--- a/include/asm-arm/ecard.h
+++ b/include/asm-arm/ecard.h
@@ -160,6 +160,7 @@ struct expansion_card {
         unsigned char           irqmask;        /* IRQ mask                     */
         unsigned char           fiqmask;        /* FIQ mask                     */
         unsigned char           claimed;        /* Card claimed?                */
+        unsigned char           easi;           /* EASI card                    */
 
         void                    *irq_data;      /* Data for use for IRQ by card */
         void                    *fiq_data;      /* Data for use for FIQ by card */
@@ -169,7 +170,6 @@ struct expansion_card {
         CONST unsigned int      dma;            /* DMA number (for request_dma) */
         CONST unsigned int      irq;            /* IRQ number (for request_irq) */
         CONST unsigned int      fiq;            /* FIQ number (for request_irq) */
-        CONST card_type_t       type;           /* Type of card                 */
         CONST struct in_ecid    cid;            /* Card Identification          */
 
         /* Private internal data */
@@ -224,56 +224,6 @@ ecard_address(struct expansion_card *ec, card_type_t type, card_speed_t speed)
 extern int ecard_request_resources(struct expansion_card *ec);
 extern void ecard_release_resources(struct expansion_card *ec);
 
-#ifdef ECARD_C
-/* Definitions internal to ecard.c - for it's use only!!
- *
- * External expansion card header as read from the card
- */
-struct ex_ecid {
-        unsigned char   r_irq:1;
-        unsigned char   r_zero:1;
-        unsigned char   r_fiq:1;
-        unsigned char   r_id:4;
-        unsigned char   r_a:1;
-
-        unsigned char   r_cd:1;
-        unsigned char   r_is:1;
-        unsigned char   r_w:2;
-        unsigned char   r_r1:4;
-
-        unsigned char   r_r2:8;
-
-        unsigned char   r_prod[2];
-
-        unsigned char   r_manu[2];
-
-        unsigned char   r_country;
-
-        unsigned char   r_fiqmask;
-        unsigned char   r_fiqoff[3];
-
-        unsigned char   r_irqmask;
-        unsigned char   r_irqoff[3];
-};
-
-/*
- * Chunk directory entry as read from the card
- */
-struct ex_chunk_dir {
-        unsigned char r_id;
-        unsigned char r_len[3];
-        unsigned long r_start;
-        union {
-                char string[256];
-                char data[1];
-        } d;
-#define c_id(x)         ((x)->r_id)
-#define c_len(x)        ((x)->r_len[0]|((x)->r_len[1]<<8)|((x)->r_len[2]<<16))
-#define c_start(x)      ((x)->r_start)
-};
-
-#endif
-
 extern struct bus_type ecard_bus_type;
 
 #define ECARD_DEV(_d)   container_of((_d), struct expansion_card, dev)
diff --git a/include/asm-arm/hardware/iop3xx.h b/include/asm-arm/hardware/iop3xx.h
index 15141a9caca8..63feceb7ede5 100644
--- a/include/asm-arm/hardware/iop3xx.h
+++ b/include/asm-arm/hardware/iop3xx.h
@@ -28,6 +28,7 @@
 extern void gpio_line_config(int line, int direction);
 extern int  gpio_line_get(int line);
 extern void gpio_line_set(int line, int value);
+extern int init_atu;
 #endif
 
 
@@ -41,7 +42,7 @@ extern void gpio_line_set(int line, int value);
                                         IOP3XX_PERIPHERAL_SIZE - 1)
 #define IOP3XX_PERIPHERAL_UPPER_VA (IOP3XX_PERIPHERAL_VIRT_BASE +\
                                         IOP3XX_PERIPHERAL_SIZE - 1)
-#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) addr -\
+#define IOP3XX_PMMR_PHYS_TO_VIRT(addr) (u32) ((u32) (addr) -\
                                         (IOP3XX_PERIPHERAL_PHYS_BASE\
                                         - IOP3XX_PERIPHERAL_VIRT_BASE))
 #define IOP3XX_REG_ADDR(reg)            (IOP3XX_PERIPHERAL_VIRT_BASE + (reg))
@@ -103,6 +104,21 @@ extern void gpio_line_set(int line, int value);
 #define IOP3XX_PCIXCMD          (volatile u16 *)IOP3XX_REG_ADDR(0x01e2)
 #define IOP3XX_PCIXSR           (volatile u32 *)IOP3XX_REG_ADDR(0x01e4)
 #define IOP3XX_PCIIRSR          (volatile u32 *)IOP3XX_REG_ADDR(0x01ec)
+#define IOP3XX_PCSR_OUT_Q_BUSY (1 << 15)
+#define IOP3XX_PCSR_IN_Q_BUSY   (1 << 14)
+#define IOP3XX_ATUCR_OUT_EN     (1 << 1)
+
+#define IOP3XX_INIT_ATU_DEFAULT 0
+#define IOP3XX_INIT_ATU_DISABLE -1
+#define IOP3XX_INIT_ATU_ENABLE   1
+
+#ifdef CONFIG_IOP3XX_ATU
+#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
+                                IOP3XX_INIT_ATU_ENABLE : init_atu)
+#else
+#define iop3xx_get_init_atu(x) (init_atu == IOP3XX_INIT_ATU_DEFAULT ?\
+                                IOP3XX_INIT_ATU_DISABLE : init_atu)
+#endif
 
 /* Messaging Unit  */
 #define IOP3XX_IMR0             (volatile u32 *)IOP3XX_REG_ADDR(0x0310)
@@ -253,14 +269,12 @@ extern void gpio_line_set(int line, int value);
 /*
  * IOP3XX I/O and Mem space regions for PCI autoconfiguration
  */
-#define IOP3XX_PCI_MEM_WINDOW_SIZE      0x04000000
-#define IOP3XX_PCI_LOWER_MEM_PA         0x80000000
-#define IOP3XX_PCI_LOWER_MEM_BA         (*IOP3XX_OMWTVR0)
+#define IOP3XX_PCI_LOWER_MEM_PA 0x80000000
 
 #define IOP3XX_PCI_IO_WINDOW_SIZE       0x00010000
 #define IOP3XX_PCI_LOWER_IO_PA          0x90000000
 #define IOP3XX_PCI_LOWER_IO_VA          0xfe000000
-#define IOP3XX_PCI_LOWER_IO_BA          (*IOP3XX_OIOWTVR)
+#define IOP3XX_PCI_LOWER_IO_BA          0x90000000
 #define IOP3XX_PCI_UPPER_IO_PA          (IOP3XX_PCI_LOWER_IO_PA +\
                                         IOP3XX_PCI_IO_WINDOW_SIZE - 1)
 #define IOP3XX_PCI_UPPER_IO_VA          (IOP3XX_PCI_LOWER_IO_VA +\
diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h
index 5f60b4220906..8261ff9e7955 100644
--- a/include/asm-arm/io.h
+++ b/include/asm-arm/io.h
@@ -56,13 +56,22 @@ extern void __raw_readsl(const void __iomem *addr, void *data, int longlen);
 
 /*
  * Architecture ioremap implementation.
- *
- * __ioremap takes CPU physical address.
- *
- * __ioremap_pfn takes a Page Frame Number and an offset into that page
  */
-extern void __iomem * __ioremap_pfn(unsigned long, unsigned long, size_t, unsigned long);
-extern void __iomem * __ioremap(unsigned long, size_t, unsigned long);
+#define MT_DEVICE               0
+#define MT_DEVICE_NONSHARED     1
+#define MT_DEVICE_CACHED        2
+#define MT_DEVICE_IXP2000       3
+/*
+ * types 4 onwards can be found in asm/mach/map.h and are undefined
+ * for ioremap
+ */
+
+/*
+ * __arm_ioremap takes CPU physical address.
+ * __arm_ioremap_pfn takes a Page Frame Number and an offset into that page
+ */
+extern void __iomem * __arm_ioremap_pfn(unsigned long, unsigned long, size_t, unsigned int);
+extern void __iomem * __arm_ioremap(unsigned long, size_t, unsigned int);
 extern void __iounmap(volatile void __iomem *addr);
 
 /*
@@ -203,14 +212,14 @@ extern void _memset_io(volatile void __iomem *, int, size_t);
  *
  */
 #ifndef __arch_ioremap
-#define ioremap(cookie,size)            __ioremap(cookie,size,0)
-#define ioremap_nocache(cookie,size)    __ioremap(cookie,size,0)
-#define ioremap_cached(cookie,size)     __ioremap(cookie,size,L_PTE_CACHEABLE)
+#define ioremap(cookie,size)            __arm_ioremap(cookie, size, MT_DEVICE)
+#define ioremap_nocache(cookie,size)    __arm_ioremap(cookie, size, MT_DEVICE)
+#define ioremap_cached(cookie,size)     __arm_ioremap(cookie, size, MT_DEVICE_CACHED)
 #define iounmap(cookie)                 __iounmap(cookie)
 #else
-#define ioremap(cookie,size)            __arch_ioremap((cookie),(size),0)
-#define ioremap_nocache(cookie,size)    __arch_ioremap((cookie),(size),0)
-#define ioremap_cached(cookie,size)     __arch_ioremap((cookie),(size),L_PTE_CACHEABLE)
+#define ioremap(cookie,size)            __arch_ioremap((cookie), (size), MT_DEVICE)
+#define ioremap_nocache(cookie,size)    __arch_ioremap((cookie), (size), MT_DEVICE)
+#define ioremap_cached(cookie,size)     __arch_ioremap((cookie), (size), MT_DEVICE_CACHED)
 #define iounmap(cookie)                 __arch_iounmap(cookie)
 #endif
 
diff --git a/include/asm-arm/kdebug.h b/include/asm-arm/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-arm/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-arm/kexec.h b/include/asm-arm/kexec.h
index 8c1c6162a80c..b5b030ef633d 100644
--- a/include/asm-arm/kexec.h
+++ b/include/asm-arm/kexec.h
@@ -16,8 +16,6 @@
 
 #ifndef __ASSEMBLY__
 
-#define MAX_NOTE_BYTES 1024
-
 struct kimage;
 /* Provide a dummy definition to avoid build failures. */
 static inline void crash_setup_regs(struct pt_regs *newregs,
diff --git a/include/asm-arm/mach/map.h b/include/asm-arm/mach/map.h
index cef5364ed5fe..7ef3c8390180 100644
--- a/include/asm-arm/mach/map.h
+++ b/include/asm-arm/mach/map.h
@@ -9,6 +9,8 @@
  *
  *  Page table mapping constructs and function prototypes
  */
+#include <asm/io.h>
+
 struct map_desc {
         unsigned long virtual;
         unsigned long pfn;
@@ -16,15 +18,16 @@ struct map_desc {
         unsigned int type;
 };
 
-#define MT_DEVICE               0
-#define MT_CACHECLEAN           1
-#define MT_MINICLEAN            2
-#define MT_LOW_VECTORS          3
-#define MT_HIGH_VECTORS         4
-#define MT_MEMORY               5
-#define MT_ROM                  6
-#define MT_IXP2000_DEVICE       7
-#define MT_NONSHARED_DEVICE     8
+/* types 0-3 are defined in asm/io.h */
+#define MT_CACHECLEAN           4
+#define MT_MINICLEAN            5
+#define MT_LOW_VECTORS          6
+#define MT_HIGH_VECTORS         7
+#define MT_MEMORY               8
+#define MT_ROM                  9
+
+#define MT_NONSHARED_DEVICE     MT_DEVICE_NONSHARED
+#define MT_IXP2000_DEVICE       MT_DEVICE_IXP2000
 
 #ifdef CONFIG_MMU
 extern void iotable_init(struct map_desc *, int);
diff --git a/include/asm-arm/pgtable-nommu.h b/include/asm-arm/pgtable-nommu.h
index 7b1c9acdf79a..0c8be19fd66b 100644
--- a/include/asm-arm/pgtable-nommu.h
+++ b/include/asm-arm/pgtable-nommu.h
@@ -83,10 +83,6 @@ extern int is_in_rom(unsigned long);
 #define io_remap_page_range     remap_page_range
 #define io_remap_pfn_range      remap_pfn_range
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 
 /*
  * All 32bit addresses are effectively valid for vmalloc...
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 7b2bafce21a2..21dec9f258d8 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -395,10 +395,6 @@ extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
 #define io_remap_pfn_range(vma,from,pfn,size,prot) \
                 remap_pfn_range(vma, from, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #define pgtable_cache_init() do { } while (0)
 
 #endif /* !__ASSEMBLY__ */
diff --git a/include/asm-arm/plat-s3c24xx/clock.h b/include/asm-arm/plat-s3c24xx/clock.h
index f6135dbb9fa9..235b753cd877 100644
--- a/include/asm-arm/plat-s3c24xx/clock.h
+++ b/include/asm-arm/plat-s3c24xx/clock.h
@@ -56,6 +56,7 @@ extern struct mutex clocks_mutex;
 extern int s3c2410_clkcon_enable(struct clk *clk, int enable);
 
 extern int s3c24xx_register_clock(struct clk *clk);
+extern int s3c24xx_register_clocks(struct clk **clk, int nr_clks);
 
 extern int s3c24xx_setup_clocks(unsigned long xtal,
                                 unsigned long fclk,
diff --git a/include/asm-arm/plat-s3c24xx/cpu.h b/include/asm-arm/plat-s3c24xx/cpu.h
index 15dd18810905..23e420e8bd5b 100644
--- a/include/asm-arm/plat-s3c24xx/cpu.h
+++ b/include/asm-arm/plat-s3c24xx/cpu.h
@@ -40,22 +40,6 @@ extern void s3c24xx_init_uartdevs(char *name,
                                   struct s3c24xx_uart_resources *res,
                                   struct s3c2410_uartcfg *cfg, int no);
 
-/* the board structure is used at first initialsation time
- * to get info such as the devices to register for this
- * board. This is done because platfrom_add_devices() cannot
- * be called from the map_io entry.
-*/
-
-struct s3c24xx_board {
-        struct platform_device  **devices;
-        unsigned int              devices_count;
-
-        struct clk              **clocks;
-        unsigned int              clocks_count;
-};
-
-extern void s3c24xx_set_board(struct s3c24xx_board *board);
-
 /* timer for 2410/2440 */
 
 struct sys_timer;
diff --git a/include/asm-arm/ptrace.h b/include/asm-arm/ptrace.h
index 5a8ef787dbf8..2d0dad8c10ac 100644
--- a/include/asm-arm/ptrace.h
+++ b/include/asm-arm/ptrace.h
@@ -10,23 +10,19 @@
 #ifndef __ASM_ARM_PTRACE_H
 #define __ASM_ARM_PTRACE_H
 
-
 #define PTRACE_GETREGS          12
 #define PTRACE_SETREGS          13
 #define PTRACE_GETFPREGS        14
 #define PTRACE_SETFPREGS        15
-
+/* PTRACE_ATTACH is 16 */
+/* PTRACE_DETACH is 17 */
 #define PTRACE_GETWMMXREGS      18
 #define PTRACE_SETWMMXREGS      19
-
+/* 20 is unused */
 #define PTRACE_OLDSETOPTIONS    21
-
 #define PTRACE_GET_THREAD_AREA  22
-
 #define PTRACE_SET_SYSCALL      23
-
 /* PTRACE_SYSCALL is 24 */
-
 #define PTRACE_GETCRUNCHREGS    25
 #define PTRACE_SETCRUNCHREGS    26
 
diff --git a/include/asm-arm/system.h b/include/asm-arm/system.h
index 69134c7518c1..f2da3b6e3a83 100644
--- a/include/asm-arm/system.h
+++ b/include/asm-arm/system.h
@@ -76,6 +76,8 @@
 #include <linux/linkage.h>
 #include <linux/irqflags.h>
 
+#define __exception     __attribute__((section(".exception.text")))
+
 struct thread_info;
 struct task_struct;
 
@@ -91,7 +93,7 @@ void die(const char *msg, struct pt_regs *regs, int err)
                 __attribute__((noreturn));
 
 struct siginfo;
-void notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
+void arm_notify_die(const char *str, struct pt_regs *regs, struct siginfo *info,
                 unsigned long err, unsigned long trap);
 
 void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
@@ -101,8 +103,6 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
 #define xchg(ptr,x) \
         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
-#define tas(ptr) (xchg((ptr),1))
-
 extern asmlinkage void __backtrace(void);
 extern asmlinkage void c_backtrace(unsigned long fp, int pmode);
 
diff --git a/include/asm-arm/thread_info.h b/include/asm-arm/thread_info.h
index 5014794f9eb3..eae85b09db2e 100644
--- a/include/asm-arm/thread_info.h
+++ b/include/asm-arm/thread_info.h
@@ -57,6 +57,7 @@ struct thread_info {
         __u32                   cpu;            /* cpu */
         __u32                   cpu_domain;     /* cpu domain */
         struct cpu_context_save cpu_context;    /* cpu context */
+        __u32                   syscall;        /* syscall number */
         __u8                    used_cp[16];    /* thread used copro */
         unsigned long           tp_value;
         struct crunch_state     crunchstate;
diff --git a/include/asm-arm26/atomic.h b/include/asm-arm26/atomic.h
index 97e944fe1cff..d6dd42374cf3 100644
--- a/include/asm-arm26/atomic.h
+++ b/include/asm-arm26/atomic.h
@@ -20,7 +20,6 @@
 #ifndef __ASM_ARM_ATOMIC_H
 #define __ASM_ARM_ATOMIC_H
 
-
 #ifdef CONFIG_SMP
 #error SMP is NOT supported
 #endif
diff --git a/include/asm-arm26/kdebug.h b/include/asm-arm26/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-arm26/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-arm26/pgtable.h b/include/asm-arm26/pgtable.h
index 63a8881fae13..2b20e9f08857 100644
--- a/include/asm-arm26/pgtable.h
+++ b/include/asm-arm26/pgtable.h
@@ -297,10 +297,6 @@ static inline pte_t mk_pte_phys(unsigned long physpage, pgprot_t pgprot)
 #define io_remap_pfn_range(vma,from,pfn,size,prot) \
                 remap_pfn_range(vma, from, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #endif /* !__ASSEMBLY__ */
 
 #endif /* _ASMARM_PGTABLE_H */
diff --git a/include/asm-arm26/system.h b/include/asm-arm26/system.h
index 00ae32aa1dba..4703593b3bb5 100644
--- a/include/asm-arm26/system.h
+++ b/include/asm-arm26/system.h
@@ -52,8 +52,6 @@ void hook_fault_code(int nr, int (*fn)(unsigned long, unsigned int,
 #define xchg(ptr,x) \
         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
-#define tas(ptr) (xchg((ptr),1))
-
 extern asmlinkage void __backtrace(void);
 
 #define set_cr(x)                                       \
diff --git a/include/asm-avr32/kdebug.h b/include/asm-avr32/kdebug.h
index f583b643ffb2..de419278fc39 100644
--- a/include/asm-avr32/kdebug.h
+++ b/include/asm-avr32/kdebug.h
@@ -3,19 +3,6 @@
 
 #include <linux/notifier.h>
 
-struct pt_regs;
-
-struct die_args {
-        struct pt_regs *regs;
-        int trapnr;
-};
-
-int register_die_notifier(struct notifier_block *nb);
-int unregister_die_notifier(struct notifier_block *nb);
-int register_page_fault_notifier(struct notifier_block *nb);
-int unregister_page_fault_notifier(struct notifier_block *nb);
-extern struct atomic_notifier_head avr32_die_chain;
-
 /* Grossly misnamed. */
 enum die_val {
         DIE_FAULT,
@@ -24,15 +11,7 @@ enum die_val {
         DIE_PAGE_FAULT,
 };
 
-static inline int notify_die(enum die_val val, struct pt_regs *regs,
-                             int trap, int sig)
-{
-        struct die_args args = {
-                .regs = regs,
-                .trapnr = trap,
-        };
-
-        return atomic_notifier_call_chain(&avr32_die_chain, val, &args);
-}
+int register_page_fault_notifier(struct notifier_block *nb);
+int unregister_page_fault_notifier(struct notifier_block *nb);
 
 #endif /* __ASM_AVR32_KDEBUG_H */
diff --git a/include/asm-avr32/pgtable.h b/include/asm-avr32/pgtable.h
index 6b8ca9db2bd5..f6cc2b0f75c3 100644
--- a/include/asm-avr32/pgtable.h
+++ b/include/asm-avr32/pgtable.h
@@ -394,10 +394,6 @@ typedef pte_t *pte_addr_t;
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
         remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /* No page table caches to initialize (?) */
 #define pgtable_cache_init()    do { } while(0)
 
diff --git a/include/asm-blackfin/Kbuild b/include/asm-blackfin/Kbuild
new file mode 100644
index 000000000000..c68e1680da01
--- /dev/null
+++ b/include/asm-blackfin/Kbuild
@@ -0,0 +1 @@
+include include/asm-generic/Kbuild.asm
diff --git a/include/asm-blackfin/a.out.h b/include/asm-blackfin/a.out.h
new file mode 100644
index 000000000000..d37a6849bf74
--- /dev/null
+++ b/include/asm-blackfin/a.out.h
@@ -0,0 +1,25 @@
+#ifndef __BFIN_A_OUT_H__
+#define __BFIN_A_OUT_H__
+
+struct exec {
+        unsigned long a_info;   /* Use macros N_MAGIC, etc for access */
+        unsigned a_text;        /* length of text, in bytes */
+        unsigned a_data;        /* length of data, in bytes */
+        unsigned a_bss;         /* length of uninitialized data area for file, in bytes */
+        unsigned a_syms;        /* length of symbol table data in file, in bytes */
+        unsigned a_entry;       /* start address */
+        unsigned a_trsize;      /* length of relocation info for text, in bytes */
+        unsigned a_drsize;      /* length of relocation info for data, in bytes */
+};
+
+#define N_TRSIZE(a)     ((a).a_trsize)
+#define N_DRSIZE(a)     ((a).a_drsize)
+#define N_SYMSIZE(a)    ((a).a_syms)
+
+#ifdef __KERNEL__
+
+#define STACK_TOP       TASK_SIZE
+
+#endif
+
+#endif                          /* __BFIN_A_OUT_H__ */
diff --git a/include/asm-blackfin/atomic.h b/include/asm-blackfin/atomic.h
new file mode 100644
index 000000000000..7cf508718605
--- /dev/null
+++ b/include/asm-blackfin/atomic.h
@@ -0,0 +1,144 @@
+#ifndef __ARCH_BLACKFIN_ATOMIC__
+#define __ARCH_BLACKFIN_ATOMIC__
+
+#include <asm/system.h> /* local_irq_XXX() */
+
+/*
+ * Atomic operations that C can't guarantee us.  Useful for
+ * resource counting etc..
+ *
+ * Generally we do not concern about SMP BFIN systems, so we don't have
+ * to deal with that.
+ *
+ * Tony Kou (tonyko@lineo.ca)   Lineo Inc.   2001
+ */
+
+typedef struct {
+        int counter;
+} atomic_t;
+#define ATOMIC_INIT(i)  { (i) }
+
+#define atomic_read(v)          ((v)->counter)
+#define atomic_set(v, i)        (((v)->counter) = i)
+
+static __inline__ void atomic_add(int i, atomic_t * v)
+{
+        long flags;
+
+        local_irq_save(flags);
+        v->counter += i;
+        local_irq_restore(flags);
+}
+
+static __inline__ void atomic_sub(int i, atomic_t * v)
+{
+        long flags;
+
+        local_irq_save(flags);
+        v->counter -= i;
+        local_irq_restore(flags);
+
+}
+
+static inline int atomic_add_return(int i, atomic_t * v)
+{
+        int __temp = 0;
+        long flags;
+
+        local_irq_save(flags);
+        v->counter += i;
+        __temp = v->counter;
+        local_irq_restore(flags);
+
+
+        return __temp;
+}
+
+#define atomic_add_negative(a, v)       (atomic_add_return((a), (v)) < 0)
+static inline int atomic_sub_return(int i, atomic_t * v)
+{
+        int __temp = 0;
+        long flags;
+
+        local_irq_save(flags);
+        v->counter -= i;
+        __temp = v->counter;
+        local_irq_restore(flags);
+
+        return __temp;
+}
+
+static __inline__ void atomic_inc(volatile atomic_t * v)
+{
+        long flags;
+
+        local_irq_save(flags);
+        v->counter++;
+        local_irq_restore(flags);
+}
+
+#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+
+#define atomic_add_unless(v, a, u)                              \
+({                                                              \
+        int c, old;                                             \
+        c = atomic_read(v);                                     \
+        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
+                c = old;                                        \
+        c != (u);                                               \
+})
+#define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
+
+static __inline__ void atomic_dec(volatile atomic_t * v)
+{
+        long flags;
+
+        local_irq_save(flags);
+        v->counter--;
+        local_irq_restore(flags);
+}
+
+static __inline__ void atomic_clear_mask(unsigned int mask, atomic_t * v)
+{
+        long flags;
+
+        local_irq_save(flags);
+        v->counter &= ~mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void atomic_set_mask(unsigned int mask, atomic_t * v)
+{
+        long flags;
+
+        local_irq_save(flags);
+        v->counter |= mask;
+        local_irq_restore(flags);
+}
+
+/* Atomic operations are already serializing */
+#define smp_mb__before_atomic_dec()    barrier()
+#define smp_mb__after_atomic_dec() barrier()
+#define smp_mb__before_atomic_inc()    barrier()
+#define smp_mb__after_atomic_inc() barrier()
+
+#define atomic_dec_return(v) atomic_sub_return(1,(v))
+#define atomic_inc_return(v) atomic_add_return(1,(v))
+
+/*
+ * atomic_inc_and_test - increment and test
+ * @v: pointer of type atomic_t
+ *
+ * Atomically increments @v by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define atomic_inc_and_test(v) (atomic_inc_return(v) == 0)
+
+#define atomic_sub_and_test(i,v) (atomic_sub_return((i), (v)) == 0)
+#define atomic_dec_and_test(v) (atomic_sub_return(1, (v)) == 0)
+
+#include <asm-generic/atomic.h>
+
+#endif                          /* __ARCH_BLACKFIN_ATOMIC __ */
diff --git a/include/asm-blackfin/auxvec.h b/include/asm-blackfin/auxvec.h
new file mode 100644
index 000000000000..215506cd87b7
--- /dev/null
+++ b/include/asm-blackfin/auxvec.h
@@ -0,0 +1,4 @@
+#ifndef __ASMBFIN_AUXVEC_H
+#define __ASMBFIN_AUXVEC_H
+
+#endif
diff --git a/include/asm-blackfin/bf5xx_timers.h b/include/asm-blackfin/bf5xx_timers.h
new file mode 100644
index 000000000000..86c770321b61
--- /dev/null
+++ b/include/asm-blackfin/bf5xx_timers.h
@@ -0,0 +1,209 @@
+/*
+ * include/asm/bf5xx_timers.h
+ *
+ * This file contains the major Data structures and constants
+ * used for General Purpose Timer Implementation in BF5xx
+ *
+ * Copyright (C) 2005 John DeHority
+ * Copyright (C) 2006 Hella Aglaia GmbH (awe@aglaia-gmbh.de)
+ *
+ */
+
+#ifndef _BLACKFIN_TIMERS_H_
+#define _BLACKFIN_TIMERS_H_
+
+#undef MAX_BLACKFIN_GPTIMERS
+/*
+ * BF537: 8 timers:
+ */
+#if defined(CONFIG_BF537)
+#  define MAX_BLACKFIN_GPTIMERS 8
+#  define TIMER0_GROUP_REG     TIMER_ENABLE
+#endif
+/*
+ * BF561: 12 timers:
+ */
+#if defined(CONFIG_BF561)
+#  define MAX_BLACKFIN_GPTIMERS 12
+#  define TIMER0_GROUP_REG     TMRS8_ENABLE
+#  define TIMER8_GROUP_REG     TMRS4_ENABLE
+#endif
+/*
+ * All others: 3 timers:
+ */
+#if !defined(MAX_BLACKFIN_GPTIMERS)
+#  define MAX_BLACKFIN_GPTIMERS 3
+#  define TIMER0_GROUP_REG     TIMER_ENABLE
+#endif
+
+#define BLACKFIN_GPTIMER_IDMASK ((1UL << MAX_BLACKFIN_GPTIMERS) - 1)
+#define BFIN_TIMER_OCTET(x) ((x) >> 3)
+
+/* used in masks for timer_enable() and timer_disable() */
+#define TIMER0bit  0x0001  /*  0001b */
+#define TIMER1bit  0x0002  /*  0010b */
+#define TIMER2bit  0x0004  /*  0100b */
+
+#if (MAX_BLACKFIN_GPTIMERS > 3)
+#  define TIMER3bit  0x0008
+#  define TIMER4bit  0x0010
+#  define TIMER5bit  0x0020
+#  define TIMER6bit  0x0040
+#  define TIMER7bit  0x0080
+#endif
+
+#if (MAX_BLACKFIN_GPTIMERS > 8)
+#  define TIMER8bit  0x0100
+#  define TIMER9bit  0x0200
+#  define TIMER10bit 0x0400
+#  define TIMER11bit 0x0800
+#endif
+
+#define TIMER0_id   0
+#define TIMER1_id   1
+#define TIMER2_id   2
+
+#if (MAX_BLACKFIN_GPTIMERS > 3)
+#  define TIMER3_id   3
+#  define TIMER4_id   4
+#  define TIMER5_id   5
+#  define TIMER6_id   6
+#  define TIMER7_id   7
+#endif
+
+#if (MAX_BLACKFIN_GPTIMERS > 8)
+#  define TIMER8_id   8
+#  define TIMER9_id   9
+#  define TIMER10_id 10
+#  define TIMER11_id 11
+#endif
+
+/* associated timers for ppi framesync: */
+
+#if defined(CONFIG_BF561)
+#  define FS0_1_TIMER_ID   TIMER8_id
+#  define FS0_2_TIMER_ID   TIMER9_id
+#  define FS1_1_TIMER_ID   TIMER10_id
+#  define FS1_2_TIMER_ID   TIMER11_id
+#  define FS0_1_TIMER_BIT  TIMER8bit
+#  define FS0_2_TIMER_BIT  TIMER9bit
+#  define FS1_1_TIMER_BIT  TIMER10bit
+#  define FS1_2_TIMER_BIT  TIMER11bit
+#  undef FS1_TIMER_ID
+#  undef FS2_TIMER_ID
+#  undef FS1_TIMER_BIT
+#  undef FS2_TIMER_BIT
+#else
+#  define FS1_TIMER_ID  TIMER0_id
+#  define FS2_TIMER_ID  TIMER1_id
+#  define FS1_TIMER_BIT TIMER0bit
+#  define FS2_TIMER_BIT TIMER1bit
+#endif
+
+/*
+** Timer Configuration Register Bits
+*/
+#define TIMER_ERR           0xC000
+#define TIMER_ERR_OVFL      0x4000
+#define TIMER_ERR_PROG_PER  0x8000
+#define TIMER_ERR_PROG_PW   0xC000
+#define TIMER_EMU_RUN       0x0200
+#define TIMER_TOGGLE_HI     0x0100
+#define TIMER_CLK_SEL       0x0080
+#define TIMER_OUT_DIS       0x0040
+#define TIMER_TIN_SEL       0x0020
+#define TIMER_IRQ_ENA       0x0010
+#define TIMER_PERIOD_CNT    0x0008
+#define TIMER_PULSE_HI      0x0004
+#define TIMER_MODE          0x0003
+#define TIMER_MODE_PWM      0x0001
+#define TIMER_MODE_WDTH     0x0002
+#define TIMER_MODE_EXT_CLK  0x0003
+
+/*
+** Timer Status Register Bits
+*/
+#define TIMER_STATUS_TIMIL0 0x0001
+#define TIMER_STATUS_TIMIL1 0x0002
+#define TIMER_STATUS_TIMIL2 0x0004
+#if (MAX_BLACKFIN_GPTIMERS > 3)
+#  define TIMER_STATUS_TIMIL3 0x00000008
+#  define TIMER_STATUS_TIMIL4 0x00010000
+#  define TIMER_STATUS_TIMIL5 0x00020000
+#  define TIMER_STATUS_TIMIL6 0x00040000
+#  define TIMER_STATUS_TIMIL7 0x00080000
+#  if (MAX_BLACKFIN_GPTIMERS > 8)
+#    define TIMER_STATUS_TIMIL8  0x0001
+#    define TIMER_STATUS_TIMIL9  0x0002
+#    define TIMER_STATUS_TIMIL10 0x0004
+#    define TIMER_STATUS_TIMIL11 0x0008
+#  endif
+#  define TIMER_STATUS_INTR   0x000F000F
+#else
+#  define TIMER_STATUS_INTR   0x0007    /* any timer interrupt */
+#endif
+
+#define TIMER_STATUS_TOVF0  0x0010      /* timer 0 overflow error */
+#define TIMER_STATUS_TOVF1  0x0020
+#define TIMER_STATUS_TOVF2  0x0040
+#if (MAX_BLACKFIN_GPTIMERS > 3)
+#  define TIMER_STATUS_TOVF3  0x00000080
+#  define TIMER_STATUS_TOVF4  0x00100000
+#  define TIMER_STATUS_TOVF5  0x00200000
+#  define TIMER_STATUS_TOVF6  0x00400000
+#  define TIMER_STATUS_TOVF7  0x00800000
+#  if (MAX_BLACKFIN_GPTIMERS > 8)
+#    define TIMER_STATUS_TOVF8   0x0010
+#    define TIMER_STATUS_TOVF9   0x0020
+#    define TIMER_STATUS_TOVF10  0x0040
+#    define TIMER_STATUS_TOVF11  0x0080
+#  endif
+#  define TIMER_STATUS_OFLOW  0x00F000F0
+#else
+#  define TIMER_STATUS_OFLOW  0x0070    /* any timer overflow */
+#endif
+
+/*
+** Timer Slave Enable Status : write 1 to clear
+*/
+#define TIMER_STATUS_TRUN0  0x1000
+#define TIMER_STATUS_TRUN1  0x2000
+#define TIMER_STATUS_TRUN2  0x4000
+#if (MAX_BLACKFIN_GPTIMERS > 3)
+#  define TIMER_STATUS_TRUN3  0x00008000
+#  define TIMER_STATUS_TRUN4  0x10000000
+#  define TIMER_STATUS_TRUN5  0x20000000
+#  define TIMER_STATUS_TRUN6  0x40000000
+#  define TIMER_STATUS_TRUN7  0x80000000
+#  define TIMER_STATUS_TRUN   0xF000F000
+#  if (MAX_BLACKFIN_GPTIMERS > 8)
+#    define TIMER_STATUS_TRUN8  0x1000
+#    define TIMER_STATUS_TRUN9  0x2000
+#    define TIMER_STATUS_TRUN10 0x4000
+#    define TIMER_STATUS_TRUN11 0x8000
+#  endif
+#else
+#  define TIMER_STATUS_TRUN   0x7000
+#endif
+
+/*******************************************************************************
+*       GP_TIMER API's
+*******************************************************************************/
+
+void  set_gptimer_pwidth    (int timer_id, int width);
+int   get_gptimer_pwidth    (int timer_id);
+void  set_gptimer_period    (int timer_id, int period);
+int   get_gptimer_period    (int timer_id);
+int   get_gptimer_count     (int timer_id);
+short get_gptimer_intr      (int timer_id);
+void  set_gptimer_config    (int timer_id, short config);
+short get_gptimer_config    (int timer_id);
+void  set_gptimer_pulse_hi  (int timer_id);
+void  clear_gptimer_pulse_hi(int timer_id);
+void  enable_gptimers       (short mask);
+void  disable_gptimers      (short mask);
+short get_enabled_timers    (void);
+int   get_gptimer_status    (int octet);
+void  set_gptimer_status    (int octet, int value);
+
+#endif
diff --git a/include/asm-blackfin/bfin-global.h b/include/asm-blackfin/bfin-global.h
new file mode 100644
index 000000000000..e37f81609fc3
--- /dev/null
+++ b/include/asm-blackfin/bfin-global.h
@@ -0,0 +1,120 @@
+/*
+ * File:         include/asm-blackfin/bfin-global.h
+ * Based on:
+ * Author: *
+ * Created:
+ * Description:  Global extern defines for blackfin
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef _BFIN_GLOBAL_H_
+#define _BFIN_GLOBAL_H_
+
+#ifndef __ASSEMBLY__
+
+#include <asm-generic/sections.h>
+#include <asm/ptrace.h>
+#include <asm/user.h>
+#include <linux/linkage.h>
+#include <linux/types.h>
+
+#if defined(CONFIG_DMA_UNCACHED_2M)
+# define DMA_UNCACHED_REGION (2 * 1024 * 1024)
+#elif defined(CONFIG_DMA_UNCACHED_1M)
+# define DMA_UNCACHED_REGION (1024 * 1024)
+#else
+# define DMA_UNCACHED_REGION (0)
+#endif
+
+extern unsigned long get_cclk(void);
+extern unsigned long get_sclk(void);
+
+extern void dump_thread(struct pt_regs *regs, struct user *dump);
+extern void dump_bfin_regs(struct pt_regs *fp, void *retaddr);
+extern void dump_bfin_trace_buffer(void);
+
+extern int init_arch_irq(void);
+extern void bfin_reset(void);
+extern void _cplb_hdr(void);
+/* Blackfin cache functions */
+extern void bfin_icache_init(void);
+extern void bfin_dcache_init(void);
+extern int read_iloc(void);
+extern int bfin_console_init(void);
+extern asmlinkage void lower_to_irq14(void);
+extern void init_dma(void);
+extern void program_IAR(void);
+extern void evt14_softirq(void);
+extern asmlinkage void asm_do_IRQ(unsigned int irq, struct pt_regs *regs);
+extern void bfin_gpio_interrupt_setup(int irq, int irq_pfx, int type);
+
+extern void *l1_data_A_sram_alloc(size_t);
+extern void *l1_data_B_sram_alloc(size_t);
+extern void *l1_inst_sram_alloc(size_t);
+extern void *l1_data_sram_alloc(size_t);
+extern void *l1_data_sram_zalloc(size_t);
+extern int l1_data_A_sram_free(const void*);
+extern int l1_data_B_sram_free(const void*);
+extern int l1_inst_sram_free(const void*);
+extern int l1_data_sram_free(const void*);
+extern int sram_free(const void*);
+
+#define L1_INST_SRAM            0x00000001
+#define L1_DATA_A_SRAM          0x00000002
+#define L1_DATA_B_SRAM          0x00000004
+#define L1_DATA_SRAM            0x00000006
+extern void *sram_alloc_with_lsl(size_t, unsigned long);
+extern int sram_free_with_lsl(const void*);
+
+extern void led_on(int);
+extern void led_off(int);
+extern void led_toggle(int);
+extern void led_disp_num(int);
+extern void led_toggle_num(int);
+extern void init_leds(void);
+
+extern char *bfin_board_name __attribute__ ((weak));
+extern unsigned long wall_jiffies;
+extern unsigned long ipdt_table[];
+extern unsigned long dpdt_table[];
+extern unsigned long icplb_table[];
+extern unsigned long dcplb_table[];
+
+extern unsigned long ipdt_swapcount_table[];
+extern unsigned long dpdt_swapcount_table[];
+
+extern unsigned long table_start, table_end;
+
+extern struct file_operations dpmc_fops;
+extern char _start;
+extern unsigned long _ramstart, _ramend, _rambase;
+extern unsigned long memory_start, memory_end, physical_mem_end;
+extern char _stext_l1[], _etext_l1[], _sdata_l1[], _edata_l1[], _sbss_l1[],
+    _ebss_l1[], _l1_lma_start[], _sdata_b_l1[], _ebss_b_l1[];
+
+#ifdef CONFIG_MTD_UCLINUX
+extern unsigned long memory_mtd_start, memory_mtd_end, mtd_size;
+#endif
+
+#endif
+
+#endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bfin5xx_spi.h b/include/asm-blackfin/bfin5xx_spi.h
new file mode 100644
index 000000000000..95c1c952e7c1
--- /dev/null
+++ b/include/asm-blackfin/bfin5xx_spi.h
@@ -0,0 +1,170 @@
+/************************************************************
+*
+* Copyright (C) 2004, Analog Devices. All Rights Reserved
+*
+* FILE bfin5xx_spi.h
+* PROGRAMMER(S): Luke Yang (Analog Devices Inc.)
+*
+*
+* DATE OF CREATION: March. 10th 2006
+*
+* SYNOPSIS:
+*
+* DESCRIPTION: header file for SPI controller driver for Blackfin5xx.
+**************************************************************
+
+* MODIFICATION HISTORY:
+* March 10, 2006  bfin5xx_spi.h Created. (Luke Yang)
+
+************************************************************/
+
+#ifndef _SPI_CHANNEL_H_
+#define _SPI_CHANNEL_H_
+
+#define SPI0_REGBASE       0xffc00500
+
+#define SPI_READ              0
+#define SPI_WRITE             1
+
+#define SPI_CTRL_OFF            0x0
+#define SPI_FLAG_OFF            0x4
+#define SPI_STAT_OFF            0x8
+#define SPI_TXBUFF_OFF          0xc
+#define SPI_RXBUFF_OFF          0x10
+#define SPI_BAUD_OFF            0x14
+#define SPI_SHAW_OFF            0x18
+
+#define CMD_SPI_OUT_ENABLE    1
+#define CMD_SPI_SET_BAUDRATE  2
+#define CMD_SPI_SET_POLAR     3
+#define CMD_SPI_SET_PHASE     4
+#define CMD_SPI_SET_MASTER    5
+#define CMD_SPI_SET_SENDOPT   6
+#define CMD_SPI_SET_RECVOPT   7
+#define CMD_SPI_SET_ORDER     8
+#define CMD_SPI_SET_LENGTH16  9
+#define CMD_SPI_GET_STAT      11
+#define CMD_SPI_GET_CFG       12
+#define CMD_SPI_SET_CSAVAIL   13
+#define CMD_SPI_SET_CSHIGH    14        /* CS unavail */
+#define CMD_SPI_SET_CSLOW     15        /* CS avail */
+#define CMD_SPI_MISO_ENABLE   16
+#define CMD_SPI_SET_CSENABLE  17
+#define CMD_SPI_SET_CSDISABLE 18
+
+#define CMD_SPI_SET_TRIGGER_MODE  19
+#define CMD_SPI_SET_TRIGGER_SENSE 20
+#define CMD_SPI_SET_TRIGGER_EDGE  21
+#define CMD_SPI_SET_TRIGGER_LEVEL 22
+
+#define CMD_SPI_SET_TIME_SPS      23
+#define CMD_SPI_SET_TIME_SAMPLES  24
+#define CMD_SPI_GET_SYSTEMCLOCK   25
+
+#define CMD_SPI_SET_WRITECONTINUOUS     26
+#define CMD_SPI_SET_SKFS                27
+
+#define CMD_SPI_GET_ALLCONFIG 32        /* For debug */
+
+#define SPI_DEFAULT_BARD    0x0100
+
+#define SPI0_IRQ_NUM        IRQ_SPI
+#define SPI_ERR_TRIG       -1
+
+#define BIT_CTL_ENABLE      0x4000
+#define BIT_CTL_OPENDRAIN   0x2000
+#define BIT_CTL_MASTER      0x1000
+#define BIT_CTL_POLAR       0x0800
+#define BIT_CTL_PHASE       0x0400
+#define BIT_CTL_BITORDER    0x0200
+#define BIT_CTL_WORDSIZE    0x0100
+#define BIT_CTL_MISOENABLE  0x0020
+#define BIT_CTL_RXMOD       0x0000
+#define BIT_CTL_TXMOD       0x0001
+#define BIT_CTL_TIMOD_DMA_TX 0x0003
+#define BIT_CTL_TIMOD_DMA_RX 0x0002
+#define BIT_CTL_SENDOPT     0x0004
+#define BIT_CTL_TIMOD       0x0003
+
+#define BIT_STAT_SPIF       0x0001
+#define BIT_STAT_MODF       0x0002
+#define BIT_STAT_TXE        0x0004
+#define BIT_STAT_TXS        0x0008
+#define BIT_STAT_RBSY       0x0010
+#define BIT_STAT_RXS        0x0020
+#define BIT_STAT_TXCOL      0x0040
+#define BIT_STAT_CLR        0xFFFF
+
+#define BIT_STU_SENDOVER    0x0001
+#define BIT_STU_RECVFULL    0x0020
+
+#define CFG_SPI_ENABLE      1
+#define CFG_SPI_DISABLE     0
+
+#define CFG_SPI_OUTENABLE   1
+#define CFG_SPI_OUTDISABLE  0
+
+#define CFG_SPI_ACTLOW      1
+#define CFG_SPI_ACTHIGH     0
+
+#define CFG_SPI_PHASESTART  1
+#define CFG_SPI_PHASEMID    0
+
+#define CFG_SPI_MASTER      1
+#define CFG_SPI_SLAVE       0
+
+#define CFG_SPI_SENELAST    0
+#define CFG_SPI_SENDZERO    1
+
+#define CFG_SPI_RCVFLUSH    1
+#define CFG_SPI_RCVDISCARD  0
+
+#define CFG_SPI_LSBFIRST    1
+#define CFG_SPI_MSBFIRST    0
+
+#define CFG_SPI_WORDSIZE16  1
+#define CFG_SPI_WORDSIZE8   0
+
+#define CFG_SPI_MISOENABLE   1
+#define CFG_SPI_MISODISABLE  0
+
+#define CFG_SPI_READ      0x00
+#define CFG_SPI_WRITE     0x01
+#define CFG_SPI_DMAREAD   0x02
+#define CFG_SPI_DMAWRITE  0x03
+
+#define CFG_SPI_CSCLEARALL  0
+#define CFG_SPI_CHIPSEL1    1
+#define CFG_SPI_CHIPSEL2    2
+#define CFG_SPI_CHIPSEL3    3
+#define CFG_SPI_CHIPSEL4    4
+#define CFG_SPI_CHIPSEL5    5
+#define CFG_SPI_CHIPSEL6    6
+#define CFG_SPI_CHIPSEL7    7
+
+#define CFG_SPI_CS1VALUE    1
+#define CFG_SPI_CS2VALUE    2
+#define CFG_SPI_CS3VALUE    3
+#define CFG_SPI_CS4VALUE    4
+#define CFG_SPI_CS5VALUE    5
+#define CFG_SPI_CS6VALUE    6
+#define CFG_SPI_CS7VALUE    7
+
+/* device.platform_data for SSP controller devices */
+struct bfin5xx_spi_master {
+        u16 num_chipselect;
+        u8 enable_dma;
+};
+
+/* spi_board_info.controller_data for SPI slave devices,
+ * copied to spi_device.platform_data ... mostly for dma tuning
+ */
+struct bfin5xx_spi_chip {
+        u16 ctl_reg;
+        u8 enable_dma;
+        u8 bits_per_word;
+        u8 cs_change_per_word;
+        u8 cs_chg_udelay;
+};
+
+#endif /* _SPI_CHANNEL_H_ */
diff --git a/include/asm-blackfin/bfin_simple_timer.h b/include/asm-blackfin/bfin_simple_timer.h
new file mode 100644
index 000000000000..fccbb595464a
--- /dev/null
+++ b/include/asm-blackfin/bfin_simple_timer.h
@@ -0,0 +1,13 @@
+#ifndef _bfin_simple_timer_h_
+#define _bfin_simple_timer_h_
+
+#include <linux/ioctl.h>
+
+#define BFIN_SIMPLE_TIMER_IOCTL_MAGIC 't'
+
+#define BFIN_SIMPLE_TIMER_SET_PERIOD _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  2)
+#define BFIN_SIMPLE_TIMER_START      _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  6)
+#define BFIN_SIMPLE_TIMER_STOP       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC,  8)
+#define BFIN_SIMPLE_TIMER_READ       _IO (BFIN_SIMPLE_TIMER_IOCTL_MAGIC, 10)
+
+#endif
diff --git a/include/asm-blackfin/bfin_sport.h b/include/asm-blackfin/bfin_sport.h
new file mode 100644
index 000000000000..c76ed8def302
--- /dev/null
+++ b/include/asm-blackfin/bfin_sport.h
@@ -0,0 +1,175 @@
+/*
+ * File:         include/asm-blackfin/bfin_sport.h
+ * Based on:
+ * Author:       Roy Huang (roy.huang@analog.com)
+ *
+ * Created:      Thu Aug. 24 2006
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __BFIN_SPORT_H__
+#define __BFIN_SPORT_H__
+
+#define SPORT_MAJOR     237
+#define SPORT_NR_DEVS   2
+
+/* Sport mode: it can be set to TDM, i2s or others */
+#define NORM_MODE       0x0
+#define TDM_MODE        0x1
+#define I2S_MODE        0x2
+
+/* Data format, normal, a-law or u-law */
+#define NORM_FORMAT     0x0
+#define ALAW_FORMAT     0x2
+#define ULAW_FORMAT     0x3
+struct sport_register;
+
+/* Function driver which use sport must initialize the structure */
+struct sport_config {
+        /*TDM (multichannels), I2S or other mode */
+        unsigned int mode:3;
+
+        /* if TDM mode is selected, channels must be set */
+        int channels;           /* Must be in 8 units */
+        unsigned int frame_delay:4;     /* Delay between frame sync pulse and first bit */
+
+        /* I2S mode */
+        unsigned int right_first:1;     /* Right stereo channel first */
+
+        /* In mormal mode, the following item need to be set */
+        unsigned int lsb_first:1;       /* order of transmit or receive data */
+        unsigned int fsync:1;   /* Frame sync required */
+        unsigned int data_indep:1;      /* data independent frame sync generated */
+        unsigned int act_low:1; /* Active low TFS */
+        unsigned int late_fsync:1;      /* Late frame sync */
+        unsigned int tckfe:1;
+        unsigned int sec_en:1;  /* Secondary side enabled */
+
+        /* Choose clock source */
+        unsigned int int_clk:1; /* Internal or external clock */
+
+        /* If external clock is used, the following fields are ignored */
+        int serial_clk;
+        int fsync_clk;
+
+        unsigned int data_format:2;     /*Normal, u-law or a-law */
+
+        int word_len;           /* How length of the word in bits, 3-32 bits */
+        int dma_enabled;
+};
+
+struct sport_register {
+        unsigned short tcr1;
+        unsigned short reserved0;
+        unsigned short tcr2;
+        unsigned short reserved1;
+        unsigned short tclkdiv;
+        unsigned short reserved2;
+        unsigned short tfsdiv;
+        unsigned short reserved3;
+        unsigned long tx;
+        unsigned long reserved_l0;
+        unsigned long rx;
+        unsigned long reserved_l1;
+        unsigned short rcr1;
+        unsigned short reserved4;
+        unsigned short rcr2;
+        unsigned short reserved5;
+        unsigned short rclkdiv;
+        unsigned short reserved6;
+        unsigned short rfsdiv;
+        unsigned short reserved7;
+        unsigned short stat;
+        unsigned short reserved8;
+        unsigned short chnl;
+        unsigned short reserved9;
+        unsigned short mcmc1;
+        unsigned short reserved10;
+        unsigned short mcmc2;
+        unsigned short reserved11;
+        unsigned long mtcs0;
+        unsigned long mtcs1;
+        unsigned long mtcs2;
+        unsigned long mtcs3;
+        unsigned long mrcs0;
+        unsigned long mrcs1;
+        unsigned long mrcs2;
+        unsigned long mrcs3;
+};
+
+#define SPORT_IOC_MAGIC         'P'
+#define SPORT_IOC_CONFIG        _IOWR('P', 0x01, struct sport_config)
+
+/* Test purpose */
+#define ENABLE_AD73311          _IOWR('P', 0x02, int)
+
+struct sport_dev {
+        struct cdev cdev;       /* Char device structure */
+
+        int sport_num;
+
+        int dma_rx_chan;
+        int dma_tx_chan;
+
+        int rx_irq;
+        unsigned char *rx_buf;  /* Buffer store the received data */
+        int rx_len;             /* How many bytes will be received */
+        int rx_received;        /* How many bytes has been received */
+
+        int tx_irq;
+        const unsigned char *tx_buf;
+        int tx_len;
+        int tx_sent;
+
+        int sport_err_irq;
+
+        struct mutex mutex;     /* mutual exclusion semaphore */
+        struct task_struct *task;
+
+        wait_queue_head_t waitq;
+        int     wait_con;
+        struct sport_register *regs;
+        struct sport_config config;
+};
+
+#define SPORT_TCR1      0
+#define SPORT_TCR2      1
+#define SPORT_TCLKDIV   2
+#define SPORT_TFSDIV    3
+#define SPORT_RCR1      8
+#define SPORT_RCR2      9
+#define SPORT_RCLKDIV   10
+#define SPORT_RFSDIV    11
+#define SPORT_CHANNEL   13
+#define SPORT_MCMC1     14
+#define SPORT_MCMC2     15
+#define SPORT_MTCS0     16
+#define SPORT_MTCS1     17
+#define SPORT_MTCS2     18
+#define SPORT_MTCS3     19
+#define SPORT_MRCS0     20
+#define SPORT_MRCS1     21
+#define SPORT_MRCS2     22
+#define SPORT_MRCS3     23
+
+#endif                          /*__BFIN_SPORT_H__*/
diff --git a/include/asm-blackfin/bitops.h b/include/asm-blackfin/bitops.h
new file mode 100644
index 000000000000..27c2d0e48e1b
--- /dev/null
+++ b/include/asm-blackfin/bitops.h
@@ -0,0 +1,213 @@
+#ifndef _BLACKFIN_BITOPS_H
+#define _BLACKFIN_BITOPS_H
+
+/*
+ * Copyright 1992, Linus Torvalds.
+ */
+
+#include <linux/compiler.h>
+#include <asm/byteorder.h>      /* swab32 */
+#include <asm/system.h>         /* save_flags */
+
+#ifdef __KERNEL__
+
+#include <asm-generic/bitops/ffs.h>
+#include <asm-generic/bitops/__ffs.h>
+#include <asm-generic/bitops/sched.h>
+#include <asm-generic/bitops/ffz.h>
+
+static __inline__ void set_bit(int nr, volatile unsigned long *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a |= mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void __set_bit(int nr, volatile unsigned long *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        *a |= mask;
+}
+
+/*
+ * clear_bit() doesn't provide any barrier for the compiler.
+ */
+#define smp_mb__before_clear_bit()      barrier()
+#define smp_mb__after_clear_bit()       barrier()
+
+static __inline__ void clear_bit(int nr, volatile unsigned long *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+        unsigned long flags;
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        *a &= ~mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void __clear_bit(int nr, volatile unsigned long *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        *a &= ~mask;
+}
+
+static __inline__ void change_bit(int nr, volatile unsigned long *addr)
+{
+        int mask, flags;
+        unsigned long *ADDR = (unsigned long *)addr;
+
+        ADDR += nr >> 5;
+        mask = 1 << (nr & 31);
+        local_irq_save(flags);
+        *ADDR ^= mask;
+        local_irq_restore(flags);
+}
+
+static __inline__ void __change_bit(int nr, volatile unsigned long *addr)
+{
+        int mask;
+        unsigned long *ADDR = (unsigned long *)addr;
+
+        ADDR += nr >> 5;
+        mask = 1 << (nr & 31);
+        *ADDR ^= mask;
+}
+
+static __inline__ int test_and_set_bit(int nr, void *addr)
+{
+        int mask, retval;
+        volatile unsigned int *a = (volatile unsigned int *)addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a |= mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static __inline__ int __test_and_set_bit(int nr, volatile unsigned long *addr)
+{
+        int mask, retval;
+        volatile unsigned int *a = (volatile unsigned int *)addr;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        retval = (mask & *a) != 0;
+        *a |= mask;
+        return retval;
+}
+
+static __inline__ int test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+        int mask, retval;
+        volatile unsigned int *a = (volatile unsigned int *)addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a &= ~mask;
+        local_irq_restore(flags);
+
+        return retval;
+}
+
+static __inline__ int __test_and_clear_bit(int nr, volatile unsigned long *addr)
+{
+        int mask, retval;
+        volatile unsigned int *a = (volatile unsigned int *)addr;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        retval = (mask & *a) != 0;
+        *a &= ~mask;
+        return retval;
+}
+
+static __inline__ int test_and_change_bit(int nr, volatile unsigned long *addr)
+{
+        int mask, retval;
+        volatile unsigned int *a = (volatile unsigned int *)addr;
+        unsigned long flags;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        local_irq_save(flags);
+        retval = (mask & *a) != 0;
+        *a ^= mask;
+        local_irq_restore(flags);
+        return retval;
+}
+
+static __inline__ int __test_and_change_bit(int nr,
+                                            volatile unsigned long *addr)
+{
+        int mask, retval;
+        volatile unsigned int *a = (volatile unsigned int *)addr;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        retval = (mask & *a) != 0;
+        *a ^= mask;
+        return retval;
+}
+
+/*
+ * This routine doesn't need to be atomic.
+ */
+static __inline__ int __constant_test_bit(int nr, const void *addr)
+{
+        return ((1UL << (nr & 31)) &
+                (((const volatile unsigned int *)addr)[nr >> 5])) != 0;
+}
+
+static __inline__ int __test_bit(int nr, const void *addr)
+{
+        int *a = (int *)addr;
+        int mask;
+
+        a += nr >> 5;
+        mask = 1 << (nr & 0x1f);
+        return ((mask & *a) != 0);
+}
+
+#define test_bit(nr,addr) \
+(__builtin_constant_p(nr) ? \
+ __constant_test_bit((nr),(addr)) : \
+ __test_bit((nr),(addr)))
+
+#include <asm-generic/bitops/find.h>
+#include <asm-generic/bitops/hweight.h>
+
+#include <asm-generic/bitops/ext2-atomic.h>
+#include <asm-generic/bitops/ext2-non-atomic.h>
+
+#include <asm-generic/bitops/minix.h>
+
+#endif                          /* __KERNEL__ */
+
+#include <asm-generic/bitops/fls.h>
+#include <asm-generic/bitops/fls64.h>
+
+#endif                          /* _BLACKFIN_BITOPS_H */
diff --git a/include/asm-blackfin/blackfin.h b/include/asm-blackfin/blackfin.h
new file mode 100644
index 000000000000..14e58de73973
--- /dev/null
+++ b/include/asm-blackfin/blackfin.h
@@ -0,0 +1,81 @@
+/*
+ * Common header file for blackfin family of processors.
+ *
+ */
+
+#ifndef _BLACKFIN_H_
+#define _BLACKFIN_H_
+
+#include <asm/macros.h>
+#include <asm/mach/blackfin.h>
+#include <asm/bfin-global.h>
+
+#ifndef __ASSEMBLY__
+
+/* SSYNC implementation for C file */
+#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+static inline void SSYNC (void)
+{
+        int _tmp;
+        __asm__ __volatile__ ("cli %0;\n\t"
+                        "nop;nop;\n\t"
+                        "ssync;\n\t"
+                        "sti %0;\n\t"
+                        :"=d"(_tmp):);
+}
+#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+static inline void SSYNC (void)
+{
+        int _tmp;
+        __asm__ __volatile__ ("cli %0;\n\t"
+                        "ssync;\n\t"
+                        "sti %0;\n\t"
+                        :"=d"(_tmp):);
+}
+#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+static inline void SSYNC (void)
+{
+        __builtin_bfin_ssync();
+}
+#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+static inline void SSYNC (void)
+{
+        __asm__ __volatile__ ("ssync;\n\t");
+}
+#endif
+
+/* CSYNC implementation for C file */
+#if defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+static inline void CSYNC (void)
+{
+        int _tmp;
+        __asm__ __volatile__ ("cli %0;\n\t"
+                        "nop;nop;\n\t"
+                        "csync;\n\t"
+                        "sti %0;\n\t"
+                        :"=d"(_tmp):);
+}
+#elif defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+static inline void CSYNC (void)
+{
+        int _tmp;
+        __asm__ __volatile__ ("cli %0;\n\t"
+                        "csync;\n\t"
+                        "sti %0;\n\t"
+                        :"=d"(_tmp):);
+}
+#elif !defined(ANOMALY_05000312) && defined(ANOMALY_05000244)
+static inline void CSYNC (void)
+{
+        __builtin_bfin_csync();
+}
+#elif !defined(ANOMALY_05000312) && !defined(ANOMALY_05000244)
+static inline void CSYNC (void)
+{
+        __asm__ __volatile__ ("csync;\n\t");
+}
+#endif
+
+#endif /* __ASSEMBLY__ */
+
+#endif                          /* _BLACKFIN_H_ */
diff --git a/include/asm-blackfin/bug.h b/include/asm-blackfin/bug.h
new file mode 100644
index 000000000000..41e53b29f167
--- /dev/null
+++ b/include/asm-blackfin/bug.h
@@ -0,0 +1,4 @@
+#ifndef _BLACKFIN_BUG_H
+#define _BLACKFIN_BUG_H
+#include <asm-generic/bug.h>
+#endif
diff --git a/include/asm-blackfin/bugs.h b/include/asm-blackfin/bugs.h
new file mode 100644
index 000000000000..9093c9c1fb81
--- /dev/null
+++ b/include/asm-blackfin/bugs.h
@@ -0,0 +1,16 @@
+/*
+ *  include/asm-blackfin/bugs.h
+ *
+ *  Copyright (C) 1994  Linus Torvalds
+ */
+
+/*
+ * This is included by init/main.c to check for architecture-dependent bugs.
+ *
+ * Needs:
+ *      void check_bugs(void);
+ */
+
+static void check_bugs(void)
+{
+}
diff --git a/include/asm-blackfin/byteorder.h b/include/asm-blackfin/byteorder.h
new file mode 100644
index 000000000000..6a673d42da18
--- /dev/null
+++ b/include/asm-blackfin/byteorder.h
@@ -0,0 +1,48 @@
+#ifndef _BLACKFIN_BYTEORDER_H
+#define _BLACKFIN_BYTEORDER_H
+
+#include <asm/types.h>
+#include <linux/compiler.h>
+
+#ifdef __GNUC__
+
+static __inline__ __attribute_const__ __u32 ___arch__swahb32(__u32 xx)
+{
+        __u32 tmp;
+        __asm__("%1 = %0 >> 8 (V);\n\t"
+                "%0 = %0 << 8 (V);\n\t"
+                "%0 = %0 | %1;\n\t"
+                : "+d"(xx), "=&d"(tmp));
+        return xx;
+}
+
+static __inline__ __attribute_const__ __u32 ___arch__swahw32(__u32 xx)
+{
+        __u32 rv;
+        __asm__("%0 = PACK(%1.L, %1.H);\n\t": "=d"(rv): "d"(xx));
+        return rv;
+}
+
+#define __arch__swahb32(x) ___arch__swahb32(x)
+#define __arch__swahw32(x) ___arch__swahw32(x)
+#define __arch__swab32(x) ___arch__swahb32(___arch__swahw32(x))
+
+static __inline__ __attribute_const__ __u16 ___arch__swab16(__u16 xx)
+{
+        __u32 xw = xx;
+        __asm__("%0 <<= 8;\n    %0.L = %0.L + %0.H (NS);\n": "+d"(xw));
+        return (__u16)xw;
+}
+
+#define __arch__swab16(x) ___arch__swab16(x)
+
+#endif
+
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
+#  define __BYTEORDER_HAS_U64__
+#  define __SWAB_64_THRU_32__
+#endif
+
+#include <linux/byteorder/little_endian.h>
+
+#endif                          /* _BLACKFIN_BYTEORDER_H */
diff --git a/include/asm-blackfin/cache.h b/include/asm-blackfin/cache.h
new file mode 100644
index 000000000000..023d72133b5a
--- /dev/null
+++ b/include/asm-blackfin/cache.h
@@ -0,0 +1,29 @@
+/*
+ * include/asm-blackfin/cache.h
+ */
+#ifndef __ARCH_BLACKFIN_CACHE_H
+#define __ARCH_BLACKFIN_CACHE_H
+
+/*
+ * Bytes per L1 cache line
+ * Blackfin loads 32 bytes for cache
+ */
+#define L1_CACHE_SHIFT  5
+#define L1_CACHE_BYTES  (1 << L1_CACHE_SHIFT)
+#define SMP_CACHE_BYTES L1_CACHE_BYTES
+
+/*
+ * Put cacheline_aliged data to L1 data memory
+ */
+#ifdef CONFIG_CACHELINE_ALIGNED_L1
+#define __cacheline_aligned                             \
+          __attribute__((__aligned__(L1_CACHE_BYTES),   \
+                __section__(".data_l1.cacheline_aligned")))
+#endif
+
+/*
+ * largest L1 which this arch supports
+ */
+#define L1_CACHE_SHIFT_MAX      5
+
+#endif
diff --git a/include/asm-blackfin/cacheflush.h b/include/asm-blackfin/cacheflush.h
new file mode 100644
index 000000000000..e5e000de3c36
--- /dev/null
+++ b/include/asm-blackfin/cacheflush.h
@@ -0,0 +1,90 @@
+/*
+ * File:         include/asm-blackfin/cacheflush.h
+ * Based on:     include/asm-m68knommu/cacheflush.h
+ * Author:       LG Soft India
+ *               Copyright (C) 2004 Analog Devices Inc.
+ * Created:      Tue Sep 21 2004
+ * Description:  Blackfin low-level cache routines adapted from the i386
+ *               and PPC versions by Greg Ungerer (gerg@snapgear.com)
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BLACKFIN_CACHEFLUSH_H
+#define _BLACKFIN_CACHEFLUSH_H
+
+#include <asm/cplb.h>
+
+extern void blackfin_icache_dcache_flush_range(unsigned int, unsigned int);
+extern void blackfin_icache_flush_range(unsigned int, unsigned int);
+extern void blackfin_dcache_flush_range(unsigned int, unsigned int);
+extern void blackfin_dcache_invalidate_range(unsigned int, unsigned int);
+extern void blackfin_dflush_page(void *);
+
+#define flush_dcache_mmap_lock(mapping)         do { } while (0)
+#define flush_dcache_mmap_unlock(mapping)       do { } while (0)
+#define flush_cache_mm(mm)                      do { } while (0)
+#define flush_cache_range(vma, start, end)      do { } while (0)
+#define flush_cache_page(vma, vmaddr)           do { } while (0)
+#define flush_cache_vmap(start, end)            do { } while (0)
+#define flush_cache_vunmap(start, end)          do { } while (0)
+
+static inline void flush_icache_range(unsigned start, unsigned end)
+{
+#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_CACHE)
+
+# if defined(CONFIG_BLKFIN_WT)
+        blackfin_icache_flush_range((start), (end));
+# else
+        blackfin_icache_dcache_flush_range((start), (end));
+# endif
+
+#else
+
+# if defined(CONFIG_BLKFIN_CACHE)
+        blackfin_icache_flush_range((start), (end));
+# endif
+# if defined(CONFIG_BLKFIN_DCACHE)
+        blackfin_dcache_flush_range((start), (end));
+# endif
+
+#endif
+}
+
+#define copy_to_user_page(vma, page, vaddr, dst, src, len) \
+do { memcpy(dst, src, len); \
+     flush_icache_range ((unsigned) (dst), (unsigned) (dst) + (len)); \
+} while (0)
+#define copy_from_user_page(vma, page, vaddr, dst, src, len)    memcpy(dst, src, len)
+
+#if defined(CONFIG_BLKFIN_DCACHE)
+# define invalidate_dcache_range(start,end)     blackfin_dcache_invalidate_range((start), (end))
+#else
+# define invalidate_dcache_range(start,end)     do { } while (0)
+#endif
+#if defined(CONFIG_BLKFIN_DCACHE) && defined(CONFIG_BLKFIN_WB)
+# define flush_dcache_range(start,end)          blackfin_dcache_flush_range((start), (end))
+# define flush_dcache_page(page)                        blackfin_dflush_page(page_address(page))
+#else
+# define flush_dcache_range(start,end)          do { } while (0)
+# define flush_dcache_page(page)                        do { } while (0)
+#endif
+
+#endif                          /* _BLACKFIN_CACHEFLUSH_H */
diff --git a/include/asm-blackfin/checksum.h b/include/asm-blackfin/checksum.h
new file mode 100644
index 000000000000..2638f2586d2f
--- /dev/null
+++ b/include/asm-blackfin/checksum.h
@@ -0,0 +1,101 @@
+#ifndef _BFIN_CHECKSUM_H
+#define _BFIN_CHECKSUM_H
+
+/*
+ * MODIFIED FOR BFIN April 30, 2001 akbar.hussain@lineo.com
+ *
+ * computes the checksum of a memory block at buff, length len,
+ * and adds in "sum" (32-bit)
+ *
+ * returns a 32-bit number suitable for feeding into itself
+ * or csum_tcpudp_magic
+ *
+ * this function must be called with even lengths, except
+ * for the last fragment, which may be odd
+ *
+ * it's best to have buff aligned on a 32-bit boundary
+ */
+unsigned int csum_partial(const unsigned char *buff, int len, unsigned int sum);
+
+/*
+ * the same as csum_partial, but copies from src while it
+ * checksums
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+unsigned int csum_partial_copy(const unsigned char *src, unsigned char *dst,
+                               int len, int sum);
+
+/*
+ * the same as csum_partial_copy, but copies from user space.
+ *
+ * here even more important to align src and dst on a 32-bit (or even
+ * better 64-bit) boundary
+ */
+
+extern unsigned int csum_partial_copy_from_user(const unsigned char *src,
+                                                unsigned char *dst, int len,
+                                                int sum, int *csum_err);
+
+#define csum_partial_copy_nocheck(src, dst, len, sum)   \
+        csum_partial_copy((src), (dst), (len), (sum))
+
+unsigned short ip_fast_csum(unsigned char *iph, unsigned int ihl);
+
+/*
+ *      Fold a partial checksum
+ */
+
+static inline unsigned int csum_fold(unsigned int sum)
+{
+        while (sum >> 16)
+                sum = (sum & 0xffff) + (sum >> 16);
+        return ((~(sum << 16)) >> 16);
+}
+
+/*
+ * computes the checksum of the TCP/UDP pseudo-header
+ * returns a 16-bit checksum, already complemented
+ */
+
+static inline unsigned int
+csum_tcpudp_nofold(unsigned long saddr, unsigned long daddr, unsigned short len,
+                   unsigned short proto, unsigned int sum)
+{
+
+        __asm__ ("%0 = %0 + %1;\n\t"
+                 "CC = AC0;\n\t"
+                 "if !CC jump 4;\n\t"
+                 "%0 = %0 + %4;\n\t"
+                 "%0 = %0 + %2;\n\t"
+                 "CC = AC0;\n\t"
+                 "if !CC jump 4;\n\t"
+                 "%0 = %0 + %4;\n\t"
+                 "%0 = %0 + %3;\n\t"
+                 "CC = AC0;\n\t"
+                 "if !CC jump 4;\n\t"
+                 "%0 = %0 + %4;\n\t"
+                 "NOP;\n\t"
+                 : "=d" (sum)
+                 : "d" (daddr), "d" (saddr), "d" ((ntohs(len)<<16)+proto*256), "d" (1), "0"(sum));
+
+        return (sum);
+}
+
+static inline unsigned short int
+csum_tcpudp_magic(unsigned long saddr, unsigned long daddr, unsigned short len,
+                  unsigned short proto, unsigned int sum)
+{
+        return csum_fold(csum_tcpudp_nofold(saddr, daddr, len, proto, sum));
+}
+
+/*
+ * this routine is used for miscellaneous IP-like checksums, mainly
+ * in icmp.c
+ */
+
+extern unsigned short ip_compute_csum(const unsigned char *buff, int len);
+
+#endif                          /* _BFIN_CHECKSUM_H */
diff --git a/include/asm-blackfin/cplb.h b/include/asm-blackfin/cplb.h
new file mode 100644
index 000000000000..e0dd56bfa4c7
--- /dev/null
+++ b/include/asm-blackfin/cplb.h
@@ -0,0 +1,51 @@
+/************************************************************************
+ *
+ * cplb.h
+ *
+ * (c) Copyright 2002-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+/* Defines necessary for cplb initialisation routines. */
+
+#ifndef _CPLB_H
+#define _CPLB_H
+
+# include <asm/blackfin.h>
+
+#define CPLB_ENABLE_ICACHE_P    0
+#define CPLB_ENABLE_DCACHE_P    1
+#define CPLB_ENABLE_DCACHE2_P   2
+#define CPLB_ENABLE_CPLBS_P     3       /* Deprecated! */
+#define CPLB_ENABLE_ICPLBS_P    4
+#define CPLB_ENABLE_DCPLBS_P    5
+
+#define CPLB_ENABLE_ICACHE      (1<<CPLB_ENABLE_ICACHE_P)
+#define CPLB_ENABLE_DCACHE      (1<<CPLB_ENABLE_DCACHE_P)
+#define CPLB_ENABLE_DCACHE2     (1<<CPLB_ENABLE_DCACHE2_P)
+#define CPLB_ENABLE_CPLBS       (1<<CPLB_ENABLE_CPLBS_P)
+#define CPLB_ENABLE_ICPLBS      (1<<CPLB_ENABLE_ICPLBS_P)
+#define CPLB_ENABLE_DCPLBS      (1<<CPLB_ENABLE_DCPLBS_P)
+#define CPLB_ENABLE_ANY_CPLBS   CPLB_ENABLE_CPLBS | \
+                                CPLB_ENABLE_ICPLBS | \
+                                CPLB_ENABLE_DCPLBS
+
+#define CPLB_RELOADED           0x0000
+#define CPLB_NO_UNLOCKED        0x0001
+#define CPLB_NO_ADDR_MATCH      0x0002
+#define CPLB_PROT_VIOL          0x0003
+#define CPLB_UNKNOWN_ERR        0x0004
+
+#define CPLB_DEF_CACHE          CPLB_L1_CHBL | CPLB_WT
+#define CPLB_CACHE_ENABLED      CPLB_L1_CHBL | CPLB_DIRTY
+
+#define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
+
+#define CPLB_I_PAGE_MGMT        CPLB_LOCK | CPLB_VALID
+#define CPLB_D_PAGE_MGMT        CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DNOCACHE           CPLB_ALL_ACCESS | CPLB_VALID
+#define CPLB_DDOCACHE           CPLB_DNOCACHE | CPLB_DEF_CACHE
+#define CPLB_INOCACHE           CPLB_USER_RD | CPLB_VALID
+#define CPLB_IDOCACHE           CPLB_INOCACHE | CPLB_L1_CHBL
+
+#endif                          /* _CPLB_H */
diff --git a/include/asm-blackfin/cplbinit.h b/include/asm-blackfin/cplbinit.h
new file mode 100644
index 000000000000..3bad2d1e6a8c
--- /dev/null
+++ b/include/asm-blackfin/cplbinit.h
@@ -0,0 +1,203 @@
+/*
+ * File:         include/asm-blackfin/cplbinit.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#include <asm/blackfin.h>
+#include <asm/cplb.h>
+
+#define INITIAL_T 0x1
+#define SWITCH_T  0x2
+#define I_CPLB    0x4
+#define D_CPLB    0x8
+
+#define IN_KERNEL 1
+
+enum
+{ZERO_P, L1I_MEM, L1D_MEM, SDRAM_KERN , SDRAM_RAM_MTD, SDRAM_DMAZ, RES_MEM, ASYNC_MEM, L2_MEM};
+
+struct cplb_desc {
+        u32 start; /* start address */
+        u32 end; /* end address */
+        u32 psize; /* prefered size if any otherwise 1MB or 4MB*/
+        u16 attr;/* attributes */
+        u16 i_conf;/* I-CPLB DATA */
+        u16 d_conf;/* D-CPLB DATA */
+        u16 valid;/* valid */
+        const s8 name[30];/* name */
+};
+
+struct cplb_tab {
+  u_long *tab;
+        u16 pos;
+        u16 size;
+};
+
+u_long icplb_table[MAX_CPLBS+1];
+u_long dcplb_table[MAX_CPLBS+1];
+
+/* Till here we are discussing about the static memory management model.
+ * However, the operating envoronments commonly define more CPLB
+ * descriptors to cover the entire addressable memory than will fit into
+ * the available on-chip 16 CPLB MMRs. When this happens, the below table
+ * will be used which will hold all the potentially required CPLB descriptors
+ *
+ * This is how Page descriptor Table is implemented in uClinux/Blackfin.
+ */
+
+#ifdef CONFIG_CPLB_SWITCH_TAB_L1
+u_long ipdt_table[MAX_SWITCH_I_CPLBS+1]__attribute__((l1_data));
+u_long dpdt_table[MAX_SWITCH_D_CPLBS+1]__attribute__((l1_data));
+
+#ifdef CONFIG_CPLB_INFO
+u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS]__attribute__((l1_data));
+u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS]__attribute__((l1_data));
+#endif /* CONFIG_CPLB_INFO */
+
+#else
+
+u_long ipdt_table[MAX_SWITCH_I_CPLBS+1];
+u_long dpdt_table[MAX_SWITCH_D_CPLBS+1];
+
+#ifdef CONFIG_CPLB_INFO
+u_long ipdt_swapcount_table[MAX_SWITCH_I_CPLBS];
+u_long dpdt_swapcount_table[MAX_SWITCH_D_CPLBS];
+#endif /* CONFIG_CPLB_INFO */
+
+#endif /*CONFIG_CPLB_SWITCH_TAB_L1*/
+
+struct s_cplb {
+        struct cplb_tab init_i;
+        struct cplb_tab init_d;
+        struct cplb_tab switch_i;
+        struct cplb_tab switch_d;
+};
+
+#if defined(CONFIG_BLKFIN_DCACHE) || defined(CONFIG_BLKFIN_CACHE)
+static struct cplb_desc cplb_data[] = {
+        {
+                .start = 0,
+                .end = SIZE_4K,
+                .psize = SIZE_4K,
+                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
+                .i_conf = SDRAM_OOPS,
+                .d_conf = SDRAM_OOPS,
+#if defined(CONFIG_DEBUG_HUNT_FOR_ZERO)
+                .valid = 1,
+#else
+                .valid = 0,
+#endif
+                .name = "ZERO Pointer Saveguard",
+        },
+        {
+                .start = L1_CODE_START,
+                .end = L1_CODE_START + L1_CODE_LENGTH,
+                .psize = SIZE_4M,
+                .attr = INITIAL_T | SWITCH_T | I_CPLB,
+                .i_conf = L1_IMEMORY,
+                .d_conf = 0,
+                .valid = 1,
+                .name = "L1 I-Memory",
+        },
+        {
+                .start = L1_DATA_A_START,
+                .end = L1_DATA_B_START + L1_DATA_B_LENGTH,
+                .psize = SIZE_4M,
+                .attr = INITIAL_T | SWITCH_T | D_CPLB,
+                .i_conf = 0,
+                .d_conf = L1_DMEMORY,
+#if ((L1_DATA_A_LENGTH > 0) || (L1_DATA_B_LENGTH > 0))
+                .valid = 1,
+#else
+                .valid = 0,
+#endif
+                .name = "L1 D-Memory",
+        },
+        {
+                .start = 0,
+                .end = 0,  /* dynamic */
+                .psize = 0,
+                .attr = INITIAL_T | SWITCH_T | I_CPLB | D_CPLB,
+                .i_conf =  SDRAM_IGENERIC,
+                .d_conf =  SDRAM_DGENERIC,
+                .valid = 1,
+                .name = "SDRAM Kernel",
+        },
+        {
+                .start = 0, /* dynamic */
+                .end = 0, /* dynamic */
+                .psize = 0,
+                .attr = INITIAL_T | SWITCH_T | D_CPLB,
+                .i_conf =  SDRAM_IGENERIC,
+                .d_conf =  SDRAM_DNON_CHBL,
+                .valid = 1,
+                .name = "SDRAM RAM MTD",
+        },
+        {
+                .start = 0, /* dynamic */
+                .end = 0,   /* dynamic */
+                .psize = SIZE_1M,
+                .attr = INITIAL_T | SWITCH_T | D_CPLB,
+                .d_conf = SDRAM_DNON_CHBL,
+                .valid = 1,//(DMA_UNCACHED_REGION > 0),
+                .name = "SDRAM Uncached DMA ZONE",
+        },
+        {
+                .start = 0, /* dynamic */
+                .end = 0, /* dynamic */
+                .psize = 0,
+                .attr = SWITCH_T | D_CPLB,
+                .i_conf = 0, /* dynamic */
+                .d_conf = 0, /* dynamic */
+                .valid = 1,
+                .name = "SDRAM Reserved Memory",
+        },
+        {
+                .start = ASYNC_BANK0_BASE,
+                .end = ASYNC_BANK3_BASE + ASYNC_BANK3_SIZE,
+                .psize = 0,
+                .attr = SWITCH_T | D_CPLB,
+                .d_conf = SDRAM_EBIU,
+                .valid = 1,
+                .name = "ASYNC Memory",
+        },
+        {
+#if defined(CONFIG_BF561)
+                .start = L2_SRAM,
+                .end = L2_SRAM_END,
+                .psize = SIZE_1M,
+                .attr = SWITCH_T | D_CPLB,
+                .i_conf = L2_MEMORY,
+                .d_conf = L2_MEMORY,
+                .valid = 1,
+#else
+                .valid = 0,
+#endif
+                .name = "L2 Memory",
+        }
+};
+#endif
diff --git a/include/asm-blackfin/cpumask.h b/include/asm-blackfin/cpumask.h
new file mode 100644
index 000000000000..b20a8e9012cb
--- /dev/null
+++ b/include/asm-blackfin/cpumask.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_BLACKFIN_CPUMASK_H
+#define _ASM_BLACKFIN_CPUMASK_H
+
+#include <asm-generic/cpumask.h>
+
+#endif                          /* _ASM_BLACKFIN_CPUMASK_H */
diff --git a/include/asm-blackfin/cputime.h b/include/asm-blackfin/cputime.h
new file mode 100644
index 000000000000..2b19705f9885
--- /dev/null
+++ b/include/asm-blackfin/cputime.h
@@ -0,0 +1,6 @@
+#ifndef __BLACKFIN_CPUTIME_H
+#define __BLACKFIN_CPUTIME_H
+
+#include <asm-generic/cputime.h>
+
+#endif                          /* __BLACKFIN_CPUTIME_H */
diff --git a/include/asm-blackfin/current.h b/include/asm-blackfin/current.h
new file mode 100644
index 000000000000..31918d29122c
--- /dev/null
+++ b/include/asm-blackfin/current.h
@@ -0,0 +1,23 @@
+#ifndef _BLACKFIN_CURRENT_H
+#define _BLACKFIN_CURRENT_H
+/*
+ *      current.h
+ *      (C) Copyright 2000, Lineo, David McCullough <davidm@lineo.com>
+ *
+ *      rather than dedicate a register (as the m68k source does), we
+ *      just keep a global,  we should probably just change it all to be
+ *      current and lose _current_task.
+ */
+#include <linux/thread_info.h>
+
+struct task_struct;
+
+static inline struct task_struct *get_current(void) __attribute__ ((__const__));
+static inline struct task_struct *get_current(void)
+{
+        return (current_thread_info()->task);
+}
+
+#define current (get_current())
+
+#endif                          /* _BLACKFIN_CURRENT_H */
diff --git a/include/asm-blackfin/delay.h b/include/asm-blackfin/delay.h
new file mode 100644
index 000000000000..52e7a10d7ff8
--- /dev/null
+++ b/include/asm-blackfin/delay.h
@@ -0,0 +1,44 @@
+#ifndef _BLACKFIN_DELAY_H
+#define _BLACKFIN_DELAY_H
+
+static inline void __delay(unsigned long loops)
+{
+
+/* FIXME: Currently the assembler doesn't recognize Loop Register Clobbers,
+   uncomment this as soon those are implemented */
+/*
+      __asm__ __volatile__ (  "\t LSETUP (1f,1f) LC0= %0\n\t"
+                              "1:\t NOP;\n\t"
+                              : :"a" (loops)
+                              : "LT0","LB0","LC0");
+
+*/
+
+        __asm__ __volatile__("[--SP] = LC0;\n\t"
+                             "[--SP] = LT0;\n\t"
+                             "[--SP] = LB0;\n\t"
+                             "LSETUP (1f,1f) LC0 = %0;\n\t"
+                             "1:\t NOP;\n\t"
+                             "LB0 = [SP++];\n\t"
+                                "LT0 = [SP++];\n\t"
+                                "LC0 = [SP++];\n"
+                                :
+                                :"a" (loops));
+}
+
+#include <linux/param.h>        /* needed for HZ */
+
+/*
+ * Use only for very small delays ( < 1 msec).  Should probably use a
+ * lookup table, really, as the multiplications take much too long with
+ * short delays.  This is a "reasonable" implementation, though (and the
+ * first constant multiplications gets optimized away if the delay is
+ * a constant)
+ */
+static inline void udelay(unsigned long usecs)
+{
+        extern unsigned long loops_per_jiffy;
+        __delay(usecs * loops_per_jiffy / (1000000 / HZ));
+}
+
+#endif                          /* defined(_BLACKFIN_DELAY_H) */
diff --git a/include/asm-blackfin/device.h b/include/asm-blackfin/device.h
new file mode 100644
index 000000000000..d8f9872b0e2d
--- /dev/null
+++ b/include/asm-blackfin/device.h
@@ -0,0 +1,7 @@
+/*
+ * Arch specific extensions to struct device
+ *
+ * This file is released under the GPLv2
+ */
+#include <asm-generic/device.h>
+
diff --git a/include/asm-blackfin/div64.h b/include/asm-blackfin/div64.h
new file mode 100644
index 000000000000..6cd978cefb28
--- /dev/null
+++ b/include/asm-blackfin/div64.h
@@ -0,0 +1 @@
+#include <asm-generic/div64.h>
diff --git a/include/asm-blackfin/dma-mapping.h b/include/asm-blackfin/dma-mapping.h
new file mode 100644
index 000000000000..7a77d7fe3a33
--- /dev/null
+++ b/include/asm-blackfin/dma-mapping.h
@@ -0,0 +1,66 @@
+#ifndef _BLACKFIN_DMA_MAPPING_H
+#define _BLACKFIN_DMA_MAPPING_H
+
+#include <asm/scatterlist.h>
+
+void dma_alloc_init(unsigned long start, unsigned long end);
+void *dma_alloc_coherent(struct device *dev, size_t size,
+                         dma_addr_t *dma_handle, gfp_t gfp);
+void dma_free_coherent(struct device *dev, size_t size, void *vaddr,
+                       dma_addr_t dma_handle);
+
+/*
+ * Now for the API extensions over the pci_ one
+ */
+#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
+#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
+
+/*
+ * Map a single buffer of the indicated size for DMA in streaming mode.
+ * The 32-bit bus address to use is returned.
+ *
+ * Once the device is given the dma address, the device owns this memory
+ * until either pci_unmap_single or pci_dma_sync_single is performed.
+ */
+extern dma_addr_t dma_map_single(struct device *dev, void *ptr, size_t size,
+                                 enum dma_data_direction direction);
+
+/*
+ * Unmap a single streaming mode DMA translation.  The dma_addr and size
+ * must match what was provided for in a previous pci_map_single call.  All
+ * other usages are undefined.
+ *
+ * After this call, reads by the cpu to the buffer are guarenteed to see
+ * whatever the device wrote there.
+ */
+extern void dma_unmap_single(struct device *dev, dma_addr_t dma_addr, size_t size,
+                          enum dma_data_direction direction);
+
+/*
+ * Map a set of buffers described by scatterlist in streaming
+ * mode for DMA.  This is the scather-gather version of the
+ * above pci_map_single interface.  Here the scatter gather list
+ * elements are each tagged with the appropriate dma address
+ * and length.  They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of
+ *       DMA address/length pairs than there are SG table elements.
+ *       (for example via virtual mapping capabilities)
+ *       The routine returns the number of addr/length pairs actually
+ *       used, at most nents.
+ *
+ * Device ownership issues as mentioned above for pci_map_single are
+ * the same here.
+ */
+extern int dma_map_sg(struct device *dev, struct scatterlist *sg, int nents,
+                      enum dma_data_direction direction);
+
+/*
+ * Unmap a set of streaming mode DMA translations.
+ * Again, cpu read rules concerning calls here are the same as for
+ * pci_unmap_single() above.
+ */
+extern void dma_unmap_sg(struct device *dev, struct scatterlist *sg,
+                      int nhwentries, enum dma_data_direction direction);
+
+#endif                          /* _BLACKFIN_DMA_MAPPING_H */
diff --git a/include/asm-blackfin/dma.h b/include/asm-blackfin/dma.h
new file mode 100644
index 000000000000..be0d913e5516
--- /dev/null
+++ b/include/asm-blackfin/dma.h
@@ -0,0 +1,188 @@
+/*
+ * File:         include/asm-blackfin/simple_bf533_dma.h
+ * Based on:     none - original work
+ * Author:       LG Soft India
+ *               Copyright (C) 2004-2005 Analog Devices Inc.
+ * Created:      Tue Sep 21 2004
+ * Description:  This file contains the major Data structures and constants
+ *               used for DMA Implementation in BF533
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BLACKFIN_DMA_H_
+#define _BLACKFIN_DMA_H_
+
+#include <asm/io.h>
+#include <linux/slab.h>
+#include <asm/irq.h>
+#include <asm/signal.h>
+#include <asm/semaphore.h>
+
+#include <linux/kernel.h>
+#include <asm/mach/dma.h>
+#include <linux/mm.h>
+#include <linux/interrupt.h>
+#include <asm/blackfin.h>
+
+#define MAX_DMA_ADDRESS PAGE_OFFSET
+
+/*****************************************************************************
+*        Generic DMA  Declarations
+*
+****************************************************************************/
+enum dma_chan_status {
+        DMA_CHANNEL_FREE,
+        DMA_CHANNEL_REQUESTED,
+        DMA_CHANNEL_ENABLED,
+};
+
+/*-------------------------
+ * config reg bits value
+ *-------------------------*/
+#define DATA_SIZE_8             0
+#define DATA_SIZE_16            1
+#define DATA_SIZE_32            2
+
+#define DMA_FLOW_STOP           0
+#define DMA_FLOW_AUTO           1
+#define DMA_FLOW_ARRAY          4
+#define DMA_FLOW_SMALL          6
+#define DMA_FLOW_LARGE          7
+
+#define DIMENSION_LINEAR    0
+#define DIMENSION_2D           1
+
+#define DIR_READ     0
+#define DIR_WRITE    1
+
+#define INTR_DISABLE   0
+#define INTR_ON_BUF    2
+#define INTR_ON_ROW    3
+
+struct dmasg {
+        unsigned long next_desc_addr;
+        unsigned long start_addr;
+        unsigned short cfg;
+        unsigned short x_count;
+        short x_modify;
+        unsigned short y_count;
+        short y_modify;
+} __attribute__((packed));
+
+struct dma_register {
+        unsigned long next_desc_ptr;    /* DMA Next Descriptor Pointer register */
+        unsigned long start_addr;       /* DMA Start address  register */
+
+        unsigned short cfg;     /* DMA Configuration register */
+        unsigned short dummy1;  /* DMA Configuration register */
+
+        unsigned long reserved;
+
+        unsigned short x_count; /* DMA x_count register */
+        unsigned short dummy2;
+
+        short x_modify; /* DMA x_modify register */
+        unsigned short dummy3;
+
+        unsigned short y_count; /* DMA y_count register */
+        unsigned short dummy4;
+
+        short y_modify; /* DMA y_modify register */
+        unsigned short dummy5;
+
+        unsigned long curr_desc_ptr;    /* DMA Current Descriptor Pointer
+                                           register */
+        unsigned short curr_addr_ptr_lo;        /* DMA Current Address Pointer
+                                                   register */
+        unsigned short curr_addr_ptr_hi;        /* DMA Current Address Pointer
+                                                   register */
+        unsigned short irq_status;      /* DMA irq status register */
+        unsigned short dummy6;
+
+        unsigned short peripheral_map;  /* DMA peripheral map register */
+        unsigned short dummy7;
+
+        unsigned short curr_x_count;    /* DMA Current x-count register */
+        unsigned short dummy8;
+
+        unsigned long reserved2;
+
+        unsigned short curr_y_count;    /* DMA Current y-count register */
+        unsigned short dummy9;
+
+        unsigned long reserved3;
+
+};
+
+typedef irqreturn_t(*dma_interrupt_t) (int irq, void *dev_id);
+
+struct dma_channel {
+        struct mutex dmalock;
+        char *device_id;
+        enum dma_chan_status chan_status;
+        struct dma_register *regs;
+        struct dmasg *sg;               /* large mode descriptor */
+        unsigned int ctrl_num;  /* controller number */
+        dma_interrupt_t irq_callback;
+        void *data;
+        unsigned int dma_enable_flag;
+        unsigned int loopback_flag;
+};
+
+/*******************************************************************************
+*       DMA API's
+*******************************************************************************/
+/* functions to set register mode */
+void set_dma_start_addr(unsigned int channel, unsigned long addr);
+void set_dma_next_desc_addr(unsigned int channel, unsigned long addr);
+void set_dma_x_count(unsigned int channel, unsigned short x_count);
+void set_dma_x_modify(unsigned int channel, short x_modify);
+void set_dma_y_count(unsigned int channel, unsigned short y_count);
+void set_dma_y_modify(unsigned int channel, short y_modify);
+void set_dma_config(unsigned int channel, unsigned short config);
+unsigned short set_bfin_dma_config(char direction, char flow_mode,
+                                   char intr_mode, char dma_mode, char width);
+
+/* get curr status for polling */
+unsigned short get_dma_curr_irqstat(unsigned int channel);
+unsigned short get_dma_curr_xcount(unsigned int channel);
+unsigned short get_dma_curr_ycount(unsigned int channel);
+
+/* set large DMA mode descriptor */
+void set_dma_sg(unsigned int channel, struct dmasg *sg, int nr_sg);
+
+/* check if current channel is in use */
+int dma_channel_active(unsigned int channel);
+
+/* common functions must be called in any mode */
+void free_dma(unsigned int channel);
+int dma_channel_active(unsigned int channel); /* check if a channel is in use */
+void disable_dma(unsigned int channel);
+void enable_dma(unsigned int channel);
+int request_dma(unsigned int channel, char *device_id);
+int set_dma_callback(unsigned int channel, dma_interrupt_t callback,
+                     void *data);
+void dma_disable_irq(unsigned int channel);
+void dma_enable_irq(unsigned int channel);
+void clear_dma_irqstat(unsigned int channel);
+void *dma_memcpy(void *dest, const void *src, size_t count);
+void *safe_dma_memcpy(void *dest, const void *src, size_t count);
+
+#endif
diff --git a/include/asm-blackfin/dpmc.h b/include/asm-blackfin/dpmc.h
new file mode 100644
index 000000000000..f162edb23033
--- /dev/null
+++ b/include/asm-blackfin/dpmc.h
@@ -0,0 +1,70 @@
+/*
+ * include/asm-blackfin/dpmc.h -  Miscellaneous IOCTL commands for Dynamic Power
+ *                              Management Controller Driver.
+ * Copyright (C) 2004 Analog Device Inc.
+ *
+ */
+#ifndef _BLACKFIN_DPMC_H_
+#define _BLACKFIN_DPMC_H_
+
+#define SLEEP_MODE              1
+#define DEEP_SLEEP_MODE         2
+#define ACTIVE_PLL_DISABLED     3
+#define FULLON_MODE             4
+#define ACTIVE_PLL_ENABLED      5
+#define HIBERNATE_MODE          6
+
+#define IOCTL_FULL_ON_MODE      _IO('s', 0xA0)
+#define IOCTL_ACTIVE_MODE       _IO('s', 0xA1)
+#define IOCTL_SLEEP_MODE        _IO('s', 0xA2)
+#define IOCTL_DEEP_SLEEP_MODE   _IO('s', 0xA3)
+#define IOCTL_HIBERNATE_MODE    _IO('s', 0xA4)
+#define IOCTL_CHANGE_FREQUENCY  _IOW('s', 0xA5, unsigned long)
+#define IOCTL_CHANGE_VOLTAGE    _IOW('s', 0xA6, unsigned long)
+#define IOCTL_SET_CCLK          _IOW('s', 0xA7, unsigned long)
+#define IOCTL_SET_SCLK          _IOW('s', 0xA8, unsigned long)
+#define IOCTL_GET_PLLSTATUS     _IOW('s', 0xA9, unsigned long)
+#define IOCTL_GET_CORECLOCK     _IOW('s', 0xAA, unsigned long)
+#define IOCTL_GET_SYSTEMCLOCK   _IOW('s', 0xAB, unsigned long)
+#define IOCTL_GET_VCO           _IOW('s', 0xAC, unsigned long)
+#define IOCTL_DISABLE_WDOG_TIMER _IO('s', 0xAD)
+#define IOCTL_UNMASK_WDOG_WAKEUP_EVENT _IO('s',0xAE)
+#define IOCTL_PROGRAM_WDOG_TIMER _IOW('s',0xAF,unsigned long)
+#define IOCTL_CLEAR_WDOG_WAKEUP_EVENT _IO('s',0xB0)
+#define IOCTL_SLEEP_DEEPER_MODE _IO('s',0xB1)
+
+#define DPMC_MINOR              254
+
+#define ON      0
+#define OFF     1
+
+#ifdef __KERNEL__
+
+unsigned long calc_volt(void);
+int calc_vlev(int vlt);
+unsigned long change_voltage(unsigned long volt);
+int calc_msel(int vco_hz);
+unsigned long change_frequency(unsigned long vco_mhz);
+int set_pll_div(unsigned short sel, unsigned char flag);
+int get_vco(void);
+unsigned long change_system_clock(unsigned long clock);
+unsigned long change_core_clock(unsigned long clock);
+unsigned long get_pll_status(void);
+void change_baud(int baud);
+void fullon_mode(void);
+void active_mode(void);
+void sleep_mode(u32 sic_iwr);
+void deep_sleep(u32 sic_iwr);
+void hibernate_mode(u32 sic_iwr);
+void sleep_deeper(u32 sic_iwr);
+void program_wdog_timer(unsigned long);
+void unmask_wdog_wakeup_evt(void);
+void clear_wdog_wakeup_evt(void);
+void disable_wdog_timer(void);
+
+extern unsigned long get_cclk(void);
+extern unsigned long get_sclk(void);
+
+#endif  /* __KERNEL__ */
+
+#endif  /*_BLACKFIN_DPMC_H_*/
diff --git a/include/asm-blackfin/elf.h b/include/asm-blackfin/elf.h
new file mode 100644
index 000000000000..5264b5536a70
--- /dev/null
+++ b/include/asm-blackfin/elf.h
@@ -0,0 +1,127 @@
+/* Changes made by  LG Soft Oct 2004*/
+
+#ifndef __ASMBFIN_ELF_H
+#define __ASMBFIN_ELF_H
+
+/*
+ * ELF register definitions..
+ */
+
+#include <asm/ptrace.h>
+#include <asm/user.h>
+
+/* Processor specific flags for the ELF header e_flags field.  */
+#define EF_BFIN_PIC             0x00000001      /* -fpic */
+#define EF_BFIN_FDPIC           0x00000002      /* -mfdpic */
+#define EF_BFIN_CODE_IN_L1      0x00000010      /* --code-in-l1 */
+#define EF_BFIN_DATA_IN_L1      0x00000020      /* --data-in-l1 */
+
+typedef unsigned long elf_greg_t;
+
+#define ELF_NGREG (sizeof(struct user_regs_struct) / sizeof(elf_greg_t))
+typedef elf_greg_t elf_gregset_t[ELF_NGREG];
+
+typedef struct user_bfinfp_struct elf_fpregset_t;
+/*
+ * This is used to ensure we don't load something for the wrong architecture.
+ */
+#define elf_check_arch(x) ((x)->e_machine == EM_BLACKFIN)
+
+#define elf_check_fdpic(x) ((x)->e_flags & EF_BFIN_FDPIC /* && !((x)->e_flags & EF_FRV_NON_PIC_RELOCS) */)
+#define elf_check_const_displacement(x) ((x)->e_flags & EF_BFIN_PIC)
+
+/* EM_BLACKFIN defined in linux/elf.h   */
+
+/*
+ * These are used to set parameters in the core dumps.
+ */
+#define ELF_CLASS       ELFCLASS32
+#define ELF_DATA        ELFDATA2LSB
+#define ELF_ARCH        EM_BLACKFIN
+
+#define ELF_PLAT_INIT(_r)       _r->p1 = 0
+
+#define ELF_FDPIC_PLAT_INIT(_regs, _exec_map_addr, _interp_map_addr, _dynamic_addr)     \
+do {                                                                                    \
+        _regs->r7       = 0;                                            \
+        _regs->p0       = _exec_map_addr;                               \
+        _regs->p1       = _interp_map_addr;                             \
+        _regs->p2       = _dynamic_addr;                                \
+} while(0)
+
+#define USE_ELF_CORE_DUMP
+#define ELF_FDPIC_CORE_EFLAGS   EF_BFIN_FDPIC
+#define ELF_EXEC_PAGESIZE       4096
+
+#define R_unused0       0       /* relocation type 0 is not defined */
+#define R_pcrel5m2      1       /*LSETUP part a */
+#define R_unused1       2       /* relocation type 2 is not defined */
+#define R_pcrel10       3       /* type 3, if cc jump <target>  */
+#define R_pcrel12_jump  4       /* type 4, jump <target> */
+#define R_rimm16        5       /* type 0x5, rN = <target> */
+#define R_luimm16       6       /* # 0x6, preg.l=<target> Load imm 16 to lower half */
+#define R_huimm16       7       /* # 0x7, preg.h=<target> Load imm 16 to upper half */
+#define R_pcrel12_jump_s 8      /* # 0x8 jump.s <target> */
+#define R_pcrel24_jump_x 9      /* # 0x9 jump.x <target> */
+#define R_pcrel24       10      /* # 0xa call <target> , not expandable */
+#define R_unusedb       11      /* # 0xb not generated */
+#define R_unusedc       12      /* # 0xc  not used */
+#define R_pcrel24_jump_l 13     /*0xd jump.l <target> */
+#define R_pcrel24_call_x 14     /* 0xE, call.x <target> if <target> is above 24 bit limit call through P1 */
+#define R_var_eq_symb    15     /* 0xf, linker should treat it same as 0x12 */
+#define R_byte_data      16     /* 0x10, .byte var = symbol */
+#define R_byte2_data     17     /* 0x11, .byte2 var = symbol */
+#define R_byte4_data     18     /* 0x12, .byte4 var = symbol and .var var=symbol */
+#define R_pcrel11        19     /* 0x13, lsetup part b */
+#define R_unused14      20      /* 0x14, undefined */
+#define R_unused15       21     /* not generated by VDSP 3.5 */
+
+/* arithmetic relocations */
+#define R_push           0xE0
+#define R_const          0xE1
+#define R_add            0xE2
+#define R_sub            0xE3
+#define R_mult           0xE4
+#define R_div            0xE5
+#define R_mod            0xE6
+#define R_lshift         0xE7
+#define R_rshift         0xE8
+#define R_and            0xE9
+#define R_or             0xEA
+#define R_xor            0xEB
+#define R_land           0xEC
+#define R_lor            0xED
+#define R_len            0xEE
+#define R_neg            0xEF
+#define R_comp           0xF0
+#define R_page           0xF1
+#define R_hwpage         0xF2
+#define R_addr           0xF3
+
+/* This is the location that an ET_DYN program is loaded if exec'ed.  Typical
+   use of this is to invoke "./ld.so someprog" to test out a new version of
+   the loader.  We need to make sure that it is out of the way of the program
+   that it will "exec", and that there is sufficient room for the brk.  */
+
+#define ELF_ET_DYN_BASE         0xD0000000UL
+
+#define ELF_CORE_COPY_REGS(pr_reg, regs)        \
+        memcpy((char *) &pr_reg, (char *)regs,  \
+               sizeof(struct pt_regs));
+
+/* This yields a mask that user programs can use to figure out what
+   instruction set this cpu supports.  */
+
+#define ELF_HWCAP       (0)
+
+/* This yields a string that ld.so will use to load implementation
+   specific libraries for optimization.  This is more specific in
+   intent than poking at uname or /proc/cpuinfo.  */
+
+#define ELF_PLATFORM  (NULL)
+
+#ifdef __KERNEL__
+#define SET_PERSONALITY(ex, ibcs2) set_personality((ibcs2)?PER_SVR4:PER_LINUX)
+#endif
+
+#endif
diff --git a/include/asm-blackfin/emergency-restart.h b/include/asm-blackfin/emergency-restart.h
new file mode 100644
index 000000000000..27f6c785d103
--- /dev/null
+++ b/include/asm-blackfin/emergency-restart.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_EMERGENCY_RESTART_H
+#define _ASM_EMERGENCY_RESTART_H
+
+#include <asm-generic/emergency-restart.h>
+
+#endif                          /* _ASM_EMERGENCY_RESTART_H */
diff --git a/include/asm-blackfin/entry.h b/include/asm-blackfin/entry.h
new file mode 100644
index 000000000000..562c6d3a3232
--- /dev/null
+++ b/include/asm-blackfin/entry.h
@@ -0,0 +1,56 @@
+#ifndef __BFIN_ENTRY_H
+#define __BFIN_ENTRY_H
+
+#include <asm/setup.h>
+#include <asm/page.h>
+
+#ifdef __ASSEMBLY__
+
+#define LFLUSH_I_AND_D  0x00000808
+#define LSIGTRAP        5
+
+/* process bits for task_struct.flags */
+#define PF_TRACESYS_OFF 3
+#define PF_TRACESYS_BIT 5
+#define PF_PTRACED_OFF  3
+#define PF_PTRACED_BIT  4
+#define PF_DTRACE_OFF   1
+#define PF_DTRACE_BIT   5
+
+/* This one is used for exceptions, emulation, and NMI.  It doesn't push
+   RETI and doesn't do cli.  */
+#define SAVE_ALL_SYS            save_context_no_interrupts
+/* This is used for all normal interrupts.  It saves a minimum of registers
+   to the stack, loads the IRQ number, and jumps to common code.  */
+#define INTERRUPT_ENTRY(N)                                              \
+    [--sp] = SYSCFG;                                                    \
+                                                                        \
+    [--sp] = P0;        /*orig_p0*/                                     \
+    [--sp] = R0;        /*orig_r0*/                                     \
+    [--sp] = (R7:0,P5:0);                                               \
+    R0 = (N);                                                           \
+    jump __common_int_entry;
+
+/* For timer interrupts, we need to save IPEND, since the user_mode
+           macro accesses it to determine where to account time.  */
+#define TIMER_INTERRUPT_ENTRY(N)                                        \
+    [--sp] = SYSCFG;                                                    \
+                                                                        \
+    [--sp] = P0;        /*orig_p0*/                                     \
+    [--sp] = R0;        /*orig_r0*/                                     \
+    [--sp] = (R7:0,P5:0);                                               \
+    p0.l = lo(IPEND);                                                   \
+    p0.h = hi(IPEND);                                                   \
+    r1 = [p0];                                                          \
+    R0 = (N);                                                           \
+    jump __common_int_entry;
+
+/* This one pushes RETI without using CLI.  Interrupts are enabled.  */
+#define SAVE_CONTEXT_SYSCALL    save_context_syscall
+#define SAVE_CONTEXT            save_context_with_interrupts
+
+#define RESTORE_ALL_SYS         restore_context_no_interrupts
+#define RESTORE_CONTEXT         restore_context_with_interrupts
+
+#endif                          /* __ASSEMBLY__ */
+#endif                          /* __BFIN_ENTRY_H */
diff --git a/include/asm-blackfin/errno.h b/include/asm-blackfin/errno.h
new file mode 100644
index 000000000000..164e4f39bb57
--- /dev/null
+++ b/include/asm-blackfin/errno.h
@@ -0,0 +1,6 @@
+#ifndef _BFIN_ERRNO_H
+#define _BFIN_ERRNO_H
+
+#include<asm-generic/errno.h>
+
+#endif                          /* _BFIN_ERRNO_H */
diff --git a/include/asm-blackfin/fcntl.h b/include/asm-blackfin/fcntl.h
new file mode 100644
index 000000000000..9c4037127857
--- /dev/null
+++ b/include/asm-blackfin/fcntl.h
@@ -0,0 +1,13 @@
+#ifndef _BFIN_FCNTL_H
+#define _BFIN_FCNTL_H
+
+/* open/fcntl - O_SYNC is only implemented on blocks devices and on files
+   located on an ext2 file system */
+#define O_DIRECTORY      040000 /* must be a directory */
+#define O_NOFOLLOW      0100000 /* don't follow links */
+#define O_DIRECT        0200000 /* direct disk access hint - currently ignored */
+#define O_LARGEFILE     0400000
+
+#include <asm-generic/fcntl.h>
+
+#endif
diff --git a/include/asm-blackfin/flat.h b/include/asm-blackfin/flat.h
new file mode 100644
index 000000000000..e70074e05f4e
--- /dev/null
+++ b/include/asm-blackfin/flat.h
@@ -0,0 +1,58 @@
+/*
+ * include/asm-blackfin/flat.h -- uClinux flat-format executables
+ *
+ * Copyright (C) 2003,
+ *
+ */
+
+#ifndef __BLACKFIN_FLAT_H__
+#define __BLACKFIN_FLAT_H__
+
+#include <asm/unaligned.h>
+
+#define flat_stack_align(sp)    /* nothing needed */
+#define flat_argvp_envp_on_stack()              0
+#define flat_old_ram_flag(flags)                (flags)
+
+extern unsigned long bfin_get_addr_from_rp (unsigned long *ptr,
+                                        unsigned long relval,
+                                        unsigned long flags,
+                                        unsigned long *persistent);
+
+extern void bfin_put_addr_at_rp(unsigned long *ptr, unsigned long addr,
+                                unsigned long relval);
+
+/* The amount by which a relocation can exceed the program image limits
+   without being regarded as an error.  */
+
+#define flat_reloc_valid(reloc, size)   ((reloc) <= (size))
+
+#define flat_get_addr_from_rp(rp, relval, flags, persistent)    \
+        bfin_get_addr_from_rp(rp, relval, flags, persistent)
+#define flat_put_addr_at_rp(rp, val, relval)    \
+        bfin_put_addr_at_rp(rp, val, relval)
+
+/* Convert a relocation entry into an address.  */
+static inline unsigned long
+flat_get_relocate_addr (unsigned long relval)
+{
+        return relval & 0x03ffffff; /* Mask out top 6 bits */
+}
+
+static inline int flat_set_persistent(unsigned long relval,
+                                      unsigned long *persistent)
+{
+        int type = (relval >> 26) & 7;
+        if (type == 3) {
+                *persistent = relval << 16;
+                return 1;
+        }
+        return 0;
+}
+
+static inline int flat_addr_absolute(unsigned long relval)
+{
+        return (relval & (1 << 29)) != 0;
+}
+
+#endif                          /* __BLACKFIN_FLAT_H__ */
diff --git a/include/asm-blackfin/futex.h b/include/asm-blackfin/futex.h
new file mode 100644
index 000000000000..6a332a9f099c
--- /dev/null
+++ b/include/asm-blackfin/futex.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_FUTEX_H
+#define _ASM_FUTEX_H
+
+#include <asm-generic/futex.h>
+
+#endif
diff --git a/include/asm-blackfin/gpio.h b/include/asm-blackfin/gpio.h
new file mode 100644
index 000000000000..d16fe3cd6135
--- /dev/null
+++ b/include/asm-blackfin/gpio.h
@@ -0,0 +1,367 @@
+/*
+ * File:         arch/blackfin/kernel/bfin_gpio.h
+ * Based on:
+ * Author:       Michael Hennerich (hennerich@blackfin.uclinux.org)
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+/*
+*  Number     BF537/6/4    BF561    BF533/2/1
+*
+*  GPIO_0       PF0         PF0        PF0
+*  GPIO_1       PF1         PF1        PF1
+*  GPIO_2       PF2         PF2        PF2
+*  GPIO_3       PF3         PF3        PF3
+*  GPIO_4       PF4         PF4        PF4
+*  GPIO_5       PF5         PF5        PF5
+*  GPIO_6       PF6         PF6        PF6
+*  GPIO_7       PF7         PF7        PF7
+*  GPIO_8       PF8         PF8        PF8
+*  GPIO_9       PF9         PF9        PF9
+*  GPIO_10      PF10        PF10       PF10
+*  GPIO_11      PF11        PF11       PF11
+*  GPIO_12      PF12        PF12       PF12
+*  GPIO_13      PF13        PF13       PF13
+*  GPIO_14      PF14        PF14       PF14
+*  GPIO_15      PF15        PF15       PF15
+*  GPIO_16      PG0         PF16
+*  GPIO_17      PG1         PF17
+*  GPIO_18      PG2         PF18
+*  GPIO_19      PG3         PF19
+*  GPIO_20      PG4         PF20
+*  GPIO_21      PG5         PF21
+*  GPIO_22      PG6         PF22
+*  GPIO_23      PG7         PF23
+*  GPIO_24      PG8         PF24
+*  GPIO_25      PG9         PF25
+*  GPIO_26      PG10        PF26
+*  GPIO_27      PG11        PF27
+*  GPIO_28      PG12        PF28
+*  GPIO_29      PG13        PF29
+*  GPIO_30      PG14        PF30
+*  GPIO_31      PG15        PF31
+*  GPIO_32      PH0         PF32
+*  GPIO_33      PH1         PF33
+*  GPIO_34      PH2         PF34
+*  GPIO_35      PH3         PF35
+*  GPIO_36      PH4         PF36
+*  GPIO_37      PH5         PF37
+*  GPIO_38      PH6         PF38
+*  GPIO_39      PH7         PF39
+*  GPIO_40      PH8         PF40
+*  GPIO_41      PH9         PF41
+*  GPIO_42      PH10        PF42
+*  GPIO_43      PH11        PF43
+*  GPIO_44      PH12        PF44
+*  GPIO_45      PH13        PF45
+*  GPIO_46      PH14        PF46
+*  GPIO_47      PH15        PF47
+*/
+
+#ifndef __ARCH_BLACKFIN_GPIO_H__
+#define __ARCH_BLACKFIN_GPIO_H__
+
+#define gpio_bank(x) ((x) >> 4)
+#define gpio_bit(x)  (1<<((x) & 0xF))
+#define gpio_sub_n(x) ((x) & 0xF)
+
+#define GPIO_BANKSIZE 16
+
+#define GPIO_0  0
+#define GPIO_1  1
+#define GPIO_2  2
+#define GPIO_3  3
+#define GPIO_4  4
+#define GPIO_5  5
+#define GPIO_6  6
+#define GPIO_7  7
+#define GPIO_8  8
+#define GPIO_9  9
+#define GPIO_10 10
+#define GPIO_11 11
+#define GPIO_12 12
+#define GPIO_13 13
+#define GPIO_14 14
+#define GPIO_15 15
+#define GPIO_16 16
+#define GPIO_17 17
+#define GPIO_18 18
+#define GPIO_19 19
+#define GPIO_20 20
+#define GPIO_21 21
+#define GPIO_22 22
+#define GPIO_23 23
+#define GPIO_24 24
+#define GPIO_25 25
+#define GPIO_26 26
+#define GPIO_27 27
+#define GPIO_28 28
+#define GPIO_29 29
+#define GPIO_30 30
+#define GPIO_31 31
+#define GPIO_32 32
+#define GPIO_33 33
+#define GPIO_34 34
+#define GPIO_35 35
+#define GPIO_36 36
+#define GPIO_37 37
+#define GPIO_38 38
+#define GPIO_39 39
+#define GPIO_40 40
+#define GPIO_41 41
+#define GPIO_42 42
+#define GPIO_43 43
+#define GPIO_44 44
+#define GPIO_45 45
+#define GPIO_46 46
+#define GPIO_47 47
+
+
+#define PERIPHERAL_USAGE 1
+#define GPIO_USAGE 0
+
+#ifdef BF533_FAMILY
+#define MAX_BLACKFIN_GPIOS 16
+#endif
+
+#ifdef BF537_FAMILY
+#define MAX_BLACKFIN_GPIOS 48
+#define PORT_F 0
+#define PORT_G 1
+#define PORT_H 2
+#define PORT_J 3
+
+#define GPIO_PF0        0
+#define GPIO_PF1        1
+#define GPIO_PF2        2
+#define GPIO_PF3        3
+#define GPIO_PF4        4
+#define GPIO_PF5        5
+#define GPIO_PF6        6
+#define GPIO_PF7        7
+#define GPIO_PF8        8
+#define GPIO_PF9        9
+#define GPIO_PF10       10
+#define GPIO_PF11       11
+#define GPIO_PF12       12
+#define GPIO_PF13       13
+#define GPIO_PF14       14
+#define GPIO_PF15       15
+#define GPIO_PG0        16
+#define GPIO_PG1        17
+#define GPIO_PG2        18
+#define GPIO_PG3        19
+#define GPIO_PG4        20
+#define GPIO_PG5        21
+#define GPIO_PG6        22
+#define GPIO_PG7        23
+#define GPIO_PG8        24
+#define GPIO_PG9        25
+#define GPIO_PG10       26
+#define GPIO_PG11       27
+#define GPIO_PG12       28
+#define GPIO_PG13       29
+#define GPIO_PG14       30
+#define GPIO_PG15       31
+#define GPIO_PH0        32
+#define GPIO_PH1        33
+#define GPIO_PH2        34
+#define GPIO_PH3        35
+#define GPIO_PH4        36
+#define GPIO_PH5        37
+#define GPIO_PH6        38
+#define GPIO_PH7        39
+#define GPIO_PH8        40
+#define GPIO_PH9        41
+#define GPIO_PH10       42
+#define GPIO_PH11       43
+#define GPIO_PH12       44
+#define GPIO_PH13       45
+#define GPIO_PH14       46
+#define GPIO_PH15       47
+
+#endif
+
+#ifdef BF561_FAMILY
+#define MAX_BLACKFIN_GPIOS 48
+#define PORT_FIO0 0
+#define PORT_FIO1 1
+#define PORT_FIO2 2
+#endif
+
+#ifndef __ASSEMBLY__
+
+/***********************************************************
+*
+* FUNCTIONS: Blackfin General Purpose Ports Access Functions
+*
+* INPUTS/OUTPUTS:
+* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
+*
+*
+* DESCRIPTION: These functions abstract direct register access
+*              to Blackfin processor General Purpose
+*              Ports Regsiters
+*
+* CAUTION: These functions do not belong to the GPIO Driver API
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+void set_gpio_dir(unsigned short, unsigned short);
+void set_gpio_inen(unsigned short, unsigned short);
+void set_gpio_polar(unsigned short, unsigned short);
+void set_gpio_edge(unsigned short, unsigned short);
+void set_gpio_both(unsigned short, unsigned short);
+void set_gpio_data(unsigned short, unsigned short);
+void set_gpio_maska(unsigned short, unsigned short);
+void set_gpio_maskb(unsigned short, unsigned short);
+void set_gpio_toggle(unsigned short);
+void set_gpiop_dir(unsigned short, unsigned short);
+void set_gpiop_inen(unsigned short, unsigned short);
+void set_gpiop_polar(unsigned short, unsigned short);
+void set_gpiop_edge(unsigned short, unsigned short);
+void set_gpiop_both(unsigned short, unsigned short);
+void set_gpiop_data(unsigned short, unsigned short);
+void set_gpiop_maska(unsigned short, unsigned short);
+void set_gpiop_maskb(unsigned short, unsigned short);
+unsigned short get_gpio_dir(unsigned short);
+unsigned short get_gpio_inen(unsigned short);
+unsigned short get_gpio_polar(unsigned short);
+unsigned short get_gpio_edge(unsigned short);
+unsigned short get_gpio_both(unsigned short);
+unsigned short get_gpio_maska(unsigned short);
+unsigned short get_gpio_maskb(unsigned short);
+unsigned short get_gpio_data(unsigned short);
+unsigned short get_gpiop_dir(unsigned short);
+unsigned short get_gpiop_inen(unsigned short);
+unsigned short get_gpiop_polar(unsigned short);
+unsigned short get_gpiop_edge(unsigned short);
+unsigned short get_gpiop_both(unsigned short);
+unsigned short get_gpiop_maska(unsigned short);
+unsigned short get_gpiop_maskb(unsigned short);
+unsigned short get_gpiop_data(unsigned short);
+
+struct gpio_port_t {
+        unsigned short data;
+        unsigned short dummy1;
+        unsigned short data_clear;
+        unsigned short dummy2;
+        unsigned short data_set;
+        unsigned short dummy3;
+        unsigned short toggle;
+        unsigned short dummy4;
+        unsigned short maska;
+        unsigned short dummy5;
+        unsigned short maska_clear;
+        unsigned short dummy6;
+        unsigned short maska_set;
+        unsigned short dummy7;
+        unsigned short maska_toggle;
+        unsigned short dummy8;
+        unsigned short maskb;
+        unsigned short dummy9;
+        unsigned short maskb_clear;
+        unsigned short dummy10;
+        unsigned short maskb_set;
+        unsigned short dummy11;
+        unsigned short maskb_toggle;
+        unsigned short dummy12;
+        unsigned short dir;
+        unsigned short dummy13;
+        unsigned short polar;
+        unsigned short dummy14;
+        unsigned short edge;
+        unsigned short dummy15;
+        unsigned short both;
+        unsigned short dummy16;
+        unsigned short inen;
+};
+
+#ifdef CONFIG_PM
+#define PM_WAKE_RISING  0x1
+#define PM_WAKE_FALLING 0x2
+#define PM_WAKE_HIGH    0x4
+#define PM_WAKE_LOW     0x8
+#define PM_WAKE_BOTH_EDGES      (PM_WAKE_RISING | PM_WAKE_FALLING)
+
+int gpio_pm_wakeup_request(unsigned short gpio, unsigned char type);
+void gpio_pm_wakeup_free(unsigned short gpio);
+unsigned int gpio_pm_setup(void);
+void gpio_pm_restore(void);
+
+struct gpio_port_s {
+        unsigned short data;
+        unsigned short data_clear;
+        unsigned short data_set;
+        unsigned short toggle;
+        unsigned short maska;
+        unsigned short maska_clear;
+        unsigned short maska_set;
+        unsigned short maska_toggle;
+        unsigned short maskb;
+        unsigned short maskb_clear;
+        unsigned short maskb_set;
+        unsigned short maskb_toggle;
+        unsigned short dir;
+        unsigned short polar;
+        unsigned short edge;
+        unsigned short both;
+        unsigned short inen;
+
+        unsigned short fer;
+};
+#endif /*CONFIG_PM*/
+
+/***********************************************************
+*
+* FUNCTIONS: Blackfin GPIO Driver
+*
+* INPUTS/OUTPUTS:
+* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
+*
+*
+* DESCRIPTION: Blackfin GPIO Driver API
+*
+* CAUTION:
+*************************************************************
+* MODIFICATION HISTORY :
+**************************************************************/
+
+int gpio_request(unsigned short, const char *);
+void gpio_free(unsigned short);
+
+void gpio_set_value(unsigned short gpio, unsigned short arg);
+unsigned short gpio_get_value(unsigned short gpio);
+
+#define gpio_get_value(gpio)            get_gpio_data(gpio)
+#define gpio_set_value(gpio, value)     set_gpio_data(gpio, value)
+
+void gpio_direction_input(unsigned short gpio);
+void gpio_direction_output(unsigned short gpio);
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ARCH_BLACKFIN_GPIO_H__ */
diff --git a/include/asm-blackfin/hardirq.h b/include/asm-blackfin/hardirq.h
new file mode 100644
index 000000000000..0cab0d35badc
--- /dev/null
+++ b/include/asm-blackfin/hardirq.h
@@ -0,0 +1,41 @@
+#ifndef __BFIN_HARDIRQ_H
+#define __BFIN_HARDIRQ_H
+
+#include <linux/cache.h>
+#include <linux/threads.h>
+#include <asm/irq.h>
+
+typedef struct {
+        unsigned int __softirq_pending;
+        unsigned int __syscall_count;
+        struct task_struct *__ksoftirqd_task;
+} ____cacheline_aligned irq_cpustat_t;
+
+#include <linux/irq_cpustat.h>  /* Standard mappings for irq_cpustat_t above */
+
+/*
+ * We put the hardirq and softirq counter into the preemption
+ * counter. The bitmask has the following meaning:
+ *
+ * - bits 0-7 are the preemption count (max preemption depth: 256)
+ * - bits 8-15 are the softirq count (max # of softirqs: 256)
+ * - bits 16-23 are the hardirq count (max # of hardirqs: 256)
+ *
+ * - ( bit 26 is the PREEMPT_ACTIVE flag. )
+ *
+ * PREEMPT_MASK: 0x000000ff
+ * HARDIRQ_MASK: 0x0000ff00
+ * SOFTIRQ_MASK: 0x00ff0000
+ */
+
+#define HARDIRQ_BITS    8
+
+#ifdef NR_IRQS
+# if (1 << HARDIRQ_BITS) < NR_IRQS
+# error HARDIRQ_BITS is too low!
+# endif
+#endif
+
+#define __ARCH_IRQ_EXIT_IRQS_DISABLED   1
+
+#endif
diff --git a/include/asm-blackfin/hw_irq.h b/include/asm-blackfin/hw_irq.h
new file mode 100644
index 000000000000..5b51eaec012c
--- /dev/null
+++ b/include/asm-blackfin/hw_irq.h
@@ -0,0 +1,6 @@
+#ifndef __ASM_BFIN_HW_IRQ_H
+#define __ASM_BFIN_HW_IRQ_H
+
+/* Dummy include. */
+
+#endif
diff --git a/include/asm-blackfin/ide.h b/include/asm-blackfin/ide.h
new file mode 100644
index 000000000000..41b2db46a168
--- /dev/null
+++ b/include/asm-blackfin/ide.h
@@ -0,0 +1,32 @@
+/****************************************************************************/
+
+/*
+ *  linux/include/asm-blackfin/ide.h
+ *
+ *  Copyright (C) 1994-1996  Linus Torvalds & authors
+ *  Copyright (C) 2001       Lineo Inc., davidm@snapgear.com
+ *  Copyright (C) 2002       Greg Ungerer (gerg@snapgear.com)
+ *  Copyright (C) 2002       Yoshinori Sato (ysato@users.sourceforge.jp)
+ *  Copyright (C) 2005       Hennerich Michael (hennerich@blackfin.uclinux.org)
+ */
+
+/****************************************************************************/
+#ifndef _BLACKFIN_IDE_H
+#define _BLACKFIN_IDE_H
+/****************************************************************************/
+#ifdef __KERNEL__
+/****************************************************************************/
+
+#define MAX_HWIFS       1
+
+/* Legacy ... BLK_DEV_IDECS */
+#define IDE_ARCH_OBSOLETE_INIT
+#define ide_default_io_ctl(base)        ((base) + 0x206) /* obsolete */
+
+
+#include <asm-generic/ide_iops.h>
+
+/****************************************************************************/
+#endif                          /* __KERNEL__ */
+#endif                          /* _BLACKFIN_IDE_H */
+/****************************************************************************/
diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h
new file mode 100644
index 000000000000..7e6995e80d97
--- /dev/null
+++ b/include/asm-blackfin/io.h
@@ -0,0 +1,207 @@
+#ifndef _BFIN_IO_H
+#define _BFIN_IO_H
+
+#ifdef __KERNEL__
+
+#ifndef __ASSEMBLY__
+#include <linux/types.h>
+#endif
+#include <linux/compiler.h>
+
+/*
+ * These are for ISA/PCI shared memory _only_ and should never be used
+ * on any other type of memory, including Zorro memory. They are meant to
+ * access the bus in the bus byte order which is little-endian!.
+ *
+ * readX/writeX() are used to access memory mapped devices. On some
+ * architectures the memory mapped IO stuff needs to be accessed
+ * differently. On the bfin architecture, we just read/write the
+ * memory location directly.
+ */
+#ifndef __ASSEMBLY__
+
+static inline unsigned char readb(void __iomem *addr)
+{
+        unsigned int val;
+        int tmp;
+
+        __asm__ __volatile__ ("cli %1;\n\t"
+                        "NOP; NOP; SSYNC;\n\t"
+                        "%0 = b [%2] (z);\n\t"
+                        "sti %1;\n\t"
+                        : "=d"(val), "=d"(tmp): "a"(addr)
+                        );
+
+        return (unsigned char) val;
+}
+
+static inline unsigned short readw(void __iomem *addr)
+{
+        unsigned int val;
+        int tmp;
+
+        __asm__ __volatile__ ("cli %1;\n\t"
+                        "NOP; NOP; SSYNC;\n\t"
+                        "%0 = w [%2] (z);\n\t"
+                        "sti %1;\n\t"
+                        : "=d"(val), "=d"(tmp): "a"(addr)
+                        );
+
+        return (unsigned short) val;
+}
+
+static inline unsigned int readl(void __iomem *addr)
+{
+        unsigned int val;
+        int tmp;
+
+        __asm__ __volatile__ ("cli %1;\n\t"
+                        "NOP; NOP; SSYNC;\n\t"
+                        "%0 = [%2];\n\t"
+                        "sti %1;\n\t"
+                        : "=d"(val), "=d"(tmp): "a"(addr)
+                        );
+        return val;
+}
+
+#endif /*  __ASSEMBLY__ */
+
+#define writeb(b,addr) (void)((*(volatile unsigned char *) (addr)) = (b))
+#define writew(b,addr) (void)((*(volatile unsigned short *) (addr)) = (b))
+#define writel(b,addr) (void)((*(volatile unsigned int *) (addr)) = (b))
+
+#define __raw_readb readb
+#define __raw_readw readw
+#define __raw_readl readl
+#define __raw_writeb writeb
+#define __raw_writew writew
+#define __raw_writel writel
+#define memset_io(a,b,c)        memset((void *)(a),(b),(c))
+#define memcpy_fromio(a,b,c)    memcpy((a),(void *)(b),(c))
+#define memcpy_toio(a,b,c)      memcpy((void *)(a),(b),(c))
+
+#define inb(addr)    readb(addr)
+#define inw(addr)    readw(addr)
+#define inl(addr)    readl(addr)
+#define outb(x,addr) ((void) writeb(x,addr))
+#define outw(x,addr) ((void) writew(x,addr))
+#define outl(x,addr) ((void) writel(x,addr))
+
+#define inb_p(addr)    inb(addr)
+#define inw_p(addr)    inw(addr)
+#define inl_p(addr)    inl(addr)
+#define outb_p(x,addr) outb(x,addr)
+#define outw_p(x,addr) outw(x,addr)
+#define outl_p(x,addr) outl(x,addr)
+
+#define ioread8_rep(a,d,c)      insb(a,d,c)
+#define ioread16_rep(a,d,c)     insw(a,d,c)
+#define ioread32_rep(a,d,c)     insl(a,d,c)
+#define iowrite8_rep(a,s,c)     outsb(a,s,c)
+#define iowrite16_rep(a,s,c)    outsw(a,s,c)
+#define iowrite32_rep(a,s,c)    outsl(a,s,c)
+
+#define ioread8(X)                      readb(X)
+#define ioread16(X)                     readw(X)
+#define ioread32(X)                     readl(X)
+#define iowrite8(val,X)                 writeb(val,X)
+#define iowrite16(val,X)                writew(val,X)
+#define iowrite32(val,X)                writel(val,X)
+
+#define IO_SPACE_LIMIT 0xffffffff
+
+/* Values for nocacheflag and cmode */
+#define IOMAP_NOCACHE_SER               1
+
+#ifndef __ASSEMBLY__
+
+extern void outsb(void __iomem *port, const void *addr, unsigned long count);
+extern void outsw(void __iomem *port, const void *addr, unsigned long count);
+extern void outsl(void __iomem *port, const void *addr, unsigned long count);
+
+extern void insb(const void __iomem *port, void *addr, unsigned long count);
+extern void insw(const void __iomem *port, void *addr, unsigned long count);
+extern void insl(const void __iomem *port, void *addr, unsigned long count);
+
+/*
+ * Map some physical address range into the kernel address space.
+ */
+static inline void __iomem *__ioremap(unsigned long physaddr, unsigned long size,
+                                int cacheflag)
+{
+        return (void __iomem *)physaddr;
+}
+
+/*
+ * Unmap a ioremap()ed region again
+ */
+static inline void iounmap(void *addr)
+{
+}
+
+/*
+ * __iounmap unmaps nearly everything, so be careful
+ * it doesn't free currently pointer/page tables anymore but it
+ * wans't used anyway and might be added later.
+ */
+static inline void __iounmap(void *addr, unsigned long size)
+{
+}
+
+/*
+ * Set new cache mode for some kernel address space.
+ * The caller must push data for that range itself, if such data may already
+ * be in the cache.
+ */
+static inline void kernel_set_cachemode(void *addr, unsigned long size,
+                                        int cmode)
+{
+}
+
+static inline void __iomem *ioremap(unsigned long physaddr, unsigned long size)
+{
+        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+static inline void __iomem *ioremap_nocache(unsigned long physaddr,
+                                            unsigned long size)
+{
+        return __ioremap(physaddr, size, IOMAP_NOCACHE_SER);
+}
+
+extern void blkfin_inv_cache_all(void);
+
+#endif
+
+#define ioport_map(port, nr)            ((void __iomem*)(port))
+#define ioport_unmap(addr)
+
+#define dma_cache_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+#define dma_cache_wback(_start,_size) do { } while (0)
+#define dma_cache_wback_inv(_start,_size) do { blkfin_inv_cache_all();} while (0)
+
+/* Pages to physical address... */
+#define page_to_phys(page)      ((page - mem_map) << PAGE_SHIFT)
+#define page_to_bus(page)       ((page - mem_map) << PAGE_SHIFT)
+
+#define mm_ptov(vaddr)          ((void *) (vaddr))
+#define mm_vtop(vaddr)          ((unsigned long) (vaddr))
+#define phys_to_virt(vaddr)     ((void *) (vaddr))
+#define virt_to_phys(vaddr)     ((unsigned long) (vaddr))
+
+#define virt_to_bus virt_to_phys
+#define bus_to_virt phys_to_virt
+
+/*
+ * Convert a physical pointer to a virtual kernel pointer for /dev/mem
+ * access
+ */
+#define xlate_dev_mem_ptr(p)    __va(p)
+
+/*
+ * Convert a virtual cached pointer to an uncached pointer
+ */
+#define xlate_dev_kmem_ptr(p)   p
+
+#endif                          /* __KERNEL__ */
+
+#endif                          /* _BFIN_IO_H */
diff --git a/include/asm-blackfin/ioctl.h b/include/asm-blackfin/ioctl.h
new file mode 100644
index 000000000000..b279fe06dfe5
--- /dev/null
+++ b/include/asm-blackfin/ioctl.h
@@ -0,0 +1 @@
+#include <asm-generic/ioctl.h>
diff --git a/include/asm-blackfin/ioctls.h b/include/asm-blackfin/ioctls.h
new file mode 100644
index 000000000000..8356204151db
--- /dev/null
+++ b/include/asm-blackfin/ioctls.h
@@ -0,0 +1,82 @@
+#ifndef __ARCH_BFIN_IOCTLS_H__
+#define __ARCH_BFIN_IOCTLS_H__
+
+#include <asm/ioctl.h>
+
+/* 0x54 is just a magic number to make these relatively unique ('T') */
+
+#define TCGETS          0x5401
+#define TCSETS          0x5402
+#define TCSETSW         0x5403
+#define TCSETSF         0x5404
+#define TCGETA          0x5405
+#define TCSETA          0x5406
+#define TCSETAW         0x5407
+#define TCSETAF         0x5408
+#define TCSBRK          0x5409
+#define TCXONC          0x540A
+#define TCFLSH          0x540B
+#define TIOCEXCL        0x540C
+#define TIOCNXCL        0x540D
+#define TIOCSCTTY       0x540E
+#define TIOCGPGRP       0x540F
+#define TIOCSPGRP       0x5410
+#define TIOCOUTQ        0x5411
+#define TIOCSTI         0x5412
+#define TIOCGWINSZ      0x5413
+#define TIOCSWINSZ      0x5414
+#define TIOCMGET        0x5415
+#define TIOCMBIS        0x5416
+#define TIOCMBIC        0x5417
+#define TIOCMSET        0x5418
+#define TIOCGSOFTCAR    0x5419
+#define TIOCSSOFTCAR    0x541A
+#define FIONREAD        0x541B
+#define TIOCINQ         FIONREAD
+#define TIOCLINUX       0x541C
+#define TIOCCONS        0x541D
+#define TIOCGSERIAL     0x541E
+#define TIOCSSERIAL     0x541F
+#define TIOCPKT         0x5420
+#define FIONBIO         0x5421
+#define TIOCNOTTY       0x5422
+#define TIOCSETD        0x5423
+#define TIOCGETD        0x5424
+#define TCSBRKP         0x5425  /* Needed for POSIX tcsendbreak() */
+#define TIOCTTYGSTRUCT  0x5426  /* For debugging only */
+#define TIOCSBRK        0x5427  /* BSD compatibility */
+#define TIOCCBRK        0x5428  /* BSD compatibility */
+#define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TIOCGPTN        _IOR('T',0x30, unsigned int)    /* Get Pty Number (of pty-mux device) */
+#define TIOCSPTLCK      _IOW('T',0x31, int)     /* Lock/unlock Pty */
+
+#define FIONCLEX        0x5450  /* these numbers need to be adjusted. */
+#define FIOCLEX         0x5451
+#define FIOASYNC        0x5452
+#define TIOCSERCONFIG   0x5453
+#define TIOCSERGWILD    0x5454
+#define TIOCSERSWILD    0x5455
+#define TIOCGLCKTRMIOS  0x5456
+#define TIOCSLCKTRMIOS  0x5457
+#define TIOCSERGSTRUCT  0x5458  /* For debugging only */
+#define TIOCSERGETLSR   0x5459  /* Get line status register */
+#define TIOCSERGETMULTI 0x545A  /* Get multiport config  */
+#define TIOCSERSETMULTI 0x545B  /* Set multiport config */
+
+#define TIOCMIWAIT      0x545C  /* wait for a change on serial input line(s) */
+#define TIOCGICOUNT     0x545D  /* read serial port inline interrupt counts */
+
+#define FIOQSIZE        0x545E
+
+/* Used for packet mode */
+#define TIOCPKT_DATA             0
+#define TIOCPKT_FLUSHREAD        1
+#define TIOCPKT_FLUSHWRITE       2
+#define TIOCPKT_STOP             4
+#define TIOCPKT_START            8
+#define TIOCPKT_NOSTOP          16
+#define TIOCPKT_DOSTOP          32
+
+#define TIOCSER_TEMT    0x01    /* Transmitter physically empty */
+
+#endif                          /* __ARCH_BFIN_IOCTLS_H__ */
diff --git a/include/asm-blackfin/ipc.h b/include/asm-blackfin/ipc.h
new file mode 100644
index 000000000000..a46e3d9c2a3f
--- /dev/null
+++ b/include/asm-blackfin/ipc.h
@@ -0,0 +1 @@
+#include <asm-generic/ipc.h>
diff --git a/include/asm-blackfin/ipcbuf.h b/include/asm-blackfin/ipcbuf.h
new file mode 100644
index 000000000000..8f0899cdf4d2
--- /dev/null
+++ b/include/asm-blackfin/ipcbuf.h
@@ -0,0 +1,30 @@
+/* Changes origined from m68k version.    Lineo Inc.  May 2001   */
+
+#ifndef __BFIN_IPCBUF_H__
+#define __BFIN_IPCBUF_H__
+
+/*
+ * The user_ipc_perm structure for m68k architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 32-bit mode_t and seq
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct ipc64_perm {
+        __kernel_key_t key;
+        __kernel_uid32_t uid;
+        __kernel_gid32_t gid;
+        __kernel_uid32_t cuid;
+        __kernel_gid32_t cgid;
+        __kernel_mode_t mode;
+        unsigned short __pad1;
+        unsigned short seq;
+        unsigned short __pad2;
+        unsigned long __unused1;
+        unsigned long __unused2;
+};
+
+#endif                          /* __BFIN_IPCBUF_H__ */
diff --git a/include/asm-blackfin/irq.h b/include/asm-blackfin/irq.h
new file mode 100644
index 000000000000..65480dab244e
--- /dev/null
+++ b/include/asm-blackfin/irq.h
@@ -0,0 +1,70 @@
+/*
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ *
+ * Changed by HuTao Apr18, 2003
+ *
+ * Copyright was missing when I got the code so took from MIPS arch ...MaTed---
+ * Copyright (C) 1994 by Waldorf GMBH, written by Ralf Baechle
+ * Copyright (C) 1995, 96, 97, 98, 99, 2000, 2001 by Ralf Baechle
+ *
+ * Adapted for BlackFin (ADI) by Ted Ma <mated@sympatico.ca>
+ * Copyright (c) 2002 Arcturus Networks Inc. (www.arcturusnetworks.com)
+ * Copyright (c) 2002 Lineo, Inc. <mattw@lineo.com>
+ */
+
+#ifndef _BFIN_IRQ_H_
+#define _BFIN_IRQ_H_
+
+#include <asm/mach/irq.h>
+#include <asm/ptrace.h>
+
+/*******************************************************************************
+ *****   INTRODUCTION ***********
+ *   On the Blackfin, the interrupt structure allows remmapping of the hardware
+ *   levels.
+ * - I'm going to assume that the H/W level is going to stay at the default
+ *   settings. If someone wants to go through and abstart this out, feel free
+ *   to mod the interrupt numbering scheme.
+ * - I'm abstracting the interrupts so that uClinux does not know anything
+ *   about the H/W levels. If you want to change the H/W AND keep the abstracted
+ *   levels that uClinux sees, you should be able to do most of it here.
+ * - I've left the "abstract" numbering sparce in case someone wants to pull the
+ *   interrupts apart (just the TX/RX for the various devices)
+ *******************************************************************************/
+
+/* SYS_IRQS and NR_IRQS are defined in <asm/mach-bf5xx/irq.h>*/
+
+/*
+ * Machine specific interrupt sources.
+ *
+ * Adding an interrupt service routine for a source with this bit
+ * set indicates a special machine specific interrupt source.
+ * The machine specific files define these sources.
+ *
+ * The IRQ_MACHSPEC bit is now gone - the only thing it did was to
+ * introduce unnecessary overhead.
+ *
+ * All interrupt handling is actually machine specific so it is better
+ * to use function pointers, as used by the Sparc port, and select the
+ * interrupt handling functions when initializing the kernel. This way
+ * we save some unnecessary overhead at run-time.
+ *                                                      01/11/97 - Jes
+ */
+
+extern void ack_bad_irq(unsigned int irq);
+
+static __inline__ int irq_canonicalize(int irq)
+{
+        return irq;
+}
+
+/* count of spurious interrupts */
+/* extern volatile unsigned int num_spurious; */
+
+#ifndef NO_IRQ
+#define NO_IRQ ((unsigned int)(-1))
+#endif
+
+#endif                          /* _BFIN_IRQ_H_ */
diff --git a/include/asm-blackfin/irq_handler.h b/include/asm-blackfin/irq_handler.h
new file mode 100644
index 000000000000..d830f0a49a1c
--- /dev/null
+++ b/include/asm-blackfin/irq_handler.h
@@ -0,0 +1,22 @@
+#ifndef _IRQ_HANDLER_H
+#define _IRQ_HANDLER_H
+
+/* BASE LEVEL interrupt handler routines */
+asmlinkage void evt_emulation(void);
+asmlinkage void evt_exception(void);
+asmlinkage void trap(void);
+asmlinkage void evt_ivhw(void);
+asmlinkage void evt_timer(void);
+asmlinkage void evt_evt2(void);
+asmlinkage void evt_evt7(void);
+asmlinkage void evt_evt8(void);
+asmlinkage void evt_evt9(void);
+asmlinkage void evt_evt10(void);
+asmlinkage void evt_evt11(void);
+asmlinkage void evt_evt12(void);
+asmlinkage void evt_evt13(void);
+asmlinkage void evt_soft_int1(void);
+asmlinkage void evt_system_call(void);
+asmlinkage void init_exception_buff(void);
+
+#endif
diff --git a/include/asm-blackfin/irq_regs.h b/include/asm-blackfin/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/include/asm-blackfin/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/include/asm-blackfin/kdebug.h b/include/asm-blackfin/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-blackfin/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-blackfin/kmap_types.h b/include/asm-blackfin/kmap_types.h
new file mode 100644
index 000000000000..e215f7104974
--- /dev/null
+++ b/include/asm-blackfin/kmap_types.h
@@ -0,0 +1,21 @@
+#ifndef _ASM_KMAP_TYPES_H
+#define _ASM_KMAP_TYPES_H
+
+enum km_type {
+        KM_BOUNCE_READ,
+        KM_SKB_SUNRPC_DATA,
+        KM_SKB_DATA_SOFTIRQ,
+        KM_USER0,
+        KM_USER1,
+        KM_BIO_SRC_IRQ,
+        KM_BIO_DST_IRQ,
+        KM_PTE0,
+        KM_PTE1,
+        KM_IRQ0,
+        KM_IRQ1,
+        KM_SOFTIRQ0,
+        KM_SOFTIRQ1,
+        KM_TYPE_NR
+};
+
+#endif
diff --git a/include/asm-blackfin/l1layout.h b/include/asm-blackfin/l1layout.h
new file mode 100644
index 000000000000..c13ded777828
--- /dev/null
+++ b/include/asm-blackfin/l1layout.h
@@ -0,0 +1,31 @@
+/*
+ * l1layout.h
+ * Defines a layout of L1 scratchpad memory that userspace can rely on.
+ */
+
+#ifndef _L1LAYOUT_H_
+#define _L1LAYOUT_H_
+
+#include <asm/blackfin.h>
+
+#ifndef __ASSEMBLY__
+
+/* Data that is "mapped" into the process VM at the start of the L1 scratch
+   memory, so that each process can access it at a fixed address.  Used for
+   stack checking.  */
+struct l1_scratch_task_info
+{
+        /* Points to the start of the stack.  */
+        void *stack_start;
+        /* Not updated by the kernel; a user process can modify this to
+           keep track of the lowest address of the stack pointer during its
+           runtime.  */
+        void *lowest_sp;
+};
+
+/* A pointer to the structure in memory.  */
+#define L1_SCRATCH_TASK_INFO ((struct l1_scratch_task_info *)L1_SCRATCH_START)
+
+#endif
+
+#endif
diff --git a/include/asm-blackfin/linkage.h b/include/asm-blackfin/linkage.h
new file mode 100644
index 000000000000..5a822bb790f7
--- /dev/null
+++ b/include/asm-blackfin/linkage.h
@@ -0,0 +1,7 @@
+#ifndef __ASM_LINKAGE_H
+#define __ASM_LINKAGE_H
+
+#define __ALIGN .align 4
+#define __ALIGN_STR ".align 4"
+
+#endif
diff --git a/include/asm-blackfin/local.h b/include/asm-blackfin/local.h
new file mode 100644
index 000000000000..75afffbc6421
--- /dev/null
+++ b/include/asm-blackfin/local.h
@@ -0,0 +1,6 @@
+#ifndef __BLACKFIN_LOCAL_H
+#define __BLACKFIN_LOCAL_H
+
+#include <asm-generic/local.h>
+
+#endif                          /* __BLACKFIN_LOCAL_H */
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h
new file mode 100644
index 000000000000..a84d3909345e
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/anomaly.h
@@ -0,0 +1,175 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision U, May 17, 2006; ADSP-BF533 Blackfin Processor Anomaly List
+ *  - Revision Y, May 17, 2006; ADSP-BF532 Blackfin Processor Anomaly List
+ *  - Revision T, May 17, 2006; ADSP-BF531 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 or 0.2 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2))
+#error Kernel will not work on BF533 Version 0.1 or 0.2
+#endif
+
+/* Issues that are common to 0.5, 0.4, and 0.3 silicon */
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+                            slot1 and store of a P register in slot 2 is not
+                            supported */
+#define ANOMALY_05000105 /* Watchpoint Status Register (WPSTAT) bits are set on
+                            every corresponding match */
+#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+                            Channel DMA stops */
+#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+                            registers. */
+#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+                            upper bits*/
+#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
+#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+                            syncs */
+#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
+                            functional */
+#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
+                            state */
+#define ANOMALY_05000229 /* SPI Slave Boot Mode modifies registers */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+                            VDDint <=0.9V */
+#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+                            an edge is detected may clear interrupt */
+#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
+                            DMA system instability */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+                            not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+                            control */
+#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
+                            killed in a particular stage*/
+#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
+                            registers are interrupted */
+#define ANOMALY_05000311 /* Erroneous flag pin operations under specific sequences*/
+
+#endif
+
+/* These issues only occur on 0.3 or 0.4 BF533 */
+#if (defined(CONFIG_BF_REV_0_4) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
+                            updated at the same time. */
+#define ANOMALY_05000158 /* Boot fails when data cache enabled: Data from a Data
+                            Cache Fill can be corrupted after or during
+                            Instruction DMA if certain core stalls exist */
+#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
+                            Purpose TX or RX modes */
+#define ANOMALY_05000198 /* Failing SYSTEM MMR accesses when stalled by
+                            preceding memory read */
+#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
+                            inactive channels in certain conditions */
+#define ANOMALY_05000202 /* Possible infinite stall with specific dual dag
+                            situation */
+#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
+#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
+#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
+                            data*/
+#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
+                            Differences in certain Conditions */
+#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
+#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
+                            hardware reset */
+#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+                            IDLE around a Change of Control causes
+                            unpredictable results */
+#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
+                            shadow of a conditional branch */
+#define ANOMALY_05000246 /* Data CPLB's should prevent spurious hardware
+                            errors */
+#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+                            interrupt not functional */
+#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
+                            loops may cause the instruction fetch unit to
+                            malfunction */
+#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
+                            the ICPLB Data registers differ */
+#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
+                            instruction will cause an infinite stall in the
+                            second to last instruction in a hardware loop */
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+                            SPORT external receive and transmit clocks. */
+#define ANOMALY_05000269 /* High I/O activity causes the output voltage of the
+                            internal voltage regulator (VDDint) to increase. */
+#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
+                            internal voltage regulator (VDDint) to decrease */
+#endif
+
+/* These issues are only on 0.4 silicon */
+#if (defined(CONFIG_BF_REV_0_4))
+#define ANOMALY_05000234 /* Incorrect Revision Number in DSPID Register */
+#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
+                            (TDM) */
+#endif
+
+/* These issues are only on 0.3 silicon */
+#if defined(CONFIG_BF_REV_0_3)
+#define ANOMALY_05000183 /* Timer Pin limitations for PPI TX Modes with
+                            External Frame Syncs */
+#define ANOMALY_05000189 /* False Protection Exceptions caused by Speculative
+                            Instruction or Data Fetches, or by Fetches at the
+                            boundary of reserved memory space */
+#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
+                            when polarity setting is changed */
+#define ANOMALY_05000194 /* Sport Restarting in specific modes may cause data
+                            corruption */
+#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
+                            fix */
+#define ANOMALY_05000201 /* Receive frame sync not ignored during active
+                            frames in sport MCM */
+#define ANOMALY_05000203 /* Specific sequence that can cause DMA error or DMA
+                            stopping */
+#if defined(CONFIG_BF533)
+#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
+                            allocate cache lines on reads only mode */
+#endif /* CONFIG_BF533 */
+#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
+#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
+                            instructions */
+#define ANOMALY_05000233 /* PPI_FS3 is not driven in 2 or 3 internal Frame
+                            Sync Transmit Mode */
+#define ANOMALY_05000271 /* Spontaneous reset of Internal Voltage Regulator */
+#endif
+
+#endif /*  _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf533/bf533.h b/include/asm-blackfin/mach-bf533/bf533.h
new file mode 100644
index 000000000000..185fc1284858
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bf533.h
@@ -0,0 +1,306 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/bf533.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __MACH_BF533_H__
+#define __MACH_BF533_H__
+
+#define SUPPORTED_REVID 2
+
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR            0x0040
+#define IMASK_IVGHW             0x0020
+
+/***************************/
+
+
+#define BLKFIN_DSUBBANKS        4
+#define BLKFIN_DWAYS            2
+#define BLKFIN_DLINES           64
+#define BLKFIN_ISUBBANKS        4
+#define BLKFIN_IWAYS            4
+#define BLKFIN_ILINES           32
+
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+
+/* IAR0 BIT FIELDS*/
+#define RTC_ERROR_BIT                   0x0FFFFFFF
+#define UART_ERROR_BIT                  0xF0FFFFFF
+#define SPORT1_ERROR_BIT                0xFF0FFFFF
+#define SPI_ERROR_BIT                   0xFFF0FFFF
+#define SPORT0_ERROR_BIT                0xFFFF0FFF
+#define PPI_ERROR_BIT                   0xFFFFF0FF
+#define DMA_ERROR_BIT                   0xFFFFFF0F
+#define PLLWAKE_ERROR_BIT               0xFFFFFFFF
+
+/* IAR1 BIT FIELDS*/
+#define DMA7_UARTTX_BIT                 0x0FFFFFFF
+#define DMA6_UARTRX_BIT                 0xF0FFFFFF
+#define DMA5_SPI_BIT                    0xFF0FFFFF
+#define DMA4_SPORT1TX_BIT               0xFFF0FFFF
+#define DMA3_SPORT1RX_BIT               0xFFFF0FFF
+#define DMA2_SPORT0TX_BIT               0xFFFFF0FF
+#define DMA1_SPORT0RX_BIT               0xFFFFFF0F
+#define DMA0_PPI_BIT                    0xFFFFFFFF
+
+/* IAR2 BIT FIELDS*/
+#define WDTIMER_BIT                     0x0FFFFFFF
+#define MEMDMA1_BIT                     0xF0FFFFFF
+#define MEMDMA0_BIT                     0xFF0FFFFF
+#define PFB_BIT                         0xFFF0FFFF
+#define PFA_BIT                         0xFFFF0FFF
+#define TIMER2_BIT                      0xFFFFF0FF
+#define TIMER1_BIT                      0xFFFFFF0F
+#define TIMER0_BIT                      0xFFFFFFFF
+
+/********************************* EBIU Settings ************************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+
+#ifdef CONFIG_C_AMBEN_ALL
+#define V_AMBEN AMBEN_ALL
+#endif
+#ifdef CONFIG_C_AMBEN
+#define V_AMBEN 0x0
+#endif
+#ifdef CONFIG_C_AMBEN_B0
+#define V_AMBEN AMBEN_B0
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1
+#define V_AMBEN AMBEN_B0_B1
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1_B2
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+#ifdef CONFIG_C_CDPRIO
+#define V_CDPRIO 0x100
+#else
+#define V_CDPRIO 0x0
+#endif
+
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
+
+#define MAX_VC  650000000
+#define MIN_VC  50000000
+
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
+/********************************PLL Settings **************************************/
+#if (CONFIG_VCO_MULT < 0)
+#error "VCO Multiplier is less than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT == 0)
+#error "VCO Multiplier should be greater than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT > 64)
+#error "VCO Multiplier is more than 64. Please select a different value"
+#endif
+
+#ifndef CONFIG_CLKIN_HALF
+#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+#else
+#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
+#endif
+
+#ifndef CONFIG_PLL_BYPASS
+#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
+#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
+#else
+#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
+#endif
+
+#if (CONFIG_SCLK_DIV < 1)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_SCLK_DIV > 15)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_CCLK_DIV != 1)
+#if (CONFIG_CCLK_DIV != 2)
+#if (CONFIG_CCLK_DIV != 4)
+#if (CONFIG_CCLK_DIV != 8)
+#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
+#endif
+#endif
+#endif
+#endif
+
+#if (CONFIG_VCO_HZ > MAX_VC)
+#error "VCO selected is more than maximum value. Please change the VCO multipler"
+#endif
+
+#if (CONFIG_SCLK_HZ > 133000000)
+#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ < 27000000)
+#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ > CONFIG_CCLK_HZ)
+#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
+#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
+#error "Please select sclk less than cclk"
+#endif
+#endif
+#endif
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
+#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
+#endif
+
+#endif                          /* CONFIG_BFIN_KERNEL_CLOCK */
+
+#ifdef CONFIG_BF533
+#define CPU "BF533"
+#define CPUID 0x027a5000
+#endif
+#ifdef CONFIG_BF532
+#define CPU "BF532"
+#define CPUID 0x0275A000
+#endif
+#ifdef CONFIG_BF531
+#define CPU "BF531"
+#define CPUID 0x027a5000
+#endif
+#ifndef CPU
+#define CPU "UNKNOWN"
+#define CPUID 0x0
+#endif
+
+#if (CONFIG_MEM_SIZE % 4)
+#error "SDRAM mem size must be multible of 4MB"
+#endif
+
+#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
+#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
+#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158_WORKAROUND             0x200
+#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else                           /*Write Through */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW  | CPLB_DIRTY \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
+
+#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
+#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
+#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
+#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
+
+#define SIZE_1K 0x00000400      /* 1K */
+#define SIZE_4K 0x00001000      /* 4K */
+#define SIZE_1M 0x00100000      /* 1M */
+#define SIZE_4M 0x00400000      /* 4M */
+
+#define MAX_CPLBS (16 * 2)
+
+/*
+* Number of required data CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 16 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Data Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+* 1 for ASYNC Memory
+*/
+
+
+#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
+
+/*
+* Number of required instruction CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 12 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Instruction Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+*/
+
+#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
+
+#endif                          /* __MACH_BF533_H__  */
diff --git a/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
new file mode 100644
index 000000000000..23bf76aa3451
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/bfin_serial_5xx.h
@@ -0,0 +1,108 @@
+#include <linux/serial.h>
+#include <asm/dma.h>
+
+#define NR_PORTS                1
+
+#define OFFSET_THR              0x00    /* Transmit Holding register            */
+#define OFFSET_RBR              0x00    /* Receive Buffer register              */
+#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
+#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
+#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
+#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
+#define OFFSET_LCR              0x0C    /* Line Control Register                */
+#define OFFSET_MCR              0x10    /* Modem Control Register               */
+#define OFFSET_LSR              0x14    /* Line Status Register                 */
+#define OFFSET_MSR              0x18    /* Modem Status Register                */
+#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
+#define OFFSET_GCTL             0x24    /* Global Control Register              */
+
+#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
+#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
+#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
+#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
+#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
+#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
+#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
+#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+
+#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
+#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
+#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
+#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
+#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+# define CONFIG_SERIAL_BFIN_CTSRTS
+# ifndef CONFIG_UART0_CTS_PIN
+#  define CONFIG_UART0_CTS_PIN -1
+# endif
+# ifndef CONFIG_UART0_RTS_PIN
+#  define CONFIG_UART0_RTS_PIN -1
+# endif
+#endif
+
+struct bfin_serial_port {
+        struct uart_port        port;
+        unsigned int            old_status;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int                     tx_done;
+        int                     tx_count;
+        struct circ_buf         rx_dma_buf;
+        struct timer_list       rx_dma_timer;
+        int                     rx_dma_nrows;
+        unsigned int            tx_dma_channel;
+        unsigned int            rx_dma_channel;
+        struct work_struct      tx_dma_workqueue;
+#else
+        struct work_struct      cts_workqueue;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int                     cts_pin;
+        int                     rts_pin;
+#endif
+};
+
+struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_res {
+        unsigned long   uart_base_addr;
+        int             uart_irq;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        unsigned int    uart_tx_dma_channel;
+        unsigned int    uart_rx_dma_channel;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int             uart_cts_pin;
+        int             uart_rts_pin;
+#endif
+};
+
+struct bfin_serial_res bfin_serial_resource[] = {
+        0xFFC00400,
+        IRQ_UART_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART_TX,
+        CH_UART_RX,
+#endif
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        CONFIG_UART0_CTS_PIN,
+        CONFIG_UART0_RTS_PIN,
+#endif
+};
+
+
+int nr_ports = NR_PORTS;
+static void bfin_serial_hw_init(struct bfin_serial_port *uart)
+{
+
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        if (uart->cts_pin >= 0) {
+                gpio_request(uart->cts_pin, NULL);
+                gpio_direction_input(uart->cts_pin);
+        }
+        if (uart->rts_pin >= 0) {
+                gpio_request(uart->rts_pin, NULL);
+                gpio_direction_input(uart->rts_pin);
+        }
+#endif
+}
diff --git a/include/asm-blackfin/mach-bf533/blackfin.h b/include/asm-blackfin/mach-bf533/blackfin.h
new file mode 100644
index 000000000000..e4384491e972
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/blackfin.h
@@ -0,0 +1,45 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/blackfin.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+
+#define BF533_FAMILY
+
+#include "bf533.h"
+#include "mem_map.h"
+#include "defBF532.h"
+#include "anomaly.h"
+
+#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#include "cdefBF532.h"
+#endif
+
+#endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf533/cdefBF532.h b/include/asm-blackfin/mach-bf533/cdefBF532.h
new file mode 100644
index 000000000000..1d7c494ceb64
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/cdefBF532.h
@@ -0,0 +1,706 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/cdefBF532.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF532_H
+#define _CDEF_BF532_H
+/*
+#if !defined(__ADSPLPBLACKFIN__)
+#warning cdefBF532.h should only be included for 532 compatible chips.
+#endif
+*/
+/*include all Core registers and bit definitions*/
+#include "defBF532.h"
+
+/*include core specific register pointer definitions*/
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+#include <asm/system.h>
+
+/* Clock and System Control (0xFFC0 0400-0xFFC0 07FF) */
+#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)              bfin_write16(PLL_CTL,val)
+#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
+#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
+#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
+#define bfin_read_SWRST()                    bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
+#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
+#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
+#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+        local_irq_save(flags);
+        asm("IDLE;");
+        local_irq_restore(flags);
+        bfin_write32(SIC_IWR, iwr);
+}
+
+/* System Interrupt Controller (0xFFC0 0C00-0xFFC0 0FFF) */
+#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
+#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
+#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
+#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
+#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
+#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
+#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
+#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
+#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
+#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
+
+/* Watchdog Timer (0xFFC0 1000-0xFFC0 13FF) */
+#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
+#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
+#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
+
+/* Real Time Clock (0xFFC0 1400-0xFFC0 17FF) */
+#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
+#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
+#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
+#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
+#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
+#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
+#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
+
+/* General Purpose IO (0xFFC0 2400-0xFFC0 27FF) */
+#define bfin_read_FIO_DIR()                  bfin_read16(FIO_DIR)
+#define bfin_write_FIO_DIR(val)              bfin_write16(FIO_DIR,val)
+#define bfin_read_FIO_FLAG_C()               bfin_read16(FIO_FLAG_C)
+#define bfin_write_FIO_FLAG_C(val)           bfin_write16(FIO_FLAG_C,val)
+#define bfin_read_FIO_FLAG_S()               bfin_read16(FIO_FLAG_S)
+#define bfin_write_FIO_FLAG_S(val)           bfin_write16(FIO_FLAG_S,val)
+#define bfin_read_FIO_MASKA_C()              bfin_read16(FIO_MASKA_C)
+#define bfin_write_FIO_MASKA_C(val)          bfin_write16(FIO_MASKA_C,val)
+#define bfin_read_FIO_MASKA_S()              bfin_read16(FIO_MASKA_S)
+#define bfin_write_FIO_MASKA_S(val)          bfin_write16(FIO_MASKA_S,val)
+#define bfin_read_FIO_MASKB_C()              bfin_read16(FIO_MASKB_C)
+#define bfin_write_FIO_MASKB_C(val)          bfin_write16(FIO_MASKB_C,val)
+#define bfin_read_FIO_MASKB_S()              bfin_read16(FIO_MASKB_S)
+#define bfin_write_FIO_MASKB_S(val)          bfin_write16(FIO_MASKB_S,val)
+#define bfin_read_FIO_POLAR()                bfin_read16(FIO_POLAR)
+#define bfin_write_FIO_POLAR(val)            bfin_write16(FIO_POLAR,val)
+#define bfin_read_FIO_EDGE()                 bfin_read16(FIO_EDGE)
+#define bfin_write_FIO_EDGE(val)             bfin_write16(FIO_EDGE,val)
+#define bfin_read_FIO_BOTH()                 bfin_read16(FIO_BOTH)
+#define bfin_write_FIO_BOTH(val)             bfin_write16(FIO_BOTH,val)
+#define bfin_read_FIO_INEN()                 bfin_read16(FIO_INEN)
+#define bfin_write_FIO_INEN(val)             bfin_write16(FIO_INEN,val)
+#define bfin_read_FIO_FLAG_D()               bfin_read16(FIO_FLAG_D)
+#define bfin_write_FIO_FLAG_D(val)           bfin_write16(FIO_FLAG_D,val)
+#define bfin_read_FIO_FLAG_T()               bfin_read16(FIO_FLAG_T)
+#define bfin_write_FIO_FLAG_T(val)           bfin_write16(FIO_FLAG_T,val)
+#define bfin_read_FIO_MASKA_D()              bfin_read16(FIO_MASKA_D)
+#define bfin_write_FIO_MASKA_D(val)          bfin_write16(FIO_MASKA_D,val)
+#define bfin_read_FIO_MASKA_T()              bfin_read16(FIO_MASKA_T)
+#define bfin_write_FIO_MASKA_T(val)          bfin_write16(FIO_MASKA_T,val)
+#define bfin_read_FIO_MASKB_D()              bfin_read16(FIO_MASKB_D)
+#define bfin_write_FIO_MASKB_D(val)          bfin_write16(FIO_MASKB_D,val)
+#define bfin_read_FIO_MASKB_T()              bfin_read16(FIO_MASKB_T)
+#define bfin_write_FIO_MASKB_T(val)          bfin_write16(FIO_MASKB_T,val)
+
+/* DMA Traffic controls */
+#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
+#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
+#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
+#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
+#define bfin_read_DMA_TC_PER()               bfin_read16(DMA_TC_PER)
+#define bfin_write_DMA_TC_PER(val)           bfin_write16(DMA_TC_PER,val)
+#define bfin_read_DMA_TC_CNT()               bfin_read16(DMA_TC_CNT)
+#define bfin_write_DMA_TC_CNT(val)           bfin_write16(DMA_TC_CNT,val)
+
+/* DMA Controller */
+#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
+#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
+#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
+#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
+#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
+#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
+#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
+#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
+#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
+#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
+#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
+#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
+#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
+#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
+#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
+#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
+#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
+#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
+#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
+#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
+#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
+#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
+#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
+#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
+#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
+#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
+#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)
+#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)
+#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)
+#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)
+#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
+#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
+#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)
+#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)
+#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
+#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
+#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)
+#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)
+#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)
+#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)
+#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
+#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
+#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)
+#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)
+#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
+#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
+#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)
+#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)
+#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)
+#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)
+#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
+#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
+#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)
+#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)
+#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)      bfin_write16(DMA5_IRQ_STATUS,val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()      bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)  bfin_write16(DMA5_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA6_CONFIG()              bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)          bfin_write16(DMA6_CONFIG,val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()       bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
+#define bfin_read_DMA6_START_ADDR()          bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
+#define bfin_read_DMA6_X_COUNT()             bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)         bfin_write16(DMA6_X_COUNT,val)
+#define bfin_read_DMA6_Y_COUNT()             bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)         bfin_write16(DMA6_Y_COUNT,val)
+#define bfin_read_DMA6_X_MODIFY()            bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)        bfin_write16(DMA6_X_MODIFY,val)
+#define bfin_read_DMA6_Y_MODIFY()            bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)        bfin_write16(DMA6_Y_MODIFY,val)
+#define bfin_read_DMA6_CURR_DESC_PTR()       bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
+#define bfin_read_DMA6_CURR_ADDR()           bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
+#define bfin_read_DMA6_CURR_X_COUNT()        bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)    bfin_write16(DMA6_CURR_X_COUNT,val)
+#define bfin_read_DMA6_CURR_Y_COUNT()        bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)    bfin_write16(DMA6_CURR_Y_COUNT,val)
+#define bfin_read_DMA6_IRQ_STATUS()          bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)      bfin_write16(DMA6_IRQ_STATUS,val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()      bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)  bfin_write16(DMA6_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA7_CONFIG()              bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)          bfin_write16(DMA7_CONFIG,val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()       bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
+#define bfin_read_DMA7_START_ADDR()          bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
+#define bfin_read_DMA7_X_COUNT()             bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)         bfin_write16(DMA7_X_COUNT,val)
+#define bfin_read_DMA7_Y_COUNT()             bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)         bfin_write16(DMA7_Y_COUNT,val)
+#define bfin_read_DMA7_X_MODIFY()            bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)        bfin_write16(DMA7_X_MODIFY,val)
+#define bfin_read_DMA7_Y_MODIFY()            bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)        bfin_write16(DMA7_Y_MODIFY,val)
+#define bfin_read_DMA7_CURR_DESC_PTR()       bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
+#define bfin_read_DMA7_CURR_ADDR()           bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
+#define bfin_read_DMA7_CURR_X_COUNT()        bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)    bfin_write16(DMA7_CURR_X_COUNT,val)
+#define bfin_read_DMA7_CURR_Y_COUNT()        bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)    bfin_write16(DMA7_CURR_Y_COUNT,val)
+#define bfin_read_DMA7_IRQ_STATUS()          bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)      bfin_write16(DMA7_IRQ_STATUS,val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()      bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)  bfin_write16(DMA7_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_D1_CONFIG()           bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)       bfin_write16(MDMA_D1_CONFIG,val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()    bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D1_START_ADDR()       bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
+#define bfin_read_MDMA_D1_X_COUNT()          bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)      bfin_write16(MDMA_D1_X_COUNT,val)
+#define bfin_read_MDMA_D1_Y_COUNT()          bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)      bfin_write16(MDMA_D1_Y_COUNT,val)
+#define bfin_read_MDMA_D1_X_MODIFY()         bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)     bfin_write16(MDMA_D1_X_MODIFY,val)
+#define bfin_read_MDMA_D1_Y_MODIFY()         bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)     bfin_write16(MDMA_D1_Y_MODIFY,val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()    bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D1_CURR_ADDR()        bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()     bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()     bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()       bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)   bfin_write16(MDMA_D1_IRQ_STATUS,val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()   bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_S1_CONFIG()           bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)       bfin_write16(MDMA_S1_CONFIG,val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()    bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S1_START_ADDR()       bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
+#define bfin_read_MDMA_S1_X_COUNT()          bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)      bfin_write16(MDMA_S1_X_COUNT,val)
+#define bfin_read_MDMA_S1_Y_COUNT()          bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)      bfin_write16(MDMA_S1_Y_COUNT,val)
+#define bfin_read_MDMA_S1_X_MODIFY()         bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)     bfin_write16(MDMA_S1_X_MODIFY,val)
+#define bfin_read_MDMA_S1_Y_MODIFY()         bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)     bfin_write16(MDMA_S1_Y_MODIFY,val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()    bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S1_CURR_ADDR()        bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()     bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()     bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()       bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)   bfin_write16(MDMA_S1_IRQ_STATUS,val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()   bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_D0_CONFIG()           bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)       bfin_write16(MDMA_D0_CONFIG,val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()    bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D0_START_ADDR()       bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
+#define bfin_read_MDMA_D0_X_COUNT()          bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)      bfin_write16(MDMA_D0_X_COUNT,val)
+#define bfin_read_MDMA_D0_Y_COUNT()          bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)      bfin_write16(MDMA_D0_Y_COUNT,val)
+#define bfin_read_MDMA_D0_X_MODIFY()         bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)     bfin_write16(MDMA_D0_X_MODIFY,val)
+#define bfin_read_MDMA_D0_Y_MODIFY()         bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)     bfin_write16(MDMA_D0_Y_MODIFY,val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()    bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D0_CURR_ADDR()        bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()     bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()     bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()       bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)   bfin_write16(MDMA_D0_IRQ_STATUS,val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()   bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_S0_CONFIG()           bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)       bfin_write16(MDMA_S0_CONFIG,val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()    bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S0_START_ADDR()       bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
+#define bfin_read_MDMA_S0_X_COUNT()          bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)      bfin_write16(MDMA_S0_X_COUNT,val)
+#define bfin_read_MDMA_S0_Y_COUNT()          bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)      bfin_write16(MDMA_S0_Y_COUNT,val)
+#define bfin_read_MDMA_S0_X_MODIFY()         bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)     bfin_write16(MDMA_S0_X_MODIFY,val)
+#define bfin_read_MDMA_S0_Y_MODIFY()         bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)     bfin_write16(MDMA_S0_Y_MODIFY,val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()    bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S0_CURR_ADDR()        bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()     bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()     bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()       bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)   bfin_write16(MDMA_S0_IRQ_STATUS,val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()   bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
+
+/* Aysnchronous Memory Controller - External Bus Interface Unit (0xFFC0 3C00-0xFFC0 3FFF) */
+#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
+#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
+#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC0 4C00-0xFFC0 4FFF) */
+#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
+#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
+#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
+#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)
+
+/* UART Controller */
+#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
+#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
+#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
+#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
+#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
+#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
+#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
+#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
+#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
+#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
+#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
+#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
+#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
+#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
+#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
+#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
+#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
+#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
+/*
+#define UART_MSR
+*/
+#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
+#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
+#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
+#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
+
+/* SPI Controller */
+#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
+#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
+#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
+#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
+#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
+#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
+#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
+
+/* TIMER 0, 1, 2 Registers */
+#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
+#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
+#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
+#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
+
+#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
+#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
+#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
+#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
+
+#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
+#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
+#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
+#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
+
+#define bfin_read_TIMER_ENABLE()             bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)         bfin_write16(TIMER_ENABLE,val)
+#define bfin_read_TIMER_DISABLE()            bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)        bfin_write16(TIMER_DISABLE,val)
+#define bfin_read_TIMER_STATUS()             bfin_read16(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)         bfin_write16(TIMER_STATUS,val)
+
+/* SPORT0 Controller */
+#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
+#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
+#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
+#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
+#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
+#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
+#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
+#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
+#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
+#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
+#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
+#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
+#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
+#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
+#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
+#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
+#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
+#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
+#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
+#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
+#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
+#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
+#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
+
+/* SPORT1 Controller */
+#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
+#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
+#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
+#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
+#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
+#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
+#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
+#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
+#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
+#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
+#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
+#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
+#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
+#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
+#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
+#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
+#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
+#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
+#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
+#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
+#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
+#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
+#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
+
+/* Parallel Peripheral Interface (PPI) */
+#define bfin_read_PPI_CONTROL()              bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)          bfin_write16(PPI_CONTROL,val)
+#define bfin_read_PPI_STATUS()               bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)           bfin_write16(PPI_STATUS,val)
+#define bfin_clear_PPI_STATUS()              bfin_read_PPI_STATUS()
+#define bfin_read_PPI_DELAY()                bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)            bfin_write16(PPI_DELAY,val)
+#define bfin_read_PPI_COUNT()                bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)            bfin_write16(PPI_COUNT,val)
+#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
+
+#endif                          /* _CDEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/defBF532.h b/include/asm-blackfin/mach-bf533/defBF532.h
new file mode 100644
index 000000000000..b240a082aa09
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/defBF532.h
@@ -0,0 +1,1175 @@
+/************************************************************************
+ *
+ * This file is subject to the terms and conditions of the GNU Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ * Non-GPL License also available as part of VisualDSP++
+ * http://www.analog.com/processors/resources/crosscore/visualDspDevSoftware.html
+ *
+ * (c) Copyright 2001-2005 Analog Devices, Inc. All rights reserved
+ *
+ * This file under source code control, please send bugs or changes to:
+ * dsptools.support@analog.com
+ *
+ ************************************************************************/
+/*
+ * File:         include/asm-blackfin/mach-bf533/defBF532.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+/* SYSTEM & MM REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532 */
+
+#ifndef _DEF_BF532_H
+#define _DEF_BF532_H
+/*
+#if !defined(__ADSPLPBLACKFIN__)
+#warning defBF532.h should only be included for 532 compatible chips
+#endif
+*/
+/* include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+
+#define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
+#define PLL_DIV                  0xFFC00004     /* PLL Divide Register (16-bit) */
+#define VR_CTL                   0xFFC00008     /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
+#define CHIPID                 0xFFC00014       /* Chip ID Register */
+#define SWRST                  0xFFC00100       /* Software Reset Register (16-bit) */
+#define SYSCR                  0xFFC00104       /* System Configuration registe */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF) */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register */
+#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0 */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1 */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2 */
+#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register */
+#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register */
+
+/* Watchdog Timer (0xFFC00200 - 0xFFC002FF) */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register */
+
+/* Real Time Clock (0xFFC00300 - 0xFFC003FF) */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Register (alternate macro) */
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR                         0xFFC00400     /* Transmit Holding register */
+#define UART_RBR                         0xFFC00400     /* Receive Buffer register */
+#define UART_DLL                         0xFFC00400     /* Divisor Latch (Low-Byte) */
+#define UART_IER                         0xFFC00404     /* Interrupt Enable Register */
+#define UART_DLH                         0xFFC00404     /* Divisor Latch (High-Byte) */
+#define UART_IIR                         0xFFC00408     /* Interrupt Identification Register */
+#define UART_LCR                         0xFFC0040C     /* Line Control Register */
+#define UART_MCR                         0xFFC00410     /* Modem Control Register */
+#define UART_LSR                         0xFFC00414     /* Line Status Register */
+#if 0
+#define UART_MSR                         0xFFC00418   /* Modem Status Register (UNUSED in ADSP-BF532) */
+#endif
+#define UART_SCR                         0xFFC0041C     /* SCR Scratch Register */
+#define UART_GCTL                        0xFFC00424     /* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL                         0xFFC00500      /* SPI Control Register */
+#define SPI_FLG                         0xFFC00504      /* SPI Flag register */
+#define SPI_STAT                        0xFFC00508      /* SPI Status register */
+#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
+#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
+#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
+
+/* TIMER 0, 1, 2 Registers (0xFFC00600 - 0xFFC006FF) */
+
+#define TIMER0_CONFIG                   0xFFC00600      /* Timer 0 Configuration Register */
+#define TIMER0_COUNTER                  0xFFC00604      /* Timer 0 Counter Register */
+#define TIMER0_PERIOD                   0xFFC00608      /* Timer 0 Period Register */
+#define TIMER0_WIDTH                    0xFFC0060C      /* Timer 0 Width Register */
+
+#define TIMER1_CONFIG                   0xFFC00610      /*  Timer 1 Configuration Register   */
+#define TIMER1_COUNTER                  0xFFC00614      /*  Timer 1 Counter Register         */
+#define TIMER1_PERIOD                   0xFFC00618      /*  Timer 1 Period Register          */
+#define TIMER1_WIDTH                    0xFFC0061C      /*  Timer 1 Width Register           */
+
+#define TIMER2_CONFIG                   0xFFC00620      /* Timer 2 Configuration Register   */
+#define TIMER2_COUNTER                  0xFFC00624      /* Timer 2 Counter Register         */
+#define TIMER2_PERIOD                   0xFFC00628      /* Timer 2 Period Register          */
+#define TIMER2_WIDTH                    0xFFC0062C      /* Timer 2 Width Register           */
+
+#define TIMER_ENABLE                    0xFFC00640      /* Timer Enable Register */
+#define TIMER_DISABLE                   0xFFC00644      /* Timer Disable Register */
+#define TIMER_STATUS                    0xFFC00648      /* Timer Status Register */
+
+/* General Purpose IO (0xFFC00700 - 0xFFC007FF) */
+
+#define FIO_FLAG_D                      0xFFC00700      /* Flag Mask to directly specify state of pins */
+#define FIO_FLAG_C                      0xFFC00704      /* Peripheral Interrupt Flag Register (clear) */
+#define FIO_FLAG_S                      0xFFC00708      /* Peripheral Interrupt Flag Register (set) */
+#define FIO_FLAG_T                      0xFFC0070C      /* Flag Mask to directly toggle state of pins */
+#define FIO_MASKA_D                     0xFFC00710      /* Flag Mask Interrupt A Register (set directly) */
+#define FIO_MASKA_C                     0xFFC00714      /* Flag Mask Interrupt A Register (clear) */
+#define FIO_MASKA_S                     0xFFC00718      /* Flag Mask Interrupt A Register (set) */
+#define FIO_MASKA_T                     0xFFC0071C      /* Flag Mask Interrupt A Register (toggle) */
+#define FIO_MASKB_D                     0xFFC00720      /* Flag Mask Interrupt B Register (set directly) */
+#define FIO_MASKB_C                     0xFFC00724      /* Flag Mask Interrupt B Register (clear) */
+#define FIO_MASKB_S                     0xFFC00728      /* Flag Mask Interrupt B Register (set) */
+#define FIO_MASKB_T                     0xFFC0072C      /* Flag Mask Interrupt B Register (toggle) */
+#define FIO_DIR                         0xFFC00730      /* Peripheral Flag Direction Register */
+#define FIO_POLAR                       0xFFC00734      /* Flag Source Polarity Register */
+#define FIO_EDGE                        0xFFC00738      /* Flag Source Sensitivity Register */
+#define FIO_BOTH                        0xFFC0073C      /* Flag Set on BOTH Edges Register */
+#define FIO_INEN                                        0xFFC00740      /* Flag Input Enable Register  */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* Asynchronous Memory Controller - External Bus Interface Unit  */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                    0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1                    0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register */
+
+/* DMA Traffic controls */
+#define DMA_TCPER 0xFFC00B0C    /* Traffic Control Periods Register */
+#define DMA_TCCNT 0xFFC00B10    /* Traffic Control Current Counts Register */
+#define DMA_TC_PER 0xFFC00B0C   /* Traffic Control Periods Register */
+#define DMA_TC_CNT 0xFFC00B10   /* Traffic Control Current Counts Register */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF) */
+#define DMA0_CONFIG             0xFFC00C08      /* DMA Channel 0 Configuration Register */
+#define DMA0_NEXT_DESC_PTR      0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register */
+#define DMA0_START_ADDR         0xFFC00C04      /* DMA Channel 0 Start Address Register */
+#define DMA0_X_COUNT            0xFFC00C10      /* DMA Channel 0 X Count Register */
+#define DMA0_Y_COUNT            0xFFC00C18      /* DMA Channel 0 Y Count Register */
+#define DMA0_X_MODIFY           0xFFC00C14      /* DMA Channel 0 X Modify Register */
+#define DMA0_Y_MODIFY           0xFFC00C1C      /* DMA Channel 0 Y Modify Register */
+#define DMA0_CURR_DESC_PTR      0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register */
+#define DMA0_CURR_ADDR          0xFFC00C24      /* DMA Channel 0 Current Address Register */
+#define DMA0_CURR_X_COUNT       0xFFC00C30      /* DMA Channel 0 Current X Count Register */
+#define DMA0_CURR_Y_COUNT       0xFFC00C38      /* DMA Channel 0 Current Y Count Register */
+#define DMA0_IRQ_STATUS         0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register */
+#define DMA0_PERIPHERAL_MAP     0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register */
+
+#define DMA1_CONFIG             0xFFC00C48      /* DMA Channel 1 Configuration Register */
+#define DMA1_NEXT_DESC_PTR      0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register */
+#define DMA1_START_ADDR         0xFFC00C44      /* DMA Channel 1 Start Address Register */
+#define DMA1_X_COUNT            0xFFC00C50      /* DMA Channel 1 X Count Register */
+#define DMA1_Y_COUNT            0xFFC00C58      /* DMA Channel 1 Y Count Register */
+#define DMA1_X_MODIFY           0xFFC00C54      /* DMA Channel 1 X Modify Register */
+#define DMA1_Y_MODIFY           0xFFC00C5C      /* DMA Channel 1 Y Modify Register */
+#define DMA1_CURR_DESC_PTR      0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register */
+#define DMA1_CURR_ADDR          0xFFC00C64      /* DMA Channel 1 Current Address Register */
+#define DMA1_CURR_X_COUNT       0xFFC00C70      /* DMA Channel 1 Current X Count Register */
+#define DMA1_CURR_Y_COUNT       0xFFC00C78      /* DMA Channel 1 Current Y Count Register */
+#define DMA1_IRQ_STATUS         0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register */
+#define DMA1_PERIPHERAL_MAP     0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register */
+
+#define DMA2_CONFIG             0xFFC00C88      /* DMA Channel 2 Configuration Register */
+#define DMA2_NEXT_DESC_PTR      0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register */
+#define DMA2_START_ADDR         0xFFC00C84      /* DMA Channel 2 Start Address Register */
+#define DMA2_X_COUNT            0xFFC00C90      /* DMA Channel 2 X Count Register */
+#define DMA2_Y_COUNT            0xFFC00C98      /* DMA Channel 2 Y Count Register */
+#define DMA2_X_MODIFY           0xFFC00C94      /* DMA Channel 2 X Modify Register */
+#define DMA2_Y_MODIFY           0xFFC00C9C      /* DMA Channel 2 Y Modify Register */
+#define DMA2_CURR_DESC_PTR      0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register */
+#define DMA2_CURR_ADDR          0xFFC00CA4      /* DMA Channel 2 Current Address Register */
+#define DMA2_CURR_X_COUNT       0xFFC00CB0      /* DMA Channel 2 Current X Count Register */
+#define DMA2_CURR_Y_COUNT       0xFFC00CB8      /* DMA Channel 2 Current Y Count Register */
+#define DMA2_IRQ_STATUS         0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register */
+#define DMA2_PERIPHERAL_MAP     0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register */
+
+#define DMA3_CONFIG             0xFFC00CC8      /* DMA Channel 3 Configuration Register */
+#define DMA3_NEXT_DESC_PTR      0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register */
+#define DMA3_START_ADDR         0xFFC00CC4      /* DMA Channel 3 Start Address Register */
+#define DMA3_X_COUNT            0xFFC00CD0      /* DMA Channel 3 X Count Register */
+#define DMA3_Y_COUNT            0xFFC00CD8      /* DMA Channel 3 Y Count Register */
+#define DMA3_X_MODIFY           0xFFC00CD4      /* DMA Channel 3 X Modify Register */
+#define DMA3_Y_MODIFY           0xFFC00CDC      /* DMA Channel 3 Y Modify Register */
+#define DMA3_CURR_DESC_PTR      0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register */
+#define DMA3_CURR_ADDR          0xFFC00CE4      /* DMA Channel 3 Current Address Register */
+#define DMA3_CURR_X_COUNT       0xFFC00CF0      /* DMA Channel 3 Current X Count Register */
+#define DMA3_CURR_Y_COUNT       0xFFC00CF8      /* DMA Channel 3 Current Y Count Register */
+#define DMA3_IRQ_STATUS         0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register */
+#define DMA3_PERIPHERAL_MAP     0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register */
+
+#define DMA4_CONFIG             0xFFC00D08      /* DMA Channel 4 Configuration Register */
+#define DMA4_NEXT_DESC_PTR      0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register */
+#define DMA4_START_ADDR         0xFFC00D04      /* DMA Channel 4 Start Address Register */
+#define DMA4_X_COUNT            0xFFC00D10      /* DMA Channel 4 X Count Register */
+#define DMA4_Y_COUNT            0xFFC00D18      /* DMA Channel 4 Y Count Register */
+#define DMA4_X_MODIFY           0xFFC00D14      /* DMA Channel 4 X Modify Register */
+#define DMA4_Y_MODIFY           0xFFC00D1C      /* DMA Channel 4 Y Modify Register */
+#define DMA4_CURR_DESC_PTR      0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register */
+#define DMA4_CURR_ADDR          0xFFC00D24      /* DMA Channel 4 Current Address Register */
+#define DMA4_CURR_X_COUNT       0xFFC00D30      /* DMA Channel 4 Current X Count Register */
+#define DMA4_CURR_Y_COUNT       0xFFC00D38      /* DMA Channel 4 Current Y Count Register */
+#define DMA4_IRQ_STATUS         0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register */
+#define DMA4_PERIPHERAL_MAP     0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register */
+
+#define DMA5_CONFIG             0xFFC00D48      /* DMA Channel 5 Configuration Register */
+#define DMA5_NEXT_DESC_PTR      0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register */
+#define DMA5_START_ADDR         0xFFC00D44      /* DMA Channel 5 Start Address Register */
+#define DMA5_X_COUNT            0xFFC00D50      /* DMA Channel 5 X Count Register */
+#define DMA5_Y_COUNT            0xFFC00D58      /* DMA Channel 5 Y Count Register */
+#define DMA5_X_MODIFY           0xFFC00D54      /* DMA Channel 5 X Modify Register */
+#define DMA5_Y_MODIFY           0xFFC00D5C      /* DMA Channel 5 Y Modify Register */
+#define DMA5_CURR_DESC_PTR      0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register */
+#define DMA5_CURR_ADDR          0xFFC00D64      /* DMA Channel 5 Current Address Register */
+#define DMA5_CURR_X_COUNT       0xFFC00D70      /* DMA Channel 5 Current X Count Register */
+#define DMA5_CURR_Y_COUNT       0xFFC00D78      /* DMA Channel 5 Current Y Count Register */
+#define DMA5_IRQ_STATUS         0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register */
+#define DMA5_PERIPHERAL_MAP     0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register */
+
+#define DMA6_CONFIG             0xFFC00D88      /* DMA Channel 6 Configuration Register */
+#define DMA6_NEXT_DESC_PTR      0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register */
+#define DMA6_START_ADDR         0xFFC00D84      /* DMA Channel 6 Start Address Register */
+#define DMA6_X_COUNT            0xFFC00D90      /* DMA Channel 6 X Count Register */
+#define DMA6_Y_COUNT            0xFFC00D98      /* DMA Channel 6 Y Count Register */
+#define DMA6_X_MODIFY           0xFFC00D94      /* DMA Channel 6 X Modify Register */
+#define DMA6_Y_MODIFY           0xFFC00D9C      /* DMA Channel 6 Y Modify Register */
+#define DMA6_CURR_DESC_PTR      0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register */
+#define DMA6_CURR_ADDR          0xFFC00DA4      /* DMA Channel 6 Current Address Register */
+#define DMA6_CURR_X_COUNT       0xFFC00DB0      /* DMA Channel 6 Current X Count Register */
+#define DMA6_CURR_Y_COUNT       0xFFC00DB8      /* DMA Channel 6 Current Y Count Register */
+#define DMA6_IRQ_STATUS         0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register */
+#define DMA6_PERIPHERAL_MAP     0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register */
+
+#define DMA7_CONFIG             0xFFC00DC8      /* DMA Channel 7 Configuration Register */
+#define DMA7_NEXT_DESC_PTR      0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register */
+#define DMA7_START_ADDR         0xFFC00DC4      /* DMA Channel 7 Start Address Register */
+#define DMA7_X_COUNT            0xFFC00DD0      /* DMA Channel 7 X Count Register */
+#define DMA7_Y_COUNT            0xFFC00DD8      /* DMA Channel 7 Y Count Register */
+#define DMA7_X_MODIFY           0xFFC00DD4      /* DMA Channel 7 X Modify Register */
+#define DMA7_Y_MODIFY           0xFFC00DDC      /* DMA Channel 7 Y Modify Register */
+#define DMA7_CURR_DESC_PTR      0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register */
+#define DMA7_CURR_ADDR          0xFFC00DE4      /* DMA Channel 7 Current Address Register */
+#define DMA7_CURR_X_COUNT       0xFFC00DF0      /* DMA Channel 7 Current X Count Register */
+#define DMA7_CURR_Y_COUNT       0xFFC00DF8      /* DMA Channel 7 Current Y Count Register */
+#define DMA7_IRQ_STATUS         0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register */
+#define DMA7_PERIPHERAL_MAP     0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register */
+
+#define MDMA_D1_CONFIG          0xFFC00E88      /* MemDMA Stream 1 Destination Configuration Register */
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00E80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
+#define MDMA_D1_START_ADDR      0xFFC00E84      /* MemDMA Stream 1 Destination Start Address Register */
+#define MDMA_D1_X_COUNT         0xFFC00E90      /* MemDMA Stream 1 Destination X Count Register */
+#define MDMA_D1_Y_COUNT         0xFFC00E98      /* MemDMA Stream 1 Destination Y Count Register */
+#define MDMA_D1_X_MODIFY        0xFFC00E94      /* MemDMA Stream 1 Destination X Modify Register */
+#define MDMA_D1_Y_MODIFY        0xFFC00E9C      /* MemDMA Stream 1 Destination Y Modify Register */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00EA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
+#define MDMA_D1_CURR_ADDR       0xFFC00EA4      /* MemDMA Stream 1 Destination Current Address Register */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00EB0      /* MemDMA Stream 1 Destination Current X Count Register */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00EB8      /* MemDMA Stream 1 Destination Current Y Count Register */
+#define MDMA_D1_IRQ_STATUS      0xFFC00EA8      /* MemDMA Stream 1 Destination Interrupt/Status Register */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00EAC      /* MemDMA Stream 1 Destination Peripheral Map Register */
+
+#define MDMA_S1_CONFIG          0xFFC00EC8      /* MemDMA Stream 1 Source Configuration Register */
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00EC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
+#define MDMA_S1_START_ADDR      0xFFC00EC4      /* MemDMA Stream 1 Source Start Address Register */
+#define MDMA_S1_X_COUNT         0xFFC00ED0      /* MemDMA Stream 1 Source X Count Register */
+#define MDMA_S1_Y_COUNT         0xFFC00ED8      /* MemDMA Stream 1 Source Y Count Register */
+#define MDMA_S1_X_MODIFY        0xFFC00ED4      /* MemDMA Stream 1 Source X Modify Register */
+#define MDMA_S1_Y_MODIFY        0xFFC00EDC      /* MemDMA Stream 1 Source Y Modify Register */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00EE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
+#define MDMA_S1_CURR_ADDR       0xFFC00EE4      /* MemDMA Stream 1 Source Current Address Register */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00EF0      /* MemDMA Stream 1 Source Current X Count Register */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00EF8      /* MemDMA Stream 1 Source Current Y Count Register */
+#define MDMA_S1_IRQ_STATUS      0xFFC00EE8      /* MemDMA Stream 1 Source Interrupt/Status Register */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00EEC      /* MemDMA Stream 1 Source Peripheral Map Register */
+
+#define MDMA_D0_CONFIG          0xFFC00E08      /* MemDMA Stream 0 Destination Configuration Register */
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00E00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
+#define MDMA_D0_START_ADDR      0xFFC00E04      /* MemDMA Stream 0 Destination Start Address Register */
+#define MDMA_D0_X_COUNT         0xFFC00E10      /* MemDMA Stream 0 Destination X Count Register */
+#define MDMA_D0_Y_COUNT         0xFFC00E18      /* MemDMA Stream 0 Destination Y Count Register */
+#define MDMA_D0_X_MODIFY        0xFFC00E14      /* MemDMA Stream 0 Destination X Modify Register */
+#define MDMA_D0_Y_MODIFY        0xFFC00E1C      /* MemDMA Stream 0 Destination Y Modify Register */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00E20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
+#define MDMA_D0_CURR_ADDR       0xFFC00E24      /* MemDMA Stream 0 Destination Current Address Register */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00E30      /* MemDMA Stream 0 Destination Current X Count Register */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00E38      /* MemDMA Stream 0 Destination Current Y Count Register */
+#define MDMA_D0_IRQ_STATUS      0xFFC00E28      /* MemDMA Stream 0 Destination Interrupt/Status Register */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00E2C      /* MemDMA Stream 0 Destination Peripheral Map Register */
+
+#define MDMA_S0_CONFIG          0xFFC00E48      /* MemDMA Stream 0 Source Configuration Register */
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00E40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
+#define MDMA_S0_START_ADDR      0xFFC00E44      /* MemDMA Stream 0 Source Start Address Register */
+#define MDMA_S0_X_COUNT         0xFFC00E50      /* MemDMA Stream 0 Source X Count Register */
+#define MDMA_S0_Y_COUNT         0xFFC00E58      /* MemDMA Stream 0 Source Y Count Register */
+#define MDMA_S0_X_MODIFY        0xFFC00E54      /* MemDMA Stream 0 Source X Modify Register */
+#define MDMA_S0_Y_MODIFY        0xFFC00E5C      /* MemDMA Stream 0 Source Y Modify Register */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00E60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
+#define MDMA_S0_CURR_ADDR       0xFFC00E64      /* MemDMA Stream 0 Source Current Address Register */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00E70      /* MemDMA Stream 0 Source Current X Count Register */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00E78      /* MemDMA Stream 0 Source Current Y Count Register */
+#define MDMA_S0_IRQ_STATUS      0xFFC00E68      /* MemDMA Stream 0 Source Interrupt/Status Register */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00E6C      /* MemDMA Stream 0 Source Peripheral Map Register */
+
+/* Parallel Peripheral Interface (PPI) (0xFFC01000 - 0xFFC010FF) */
+
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register */
+
+/*********************************************************************************** */
+/* System MMR Register Bits */
+/******************************************************************************* */
+
+/* ********************* PLL AND RESET MASKS ************************ */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN              0x00000000       /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2         0x00000001       /* Pass CLKIN/2 to PLL */
+#define PLL_OFF                0x00000002       /* Shut off PLL clocks */
+#define STOPCK_OFF             0x00000008       /* Core clock off */
+#define PDWN                   0x00000020       /* Put the PLL in a Deep Sleep state */
+#define BYPASS                 0x00000100       /* Bypass the PLL */
+
+/* PLL_DIV Masks */
+
+#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
+
+#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
+#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
+#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
+#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
+
+/* PLL_STAT Masks                                                                                                                                       */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
+#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
+#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Mask */
+#define SYSTEM_RESET           0x00000007       /* Initiates a system software reset */
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+    /* SIC_IAR0 Masks */
+
+#define P0_IVG(x)    ((x)-7)    /* Peripheral #0 assigned IVG #x  */
+#define P1_IVG(x)    ((x)-7) << 0x4     /* Peripheral #1 assigned IVG #x  */
+#define P2_IVG(x)    ((x)-7) << 0x8     /* Peripheral #2 assigned IVG #x  */
+#define P3_IVG(x)    ((x)-7) << 0xC     /* Peripheral #3 assigned IVG #x  */
+#define P4_IVG(x)    ((x)-7) << 0x10    /* Peripheral #4 assigned IVG #x  */
+#define P5_IVG(x)    ((x)-7) << 0x14    /* Peripheral #5 assigned IVG #x  */
+#define P6_IVG(x)    ((x)-7) << 0x18    /* Peripheral #6 assigned IVG #x  */
+#define P7_IVG(x)    ((x)-7) << 0x1C    /* Peripheral #7 assigned IVG #x  */
+
+/* SIC_IAR1 Masks */
+
+#define P8_IVG(x)     ((x)-7)   /* Peripheral #8 assigned IVG #x  */
+#define P9_IVG(x)     ((x)-7) << 0x4    /* Peripheral #9 assigned IVG #x  */
+#define P10_IVG(x)    ((x)-7) << 0x8    /* Peripheral #10 assigned IVG #x  */
+#define P11_IVG(x)    ((x)-7) << 0xC    /* Peripheral #11 assigned IVG #x  */
+#define P12_IVG(x)    ((x)-7) << 0x10   /* Peripheral #12 assigned IVG #x  */
+#define P13_IVG(x)    ((x)-7) << 0x14   /* Peripheral #13 assigned IVG #x  */
+#define P14_IVG(x)    ((x)-7) << 0x18   /* Peripheral #14 assigned IVG #x  */
+#define P15_IVG(x)    ((x)-7) << 0x1C   /* Peripheral #15 assigned IVG #x  */
+
+/* SIC_IAR2 Masks */
+#define P16_IVG(x)    ((x)-7)   /* Peripheral #16 assigned IVG #x  */
+#define P17_IVG(x)    ((x)-7) << 0x4    /* Peripheral #17 assigned IVG #x  */
+#define P18_IVG(x)    ((x)-7) << 0x8    /* Peripheral #18 assigned IVG #x  */
+#define P19_IVG(x)    ((x)-7) << 0xC    /* Peripheral #19 assigned IVG #x  */
+#define P20_IVG(x)    ((x)-7) << 0x10   /* Peripheral #20 assigned IVG #x  */
+#define P21_IVG(x)    ((x)-7) << 0x14   /* Peripheral #21 assigned IVG #x  */
+#define P22_IVG(x)    ((x)-7) << 0x18   /* Peripheral #22 assigned IVG #x  */
+#define P23_IVG(x)    ((x)-7) << 0x1C   /* Peripheral #23 assigned IVG #x  */
+
+/* SIC_IMASK Masks */
+#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
+#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
+#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
+
+/* *********  WATCHDOG TIMER MASKS  ********************8 */
+
+/* Watchdog Timer WDOG_CTL Register */
+#define ICTL(x) ((x<<1) & 0x0006)
+#define ENABLE_RESET     0x00000000     /* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI       0x00000002     /* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI       0x00000004     /* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT      0x00000006     /* Disable Watchdog Timer interrupts */
+
+#define TMR_EN          0x0000
+#define TMR_DIS         0x0AD0
+#define TRO             0x8000
+
+#define ICTL_P0         0x01
+#define ICTL_P1         0x02
+#define TRO_P           0x0F
+
+/* ***************************** UART CONTROLLER MASKS ********************** */
+
+/* UART_LCR Register */
+
+#define DLAB    0x80
+#define SB      0x40
+#define STP      0x20
+#define EPS     0x10
+#define PEN     0x08
+#define STB     0x04
+#define WLS(x)  ((x-5) & 0x03)
+
+#define DLAB_P  0x07
+#define SB_P    0x06
+#define STP_P   0x05
+#define EPS_P   0x04
+#define PEN_P   0x03
+#define STB_P   0x02
+#define WLS_P1  0x01
+#define WLS_P0  0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA        0x10
+#define LOOP_ENA_P      0x04
+
+/* UART_LSR Register */
+#define TEMT    0x40
+#define THRE    0x20
+#define BI      0x10
+#define FE      0x08
+#define PE      0x04
+#define OE      0x02
+#define DR      0x01
+
+#define TEMP_P  0x06
+#define THRE_P  0x05
+#define BI_P    0x04
+#define FE_P    0x03
+#define PE_P    0x02
+#define OE_P    0x01
+#define DR_P    0x00
+
+/* UART_IER Register */
+#define ELSI    0x04
+#define ETBEI   0x02
+#define ERBFI   0x01
+
+#define ELSI_P  0x02
+#define ETBEI_P 0x01
+#define ERBFI_P 0x00
+
+/* UART_IIR Register */
+#define STATUS(x)       ((x << 1) & 0x06)
+#define NINT            0x01
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+#define NINT_P          0x00
+#define IIR_TX_READY    0x02    /* UART_THR empty                               */
+#define IIR_RX_READY    0x04    /* Receive data ready                           */
+#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
+#define IIR_STATUS      0x06
+
+/* UART_GCTL Register */
+#define FFE     0x20
+#define FPE     0x10
+#define RPOLC   0x08
+#define TPOLC   0x04
+#define IREN    0x02
+#define UCEN    0x01
+
+#define FFE_P   0x05
+#define FPE_P   0x04
+#define RPOLC_P 0x03
+#define TPOLC_P 0x02
+#define IREN_P  0x01
+#define UCEN_P  0x00
+
+/* **********  SERIAL PORT MASKS  ********************** */
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN    0x0001         /* TX enable  */
+#define ITCLK    0x0002         /* Internal TX Clock Select  */
+#define TDTYPE   0x000C         /* TX Data Formatting Select */
+#define TLSBIT   0x0010         /* TX Bit Order */
+#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
+#define TFSR     0x0400         /* TX Frame Sync Required Select  */
+#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
+#define LTFS     0x1000         /* Low TX Frame Sync Select  */
+#define LATFS    0x2000         /* Late TX Frame Sync Select  */
+#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN        0x001F      /*TX Word Length  */
+#define TXSE        0x0100      /*TX Secondary Enable */
+#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
+#define TRFST       0x0400      /*TX Right-First Data Order  */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN    0x0001         /* RX enable  */
+#define IRCLK    0x0002         /* Internal RX Clock Select  */
+#define RDTYPE   0x000C         /* RX Data Formatting Select */
+#define RULAW    0x0008         /* u-Law enable  */
+#define RALAW    0x000C         /* A-Law enable  */
+#define RLSBIT   0x0010         /* RX Bit Order */
+#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
+#define RFSR     0x0400         /* RX Frame Sync Required Select  */
+#define LRFS     0x1000         /* Low RX Frame Sync Select  */
+#define LARFS    0x2000         /* Late RX Frame Sync Select  */
+#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN        0x001F      /*RX Word Length  */
+#define RXSE        0x0100      /*RX Secondary Enable */
+#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
+#define RRFST       0x0400      /*Right-First Data Order  */
+
+/*SPORTx_STAT Masks */
+#define RXNE            0x0001  /*RX FIFO Not Empty Status */
+#define RUVF            0x0002  /*RX Underflow Status */
+#define ROVF            0x0004  /*RX Overflow Status */
+#define TXF             0x0008  /*TX FIFO Full Status */
+#define TUVF            0x0010  /*TX Underflow Status */
+#define TOVF            0x0020  /*TX Overflow Status */
+#define TXHRE           0x0040  /*TX Hold Register Empty */
+
+/*SPORTx_MCMC1 Masks */
+#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
+#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
+
+/*SPORTx_MCMC2 Masks */
+#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
+#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
+#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
+#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
+#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
+#define MFD             0x0000F000      /*Multichannel Frame Delay    */
+
+/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
+
+/*  PPI_CONTROL Masks         */
+#define PORT_EN              0x00000001 /* PPI Port Enable  */
+#define PORT_DIR             0x00000002 /* PPI Port Direction       */
+#define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
+#define PORT_CFG             0x00000030 /* PPI Port Configuration */
+#define FLD_SEL              0x00000040 /* PPI Active Field Select */
+#define PACK_EN              0x00000080 /* PPI Packing Mode */
+#define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
+#define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
+#define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
+#define DLENGTH              0x00003800 /* PPI Data Length  */
+#define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
+#define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#define POL                  0x0000C000 /* PPI Signal Polarities       */
+
+/* PPI_STATUS Masks                                          */
+#define FLD                  0x00000400 /* Field Indicator   */
+#define FT_ERR               0x00000800 /* Frame Track Error */
+#define OVR                  0x00001000 /* FIFO Overflow Error */
+#define UNDR                 0x00002000 /* FIFO Underrun Error */
+#define ERR_DET              0x00004000 /* Error Detected Indicator */
+#define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
+
+/* **********  DMA CONTROLLER MASKS  *********************8 */
+
+/*DMAx_CONFIG, MDMA_yy_CONFIG Masks */
+#define DMAEN           0x00000001      /* Channel Enable */
+#define WNR             0x00000002      /* Channel Direction (W/R*) */
+#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
+#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
+#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
+#define DMA2D           0x00000010      /* 2D/1D* Mode */
+#define RESTART         0x00000020      /* Restart */
+#define DI_SEL          0x00000040      /* Data Interrupt Select */
+#define DI_EN           0x00000080      /* Data Interrupt Enable */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
+#define NDSIZE          0x00000900      /* Next Descriptor Size */
+#define DMAFLOW         0x00007000      /* Flow Control */
+#define DMAFLOW_STOP            0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
+
+#define DMAEN_P                 0       /* Channel Enable */
+#define WNR_P                   1       /* Channel Direction (W/R*) */
+#define DMA2D_P                 4       /* 2D/1D* Mode */
+#define RESTART_P               5       /* Restart */
+#define DI_SEL_P                6       /* Data Interrupt Select */
+#define DI_EN_P                 7       /* Data Interrupt Enable */
+
+/*DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks */
+
+#define DMA_DONE                0x00000001      /* DMA Done Indicator */
+#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
+#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
+#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
+
+#define DMA_DONE_P              0       /* DMA Done Indicator */
+#define DMA_ERR_P               1       /* DMA Error Indicator */
+#define DFETCH_P                2       /* Descriptor Fetch Indicator */
+#define DMA_RUN_P               3       /* DMA Running Indicator */
+
+/*DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE               0x00000040  /* DMA Channel Type Indicator */
+#define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
+#define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
+#define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
+#define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
+#define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
+#define PMAP                0x00007000  /* DMA Peripheral Map Field */
+
+/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0  0x0001
+#define TIMEN1  0x0002
+#define TIMEN2  0x0004
+
+#define TIMEN0_P        0x00
+#define TIMEN1_P        0x01
+#define TIMEN2_P        0x02
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0 0x0001
+#define TIMDIS1 0x0002
+#define TIMDIS2 0x0004
+
+#define TIMDIS0_P       0x00
+#define TIMDIS1_P       0x01
+#define TIMDIS2_P       0x02
+
+/* TIMER_STATUS Register */
+#define TIMIL0          0x0001
+#define TIMIL1          0x0002
+#define TIMIL2          0x0004
+#define TOVL_ERR0       0x0010
+#define TOVL_ERR1       0x0020
+#define TOVL_ERR2       0x0040
+#define TRUN0           0x1000
+#define TRUN1           0x2000
+#define TRUN2           0x4000
+
+#define TIMIL0_P        0x00
+#define TIMIL1_P        0x01
+#define TIMIL2_P        0x02
+#define TOVL_ERR0_P     0x04
+#define TOVL_ERR1_P     0x05
+#define TOVL_ERR2_P     0x06
+#define TRUN0_P         0x0C
+#define TRUN1_P         0x0D
+#define TRUN2_P         0x0E
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT         0x0001
+#define WDTH_CAP        0x0002
+#define EXT_CLK         0x0003
+#define PULSE_HI        0x0004
+#define PERIOD_CNT      0x0008
+#define IRQ_ENA         0x0010
+#define TIN_SEL         0x0020
+#define OUT_DIS         0x0040
+#define CLK_SEL         0x0080
+#define TOGGLE_HI       0x0100
+#define EMU_RUN         0x0200
+#define ERR_TYP(x)      ((x & 0x03) << 14)
+
+#define TMODE_P0                0x00
+#define TMODE_P1                0x01
+#define PULSE_HI_P              0x02
+#define PERIOD_CNT_P            0x03
+#define IRQ_ENA_P               0x04
+#define TIN_SEL_P               0x05
+#define OUT_DIS_P               0x06
+#define CLK_SEL_P               0x07
+#define TOGGLE_HI_P             0x08
+#define EMU_RUN_P               0x09
+#define ERR_TYP_P0              0x0E
+#define ERR_TYP_P1              0x0F
+
+/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
+
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
+#define PF0         0x0001
+#define PF1         0x0002
+#define PF2         0x0004
+#define PF3         0x0008
+#define PF4         0x0010
+#define PF5         0x0020
+#define PF6         0x0040
+#define PF7         0x0080
+#define PF8         0x0100
+#define PF9         0x0200
+#define PF10        0x0400
+#define PF11        0x0800
+#define PF12        0x1000
+#define PF13        0x2000
+#define PF14        0x4000
+#define PF15        0x8000
+
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
+#define PF0_P         0
+#define PF1_P         1
+#define PF2_P         2
+#define PF3_P         3
+#define PF4_P         4
+#define PF5_P         5
+#define PF6_P         6
+#define PF7_P         7
+#define PF8_P         8
+#define PF9_P         9
+#define PF10_P        10
+#define PF11_P        11
+#define PF12_P        12
+#define PF13_P        13
+#define PF14_P        14
+#define PF15_P        15
+
+/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
+
+/* SPI_CTL Masks */
+#define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
+#define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
+#define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
+#define SPI_LEN                0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR                   0x00001000       /* Configures SPI as master (=1) or slave (=0) */
+#define WOM                    0x00002000       /* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE                    0x00004000       /* SPI module enable (=1), disable (=0) */
+
+/* SPI_FLG Masks */
+#define FLS1                   0x00000002       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2                   0x00000004       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3                   0x00000008       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4                   0x00000010       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5                   0x00000020       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6                   0x00000040       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7                   0x00000080       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1                   0x00000200       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
+#define FLG2                   0x00000400       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3                   0x00000800       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
+#define FLG4                   0x00001000       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
+#define FLG5                   0x00002000       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
+#define FLG6                   0x00004000       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
+#define FLG7                   0x00008000       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P                 0x00000001       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P                 0x00000002       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P                 0x00000003       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P                 0x00000004       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P                 0x00000005       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P                 0x00000006       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P                 0x00000007       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P                 0x00000009       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
+#define FLG2_P                 0x0000000A       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P                 0x0000000B       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
+#define FLG4_P                 0x0000000C       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
+#define FLG5_P                 0x0000000D       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
+#define FLG6_P                 0x0000000E       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
+#define FLG7_P                 0x0000000F       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF                   0x00000001       /* Set (=1) when SPI single-word transfer complete */
+#define MODF                   0x00000002       /* Set (=1) in a master device when some other device tries to become master */
+#define TXE                    0x00000004       /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS                    0x00000008       /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY                   0x00000010       /* Set (=1) when data is received with RDBR full */
+#define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
+#define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
+
+/* AMGCTL Masks */
+#define AMCKEN                  0x00000001      /* Enable CLKOUT */
+#define AMBEN_B0                0x00000002      /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1             0x00000004      /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2          0x00000006      /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL               0x00000008      /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P                0x00000000      /* Enable CLKOUT */
+#define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
+
+/* **********************  SDRAM CONTROLLER MASKS  *************************** */
+
+/* SDGCTL Masks */
+#define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
+#define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
+#define PFE                     0x00000010      /* Enable SDRAM prefetch */
+#define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
+#define PUPSD                   0x00200000      /*Power-up start delay */
+#define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
+#define EBUFE                   0x02000000      /* Enable external buffering timing */
+#define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
+#define EMREN                   0x10000000      /* Extended mode register enable */
+#define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
+#define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EBE                     0x00000001      /* Enable SDRAM external bank */
+#define EBSZ_16                 0x00000000      /* SDRAM external bank size = 16MB */
+#define EBSZ_32                 0x00000002      /* SDRAM external bank size = 32MB */
+#define EBSZ_64                 0x00000004      /* SDRAM external bank size = 64MB */
+#define EBSZ_128                        0x00000006      /* SDRAM external bank size = 128MB */
+#define EBCAW_8                 0x00000000      /* SDRAM external bank column address width = 8 bits */
+#define EBCAW_9                 0x00000010      /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_10                        0x00000020      /* SDRAM external bank column address width = 9 bits */
+#define EBCAW_11                        0x00000030      /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI                    0x00000001      /* SDRAM controller is idle  */
+#define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
+#define SDPUA                   0x00000004      /* SDRAM power up active  */
+#define SDRS                    0x00000008      /* SDRAM is in reset state */
+#define SDEASE                0x00000010        /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT                  0x00000020      /* Bus granted */
+
+/*VR_CTL Masks*/
+#define WAKE                    0x100
+#define VLEV_6                  0x60
+#define VLEV_7                  0x70
+#define VLEV_8                  0x80
+#define VLEV_9                  0x90
+#define VLEV_10                 0xA0
+#define VLEV_11                 0xB0
+#define VLEV_12                 0xC0
+#define VLEV_13                 0xD0
+#define VLEV_14                 0xE0
+#define VLEV_15                 0xF0
+#define FREQ_3                  0x03
+
+#endif                          /* _DEF_BF532_H */
diff --git a/include/asm-blackfin/mach-bf533/dma.h b/include/asm-blackfin/mach-bf533/dma.h
new file mode 100644
index 000000000000..bd9d5e94307d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/dma.h
@@ -0,0 +1,54 @@
+/*****************************************************************************
+*
+*        BF-533/2/1 Specific Declarations
+*
+****************************************************************************/
+/*
+ * File:         include/asm-blackfin/mach-bf533/dma.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+
+#define MAX_BLACKFIN_DMA_CHANNEL 12
+
+#define CH_PPI          0
+#define CH_SPORT0_RX    1
+#define CH_SPORT0_TX    2
+#define CH_SPORT1_RX    3
+#define CH_SPORT1_TX    4
+#define CH_SPI          5
+#define CH_UART_RX      6
+#define CH_UART_TX      7
+#define CH_MEM_STREAM0_DEST     8        /* TX */
+#define CH_MEM_STREAM0_SRC      9        /* RX */
+#define CH_MEM_STREAM1_DEST     10       /* TX */
+#define CH_MEM_STREAM1_SRC      11       /* RX */
+
+#endif
diff --git a/include/asm-blackfin/mach-bf533/irq.h b/include/asm-blackfin/mach-bf533/irq.h
new file mode 100644
index 000000000000..9879e68e315c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/irq.h
@@ -0,0 +1,177 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/defBF532.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BF533_IRQ_H_
+#define _BF533_IRQ_H_
+
+/*
+ * Interrupt source definitions
+             Event Source    Core Event Name
+Core        Emulation               **
+ Events         (highest priority)  EMU         0
+            Reset                   RST         1
+            NMI                     NMI         2
+            Exception               EVX         3
+            Reserved                --          4
+            Hardware Error          IVHW        5
+            Core Timer              IVTMR       6 *
+            PLL Wakeup Interrupt    IVG7        7
+            DMA Error (generic)     IVG7        8
+            PPI Error Interrupt     IVG7        9
+            SPORT0 Error Interrupt  IVG7        10
+            SPORT1 Error Interrupt  IVG7        11
+            SPI Error Interrupt     IVG7        12
+            UART Error Interrupt    IVG7        13
+            RTC Interrupt           IVG8        14
+            DMA0 Interrupt (PPI)    IVG8        15
+            DMA1 (SPORT0 RX)        IVG9        16
+            DMA2 (SPORT0 TX)        IVG9        17
+            DMA3 (SPORT1 RX)        IVG9        18
+            DMA4 (SPORT1 TX)        IVG9        19
+            DMA5 (PPI)              IVG10       20
+            DMA6 (UART RX)          IVG10       21
+            DMA7 (UART TX)          IVG10       22
+            Timer0                  IVG11       23
+            Timer1                  IVG11       24
+            Timer2                  IVG11       25
+            PF Interrupt A          IVG12       26
+            PF Interrupt B          IVG12       27
+            DMA8/9 Interrupt        IVG13       28
+            DMA10/11 Interrupt      IVG13       29
+            Watchdog Timer          IVG13       30
+            Software Interrupt 1    IVG14       31
+            Software Interrupt 2    --
+                 (lowest priority)  IVG15       32 *
+ */
+#define SYS_IRQS                32
+#define NR_PERI_INTS    24
+
+/* The ABSTRACT IRQ definitions */
+/** the first seven of the following are fixed, the rest you change if you need to **/
+#define IRQ_EMU                 0       /*Emulation */
+#define IRQ_RST                 1       /*reset */
+#define IRQ_NMI                 2       /*Non Maskable */
+#define IRQ_EVX                 3       /*Exception */
+#define IRQ_UNUSED              4       /*- unused interrupt*/
+#define IRQ_HWERR               5       /*Hardware Error */
+#define IRQ_CORETMR             6       /*Core timer */
+
+#define IRQ_PLL_WAKEUP          7       /*PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR           8       /*DMA Error (general) */
+#define IRQ_PPI_ERROR           9       /*PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR        10      /*SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR        11      /*SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR           12      /*SPI Error Interrupt */
+#define IRQ_UART_ERROR          13      /*UART Error Interrupt */
+#define IRQ_RTC                 14      /*RTC Interrupt */
+#define IRQ_PPI                 15      /*DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX           16      /*DMA1 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX           17      /*DMA2 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX           18      /*DMA3 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX           19      /*DMA4 Interrupt (SPORT1 TX) */
+#define IRQ_SPI                 20      /*DMA5 Interrupt (SPI) */
+#define IRQ_UART_RX             21      /*DMA6 Interrupt (UART RX) */
+#define IRQ_UART_TX             22      /*DMA7 Interrupt (UART TX) */
+#define IRQ_TMR0                23      /*Timer 0 */
+#define IRQ_TMR1                24      /*Timer 1 */
+#define IRQ_TMR2                25      /*Timer 2 */
+#define IRQ_PROG_INTA           26      /*Programmable Flags A (8) */
+#define IRQ_PROG_INTB           27      /*Programmable Flags B (8) */
+#define IRQ_MEM_DMA0            28      /*DMA8/9 Interrupt (Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1            29      /*DMA10/11 Interrupt (Memory DMA Stream 1) */
+#define IRQ_WATCH               30      /*Watch Dog Timer */
+
+#define IRQ_SW_INT1             31      /*Software Int 1 */
+#define IRQ_SW_INT2             32      /*Software Int 2 (reserved for SYSCALL) */
+
+#define IRQ_PF0                 33
+#define IRQ_PF1                 34
+#define IRQ_PF2                 35
+#define IRQ_PF3                 36
+#define IRQ_PF4                 37
+#define IRQ_PF5                 38
+#define IRQ_PF6                 39
+#define IRQ_PF7                 40
+#define IRQ_PF8                 41
+#define IRQ_PF9                 42
+#define IRQ_PF10                43
+#define IRQ_PF11                44
+#define IRQ_PF12                45
+#define IRQ_PF13                46
+#define IRQ_PF14                47
+#define IRQ_PF15                48
+
+#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+#define NR_IRQS         (IRQ_PF15+1)
+#else
+#define NR_IRQS         SYS_IRQS
+#endif
+
+#define IVG7                    7
+#define IVG8                    8
+#define IVG9                    9
+#define IVG10                   10
+#define IVG11                   11
+#define IVG12                   12
+#define IVG13                   13
+#define IVG14                   14
+#define IVG15                   15
+
+/* IAR0 BIT FIELDS*/
+#define RTC_ERROR_POS                   28
+#define UART_ERROR_POS                  24
+#define SPORT1_ERROR_POS                20
+#define SPI_ERROR_POS                   16
+#define SPORT0_ERROR_POS                12
+#define PPI_ERROR_POS                   8
+#define DMA_ERROR_POS                   4
+#define PLLWAKE_ERROR_POS               0
+
+/* IAR1 BIT FIELDS*/
+#define DMA7_UARTTX_POS                 28
+#define DMA6_UARTRX_POS                 24
+#define DMA5_SPI_POS                    20
+#define DMA4_SPORT1TX_POS               16
+#define DMA3_SPORT1RX_POS               12
+#define DMA2_SPORT0TX_POS               8
+#define DMA1_SPORT0RX_POS               4
+#define DMA0_PPI_POS                    0
+
+/* IAR2 BIT FIELDS*/
+#define WDTIMER_POS                     28
+#define MEMDMA1_POS                     24
+#define MEMDMA0_POS                     20
+#define PFB_POS                         16
+#define PFA_POS                         12
+#define TIMER2_POS                      8
+#define TIMER1_POS                      4
+#define TIMER0_POS                      0
+
+#endif                          /* _BF533_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf533/mem_init.h b/include/asm-blackfin/mach-bf533/mem_init.h
new file mode 100644
index 000000000000..1620dae5254d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_init.h
@@ -0,0 +1,316 @@
+/*
+ * File:         include/asm-blackfin/mach-bf533/mem_init.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD)
+#if (CONFIG_SCLK_HZ > 119402985)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_7
+#define SDRAM_tRAS_num  7
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_6
+#define SDRAM_tRAS_num  6
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 8955223) && (CONFIG_SCLK_HZ <= 104477612)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_5
+#define SDRAM_tRAS_num  5
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_4
+#define SDRAM_tRAS_num  4
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_3
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_4
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_3
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_2
+#define SDRAM_tRAS_num  2
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ <= 29850746)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_1
+#define SDRAM_tRAS_num  1
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#endif
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_GENERIC_BOARD)
+  /*SDRAM INFORMATION: Modify this for your board */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_SIZE == 128)
+#define SDRAM_SIZE      EBSZ_128
+#endif
+#if (CONFIG_MEM_SIZE == 64)
+#define SDRAM_SIZE      EBSZ_64
+#endif
+#if (CONFIG_MEM_SIZE == 32)
+#define SDRAM_SIZE      EBSZ_32
+#endif
+#if (CONFIG_MEM_SIZE == 16)
+#define SDRAM_SIZE      EBSZ_16
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 11)
+#define SDRAM_WIDTH     EBCAW_11
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 10)
+#define SDRAM_WIDTH     EBCAW_10
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 9)
+#define SDRAM_WIDTH     EBCAW_9
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 8)
+#define SDRAM_WIDTH     EBCAW_8
+#endif
+
+#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EBE)
+
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref)  / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
+
+#if defined CONFIG_CLKIN_HALF
+#define CLKIN_HALF       1
+#else
+#define CLKIN_HALF       0
+#endif
+
+#if defined CONFIG_PLL_BYPASS
+#define PLL_BYPASS      1
+#else
+#define PLL_BYPASS       0
+#endif
+
+/***************************************Currently Not Being Used *********************************/
+#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
+#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0  \
+        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
+         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf533/mem_map.h b/include/asm-blackfin/mach-bf533/mem_map.h
new file mode 100644
index 000000000000..e84baa3e939d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf533/mem_map.h
@@ -0,0 +1,168 @@
+
+/*
+ * File:         include/asm-blackfin/mach-bf533/mem_map.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MEM_MAP_533_H_
+#define _MEM_MAP_533_H_
+
+#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
+#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
+
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+
+/* Level 1 Memory */
+
+#ifdef CONFIG_BLKFIN_CACHE
+#define BLKFIN_ICACHESIZE       (16*1024)
+#else
+#define BLKFIN_ICACHESIZE       (0*1024)
+#endif
+
+/* Memory Map for ADSP-BF533 processors */
+
+#ifdef CONFIG_BF533
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+
+#ifdef CONFIG_BLKFIN_CACHE
+#define L1_CODE_LENGTH      (0x14000 - 0x4000)
+#else
+#define L1_CODE_LENGTH      0x14000
+#endif
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif
+
+/* Memory Map for ADSP-BF532 processors */
+
+#ifdef CONFIG_BF532
+#define L1_CODE_START       0xFFA08000
+#define L1_DATA_A_START     0xFF804000
+#define L1_DATA_B_START     0xFF904000
+
+#ifdef CONFIG_BLKFIN_CACHE
+#define L1_CODE_LENGTH      (0xC000 - 0x4000)
+#else
+#define L1_CODE_LENGTH      0xC000
+#endif
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x4000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x4000
+#define L1_DATA_B_LENGTH      0x4000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif
+
+/* Memory Map for ADSP-BF531 processors */
+
+#ifdef CONFIG_BF531
+#define L1_CODE_START       0xFFA08000
+#define L1_DATA_A_START     0xFF804000
+#define L1_DATA_B_START     0xFF904000
+#define L1_CODE_LENGTH      0x4000
+#define L1_DATA_B_LENGTH      0x0000
+
+
+#ifdef CONFIG_BLKFIN_DCACHE
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB  | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB  | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x4000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif
+
+#endif
+
+/* Scratch Pad Memory */
+
+#if defined(CONFIG_BF533) || defined(CONFIG_BF532) || defined(CONFIG_BF531)
+#define L1_SCRATCH_START        0xFFB00000
+#define L1_SCRATCH_LENGTH       0x1000
+#endif
+
+#endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h
new file mode 100644
index 000000000000..7f040f5ba018
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/anomaly.h
@@ -0,0 +1,120 @@
+
+/*
+ * File:         include/asm-blackfin/mach-bf537/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision J, June 1, 2006; ADSP-BF537 Blackfin Processor Anomaly List
+ *  - Revision I, June 1, 2006; ADSP-BF536 Blackfin Processor Anomaly List
+ *  - Revision J, June 1, 2006; ADSP-BF534 Blackfin Processor Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1))
+#error Kernel will not work on BF537/6/4 Version 0.1
+#endif
+
+#if (defined(CONFIG_BF_REV_0_3) || defined(CONFIG_BF_REV_0_2))
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+                            slot1 and store of a P register in slot 2 is not
+                            supported */
+#define ANOMALY_05000119 /* DMA_RUN bit is not valid after a Peripheral Receive
+                            Channel DMA stops */
+#define ANOMALY_05000122 /* Rx.H can not be used to access 16-bit System MMR
+                            registers. */
+#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+                            upper bits*/
+#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+                            syncs */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000247 /* CLKIN Buffer Output Enable Reset Behavior Is
+                            Changed */
+#endif
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+                            SPORT external receive and transmit clocks. */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+                            VDDint <=0.9V */
+#define ANOMALY_05000273 /* Writes to Synchronous SDRAM memory may be lost */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+                            an edge is detected may clear interrupt */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+                            not restored */
+#define ANOMALY_05000282 /* Memory DMA corruption with 32-bit data and traffic
+                            control */
+#define ANOMALY_05000283 /* A system MMR write is stalled indefinitely when
+                            killed in a particular stage*/
+#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
+                            registers are interrupted */
+#endif
+
+#if defined(CONFIG_BF_REV_0_2)
+#define ANOMALY_05000244 /* With instruction cache enabled, a CSYNC or SSYNC or
+                            IDLE around a Change of Control causes
+                            unpredictable results */
+#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
+                            (TDM) */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000252 /* EMAC Tx DMA error after an early frame abort */
+#endif
+#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000255 /* Entering Hibernate Mode with RTC Seconds event
+                            interrupt not functional */
+#if (defined(CONFIG_BF537) || defined(CONFIG_BF536))
+#define ANOMALY_05000256 /* EMAC MDIO input latched on wrong MDC edge */
+#endif
+#define ANOMALY_05000257 /* An interrupt or exception during short Hardware
+                            loops may cause the instruction fetch unit to
+                            malfunction */
+#define ANOMALY_05000258 /* Instruction Cache is corrupted when bit 9 and 12 of
+                            the ICPLB Data registers differ */
+#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB exception */
+#define ANOMALY_05000264 /* A Sync instruction (CSYNC, SSYNC) or an IDLE
+                            instruction will cause an infinite stall in the
+                            second to last instruction in a hardware loop */
+#define ANOMALY_05000268 /* Memory DMA error when peripheral DMA is running
+                            and non-zero DEB_TRAFFIC_PERIOD value */
+#define ANOMALY_05000270 /* High I/O activity causes the output voltage of the
+                            internal voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000277 /* Writes to a flag data register one SCLK cycle after
+                            an edge is detected may clear interrupt */
+#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
+                            DMA system instability */
+#define ANOMALY_05000280 /* SPI Master boot mode does not work well with
+                            Atmel Dataflash devices */
+
+#endif  /* CONFIG_BF_REV_0_2 */
+
+#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf537/bf537.h b/include/asm-blackfin/mach-bf537/bf537.h
new file mode 100644
index 000000000000..b8924cd7730c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bf537.h
@@ -0,0 +1,287 @@
+/*
+ * File:         include/asm-blackfin/mach-bf537/bf537.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF537
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __MACH_BF537_H__
+#define __MACH_BF537_H__
+
+#define SUPPORTED_REVID 2
+
+/* Masks for generic ERROR IRQ demultiplexing used in int-priority-sc.c */
+
+#define SPI_ERR_MASK (TXCOL | RBSY | MODF | TXE)        /* SPI_STAT */
+#define SPORT_ERR_MASK (ROVF | RUVF | TOVF | TUVF)      /* SPORTx_STAT */
+#define PPI_ERR_MASK (0xFFFF & ~FLD)    /* PPI_STATUS */
+#define EMAC_ERR_MASK (PHYINT | MMCINT | RXFSINT | TXFSINT | WAKEDET | RXDMAERR | TXDMAERR | STMDONE)   /* EMAC_SYSTAT */
+#define UART_ERR_MASK_STAT1 (0x4)       /* UARTx_IIR */
+#define UART_ERR_MASK_STAT0 (0x2)       /* UARTx_IIR */
+#define CAN_ERR_MASK  (EWTIF | EWRIF | EPIF | BOIF | WUIF | UIAIF | AAIF | RMLIF | UCEIF | EXTIF | ADIF)        /* CAN_GIF */
+
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR    0x0040
+#define IMASK_IVGHW             0x0020
+
+/***************************/
+
+
+#define BLKFIN_DSUBBANKS        4
+#define BLKFIN_DWAYS            2
+#define BLKFIN_DLINES           64
+#define BLKFIN_ISUBBANKS        4
+#define BLKFIN_IWAYS            4
+#define BLKFIN_ILINES           32
+
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+
+/********************************* EBIU Settings ************************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+
+#ifdef CONFIG_C_AMBEN_ALL
+#define V_AMBEN AMBEN_ALL
+#endif
+#ifdef CONFIG_C_AMBEN
+#define V_AMBEN 0x0
+#endif
+#ifdef CONFIG_C_AMBEN_B0
+#define V_AMBEN AMBEN_B0
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1
+#define V_AMBEN AMBEN_B0_B1
+#endif
+#ifdef CONFIG_C_AMBEN_B0_B1_B2
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+#ifdef CONFIG_C_CDPRIO
+#define V_CDPRIO 0x100
+#else
+#define V_CDPRIO 0x0
+#endif
+
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO)
+
+#define MAX_VC  650000000
+#define MIN_VC  50000000
+
+/********************************PLL Settings **************************************/
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
+#if (CONFIG_VCO_MULT < 0)
+#error "VCO Multiplier is less than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT == 0)
+#error "VCO Multiplier should be greater than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT > 64)
+#error "VCO Multiplier is more than 64. Please select a different value"
+#endif
+
+#ifndef CONFIG_CLKIN_HALF
+#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+#else
+#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
+#endif
+
+#ifndef CONFIG_PLL_BYPASS
+#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
+#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
+#else
+#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
+#endif
+
+#if (CONFIG_SCLK_DIV < 1)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_SCLK_DIV > 15)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_CCLK_DIV != 1)
+#if (CONFIG_CCLK_DIV != 2)
+#if (CONFIG_CCLK_DIV != 4)
+#if (CONFIG_CCLK_DIV != 8)
+#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
+#endif
+#endif
+#endif
+#endif
+
+#if (CONFIG_VCO_HZ > MAX_VC)
+#error "VCO selected is more than maximum value. Please change the VCO multipler"
+#endif
+
+#if (CONFIG_SCLK_HZ > 133000000)
+#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ < 27000000)
+#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
+#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
+#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
+#error "Please select sclk less than cclk"
+#endif
+#endif
+#endif
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
+#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
+#endif
+
+#endif                          /* CONFIG_BFIN_KERNEL_CLOCK */
+
+#ifdef CONFIG_BF537
+#define CPU "BF537"
+#define CPUID 0x027c8000
+#endif
+#ifdef CONFIG_BF536
+#define CPU "BF536"
+#define CPUID 0x027c8000
+#endif
+#ifdef CONFIG_BF534
+#define CPU "BF534"
+#define CPUID 0x027c6000
+#endif
+#ifndef CPU
+#define CPU "UNKNOWN"
+#define CPUID 0x0
+#endif
+
+#if (CONFIG_MEM_SIZE % 4)
+#error "SDRAM mem size must be multible of 4MB"
+#endif
+
+#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
+#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
+#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158_WORKAROUND             0x200
+#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else                           /*Write Through */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
+#endif
+
+
+#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
+#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
+#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY )
+#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY )
+
+#define SIZE_1K 0x00000400      /* 1K */
+#define SIZE_4K 0x00001000      /* 4K */
+#define SIZE_1M 0x00100000      /* 1M */
+#define SIZE_4M 0x00400000      /* 4M */
+
+#define MAX_CPLBS (16 * 2)
+
+/*
+* Number of required data CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 16 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Data Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+* 1 for ASYNC Memory
+*/
+
+
+#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1) * 2)
+
+/*
+* Number of required instruction CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 12 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Instruction Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+*/
+
+#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1) * 2)
+
+#endif                          /* __MACH_BF537_H__  */
diff --git a/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
new file mode 100644
index 000000000000..8f5d9c4d8d5b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/bfin_serial_5xx.h
@@ -0,0 +1,147 @@
+#include <linux/serial.h>
+#include <asm/dma.h>
+
+#define NR_PORTS                2
+
+#define OFFSET_THR              0x00    /* Transmit Holding register            */
+#define OFFSET_RBR              0x00    /* Receive Buffer register              */
+#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
+#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
+#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
+#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
+#define OFFSET_LCR              0x0C    /* Line Control Register                */
+#define OFFSET_MCR              0x10    /* Modem Control Register               */
+#define OFFSET_LSR              0x14    /* Line Status Register                 */
+#define OFFSET_MSR              0x18    /* Modem Status Register                */
+#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
+#define OFFSET_GCTL             0x24    /* Global Control Register              */
+
+#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
+#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
+#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
+#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
+#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
+#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
+#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
+#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+
+#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
+#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
+#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
+#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
+#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+
+#if defined(CONFIG_BFIN_UART0_CTSRTS) || defined(CONFIG_BFIN_UART1_CTSRTS)
+# define CONFIG_SERIAL_BFIN_CTSRTS
+
+# ifndef CONFIG_UART0_CTS_PIN
+#  define CONFIG_UART0_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART0_RTS_PIN
+#  define CONFIG_UART0_RTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_CTS_PIN
+#  define CONFIG_UART1_CTS_PIN -1
+# endif
+
+# ifndef CONFIG_UART1_RTS_PIN
+#  define CONFIG_UART1_RTS_PIN -1
+# endif
+#endif
+/*
+ * The pin configuration is different from schematic
+ */
+struct bfin_serial_port {
+        struct uart_port        port;
+        unsigned int            old_status;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int                     tx_done;
+        int                     tx_count;
+        struct circ_buf         rx_dma_buf;
+        struct timer_list       rx_dma_timer;
+        int                     rx_dma_nrows;
+        unsigned int            tx_dma_channel;
+        unsigned int            rx_dma_channel;
+        struct work_struct      tx_dma_workqueue;
+#else
+        struct work_struct      cts_workqueue;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int             cts_pin;
+        int             rts_pin;
+#endif
+};
+
+struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_res {
+        unsigned long   uart_base_addr;
+        int             uart_irq;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        unsigned int    uart_tx_dma_channel;
+        unsigned int    uart_rx_dma_channel;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int     uart_cts_pin;
+        int     uart_rts_pin;
+#endif
+};
+
+struct bfin_serial_res bfin_serial_resource[] = {
+#ifdef CONFIG_SERIAL_BFIN_UART0
+        {
+        0xFFC00400,
+        IRQ_UART0_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART0_TX,
+        CH_UART0_RX,
+#endif
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        CONFIG_UART0_CTS_PIN,
+        CONFIG_UART0_RTS_PIN,
+#endif
+        },
+#endif
+#ifdef CONFIG_SERIAL_BFIN_UART1
+        {
+        0xFFC02000,
+        IRQ_UART1_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART1_TX,
+        CH_UART1_RX,
+#endif
+#ifdef CONFIG_BFIN_UART1_CTSRTS
+        CONFIG_UART1_CTS_PIN,
+        CONFIG_UART1_RTS_PIN,
+#endif
+        },
+#endif
+};
+
+int nr_ports = ARRAY_SIZE(bfin_serial_resource);
+
+static void bfin_serial_hw_init(struct bfin_serial_port *uart)
+{
+        unsigned short val;
+        val = bfin_read16(BFIN_PORT_MUX);
+        val &= ~(PFDE | PFTE);
+        bfin_write16(BFIN_PORT_MUX, val);
+
+        val = bfin_read16(PORTF_FER);
+        val |= 0xF;
+        bfin_write16(PORTF_FER, val);
+
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        if (uart->cts_pin >= 0) {
+                gpio_request(uart->cts_pin, NULL);
+                gpio_direction_input(uart->cts_pin);
+        }
+
+        if (uart->rts_pin >= 0) {
+                gpio_request(uart->rts_pin, NULL);
+                gpio_direction_output(uart->rts_pin);
+        }
+#endif
+}
diff --git a/include/asm-blackfin/mach-bf537/blackfin.h b/include/asm-blackfin/mach-bf537/blackfin.h
new file mode 100644
index 000000000000..bbd97051ec9c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/blackfin.h
@@ -0,0 +1,430 @@
+/*
+ * File:         include/asm-blackfin/mach-bf537/blackfin.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+
+#define BF537_FAMILY
+
+#include "bf537.h"
+#include "mem_map.h"
+#include "defBF534.h"
+#include "anomaly.h"
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+#include "defBF537.h"
+#endif
+
+#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#include "cdefBF534.h"
+
+/* UART 0*/
+#define bfin_read_UART_THR() bfin_read_UART0_THR()
+#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
+#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
+#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
+#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
+#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
+#define bfin_read_UART_IER() bfin_read_UART0_IER()
+#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
+#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
+#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
+#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
+#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
+#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
+#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
+#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
+#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
+#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
+#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
+#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
+#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
+#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
+#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536)
+#include "cdefBF537.h"
+#endif
+#endif
+
+/* MAP used DEFINES from BF533 to BF537 - so we don't need to change them in the driver, kernel, etc. */
+
+/* UART_IIR Register */
+#define STATUS(x)       ((x << 1) & 0x06)
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+
+/* UART 0*/
+
+/* DMA Channnel */
+#define bfin_read_CH_UART_RX() bfin_read_CH_UART0_RX()
+#define bfin_write_CH_UART_RX(val) bfin_write_CH_UART0_RX(val)
+#define CH_UART_RX CH_UART0_RX
+#define bfin_read_CH_UART_TX() bfin_read_CH_UART0_TX()
+#define bfin_write_CH_UART_TX(val) bfin_write_CH_UART0_TX(val)
+#define CH_UART_TX CH_UART0_TX
+
+/* System Interrupt Controller */
+#define bfin_read_IRQ_UART_RX() bfin_read_IRQ_UART0_RX()
+#define bfin_write_IRQ_UART_RX(val) bfin_write_IRQ_UART0_RX(val)
+#define IRQ_UART_RX IRQ_UART0_RX
+#define bfin_read_IRQ_UART_TX() bfin_read_IRQ_UART0_TX()
+#define bfin_write_IRQ_UART_TX(val) bfin_write_IRQ_UART0_TX(val)
+#define IRQ_UART_TX IRQ_UART0_TX
+#define bfin_read_IRQ_UART_ERROR() bfin_read_IRQ_UART0_ERROR()
+#define bfin_write_IRQ_UART_ERROR(val) bfin_write_IRQ_UART0_ERROR(val)
+#define IRQ_UART_ERROR IRQ_UART0_ERROR
+
+/* MMR Registers*/
+#define bfin_read_UART_THR() bfin_read_UART0_THR()
+#define bfin_write_UART_THR(val) bfin_write_UART0_THR(val)
+#define UART_THR UART0_THR
+#define bfin_read_UART_RBR() bfin_read_UART0_RBR()
+#define bfin_write_UART_RBR(val) bfin_write_UART0_RBR(val)
+#define UART_RBR UART0_RBR
+#define bfin_read_UART_DLL() bfin_read_UART0_DLL()
+#define bfin_write_UART_DLL(val) bfin_write_UART0_DLL(val)
+#define UART_DLL UART0_DLL
+#define bfin_read_UART_IER() bfin_read_UART0_IER()
+#define bfin_write_UART_IER(val) bfin_write_UART0_IER(val)
+#define UART_IER UART0_IER
+#define bfin_read_UART_DLH() bfin_read_UART0_DLH()
+#define bfin_write_UART_DLH(val) bfin_write_UART0_DLH(val)
+#define UART_DLH UART0_DLH
+#define bfin_read_UART_IIR() bfin_read_UART0_IIR()
+#define bfin_write_UART_IIR(val) bfin_write_UART0_IIR(val)
+#define UART_IIR UART0_IIR
+#define bfin_read_UART_LCR() bfin_read_UART0_LCR()
+#define bfin_write_UART_LCR(val) bfin_write_UART0_LCR(val)
+#define UART_LCR UART0_LCR
+#define bfin_read_UART_MCR() bfin_read_UART0_MCR()
+#define bfin_write_UART_MCR(val) bfin_write_UART0_MCR(val)
+#define UART_MCR UART0_MCR
+#define bfin_read_UART_LSR() bfin_read_UART0_LSR()
+#define bfin_write_UART_LSR(val) bfin_write_UART0_LSR(val)
+#define UART_LSR UART0_LSR
+#define bfin_read_UART_SCR() bfin_read_UART0_SCR()
+#define bfin_write_UART_SCR(val) bfin_write_UART0_SCR(val)
+#define UART_SCR  UART0_SCR
+#define bfin_read_UART_GCTL() bfin_read_UART0_GCTL()
+#define bfin_write_UART_GCTL(val) bfin_write_UART0_GCTL(val)
+#define UART_GCTL UART0_GCTL
+
+/* DPMC*/
+#define bfin_read_STOPCK_OFF() bfin_read_STOPCK()
+#define bfin_write_STOPCK_OFF(val) bfin_write_STOPCK(val)
+#define STOPCK_OFF STOPCK
+
+/* FIO USE PORT F*/
+#ifdef CONFIG_BF537_PORT_F
+#define bfin_read_PORT_FER() bfin_read_PORTF_FER()
+#define bfin_write_PORT_FER(val) bfin_write_PORTF_FER(val)
+#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
+#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
+#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
+#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
+#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
+#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
+#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
+#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
+#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
+#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
+#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
+#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
+#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
+#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
+#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
+#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
+#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
+#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
+#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
+#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
+#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
+#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
+#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
+#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
+#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
+#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
+#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
+#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
+#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
+#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
+#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
+
+#define bfin_read_FIO_FLAG_D() bfin_read_PORTFIO()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTFIO(val)
+#define FIO_FLAG_D              PORTFIO
+#define bfin_read_FIO_FLAG_C() bfin_read_PORTFIO_CLEAR()
+#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTFIO_CLEAR(val)
+#define FIO_FLAG_C              PORTFIO_CLEAR
+#define bfin_read_FIO_FLAG_S() bfin_read_PORTFIO_SET()
+#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTFIO_SET(val)
+#define FIO_FLAG_S              PORTFIO_SET
+#define bfin_read_FIO_FLAG_T() bfin_read_PORTFIO_TOGGLE()
+#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTFIO_TOGGLE(val)
+#define FIO_FLAG_T              PORTFIO_TOGGLE
+#define bfin_read_FIO_MASKA_D() bfin_read_PORTFIO_MASKA()
+#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTFIO_MASKA(val)
+#define FIO_MASKA_D         PORTFIO_MASKA
+#define bfin_read_FIO_MASKA_C() bfin_read_PORTFIO_MASKA_CLEAR()
+#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTFIO_MASKA_CLEAR(val)
+#define FIO_MASKA_C     PORTFIO_MASKA_CLEAR
+#define bfin_read_FIO_MASKA_S() bfin_read_PORTFIO_MASKA_SET()
+#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTFIO_MASKA_SET(val)
+#define FIO_MASKA_S     PORTFIO_MASKA_SET
+#define bfin_read_FIO_MASKA_T() bfin_read_PORTFIO_MASKA_TOGGLE()
+#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTFIO_MASKA_TOGGLE(val)
+#define FIO_MASKA_T     PORTFIO_MASKA_TOGGLE
+#define bfin_read_FIO_MASKB_D() bfin_read_PORTFIO_MASKB()
+#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTFIO_MASKB(val)
+#define FIO_MASKB_D     PORTFIO_MASKB
+#define bfin_read_FIO_MASKB_C() bfin_read_PORTFIO_MASKB_CLEAR()
+#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTFIO_MASKB_CLEAR(val)
+#define FIO_MASKB_C     PORTFIO_MASKB_CLEAR
+#define bfin_read_FIO_MASKB_S() bfin_read_PORTFIO_MASKB_SET()
+#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTFIO_MASKB_SET(val)
+#define FIO_MASKB_S     PORTFIO_MASKB_SET
+#define bfin_read_FIO_MASKB_T() bfin_read_PORTFIO_MASKB_TOGGLE()
+#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTFIO_MASKB_TOGGLE(val)
+#define FIO_MASKB_T     PORTFIO_MASKB_TOGGLE
+#define bfin_read_FIO_DIR() bfin_read_PORTFIO_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_PORTFIO_DIR(val)
+#define FIO_DIR             PORTFIO_DIR
+#define bfin_read_FIO_POLAR() bfin_read_PORTFIO_POLAR()
+#define bfin_write_FIO_POLAR(val) bfin_write_PORTFIO_POLAR(val)
+#define FIO_POLAR               PORTFIO_POLAR
+#define bfin_read_FIO_EDGE() bfin_read_PORTFIO_EDGE()
+#define bfin_write_FIO_EDGE(val) bfin_write_PORTFIO_EDGE(val)
+#define FIO_EDGE                PORTFIO_EDGE
+#define bfin_read_FIO_BOTH() bfin_read_PORTFIO_BOTH()
+#define bfin_write_FIO_BOTH(val) bfin_write_PORTFIO_BOTH(val)
+#define FIO_BOTH                PORTFIO_BOTH
+#define bfin_read_FIO_INEN() bfin_read_PORTFIO_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_PORTFIO_INEN(val)
+#define FIO_INEN                PORTFIO_INEN
+#endif
+
+/* FIO USE PORT G*/
+#ifdef CONFIG_BF537_PORT_G
+#define bfin_read_PORT_FER() bfin_read_PORTG_FER()
+#define bfin_write_PORT_FER(val) bfin_write_PORTG_FER(val)
+#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
+#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
+#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
+#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
+#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
+#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
+#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
+#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
+#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
+#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
+#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
+#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
+#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
+#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
+#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
+#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
+#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
+#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
+#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
+#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
+#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
+#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
+#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
+#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
+#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
+#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
+#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
+#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
+#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
+#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
+#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
+
+#define bfin_read_FIO_FLAG_D() bfin_read_PORTGIO()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTGIO(val)
+#define FIO_FLAG_D              PORTGIO
+#define bfin_read_FIO_FLAG_C() bfin_read_PORTGIO_CLEAR()
+#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTGIO_CLEAR(val)
+#define FIO_FLAG_C              PORTGIO_CLEAR
+#define bfin_read_FIO_FLAG_S() bfin_read_PORTGIO_SET()
+#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTGIO_SET(val)
+#define FIO_FLAG_S              PORTGIO_SET
+#define bfin_read_FIO_FLAG_T() bfin_read_PORTGIO_TOGGLE()
+#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTGIO_TOGGLE(val)
+#define FIO_FLAG_T              PORTGIO_TOGGLE
+#define bfin_read_FIO_MASKA_D() bfin_read_PORTGIO_MASKA()
+#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTGIO_MASKA(val)
+#define FIO_MASKA_D         PORTGIO_MASKA
+#define bfin_read_FIO_MASKA_C() bfin_read_PORTGIO_MASKA_CLEAR()
+#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTGIO_MASKA_CLEAR(val)
+#define FIO_MASKA_C         PORTGIO_MASKA_CLEAR
+#define bfin_read_FIO_MASKA_S() bfin_read_PORTGIO_MASKA_SET()
+#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTGIO_MASKA_SET(val)
+#define FIO_MASKA_S         PORTGIO_MASKA_SET
+#define bfin_read_FIO_MASKA_T() bfin_read_PORTGIO_MASKA_TOGGLE()
+#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTGIO_MASKA_TOGGLE(val)
+#define FIO_MASKA_T         PORTGIO_MASKA_TOGGLE
+#define bfin_read_FIO_MASKB_D() bfin_read_PORTGIO_MASKB()
+#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTGIO_MASKB(val)
+#define FIO_MASKB_D         PORTGIO_MASKB
+#define bfin_read_FIO_MASKB_C() bfin_read_PORTGIO_MASKB_CLEAR()
+#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTGIO_MASKB_CLEAR(val)
+#define FIO_MASKB_C         PORTGIO_MASKB_CLEAR
+#define bfin_read_FIO_MASKB_S() bfin_read_PORTGIO_MASKB_SET()
+#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTGIO_MASKB_SET(val)
+#define FIO_MASKB_S         PORTGIO_MASKB_SET
+#define bfin_read_FIO_MASKB_T() bfin_read_PORTGIO_MASKB_TOGGLE()
+#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTGIO_MASKB_TOGGLE(val)
+#define FIO_MASKB_T         PORTGIO_MASKB_TOGGLE
+#define bfin_read_FIO_DIR() bfin_read_PORTGIO_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_PORTGIO_DIR(val)
+#define FIO_DIR             PORTGIO_DIR
+#define bfin_read_FIO_POLAR() bfin_read_PORTGIO_POLAR()
+#define bfin_write_FIO_POLAR(val) bfin_write_PORTGIO_POLAR(val)
+#define FIO_POLAR               PORTGIO_POLAR
+#define bfin_read_FIO_EDGE() bfin_read_PORTGIO_EDGE()
+#define bfin_write_FIO_EDGE(val) bfin_write_PORTGIO_EDGE(val)
+#define FIO_EDGE                PORTGIO_EDGE
+#define bfin_read_FIO_BOTH() bfin_read_PORTGIO_BOTH()
+#define bfin_write_FIO_BOTH(val) bfin_write_PORTGIO_BOTH(val)
+#define FIO_BOTH                PORTGIO_BOTH
+#define bfin_read_FIO_INEN() bfin_read_PORTGIO_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_PORTGIO_INEN(val)
+#define FIO_INEN                PORTGIO_INEN
+
+#endif
+
+/* FIO USE PORT H*/
+#ifdef CONFIG_BF537_PORT_H
+#define bfin_read_PORT_FER() bfin_read_PORTH_FER()
+#define bfin_write_PORT_FER(val) bfin_write_PORTH_FER(val)
+#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
+#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
+#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
+#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
+#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
+#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
+#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
+#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
+#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
+#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
+#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
+#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
+#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
+#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
+#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
+#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
+#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
+#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
+#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
+#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
+#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
+#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
+#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
+#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
+#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
+#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
+#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
+#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
+#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
+#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
+#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
+
+#define bfin_read_FIO_FLAG_D() bfin_read_PORTHIO()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_PORTHIO(val)
+#define FIO_FLAG_D              PORTHIO
+#define bfin_read_FIO_FLAG_C() bfin_read_PORTHIO_CLEAR()
+#define bfin_write_FIO_FLAG_C(val) bfin_write_PORTHIO_CLEAR(val)
+#define FIO_FLAG_C              PORTHIO_CLEAR
+#define bfin_read_FIO_FLAG_S() bfin_read_PORTHIO_SET()
+#define bfin_write_FIO_FLAG_S(val) bfin_write_PORTHIO_SET(val)
+#define FIO_FLAG_S              PORTHIO_SET
+#define bfin_read_FIO_FLAG_T() bfin_read_PORTHIO_TOGGLE()
+#define bfin_write_FIO_FLAG_T(val) bfin_write_PORTHIO_TOGGLE(val)
+#define FIO_FLAG_T              PORTHIO_TOGGLE
+#define bfin_read_FIO_MASKA_D() bfin_read_PORTHIO_MASKA()
+#define bfin_write_FIO_MASKA_D(val) bfin_write_PORTHIO_MASKA(val)
+#define FIO_MASKA_D         PORTHIO_MASKA
+#define bfin_read_FIO_MASKA_C() bfin_read_PORTHIO_MASKA_CLEAR()
+#define bfin_write_FIO_MASKA_C(val) bfin_write_PORTHIO_MASKA_CLEAR(val)
+#define FIO_MASKA_C         PORTHIO_MASKA_CLEAR
+#define bfin_read_FIO_MASKA_S() bfin_read_PORTHIO_MASKA_SET()
+#define bfin_write_FIO_MASKA_S(val) bfin_write_PORTHIO_MASKA_SET(val)
+#define FIO_MASKA_S         PORTHIO_MASKA_SET
+#define bfin_read_FIO_MASKA_T() bfin_read_PORTHIO_MASKA_TOGGLE()
+#define bfin_write_FIO_MASKA_T(val) bfin_write_PORTHIO_MASKA_TOGGLE(val)
+#define FIO_MASKA_T         PORTHIO_MASKA_TOGGLE
+#define bfin_read_FIO_MASKB_D() bfin_read_PORTHIO_MASKB()
+#define bfin_write_FIO_MASKB_D(val) bfin_write_PORTHIO_MASKB(val)
+#define FIO_MASKB_D         PORTHIO_MASKB
+#define bfin_read_FIO_MASKB_C() bfin_read_PORTHIO_MASKB_CLEAR()
+#define bfin_write_FIO_MASKB_C(val) bfin_write_PORTHIO_MASKB_CLEAR(val)
+#define FIO_MASKB_C         PORTHIO_MASKB_CLEAR
+#define bfin_read_FIO_MASKB_S() bfin_read_PORTHIO_MASKB_SET()
+#define bfin_write_FIO_MASKB_S(val) bfin_write_PORTHIO_MASKB_SET(val)
+#define FIO_MASKB_S         PORTHIO_MASKB_SET
+#define bfin_read_FIO_MASKB_T() bfin_read_PORTHIO_MASKB_TOGGLE()
+#define bfin_write_FIO_MASKB_T(val) bfin_write_PORTHIO_MASKB_TOGGLE(val)
+#define FIO_MASKB_T         PORTHIO_MASKB_TOGGLE
+#define bfin_read_FIO_DIR() bfin_read_PORTHIO_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_PORTHIO_DIR(val)
+#define FIO_DIR             PORTHIO_DIR
+#define bfin_read_FIO_POLAR() bfin_read_PORTHIO_POLAR()
+#define bfin_write_FIO_POLAR(val) bfin_write_PORTHIO_POLAR(val)
+#define FIO_POLAR               PORTHIO_POLAR
+#define bfin_read_FIO_EDGE() bfin_read_PORTHIO_EDGE()
+#define bfin_write_FIO_EDGE(val) bfin_write_PORTHIO_EDGE(val)
+#define FIO_EDGE                PORTHIO_EDGE
+#define bfin_read_FIO_BOTH() bfin_read_PORTHIO_BOTH()
+#define bfin_write_FIO_BOTH(val) bfin_write_PORTHIO_BOTH(val)
+#define FIO_BOTH                PORTHIO_BOTH
+#define bfin_read_FIO_INEN() bfin_read_PORTHIO_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_PORTHIO_INEN(val)
+#define FIO_INEN                PORTHIO_INEN
+
+#endif
+
+/* PLL_DIV Masks                                                                                                        */
+#define CCLK_DIV1 CSEL_DIV1     /*          CCLK = VCO / 1                                  */
+#define CCLK_DIV2 CSEL_DIV2     /*          CCLK = VCO / 2                                  */
+#define CCLK_DIV4 CSEL_DIV4     /*          CCLK = VCO / 4                                  */
+#define CCLK_DIV8 CSEL_DIV8     /*          CCLK = VCO / 8                                  */
+
+#endif
diff --git a/include/asm-blackfin/mach-bf537/cdefBF534.h b/include/asm-blackfin/mach-bf537/cdefBF534.h
new file mode 100644
index 000000000000..7b658c175f85
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/cdefBF534.h
@@ -0,0 +1,1823 @@
+/*
+ * File:         include/asm-blackfin/mach-bf537/cdefbf534.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  system mmr register map
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF534_H
+#define _CDEF_BF534_H
+
+/* Include all Core registers and bit definitions                                                                       */
+#include "defBF534.h"
+
+/* Include core specific register pointer definitions                                                           */
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+#include <asm/system.h>
+
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)              bfin_write16(PLL_CTL,val)
+#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
+#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SIC_IWR);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SIC_IWR, IWR_ENABLE(0));
+        local_irq_save(flags);
+        asm("IDLE;");
+        local_irq_restore(flags);
+        bfin_write32(SIC_IWR, iwr);
+}
+#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
+#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
+#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define bfin_read_SWRST()                    bfin_read16(SWRST)
+#define bfin_write_SWRST(val)                bfin_write16(SWRST,val)
+#define bfin_read_SYSCR()                    bfin_read16(SYSCR)
+#define bfin_write_SYSCR(val)                bfin_write16(SYSCR,val)
+#define pSIC_RVECT                      ((void * volatile *)SIC_RVECT)
+#define bfin_read_SIC_RVECT()                bfin_read32(SIC_RVECT)
+#define bfin_write_SIC_RVECT(val)            bfin_write32(SIC_RVECT,val)
+#define bfin_read_SIC_IMASK()                bfin_read32(SIC_IMASK)
+#define bfin_write_SIC_IMASK(val)            bfin_write32(SIC_IMASK,val)
+#define bfin_read_SIC_IAR0()                 bfin_read32(SIC_IAR0)
+#define bfin_write_SIC_IAR0(val)             bfin_write32(SIC_IAR0,val)
+#define bfin_read_SIC_IAR1()                 bfin_read32(SIC_IAR1)
+#define bfin_write_SIC_IAR1(val)             bfin_write32(SIC_IAR1,val)
+#define bfin_read_SIC_IAR2()                 bfin_read32(SIC_IAR2)
+#define bfin_write_SIC_IAR2(val)             bfin_write32(SIC_IAR2,val)
+#define bfin_read_SIC_IAR3()                 bfin_read32(SIC_IAR3)
+#define bfin_write_SIC_IAR3(val)             bfin_write32(SIC_IAR3,val)
+#define bfin_read_SIC_ISR()                  bfin_read32(SIC_ISR)
+#define bfin_write_SIC_ISR(val)              bfin_write32(SIC_ISR,val)
+#define bfin_read_SIC_IWR()                  bfin_read32(SIC_IWR)
+#define bfin_write_SIC_IWR(val)              bfin_write32(SIC_IWR,val)
+
+/* Watchdog Timer               (0xFFC00200 - 0xFFC002FF)                                                                       */
+#define bfin_read_WDOG_CTL()                 bfin_read16(WDOG_CTL)
+#define bfin_write_WDOG_CTL(val)             bfin_write16(WDOG_CTL,val)
+#define bfin_read_WDOG_CNT()                 bfin_read32(WDOG_CNT)
+#define bfin_write_WDOG_CNT(val)             bfin_write32(WDOG_CNT,val)
+#define bfin_read_WDOG_STAT()                bfin_read32(WDOG_STAT)
+#define bfin_write_WDOG_STAT(val)            bfin_write32(WDOG_STAT,val)
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define bfin_read_RTC_STAT()                 bfin_read32(RTC_STAT)
+#define bfin_write_RTC_STAT(val)             bfin_write32(RTC_STAT,val)
+#define bfin_read_RTC_ICTL()                 bfin_read16(RTC_ICTL)
+#define bfin_write_RTC_ICTL(val)             bfin_write16(RTC_ICTL,val)
+#define bfin_read_RTC_ISTAT()                bfin_read16(RTC_ISTAT)
+#define bfin_write_RTC_ISTAT(val)            bfin_write16(RTC_ISTAT,val)
+#define bfin_read_RTC_SWCNT()                bfin_read16(RTC_SWCNT)
+#define bfin_write_RTC_SWCNT(val)            bfin_write16(RTC_SWCNT,val)
+#define bfin_read_RTC_ALARM()                bfin_read32(RTC_ALARM)
+#define bfin_write_RTC_ALARM(val)            bfin_write32(RTC_ALARM,val)
+#define bfin_read_RTC_FAST()                 bfin_read16(RTC_FAST)
+#define bfin_write_RTC_FAST(val)             bfin_write16(RTC_FAST,val)
+#define bfin_read_RTC_PREN()                 bfin_read16(RTC_PREN)
+#define bfin_write_RTC_PREN(val)             bfin_write16(RTC_PREN,val)
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define bfin_read_UART0_THR()                bfin_read16(UART0_THR)
+#define bfin_write_UART0_THR(val)            bfin_write16(UART0_THR,val)
+#define bfin_read_UART0_RBR()                bfin_read16(UART0_RBR)
+#define bfin_write_UART0_RBR(val)            bfin_write16(UART0_RBR,val)
+#define bfin_read_UART0_DLL()                bfin_read16(UART0_DLL)
+#define bfin_write_UART0_DLL(val)            bfin_write16(UART0_DLL,val)
+#define bfin_read_UART0_IER()                bfin_read16(UART0_IER)
+#define bfin_write_UART0_IER(val)            bfin_write16(UART0_IER,val)
+#define bfin_read_UART0_DLH()                bfin_read16(UART0_DLH)
+#define bfin_write_UART0_DLH(val)            bfin_write16(UART0_DLH,val)
+#define bfin_read_UART0_IIR()                bfin_read16(UART0_IIR)
+#define bfin_write_UART0_IIR(val)            bfin_write16(UART0_IIR,val)
+#define bfin_read_UART0_LCR()                bfin_read16(UART0_LCR)
+#define bfin_write_UART0_LCR(val)            bfin_write16(UART0_LCR,val)
+#define bfin_read_UART0_MCR()                bfin_read16(UART0_MCR)
+#define bfin_write_UART0_MCR(val)            bfin_write16(UART0_MCR,val)
+#define bfin_read_UART0_LSR()                bfin_read16(UART0_LSR)
+#define bfin_write_UART0_LSR(val)            bfin_write16(UART0_LSR,val)
+#define bfin_read_UART0_MSR()                bfin_read16(UART0_MSR)
+#define bfin_write_UART0_MSR(val)            bfin_write16(UART0_MSR,val)
+#define bfin_read_UART0_SCR()                bfin_read16(UART0_SCR)
+#define bfin_write_UART0_SCR(val)            bfin_write16(UART0_SCR,val)
+#define bfin_read_UART0_GCTL()               bfin_read16(UART0_GCTL)
+#define bfin_write_UART0_GCTL(val)           bfin_write16(UART0_GCTL,val)
+
+/* SPI Controller               (0xFFC00500 - 0xFFC005FF)                                                                       */
+#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
+#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
+#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
+#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
+#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
+#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
+#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
+#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
+#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
+#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
+
+#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
+#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
+#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
+#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
+
+#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
+#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
+#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
+#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
+
+#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
+#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
+#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
+#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
+
+#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
+#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
+#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
+#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
+
+#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
+#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
+#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
+#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
+
+#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
+#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
+#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
+#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
+
+#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
+#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
+#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
+#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
+
+#define bfin_read_TIMER_ENABLE()             bfin_read16(TIMER_ENABLE)
+#define bfin_write_TIMER_ENABLE(val)         bfin_write16(TIMER_ENABLE,val)
+#define bfin_read_TIMER_DISABLE()            bfin_read16(TIMER_DISABLE)
+#define bfin_write_TIMER_DISABLE(val)        bfin_write16(TIMER_DISABLE,val)
+#define bfin_read_TIMER_STATUS()             bfin_read32(TIMER_STATUS)
+#define bfin_write_TIMER_STATUS(val)         bfin_write32(TIMER_STATUS,val)
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                         */
+#define bfin_read_PORTFIO()                  bfin_read16(PORTFIO)
+#define bfin_write_PORTFIO(val)              bfin_write16(PORTFIO,val)
+#define bfin_read_PORTFIO_CLEAR()            bfin_read16(PORTFIO_CLEAR)
+#define bfin_write_PORTFIO_CLEAR(val)        bfin_write16(PORTFIO_CLEAR,val)
+#define bfin_read_PORTFIO_SET()              bfin_read16(PORTFIO_SET)
+#define bfin_write_PORTFIO_SET(val)          bfin_write16(PORTFIO_SET,val)
+#define bfin_read_PORTFIO_TOGGLE()           bfin_read16(PORTFIO_TOGGLE)
+#define bfin_write_PORTFIO_TOGGLE(val)       bfin_write16(PORTFIO_TOGGLE,val)
+#define bfin_read_PORTFIO_MASKA()            bfin_read16(PORTFIO_MASKA)
+#define bfin_write_PORTFIO_MASKA(val)        bfin_write16(PORTFIO_MASKA,val)
+#define bfin_read_PORTFIO_MASKA_CLEAR()      bfin_read16(PORTFIO_MASKA_CLEAR)
+#define bfin_write_PORTFIO_MASKA_CLEAR(val)  bfin_write16(PORTFIO_MASKA_CLEAR,val)
+#define bfin_read_PORTFIO_MASKA_SET()        bfin_read16(PORTFIO_MASKA_SET)
+#define bfin_write_PORTFIO_MASKA_SET(val)    bfin_write16(PORTFIO_MASKA_SET,val)
+#define bfin_read_PORTFIO_MASKA_TOGGLE()     bfin_read16(PORTFIO_MASKA_TOGGLE)
+#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE,val)
+#define bfin_read_PORTFIO_MASKB()            bfin_read16(PORTFIO_MASKB)
+#define bfin_write_PORTFIO_MASKB(val)        bfin_write16(PORTFIO_MASKB,val)
+#define bfin_read_PORTFIO_MASKB_CLEAR()      bfin_read16(PORTFIO_MASKB_CLEAR)
+#define bfin_write_PORTFIO_MASKB_CLEAR(val)  bfin_write16(PORTFIO_MASKB_CLEAR,val)
+#define bfin_read_PORTFIO_MASKB_SET()        bfin_read16(PORTFIO_MASKB_SET)
+#define bfin_write_PORTFIO_MASKB_SET(val)    bfin_write16(PORTFIO_MASKB_SET,val)
+#define bfin_read_PORTFIO_MASKB_TOGGLE()     bfin_read16(PORTFIO_MASKB_TOGGLE)
+#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE,val)
+#define bfin_read_PORTFIO_DIR()              bfin_read16(PORTFIO_DIR)
+#define bfin_write_PORTFIO_DIR(val)          bfin_write16(PORTFIO_DIR,val)
+#define bfin_read_PORTFIO_POLAR()            bfin_read16(PORTFIO_POLAR)
+#define bfin_write_PORTFIO_POLAR(val)        bfin_write16(PORTFIO_POLAR,val)
+#define bfin_read_PORTFIO_EDGE()             bfin_read16(PORTFIO_EDGE)
+#define bfin_write_PORTFIO_EDGE(val)         bfin_write16(PORTFIO_EDGE,val)
+#define bfin_read_PORTFIO_BOTH()             bfin_read16(PORTFIO_BOTH)
+#define bfin_write_PORTFIO_BOTH(val)         bfin_write16(PORTFIO_BOTH,val)
+#define bfin_read_PORTFIO_INEN()             bfin_read16(PORTFIO_INEN)
+#define bfin_write_PORTFIO_INEN(val)         bfin_write16(PORTFIO_INEN,val)
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                               */
+#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
+#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
+#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
+#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
+#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
+#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
+#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
+#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
+#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
+#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
+#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
+#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
+#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
+#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
+#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
+#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
+#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
+#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
+#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
+#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
+#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
+#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
+#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                               */
+#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
+#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
+#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
+#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
+#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
+#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
+#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
+#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
+#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
+#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
+#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
+#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
+#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
+#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
+#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
+#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
+#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
+#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
+#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
+#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
+#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
+#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
+#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                        */
+#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
+#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
+#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
+#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
+#define bfin_read_EBIU_SDBCTL()              bfin_read16(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)          bfin_write16(EBIU_SDBCTL,val)
+#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
+#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define pDMA_TCPER                      ((volatile unsigned short *)DMA_TCPER)
+#define bfin_read_DMA_TCPER()                bfin_read16(DMA_TCPER)
+#define bfin_write_DMA_TCPER(val)            bfin_write16(DMA_TCPER,val)
+#define pDMA_TCCNT                      ((volatile unsigned short *)DMA_TCCNT)
+#define bfin_read_DMA_TCCNT()                bfin_read16(DMA_TCCNT)
+#define bfin_write_DMA_TCCNT(val)            bfin_write16(DMA_TCCNT,val)
+
+/* DMA Controller                                                                                                                                       */
+#define bfin_read_DMA0_CONFIG()              bfin_read16(DMA0_CONFIG)
+#define bfin_write_DMA0_CONFIG(val)          bfin_write16(DMA0_CONFIG,val)
+#define bfin_read_DMA0_NEXT_DESC_PTR()       bfin_read32(DMA0_NEXT_DESC_PTR)
+#define bfin_write_DMA0_NEXT_DESC_PTR(val)   bfin_write32(DMA0_NEXT_DESC_PTR,val)
+#define bfin_read_DMA0_START_ADDR()          bfin_read32(DMA0_START_ADDR)
+#define bfin_write_DMA0_START_ADDR(val)      bfin_write32(DMA0_START_ADDR,val)
+#define bfin_read_DMA0_X_COUNT()             bfin_read16(DMA0_X_COUNT)
+#define bfin_write_DMA0_X_COUNT(val)         bfin_write16(DMA0_X_COUNT,val)
+#define bfin_read_DMA0_Y_COUNT()             bfin_read16(DMA0_Y_COUNT)
+#define bfin_write_DMA0_Y_COUNT(val)         bfin_write16(DMA0_Y_COUNT,val)
+#define bfin_read_DMA0_X_MODIFY()            bfin_read16(DMA0_X_MODIFY)
+#define bfin_write_DMA0_X_MODIFY(val)        bfin_write16(DMA0_X_MODIFY,val)
+#define bfin_read_DMA0_Y_MODIFY()            bfin_read16(DMA0_Y_MODIFY)
+#define bfin_write_DMA0_Y_MODIFY(val)        bfin_write16(DMA0_Y_MODIFY,val)
+#define bfin_read_DMA0_CURR_DESC_PTR()       bfin_read32(DMA0_CURR_DESC_PTR)
+#define bfin_write_DMA0_CURR_DESC_PTR(val)   bfin_write32(DMA0_CURR_DESC_PTR,val)
+#define bfin_read_DMA0_CURR_ADDR()           bfin_read32(DMA0_CURR_ADDR)
+#define bfin_write_DMA0_CURR_ADDR(val)       bfin_write32(DMA0_CURR_ADDR,val)
+#define bfin_read_DMA0_CURR_X_COUNT()        bfin_read16(DMA0_CURR_X_COUNT)
+#define bfin_write_DMA0_CURR_X_COUNT(val)    bfin_write16(DMA0_CURR_X_COUNT,val)
+#define bfin_read_DMA0_CURR_Y_COUNT()        bfin_read16(DMA0_CURR_Y_COUNT)
+#define bfin_write_DMA0_CURR_Y_COUNT(val)    bfin_write16(DMA0_CURR_Y_COUNT,val)
+#define bfin_read_DMA0_IRQ_STATUS()          bfin_read16(DMA0_IRQ_STATUS)
+#define bfin_write_DMA0_IRQ_STATUS(val)      bfin_write16(DMA0_IRQ_STATUS,val)
+#define bfin_read_DMA0_PERIPHERAL_MAP()      bfin_read16(DMA0_PERIPHERAL_MAP)
+#define bfin_write_DMA0_PERIPHERAL_MAP(val)  bfin_write16(DMA0_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA1_CONFIG()              bfin_read16(DMA1_CONFIG)
+#define bfin_write_DMA1_CONFIG(val)          bfin_write16(DMA1_CONFIG,val)
+#define bfin_read_DMA1_NEXT_DESC_PTR()       bfin_read32(DMA1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_NEXT_DESC_PTR(val)   bfin_write32(DMA1_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_START_ADDR()          bfin_read32(DMA1_START_ADDR)
+#define bfin_write_DMA1_START_ADDR(val)      bfin_write32(DMA1_START_ADDR,val)
+#define bfin_read_DMA1_X_COUNT()             bfin_read16(DMA1_X_COUNT)
+#define bfin_write_DMA1_X_COUNT(val)         bfin_write16(DMA1_X_COUNT,val)
+#define bfin_read_DMA1_Y_COUNT()             bfin_read16(DMA1_Y_COUNT)
+#define bfin_write_DMA1_Y_COUNT(val)         bfin_write16(DMA1_Y_COUNT,val)
+#define bfin_read_DMA1_X_MODIFY()            bfin_read16(DMA1_X_MODIFY)
+#define bfin_write_DMA1_X_MODIFY(val)        bfin_write16(DMA1_X_MODIFY,val)
+#define bfin_read_DMA1_Y_MODIFY()            bfin_read16(DMA1_Y_MODIFY)
+#define bfin_write_DMA1_Y_MODIFY(val)        bfin_write16(DMA1_Y_MODIFY,val)
+#define bfin_read_DMA1_CURR_DESC_PTR()       bfin_read32(DMA1_CURR_DESC_PTR)
+#define bfin_write_DMA1_CURR_DESC_PTR(val)   bfin_write32(DMA1_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_CURR_ADDR()           bfin_read32(DMA1_CURR_ADDR)
+#define bfin_write_DMA1_CURR_ADDR(val)       bfin_write32(DMA1_CURR_ADDR,val)
+#define bfin_read_DMA1_CURR_X_COUNT()        bfin_read16(DMA1_CURR_X_COUNT)
+#define bfin_write_DMA1_CURR_X_COUNT(val)    bfin_write16(DMA1_CURR_X_COUNT,val)
+#define bfin_read_DMA1_CURR_Y_COUNT()        bfin_read16(DMA1_CURR_Y_COUNT)
+#define bfin_write_DMA1_CURR_Y_COUNT(val)    bfin_write16(DMA1_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_IRQ_STATUS()          bfin_read16(DMA1_IRQ_STATUS)
+#define bfin_write_DMA1_IRQ_STATUS(val)      bfin_write16(DMA1_IRQ_STATUS,val)
+#define bfin_read_DMA1_PERIPHERAL_MAP()      bfin_read16(DMA1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_PERIPHERAL_MAP(val)  bfin_write16(DMA1_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA2_CONFIG()              bfin_read16(DMA2_CONFIG)
+#define bfin_write_DMA2_CONFIG(val)          bfin_write16(DMA2_CONFIG,val)
+#define bfin_read_DMA2_NEXT_DESC_PTR()       bfin_read32(DMA2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_NEXT_DESC_PTR(val)   bfin_write32(DMA2_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_START_ADDR()          bfin_read32(DMA2_START_ADDR)
+#define bfin_write_DMA2_START_ADDR(val)      bfin_write32(DMA2_START_ADDR,val)
+#define bfin_read_DMA2_X_COUNT()             bfin_read16(DMA2_X_COUNT)
+#define bfin_write_DMA2_X_COUNT(val)         bfin_write16(DMA2_X_COUNT,val)
+#define bfin_read_DMA2_Y_COUNT()             bfin_read16(DMA2_Y_COUNT)
+#define bfin_write_DMA2_Y_COUNT(val)         bfin_write16(DMA2_Y_COUNT,val)
+#define bfin_read_DMA2_X_MODIFY()            bfin_read16(DMA2_X_MODIFY)
+#define bfin_write_DMA2_X_MODIFY(val)        bfin_write16(DMA2_X_MODIFY,val)
+#define bfin_read_DMA2_Y_MODIFY()            bfin_read16(DMA2_Y_MODIFY)
+#define bfin_write_DMA2_Y_MODIFY(val)        bfin_write16(DMA2_Y_MODIFY,val)
+#define bfin_read_DMA2_CURR_DESC_PTR()       bfin_read32(DMA2_CURR_DESC_PTR)
+#define bfin_write_DMA2_CURR_DESC_PTR(val)   bfin_write32(DMA2_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_CURR_ADDR()           bfin_read32(DMA2_CURR_ADDR)
+#define bfin_write_DMA2_CURR_ADDR(val)       bfin_write32(DMA2_CURR_ADDR,val)
+#define bfin_read_DMA2_CURR_X_COUNT()        bfin_read16(DMA2_CURR_X_COUNT)
+#define bfin_write_DMA2_CURR_X_COUNT(val)    bfin_write16(DMA2_CURR_X_COUNT,val)
+#define bfin_read_DMA2_CURR_Y_COUNT()        bfin_read16(DMA2_CURR_Y_COUNT)
+#define bfin_write_DMA2_CURR_Y_COUNT(val)    bfin_write16(DMA2_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_IRQ_STATUS()          bfin_read16(DMA2_IRQ_STATUS)
+#define bfin_write_DMA2_IRQ_STATUS(val)      bfin_write16(DMA2_IRQ_STATUS,val)
+#define bfin_read_DMA2_PERIPHERAL_MAP()      bfin_read16(DMA2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_PERIPHERAL_MAP(val)  bfin_write16(DMA2_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA3_CONFIG()              bfin_read16(DMA3_CONFIG)
+#define bfin_write_DMA3_CONFIG(val)          bfin_write16(DMA3_CONFIG,val)
+#define bfin_read_DMA3_NEXT_DESC_PTR()       bfin_read32(DMA3_NEXT_DESC_PTR)
+#define bfin_write_DMA3_NEXT_DESC_PTR(val)   bfin_write32(DMA3_NEXT_DESC_PTR,val)
+#define bfin_read_DMA3_START_ADDR()          bfin_read32(DMA3_START_ADDR)
+#define bfin_write_DMA3_START_ADDR(val)      bfin_write32(DMA3_START_ADDR,val)
+#define bfin_read_DMA3_X_COUNT()             bfin_read16(DMA3_X_COUNT)
+#define bfin_write_DMA3_X_COUNT(val)         bfin_write16(DMA3_X_COUNT,val)
+#define bfin_read_DMA3_Y_COUNT()             bfin_read16(DMA3_Y_COUNT)
+#define bfin_write_DMA3_Y_COUNT(val)         bfin_write16(DMA3_Y_COUNT,val)
+#define bfin_read_DMA3_X_MODIFY()            bfin_read16(DMA3_X_MODIFY)
+#define bfin_write_DMA3_X_MODIFY(val)        bfin_write16(DMA3_X_MODIFY,val)
+#define bfin_read_DMA3_Y_MODIFY()            bfin_read16(DMA3_Y_MODIFY)
+#define bfin_write_DMA3_Y_MODIFY(val)        bfin_write16(DMA3_Y_MODIFY,val)
+#define bfin_read_DMA3_CURR_DESC_PTR()       bfin_read32(DMA3_CURR_DESC_PTR)
+#define bfin_write_DMA3_CURR_DESC_PTR(val)   bfin_write32(DMA3_CURR_DESC_PTR,val)
+#define bfin_read_DMA3_CURR_ADDR()           bfin_read32(DMA3_CURR_ADDR)
+#define bfin_write_DMA3_CURR_ADDR(val)       bfin_write32(DMA3_CURR_ADDR,val)
+#define bfin_read_DMA3_CURR_X_COUNT()        bfin_read16(DMA3_CURR_X_COUNT)
+#define bfin_write_DMA3_CURR_X_COUNT(val)    bfin_write16(DMA3_CURR_X_COUNT,val)
+#define bfin_read_DMA3_CURR_Y_COUNT()        bfin_read16(DMA3_CURR_Y_COUNT)
+#define bfin_write_DMA3_CURR_Y_COUNT(val)    bfin_write16(DMA3_CURR_Y_COUNT,val)
+#define bfin_read_DMA3_IRQ_STATUS()          bfin_read16(DMA3_IRQ_STATUS)
+#define bfin_write_DMA3_IRQ_STATUS(val)      bfin_write16(DMA3_IRQ_STATUS,val)
+#define bfin_read_DMA3_PERIPHERAL_MAP()      bfin_read16(DMA3_PERIPHERAL_MAP)
+#define bfin_write_DMA3_PERIPHERAL_MAP(val)  bfin_write16(DMA3_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA4_CONFIG()              bfin_read16(DMA4_CONFIG)
+#define bfin_write_DMA4_CONFIG(val)          bfin_write16(DMA4_CONFIG,val)
+#define bfin_read_DMA4_NEXT_DESC_PTR()       bfin_read32(DMA4_NEXT_DESC_PTR)
+#define bfin_write_DMA4_NEXT_DESC_PTR(val)   bfin_write32(DMA4_NEXT_DESC_PTR,val)
+#define bfin_read_DMA4_START_ADDR()          bfin_read32(DMA4_START_ADDR)
+#define bfin_write_DMA4_START_ADDR(val)      bfin_write32(DMA4_START_ADDR,val)
+#define bfin_read_DMA4_X_COUNT()             bfin_read16(DMA4_X_COUNT)
+#define bfin_write_DMA4_X_COUNT(val)         bfin_write16(DMA4_X_COUNT,val)
+#define bfin_read_DMA4_Y_COUNT()             bfin_read16(DMA4_Y_COUNT)
+#define bfin_write_DMA4_Y_COUNT(val)         bfin_write16(DMA4_Y_COUNT,val)
+#define bfin_read_DMA4_X_MODIFY()            bfin_read16(DMA4_X_MODIFY)
+#define bfin_write_DMA4_X_MODIFY(val)        bfin_write16(DMA4_X_MODIFY,val)
+#define bfin_read_DMA4_Y_MODIFY()            bfin_read16(DMA4_Y_MODIFY)
+#define bfin_write_DMA4_Y_MODIFY(val)        bfin_write16(DMA4_Y_MODIFY,val)
+#define bfin_read_DMA4_CURR_DESC_PTR()       bfin_read32(DMA4_CURR_DESC_PTR)
+#define bfin_write_DMA4_CURR_DESC_PTR(val)   bfin_write32(DMA4_CURR_DESC_PTR,val)
+#define bfin_read_DMA4_CURR_ADDR()           bfin_read32(DMA4_CURR_ADDR)
+#define bfin_write_DMA4_CURR_ADDR(val)       bfin_write32(DMA4_CURR_ADDR,val)
+#define bfin_read_DMA4_CURR_X_COUNT()        bfin_read16(DMA4_CURR_X_COUNT)
+#define bfin_write_DMA4_CURR_X_COUNT(val)    bfin_write16(DMA4_CURR_X_COUNT,val)
+#define bfin_read_DMA4_CURR_Y_COUNT()        bfin_read16(DMA4_CURR_Y_COUNT)
+#define bfin_write_DMA4_CURR_Y_COUNT(val)    bfin_write16(DMA4_CURR_Y_COUNT,val)
+#define bfin_read_DMA4_IRQ_STATUS()          bfin_read16(DMA4_IRQ_STATUS)
+#define bfin_write_DMA4_IRQ_STATUS(val)      bfin_write16(DMA4_IRQ_STATUS,val)
+#define bfin_read_DMA4_PERIPHERAL_MAP()      bfin_read16(DMA4_PERIPHERAL_MAP)
+#define bfin_write_DMA4_PERIPHERAL_MAP(val)  bfin_write16(DMA4_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA5_CONFIG()              bfin_read16(DMA5_CONFIG)
+#define bfin_write_DMA5_CONFIG(val)          bfin_write16(DMA5_CONFIG,val)
+#define bfin_read_DMA5_NEXT_DESC_PTR()       bfin_read32(DMA5_NEXT_DESC_PTR)
+#define bfin_write_DMA5_NEXT_DESC_PTR(val)   bfin_write32(DMA5_NEXT_DESC_PTR,val)
+#define bfin_read_DMA5_START_ADDR()          bfin_read32(DMA5_START_ADDR)
+#define bfin_write_DMA5_START_ADDR(val)      bfin_write32(DMA5_START_ADDR,val)
+#define bfin_read_DMA5_X_COUNT()             bfin_read16(DMA5_X_COUNT)
+#define bfin_write_DMA5_X_COUNT(val)         bfin_write16(DMA5_X_COUNT,val)
+#define bfin_read_DMA5_Y_COUNT()             bfin_read16(DMA5_Y_COUNT)
+#define bfin_write_DMA5_Y_COUNT(val)         bfin_write16(DMA5_Y_COUNT,val)
+#define bfin_read_DMA5_X_MODIFY()            bfin_read16(DMA5_X_MODIFY)
+#define bfin_write_DMA5_X_MODIFY(val)        bfin_write16(DMA5_X_MODIFY,val)
+#define bfin_read_DMA5_Y_MODIFY()            bfin_read16(DMA5_Y_MODIFY)
+#define bfin_write_DMA5_Y_MODIFY(val)        bfin_write16(DMA5_Y_MODIFY,val)
+#define bfin_read_DMA5_CURR_DESC_PTR()       bfin_read32(DMA5_CURR_DESC_PTR)
+#define bfin_write_DMA5_CURR_DESC_PTR(val)   bfin_write32(DMA5_CURR_DESC_PTR,val)
+#define bfin_read_DMA5_CURR_ADDR()           bfin_read32(DMA5_CURR_ADDR)
+#define bfin_write_DMA5_CURR_ADDR(val)       bfin_write32(DMA5_CURR_ADDR,val)
+#define bfin_read_DMA5_CURR_X_COUNT()        bfin_read16(DMA5_CURR_X_COUNT)
+#define bfin_write_DMA5_CURR_X_COUNT(val)    bfin_write16(DMA5_CURR_X_COUNT,val)
+#define bfin_read_DMA5_CURR_Y_COUNT()        bfin_read16(DMA5_CURR_Y_COUNT)
+#define bfin_write_DMA5_CURR_Y_COUNT(val)    bfin_write16(DMA5_CURR_Y_COUNT,val)
+#define bfin_read_DMA5_IRQ_STATUS()          bfin_read16(DMA5_IRQ_STATUS)
+#define bfin_write_DMA5_IRQ_STATUS(val)      bfin_write16(DMA5_IRQ_STATUS,val)
+#define bfin_read_DMA5_PERIPHERAL_MAP()      bfin_read16(DMA5_PERIPHERAL_MAP)
+#define bfin_write_DMA5_PERIPHERAL_MAP(val)  bfin_write16(DMA5_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA6_CONFIG()              bfin_read16(DMA6_CONFIG)
+#define bfin_write_DMA6_CONFIG(val)          bfin_write16(DMA6_CONFIG,val)
+#define bfin_read_DMA6_NEXT_DESC_PTR()       bfin_read32(DMA6_NEXT_DESC_PTR)
+#define bfin_write_DMA6_NEXT_DESC_PTR(val)   bfin_write32(DMA6_NEXT_DESC_PTR,val)
+#define bfin_read_DMA6_START_ADDR()          bfin_read32(DMA6_START_ADDR)
+#define bfin_write_DMA6_START_ADDR(val)      bfin_write32(DMA6_START_ADDR,val)
+#define bfin_read_DMA6_X_COUNT()             bfin_read16(DMA6_X_COUNT)
+#define bfin_write_DMA6_X_COUNT(val)         bfin_write16(DMA6_X_COUNT,val)
+#define bfin_read_DMA6_Y_COUNT()             bfin_read16(DMA6_Y_COUNT)
+#define bfin_write_DMA6_Y_COUNT(val)         bfin_write16(DMA6_Y_COUNT,val)
+#define bfin_read_DMA6_X_MODIFY()            bfin_read16(DMA6_X_MODIFY)
+#define bfin_write_DMA6_X_MODIFY(val)        bfin_write16(DMA6_X_MODIFY,val)
+#define bfin_read_DMA6_Y_MODIFY()            bfin_read16(DMA6_Y_MODIFY)
+#define bfin_write_DMA6_Y_MODIFY(val)        bfin_write16(DMA6_Y_MODIFY,val)
+#define bfin_read_DMA6_CURR_DESC_PTR()       bfin_read32(DMA6_CURR_DESC_PTR)
+#define bfin_write_DMA6_CURR_DESC_PTR(val)   bfin_write32(DMA6_CURR_DESC_PTR,val)
+#define bfin_read_DMA6_CURR_ADDR()           bfin_read32(DMA6_CURR_ADDR)
+#define bfin_write_DMA6_CURR_ADDR(val)       bfin_write32(DMA6_CURR_ADDR,val)
+#define bfin_read_DMA6_CURR_X_COUNT()        bfin_read16(DMA6_CURR_X_COUNT)
+#define bfin_write_DMA6_CURR_X_COUNT(val)    bfin_write16(DMA6_CURR_X_COUNT,val)
+#define bfin_read_DMA6_CURR_Y_COUNT()        bfin_read16(DMA6_CURR_Y_COUNT)
+#define bfin_write_DMA6_CURR_Y_COUNT(val)    bfin_write16(DMA6_CURR_Y_COUNT,val)
+#define bfin_read_DMA6_IRQ_STATUS()          bfin_read16(DMA6_IRQ_STATUS)
+#define bfin_write_DMA6_IRQ_STATUS(val)      bfin_write16(DMA6_IRQ_STATUS,val)
+#define bfin_read_DMA6_PERIPHERAL_MAP()      bfin_read16(DMA6_PERIPHERAL_MAP)
+#define bfin_write_DMA6_PERIPHERAL_MAP(val)  bfin_write16(DMA6_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA7_CONFIG()              bfin_read16(DMA7_CONFIG)
+#define bfin_write_DMA7_CONFIG(val)          bfin_write16(DMA7_CONFIG,val)
+#define bfin_read_DMA7_NEXT_DESC_PTR()       bfin_read32(DMA7_NEXT_DESC_PTR)
+#define bfin_write_DMA7_NEXT_DESC_PTR(val)   bfin_write32(DMA7_NEXT_DESC_PTR,val)
+#define bfin_read_DMA7_START_ADDR()          bfin_read32(DMA7_START_ADDR)
+#define bfin_write_DMA7_START_ADDR(val)      bfin_write32(DMA7_START_ADDR,val)
+#define bfin_read_DMA7_X_COUNT()             bfin_read16(DMA7_X_COUNT)
+#define bfin_write_DMA7_X_COUNT(val)         bfin_write16(DMA7_X_COUNT,val)
+#define bfin_read_DMA7_Y_COUNT()             bfin_read16(DMA7_Y_COUNT)
+#define bfin_write_DMA7_Y_COUNT(val)         bfin_write16(DMA7_Y_COUNT,val)
+#define bfin_read_DMA7_X_MODIFY()            bfin_read16(DMA7_X_MODIFY)
+#define bfin_write_DMA7_X_MODIFY(val)        bfin_write16(DMA7_X_MODIFY,val)
+#define bfin_read_DMA7_Y_MODIFY()            bfin_read16(DMA7_Y_MODIFY)
+#define bfin_write_DMA7_Y_MODIFY(val)        bfin_write16(DMA7_Y_MODIFY,val)
+#define bfin_read_DMA7_CURR_DESC_PTR()       bfin_read32(DMA7_CURR_DESC_PTR)
+#define bfin_write_DMA7_CURR_DESC_PTR(val)   bfin_write32(DMA7_CURR_DESC_PTR,val)
+#define bfin_read_DMA7_CURR_ADDR()           bfin_read32(DMA7_CURR_ADDR)
+#define bfin_write_DMA7_CURR_ADDR(val)       bfin_write32(DMA7_CURR_ADDR,val)
+#define bfin_read_DMA7_CURR_X_COUNT()        bfin_read16(DMA7_CURR_X_COUNT)
+#define bfin_write_DMA7_CURR_X_COUNT(val)    bfin_write16(DMA7_CURR_X_COUNT,val)
+#define bfin_read_DMA7_CURR_Y_COUNT()        bfin_read16(DMA7_CURR_Y_COUNT)
+#define bfin_write_DMA7_CURR_Y_COUNT(val)    bfin_write16(DMA7_CURR_Y_COUNT,val)
+#define bfin_read_DMA7_IRQ_STATUS()          bfin_read16(DMA7_IRQ_STATUS)
+#define bfin_write_DMA7_IRQ_STATUS(val)      bfin_write16(DMA7_IRQ_STATUS,val)
+#define bfin_read_DMA7_PERIPHERAL_MAP()      bfin_read16(DMA7_PERIPHERAL_MAP)
+#define bfin_write_DMA7_PERIPHERAL_MAP(val)  bfin_write16(DMA7_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA8_CONFIG()              bfin_read16(DMA8_CONFIG)
+#define bfin_write_DMA8_CONFIG(val)          bfin_write16(DMA8_CONFIG,val)
+#define bfin_read_DMA8_NEXT_DESC_PTR()       bfin_read32(DMA8_NEXT_DESC_PTR)
+#define bfin_write_DMA8_NEXT_DESC_PTR(val)   bfin_write32(DMA8_NEXT_DESC_PTR,val)
+#define bfin_read_DMA8_START_ADDR()          bfin_read32(DMA8_START_ADDR)
+#define bfin_write_DMA8_START_ADDR(val)      bfin_write32(DMA8_START_ADDR,val)
+#define bfin_read_DMA8_X_COUNT()             bfin_read16(DMA8_X_COUNT)
+#define bfin_write_DMA8_X_COUNT(val)         bfin_write16(DMA8_X_COUNT,val)
+#define bfin_read_DMA8_Y_COUNT()             bfin_read16(DMA8_Y_COUNT)
+#define bfin_write_DMA8_Y_COUNT(val)         bfin_write16(DMA8_Y_COUNT,val)
+#define bfin_read_DMA8_X_MODIFY()            bfin_read16(DMA8_X_MODIFY)
+#define bfin_write_DMA8_X_MODIFY(val)        bfin_write16(DMA8_X_MODIFY,val)
+#define bfin_read_DMA8_Y_MODIFY()            bfin_read16(DMA8_Y_MODIFY)
+#define bfin_write_DMA8_Y_MODIFY(val)        bfin_write16(DMA8_Y_MODIFY,val)
+#define bfin_read_DMA8_CURR_DESC_PTR()       bfin_read32(DMA8_CURR_DESC_PTR)
+#define bfin_write_DMA8_CURR_DESC_PTR(val)   bfin_write32(DMA8_CURR_DESC_PTR,val)
+#define bfin_read_DMA8_CURR_ADDR()           bfin_read32(DMA8_CURR_ADDR)
+#define bfin_write_DMA8_CURR_ADDR(val)       bfin_write32(DMA8_CURR_ADDR,val)
+#define bfin_read_DMA8_CURR_X_COUNT()        bfin_read16(DMA8_CURR_X_COUNT)
+#define bfin_write_DMA8_CURR_X_COUNT(val)    bfin_write16(DMA8_CURR_X_COUNT,val)
+#define bfin_read_DMA8_CURR_Y_COUNT()        bfin_read16(DMA8_CURR_Y_COUNT)
+#define bfin_write_DMA8_CURR_Y_COUNT(val)    bfin_write16(DMA8_CURR_Y_COUNT,val)
+#define bfin_read_DMA8_IRQ_STATUS()          bfin_read16(DMA8_IRQ_STATUS)
+#define bfin_write_DMA8_IRQ_STATUS(val)      bfin_write16(DMA8_IRQ_STATUS,val)
+#define bfin_read_DMA8_PERIPHERAL_MAP()      bfin_read16(DMA8_PERIPHERAL_MAP)
+#define bfin_write_DMA8_PERIPHERAL_MAP(val)  bfin_write16(DMA8_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA9_CONFIG()              bfin_read16(DMA9_CONFIG)
+#define bfin_write_DMA9_CONFIG(val)          bfin_write16(DMA9_CONFIG,val)
+#define bfin_read_DMA9_NEXT_DESC_PTR()       bfin_read32(DMA9_NEXT_DESC_PTR)
+#define bfin_write_DMA9_NEXT_DESC_PTR(val)   bfin_write32(DMA9_NEXT_DESC_PTR,val)
+#define bfin_read_DMA9_START_ADDR()          bfin_read32(DMA9_START_ADDR)
+#define bfin_write_DMA9_START_ADDR(val)      bfin_write32(DMA9_START_ADDR,val)
+#define bfin_read_DMA9_X_COUNT()             bfin_read16(DMA9_X_COUNT)
+#define bfin_write_DMA9_X_COUNT(val)         bfin_write16(DMA9_X_COUNT,val)
+#define bfin_read_DMA9_Y_COUNT()             bfin_read16(DMA9_Y_COUNT)
+#define bfin_write_DMA9_Y_COUNT(val)         bfin_write16(DMA9_Y_COUNT,val)
+#define bfin_read_DMA9_X_MODIFY()            bfin_read16(DMA9_X_MODIFY)
+#define bfin_write_DMA9_X_MODIFY(val)        bfin_write16(DMA9_X_MODIFY,val)
+#define bfin_read_DMA9_Y_MODIFY()            bfin_read16(DMA9_Y_MODIFY)
+#define bfin_write_DMA9_Y_MODIFY(val)        bfin_write16(DMA9_Y_MODIFY,val)
+#define bfin_read_DMA9_CURR_DESC_PTR()       bfin_read32(DMA9_CURR_DESC_PTR)
+#define bfin_write_DMA9_CURR_DESC_PTR(val)   bfin_write32(DMA9_CURR_DESC_PTR,val)
+#define bfin_read_DMA9_CURR_ADDR()           bfin_read32(DMA9_CURR_ADDR)
+#define bfin_write_DMA9_CURR_ADDR(val)       bfin_write32(DMA9_CURR_ADDR,val)
+#define bfin_read_DMA9_CURR_X_COUNT()        bfin_read16(DMA9_CURR_X_COUNT)
+#define bfin_write_DMA9_CURR_X_COUNT(val)    bfin_write16(DMA9_CURR_X_COUNT,val)
+#define bfin_read_DMA9_CURR_Y_COUNT()        bfin_read16(DMA9_CURR_Y_COUNT)
+#define bfin_write_DMA9_CURR_Y_COUNT(val)    bfin_write16(DMA9_CURR_Y_COUNT,val)
+#define bfin_read_DMA9_IRQ_STATUS()          bfin_read16(DMA9_IRQ_STATUS)
+#define bfin_write_DMA9_IRQ_STATUS(val)      bfin_write16(DMA9_IRQ_STATUS,val)
+#define bfin_read_DMA9_PERIPHERAL_MAP()      bfin_read16(DMA9_PERIPHERAL_MAP)
+#define bfin_write_DMA9_PERIPHERAL_MAP(val)  bfin_write16(DMA9_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA10_CONFIG()             bfin_read16(DMA10_CONFIG)
+#define bfin_write_DMA10_CONFIG(val)         bfin_write16(DMA10_CONFIG,val)
+#define bfin_read_DMA10_NEXT_DESC_PTR()      bfin_read32(DMA10_NEXT_DESC_PTR)
+#define bfin_write_DMA10_NEXT_DESC_PTR(val)  bfin_write32(DMA10_NEXT_DESC_PTR,val)
+#define bfin_read_DMA10_START_ADDR()         bfin_read32(DMA10_START_ADDR)
+#define bfin_write_DMA10_START_ADDR(val)     bfin_write32(DMA10_START_ADDR,val)
+#define bfin_read_DMA10_X_COUNT()            bfin_read16(DMA10_X_COUNT)
+#define bfin_write_DMA10_X_COUNT(val)        bfin_write16(DMA10_X_COUNT,val)
+#define bfin_read_DMA10_Y_COUNT()            bfin_read16(DMA10_Y_COUNT)
+#define bfin_write_DMA10_Y_COUNT(val)        bfin_write16(DMA10_Y_COUNT,val)
+#define bfin_read_DMA10_X_MODIFY()           bfin_read16(DMA10_X_MODIFY)
+#define bfin_write_DMA10_X_MODIFY(val)       bfin_write16(DMA10_X_MODIFY,val)
+#define bfin_read_DMA10_Y_MODIFY()           bfin_read16(DMA10_Y_MODIFY)
+#define bfin_write_DMA10_Y_MODIFY(val)       bfin_write16(DMA10_Y_MODIFY,val)
+#define bfin_read_DMA10_CURR_DESC_PTR()      bfin_read32(DMA10_CURR_DESC_PTR)
+#define bfin_write_DMA10_CURR_DESC_PTR(val)  bfin_write32(DMA10_CURR_DESC_PTR,val)
+#define bfin_read_DMA10_CURR_ADDR()          bfin_read32(DMA10_CURR_ADDR)
+#define bfin_write_DMA10_CURR_ADDR(val)      bfin_write32(DMA10_CURR_ADDR,val)
+#define bfin_read_DMA10_CURR_X_COUNT()       bfin_read16(DMA10_CURR_X_COUNT)
+#define bfin_write_DMA10_CURR_X_COUNT(val)   bfin_write16(DMA10_CURR_X_COUNT,val)
+#define bfin_read_DMA10_CURR_Y_COUNT()       bfin_read16(DMA10_CURR_Y_COUNT)
+#define bfin_write_DMA10_CURR_Y_COUNT(val)   bfin_write16(DMA10_CURR_Y_COUNT,val)
+#define bfin_read_DMA10_IRQ_STATUS()         bfin_read16(DMA10_IRQ_STATUS)
+#define bfin_write_DMA10_IRQ_STATUS(val)     bfin_write16(DMA10_IRQ_STATUS,val)
+#define bfin_read_DMA10_PERIPHERAL_MAP()     bfin_read16(DMA10_PERIPHERAL_MAP)
+#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP,val)
+
+#define bfin_read_DMA11_CONFIG()             bfin_read16(DMA11_CONFIG)
+#define bfin_write_DMA11_CONFIG(val)         bfin_write16(DMA11_CONFIG,val)
+#define bfin_read_DMA11_NEXT_DESC_PTR()      bfin_read32(DMA11_NEXT_DESC_PTR)
+#define bfin_write_DMA11_NEXT_DESC_PTR(val)  bfin_write32(DMA11_NEXT_DESC_PTR,val)
+#define bfin_read_DMA11_START_ADDR()         bfin_read32(DMA11_START_ADDR)
+#define bfin_write_DMA11_START_ADDR(val)     bfin_write32(DMA11_START_ADDR,val)
+#define bfin_read_DMA11_X_COUNT()            bfin_read16(DMA11_X_COUNT)
+#define bfin_write_DMA11_X_COUNT(val)        bfin_write16(DMA11_X_COUNT,val)
+#define bfin_read_DMA11_Y_COUNT()            bfin_read16(DMA11_Y_COUNT)
+#define bfin_write_DMA11_Y_COUNT(val)        bfin_write16(DMA11_Y_COUNT,val)
+#define bfin_read_DMA11_X_MODIFY()           bfin_read16(DMA11_X_MODIFY)
+#define bfin_write_DMA11_X_MODIFY(val)       bfin_write16(DMA11_X_MODIFY,val)
+#define bfin_read_DMA11_Y_MODIFY()           bfin_read16(DMA11_Y_MODIFY)
+#define bfin_write_DMA11_Y_MODIFY(val)       bfin_write16(DMA11_Y_MODIFY,val)
+#define bfin_read_DMA11_CURR_DESC_PTR()      bfin_read32(DMA11_CURR_DESC_PTR)
+#define bfin_write_DMA11_CURR_DESC_PTR(val)  bfin_write32(DMA11_CURR_DESC_PTR,val)
+#define bfin_read_DMA11_CURR_ADDR()          bfin_read32(DMA11_CURR_ADDR)
+#define bfin_write_DMA11_CURR_ADDR(val)      bfin_write32(DMA11_CURR_ADDR,val)
+#define bfin_read_DMA11_CURR_X_COUNT()       bfin_read16(DMA11_CURR_X_COUNT)
+#define bfin_write_DMA11_CURR_X_COUNT(val)   bfin_write16(DMA11_CURR_X_COUNT,val)
+#define bfin_read_DMA11_CURR_Y_COUNT()       bfin_read16(DMA11_CURR_Y_COUNT)
+#define bfin_write_DMA11_CURR_Y_COUNT(val)   bfin_write16(DMA11_CURR_Y_COUNT,val)
+#define bfin_read_DMA11_IRQ_STATUS()         bfin_read16(DMA11_IRQ_STATUS)
+#define bfin_write_DMA11_IRQ_STATUS(val)     bfin_write16(DMA11_IRQ_STATUS,val)
+#define bfin_read_DMA11_PERIPHERAL_MAP()     bfin_read16(DMA11_PERIPHERAL_MAP)
+#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_D0_CONFIG()           bfin_read16(MDMA_D0_CONFIG)
+#define bfin_write_MDMA_D0_CONFIG(val)       bfin_write16(MDMA_D0_CONFIG,val)
+#define bfin_read_MDMA_D0_NEXT_DESC_PTR()    bfin_read32(MDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D0_START_ADDR()       bfin_read32(MDMA_D0_START_ADDR)
+#define bfin_write_MDMA_D0_START_ADDR(val)   bfin_write32(MDMA_D0_START_ADDR,val)
+#define bfin_read_MDMA_D0_X_COUNT()          bfin_read16(MDMA_D0_X_COUNT)
+#define bfin_write_MDMA_D0_X_COUNT(val)      bfin_write16(MDMA_D0_X_COUNT,val)
+#define bfin_read_MDMA_D0_Y_COUNT()          bfin_read16(MDMA_D0_Y_COUNT)
+#define bfin_write_MDMA_D0_Y_COUNT(val)      bfin_write16(MDMA_D0_Y_COUNT,val)
+#define bfin_read_MDMA_D0_X_MODIFY()         bfin_read16(MDMA_D0_X_MODIFY)
+#define bfin_write_MDMA_D0_X_MODIFY(val)     bfin_write16(MDMA_D0_X_MODIFY,val)
+#define bfin_read_MDMA_D0_Y_MODIFY()         bfin_read16(MDMA_D0_Y_MODIFY)
+#define bfin_write_MDMA_D0_Y_MODIFY(val)     bfin_write16(MDMA_D0_Y_MODIFY,val)
+#define bfin_read_MDMA_D0_CURR_DESC_PTR()    bfin_read32(MDMA_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D0_CURR_ADDR()        bfin_read32(MDMA_D0_CURR_ADDR)
+#define bfin_write_MDMA_D0_CURR_ADDR(val)    bfin_write32(MDMA_D0_CURR_ADDR,val)
+#define bfin_read_MDMA_D0_CURR_X_COUNT()     bfin_read16(MDMA_D0_CURR_X_COUNT)
+#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D0_CURR_Y_COUNT()     bfin_read16(MDMA_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()       bfin_read16(MDMA_D0_IRQ_STATUS)
+#define bfin_write_MDMA_D0_IRQ_STATUS(val)   bfin_write16(MDMA_D0_IRQ_STATUS,val)
+#define bfin_read_MDMA_D0_PERIPHERAL_MAP()   bfin_read16(MDMA_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_S0_CONFIG()           bfin_read16(MDMA_S0_CONFIG)
+#define bfin_write_MDMA_S0_CONFIG(val)       bfin_write16(MDMA_S0_CONFIG,val)
+#define bfin_read_MDMA_S0_NEXT_DESC_PTR()    bfin_read32(MDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S0_START_ADDR()       bfin_read32(MDMA_S0_START_ADDR)
+#define bfin_write_MDMA_S0_START_ADDR(val)   bfin_write32(MDMA_S0_START_ADDR,val)
+#define bfin_read_MDMA_S0_X_COUNT()          bfin_read16(MDMA_S0_X_COUNT)
+#define bfin_write_MDMA_S0_X_COUNT(val)      bfin_write16(MDMA_S0_X_COUNT,val)
+#define bfin_read_MDMA_S0_Y_COUNT()          bfin_read16(MDMA_S0_Y_COUNT)
+#define bfin_write_MDMA_S0_Y_COUNT(val)      bfin_write16(MDMA_S0_Y_COUNT,val)
+#define bfin_read_MDMA_S0_X_MODIFY()         bfin_read16(MDMA_S0_X_MODIFY)
+#define bfin_write_MDMA_S0_X_MODIFY(val)     bfin_write16(MDMA_S0_X_MODIFY,val)
+#define bfin_read_MDMA_S0_Y_MODIFY()         bfin_read16(MDMA_S0_Y_MODIFY)
+#define bfin_write_MDMA_S0_Y_MODIFY(val)     bfin_write16(MDMA_S0_Y_MODIFY,val)
+#define bfin_read_MDMA_S0_CURR_DESC_PTR()    bfin_read32(MDMA_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S0_CURR_ADDR()        bfin_read32(MDMA_S0_CURR_ADDR)
+#define bfin_write_MDMA_S0_CURR_ADDR(val)    bfin_write32(MDMA_S0_CURR_ADDR,val)
+#define bfin_read_MDMA_S0_CURR_X_COUNT()     bfin_read16(MDMA_S0_CURR_X_COUNT)
+#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S0_CURR_Y_COUNT()     bfin_read16(MDMA_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()       bfin_read16(MDMA_S0_IRQ_STATUS)
+#define bfin_write_MDMA_S0_IRQ_STATUS(val)   bfin_write16(MDMA_S0_IRQ_STATUS,val)
+#define bfin_read_MDMA_S0_PERIPHERAL_MAP()   bfin_read16(MDMA_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_D1_CONFIG()           bfin_read16(MDMA_D1_CONFIG)
+#define bfin_write_MDMA_D1_CONFIG(val)       bfin_write16(MDMA_D1_CONFIG,val)
+#define bfin_read_MDMA_D1_NEXT_DESC_PTR()    bfin_read32(MDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_D1_START_ADDR()       bfin_read32(MDMA_D1_START_ADDR)
+#define bfin_write_MDMA_D1_START_ADDR(val)   bfin_write32(MDMA_D1_START_ADDR,val)
+#define bfin_read_MDMA_D1_X_COUNT()          bfin_read16(MDMA_D1_X_COUNT)
+#define bfin_write_MDMA_D1_X_COUNT(val)      bfin_write16(MDMA_D1_X_COUNT,val)
+#define bfin_read_MDMA_D1_Y_COUNT()          bfin_read16(MDMA_D1_Y_COUNT)
+#define bfin_write_MDMA_D1_Y_COUNT(val)      bfin_write16(MDMA_D1_Y_COUNT,val)
+#define bfin_read_MDMA_D1_X_MODIFY()         bfin_read16(MDMA_D1_X_MODIFY)
+#define bfin_write_MDMA_D1_X_MODIFY(val)     bfin_write16(MDMA_D1_X_MODIFY,val)
+#define bfin_read_MDMA_D1_Y_MODIFY()         bfin_read16(MDMA_D1_Y_MODIFY)
+#define bfin_write_MDMA_D1_Y_MODIFY(val)     bfin_write16(MDMA_D1_Y_MODIFY,val)
+#define bfin_read_MDMA_D1_CURR_DESC_PTR()    bfin_read32(MDMA_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_D1_CURR_ADDR()        bfin_read32(MDMA_D1_CURR_ADDR)
+#define bfin_write_MDMA_D1_CURR_ADDR(val)    bfin_write32(MDMA_D1_CURR_ADDR,val)
+#define bfin_read_MDMA_D1_CURR_X_COUNT()     bfin_read16(MDMA_D1_CURR_X_COUNT)
+#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_D1_CURR_Y_COUNT()     bfin_read16(MDMA_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_D1_IRQ_STATUS()       bfin_read16(MDMA_D1_IRQ_STATUS)
+#define bfin_write_MDMA_D1_IRQ_STATUS(val)   bfin_write16(MDMA_D1_IRQ_STATUS,val)
+#define bfin_read_MDMA_D1_PERIPHERAL_MAP()   bfin_read16(MDMA_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP,val)
+
+#define bfin_read_MDMA_S1_CONFIG()           bfin_read16(MDMA_S1_CONFIG)
+#define bfin_write_MDMA_S1_CONFIG(val)       bfin_write16(MDMA_S1_CONFIG,val)
+#define bfin_read_MDMA_S1_NEXT_DESC_PTR()    bfin_read32(MDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA_S1_START_ADDR()       bfin_read32(MDMA_S1_START_ADDR)
+#define bfin_write_MDMA_S1_START_ADDR(val)   bfin_write32(MDMA_S1_START_ADDR,val)
+#define bfin_read_MDMA_S1_X_COUNT()          bfin_read16(MDMA_S1_X_COUNT)
+#define bfin_write_MDMA_S1_X_COUNT(val)      bfin_write16(MDMA_S1_X_COUNT,val)
+#define bfin_read_MDMA_S1_Y_COUNT()          bfin_read16(MDMA_S1_Y_COUNT)
+#define bfin_write_MDMA_S1_Y_COUNT(val)      bfin_write16(MDMA_S1_Y_COUNT,val)
+#define bfin_read_MDMA_S1_X_MODIFY()         bfin_read16(MDMA_S1_X_MODIFY)
+#define bfin_write_MDMA_S1_X_MODIFY(val)     bfin_write16(MDMA_S1_X_MODIFY,val)
+#define bfin_read_MDMA_S1_Y_MODIFY()         bfin_read16(MDMA_S1_Y_MODIFY)
+#define bfin_write_MDMA_S1_Y_MODIFY(val)     bfin_write16(MDMA_S1_Y_MODIFY,val)
+#define bfin_read_MDMA_S1_CURR_DESC_PTR()    bfin_read32(MDMA_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA_S1_CURR_ADDR()        bfin_read32(MDMA_S1_CURR_ADDR)
+#define bfin_write_MDMA_S1_CURR_ADDR(val)    bfin_write32(MDMA_S1_CURR_ADDR,val)
+#define bfin_read_MDMA_S1_CURR_X_COUNT()     bfin_read16(MDMA_S1_CURR_X_COUNT)
+#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT,val)
+#define bfin_read_MDMA_S1_CURR_Y_COUNT()     bfin_read16(MDMA_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA_S1_IRQ_STATUS()       bfin_read16(MDMA_S1_IRQ_STATUS)
+#define bfin_write_MDMA_S1_IRQ_STATUS(val)   bfin_write16(MDMA_S1_IRQ_STATUS,val)
+#define bfin_read_MDMA_S1_PERIPHERAL_MAP()   bfin_read16(MDMA_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP,val)
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                                                      */
+#define bfin_read_PPI_CONTROL()              bfin_read16(PPI_CONTROL)
+#define bfin_write_PPI_CONTROL(val)          bfin_write16(PPI_CONTROL,val)
+#define bfin_read_PPI_STATUS()               bfin_read16(PPI_STATUS)
+#define bfin_write_PPI_STATUS(val)           bfin_write16(PPI_STATUS,val)
+#define bfin_clear_PPI_STATUS()              bfin_write_PPI_STATUS(0xFFFF)
+#define bfin_read_PPI_DELAY()                bfin_read16(PPI_DELAY)
+#define bfin_write_PPI_DELAY(val)            bfin_write16(PPI_DELAY,val)
+#define bfin_read_PPI_COUNT()                bfin_read16(PPI_COUNT)
+#define bfin_write_PPI_COUNT(val)            bfin_write16(PPI_COUNT,val)
+#define bfin_read_PPI_FRAME()                bfin_read16(PPI_FRAME)
+#define bfin_write_PPI_FRAME(val)            bfin_write16(PPI_FRAME,val)
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define bfin_read_TWI_CLKDIV()               bfin_read16(TWI_CLKDIV)
+#define bfin_write_TWI_CLKDIV(val)           bfin_write16(TWI_CLKDIV,val)
+#define bfin_read_TWI_CONTROL()              bfin_read16(TWI_CONTROL)
+#define bfin_write_TWI_CONTROL(val)          bfin_write16(TWI_CONTROL,val)
+#define bfin_read_TWI_SLAVE_CTL()            bfin_read16(TWI_SLAVE_CTL)
+#define bfin_write_TWI_SLAVE_CTL(val)        bfin_write16(TWI_SLAVE_CTL,val)
+#define bfin_read_TWI_SLAVE_STAT()           bfin_read16(TWI_SLAVE_STAT)
+#define bfin_write_TWI_SLAVE_STAT(val)       bfin_write16(TWI_SLAVE_STAT,val)
+#define bfin_read_TWI_SLAVE_ADDR()           bfin_read16(TWI_SLAVE_ADDR)
+#define bfin_write_TWI_SLAVE_ADDR(val)       bfin_write16(TWI_SLAVE_ADDR,val)
+#define bfin_read_TWI_MASTER_CTL()           bfin_read16(TWI_MASTER_CTL)
+#define bfin_write_TWI_MASTER_CTL(val)       bfin_write16(TWI_MASTER_CTL,val)
+#define bfin_read_TWI_MASTER_STAT()          bfin_read16(TWI_MASTER_STAT)
+#define bfin_write_TWI_MASTER_STAT(val)      bfin_write16(TWI_MASTER_STAT,val)
+#define bfin_read_TWI_MASTER_ADDR()          bfin_read16(TWI_MASTER_ADDR)
+#define bfin_write_TWI_MASTER_ADDR(val)      bfin_write16(TWI_MASTER_ADDR,val)
+#define bfin_read_TWI_INT_STAT()             bfin_read16(TWI_INT_STAT)
+#define bfin_write_TWI_INT_STAT(val)         bfin_write16(TWI_INT_STAT,val)
+#define bfin_read_TWI_INT_MASK()             bfin_read16(TWI_INT_MASK)
+#define bfin_write_TWI_INT_MASK(val)         bfin_write16(TWI_INT_MASK,val)
+#define bfin_read_TWI_FIFO_CTL()             bfin_read16(TWI_FIFO_CTL)
+#define bfin_write_TWI_FIFO_CTL(val)         bfin_write16(TWI_FIFO_CTL,val)
+#define bfin_read_TWI_FIFO_STAT()            bfin_read16(TWI_FIFO_STAT)
+#define bfin_write_TWI_FIFO_STAT(val)        bfin_write16(TWI_FIFO_STAT,val)
+#define bfin_read_TWI_XMT_DATA8()            bfin_read16(TWI_XMT_DATA8)
+#define bfin_write_TWI_XMT_DATA8(val)        bfin_write16(TWI_XMT_DATA8,val)
+#define bfin_read_TWI_XMT_DATA16()           bfin_read16(TWI_XMT_DATA16)
+#define bfin_write_TWI_XMT_DATA16(val)       bfin_write16(TWI_XMT_DATA16,val)
+#define bfin_read_TWI_RCV_DATA8()            bfin_read16(TWI_RCV_DATA8)
+#define bfin_write_TWI_RCV_DATA8(val)        bfin_write16(TWI_RCV_DATA8,val)
+#define bfin_read_TWI_RCV_DATA16()           bfin_read16(TWI_RCV_DATA16)
+#define bfin_write_TWI_RCV_DATA16(val)       bfin_write16(TWI_RCV_DATA16,val)
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                         */
+#define bfin_read_PORTGIO()                  bfin_read16(PORTGIO)
+#define bfin_write_PORTGIO(val)              bfin_write16(PORTGIO,val)
+#define bfin_read_PORTGIO_CLEAR()            bfin_read16(PORTGIO_CLEAR)
+#define bfin_write_PORTGIO_CLEAR(val)        bfin_write16(PORTGIO_CLEAR,val)
+#define bfin_read_PORTGIO_SET()              bfin_read16(PORTGIO_SET)
+#define bfin_write_PORTGIO_SET(val)          bfin_write16(PORTGIO_SET,val)
+#define bfin_read_PORTGIO_TOGGLE()           bfin_read16(PORTGIO_TOGGLE)
+#define bfin_write_PORTGIO_TOGGLE(val)       bfin_write16(PORTGIO_TOGGLE,val)
+#define bfin_read_PORTGIO_MASKA()            bfin_read16(PORTGIO_MASKA)
+#define bfin_write_PORTGIO_MASKA(val)        bfin_write16(PORTGIO_MASKA,val)
+#define bfin_read_PORTGIO_MASKA_CLEAR()      bfin_read16(PORTGIO_MASKA_CLEAR)
+#define bfin_write_PORTGIO_MASKA_CLEAR(val)  bfin_write16(PORTGIO_MASKA_CLEAR,val)
+#define bfin_read_PORTGIO_MASKA_SET()        bfin_read16(PORTGIO_MASKA_SET)
+#define bfin_write_PORTGIO_MASKA_SET(val)    bfin_write16(PORTGIO_MASKA_SET,val)
+#define bfin_read_PORTGIO_MASKA_TOGGLE()     bfin_read16(PORTGIO_MASKA_TOGGLE)
+#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE,val)
+#define bfin_read_PORTGIO_MASKB()            bfin_read16(PORTGIO_MASKB)
+#define bfin_write_PORTGIO_MASKB(val)        bfin_write16(PORTGIO_MASKB,val)
+#define bfin_read_PORTGIO_MASKB_CLEAR()      bfin_read16(PORTGIO_MASKB_CLEAR)
+#define bfin_write_PORTGIO_MASKB_CLEAR(val)  bfin_write16(PORTGIO_MASKB_CLEAR,val)
+#define bfin_read_PORTGIO_MASKB_SET()        bfin_read16(PORTGIO_MASKB_SET)
+#define bfin_write_PORTGIO_MASKB_SET(val)    bfin_write16(PORTGIO_MASKB_SET,val)
+#define bfin_read_PORTGIO_MASKB_TOGGLE()     bfin_read16(PORTGIO_MASKB_TOGGLE)
+#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE,val)
+#define bfin_read_PORTGIO_DIR()              bfin_read16(PORTGIO_DIR)
+#define bfin_write_PORTGIO_DIR(val)          bfin_write16(PORTGIO_DIR,val)
+#define bfin_read_PORTGIO_POLAR()            bfin_read16(PORTGIO_POLAR)
+#define bfin_write_PORTGIO_POLAR(val)        bfin_write16(PORTGIO_POLAR,val)
+#define bfin_read_PORTGIO_EDGE()             bfin_read16(PORTGIO_EDGE)
+#define bfin_write_PORTGIO_EDGE(val)         bfin_write16(PORTGIO_EDGE,val)
+#define bfin_read_PORTGIO_BOTH()             bfin_read16(PORTGIO_BOTH)
+#define bfin_write_PORTGIO_BOTH(val)         bfin_write16(PORTGIO_BOTH,val)
+#define bfin_read_PORTGIO_INEN()             bfin_read16(PORTGIO_INEN)
+#define bfin_write_PORTGIO_INEN(val)         bfin_write16(PORTGIO_INEN,val)
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                         */
+#define bfin_read_PORTHIO()                  bfin_read16(PORTHIO)
+#define bfin_write_PORTHIO(val)              bfin_write16(PORTHIO,val)
+#define bfin_read_PORTHIO_CLEAR()            bfin_read16(PORTHIO_CLEAR)
+#define bfin_write_PORTHIO_CLEAR(val)        bfin_write16(PORTHIO_CLEAR,val)
+#define bfin_read_PORTHIO_SET()              bfin_read16(PORTHIO_SET)
+#define bfin_write_PORTHIO_SET(val)          bfin_write16(PORTHIO_SET,val)
+#define bfin_read_PORTHIO_TOGGLE()           bfin_read16(PORTHIO_TOGGLE)
+#define bfin_write_PORTHIO_TOGGLE(val)       bfin_write16(PORTHIO_TOGGLE,val)
+#define bfin_read_PORTHIO_MASKA()            bfin_read16(PORTHIO_MASKA)
+#define bfin_write_PORTHIO_MASKA(val)        bfin_write16(PORTHIO_MASKA,val)
+#define bfin_read_PORTHIO_MASKA_CLEAR()      bfin_read16(PORTHIO_MASKA_CLEAR)
+#define bfin_write_PORTHIO_MASKA_CLEAR(val)  bfin_write16(PORTHIO_MASKA_CLEAR,val)
+#define bfin_read_PORTHIO_MASKA_SET()        bfin_read16(PORTHIO_MASKA_SET)
+#define bfin_write_PORTHIO_MASKA_SET(val)    bfin_write16(PORTHIO_MASKA_SET,val)
+#define bfin_read_PORTHIO_MASKA_TOGGLE()     bfin_read16(PORTHIO_MASKA_TOGGLE)
+#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE,val)
+#define bfin_read_PORTHIO_MASKB()            bfin_read16(PORTHIO_MASKB)
+#define bfin_write_PORTHIO_MASKB(val)        bfin_write16(PORTHIO_MASKB,val)
+#define bfin_read_PORTHIO_MASKB_CLEAR()      bfin_read16(PORTHIO_MASKB_CLEAR)
+#define bfin_write_PORTHIO_MASKB_CLEAR(val)  bfin_write16(PORTHIO_MASKB_CLEAR,val)
+#define bfin_read_PORTHIO_MASKB_SET()        bfin_read16(PORTHIO_MASKB_SET)
+#define bfin_write_PORTHIO_MASKB_SET(val)    bfin_write16(PORTHIO_MASKB_SET,val)
+#define bfin_read_PORTHIO_MASKB_TOGGLE()     bfin_read16(PORTHIO_MASKB_TOGGLE)
+#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE,val)
+#define bfin_read_PORTHIO_DIR()              bfin_read16(PORTHIO_DIR)
+#define bfin_write_PORTHIO_DIR(val)          bfin_write16(PORTHIO_DIR,val)
+#define bfin_read_PORTHIO_POLAR()            bfin_read16(PORTHIO_POLAR)
+#define bfin_write_PORTHIO_POLAR(val)        bfin_write16(PORTHIO_POLAR,val)
+#define bfin_read_PORTHIO_EDGE()             bfin_read16(PORTHIO_EDGE)
+#define bfin_write_PORTHIO_EDGE(val)         bfin_write16(PORTHIO_EDGE,val)
+#define bfin_read_PORTHIO_BOTH()             bfin_read16(PORTHIO_BOTH)
+#define bfin_write_PORTHIO_BOTH(val)         bfin_write16(PORTHIO_BOTH,val)
+#define bfin_read_PORTHIO_INEN()             bfin_read16(PORTHIO_INEN)
+#define bfin_write_PORTHIO_INEN(val)         bfin_write16(PORTHIO_INEN,val)
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define bfin_read_UART1_THR()                bfin_read16(UART1_THR)
+#define bfin_write_UART1_THR(val)            bfin_write16(UART1_THR,val)
+#define bfin_read_UART1_RBR()                bfin_read16(UART1_RBR)
+#define bfin_write_UART1_RBR(val)            bfin_write16(UART1_RBR,val)
+#define bfin_read_UART1_DLL()                bfin_read16(UART1_DLL)
+#define bfin_write_UART1_DLL(val)            bfin_write16(UART1_DLL,val)
+#define bfin_read_UART1_IER()                bfin_read16(UART1_IER)
+#define bfin_write_UART1_IER(val)            bfin_write16(UART1_IER,val)
+#define bfin_read_UART1_DLH()                bfin_read16(UART1_DLH)
+#define bfin_write_UART1_DLH(val)            bfin_write16(UART1_DLH,val)
+#define bfin_read_UART1_IIR()                bfin_read16(UART1_IIR)
+#define bfin_write_UART1_IIR(val)            bfin_write16(UART1_IIR,val)
+#define bfin_read_UART1_LCR()                bfin_read16(UART1_LCR)
+#define bfin_write_UART1_LCR(val)            bfin_write16(UART1_LCR,val)
+#define bfin_read_UART1_MCR()                bfin_read16(UART1_MCR)
+#define bfin_write_UART1_MCR(val)            bfin_write16(UART1_MCR,val)
+#define bfin_read_UART1_LSR()                bfin_read16(UART1_LSR)
+#define bfin_write_UART1_LSR(val)            bfin_write16(UART1_LSR,val)
+#define bfin_read_UART1_MSR()                bfin_read16(UART1_MSR)
+#define bfin_write_UART1_MSR(val)            bfin_write16(UART1_MSR,val)
+#define bfin_read_UART1_SCR()                bfin_read16(UART1_SCR)
+#define bfin_write_UART1_SCR(val)            bfin_write16(UART1_SCR,val)
+#define bfin_read_UART1_GCTL()               bfin_read16(UART1_GCTL)
+#define bfin_write_UART1_GCTL(val)           bfin_write16(UART1_GCTL,val)
+
+/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                               */
+/* For Mailboxes 0-15 */
+#define bfin_read_CAN_MC1()                  bfin_read16(CAN_MC1)
+#define bfin_write_CAN_MC1(val)              bfin_write16(CAN_MC1,val)
+#define bfin_read_CAN_MD1()                  bfin_read16(CAN_MD1)
+#define bfin_write_CAN_MD1(val)              bfin_write16(CAN_MD1,val)
+#define bfin_read_CAN_TRS1()                 bfin_read16(CAN_TRS1)
+#define bfin_write_CAN_TRS1(val)             bfin_write16(CAN_TRS1,val)
+#define bfin_read_CAN_TRR1()                 bfin_read16(CAN_TRR1)
+#define bfin_write_CAN_TRR1(val)             bfin_write16(CAN_TRR1,val)
+#define bfin_read_CAN_TA1()                  bfin_read16(CAN_TA1)
+#define bfin_write_CAN_TA1(val)              bfin_write16(CAN_TA1,val)
+#define bfin_read_CAN_AA1()                  bfin_read16(CAN_AA1)
+#define bfin_write_CAN_AA1(val)              bfin_write16(CAN_AA1,val)
+#define bfin_read_CAN_RMP1()                 bfin_read16(CAN_RMP1)
+#define bfin_write_CAN_RMP1(val)             bfin_write16(CAN_RMP1,val)
+#define bfin_read_CAN_RML1()                 bfin_read16(CAN_RML1)
+#define bfin_write_CAN_RML1(val)             bfin_write16(CAN_RML1,val)
+#define bfin_read_CAN_MBTIF1()               bfin_read16(CAN_MBTIF1)
+#define bfin_write_CAN_MBTIF1(val)           bfin_write16(CAN_MBTIF1,val)
+#define bfin_read_CAN_MBRIF1()               bfin_read16(CAN_MBRIF1)
+#define bfin_write_CAN_MBRIF1(val)           bfin_write16(CAN_MBRIF1,val)
+#define bfin_read_CAN_MBIM1()                bfin_read16(CAN_MBIM1)
+#define bfin_write_CAN_MBIM1(val)            bfin_write16(CAN_MBIM1,val)
+#define bfin_read_CAN_RFH1()                 bfin_read16(CAN_RFH1)
+#define bfin_write_CAN_RFH1(val)             bfin_write16(CAN_RFH1,val)
+#define bfin_read_CAN_OPSS1()                bfin_read16(CAN_OPSS1)
+#define bfin_write_CAN_OPSS1(val)            bfin_write16(CAN_OPSS1,val)
+
+/* For Mailboxes 16-31 */
+#define bfin_read_CAN_MC2()                  bfin_read16(CAN_MC2)
+#define bfin_write_CAN_MC2(val)              bfin_write16(CAN_MC2,val)
+#define bfin_read_CAN_MD2()                  bfin_read16(CAN_MD2)
+#define bfin_write_CAN_MD2(val)              bfin_write16(CAN_MD2,val)
+#define bfin_read_CAN_TRS2()                 bfin_read16(CAN_TRS2)
+#define bfin_write_CAN_TRS2(val)             bfin_write16(CAN_TRS2,val)
+#define bfin_read_CAN_TRR2()                 bfin_read16(CAN_TRR2)
+#define bfin_write_CAN_TRR2(val)             bfin_write16(CAN_TRR2,val)
+#define bfin_read_CAN_TA2()                  bfin_read16(CAN_TA2)
+#define bfin_write_CAN_TA2(val)              bfin_write16(CAN_TA2,val)
+#define bfin_read_CAN_AA2()                  bfin_read16(CAN_AA2)
+#define bfin_write_CAN_AA2(val)              bfin_write16(CAN_AA2,val)
+#define bfin_read_CAN_RMP2()                 bfin_read16(CAN_RMP2)
+#define bfin_write_CAN_RMP2(val)             bfin_write16(CAN_RMP2,val)
+#define bfin_read_CAN_RML2()                 bfin_read16(CAN_RML2)
+#define bfin_write_CAN_RML2(val)             bfin_write16(CAN_RML2,val)
+#define bfin_read_CAN_MBTIF2()               bfin_read16(CAN_MBTIF2)
+#define bfin_write_CAN_MBTIF2(val)           bfin_write16(CAN_MBTIF2,val)
+#define bfin_read_CAN_MBRIF2()               bfin_read16(CAN_MBRIF2)
+#define bfin_write_CAN_MBRIF2(val)           bfin_write16(CAN_MBRIF2,val)
+#define bfin_read_CAN_MBIM2()                bfin_read16(CAN_MBIM2)
+#define bfin_write_CAN_MBIM2(val)            bfin_write16(CAN_MBIM2,val)
+#define bfin_read_CAN_RFH2()                 bfin_read16(CAN_RFH2)
+#define bfin_write_CAN_RFH2(val)             bfin_write16(CAN_RFH2,val)
+#define bfin_read_CAN_OPSS2()                bfin_read16(CAN_OPSS2)
+#define bfin_write_CAN_OPSS2(val)            bfin_write16(CAN_OPSS2,val)
+
+#define bfin_read_CAN_CLOCK()                bfin_read16(CAN_CLOCK)
+#define bfin_write_CAN_CLOCK(val)            bfin_write16(CAN_CLOCK,val)
+#define bfin_read_CAN_TIMING()               bfin_read16(CAN_TIMING)
+#define bfin_write_CAN_TIMING(val)           bfin_write16(CAN_TIMING,val)
+#define bfin_read_CAN_DEBUG()                bfin_read16(CAN_DEBUG)
+#define bfin_write_CAN_DEBUG(val)            bfin_write16(CAN_DEBUG,val)
+#define bfin_read_CAN_STATUS()               bfin_read16(CAN_STATUS)
+#define bfin_write_CAN_STATUS(val)           bfin_write16(CAN_STATUS,val)
+#define bfin_read_CAN_CEC()                  bfin_read16(CAN_CEC)
+#define bfin_write_CAN_CEC(val)              bfin_write16(CAN_CEC,val)
+#define bfin_read_CAN_GIS()                  bfin_read16(CAN_GIS)
+#define bfin_write_CAN_GIS(val)              bfin_write16(CAN_GIS,val)
+#define bfin_read_CAN_GIM()                  bfin_read16(CAN_GIM)
+#define bfin_write_CAN_GIM(val)              bfin_write16(CAN_GIM,val)
+#define bfin_read_CAN_GIF()                  bfin_read16(CAN_GIF)
+#define bfin_write_CAN_GIF(val)              bfin_write16(CAN_GIF,val)
+#define bfin_read_CAN_CONTROL()              bfin_read16(CAN_CONTROL)
+#define bfin_write_CAN_CONTROL(val)          bfin_write16(CAN_CONTROL,val)
+#define bfin_read_CAN_INTR()                 bfin_read16(CAN_INTR)
+#define bfin_write_CAN_INTR(val)             bfin_write16(CAN_INTR,val)
+#define bfin_read_CAN_SFCMVER()              bfin_read16(CAN_SFCMVER)
+#define bfin_write_CAN_SFCMVER(val)          bfin_write16(CAN_SFCMVER,val)
+#define bfin_read_CAN_MBTD()                 bfin_read16(CAN_MBTD)
+#define bfin_write_CAN_MBTD(val)             bfin_write16(CAN_MBTD,val)
+#define bfin_read_CAN_EWR()                  bfin_read16(CAN_EWR)
+#define bfin_write_CAN_EWR(val)              bfin_write16(CAN_EWR,val)
+#define bfin_read_CAN_ESR()                  bfin_read16(CAN_ESR)
+#define bfin_write_CAN_ESR(val)              bfin_write16(CAN_ESR,val)
+#define bfin_read_CAN_UCREG()                bfin_read16(CAN_UCREG)
+#define bfin_write_CAN_UCREG(val)            bfin_write16(CAN_UCREG,val)
+#define bfin_read_CAN_UCCNT()                bfin_read16(CAN_UCCNT)
+#define bfin_write_CAN_UCCNT(val)            bfin_write16(CAN_UCCNT,val)
+#define bfin_read_CAN_UCRC()                 bfin_read16(CAN_UCRC)
+#define bfin_write_CAN_UCRC(val)             bfin_write16(CAN_UCRC,val)
+#define bfin_read_CAN_UCCNF()                bfin_read16(CAN_UCCNF)
+#define bfin_write_CAN_UCCNF(val)            bfin_write16(CAN_UCCNF,val)
+#define bfin_read_CAN_SFCMVER2()             bfin_read16(CAN_SFCMVER2)
+#define bfin_write_CAN_SFCMVER2(val)         bfin_write16(CAN_SFCMVER2,val)
+
+/* Mailbox Acceptance Masks */
+#define bfin_read_CAN_AM00L()                bfin_read16(CAN_AM00L)
+#define bfin_write_CAN_AM00L(val)            bfin_write16(CAN_AM00L,val)
+#define bfin_read_CAN_AM00H()                bfin_read16(CAN_AM00H)
+#define bfin_write_CAN_AM00H(val)            bfin_write16(CAN_AM00H,val)
+#define bfin_read_CAN_AM01L()                bfin_read16(CAN_AM01L)
+#define bfin_write_CAN_AM01L(val)            bfin_write16(CAN_AM01L,val)
+#define bfin_read_CAN_AM01H()                bfin_read16(CAN_AM01H)
+#define bfin_write_CAN_AM01H(val)            bfin_write16(CAN_AM01H,val)
+#define bfin_read_CAN_AM02L()                bfin_read16(CAN_AM02L)
+#define bfin_write_CAN_AM02L(val)            bfin_write16(CAN_AM02L,val)
+#define bfin_read_CAN_AM02H()                bfin_read16(CAN_AM02H)
+#define bfin_write_CAN_AM02H(val)            bfin_write16(CAN_AM02H,val)
+#define bfin_read_CAN_AM03L()                bfin_read16(CAN_AM03L)
+#define bfin_write_CAN_AM03L(val)            bfin_write16(CAN_AM03L,val)
+#define bfin_read_CAN_AM03H()                bfin_read16(CAN_AM03H)
+#define bfin_write_CAN_AM03H(val)            bfin_write16(CAN_AM03H,val)
+#define bfin_read_CAN_AM04L()                bfin_read16(CAN_AM04L)
+#define bfin_write_CAN_AM04L(val)            bfin_write16(CAN_AM04L,val)
+#define bfin_read_CAN_AM04H()                bfin_read16(CAN_AM04H)
+#define bfin_write_CAN_AM04H(val)            bfin_write16(CAN_AM04H,val)
+#define bfin_read_CAN_AM05L()                bfin_read16(CAN_AM05L)
+#define bfin_write_CAN_AM05L(val)            bfin_write16(CAN_AM05L,val)
+#define bfin_read_CAN_AM05H()                bfin_read16(CAN_AM05H)
+#define bfin_write_CAN_AM05H(val)            bfin_write16(CAN_AM05H,val)
+#define bfin_read_CAN_AM06L()                bfin_read16(CAN_AM06L)
+#define bfin_write_CAN_AM06L(val)            bfin_write16(CAN_AM06L,val)
+#define bfin_read_CAN_AM06H()                bfin_read16(CAN_AM06H)
+#define bfin_write_CAN_AM06H(val)            bfin_write16(CAN_AM06H,val)
+#define bfin_read_CAN_AM07L()                bfin_read16(CAN_AM07L)
+#define bfin_write_CAN_AM07L(val)            bfin_write16(CAN_AM07L,val)
+#define bfin_read_CAN_AM07H()                bfin_read16(CAN_AM07H)
+#define bfin_write_CAN_AM07H(val)            bfin_write16(CAN_AM07H,val)
+#define bfin_read_CAN_AM08L()                bfin_read16(CAN_AM08L)
+#define bfin_write_CAN_AM08L(val)            bfin_write16(CAN_AM08L,val)
+#define bfin_read_CAN_AM08H()                bfin_read16(CAN_AM08H)
+#define bfin_write_CAN_AM08H(val)            bfin_write16(CAN_AM08H,val)
+#define bfin_read_CAN_AM09L()                bfin_read16(CAN_AM09L)
+#define bfin_write_CAN_AM09L(val)            bfin_write16(CAN_AM09L,val)
+#define bfin_read_CAN_AM09H()                bfin_read16(CAN_AM09H)
+#define bfin_write_CAN_AM09H(val)            bfin_write16(CAN_AM09H,val)
+#define bfin_read_CAN_AM10L()                bfin_read16(CAN_AM10L)
+#define bfin_write_CAN_AM10L(val)            bfin_write16(CAN_AM10L,val)
+#define bfin_read_CAN_AM10H()                bfin_read16(CAN_AM10H)
+#define bfin_write_CAN_AM10H(val)            bfin_write16(CAN_AM10H,val)
+#define bfin_read_CAN_AM11L()                bfin_read16(CAN_AM11L)
+#define bfin_write_CAN_AM11L(val)            bfin_write16(CAN_AM11L,val)
+#define bfin_read_CAN_AM11H()                bfin_read16(CAN_AM11H)
+#define bfin_write_CAN_AM11H(val)            bfin_write16(CAN_AM11H,val)
+#define bfin_read_CAN_AM12L()                bfin_read16(CAN_AM12L)
+#define bfin_write_CAN_AM12L(val)            bfin_write16(CAN_AM12L,val)
+#define bfin_read_CAN_AM12H()                bfin_read16(CAN_AM12H)
+#define bfin_write_CAN_AM12H(val)            bfin_write16(CAN_AM12H,val)
+#define bfin_read_CAN_AM13L()                bfin_read16(CAN_AM13L)
+#define bfin_write_CAN_AM13L(val)            bfin_write16(CAN_AM13L,val)
+#define bfin_read_CAN_AM13H()                bfin_read16(CAN_AM13H)
+#define bfin_write_CAN_AM13H(val)            bfin_write16(CAN_AM13H,val)
+#define bfin_read_CAN_AM14L()                bfin_read16(CAN_AM14L)
+#define bfin_write_CAN_AM14L(val)            bfin_write16(CAN_AM14L,val)
+#define bfin_read_CAN_AM14H()                bfin_read16(CAN_AM14H)
+#define bfin_write_CAN_AM14H(val)            bfin_write16(CAN_AM14H,val)
+#define bfin_read_CAN_AM15L()                bfin_read16(CAN_AM15L)
+#define bfin_write_CAN_AM15L(val)            bfin_write16(CAN_AM15L,val)
+#define bfin_read_CAN_AM15H()                bfin_read16(CAN_AM15H)
+#define bfin_write_CAN_AM15H(val)            bfin_write16(CAN_AM15H,val)
+
+#define bfin_read_CAN_AM16L()                bfin_read16(CAN_AM16L)
+#define bfin_write_CAN_AM16L(val)            bfin_write16(CAN_AM16L,val)
+#define bfin_read_CAN_AM16H()                bfin_read16(CAN_AM16H)
+#define bfin_write_CAN_AM16H(val)            bfin_write16(CAN_AM16H,val)
+#define bfin_read_CAN_AM17L()                bfin_read16(CAN_AM17L)
+#define bfin_write_CAN_AM17L(val)            bfin_write16(CAN_AM17L,val)
+#define bfin_read_CAN_AM17H()                bfin_read16(CAN_AM17H)
+#define bfin_write_CAN_AM17H(val)            bfin_write16(CAN_AM17H,val)
+#define bfin_read_CAN_AM18L()                bfin_read16(CAN_AM18L)
+#define bfin_write_CAN_AM18L(val)            bfin_write16(CAN_AM18L,val)
+#define bfin_read_CAN_AM18H()                bfin_read16(CAN_AM18H)
+#define bfin_write_CAN_AM18H(val)            bfin_write16(CAN_AM18H,val)
+#define bfin_read_CAN_AM19L()                bfin_read16(CAN_AM19L)
+#define bfin_write_CAN_AM19L(val)            bfin_write16(CAN_AM19L,val)
+#define bfin_read_CAN_AM19H()                bfin_read16(CAN_AM19H)
+#define bfin_write_CAN_AM19H(val)            bfin_write16(CAN_AM19H,val)
+#define bfin_read_CAN_AM20L()                bfin_read16(CAN_AM20L)
+#define bfin_write_CAN_AM20L(val)            bfin_write16(CAN_AM20L,val)
+#define bfin_read_CAN_AM20H()                bfin_read16(CAN_AM20H)
+#define bfin_write_CAN_AM20H(val)            bfin_write16(CAN_AM20H,val)
+#define bfin_read_CAN_AM21L()                bfin_read16(CAN_AM21L)
+#define bfin_write_CAN_AM21L(val)            bfin_write16(CAN_AM21L,val)
+#define bfin_read_CAN_AM21H()                bfin_read16(CAN_AM21H)
+#define bfin_write_CAN_AM21H(val)            bfin_write16(CAN_AM21H,val)
+#define bfin_read_CAN_AM22L()                bfin_read16(CAN_AM22L)
+#define bfin_write_CAN_AM22L(val)            bfin_write16(CAN_AM22L,val)
+#define bfin_read_CAN_AM22H()                bfin_read16(CAN_AM22H)
+#define bfin_write_CAN_AM22H(val)            bfin_write16(CAN_AM22H,val)
+#define bfin_read_CAN_AM23L()                bfin_read16(CAN_AM23L)
+#define bfin_write_CAN_AM23L(val)            bfin_write16(CAN_AM23L,val)
+#define bfin_read_CAN_AM23H()                bfin_read16(CAN_AM23H)
+#define bfin_write_CAN_AM23H(val)            bfin_write16(CAN_AM23H,val)
+#define bfin_read_CAN_AM24L()                bfin_read16(CAN_AM24L)
+#define bfin_write_CAN_AM24L(val)            bfin_write16(CAN_AM24L,val)
+#define bfin_read_CAN_AM24H()                bfin_read16(CAN_AM24H)
+#define bfin_write_CAN_AM24H(val)            bfin_write16(CAN_AM24H,val)
+#define bfin_read_CAN_AM25L()                bfin_read16(CAN_AM25L)
+#define bfin_write_CAN_AM25L(val)            bfin_write16(CAN_AM25L,val)
+#define bfin_read_CAN_AM25H()                bfin_read16(CAN_AM25H)
+#define bfin_write_CAN_AM25H(val)            bfin_write16(CAN_AM25H,val)
+#define bfin_read_CAN_AM26L()                bfin_read16(CAN_AM26L)
+#define bfin_write_CAN_AM26L(val)            bfin_write16(CAN_AM26L,val)
+#define bfin_read_CAN_AM26H()                bfin_read16(CAN_AM26H)
+#define bfin_write_CAN_AM26H(val)            bfin_write16(CAN_AM26H,val)
+#define bfin_read_CAN_AM27L()                bfin_read16(CAN_AM27L)
+#define bfin_write_CAN_AM27L(val)            bfin_write16(CAN_AM27L,val)
+#define bfin_read_CAN_AM27H()                bfin_read16(CAN_AM27H)
+#define bfin_write_CAN_AM27H(val)            bfin_write16(CAN_AM27H,val)
+#define bfin_read_CAN_AM28L()                bfin_read16(CAN_AM28L)
+#define bfin_write_CAN_AM28L(val)            bfin_write16(CAN_AM28L,val)
+#define bfin_read_CAN_AM28H()                bfin_read16(CAN_AM28H)
+#define bfin_write_CAN_AM28H(val)            bfin_write16(CAN_AM28H,val)
+#define bfin_read_CAN_AM29L()                bfin_read16(CAN_AM29L)
+#define bfin_write_CAN_AM29L(val)            bfin_write16(CAN_AM29L,val)
+#define bfin_read_CAN_AM29H()                bfin_read16(CAN_AM29H)
+#define bfin_write_CAN_AM29H(val)            bfin_write16(CAN_AM29H,val)
+#define bfin_read_CAN_AM30L()                bfin_read16(CAN_AM30L)
+#define bfin_write_CAN_AM30L(val)            bfin_write16(CAN_AM30L,val)
+#define bfin_read_CAN_AM30H()                bfin_read16(CAN_AM30H)
+#define bfin_write_CAN_AM30H(val)            bfin_write16(CAN_AM30H,val)
+#define bfin_read_CAN_AM31L()                bfin_read16(CAN_AM31L)
+#define bfin_write_CAN_AM31L(val)            bfin_write16(CAN_AM31L,val)
+#define bfin_read_CAN_AM31H()                bfin_read16(CAN_AM31H)
+#define bfin_write_CAN_AM31H(val)            bfin_write16(CAN_AM31H,val)
+
+/* CAN Acceptance Mask Area Macros      */
+#define bfin_read_CAN_AM_L(x)()              bfin_read16(CAN_AM_L(x))
+#define bfin_write_CAN_AM_L(x)(val)          bfin_write16(CAN_AM_L(x),val)
+#define bfin_read_CAN_AM_H(x)()              bfin_read16(CAN_AM_H(x))
+#define bfin_write_CAN_AM_H(x)(val)          bfin_write16(CAN_AM_H(x),val)
+
+/* Mailbox Registers */
+#define bfin_read_CAN_MB00_ID1()             bfin_read16(CAN_MB00_ID1)
+#define bfin_write_CAN_MB00_ID1(val)         bfin_write16(CAN_MB00_ID1,val)
+#define bfin_read_CAN_MB00_ID0()             bfin_read16(CAN_MB00_ID0)
+#define bfin_write_CAN_MB00_ID0(val)         bfin_write16(CAN_MB00_ID0,val)
+#define bfin_read_CAN_MB00_TIMESTAMP()       bfin_read16(CAN_MB00_TIMESTAMP)
+#define bfin_write_CAN_MB00_TIMESTAMP(val)   bfin_write16(CAN_MB00_TIMESTAMP,val)
+#define bfin_read_CAN_MB00_LENGTH()          bfin_read16(CAN_MB00_LENGTH)
+#define bfin_write_CAN_MB00_LENGTH(val)      bfin_write16(CAN_MB00_LENGTH,val)
+#define bfin_read_CAN_MB00_DATA3()           bfin_read16(CAN_MB00_DATA3)
+#define bfin_write_CAN_MB00_DATA3(val)       bfin_write16(CAN_MB00_DATA3,val)
+#define bfin_read_CAN_MB00_DATA2()           bfin_read16(CAN_MB00_DATA2)
+#define bfin_write_CAN_MB00_DATA2(val)       bfin_write16(CAN_MB00_DATA2,val)
+#define bfin_read_CAN_MB00_DATA1()           bfin_read16(CAN_MB00_DATA1)
+#define bfin_write_CAN_MB00_DATA1(val)       bfin_write16(CAN_MB00_DATA1,val)
+#define bfin_read_CAN_MB00_DATA0()           bfin_read16(CAN_MB00_DATA0)
+#define bfin_write_CAN_MB00_DATA0(val)       bfin_write16(CAN_MB00_DATA0,val)
+
+#define bfin_read_CAN_MB01_ID1()             bfin_read16(CAN_MB01_ID1)
+#define bfin_write_CAN_MB01_ID1(val)         bfin_write16(CAN_MB01_ID1,val)
+#define bfin_read_CAN_MB01_ID0()             bfin_read16(CAN_MB01_ID0)
+#define bfin_write_CAN_MB01_ID0(val)         bfin_write16(CAN_MB01_ID0,val)
+#define bfin_read_CAN_MB01_TIMESTAMP()       bfin_read16(CAN_MB01_TIMESTAMP)
+#define bfin_write_CAN_MB01_TIMESTAMP(val)   bfin_write16(CAN_MB01_TIMESTAMP,val)
+#define bfin_read_CAN_MB01_LENGTH()          bfin_read16(CAN_MB01_LENGTH)
+#define bfin_write_CAN_MB01_LENGTH(val)      bfin_write16(CAN_MB01_LENGTH,val)
+#define bfin_read_CAN_MB01_DATA3()           bfin_read16(CAN_MB01_DATA3)
+#define bfin_write_CAN_MB01_DATA3(val)       bfin_write16(CAN_MB01_DATA3,val)
+#define bfin_read_CAN_MB01_DATA2()           bfin_read16(CAN_MB01_DATA2)
+#define bfin_write_CAN_MB01_DATA2(val)       bfin_write16(CAN_MB01_DATA2,val)
+#define bfin_read_CAN_MB01_DATA1()           bfin_read16(CAN_MB01_DATA1)
+#define bfin_write_CAN_MB01_DATA1(val)       bfin_write16(CAN_MB01_DATA1,val)
+#define bfin_read_CAN_MB01_DATA0()           bfin_read16(CAN_MB01_DATA0)
+#define bfin_write_CAN_MB01_DATA0(val)       bfin_write16(CAN_MB01_DATA0,val)
+
+#define bfin_read_CAN_MB02_ID1()             bfin_read16(CAN_MB02_ID1)
+#define bfin_write_CAN_MB02_ID1(val)         bfin_write16(CAN_MB02_ID1,val)
+#define bfin_read_CAN_MB02_ID0()             bfin_read16(CAN_MB02_ID0)
+#define bfin_write_CAN_MB02_ID0(val)         bfin_write16(CAN_MB02_ID0,val)
+#define bfin_read_CAN_MB02_TIMESTAMP()       bfin_read16(CAN_MB02_TIMESTAMP)
+#define bfin_write_CAN_MB02_TIMESTAMP(val)   bfin_write16(CAN_MB02_TIMESTAMP,val)
+#define bfin_read_CAN_MB02_LENGTH()          bfin_read16(CAN_MB02_LENGTH)
+#define bfin_write_CAN_MB02_LENGTH(val)      bfin_write16(CAN_MB02_LENGTH,val)
+#define bfin_read_CAN_MB02_DATA3()           bfin_read16(CAN_MB02_DATA3)
+#define bfin_write_CAN_MB02_DATA3(val)       bfin_write16(CAN_MB02_DATA3,val)
+#define bfin_read_CAN_MB02_DATA2()           bfin_read16(CAN_MB02_DATA2)
+#define bfin_write_CAN_MB02_DATA2(val)       bfin_write16(CAN_MB02_DATA2,val)
+#define bfin_read_CAN_MB02_DATA1()           bfin_read16(CAN_MB02_DATA1)
+#define bfin_write_CAN_MB02_DATA1(val)       bfin_write16(CAN_MB02_DATA1,val)
+#define bfin_read_CAN_MB02_DATA0()           bfin_read16(CAN_MB02_DATA0)
+#define bfin_write_CAN_MB02_DATA0(val)       bfin_write16(CAN_MB02_DATA0,val)
+
+#define bfin_read_CAN_MB03_ID1()             bfin_read16(CAN_MB03_ID1)
+#define bfin_write_CAN_MB03_ID1(val)         bfin_write16(CAN_MB03_ID1,val)
+#define bfin_read_CAN_MB03_ID0()             bfin_read16(CAN_MB03_ID0)
+#define bfin_write_CAN_MB03_ID0(val)         bfin_write16(CAN_MB03_ID0,val)
+#define bfin_read_CAN_MB03_TIMESTAMP()       bfin_read16(CAN_MB03_TIMESTAMP)
+#define bfin_write_CAN_MB03_TIMESTAMP(val)   bfin_write16(CAN_MB03_TIMESTAMP,val)
+#define bfin_read_CAN_MB03_LENGTH()          bfin_read16(CAN_MB03_LENGTH)
+#define bfin_write_CAN_MB03_LENGTH(val)      bfin_write16(CAN_MB03_LENGTH,val)
+#define bfin_read_CAN_MB03_DATA3()           bfin_read16(CAN_MB03_DATA3)
+#define bfin_write_CAN_MB03_DATA3(val)       bfin_write16(CAN_MB03_DATA3,val)
+#define bfin_read_CAN_MB03_DATA2()           bfin_read16(CAN_MB03_DATA2)
+#define bfin_write_CAN_MB03_DATA2(val)       bfin_write16(CAN_MB03_DATA2,val)
+#define bfin_read_CAN_MB03_DATA1()           bfin_read16(CAN_MB03_DATA1)
+#define bfin_write_CAN_MB03_DATA1(val)       bfin_write16(CAN_MB03_DATA1,val)
+#define bfin_read_CAN_MB03_DATA0()           bfin_read16(CAN_MB03_DATA0)
+#define bfin_write_CAN_MB03_DATA0(val)       bfin_write16(CAN_MB03_DATA0,val)
+
+#define bfin_read_CAN_MB04_ID1()             bfin_read16(CAN_MB04_ID1)
+#define bfin_write_CAN_MB04_ID1(val)         bfin_write16(CAN_MB04_ID1,val)
+#define bfin_read_CAN_MB04_ID0()             bfin_read16(CAN_MB04_ID0)
+#define bfin_write_CAN_MB04_ID0(val)         bfin_write16(CAN_MB04_ID0,val)
+#define bfin_read_CAN_MB04_TIMESTAMP()       bfin_read16(CAN_MB04_TIMESTAMP)
+#define bfin_write_CAN_MB04_TIMESTAMP(val)   bfin_write16(CAN_MB04_TIMESTAMP,val)
+#define bfin_read_CAN_MB04_LENGTH()          bfin_read16(CAN_MB04_LENGTH)
+#define bfin_write_CAN_MB04_LENGTH(val)      bfin_write16(CAN_MB04_LENGTH,val)
+#define bfin_read_CAN_MB04_DATA3()           bfin_read16(CAN_MB04_DATA3)
+#define bfin_write_CAN_MB04_DATA3(val)       bfin_write16(CAN_MB04_DATA3,val)
+#define bfin_read_CAN_MB04_DATA2()           bfin_read16(CAN_MB04_DATA2)
+#define bfin_write_CAN_MB04_DATA2(val)       bfin_write16(CAN_MB04_DATA2,val)
+#define bfin_read_CAN_MB04_DATA1()           bfin_read16(CAN_MB04_DATA1)
+#define bfin_write_CAN_MB04_DATA1(val)       bfin_write16(CAN_MB04_DATA1,val)
+#define bfin_read_CAN_MB04_DATA0()           bfin_read16(CAN_MB04_DATA0)
+#define bfin_write_CAN_MB04_DATA0(val)       bfin_write16(CAN_MB04_DATA0,val)
+
+#define bfin_read_CAN_MB05_ID1()             bfin_read16(CAN_MB05_ID1)
+#define bfin_write_CAN_MB05_ID1(val)         bfin_write16(CAN_MB05_ID1,val)
+#define bfin_read_CAN_MB05_ID0()             bfin_read16(CAN_MB05_ID0)
+#define bfin_write_CAN_MB05_ID0(val)         bfin_write16(CAN_MB05_ID0,val)
+#define bfin_read_CAN_MB05_TIMESTAMP()       bfin_read16(CAN_MB05_TIMESTAMP)
+#define bfin_write_CAN_MB05_TIMESTAMP(val)   bfin_write16(CAN_MB05_TIMESTAMP,val)
+#define bfin_read_CAN_MB05_LENGTH()          bfin_read16(CAN_MB05_LENGTH)
+#define bfin_write_CAN_MB05_LENGTH(val)      bfin_write16(CAN_MB05_LENGTH,val)
+#define bfin_read_CAN_MB05_DATA3()           bfin_read16(CAN_MB05_DATA3)
+#define bfin_write_CAN_MB05_DATA3(val)       bfin_write16(CAN_MB05_DATA3,val)
+#define bfin_read_CAN_MB05_DATA2()           bfin_read16(CAN_MB05_DATA2)
+#define bfin_write_CAN_MB05_DATA2(val)       bfin_write16(CAN_MB05_DATA2,val)
+#define bfin_read_CAN_MB05_DATA1()           bfin_read16(CAN_MB05_DATA1)
+#define bfin_write_CAN_MB05_DATA1(val)       bfin_write16(CAN_MB05_DATA1,val)
+#define bfin_read_CAN_MB05_DATA0()           bfin_read16(CAN_MB05_DATA0)
+#define bfin_write_CAN_MB05_DATA0(val)       bfin_write16(CAN_MB05_DATA0,val)
+
+#define bfin_read_CAN_MB06_ID1()             bfin_read16(CAN_MB06_ID1)
+#define bfin_write_CAN_MB06_ID1(val)         bfin_write16(CAN_MB06_ID1,val)
+#define bfin_read_CAN_MB06_ID0()             bfin_read16(CAN_MB06_ID0)
+#define bfin_write_CAN_MB06_ID0(val)         bfin_write16(CAN_MB06_ID0,val)
+#define bfin_read_CAN_MB06_TIMESTAMP()       bfin_read16(CAN_MB06_TIMESTAMP)
+#define bfin_write_CAN_MB06_TIMESTAMP(val)   bfin_write16(CAN_MB06_TIMESTAMP,val)
+#define bfin_read_CAN_MB06_LENGTH()          bfin_read16(CAN_MB06_LENGTH)
+#define bfin_write_CAN_MB06_LENGTH(val)      bfin_write16(CAN_MB06_LENGTH,val)
+#define bfin_read_CAN_MB06_DATA3()           bfin_read16(CAN_MB06_DATA3)
+#define bfin_write_CAN_MB06_DATA3(val)       bfin_write16(CAN_MB06_DATA3,val)
+#define bfin_read_CAN_MB06_DATA2()           bfin_read16(CAN_MB06_DATA2)
+#define bfin_write_CAN_MB06_DATA2(val)       bfin_write16(CAN_MB06_DATA2,val)
+#define bfin_read_CAN_MB06_DATA1()           bfin_read16(CAN_MB06_DATA1)
+#define bfin_write_CAN_MB06_DATA1(val)       bfin_write16(CAN_MB06_DATA1,val)
+#define bfin_read_CAN_MB06_DATA0()           bfin_read16(CAN_MB06_DATA0)
+#define bfin_write_CAN_MB06_DATA0(val)       bfin_write16(CAN_MB06_DATA0,val)
+
+#define bfin_read_CAN_MB07_ID1()             bfin_read16(CAN_MB07_ID1)
+#define bfin_write_CAN_MB07_ID1(val)         bfin_write16(CAN_MB07_ID1,val)
+#define bfin_read_CAN_MB07_ID0()             bfin_read16(CAN_MB07_ID0)
+#define bfin_write_CAN_MB07_ID0(val)         bfin_write16(CAN_MB07_ID0,val)
+#define bfin_read_CAN_MB07_TIMESTAMP()       bfin_read16(CAN_MB07_TIMESTAMP)
+#define bfin_write_CAN_MB07_TIMESTAMP(val)   bfin_write16(CAN_MB07_TIMESTAMP,val)
+#define bfin_read_CAN_MB07_LENGTH()          bfin_read16(CAN_MB07_LENGTH)
+#define bfin_write_CAN_MB07_LENGTH(val)      bfin_write16(CAN_MB07_LENGTH,val)
+#define bfin_read_CAN_MB07_DATA3()           bfin_read16(CAN_MB07_DATA3)
+#define bfin_write_CAN_MB07_DATA3(val)       bfin_write16(CAN_MB07_DATA3,val)
+#define bfin_read_CAN_MB07_DATA2()           bfin_read16(CAN_MB07_DATA2)
+#define bfin_write_CAN_MB07_DATA2(val)       bfin_write16(CAN_MB07_DATA2,val)
+#define bfin_read_CAN_MB07_DATA1()           bfin_read16(CAN_MB07_DATA1)
+#define bfin_write_CAN_MB07_DATA1(val)       bfin_write16(CAN_MB07_DATA1,val)
+#define bfin_read_CAN_MB07_DATA0()           bfin_read16(CAN_MB07_DATA0)
+#define bfin_write_CAN_MB07_DATA0(val)       bfin_write16(CAN_MB07_DATA0,val)
+
+#define bfin_read_CAN_MB08_ID1()             bfin_read16(CAN_MB08_ID1)
+#define bfin_write_CAN_MB08_ID1(val)         bfin_write16(CAN_MB08_ID1,val)
+#define bfin_read_CAN_MB08_ID0()             bfin_read16(CAN_MB08_ID0)
+#define bfin_write_CAN_MB08_ID0(val)         bfin_write16(CAN_MB08_ID0,val)
+#define bfin_read_CAN_MB08_TIMESTAMP()       bfin_read16(CAN_MB08_TIMESTAMP)
+#define bfin_write_CAN_MB08_TIMESTAMP(val)   bfin_write16(CAN_MB08_TIMESTAMP,val)
+#define bfin_read_CAN_MB08_LENGTH()          bfin_read16(CAN_MB08_LENGTH)
+#define bfin_write_CAN_MB08_LENGTH(val)      bfin_write16(CAN_MB08_LENGTH,val)
+#define bfin_read_CAN_MB08_DATA3()           bfin_read16(CAN_MB08_DATA3)
+#define bfin_write_CAN_MB08_DATA3(val)       bfin_write16(CAN_MB08_DATA3,val)
+#define bfin_read_CAN_MB08_DATA2()           bfin_read16(CAN_MB08_DATA2)
+#define bfin_write_CAN_MB08_DATA2(val)       bfin_write16(CAN_MB08_DATA2,val)
+#define bfin_read_CAN_MB08_DATA1()           bfin_read16(CAN_MB08_DATA1)
+#define bfin_write_CAN_MB08_DATA1(val)       bfin_write16(CAN_MB08_DATA1,val)
+#define bfin_read_CAN_MB08_DATA0()           bfin_read16(CAN_MB08_DATA0)
+#define bfin_write_CAN_MB08_DATA0(val)       bfin_write16(CAN_MB08_DATA0,val)
+
+#define bfin_read_CAN_MB09_ID1()             bfin_read16(CAN_MB09_ID1)
+#define bfin_write_CAN_MB09_ID1(val)         bfin_write16(CAN_MB09_ID1,val)
+#define bfin_read_CAN_MB09_ID0()             bfin_read16(CAN_MB09_ID0)
+#define bfin_write_CAN_MB09_ID0(val)         bfin_write16(CAN_MB09_ID0,val)
+#define bfin_read_CAN_MB09_TIMESTAMP()       bfin_read16(CAN_MB09_TIMESTAMP)
+#define bfin_write_CAN_MB09_TIMESTAMP(val)   bfin_write16(CAN_MB09_TIMESTAMP,val)
+#define bfin_read_CAN_MB09_LENGTH()          bfin_read16(CAN_MB09_LENGTH)
+#define bfin_write_CAN_MB09_LENGTH(val)      bfin_write16(CAN_MB09_LENGTH,val)
+#define bfin_read_CAN_MB09_DATA3()           bfin_read16(CAN_MB09_DATA3)
+#define bfin_write_CAN_MB09_DATA3(val)       bfin_write16(CAN_MB09_DATA3,val)
+#define bfin_read_CAN_MB09_DATA2()           bfin_read16(CAN_MB09_DATA2)
+#define bfin_write_CAN_MB09_DATA2(val)       bfin_write16(CAN_MB09_DATA2,val)
+#define bfin_read_CAN_MB09_DATA1()           bfin_read16(CAN_MB09_DATA1)
+#define bfin_write_CAN_MB09_DATA1(val)       bfin_write16(CAN_MB09_DATA1,val)
+#define bfin_read_CAN_MB09_DATA0()           bfin_read16(CAN_MB09_DATA0)
+#define bfin_write_CAN_MB09_DATA0(val)       bfin_write16(CAN_MB09_DATA0,val)
+
+#define bfin_read_CAN_MB10_ID1()             bfin_read16(CAN_MB10_ID1)
+#define bfin_write_CAN_MB10_ID1(val)         bfin_write16(CAN_MB10_ID1,val)
+#define bfin_read_CAN_MB10_ID0()             bfin_read16(CAN_MB10_ID0)
+#define bfin_write_CAN_MB10_ID0(val)         bfin_write16(CAN_MB10_ID0,val)
+#define bfin_read_CAN_MB10_TIMESTAMP()       bfin_read16(CAN_MB10_TIMESTAMP)
+#define bfin_write_CAN_MB10_TIMESTAMP(val)   bfin_write16(CAN_MB10_TIMESTAMP,val)
+#define bfin_read_CAN_MB10_LENGTH()          bfin_read16(CAN_MB10_LENGTH)
+#define bfin_write_CAN_MB10_LENGTH(val)      bfin_write16(CAN_MB10_LENGTH,val)
+#define bfin_read_CAN_MB10_DATA3()           bfin_read16(CAN_MB10_DATA3)
+#define bfin_write_CAN_MB10_DATA3(val)       bfin_write16(CAN_MB10_DATA3,val)
+#define bfin_read_CAN_MB10_DATA2()           bfin_read16(CAN_MB10_DATA2)
+#define bfin_write_CAN_MB10_DATA2(val)       bfin_write16(CAN_MB10_DATA2,val)
+#define bfin_read_CAN_MB10_DATA1()           bfin_read16(CAN_MB10_DATA1)
+#define bfin_write_CAN_MB10_DATA1(val)       bfin_write16(CAN_MB10_DATA1,val)
+#define bfin_read_CAN_MB10_DATA0()           bfin_read16(CAN_MB10_DATA0)
+#define bfin_write_CAN_MB10_DATA0(val)       bfin_write16(CAN_MB10_DATA0,val)
+
+#define bfin_read_CAN_MB11_ID1()             bfin_read16(CAN_MB11_ID1)
+#define bfin_write_CAN_MB11_ID1(val)         bfin_write16(CAN_MB11_ID1,val)
+#define bfin_read_CAN_MB11_ID0()             bfin_read16(CAN_MB11_ID0)
+#define bfin_write_CAN_MB11_ID0(val)         bfin_write16(CAN_MB11_ID0,val)
+#define bfin_read_CAN_MB11_TIMESTAMP()       bfin_read16(CAN_MB11_TIMESTAMP)
+#define bfin_write_CAN_MB11_TIMESTAMP(val)   bfin_write16(CAN_MB11_TIMESTAMP,val)
+#define bfin_read_CAN_MB11_LENGTH()          bfin_read16(CAN_MB11_LENGTH)
+#define bfin_write_CAN_MB11_LENGTH(val)      bfin_write16(CAN_MB11_LENGTH,val)
+#define bfin_read_CAN_MB11_DATA3()           bfin_read16(CAN_MB11_DATA3)
+#define bfin_write_CAN_MB11_DATA3(val)       bfin_write16(CAN_MB11_DATA3,val)
+#define bfin_read_CAN_MB11_DATA2()           bfin_read16(CAN_MB11_DATA2)
+#define bfin_write_CAN_MB11_DATA2(val)       bfin_write16(CAN_MB11_DATA2,val)
+#define bfin_read_CAN_MB11_DATA1()           bfin_read16(CAN_MB11_DATA1)
+#define bfin_write_CAN_MB11_DATA1(val)       bfin_write16(CAN_MB11_DATA1,val)
+#define bfin_read_CAN_MB11_DATA0()           bfin_read16(CAN_MB11_DATA0)
+#define bfin_write_CAN_MB11_DATA0(val)       bfin_write16(CAN_MB11_DATA0,val)
+
+#define bfin_read_CAN_MB12_ID1()             bfin_read16(CAN_MB12_ID1)
+#define bfin_write_CAN_MB12_ID1(val)         bfin_write16(CAN_MB12_ID1,val)
+#define bfin_read_CAN_MB12_ID0()             bfin_read16(CAN_MB12_ID0)
+#define bfin_write_CAN_MB12_ID0(val)         bfin_write16(CAN_MB12_ID0,val)
+#define bfin_read_CAN_MB12_TIMESTAMP()       bfin_read16(CAN_MB12_TIMESTAMP)
+#define bfin_write_CAN_MB12_TIMESTAMP(val)   bfin_write16(CAN_MB12_TIMESTAMP,val)
+#define bfin_read_CAN_MB12_LENGTH()          bfin_read16(CAN_MB12_LENGTH)
+#define bfin_write_CAN_MB12_LENGTH(val)      bfin_write16(CAN_MB12_LENGTH,val)
+#define bfin_read_CAN_MB12_DATA3()           bfin_read16(CAN_MB12_DATA3)
+#define bfin_write_CAN_MB12_DATA3(val)       bfin_write16(CAN_MB12_DATA3,val)
+#define bfin_read_CAN_MB12_DATA2()           bfin_read16(CAN_MB12_DATA2)
+#define bfin_write_CAN_MB12_DATA2(val)       bfin_write16(CAN_MB12_DATA2,val)
+#define bfin_read_CAN_MB12_DATA1()           bfin_read16(CAN_MB12_DATA1)
+#define bfin_write_CAN_MB12_DATA1(val)       bfin_write16(CAN_MB12_DATA1,val)
+#define bfin_read_CAN_MB12_DATA0()           bfin_read16(CAN_MB12_DATA0)
+#define bfin_write_CAN_MB12_DATA0(val)       bfin_write16(CAN_MB12_DATA0,val)
+
+#define bfin_read_CAN_MB13_ID1()             bfin_read16(CAN_MB13_ID1)
+#define bfin_write_CAN_MB13_ID1(val)         bfin_write16(CAN_MB13_ID1,val)
+#define bfin_read_CAN_MB13_ID0()             bfin_read16(CAN_MB13_ID0)
+#define bfin_write_CAN_MB13_ID0(val)         bfin_write16(CAN_MB13_ID0,val)
+#define bfin_read_CAN_MB13_TIMESTAMP()       bfin_read16(CAN_MB13_TIMESTAMP)
+#define bfin_write_CAN_MB13_TIMESTAMP(val)   bfin_write16(CAN_MB13_TIMESTAMP,val)
+#define bfin_read_CAN_MB13_LENGTH()          bfin_read16(CAN_MB13_LENGTH)
+#define bfin_write_CAN_MB13_LENGTH(val)      bfin_write16(CAN_MB13_LENGTH,val)
+#define bfin_read_CAN_MB13_DATA3()           bfin_read16(CAN_MB13_DATA3)
+#define bfin_write_CAN_MB13_DATA3(val)       bfin_write16(CAN_MB13_DATA3,val)
+#define bfin_read_CAN_MB13_DATA2()           bfin_read16(CAN_MB13_DATA2)
+#define bfin_write_CAN_MB13_DATA2(val)       bfin_write16(CAN_MB13_DATA2,val)
+#define bfin_read_CAN_MB13_DATA1()           bfin_read16(CAN_MB13_DATA1)
+#define bfin_write_CAN_MB13_DATA1(val)       bfin_write16(CAN_MB13_DATA1,val)
+#define bfin_read_CAN_MB13_DATA0()           bfin_read16(CAN_MB13_DATA0)
+#define bfin_write_CAN_MB13_DATA0(val)       bfin_write16(CAN_MB13_DATA0,val)
+
+#define bfin_read_CAN_MB14_ID1()             bfin_read16(CAN_MB14_ID1)
+#define bfin_write_CAN_MB14_ID1(val)         bfin_write16(CAN_MB14_ID1,val)
+#define bfin_read_CAN_MB14_ID0()             bfin_read16(CAN_MB14_ID0)
+#define bfin_write_CAN_MB14_ID0(val)         bfin_write16(CAN_MB14_ID0,val)
+#define bfin_read_CAN_MB14_TIMESTAMP()       bfin_read16(CAN_MB14_TIMESTAMP)
+#define bfin_write_CAN_MB14_TIMESTAMP(val)   bfin_write16(CAN_MB14_TIMESTAMP,val)
+#define bfin_read_CAN_MB14_LENGTH()          bfin_read16(CAN_MB14_LENGTH)
+#define bfin_write_CAN_MB14_LENGTH(val)      bfin_write16(CAN_MB14_LENGTH,val)
+#define bfin_read_CAN_MB14_DATA3()           bfin_read16(CAN_MB14_DATA3)
+#define bfin_write_CAN_MB14_DATA3(val)       bfin_write16(CAN_MB14_DATA3,val)
+#define bfin_read_CAN_MB14_DATA2()           bfin_read16(CAN_MB14_DATA2)
+#define bfin_write_CAN_MB14_DATA2(val)       bfin_write16(CAN_MB14_DATA2,val)
+#define bfin_read_CAN_MB14_DATA1()           bfin_read16(CAN_MB14_DATA1)
+#define bfin_write_CAN_MB14_DATA1(val)       bfin_write16(CAN_MB14_DATA1,val)
+#define bfin_read_CAN_MB14_DATA0()           bfin_read16(CAN_MB14_DATA0)
+#define bfin_write_CAN_MB14_DATA0(val)       bfin_write16(CAN_MB14_DATA0,val)
+
+#define bfin_read_CAN_MB15_ID1()             bfin_read16(CAN_MB15_ID1)
+#define bfin_write_CAN_MB15_ID1(val)         bfin_write16(CAN_MB15_ID1,val)
+#define bfin_read_CAN_MB15_ID0()             bfin_read16(CAN_MB15_ID0)
+#define bfin_write_CAN_MB15_ID0(val)         bfin_write16(CAN_MB15_ID0,val)
+#define bfin_read_CAN_MB15_TIMESTAMP()       bfin_read16(CAN_MB15_TIMESTAMP)
+#define bfin_write_CAN_MB15_TIMESTAMP(val)   bfin_write16(CAN_MB15_TIMESTAMP,val)
+#define bfin_read_CAN_MB15_LENGTH()          bfin_read16(CAN_MB15_LENGTH)
+#define bfin_write_CAN_MB15_LENGTH(val)      bfin_write16(CAN_MB15_LENGTH,val)
+#define bfin_read_CAN_MB15_DATA3()           bfin_read16(CAN_MB15_DATA3)
+#define bfin_write_CAN_MB15_DATA3(val)       bfin_write16(CAN_MB15_DATA3,val)
+#define bfin_read_CAN_MB15_DATA2()           bfin_read16(CAN_MB15_DATA2)
+#define bfin_write_CAN_MB15_DATA2(val)       bfin_write16(CAN_MB15_DATA2,val)
+#define bfin_read_CAN_MB15_DATA1()           bfin_read16(CAN_MB15_DATA1)
+#define bfin_write_CAN_MB15_DATA1(val)       bfin_write16(CAN_MB15_DATA1,val)
+#define bfin_read_CAN_MB15_DATA0()           bfin_read16(CAN_MB15_DATA0)
+#define bfin_write_CAN_MB15_DATA0(val)       bfin_write16(CAN_MB15_DATA0,val)
+
+#define bfin_read_CAN_MB16_ID1()             bfin_read16(CAN_MB16_ID1)
+#define bfin_write_CAN_MB16_ID1(val)         bfin_write16(CAN_MB16_ID1,val)
+#define bfin_read_CAN_MB16_ID0()             bfin_read16(CAN_MB16_ID0)
+#define bfin_write_CAN_MB16_ID0(val)         bfin_write16(CAN_MB16_ID0,val)
+#define bfin_read_CAN_MB16_TIMESTAMP()       bfin_read16(CAN_MB16_TIMESTAMP)
+#define bfin_write_CAN_MB16_TIMESTAMP(val)   bfin_write16(CAN_MB16_TIMESTAMP,val)
+#define bfin_read_CAN_MB16_LENGTH()          bfin_read16(CAN_MB16_LENGTH)
+#define bfin_write_CAN_MB16_LENGTH(val)      bfin_write16(CAN_MB16_LENGTH,val)
+#define bfin_read_CAN_MB16_DATA3()           bfin_read16(CAN_MB16_DATA3)
+#define bfin_write_CAN_MB16_DATA3(val)       bfin_write16(CAN_MB16_DATA3,val)
+#define bfin_read_CAN_MB16_DATA2()           bfin_read16(CAN_MB16_DATA2)
+#define bfin_write_CAN_MB16_DATA2(val)       bfin_write16(CAN_MB16_DATA2,val)
+#define bfin_read_CAN_MB16_DATA1()           bfin_read16(CAN_MB16_DATA1)
+#define bfin_write_CAN_MB16_DATA1(val)       bfin_write16(CAN_MB16_DATA1,val)
+#define bfin_read_CAN_MB16_DATA0()           bfin_read16(CAN_MB16_DATA0)
+#define bfin_write_CAN_MB16_DATA0(val)       bfin_write16(CAN_MB16_DATA0,val)
+
+#define bfin_read_CAN_MB17_ID1()             bfin_read16(CAN_MB17_ID1)
+#define bfin_write_CAN_MB17_ID1(val)         bfin_write16(CAN_MB17_ID1,val)
+#define bfin_read_CAN_MB17_ID0()             bfin_read16(CAN_MB17_ID0)
+#define bfin_write_CAN_MB17_ID0(val)         bfin_write16(CAN_MB17_ID0,val)
+#define bfin_read_CAN_MB17_TIMESTAMP()       bfin_read16(CAN_MB17_TIMESTAMP)
+#define bfin_write_CAN_MB17_TIMESTAMP(val)   bfin_write16(CAN_MB17_TIMESTAMP,val)
+#define bfin_read_CAN_MB17_LENGTH()          bfin_read16(CAN_MB17_LENGTH)
+#define bfin_write_CAN_MB17_LENGTH(val)      bfin_write16(CAN_MB17_LENGTH,val)
+#define bfin_read_CAN_MB17_DATA3()           bfin_read16(CAN_MB17_DATA3)
+#define bfin_write_CAN_MB17_DATA3(val)       bfin_write16(CAN_MB17_DATA3,val)
+#define bfin_read_CAN_MB17_DATA2()           bfin_read16(CAN_MB17_DATA2)
+#define bfin_write_CAN_MB17_DATA2(val)       bfin_write16(CAN_MB17_DATA2,val)
+#define bfin_read_CAN_MB17_DATA1()           bfin_read16(CAN_MB17_DATA1)
+#define bfin_write_CAN_MB17_DATA1(val)       bfin_write16(CAN_MB17_DATA1,val)
+#define bfin_read_CAN_MB17_DATA0()           bfin_read16(CAN_MB17_DATA0)
+#define bfin_write_CAN_MB17_DATA0(val)       bfin_write16(CAN_MB17_DATA0,val)
+
+#define bfin_read_CAN_MB18_ID1()             bfin_read16(CAN_MB18_ID1)
+#define bfin_write_CAN_MB18_ID1(val)         bfin_write16(CAN_MB18_ID1,val)
+#define bfin_read_CAN_MB18_ID0()             bfin_read16(CAN_MB18_ID0)
+#define bfin_write_CAN_MB18_ID0(val)         bfin_write16(CAN_MB18_ID0,val)
+#define bfin_read_CAN_MB18_TIMESTAMP()       bfin_read16(CAN_MB18_TIMESTAMP)
+#define bfin_write_CAN_MB18_TIMESTAMP(val)   bfin_write16(CAN_MB18_TIMESTAMP,val)
+#define bfin_read_CAN_MB18_LENGTH()          bfin_read16(CAN_MB18_LENGTH)
+#define bfin_write_CAN_MB18_LENGTH(val)      bfin_write16(CAN_MB18_LENGTH,val)
+#define bfin_read_CAN_MB18_DATA3()           bfin_read16(CAN_MB18_DATA3)
+#define bfin_write_CAN_MB18_DATA3(val)       bfin_write16(CAN_MB18_DATA3,val)
+#define bfin_read_CAN_MB18_DATA2()           bfin_read16(CAN_MB18_DATA2)
+#define bfin_write_CAN_MB18_DATA2(val)       bfin_write16(CAN_MB18_DATA2,val)
+#define bfin_read_CAN_MB18_DATA1()           bfin_read16(CAN_MB18_DATA1)
+#define bfin_write_CAN_MB18_DATA1(val)       bfin_write16(CAN_MB18_DATA1,val)
+#define bfin_read_CAN_MB18_DATA0()           bfin_read16(CAN_MB18_DATA0)
+#define bfin_write_CAN_MB18_DATA0(val)       bfin_write16(CAN_MB18_DATA0,val)
+
+#define bfin_read_CAN_MB19_ID1()             bfin_read16(CAN_MB19_ID1)
+#define bfin_write_CAN_MB19_ID1(val)         bfin_write16(CAN_MB19_ID1,val)
+#define bfin_read_CAN_MB19_ID0()             bfin_read16(CAN_MB19_ID0)
+#define bfin_write_CAN_MB19_ID0(val)         bfin_write16(CAN_MB19_ID0,val)
+#define bfin_read_CAN_MB19_TIMESTAMP()       bfin_read16(CAN_MB19_TIMESTAMP)
+#define bfin_write_CAN_MB19_TIMESTAMP(val)   bfin_write16(CAN_MB19_TIMESTAMP,val)
+#define bfin_read_CAN_MB19_LENGTH()          bfin_read16(CAN_MB19_LENGTH)
+#define bfin_write_CAN_MB19_LENGTH(val)      bfin_write16(CAN_MB19_LENGTH,val)
+#define bfin_read_CAN_MB19_DATA3()           bfin_read16(CAN_MB19_DATA3)
+#define bfin_write_CAN_MB19_DATA3(val)       bfin_write16(CAN_MB19_DATA3,val)
+#define bfin_read_CAN_MB19_DATA2()           bfin_read16(CAN_MB19_DATA2)
+#define bfin_write_CAN_MB19_DATA2(val)       bfin_write16(CAN_MB19_DATA2,val)
+#define bfin_read_CAN_MB19_DATA1()           bfin_read16(CAN_MB19_DATA1)
+#define bfin_write_CAN_MB19_DATA1(val)       bfin_write16(CAN_MB19_DATA1,val)
+#define bfin_read_CAN_MB19_DATA0()           bfin_read16(CAN_MB19_DATA0)
+#define bfin_write_CAN_MB19_DATA0(val)       bfin_write16(CAN_MB19_DATA0,val)
+
+#define bfin_read_CAN_MB20_ID1()             bfin_read16(CAN_MB20_ID1)
+#define bfin_write_CAN_MB20_ID1(val)         bfin_write16(CAN_MB20_ID1,val)
+#define bfin_read_CAN_MB20_ID0()             bfin_read16(CAN_MB20_ID0)
+#define bfin_write_CAN_MB20_ID0(val)         bfin_write16(CAN_MB20_ID0,val)
+#define bfin_read_CAN_MB20_TIMESTAMP()       bfin_read16(CAN_MB20_TIMESTAMP)
+#define bfin_write_CAN_MB20_TIMESTAMP(val)   bfin_write16(CAN_MB20_TIMESTAMP,val)
+#define bfin_read_CAN_MB20_LENGTH()          bfin_read16(CAN_MB20_LENGTH)
+#define bfin_write_CAN_MB20_LENGTH(val)      bfin_write16(CAN_MB20_LENGTH,val)
+#define bfin_read_CAN_MB20_DATA3()           bfin_read16(CAN_MB20_DATA3)
+#define bfin_write_CAN_MB20_DATA3(val)       bfin_write16(CAN_MB20_DATA3,val)
+#define bfin_read_CAN_MB20_DATA2()           bfin_read16(CAN_MB20_DATA2)
+#define bfin_write_CAN_MB20_DATA2(val)       bfin_write16(CAN_MB20_DATA2,val)
+#define bfin_read_CAN_MB20_DATA1()           bfin_read16(CAN_MB20_DATA1)
+#define bfin_write_CAN_MB20_DATA1(val)       bfin_write16(CAN_MB20_DATA1,val)
+#define bfin_read_CAN_MB20_DATA0()           bfin_read16(CAN_MB20_DATA0)
+#define bfin_write_CAN_MB20_DATA0(val)       bfin_write16(CAN_MB20_DATA0,val)
+
+#define bfin_read_CAN_MB21_ID1()             bfin_read16(CAN_MB21_ID1)
+#define bfin_write_CAN_MB21_ID1(val)         bfin_write16(CAN_MB21_ID1,val)
+#define bfin_read_CAN_MB21_ID0()             bfin_read16(CAN_MB21_ID0)
+#define bfin_write_CAN_MB21_ID0(val)         bfin_write16(CAN_MB21_ID0,val)
+#define bfin_read_CAN_MB21_TIMESTAMP()       bfin_read16(CAN_MB21_TIMESTAMP)
+#define bfin_write_CAN_MB21_TIMESTAMP(val)   bfin_write16(CAN_MB21_TIMESTAMP,val)
+#define bfin_read_CAN_MB21_LENGTH()          bfin_read16(CAN_MB21_LENGTH)
+#define bfin_write_CAN_MB21_LENGTH(val)      bfin_write16(CAN_MB21_LENGTH,val)
+#define bfin_read_CAN_MB21_DATA3()           bfin_read16(CAN_MB21_DATA3)
+#define bfin_write_CAN_MB21_DATA3(val)       bfin_write16(CAN_MB21_DATA3,val)
+#define bfin_read_CAN_MB21_DATA2()           bfin_read16(CAN_MB21_DATA2)
+#define bfin_write_CAN_MB21_DATA2(val)       bfin_write16(CAN_MB21_DATA2,val)
+#define bfin_read_CAN_MB21_DATA1()           bfin_read16(CAN_MB21_DATA1)
+#define bfin_write_CAN_MB21_DATA1(val)       bfin_write16(CAN_MB21_DATA1,val)
+#define bfin_read_CAN_MB21_DATA0()           bfin_read16(CAN_MB21_DATA0)
+#define bfin_write_CAN_MB21_DATA0(val)       bfin_write16(CAN_MB21_DATA0,val)
+
+#define bfin_read_CAN_MB22_ID1()             bfin_read16(CAN_MB22_ID1)
+#define bfin_write_CAN_MB22_ID1(val)         bfin_write16(CAN_MB22_ID1,val)
+#define bfin_read_CAN_MB22_ID0()             bfin_read16(CAN_MB22_ID0)
+#define bfin_write_CAN_MB22_ID0(val)         bfin_write16(CAN_MB22_ID0,val)
+#define bfin_read_CAN_MB22_TIMESTAMP()       bfin_read16(CAN_MB22_TIMESTAMP)
+#define bfin_write_CAN_MB22_TIMESTAMP(val)   bfin_write16(CAN_MB22_TIMESTAMP,val)
+#define bfin_read_CAN_MB22_LENGTH()          bfin_read16(CAN_MB22_LENGTH)
+#define bfin_write_CAN_MB22_LENGTH(val)      bfin_write16(CAN_MB22_LENGTH,val)
+#define bfin_read_CAN_MB22_DATA3()           bfin_read16(CAN_MB22_DATA3)
+#define bfin_write_CAN_MB22_DATA3(val)       bfin_write16(CAN_MB22_DATA3,val)
+#define bfin_read_CAN_MB22_DATA2()           bfin_read16(CAN_MB22_DATA2)
+#define bfin_write_CAN_MB22_DATA2(val)       bfin_write16(CAN_MB22_DATA2,val)
+#define bfin_read_CAN_MB22_DATA1()           bfin_read16(CAN_MB22_DATA1)
+#define bfin_write_CAN_MB22_DATA1(val)       bfin_write16(CAN_MB22_DATA1,val)
+#define bfin_read_CAN_MB22_DATA0()           bfin_read16(CAN_MB22_DATA0)
+#define bfin_write_CAN_MB22_DATA0(val)       bfin_write16(CAN_MB22_DATA0,val)
+
+#define bfin_read_CAN_MB23_ID1()             bfin_read16(CAN_MB23_ID1)
+#define bfin_write_CAN_MB23_ID1(val)         bfin_write16(CAN_MB23_ID1,val)
+#define bfin_read_CAN_MB23_ID0()             bfin_read16(CAN_MB23_ID0)
+#define bfin_write_CAN_MB23_ID0(val)         bfin_write16(CAN_MB23_ID0,val)
+#define bfin_read_CAN_MB23_TIMESTAMP()       bfin_read16(CAN_MB23_TIMESTAMP)
+#define bfin_write_CAN_MB23_TIMESTAMP(val)   bfin_write16(CAN_MB23_TIMESTAMP,val)
+#define bfin_read_CAN_MB23_LENGTH()          bfin_read16(CAN_MB23_LENGTH)
+#define bfin_write_CAN_MB23_LENGTH(val)      bfin_write16(CAN_MB23_LENGTH,val)
+#define bfin_read_CAN_MB23_DATA3()           bfin_read16(CAN_MB23_DATA3)
+#define bfin_write_CAN_MB23_DATA3(val)       bfin_write16(CAN_MB23_DATA3,val)
+#define bfin_read_CAN_MB23_DATA2()           bfin_read16(CAN_MB23_DATA2)
+#define bfin_write_CAN_MB23_DATA2(val)       bfin_write16(CAN_MB23_DATA2,val)
+#define bfin_read_CAN_MB23_DATA1()           bfin_read16(CAN_MB23_DATA1)
+#define bfin_write_CAN_MB23_DATA1(val)       bfin_write16(CAN_MB23_DATA1,val)
+#define bfin_read_CAN_MB23_DATA0()           bfin_read16(CAN_MB23_DATA0)
+#define bfin_write_CAN_MB23_DATA0(val)       bfin_write16(CAN_MB23_DATA0,val)
+
+#define bfin_read_CAN_MB24_ID1()             bfin_read16(CAN_MB24_ID1)
+#define bfin_write_CAN_MB24_ID1(val)         bfin_write16(CAN_MB24_ID1,val)
+#define bfin_read_CAN_MB24_ID0()             bfin_read16(CAN_MB24_ID0)
+#define bfin_write_CAN_MB24_ID0(val)         bfin_write16(CAN_MB24_ID0,val)
+#define bfin_read_CAN_MB24_TIMESTAMP()       bfin_read16(CAN_MB24_TIMESTAMP)
+#define bfin_write_CAN_MB24_TIMESTAMP(val)   bfin_write16(CAN_MB24_TIMESTAMP,val)
+#define bfin_read_CAN_MB24_LENGTH()          bfin_read16(CAN_MB24_LENGTH)
+#define bfin_write_CAN_MB24_LENGTH(val)      bfin_write16(CAN_MB24_LENGTH,val)
+#define bfin_read_CAN_MB24_DATA3()           bfin_read16(CAN_MB24_DATA3)
+#define bfin_write_CAN_MB24_DATA3(val)       bfin_write16(CAN_MB24_DATA3,val)
+#define bfin_read_CAN_MB24_DATA2()           bfin_read16(CAN_MB24_DATA2)
+#define bfin_write_CAN_MB24_DATA2(val)       bfin_write16(CAN_MB24_DATA2,val)
+#define bfin_read_CAN_MB24_DATA1()           bfin_read16(CAN_MB24_DATA1)
+#define bfin_write_CAN_MB24_DATA1(val)       bfin_write16(CAN_MB24_DATA1,val)
+#define bfin_read_CAN_MB24_DATA0()           bfin_read16(CAN_MB24_DATA0)
+#define bfin_write_CAN_MB24_DATA0(val)       bfin_write16(CAN_MB24_DATA0,val)
+
+#define bfin_read_CAN_MB25_ID1()             bfin_read16(CAN_MB25_ID1)
+#define bfin_write_CAN_MB25_ID1(val)         bfin_write16(CAN_MB25_ID1,val)
+#define bfin_read_CAN_MB25_ID0()             bfin_read16(CAN_MB25_ID0)
+#define bfin_write_CAN_MB25_ID0(val)         bfin_write16(CAN_MB25_ID0,val)
+#define bfin_read_CAN_MB25_TIMESTAMP()       bfin_read16(CAN_MB25_TIMESTAMP)
+#define bfin_write_CAN_MB25_TIMESTAMP(val)   bfin_write16(CAN_MB25_TIMESTAMP,val)
+#define bfin_read_CAN_MB25_LENGTH()          bfin_read16(CAN_MB25_LENGTH)
+#define bfin_write_CAN_MB25_LENGTH(val)      bfin_write16(CAN_MB25_LENGTH,val)
+#define bfin_read_CAN_MB25_DATA3()           bfin_read16(CAN_MB25_DATA3)
+#define bfin_write_CAN_MB25_DATA3(val)       bfin_write16(CAN_MB25_DATA3,val)
+#define bfin_read_CAN_MB25_DATA2()           bfin_read16(CAN_MB25_DATA2)
+#define bfin_write_CAN_MB25_DATA2(val)       bfin_write16(CAN_MB25_DATA2,val)
+#define bfin_read_CAN_MB25_DATA1()           bfin_read16(CAN_MB25_DATA1)
+#define bfin_write_CAN_MB25_DATA1(val)       bfin_write16(CAN_MB25_DATA1,val)
+#define bfin_read_CAN_MB25_DATA0()           bfin_read16(CAN_MB25_DATA0)
+#define bfin_write_CAN_MB25_DATA0(val)       bfin_write16(CAN_MB25_DATA0,val)
+
+#define bfin_read_CAN_MB26_ID1()             bfin_read16(CAN_MB26_ID1)
+#define bfin_write_CAN_MB26_ID1(val)         bfin_write16(CAN_MB26_ID1,val)
+#define bfin_read_CAN_MB26_ID0()             bfin_read16(CAN_MB26_ID0)
+#define bfin_write_CAN_MB26_ID0(val)         bfin_write16(CAN_MB26_ID0,val)
+#define bfin_read_CAN_MB26_TIMESTAMP()       bfin_read16(CAN_MB26_TIMESTAMP)
+#define bfin_write_CAN_MB26_TIMESTAMP(val)   bfin_write16(CAN_MB26_TIMESTAMP,val)
+#define bfin_read_CAN_MB26_LENGTH()          bfin_read16(CAN_MB26_LENGTH)
+#define bfin_write_CAN_MB26_LENGTH(val)      bfin_write16(CAN_MB26_LENGTH,val)
+#define bfin_read_CAN_MB26_DATA3()           bfin_read16(CAN_MB26_DATA3)
+#define bfin_write_CAN_MB26_DATA3(val)       bfin_write16(CAN_MB26_DATA3,val)
+#define bfin_read_CAN_MB26_DATA2()           bfin_read16(CAN_MB26_DATA2)
+#define bfin_write_CAN_MB26_DATA2(val)       bfin_write16(CAN_MB26_DATA2,val)
+#define bfin_read_CAN_MB26_DATA1()           bfin_read16(CAN_MB26_DATA1)
+#define bfin_write_CAN_MB26_DATA1(val)       bfin_write16(CAN_MB26_DATA1,val)
+#define bfin_read_CAN_MB26_DATA0()           bfin_read16(CAN_MB26_DATA0)
+#define bfin_write_CAN_MB26_DATA0(val)       bfin_write16(CAN_MB26_DATA0,val)
+
+#define bfin_read_CAN_MB27_ID1()             bfin_read16(CAN_MB27_ID1)
+#define bfin_write_CAN_MB27_ID1(val)         bfin_write16(CAN_MB27_ID1,val)
+#define bfin_read_CAN_MB27_ID0()             bfin_read16(CAN_MB27_ID0)
+#define bfin_write_CAN_MB27_ID0(val)         bfin_write16(CAN_MB27_ID0,val)
+#define bfin_read_CAN_MB27_TIMESTAMP()       bfin_read16(CAN_MB27_TIMESTAMP)
+#define bfin_write_CAN_MB27_TIMESTAMP(val)   bfin_write16(CAN_MB27_TIMESTAMP,val)
+#define bfin_read_CAN_MB27_LENGTH()          bfin_read16(CAN_MB27_LENGTH)
+#define bfin_write_CAN_MB27_LENGTH(val)      bfin_write16(CAN_MB27_LENGTH,val)
+#define bfin_read_CAN_MB27_DATA3()           bfin_read16(CAN_MB27_DATA3)
+#define bfin_write_CAN_MB27_DATA3(val)       bfin_write16(CAN_MB27_DATA3,val)
+#define bfin_read_CAN_MB27_DATA2()           bfin_read16(CAN_MB27_DATA2)
+#define bfin_write_CAN_MB27_DATA2(val)       bfin_write16(CAN_MB27_DATA2,val)
+#define bfin_read_CAN_MB27_DATA1()           bfin_read16(CAN_MB27_DATA1)
+#define bfin_write_CAN_MB27_DATA1(val)       bfin_write16(CAN_MB27_DATA1,val)
+#define bfin_read_CAN_MB27_DATA0()           bfin_read16(CAN_MB27_DATA0)
+#define bfin_write_CAN_MB27_DATA0(val)       bfin_write16(CAN_MB27_DATA0,val)
+
+#define bfin_read_CAN_MB28_ID1()             bfin_read16(CAN_MB28_ID1)
+#define bfin_write_CAN_MB28_ID1(val)         bfin_write16(CAN_MB28_ID1,val)
+#define bfin_read_CAN_MB28_ID0()             bfin_read16(CAN_MB28_ID0)
+#define bfin_write_CAN_MB28_ID0(val)         bfin_write16(CAN_MB28_ID0,val)
+#define bfin_read_CAN_MB28_TIMESTAMP()       bfin_read16(CAN_MB28_TIMESTAMP)
+#define bfin_write_CAN_MB28_TIMESTAMP(val)   bfin_write16(CAN_MB28_TIMESTAMP,val)
+#define bfin_read_CAN_MB28_LENGTH()          bfin_read16(CAN_MB28_LENGTH)
+#define bfin_write_CAN_MB28_LENGTH(val)      bfin_write16(CAN_MB28_LENGTH,val)
+#define bfin_read_CAN_MB28_DATA3()           bfin_read16(CAN_MB28_DATA3)
+#define bfin_write_CAN_MB28_DATA3(val)       bfin_write16(CAN_MB28_DATA3,val)
+#define bfin_read_CAN_MB28_DATA2()           bfin_read16(CAN_MB28_DATA2)
+#define bfin_write_CAN_MB28_DATA2(val)       bfin_write16(CAN_MB28_DATA2,val)
+#define bfin_read_CAN_MB28_DATA1()           bfin_read16(CAN_MB28_DATA1)
+#define bfin_write_CAN_MB28_DATA1(val)       bfin_write16(CAN_MB28_DATA1,val)
+#define bfin_read_CAN_MB28_DATA0()           bfin_read16(CAN_MB28_DATA0)
+#define bfin_write_CAN_MB28_DATA0(val)       bfin_write16(CAN_MB28_DATA0,val)
+
+#define bfin_read_CAN_MB29_ID1()             bfin_read16(CAN_MB29_ID1)
+#define bfin_write_CAN_MB29_ID1(val)         bfin_write16(CAN_MB29_ID1,val)
+#define bfin_read_CAN_MB29_ID0()             bfin_read16(CAN_MB29_ID0)
+#define bfin_write_CAN_MB29_ID0(val)         bfin_write16(CAN_MB29_ID0,val)
+#define bfin_read_CAN_MB29_TIMESTAMP()       bfin_read16(CAN_MB29_TIMESTAMP)
+#define bfin_write_CAN_MB29_TIMESTAMP(val)   bfin_write16(CAN_MB29_TIMESTAMP,val)
+#define bfin_read_CAN_MB29_LENGTH()          bfin_read16(CAN_MB29_LENGTH)
+#define bfin_write_CAN_MB29_LENGTH(val)      bfin_write16(CAN_MB29_LENGTH,val)
+#define bfin_read_CAN_MB29_DATA3()           bfin_read16(CAN_MB29_DATA3)
+#define bfin_write_CAN_MB29_DATA3(val)       bfin_write16(CAN_MB29_DATA3,val)
+#define bfin_read_CAN_MB29_DATA2()           bfin_read16(CAN_MB29_DATA2)
+#define bfin_write_CAN_MB29_DATA2(val)       bfin_write16(CAN_MB29_DATA2,val)
+#define bfin_read_CAN_MB29_DATA1()           bfin_read16(CAN_MB29_DATA1)
+#define bfin_write_CAN_MB29_DATA1(val)       bfin_write16(CAN_MB29_DATA1,val)
+#define bfin_read_CAN_MB29_DATA0()           bfin_read16(CAN_MB29_DATA0)
+#define bfin_write_CAN_MB29_DATA0(val)       bfin_write16(CAN_MB29_DATA0,val)
+
+#define bfin_read_CAN_MB30_ID1()             bfin_read16(CAN_MB30_ID1)
+#define bfin_write_CAN_MB30_ID1(val)         bfin_write16(CAN_MB30_ID1,val)
+#define bfin_read_CAN_MB30_ID0()             bfin_read16(CAN_MB30_ID0)
+#define bfin_write_CAN_MB30_ID0(val)         bfin_write16(CAN_MB30_ID0,val)
+#define bfin_read_CAN_MB30_TIMESTAMP()       bfin_read16(CAN_MB30_TIMESTAMP)
+#define bfin_write_CAN_MB30_TIMESTAMP(val)   bfin_write16(CAN_MB30_TIMESTAMP,val)
+#define bfin_read_CAN_MB30_LENGTH()          bfin_read16(CAN_MB30_LENGTH)
+#define bfin_write_CAN_MB30_LENGTH(val)      bfin_write16(CAN_MB30_LENGTH,val)
+#define bfin_read_CAN_MB30_DATA3()           bfin_read16(CAN_MB30_DATA3)
+#define bfin_write_CAN_MB30_DATA3(val)       bfin_write16(CAN_MB30_DATA3,val)
+#define bfin_read_CAN_MB30_DATA2()           bfin_read16(CAN_MB30_DATA2)
+#define bfin_write_CAN_MB30_DATA2(val)       bfin_write16(CAN_MB30_DATA2,val)
+#define bfin_read_CAN_MB30_DATA1()           bfin_read16(CAN_MB30_DATA1)
+#define bfin_write_CAN_MB30_DATA1(val)       bfin_write16(CAN_MB30_DATA1,val)
+#define bfin_read_CAN_MB30_DATA0()           bfin_read16(CAN_MB30_DATA0)
+#define bfin_write_CAN_MB30_DATA0(val)       bfin_write16(CAN_MB30_DATA0,val)
+
+#define bfin_read_CAN_MB31_ID1()             bfin_read16(CAN_MB31_ID1)
+#define bfin_write_CAN_MB31_ID1(val)         bfin_write16(CAN_MB31_ID1,val)
+#define bfin_read_CAN_MB31_ID0()             bfin_read16(CAN_MB31_ID0)
+#define bfin_write_CAN_MB31_ID0(val)         bfin_write16(CAN_MB31_ID0,val)
+#define bfin_read_CAN_MB31_TIMESTAMP()       bfin_read16(CAN_MB31_TIMESTAMP)
+#define bfin_write_CAN_MB31_TIMESTAMP(val)   bfin_write16(CAN_MB31_TIMESTAMP,val)
+#define bfin_read_CAN_MB31_LENGTH()          bfin_read16(CAN_MB31_LENGTH)
+#define bfin_write_CAN_MB31_LENGTH(val)      bfin_write16(CAN_MB31_LENGTH,val)
+#define bfin_read_CAN_MB31_DATA3()           bfin_read16(CAN_MB31_DATA3)
+#define bfin_write_CAN_MB31_DATA3(val)       bfin_write16(CAN_MB31_DATA3,val)
+#define bfin_read_CAN_MB31_DATA2()           bfin_read16(CAN_MB31_DATA2)
+#define bfin_write_CAN_MB31_DATA2(val)       bfin_write16(CAN_MB31_DATA2,val)
+#define bfin_read_CAN_MB31_DATA1()           bfin_read16(CAN_MB31_DATA1)
+#define bfin_write_CAN_MB31_DATA1(val)       bfin_write16(CAN_MB31_DATA1,val)
+#define bfin_read_CAN_MB31_DATA0()           bfin_read16(CAN_MB31_DATA0)
+#define bfin_write_CAN_MB31_DATA0(val)       bfin_write16(CAN_MB31_DATA0,val)
+
+/* CAN Mailbox Area Macros              */
+#define bfin_read_CAN_MB_ID1(x)()            bfin_read16(CAN_MB_ID1(x))
+#define bfin_write_CAN_MB_ID1(x)(val)        bfin_write16(CAN_MB_ID1(x),val)
+#define bfin_read_CAN_MB_ID0(x)()            bfin_read16(CAN_MB_ID0(x))
+#define bfin_write_CAN_MB_ID0(x)(val)        bfin_write16(CAN_MB_ID0(x),val)
+#define bfin_read_CAN_MB_TIMESTAMP(x)()      bfin_read16(CAN_MB_TIMESTAMP(x))
+#define bfin_write_CAN_MB_TIMESTAMP(x)(val)  bfin_write16(CAN_MB_TIMESTAMP(x),val)
+#define bfin_read_CAN_MB_LENGTH(x)()         bfin_read16(CAN_MB_LENGTH(x))
+#define bfin_write_CAN_MB_LENGTH(x)(val)     bfin_write16(CAN_MB_LENGTH(x),val)
+#define bfin_read_CAN_MB_DATA3(x)()          bfin_read16(CAN_MB_DATA3(x))
+#define bfin_write_CAN_MB_DATA3(x)(val)      bfin_write16(CAN_MB_DATA3(x),val)
+#define bfin_read_CAN_MB_DATA2(x)()          bfin_read16(CAN_MB_DATA2(x))
+#define bfin_write_CAN_MB_DATA2(x)(val)      bfin_write16(CAN_MB_DATA2(x),val)
+#define bfin_read_CAN_MB_DATA1(x)()          bfin_read16(CAN_MB_DATA1(x))
+#define bfin_write_CAN_MB_DATA1(x)(val)      bfin_write16(CAN_MB_DATA1(x),val)
+#define bfin_read_CAN_MB_DATA0(x)()          bfin_read16(CAN_MB_DATA0(x))
+#define bfin_write_CAN_MB_DATA0(x)(val)      bfin_write16(CAN_MB_DATA0(x),val)
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                               */
+#define bfin_read_PORTF_FER()                bfin_read16(PORTF_FER)
+#define bfin_write_PORTF_FER(val)            bfin_write16(PORTF_FER,val)
+#define bfin_read_PORTG_FER()                bfin_read16(PORTG_FER)
+#define bfin_write_PORTG_FER(val)            bfin_write16(PORTG_FER,val)
+#define bfin_read_PORTH_FER()                bfin_read16(PORTH_FER)
+#define bfin_write_PORTH_FER(val)            bfin_write16(PORTH_FER,val)
+#define bfin_read_PORT_MUX()                 bfin_read16(BFIN_PORT_MUX)
+#define bfin_write_PORT_MUX(val)             bfin_write16(BFIN_PORT_MUX,val)
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                               */
+#define bfin_read_HMDMA0_CONTROL()           bfin_read16(HMDMA0_CONTROL)
+#define bfin_write_HMDMA0_CONTROL(val)       bfin_write16(HMDMA0_CONTROL,val)
+#define bfin_read_HMDMA0_ECINIT()            bfin_read16(HMDMA0_ECINIT)
+#define bfin_write_HMDMA0_ECINIT(val)        bfin_write16(HMDMA0_ECINIT,val)
+#define bfin_read_HMDMA0_BCINIT()            bfin_read16(HMDMA0_BCINIT)
+#define bfin_write_HMDMA0_BCINIT(val)        bfin_write16(HMDMA0_BCINIT,val)
+#define bfin_read_HMDMA0_ECURGENT()          bfin_read16(HMDMA0_ECURGENT)
+#define bfin_write_HMDMA0_ECURGENT(val)      bfin_write16(HMDMA0_ECURGENT,val)
+#define bfin_read_HMDMA0_ECOVERFLOW()        bfin_read16(HMDMA0_ECOVERFLOW)
+#define bfin_write_HMDMA0_ECOVERFLOW(val)    bfin_write16(HMDMA0_ECOVERFLOW,val)
+#define bfin_read_HMDMA0_ECOUNT()            bfin_read16(HMDMA0_ECOUNT)
+#define bfin_write_HMDMA0_ECOUNT(val)        bfin_write16(HMDMA0_ECOUNT,val)
+#define bfin_read_HMDMA0_BCOUNT()            bfin_read16(HMDMA0_BCOUNT)
+#define bfin_write_HMDMA0_BCOUNT(val)        bfin_write16(HMDMA0_BCOUNT,val)
+
+#define bfin_read_HMDMA1_CONTROL()           bfin_read16(HMDMA1_CONTROL)
+#define bfin_write_HMDMA1_CONTROL(val)       bfin_write16(HMDMA1_CONTROL,val)
+#define bfin_read_HMDMA1_ECINIT()            bfin_read16(HMDMA1_ECINIT)
+#define bfin_write_HMDMA1_ECINIT(val)        bfin_write16(HMDMA1_ECINIT,val)
+#define bfin_read_HMDMA1_BCINIT()            bfin_read16(HMDMA1_BCINIT)
+#define bfin_write_HMDMA1_BCINIT(val)        bfin_write16(HMDMA1_BCINIT,val)
+#define bfin_read_HMDMA1_ECURGENT()          bfin_read16(HMDMA1_ECURGENT)
+#define bfin_write_HMDMA1_ECURGENT(val)      bfin_write16(HMDMA1_ECURGENT,val)
+#define bfin_read_HMDMA1_ECOVERFLOW()        bfin_read16(HMDMA1_ECOVERFLOW)
+#define bfin_write_HMDMA1_ECOVERFLOW(val)    bfin_write16(HMDMA1_ECOVERFLOW,val)
+#define bfin_read_HMDMA1_ECOUNT()            bfin_read16(HMDMA1_ECOUNT)
+#define bfin_write_HMDMA1_ECOUNT(val)        bfin_write16(HMDMA1_ECOUNT,val)
+#define bfin_read_HMDMA1_BCOUNT()            bfin_read16(HMDMA1_BCOUNT)
+#define bfin_write_HMDMA1_BCOUNT(val)        bfin_write16(HMDMA1_BCOUNT,val)
+
+#endif                          /* _CDEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/cdefBF537.h b/include/asm-blackfin/mach-bf537/cdefBF537.h
new file mode 100644
index 000000000000..932a1b6b5d14
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/cdefBF537.h
@@ -0,0 +1,209 @@
+/*
+ * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *      System MMR Register Map
+ * Rev:
+ *
+ * Modified:
+ *
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF537_H
+#define _CDEF_BF537_H
+
+/* Include MMRs Common to BF534                                                                 */
+#include "cdefBF534.h"
+
+/* Include all Core registers and bit definitions                                                                       */
+#include "defBF537.h"
+
+/* Include Macro "Defines" For EMAC (Unique to BF536/BF537              */
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                               */
+#define pEMAC_OPMODE            ((volatile unsigned long  *)EMAC_OPMODE)
+#define bfin_read_EMAC_OPMODE()              bfin_read32(EMAC_OPMODE)
+#define bfin_write_EMAC_OPMODE(val)          bfin_write32(EMAC_OPMODE,val)
+#define bfin_read_EMAC_ADDRLO()              bfin_read32(EMAC_ADDRLO)
+#define bfin_write_EMAC_ADDRLO(val)          bfin_write32(EMAC_ADDRLO,val)
+#define bfin_read_EMAC_ADDRHI()              bfin_read32(EMAC_ADDRHI)
+#define bfin_write_EMAC_ADDRHI(val)          bfin_write32(EMAC_ADDRHI,val)
+#define bfin_read_EMAC_HASHLO()              bfin_read32(EMAC_HASHLO)
+#define bfin_write_EMAC_HASHLO(val)          bfin_write32(EMAC_HASHLO,val)
+#define bfin_read_EMAC_HASHHI()              bfin_read32(EMAC_HASHHI)
+#define bfin_write_EMAC_HASHHI(val)          bfin_write32(EMAC_HASHHI,val)
+#define bfin_read_EMAC_STAADD()              bfin_read32(EMAC_STAADD)
+#define bfin_write_EMAC_STAADD(val)          bfin_write32(EMAC_STAADD,val)
+#define bfin_read_EMAC_STADAT()              bfin_read32(EMAC_STADAT)
+#define bfin_write_EMAC_STADAT(val)          bfin_write32(EMAC_STADAT,val)
+#define bfin_read_EMAC_FLC()                 bfin_read32(EMAC_FLC)
+#define bfin_write_EMAC_FLC(val)             bfin_write32(EMAC_FLC,val)
+#define bfin_read_EMAC_VLAN1()               bfin_read32(EMAC_VLAN1)
+#define bfin_write_EMAC_VLAN1(val)           bfin_write32(EMAC_VLAN1,val)
+#define bfin_read_EMAC_VLAN2()               bfin_read32(EMAC_VLAN2)
+#define bfin_write_EMAC_VLAN2(val)           bfin_write32(EMAC_VLAN2,val)
+#define bfin_read_EMAC_WKUP_CTL()            bfin_read32(EMAC_WKUP_CTL)
+#define bfin_write_EMAC_WKUP_CTL(val)        bfin_write32(EMAC_WKUP_CTL,val)
+#define bfin_read_EMAC_WKUP_FFMSK0()         bfin_read32(EMAC_WKUP_FFMSK0)
+#define bfin_write_EMAC_WKUP_FFMSK0(val)     bfin_write32(EMAC_WKUP_FFMSK0,val)
+#define bfin_read_EMAC_WKUP_FFMSK1()         bfin_read32(EMAC_WKUP_FFMSK1)
+#define bfin_write_EMAC_WKUP_FFMSK1(val)     bfin_write32(EMAC_WKUP_FFMSK1,val)
+#define bfin_read_EMAC_WKUP_FFMSK2()         bfin_read32(EMAC_WKUP_FFMSK2)
+#define bfin_write_EMAC_WKUP_FFMSK2(val)     bfin_write32(EMAC_WKUP_FFMSK2,val)
+#define bfin_read_EMAC_WKUP_FFMSK3()         bfin_read32(EMAC_WKUP_FFMSK3)
+#define bfin_write_EMAC_WKUP_FFMSK3(val)     bfin_write32(EMAC_WKUP_FFMSK3,val)
+#define bfin_read_EMAC_WKUP_FFCMD()          bfin_read32(EMAC_WKUP_FFCMD)
+#define bfin_write_EMAC_WKUP_FFCMD(val)      bfin_write32(EMAC_WKUP_FFCMD,val)
+#define bfin_read_EMAC_WKUP_FFOFF()          bfin_read32(EMAC_WKUP_FFOFF)
+#define bfin_write_EMAC_WKUP_FFOFF(val)      bfin_write32(EMAC_WKUP_FFOFF,val)
+#define bfin_read_EMAC_WKUP_FFCRC0()         bfin_read32(EMAC_WKUP_FFCRC0)
+#define bfin_write_EMAC_WKUP_FFCRC0(val)     bfin_write32(EMAC_WKUP_FFCRC0,val)
+#define bfin_read_EMAC_WKUP_FFCRC1()         bfin_read32(EMAC_WKUP_FFCRC1)
+#define bfin_write_EMAC_WKUP_FFCRC1(val)     bfin_write32(EMAC_WKUP_FFCRC1,val)
+
+#define pEMAC_SYSCTL            ((volatile unsigned long  *)EMAC_SYSCTL)
+#define bfin_read_EMAC_SYSCTL()              bfin_read32(EMAC_SYSCTL)
+#define bfin_write_EMAC_SYSCTL(val)          bfin_write32(EMAC_SYSCTL,val)
+#define bfin_read_EMAC_SYSTAT()              bfin_read32(EMAC_SYSTAT)
+#define bfin_write_EMAC_SYSTAT(val)          bfin_write32(EMAC_SYSTAT,val)
+#define bfin_read_EMAC_RX_STAT()             bfin_read32(EMAC_RX_STAT)
+#define bfin_write_EMAC_RX_STAT(val)         bfin_write32(EMAC_RX_STAT,val)
+#define bfin_read_EMAC_RX_STKY()             bfin_read32(EMAC_RX_STKY)
+#define bfin_write_EMAC_RX_STKY(val)         bfin_write32(EMAC_RX_STKY,val)
+#define bfin_read_EMAC_RX_IRQE()             bfin_read32(EMAC_RX_IRQE)
+#define bfin_write_EMAC_RX_IRQE(val)         bfin_write32(EMAC_RX_IRQE,val)
+#define bfin_read_EMAC_TX_STAT()             bfin_read32(EMAC_TX_STAT)
+#define bfin_write_EMAC_TX_STAT(val)         bfin_write32(EMAC_TX_STAT,val)
+#define bfin_read_EMAC_TX_STKY()             bfin_read32(EMAC_TX_STKY)
+#define bfin_write_EMAC_TX_STKY(val)         bfin_write32(EMAC_TX_STKY,val)
+#define bfin_read_EMAC_TX_IRQE()             bfin_read32(EMAC_TX_IRQE)
+#define bfin_write_EMAC_TX_IRQE(val)         bfin_write32(EMAC_TX_IRQE,val)
+
+#define bfin_read_EMAC_MMC_CTL()             bfin_read32(EMAC_MMC_CTL)
+#define bfin_write_EMAC_MMC_CTL(val)         bfin_write32(EMAC_MMC_CTL,val)
+#define bfin_read_EMAC_MMC_RIRQS()           bfin_read32(EMAC_MMC_RIRQS)
+#define bfin_write_EMAC_MMC_RIRQS(val)       bfin_write32(EMAC_MMC_RIRQS,val)
+#define bfin_read_EMAC_MMC_RIRQE()           bfin_read32(EMAC_MMC_RIRQE)
+#define bfin_write_EMAC_MMC_RIRQE(val)       bfin_write32(EMAC_MMC_RIRQE,val)
+#define bfin_read_EMAC_MMC_TIRQS()           bfin_read32(EMAC_MMC_TIRQS)
+#define bfin_write_EMAC_MMC_TIRQS(val)       bfin_write32(EMAC_MMC_TIRQS,val)
+#define bfin_read_EMAC_MMC_TIRQE()           bfin_read32(EMAC_MMC_TIRQE)
+#define bfin_write_EMAC_MMC_TIRQE(val)       bfin_write32(EMAC_MMC_TIRQE,val)
+
+#define bfin_read_EMAC_RXC_OK()              bfin_read32(EMAC_RXC_OK)
+#define bfin_write_EMAC_RXC_OK(val)          bfin_write32(EMAC_RXC_OK,val)
+#define bfin_read_EMAC_RXC_FCS()             bfin_read32(EMAC_RXC_FCS)
+#define bfin_write_EMAC_RXC_FCS(val)         bfin_write32(EMAC_RXC_FCS,val)
+#define bfin_read_EMAC_RXC_ALIGN()           bfin_read32(EMAC_RXC_ALIGN)
+#define bfin_write_EMAC_RXC_ALIGN(val)       bfin_write32(EMAC_RXC_ALIGN,val)
+#define bfin_read_EMAC_RXC_OCTET()           bfin_read32(EMAC_RXC_OCTET)
+#define bfin_write_EMAC_RXC_OCTET(val)       bfin_write32(EMAC_RXC_OCTET,val)
+#define bfin_read_EMAC_RXC_DMAOVF()          bfin_read32(EMAC_RXC_DMAOVF)
+#define bfin_write_EMAC_RXC_DMAOVF(val)      bfin_write32(EMAC_RXC_DMAOVF,val)
+#define bfin_read_EMAC_RXC_UNICST()          bfin_read32(EMAC_RXC_UNICST)
+#define bfin_write_EMAC_RXC_UNICST(val)      bfin_write32(EMAC_RXC_UNICST,val)
+#define bfin_read_EMAC_RXC_MULTI()           bfin_read32(EMAC_RXC_MULTI)
+#define bfin_write_EMAC_RXC_MULTI(val)       bfin_write32(EMAC_RXC_MULTI,val)
+#define bfin_read_EMAC_RXC_BROAD()           bfin_read32(EMAC_RXC_BROAD)
+#define bfin_write_EMAC_RXC_BROAD(val)       bfin_write32(EMAC_RXC_BROAD,val)
+#define bfin_read_EMAC_RXC_LNERRI()          bfin_read32(EMAC_RXC_LNERRI)
+#define bfin_write_EMAC_RXC_LNERRI(val)      bfin_write32(EMAC_RXC_LNERRI,val)
+#define bfin_read_EMAC_RXC_LNERRO()          bfin_read32(EMAC_RXC_LNERRO)
+#define bfin_write_EMAC_RXC_LNERRO(val)      bfin_write32(EMAC_RXC_LNERRO,val)
+#define bfin_read_EMAC_RXC_LONG()            bfin_read32(EMAC_RXC_LONG)
+#define bfin_write_EMAC_RXC_LONG(val)        bfin_write32(EMAC_RXC_LONG,val)
+#define bfin_read_EMAC_RXC_MACCTL()          bfin_read32(EMAC_RXC_MACCTL)
+#define bfin_write_EMAC_RXC_MACCTL(val)      bfin_write32(EMAC_RXC_MACCTL,val)
+#define bfin_read_EMAC_RXC_OPCODE()          bfin_read32(EMAC_RXC_OPCODE)
+#define bfin_write_EMAC_RXC_OPCODE(val)      bfin_write32(EMAC_RXC_OPCODE,val)
+#define bfin_read_EMAC_RXC_PAUSE()           bfin_read32(EMAC_RXC_PAUSE)
+#define bfin_write_EMAC_RXC_PAUSE(val)       bfin_write32(EMAC_RXC_PAUSE,val)
+#define bfin_read_EMAC_RXC_ALLFRM()          bfin_read32(EMAC_RXC_ALLFRM)
+#define bfin_write_EMAC_RXC_ALLFRM(val)      bfin_write32(EMAC_RXC_ALLFRM,val)
+#define bfin_read_EMAC_RXC_ALLOCT()          bfin_read32(EMAC_RXC_ALLOCT)
+#define bfin_write_EMAC_RXC_ALLOCT(val)      bfin_write32(EMAC_RXC_ALLOCT,val)
+#define bfin_read_EMAC_RXC_TYPED()           bfin_read32(EMAC_RXC_TYPED)
+#define bfin_write_EMAC_RXC_TYPED(val)       bfin_write32(EMAC_RXC_TYPED,val)
+#define bfin_read_EMAC_RXC_SHORT()           bfin_read32(EMAC_RXC_SHORT)
+#define bfin_write_EMAC_RXC_SHORT(val)       bfin_write32(EMAC_RXC_SHORT,val)
+#define bfin_read_EMAC_RXC_EQ64()            bfin_read32(EMAC_RXC_EQ64)
+#define bfin_write_EMAC_RXC_EQ64(val)        bfin_write32(EMAC_RXC_EQ64,val)
+#define pEMAC_RXC_LT128         ((volatile unsigned long  *)EMAC_RXC_LT128)
+#define bfin_read_EMAC_RXC_LT128()           bfin_read32(EMAC_RXC_LT128)
+#define bfin_write_EMAC_RXC_LT128(val)       bfin_write32(EMAC_RXC_LT128,val)
+#define bfin_read_EMAC_RXC_LT256()           bfin_read32(EMAC_RXC_LT256)
+#define bfin_write_EMAC_RXC_LT256(val)       bfin_write32(EMAC_RXC_LT256,val)
+#define bfin_read_EMAC_RXC_LT512()           bfin_read32(EMAC_RXC_LT512)
+#define bfin_write_EMAC_RXC_LT512(val)       bfin_write32(EMAC_RXC_LT512,val)
+#define bfin_read_EMAC_RXC_LT1024()          bfin_read32(EMAC_RXC_LT1024)
+#define bfin_write_EMAC_RXC_LT1024(val)      bfin_write32(EMAC_RXC_LT1024,val)
+#define bfin_read_EMAC_RXC_GE1024()          bfin_read32(EMAC_RXC_GE1024)
+#define bfin_write_EMAC_RXC_GE1024(val)      bfin_write32(EMAC_RXC_GE1024,val)
+
+#define bfin_read_EMAC_TXC_OK()              bfin_read32(EMAC_TXC_OK)
+#define bfin_write_EMAC_TXC_OK(val)          bfin_write32(EMAC_TXC_OK,val)
+#define bfin_read_EMAC_TXC_1COL()            bfin_read32(EMAC_TXC_1COL)
+#define bfin_write_EMAC_TXC_1COL(val)        bfin_write32(EMAC_TXC_1COL,val)
+#define bfin_read_EMAC_TXC_GT1COL()          bfin_read32(EMAC_TXC_GT1COL)
+#define bfin_write_EMAC_TXC_GT1COL(val)      bfin_write32(EMAC_TXC_GT1COL,val)
+#define bfin_read_EMAC_TXC_OCTET()           bfin_read32(EMAC_TXC_OCTET)
+#define bfin_write_EMAC_TXC_OCTET(val)       bfin_write32(EMAC_TXC_OCTET,val)
+#define bfin_read_EMAC_TXC_DEFER()           bfin_read32(EMAC_TXC_DEFER)
+#define bfin_write_EMAC_TXC_DEFER(val)       bfin_write32(EMAC_TXC_DEFER,val)
+#define bfin_read_EMAC_TXC_LATECL()          bfin_read32(EMAC_TXC_LATECL)
+#define bfin_write_EMAC_TXC_LATECL(val)      bfin_write32(EMAC_TXC_LATECL,val)
+#define bfin_read_EMAC_TXC_XS_COL()          bfin_read32(EMAC_TXC_XS_COL)
+#define bfin_write_EMAC_TXC_XS_COL(val)      bfin_write32(EMAC_TXC_XS_COL,val)
+#define bfin_read_EMAC_TXC_DMAUND()          bfin_read32(EMAC_TXC_DMAUND)
+#define bfin_write_EMAC_TXC_DMAUND(val)      bfin_write32(EMAC_TXC_DMAUND,val)
+#define bfin_read_EMAC_TXC_CRSERR()          bfin_read32(EMAC_TXC_CRSERR)
+#define bfin_write_EMAC_TXC_CRSERR(val)      bfin_write32(EMAC_TXC_CRSERR,val)
+#define bfin_read_EMAC_TXC_UNICST()          bfin_read32(EMAC_TXC_UNICST)
+#define bfin_write_EMAC_TXC_UNICST(val)      bfin_write32(EMAC_TXC_UNICST,val)
+#define bfin_read_EMAC_TXC_MULTI()           bfin_read32(EMAC_TXC_MULTI)
+#define bfin_write_EMAC_TXC_MULTI(val)       bfin_write32(EMAC_TXC_MULTI,val)
+#define bfin_read_EMAC_TXC_BROAD()           bfin_read32(EMAC_TXC_BROAD)
+#define bfin_write_EMAC_TXC_BROAD(val)       bfin_write32(EMAC_TXC_BROAD,val)
+#define bfin_read_EMAC_TXC_XS_DFR()          bfin_read32(EMAC_TXC_XS_DFR)
+#define bfin_write_EMAC_TXC_XS_DFR(val)      bfin_write32(EMAC_TXC_XS_DFR,val)
+#define bfin_read_EMAC_TXC_MACCTL()          bfin_read32(EMAC_TXC_MACCTL)
+#define bfin_write_EMAC_TXC_MACCTL(val)      bfin_write32(EMAC_TXC_MACCTL,val)
+#define bfin_read_EMAC_TXC_ALLFRM()          bfin_read32(EMAC_TXC_ALLFRM)
+#define bfin_write_EMAC_TXC_ALLFRM(val)      bfin_write32(EMAC_TXC_ALLFRM,val)
+#define bfin_read_EMAC_TXC_ALLOCT()          bfin_read32(EMAC_TXC_ALLOCT)
+#define bfin_write_EMAC_TXC_ALLOCT(val)      bfin_write32(EMAC_TXC_ALLOCT,val)
+#define bfin_read_EMAC_TXC_EQ64()            bfin_read32(EMAC_TXC_EQ64)
+#define bfin_write_EMAC_TXC_EQ64(val)        bfin_write32(EMAC_TXC_EQ64,val)
+#define bfin_read_EMAC_TXC_LT128()           bfin_read32(EMAC_TXC_LT128)
+#define bfin_write_EMAC_TXC_LT128(val)       bfin_write32(EMAC_TXC_LT128,val)
+#define bfin_read_EMAC_TXC_LT256()           bfin_read32(EMAC_TXC_LT256)
+#define bfin_write_EMAC_TXC_LT256(val)       bfin_write32(EMAC_TXC_LT256,val)
+#define bfin_read_EMAC_TXC_LT512()           bfin_read32(EMAC_TXC_LT512)
+#define bfin_write_EMAC_TXC_LT512(val)       bfin_write32(EMAC_TXC_LT512,val)
+#define bfin_read_EMAC_TXC_LT1024()          bfin_read32(EMAC_TXC_LT1024)
+#define bfin_write_EMAC_TXC_LT1024(val)      bfin_write32(EMAC_TXC_LT1024,val)
+#define bfin_read_EMAC_TXC_GE1024()          bfin_read32(EMAC_TXC_GE1024)
+#define bfin_write_EMAC_TXC_GE1024(val)      bfin_write32(EMAC_TXC_GE1024,val)
+#define bfin_read_EMAC_TXC_ABORT()           bfin_read32(EMAC_TXC_ABORT)
+#define bfin_write_EMAC_TXC_ABORT(val)       bfin_write32(EMAC_TXC_ABORT,val)
+
+#endif                          /* _CDEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF534.h b/include/asm-blackfin/mach-bf537/defBF534.h
new file mode 100644
index 000000000000..e605e9709004
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/defBF534.h
@@ -0,0 +1,2501 @@
+/*
+ * File:         include/asm-blackfin/mach-bf537/cdefBF537.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF534_H
+#define _DEF_BF534_H
+
+/* Include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/************************************************************************************
+** System MMR Register Map
+*************************************************************************************/
+/* Clock and System Control     (0xFFC00000 - 0xFFC000FF)                                                               */
+#define PLL_CTL                         0xFFC00000      /* PLL Control Register                                         */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register                                          */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register           */
+#define PLL_STAT                        0xFFC0000C      /* PLL Status Register                                          */
+#define PLL_LOCKCNT                     0xFFC00010      /* PLL Lock Count Register                                      */
+#define CHIPID                          0xFFC00014      /* Chip ID Register                                             */
+
+/* System Interrupt Controller (0xFFC00100 - 0xFFC001FF)                                                        */
+#define SWRST                           0xFFC00100      /* Software Reset Register                                      */
+#define SYSCR                           0xFFC00104      /* System Configuration Register                        */
+#define SIC_RVECT                       0xFFC00108      /* Interrupt Reset Vector Address Register      */
+#define SIC_IMASK                       0xFFC0010C      /* Interrupt Mask Register                                      */
+#define SIC_IAR0                        0xFFC00110      /* Interrupt Assignment Register 0                      */
+#define SIC_IAR1                        0xFFC00114      /* Interrupt Assignment Register 1                      */
+#define SIC_IAR2                        0xFFC00118      /* Interrupt Assignment Register 2                      */
+#define SIC_IAR3                        0xFFC0011C      /* Interrupt Assignment Register 3                      */
+#define SIC_ISR                         0xFFC00120      /* Interrupt Status Register                            */
+#define SIC_IWR                         0xFFC00124      /* Interrupt Wakeup Register                            */
+
+/* Watchdog Timer                       (0xFFC00200 - 0xFFC002FF)                                                               */
+#define WDOG_CTL                        0xFFC00200      /* Watchdog Control Register                            */
+#define WDOG_CNT                        0xFFC00204      /* Watchdog Count Register                                      */
+#define WDOG_STAT                       0xFFC00208      /* Watchdog Status Register                                     */
+
+/* Real Time Clock              (0xFFC00300 - 0xFFC003FF)                                                                       */
+#define RTC_STAT                        0xFFC00300      /* RTC Status Register                                          */
+#define RTC_ICTL                        0xFFC00304      /* RTC Interrupt Control Register                       */
+#define RTC_ISTAT                       0xFFC00308      /* RTC Interrupt Status Register                        */
+#define RTC_SWCNT                       0xFFC0030C      /* RTC Stopwatch Count Register                         */
+#define RTC_ALARM                       0xFFC00310      /* RTC Alarm Time Register                                      */
+#define RTC_FAST                        0xFFC00314      /* RTC Prescaler Enable Register                        */
+#define RTC_PREN                        0xFFC00314      /* RTC Prescaler Enable Alternate Macro         */
+
+/* UART0 Controller             (0xFFC00400 - 0xFFC004FF)                                                                       */
+#define UART0_THR                       0xFFC00400      /* Transmit Holding register                            */
+#define UART0_RBR                       0xFFC00400      /* Receive Buffer register                                      */
+#define UART0_DLL                       0xFFC00400      /* Divisor Latch (Low-Byte)                                     */
+#define UART0_IER                       0xFFC00404      /* Interrupt Enable Register                            */
+#define UART0_DLH                       0xFFC00404      /* Divisor Latch (High-Byte)                            */
+#define UART0_IIR                       0xFFC00408      /* Interrupt Identification Register            */
+#define UART0_LCR                       0xFFC0040C      /* Line Control Register                                        */
+#define UART0_MCR                       0xFFC00410      /* Modem Control Register                                       */
+#define UART0_LSR                       0xFFC00414      /* Line Status Register                                         */
+#define UART0_MSR                       0xFFC00418      /* Modem Status Register                                        */
+#define UART0_SCR                       0xFFC0041C      /* SCR Scratch Register                                         */
+#define UART0_GCTL                      0xFFC00424      /* Global Control Register                                      */
+
+/* SPI Controller                       (0xFFC00500 - 0xFFC005FF)                                                               */
+#define SPI_CTL                         0xFFC00500      /* SPI Control Register                                         */
+#define SPI_FLG                         0xFFC00504      /* SPI Flag register                                            */
+#define SPI_STAT                        0xFFC00508      /* SPI Status register                                          */
+#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register            */
+#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register                     */
+#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register                                       */
+#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register                                     */
+
+/* TIMER0-7 Registers           (0xFFC00600 - 0xFFC006FF)                                                               */
+#define TIMER0_CONFIG           0xFFC00600      /* Timer 0 Configuration Register                       */
+#define TIMER0_COUNTER          0xFFC00604      /* Timer 0 Counter Register                                     */
+#define TIMER0_PERIOD           0xFFC00608      /* Timer 0 Period Register                                      */
+#define TIMER0_WIDTH            0xFFC0060C      /* Timer 0 Width Register                                       */
+
+#define TIMER1_CONFIG           0xFFC00610      /* Timer 1 Configuration Register                       */
+#define TIMER1_COUNTER          0xFFC00614      /* Timer 1 Counter Register                             */
+#define TIMER1_PERIOD           0xFFC00618      /* Timer 1 Period Register                              */
+#define TIMER1_WIDTH            0xFFC0061C      /* Timer 1 Width Register                               */
+
+#define TIMER2_CONFIG           0xFFC00620      /* Timer 2 Configuration Register                       */
+#define TIMER2_COUNTER          0xFFC00624      /* Timer 2 Counter Register                             */
+#define TIMER2_PERIOD           0xFFC00628      /* Timer 2 Period Register                              */
+#define TIMER2_WIDTH            0xFFC0062C      /* Timer 2 Width Register                               */
+
+#define TIMER3_CONFIG           0xFFC00630      /* Timer 3 Configuration Register                       */
+#define TIMER3_COUNTER          0xFFC00634      /* Timer 3 Counter Register                                     */
+#define TIMER3_PERIOD           0xFFC00638      /* Timer 3 Period Register                                      */
+#define TIMER3_WIDTH            0xFFC0063C      /* Timer 3 Width Register                                       */
+
+#define TIMER4_CONFIG           0xFFC00640      /* Timer 4 Configuration Register                       */
+#define TIMER4_COUNTER          0xFFC00644      /* Timer 4 Counter Register                             */
+#define TIMER4_PERIOD           0xFFC00648      /* Timer 4 Period Register                              */
+#define TIMER4_WIDTH            0xFFC0064C      /* Timer 4 Width Register                               */
+
+#define TIMER5_CONFIG           0xFFC00650      /* Timer 5 Configuration Register                       */
+#define TIMER5_COUNTER          0xFFC00654      /* Timer 5 Counter Register                             */
+#define TIMER5_PERIOD           0xFFC00658      /* Timer 5 Period Register                              */
+#define TIMER5_WIDTH            0xFFC0065C      /* Timer 5 Width Register                               */
+
+#define TIMER6_CONFIG           0xFFC00660      /* Timer 6 Configuration Register                       */
+#define TIMER6_COUNTER          0xFFC00664      /* Timer 6 Counter Register                             */
+#define TIMER6_PERIOD           0xFFC00668      /* Timer 6 Period Register                              */
+#define TIMER6_WIDTH            0xFFC0066C      /* Timer 6 Width Register                               */
+
+#define TIMER7_CONFIG           0xFFC00670      /* Timer 7 Configuration Register                       */
+#define TIMER7_COUNTER          0xFFC00674      /* Timer 7 Counter Register                             */
+#define TIMER7_PERIOD           0xFFC00678      /* Timer 7 Period Register                              */
+#define TIMER7_WIDTH            0xFFC0067C      /* Timer 7 Width Register                               */
+
+#define TIMER_ENABLE            0xFFC00680      /* Timer Enable Register                                        */
+#define TIMER_DISABLE           0xFFC00684      /* Timer Disable Register                                       */
+#define TIMER_STATUS            0xFFC00688      /* Timer Status Register                                        */
+
+/* General Purpose I/O Port F (0xFFC00700 - 0xFFC007FF)                                                                                         */
+#define PORTFIO                                 0xFFC00700      /* Port F I/O Pin State Specify Register                                */
+#define PORTFIO_CLEAR                   0xFFC00704      /* Port F I/O Peripheral Interrupt Clear Register               */
+#define PORTFIO_SET                             0xFFC00708      /* Port F I/O Peripheral Interrupt Set Register                 */
+#define PORTFIO_TOGGLE                  0xFFC0070C      /* Port F I/O Pin State Toggle Register                                 */
+#define PORTFIO_MASKA                   0xFFC00710      /* Port F I/O Mask State Specify Interrupt A Register   */
+#define PORTFIO_MASKA_CLEAR             0xFFC00714      /* Port F I/O Mask Disable Interrupt A Register                 */
+#define PORTFIO_MASKA_SET               0xFFC00718      /* Port F I/O Mask Enable Interrupt A Register                  */
+#define PORTFIO_MASKA_TOGGLE    0xFFC0071C      /* Port F I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTFIO_MASKB                   0xFFC00720      /* Port F I/O Mask State Specify Interrupt B Register   */
+#define PORTFIO_MASKB_CLEAR             0xFFC00724      /* Port F I/O Mask Disable Interrupt B Register                 */
+#define PORTFIO_MASKB_SET               0xFFC00728      /* Port F I/O Mask Enable Interrupt B Register                  */
+#define PORTFIO_MASKB_TOGGLE    0xFFC0072C      /* Port F I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTFIO_DIR                             0xFFC00730      /* Port F I/O Direction Register                                                */
+#define PORTFIO_POLAR                   0xFFC00734      /* Port F I/O Source Polarity Register                                  */
+#define PORTFIO_EDGE                    0xFFC00738      /* Port F I/O Source Sensitivity Register                               */
+#define PORTFIO_BOTH                    0xFFC0073C      /* Port F I/O Set on BOTH Edges Register                                */
+#define PORTFIO_INEN                    0xFFC00740      /* Port F I/O Input Enable Register                                     */
+
+/* SPORT0 Controller            (0xFFC00800 - 0xFFC008FF)                                                                               */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_TCLKDIV          0xFFC00808      /* SPORT0 Transmit Clock Divider                                        */
+#define SPORT0_TFSDIV           0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider                           */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register                                                      */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register                                                      */
+#define SPORT0_RCR1                     0xFFC00820      /* SPORT0 Transmit Configuration 1 Register                     */
+#define SPORT0_RCR2                     0xFFC00824      /* SPORT0 Transmit Configuration 2 Register                     */
+#define SPORT0_RCLKDIV          0xFFC00828      /* SPORT0 Receive Clock Divider                                         */
+#define SPORT0_RFSDIV           0xFFC0082C      /* SPORT0 Receive Frame Sync Divider                            */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register                                                       */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register                                      */
+#define SPORT0_MCMC1            0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1        */
+#define SPORT0_MCMC2            0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2        */
+#define SPORT0_MTCS0            0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0      */
+#define SPORT0_MTCS1            0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1      */
+#define SPORT0_MTCS2            0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2      */
+#define SPORT0_MTCS3            0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3      */
+#define SPORT0_MRCS0            0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0       */
+#define SPORT0_MRCS1            0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1       */
+#define SPORT0_MRCS2            0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2       */
+#define SPORT0_MRCS3            0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3       */
+
+/* SPORT1 Controller            (0xFFC00900 - 0xFFC009FF)                                                                               */
+#define SPORT1_TCR1                     0xFFC00900      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_TCR2                     0xFFC00904      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_TCLKDIV          0xFFC00908      /* SPORT1 Transmit Clock Divider                                        */
+#define SPORT1_TFSDIV           0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider                           */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register                                                      */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register                                                      */
+#define SPORT1_RCR1                     0xFFC00920      /* SPORT1 Transmit Configuration 1 Register                     */
+#define SPORT1_RCR2                     0xFFC00924      /* SPORT1 Transmit Configuration 2 Register                     */
+#define SPORT1_RCLKDIV          0xFFC00928      /* SPORT1 Receive Clock Divider                                         */
+#define SPORT1_RFSDIV           0xFFC0092C      /* SPORT1 Receive Frame Sync Divider                            */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register                                                       */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register                                      */
+#define SPORT1_MCMC1            0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1        */
+#define SPORT1_MCMC2            0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2        */
+#define SPORT1_MTCS0            0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0      */
+#define SPORT1_MTCS1            0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1      */
+#define SPORT1_MTCS2            0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2      */
+#define SPORT1_MTCS3            0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3      */
+#define SPORT1_MRCS0            0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0       */
+#define SPORT1_MRCS1            0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1       */
+#define SPORT1_MRCS2            0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2       */
+#define SPORT1_MRCS3            0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3       */
+
+/* External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF)                                                                */
+#define EBIU_AMGCTL                     0xFFC00A00      /* Asynchronous Memory Global Control Register  */
+#define EBIU_AMBCTL0            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0  */
+#define EBIU_AMBCTL1            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1  */
+#define EBIU_SDGCTL                     0xFFC00A10      /* SDRAM Global Control Register                                */
+#define EBIU_SDBCTL                     0xFFC00A14      /* SDRAM Bank Control Register                                  */
+#define EBIU_SDRRC                      0xFFC00A18      /* SDRAM Refresh Rate Control Register                  */
+#define EBIU_SDSTAT                     0xFFC00A1C      /* SDRAM Status Register                                                */
+
+/* DMA Traffic Control Registers                                                                                                        */
+#define DMA_TCPER                       0xFFC00B0C      /* Traffic Control Periods Register                     */
+#define DMA_TCCNT                       0xFFC00B10      /* Traffic Control Current Counts Register      */
+
+/* DMA Controller (0xFFC00C00 - 0xFFC00FFF)                                                                                                                     */
+#define DMA0_NEXT_DESC_PTR              0xFFC00C00      /* DMA Channel 0 Next Descriptor Pointer Register               */
+#define DMA0_START_ADDR                 0xFFC00C04      /* DMA Channel 0 Start Address Register                                 */
+#define DMA0_CONFIG                             0xFFC00C08      /* DMA Channel 0 Configuration Register                                 */
+#define DMA0_X_COUNT                    0xFFC00C10      /* DMA Channel 0 X Count Register                                               */
+#define DMA0_X_MODIFY                   0xFFC00C14      /* DMA Channel 0 X Modify Register                                              */
+#define DMA0_Y_COUNT                    0xFFC00C18      /* DMA Channel 0 Y Count Register                                               */
+#define DMA0_Y_MODIFY                   0xFFC00C1C      /* DMA Channel 0 Y Modify Register                                              */
+#define DMA0_CURR_DESC_PTR              0xFFC00C20      /* DMA Channel 0 Current Descriptor Pointer Register    */
+#define DMA0_CURR_ADDR                  0xFFC00C24      /* DMA Channel 0 Current Address Register                               */
+#define DMA0_IRQ_STATUS                 0xFFC00C28      /* DMA Channel 0 Interrupt/Status Register                              */
+#define DMA0_PERIPHERAL_MAP             0xFFC00C2C      /* DMA Channel 0 Peripheral Map Register                                */
+#define DMA0_CURR_X_COUNT               0xFFC00C30      /* DMA Channel 0 Current X Count Register                               */
+#define DMA0_CURR_Y_COUNT               0xFFC00C38      /* DMA Channel 0 Current Y Count Register                               */
+
+#define DMA1_NEXT_DESC_PTR              0xFFC00C40      /* DMA Channel 1 Next Descriptor Pointer Register               */
+#define DMA1_START_ADDR                 0xFFC00C44      /* DMA Channel 1 Start Address Register                                 */
+#define DMA1_CONFIG                             0xFFC00C48      /* DMA Channel 1 Configuration Register                                 */
+#define DMA1_X_COUNT                    0xFFC00C50      /* DMA Channel 1 X Count Register                                               */
+#define DMA1_X_MODIFY                   0xFFC00C54      /* DMA Channel 1 X Modify Register                                              */
+#define DMA1_Y_COUNT                    0xFFC00C58      /* DMA Channel 1 Y Count Register                                               */
+#define DMA1_Y_MODIFY                   0xFFC00C5C      /* DMA Channel 1 Y Modify Register                                              */
+#define DMA1_CURR_DESC_PTR              0xFFC00C60      /* DMA Channel 1 Current Descriptor Pointer Register    */
+#define DMA1_CURR_ADDR                  0xFFC00C64      /* DMA Channel 1 Current Address Register                               */
+#define DMA1_IRQ_STATUS                 0xFFC00C68      /* DMA Channel 1 Interrupt/Status Register                              */
+#define DMA1_PERIPHERAL_MAP             0xFFC00C6C      /* DMA Channel 1 Peripheral Map Register                                */
+#define DMA1_CURR_X_COUNT               0xFFC00C70      /* DMA Channel 1 Current X Count Register                               */
+#define DMA1_CURR_Y_COUNT               0xFFC00C78      /* DMA Channel 1 Current Y Count Register                               */
+
+#define DMA2_NEXT_DESC_PTR              0xFFC00C80      /* DMA Channel 2 Next Descriptor Pointer Register               */
+#define DMA2_START_ADDR                 0xFFC00C84      /* DMA Channel 2 Start Address Register                                 */
+#define DMA2_CONFIG                             0xFFC00C88      /* DMA Channel 2 Configuration Register                                 */
+#define DMA2_X_COUNT                    0xFFC00C90      /* DMA Channel 2 X Count Register                                               */
+#define DMA2_X_MODIFY                   0xFFC00C94      /* DMA Channel 2 X Modify Register                                              */
+#define DMA2_Y_COUNT                    0xFFC00C98      /* DMA Channel 2 Y Count Register                                               */
+#define DMA2_Y_MODIFY                   0xFFC00C9C      /* DMA Channel 2 Y Modify Register                                              */
+#define DMA2_CURR_DESC_PTR              0xFFC00CA0      /* DMA Channel 2 Current Descriptor Pointer Register    */
+#define DMA2_CURR_ADDR                  0xFFC00CA4      /* DMA Channel 2 Current Address Register                               */
+#define DMA2_IRQ_STATUS                 0xFFC00CA8      /* DMA Channel 2 Interrupt/Status Register                              */
+#define DMA2_PERIPHERAL_MAP             0xFFC00CAC      /* DMA Channel 2 Peripheral Map Register                                */
+#define DMA2_CURR_X_COUNT               0xFFC00CB0      /* DMA Channel 2 Current X Count Register                               */
+#define DMA2_CURR_Y_COUNT               0xFFC00CB8      /* DMA Channel 2 Current Y Count Register                               */
+
+#define DMA3_NEXT_DESC_PTR              0xFFC00CC0      /* DMA Channel 3 Next Descriptor Pointer Register               */
+#define DMA3_START_ADDR                 0xFFC00CC4      /* DMA Channel 3 Start Address Register                                 */
+#define DMA3_CONFIG                             0xFFC00CC8      /* DMA Channel 3 Configuration Register                                 */
+#define DMA3_X_COUNT                    0xFFC00CD0      /* DMA Channel 3 X Count Register                                               */
+#define DMA3_X_MODIFY                   0xFFC00CD4      /* DMA Channel 3 X Modify Register                                              */
+#define DMA3_Y_COUNT                    0xFFC00CD8      /* DMA Channel 3 Y Count Register                                               */
+#define DMA3_Y_MODIFY                   0xFFC00CDC      /* DMA Channel 3 Y Modify Register                                              */
+#define DMA3_CURR_DESC_PTR              0xFFC00CE0      /* DMA Channel 3 Current Descriptor Pointer Register    */
+#define DMA3_CURR_ADDR                  0xFFC00CE4      /* DMA Channel 3 Current Address Register                               */
+#define DMA3_IRQ_STATUS                 0xFFC00CE8      /* DMA Channel 3 Interrupt/Status Register                              */
+#define DMA3_PERIPHERAL_MAP             0xFFC00CEC      /* DMA Channel 3 Peripheral Map Register                                */
+#define DMA3_CURR_X_COUNT               0xFFC00CF0      /* DMA Channel 3 Current X Count Register                               */
+#define DMA3_CURR_Y_COUNT               0xFFC00CF8      /* DMA Channel 3 Current Y Count Register                               */
+
+#define DMA4_NEXT_DESC_PTR              0xFFC00D00      /* DMA Channel 4 Next Descriptor Pointer Register               */
+#define DMA4_START_ADDR                 0xFFC00D04      /* DMA Channel 4 Start Address Register                                 */
+#define DMA4_CONFIG                             0xFFC00D08      /* DMA Channel 4 Configuration Register                                 */
+#define DMA4_X_COUNT                    0xFFC00D10      /* DMA Channel 4 X Count Register                                               */
+#define DMA4_X_MODIFY                   0xFFC00D14      /* DMA Channel 4 X Modify Register                                              */
+#define DMA4_Y_COUNT                    0xFFC00D18      /* DMA Channel 4 Y Count Register                                               */
+#define DMA4_Y_MODIFY                   0xFFC00D1C      /* DMA Channel 4 Y Modify Register                                              */
+#define DMA4_CURR_DESC_PTR              0xFFC00D20      /* DMA Channel 4 Current Descriptor Pointer Register    */
+#define DMA4_CURR_ADDR                  0xFFC00D24      /* DMA Channel 4 Current Address Register                               */
+#define DMA4_IRQ_STATUS                 0xFFC00D28      /* DMA Channel 4 Interrupt/Status Register                              */
+#define DMA4_PERIPHERAL_MAP             0xFFC00D2C      /* DMA Channel 4 Peripheral Map Register                                */
+#define DMA4_CURR_X_COUNT               0xFFC00D30      /* DMA Channel 4 Current X Count Register                               */
+#define DMA4_CURR_Y_COUNT               0xFFC00D38      /* DMA Channel 4 Current Y Count Register                               */
+
+#define DMA5_NEXT_DESC_PTR              0xFFC00D40      /* DMA Channel 5 Next Descriptor Pointer Register               */
+#define DMA5_START_ADDR                 0xFFC00D44      /* DMA Channel 5 Start Address Register                                 */
+#define DMA5_CONFIG                             0xFFC00D48      /* DMA Channel 5 Configuration Register                                 */
+#define DMA5_X_COUNT                    0xFFC00D50      /* DMA Channel 5 X Count Register                                               */
+#define DMA5_X_MODIFY                   0xFFC00D54      /* DMA Channel 5 X Modify Register                                              */
+#define DMA5_Y_COUNT                    0xFFC00D58      /* DMA Channel 5 Y Count Register                                               */
+#define DMA5_Y_MODIFY                   0xFFC00D5C      /* DMA Channel 5 Y Modify Register                                              */
+#define DMA5_CURR_DESC_PTR              0xFFC00D60      /* DMA Channel 5 Current Descriptor Pointer Register    */
+#define DMA5_CURR_ADDR                  0xFFC00D64      /* DMA Channel 5 Current Address Register                               */
+#define DMA5_IRQ_STATUS                 0xFFC00D68      /* DMA Channel 5 Interrupt/Status Register                              */
+#define DMA5_PERIPHERAL_MAP             0xFFC00D6C      /* DMA Channel 5 Peripheral Map Register                                */
+#define DMA5_CURR_X_COUNT               0xFFC00D70      /* DMA Channel 5 Current X Count Register                               */
+#define DMA5_CURR_Y_COUNT               0xFFC00D78      /* DMA Channel 5 Current Y Count Register                               */
+
+#define DMA6_NEXT_DESC_PTR              0xFFC00D80      /* DMA Channel 6 Next Descriptor Pointer Register               */
+#define DMA6_START_ADDR                 0xFFC00D84      /* DMA Channel 6 Start Address Register                                 */
+#define DMA6_CONFIG                             0xFFC00D88      /* DMA Channel 6 Configuration Register                                 */
+#define DMA6_X_COUNT                    0xFFC00D90      /* DMA Channel 6 X Count Register                                               */
+#define DMA6_X_MODIFY                   0xFFC00D94      /* DMA Channel 6 X Modify Register                                              */
+#define DMA6_Y_COUNT                    0xFFC00D98      /* DMA Channel 6 Y Count Register                                               */
+#define DMA6_Y_MODIFY                   0xFFC00D9C      /* DMA Channel 6 Y Modify Register                                              */
+#define DMA6_CURR_DESC_PTR              0xFFC00DA0      /* DMA Channel 6 Current Descriptor Pointer Register    */
+#define DMA6_CURR_ADDR                  0xFFC00DA4      /* DMA Channel 6 Current Address Register                               */
+#define DMA6_IRQ_STATUS                 0xFFC00DA8      /* DMA Channel 6 Interrupt/Status Register                              */
+#define DMA6_PERIPHERAL_MAP             0xFFC00DAC      /* DMA Channel 6 Peripheral Map Register                                */
+#define DMA6_CURR_X_COUNT               0xFFC00DB0      /* DMA Channel 6 Current X Count Register                               */
+#define DMA6_CURR_Y_COUNT               0xFFC00DB8      /* DMA Channel 6 Current Y Count Register                               */
+
+#define DMA7_NEXT_DESC_PTR              0xFFC00DC0      /* DMA Channel 7 Next Descriptor Pointer Register               */
+#define DMA7_START_ADDR                 0xFFC00DC4      /* DMA Channel 7 Start Address Register                                 */
+#define DMA7_CONFIG                             0xFFC00DC8      /* DMA Channel 7 Configuration Register                                 */
+#define DMA7_X_COUNT                    0xFFC00DD0      /* DMA Channel 7 X Count Register                                               */
+#define DMA7_X_MODIFY                   0xFFC00DD4      /* DMA Channel 7 X Modify Register                                              */
+#define DMA7_Y_COUNT                    0xFFC00DD8      /* DMA Channel 7 Y Count Register                                               */
+#define DMA7_Y_MODIFY                   0xFFC00DDC      /* DMA Channel 7 Y Modify Register                                              */
+#define DMA7_CURR_DESC_PTR              0xFFC00DE0      /* DMA Channel 7 Current Descriptor Pointer Register    */
+#define DMA7_CURR_ADDR                  0xFFC00DE4      /* DMA Channel 7 Current Address Register                               */
+#define DMA7_IRQ_STATUS                 0xFFC00DE8      /* DMA Channel 7 Interrupt/Status Register                              */
+#define DMA7_PERIPHERAL_MAP             0xFFC00DEC      /* DMA Channel 7 Peripheral Map Register                                */
+#define DMA7_CURR_X_COUNT               0xFFC00DF0      /* DMA Channel 7 Current X Count Register                               */
+#define DMA7_CURR_Y_COUNT               0xFFC00DF8      /* DMA Channel 7 Current Y Count Register                               */
+
+#define DMA8_NEXT_DESC_PTR              0xFFC00E00      /* DMA Channel 8 Next Descriptor Pointer Register               */
+#define DMA8_START_ADDR                 0xFFC00E04      /* DMA Channel 8 Start Address Register                                 */
+#define DMA8_CONFIG                             0xFFC00E08      /* DMA Channel 8 Configuration Register                                 */
+#define DMA8_X_COUNT                    0xFFC00E10      /* DMA Channel 8 X Count Register                                               */
+#define DMA8_X_MODIFY                   0xFFC00E14      /* DMA Channel 8 X Modify Register                                              */
+#define DMA8_Y_COUNT                    0xFFC00E18      /* DMA Channel 8 Y Count Register                                               */
+#define DMA8_Y_MODIFY                   0xFFC00E1C      /* DMA Channel 8 Y Modify Register                                              */
+#define DMA8_CURR_DESC_PTR              0xFFC00E20      /* DMA Channel 8 Current Descriptor Pointer Register    */
+#define DMA8_CURR_ADDR                  0xFFC00E24      /* DMA Channel 8 Current Address Register                               */
+#define DMA8_IRQ_STATUS                 0xFFC00E28      /* DMA Channel 8 Interrupt/Status Register                              */
+#define DMA8_PERIPHERAL_MAP             0xFFC00E2C      /* DMA Channel 8 Peripheral Map Register                                */
+#define DMA8_CURR_X_COUNT               0xFFC00E30      /* DMA Channel 8 Current X Count Register                               */
+#define DMA8_CURR_Y_COUNT               0xFFC00E38      /* DMA Channel 8 Current Y Count Register                               */
+
+#define DMA9_NEXT_DESC_PTR              0xFFC00E40      /* DMA Channel 9 Next Descriptor Pointer Register               */
+#define DMA9_START_ADDR                 0xFFC00E44      /* DMA Channel 9 Start Address Register                                 */
+#define DMA9_CONFIG                             0xFFC00E48      /* DMA Channel 9 Configuration Register                                 */
+#define DMA9_X_COUNT                    0xFFC00E50      /* DMA Channel 9 X Count Register                                               */
+#define DMA9_X_MODIFY                   0xFFC00E54      /* DMA Channel 9 X Modify Register                                              */
+#define DMA9_Y_COUNT                    0xFFC00E58      /* DMA Channel 9 Y Count Register                                               */
+#define DMA9_Y_MODIFY                   0xFFC00E5C      /* DMA Channel 9 Y Modify Register                                              */
+#define DMA9_CURR_DESC_PTR              0xFFC00E60      /* DMA Channel 9 Current Descriptor Pointer Register    */
+#define DMA9_CURR_ADDR                  0xFFC00E64      /* DMA Channel 9 Current Address Register                               */
+#define DMA9_IRQ_STATUS                 0xFFC00E68      /* DMA Channel 9 Interrupt/Status Register                              */
+#define DMA9_PERIPHERAL_MAP             0xFFC00E6C      /* DMA Channel 9 Peripheral Map Register                                */
+#define DMA9_CURR_X_COUNT               0xFFC00E70      /* DMA Channel 9 Current X Count Register                               */
+#define DMA9_CURR_Y_COUNT               0xFFC00E78      /* DMA Channel 9 Current Y Count Register                               */
+
+#define DMA10_NEXT_DESC_PTR             0xFFC00E80      /* DMA Channel 10 Next Descriptor Pointer Register              */
+#define DMA10_START_ADDR                0xFFC00E84      /* DMA Channel 10 Start Address Register                                */
+#define DMA10_CONFIG                    0xFFC00E88      /* DMA Channel 10 Configuration Register                                */
+#define DMA10_X_COUNT                   0xFFC00E90      /* DMA Channel 10 X Count Register                                              */
+#define DMA10_X_MODIFY                  0xFFC00E94      /* DMA Channel 10 X Modify Register                                             */
+#define DMA10_Y_COUNT                   0xFFC00E98      /* DMA Channel 10 Y Count Register                                              */
+#define DMA10_Y_MODIFY                  0xFFC00E9C      /* DMA Channel 10 Y Modify Register                                             */
+#define DMA10_CURR_DESC_PTR             0xFFC00EA0      /* DMA Channel 10 Current Descriptor Pointer Register   */
+#define DMA10_CURR_ADDR                 0xFFC00EA4      /* DMA Channel 10 Current Address Register                              */
+#define DMA10_IRQ_STATUS                0xFFC00EA8      /* DMA Channel 10 Interrupt/Status Register                             */
+#define DMA10_PERIPHERAL_MAP    0xFFC00EAC      /* DMA Channel 10 Peripheral Map Register                               */
+#define DMA10_CURR_X_COUNT              0xFFC00EB0      /* DMA Channel 10 Current X Count Register                              */
+#define DMA10_CURR_Y_COUNT              0xFFC00EB8      /* DMA Channel 10 Current Y Count Register                              */
+
+#define DMA11_NEXT_DESC_PTR             0xFFC00EC0      /* DMA Channel 11 Next Descriptor Pointer Register              */
+#define DMA11_START_ADDR                0xFFC00EC4      /* DMA Channel 11 Start Address Register                                */
+#define DMA11_CONFIG                    0xFFC00EC8      /* DMA Channel 11 Configuration Register                                */
+#define DMA11_X_COUNT                   0xFFC00ED0      /* DMA Channel 11 X Count Register                                              */
+#define DMA11_X_MODIFY                  0xFFC00ED4      /* DMA Channel 11 X Modify Register                                             */
+#define DMA11_Y_COUNT                   0xFFC00ED8      /* DMA Channel 11 Y Count Register                                              */
+#define DMA11_Y_MODIFY                  0xFFC00EDC      /* DMA Channel 11 Y Modify Register                                             */
+#define DMA11_CURR_DESC_PTR             0xFFC00EE0      /* DMA Channel 11 Current Descriptor Pointer Register   */
+#define DMA11_CURR_ADDR                 0xFFC00EE4      /* DMA Channel 11 Current Address Register                              */
+#define DMA11_IRQ_STATUS                0xFFC00EE8      /* DMA Channel 11 Interrupt/Status Register                             */
+#define DMA11_PERIPHERAL_MAP    0xFFC00EEC      /* DMA Channel 11 Peripheral Map Register                               */
+#define DMA11_CURR_X_COUNT              0xFFC00EF0      /* DMA Channel 11 Current X Count Register                              */
+#define DMA11_CURR_Y_COUNT              0xFFC00EF8      /* DMA Channel 11 Current Y Count Register                              */
+
+#define MDMA_D0_NEXT_DESC_PTR   0xFFC00F00      /* MemDMA Stream 0 Destination Next Descriptor Pointer Register         */
+#define MDMA_D0_START_ADDR              0xFFC00F04      /* MemDMA Stream 0 Destination Start Address Register                           */
+#define MDMA_D0_CONFIG                  0xFFC00F08      /* MemDMA Stream 0 Destination Configuration Register                           */
+#define MDMA_D0_X_COUNT                 0xFFC00F10      /* MemDMA Stream 0 Destination X Count Register                                         */
+#define MDMA_D0_X_MODIFY                0xFFC00F14      /* MemDMA Stream 0 Destination X Modify Register                                        */
+#define MDMA_D0_Y_COUNT                 0xFFC00F18      /* MemDMA Stream 0 Destination Y Count Register                                         */
+#define MDMA_D0_Y_MODIFY                0xFFC00F1C      /* MemDMA Stream 0 Destination Y Modify Register                                        */
+#define MDMA_D0_CURR_DESC_PTR   0xFFC00F20      /* MemDMA Stream 0 Destination Current Descriptor Pointer Register      */
+#define MDMA_D0_CURR_ADDR               0xFFC00F24      /* MemDMA Stream 0 Destination Current Address Register                         */
+#define MDMA_D0_IRQ_STATUS              0xFFC00F28      /* MemDMA Stream 0 Destination Interrupt/Status Register                        */
+#define MDMA_D0_PERIPHERAL_MAP  0xFFC00F2C      /* MemDMA Stream 0 Destination Peripheral Map Register                          */
+#define MDMA_D0_CURR_X_COUNT    0xFFC00F30      /* MemDMA Stream 0 Destination Current X Count Register                         */
+#define MDMA_D0_CURR_Y_COUNT    0xFFC00F38      /* MemDMA Stream 0 Destination Current Y Count Register                         */
+
+#define MDMA_S0_NEXT_DESC_PTR   0xFFC00F40      /* MemDMA Stream 0 Source Next Descriptor Pointer Register                      */
+#define MDMA_S0_START_ADDR              0xFFC00F44      /* MemDMA Stream 0 Source Start Address Register                                        */
+#define MDMA_S0_CONFIG                  0xFFC00F48      /* MemDMA Stream 0 Source Configuration Register                                        */
+#define MDMA_S0_X_COUNT                 0xFFC00F50      /* MemDMA Stream 0 Source X Count Register                                                      */
+#define MDMA_S0_X_MODIFY                0xFFC00F54      /* MemDMA Stream 0 Source X Modify Register                                                     */
+#define MDMA_S0_Y_COUNT                 0xFFC00F58      /* MemDMA Stream 0 Source Y Count Register                                                      */
+#define MDMA_S0_Y_MODIFY                0xFFC00F5C      /* MemDMA Stream 0 Source Y Modify Register                                                     */
+#define MDMA_S0_CURR_DESC_PTR   0xFFC00F60      /* MemDMA Stream 0 Source Current Descriptor Pointer Register           */
+#define MDMA_S0_CURR_ADDR               0xFFC00F64      /* MemDMA Stream 0 Source Current Address Register                                      */
+#define MDMA_S0_IRQ_STATUS              0xFFC00F68      /* MemDMA Stream 0 Source Interrupt/Status Register                                     */
+#define MDMA_S0_PERIPHERAL_MAP  0xFFC00F6C      /* MemDMA Stream 0 Source Peripheral Map Register                                       */
+#define MDMA_S0_CURR_X_COUNT    0xFFC00F70      /* MemDMA Stream 0 Source Current X Count Register                                      */
+#define MDMA_S0_CURR_Y_COUNT    0xFFC00F78      /* MemDMA Stream 0 Source Current Y Count Register                                      */
+
+#define MDMA_D1_NEXT_DESC_PTR   0xFFC00F80      /* MemDMA Stream 1 Destination Next Descriptor Pointer Register         */
+#define MDMA_D1_START_ADDR              0xFFC00F84      /* MemDMA Stream 1 Destination Start Address Register                           */
+#define MDMA_D1_CONFIG                  0xFFC00F88      /* MemDMA Stream 1 Destination Configuration Register                           */
+#define MDMA_D1_X_COUNT                 0xFFC00F90      /* MemDMA Stream 1 Destination X Count Register                                         */
+#define MDMA_D1_X_MODIFY                0xFFC00F94      /* MemDMA Stream 1 Destination X Modify Register                                        */
+#define MDMA_D1_Y_COUNT                 0xFFC00F98      /* MemDMA Stream 1 Destination Y Count Register                                         */
+#define MDMA_D1_Y_MODIFY                0xFFC00F9C      /* MemDMA Stream 1 Destination Y Modify Register                                        */
+#define MDMA_D1_CURR_DESC_PTR   0xFFC00FA0      /* MemDMA Stream 1 Destination Current Descriptor Pointer Register      */
+#define MDMA_D1_CURR_ADDR               0xFFC00FA4      /* MemDMA Stream 1 Destination Current Address Register                         */
+#define MDMA_D1_IRQ_STATUS              0xFFC00FA8      /* MemDMA Stream 1 Destination Interrupt/Status Register                        */
+#define MDMA_D1_PERIPHERAL_MAP  0xFFC00FAC      /* MemDMA Stream 1 Destination Peripheral Map Register                          */
+#define MDMA_D1_CURR_X_COUNT    0xFFC00FB0      /* MemDMA Stream 1 Destination Current X Count Register                         */
+#define MDMA_D1_CURR_Y_COUNT    0xFFC00FB8      /* MemDMA Stream 1 Destination Current Y Count Register                         */
+
+#define MDMA_S1_NEXT_DESC_PTR   0xFFC00FC0      /* MemDMA Stream 1 Source Next Descriptor Pointer Register                      */
+#define MDMA_S1_START_ADDR              0xFFC00FC4      /* MemDMA Stream 1 Source Start Address Register                                        */
+#define MDMA_S1_CONFIG                  0xFFC00FC8      /* MemDMA Stream 1 Source Configuration Register                                        */
+#define MDMA_S1_X_COUNT                 0xFFC00FD0      /* MemDMA Stream 1 Source X Count Register                                                      */
+#define MDMA_S1_X_MODIFY                0xFFC00FD4      /* MemDMA Stream 1 Source X Modify Register                                                     */
+#define MDMA_S1_Y_COUNT                 0xFFC00FD8      /* MemDMA Stream 1 Source Y Count Register                                                      */
+#define MDMA_S1_Y_MODIFY                0xFFC00FDC      /* MemDMA Stream 1 Source Y Modify Register                                                     */
+#define MDMA_S1_CURR_DESC_PTR   0xFFC00FE0      /* MemDMA Stream 1 Source Current Descriptor Pointer Register           */
+#define MDMA_S1_CURR_ADDR               0xFFC00FE4      /* MemDMA Stream 1 Source Current Address Register                                      */
+#define MDMA_S1_IRQ_STATUS              0xFFC00FE8      /* MemDMA Stream 1 Source Interrupt/Status Register                                     */
+#define MDMA_S1_PERIPHERAL_MAP  0xFFC00FEC      /* MemDMA Stream 1 Source Peripheral Map Register                                       */
+#define MDMA_S1_CURR_X_COUNT    0xFFC00FF0      /* MemDMA Stream 1 Source Current X Count Register                                      */
+#define MDMA_S1_CURR_Y_COUNT    0xFFC00FF8      /* MemDMA Stream 1 Source Current Y Count Register                                      */
+
+/* Parallel Peripheral Interface (0xFFC01000 - 0xFFC010FF)                              */
+#define PPI_CONTROL                     0xFFC01000      /* PPI Control Register                 */
+#define PPI_STATUS                      0xFFC01004      /* PPI Status Register                  */
+#define PPI_COUNT                       0xFFC01008      /* PPI Transfer Count Register  */
+#define PPI_DELAY                       0xFFC0100C      /* PPI Delay Count Register             */
+#define PPI_FRAME                       0xFFC01010      /* PPI Frame Length Register    */
+
+/* Two-Wire Interface           (0xFFC01400 - 0xFFC014FF)                                                               */
+#define TWI_CLKDIV                      0xFFC01400      /* Serial Clock Divider Register                        */
+#define TWI_CONTROL                     0xFFC01404      /* TWI Control Register                                         */
+#define TWI_SLAVE_CTL           0xFFC01408      /* Slave Mode Control Register                          */
+#define TWI_SLAVE_STAT          0xFFC0140C      /* Slave Mode Status Register                           */
+#define TWI_SLAVE_ADDR          0xFFC01410      /* Slave Mode Address Register                          */
+#define TWI_MASTER_CTL          0xFFC01414      /* Master Mode Control Register                         */
+#define TWI_MASTER_STAT         0xFFC01418      /* Master Mode Status Register                          */
+#define TWI_MASTER_ADDR         0xFFC0141C      /* Master Mode Address Register                         */
+#define TWI_INT_STAT            0xFFC01420      /* TWI Interrupt Status Register                        */
+#define TWI_INT_MASK            0xFFC01424      /* TWI Master Interrupt Mask Register           */
+#define TWI_FIFO_CTL            0xFFC01428      /* FIFO Control Register                                        */
+#define TWI_FIFO_STAT           0xFFC0142C      /* FIFO Status Register                                         */
+#define TWI_XMT_DATA8           0xFFC01480      /* FIFO Transmit Data Single Byte Register      */
+#define TWI_XMT_DATA16          0xFFC01484      /* FIFO Transmit Data Double Byte Register      */
+#define TWI_RCV_DATA8           0xFFC01488      /* FIFO Receive Data Single Byte Register       */
+#define TWI_RCV_DATA16          0xFFC0148C      /* FIFO Receive Data Double Byte Register       */
+
+/* General Purpose I/O Port G (0xFFC01500 - 0xFFC015FF)                                                                                         */
+#define PORTGIO                                 0xFFC01500      /* Port G I/O Pin State Specify Register                                */
+#define PORTGIO_CLEAR                   0xFFC01504      /* Port G I/O Peripheral Interrupt Clear Register               */
+#define PORTGIO_SET                             0xFFC01508      /* Port G I/O Peripheral Interrupt Set Register                 */
+#define PORTGIO_TOGGLE                  0xFFC0150C      /* Port G I/O Pin State Toggle Register                                 */
+#define PORTGIO_MASKA                   0xFFC01510      /* Port G I/O Mask State Specify Interrupt A Register   */
+#define PORTGIO_MASKA_CLEAR             0xFFC01514      /* Port G I/O Mask Disable Interrupt A Register                 */
+#define PORTGIO_MASKA_SET               0xFFC01518      /* Port G I/O Mask Enable Interrupt A Register                  */
+#define PORTGIO_MASKA_TOGGLE    0xFFC0151C      /* Port G I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTGIO_MASKB                   0xFFC01520      /* Port G I/O Mask State Specify Interrupt B Register   */
+#define PORTGIO_MASKB_CLEAR             0xFFC01524      /* Port G I/O Mask Disable Interrupt B Register                 */
+#define PORTGIO_MASKB_SET               0xFFC01528      /* Port G I/O Mask Enable Interrupt B Register                  */
+#define PORTGIO_MASKB_TOGGLE    0xFFC0152C      /* Port G I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTGIO_DIR                             0xFFC01530      /* Port G I/O Direction Register                                                */
+#define PORTGIO_POLAR                   0xFFC01534      /* Port G I/O Source Polarity Register                                  */
+#define PORTGIO_EDGE                    0xFFC01538      /* Port G I/O Source Sensitivity Register                               */
+#define PORTGIO_BOTH                    0xFFC0153C      /* Port G I/O Set on BOTH Edges Register                                */
+#define PORTGIO_INEN                    0xFFC01540      /* Port G I/O Input Enable Register                                             */
+
+/* General Purpose I/O Port H (0xFFC01700 - 0xFFC017FF)                                                                                         */
+#define PORTHIO                                 0xFFC01700      /* Port H I/O Pin State Specify Register                                */
+#define PORTHIO_CLEAR                   0xFFC01704      /* Port H I/O Peripheral Interrupt Clear Register               */
+#define PORTHIO_SET                             0xFFC01708      /* Port H I/O Peripheral Interrupt Set Register                 */
+#define PORTHIO_TOGGLE                  0xFFC0170C      /* Port H I/O Pin State Toggle Register                                 */
+#define PORTHIO_MASKA                   0xFFC01710      /* Port H I/O Mask State Specify Interrupt A Register   */
+#define PORTHIO_MASKA_CLEAR             0xFFC01714      /* Port H I/O Mask Disable Interrupt A Register                 */
+#define PORTHIO_MASKA_SET               0xFFC01718      /* Port H I/O Mask Enable Interrupt A Register                  */
+#define PORTHIO_MASKA_TOGGLE    0xFFC0171C      /* Port H I/O Mask Toggle Enable Interrupt A Register   */
+#define PORTHIO_MASKB                   0xFFC01720      /* Port H I/O Mask State Specify Interrupt B Register   */
+#define PORTHIO_MASKB_CLEAR             0xFFC01724      /* Port H I/O Mask Disable Interrupt B Register                 */
+#define PORTHIO_MASKB_SET               0xFFC01728      /* Port H I/O Mask Enable Interrupt B Register                  */
+#define PORTHIO_MASKB_TOGGLE    0xFFC0172C      /* Port H I/O Mask Toggle Enable Interrupt B Register   */
+#define PORTHIO_DIR                             0xFFC01730      /* Port H I/O Direction Register                                                */
+#define PORTHIO_POLAR                   0xFFC01734      /* Port H I/O Source Polarity Register                                  */
+#define PORTHIO_EDGE                    0xFFC01738      /* Port H I/O Source Sensitivity Register                               */
+#define PORTHIO_BOTH                    0xFFC0173C      /* Port H I/O Set on BOTH Edges Register                                */
+#define PORTHIO_INEN                    0xFFC01740      /* Port H I/O Input Enable Register                                             */
+
+/* UART1 Controller             (0xFFC02000 - 0xFFC020FF)                                                               */
+#define UART1_THR                       0xFFC02000      /* Transmit Holding register                    */
+#define UART1_RBR                       0xFFC02000      /* Receive Buffer register                              */
+#define UART1_DLL                       0xFFC02000      /* Divisor Latch (Low-Byte)                             */
+#define UART1_IER                       0xFFC02004      /* Interrupt Enable Register                    */
+#define UART1_DLH                       0xFFC02004      /* Divisor Latch (High-Byte)                    */
+#define UART1_IIR                       0xFFC02008      /* Interrupt Identification Register    */
+#define UART1_LCR                       0xFFC0200C      /* Line Control Register                                */
+#define UART1_MCR                       0xFFC02010      /* Modem Control Register                               */
+#define UART1_LSR                       0xFFC02014      /* Line Status Register                                 */
+#define UART1_MSR                       0xFFC02018      /* Modem Status Register                                */
+#define UART1_SCR                       0xFFC0201C      /* SCR Scratch Register                                 */
+#define UART1_GCTL                      0xFFC02024      /* Global Control Register                              */
+
+/* CAN Controller               (0xFFC02A00 - 0xFFC02FFF)                                                                               */
+/* For Mailboxes 0-15                                                                                                                                   */
+#define CAN_MC1                         0xFFC02A00      /* Mailbox config reg 1                                                 */
+#define CAN_MD1                         0xFFC02A04      /* Mailbox direction reg 1                                              */
+#define CAN_TRS1                        0xFFC02A08      /* Transmit Request Set reg 1                                   */
+#define CAN_TRR1                        0xFFC02A0C      /* Transmit Request Reset reg 1                                 */
+#define CAN_TA1                         0xFFC02A10      /* Transmit Acknowledge reg 1                                   */
+#define CAN_AA1                         0xFFC02A14      /* Transmit Abort Acknowledge reg 1                             */
+#define CAN_RMP1                        0xFFC02A18      /* Receive Message Pending reg 1                                */
+#define CAN_RML1                        0xFFC02A1C      /* Receive Message Lost reg 1                                   */
+#define CAN_MBTIF1                      0xFFC02A20      /* Mailbox Transmit Interrupt Flag reg 1                */
+#define CAN_MBRIF1                      0xFFC02A24      /* Mailbox Receive  Interrupt Flag reg 1                */
+#define CAN_MBIM1                       0xFFC02A28      /* Mailbox Interrupt Mask reg 1                                 */
+#define CAN_RFH1                        0xFFC02A2C      /* Remote Frame Handling reg 1                                  */
+#define CAN_OPSS1                       0xFFC02A30      /* Overwrite Protection Single Shot Xmit reg 1  */
+
+/* For Mailboxes 16-31                                                                                                                                  */
+#define CAN_MC2                         0xFFC02A40      /* Mailbox config reg 2                                                 */
+#define CAN_MD2                         0xFFC02A44      /* Mailbox direction reg 2                                              */
+#define CAN_TRS2                        0xFFC02A48      /* Transmit Request Set reg 2                                   */
+#define CAN_TRR2                        0xFFC02A4C      /* Transmit Request Reset reg 2                                 */
+#define CAN_TA2                         0xFFC02A50      /* Transmit Acknowledge reg 2                                   */
+#define CAN_AA2                         0xFFC02A54      /* Transmit Abort Acknowledge reg 2                             */
+#define CAN_RMP2                        0xFFC02A58      /* Receive Message Pending reg 2                                */
+#define CAN_RML2                        0xFFC02A5C      /* Receive Message Lost reg 2                                   */
+#define CAN_MBTIF2                      0xFFC02A60      /* Mailbox Transmit Interrupt Flag reg 2                */
+#define CAN_MBRIF2                      0xFFC02A64      /* Mailbox Receive  Interrupt Flag reg 2                */
+#define CAN_MBIM2                       0xFFC02A68      /* Mailbox Interrupt Mask reg 2                                 */
+#define CAN_RFH2                        0xFFC02A6C      /* Remote Frame Handling reg 2                                  */
+#define CAN_OPSS2                       0xFFC02A70      /* Overwrite Protection Single Shot Xmit reg 2  */
+
+/* CAN Configuration, Control, and Status Registers                                                                             */
+#define CAN_CLOCK                       0xFFC02A80      /* Bit Timing Configuration register 0                  */
+#define CAN_TIMING                      0xFFC02A84      /* Bit Timing Configuration register 1                  */
+#define CAN_DEBUG                       0xFFC02A88      /* Debug Register                                                               */
+#define CAN_STATUS                      0xFFC02A8C      /* Global Status Register                                               */
+#define CAN_CEC                         0xFFC02A90      /* Error Counter Register                                               */
+#define CAN_GIS                         0xFFC02A94      /* Global Interrupt Status Register                             */
+#define CAN_GIM                         0xFFC02A98      /* Global Interrupt Mask Register                               */
+#define CAN_GIF                         0xFFC02A9C      /* Global Interrupt Flag Register                               */
+#define CAN_CONTROL                     0xFFC02AA0      /* Master Control Register                                              */
+#define CAN_INTR                        0xFFC02AA4      /* Interrupt Pending Register                                   */
+#define CAN_SFCMVER                     0xFFC02AA8      /* Version Code Register                                                */
+#define CAN_MBTD                        0xFFC02AAC      /* Mailbox Temporary Disable Feature                    */
+#define CAN_EWR                         0xFFC02AB0      /* Programmable Warning Level                                   */
+#define CAN_ESR                         0xFFC02AB4      /* Error Status Register                                                */
+#define CAN_UCREG                       0xFFC02AC0      /* Universal Counter Register/Capture Register  */
+#define CAN_UCCNT                       0xFFC02AC4      /* Universal Counter                                                    */
+#define CAN_UCRC                        0xFFC02AC8      /* Universal Counter Force Reload Register              */
+#define CAN_UCCNF                       0xFFC02ACC      /* Universal Counter Configuration Register             */
+
+/* Mailbox Acceptance Masks                                                                                             */
+#define CAN_AM00L                       0xFFC02B00      /* Mailbox 0 Low Acceptance Mask        */
+#define CAN_AM00H                       0xFFC02B04      /* Mailbox 0 High Acceptance Mask       */
+#define CAN_AM01L                       0xFFC02B08      /* Mailbox 1 Low Acceptance Mask        */
+#define CAN_AM01H                       0xFFC02B0C      /* Mailbox 1 High Acceptance Mask       */
+#define CAN_AM02L                       0xFFC02B10      /* Mailbox 2 Low Acceptance Mask        */
+#define CAN_AM02H                       0xFFC02B14      /* Mailbox 2 High Acceptance Mask       */
+#define CAN_AM03L                       0xFFC02B18      /* Mailbox 3 Low Acceptance Mask        */
+#define CAN_AM03H                       0xFFC02B1C      /* Mailbox 3 High Acceptance Mask       */
+#define CAN_AM04L                       0xFFC02B20      /* Mailbox 4 Low Acceptance Mask        */
+#define CAN_AM04H                       0xFFC02B24      /* Mailbox 4 High Acceptance Mask       */
+#define CAN_AM05L                       0xFFC02B28      /* Mailbox 5 Low Acceptance Mask        */
+#define CAN_AM05H                       0xFFC02B2C      /* Mailbox 5 High Acceptance Mask       */
+#define CAN_AM06L                       0xFFC02B30      /* Mailbox 6 Low Acceptance Mask        */
+#define CAN_AM06H                       0xFFC02B34      /* Mailbox 6 High Acceptance Mask       */
+#define CAN_AM07L                       0xFFC02B38      /* Mailbox 7 Low Acceptance Mask        */
+#define CAN_AM07H                       0xFFC02B3C      /* Mailbox 7 High Acceptance Mask       */
+#define CAN_AM08L                       0xFFC02B40      /* Mailbox 8 Low Acceptance Mask        */
+#define CAN_AM08H                       0xFFC02B44      /* Mailbox 8 High Acceptance Mask       */
+#define CAN_AM09L                       0xFFC02B48      /* Mailbox 9 Low Acceptance Mask        */
+#define CAN_AM09H                       0xFFC02B4C      /* Mailbox 9 High Acceptance Mask       */
+#define CAN_AM10L                       0xFFC02B50      /* Mailbox 10 Low Acceptance Mask       */
+#define CAN_AM10H                       0xFFC02B54      /* Mailbox 10 High Acceptance Mask      */
+#define CAN_AM11L                       0xFFC02B58      /* Mailbox 11 Low Acceptance Mask       */
+#define CAN_AM11H                       0xFFC02B5C      /* Mailbox 11 High Acceptance Mask      */
+#define CAN_AM12L                       0xFFC02B60      /* Mailbox 12 Low Acceptance Mask       */
+#define CAN_AM12H                       0xFFC02B64      /* Mailbox 12 High Acceptance Mask      */
+#define CAN_AM13L                       0xFFC02B68      /* Mailbox 13 Low Acceptance Mask       */
+#define CAN_AM13H                       0xFFC02B6C      /* Mailbox 13 High Acceptance Mask      */
+#define CAN_AM14L                       0xFFC02B70      /* Mailbox 14 Low Acceptance Mask       */
+#define CAN_AM14H                       0xFFC02B74      /* Mailbox 14 High Acceptance Mask      */
+#define CAN_AM15L                       0xFFC02B78      /* Mailbox 15 Low Acceptance Mask       */
+#define CAN_AM15H                       0xFFC02B7C      /* Mailbox 15 High Acceptance Mask      */
+
+#define CAN_AM16L                       0xFFC02B80      /* Mailbox 16 Low Acceptance Mask       */
+#define CAN_AM16H                       0xFFC02B84      /* Mailbox 16 High Acceptance Mask      */
+#define CAN_AM17L                       0xFFC02B88      /* Mailbox 17 Low Acceptance Mask       */
+#define CAN_AM17H                       0xFFC02B8C      /* Mailbox 17 High Acceptance Mask      */
+#define CAN_AM18L                       0xFFC02B90      /* Mailbox 18 Low Acceptance Mask       */
+#define CAN_AM18H                       0xFFC02B94      /* Mailbox 18 High Acceptance Mask      */
+#define CAN_AM19L                       0xFFC02B98      /* Mailbox 19 Low Acceptance Mask       */
+#define CAN_AM19H                       0xFFC02B9C      /* Mailbox 19 High Acceptance Mask      */
+#define CAN_AM20L                       0xFFC02BA0      /* Mailbox 20 Low Acceptance Mask       */
+#define CAN_AM20H                       0xFFC02BA4      /* Mailbox 20 High Acceptance Mask      */
+#define CAN_AM21L                       0xFFC02BA8      /* Mailbox 21 Low Acceptance Mask       */
+#define CAN_AM21H                       0xFFC02BAC      /* Mailbox 21 High Acceptance Mask      */
+#define CAN_AM22L                       0xFFC02BB0      /* Mailbox 22 Low Acceptance Mask       */
+#define CAN_AM22H                       0xFFC02BB4      /* Mailbox 22 High Acceptance Mask      */
+#define CAN_AM23L                       0xFFC02BB8      /* Mailbox 23 Low Acceptance Mask       */
+#define CAN_AM23H                       0xFFC02BBC      /* Mailbox 23 High Acceptance Mask      */
+#define CAN_AM24L                       0xFFC02BC0      /* Mailbox 24 Low Acceptance Mask       */
+#define CAN_AM24H                       0xFFC02BC4      /* Mailbox 24 High Acceptance Mask      */
+#define CAN_AM25L                       0xFFC02BC8      /* Mailbox 25 Low Acceptance Mask       */
+#define CAN_AM25H                       0xFFC02BCC      /* Mailbox 25 High Acceptance Mask      */
+#define CAN_AM26L                       0xFFC02BD0      /* Mailbox 26 Low Acceptance Mask       */
+#define CAN_AM26H                       0xFFC02BD4      /* Mailbox 26 High Acceptance Mask      */
+#define CAN_AM27L                       0xFFC02BD8      /* Mailbox 27 Low Acceptance Mask       */
+#define CAN_AM27H                       0xFFC02BDC      /* Mailbox 27 High Acceptance Mask      */
+#define CAN_AM28L                       0xFFC02BE0      /* Mailbox 28 Low Acceptance Mask       */
+#define CAN_AM28H                       0xFFC02BE4      /* Mailbox 28 High Acceptance Mask      */
+#define CAN_AM29L                       0xFFC02BE8      /* Mailbox 29 Low Acceptance Mask       */
+#define CAN_AM29H                       0xFFC02BEC      /* Mailbox 29 High Acceptance Mask      */
+#define CAN_AM30L                       0xFFC02BF0      /* Mailbox 30 Low Acceptance Mask       */
+#define CAN_AM30H                       0xFFC02BF4      /* Mailbox 30 High Acceptance Mask      */
+#define CAN_AM31L                       0xFFC02BF8      /* Mailbox 31 Low Acceptance Mask       */
+#define CAN_AM31H                       0xFFC02BFC      /* Mailbox 31 High Acceptance Mask      */
+
+/* CAN Acceptance Mask Macros                           */
+#define CAN_AM_L(x)             (CAN_AM00L+((x)*0x8))
+#define CAN_AM_H(x)             (CAN_AM00H+((x)*0x8))
+
+/* Mailbox Registers                                                                                                                            */
+#define CAN_MB00_DATA0          0xFFC02C00      /* Mailbox 0 Data Word 0 [15:0] Register        */
+#define CAN_MB00_DATA1          0xFFC02C04      /* Mailbox 0 Data Word 1 [31:16] Register       */
+#define CAN_MB00_DATA2          0xFFC02C08      /* Mailbox 0 Data Word 2 [47:32] Register       */
+#define CAN_MB00_DATA3          0xFFC02C0C      /* Mailbox 0 Data Word 3 [63:48] Register       */
+#define CAN_MB00_LENGTH         0xFFC02C10      /* Mailbox 0 Data Length Code Register          */
+#define CAN_MB00_TIMESTAMP      0xFFC02C14      /* Mailbox 0 Time Stamp Value Register          */
+#define CAN_MB00_ID0            0xFFC02C18      /* Mailbox 0 Identifier Low Register            */
+#define CAN_MB00_ID1            0xFFC02C1C      /* Mailbox 0 Identifier High Register           */
+
+#define CAN_MB01_DATA0          0xFFC02C20      /* Mailbox 1 Data Word 0 [15:0] Register        */
+#define CAN_MB01_DATA1          0xFFC02C24      /* Mailbox 1 Data Word 1 [31:16] Register       */
+#define CAN_MB01_DATA2          0xFFC02C28      /* Mailbox 1 Data Word 2 [47:32] Register       */
+#define CAN_MB01_DATA3          0xFFC02C2C      /* Mailbox 1 Data Word 3 [63:48] Register       */
+#define CAN_MB01_LENGTH         0xFFC02C30      /* Mailbox 1 Data Length Code Register          */
+#define CAN_MB01_TIMESTAMP      0xFFC02C34      /* Mailbox 1 Time Stamp Value Register          */
+#define CAN_MB01_ID0            0xFFC02C38      /* Mailbox 1 Identifier Low Register            */
+#define CAN_MB01_ID1            0xFFC02C3C      /* Mailbox 1 Identifier High Register           */
+
+#define CAN_MB02_DATA0          0xFFC02C40      /* Mailbox 2 Data Word 0 [15:0] Register        */
+#define CAN_MB02_DATA1          0xFFC02C44      /* Mailbox 2 Data Word 1 [31:16] Register       */
+#define CAN_MB02_DATA2          0xFFC02C48      /* Mailbox 2 Data Word 2 [47:32] Register       */
+#define CAN_MB02_DATA3          0xFFC02C4C      /* Mailbox 2 Data Word 3 [63:48] Register       */
+#define CAN_MB02_LENGTH         0xFFC02C50      /* Mailbox 2 Data Length Code Register          */
+#define CAN_MB02_TIMESTAMP      0xFFC02C54      /* Mailbox 2 Time Stamp Value Register          */
+#define CAN_MB02_ID0            0xFFC02C58      /* Mailbox 2 Identifier Low Register            */
+#define CAN_MB02_ID1            0xFFC02C5C      /* Mailbox 2 Identifier High Register           */
+
+#define CAN_MB03_DATA0          0xFFC02C60      /* Mailbox 3 Data Word 0 [15:0] Register        */
+#define CAN_MB03_DATA1          0xFFC02C64      /* Mailbox 3 Data Word 1 [31:16] Register       */
+#define CAN_MB03_DATA2          0xFFC02C68      /* Mailbox 3 Data Word 2 [47:32] Register       */
+#define CAN_MB03_DATA3          0xFFC02C6C      /* Mailbox 3 Data Word 3 [63:48] Register       */
+#define CAN_MB03_LENGTH         0xFFC02C70      /* Mailbox 3 Data Length Code Register          */
+#define CAN_MB03_TIMESTAMP      0xFFC02C74      /* Mailbox 3 Time Stamp Value Register          */
+#define CAN_MB03_ID0            0xFFC02C78      /* Mailbox 3 Identifier Low Register            */
+#define CAN_MB03_ID1            0xFFC02C7C      /* Mailbox 3 Identifier High Register           */
+
+#define CAN_MB04_DATA0          0xFFC02C80      /* Mailbox 4 Data Word 0 [15:0] Register        */
+#define CAN_MB04_DATA1          0xFFC02C84      /* Mailbox 4 Data Word 1 [31:16] Register       */
+#define CAN_MB04_DATA2          0xFFC02C88      /* Mailbox 4 Data Word 2 [47:32] Register       */
+#define CAN_MB04_DATA3          0xFFC02C8C      /* Mailbox 4 Data Word 3 [63:48] Register       */
+#define CAN_MB04_LENGTH         0xFFC02C90      /* Mailbox 4 Data Length Code Register          */
+#define CAN_MB04_TIMESTAMP      0xFFC02C94      /* Mailbox 4 Time Stamp Value Register          */
+#define CAN_MB04_ID0            0xFFC02C98      /* Mailbox 4 Identifier Low Register            */
+#define CAN_MB04_ID1            0xFFC02C9C      /* Mailbox 4 Identifier High Register           */
+
+#define CAN_MB05_DATA0          0xFFC02CA0      /* Mailbox 5 Data Word 0 [15:0] Register        */
+#define CAN_MB05_DATA1          0xFFC02CA4      /* Mailbox 5 Data Word 1 [31:16] Register       */
+#define CAN_MB05_DATA2          0xFFC02CA8      /* Mailbox 5 Data Word 2 [47:32] Register       */
+#define CAN_MB05_DATA3          0xFFC02CAC      /* Mailbox 5 Data Word 3 [63:48] Register       */
+#define CAN_MB05_LENGTH         0xFFC02CB0      /* Mailbox 5 Data Length Code Register          */
+#define CAN_MB05_TIMESTAMP      0xFFC02CB4      /* Mailbox 5 Time Stamp Value Register          */
+#define CAN_MB05_ID0            0xFFC02CB8      /* Mailbox 5 Identifier Low Register            */
+#define CAN_MB05_ID1            0xFFC02CBC      /* Mailbox 5 Identifier High Register           */
+
+#define CAN_MB06_DATA0          0xFFC02CC0      /* Mailbox 6 Data Word 0 [15:0] Register        */
+#define CAN_MB06_DATA1          0xFFC02CC4      /* Mailbox 6 Data Word 1 [31:16] Register       */
+#define CAN_MB06_DATA2          0xFFC02CC8      /* Mailbox 6 Data Word 2 [47:32] Register       */
+#define CAN_MB06_DATA3          0xFFC02CCC      /* Mailbox 6 Data Word 3 [63:48] Register       */
+#define CAN_MB06_LENGTH         0xFFC02CD0      /* Mailbox 6 Data Length Code Register          */
+#define CAN_MB06_TIMESTAMP      0xFFC02CD4      /* Mailbox 6 Time Stamp Value Register          */
+#define CAN_MB06_ID0            0xFFC02CD8      /* Mailbox 6 Identifier Low Register            */
+#define CAN_MB06_ID1            0xFFC02CDC      /* Mailbox 6 Identifier High Register           */
+
+#define CAN_MB07_DATA0          0xFFC02CE0      /* Mailbox 7 Data Word 0 [15:0] Register        */
+#define CAN_MB07_DATA1          0xFFC02CE4      /* Mailbox 7 Data Word 1 [31:16] Register       */
+#define CAN_MB07_DATA2          0xFFC02CE8      /* Mailbox 7 Data Word 2 [47:32] Register       */
+#define CAN_MB07_DATA3          0xFFC02CEC      /* Mailbox 7 Data Word 3 [63:48] Register       */
+#define CAN_MB07_LENGTH         0xFFC02CF0      /* Mailbox 7 Data Length Code Register          */
+#define CAN_MB07_TIMESTAMP      0xFFC02CF4      /* Mailbox 7 Time Stamp Value Register          */
+#define CAN_MB07_ID0            0xFFC02CF8      /* Mailbox 7 Identifier Low Register            */
+#define CAN_MB07_ID1            0xFFC02CFC      /* Mailbox 7 Identifier High Register           */
+
+#define CAN_MB08_DATA0          0xFFC02D00      /* Mailbox 8 Data Word 0 [15:0] Register        */
+#define CAN_MB08_DATA1          0xFFC02D04      /* Mailbox 8 Data Word 1 [31:16] Register       */
+#define CAN_MB08_DATA2          0xFFC02D08      /* Mailbox 8 Data Word 2 [47:32] Register       */
+#define CAN_MB08_DATA3          0xFFC02D0C      /* Mailbox 8 Data Word 3 [63:48] Register       */
+#define CAN_MB08_LENGTH         0xFFC02D10      /* Mailbox 8 Data Length Code Register          */
+#define CAN_MB08_TIMESTAMP      0xFFC02D14      /* Mailbox 8 Time Stamp Value Register          */
+#define CAN_MB08_ID0            0xFFC02D18      /* Mailbox 8 Identifier Low Register            */
+#define CAN_MB08_ID1            0xFFC02D1C      /* Mailbox 8 Identifier High Register           */
+
+#define CAN_MB09_DATA0          0xFFC02D20      /* Mailbox 9 Data Word 0 [15:0] Register        */
+#define CAN_MB09_DATA1          0xFFC02D24      /* Mailbox 9 Data Word 1 [31:16] Register       */
+#define CAN_MB09_DATA2          0xFFC02D28      /* Mailbox 9 Data Word 2 [47:32] Register       */
+#define CAN_MB09_DATA3          0xFFC02D2C      /* Mailbox 9 Data Word 3 [63:48] Register       */
+#define CAN_MB09_LENGTH         0xFFC02D30      /* Mailbox 9 Data Length Code Register          */
+#define CAN_MB09_TIMESTAMP      0xFFC02D34      /* Mailbox 9 Time Stamp Value Register          */
+#define CAN_MB09_ID0            0xFFC02D38      /* Mailbox 9 Identifier Low Register            */
+#define CAN_MB09_ID1            0xFFC02D3C      /* Mailbox 9 Identifier High Register           */
+
+#define CAN_MB10_DATA0          0xFFC02D40      /* Mailbox 10 Data Word 0 [15:0] Register       */
+#define CAN_MB10_DATA1          0xFFC02D44      /* Mailbox 10 Data Word 1 [31:16] Register      */
+#define CAN_MB10_DATA2          0xFFC02D48      /* Mailbox 10 Data Word 2 [47:32] Register      */
+#define CAN_MB10_DATA3          0xFFC02D4C      /* Mailbox 10 Data Word 3 [63:48] Register      */
+#define CAN_MB10_LENGTH         0xFFC02D50      /* Mailbox 10 Data Length Code Register         */
+#define CAN_MB10_TIMESTAMP      0xFFC02D54      /* Mailbox 10 Time Stamp Value Register         */
+#define CAN_MB10_ID0            0xFFC02D58      /* Mailbox 10 Identifier Low Register           */
+#define CAN_MB10_ID1            0xFFC02D5C      /* Mailbox 10 Identifier High Register          */
+
+#define CAN_MB11_DATA0          0xFFC02D60      /* Mailbox 11 Data Word 0 [15:0] Register       */
+#define CAN_MB11_DATA1          0xFFC02D64      /* Mailbox 11 Data Word 1 [31:16] Register      */
+#define CAN_MB11_DATA2          0xFFC02D68      /* Mailbox 11 Data Word 2 [47:32] Register      */
+#define CAN_MB11_DATA3          0xFFC02D6C      /* Mailbox 11 Data Word 3 [63:48] Register      */
+#define CAN_MB11_LENGTH         0xFFC02D70      /* Mailbox 11 Data Length Code Register         */
+#define CAN_MB11_TIMESTAMP      0xFFC02D74      /* Mailbox 11 Time Stamp Value Register         */
+#define CAN_MB11_ID0            0xFFC02D78      /* Mailbox 11 Identifier Low Register           */
+#define CAN_MB11_ID1            0xFFC02D7C      /* Mailbox 11 Identifier High Register          */
+
+#define CAN_MB12_DATA0          0xFFC02D80      /* Mailbox 12 Data Word 0 [15:0] Register       */
+#define CAN_MB12_DATA1          0xFFC02D84      /* Mailbox 12 Data Word 1 [31:16] Register      */
+#define CAN_MB12_DATA2          0xFFC02D88      /* Mailbox 12 Data Word 2 [47:32] Register      */
+#define CAN_MB12_DATA3          0xFFC02D8C      /* Mailbox 12 Data Word 3 [63:48] Register      */
+#define CAN_MB12_LENGTH         0xFFC02D90      /* Mailbox 12 Data Length Code Register         */
+#define CAN_MB12_TIMESTAMP      0xFFC02D94      /* Mailbox 12 Time Stamp Value Register         */
+#define CAN_MB12_ID0            0xFFC02D98      /* Mailbox 12 Identifier Low Register           */
+#define CAN_MB12_ID1            0xFFC02D9C      /* Mailbox 12 Identifier High Register          */
+
+#define CAN_MB13_DATA0          0xFFC02DA0      /* Mailbox 13 Data Word 0 [15:0] Register       */
+#define CAN_MB13_DATA1          0xFFC02DA4      /* Mailbox 13 Data Word 1 [31:16] Register      */
+#define CAN_MB13_DATA2          0xFFC02DA8      /* Mailbox 13 Data Word 2 [47:32] Register      */
+#define CAN_MB13_DATA3          0xFFC02DAC      /* Mailbox 13 Data Word 3 [63:48] Register      */
+#define CAN_MB13_LENGTH         0xFFC02DB0      /* Mailbox 13 Data Length Code Register         */
+#define CAN_MB13_TIMESTAMP      0xFFC02DB4      /* Mailbox 13 Time Stamp Value Register         */
+#define CAN_MB13_ID0            0xFFC02DB8      /* Mailbox 13 Identifier Low Register           */
+#define CAN_MB13_ID1            0xFFC02DBC      /* Mailbox 13 Identifier High Register          */
+
+#define CAN_MB14_DATA0          0xFFC02DC0      /* Mailbox 14 Data Word 0 [15:0] Register       */
+#define CAN_MB14_DATA1          0xFFC02DC4      /* Mailbox 14 Data Word 1 [31:16] Register      */
+#define CAN_MB14_DATA2          0xFFC02DC8      /* Mailbox 14 Data Word 2 [47:32] Register      */
+#define CAN_MB14_DATA3          0xFFC02DCC      /* Mailbox 14 Data Word 3 [63:48] Register      */
+#define CAN_MB14_LENGTH         0xFFC02DD0      /* Mailbox 14 Data Length Code Register         */
+#define CAN_MB14_TIMESTAMP      0xFFC02DD4      /* Mailbox 14 Time Stamp Value Register         */
+#define CAN_MB14_ID0            0xFFC02DD8      /* Mailbox 14 Identifier Low Register           */
+#define CAN_MB14_ID1            0xFFC02DDC      /* Mailbox 14 Identifier High Register          */
+
+#define CAN_MB15_DATA0          0xFFC02DE0      /* Mailbox 15 Data Word 0 [15:0] Register       */
+#define CAN_MB15_DATA1          0xFFC02DE4      /* Mailbox 15 Data Word 1 [31:16] Register      */
+#define CAN_MB15_DATA2          0xFFC02DE8      /* Mailbox 15 Data Word 2 [47:32] Register      */
+#define CAN_MB15_DATA3          0xFFC02DEC      /* Mailbox 15 Data Word 3 [63:48] Register      */
+#define CAN_MB15_LENGTH         0xFFC02DF0      /* Mailbox 15 Data Length Code Register         */
+#define CAN_MB15_TIMESTAMP      0xFFC02DF4      /* Mailbox 15 Time Stamp Value Register         */
+#define CAN_MB15_ID0            0xFFC02DF8      /* Mailbox 15 Identifier Low Register           */
+#define CAN_MB15_ID1            0xFFC02DFC      /* Mailbox 15 Identifier High Register          */
+
+#define CAN_MB16_DATA0          0xFFC02E00      /* Mailbox 16 Data Word 0 [15:0] Register       */
+#define CAN_MB16_DATA1          0xFFC02E04      /* Mailbox 16 Data Word 1 [31:16] Register      */
+#define CAN_MB16_DATA2          0xFFC02E08      /* Mailbox 16 Data Word 2 [47:32] Register      */
+#define CAN_MB16_DATA3          0xFFC02E0C      /* Mailbox 16 Data Word 3 [63:48] Register      */
+#define CAN_MB16_LENGTH         0xFFC02E10      /* Mailbox 16 Data Length Code Register         */
+#define CAN_MB16_TIMESTAMP      0xFFC02E14      /* Mailbox 16 Time Stamp Value Register         */
+#define CAN_MB16_ID0            0xFFC02E18      /* Mailbox 16 Identifier Low Register           */
+#define CAN_MB16_ID1            0xFFC02E1C      /* Mailbox 16 Identifier High Register          */
+
+#define CAN_MB17_DATA0          0xFFC02E20      /* Mailbox 17 Data Word 0 [15:0] Register       */
+#define CAN_MB17_DATA1          0xFFC02E24      /* Mailbox 17 Data Word 1 [31:16] Register      */
+#define CAN_MB17_DATA2          0xFFC02E28      /* Mailbox 17 Data Word 2 [47:32] Register      */
+#define CAN_MB17_DATA3          0xFFC02E2C      /* Mailbox 17 Data Word 3 [63:48] Register      */
+#define CAN_MB17_LENGTH         0xFFC02E30      /* Mailbox 17 Data Length Code Register         */
+#define CAN_MB17_TIMESTAMP      0xFFC02E34      /* Mailbox 17 Time Stamp Value Register         */
+#define CAN_MB17_ID0            0xFFC02E38      /* Mailbox 17 Identifier Low Register           */
+#define CAN_MB17_ID1            0xFFC02E3C      /* Mailbox 17 Identifier High Register          */
+
+#define CAN_MB18_DATA0          0xFFC02E40      /* Mailbox 18 Data Word 0 [15:0] Register       */
+#define CAN_MB18_DATA1          0xFFC02E44      /* Mailbox 18 Data Word 1 [31:16] Register      */
+#define CAN_MB18_DATA2          0xFFC02E48      /* Mailbox 18 Data Word 2 [47:32] Register      */
+#define CAN_MB18_DATA3          0xFFC02E4C      /* Mailbox 18 Data Word 3 [63:48] Register      */
+#define CAN_MB18_LENGTH         0xFFC02E50      /* Mailbox 18 Data Length Code Register         */
+#define CAN_MB18_TIMESTAMP      0xFFC02E54      /* Mailbox 18 Time Stamp Value Register         */
+#define CAN_MB18_ID0            0xFFC02E58      /* Mailbox 18 Identifier Low Register           */
+#define CAN_MB18_ID1            0xFFC02E5C      /* Mailbox 18 Identifier High Register          */
+
+#define CAN_MB19_DATA0          0xFFC02E60      /* Mailbox 19 Data Word 0 [15:0] Register       */
+#define CAN_MB19_DATA1          0xFFC02E64      /* Mailbox 19 Data Word 1 [31:16] Register      */
+#define CAN_MB19_DATA2          0xFFC02E68      /* Mailbox 19 Data Word 2 [47:32] Register      */
+#define CAN_MB19_DATA3          0xFFC02E6C      /* Mailbox 19 Data Word 3 [63:48] Register      */
+#define CAN_MB19_LENGTH         0xFFC02E70      /* Mailbox 19 Data Length Code Register         */
+#define CAN_MB19_TIMESTAMP      0xFFC02E74      /* Mailbox 19 Time Stamp Value Register         */
+#define CAN_MB19_ID0            0xFFC02E78      /* Mailbox 19 Identifier Low Register           */
+#define CAN_MB19_ID1            0xFFC02E7C      /* Mailbox 19 Identifier High Register          */
+
+#define CAN_MB20_DATA0          0xFFC02E80      /* Mailbox 20 Data Word 0 [15:0] Register       */
+#define CAN_MB20_DATA1          0xFFC02E84      /* Mailbox 20 Data Word 1 [31:16] Register      */
+#define CAN_MB20_DATA2          0xFFC02E88      /* Mailbox 20 Data Word 2 [47:32] Register      */
+#define CAN_MB20_DATA3          0xFFC02E8C      /* Mailbox 20 Data Word 3 [63:48] Register      */
+#define CAN_MB20_LENGTH         0xFFC02E90      /* Mailbox 20 Data Length Code Register         */
+#define CAN_MB20_TIMESTAMP      0xFFC02E94      /* Mailbox 20 Time Stamp Value Register         */
+#define CAN_MB20_ID0            0xFFC02E98      /* Mailbox 20 Identifier Low Register           */
+#define CAN_MB20_ID1            0xFFC02E9C      /* Mailbox 20 Identifier High Register          */
+
+#define CAN_MB21_DATA0          0xFFC02EA0      /* Mailbox 21 Data Word 0 [15:0] Register       */
+#define CAN_MB21_DATA1          0xFFC02EA4      /* Mailbox 21 Data Word 1 [31:16] Register      */
+#define CAN_MB21_DATA2          0xFFC02EA8      /* Mailbox 21 Data Word 2 [47:32] Register      */
+#define CAN_MB21_DATA3          0xFFC02EAC      /* Mailbox 21 Data Word 3 [63:48] Register      */
+#define CAN_MB21_LENGTH         0xFFC02EB0      /* Mailbox 21 Data Length Code Register         */
+#define CAN_MB21_TIMESTAMP      0xFFC02EB4      /* Mailbox 21 Time Stamp Value Register         */
+#define CAN_MB21_ID0            0xFFC02EB8      /* Mailbox 21 Identifier Low Register           */
+#define CAN_MB21_ID1            0xFFC02EBC      /* Mailbox 21 Identifier High Register          */
+
+#define CAN_MB22_DATA0          0xFFC02EC0      /* Mailbox 22 Data Word 0 [15:0] Register       */
+#define CAN_MB22_DATA1          0xFFC02EC4      /* Mailbox 22 Data Word 1 [31:16] Register      */
+#define CAN_MB22_DATA2          0xFFC02EC8      /* Mailbox 22 Data Word 2 [47:32] Register      */
+#define CAN_MB22_DATA3          0xFFC02ECC      /* Mailbox 22 Data Word 3 [63:48] Register      */
+#define CAN_MB22_LENGTH         0xFFC02ED0      /* Mailbox 22 Data Length Code Register         */
+#define CAN_MB22_TIMESTAMP      0xFFC02ED4      /* Mailbox 22 Time Stamp Value Register         */
+#define CAN_MB22_ID0            0xFFC02ED8      /* Mailbox 22 Identifier Low Register           */
+#define CAN_MB22_ID1            0xFFC02EDC      /* Mailbox 22 Identifier High Register          */
+
+#define CAN_MB23_DATA0          0xFFC02EE0      /* Mailbox 23 Data Word 0 [15:0] Register       */
+#define CAN_MB23_DATA1          0xFFC02EE4      /* Mailbox 23 Data Word 1 [31:16] Register      */
+#define CAN_MB23_DATA2          0xFFC02EE8      /* Mailbox 23 Data Word 2 [47:32] Register      */
+#define CAN_MB23_DATA3          0xFFC02EEC      /* Mailbox 23 Data Word 3 [63:48] Register      */
+#define CAN_MB23_LENGTH         0xFFC02EF0      /* Mailbox 23 Data Length Code Register         */
+#define CAN_MB23_TIMESTAMP      0xFFC02EF4      /* Mailbox 23 Time Stamp Value Register         */
+#define CAN_MB23_ID0            0xFFC02EF8      /* Mailbox 23 Identifier Low Register           */
+#define CAN_MB23_ID1            0xFFC02EFC      /* Mailbox 23 Identifier High Register          */
+
+#define CAN_MB24_DATA0          0xFFC02F00      /* Mailbox 24 Data Word 0 [15:0] Register       */
+#define CAN_MB24_DATA1          0xFFC02F04      /* Mailbox 24 Data Word 1 [31:16] Register      */
+#define CAN_MB24_DATA2          0xFFC02F08      /* Mailbox 24 Data Word 2 [47:32] Register      */
+#define CAN_MB24_DATA3          0xFFC02F0C      /* Mailbox 24 Data Word 3 [63:48] Register      */
+#define CAN_MB24_LENGTH         0xFFC02F10      /* Mailbox 24 Data Length Code Register         */
+#define CAN_MB24_TIMESTAMP      0xFFC02F14      /* Mailbox 24 Time Stamp Value Register         */
+#define CAN_MB24_ID0            0xFFC02F18      /* Mailbox 24 Identifier Low Register           */
+#define CAN_MB24_ID1            0xFFC02F1C      /* Mailbox 24 Identifier High Register          */
+
+#define CAN_MB25_DATA0          0xFFC02F20      /* Mailbox 25 Data Word 0 [15:0] Register       */
+#define CAN_MB25_DATA1          0xFFC02F24      /* Mailbox 25 Data Word 1 [31:16] Register      */
+#define CAN_MB25_DATA2          0xFFC02F28      /* Mailbox 25 Data Word 2 [47:32] Register      */
+#define CAN_MB25_DATA3          0xFFC02F2C      /* Mailbox 25 Data Word 3 [63:48] Register      */
+#define CAN_MB25_LENGTH         0xFFC02F30      /* Mailbox 25 Data Length Code Register         */
+#define CAN_MB25_TIMESTAMP      0xFFC02F34      /* Mailbox 25 Time Stamp Value Register         */
+#define CAN_MB25_ID0            0xFFC02F38      /* Mailbox 25 Identifier Low Register           */
+#define CAN_MB25_ID1            0xFFC02F3C      /* Mailbox 25 Identifier High Register          */
+
+#define CAN_MB26_DATA0          0xFFC02F40      /* Mailbox 26 Data Word 0 [15:0] Register       */
+#define CAN_MB26_DATA1          0xFFC02F44      /* Mailbox 26 Data Word 1 [31:16] Register      */
+#define CAN_MB26_DATA2          0xFFC02F48      /* Mailbox 26 Data Word 2 [47:32] Register      */
+#define CAN_MB26_DATA3          0xFFC02F4C      /* Mailbox 26 Data Word 3 [63:48] Register      */
+#define CAN_MB26_LENGTH         0xFFC02F50      /* Mailbox 26 Data Length Code Register         */
+#define CAN_MB26_TIMESTAMP      0xFFC02F54      /* Mailbox 26 Time Stamp Value Register         */
+#define CAN_MB26_ID0            0xFFC02F58      /* Mailbox 26 Identifier Low Register           */
+#define CAN_MB26_ID1            0xFFC02F5C      /* Mailbox 26 Identifier High Register          */
+
+#define CAN_MB27_DATA0          0xFFC02F60      /* Mailbox 27 Data Word 0 [15:0] Register       */
+#define CAN_MB27_DATA1          0xFFC02F64      /* Mailbox 27 Data Word 1 [31:16] Register      */
+#define CAN_MB27_DATA2          0xFFC02F68      /* Mailbox 27 Data Word 2 [47:32] Register      */
+#define CAN_MB27_DATA3          0xFFC02F6C      /* Mailbox 27 Data Word 3 [63:48] Register      */
+#define CAN_MB27_LENGTH         0xFFC02F70      /* Mailbox 27 Data Length Code Register         */
+#define CAN_MB27_TIMESTAMP      0xFFC02F74      /* Mailbox 27 Time Stamp Value Register         */
+#define CAN_MB27_ID0            0xFFC02F78      /* Mailbox 27 Identifier Low Register           */
+#define CAN_MB27_ID1            0xFFC02F7C      /* Mailbox 27 Identifier High Register          */
+
+#define CAN_MB28_DATA0          0xFFC02F80      /* Mailbox 28 Data Word 0 [15:0] Register       */
+#define CAN_MB28_DATA1          0xFFC02F84      /* Mailbox 28 Data Word 1 [31:16] Register      */
+#define CAN_MB28_DATA2          0xFFC02F88      /* Mailbox 28 Data Word 2 [47:32] Register      */
+#define CAN_MB28_DATA3          0xFFC02F8C      /* Mailbox 28 Data Word 3 [63:48] Register      */
+#define CAN_MB28_LENGTH         0xFFC02F90      /* Mailbox 28 Data Length Code Register         */
+#define CAN_MB28_TIMESTAMP      0xFFC02F94      /* Mailbox 28 Time Stamp Value Register         */
+#define CAN_MB28_ID0            0xFFC02F98      /* Mailbox 28 Identifier Low Register           */
+#define CAN_MB28_ID1            0xFFC02F9C      /* Mailbox 28 Identifier High Register          */
+
+#define CAN_MB29_DATA0          0xFFC02FA0      /* Mailbox 29 Data Word 0 [15:0] Register       */
+#define CAN_MB29_DATA1          0xFFC02FA4      /* Mailbox 29 Data Word 1 [31:16] Register      */
+#define CAN_MB29_DATA2          0xFFC02FA8      /* Mailbox 29 Data Word 2 [47:32] Register      */
+#define CAN_MB29_DATA3          0xFFC02FAC      /* Mailbox 29 Data Word 3 [63:48] Register      */
+#define CAN_MB29_LENGTH         0xFFC02FB0      /* Mailbox 29 Data Length Code Register         */
+#define CAN_MB29_TIMESTAMP      0xFFC02FB4      /* Mailbox 29 Time Stamp Value Register         */
+#define CAN_MB29_ID0            0xFFC02FB8      /* Mailbox 29 Identifier Low Register           */
+#define CAN_MB29_ID1            0xFFC02FBC      /* Mailbox 29 Identifier High Register          */
+
+#define CAN_MB30_DATA0          0xFFC02FC0      /* Mailbox 30 Data Word 0 [15:0] Register       */
+#define CAN_MB30_DATA1          0xFFC02FC4      /* Mailbox 30 Data Word 1 [31:16] Register      */
+#define CAN_MB30_DATA2          0xFFC02FC8      /* Mailbox 30 Data Word 2 [47:32] Register      */
+#define CAN_MB30_DATA3          0xFFC02FCC      /* Mailbox 30 Data Word 3 [63:48] Register      */
+#define CAN_MB30_LENGTH         0xFFC02FD0      /* Mailbox 30 Data Length Code Register         */
+#define CAN_MB30_TIMESTAMP      0xFFC02FD4      /* Mailbox 30 Time Stamp Value Register         */
+#define CAN_MB30_ID0            0xFFC02FD8      /* Mailbox 30 Identifier Low Register           */
+#define CAN_MB30_ID1            0xFFC02FDC      /* Mailbox 30 Identifier High Register          */
+
+#define CAN_MB31_DATA0          0xFFC02FE0      /* Mailbox 31 Data Word 0 [15:0] Register       */
+#define CAN_MB31_DATA1          0xFFC02FE4      /* Mailbox 31 Data Word 1 [31:16] Register      */
+#define CAN_MB31_DATA2          0xFFC02FE8      /* Mailbox 31 Data Word 2 [47:32] Register      */
+#define CAN_MB31_DATA3          0xFFC02FEC      /* Mailbox 31 Data Word 3 [63:48] Register      */
+#define CAN_MB31_LENGTH         0xFFC02FF0      /* Mailbox 31 Data Length Code Register         */
+#define CAN_MB31_TIMESTAMP      0xFFC02FF4      /* Mailbox 31 Time Stamp Value Register         */
+#define CAN_MB31_ID0            0xFFC02FF8      /* Mailbox 31 Identifier Low Register           */
+#define CAN_MB31_ID1            0xFFC02FFC      /* Mailbox 31 Identifier High Register          */
+
+/* CAN Mailbox Area Macros                              */
+#define CAN_MB_ID1(x)           (CAN_MB00_ID1+((x)*0x20))
+#define CAN_MB_ID0(x)           (CAN_MB00_ID0+((x)*0x20))
+#define CAN_MB_TIMESTAMP(x)     (CAN_MB00_TIMESTAMP+((x)*0x20))
+#define CAN_MB_LENGTH(x)        (CAN_MB00_LENGTH+((x)*0x20))
+#define CAN_MB_DATA3(x)         (CAN_MB00_DATA3+((x)*0x20))
+#define CAN_MB_DATA2(x)         (CAN_MB00_DATA2+((x)*0x20))
+#define CAN_MB_DATA1(x)         (CAN_MB00_DATA1+((x)*0x20))
+#define CAN_MB_DATA0(x)         (CAN_MB00_DATA0+((x)*0x20))
+
+/* Pin Control Registers        (0xFFC03200 - 0xFFC032FF)                                                                                       */
+#define PORTF_FER                       0xFFC03200      /* Port F Function Enable Register (Alternate/Flag*)    */
+#define PORTG_FER                       0xFFC03204      /* Port G Function Enable Register (Alternate/Flag*)    */
+#define PORTH_FER                       0xFFC03208      /* Port H Function Enable Register (Alternate/Flag*)    */
+#define BFIN_PORT_MUX                   0xFFC0320C      /* Port Multiplexer Control Register                                    */
+
+/* Handshake MDMA Registers     (0xFFC03300 - 0xFFC033FF)                                                                               */
+#define HMDMA0_CONTROL          0xFFC03300      /* Handshake MDMA0 Control Register                                     */
+#define HMDMA0_ECINIT           0xFFC03304      /* HMDMA0 Initial Edge Count Register                           */
+#define HMDMA0_BCINIT           0xFFC03308      /* HMDMA0 Initial Block Count Register                          */
+#define HMDMA0_ECURGENT         0xFFC0330C      /* HMDMA0 Urgent Edge Count Threshhold Register         */
+#define HMDMA0_ECOVERFLOW       0xFFC03310      /* HMDMA0 Edge Count Overflow Interrupt Register        */
+#define HMDMA0_ECOUNT           0xFFC03314      /* HMDMA0 Current Edge Count Register                           */
+#define HMDMA0_BCOUNT           0xFFC03318      /* HMDMA0 Current Block Count Register                          */
+
+#define HMDMA1_CONTROL          0xFFC03340      /* Handshake MDMA1 Control Register                                     */
+#define HMDMA1_ECINIT           0xFFC03344      /* HMDMA1 Initial Edge Count Register                           */
+#define HMDMA1_BCINIT           0xFFC03348      /* HMDMA1 Initial Block Count Register                          */
+#define HMDMA1_ECURGENT         0xFFC0334C      /* HMDMA1 Urgent Edge Count Threshhold Register         */
+#define HMDMA1_ECOVERFLOW       0xFFC03350      /* HMDMA1 Edge Count Overflow Interrupt Register        */
+#define HMDMA1_ECOUNT           0xFFC03354      /* HMDMA1 Current Edge Count Register                           */
+#define HMDMA1_BCOUNT           0xFFC03358      /* HMDMA1 Current Block Count Register                          */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+/*
+** ********************* PLL AND RESET MASKS ****************************************/
+/* PLL_CTL Masks                                                                                                                                        */
+#define DF                              0x0001  /* 0: PLL = CLKIN, 1: PLL = CLKIN/2                                     */
+#define PLL_OFF                 0x0002  /* PLL Not Powered                                                                      */
+#define STOPCK                  0x0008  /* Core Clock Off                                                                       */
+#define PDWN                    0x0020  /* Enter Deep Sleep Mode                                                        */
+#define IN_DELAY                0x0040  /* Add 200ps Delay To EBIU Input Latches                        */
+#define OUT_DELAY               0x0080  /* Add 200ps Delay To EBIU Output Signals                       */
+#define BYPASS                  0x0100  /* Bypass the PLL                                                                       */
+#define MSEL                    0x7E00  /* Multiplier Select For CCLK/VCO Factors                       */
+/* PLL_CTL Macros (Only Use With Logic OR While Setting Lower Order Bits)                       */
+#define SET_MSEL(x)             (((x)&0x3F) << 0x9)     /* Set MSEL = 0-63 --> VCO = CLKIN*MSEL         */
+
+/* PLL_DIV Masks                                                                                                                */
+#define SSEL                    0x000F  /* System Select                                                */
+#define CSEL                    0x0030  /* Core Select                                                  */
+#define CSEL_DIV1               0x0000  /*              CCLK = VCO / 1                                  */
+#define CSEL_DIV2               0x0010  /*              CCLK = VCO / 2                                  */
+#define CSEL_DIV4               0x0020  /*              CCLK = VCO / 4                                  */
+#define CSEL_DIV8               0x0030  /*              CCLK = VCO / 8                                  */
+/* PLL_DIV Macros                                                                                                               */
+#define SET_SSEL(x)             ((x)&0xF)       /* Set SSEL = 0-15 --> SCLK = VCO/SSEL  */
+
+/* VR_CTL Masks                                                                                                                                 */
+#define FREQ                    0x0003  /* Switching Oscillator Frequency For Regulator */
+#define HIBERNATE               0x0000  /*              Powerdown/Bypass On-Board Regulation    */
+#define FREQ_333                0x0001  /*              Switching Frequency Is 333 kHz                  */
+#define FREQ_667                0x0002  /*              Switching Frequency Is 667 kHz                  */
+#define FREQ_1000               0x0003  /*              Switching Frequency Is 1 MHz                    */
+
+#define GAIN                    0x000C  /* Voltage Level Gain   */
+#define GAIN_5                  0x0000  /*              GAIN = 5                */
+#define GAIN_10                 0x0004  /*              GAIN = 10               */
+#define GAIN_20                 0x0008  /*              GAIN = 20               */
+#define GAIN_50                 0x000C  /*              GAIN = 50               */
+
+#define VLEV                    0x00F0  /* Internal Voltage Level                                       */
+#define VLEV_085                0x0060  /*              VLEV = 0.85 V (-5% - +10% Accuracy)     */
+#define VLEV_090                0x0070  /*              VLEV = 0.90 V (-5% - +10% Accuracy)     */
+#define VLEV_095                0x0080  /*              VLEV = 0.95 V (-5% - +10% Accuracy)     */
+#define VLEV_100                0x0090  /*              VLEV = 1.00 V (-5% - +10% Accuracy)     */
+#define VLEV_105                0x00A0  /*              VLEV = 1.05 V (-5% - +10% Accuracy)     */
+#define VLEV_110                0x00B0  /*              VLEV = 1.10 V (-5% - +10% Accuracy)     */
+#define VLEV_115                0x00C0  /*              VLEV = 1.15 V (-5% - +10% Accuracy)     */
+#define VLEV_120                0x00D0  /*              VLEV = 1.20 V (-5% - +10% Accuracy)     */
+#define VLEV_125                0x00E0  /*              VLEV = 1.25 V (-5% - +10% Accuracy)     */
+#define VLEV_130                0x00F0  /*              VLEV = 1.30 V (-5% - +10% Accuracy)     */
+
+#define WAKE                    0x0100  /* Enable RTC/Reset Wakeup From Hibernate       */
+#define PHYWE                   0x0200  /* Enable PHY Wakeup From Hibernate                     */
+#define CANWE                   0x0400  /* Enable CAN Wakeup From Hibernate                     */
+#define PHYCLKOE                0x4000  /* PHY Clock Output Enable                                      */
+#define CKELOW                  0x8000  /* Enable Drive CKE Low During Reset            */
+
+/* PLL_STAT Masks                                                                                                                                       */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
+#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
+#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* SWRST Masks                                                                                                                                          */
+#define SYSTEM_RESET            0x0007  /* Initiates A System Software Reset                    */
+#define DOUBLE_FAULT            0x0008  /* Core Double Fault Causes Reset                               */
+#define RESET_DOUBLE            0x2000  /* SW Reset Generated By Core Double-Fault              */
+#define RESET_WDOG                      0x4000  /* SW Reset Generated By Watchdog Timer                 */
+#define RESET_SOFTWARE          0x8000  /* SW Reset Occurred Since Last Read Of SWRST   */
+
+/* SYSCR Masks                                                                                                                                                          */
+#define BMODE                           0x0006  /* Boot Mode - Latched During HW Reset From Mode Pins   */
+#define NOBOOT                          0x0010  /* Execute From L1 or ASYNC Bank 0 When BMODE = 0               */
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS *************************************/
+
+/* SIC_IAR0 Macros                                                                                                                      */
+#define P0_IVG(x)               (((x)&0xF)-7)   /* Peripheral #0 assigned IVG #x        */
+#define P1_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #1 assigned IVG #x        */
+#define P2_IVG(x)               (((x)&0xF)-7) << 0x8    /* Peripheral #2 assigned IVG #x        */
+#define P3_IVG(x)               (((x)&0xF)-7) << 0xC    /* Peripheral #3 assigned IVG #x        */
+#define P4_IVG(x)               (((x)&0xF)-7) << 0x10   /* Peripheral #4 assigned IVG #x        */
+#define P5_IVG(x)               (((x)&0xF)-7) << 0x14   /* Peripheral #5 assigned IVG #x        */
+#define P6_IVG(x)               (((x)&0xF)-7) << 0x18   /* Peripheral #6 assigned IVG #x        */
+#define P7_IVG(x)               (((x)&0xF)-7) << 0x1C   /* Peripheral #7 assigned IVG #x        */
+
+/* SIC_IAR1 Macros                                                                                                                      */
+#define P8_IVG(x)               (((x)&0xF)-7)   /* Peripheral #8 assigned IVG #x        */
+#define P9_IVG(x)               (((x)&0xF)-7) << 0x4    /* Peripheral #9 assigned IVG #x        */
+#define P10_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #10 assigned IVG #x       */
+#define P11_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #11 assigned IVG #x       */
+#define P12_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #12 assigned IVG #x       */
+#define P13_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #13 assigned IVG #x       */
+#define P14_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #14 assigned IVG #x       */
+#define P15_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #15 assigned IVG #x       */
+
+/* SIC_IAR2 Macros                                                                                                                      */
+#define P16_IVG(x)              (((x)&0xF)-7)   /* Peripheral #16 assigned IVG #x       */
+#define P17_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #17 assigned IVG #x       */
+#define P18_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #18 assigned IVG #x       */
+#define P19_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #19 assigned IVG #x       */
+#define P20_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #20 assigned IVG #x       */
+#define P21_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #21 assigned IVG #x       */
+#define P22_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #22 assigned IVG #x       */
+#define P23_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #23 assigned IVG #x       */
+
+/* SIC_IAR3 Macros                                                                                                                      */
+#define P24_IVG(x)              (((x)&0xF)-7)   /* Peripheral #24 assigned IVG #x       */
+#define P25_IVG(x)              (((x)&0xF)-7) << 0x4    /* Peripheral #25 assigned IVG #x       */
+#define P26_IVG(x)              (((x)&0xF)-7) << 0x8    /* Peripheral #26 assigned IVG #x       */
+#define P27_IVG(x)              (((x)&0xF)-7) << 0xC    /* Peripheral #27 assigned IVG #x       */
+#define P28_IVG(x)              (((x)&0xF)-7) << 0x10   /* Peripheral #28 assigned IVG #x       */
+#define P29_IVG(x)              (((x)&0xF)-7) << 0x14   /* Peripheral #29 assigned IVG #x       */
+#define P30_IVG(x)              (((x)&0xF)-7) << 0x18   /* Peripheral #30 assigned IVG #x       */
+#define P31_IVG(x)              (((x)&0xF)-7) << 0x1C   /* Peripheral #31 assigned IVG #x       */
+
+/* SIC_IMASK Masks                                                                                                                                              */
+#define SIC_UNMASK_ALL  0x00000000      /* Unmask all peripheral interrupts     */
+#define SIC_MASK_ALL    0xFFFFFFFF      /* Mask all peripheral interrupts       */
+#define SIC_MASK(x)             (1 << ((x)&0x1F))       /* Mask Peripheral #x interrupt         */
+#define SIC_UNMASK(x)   (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Unmask Peripheral #x interrupt       */
+
+/* SIC_IWR Masks                                                                                                                                                */
+#define IWR_DISABLE_ALL 0x00000000      /* Wakeup Disable all peripherals       */
+#define IWR_ENABLE_ALL  0xFFFFFFFF      /* Wakeup Enable all peripherals        */
+#define IWR_ENABLE(x)   (1 << ((x)&0x1F))       /* Wakeup Enable Peripheral #x          */
+#define IWR_DISABLE(x)  (0xFFFFFFFF ^ (1 << ((x)&0x1F)))        /* Wakeup Disable Peripheral #x         */
+
+/* ***************  WATCHDOG TIMER MASKS  *******************************************/
+/* WDOG_CTL Masks                                                                                                                                       */
+#define WDOG_RESET              0x0000  /* Generate Reset Event                                                 */
+#define WDOG_NMI                0x0002  /* Generate Non-Maskable Interrupt (NMI) Event  */
+#define WDOG_GPI                0x0004  /* Generate General Purpose (GP) Interrupt              */
+#define WDOG_NONE               0x0006  /* Disable Watchdog Timer Interrupts                    */
+#define TMR_EN                  0x0FF0  /* Watchdog Counter Enable                                              */
+#define TMR_DIS                 0x0AD0  /* Watchdog Counter Disable                                             */
+#define TRO                     0x8000  /* Watchdog Expired                                                     */
+
+/* ************** UART CONTROLLER MASKS *************************/
+/* UARTx_LCR Masks                                                                                              */
+#define WLS(x)          ((((x)&0x3)-5) & 0x03)  /* Word Length Select   */
+#define STB                     0x04    /* Stop Bits                    */
+#define PEN                     0x08    /* Parity Enable                */
+#define EPS                     0x10    /* Even Parity Select   */
+#define STP                     0x20    /* Stick Parity                 */
+#define SB                      0x40    /* Set Break                    */
+#define DLAB            0x80    /* Divisor Latch Access */
+
+/* UARTx_MCR Mask                                                                               */
+#define LOOP            0x10    /* Loopback Mode Enable         */
+
+/* UARTx_LSR Masks                                                                              */
+#define DR                      0x01    /* Data Ready                           */
+#define OE                      0x02    /* Overrun Error                        */
+#define PE                      0x04    /* Parity Error                         */
+#define FE                      0x08    /* Framing Error                        */
+#define BI                      0x10    /* Break Interrupt                      */
+#define THRE            0x20    /* THR Empty                            */
+#define TEMT            0x40    /* TSR and UART_THR Empty       */
+
+/* UARTx_IER Masks                                                                                                                      */
+#define ERBFI           0x01    /* Enable Receive Buffer Full Interrupt         */
+#define ETBEI           0x02    /* Enable Transmit Buffer Empty Interrupt       */
+#define ELSI            0x04    /* Enable RX Status Interrupt                           */
+
+/* UARTx_IIR Masks                                                                                                              */
+#define NINT            0x01    /* Pending Interrupt                                    */
+#define IIR_TX_READY    0x02    /* UART_THR empty                               */
+#define IIR_RX_READY    0x04    /* Receive data ready                           */
+#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
+#define IIR_STATUS      0x06
+
+/* UARTx_GCTL Masks                                                                                                     */
+#define UCEN            0x01    /* Enable UARTx Clocks                          */
+#define IREN            0x02    /* Enable IrDA Mode                                     */
+#define TPOLC           0x04    /* IrDA TX Polarity Change                      */
+#define RPOLC           0x08    /* IrDA RX Polarity Change                      */
+#define FPE                     0x10    /* Force Parity Error On Transmit       */
+#define FFE                     0x20    /* Force Framing Error On Transmit      */
+
+/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  ****************************/
+/* SPI_CTL Masks                                                                                                                                        */
+#define TIMOD           0x0003  /* Transfer Initiate Mode                                                       */
+#define RDBR_CORE       0x0000  /*              RDBR Read Initiates, IRQ When RDBR Full         */
+#define TDBR_CORE       0x0001  /*              TDBR Write Initiates, IRQ When TDBR Empty       */
+#define RDBR_DMA        0x0002  /*              DMA Read, DMA Until FIFO Empty                          */
+#define TDBR_DMA        0x0003  /*              DMA Write, DMA Until FIFO Full                          */
+#define SZ                      0x0004  /* Send Zero (When TDBR Empty, Send Zero/Last*)         */
+#define GM                      0x0008  /* Get More (When RDBR Full, Overwrite/Discard*)        */
+#define PSSE            0x0010  /* Slave-Select Input Enable                                            */
+#define EMISO           0x0020  /* Enable MISO As Output                                                        */
+#define SPI_SIZE        0x0100  /* Size of Words (16/8* Bits)                                           */
+#define LSBF            0x0200  /* LSB First                                                                            */
+#define CPHA            0x0400  /* Clock Phase                                                                          */
+#define CPOL            0x0800  /* Clock Polarity                                                                       */
+#define MSTR            0x1000  /* Master/Slave*                                                                        */
+#define WOM                     0x2000  /* Write Open Drain Master                                                      */
+#define SPE                     0x4000  /* SPI Enable                                                                           */
+
+/* SPI_FLG Masks                                                                                                                                        */
+#define FLS1            0x0002  /* Enables SPI_FLOUT1 as SPI Slave-Select Output        */
+#define FLS2            0x0004  /* Enables SPI_FLOUT2 as SPI Slave-Select Output        */
+#define FLS3            0x0008  /* Enables SPI_FLOUT3 as SPI Slave-Select Output        */
+#define FLS4            0x0010  /* Enables SPI_FLOUT4 as SPI Slave-Select Output        */
+#define FLS5            0x0020  /* Enables SPI_FLOUT5 as SPI Slave-Select Output        */
+#define FLS6            0x0040  /* Enables SPI_FLOUT6 as SPI Slave-Select Output        */
+#define FLS7            0x0080  /* Enables SPI_FLOUT7 as SPI Slave-Select Output        */
+#define FLG1            0xFDFF  /* Activates SPI_FLOUT1                                                         */
+#define FLG2            0xFBFF  /* Activates SPI_FLOUT2                                                         */
+#define FLG3            0xF7FF  /* Activates SPI_FLOUT3                                                         */
+#define FLG4            0xEFFF  /* Activates SPI_FLOUT4                                                         */
+#define FLG5            0xDFFF  /* Activates SPI_FLOUT5                                                         */
+#define FLG6            0xBFFF  /* Activates SPI_FLOUT6                                                         */
+#define FLG7            0x7FFF  /* Activates SPI_FLOUT7                                                         */
+
+/* SPI_STAT Masks                                                                                                                                                               */
+#define SPIF            0x0001  /* SPI Finished (Single-Word Transfer Complete)                                 */
+#define MODF            0x0002  /* Mode Fault Error (Another Device Tried To Become Master)             */
+#define TXE                     0x0004  /* Transmission Error (Data Sent With No New Data In TDBR)              */
+#define TXS                     0x0008  /* SPI_TDBR Data Buffer Status (Full/Empty*)                                    */
+#define RBSY            0x0010  /* Receive Error (Data Received With RDBR Full)                                 */
+#define RXS                     0x0020  /* SPI_RDBR Data Buffer Status (Full/Empty*)                                    */
+#define TXCOL           0x0040  /* Transmit Collision Error (Corrupt Data May Have Been Sent)   */
+
+/*  ****************  GENERAL PURPOSE TIMER MASKS  **********************/
+/* TIMER_ENABLE Masks                                                                                                   */
+#define TIMEN0                  0x0001  /* Enable Timer 0                                       */
+#define TIMEN1                  0x0002  /* Enable Timer 1                                       */
+#define TIMEN2                  0x0004  /* Enable Timer 2                                       */
+#define TIMEN3                  0x0008  /* Enable Timer 3                                       */
+#define TIMEN4                  0x0010  /* Enable Timer 4                                       */
+#define TIMEN5                  0x0020  /* Enable Timer 5                                       */
+#define TIMEN6                  0x0040  /* Enable Timer 6                                       */
+#define TIMEN7                  0x0080  /* Enable Timer 7                                       */
+
+/* TIMER_DISABLE Masks                                                                                                  */
+#define TIMDIS0                 TIMEN0  /* Disable Timer 0                                      */
+#define TIMDIS1                 TIMEN1  /* Disable Timer 1                                      */
+#define TIMDIS2                 TIMEN2  /* Disable Timer 2                                      */
+#define TIMDIS3                 TIMEN3  /* Disable Timer 3                                      */
+#define TIMDIS4                 TIMEN4  /* Disable Timer 4                                      */
+#define TIMDIS5                 TIMEN5  /* Disable Timer 5                                      */
+#define TIMDIS6                 TIMEN6  /* Disable Timer 6                                      */
+#define TIMDIS7                 TIMEN7  /* Disable Timer 7                                      */
+
+/* TIMER_STATUS Masks                                                                                                   */
+#define TIMIL0                  0x00000001      /* Timer 0 Interrupt                            */
+#define TIMIL1                  0x00000002      /* Timer 1 Interrupt                            */
+#define TIMIL2                  0x00000004      /* Timer 2 Interrupt                            */
+#define TIMIL3                  0x00000008      /* Timer 3 Interrupt                            */
+#define TOVL_ERR0               0x00000010      /* Timer 0 Counter Overflow                     */
+#define TOVL_ERR1               0x00000020      /* Timer 1 Counter Overflow                     */
+#define TOVL_ERR2               0x00000040      /* Timer 2 Counter Overflow                     */
+#define TOVL_ERR3               0x00000080      /* Timer 3 Counter Overflow                     */
+#define TRUN0                   0x00001000      /* Timer 0 Slave Enable Status          */
+#define TRUN1                   0x00002000      /* Timer 1 Slave Enable Status          */
+#define TRUN2                   0x00004000      /* Timer 2 Slave Enable Status          */
+#define TRUN3                   0x00008000      /* Timer 3 Slave Enable Status          */
+#define TIMIL4                  0x00010000      /* Timer 4 Interrupt                            */
+#define TIMIL5                  0x00020000      /* Timer 5 Interrupt                            */
+#define TIMIL6                  0x00040000      /* Timer 6 Interrupt                            */
+#define TIMIL7                  0x00080000      /* Timer 7 Interrupt                            */
+#define TOVL_ERR4               0x00100000      /* Timer 4 Counter Overflow                     */
+#define TOVL_ERR5               0x00200000      /* Timer 5 Counter Overflow                     */
+#define TOVL_ERR6               0x00400000      /* Timer 6 Counter Overflow                     */
+#define TOVL_ERR7               0x00800000      /* Timer 7 Counter Overflow                     */
+#define TRUN4                   0x10000000      /* Timer 4 Slave Enable Status          */
+#define TRUN5                   0x20000000      /* Timer 5 Slave Enable Status          */
+#define TRUN6                   0x40000000      /* Timer 6 Slave Enable Status          */
+#define TRUN7                   0x80000000      /* Timer 7 Slave Enable Status          */
+
+/* TIMERx_CONFIG Masks                                                                                                  */
+#define PWM_OUT                 0x0001  /* Pulse-Width Modulation Output Mode   */
+#define WDTH_CAP                0x0002  /* Width Capture Input Mode                             */
+#define EXT_CLK                 0x0003  /* External Clock Mode                                  */
+#define PULSE_HI                0x0004  /* Action Pulse (Positive/Negative*)    */
+#define PERIOD_CNT              0x0008  /* Period Count                                                 */
+#define IRQ_ENA                 0x0010  /* Interrupt Request Enable                             */
+#define TIN_SEL                 0x0020  /* Timer Input Select                                   */
+#define OUT_DIS                 0x0040  /* Output Pad Disable                                   */
+#define CLK_SEL                 0x0080  /* Timer Clock Select                                   */
+#define TOGGLE_HI               0x0100  /* PWM_OUT PULSE_HI Toggle Mode                 */
+#define EMU_RUN                 0x0200  /* Emulation Behavior Select                    */
+#define ERR_TYP                 0xC000  /* Error Type                                                   */
+
+/* ******************   GPIO PORTS F, G, H MASKS  ***********************/
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks                                 */
+/* Port F Masks                                                                                                                 */
+#define PF0             0x0001
+#define PF1             0x0002
+#define PF2             0x0004
+#define PF3             0x0008
+#define PF4             0x0010
+#define PF5             0x0020
+#define PF6             0x0040
+#define PF7             0x0080
+#define PF8             0x0100
+#define PF9             0x0200
+#define PF10    0x0400
+#define PF11    0x0800
+#define PF12    0x1000
+#define PF13    0x2000
+#define PF14    0x4000
+#define PF15    0x8000
+
+/* Port G Masks                                                                                                                 */
+#define PG0             0x0001
+#define PG1             0x0002
+#define PG2             0x0004
+#define PG3             0x0008
+#define PG4             0x0010
+#define PG5             0x0020
+#define PG6             0x0040
+#define PG7             0x0080
+#define PG8             0x0100
+#define PG9             0x0200
+#define PG10    0x0400
+#define PG11    0x0800
+#define PG12    0x1000
+#define PG13    0x2000
+#define PG14    0x4000
+#define PG15    0x8000
+
+/* Port H Masks                                                                                                                 */
+#define PH0             0x0001
+#define PH1             0x0002
+#define PH2             0x0004
+#define PH3             0x0008
+#define PH4             0x0010
+#define PH5             0x0020
+#define PH6             0x0040
+#define PH7             0x0080
+#define PH8             0x0100
+#define PH9             0x0200
+#define PH10    0x0400
+#define PH11    0x0800
+#define PH12    0x1000
+#define PH13    0x2000
+#define PH14    0x4000
+#define PH15    0x8000
+
+/* *******************  SERIAL PORT MASKS  **************************************/
+/* SPORTx_TCR1 Masks                                                                                                                    */
+#define TSPEN           0x0001  /* Transmit Enable                                                              */
+#define ITCLK           0x0002  /* Internal Transmit Clock Select                               */
+#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
+#define TLSBIT          0x0010  /* Transmit Bit Order                                                   */
+#define ITFS            0x0200  /* Internal Transmit Frame Sync Select                  */
+#define TFSR            0x0400  /* Transmit Frame Sync Required Select                  */
+#define DITFS           0x0800  /* Data-Independent Transmit Frame Sync Select  */
+#define LTFS            0x1000  /* Low Transmit Frame Sync Select                               */
+#define LATFS           0x2000  /* Late Transmit Frame Sync Select                              */
+#define TCKFE           0x4000  /* Clock Falling Edge Select                                    */
+
+/* SPORTx_TCR2 Masks and Macro                                                                                                  */
+#define SLEN(x)         ((x)&0x1F)      /* SPORT TX Word Length (2 - 31)                                */
+#define TXSE            0x0100  /* TX Secondary Enable                                                  */
+#define TSFSE           0x0200  /* Transmit Stereo Frame Sync Enable                    */
+#define TRFST           0x0400  /* Left/Right Order (1 = Right Channel 1st)             */
+
+/* SPORTx_RCR1 Masks                                                                                                                    */
+#define RSPEN           0x0001  /* Receive Enable                                                               */
+#define IRCLK           0x0002  /* Internal Receive Clock Select                                */
+#define DTYPE_NORM      0x0004  /* Data Format Normal                                                   */
+#define DTYPE_ULAW      0x0008  /* Compand Using u-Law                                                  */
+#define DTYPE_ALAW      0x000C  /* Compand Using A-Law                                                  */
+#define RLSBIT          0x0010  /* Receive Bit Order                                                    */
+#define IRFS            0x0200  /* Internal Receive Frame Sync Select                   */
+#define RFSR            0x0400  /* Receive Frame Sync Required Select                   */
+#define LRFS            0x1000  /* Low Receive Frame Sync Select                                */
+#define LARFS           0x2000  /* Late Receive Frame Sync Select                               */
+#define RCKFE           0x4000  /* Clock Falling Edge Select                                    */
+
+/* SPORTx_RCR2 Masks                                                                                                                    */
+#define SLEN(x)         ((x)&0x1F)      /* SPORT RX Word Length (2 - 31)                                */
+#define RXSE            0x0100  /* RX Secondary Enable                                                  */
+#define RSFSE           0x0200  /* RX Stereo Frame Sync Enable                                  */
+#define RRFST           0x0400  /* Right-First Data Order                                               */
+
+/* SPORTx_STAT Masks                                                                                                                    */
+#define RXNE            0x0001  /* Receive FIFO Not Empty Status                                */
+#define RUVF            0x0002  /* Sticky Receive Underflow Status                              */
+#define ROVF            0x0004  /* Sticky Receive Overflow Status                               */
+#define TXF                     0x0008  /* Transmit FIFO Full Status                                    */
+#define TUVF            0x0010  /* Sticky Transmit Underflow Status                             */
+#define TOVF            0x0020  /* Sticky Transmit Overflow Status                              */
+#define TXHRE           0x0040  /* Transmit Hold Register Empty                                 */
+
+/* SPORTx_MCMC1 Macros                                                                                                                  */
+#define SP_WOFF(x)              ((x) & 0x3FF)   /* Multichannel Window Offset Field                     */
+
+/* Only use WSIZE Macro With Logic OR While Setting Lower Order Bits                                            */
+#define SP_WSIZE(x)     (((((x)>>0x3)-1)&0xF) << 0xC)   /* Multichannel Window Size = (x/8)-1   */
+
+/* SPORTx_MCMC2 Masks                                                                                                                   */
+#define REC_BYPASS      0x0000  /* Bypass Mode (No Clock Recovery)                              */
+#define REC_2FROM4      0x0002  /* Recover 2 MHz Clock from 4 MHz Clock                 */
+#define REC_8FROM16     0x0003  /* Recover 8 MHz Clock from 16 MHz Clock                */
+#define MCDTXPE         0x0004  /* Multichannel DMA Transmit Packing                    */
+#define MCDRXPE         0x0008  /* Multichannel DMA Receive Packing                             */
+#define MCMEN           0x0010  /* Multichannel Frame Mode Enable                               */
+#define FSDR            0x0080  /* Multichannel Frame Sync to Data Relationship */
+#define MFD_0           0x0000  /* Multichannel Frame Delay = 0                                 */
+#define MFD_1           0x1000  /* Multichannel Frame Delay = 1                                 */
+#define MFD_2           0x2000  /* Multichannel Frame Delay = 2                                 */
+#define MFD_3           0x3000  /* Multichannel Frame Delay = 3                                 */
+#define MFD_4           0x4000  /* Multichannel Frame Delay = 4                                 */
+#define MFD_5           0x5000  /* Multichannel Frame Delay = 5                                 */
+#define MFD_6           0x6000  /* Multichannel Frame Delay = 6                                 */
+#define MFD_7           0x7000  /* Multichannel Frame Delay = 7                                 */
+#define MFD_8           0x8000  /* Multichannel Frame Delay = 8                                 */
+#define MFD_9           0x9000  /* Multichannel Frame Delay = 9                                 */
+#define MFD_10          0xA000  /* Multichannel Frame Delay = 10                                */
+#define MFD_11          0xB000  /* Multichannel Frame Delay = 11                                */
+#define MFD_12          0xC000  /* Multichannel Frame Delay = 12                                */
+#define MFD_13          0xD000  /* Multichannel Frame Delay = 13                                */
+#define MFD_14          0xE000  /* Multichannel Frame Delay = 14                                */
+#define MFD_15          0xF000  /* Multichannel Frame Delay = 15                                */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  *************************/
+/* EBIU_AMGCTL Masks                                                                                                                                    */
+#define AMCKEN                  0x0001  /* Enable CLKOUT                                                                        */
+#define AMBEN_NONE              0x0000  /* All Banks Disabled                                                           */
+#define AMBEN_B0                0x0002  /* Enable Async Memory Bank 0 only                                      */
+#define AMBEN_B0_B1             0x0004  /* Enable Async Memory Banks 0 & 1 only                         */
+#define AMBEN_B0_B1_B2  0x0006  /* Enable Async Memory Banks 0, 1, and 2                        */
+#define AMBEN_ALL               0x0008  /* Enable Async Memory Banks (all) 0, 1, 2, and 3       */
+
+/* EBIU_AMBCTL0 Masks                                                                                                                                   */
+#define B0RDYEN                 0x00000001      /* Bank 0 (B0) RDY Enable                                                   */
+#define B0RDYPOL                0x00000002      /* B0 RDY Active High                                                               */
+#define B0TT_1                  0x00000004      /* B0 Transition Time (Read to Write) = 1 cycle             */
+#define B0TT_2                  0x00000008      /* B0 Transition Time (Read to Write) = 2 cycles    */
+#define B0TT_3                  0x0000000C      /* B0 Transition Time (Read to Write) = 3 cycles    */
+#define B0TT_4                  0x00000000      /* B0 Transition Time (Read to Write) = 4 cycles    */
+#define B0ST_1                  0x00000010      /* B0 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B0ST_2                  0x00000020      /* B0 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B0ST_3                  0x00000030      /* B0 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B0ST_4                  0x00000000      /* B0 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B0HT_1                  0x00000040      /* B0 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B0HT_2                  0x00000080      /* B0 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B0HT_3                  0x000000C0      /* B0 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B0HT_0                  0x00000000      /* B0 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B0RAT_1                 0x00000100      /* B0 Read Access Time = 1 cycle                                    */
+#define B0RAT_2                 0x00000200      /* B0 Read Access Time = 2 cycles                                   */
+#define B0RAT_3                 0x00000300      /* B0 Read Access Time = 3 cycles                                   */
+#define B0RAT_4                 0x00000400      /* B0 Read Access Time = 4 cycles                                   */
+#define B0RAT_5                 0x00000500      /* B0 Read Access Time = 5 cycles                                   */
+#define B0RAT_6                 0x00000600      /* B0 Read Access Time = 6 cycles                                   */
+#define B0RAT_7                 0x00000700      /* B0 Read Access Time = 7 cycles                                   */
+#define B0RAT_8                 0x00000800      /* B0 Read Access Time = 8 cycles                                   */
+#define B0RAT_9                 0x00000900      /* B0 Read Access Time = 9 cycles                                   */
+#define B0RAT_10                0x00000A00      /* B0 Read Access Time = 10 cycles                                  */
+#define B0RAT_11                0x00000B00      /* B0 Read Access Time = 11 cycles                                  */
+#define B0RAT_12                0x00000C00      /* B0 Read Access Time = 12 cycles                                  */
+#define B0RAT_13                0x00000D00      /* B0 Read Access Time = 13 cycles                                  */
+#define B0RAT_14                0x00000E00      /* B0 Read Access Time = 14 cycles                                  */
+#define B0RAT_15                0x00000F00      /* B0 Read Access Time = 15 cycles                                  */
+#define B0WAT_1                 0x00001000      /* B0 Write Access Time = 1 cycle                                   */
+#define B0WAT_2                 0x00002000      /* B0 Write Access Time = 2 cycles                                  */
+#define B0WAT_3                 0x00003000      /* B0 Write Access Time = 3 cycles                                  */
+#define B0WAT_4                 0x00004000      /* B0 Write Access Time = 4 cycles                                  */
+#define B0WAT_5                 0x00005000      /* B0 Write Access Time = 5 cycles                                  */
+#define B0WAT_6                 0x00006000      /* B0 Write Access Time = 6 cycles                                  */
+#define B0WAT_7                 0x00007000      /* B0 Write Access Time = 7 cycles                                  */
+#define B0WAT_8                 0x00008000      /* B0 Write Access Time = 8 cycles                                  */
+#define B0WAT_9                 0x00009000      /* B0 Write Access Time = 9 cycles                                  */
+#define B0WAT_10                0x0000A000      /* B0 Write Access Time = 10 cycles                                 */
+#define B0WAT_11                0x0000B000      /* B0 Write Access Time = 11 cycles                                 */
+#define B0WAT_12                0x0000C000      /* B0 Write Access Time = 12 cycles                                 */
+#define B0WAT_13                0x0000D000      /* B0 Write Access Time = 13 cycles                                 */
+#define B0WAT_14                0x0000E000      /* B0 Write Access Time = 14 cycles                                 */
+#define B0WAT_15                0x0000F000      /* B0 Write Access Time = 15 cycles                                 */
+
+#define B1RDYEN                 0x00010000      /* Bank 1 (B1) RDY Enable                           */
+#define B1RDYPOL                0x00020000      /* B1 RDY Active High                               */
+#define B1TT_1                  0x00040000      /* B1 Transition Time (Read to Write) = 1 cycle     */
+#define B1TT_2                  0x00080000      /* B1 Transition Time (Read to Write) = 2 cycles    */
+#define B1TT_3                  0x000C0000      /* B1 Transition Time (Read to Write) = 3 cycles    */
+#define B1TT_4                  0x00000000      /* B1 Transition Time (Read to Write) = 4 cycles    */
+#define B1ST_1                  0x00100000      /* B1 Setup Time (AOE to Read/Write) = 1 cycle      */
+#define B1ST_2                  0x00200000      /* B1 Setup Time (AOE to Read/Write) = 2 cycles     */
+#define B1ST_3                  0x00300000      /* B1 Setup Time (AOE to Read/Write) = 3 cycles     */
+#define B1ST_4                  0x00000000      /* B1 Setup Time (AOE to Read/Write) = 4 cycles     */
+#define B1HT_1                  0x00400000      /* B1 Hold Time (~Read/Write to ~AOE) = 1 cycle     */
+#define B1HT_2                  0x00800000      /* B1 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B1HT_3                  0x00C00000      /* B1 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B1HT_0                  0x00000000      /* B1 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B1RAT_1                 0x01000000      /* B1 Read Access Time = 1 cycle                                    */
+#define B1RAT_2                 0x02000000      /* B1 Read Access Time = 2 cycles                                   */
+#define B1RAT_3                 0x03000000      /* B1 Read Access Time = 3 cycles                                   */
+#define B1RAT_4                 0x04000000      /* B1 Read Access Time = 4 cycles                                   */
+#define B1RAT_5                 0x05000000      /* B1 Read Access Time = 5 cycles                                   */
+#define B1RAT_6                 0x06000000      /* B1 Read Access Time = 6 cycles                                   */
+#define B1RAT_7                 0x07000000      /* B1 Read Access Time = 7 cycles                                   */
+#define B1RAT_8                 0x08000000      /* B1 Read Access Time = 8 cycles                                   */
+#define B1RAT_9                 0x09000000      /* B1 Read Access Time = 9 cycles                                   */
+#define B1RAT_10                0x0A000000      /* B1 Read Access Time = 10 cycles                                  */
+#define B1RAT_11                0x0B000000      /* B1 Read Access Time = 11 cycles                                  */
+#define B1RAT_12                0x0C000000      /* B1 Read Access Time = 12 cycles                                  */
+#define B1RAT_13                0x0D000000      /* B1 Read Access Time = 13 cycles                                  */
+#define B1RAT_14                0x0E000000      /* B1 Read Access Time = 14 cycles                                  */
+#define B1RAT_15                0x0F000000      /* B1 Read Access Time = 15 cycles                                  */
+#define B1WAT_1                 0x10000000      /* B1 Write Access Time = 1 cycle                                   */
+#define B1WAT_2                 0x20000000      /* B1 Write Access Time = 2 cycles                                  */
+#define B1WAT_3                 0x30000000      /* B1 Write Access Time = 3 cycles                                  */
+#define B1WAT_4                 0x40000000      /* B1 Write Access Time = 4 cycles                                  */
+#define B1WAT_5                 0x50000000      /* B1 Write Access Time = 5 cycles                                  */
+#define B1WAT_6                 0x60000000      /* B1 Write Access Time = 6 cycles                                  */
+#define B1WAT_7                 0x70000000      /* B1 Write Access Time = 7 cycles                                  */
+#define B1WAT_8                 0x80000000      /* B1 Write Access Time = 8 cycles                                  */
+#define B1WAT_9                 0x90000000      /* B1 Write Access Time = 9 cycles                                  */
+#define B1WAT_10                0xA0000000      /* B1 Write Access Time = 10 cycles                                 */
+#define B1WAT_11                0xB0000000      /* B1 Write Access Time = 11 cycles                                 */
+#define B1WAT_12                0xC0000000      /* B1 Write Access Time = 12 cycles                                 */
+#define B1WAT_13                0xD0000000      /* B1 Write Access Time = 13 cycles                                 */
+#define B1WAT_14                0xE0000000      /* B1 Write Access Time = 14 cycles                                 */
+#define B1WAT_15                0xF0000000      /* B1 Write Access Time = 15 cycles                                 */
+
+/* EBIU_AMBCTL1 Masks                                                                                                                                   */
+#define B2RDYEN                 0x00000001      /* Bank 2 (B2) RDY Enable                                                   */
+#define B2RDYPOL                0x00000002      /* B2 RDY Active High                                                               */
+#define B2TT_1                  0x00000004      /* B2 Transition Time (Read to Write) = 1 cycle             */
+#define B2TT_2                  0x00000008      /* B2 Transition Time (Read to Write) = 2 cycles    */
+#define B2TT_3                  0x0000000C      /* B2 Transition Time (Read to Write) = 3 cycles    */
+#define B2TT_4                  0x00000000      /* B2 Transition Time (Read to Write) = 4 cycles    */
+#define B2ST_1                  0x00000010      /* B2 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B2ST_2                  0x00000020      /* B2 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B2ST_3                  0x00000030      /* B2 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B2ST_4                  0x00000000      /* B2 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B2HT_1                  0x00000040      /* B2 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B2HT_2                  0x00000080      /* B2 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B2HT_3                  0x000000C0      /* B2 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B2HT_0                  0x00000000      /* B2 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B2RAT_1                 0x00000100      /* B2 Read Access Time = 1 cycle                                    */
+#define B2RAT_2                 0x00000200      /* B2 Read Access Time = 2 cycles                                   */
+#define B2RAT_3                 0x00000300      /* B2 Read Access Time = 3 cycles                                   */
+#define B2RAT_4                 0x00000400      /* B2 Read Access Time = 4 cycles                                   */
+#define B2RAT_5                 0x00000500      /* B2 Read Access Time = 5 cycles                                   */
+#define B2RAT_6                 0x00000600      /* B2 Read Access Time = 6 cycles                                   */
+#define B2RAT_7                 0x00000700      /* B2 Read Access Time = 7 cycles                                   */
+#define B2RAT_8                 0x00000800      /* B2 Read Access Time = 8 cycles                                   */
+#define B2RAT_9                 0x00000900      /* B2 Read Access Time = 9 cycles                                   */
+#define B2RAT_10                0x00000A00      /* B2 Read Access Time = 10 cycles                                  */
+#define B2RAT_11                0x00000B00      /* B2 Read Access Time = 11 cycles                                  */
+#define B2RAT_12                0x00000C00      /* B2 Read Access Time = 12 cycles                                  */
+#define B2RAT_13                0x00000D00      /* B2 Read Access Time = 13 cycles                                  */
+#define B2RAT_14                0x00000E00      /* B2 Read Access Time = 14 cycles                                  */
+#define B2RAT_15                0x00000F00      /* B2 Read Access Time = 15 cycles                                  */
+#define B2WAT_1                 0x00001000      /* B2 Write Access Time = 1 cycle                                   */
+#define B2WAT_2                 0x00002000      /* B2 Write Access Time = 2 cycles                                  */
+#define B2WAT_3                 0x00003000      /* B2 Write Access Time = 3 cycles                                  */
+#define B2WAT_4                 0x00004000      /* B2 Write Access Time = 4 cycles                                  */
+#define B2WAT_5                 0x00005000      /* B2 Write Access Time = 5 cycles                                  */
+#define B2WAT_6                 0x00006000      /* B2 Write Access Time = 6 cycles                                  */
+#define B2WAT_7                 0x00007000      /* B2 Write Access Time = 7 cycles                                  */
+#define B2WAT_8                 0x00008000      /* B2 Write Access Time = 8 cycles                                  */
+#define B2WAT_9                 0x00009000      /* B2 Write Access Time = 9 cycles                                  */
+#define B2WAT_10                0x0000A000      /* B2 Write Access Time = 10 cycles                                 */
+#define B2WAT_11                0x0000B000      /* B2 Write Access Time = 11 cycles                                 */
+#define B2WAT_12                0x0000C000      /* B2 Write Access Time = 12 cycles                                 */
+#define B2WAT_13                0x0000D000      /* B2 Write Access Time = 13 cycles                                 */
+#define B2WAT_14                0x0000E000      /* B2 Write Access Time = 14 cycles                                 */
+#define B2WAT_15                0x0000F000      /* B2 Write Access Time = 15 cycles                                 */
+
+#define B3RDYEN                 0x00010000      /* Bank 3 (B3) RDY Enable                                                   */
+#define B3RDYPOL                0x00020000      /* B3 RDY Active High                                                               */
+#define B3TT_1                  0x00040000      /* B3 Transition Time (Read to Write) = 1 cycle             */
+#define B3TT_2                  0x00080000      /* B3 Transition Time (Read to Write) = 2 cycles    */
+#define B3TT_3                  0x000C0000      /* B3 Transition Time (Read to Write) = 3 cycles    */
+#define B3TT_4                  0x00000000      /* B3 Transition Time (Read to Write) = 4 cycles    */
+#define B3ST_1                  0x00100000      /* B3 Setup Time (AOE to Read/Write) = 1 cycle              */
+#define B3ST_2                  0x00200000      /* B3 Setup Time (AOE to Read/Write) = 2 cycles             */
+#define B3ST_3                  0x00300000      /* B3 Setup Time (AOE to Read/Write) = 3 cycles             */
+#define B3ST_4                  0x00000000      /* B3 Setup Time (AOE to Read/Write) = 4 cycles             */
+#define B3HT_1                  0x00400000      /* B3 Hold Time (~Read/Write to ~AOE) = 1 cycle             */
+#define B3HT_2                  0x00800000      /* B3 Hold Time (~Read/Write to ~AOE) = 2 cycles    */
+#define B3HT_3                  0x00C00000      /* B3 Hold Time (~Read/Write to ~AOE) = 3 cycles    */
+#define B3HT_0                  0x00000000      /* B3 Hold Time (~Read/Write to ~AOE) = 0 cycles    */
+#define B3RAT_1                 0x01000000      /* B3 Read Access Time = 1 cycle                                    */
+#define B3RAT_2                 0x02000000      /* B3 Read Access Time = 2 cycles                                   */
+#define B3RAT_3                 0x03000000      /* B3 Read Access Time = 3 cycles                                   */
+#define B3RAT_4                 0x04000000      /* B3 Read Access Time = 4 cycles                                   */
+#define B3RAT_5                 0x05000000      /* B3 Read Access Time = 5 cycles                                   */
+#define B3RAT_6                 0x06000000      /* B3 Read Access Time = 6 cycles                                   */
+#define B3RAT_7                 0x07000000      /* B3 Read Access Time = 7 cycles                                   */
+#define B3RAT_8                 0x08000000      /* B3 Read Access Time = 8 cycles                                   */
+#define B3RAT_9                 0x09000000      /* B3 Read Access Time = 9 cycles                                   */
+#define B3RAT_10                0x0A000000      /* B3 Read Access Time = 10 cycles                                  */
+#define B3RAT_11                0x0B000000      /* B3 Read Access Time = 11 cycles                                  */
+#define B3RAT_12                0x0C000000      /* B3 Read Access Time = 12 cycles                                  */
+#define B3RAT_13                0x0D000000      /* B3 Read Access Time = 13 cycles                                  */
+#define B3RAT_14                0x0E000000      /* B3 Read Access Time = 14 cycles                                  */
+#define B3RAT_15                0x0F000000      /* B3 Read Access Time = 15 cycles                                  */
+#define B3WAT_1                 0x10000000      /* B3 Write Access Time = 1 cycle                                   */
+#define B3WAT_2                 0x20000000      /* B3 Write Access Time = 2 cycles                                  */
+#define B3WAT_3                 0x30000000      /* B3 Write Access Time = 3 cycles                                  */
+#define B3WAT_4                 0x40000000      /* B3 Write Access Time = 4 cycles                                  */
+#define B3WAT_5                 0x50000000      /* B3 Write Access Time = 5 cycles                                  */
+#define B3WAT_6                 0x60000000      /* B3 Write Access Time = 6 cycles                                  */
+#define B3WAT_7                 0x70000000      /* B3 Write Access Time = 7 cycles                                  */
+#define B3WAT_8                 0x80000000      /* B3 Write Access Time = 8 cycles                                  */
+#define B3WAT_9                 0x90000000      /* B3 Write Access Time = 9 cycles                                  */
+#define B3WAT_10                0xA0000000      /* B3 Write Access Time = 10 cycles                                 */
+#define B3WAT_11                0xB0000000      /* B3 Write Access Time = 11 cycles                                 */
+#define B3WAT_12                0xC0000000      /* B3 Write Access Time = 12 cycles                                 */
+#define B3WAT_13                0xD0000000      /* B3 Write Access Time = 13 cycles                                 */
+#define B3WAT_14                0xE0000000      /* B3 Write Access Time = 14 cycles                                 */
+#define B3WAT_15                0xF0000000      /* B3 Write Access Time = 15 cycles                                 */
+
+/* **********************  SDRAM CONTROLLER MASKS  **********************************************/
+/* EBIU_SDGCTL Masks                                                                                                                                                    */
+#define SCTLE                   0x00000001      /* Enable SDRAM Signals                                                                         */
+#define CL_2                    0x00000008      /* SDRAM CAS Latency = 2 cycles                                                         */
+#define CL_3                    0x0000000C      /* SDRAM CAS Latency = 3 cycles                                                         */
+#define PASR_ALL                0x00000000      /* All 4 SDRAM Banks Refreshed In Self-Refresh                          */
+#define PASR_B0_B1              0x00000010      /* SDRAM Banks 0 and 1 Are Refreshed In Self-Refresh            */
+#define PASR_B0                 0x00000020      /* Only SDRAM Bank 0 Is Refreshed In Self-Refresh                       */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle                                                                         */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles                                                                        */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles                                                                        */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles                                                                        */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles                                                                        */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles                                                                        */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles                                                                        */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles                                                                        */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles                                                                        */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles                                                                       */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles                                                                       */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles                                                                       */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles                                                                       */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles                                                                       */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles                                                                       */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle                                                                          */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles                                                                         */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles                                                                         */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles                                                                         */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles                                                                         */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles                                                                         */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles                                                                         */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle                                                                         */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles                                                                        */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles                                                                        */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles                                                                        */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles                                                                        */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles                                                                        */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles                                                                        */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle                                                                          */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles                                                                         */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles                                                                         */
+#define PUPSD                   0x00200000      /* Power-Up Start Delay (15 SCLK Cycles Delay)                          */
+#define PSM                             0x00400000      /* Power-Up Sequence (Mode Register Before/After* Refresh)      */
+#define PSS                             0x00800000      /* Enable Power-Up Sequence on Next SDRAM Access                        */
+#define SRFS                    0x01000000      /* Enable SDRAM Self-Refresh Mode                                                       */
+#define EBUFE                   0x02000000      /* Enable External Buffering Timing                                                     */
+#define FBBRW                   0x04000000      /* Enable Fast Back-To-Back Read To Write                                       */
+#define EMREN                   0x10000000      /* Extended Mode Register Enable                                                        */
+#define TCSR                    0x20000000      /* Temp-Compensated Self-Refresh Value (85/45* Deg C)           */
+#define CDDBG                   0x40000000      /* Tristate SDRAM Controls During Bus Grant                                     */
+
+/* EBIU_SDBCTL Masks                                                                                                                                            */
+#define EBE                             0x0001  /* Enable SDRAM External Bank                                                   */
+#define EBSZ_16                 0x0000  /* SDRAM External Bank Size = 16MB                                              */
+#define EBSZ_32                 0x0002  /* SDRAM External Bank Size = 32MB                                              */
+#define EBSZ_64                 0x0004  /* SDRAM External Bank Size = 64MB                                              */
+#define EBSZ_128                0x0006  /* SDRAM External Bank Size = 128MB                                             */
+#define EBCAW_8                 0x0000  /* SDRAM External Bank Column Address Width = 8 Bits    */
+#define EBCAW_9                 0x0010  /* SDRAM External Bank Column Address Width = 9 Bits    */
+#define EBCAW_10                0x0020  /* SDRAM External Bank Column Address Width = 10 Bits   */
+#define EBCAW_11                0x0030  /* SDRAM External Bank Column Address Width = 11 Bits   */
+
+/* EBIU_SDSTAT Masks                                                                                                            */
+#define SDCI                    0x0001  /* SDRAM Controller Idle                                */
+#define SDSRA                   0x0002  /* SDRAM Self-Refresh Active                    */
+#define SDPUA                   0x0004  /* SDRAM Power-Up Active                                */
+#define SDRS                    0x0008  /* SDRAM Will Power-Up On Next Access   */
+#define SDEASE                  0x0010  /* SDRAM EAB Sticky Error Status                */
+#define BGSTAT                  0x0020  /* Bus Grant Status                                             */
+
+/* **************************  DMA CONTROLLER MASKS  ********************************/
+/* DMAx_CONFIG, MDMA_yy_CONFIG Masks                                                                                            */
+#define DMAEN                   0x0001  /* DMA Channel Enable                                                   */
+#define WNR                             0x0002  /* Channel Direction (W/R*)                                             */
+#define WDSIZE_8                0x0000  /* Transfer Word Size = 8                                               */
+#define WDSIZE_16               0x0004  /* Transfer Word Size = 16                                              */
+#define WDSIZE_32               0x0008  /* Transfer Word Size = 32                                              */
+#define DMA2D                   0x0010  /* DMA Mode (2D/1D*)                                                    */
+#define RESTART                 0x0020  /* DMA Buffer Clear                                                             */
+#define DI_SEL                  0x0040  /* Data Interrupt Timing Select                                 */
+#define DI_EN                   0x0080  /* Data Interrupt Enable                                                */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
+#define NDSIZE                  0x0900  /* Next Descriptor Size */
+
+#define DMAFLOW                 0x7000  /* Flow Control */
+#define DMAFLOW_STOP            0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP Masks                                                            */
+#define CTYPE                   0x0040  /* DMA Channel Type Indicator (Memory/Peripheral*)      */
+#define PMAP                    0xF000  /* Peripheral Mapped To This Channel                            */
+#define PMAP_PPI                0x0000  /*              PPI Port DMA                                                            */
+#define PMAP_EMACRX             0x1000  /*              Ethernet Receive DMA                                            */
+#define PMAP_EMACTX             0x2000  /*              Ethernet Transmit DMA                                           */
+#define PMAP_SPORT0RX   0x3000  /*              SPORT0 Receive DMA                                                      */
+#define PMAP_SPORT0TX   0x4000  /*              SPORT0 Transmit DMA                                                     */
+#define PMAP_SPORT1RX   0x5000  /*              SPORT1 Receive DMA                                                      */
+#define PMAP_SPORT1TX   0x6000  /*              SPORT1 Transmit DMA                                                     */
+#define PMAP_SPI                0x7000  /*              SPI Port DMA                                                            */
+#define PMAP_UART0RX    0x8000  /*              UART0 Port Receive DMA                                          */
+#define PMAP_UART0TX    0x9000  /*              UART0 Port Transmit DMA                                         */
+#define PMAP_UART1RX    0xA000  /*              UART1 Port Receive DMA                                          */
+#define PMAP_UART1TX    0xB000  /*              UART1 Port Transmit DMA                                         */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS Masks                                            */
+#define DMA_DONE                0x0001  /* DMA Completion Interrupt Status      */
+#define DMA_ERR                 0x0002  /* DMA Error Interrupt Status           */
+#define DFETCH                  0x0004  /* DMA Descriptor Fetch Indicator       */
+#define DMA_RUN                 0x0008  /* DMA Channel Running Indicator        */
+
+/*  ************  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS *************/
+/*  PPI_CONTROL Masks                                                                                                   */
+#define PORT_EN                 0x0001  /* PPI Port Enable                                      */
+#define PORT_DIR                0x0002  /* PPI Port Direction                           */
+#define XFR_TYPE                0x000C  /* PPI Transfer Type                            */
+#define PORT_CFG                0x0030  /* PPI Port Configuration                       */
+#define FLD_SEL                 0x0040  /* PPI Active Field Select                      */
+#define PACK_EN                 0x0080  /* PPI Packing Mode                                     */
+#define DMA32                   0x0100  /* PPI 32-bit DMA Enable                        */
+#define SKIP_EN                 0x0200  /* PPI Skip Element Enable                      */
+#define SKIP_EO                 0x0400  /* PPI Skip Even/Odd Elements           */
+#define DLENGTH         0x3800  /* PPI Data Length  */
+#define DLEN_8                  0x0000  /* Data Length = 8 Bits                         */
+#define DLEN_10                 0x0800  /* Data Length = 10 Bits                        */
+#define DLEN_11                 0x1000  /* Data Length = 11 Bits                        */
+#define DLEN_12                 0x1800  /* Data Length = 12 Bits                        */
+#define DLEN_13                 0x2000  /* Data Length = 13 Bits                        */
+#define DLEN_14                 0x2800  /* Data Length = 14 Bits                        */
+#define DLEN_15                 0x3000  /* Data Length = 15 Bits                        */
+#define DLEN_16                 0x3800  /* Data Length = 16 Bits                        */
+#define POLC                    0x4000  /* PPI Clock Polarity                           */
+#define POLS                    0x8000  /* PPI Frame Sync Polarity                      */
+
+/* PPI_STATUS Masks                                                                                                             */
+#define FLD                             0x0400  /* Field Indicator                                      */
+#define FT_ERR                  0x0800  /* Frame Track Error                            */
+#define OVR                             0x1000  /* FIFO Overflow Error                          */
+#define UNDR                    0x2000  /* FIFO Underrun Error                          */
+#define ERR_DET                 0x4000  /* Error Detected Indicator                     */
+#define ERR_NCOR                0x8000  /* Error Not Corrected Indicator        */
+
+/*  ********************  TWO-WIRE INTERFACE (TWI) MASKS  ***********************/
+/* TWI_CLKDIV Macros (Use: *pTWI_CLKDIV = CLKLOW(x)|CLKHI(y);  )                                */
+#define CLKLOW(x)       ((x) & 0xFF)    /* Periods Clock Is Held Low                    */
+#define CLKHI(y)        (((y)&0xFF)<<0x8)       /* Periods Before New Clock Low                 */
+
+/* TWI_PRESCALE Masks                                                                                                                   */
+#define PRESCALE        0x007F  /* SCLKs Per Internal Time Reference (10MHz)    */
+#define TWI_ENA         0x0080  /* TWI Enable                                                                   */
+#define SCCB            0x0200  /* SCCB Compatibility Enable                                    */
+
+/* TWI_SLAVE_CTRL Masks                                                                                                                 */
+#define SEN                     0x0001  /* Slave Enable                                                                 */
+#define SADD_LEN        0x0002  /* Slave Address Length                                                 */
+#define STDVAL          0x0004  /* Slave Transmit Data Valid                                    */
+#define NAK                     0x0008  /* NAK/ACK* Generated At Conclusion Of Transfer */
+#define GEN                     0x0010  /* General Call Adrress Matching Enabled                */
+
+/* TWI_SLAVE_STAT Masks                                                                                                                 */
+#define SDIR            0x0001  /* Slave Transfer Direction (Transmit/Receive*) */
+#define GCALL           0x0002  /* General Call Indicator                                               */
+
+/* TWI_MASTER_CTRL Masks                                                                                                        */
+#define MEN                     0x0001  /* Master Mode Enable                                           */
+#define MADD_LEN        0x0002  /* Master Address Length                                        */
+#define MDIR            0x0004  /* Master Transmit Direction (RX/TX*)           */
+#define FAST            0x0008  /* Use Fast Mode Timing Specs                           */
+#define STOP            0x0010  /* Issue Stop Condition                                         */
+#define RSTART          0x0020  /* Repeat Start or Stop* At End Of Transfer     */
+#define DCNT            0x3FC0  /* Data Bytes To Transfer                                       */
+#define SDAOVR          0x4000  /* Serial Data Override                                         */
+#define SCLOVR          0x8000  /* Serial Clock Override                                        */
+
+/* TWI_MASTER_STAT Masks                                                                                                                */
+#define MPROG           0x0001  /* Master Transfer In Progress                                  */
+#define LOSTARB         0x0002  /* Lost Arbitration Indicator (Xfer Aborted)    */
+#define ANAK            0x0004  /* Address Not Acknowledged                                             */
+#define DNAK            0x0008  /* Data Not Acknowledged                                                */
+#define BUFRDERR        0x0010  /* Buffer Read Error                                                    */
+#define BUFWRERR        0x0020  /* Buffer Write Error                                                   */
+#define SDASEN          0x0040  /* Serial Data Sense                                                    */
+#define SCLSEN          0x0080  /* Serial Clock Sense                                                   */
+#define BUSBUSY         0x0100  /* Bus Busy Indicator                                                   */
+
+/* TWI_INT_SRC and TWI_INT_ENABLE Masks                                         */
+#define SINIT           0x0001  /* Slave Transfer Initiated     */
+#define SCOMP           0x0002  /* Slave Transfer Complete      */
+#define SERR            0x0004  /* Slave Transfer Error         */
+#define SOVF            0x0008  /* Slave Overflow                       */
+#define MCOMP           0x0010  /* Master Transfer Complete     */
+#define MERR            0x0020  /* Master Transfer Error        */
+#define XMTSERV         0x0040  /* Transmit FIFO Service        */
+#define RCVSERV         0x0080  /* Receive FIFO Service         */
+
+/* TWI_FIFO_CTRL Masks                                                                                          */
+#define XMTFLUSH        0x0001  /* Transmit Buffer Flush                        */
+#define RCVFLUSH        0x0002  /* Receive Buffer Flush                         */
+#define XMTINTLEN       0x0004  /* Transmit Buffer Interrupt Length     */
+#define RCVINTLEN       0x0008  /* Receive Buffer Interrupt Length      */
+
+/* TWI_FIFO_STAT Masks                                                                                                                  */
+#define XMTSTAT         0x0003  /* Transmit FIFO Status                                                 */
+#define XMT_EMPTY       0x0000  /*              Transmit FIFO Empty                                             */
+#define XMT_HALF        0x0001  /*              Transmit FIFO Has 1 Byte To Write               */
+#define XMT_FULL        0x0003  /*              Transmit FIFO Full (2 Bytes To Write)   */
+
+#define RCVSTAT         0x000C  /* Receive FIFO Status                                                  */
+#define RCV_EMPTY       0x0000  /*              Receive FIFO Empty                                              */
+#define RCV_HALF        0x0004  /*              Receive FIFO Has 1 Byte To Read                 */
+#define RCV_FULL        0x000C  /*              Receive FIFO Full (2 Bytes To Read)             */
+
+/* ************  CONTROLLER AREA NETWORK (CAN) MASKS  ***************/
+/* CAN_CONTROL Masks                                                                                            */
+#define SRS                     0x0001  /* Software Reset                                               */
+#define DNM                     0x0002  /* Device Net Mode                                              */
+#define ABO                     0x0004  /* Auto-Bus On Enable                                   */
+#define TXPRIO          0x0008  /* TX Priority (Priority/Mailbox*)              */
+#define WBA                     0x0010  /* Wake-Up On CAN Bus Activity Enable   */
+#define SMR                     0x0020  /* Sleep Mode Request                                   */
+#define CSR                     0x0040  /* CAN Suspend Mode Request                             */
+#define CCR                     0x0080  /* CAN Configuration Mode Request               */
+
+/* CAN_STATUS Masks                                                                                             */
+#define WT                      0x0001  /* TX Warning Flag                                      */
+#define WR                      0x0002  /* RX Warning Flag                                      */
+#define EP                      0x0004  /* Error Passive Mode                           */
+#define EBO                     0x0008  /* Error Bus Off Mode                           */
+#define SMA                     0x0020  /* Sleep Mode Acknowledge                       */
+#define CSA                     0x0040  /* Suspend Mode Acknowledge                     */
+#define CCA                     0x0080  /* Configuration Mode Acknowledge       */
+#define MBPTR           0x1F00  /* Mailbox Pointer                                      */
+#define TRM                     0x4000  /* Transmit Mode                                        */
+#define REC                     0x8000  /* Receive Mode                                         */
+
+/* CAN_CLOCK Masks                                                                      */
+#define BRP                     0x03FF  /* Bit-Rate Pre-Scaler  */
+
+/* CAN_TIMING Masks                                                                                     */
+#define TSEG1           0x000F  /* Time Segment 1                               */
+#define TSEG2           0x0070  /* Time Segment 2                               */
+#define SAM                     0x0080  /* Sampling                                             */
+#define SJW                     0x0300  /* Synchronization Jump Width   */
+
+/* CAN_DEBUG Masks                                                                                      */
+#define DEC                     0x0001  /* Disable CAN Error Counters   */
+#define DRI                     0x0002  /* Disable CAN RX Input                 */
+#define DTO                     0x0004  /* Disable CAN TX Output                */
+#define DIL                     0x0008  /* Disable CAN Internal Loop    */
+#define MAA                     0x0010  /* Mode Auto-Acknowledge Enable */
+#define MRB                     0x0020  /* Mode Read Back Enable                */
+#define CDE                     0x8000  /* CAN Debug Enable                             */
+
+/* CAN_CEC Masks                                                                                */
+#define RXECNT          0x00FF  /* Receive Error Counter        */
+#define TXECNT          0xFF00  /* Transmit Error Counter       */
+
+/* CAN_INTR Masks                                                                                       */
+#define MBRIF           0x0001  /* Mailbox Receive Interrupt    */
+#define MBTIF           0x0002  /* Mailbox Transmit Interrupt   */
+#define GIRQ            0x0004  /* Global Interrupt                             */
+#define SMACK           0x0008  /* Sleep Mode Acknowledge               */
+#define CANTX           0x0040  /* CAN TX Bus Value                             */
+#define CANRX           0x0080  /* CAN RX Bus Value                             */
+
+/* CAN_MBxx_ID1 and CAN_MBxx_ID0 Masks                                                                          */
+#define DFC                     0xFFFF  /* Data Filtering Code (If Enabled) (ID0)               */
+#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (ID0)   */
+#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (ID1)    */
+#define BASEID          0x1FFC  /* Base Identifier                                                              */
+#define IDE                     0x2000  /* Identifier Extension                                                 */
+#define RTR                     0x4000  /* Remote Frame Transmission Request                    */
+#define AME                     0x8000  /* Acceptance Mask Enable                                               */
+
+/* CAN_MBxx_TIMESTAMP Masks                                     */
+#define TSV                     0xFFFF  /* Timestamp    */
+
+/* CAN_MBxx_LENGTH Masks                                                */
+#define DLC                     0x000F  /* Data Length Code     */
+
+/* CAN_AMxxH and CAN_AMxxL Masks                                                                                                */
+#define DFM                     0xFFFF  /* Data Field Mask (If Enabled) (CAN_AMxxL)                     */
+#define EXTID_LO        0xFFFF  /* Lower 16 Bits of Extended Identifier (CAN_AMxxL)     */
+#define EXTID_HI        0x0003  /* Upper 2 Bits of Extended Identifier (CAN_AMxxH)      */
+#define BASEID          0x1FFC  /* Base Identifier                                                                      */
+#define AMIDE           0x2000  /* Acceptance Mask ID Extension Enable                          */
+#define FMD                     0x4000  /* Full Mask Data Field Enable                                          */
+#define FDF                     0x8000  /* Filter On Data Field Enable                                          */
+
+/* CAN_MC1 Masks                                                                        */
+#define MC0                     0x0001  /* Enable Mailbox 0             */
+#define MC1                     0x0002  /* Enable Mailbox 1             */
+#define MC2                     0x0004  /* Enable Mailbox 2             */
+#define MC3                     0x0008  /* Enable Mailbox 3             */
+#define MC4                     0x0010  /* Enable Mailbox 4             */
+#define MC5                     0x0020  /* Enable Mailbox 5             */
+#define MC6                     0x0040  /* Enable Mailbox 6             */
+#define MC7                     0x0080  /* Enable Mailbox 7             */
+#define MC8                     0x0100  /* Enable Mailbox 8             */
+#define MC9                     0x0200  /* Enable Mailbox 9             */
+#define MC10            0x0400  /* Enable Mailbox 10    */
+#define MC11            0x0800  /* Enable Mailbox 11    */
+#define MC12            0x1000  /* Enable Mailbox 12    */
+#define MC13            0x2000  /* Enable Mailbox 13    */
+#define MC14            0x4000  /* Enable Mailbox 14    */
+#define MC15            0x8000  /* Enable Mailbox 15    */
+
+/* CAN_MC2 Masks                                                                        */
+#define MC16            0x0001  /* Enable Mailbox 16    */
+#define MC17            0x0002  /* Enable Mailbox 17    */
+#define MC18            0x0004  /* Enable Mailbox 18    */
+#define MC19            0x0008  /* Enable Mailbox 19    */
+#define MC20            0x0010  /* Enable Mailbox 20    */
+#define MC21            0x0020  /* Enable Mailbox 21    */
+#define MC22            0x0040  /* Enable Mailbox 22    */
+#define MC23            0x0080  /* Enable Mailbox 23    */
+#define MC24            0x0100  /* Enable Mailbox 24    */
+#define MC25            0x0200  /* Enable Mailbox 25    */
+#define MC26            0x0400  /* Enable Mailbox 26    */
+#define MC27            0x0800  /* Enable Mailbox 27    */
+#define MC28            0x1000  /* Enable Mailbox 28    */
+#define MC29            0x2000  /* Enable Mailbox 29    */
+#define MC30            0x4000  /* Enable Mailbox 30    */
+#define MC31            0x8000  /* Enable Mailbox 31    */
+
+/* CAN_MD1 Masks                                                                                                */
+#define MD0                     0x0001  /* Enable Mailbox 0 For Receive         */
+#define MD1                     0x0002  /* Enable Mailbox 1 For Receive         */
+#define MD2                     0x0004  /* Enable Mailbox 2 For Receive         */
+#define MD3                     0x0008  /* Enable Mailbox 3 For Receive         */
+#define MD4                     0x0010  /* Enable Mailbox 4 For Receive         */
+#define MD5                     0x0020  /* Enable Mailbox 5 For Receive         */
+#define MD6                     0x0040  /* Enable Mailbox 6 For Receive         */
+#define MD7                     0x0080  /* Enable Mailbox 7 For Receive         */
+#define MD8                     0x0100  /* Enable Mailbox 8 For Receive         */
+#define MD9                     0x0200  /* Enable Mailbox 9 For Receive         */
+#define MD10            0x0400  /* Enable Mailbox 10 For Receive        */
+#define MD11            0x0800  /* Enable Mailbox 11 For Receive        */
+#define MD12            0x1000  /* Enable Mailbox 12 For Receive        */
+#define MD13            0x2000  /* Enable Mailbox 13 For Receive        */
+#define MD14            0x4000  /* Enable Mailbox 14 For Receive        */
+#define MD15            0x8000  /* Enable Mailbox 15 For Receive        */
+
+/* CAN_MD2 Masks                                                                                                */
+#define MD16            0x0001  /* Enable Mailbox 16 For Receive        */
+#define MD17            0x0002  /* Enable Mailbox 17 For Receive        */
+#define MD18            0x0004  /* Enable Mailbox 18 For Receive        */
+#define MD19            0x0008  /* Enable Mailbox 19 For Receive        */
+#define MD20            0x0010  /* Enable Mailbox 20 For Receive        */
+#define MD21            0x0020  /* Enable Mailbox 21 For Receive        */
+#define MD22            0x0040  /* Enable Mailbox 22 For Receive        */
+#define MD23            0x0080  /* Enable Mailbox 23 For Receive        */
+#define MD24            0x0100  /* Enable Mailbox 24 For Receive        */
+#define MD25            0x0200  /* Enable Mailbox 25 For Receive        */
+#define MD26            0x0400  /* Enable Mailbox 26 For Receive        */
+#define MD27            0x0800  /* Enable Mailbox 27 For Receive        */
+#define MD28            0x1000  /* Enable Mailbox 28 For Receive        */
+#define MD29            0x2000  /* Enable Mailbox 29 For Receive        */
+#define MD30            0x4000  /* Enable Mailbox 30 For Receive        */
+#define MD31            0x8000  /* Enable Mailbox 31 For Receive        */
+
+/* CAN_RMP1 Masks                                                                                               */
+#define RMP0            0x0001  /* RX Message Pending In Mailbox 0      */
+#define RMP1            0x0002  /* RX Message Pending In Mailbox 1      */
+#define RMP2            0x0004  /* RX Message Pending In Mailbox 2      */
+#define RMP3            0x0008  /* RX Message Pending In Mailbox 3      */
+#define RMP4            0x0010  /* RX Message Pending In Mailbox 4      */
+#define RMP5            0x0020  /* RX Message Pending In Mailbox 5      */
+#define RMP6            0x0040  /* RX Message Pending In Mailbox 6      */
+#define RMP7            0x0080  /* RX Message Pending In Mailbox 7      */
+#define RMP8            0x0100  /* RX Message Pending In Mailbox 8      */
+#define RMP9            0x0200  /* RX Message Pending In Mailbox 9      */
+#define RMP10           0x0400  /* RX Message Pending In Mailbox 10     */
+#define RMP11           0x0800  /* RX Message Pending In Mailbox 11     */
+#define RMP12           0x1000  /* RX Message Pending In Mailbox 12     */
+#define RMP13           0x2000  /* RX Message Pending In Mailbox 13     */
+#define RMP14           0x4000  /* RX Message Pending In Mailbox 14     */
+#define RMP15           0x8000  /* RX Message Pending In Mailbox 15     */
+
+/* CAN_RMP2 Masks                                                                                               */
+#define RMP16           0x0001  /* RX Message Pending In Mailbox 16     */
+#define RMP17           0x0002  /* RX Message Pending In Mailbox 17     */
+#define RMP18           0x0004  /* RX Message Pending In Mailbox 18     */
+#define RMP19           0x0008  /* RX Message Pending In Mailbox 19     */
+#define RMP20           0x0010  /* RX Message Pending In Mailbox 20     */
+#define RMP21           0x0020  /* RX Message Pending In Mailbox 21     */
+#define RMP22           0x0040  /* RX Message Pending In Mailbox 22     */
+#define RMP23           0x0080  /* RX Message Pending In Mailbox 23     */
+#define RMP24           0x0100  /* RX Message Pending In Mailbox 24     */
+#define RMP25           0x0200  /* RX Message Pending In Mailbox 25     */
+#define RMP26           0x0400  /* RX Message Pending In Mailbox 26     */
+#define RMP27           0x0800  /* RX Message Pending In Mailbox 27     */
+#define RMP28           0x1000  /* RX Message Pending In Mailbox 28     */
+#define RMP29           0x2000  /* RX Message Pending In Mailbox 29     */
+#define RMP30           0x4000  /* RX Message Pending In Mailbox 30     */
+#define RMP31           0x8000  /* RX Message Pending In Mailbox 31     */
+
+/* CAN_RML1 Masks                                                                                               */
+#define RML0            0x0001  /* RX Message Lost In Mailbox 0         */
+#define RML1            0x0002  /* RX Message Lost In Mailbox 1         */
+#define RML2            0x0004  /* RX Message Lost In Mailbox 2         */
+#define RML3            0x0008  /* RX Message Lost In Mailbox 3         */
+#define RML4            0x0010  /* RX Message Lost In Mailbox 4         */
+#define RML5            0x0020  /* RX Message Lost In Mailbox 5         */
+#define RML6            0x0040  /* RX Message Lost In Mailbox 6         */
+#define RML7            0x0080  /* RX Message Lost In Mailbox 7         */
+#define RML8            0x0100  /* RX Message Lost In Mailbox 8         */
+#define RML9            0x0200  /* RX Message Lost In Mailbox 9         */
+#define RML10           0x0400  /* RX Message Lost In Mailbox 10        */
+#define RML11           0x0800  /* RX Message Lost In Mailbox 11        */
+#define RML12           0x1000  /* RX Message Lost In Mailbox 12        */
+#define RML13           0x2000  /* RX Message Lost In Mailbox 13        */
+#define RML14           0x4000  /* RX Message Lost In Mailbox 14        */
+#define RML15           0x8000  /* RX Message Lost In Mailbox 15        */
+
+/* CAN_RML2 Masks                                                                                               */
+#define RML16           0x0001  /* RX Message Lost In Mailbox 16        */
+#define RML17           0x0002  /* RX Message Lost In Mailbox 17        */
+#define RML18           0x0004  /* RX Message Lost In Mailbox 18        */
+#define RML19           0x0008  /* RX Message Lost In Mailbox 19        */
+#define RML20           0x0010  /* RX Message Lost In Mailbox 20        */
+#define RML21           0x0020  /* RX Message Lost In Mailbox 21        */
+#define RML22           0x0040  /* RX Message Lost In Mailbox 22        */
+#define RML23           0x0080  /* RX Message Lost In Mailbox 23        */
+#define RML24           0x0100  /* RX Message Lost In Mailbox 24        */
+#define RML25           0x0200  /* RX Message Lost In Mailbox 25        */
+#define RML26           0x0400  /* RX Message Lost In Mailbox 26        */
+#define RML27           0x0800  /* RX Message Lost In Mailbox 27        */
+#define RML28           0x1000  /* RX Message Lost In Mailbox 28        */
+#define RML29           0x2000  /* RX Message Lost In Mailbox 29        */
+#define RML30           0x4000  /* RX Message Lost In Mailbox 30        */
+#define RML31           0x8000  /* RX Message Lost In Mailbox 31        */
+
+/* CAN_OPSS1 Masks                                                                                                                                                              */
+#define OPSS0           0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 0       */
+#define OPSS1           0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 1       */
+#define OPSS2           0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 2       */
+#define OPSS3           0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 3       */
+#define OPSS4           0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 4       */
+#define OPSS5           0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 5       */
+#define OPSS6           0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 6       */
+#define OPSS7           0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 7       */
+#define OPSS8           0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 8       */
+#define OPSS9           0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 9       */
+#define OPSS10          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 10      */
+#define OPSS11          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 11      */
+#define OPSS12          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 12      */
+#define OPSS13          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 13      */
+#define OPSS14          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 14      */
+#define OPSS15          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 15      */
+
+/* CAN_OPSS2 Masks                                                                                                                                                              */
+#define OPSS16          0x0001  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 16      */
+#define OPSS17          0x0002  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 17      */
+#define OPSS18          0x0004  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 18      */
+#define OPSS19          0x0008  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 19      */
+#define OPSS20          0x0010  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 20      */
+#define OPSS21          0x0020  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 21      */
+#define OPSS22          0x0040  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 22      */
+#define OPSS23          0x0080  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 23      */
+#define OPSS24          0x0100  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 24      */
+#define OPSS25          0x0200  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 25      */
+#define OPSS26          0x0400  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 26      */
+#define OPSS27          0x0800  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 27      */
+#define OPSS28          0x1000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 28      */
+#define OPSS29          0x2000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 29      */
+#define OPSS30          0x4000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 30      */
+#define OPSS31          0x8000  /* Enable RX Overwrite Protection or TX Single-Shot For Mailbox 31      */
+
+/* CAN_TRR1 Masks                                                                                                               */
+#define TRR0            0x0001  /* Deny But Don't Lock Access To Mailbox 0      */
+#define TRR1            0x0002  /* Deny But Don't Lock Access To Mailbox 1      */
+#define TRR2            0x0004  /* Deny But Don't Lock Access To Mailbox 2      */
+#define TRR3            0x0008  /* Deny But Don't Lock Access To Mailbox 3      */
+#define TRR4            0x0010  /* Deny But Don't Lock Access To Mailbox 4      */
+#define TRR5            0x0020  /* Deny But Don't Lock Access To Mailbox 5      */
+#define TRR6            0x0040  /* Deny But Don't Lock Access To Mailbox 6      */
+#define TRR7            0x0080  /* Deny But Don't Lock Access To Mailbox 7      */
+#define TRR8            0x0100  /* Deny But Don't Lock Access To Mailbox 8      */
+#define TRR9            0x0200  /* Deny But Don't Lock Access To Mailbox 9      */
+#define TRR10           0x0400  /* Deny But Don't Lock Access To Mailbox 10     */
+#define TRR11           0x0800  /* Deny But Don't Lock Access To Mailbox 11     */
+#define TRR12           0x1000  /* Deny But Don't Lock Access To Mailbox 12     */
+#define TRR13           0x2000  /* Deny But Don't Lock Access To Mailbox 13     */
+#define TRR14           0x4000  /* Deny But Don't Lock Access To Mailbox 14     */
+#define TRR15           0x8000  /* Deny But Don't Lock Access To Mailbox 15     */
+
+/* CAN_TRR2 Masks                                                                                                               */
+#define TRR16           0x0001  /* Deny But Don't Lock Access To Mailbox 16     */
+#define TRR17           0x0002  /* Deny But Don't Lock Access To Mailbox 17     */
+#define TRR18           0x0004  /* Deny But Don't Lock Access To Mailbox 18     */
+#define TRR19           0x0008  /* Deny But Don't Lock Access To Mailbox 19     */
+#define TRR20           0x0010  /* Deny But Don't Lock Access To Mailbox 20     */
+#define TRR21           0x0020  /* Deny But Don't Lock Access To Mailbox 21     */
+#define TRR22           0x0040  /* Deny But Don't Lock Access To Mailbox 22     */
+#define TRR23           0x0080  /* Deny But Don't Lock Access To Mailbox 23     */
+#define TRR24           0x0100  /* Deny But Don't Lock Access To Mailbox 24     */
+#define TRR25           0x0200  /* Deny But Don't Lock Access To Mailbox 25     */
+#define TRR26           0x0400  /* Deny But Don't Lock Access To Mailbox 26     */
+#define TRR27           0x0800  /* Deny But Don't Lock Access To Mailbox 27     */
+#define TRR28           0x1000  /* Deny But Don't Lock Access To Mailbox 28     */
+#define TRR29           0x2000  /* Deny But Don't Lock Access To Mailbox 29     */
+#define TRR30           0x4000  /* Deny But Don't Lock Access To Mailbox 30     */
+#define TRR31           0x8000  /* Deny But Don't Lock Access To Mailbox 31     */
+
+/* CAN_TRS1 Masks                                                                                                       */
+#define TRS0            0x0001  /* Remote Frame Request For Mailbox 0   */
+#define TRS1            0x0002  /* Remote Frame Request For Mailbox 1   */
+#define TRS2            0x0004  /* Remote Frame Request For Mailbox 2   */
+#define TRS3            0x0008  /* Remote Frame Request For Mailbox 3   */
+#define TRS4            0x0010  /* Remote Frame Request For Mailbox 4   */
+#define TRS5            0x0020  /* Remote Frame Request For Mailbox 5   */
+#define TRS6            0x0040  /* Remote Frame Request For Mailbox 6   */
+#define TRS7            0x0080  /* Remote Frame Request For Mailbox 7   */
+#define TRS8            0x0100  /* Remote Frame Request For Mailbox 8   */
+#define TRS9            0x0200  /* Remote Frame Request For Mailbox 9   */
+#define TRS10           0x0400  /* Remote Frame Request For Mailbox 10  */
+#define TRS11           0x0800  /* Remote Frame Request For Mailbox 11  */
+#define TRS12           0x1000  /* Remote Frame Request For Mailbox 12  */
+#define TRS13           0x2000  /* Remote Frame Request For Mailbox 13  */
+#define TRS14           0x4000  /* Remote Frame Request For Mailbox 14  */
+#define TRS15           0x8000  /* Remote Frame Request For Mailbox 15  */
+
+/* CAN_TRS2 Masks                                                                                                       */
+#define TRS16           0x0001  /* Remote Frame Request For Mailbox 16  */
+#define TRS17           0x0002  /* Remote Frame Request For Mailbox 17  */
+#define TRS18           0x0004  /* Remote Frame Request For Mailbox 18  */
+#define TRS19           0x0008  /* Remote Frame Request For Mailbox 19  */
+#define TRS20           0x0010  /* Remote Frame Request For Mailbox 20  */
+#define TRS21           0x0020  /* Remote Frame Request For Mailbox 21  */
+#define TRS22           0x0040  /* Remote Frame Request For Mailbox 22  */
+#define TRS23           0x0080  /* Remote Frame Request For Mailbox 23  */
+#define TRS24           0x0100  /* Remote Frame Request For Mailbox 24  */
+#define TRS25           0x0200  /* Remote Frame Request For Mailbox 25  */
+#define TRS26           0x0400  /* Remote Frame Request For Mailbox 26  */
+#define TRS27           0x0800  /* Remote Frame Request For Mailbox 27  */
+#define TRS28           0x1000  /* Remote Frame Request For Mailbox 28  */
+#define TRS29           0x2000  /* Remote Frame Request For Mailbox 29  */
+#define TRS30           0x4000  /* Remote Frame Request For Mailbox 30  */
+#define TRS31           0x8000  /* Remote Frame Request For Mailbox 31  */
+
+/* CAN_AA1 Masks                                                                                                */
+#define AA0                     0x0001  /* Aborted Message In Mailbox 0         */
+#define AA1                     0x0002  /* Aborted Message In Mailbox 1         */
+#define AA2                     0x0004  /* Aborted Message In Mailbox 2         */
+#define AA3                     0x0008  /* Aborted Message In Mailbox 3         */
+#define AA4                     0x0010  /* Aborted Message In Mailbox 4         */
+#define AA5                     0x0020  /* Aborted Message In Mailbox 5         */
+#define AA6                     0x0040  /* Aborted Message In Mailbox 6         */
+#define AA7                     0x0080  /* Aborted Message In Mailbox 7         */
+#define AA8                     0x0100  /* Aborted Message In Mailbox 8         */
+#define AA9                     0x0200  /* Aborted Message In Mailbox 9         */
+#define AA10            0x0400  /* Aborted Message In Mailbox 10        */
+#define AA11            0x0800  /* Aborted Message In Mailbox 11        */
+#define AA12            0x1000  /* Aborted Message In Mailbox 12        */
+#define AA13            0x2000  /* Aborted Message In Mailbox 13        */
+#define AA14            0x4000  /* Aborted Message In Mailbox 14        */
+#define AA15            0x8000  /* Aborted Message In Mailbox 15        */
+
+/* CAN_AA2 Masks                                                                                                */
+#define AA16            0x0001  /* Aborted Message In Mailbox 16        */
+#define AA17            0x0002  /* Aborted Message In Mailbox 17        */
+#define AA18            0x0004  /* Aborted Message In Mailbox 18        */
+#define AA19            0x0008  /* Aborted Message In Mailbox 19        */
+#define AA20            0x0010  /* Aborted Message In Mailbox 20        */
+#define AA21            0x0020  /* Aborted Message In Mailbox 21        */
+#define AA22            0x0040  /* Aborted Message In Mailbox 22        */
+#define AA23            0x0080  /* Aborted Message In Mailbox 23        */
+#define AA24            0x0100  /* Aborted Message In Mailbox 24        */
+#define AA25            0x0200  /* Aborted Message In Mailbox 25        */
+#define AA26            0x0400  /* Aborted Message In Mailbox 26        */
+#define AA27            0x0800  /* Aborted Message In Mailbox 27        */
+#define AA28            0x1000  /* Aborted Message In Mailbox 28        */
+#define AA29            0x2000  /* Aborted Message In Mailbox 29        */
+#define AA30            0x4000  /* Aborted Message In Mailbox 30        */
+#define AA31            0x8000  /* Aborted Message In Mailbox 31        */
+
+/* CAN_TA1 Masks                                                                                                        */
+#define TA0                     0x0001  /* Transmit Successful From Mailbox 0   */
+#define TA1                     0x0002  /* Transmit Successful From Mailbox 1   */
+#define TA2                     0x0004  /* Transmit Successful From Mailbox 2   */
+#define TA3                     0x0008  /* Transmit Successful From Mailbox 3   */
+#define TA4                     0x0010  /* Transmit Successful From Mailbox 4   */
+#define TA5                     0x0020  /* Transmit Successful From Mailbox 5   */
+#define TA6                     0x0040  /* Transmit Successful From Mailbox 6   */
+#define TA7                     0x0080  /* Transmit Successful From Mailbox 7   */
+#define TA8                     0x0100  /* Transmit Successful From Mailbox 8   */
+#define TA9                     0x0200  /* Transmit Successful From Mailbox 9   */
+#define TA10            0x0400  /* Transmit Successful From Mailbox 10  */
+#define TA11            0x0800  /* Transmit Successful From Mailbox 11  */
+#define TA12            0x1000  /* Transmit Successful From Mailbox 12  */
+#define TA13            0x2000  /* Transmit Successful From Mailbox 13  */
+#define TA14            0x4000  /* Transmit Successful From Mailbox 14  */
+#define TA15            0x8000  /* Transmit Successful From Mailbox 15  */
+
+/* CAN_TA2 Masks                                                                                                        */
+#define TA16            0x0001  /* Transmit Successful From Mailbox 16  */
+#define TA17            0x0002  /* Transmit Successful From Mailbox 17  */
+#define TA18            0x0004  /* Transmit Successful From Mailbox 18  */
+#define TA19            0x0008  /* Transmit Successful From Mailbox 19  */
+#define TA20            0x0010  /* Transmit Successful From Mailbox 20  */
+#define TA21            0x0020  /* Transmit Successful From Mailbox 21  */
+#define TA22            0x0040  /* Transmit Successful From Mailbox 22  */
+#define TA23            0x0080  /* Transmit Successful From Mailbox 23  */
+#define TA24            0x0100  /* Transmit Successful From Mailbox 24  */
+#define TA25            0x0200  /* Transmit Successful From Mailbox 25  */
+#define TA26            0x0400  /* Transmit Successful From Mailbox 26  */
+#define TA27            0x0800  /* Transmit Successful From Mailbox 27  */
+#define TA28            0x1000  /* Transmit Successful From Mailbox 28  */
+#define TA29            0x2000  /* Transmit Successful From Mailbox 29  */
+#define TA30            0x4000  /* Transmit Successful From Mailbox 30  */
+#define TA31            0x8000  /* Transmit Successful From Mailbox 31  */
+
+/* CAN_MBTD Masks                                                                                               */
+#define TDPTR           0x001F  /* Mailbox To Temporarily Disable       */
+#define TDA                     0x0040  /* Temporary Disable Acknowledge        */
+#define TDR                     0x0080  /* Temporary Disable Request            */
+
+/* CAN_RFH1 Masks                                                                                                                                               */
+#define RFH0            0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 0         */
+#define RFH1            0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 1         */
+#define RFH2            0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 2         */
+#define RFH3            0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 3         */
+#define RFH4            0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 4         */
+#define RFH5            0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 5         */
+#define RFH6            0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 6         */
+#define RFH7            0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 7         */
+#define RFH8            0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 8         */
+#define RFH9            0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 9         */
+#define RFH10           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 10        */
+#define RFH11           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 11        */
+#define RFH12           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 12        */
+#define RFH13           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 13        */
+#define RFH14           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 14        */
+#define RFH15           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 15        */
+
+/* CAN_RFH2 Masks                                                                                                                                               */
+#define RFH16           0x0001  /* Enable Automatic Remote Frame Handling For Mailbox 16        */
+#define RFH17           0x0002  /* Enable Automatic Remote Frame Handling For Mailbox 17        */
+#define RFH18           0x0004  /* Enable Automatic Remote Frame Handling For Mailbox 18        */
+#define RFH19           0x0008  /* Enable Automatic Remote Frame Handling For Mailbox 19        */
+#define RFH20           0x0010  /* Enable Automatic Remote Frame Handling For Mailbox 20        */
+#define RFH21           0x0020  /* Enable Automatic Remote Frame Handling For Mailbox 21        */
+#define RFH22           0x0040  /* Enable Automatic Remote Frame Handling For Mailbox 22        */
+#define RFH23           0x0080  /* Enable Automatic Remote Frame Handling For Mailbox 23        */
+#define RFH24           0x0100  /* Enable Automatic Remote Frame Handling For Mailbox 24        */
+#define RFH25           0x0200  /* Enable Automatic Remote Frame Handling For Mailbox 25        */
+#define RFH26           0x0400  /* Enable Automatic Remote Frame Handling For Mailbox 26        */
+#define RFH27           0x0800  /* Enable Automatic Remote Frame Handling For Mailbox 27        */
+#define RFH28           0x1000  /* Enable Automatic Remote Frame Handling For Mailbox 28        */
+#define RFH29           0x2000  /* Enable Automatic Remote Frame Handling For Mailbox 29        */
+#define RFH30           0x4000  /* Enable Automatic Remote Frame Handling For Mailbox 30        */
+#define RFH31           0x8000  /* Enable Automatic Remote Frame Handling For Mailbox 31        */
+
+/* CAN_MBTIF1 Masks                                                                                                     */
+#define MBTIF0          0x0001  /* TX Interrupt Active In Mailbox 0             */
+#define MBTIF1          0x0002  /* TX Interrupt Active In Mailbox 1             */
+#define MBTIF2          0x0004  /* TX Interrupt Active In Mailbox 2             */
+#define MBTIF3          0x0008  /* TX Interrupt Active In Mailbox 3             */
+#define MBTIF4          0x0010  /* TX Interrupt Active In Mailbox 4             */
+#define MBTIF5          0x0020  /* TX Interrupt Active In Mailbox 5             */
+#define MBTIF6          0x0040  /* TX Interrupt Active In Mailbox 6             */
+#define MBTIF7          0x0080  /* TX Interrupt Active In Mailbox 7             */
+#define MBTIF8          0x0100  /* TX Interrupt Active In Mailbox 8             */
+#define MBTIF9          0x0200  /* TX Interrupt Active In Mailbox 9             */
+#define MBTIF10         0x0400  /* TX Interrupt Active In Mailbox 10    */
+#define MBTIF11         0x0800  /* TX Interrupt Active In Mailbox 11    */
+#define MBTIF12         0x1000  /* TX Interrupt Active In Mailbox 12    */
+#define MBTIF13         0x2000  /* TX Interrupt Active In Mailbox 13    */
+#define MBTIF14         0x4000  /* TX Interrupt Active In Mailbox 14    */
+#define MBTIF15         0x8000  /* TX Interrupt Active In Mailbox 15    */
+
+/* CAN_MBTIF2 Masks                                                                                                     */
+#define MBTIF16         0x0001  /* TX Interrupt Active In Mailbox 16    */
+#define MBTIF17         0x0002  /* TX Interrupt Active In Mailbox 17    */
+#define MBTIF18         0x0004  /* TX Interrupt Active In Mailbox 18    */
+#define MBTIF19         0x0008  /* TX Interrupt Active In Mailbox 19    */
+#define MBTIF20         0x0010  /* TX Interrupt Active In Mailbox 20    */
+#define MBTIF21         0x0020  /* TX Interrupt Active In Mailbox 21    */
+#define MBTIF22         0x0040  /* TX Interrupt Active In Mailbox 22    */
+#define MBTIF23         0x0080  /* TX Interrupt Active In Mailbox 23    */
+#define MBTIF24         0x0100  /* TX Interrupt Active In Mailbox 24    */
+#define MBTIF25         0x0200  /* TX Interrupt Active In Mailbox 25    */
+#define MBTIF26         0x0400  /* TX Interrupt Active In Mailbox 26    */
+#define MBTIF27         0x0800  /* TX Interrupt Active In Mailbox 27    */
+#define MBTIF28         0x1000  /* TX Interrupt Active In Mailbox 28    */
+#define MBTIF29         0x2000  /* TX Interrupt Active In Mailbox 29    */
+#define MBTIF30         0x4000  /* TX Interrupt Active In Mailbox 30    */
+#define MBTIF31         0x8000  /* TX Interrupt Active In Mailbox 31    */
+
+/* CAN_MBRIF1 Masks                                                                                                     */
+#define MBRIF0          0x0001  /* RX Interrupt Active In Mailbox 0             */
+#define MBRIF1          0x0002  /* RX Interrupt Active In Mailbox 1             */
+#define MBRIF2          0x0004  /* RX Interrupt Active In Mailbox 2             */
+#define MBRIF3          0x0008  /* RX Interrupt Active In Mailbox 3             */
+#define MBRIF4          0x0010  /* RX Interrupt Active In Mailbox 4             */
+#define MBRIF5          0x0020  /* RX Interrupt Active In Mailbox 5             */
+#define MBRIF6          0x0040  /* RX Interrupt Active In Mailbox 6             */
+#define MBRIF7          0x0080  /* RX Interrupt Active In Mailbox 7             */
+#define MBRIF8          0x0100  /* RX Interrupt Active In Mailbox 8             */
+#define MBRIF9          0x0200  /* RX Interrupt Active In Mailbox 9             */
+#define MBRIF10         0x0400  /* RX Interrupt Active In Mailbox 10    */
+#define MBRIF11         0x0800  /* RX Interrupt Active In Mailbox 11    */
+#define MBRIF12         0x1000  /* RX Interrupt Active In Mailbox 12    */
+#define MBRIF13         0x2000  /* RX Interrupt Active In Mailbox 13    */
+#define MBRIF14         0x4000  /* RX Interrupt Active In Mailbox 14    */
+#define MBRIF15         0x8000  /* RX Interrupt Active In Mailbox 15    */
+
+/* CAN_MBRIF2 Masks                                                                                                     */
+#define MBRIF16         0x0001  /* RX Interrupt Active In Mailbox 16    */
+#define MBRIF17         0x0002  /* RX Interrupt Active In Mailbox 17    */
+#define MBRIF18         0x0004  /* RX Interrupt Active In Mailbox 18    */
+#define MBRIF19         0x0008  /* RX Interrupt Active In Mailbox 19    */
+#define MBRIF20         0x0010  /* RX Interrupt Active In Mailbox 20    */
+#define MBRIF21         0x0020  /* RX Interrupt Active In Mailbox 21    */
+#define MBRIF22         0x0040  /* RX Interrupt Active In Mailbox 22    */
+#define MBRIF23         0x0080  /* RX Interrupt Active In Mailbox 23    */
+#define MBRIF24         0x0100  /* RX Interrupt Active In Mailbox 24    */
+#define MBRIF25         0x0200  /* RX Interrupt Active In Mailbox 25    */
+#define MBRIF26         0x0400  /* RX Interrupt Active In Mailbox 26    */
+#define MBRIF27         0x0800  /* RX Interrupt Active In Mailbox 27    */
+#define MBRIF28         0x1000  /* RX Interrupt Active In Mailbox 28    */
+#define MBRIF29         0x2000  /* RX Interrupt Active In Mailbox 29    */
+#define MBRIF30         0x4000  /* RX Interrupt Active In Mailbox 30    */
+#define MBRIF31         0x8000  /* RX Interrupt Active In Mailbox 31    */
+
+/* CAN_MBIM1 Masks                                                                                              */
+#define MBIM0           0x0001  /* Enable Interrupt For Mailbox 0       */
+#define MBIM1           0x0002  /* Enable Interrupt For Mailbox 1       */
+#define MBIM2           0x0004  /* Enable Interrupt For Mailbox 2       */
+#define MBIM3           0x0008  /* Enable Interrupt For Mailbox 3       */
+#define MBIM4           0x0010  /* Enable Interrupt For Mailbox 4       */
+#define MBIM5           0x0020  /* Enable Interrupt For Mailbox 5       */
+#define MBIM6           0x0040  /* Enable Interrupt For Mailbox 6       */
+#define MBIM7           0x0080  /* Enable Interrupt For Mailbox 7       */
+#define MBIM8           0x0100  /* Enable Interrupt For Mailbox 8       */
+#define MBIM9           0x0200  /* Enable Interrupt For Mailbox 9       */
+#define MBIM10          0x0400  /* Enable Interrupt For Mailbox 10      */
+#define MBIM11          0x0800  /* Enable Interrupt For Mailbox 11      */
+#define MBIM12          0x1000  /* Enable Interrupt For Mailbox 12      */
+#define MBIM13          0x2000  /* Enable Interrupt For Mailbox 13      */
+#define MBIM14          0x4000  /* Enable Interrupt For Mailbox 14      */
+#define MBIM15          0x8000  /* Enable Interrupt For Mailbox 15      */
+
+/* CAN_MBIM2 Masks                                                                                              */
+#define MBIM16          0x0001  /* Enable Interrupt For Mailbox 16      */
+#define MBIM17          0x0002  /* Enable Interrupt For Mailbox 17      */
+#define MBIM18          0x0004  /* Enable Interrupt For Mailbox 18      */
+#define MBIM19          0x0008  /* Enable Interrupt For Mailbox 19      */
+#define MBIM20          0x0010  /* Enable Interrupt For Mailbox 20      */
+#define MBIM21          0x0020  /* Enable Interrupt For Mailbox 21      */
+#define MBIM22          0x0040  /* Enable Interrupt For Mailbox 22      */
+#define MBIM23          0x0080  /* Enable Interrupt For Mailbox 23      */
+#define MBIM24          0x0100  /* Enable Interrupt For Mailbox 24      */
+#define MBIM25          0x0200  /* Enable Interrupt For Mailbox 25      */
+#define MBIM26          0x0400  /* Enable Interrupt For Mailbox 26      */
+#define MBIM27          0x0800  /* Enable Interrupt For Mailbox 27      */
+#define MBIM28          0x1000  /* Enable Interrupt For Mailbox 28      */
+#define MBIM29          0x2000  /* Enable Interrupt For Mailbox 29      */
+#define MBIM30          0x4000  /* Enable Interrupt For Mailbox 30      */
+#define MBIM31          0x8000  /* Enable Interrupt For Mailbox 31      */
+
+/* CAN_GIM Masks                                                                                                                                */
+#define EWTIM           0x0001  /* Enable TX Error Count Interrupt                                      */
+#define EWRIM           0x0002  /* Enable RX Error Count Interrupt                                      */
+#define EPIM            0x0004  /* Enable Error-Passive Mode Interrupt                          */
+#define BOIM            0x0008  /* Enable Bus Off Interrupt                                                     */
+#define WUIM            0x0010  /* Enable Wake-Up Interrupt                                                     */
+#define UIAIM           0x0020  /* Enable Access To Unimplemented Address Interrupt     */
+#define AAIM            0x0040  /* Enable Abort Acknowledge Interrupt                           */
+#define RMLIM           0x0080  /* Enable RX Message Lost Interrupt                                     */
+#define UCEIM           0x0100  /* Enable Universal Counter Overflow Interrupt          */
+#define EXTIM           0x0200  /* Enable External Trigger Output Interrupt                     */
+#define ADIM            0x0400  /* Enable Access Denied Interrupt                                       */
+
+/* CAN_GIS Masks                                                                                                                        */
+#define EWTIS           0x0001  /* TX Error Count IRQ Status                                    */
+#define EWRIS           0x0002  /* RX Error Count IRQ Status                                    */
+#define EPIS            0x0004  /* Error-Passive Mode IRQ Status                                */
+#define BOIS            0x0008  /* Bus Off IRQ Status                                                   */
+#define WUIS            0x0010  /* Wake-Up IRQ Status                                                   */
+#define UIAIS           0x0020  /* Access To Unimplemented Address IRQ Status   */
+#define AAIS            0x0040  /* Abort Acknowledge IRQ Status                                 */
+#define RMLIS           0x0080  /* RX Message Lost IRQ Status                                   */
+#define UCEIS           0x0100  /* Universal Counter Overflow IRQ Status                */
+#define EXTIS           0x0200  /* External Trigger Output IRQ Status                   */
+#define ADIS            0x0400  /* Access Denied IRQ Status                                             */
+
+/* CAN_GIF Masks                                                                                                                        */
+#define EWTIF           0x0001  /* TX Error Count IRQ Flag                                              */
+#define EWRIF           0x0002  /* RX Error Count IRQ Flag                                              */
+#define EPIF            0x0004  /* Error-Passive Mode IRQ Flag                                  */
+#define BOIF            0x0008  /* Bus Off IRQ Flag                                                             */
+#define WUIF            0x0010  /* Wake-Up IRQ Flag                                                             */
+#define UIAIF           0x0020  /* Access To Unimplemented Address IRQ Flag             */
+#define AAIF            0x0040  /* Abort Acknowledge IRQ Flag                                   */
+#define RMLIF           0x0080  /* RX Message Lost IRQ Flag                                             */
+#define UCEIF           0x0100  /* Universal Counter Overflow IRQ Flag                  */
+#define EXTIF           0x0200  /* External Trigger Output IRQ Flag                             */
+#define ADIF            0x0400  /* Access Denied IRQ Flag                                               */
+
+/* CAN_UCCNF Masks                                                                                                                      */
+#define UCCNF           0x000F  /* Universal Counter Mode                                               */
+#define UC_STAMP        0x0001  /*              Timestamp Mode                                                  */
+#define UC_WDOG         0x0002  /*              Watchdog Mode                                                   */
+#define UC_AUTOTX       0x0003  /*              Auto-Transmit Mode                                              */
+#define UC_ERROR        0x0006  /*              CAN Error Frame Count                                   */
+#define UC_OVER         0x0007  /*              CAN Overload Frame Count                                */
+#define UC_LOST         0x0008  /*              Arbitration Lost During TX Count                */
+#define UC_AA           0x0009  /*              TX Abort Count                                                  */
+#define UC_TA           0x000A  /*              TX Successful Count                                             */
+#define UC_REJECT       0x000B  /*              RX Message Rejected Count                               */
+#define UC_RML          0x000C  /*              RX Message Lost Count                                   */
+#define UC_RX           0x000D  /*              Total Successful RX Messages Count              */
+#define UC_RMP          0x000E  /*              Successful RX W/Matching ID Count               */
+#define UC_ALL          0x000F  /*              Correct Message On CAN Bus Line Count   */
+#define UCRC            0x0020  /* Universal Counter Reload/Clear                               */
+#define UCCT            0x0040  /* Universal Counter CAN Trigger                                */
+#define UCE                     0x0080  /* Universal Counter Enable                                             */
+
+/* CAN_ESR Masks                                                                                */
+#define ACKE            0x0004  /* Acknowledge Error            */
+#define SER                     0x0008  /* Stuff Error                          */
+#define CRCE            0x0010  /* CRC Error                            */
+#define SA0                     0x0020  /* Stuck At Dominant Error      */
+#define BEF                     0x0040  /* Bit Error Flag                       */
+#define FER                     0x0080  /* Form Error Flag                      */
+
+/* CAN_EWR Masks                                                                                                */
+#define EWLREC          0x00FF  /* RX Error Count Limit (For EWRIS)     */
+#define EWLTEC          0xFF00  /* TX Error Count Limit (For EWTIS)     */
+
+/*  *******************  PIN CONTROL REGISTER MASKS  ************************/
+/* PORT_MUX Masks                                                                                                                       */
+#define PJSE                    0x0001  /* Port J SPI/SPORT Enable                      */
+#define PJSE_SPORT              0x0000  /*              Enable TFS0/DT0PRI                      */
+#define PJSE_SPI                0x0001  /*              Enable SPI_SSEL3:2                      */
+
+#define PJCE(x)                 (((x)&0x3)<<1)  /* Port J CAN/SPI/SPORT Enable          */
+#define PJCE_SPORT              0x0000  /*              Enable DR0SEC/DT0SEC            */
+#define PJCE_CAN                0x0002  /*              Enable CAN RX/TX                        */
+#define PJCE_SPI                0x0004  /*              Enable SPI_SSEL7                        */
+
+#define PFDE                    0x0008  /* Port F DMA Request Enable            */
+#define PGDE_UART               0x0000  /*              Enable UART0 RX/TX                      */
+#define PGDE_DMA                0x0008  /*              Enable DMAR1:0                          */
+
+#define PFTE                    0x0010  /* Port F Timer Enable                          */
+#define PFTE_UART               0x0000  /*              Enable UART1 RX/TX                      */
+#define PFTE_TIMER              0x0010  /*              Enable TMR7:6                           */
+
+#define PFS6E                   0x0020  /* Port F SPI SSEL 6 Enable                     */
+#define PFS6E_TIMER             0x0000  /*              Enable TMR5                                     */
+#define PFS6E_SPI               0x0020  /*              Enable SPI_SSEL6                        */
+
+#define PFS5E                   0x0040  /* Port F SPI SSEL 5 Enable                     */
+#define PFS5E_TIMER             0x0000  /*              Enable TMR4                                     */
+#define PFS5E_SPI               0x0040  /*              Enable SPI_SSEL5                        */
+
+#define PFS4E                   0x0080  /* Port F SPI SSEL 4 Enable                     */
+#define PFS4E_TIMER             0x0000  /*              Enable TMR3                                     */
+#define PFS4E_SPI               0x0080  /*              Enable SPI_SSEL4                        */
+
+#define PFFE                    0x0100  /* Port F PPI Frame Sync Enable         */
+#define PFFE_TIMER              0x0000  /*              Enable TMR2                                     */
+#define PFFE_PPI                0x0100  /*              Enable PPI FS3                          */
+
+#define PGSE                    0x0200  /* Port G SPORT1 Secondary Enable       */
+#define PGSE_PPI                0x0000  /*              Enable PPI D9:8                         */
+#define PGSE_SPORT              0x0200  /*              Enable DR1SEC/DT1SEC            */
+
+#define PGRE                    0x0400  /* Port G SPORT1 Receive Enable         */
+#define PGRE_PPI                0x0000  /*              Enable PPI D12:10                       */
+#define PGRE_SPORT              0x0400  /*              Enable DR1PRI/RFS1/RSCLK1       */
+
+#define PGTE                    0x0800  /* Port G SPORT1 Transmit Enable        */
+#define PGTE_PPI                0x0000  /*              Enable PPI D15:13                       */
+#define PGTE_SPORT              0x0800  /*              Enable DT1PRI/TFS1/TSCLK1       */
+
+/*  ******************  HANDSHAKE DMA (HDMA) MASKS  *********************/
+/* HDMAx_CTL Masks                                                                                                              */
+#define HMDMAEN         0x0001  /* Enable Handshake DMA 0/1                                     */
+#define REP                     0x0002  /* HDMA Request Polarity                                        */
+#define UTE                     0x0004  /* Urgency Threshold Enable                                     */
+#define OIE                     0x0010  /* Overflow Interrupt Enable                            */
+#define BDIE            0x0020  /* Block Done Interrupt Enable                          */
+#define MBDI            0x0040  /* Mask Block Done IRQ If Pending ECNT          */
+#define DRQ                     0x0300  /* HDMA Request Type                                            */
+#define DRQ_NONE        0x0000  /*              No Request                                                      */
+#define DRQ_SINGLE      0x0100  /*              Channels Request Single                         */
+#define DRQ_MULTI       0x0200  /*              Channels Request Multi (Default)        */
+#define DRQ_URGENT      0x0300  /*              Channels Request Multi Urgent           */
+#define RBC                     0x1000  /* Reload BCNT With IBCNT                                       */
+#define PS                      0x2000  /* HDMA Pin Status                                                      */
+#define OI                      0x4000  /* Overflow Interrupt Generated                         */
+#define BDI                     0x8000  /* Block Done Interrupt Generated                       */
+
+#endif                          /* _DEF_BF534_H */
diff --git a/include/asm-blackfin/mach-bf537/defBF537.h b/include/asm-blackfin/mach-bf537/defBF537.h
new file mode 100644
index 000000000000..26f9c02eb73c
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/defBF537.h
@@ -0,0 +1,404 @@
+/*
+ * file:         include/asm-blackfin/mach-bf537/defbf537.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _DEF_BF537_H
+#define _DEF_BF537_H
+
+/*include all Core registers and bit definitions*/
+#include "defBF537.h"
+
+/*include core specific register pointer definitions*/
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+/************************************************************************************
+** Define EMAC Section Unique to BF536/BF537
+*************************************************************************************/
+
+/* 10/100 Ethernet Controller   (0xFFC03000 - 0xFFC031FF)                                                                               */
+#define EMAC_OPMODE                     0xFFC03000      /* Operating Mode Register                                                              */
+#define EMAC_ADDRLO                     0xFFC03004      /* Address Low (32 LSBs) Register                                               */
+#define EMAC_ADDRHI                     0xFFC03008      /* Address High (16 MSBs) Register                                              */
+#define EMAC_HASHLO                     0xFFC0300C      /* Multicast Hash Table Low (Bins 31-0) Register                */
+#define EMAC_HASHHI                     0xFFC03010      /* Multicast Hash Table High (Bins 63-32) Register              */
+#define EMAC_STAADD                     0xFFC03014      /* Station Management Address Register                                  */
+#define EMAC_STADAT                     0xFFC03018      /* Station Management Data Register                                     */
+#define EMAC_FLC                        0xFFC0301C      /* Flow Control Register                                                                */
+#define EMAC_VLAN1                      0xFFC03020      /* VLAN1 Tag Register                                                                   */
+#define EMAC_VLAN2                      0xFFC03024      /* VLAN2 Tag Register                                                                   */
+#define EMAC_WKUP_CTL           0xFFC0302C      /* Wake-Up Control/Status Register                                              */
+#define EMAC_WKUP_FFMSK0        0xFFC03030      /* Wake-Up Frame Filter 0 Byte Mask Register                    */
+#define EMAC_WKUP_FFMSK1        0xFFC03034      /* Wake-Up Frame Filter 1 Byte Mask Register                    */
+#define EMAC_WKUP_FFMSK2        0xFFC03038      /* Wake-Up Frame Filter 2 Byte Mask Register                    */
+#define EMAC_WKUP_FFMSK3        0xFFC0303C      /* Wake-Up Frame Filter 3 Byte Mask Register                    */
+#define EMAC_WKUP_FFCMD         0xFFC03040      /* Wake-Up Frame Filter Commands Register                               */
+#define EMAC_WKUP_FFOFF         0xFFC03044      /* Wake-Up Frame Filter Offsets Register                                */
+#define EMAC_WKUP_FFCRC0        0xFFC03048      /* Wake-Up Frame Filter 0,1 CRC-16 Register                             */
+#define EMAC_WKUP_FFCRC1        0xFFC0304C      /* Wake-Up Frame Filter 2,3 CRC-16 Register                             */
+
+#define EMAC_SYSCTL                     0xFFC03060      /* EMAC System Control Register                                                 */
+#define EMAC_SYSTAT                     0xFFC03064      /* EMAC System Status Register                                                  */
+#define EMAC_RX_STAT            0xFFC03068      /* RX Current Frame Status Register                                             */
+#define EMAC_RX_STKY            0xFFC0306C      /* RX Sticky Frame Status Register                                              */
+#define EMAC_RX_IRQE            0xFFC03070      /* RX Frame Status Interrupt Enables Register                   */
+#define EMAC_TX_STAT            0xFFC03074      /* TX Current Frame Status Register                                             */
+#define EMAC_TX_STKY            0xFFC03078      /* TX Sticky Frame Status Register                                              */
+#define EMAC_TX_IRQE            0xFFC0307C      /* TX Frame Status Interrupt Enables Register                   */
+
+#define EMAC_MMC_CTL            0xFFC03080      /* MMC Counter Control Register                                                 */
+#define EMAC_MMC_RIRQS          0xFFC03084      /* MMC RX Interrupt Status Register                                             */
+#define EMAC_MMC_RIRQE          0xFFC03088      /* MMC RX Interrupt Enables Register                                    */
+#define EMAC_MMC_TIRQS          0xFFC0308C      /* MMC TX Interrupt Status Register                                             */
+#define EMAC_MMC_TIRQE          0xFFC03090      /* MMC TX Interrupt Enables Register                                    */
+
+#define EMAC_RXC_OK                     0xFFC03100      /* RX Frame Successful Count                                                    */
+#define EMAC_RXC_FCS            0xFFC03104      /* RX Frame FCS Failure Count                                                   */
+#define EMAC_RXC_ALIGN          0xFFC03108      /* RX Alignment Error Count                                                             */
+#define EMAC_RXC_OCTET          0xFFC0310C      /* RX Octets Successfully Received Count                                */
+#define EMAC_RXC_DMAOVF         0xFFC03110      /* Internal MAC Sublayer Error RX Frame Count                   */
+#define EMAC_RXC_UNICST         0xFFC03114      /* Unicast RX Frame Count                                                               */
+#define EMAC_RXC_MULTI          0xFFC03118      /* Multicast RX Frame Count                                                             */
+#define EMAC_RXC_BROAD          0xFFC0311C      /* Broadcast RX Frame Count                                                             */
+#define EMAC_RXC_LNERRI         0xFFC03120      /* RX Frame In Range Error Count                                                */
+#define EMAC_RXC_LNERRO         0xFFC03124      /* RX Frame Out Of Range Error Count                                    */
+#define EMAC_RXC_LONG           0xFFC03128      /* RX Frame Too Long Count                                                              */
+#define EMAC_RXC_MACCTL         0xFFC0312C      /* MAC Control RX Frame Count                                                   */
+#define EMAC_RXC_OPCODE         0xFFC03130      /* Unsupported Op-Code RX Frame Count                                   */
+#define EMAC_RXC_PAUSE          0xFFC03134      /* MAC Control Pause RX Frame Count                                             */
+#define EMAC_RXC_ALLFRM         0xFFC03138      /* Overall RX Frame Count                                                               */
+#define EMAC_RXC_ALLOCT         0xFFC0313C      /* Overall RX Octet Count                                                               */
+#define EMAC_RXC_TYPED          0xFFC03140      /* Type/Length Consistent RX Frame Count                                */
+#define EMAC_RXC_SHORT          0xFFC03144      /* RX Frame Fragment Count - Byte Count x < 64                  */
+#define EMAC_RXC_EQ64           0xFFC03148      /* Good RX Frame Count - Byte Count x = 64                              */
+#define EMAC_RXC_LT128          0xFFC0314C      /* Good RX Frame Count - Byte Count  64 <= x < 128              */
+#define EMAC_RXC_LT256          0xFFC03150      /* Good RX Frame Count - Byte Count 128 <= x < 256              */
+#define EMAC_RXC_LT512          0xFFC03154      /* Good RX Frame Count - Byte Count 256 <= x < 512              */
+#define EMAC_RXC_LT1024         0xFFC03158      /* Good RX Frame Count - Byte Count 512 <= x < 1024             */
+#define EMAC_RXC_GE1024         0xFFC0315C      /* Good RX Frame Count - Byte Count x >= 1024                   */
+
+#define EMAC_TXC_OK                     0xFFC03180      /* TX Frame Successful Count                                                    */
+#define EMAC_TXC_1COL           0xFFC03184      /* TX Frames Successful After Single Collision Count    */
+#define EMAC_TXC_GT1COL         0xFFC03188      /* TX Frames Successful After Multiple Collisions Count */
+#define EMAC_TXC_OCTET          0xFFC0318C      /* TX Octets Successfully Received Count                                */
+#define EMAC_TXC_DEFER          0xFFC03190      /* TX Frame Delayed Due To Busy Count                                   */
+#define EMAC_TXC_LATECL         0xFFC03194      /* Late TX Collisions Count                                                             */
+#define EMAC_TXC_XS_COL         0xFFC03198      /* TX Frame Failed Due To Excessive Collisions Count    */
+#define EMAC_TXC_DMAUND         0xFFC0319C      /* Internal MAC Sublayer Error TX Frame Count                   */
+#define EMAC_TXC_CRSERR         0xFFC031A0      /* Carrier Sense Deasserted During TX Frame Count               */
+#define EMAC_TXC_UNICST         0xFFC031A4      /* Unicast TX Frame Count                                                               */
+#define EMAC_TXC_MULTI          0xFFC031A8      /* Multicast TX Frame Count                                                             */
+#define EMAC_TXC_BROAD          0xFFC031AC      /* Broadcast TX Frame Count                                                             */
+#define EMAC_TXC_XS_DFR         0xFFC031B0      /* TX Frames With Excessive Deferral Count                              */
+#define EMAC_TXC_MACCTL         0xFFC031B4      /* MAC Control TX Frame Count                                                   */
+#define EMAC_TXC_ALLFRM         0xFFC031B8      /* Overall TX Frame Count                                                               */
+#define EMAC_TXC_ALLOCT         0xFFC031BC      /* Overall TX Octet Count                                                               */
+#define EMAC_TXC_EQ64           0xFFC031C0      /* Good TX Frame Count - Byte Count x = 64                              */
+#define EMAC_TXC_LT128          0xFFC031C4      /* Good TX Frame Count - Byte Count  64 <= x < 128              */
+#define EMAC_TXC_LT256          0xFFC031C8      /* Good TX Frame Count - Byte Count 128 <= x < 256              */
+#define EMAC_TXC_LT512          0xFFC031CC      /* Good TX Frame Count - Byte Count 256 <= x < 512              */
+#define EMAC_TXC_LT1024         0xFFC031D0      /* Good TX Frame Count - Byte Count 512 <= x < 1024             */
+#define EMAC_TXC_GE1024         0xFFC031D4      /* Good TX Frame Count - Byte Count x >= 1024                   */
+#define EMAC_TXC_ABORT          0xFFC031D8      /* Total TX Frames Aborted Count                                                */
+
+/* Listing for IEEE-Supported Count Registers                                                                                                                                   */
+#define FramesReceivedOK                                EMAC_RXC_OK     /* RX Frame Successful Count                                                    */
+#define FrameCheckSequenceErrors                EMAC_RXC_FCS    /* RX Frame FCS Failure Count                                                   */
+#define AlignmentErrors                                 EMAC_RXC_ALIGN  /* RX Alignment Error Count                                                             */
+#define OctetsReceivedOK                                EMAC_RXC_OCTET  /* RX Octets Successfully Received Count                                */
+#define FramesLostDueToIntMACRcvError   EMAC_RXC_DMAOVF /* Internal MAC Sublayer Error RX Frame Count                   */
+#define UnicastFramesReceivedOK                 EMAC_RXC_UNICST /* Unicast RX Frame Count                                                               */
+#define MulticastFramesReceivedOK               EMAC_RXC_MULTI  /* Multicast RX Frame Count                                                             */
+#define BroadcastFramesReceivedOK               EMAC_RXC_BROAD  /* Broadcast RX Frame Count                                                             */
+#define InRangeLengthErrors                             EMAC_RXC_LNERRI /* RX Frame In Range Error Count                                                */
+#define OutOfRangeLengthField                   EMAC_RXC_LNERRO /* RX Frame Out Of Range Error Count                                    */
+#define FrameTooLongErrors                              EMAC_RXC_LONG   /* RX Frame Too Long Count                                                              */
+#define MACControlFramesReceived                EMAC_RXC_MACCTL /* MAC Control RX Frame Count                                                   */
+#define UnsupportedOpcodesReceived              EMAC_RXC_OPCODE /* Unsupported Op-Code RX Frame Count                                   */
+#define PAUSEMACCtrlFramesReceived              EMAC_RXC_PAUSE  /* MAC Control Pause RX Frame Count                                             */
+#define FramesReceivedAll                               EMAC_RXC_ALLFRM /* Overall RX Frame Count                                                               */
+#define OctetsReceivedAll                               EMAC_RXC_ALLOCT /* Overall RX Octet Count                                                               */
+#define TypedFramesReceived                             EMAC_RXC_TYPED  /* Type/Length Consistent RX Frame Count                                */
+#define FramesLenLt64Received                   EMAC_RXC_SHORT  /* RX Frame Fragment Count - Byte Count x < 64                  */
+#define FramesLenEq64Received                   EMAC_RXC_EQ64   /* Good RX Frame Count - Byte Count x = 64                              */
+#define FramesLen65_127Received                 EMAC_RXC_LT128  /* Good RX Frame Count - Byte Count  64 <= x < 128              */
+#define FramesLen128_255Received                EMAC_RXC_LT256  /* Good RX Frame Count - Byte Count 128 <= x < 256              */
+#define FramesLen256_511Received                EMAC_RXC_LT512  /* Good RX Frame Count - Byte Count 256 <= x < 512              */
+#define FramesLen512_1023Received               EMAC_RXC_LT1024 /* Good RX Frame Count - Byte Count 512 <= x < 1024             */
+#define FramesLen1024_MaxReceived               EMAC_RXC_GE1024 /* Good RX Frame Count - Byte Count x >= 1024                   */
+
+#define FramesTransmittedOK                             EMAC_TXC_OK     /* TX Frame Successful Count                                                    */
+#define SingleCollisionFrames                   EMAC_TXC_1COL   /* TX Frames Successful After Single Collision Count    */
+#define MultipleCollisionFrames                 EMAC_TXC_GT1COL /* TX Frames Successful After Multiple Collisions Count */
+#define OctetsTransmittedOK                             EMAC_TXC_OCTET  /* TX Octets Successfully Received Count                                */
+#define FramesWithDeferredXmissions             EMAC_TXC_DEFER  /* TX Frame Delayed Due To Busy Count                                   */
+#define LateCollisions                                  EMAC_TXC_LATECL /* Late TX Collisions Count                                                             */
+#define FramesAbortedDueToXSColls               EMAC_TXC_XS_COL /* TX Frame Failed Due To Excessive Collisions Count    */
+#define FramesLostDueToIntMacXmitError  EMAC_TXC_DMAUND /* Internal MAC Sublayer Error TX Frame Count                   */
+#define CarrierSenseErrors                              EMAC_TXC_CRSERR /* Carrier Sense Deasserted During TX Frame Count               */
+#define UnicastFramesXmittedOK                  EMAC_TXC_UNICST /* Unicast TX Frame Count                                                               */
+#define MulticastFramesXmittedOK                EMAC_TXC_MULTI  /* Multicast TX Frame Count                                                             */
+#define BroadcastFramesXmittedOK                EMAC_TXC_BROAD  /* Broadcast TX Frame Count                                                             */
+#define FramesWithExcessiveDeferral             EMAC_TXC_XS_DFR /* TX Frames With Excessive Deferral Count                              */
+#define MACControlFramesTransmitted             EMAC_TXC_MACCTL /* MAC Control TX Frame Count                                                   */
+#define FramesTransmittedAll                    EMAC_TXC_ALLFRM /* Overall TX Frame Count                                                               */
+#define OctetsTransmittedAll                    EMAC_TXC_ALLOCT /* Overall TX Octet Count                                                               */
+#define FramesLenEq64Transmitted                EMAC_TXC_EQ64   /* Good TX Frame Count - Byte Count x = 64                              */
+#define FramesLen65_127Transmitted              EMAC_TXC_LT128  /* Good TX Frame Count - Byte Count  64 <= x < 128              */
+#define FramesLen128_255Transmitted             EMAC_TXC_LT256  /* Good TX Frame Count - Byte Count 128 <= x < 256              */
+#define FramesLen256_511Transmitted             EMAC_TXC_LT512  /* Good TX Frame Count - Byte Count 256 <= x < 512              */
+#define FramesLen512_1023Transmitted    EMAC_TXC_LT1024 /* Good TX Frame Count - Byte Count 512 <= x < 1024             */
+#define FramesLen1024_MaxTransmitted    EMAC_TXC_GE1024 /* Good TX Frame Count - Byte Count x >= 1024                   */
+#define TxAbortedFrames                                 EMAC_TXC_ABORT  /* Total TX Frames Aborted Count                                                */
+
+/***********************************************************************************
+** System MMR Register Bits And Macros
+**
+** Disclaimer:  All macros are intended to make C and Assembly code more readable.
+**                              Use these macros carefully, as any that do left shifts for field
+**                              depositing will result in the lower order bits being destroyed.  Any
+**                              macro that shifts left to properly position the bit-field should be
+**                              used as part of an OR to initialize a register and NOT as a dynamic
+**                              modifier UNLESS the lower order bits are saved and ORed back in when
+**                              the macro is used.
+*************************************************************************************/
+/************************  ETHERNET 10/100 CONTROLLER MASKS  ************************/
+/* EMAC_OPMODE Masks                                                                                                                            */
+#define RE                      0x00000001      /* Receiver Enable                                                                      */
+#define ASTP            0x00000002      /* Enable Automatic Pad Stripping On RX Frames          */
+#define HU                      0x00000010      /* Hash Filter Unicast Address                                          */
+#define HM                      0x00000020      /* Hash Filter Multicast Address                                        */
+#define PAM                     0x00000040      /* Pass-All-Multicast Mode Enable                                       */
+#define PR                      0x00000080      /* Promiscuous Mode Enable                                                      */
+#define IFE                     0x00000100      /* Inverse Filtering Enable                                                     */
+#define DBF                     0x00000200      /* Disable Broadcast Frame Reception                            */
+#define PBF                     0x00000400      /* Pass Bad Frames Enable                                                       */
+#define PSF                     0x00000800      /* Pass Short Frames Enable                                                     */
+#define RAF                     0x00001000      /* Receive-All Mode                                                                     */
+#define TE                      0x00010000      /* Transmitter Enable                                                           */
+#define DTXPAD          0x00020000      /* Disable Automatic TX Padding                                         */
+#define DTXCRC          0x00040000      /* Disable Automatic TX CRC Generation                          */
+#define DC                      0x00080000      /* Deferral Check                                                                       */
+#define BOLMT           0x00300000      /* Back-Off Limit                                                                       */
+#define BOLMT_10        0x00000000      /*              10-bit range                                                            */
+#define BOLMT_8         0x00100000      /*              8-bit range                                                                     */
+#define BOLMT_4         0x00200000      /*              4-bit range                                                                     */
+#define BOLMT_1         0x00300000      /*              1-bit range                                                                     */
+#define DRTY            0x00400000      /* Disable TX Retry On Collision                                        */
+#define LCTRE           0x00800000      /* Enable TX Retry On Late Collision                            */
+#define RMII            0x01000000      /* RMII/MII* Mode                                                                       */
+#define RMII_10         0x02000000      /* Speed Select for RMII Port (10MBit/100MBit*)         */
+#define FDMODE          0x04000000      /* Duplex Mode Enable (Full/Half*)                                      */
+#define LB                      0x08000000      /* Internal Loopback Enable                                                     */
+#define DRO                     0x10000000      /* Disable Receive Own Frames (Half-Duplex Mode)        */
+
+/* EMAC_STAADD Masks                                                                                                                            */
+#define STABUSY         0x00000001      /* Initiate Station Mgt Reg Access / STA Busy Stat      */
+#define STAOP           0x00000002      /* Station Management Operation Code (Write/Read*)      */
+#define STADISPRE       0x00000004      /* Disable Preamble Generation                                          */
+#define STAIE           0x00000008      /* Station Mgt. Transfer Done Interrupt Enable          */
+#define REGAD           0x000007C0      /* STA Register Address                                                         */
+#define PHYAD           0x0000F800      /* PHY Device Address                                                           */
+
+#define SET_REGAD(x)    (((x)&0x1F)<<  6 )      /* Set STA Register Address                             */
+#define SET_PHYAD(x)    (((x)&0x1F)<< 11 )      /* Set PHY Device Address                               */
+
+/* EMAC_STADAT Mask                                                                                     */
+#define STADATA         0x0000FFFF      /* Station Management Data      */
+
+/* EMAC_FLC Masks                                                                                                                                       */
+#define FLCBUSY         0x00000001      /* Send Flow Ctrl Frame / Flow Ctrl Busy Status         */
+#define FLCE            0x00000002      /* Flow Control Enable                                                          */
+#define PCF                     0x00000004      /* Pass Control Frames                                                          */
+#define BKPRSEN         0x00000008      /* Enable Backpressure                                                          */
+#define FLCPAUSE        0xFFFF0000      /* Pause Time                                                                           */
+
+#define SET_FLCPAUSE(x) (((x)&0xFFFF)<< 16)     /* Set Pause Time                                               */
+
+/* EMAC_WKUP_CTL Masks                                                                                                                          */
+#define CAPWKFRM        0x00000001      /* Capture Wake-Up Frames                                                       */
+#define MPKE            0x00000002      /* Magic Packet Enable                                                          */
+#define RWKE            0x00000004      /* Remote Wake-Up Frame Enable                                          */
+#define GUWKE           0x00000008      /* Global Unicast Wake Enable                                           */
+#define MPKS            0x00000020      /* Magic Packet Received Status                                         */
+#define RWKS            0x00000F00      /* Wake-Up Frame Received Status, Filters 3:0           */
+
+/* EMAC_WKUP_FFCMD Masks                                                                                                                        */
+#define WF0_E           0x00000001      /* Enable Wake-Up Filter 0                                                      */
+#define WF0_T           0x00000008      /* Wake-Up Filter 0 Addr Type (Multicast/Unicast*)      */
+#define WF1_E           0x00000100      /* Enable Wake-Up Filter 1                                                      */
+#define WF1_T           0x00000800      /* Wake-Up Filter 1 Addr Type (Multicast/Unicast*)      */
+#define WF2_E           0x00010000      /* Enable Wake-Up Filter 2                                                      */
+#define WF2_T           0x00080000      /* Wake-Up Filter 2 Addr Type (Multicast/Unicast*)      */
+#define WF3_E           0x01000000      /* Enable Wake-Up Filter 3                                                      */
+#define WF3_T           0x08000000      /* Wake-Up Filter 3 Addr Type (Multicast/Unicast*)      */
+
+/* EMAC_WKUP_FFOFF Masks                                                                                                                        */
+#define WF0_OFF         0x000000FF      /* Wake-Up Filter 0 Pattern Offset                                      */
+#define WF1_OFF         0x0000FF00      /* Wake-Up Filter 1 Pattern Offset                                      */
+#define WF2_OFF         0x00FF0000      /* Wake-Up Filter 2 Pattern Offset                                      */
+#define WF3_OFF         0xFF000000      /* Wake-Up Filter 3 Pattern Offset                                      */
+
+#define SET_WF0_OFF(x) (((x)&0xFF)<<  0 )       /* Set Wake-Up Filter 0 Byte Offset           */
+#define SET_WF1_OFF(x) (((x)&0xFF)<<  8 )       /* Set Wake-Up Filter 1 Byte Offset           */
+#define SET_WF2_OFF(x) (((x)&0xFF)<< 16 )       /* Set Wake-Up Filter 2 Byte Offset           */
+#define SET_WF3_OFF(x) (((x)&0xFF)<< 24 )       /* Set Wake-Up Filter 3 Byte Offset           */
+/* Set ALL Offsets                                                                                                                                      */
+#define SET_WF_OFFS(x0,x1,x2,x3)        (SET_WF0_OFF((x0))|SET_WF1_OFF((x1))|SET_WF2_OFF((x2))|SET_WF3_OFF((x3)))
+
+/* EMAC_WKUP_FFCRC0 Masks                                                                                                                       */
+#define WF0_CRC         0x0000FFFF      /* Wake-Up Filter 0 Pattern CRC                                         */
+#define WF1_CRC         0xFFFF0000      /* Wake-Up Filter 1 Pattern CRC                                         */
+
+#define SET_WF0_CRC(x) (((x)&0xFFFF)<<   0 )    /* Set Wake-Up Filter 0 Target CRC         */
+#define SET_WF1_CRC(x) (((x)&0xFFFF)<<  16 )    /* Set Wake-Up Filter 1 Target CRC         */
+
+/* EMAC_WKUP_FFCRC1 Masks                                                                                                                       */
+#define WF2_CRC         0x0000FFFF      /* Wake-Up Filter 2 Pattern CRC                                         */
+#define WF3_CRC         0xFFFF0000      /* Wake-Up Filter 3 Pattern CRC                                         */
+
+#define SET_WF2_CRC(x) (((x)&0xFFFF)<<   0 )    /* Set Wake-Up Filter 2 Target CRC         */
+#define SET_WF3_CRC(x) (((x)&0xFFFF)<<  16 )    /* Set Wake-Up Filter 3 Target CRC         */
+
+/* EMAC_SYSCTL Masks                                                                                                                            */
+#define PHYIE           0x00000001      /* PHY_INT Interrupt Enable                                                     */
+#define RXDWA           0x00000002      /* Receive Frame DMA Word Alignment (Odd/Even*)         */
+#define RXCKS           0x00000004      /* Enable RX Frame TCP/UDP Checksum Computation         */
+#define MDCDIV          0x00003F00      /* SCLK:MDC Clock Divisor [MDC=SCLK/(2*(N+1))]          */
+
+#define SET_MDCDIV(x)   (((x)&0x3F)<< 8)        /* Set MDC Clock Divisor                                */
+
+/* EMAC_SYSTAT Masks                                                                                                                    */
+#define PHYINT          0x00000001      /* PHY_INT Interrupt Status                                             */
+#define MMCINT          0x00000002      /* MMC Counter Interrupt Status                                 */
+#define RXFSINT         0x00000004      /* RX Frame-Status Interrupt Status                             */
+#define TXFSINT         0x00000008      /* TX Frame-Status Interrupt Status                             */
+#define WAKEDET         0x00000010      /* Wake-Up Detected Status                                              */
+#define RXDMAERR        0x00000020      /* RX DMA Direction Error Status                                */
+#define TXDMAERR        0x00000040      /* TX DMA Direction Error Status                                */
+#define STMDONE         0x00000080      /* Station Mgt. Transfer Done Interrupt Status  */
+
+/* EMAC_RX_STAT, EMAC_RX_STKY, and EMAC_RX_IRQE Masks                                                   */
+#define RX_FRLEN        0x000007FF      /* Frame Length In Bytes                                                */
+#define RX_COMP         0x00001000      /* RX Frame Complete                                                    */
+#define RX_OK           0x00002000      /* RX Frame Received With No Errors                             */
+#define RX_LONG         0x00004000      /* RX Frame Too Long Error                                              */
+#define RX_ALIGN        0x00008000      /* RX Frame Alignment Error                                             */
+#define RX_CRC          0x00010000      /* RX Frame CRC Error                                                   */
+#define RX_LEN          0x00020000      /* RX Frame Length Error                                                */
+#define RX_FRAG         0x00040000      /* RX Frame Fragment Error                                              */
+#define RX_ADDR         0x00080000      /* RX Frame Address Filter Failed Error                 */
+#define RX_DMAO         0x00100000      /* RX Frame DMA Overrun Error                                   */
+#define RX_PHY          0x00200000      /* RX Frame PHY Error                                                   */
+#define RX_LATE         0x00400000      /* RX Frame Late Collision Error                                */
+#define RX_RANGE        0x00800000      /* RX Frame Length Field Out of Range Error             */
+#define RX_MULTI        0x01000000      /* RX Multicast Frame Indicator                                 */
+#define RX_BROAD        0x02000000      /* RX Broadcast Frame Indicator                                 */
+#define RX_CTL          0x04000000      /* RX Control Frame Indicator                                   */
+#define RX_UCTL         0x08000000      /* Unsupported RX Control Frame Indicator               */
+#define RX_TYPE         0x10000000      /* RX Typed Frame Indicator                                             */
+#define RX_VLAN1        0x20000000      /* RX VLAN1 Frame Indicator                                             */
+#define RX_VLAN2        0x40000000      /* RX VLAN2 Frame Indicator                                             */
+#define RX_ACCEPT       0x80000000      /* RX Frame Accepted Indicator                                  */
+
+/*  EMAC_TX_STAT, EMAC_TX_STKY, and EMAC_TX_IRQE Masks                                                  */
+#define TX_COMP         0x00000001      /* TX Frame Complete                                                    */
+#define TX_OK           0x00000002      /* TX Frame Sent With No Errors                                 */
+#define TX_ECOLL        0x00000004      /* TX Frame Excessive Collision Error                   */
+#define TX_LATE         0x00000008      /* TX Frame Late Collision Error                                */
+#define TX_DMAU         0x00000010      /* TX Frame DMA Underrun Error (STAT)                   */
+#define TX_MACE         0x00000010      /* Internal MAC Error Detected (STKY and IRQE)  */
+#define TX_EDEFER       0x00000020      /* TX Frame Excessive Deferral Error                    */
+#define TX_BROAD        0x00000040      /* TX Broadcast Frame Indicator                                 */
+#define TX_MULTI        0x00000080      /* TX Multicast Frame Indicator                                 */
+#define TX_CCNT         0x00000F00      /* TX Frame Collision Count                                             */
+#define TX_DEFER        0x00001000      /* TX Frame Deferred Indicator                                  */
+#define TX_CRS          0x00002000      /* TX Frame Carrier Sense Not Asserted Error    */
+#define TX_LOSS         0x00004000      /* TX Frame Carrier Lost During TX Error                */
+#define TX_RETRY        0x00008000      /* TX Frame Successful After Retry                              */
+#define TX_FRLEN        0x07FF0000      /* TX Frame Length (Bytes)                                              */
+
+/* EMAC_MMC_CTL Masks                                                                                                                   */
+#define RSTC            0x00000001      /* Reset All Counters                                                   */
+#define CROLL           0x00000002      /* Counter Roll-Over Enable                                             */
+#define CCOR            0x00000004      /* Counter Clear-On-Read Mode Enable                    */
+#define MMCE            0x00000008      /* Enable MMC Counter Operation                                 */
+
+/* EMAC_MMC_RIRQS and EMAC_MMC_RIRQE Masks                                                                                      */
+#define RX_OK_CNT               0x00000001      /* RX Frames Received With No Errors                    */
+#define RX_FCS_CNT              0x00000002      /* RX Frames W/Frame Check Sequence Errors              */
+#define RX_ALIGN_CNT    0x00000004      /* RX Frames With Alignment Errors                              */
+#define RX_OCTET_CNT    0x00000008      /* RX Octets Received OK                                                */
+#define RX_LOST_CNT             0x00000010      /* RX Frames Lost Due To Internal MAC RX Error  */
+#define RX_UNI_CNT              0x00000020      /* Unicast RX Frames Received OK                                */
+#define RX_MULTI_CNT    0x00000040      /* Multicast RX Frames Received OK                              */
+#define RX_BROAD_CNT    0x00000080      /* Broadcast RX Frames Received OK                              */
+#define RX_IRL_CNT              0x00000100      /* RX Frames With In-Range Length Errors                */
+#define RX_ORL_CNT              0x00000200      /* RX Frames With Out-Of-Range Length Errors    */
+#define RX_LONG_CNT             0x00000400      /* RX Frames With Frame Too Long Errors                 */
+#define RX_MACCTL_CNT   0x00000800      /* MAC Control RX Frames Received                               */
+#define RX_OPCODE_CTL   0x00001000      /* Unsupported Op-Code RX Frames Received               */
+#define RX_PAUSE_CNT    0x00002000      /* PAUSEMAC Control RX Frames Received                  */
+#define RX_ALLF_CNT             0x00004000      /* All RX Frames Received                                               */
+#define RX_ALLO_CNT             0x00008000      /* All RX Octets Received                                               */
+#define RX_TYPED_CNT    0x00010000      /* Typed RX Frames Received                                             */
+#define RX_SHORT_CNT    0x00020000      /* RX Frame Fragments (< 64 Bytes) Received             */
+#define RX_EQ64_CNT             0x00040000      /* 64-Byte RX Frames Received                                   */
+#define RX_LT128_CNT    0x00080000      /* 65-127-Byte RX Frames Received                               */
+#define RX_LT256_CNT    0x00100000      /* 128-255-Byte RX Frames Received                              */
+#define RX_LT512_CNT    0x00200000      /* 256-511-Byte RX Frames Received                              */
+#define RX_LT1024_CNT   0x00400000      /* 512-1023-Byte RX Frames Received                             */
+#define RX_GE1024_CNT   0x00800000      /* 1024-Max-Byte RX Frames Received                             */
+
+/* EMAC_MMC_TIRQS and EMAC_MMC_TIRQE Masks                                                                                      */
+#define TX_OK_CNT               0x00000001      /* TX Frames Sent OK                                                    */
+#define TX_SCOLL_CNT    0x00000002      /* TX Frames With Single Collisions                             */
+#define TX_MCOLL_CNT    0x00000004      /* TX Frames With Multiple Collisions                   */
+#define TX_OCTET_CNT    0x00000008      /* TX Octets Sent OK                                                    */
+#define TX_DEFER_CNT    0x00000010      /* TX Frames With Deferred Transmission                 */
+#define TX_LATE_CNT             0x00000020      /* TX Frames With Late Collisions                               */
+#define TX_ABORTC_CNT   0x00000040      /* TX Frames Aborted Due To Excess Collisions   */
+#define TX_LOST_CNT             0x00000080      /* TX Frames Lost Due To Internal MAC TX Error  */
+#define TX_CRS_CNT              0x00000100      /* TX Frames With Carrier Sense Errors                  */
+#define TX_UNI_CNT              0x00000200      /* Unicast TX Frames Sent                                               */
+#define TX_MULTI_CNT    0x00000400      /* Multicast TX Frames Sent                                             */
+#define TX_BROAD_CNT    0x00000800      /* Broadcast TX Frames Sent                                             */
+#define TX_EXDEF_CTL    0x00001000      /* TX Frames With Excessive Deferral                    */
+#define TX_MACCTL_CNT   0x00002000      /* MAC Control TX Frames Sent                                   */
+#define TX_ALLF_CNT             0x00004000      /* All TX Frames Sent                                                   */
+#define TX_ALLO_CNT             0x00008000      /* All TX Octets Sent                                                   */
+#define TX_EQ64_CNT             0x00010000      /* 64-Byte TX Frames Sent                                               */
+#define TX_LT128_CNT    0x00020000      /* 65-127-Byte TX Frames Sent                                   */
+#define TX_LT256_CNT    0x00040000      /* 128-255-Byte TX Frames Sent                                  */
+#define TX_LT512_CNT    0x00080000      /* 256-511-Byte TX Frames Sent                                  */
+#define TX_LT1024_CNT   0x00100000      /* 512-1023-Byte TX Frames Sent                                 */
+#define TX_GE1024_CNT   0x00200000      /* 1024-Max-Byte TX Frames Sent                                 */
+#define TX_ABORT_CNT    0x00400000      /* TX Frames Aborted                                                    */
+
+#endif                          /* _DEF_BF537_H */
diff --git a/include/asm-blackfin/mach-bf537/dma.h b/include/asm-blackfin/mach-bf537/dma.h
new file mode 100644
index 000000000000..7a964040870a
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/dma.h
@@ -0,0 +1,55 @@
+/*
+ * file:         include/asm-blackfin/mach-bf537/dma.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+
+#define MAX_BLACKFIN_DMA_CHANNEL 16
+
+#define CH_PPI                      0
+#define CH_EMAC_RX                  1
+#define CH_EMAC_TX                  2
+#define CH_SPORT0_RX            3
+#define CH_SPORT0_TX            4
+#define CH_SPORT1_RX            5
+#define CH_SPORT1_TX            6
+#define CH_SPI                      7
+#define CH_UART0_RX             8
+#define CH_UART0_TX             9
+#define CH_UART1_RX             10
+#define CH_UART1_TX             11
+
+#define CH_MEM_STREAM0_DEST     12       /* TX */
+#define CH_MEM_STREAM0_SRC      13       /* RX */
+#define CH_MEM_STREAM1_DEST     14       /* TX */
+#define CH_MEM_STREAM1_SRC      15       /* RX */
+
+#endif
diff --git a/include/asm-blackfin/mach-bf537/irq.h b/include/asm-blackfin/mach-bf537/irq.h
new file mode 100644
index 000000000000..8af2a832ef6b
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/irq.h
@@ -0,0 +1,219 @@
+/*
+ * file:         include/asm-blackfin/mach-bf537/irq.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      system mmr register map
+ * rev:
+ *
+ * modified:
+ *
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _BF537_IRQ_H_
+#define _BF537_IRQ_H_
+
+/*
+ * Interrupt source definitions
+             Event Source    Core Event Name
+Core        Emulation               **
+ Events         (highest priority)  EMU         0
+            Reset                   RST         1
+            NMI                     NMI         2
+            Exception               EVX         3
+            Reserved                --          4
+            Hardware Error          IVHW        5
+            Core Timer              IVTMR       6 *
+
+.....
+
+            Software Interrupt 1    IVG14       31
+            Software Interrupt 2    --
+                 (lowest priority)  IVG15       32 *
+ */
+
+#define SYS_IRQS        41
+#define NR_PERI_INTS    32
+
+/* The ABSTRACT IRQ definitions */
+/** the first seven of the following are fixed, the rest you change if you need to **/
+#define IRQ_EMU             0   /*Emulation */
+#define IRQ_RST             1   /*reset */
+#define IRQ_NMI             2   /*Non Maskable */
+#define IRQ_EVX             3   /*Exception */
+#define IRQ_UNUSED          4   /*- unused interrupt*/
+#define IRQ_HWERR           5   /*Hardware Error */
+#define IRQ_CORETMR         6   /*Core timer */
+
+#define IRQ_PLL_WAKEUP      7   /*PLL Wakeup Interrupt */
+#define IRQ_DMA_ERROR       8   /*DMA Error (general) */
+#define IRQ_GENERIC_ERROR   9   /*GENERIC Error Interrupt */
+#define IRQ_RTC             10  /*RTC Interrupt */
+#define IRQ_PPI             11  /*DMA0 Interrupt (PPI) */
+#define IRQ_SPORT0_RX       12  /*DMA3 Interrupt (SPORT0 RX) */
+#define IRQ_SPORT0_TX       13  /*DMA4 Interrupt (SPORT0 TX) */
+#define IRQ_SPORT1_RX       14  /*DMA5 Interrupt (SPORT1 RX) */
+#define IRQ_SPORT1_TX       15  /*DMA6 Interrupt (SPORT1 TX) */
+#define IRQ_TWI             16  /*TWI Interrupt */
+#define IRQ_SPI             17  /*DMA7 Interrupt (SPI) */
+#define IRQ_UART0_RX        18  /*DMA8 Interrupt (UART0 RX) */
+#define IRQ_UART0_TX        19  /*DMA9 Interrupt (UART0 TX) */
+#define IRQ_UART1_RX        20  /*DMA10 Interrupt (UART1 RX) */
+#define IRQ_UART1_TX        21  /*DMA11 Interrupt (UART1 TX) */
+#define IRQ_CAN_RX          22  /*CAN Receive Interrupt */
+#define IRQ_CAN_TX          23  /*CAN Transmit Interrupt */
+#define IRQ_MAC_RX          24  /*DMA1 (Ethernet RX) Interrupt */
+#define IRQ_MAC_TX          25  /*DMA2 (Ethernet TX) Interrupt */
+#define IRQ_TMR0            26  /*Timer 0 */
+#define IRQ_TMR1            27  /*Timer 1 */
+#define IRQ_TMR2            28  /*Timer 2 */
+#define IRQ_TMR3            29  /*Timer 3 */
+#define IRQ_TMR4            30  /*Timer 4 */
+#define IRQ_TMR5            31  /*Timer 5 */
+#define IRQ_TMR6            32  /*Timer 6 */
+#define IRQ_TMR7            33  /*Timer 7 */
+#define IRQ_PROG_INTA       34  /* PF Ports F&G (PF15:0) Interrupt A */
+#define IRQ_PORTG_INTB      35  /* PF Port G (PF15:0) Interrupt B */
+#define IRQ_MEM_DMA0        36  /*(Memory DMA Stream 0) */
+#define IRQ_MEM_DMA1        37  /*(Memory DMA Stream 1) */
+#define IRQ_PROG_INTB       38  /* PF Ports F (PF15:0) Interrupt B */
+#define IRQ_WATCH           38  /*Watch Dog Timer */
+#define IRQ_SW_INT1         40  /*Software Int 1 */
+#define IRQ_SW_INT2         41  /*Software Int 2 (reserved for SYSCALL) */
+
+#define IRQ_PPI_ERROR       42  /*PPI Error Interrupt */
+#define IRQ_CAN_ERROR       43  /*CAN Error Interrupt */
+#define IRQ_MAC_ERROR       44  /*PPI Error Interrupt */
+#define IRQ_SPORT0_ERROR    45  /*SPORT0 Error Interrupt */
+#define IRQ_SPORT1_ERROR    46  /*SPORT1 Error Interrupt */
+#define IRQ_SPI_ERROR       47  /*SPI Error Interrupt */
+#define IRQ_UART0_ERROR     48  /*UART Error Interrupt */
+#define IRQ_UART1_ERROR     49  /*UART Error Interrupt */
+
+#define IRQ_PF0         50
+#define IRQ_PF1         51
+#define IRQ_PF2         52
+#define IRQ_PF3         53
+#define IRQ_PF4         54
+#define IRQ_PF5         55
+#define IRQ_PF6         56
+#define IRQ_PF7         57
+#define IRQ_PF8         58
+#define IRQ_PF9         59
+#define IRQ_PF10        60
+#define IRQ_PF11        61
+#define IRQ_PF12        62
+#define IRQ_PF13        63
+#define IRQ_PF14        64
+#define IRQ_PF15        65
+
+#define IRQ_PG0         66
+#define IRQ_PG1         67
+#define IRQ_PG2         68
+#define IRQ_PG3         69
+#define IRQ_PG4         70
+#define IRQ_PG5         71
+#define IRQ_PG6         72
+#define IRQ_PG7         73
+#define IRQ_PG8         74
+#define IRQ_PG9         75
+#define IRQ_PG10        76
+#define IRQ_PG11        77
+#define IRQ_PG12        78
+#define IRQ_PG13        79
+#define IRQ_PG14        80
+#define IRQ_PG15        81
+
+#define IRQ_PH0         82
+#define IRQ_PH1         83
+#define IRQ_PH2         84
+#define IRQ_PH3         85
+#define IRQ_PH4         86
+#define IRQ_PH5         87
+#define IRQ_PH6         88
+#define IRQ_PH7         89
+#define IRQ_PH8         90
+#define IRQ_PH9         91
+#define IRQ_PH10        92
+#define IRQ_PH11        93
+#define IRQ_PH12        94
+#define IRQ_PH13        95
+#define IRQ_PH14        96
+#define IRQ_PH15        97
+
+#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+#define NR_IRQS     (IRQ_PH15+1)
+#else
+#define NR_IRQS     (IRQ_UART1_ERROR+1)
+#endif
+
+#define IVG7            7
+#define IVG8            8
+#define IVG9            9
+#define IVG10           10
+#define IVG11           11
+#define IVG12           12
+#define IVG13           13
+#define IVG14           14
+#define IVG15           15
+
+/* IAR0 BIT FIELDS*/
+#define IRQ_PLL_WAKEUP_POS  0
+#define IRQ_DMA_ERROR_POS   4
+#define IRQ_ERROR_POS       8
+#define IRQ_RTC_POS         12
+#define IRQ_PPI_POS         16
+#define IRQ_SPORT0_RX_POS   20
+#define IRQ_SPORT0_TX_POS   24
+#define IRQ_SPORT1_RX_POS   28
+
+/* IAR1 BIT FIELDS*/
+#define IRQ_SPORT1_TX_POS   0
+#define IRQ_TWI_POS         4
+#define IRQ_SPI_POS         8
+#define IRQ_UART0_RX_POS    12
+#define IRQ_UART0_TX_POS    16
+#define IRQ_UART1_RX_POS    20
+#define IRQ_UART1_TX_POS    24
+#define IRQ_CAN_RX_POS      28
+
+/* IAR2 BIT FIELDS*/
+#define IRQ_CAN_TX_POS      0
+#define IRQ_MAC_RX_POS      4
+#define IRQ_MAC_TX_POS      8
+#define IRQ_TMR0_POS        12
+#define IRQ_TMR1_POS        16
+#define IRQ_TMR2_POS        20
+#define IRQ_TMR3_POS        24
+#define IRQ_TMR4_POS        28
+
+/* IAR3 BIT FIELDS*/
+#define IRQ_TMR5_POS        0
+#define IRQ_TMR6_POS        4
+#define IRQ_TMR7_POS        8
+#define IRQ_PROG_INTA_POS   12
+#define IRQ_PORTG_INTB_POS   16
+#define IRQ_MEM_DMA0_POS    20
+#define IRQ_MEM_DMA1_POS    24
+#define IRQ_WATCH_POS       28
+
+#endif                          /* _BF537_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf537/mem_init.h b/include/asm-blackfin/mach-bf537/mem_init.h
new file mode 100644
index 000000000000..9ad979d416c6
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/mem_init.h
@@ -0,0 +1,330 @@
+/*
+ * File:         include/asm-blackfin/mach-bf537/mem_init.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_MT48LC16M8A2TG_75 || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC32M8A2_75)
+#if (CONFIG_SCLK_HZ > 119402985)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_7
+#define SDRAM_tRAS_num  7
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_6
+#define SDRAM_tRAS_num  6
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_5
+#define SDRAM_tRAS_num  5
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_4
+#define SDRAM_tRAS_num  4
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_3
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_4
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_3
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_2
+#define SDRAM_tRAS_num  2
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ <= 29850746)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_1
+#define SDRAM_tRAS_num  1
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#endif
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC16M8A2TG_75)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC32M8A2_75)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_GENERIC_BOARD)
+  /*SDRAM INFORMATION: Modify this for your board */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_SIZE == 128)
+#define SDRAM_SIZE      EBSZ_128
+#endif
+#if (CONFIG_MEM_SIZE == 64)
+#define SDRAM_SIZE      EBSZ_64
+#endif
+#if (CONFIG_MEM_SIZE == 32)
+#define SDRAM_SIZE      EBSZ_32
+#endif
+#if (CONFIG_MEM_SIZE == 16)
+#define SDRAM_SIZE      EBSZ_16
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 11)
+#define SDRAM_WIDTH     EBCAW_11
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 10)
+#define SDRAM_WIDTH     EBCAW_10
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 9)
+#define SDRAM_WIDTH     EBCAW_9
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 8)
+#define SDRAM_WIDTH     EBCAW_8
+#endif
+
+#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EBE)
+
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
+
+#if defined CONFIG_CLKIN_HALF
+#define CLKIN_HALF       1
+#else
+#define CLKIN_HALF       0
+#endif
+
+#if defined CONFIG_PLL_BYPASS
+#define PLL_BYPASS      1
+#else
+#define PLL_BYPASS       0
+#endif
+
+/***************************************Currently Not Being Used *********************************/
+#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
+#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0  \
+        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
+         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf537/mem_map.h b/include/asm-blackfin/mach-bf537/mem_map.h
new file mode 100644
index 000000000000..2a808c1202bf
--- /dev/null
+++ b/include/asm-blackfin/mach-bf537/mem_map.h
@@ -0,0 +1,175 @@
+/*
+ * file:         include/asm-blackfin/mach-bf537/mem_map.h
+ * based on:
+ * author:
+ *
+ * created:
+ * description:
+ *      Memory MAP Common header file for blackfin BF537/6/4 of processors.
+ * rev:
+ *
+ * modified:
+ *
+ * bugs:         enter bugs at http://blackfin.uclinux.org/
+ *
+ * this program is free software; you can redistribute it and/or modify
+ * it under the terms of the gnu general public license as published by
+ * the free software foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * this program is distributed in the hope that it will be useful,
+ * but without any warranty; without even the implied warranty of
+ * merchantability or fitness for a particular purpose.  see the
+ * gnu general public license for more details.
+ *
+ * you should have received a copy of the gnu general public license
+ * along with this program; see the file copying.
+ * if not, write to the free software foundation,
+ * 59 temple place - suite 330, boston, ma 02111-1307, usa.
+ */
+
+#ifndef _MEM_MAP_537_H_
+#define _MEM_MAP_537_H_
+
+#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
+#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0x20300000       /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK2_BASE        0x20200000       /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK1_BASE        0x20100000       /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x00100000      /* 1M */
+#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x00100000      /* 1M */
+
+/* Boot ROM Memory */
+
+#define BOOT_ROM_START          0xEF000000
+
+/* Level 1 Memory */
+
+/* Memory Map for ADSP-BF537 processors */
+
+#ifdef CONFIG_BLKFIN_CACHE
+#define BLKFIN_ICACHESIZE       (16*1024)
+#else
+#define BLKFIN_ICACHESIZE       (0*1024)
+#endif
+
+
+#ifdef CONFIG_BF537
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+
+#define L1_CODE_LENGTH      0xC000
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+
+#endif /*CONFIG_BF537*/
+
+/* Memory Map for ADSP-BF536 processors */
+
+#ifdef CONFIG_BF536
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF804000
+#define L1_DATA_B_START     0xFF904000
+
+#define L1_CODE_LENGTH      0xC000
+
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x4000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x4000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x4000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x4000
+#define L1_DATA_B_LENGTH      0x4000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+
+#endif
+
+/* Memory Map for ADSP-BF534 processors */
+
+#ifdef CONFIG_BF534
+#define L1_CODE_START       0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+
+#define L1_CODE_LENGTH      0xC000
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+
+#endif
+
+/* Scratch Pad Memory */
+
+#if defined(CONFIG_BF537) || defined(CONFIG_BF536) || defined(CONFIG_BF534)
+#define L1_SCRATCH_START        0xFFB00000
+#define L1_SCRATCH_LENGTH       0x1000
+#endif
+
+#endif                          /* _MEM_MAP_537_H_ */
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h
new file mode 100644
index 000000000000..f5b32d66517d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/anomaly.h
@@ -0,0 +1,184 @@
+
+/*
+ * File:         include/asm-blackfin/mach-bf561/anomaly.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+/* This file shoule be up to date with:
+ *  - Revision L, 10Aug2006; ADSP-BF561 Silicon Anomaly List
+ */
+
+#ifndef _MACH_ANOMALY_H_
+#define _MACH_ANOMALY_H_
+
+/* We do not support 0.1 or 0.4 silicon - sorry */
+#if (defined(CONFIG_BF_REV_0_1) || defined(CONFIG_BF_REV_0_2) || defined(CONFIG_BF_REV_0_4))
+#error Kernel will not work on BF561 Version 0.1, 0.2, or 0.4
+#endif
+
+/* Issues that are common to 0.5 and  0.3 silicon */
+#if  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000074 /* A multi issue instruction with dsp32shiftimm in
+                            slot1 and store of a P register in slot 2 is not
+                            supported */
+#define ANOMALY_05000099 /* UART Line Status Register (UART_LSR) bits are not
+                            updated at the same time. */
+#define ANOMALY_05000120 /* Testset instructions restricted to 32-bit aligned
+                            memory locations */
+#define ANOMALY_05000122 /* Rx.H cannot be used to access 16-bit System MMR
+                            registers */
+#define ANOMALY_05000127 /* Signbits instruction not functional under certain
+                            conditions */
+#define ANOMALY_05000149 /* IMDMA S1/D1 channel may stall */
+#define ANOMALY_05000166 /* PPI Data Lengths Between 8 and 16 do not zero out
+                            upper bits */
+#define ANOMALY_05000167 /* Turning Serial Ports on With External Frame Syncs */
+#define ANOMALY_05000180 /* PPI_DELAY not functional in PPI modes with 0 frame
+                            syncs */
+#define ANOMALY_05000182 /* IMDMA does not operate to full speed for 600MHz
+                            and higher devices */
+#define ANOMALY_05000187 /* IMDMA Corrupted Data after a Halt */
+#define ANOMALY_05000190 /* PPI not functional at core voltage < 1Volt */
+#define ANOMALY_05000208 /* VSTAT status bit in PLL_STAT register is not
+                            functional */
+#define ANOMALY_05000245 /* Spurious Hardware Error from an access in the
+                            shadow of a conditional branch */
+#define ANOMALY_05000257 /* Interrupt/Exception during short hardware loop
+                            may cause bad instruction fetches */
+#define ANOMALY_05000265 /* Sensitivity to noise with slow input edge rates on
+                            external SPORT TX and RX clocks */
+#define ANOMALY_05000267 /* IMDMA may corrupt data under certain conditions */
+#define ANOMALY_05000269 /* High I/O activity causes output voltage of internal
+                            voltage regulator (VDDint) to increase */
+#define ANOMALY_05000270 /* High I/O activity causes output voltage of internal
+                            voltage regulator (VDDint) to decrease */
+#define ANOMALY_05000272 /* Certain data cache write through modes fail for
+                            VDDint <=0.9V */
+#define ANOMALY_05000274 /* Data cache write back to external synchronous memory
+                            may be lost */
+#define ANOMALY_05000275 /* PPI Timing and sampling informaton updates */
+#define ANOMALY_05000312 /* Errors when SSYNC, CSYNC, or loads to LT, LB and LC
+                            registers are interrupted */
+
+#endif /*  (defined(CONFIG_BF_REV_0_5) || defined(CONFIG_BF_REV_0_3)) */
+
+#if  (defined(CONFIG_BF_REV_0_5))
+#define ANOMALY_05000254 /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT
+                            mode with external clock */
+#define ANOMALY_05000266 /* IMDMA destination IRQ status must be read prior to
+                            using IMDMA */
+#endif
+
+#if  (defined(CONFIG_BF_REV_0_3))
+#define ANOMALY_05000156 /* Timers in PWM-Out Mode with PPI GP Receive (Input)
+                            Mode with 0 Frame Syncs */
+#define ANOMALY_05000168 /* SDRAM auto-refresh and subsequent Power Ups */
+#define ANOMALY_05000169 /* DATA CPLB page miss can result in lost write-through
+                            cache data writes */
+#define ANOMALY_05000171 /* Boot-ROM code modifies SICA_IWRx wakeup registers */
+#define ANOMALY_05000174 /* Cache Fill Buffer Data lost */
+#define ANOMALY_05000175 /* Overlapping Sequencer and Memory Stalls */
+#define ANOMALY_05000176 /* Multiplication of (-1) by (-1) followed by an
+                            accumulator saturation */
+#define ANOMALY_05000179 /* PPI_COUNT cannot be programmed to 0 in General
+                            Purpose TX or RX modes */
+#define ANOMALY_05000181 /* Disabling the PPI resets the PPI configuration
+                            registers */
+#define ANOMALY_05000184 /* Timer Pin limitations for PPI TX Modes with
+                            External Frame Syncs */
+#define ANOMALY_05000185 /* PPI TX Mode with 2 External Frame Syncs */
+#define ANOMALY_05000186 /* PPI packing with Data Length greater than 8 bits
+                            (not a meaningful mode) */
+#define ANOMALY_05000188 /* IMDMA Restrictions on Descriptor and Buffer
+                            Placement in Memory */
+#define ANOMALY_05000189 /* False Protection Exception */
+#define ANOMALY_05000193 /* False Flag Pin Interrupts on Edge Sensitive Inputs
+                            when polarity setting is changed */
+#define ANOMALY_05000194 /* Restarting SPORT in specific modes may cause data
+                            corruption */
+#define ANOMALY_05000198 /* Failing MMR accesses when stalled by preceding
+                            memory read */
+#define ANOMALY_05000199 /* DMA current address shows wrong value during carry
+                            fix */
+#define ANOMALY_05000200 /* SPORT TFS and DT are incorrectly driven during
+                            inactive channels in certain conditions */
+#define ANOMALY_05000202 /* Possible infinite stall with specific dual-DAG
+                            situation */
+#define ANOMALY_05000204 /* Incorrect data read with write-through cache and
+                            allocate cache lines on reads only mode */
+#define ANOMALY_05000205 /* Specific sequence that can cause DMA error or DMA
+                            stopping */
+#define ANOMALY_05000207 /* Recovery from "brown-out" condition */
+#define ANOMALY_05000209 /* Speed-Path in computational unit affects certain
+                            instructions */
+#define ANOMALY_05000215 /* UART TX Interrupt masked erroneously */
+#define ANOMALY_05000219 /* NMI event at boot time results in unpredictable
+                            state */
+#define ANOMALY_05000220 /* Data Corruption with Cached External Memory and
+                            Non-Cached On-Chip L2 Memory */
+#define ANOMALY_05000225 /* Incorrect pulse-width of UART start-bit */
+#define ANOMALY_05000227 /* Scratchpad memory bank reads may return incorrect
+                            data */
+#define ANOMALY_05000230 /* UART Receiver is less robust against Baudrate
+                            Differences in certain Conditions */
+#define ANOMALY_05000231 /* UART STB bit incorrectly affects receiver setting */
+#define ANOMALY_05000232 /* SPORT data transmit lines are incorrectly driven in
+                            multichannel mode */
+#define ANOMALY_05000242 /* DF bit in PLL_CTL register does not respond to
+                            hardware reset */
+#define ANOMALY_05000244 /* If i-cache is on, CSYNC/SSYNC/IDLE around Change of
+                            Control causes failures */
+#define ANOMALY_05000248 /* TESTSET operation forces stall on the other core */
+#define ANOMALY_05000250 /* Incorrect Bit-Shift of Data Word in Multichannel
+                            (TDM) mode in certain conditions */
+#define ANOMALY_05000251 /* Exception not generated for MMR accesses in
+                            reserved region */
+#define ANOMALY_05000253 /* Maximum external clock speed for Timers */
+#define ANOMALY_05000258 /* Instruction Cache is corrupted when bits 9 and 12
+                            of the ICPLB Data registers differ */
+#define ANOMALY_05000260 /* ICPLB_STATUS MMR register may be corrupted */
+#define ANOMALY_05000261 /* DCPLB_FAULT_ADDR MMR register may be corrupted */
+#define ANOMALY_05000262 /* Stores to data cache may be lost */
+#define ANOMALY_05000263 /* Hardware loop corrupted when taking an ICPLB
+                            exception */
+#define ANOMALY_05000264 /* CSYNC/SSYNC/IDLE causes infinite stall in second
+                            to last instruction in hardware loop */
+#define ANOMALY_05000276 /* Timing requirements change for External Frame
+                            Sync PPI Modes with non-zero PPI_DELAY */
+#define ANOMALY_05000278 /* Disabling Peripherals with DMA running may cause
+                            DMA system instability */
+#define ANOMALY_05000281 /* False Hardware Error Exception when ISR context is
+                            not restored */
+#define ANOMALY_05000283 /* An MMR write is stalled indefinitely when killed
+                            in a particular stage */
+#define ANOMALY_05000287 /* A read will receive incorrect data under certain
+                            conditions */
+#define ANOMALY_05000288 /* SPORTs may receive bad data if FIFOs fill up */
+#endif
+
+#endif /* _MACH_ANOMALY_H_ */
diff --git a/include/asm-blackfin/mach-bf561/bf561.h b/include/asm-blackfin/mach-bf561/bf561.h
new file mode 100644
index 000000000000..96a5d3a47e45
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bf561.h
@@ -0,0 +1,408 @@
+/*
+ * File:         include/asm-blackfin/mach-bf561/bf561.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __MACH_BF561_H__
+#define __MACH_BF561_H__
+
+#define SUPPORTED_REVID         0x3
+
+#define OFFSET_(x) ((x) & 0x0000FFFF)
+#define L1_ISRAM                0xFFA00000
+#define L1_ISRAM_END            0xFFA04000
+#define DATA_BANKA_SRAM         0xFF800000
+#define DATA_BANKA_SRAM_END     0xFF804000
+#define DATA_BANKB_SRAM         0xFF900000
+#define DATA_BANKB_SRAM_END     0xFF904000
+#define L1_DSRAMA               0xFF800000
+#define L1_DSRAMA_END           0xFF804000
+#define L1_DSRAMB               0xFF900000
+#define L1_DSRAMB_END           0xFF904000
+#define L2_SRAM                 0xFEB00000
+#define L2_SRAM_END             0xFEB20000
+#define AMB_FLASH               0x20000000
+#define AMB_FLASH_END           0x21000000
+#define AMB_FLASH_LENGTH        0x01000000
+#define L1_ISRAM_LENGTH         0x4000
+#define L1_DSRAMA_LENGTH        0x4000
+#define L1_DSRAMB_LENGTH        0x4000
+#define L2_SRAM_LENGTH          0x20000
+
+/*some misc defines*/
+#define IMASK_IVG15             0x8000
+#define IMASK_IVG14             0x4000
+#define IMASK_IVG13             0x2000
+#define IMASK_IVG12             0x1000
+
+#define IMASK_IVG11             0x0800
+#define IMASK_IVG10             0x0400
+#define IMASK_IVG9              0x0200
+#define IMASK_IVG8              0x0100
+
+#define IMASK_IVG7              0x0080
+#define IMASK_IVGTMR            0x0040
+#define IMASK_IVGHW             0x0020
+
+/***************************
+ * Blackfin Cache setup
+ */
+
+
+#define BLKFIN_ISUBBANKS        4
+#define BLKFIN_IWAYS            4
+#define BLKFIN_ILINES           32
+
+#define BLKFIN_DSUBBANKS        4
+#define BLKFIN_DWAYS            2
+#define BLKFIN_DLINES           64
+
+#define WAY0_L                  0x1
+#define WAY1_L                  0x2
+#define WAY01_L                 0x3
+#define WAY2_L                  0x4
+#define WAY02_L                 0x5
+#define WAY12_L                 0x6
+#define WAY012_L                0x7
+
+#define WAY3_L                  0x8
+#define WAY03_L                 0x9
+#define WAY13_L                 0xA
+#define WAY013_L                0xB
+
+#define WAY32_L                 0xC
+#define WAY320_L                0xD
+#define WAY321_L                0xE
+#define WAYALL_L                0xF
+
+#define DMC_ENABLE (2<<2)       /*yes, 2, not 1 */
+
+/* IAR0 BIT FIELDS */
+#define PLL_WAKEUP_BIT          0xFFFFFFFF
+#define DMA1_ERROR_BIT          0xFFFFFF0F
+#define DMA2_ERROR_BIT          0xFFFFF0FF
+#define IMDMA_ERROR_BIT         0xFFFF0FFF
+#define PPI1_ERROR_BIT          0xFFF0FFFF
+#define PPI2_ERROR_BIT          0xFF0FFFFF
+#define SPORT0_ERROR_BIT        0xF0FFFFFF
+#define SPORT1_ERROR_BIT        0x0FFFFFFF
+/* IAR1 BIT FIELDS */
+#define SPI_ERROR_BIT           0xFFFFFFFF
+#define UART_ERROR_BIT          0xFFFFFF0F
+#define RESERVED_ERROR_BIT      0xFFFFF0FF
+#define DMA1_0_BIT              0xFFFF0FFF
+#define DMA1_1_BIT              0xFFF0FFFF
+#define DMA1_2_BIT              0xFF0FFFFF
+#define DMA1_3_BIT              0xF0FFFFFF
+#define DMA1_4_BIT              0x0FFFFFFF
+/* IAR2 BIT FIELDS */
+#define DMA1_5_BIT              0xFFFFFFFF
+#define DMA1_6_BIT              0xFFFFFF0F
+#define DMA1_7_BIT              0xFFFFF0FF
+#define DMA1_8_BIT              0xFFFF0FFF
+#define DMA1_9_BIT              0xFFF0FFFF
+#define DMA1_10_BIT             0xFF0FFFFF
+#define DMA1_11_BIT             0xF0FFFFFF
+#define DMA2_0_BIT              0x0FFFFFFF
+/* IAR3 BIT FIELDS */
+#define DMA2_1_BIT              0xFFFFFFFF
+#define DMA2_2_BIT              0xFFFFFF0F
+#define DMA2_3_BIT              0xFFFFF0FF
+#define DMA2_4_BIT              0xFFFF0FFF
+#define DMA2_5_BIT              0xFFF0FFFF
+#define DMA2_6_BIT              0xFF0FFFFF
+#define DMA2_7_BIT              0xF0FFFFFF
+#define DMA2_8_BIT              0x0FFFFFFF
+/* IAR4 BIT FIELDS */
+#define DMA2_9_BIT              0xFFFFFFFF
+#define DMA2_10_BIT             0xFFFFFF0F
+#define DMA2_11_BIT             0xFFFFF0FF
+#define TIMER0_BIT              0xFFFF0FFF
+#define TIMER1_BIT              0xFFF0FFFF
+#define TIMER2_BIT              0xFF0FFFFF
+#define TIMER3_BIT              0xF0FFFFFF
+#define TIMER4_BIT              0x0FFFFFFF
+/* IAR5 BIT FIELDS */
+#define TIMER5_BIT              0xFFFFFFFF
+#define TIMER6_BIT              0xFFFFFF0F
+#define TIMER7_BIT              0xFFFFF0FF
+#define TIMER8_BIT              0xFFFF0FFF
+#define TIMER9_BIT              0xFFF0FFFF
+#define TIMER10_BIT             0xFF0FFFFF
+#define TIMER11_BIT             0xF0FFFFFF
+#define PROG0_INTA_BIT          0x0FFFFFFF
+/* IAR6 BIT FIELDS */
+#define PROG0_INTB_BIT          0xFFFFFFFF
+#define PROG1_INTA_BIT          0xFFFFFF0F
+#define PROG1_INTB_BIT          0xFFFFF0FF
+#define PROG2_INTA_BIT          0xFFFF0FFF
+#define PROG2_INTB_BIT          0xFFF0FFFF
+#define DMA1_WRRD0_BIT          0xFF0FFFFF
+#define DMA1_WRRD1_BIT          0xF0FFFFFF
+#define DMA2_WRRD0_BIT          0x0FFFFFFF
+/* IAR7 BIT FIELDS */
+#define DMA2_WRRD1_BIT          0xFFFFFFFF
+#define IMDMA_WRRD0_BIT         0xFFFFFF0F
+#define IMDMA_WRRD1_BIT         0xFFFFF0FF
+#define WATCH_BIT               0xFFFF0FFF
+#define RESERVED_1_BIT          0xFFF0FFFF
+#define RESERVED_2_BIT          0xFF0FFFFF
+#define SUPPLE_0_BIT            0xF0FFFFFF
+#define SUPPLE_1_BIT            0x0FFFFFFF
+
+/* Miscellaneous Values */
+
+/****************************** EBIU Settings ********************************/
+#define AMBCTL0VAL      ((CONFIG_BANK_1 << 16) | CONFIG_BANK_0)
+#define AMBCTL1VAL      ((CONFIG_BANK_3 << 16) | CONFIG_BANK_2)
+
+#if defined(CONFIG_C_AMBEN_ALL)
+#define V_AMBEN AMBEN_ALL
+#elif defined(CONFIG_C_AMBEN)
+#define V_AMBEN 0x0
+#elif defined(CONFIG_C_AMBEN_B0)
+#define V_AMBEN AMBEN_B0
+#elif defined(CONFIG_C_AMBEN_B0_B1)
+#define V_AMBEN AMBEN_B0_B1
+#elif defined(CONFIG_C_AMBEN_B0_B1_B2)
+#define V_AMBEN AMBEN_B0_B1_B2
+#endif
+
+#ifdef CONFIG_C_AMCKEN
+#define V_AMCKEN AMCKEN
+#else
+#define V_AMCKEN 0x0
+#endif
+
+#ifdef CONFIG_C_B0PEN
+#define V_B0PEN 0x10
+#else
+#define V_B0PEN 0x00
+#endif
+
+#ifdef CONFIG_C_B1PEN
+#define V_B1PEN 0x20
+#else
+#define V_B1PEN 0x00
+#endif
+
+#ifdef CONFIG_C_B2PEN
+#define V_B2PEN 0x40
+#else
+#define V_B2PEN 0x00
+#endif
+
+#ifdef CONFIG_C_B3PEN
+#define V_B3PEN 0x80
+#else
+#define V_B3PEN 0x00
+#endif
+
+#ifdef CONFIG_C_CDPRIO
+#define V_CDPRIO 0x100
+#else
+#define V_CDPRIO 0x0
+#endif
+
+#define AMGCTLVAL       (V_AMBEN | V_AMCKEN | V_CDPRIO | V_B0PEN | V_B1PEN | V_B2PEN | V_B3PEN | 0x0002)
+
+#define MAX_VC  600000000
+#define MIN_VC  50000000
+
+/******************************* PLL Settings ********************************/
+#ifdef CONFIG_BFIN_KERNEL_CLOCK
+#if (CONFIG_VCO_MULT < 0)
+#error "VCO Multiplier is less than 0. Please select a different value"
+#endif
+
+#if (CONFIG_VCO_MULT == 0)
+#error "VCO Multiplier should be greater than 0. Please select a different value"
+#endif
+
+#ifndef CONFIG_CLKIN_HALF
+#define CONFIG_VCO_HZ   (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
+#else
+#define CONFIG_VCO_HZ   ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)/2)
+#endif
+
+#ifndef CONFIG_PLL_BYPASS
+#define CONFIG_CCLK_HZ  (CONFIG_VCO_HZ/CONFIG_CCLK_DIV)
+#define CONFIG_SCLK_HZ  (CONFIG_VCO_HZ/CONFIG_SCLK_DIV)
+#else
+#define CONFIG_CCLK_HZ  CONFIG_CLKIN_HZ
+#define CONFIG_SCLK_HZ  CONFIG_CLKIN_HZ
+#endif
+
+#if (CONFIG_SCLK_DIV < 1)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_SCLK_DIV > 15)
+#error "SCLK DIV cannot be less than 1 or more than 15. Please select a proper value"
+#endif
+
+#if (CONFIG_CCLK_DIV != 1)
+#if (CONFIG_CCLK_DIV != 2)
+#if (CONFIG_CCLK_DIV != 4)
+#if (CONFIG_CCLK_DIV != 8)
+#error "CCLK DIV can be 1,2,4 or 8 only. Please select a proper value"
+#endif
+#endif
+#endif
+#endif
+
+#if (CONFIG_VCO_HZ > MAX_VC)
+#error "VCO selected is more than maximum value. Please change the VCO multipler"
+#endif
+
+#if (CONFIG_SCLK_HZ > 133000000)
+#error "Sclk value selected is more than maximum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ < 27000000)
+#error "Sclk value selected is less than minimum. Please select a proper value for SCLK multiplier"
+#endif
+
+#if (CONFIG_SCLK_HZ >= CONFIG_CCLK_HZ)
+#if (CONFIG_SCLK_HZ != CONFIG_CLKIN_HZ)
+#if (CONFIG_CCLK_HZ != CONFIG_CLKIN_HZ)
+#error "Please select sclk less than cclk"
+#endif
+#endif
+#endif
+
+#if (CONFIG_CCLK_DIV == 1)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV1
+#endif
+#if (CONFIG_CCLK_DIV == 2)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV2
+#endif
+#if (CONFIG_CCLK_DIV == 4)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV4
+#endif
+#if (CONFIG_CCLK_DIV == 8)
+#define CONFIG_CCLK_ACT_DIV   CCLK_DIV8
+#endif
+#ifndef CONFIG_CCLK_ACT_DIV
+#define CONFIG_CCLK_ACT_DIV   CONFIG_CCLK_DIV_not_defined_properly
+#endif
+
+#if defined(ANOMALY_05000273) && (CONFIG_CCLK_DIV == 1)
+#error ANOMALY 05000273, please make sure CCLK is at least 2x SCLK
+#endif
+
+#endif                          /* CONFIG_BFIN_KERNEL_CLOCK */
+
+#ifdef CONFIG_BF561
+#define CPU "BF561"
+#define CPUID 0x027bb000
+#endif
+#ifndef CPU
+#define CPU "UNKNOWN"
+#define CPUID 0x0
+#endif
+
+#if (CONFIG_MEM_SIZE % 4)
+#error "SDRAM memory size must be a multiple of 4MB!"
+#endif
+#define SDRAM_IGENERIC    (CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_PORTPRIO)
+#define SDRAM_IKERNEL     (SDRAM_IGENERIC | CPLB_LOCK)
+#define L1_IMEMORY        (               CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
+#define SDRAM_INON_CHBL   (               CPLB_USER_RD | CPLB_VALID)
+
+/*Use the menuconfig cache policy here - CONFIG_BLKFIN_WT/CONFIG_BLKFIN_WB*/
+
+#define ANOMALY_05000158_WORKAROUND             0x200
+#ifdef CONFIG_BLKFIN_WB         /*Write Back Policy */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_DIRTY \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#else                           /*Write Through */
+#define SDRAM_DGENERIC   (CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_DIRTY \
+                        | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
+#endif
+
+
+#define L1_DMEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
+#define SDRAM_DNON_CHBL  (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
+#define SDRAM_EBIU       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
+#define SDRAM_OOPS       (CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_LOCK | CPLB_DIRTY)
+
+#define L2_MEMORY       (CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND | CPLB_DIRTY)
+
+#define SIZE_1K 0x00000400      /* 1K */
+#define SIZE_4K 0x00001000      /* 4K */
+#define SIZE_1M 0x00100000      /* 1M */
+#define SIZE_4M 0x00400000      /* 4M */
+
+#define MAX_CPLBS (16 * 2)
+
+/*
+* Number of required data CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 16 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Data Memory
+* 1 for L2 Data Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+* 64 for ASYNC Memory
+*/
+
+
+#define MAX_SWITCH_D_CPLBS (((CONFIG_MEM_SIZE / 4) + 16 + 1 + 1 + 1 + 64) * 2)
+
+/*
+* Number of required instruction CPLB switchtable entries
+* MEMSIZE / 4 (we mostly install 4M page size CPLBs
+* approx 12 for smaller 1MB page size CPLBs for allignment purposes
+* 1 for L1 Instruction Memory
+* 1 for L2 Instruction Memory
+* 1 for CONFIG_DEBUG_HUNT_FOR_ZERO
+*/
+
+#define MAX_SWITCH_I_CPLBS (((CONFIG_MEM_SIZE / 4) + 12 + 1 + 1 + 1) * 2)
+
+#if 0                           /* comment by mhfan */
+/* Event Vector Table Address */
+#define EVT_EMULATION_ADDR      0xffe02000
+#define EVT_RESET_ADDR          0xffe02004
+#define EVT_NMI_ADDR            0xffe02008
+#define EVT_EXCEPTION_ADDR      0xffe0200c
+#define EVT_GLOBAL_INT_ENB_ADDR 0xffe02010
+#define EVT_HARDWARE_ERROR_ADDR 0xffe02014
+#define EVT_TIMER_ADDR          0xffe02018
+#define EVT_IVG7_ADDR           0xffe0201c
+#define EVT_IVG8_ADDR           0xffe02020
+#define EVT_IVG9_ADDR           0xffe02024
+#define EVT_IVG10_ADDR          0xffe02028
+#define EVT_IVG11_ADDR          0xffe0202c
+#define EVT_IVG12_ADDR          0xffe02030
+#define EVT_IVG13_ADDR          0xffe02034
+#define EVT_IVG14_ADDR          0xffe02038
+#define EVT_IVG15_ADDR          0xffe0203c
+#define EVT_OVERRIDE_ADDR       0xffe02100
+#endif                          /* comment by mhfan */
+
+#endif                          /* __MACH_BF561_H__  */
diff --git a/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
new file mode 100644
index 000000000000..23bf76aa3451
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/bfin_serial_5xx.h
@@ -0,0 +1,108 @@
+#include <linux/serial.h>
+#include <asm/dma.h>
+
+#define NR_PORTS                1
+
+#define OFFSET_THR              0x00    /* Transmit Holding register            */
+#define OFFSET_RBR              0x00    /* Receive Buffer register              */
+#define OFFSET_DLL              0x00    /* Divisor Latch (Low-Byte)             */
+#define OFFSET_IER              0x04    /* Interrupt Enable Register            */
+#define OFFSET_DLH              0x04    /* Divisor Latch (High-Byte)            */
+#define OFFSET_IIR              0x08    /* Interrupt Identification Register    */
+#define OFFSET_LCR              0x0C    /* Line Control Register                */
+#define OFFSET_MCR              0x10    /* Modem Control Register               */
+#define OFFSET_LSR              0x14    /* Line Status Register                 */
+#define OFFSET_MSR              0x18    /* Modem Status Register                */
+#define OFFSET_SCR              0x1C    /* SCR Scratch Register                 */
+#define OFFSET_GCTL             0x24    /* Global Control Register              */
+
+#define UART_GET_CHAR(uart)     bfin_read16(((uart)->port.membase + OFFSET_RBR))
+#define UART_GET_DLL(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLL))
+#define UART_GET_IER(uart)      bfin_read16(((uart)->port.membase + OFFSET_IER))
+#define UART_GET_DLH(uart)      bfin_read16(((uart)->port.membase + OFFSET_DLH))
+#define UART_GET_IIR(uart)      bfin_read16(((uart)->port.membase + OFFSET_IIR))
+#define UART_GET_LCR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LCR))
+#define UART_GET_LSR(uart)      bfin_read16(((uart)->port.membase + OFFSET_LSR))
+#define UART_GET_GCTL(uart)     bfin_read16(((uart)->port.membase + OFFSET_GCTL))
+
+#define UART_PUT_CHAR(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_THR),v)
+#define UART_PUT_DLL(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLL),v)
+#define UART_PUT_IER(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_IER),v)
+#define UART_PUT_DLH(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_DLH),v)
+#define UART_PUT_LCR(uart,v)    bfin_write16(((uart)->port.membase + OFFSET_LCR),v)
+#define UART_PUT_GCTL(uart,v)   bfin_write16(((uart)->port.membase + OFFSET_GCTL),v)
+
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+# define CONFIG_SERIAL_BFIN_CTSRTS
+# ifndef CONFIG_UART0_CTS_PIN
+#  define CONFIG_UART0_CTS_PIN -1
+# endif
+# ifndef CONFIG_UART0_RTS_PIN
+#  define CONFIG_UART0_RTS_PIN -1
+# endif
+#endif
+
+struct bfin_serial_port {
+        struct uart_port        port;
+        unsigned int            old_status;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        int                     tx_done;
+        int                     tx_count;
+        struct circ_buf         rx_dma_buf;
+        struct timer_list       rx_dma_timer;
+        int                     rx_dma_nrows;
+        unsigned int            tx_dma_channel;
+        unsigned int            rx_dma_channel;
+        struct work_struct      tx_dma_workqueue;
+#else
+        struct work_struct      cts_workqueue;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int                     cts_pin;
+        int                     rts_pin;
+#endif
+};
+
+struct bfin_serial_port bfin_serial_ports[NR_PORTS];
+struct bfin_serial_res {
+        unsigned long   uart_base_addr;
+        int             uart_irq;
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        unsigned int    uart_tx_dma_channel;
+        unsigned int    uart_rx_dma_channel;
+#endif
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        int             uart_cts_pin;
+        int             uart_rts_pin;
+#endif
+};
+
+struct bfin_serial_res bfin_serial_resource[] = {
+        0xFFC00400,
+        IRQ_UART_RX,
+#ifdef CONFIG_SERIAL_BFIN_DMA
+        CH_UART_TX,
+        CH_UART_RX,
+#endif
+#ifdef CONFIG_BFIN_UART0_CTSRTS
+        CONFIG_UART0_CTS_PIN,
+        CONFIG_UART0_RTS_PIN,
+#endif
+};
+
+
+int nr_ports = NR_PORTS;
+static void bfin_serial_hw_init(struct bfin_serial_port *uart)
+{
+
+#ifdef CONFIG_SERIAL_BFIN_CTSRTS
+        if (uart->cts_pin >= 0) {
+                gpio_request(uart->cts_pin, NULL);
+                gpio_direction_input(uart->cts_pin);
+        }
+        if (uart->rts_pin >= 0) {
+                gpio_request(uart->rts_pin, NULL);
+                gpio_direction_input(uart->rts_pin);
+        }
+#endif
+}
diff --git a/include/asm-blackfin/mach-bf561/blackfin.h b/include/asm-blackfin/mach-bf561/blackfin.h
new file mode 100644
index 000000000000..2537c845e8b0
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/blackfin.h
@@ -0,0 +1,52 @@
+/*
+ * File:         include/asm-blackfin/mach-bf561/blackfin.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _MACH_BLACKFIN_H_
+#define _MACH_BLACKFIN_H_
+
+#define BF561_FAMILY
+
+#include "bf561.h"
+#include "mem_map.h"
+#include "defBF561.h"
+#include "anomaly.h"
+
+#if !(defined(__ASSEMBLY__) || defined(ASSEMBLY))
+#include "cdefBF561.h"
+#endif
+
+#define bfin_read_FIO_FLAG_D() bfin_read_FIO0_FLAG_D()
+#define bfin_write_FIO_FLAG_D(val) bfin_write_FIO0_FLAG_D(val)
+#define bfin_read_FIO_DIR() bfin_read_FIO0_DIR()
+#define bfin_write_FIO_DIR(val) bfin_write_FIO0_DIR(val)
+#define bfin_read_FIO_INEN() bfin_read_FIO0_INEN()
+#define bfin_write_FIO_INEN(val) bfin_write_FIO0_INEN(val)
+
+#endif                          /* _MACH_BLACKFIN_H_ */
diff --git a/include/asm-blackfin/mach-bf561/cdefBF561.h b/include/asm-blackfin/mach-bf561/cdefBF561.h
new file mode 100644
index 000000000000..5dc0ed835447
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/cdefBF561.h
@@ -0,0 +1,1543 @@
+/*
+ * File:         include/asm-blackfin/mach-bf561/cdefBF561.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:  C POINTERS TO SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _CDEF_BF561_H
+#define _CDEF_BF561_H
+
+/*
+#if !defined(__ADSPBF561__)
+#warning cdefBF561.h should only be included for BF561 chip.
+#endif
+*/
+/* include all Core registers and bit definitions */
+#include "defBF561.h"
+
+/*include core specific register pointer definitions*/
+#include <asm/mach-common/cdef_LPBlackfin.h>
+
+#include <asm/system.h>
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+#define bfin_read_PLL_CTL()                  bfin_read16(PLL_CTL)
+#define bfin_write_PLL_CTL(val)              bfin_write16(PLL_CTL,val)
+#define bfin_read_PLL_DIV()                  bfin_read16(PLL_DIV)
+#define bfin_write_PLL_DIV(val)              bfin_write16(PLL_DIV,val)
+#define bfin_read_VR_CTL()                   bfin_read16(VR_CTL)
+/* Writing to VR_CTL initiates a PLL relock sequence. */
+static __inline__ void bfin_write_VR_CTL(unsigned int val)
+{
+        unsigned long flags, iwr;
+
+        bfin_write16(VR_CTL, val);
+        __builtin_bfin_ssync();
+        /* Enable the PLL Wakeup bit in SIC IWR */
+        iwr = bfin_read32(SICA_IWR0);
+        /* Only allow PPL Wakeup) */
+        bfin_write32(SICA_IWR0, IWR_ENABLE(0));
+        local_irq_save(flags);
+        asm("IDLE;");
+        local_irq_restore(flags);
+        bfin_write32(SICA_IWR0, iwr);
+}
+#define bfin_read_PLL_STAT()                 bfin_read16(PLL_STAT)
+#define bfin_write_PLL_STAT(val)             bfin_write16(PLL_STAT,val)
+#define bfin_read_PLL_LOCKCNT()              bfin_read16(PLL_LOCKCNT)
+#define bfin_write_PLL_LOCKCNT(val)          bfin_write16(PLL_LOCKCNT,val)
+#define bfin_read_CHIPID()                   bfin_read32(CHIPID)
+
+/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
+#define bfin_read_SICA_SWRST()               bfin_read16(SICA_SWRST)
+#define bfin_write_SICA_SWRST(val)           bfin_write16(SICA_SWRST,val)
+#define bfin_read_SICA_SYSCR()               bfin_read16(SICA_SYSCR)
+#define bfin_write_SICA_SYSCR(val)           bfin_write16(SICA_SYSCR,val)
+#define bfin_read_SICA_RVECT()               bfin_read16(SICA_RVECT)
+#define bfin_write_SICA_RVECT(val)           bfin_write16(SICA_RVECT,val)
+#define bfin_read_SICA_IMASK()               bfin_read32(SICA_IMASK)
+#define bfin_write_SICA_IMASK(val)           bfin_write32(SICA_IMASK,val)
+#define bfin_read_SICA_IMASK0()              bfin_read32(SICA_IMASK0)
+#define bfin_write_SICA_IMASK0(val)          bfin_write32(SICA_IMASK0,val)
+#define bfin_read_SICA_IMASK1()              bfin_read32(SICA_IMASK1)
+#define bfin_write_SICA_IMASK1(val)          bfin_write32(SICA_IMASK1,val)
+#define bfin_read_SICA_IAR0()                bfin_read32(SICA_IAR0)
+#define bfin_write_SICA_IAR0(val)            bfin_write32(SICA_IAR0,val)
+#define bfin_read_SICA_IAR1()                bfin_read32(SICA_IAR1)
+#define bfin_write_SICA_IAR1(val)            bfin_write32(SICA_IAR1,val)
+#define bfin_read_SICA_IAR2()                bfin_read32(SICA_IAR2)
+#define bfin_write_SICA_IAR2(val)            bfin_write32(SICA_IAR2,val)
+#define bfin_read_SICA_IAR3()                bfin_read32(SICA_IAR3)
+#define bfin_write_SICA_IAR3(val)            bfin_write32(SICA_IAR3,val)
+#define bfin_read_SICA_IAR4()                bfin_read32(SICA_IAR4)
+#define bfin_write_SICA_IAR4(val)            bfin_write32(SICA_IAR4,val)
+#define bfin_read_SICA_IAR5()                bfin_read32(SICA_IAR5)
+#define bfin_write_SICA_IAR5(val)            bfin_write32(SICA_IAR5,val)
+#define bfin_read_SICA_IAR6()                bfin_read32(SICA_IAR6)
+#define bfin_write_SICA_IAR6(val)            bfin_write32(SICA_IAR6,val)
+#define bfin_read_SICA_IAR7()                bfin_read32(SICA_IAR7)
+#define bfin_write_SICA_IAR7(val)            bfin_write32(SICA_IAR7,val)
+#define bfin_read_SICA_ISR0()                bfin_read32(SICA_ISR0)
+#define bfin_write_SICA_ISR0(val)            bfin_write32(SICA_ISR0,val)
+#define bfin_read_SICA_ISR1()                bfin_read32(SICA_ISR1)
+#define bfin_write_SICA_ISR1(val)            bfin_write32(SICA_ISR1,val)
+#define bfin_read_SICA_IWR0()                bfin_read32(SICA_IWR0)
+#define bfin_write_SICA_IWR0(val)            bfin_write32(SICA_IWR0,val)
+#define bfin_read_SICA_IWR1()                bfin_read32(SICA_IWR1)
+#define bfin_write_SICA_IWR1(val)            bfin_write32(SICA_IWR1,val)
+
+/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
+#define bfin_read_SICB_SWRST()               bfin_read16(SICB_SWRST)
+#define bfin_write_SICB_SWRST(val)           bfin_write16(SICB_SWRST,val)
+#define bfin_read_SICB_SYSCR()               bfin_read16(SICB_SYSCR)
+#define bfin_write_SICB_SYSCR(val)           bfin_write16(SICB_SYSCR,val)
+#define bfin_read_SICB_RVECT()               bfin_read16(SICB_RVECT)
+#define bfin_write_SICB_RVECT(val)           bfin_write16(SICB_RVECT,val)
+#define bfin_read_SICB_IMASK0()              bfin_read32(SICB_IMASK0)
+#define bfin_write_SICB_IMASK0(val)          bfin_write32(SICB_IMASK0,val)
+#define bfin_read_SICB_IMASK1()              bfin_read32(SICB_IMASK1)
+#define bfin_write_SICB_IMASK1(val)          bfin_write32(SICB_IMASK1,val)
+#define bfin_read_SICB_IAR0()                bfin_read32(SICB_IAR0)
+#define bfin_write_SICB_IAR0(val)            bfin_write32(SICB_IAR0,val)
+#define bfin_read_SICB_IAR1()                bfin_read32(SICB_IAR1)
+#define bfin_write_SICB_IAR1(val)            bfin_write32(SICB_IAR1,val)
+#define bfin_read_SICB_IAR2()                bfin_read32(SICB_IAR2)
+#define bfin_write_SICB_IAR2(val)            bfin_write32(SICB_IAR2,val)
+#define bfin_read_SICB_IAR3()                bfin_read32(SICB_IAR3)
+#define bfin_write_SICB_IAR3(val)            bfin_write32(SICB_IAR3,val)
+#define bfin_read_SICB_IAR4()                bfin_read32(SICB_IAR4)
+#define bfin_write_SICB_IAR4(val)            bfin_write32(SICB_IAR4,val)
+#define bfin_read_SICB_IAR5()                bfin_read32(SICB_IAR5)
+#define bfin_write_SICB_IAR5(val)            bfin_write32(SICB_IAR5,val)
+#define bfin_read_SICB_IAR6()                bfin_read32(SICB_IAR6)
+#define bfin_write_SICB_IAR6(val)            bfin_write32(SICB_IAR6,val)
+#define bfin_read_SICB_IAR7()                bfin_read32(SICB_IAR7)
+#define bfin_write_SICB_IAR7(val)            bfin_write32(SICB_IAR7,val)
+#define bfin_read_SICB_ISR0()                bfin_read32(SICB_ISR0)
+#define bfin_write_SICB_ISR0(val)            bfin_write32(SICB_ISR0,val)
+#define bfin_read_SICB_ISR1()                bfin_read32(SICB_ISR1)
+#define bfin_write_SICB_ISR1(val)            bfin_write32(SICB_ISR1,val)
+#define bfin_read_SICB_IWR0()                bfin_read32(SICB_IWR0)
+#define bfin_write_SICB_IWR0(val)            bfin_write32(SICB_IWR0,val)
+#define bfin_read_SICB_IWR1()                bfin_read32(SICB_IWR1)
+#define bfin_write_SICB_IWR1(val)            bfin_write32(SICB_IWR1,val)
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define bfin_read_WDOGA_CTL()                bfin_read16(WDOGA_CTL)
+#define bfin_write_WDOGA_CTL(val)            bfin_write16(WDOGA_CTL,val)
+#define bfin_read_WDOGA_CNT()                bfin_read32(WDOGA_CNT)
+#define bfin_write_WDOGA_CNT(val)            bfin_write32(WDOGA_CNT,val)
+#define bfin_read_WDOGA_STAT()               bfin_read32(WDOGA_STAT)
+#define bfin_write_WDOGA_STAT(val)           bfin_write32(WDOGA_STAT,val)
+
+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
+#define bfin_read_WDOGB_CTL()                bfin_read16(WDOGB_CTL)
+#define bfin_write_WDOGB_CTL(val)            bfin_write16(WDOGB_CTL,val)
+#define bfin_read_WDOGB_CNT()                bfin_read32(WDOGB_CNT)
+#define bfin_write_WDOGB_CNT(val)            bfin_write32(WDOGB_CNT,val)
+#define bfin_read_WDOGB_STAT()               bfin_read32(WDOGB_STAT)
+#define bfin_write_WDOGB_STAT(val)           bfin_write32(WDOGB_STAT,val)
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define bfin_read_UART_THR()                 bfin_read16(UART_THR)
+#define bfin_write_UART_THR(val)             bfin_write16(UART_THR,val)
+#define bfin_read_UART_RBR()                 bfin_read16(UART_RBR)
+#define bfin_write_UART_RBR(val)             bfin_write16(UART_RBR,val)
+#define bfin_read_UART_DLL()                 bfin_read16(UART_DLL)
+#define bfin_write_UART_DLL(val)             bfin_write16(UART_DLL,val)
+#define bfin_read_UART_IER()                 bfin_read16(UART_IER)
+#define bfin_write_UART_IER(val)             bfin_write16(UART_IER,val)
+#define bfin_read_UART_DLH()                 bfin_read16(UART_DLH)
+#define bfin_write_UART_DLH(val)             bfin_write16(UART_DLH,val)
+#define bfin_read_UART_IIR()                 bfin_read16(UART_IIR)
+#define bfin_write_UART_IIR(val)             bfin_write16(UART_IIR,val)
+#define bfin_read_UART_LCR()                 bfin_read16(UART_LCR)
+#define bfin_write_UART_LCR(val)             bfin_write16(UART_LCR,val)
+#define bfin_read_UART_MCR()                 bfin_read16(UART_MCR)
+#define bfin_write_UART_MCR(val)             bfin_write16(UART_MCR,val)
+#define bfin_read_UART_LSR()                 bfin_read16(UART_LSR)
+#define bfin_write_UART_LSR(val)             bfin_write16(UART_LSR,val)
+#define bfin_read_UART_MSR()                 bfin_read16(UART_MSR)
+#define bfin_write_UART_MSR(val)             bfin_write16(UART_MSR,val)
+#define bfin_read_UART_SCR()                 bfin_read16(UART_SCR)
+#define bfin_write_UART_SCR(val)             bfin_write16(UART_SCR,val)
+#define bfin_read_UART_GCTL()                bfin_read16(UART_GCTL)
+#define bfin_write_UART_GCTL(val)            bfin_write16(UART_GCTL,val)
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define bfin_read_SPI_CTL()                  bfin_read16(SPI_CTL)
+#define bfin_write_SPI_CTL(val)              bfin_write16(SPI_CTL,val)
+#define bfin_read_SPI_FLG()                  bfin_read16(SPI_FLG)
+#define bfin_write_SPI_FLG(val)              bfin_write16(SPI_FLG,val)
+#define bfin_read_SPI_STAT()                 bfin_read16(SPI_STAT)
+#define bfin_write_SPI_STAT(val)             bfin_write16(SPI_STAT,val)
+#define bfin_read_SPI_TDBR()                 bfin_read16(SPI_TDBR)
+#define bfin_write_SPI_TDBR(val)             bfin_write16(SPI_TDBR,val)
+#define bfin_read_SPI_RDBR()                 bfin_read16(SPI_RDBR)
+#define bfin_write_SPI_RDBR(val)             bfin_write16(SPI_RDBR,val)
+#define bfin_read_SPI_BAUD()                 bfin_read16(SPI_BAUD)
+#define bfin_write_SPI_BAUD(val)             bfin_write16(SPI_BAUD,val)
+#define bfin_read_SPI_SHADOW()               bfin_read16(SPI_SHADOW)
+#define bfin_write_SPI_SHADOW(val)           bfin_write16(SPI_SHADOW,val)
+
+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
+#define bfin_read_TIMER0_CONFIG()            bfin_read16(TIMER0_CONFIG)
+#define bfin_write_TIMER0_CONFIG(val)        bfin_write16(TIMER0_CONFIG,val)
+#define bfin_read_TIMER0_COUNTER()           bfin_read32(TIMER0_COUNTER)
+#define bfin_write_TIMER0_COUNTER(val)       bfin_write32(TIMER0_COUNTER,val)
+#define bfin_read_TIMER0_PERIOD()            bfin_read32(TIMER0_PERIOD)
+#define bfin_write_TIMER0_PERIOD(val)        bfin_write32(TIMER0_PERIOD,val)
+#define bfin_read_TIMER0_WIDTH()             bfin_read32(TIMER0_WIDTH)
+#define bfin_write_TIMER0_WIDTH(val)         bfin_write32(TIMER0_WIDTH,val)
+#define bfin_read_TIMER1_CONFIG()            bfin_read16(TIMER1_CONFIG)
+#define bfin_write_TIMER1_CONFIG(val)        bfin_write16(TIMER1_CONFIG,val)
+#define bfin_read_TIMER1_COUNTER()           bfin_read32(TIMER1_COUNTER)
+#define bfin_write_TIMER1_COUNTER(val)       bfin_write32(TIMER1_COUNTER,val)
+#define bfin_read_TIMER1_PERIOD()            bfin_read32(TIMER1_PERIOD)
+#define bfin_write_TIMER1_PERIOD(val)        bfin_write32(TIMER1_PERIOD,val)
+#define bfin_read_TIMER1_WIDTH()             bfin_read32(TIMER1_WIDTH)
+#define bfin_write_TIMER1_WIDTH(val)         bfin_write32(TIMER1_WIDTH,val)
+#define bfin_read_TIMER2_CONFIG()            bfin_read16(TIMER2_CONFIG)
+#define bfin_write_TIMER2_CONFIG(val)        bfin_write16(TIMER2_CONFIG,val)
+#define bfin_read_TIMER2_COUNTER()           bfin_read32(TIMER2_COUNTER)
+#define bfin_write_TIMER2_COUNTER(val)       bfin_write32(TIMER2_COUNTER,val)
+#define bfin_read_TIMER2_PERIOD()            bfin_read32(TIMER2_PERIOD)
+#define bfin_write_TIMER2_PERIOD(val)        bfin_write32(TIMER2_PERIOD,val)
+#define bfin_read_TIMER2_WIDTH()             bfin_read32(TIMER2_WIDTH)
+#define bfin_write_TIMER2_WIDTH(val)         bfin_write32(TIMER2_WIDTH,val)
+#define bfin_read_TIMER3_CONFIG()            bfin_read16(TIMER3_CONFIG)
+#define bfin_write_TIMER3_CONFIG(val)        bfin_write16(TIMER3_CONFIG,val)
+#define bfin_read_TIMER3_COUNTER()           bfin_read32(TIMER3_COUNTER)
+#define bfin_write_TIMER3_COUNTER(val)       bfin_write32(TIMER3_COUNTER,val)
+#define bfin_read_TIMER3_PERIOD()            bfin_read32(TIMER3_PERIOD)
+#define bfin_write_TIMER3_PERIOD(val)        bfin_write32(TIMER3_PERIOD,val)
+#define bfin_read_TIMER3_WIDTH()             bfin_read32(TIMER3_WIDTH)
+#define bfin_write_TIMER3_WIDTH(val)         bfin_write32(TIMER3_WIDTH,val)
+#define bfin_read_TIMER4_CONFIG()            bfin_read16(TIMER4_CONFIG)
+#define bfin_write_TIMER4_CONFIG(val)        bfin_write16(TIMER4_CONFIG,val)
+#define bfin_read_TIMER4_COUNTER()           bfin_read32(TIMER4_COUNTER)
+#define bfin_write_TIMER4_COUNTER(val)       bfin_write32(TIMER4_COUNTER,val)
+#define bfin_read_TIMER4_PERIOD()            bfin_read32(TIMER4_PERIOD)
+#define bfin_write_TIMER4_PERIOD(val)        bfin_write32(TIMER4_PERIOD,val)
+#define bfin_read_TIMER4_WIDTH()             bfin_read32(TIMER4_WIDTH)
+#define bfin_write_TIMER4_WIDTH(val)         bfin_write32(TIMER4_WIDTH,val)
+#define bfin_read_TIMER5_CONFIG()            bfin_read16(TIMER5_CONFIG)
+#define bfin_write_TIMER5_CONFIG(val)        bfin_write16(TIMER5_CONFIG,val)
+#define bfin_read_TIMER5_COUNTER()           bfin_read32(TIMER5_COUNTER)
+#define bfin_write_TIMER5_COUNTER(val)       bfin_write32(TIMER5_COUNTER,val)
+#define bfin_read_TIMER5_PERIOD()            bfin_read32(TIMER5_PERIOD)
+#define bfin_write_TIMER5_PERIOD(val)        bfin_write32(TIMER5_PERIOD,val)
+#define bfin_read_TIMER5_WIDTH()             bfin_read32(TIMER5_WIDTH)
+#define bfin_write_TIMER5_WIDTH(val)         bfin_write32(TIMER5_WIDTH,val)
+#define bfin_read_TIMER6_CONFIG()            bfin_read16(TIMER6_CONFIG)
+#define bfin_write_TIMER6_CONFIG(val)        bfin_write16(TIMER6_CONFIG,val)
+#define bfin_read_TIMER6_COUNTER()           bfin_read32(TIMER6_COUNTER)
+#define bfin_write_TIMER6_COUNTER(val)       bfin_write32(TIMER6_COUNTER,val)
+#define bfin_read_TIMER6_PERIOD()            bfin_read32(TIMER6_PERIOD)
+#define bfin_write_TIMER6_PERIOD(val)        bfin_write32(TIMER6_PERIOD,val)
+#define bfin_read_TIMER6_WIDTH()             bfin_read32(TIMER6_WIDTH)
+#define bfin_write_TIMER6_WIDTH(val)         bfin_write32(TIMER6_WIDTH,val)
+#define bfin_read_TIMER7_CONFIG()            bfin_read16(TIMER7_CONFIG)
+#define bfin_write_TIMER7_CONFIG(val)        bfin_write16(TIMER7_CONFIG,val)
+#define bfin_read_TIMER7_COUNTER()           bfin_read32(TIMER7_COUNTER)
+#define bfin_write_TIMER7_COUNTER(val)       bfin_write32(TIMER7_COUNTER,val)
+#define bfin_read_TIMER7_PERIOD()            bfin_read32(TIMER7_PERIOD)
+#define bfin_write_TIMER7_PERIOD(val)        bfin_write32(TIMER7_PERIOD,val)
+#define bfin_read_TIMER7_WIDTH()             bfin_read32(TIMER7_WIDTH)
+#define bfin_write_TIMER7_WIDTH(val)         bfin_write32(TIMER7_WIDTH,val)
+
+/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
+#define bfin_read_TMRS8_ENABLE()             bfin_read16(TMRS8_ENABLE)
+#define bfin_write_TMRS8_ENABLE(val)         bfin_write16(TMRS8_ENABLE,val)
+#define bfin_read_TMRS8_DISABLE()            bfin_read16(TMRS8_DISABLE)
+#define bfin_write_TMRS8_DISABLE(val)        bfin_write16(TMRS8_DISABLE,val)
+#define bfin_read_TMRS8_STATUS()             bfin_read32(TMRS8_STATUS)
+#define bfin_write_TMRS8_STATUS(val)         bfin_write32(TMRS8_STATUS,val)
+#define bfin_read_TIMER8_CONFIG()            bfin_read16(TIMER8_CONFIG)
+#define bfin_write_TIMER8_CONFIG(val)        bfin_write16(TIMER8_CONFIG,val)
+#define bfin_read_TIMER8_COUNTER()           bfin_read32(TIMER8_COUNTER)
+#define bfin_write_TIMER8_COUNTER(val)       bfin_write32(TIMER8_COUNTER,val)
+#define bfin_read_TIMER8_PERIOD()            bfin_read32(TIMER8_PERIOD)
+#define bfin_write_TIMER8_PERIOD(val)        bfin_write32(TIMER8_PERIOD,val)
+#define bfin_read_TIMER8_WIDTH()             bfin_read32(TIMER8_WIDTH)
+#define bfin_write_TIMER8_WIDTH(val)         bfin_write32(TIMER8_WIDTH,val)
+#define bfin_read_TIMER9_CONFIG()            bfin_read16(TIMER9_CONFIG)
+#define bfin_write_TIMER9_CONFIG(val)        bfin_write16(TIMER9_CONFIG,val)
+#define bfin_read_TIMER9_COUNTER()           bfin_read32(TIMER9_COUNTER)
+#define bfin_write_TIMER9_COUNTER(val)       bfin_write32(TIMER9_COUNTER,val)
+#define bfin_read_TIMER9_PERIOD()            bfin_read32(TIMER9_PERIOD)
+#define bfin_write_TIMER9_PERIOD(val)        bfin_write32(TIMER9_PERIOD,val)
+#define bfin_read_TIMER9_WIDTH()             bfin_read32(TIMER9_WIDTH)
+#define bfin_write_TIMER9_WIDTH(val)         bfin_write32(TIMER9_WIDTH,val)
+#define bfin_read_TIMER10_CONFIG()           bfin_read16(TIMER10_CONFIG)
+#define bfin_write_TIMER10_CONFIG(val)       bfin_write16(TIMER10_CONFIG,val)
+#define bfin_read_TIMER10_COUNTER()          bfin_read32(TIMER10_COUNTER)
+#define bfin_write_TIMER10_COUNTER(val)      bfin_write32(TIMER10_COUNTER,val)
+#define bfin_read_TIMER10_PERIOD()           bfin_read32(TIMER10_PERIOD)
+#define bfin_write_TIMER10_PERIOD(val)       bfin_write32(TIMER10_PERIOD,val)
+#define bfin_read_TIMER10_WIDTH()            bfin_read32(TIMER10_WIDTH)
+#define bfin_write_TIMER10_WIDTH(val)        bfin_write32(TIMER10_WIDTH,val)
+#define bfin_read_TIMER11_CONFIG()           bfin_read16(TIMER11_CONFIG)
+#define bfin_write_TIMER11_CONFIG(val)       bfin_write16(TIMER11_CONFIG,val)
+#define bfin_read_TIMER11_COUNTER()          bfin_read32(TIMER11_COUNTER)
+#define bfin_write_TIMER11_COUNTER(val)      bfin_write32(TIMER11_COUNTER,val)
+#define bfin_read_TIMER11_PERIOD()           bfin_read32(TIMER11_PERIOD)
+#define bfin_write_TIMER11_PERIOD(val)       bfin_write32(TIMER11_PERIOD,val)
+#define bfin_read_TIMER11_WIDTH()            bfin_read32(TIMER11_WIDTH)
+#define bfin_write_TIMER11_WIDTH(val)        bfin_write32(TIMER11_WIDTH,val)
+#define bfin_read_TMRS4_ENABLE()             bfin_read16(TMRS4_ENABLE)
+#define bfin_write_TMRS4_ENABLE(val)         bfin_write16(TMRS4_ENABLE,val)
+#define bfin_read_TMRS4_DISABLE()            bfin_read16(TMRS4_DISABLE)
+#define bfin_write_TMRS4_DISABLE(val)        bfin_write16(TMRS4_DISABLE,val)
+#define bfin_read_TMRS4_STATUS()             bfin_read32(TMRS4_STATUS)
+#define bfin_write_TMRS4_STATUS(val)         bfin_write32(TMRS4_STATUS,val)
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define bfin_read_FIO0_FLAG_D()              bfin_read16(FIO0_FLAG_D)
+#define bfin_write_FIO0_FLAG_D(val)          bfin_write16(FIO0_FLAG_D,val)
+#define bfin_read_FIO0_FLAG_C()              bfin_read16(FIO0_FLAG_C)
+#define bfin_write_FIO0_FLAG_C(val)          bfin_write16(FIO0_FLAG_C,val)
+#define bfin_read_FIO0_FLAG_S()              bfin_read16(FIO0_FLAG_S)
+#define bfin_write_FIO0_FLAG_S(val)          bfin_write16(FIO0_FLAG_S,val)
+#define bfin_read_FIO0_FLAG_T()              bfin_read16(FIO0_FLAG_T)
+#define bfin_write_FIO0_FLAG_T(val)          bfin_write16(FIO0_FLAG_T,val)
+#define bfin_read_FIO0_MASKA_D()             bfin_read16(FIO0_MASKA_D)
+#define bfin_write_FIO0_MASKA_D(val)         bfin_write16(FIO0_MASKA_D,val)
+#define bfin_read_FIO0_MASKA_C()             bfin_read16(FIO0_MASKA_C)
+#define bfin_write_FIO0_MASKA_C(val)         bfin_write16(FIO0_MASKA_C,val)
+#define bfin_read_FIO0_MASKA_S()             bfin_read16(FIO0_MASKA_S)
+#define bfin_write_FIO0_MASKA_S(val)         bfin_write16(FIO0_MASKA_S,val)
+#define bfin_read_FIO0_MASKA_T()             bfin_read16(FIO0_MASKA_T)
+#define bfin_write_FIO0_MASKA_T(val)         bfin_write16(FIO0_MASKA_T,val)
+#define bfin_read_FIO0_MASKB_D()             bfin_read16(FIO0_MASKB_D)
+#define bfin_write_FIO0_MASKB_D(val)         bfin_write16(FIO0_MASKB_D,val)
+#define bfin_read_FIO0_MASKB_C()             bfin_read16(FIO0_MASKB_C)
+#define bfin_write_FIO0_MASKB_C(val)         bfin_write16(FIO0_MASKB_C,val)
+#define bfin_read_FIO0_MASKB_S()             bfin_read16(FIO0_MASKB_S)
+#define bfin_write_FIO0_MASKB_S(val)         bfin_write16(FIO0_MASKB_S,val)
+#define bfin_read_FIO0_MASKB_T()             bfin_read16(FIO0_MASKB_T)
+#define bfin_write_FIO0_MASKB_T(val)         bfin_write16(FIO0_MASKB_T,val)
+#define bfin_read_FIO0_DIR()                 bfin_read16(FIO0_DIR)
+#define bfin_write_FIO0_DIR(val)             bfin_write16(FIO0_DIR,val)
+#define bfin_read_FIO0_POLAR()               bfin_read16(FIO0_POLAR)
+#define bfin_write_FIO0_POLAR(val)           bfin_write16(FIO0_POLAR,val)
+#define bfin_read_FIO0_EDGE()                bfin_read16(FIO0_EDGE)
+#define bfin_write_FIO0_EDGE(val)            bfin_write16(FIO0_EDGE,val)
+#define bfin_read_FIO0_BOTH()                bfin_read16(FIO0_BOTH)
+#define bfin_write_FIO0_BOTH(val)            bfin_write16(FIO0_BOTH,val)
+#define bfin_read_FIO0_INEN()                bfin_read16(FIO0_INEN)
+#define bfin_write_FIO0_INEN(val)            bfin_write16(FIO0_INEN,val)
+/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
+#define bfin_read_FIO1_FLAG_D()              bfin_read16(FIO1_FLAG_D)
+#define bfin_write_FIO1_FLAG_D(val)          bfin_write16(FIO1_FLAG_D,val)
+#define bfin_read_FIO1_FLAG_C()              bfin_read16(FIO1_FLAG_C)
+#define bfin_write_FIO1_FLAG_C(val)          bfin_write16(FIO1_FLAG_C,val)
+#define bfin_read_FIO1_FLAG_S()              bfin_read16(FIO1_FLAG_S)
+#define bfin_write_FIO1_FLAG_S(val)          bfin_write16(FIO1_FLAG_S,val)
+#define bfin_read_FIO1_FLAG_T()              bfin_read16(FIO1_FLAG_T)
+#define bfin_write_FIO1_FLAG_T(val)          bfin_write16(FIO1_FLAG_T,val)
+#define bfin_read_FIO1_MASKA_D()             bfin_read16(FIO1_MASKA_D)
+#define bfin_write_FIO1_MASKA_D(val)         bfin_write16(FIO1_MASKA_D,val)
+#define bfin_read_FIO1_MASKA_C()             bfin_read16(FIO1_MASKA_C)
+#define bfin_write_FIO1_MASKA_C(val)         bfin_write16(FIO1_MASKA_C,val)
+#define bfin_read_FIO1_MASKA_S()             bfin_read16(FIO1_MASKA_S)
+#define bfin_write_FIO1_MASKA_S(val)         bfin_write16(FIO1_MASKA_S,val)
+#define bfin_read_FIO1_MASKA_T()             bfin_read16(FIO1_MASKA_T)
+#define bfin_write_FIO1_MASKA_T(val)         bfin_write16(FIO1_MASKA_T,val)
+#define bfin_read_FIO1_MASKB_D()             bfin_read16(FIO1_MASKB_D)
+#define bfin_write_FIO1_MASKB_D(val)         bfin_write16(FIO1_MASKB_D,val)
+#define bfin_read_FIO1_MASKB_C()             bfin_read16(FIO1_MASKB_C)
+#define bfin_write_FIO1_MASKB_C(val)         bfin_write16(FIO1_MASKB_C,val)
+#define bfin_read_FIO1_MASKB_S()             bfin_read16(FIO1_MASKB_S)
+#define bfin_write_FIO1_MASKB_S(val)         bfin_write16(FIO1_MASKB_S,val)
+#define bfin_read_FIO1_MASKB_T()             bfin_read16(FIO1_MASKB_T)
+#define bfin_write_FIO1_MASKB_T(val)         bfin_write16(FIO1_MASKB_T,val)
+#define bfin_read_FIO1_DIR()                 bfin_read16(FIO1_DIR)
+#define bfin_write_FIO1_DIR(val)             bfin_write16(FIO1_DIR,val)
+#define bfin_read_FIO1_POLAR()               bfin_read16(FIO1_POLAR)
+#define bfin_write_FIO1_POLAR(val)           bfin_write16(FIO1_POLAR,val)
+#define bfin_read_FIO1_EDGE()                bfin_read16(FIO1_EDGE)
+#define bfin_write_FIO1_EDGE(val)            bfin_write16(FIO1_EDGE,val)
+#define bfin_read_FIO1_BOTH()                bfin_read16(FIO1_BOTH)
+#define bfin_write_FIO1_BOTH(val)            bfin_write16(FIO1_BOTH,val)
+#define bfin_read_FIO1_INEN()                bfin_read16(FIO1_INEN)
+#define bfin_write_FIO1_INEN(val)            bfin_write16(FIO1_INEN,val)
+/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
+#define bfin_read_FIO2_FLAG_D()              bfin_read16(FIO2_FLAG_D)
+#define bfin_write_FIO2_FLAG_D(val)          bfin_write16(FIO2_FLAG_D,val)
+#define bfin_read_FIO2_FLAG_C()              bfin_read16(FIO2_FLAG_C)
+#define bfin_write_FIO2_FLAG_C(val)          bfin_write16(FIO2_FLAG_C,val)
+#define bfin_read_FIO2_FLAG_S()              bfin_read16(FIO2_FLAG_S)
+#define bfin_write_FIO2_FLAG_S(val)          bfin_write16(FIO2_FLAG_S,val)
+#define bfin_read_FIO2_FLAG_T()              bfin_read16(FIO2_FLAG_T)
+#define bfin_write_FIO2_FLAG_T(val)          bfin_write16(FIO2_FLAG_T,val)
+#define bfin_read_FIO2_MASKA_D()             bfin_read16(FIO2_MASKA_D)
+#define bfin_write_FIO2_MASKA_D(val)         bfin_write16(FIO2_MASKA_D,val)
+#define bfin_read_FIO2_MASKA_C()             bfin_read16(FIO2_MASKA_C)
+#define bfin_write_FIO2_MASKA_C(val)         bfin_write16(FIO2_MASKA_C,val)
+#define bfin_read_FIO2_MASKA_S()             bfin_read16(FIO2_MASKA_S)
+#define bfin_write_FIO2_MASKA_S(val)         bfin_write16(FIO2_MASKA_S,val)
+#define bfin_read_FIO2_MASKA_T()             bfin_read16(FIO2_MASKA_T)
+#define bfin_write_FIO2_MASKA_T(val)         bfin_write16(FIO2_MASKA_T,val)
+#define bfin_read_FIO2_MASKB_D()             bfin_read16(FIO2_MASKB_D)
+#define bfin_write_FIO2_MASKB_D(val)         bfin_write16(FIO2_MASKB_D,val)
+#define bfin_read_FIO2_MASKB_C()             bfin_read16(FIO2_MASKB_C)
+#define bfin_write_FIO2_MASKB_C(val)         bfin_write16(FIO2_MASKB_C,val)
+#define bfin_read_FIO2_MASKB_S()             bfin_read16(FIO2_MASKB_S)
+#define bfin_write_FIO2_MASKB_S(val)         bfin_write16(FIO2_MASKB_S,val)
+#define bfin_read_FIO2_MASKB_T()             bfin_read16(FIO2_MASKB_T)
+#define bfin_write_FIO2_MASKB_T(val)         bfin_write16(FIO2_MASKB_T,val)
+#define bfin_read_FIO2_DIR()                 bfin_read16(FIO2_DIR)
+#define bfin_write_FIO2_DIR(val)             bfin_write16(FIO2_DIR,val)
+#define bfin_read_FIO2_POLAR()               bfin_read16(FIO2_POLAR)
+#define bfin_write_FIO2_POLAR(val)           bfin_write16(FIO2_POLAR,val)
+#define bfin_read_FIO2_EDGE()                bfin_read16(FIO2_EDGE)
+#define bfin_write_FIO2_EDGE(val)            bfin_write16(FIO2_EDGE,val)
+#define bfin_read_FIO2_BOTH()                bfin_read16(FIO2_BOTH)
+#define bfin_write_FIO2_BOTH(val)            bfin_write16(FIO2_BOTH,val)
+#define bfin_read_FIO2_INEN()                bfin_read16(FIO2_INEN)
+#define bfin_write_FIO2_INEN(val)            bfin_write16(FIO2_INEN,val)
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define bfin_read_SPORT0_TCR1()              bfin_read16(SPORT0_TCR1)
+#define bfin_write_SPORT0_TCR1(val)          bfin_write16(SPORT0_TCR1,val)
+#define bfin_read_SPORT0_TCR2()              bfin_read16(SPORT0_TCR2)
+#define bfin_write_SPORT0_TCR2(val)          bfin_write16(SPORT0_TCR2,val)
+#define bfin_read_SPORT0_TCLKDIV()           bfin_read16(SPORT0_TCLKDIV)
+#define bfin_write_SPORT0_TCLKDIV(val)       bfin_write16(SPORT0_TCLKDIV,val)
+#define bfin_read_SPORT0_TFSDIV()            bfin_read16(SPORT0_TFSDIV)
+#define bfin_write_SPORT0_TFSDIV(val)        bfin_write16(SPORT0_TFSDIV,val)
+#define bfin_read_SPORT0_TX()                bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX(val)            bfin_write32(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX()                bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX(val)            bfin_write32(SPORT0_RX,val)
+#define bfin_read_SPORT0_TX32()              bfin_read32(SPORT0_TX)
+#define bfin_write_SPORT0_TX32(val)          bfin_write32(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX32()              bfin_read32(SPORT0_RX)
+#define bfin_write_SPORT0_RX32(val)          bfin_write32(SPORT0_RX,val)
+#define bfin_read_SPORT0_TX16()              bfin_read16(SPORT0_TX)
+#define bfin_write_SPORT0_TX16(val)          bfin_write16(SPORT0_TX,val)
+#define bfin_read_SPORT0_RX16()              bfin_read16(SPORT0_RX)
+#define bfin_write_SPORT0_RX16(val)          bfin_write16(SPORT0_RX,val)
+#define bfin_read_SPORT0_RCR1()              bfin_read16(SPORT0_RCR1)
+#define bfin_write_SPORT0_RCR1(val)          bfin_write16(SPORT0_RCR1,val)
+#define bfin_read_SPORT0_RCR2()              bfin_read16(SPORT0_RCR2)
+#define bfin_write_SPORT0_RCR2(val)          bfin_write16(SPORT0_RCR2,val)
+#define bfin_read_SPORT0_RCLKDIV()           bfin_read16(SPORT0_RCLKDIV)
+#define bfin_write_SPORT0_RCLKDIV(val)       bfin_write16(SPORT0_RCLKDIV,val)
+#define bfin_read_SPORT0_RFSDIV()            bfin_read16(SPORT0_RFSDIV)
+#define bfin_write_SPORT0_RFSDIV(val)        bfin_write16(SPORT0_RFSDIV,val)
+#define bfin_read_SPORT0_STAT()              bfin_read16(SPORT0_STAT)
+#define bfin_write_SPORT0_STAT(val)          bfin_write16(SPORT0_STAT,val)
+#define bfin_read_SPORT0_CHNL()              bfin_read16(SPORT0_CHNL)
+#define bfin_write_SPORT0_CHNL(val)          bfin_write16(SPORT0_CHNL,val)
+#define bfin_read_SPORT0_MCMC1()             bfin_read16(SPORT0_MCMC1)
+#define bfin_write_SPORT0_MCMC1(val)         bfin_write16(SPORT0_MCMC1,val)
+#define bfin_read_SPORT0_MCMC2()             bfin_read16(SPORT0_MCMC2)
+#define bfin_write_SPORT0_MCMC2(val)         bfin_write16(SPORT0_MCMC2,val)
+#define bfin_read_SPORT0_MTCS0()             bfin_read32(SPORT0_MTCS0)
+#define bfin_write_SPORT0_MTCS0(val)         bfin_write32(SPORT0_MTCS0,val)
+#define bfin_read_SPORT0_MTCS1()             bfin_read32(SPORT0_MTCS1)
+#define bfin_write_SPORT0_MTCS1(val)         bfin_write32(SPORT0_MTCS1,val)
+#define bfin_read_SPORT0_MTCS2()             bfin_read32(SPORT0_MTCS2)
+#define bfin_write_SPORT0_MTCS2(val)         bfin_write32(SPORT0_MTCS2,val)
+#define bfin_read_SPORT0_MTCS3()             bfin_read32(SPORT0_MTCS3)
+#define bfin_write_SPORT0_MTCS3(val)         bfin_write32(SPORT0_MTCS3,val)
+#define bfin_read_SPORT0_MRCS0()             bfin_read32(SPORT0_MRCS0)
+#define bfin_write_SPORT0_MRCS0(val)         bfin_write32(SPORT0_MRCS0,val)
+#define bfin_read_SPORT0_MRCS1()             bfin_read32(SPORT0_MRCS1)
+#define bfin_write_SPORT0_MRCS1(val)         bfin_write32(SPORT0_MRCS1,val)
+#define bfin_read_SPORT0_MRCS2()             bfin_read32(SPORT0_MRCS2)
+#define bfin_write_SPORT0_MRCS2(val)         bfin_write32(SPORT0_MRCS2,val)
+#define bfin_read_SPORT0_MRCS3()             bfin_read32(SPORT0_MRCS3)
+#define bfin_write_SPORT0_MRCS3(val)         bfin_write32(SPORT0_MRCS3,val)
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define bfin_read_SPORT1_TCR1()              bfin_read16(SPORT1_TCR1)
+#define bfin_write_SPORT1_TCR1(val)          bfin_write16(SPORT1_TCR1,val)
+#define bfin_read_SPORT1_TCR2()              bfin_read16(SPORT1_TCR2)
+#define bfin_write_SPORT1_TCR2(val)          bfin_write16(SPORT1_TCR2,val)
+#define bfin_read_SPORT1_TCLKDIV()           bfin_read16(SPORT1_TCLKDIV)
+#define bfin_write_SPORT1_TCLKDIV(val)       bfin_write16(SPORT1_TCLKDIV,val)
+#define bfin_read_SPORT1_TFSDIV()            bfin_read16(SPORT1_TFSDIV)
+#define bfin_write_SPORT1_TFSDIV(val)        bfin_write16(SPORT1_TFSDIV,val)
+#define bfin_read_SPORT1_TX()                bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX(val)            bfin_write32(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX()                bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX(val)            bfin_write32(SPORT1_RX,val)
+#define bfin_read_SPORT1_TX32()              bfin_read32(SPORT1_TX)
+#define bfin_write_SPORT1_TX32(val)          bfin_write32(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX32()              bfin_read32(SPORT1_RX)
+#define bfin_write_SPORT1_RX32(val)          bfin_write32(SPORT1_RX,val)
+#define bfin_read_SPORT1_TX16()              bfin_read16(SPORT1_TX)
+#define bfin_write_SPORT1_TX16(val)          bfin_write16(SPORT1_TX,val)
+#define bfin_read_SPORT1_RX16()              bfin_read16(SPORT1_RX)
+#define bfin_write_SPORT1_RX16(val)          bfin_write16(SPORT1_RX,val)
+#define bfin_read_SPORT1_RCR1()              bfin_read16(SPORT1_RCR1)
+#define bfin_write_SPORT1_RCR1(val)          bfin_write16(SPORT1_RCR1,val)
+#define bfin_read_SPORT1_RCR2()              bfin_read16(SPORT1_RCR2)
+#define bfin_write_SPORT1_RCR2(val)          bfin_write16(SPORT1_RCR2,val)
+#define bfin_read_SPORT1_RCLKDIV()           bfin_read16(SPORT1_RCLKDIV)
+#define bfin_write_SPORT1_RCLKDIV(val)       bfin_write16(SPORT1_RCLKDIV,val)
+#define bfin_read_SPORT1_RFSDIV()            bfin_read16(SPORT1_RFSDIV)
+#define bfin_write_SPORT1_RFSDIV(val)        bfin_write16(SPORT1_RFSDIV,val)
+#define bfin_read_SPORT1_STAT()              bfin_read16(SPORT1_STAT)
+#define bfin_write_SPORT1_STAT(val)          bfin_write16(SPORT1_STAT,val)
+#define bfin_read_SPORT1_CHNL()              bfin_read16(SPORT1_CHNL)
+#define bfin_write_SPORT1_CHNL(val)          bfin_write16(SPORT1_CHNL,val)
+#define bfin_read_SPORT1_MCMC1()             bfin_read16(SPORT1_MCMC1)
+#define bfin_write_SPORT1_MCMC1(val)         bfin_write16(SPORT1_MCMC1,val)
+#define bfin_read_SPORT1_MCMC2()             bfin_read16(SPORT1_MCMC2)
+#define bfin_write_SPORT1_MCMC2(val)         bfin_write16(SPORT1_MCMC2,val)
+#define bfin_read_SPORT1_MTCS0()             bfin_read32(SPORT1_MTCS0)
+#define bfin_write_SPORT1_MTCS0(val)         bfin_write32(SPORT1_MTCS0,val)
+#define bfin_read_SPORT1_MTCS1()             bfin_read32(SPORT1_MTCS1)
+#define bfin_write_SPORT1_MTCS1(val)         bfin_write32(SPORT1_MTCS1,val)
+#define bfin_read_SPORT1_MTCS2()             bfin_read32(SPORT1_MTCS2)
+#define bfin_write_SPORT1_MTCS2(val)         bfin_write32(SPORT1_MTCS2,val)
+#define bfin_read_SPORT1_MTCS3()             bfin_read32(SPORT1_MTCS3)
+#define bfin_write_SPORT1_MTCS3(val)         bfin_write32(SPORT1_MTCS3,val)
+#define bfin_read_SPORT1_MRCS0()             bfin_read32(SPORT1_MRCS0)
+#define bfin_write_SPORT1_MRCS0(val)         bfin_write32(SPORT1_MRCS0,val)
+#define bfin_read_SPORT1_MRCS1()             bfin_read32(SPORT1_MRCS1)
+#define bfin_write_SPORT1_MRCS1(val)         bfin_write32(SPORT1_MRCS1,val)
+#define bfin_read_SPORT1_MRCS2()             bfin_read32(SPORT1_MRCS2)
+#define bfin_write_SPORT1_MRCS2(val)         bfin_write32(SPORT1_MRCS2,val)
+#define bfin_read_SPORT1_MRCS3()             bfin_read32(SPORT1_MRCS3)
+#define bfin_write_SPORT1_MRCS3(val)         bfin_write32(SPORT1_MRCS3,val)
+/* Asynchronous Memory Controller - External Bus Interface Unit */
+#define bfin_read_EBIU_AMGCTL()              bfin_read16(EBIU_AMGCTL)
+#define bfin_write_EBIU_AMGCTL(val)          bfin_write16(EBIU_AMGCTL,val)
+#define bfin_read_EBIU_AMBCTL0()             bfin_read32(EBIU_AMBCTL0)
+#define bfin_write_EBIU_AMBCTL0(val)         bfin_write32(EBIU_AMBCTL0,val)
+#define bfin_read_EBIU_AMBCTL1()             bfin_read32(EBIU_AMBCTL1)
+#define bfin_write_EBIU_AMBCTL1(val)         bfin_write32(EBIU_AMBCTL1,val)
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define bfin_read_EBIU_SDGCTL()              bfin_read32(EBIU_SDGCTL)
+#define bfin_write_EBIU_SDGCTL(val)          bfin_write32(EBIU_SDGCTL,val)
+#define bfin_read_EBIU_SDBCTL()              bfin_read32(EBIU_SDBCTL)
+#define bfin_write_EBIU_SDBCTL(val)          bfin_write32(EBIU_SDBCTL,val)
+#define bfin_read_EBIU_SDRRC()               bfin_read16(EBIU_SDRRC)
+#define bfin_write_EBIU_SDRRC(val)           bfin_write16(EBIU_SDRRC,val)
+#define bfin_read_EBIU_SDSTAT()              bfin_read16(EBIU_SDSTAT)
+#define bfin_write_EBIU_SDSTAT(val)          bfin_write16(EBIU_SDSTAT,val)
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
+#define bfin_read_PPI0_CONTROL()             bfin_read16(PPI0_CONTROL)
+#define bfin_write_PPI0_CONTROL(val)         bfin_write16(PPI0_CONTROL,val)
+#define bfin_read_PPI0_STATUS()              bfin_read16(PPI0_STATUS)
+#define bfin_write_PPI0_STATUS(val)          bfin_write16(PPI0_STATUS,val)
+#define bfin_read_PPI0_COUNT()               bfin_read16(PPI0_COUNT)
+#define bfin_write_PPI0_COUNT(val)           bfin_write16(PPI0_COUNT,val)
+#define bfin_read_PPI0_DELAY()               bfin_read16(PPI0_DELAY)
+#define bfin_write_PPI0_DELAY(val)           bfin_write16(PPI0_DELAY,val)
+#define bfin_read_PPI0_FRAME()               bfin_read16(PPI0_FRAME)
+#define bfin_write_PPI0_FRAME(val)           bfin_write16(PPI0_FRAME,val)
+/* Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
+#define bfin_read_PPI1_CONTROL()             bfin_read16(PPI1_CONTROL)
+#define bfin_write_PPI1_CONTROL(val)         bfin_write16(PPI1_CONTROL,val)
+#define bfin_read_PPI1_STATUS()              bfin_read16(PPI1_STATUS)
+#define bfin_write_PPI1_STATUS(val)          bfin_write16(PPI1_STATUS,val)
+#define bfin_read_PPI1_COUNT()               bfin_read16(PPI1_COUNT)
+#define bfin_write_PPI1_COUNT(val)           bfin_write16(PPI1_COUNT,val)
+#define bfin_read_PPI1_DELAY()               bfin_read16(PPI1_DELAY)
+#define bfin_write_PPI1_DELAY(val)           bfin_write16(PPI1_DELAY,val)
+#define bfin_read_PPI1_FRAME()               bfin_read16(PPI1_FRAME)
+#define bfin_write_PPI1_FRAME(val)           bfin_write16(PPI1_FRAME,val)
+/*DMA traffic control registers */
+#define bfin_read_DMA1_TC_PER()              bfin_read16(DMA1_TC_PER)
+#define bfin_write_DMA1_TC_PER(val)          bfin_write16(DMA1_TC_PER,val)
+#define bfin_read_DMA1_TC_CNT()              bfin_read16(DMA1_TC_CNT)
+#define bfin_write_DMA1_TC_CNT(val)          bfin_write16(DMA1_TC_CNT,val)
+#define bfin_read_DMA2_TC_PER()              bfin_read16(DMA2_TC_PER)
+#define bfin_write_DMA2_TC_PER(val)          bfin_write16(DMA2_TC_PER,val)
+#define bfin_read_DMA2_TC_CNT()              bfin_read16(DMA2_TC_CNT)
+#define bfin_write_DMA2_TC_CNT(val)          bfin_write16(DMA2_TC_CNT,val)
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define bfin_read_DMA1_0_CONFIG()            bfin_read16(DMA1_0_CONFIG)
+#define bfin_write_DMA1_0_CONFIG(val)        bfin_write16(DMA1_0_CONFIG,val)
+#define bfin_read_DMA1_0_NEXT_DESC_PTR()     bfin_read32(DMA1_0_NEXT_DESC_PTR)
+#define bfin_write_DMA1_0_NEXT_DESC_PTR(val) bfin_write32(DMA1_0_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_0_START_ADDR()        bfin_read32(DMA1_0_START_ADDR)
+#define bfin_write_DMA1_0_START_ADDR(val)    bfin_write32(DMA1_0_START_ADDR,val)
+#define bfin_read_DMA1_0_X_COUNT()           bfin_read16(DMA1_0_X_COUNT)
+#define bfin_write_DMA1_0_X_COUNT(val)       bfin_write16(DMA1_0_X_COUNT,val)
+#define bfin_read_DMA1_0_Y_COUNT()           bfin_read16(DMA1_0_Y_COUNT)
+#define bfin_write_DMA1_0_Y_COUNT(val)       bfin_write16(DMA1_0_Y_COUNT,val)
+#define bfin_read_DMA1_0_X_MODIFY()          bfin_read16(DMA1_0_X_MODIFY)
+#define bfin_write_DMA1_0_X_MODIFY(val)      bfin_write16(DMA1_0_X_MODIFY,val)
+#define bfin_read_DMA1_0_Y_MODIFY()          bfin_read16(DMA1_0_Y_MODIFY)
+#define bfin_write_DMA1_0_Y_MODIFY(val)      bfin_write16(DMA1_0_Y_MODIFY,val)
+#define bfin_read_DMA1_0_CURR_DESC_PTR()     bfin_read32(DMA1_0_CURR_DESC_PTR)
+#define bfin_write_DMA1_0_CURR_DESC_PTR(val) bfin_write32(DMA1_0_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_0_CURR_ADDR()         bfin_read32(DMA1_0_CURR_ADDR)
+#define bfin_write_DMA1_0_CURR_ADDR(val)     bfin_write32(DMA1_0_CURR_ADDR,val)
+#define bfin_read_DMA1_0_CURR_X_COUNT()      bfin_read16(DMA1_0_CURR_X_COUNT)
+#define bfin_write_DMA1_0_CURR_X_COUNT(val)  bfin_write16(DMA1_0_CURR_X_COUNT,val)
+#define bfin_read_DMA1_0_CURR_Y_COUNT()      bfin_read16(DMA1_0_CURR_Y_COUNT)
+#define bfin_write_DMA1_0_CURR_Y_COUNT(val)  bfin_write16(DMA1_0_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_0_IRQ_STATUS()        bfin_read16(DMA1_0_IRQ_STATUS)
+#define bfin_write_DMA1_0_IRQ_STATUS(val)    bfin_write16(DMA1_0_IRQ_STATUS,val)
+#define bfin_read_DMA1_0_PERIPHERAL_MAP()    bfin_read16(DMA1_0_PERIPHERAL_MAP)
+#define bfin_write_DMA1_0_PERIPHERAL_MAP(val) bfin_write16(DMA1_0_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_1_CONFIG()            bfin_read16(DMA1_1_CONFIG)
+#define bfin_write_DMA1_1_CONFIG(val)        bfin_write16(DMA1_1_CONFIG,val)
+#define bfin_read_DMA1_1_NEXT_DESC_PTR()     bfin_read32(DMA1_1_NEXT_DESC_PTR)
+#define bfin_write_DMA1_1_NEXT_DESC_PTR(val) bfin_write32(DMA1_1_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_1_START_ADDR()        bfin_read32(DMA1_1_START_ADDR)
+#define bfin_write_DMA1_1_START_ADDR(val)    bfin_write32(DMA1_1_START_ADDR,val)
+#define bfin_read_DMA1_1_X_COUNT()           bfin_read16(DMA1_1_X_COUNT)
+#define bfin_write_DMA1_1_X_COUNT(val)       bfin_write16(DMA1_1_X_COUNT,val)
+#define bfin_read_DMA1_1_Y_COUNT()           bfin_read16(DMA1_1_Y_COUNT)
+#define bfin_write_DMA1_1_Y_COUNT(val)       bfin_write16(DMA1_1_Y_COUNT,val)
+#define bfin_read_DMA1_1_X_MODIFY()          bfin_read16(DMA1_1_X_MODIFY)
+#define bfin_write_DMA1_1_X_MODIFY(val)      bfin_write16(DMA1_1_X_MODIFY,val)
+#define bfin_read_DMA1_1_Y_MODIFY()          bfin_read16(DMA1_1_Y_MODIFY)
+#define bfin_write_DMA1_1_Y_MODIFY(val)      bfin_write16(DMA1_1_Y_MODIFY,val)
+#define bfin_read_DMA1_1_CURR_DESC_PTR()     bfin_read32(DMA1_1_CURR_DESC_PTR)
+#define bfin_write_DMA1_1_CURR_DESC_PTR(val) bfin_write32(DMA1_1_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_1_CURR_ADDR()         bfin_read32(DMA1_1_CURR_ADDR)
+#define bfin_write_DMA1_1_CURR_ADDR(val)     bfin_write32(DMA1_1_CURR_ADDR,val)
+#define bfin_read_DMA1_1_CURR_X_COUNT()      bfin_read16(DMA1_1_CURR_X_COUNT)
+#define bfin_write_DMA1_1_CURR_X_COUNT(val)  bfin_write16(DMA1_1_CURR_X_COUNT,val)
+#define bfin_read_DMA1_1_CURR_Y_COUNT()      bfin_read16(DMA1_1_CURR_Y_COUNT)
+#define bfin_write_DMA1_1_CURR_Y_COUNT(val)  bfin_write16(DMA1_1_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_1_IRQ_STATUS()        bfin_read16(DMA1_1_IRQ_STATUS)
+#define bfin_write_DMA1_1_IRQ_STATUS(val)    bfin_write16(DMA1_1_IRQ_STATUS,val)
+#define bfin_read_DMA1_1_PERIPHERAL_MAP()    bfin_read16(DMA1_1_PERIPHERAL_MAP)
+#define bfin_write_DMA1_1_PERIPHERAL_MAP(val) bfin_write16(DMA1_1_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_2_CONFIG()            bfin_read16(DMA1_2_CONFIG)
+#define bfin_write_DMA1_2_CONFIG(val)        bfin_write16(DMA1_2_CONFIG,val)
+#define bfin_read_DMA1_2_NEXT_DESC_PTR()     bfin_read32(DMA1_2_NEXT_DESC_PTR)
+#define bfin_write_DMA1_2_NEXT_DESC_PTR(val) bfin_write32(DMA1_2_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_2_START_ADDR()        bfin_read32(DMA1_2_START_ADDR)
+#define bfin_write_DMA1_2_START_ADDR(val)    bfin_write32(DMA1_2_START_ADDR,val)
+#define bfin_read_DMA1_2_X_COUNT()           bfin_read16(DMA1_2_X_COUNT)
+#define bfin_write_DMA1_2_X_COUNT(val)       bfin_write16(DMA1_2_X_COUNT,val)
+#define bfin_read_DMA1_2_Y_COUNT()           bfin_read16(DMA1_2_Y_COUNT)
+#define bfin_write_DMA1_2_Y_COUNT(val)       bfin_write16(DMA1_2_Y_COUNT,val)
+#define bfin_read_DMA1_2_X_MODIFY()          bfin_read16(DMA1_2_X_MODIFY)
+#define bfin_write_DMA1_2_X_MODIFY(val)      bfin_write16(DMA1_2_X_MODIFY,val)
+#define bfin_read_DMA1_2_Y_MODIFY()          bfin_read16(DMA1_2_Y_MODIFY)
+#define bfin_write_DMA1_2_Y_MODIFY(val)      bfin_write16(DMA1_2_Y_MODIFY,val)
+#define bfin_read_DMA1_2_CURR_DESC_PTR()     bfin_read32(DMA1_2_CURR_DESC_PTR)
+#define bfin_write_DMA1_2_CURR_DESC_PTR(val) bfin_write32(DMA1_2_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_2_CURR_ADDR()         bfin_read32(DMA1_2_CURR_ADDR)
+#define bfin_write_DMA1_2_CURR_ADDR(val)     bfin_write32(DMA1_2_CURR_ADDR,val)
+#define bfin_read_DMA1_2_CURR_X_COUNT()      bfin_read16(DMA1_2_CURR_X_COUNT)
+#define bfin_write_DMA1_2_CURR_X_COUNT(val)  bfin_write16(DMA1_2_CURR_X_COUNT,val)
+#define bfin_read_DMA1_2_CURR_Y_COUNT()      bfin_read16(DMA1_2_CURR_Y_COUNT)
+#define bfin_write_DMA1_2_CURR_Y_COUNT(val)  bfin_write16(DMA1_2_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_2_IRQ_STATUS()        bfin_read16(DMA1_2_IRQ_STATUS)
+#define bfin_write_DMA1_2_IRQ_STATUS(val)    bfin_write16(DMA1_2_IRQ_STATUS,val)
+#define bfin_read_DMA1_2_PERIPHERAL_MAP()    bfin_read16(DMA1_2_PERIPHERAL_MAP)
+#define bfin_write_DMA1_2_PERIPHERAL_MAP(val) bfin_write16(DMA1_2_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_3_CONFIG()            bfin_read16(DMA1_3_CONFIG)
+#define bfin_write_DMA1_3_CONFIG(val)        bfin_write16(DMA1_3_CONFIG,val)
+#define bfin_read_DMA1_3_NEXT_DESC_PTR()     bfin_read32(DMA1_3_NEXT_DESC_PTR)
+#define bfin_write_DMA1_3_NEXT_DESC_PTR(val) bfin_write32(DMA1_3_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_3_START_ADDR()        bfin_read32(DMA1_3_START_ADDR)
+#define bfin_write_DMA1_3_START_ADDR(val)    bfin_write32(DMA1_3_START_ADDR,val)
+#define bfin_read_DMA1_3_X_COUNT()           bfin_read16(DMA1_3_X_COUNT)
+#define bfin_write_DMA1_3_X_COUNT(val)       bfin_write16(DMA1_3_X_COUNT,val)
+#define bfin_read_DMA1_3_Y_COUNT()           bfin_read16(DMA1_3_Y_COUNT)
+#define bfin_write_DMA1_3_Y_COUNT(val)       bfin_write16(DMA1_3_Y_COUNT,val)
+#define bfin_read_DMA1_3_X_MODIFY()          bfin_read16(DMA1_3_X_MODIFY)
+#define bfin_write_DMA1_3_X_MODIFY(val)      bfin_write16(DMA1_3_X_MODIFY,val)
+#define bfin_read_DMA1_3_Y_MODIFY()          bfin_read16(DMA1_3_Y_MODIFY)
+#define bfin_write_DMA1_3_Y_MODIFY(val)      bfin_write16(DMA1_3_Y_MODIFY,val)
+#define bfin_read_DMA1_3_CURR_DESC_PTR()     bfin_read32(DMA1_3_CURR_DESC_PTR)
+#define bfin_write_DMA1_3_CURR_DESC_PTR(val) bfin_write32(DMA1_3_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_3_CURR_ADDR()         bfin_read32(DMA1_3_CURR_ADDR)
+#define bfin_write_DMA1_3_CURR_ADDR(val)     bfin_write32(DMA1_3_CURR_ADDR,val)
+#define bfin_read_DMA1_3_CURR_X_COUNT()      bfin_read16(DMA1_3_CURR_X_COUNT)
+#define bfin_write_DMA1_3_CURR_X_COUNT(val)  bfin_write16(DMA1_3_CURR_X_COUNT,val)
+#define bfin_read_DMA1_3_CURR_Y_COUNT()      bfin_read16(DMA1_3_CURR_Y_COUNT)
+#define bfin_write_DMA1_3_CURR_Y_COUNT(val)  bfin_write16(DMA1_3_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_3_IRQ_STATUS()        bfin_read16(DMA1_3_IRQ_STATUS)
+#define bfin_write_DMA1_3_IRQ_STATUS(val)    bfin_write16(DMA1_3_IRQ_STATUS,val)
+#define bfin_read_DMA1_3_PERIPHERAL_MAP()    bfin_read16(DMA1_3_PERIPHERAL_MAP)
+#define bfin_write_DMA1_3_PERIPHERAL_MAP(val) bfin_write16(DMA1_3_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_4_CONFIG()            bfin_read16(DMA1_4_CONFIG)
+#define bfin_write_DMA1_4_CONFIG(val)        bfin_write16(DMA1_4_CONFIG,val)
+#define bfin_read_DMA1_4_NEXT_DESC_PTR()     bfin_read32(DMA1_4_NEXT_DESC_PTR)
+#define bfin_write_DMA1_4_NEXT_DESC_PTR(val) bfin_write32(DMA1_4_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_4_START_ADDR()        bfin_read32(DMA1_4_START_ADDR)
+#define bfin_write_DMA1_4_START_ADDR(val)    bfin_write32(DMA1_4_START_ADDR,val)
+#define bfin_read_DMA1_4_X_COUNT()           bfin_read16(DMA1_4_X_COUNT)
+#define bfin_write_DMA1_4_X_COUNT(val)       bfin_write16(DMA1_4_X_COUNT,val)
+#define bfin_read_DMA1_4_Y_COUNT()           bfin_read16(DMA1_4_Y_COUNT)
+#define bfin_write_DMA1_4_Y_COUNT(val)       bfin_write16(DMA1_4_Y_COUNT,val)
+#define bfin_read_DMA1_4_X_MODIFY()          bfin_read16(DMA1_4_X_MODIFY)
+#define bfin_write_DMA1_4_X_MODIFY(val)      bfin_write16(DMA1_4_X_MODIFY,val)
+#define bfin_read_DMA1_4_Y_MODIFY()          bfin_read16(DMA1_4_Y_MODIFY)
+#define bfin_write_DMA1_4_Y_MODIFY(val)      bfin_write16(DMA1_4_Y_MODIFY,val)
+#define bfin_read_DMA1_4_CURR_DESC_PTR()     bfin_read32(DMA1_4_CURR_DESC_PTR)
+#define bfin_write_DMA1_4_CURR_DESC_PTR(val) bfin_write32(DMA1_4_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_4_CURR_ADDR()         bfin_read32(DMA1_4_CURR_ADDR)
+#define bfin_write_DMA1_4_CURR_ADDR(val)     bfin_write32(DMA1_4_CURR_ADDR,val)
+#define bfin_read_DMA1_4_CURR_X_COUNT()      bfin_read16(DMA1_4_CURR_X_COUNT)
+#define bfin_write_DMA1_4_CURR_X_COUNT(val)  bfin_write16(DMA1_4_CURR_X_COUNT,val)
+#define bfin_read_DMA1_4_CURR_Y_COUNT()      bfin_read16(DMA1_4_CURR_Y_COUNT)
+#define bfin_write_DMA1_4_CURR_Y_COUNT(val)  bfin_write16(DMA1_4_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_4_IRQ_STATUS()        bfin_read16(DMA1_4_IRQ_STATUS)
+#define bfin_write_DMA1_4_IRQ_STATUS(val)    bfin_write16(DMA1_4_IRQ_STATUS,val)
+#define bfin_read_DMA1_4_PERIPHERAL_MAP()    bfin_read16(DMA1_4_PERIPHERAL_MAP)
+#define bfin_write_DMA1_4_PERIPHERAL_MAP(val) bfin_write16(DMA1_4_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_5_CONFIG()            bfin_read16(DMA1_5_CONFIG)
+#define bfin_write_DMA1_5_CONFIG(val)        bfin_write16(DMA1_5_CONFIG,val)
+#define bfin_read_DMA1_5_NEXT_DESC_PTR()     bfin_read32(DMA1_5_NEXT_DESC_PTR)
+#define bfin_write_DMA1_5_NEXT_DESC_PTR(val) bfin_write32(DMA1_5_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_5_START_ADDR()        bfin_read32(DMA1_5_START_ADDR)
+#define bfin_write_DMA1_5_START_ADDR(val)    bfin_write32(DMA1_5_START_ADDR,val)
+#define bfin_read_DMA1_5_X_COUNT()           bfin_read16(DMA1_5_X_COUNT)
+#define bfin_write_DMA1_5_X_COUNT(val)       bfin_write16(DMA1_5_X_COUNT,val)
+#define bfin_read_DMA1_5_Y_COUNT()           bfin_read16(DMA1_5_Y_COUNT)
+#define bfin_write_DMA1_5_Y_COUNT(val)       bfin_write16(DMA1_5_Y_COUNT,val)
+#define bfin_read_DMA1_5_X_MODIFY()          bfin_read16(DMA1_5_X_MODIFY)
+#define bfin_write_DMA1_5_X_MODIFY(val)      bfin_write16(DMA1_5_X_MODIFY,val)
+#define bfin_read_DMA1_5_Y_MODIFY()          bfin_read16(DMA1_5_Y_MODIFY)
+#define bfin_write_DMA1_5_Y_MODIFY(val)      bfin_write16(DMA1_5_Y_MODIFY,val)
+#define bfin_read_DMA1_5_CURR_DESC_PTR()     bfin_read32(DMA1_5_CURR_DESC_PTR)
+#define bfin_write_DMA1_5_CURR_DESC_PTR(val) bfin_write32(DMA1_5_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_5_CURR_ADDR()         bfin_read32(DMA1_5_CURR_ADDR)
+#define bfin_write_DMA1_5_CURR_ADDR(val)     bfin_write32(DMA1_5_CURR_ADDR,val)
+#define bfin_read_DMA1_5_CURR_X_COUNT()      bfin_read16(DMA1_5_CURR_X_COUNT)
+#define bfin_write_DMA1_5_CURR_X_COUNT(val)  bfin_write16(DMA1_5_CURR_X_COUNT,val)
+#define bfin_read_DMA1_5_CURR_Y_COUNT()      bfin_read16(DMA1_5_CURR_Y_COUNT)
+#define bfin_write_DMA1_5_CURR_Y_COUNT(val)  bfin_write16(DMA1_5_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_5_IRQ_STATUS()        bfin_read16(DMA1_5_IRQ_STATUS)
+#define bfin_write_DMA1_5_IRQ_STATUS(val)    bfin_write16(DMA1_5_IRQ_STATUS,val)
+#define bfin_read_DMA1_5_PERIPHERAL_MAP()    bfin_read16(DMA1_5_PERIPHERAL_MAP)
+#define bfin_write_DMA1_5_PERIPHERAL_MAP(val) bfin_write16(DMA1_5_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_6_CONFIG()            bfin_read16(DMA1_6_CONFIG)
+#define bfin_write_DMA1_6_CONFIG(val)        bfin_write16(DMA1_6_CONFIG,val)
+#define bfin_read_DMA1_6_NEXT_DESC_PTR()     bfin_read32(DMA1_6_NEXT_DESC_PTR)
+#define bfin_write_DMA1_6_NEXT_DESC_PTR(val) bfin_write32(DMA1_6_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_6_START_ADDR()        bfin_read32(DMA1_6_START_ADDR)
+#define bfin_write_DMA1_6_START_ADDR(val)    bfin_write32(DMA1_6_START_ADDR,val)
+#define bfin_read_DMA1_6_X_COUNT()           bfin_read16(DMA1_6_X_COUNT)
+#define bfin_write_DMA1_6_X_COUNT(val)       bfin_write16(DMA1_6_X_COUNT,val)
+#define bfin_read_DMA1_6_Y_COUNT()           bfin_read16(DMA1_6_Y_COUNT)
+#define bfin_write_DMA1_6_Y_COUNT(val)       bfin_write16(DMA1_6_Y_COUNT,val)
+#define bfin_read_DMA1_6_X_MODIFY()          bfin_read16(DMA1_6_X_MODIFY)
+#define bfin_write_DMA1_6_X_MODIFY(val)      bfin_write16(DMA1_6_X_MODIFY,val)
+#define bfin_read_DMA1_6_Y_MODIFY()          bfin_read16(DMA1_6_Y_MODIFY)
+#define bfin_write_DMA1_6_Y_MODIFY(val)      bfin_write16(DMA1_6_Y_MODIFY,val)
+#define bfin_read_DMA1_6_CURR_DESC_PTR()     bfin_read32(DMA1_6_CURR_DESC_PTR)
+#define bfin_write_DMA1_6_CURR_DESC_PTR(val) bfin_write32(DMA1_6_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_6_CURR_ADDR()         bfin_read32(DMA1_6_CURR_ADDR)
+#define bfin_write_DMA1_6_CURR_ADDR(val)     bfin_write32(DMA1_6_CURR_ADDR,val)
+#define bfin_read_DMA1_6_CURR_X_COUNT()      bfin_read16(DMA1_6_CURR_X_COUNT)
+#define bfin_write_DMA1_6_CURR_X_COUNT(val)  bfin_write16(DMA1_6_CURR_X_COUNT,val)
+#define bfin_read_DMA1_6_CURR_Y_COUNT()      bfin_read16(DMA1_6_CURR_Y_COUNT)
+#define bfin_write_DMA1_6_CURR_Y_COUNT(val)  bfin_write16(DMA1_6_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_6_IRQ_STATUS()        bfin_read16(DMA1_6_IRQ_STATUS)
+#define bfin_write_DMA1_6_IRQ_STATUS(val)    bfin_write16(DMA1_6_IRQ_STATUS,val)
+#define bfin_read_DMA1_6_PERIPHERAL_MAP()    bfin_read16(DMA1_6_PERIPHERAL_MAP)
+#define bfin_write_DMA1_6_PERIPHERAL_MAP(val) bfin_write16(DMA1_6_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_7_CONFIG()            bfin_read16(DMA1_7_CONFIG)
+#define bfin_write_DMA1_7_CONFIG(val)        bfin_write16(DMA1_7_CONFIG,val)
+#define bfin_read_DMA1_7_NEXT_DESC_PTR()     bfin_read32(DMA1_7_NEXT_DESC_PTR)
+#define bfin_write_DMA1_7_NEXT_DESC_PTR(val) bfin_write32(DMA1_7_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_7_START_ADDR()        bfin_read32(DMA1_7_START_ADDR)
+#define bfin_write_DMA1_7_START_ADDR(val)    bfin_write32(DMA1_7_START_ADDR,val)
+#define bfin_read_DMA1_7_X_COUNT()           bfin_read16(DMA1_7_X_COUNT)
+#define bfin_write_DMA1_7_X_COUNT(val)       bfin_write16(DMA1_7_X_COUNT,val)
+#define bfin_read_DMA1_7_Y_COUNT()           bfin_read16(DMA1_7_Y_COUNT)
+#define bfin_write_DMA1_7_Y_COUNT(val)       bfin_write16(DMA1_7_Y_COUNT,val)
+#define bfin_read_DMA1_7_X_MODIFY()          bfin_read16(DMA1_7_X_MODIFY)
+#define bfin_write_DMA1_7_X_MODIFY(val)      bfin_write16(DMA1_7_X_MODIFY,val)
+#define bfin_read_DMA1_7_Y_MODIFY()          bfin_read16(DMA1_7_Y_MODIFY)
+#define bfin_write_DMA1_7_Y_MODIFY(val)      bfin_write16(DMA1_7_Y_MODIFY,val)
+#define bfin_read_DMA1_7_CURR_DESC_PTR()     bfin_read32(DMA1_7_CURR_DESC_PTR)
+#define bfin_write_DMA1_7_CURR_DESC_PTR(val) bfin_write32(DMA1_7_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_7_CURR_ADDR()         bfin_read32(DMA1_7_CURR_ADDR)
+#define bfin_write_DMA1_7_CURR_ADDR(val)     bfin_write32(DMA1_7_CURR_ADDR,val)
+#define bfin_read_DMA1_7_CURR_X_COUNT()      bfin_read16(DMA1_7_CURR_X_COUNT)
+#define bfin_write_DMA1_7_CURR_X_COUNT(val)  bfin_write16(DMA1_7_CURR_X_COUNT,val)
+#define bfin_read_DMA1_7_CURR_Y_COUNT()      bfin_read16(DMA1_7_CURR_Y_COUNT)
+#define bfin_write_DMA1_7_CURR_Y_COUNT(val)  bfin_write16(DMA1_7_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_7_IRQ_STATUS()        bfin_read16(DMA1_7_IRQ_STATUS)
+#define bfin_write_DMA1_7_IRQ_STATUS(val)    bfin_write16(DMA1_7_IRQ_STATUS,val)
+#define bfin_read_DMA1_7_PERIPHERAL_MAP()    bfin_read16(DMA1_7_PERIPHERAL_MAP)
+#define bfin_write_DMA1_7_PERIPHERAL_MAP(val) bfin_write16(DMA1_7_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_8_CONFIG()            bfin_read16(DMA1_8_CONFIG)
+#define bfin_write_DMA1_8_CONFIG(val)        bfin_write16(DMA1_8_CONFIG,val)
+#define bfin_read_DMA1_8_NEXT_DESC_PTR()     bfin_read32(DMA1_8_NEXT_DESC_PTR)
+#define bfin_write_DMA1_8_NEXT_DESC_PTR(val) bfin_write32(DMA1_8_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_8_START_ADDR()        bfin_read32(DMA1_8_START_ADDR)
+#define bfin_write_DMA1_8_START_ADDR(val)    bfin_write32(DMA1_8_START_ADDR,val)
+#define bfin_read_DMA1_8_X_COUNT()           bfin_read16(DMA1_8_X_COUNT)
+#define bfin_write_DMA1_8_X_COUNT(val)       bfin_write16(DMA1_8_X_COUNT,val)
+#define bfin_read_DMA1_8_Y_COUNT()           bfin_read16(DMA1_8_Y_COUNT)
+#define bfin_write_DMA1_8_Y_COUNT(val)       bfin_write16(DMA1_8_Y_COUNT,val)
+#define bfin_read_DMA1_8_X_MODIFY()          bfin_read16(DMA1_8_X_MODIFY)
+#define bfin_write_DMA1_8_X_MODIFY(val)      bfin_write16(DMA1_8_X_MODIFY,val)
+#define bfin_read_DMA1_8_Y_MODIFY()          bfin_read16(DMA1_8_Y_MODIFY)
+#define bfin_write_DMA1_8_Y_MODIFY(val)      bfin_write16(DMA1_8_Y_MODIFY,val)
+#define bfin_read_DMA1_8_CURR_DESC_PTR()     bfin_read32(DMA1_8_CURR_DESC_PTR)
+#define bfin_write_DMA1_8_CURR_DESC_PTR(val) bfin_write32(DMA1_8_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_8_CURR_ADDR()         bfin_read32(DMA1_8_CURR_ADDR)
+#define bfin_write_DMA1_8_CURR_ADDR(val)     bfin_write32(DMA1_8_CURR_ADDR,val)
+#define bfin_read_DMA1_8_CURR_X_COUNT()      bfin_read16(DMA1_8_CURR_X_COUNT)
+#define bfin_write_DMA1_8_CURR_X_COUNT(val)  bfin_write16(DMA1_8_CURR_X_COUNT,val)
+#define bfin_read_DMA1_8_CURR_Y_COUNT()      bfin_read16(DMA1_8_CURR_Y_COUNT)
+#define bfin_write_DMA1_8_CURR_Y_COUNT(val)  bfin_write16(DMA1_8_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_8_IRQ_STATUS()        bfin_read16(DMA1_8_IRQ_STATUS)
+#define bfin_write_DMA1_8_IRQ_STATUS(val)    bfin_write16(DMA1_8_IRQ_STATUS,val)
+#define bfin_read_DMA1_8_PERIPHERAL_MAP()    bfin_read16(DMA1_8_PERIPHERAL_MAP)
+#define bfin_write_DMA1_8_PERIPHERAL_MAP(val) bfin_write16(DMA1_8_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_9_CONFIG()            bfin_read16(DMA1_9_CONFIG)
+#define bfin_write_DMA1_9_CONFIG(val)        bfin_write16(DMA1_9_CONFIG,val)
+#define bfin_read_DMA1_9_NEXT_DESC_PTR()     bfin_read32(DMA1_9_NEXT_DESC_PTR)
+#define bfin_write_DMA1_9_NEXT_DESC_PTR(val) bfin_write32(DMA1_9_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_9_START_ADDR()        bfin_read32(DMA1_9_START_ADDR)
+#define bfin_write_DMA1_9_START_ADDR(val)    bfin_write32(DMA1_9_START_ADDR,val)
+#define bfin_read_DMA1_9_X_COUNT()           bfin_read16(DMA1_9_X_COUNT)
+#define bfin_write_DMA1_9_X_COUNT(val)       bfin_write16(DMA1_9_X_COUNT,val)
+#define bfin_read_DMA1_9_Y_COUNT()           bfin_read16(DMA1_9_Y_COUNT)
+#define bfin_write_DMA1_9_Y_COUNT(val)       bfin_write16(DMA1_9_Y_COUNT,val)
+#define bfin_read_DMA1_9_X_MODIFY()          bfin_read16(DMA1_9_X_MODIFY)
+#define bfin_write_DMA1_9_X_MODIFY(val)      bfin_write16(DMA1_9_X_MODIFY,val)
+#define bfin_read_DMA1_9_Y_MODIFY()          bfin_read16(DMA1_9_Y_MODIFY)
+#define bfin_write_DMA1_9_Y_MODIFY(val)      bfin_write16(DMA1_9_Y_MODIFY,val)
+#define bfin_read_DMA1_9_CURR_DESC_PTR()     bfin_read32(DMA1_9_CURR_DESC_PTR)
+#define bfin_write_DMA1_9_CURR_DESC_PTR(val) bfin_write32(DMA1_9_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_9_CURR_ADDR()         bfin_read32(DMA1_9_CURR_ADDR)
+#define bfin_write_DMA1_9_CURR_ADDR(val)     bfin_write32(DMA1_9_CURR_ADDR,val)
+#define bfin_read_DMA1_9_CURR_X_COUNT()      bfin_read16(DMA1_9_CURR_X_COUNT)
+#define bfin_write_DMA1_9_CURR_X_COUNT(val)  bfin_write16(DMA1_9_CURR_X_COUNT,val)
+#define bfin_read_DMA1_9_CURR_Y_COUNT()      bfin_read16(DMA1_9_CURR_Y_COUNT)
+#define bfin_write_DMA1_9_CURR_Y_COUNT(val)  bfin_write16(DMA1_9_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_9_IRQ_STATUS()        bfin_read16(DMA1_9_IRQ_STATUS)
+#define bfin_write_DMA1_9_IRQ_STATUS(val)    bfin_write16(DMA1_9_IRQ_STATUS,val)
+#define bfin_read_DMA1_9_PERIPHERAL_MAP()    bfin_read16(DMA1_9_PERIPHERAL_MAP)
+#define bfin_write_DMA1_9_PERIPHERAL_MAP(val) bfin_write16(DMA1_9_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_10_CONFIG()           bfin_read16(DMA1_10_CONFIG)
+#define bfin_write_DMA1_10_CONFIG(val)       bfin_write16(DMA1_10_CONFIG,val)
+#define bfin_read_DMA1_10_NEXT_DESC_PTR()    bfin_read32(DMA1_10_NEXT_DESC_PTR)
+#define bfin_write_DMA1_10_NEXT_DESC_PTR(val) bfin_write32(DMA1_10_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_10_START_ADDR()       bfin_read32(DMA1_10_START_ADDR)
+#define bfin_write_DMA1_10_START_ADDR(val)   bfin_write32(DMA1_10_START_ADDR,val)
+#define bfin_read_DMA1_10_X_COUNT()          bfin_read16(DMA1_10_X_COUNT)
+#define bfin_write_DMA1_10_X_COUNT(val)      bfin_write16(DMA1_10_X_COUNT,val)
+#define bfin_read_DMA1_10_Y_COUNT()          bfin_read16(DMA1_10_Y_COUNT)
+#define bfin_write_DMA1_10_Y_COUNT(val)      bfin_write16(DMA1_10_Y_COUNT,val)
+#define bfin_read_DMA1_10_X_MODIFY()         bfin_read16(DMA1_10_X_MODIFY)
+#define bfin_write_DMA1_10_X_MODIFY(val)     bfin_write16(DMA1_10_X_MODIFY,val)
+#define bfin_read_DMA1_10_Y_MODIFY()         bfin_read16(DMA1_10_Y_MODIFY)
+#define bfin_write_DMA1_10_Y_MODIFY(val)     bfin_write16(DMA1_10_Y_MODIFY,val)
+#define bfin_read_DMA1_10_CURR_DESC_PTR()    bfin_read32(DMA1_10_CURR_DESC_PTR)
+#define bfin_write_DMA1_10_CURR_DESC_PTR(val) bfin_write32(DMA1_10_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_10_CURR_ADDR()        bfin_read32(DMA1_10_CURR_ADDR)
+#define bfin_write_DMA1_10_CURR_ADDR(val)    bfin_write32(DMA1_10_CURR_ADDR,val)
+#define bfin_read_DMA1_10_CURR_X_COUNT()     bfin_read16(DMA1_10_CURR_X_COUNT)
+#define bfin_write_DMA1_10_CURR_X_COUNT(val) bfin_write16(DMA1_10_CURR_X_COUNT,val)
+#define bfin_read_DMA1_10_CURR_Y_COUNT()     bfin_read16(DMA1_10_CURR_Y_COUNT)
+#define bfin_write_DMA1_10_CURR_Y_COUNT(val) bfin_write16(DMA1_10_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_10_IRQ_STATUS()       bfin_read16(DMA1_10_IRQ_STATUS)
+#define bfin_write_DMA1_10_IRQ_STATUS(val)   bfin_write16(DMA1_10_IRQ_STATUS,val)
+#define bfin_read_DMA1_10_PERIPHERAL_MAP()   bfin_read16(DMA1_10_PERIPHERAL_MAP)
+#define bfin_write_DMA1_10_PERIPHERAL_MAP(val) bfin_write16(DMA1_10_PERIPHERAL_MAP,val)
+#define bfin_read_DMA1_11_CONFIG()           bfin_read16(DMA1_11_CONFIG)
+#define bfin_write_DMA1_11_CONFIG(val)       bfin_write16(DMA1_11_CONFIG,val)
+#define bfin_read_DMA1_11_NEXT_DESC_PTR()    bfin_read32(DMA1_11_NEXT_DESC_PTR)
+#define bfin_write_DMA1_11_NEXT_DESC_PTR(val) bfin_write32(DMA1_11_NEXT_DESC_PTR,val)
+#define bfin_read_DMA1_11_START_ADDR()       bfin_read32(DMA1_11_START_ADDR)
+#define bfin_write_DMA1_11_START_ADDR(val)   bfin_write32(DMA1_11_START_ADDR,val)
+#define bfin_read_DMA1_11_X_COUNT()          bfin_read16(DMA1_11_X_COUNT)
+#define bfin_write_DMA1_11_X_COUNT(val)      bfin_write16(DMA1_11_X_COUNT,val)
+#define bfin_read_DMA1_11_Y_COUNT()          bfin_read16(DMA1_11_Y_COUNT)
+#define bfin_write_DMA1_11_Y_COUNT(val)      bfin_write16(DMA1_11_Y_COUNT,val)
+#define bfin_read_DMA1_11_X_MODIFY()         bfin_read16(DMA1_11_X_MODIFY)
+#define bfin_write_DMA1_11_X_MODIFY(val)     bfin_write16(DMA1_11_X_MODIFY,val)
+#define bfin_read_DMA1_11_Y_MODIFY()         bfin_read16(DMA1_11_Y_MODIFY)
+#define bfin_write_DMA1_11_Y_MODIFY(val)     bfin_write16(DMA1_11_Y_MODIFY,val)
+#define bfin_read_DMA1_11_CURR_DESC_PTR()    bfin_read32(DMA1_11_CURR_DESC_PTR)
+#define bfin_write_DMA1_11_CURR_DESC_PTR(val) bfin_write32(DMA1_11_CURR_DESC_PTR,val)
+#define bfin_read_DMA1_11_CURR_ADDR()        bfin_read32(DMA1_11_CURR_ADDR)
+#define bfin_write_DMA1_11_CURR_ADDR(val)    bfin_write32(DMA1_11_CURR_ADDR,val)
+#define bfin_read_DMA1_11_CURR_X_COUNT()     bfin_read16(DMA1_11_CURR_X_COUNT)
+#define bfin_write_DMA1_11_CURR_X_COUNT(val) bfin_write16(DMA1_11_CURR_X_COUNT,val)
+#define bfin_read_DMA1_11_CURR_Y_COUNT()     bfin_read16(DMA1_11_CURR_Y_COUNT)
+#define bfin_write_DMA1_11_CURR_Y_COUNT(val) bfin_write16(DMA1_11_CURR_Y_COUNT,val)
+#define bfin_read_DMA1_11_IRQ_STATUS()       bfin_read16(DMA1_11_IRQ_STATUS)
+#define bfin_write_DMA1_11_IRQ_STATUS(val)   bfin_write16(DMA1_11_IRQ_STATUS,val)
+#define bfin_read_DMA1_11_PERIPHERAL_MAP()   bfin_read16(DMA1_11_PERIPHERAL_MAP)
+#define bfin_write_DMA1_11_PERIPHERAL_MAP(val) bfin_write16(DMA1_11_PERIPHERAL_MAP,val)
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define bfin_read_MDMA1_D0_CONFIG()          bfin_read16(MDMA1_D0_CONFIG)
+#define bfin_write_MDMA1_D0_CONFIG(val)      bfin_write16(MDMA1_D0_CONFIG,val)
+#define bfin_read_MDMA1_D0_NEXT_DESC_PTR()   bfin_read32(MDMA1_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA1_D0_START_ADDR()      bfin_read32(MDMA1_D0_START_ADDR)
+#define bfin_write_MDMA1_D0_START_ADDR(val)  bfin_write32(MDMA1_D0_START_ADDR,val)
+#define bfin_read_MDMA1_D0_X_COUNT()         bfin_read16(MDMA1_D0_X_COUNT)
+#define bfin_write_MDMA1_D0_X_COUNT(val)     bfin_write16(MDMA1_D0_X_COUNT,val)
+#define bfin_read_MDMA1_D0_Y_COUNT()         bfin_read16(MDMA1_D0_Y_COUNT)
+#define bfin_write_MDMA1_D0_Y_COUNT(val)     bfin_write16(MDMA1_D0_Y_COUNT,val)
+#define bfin_read_MDMA1_D0_X_MODIFY()        bfin_read16(MDMA1_D0_X_MODIFY)
+#define bfin_write_MDMA1_D0_X_MODIFY(val)    bfin_write16(MDMA1_D0_X_MODIFY,val)
+#define bfin_read_MDMA1_D0_Y_MODIFY()        bfin_read16(MDMA1_D0_Y_MODIFY)
+#define bfin_write_MDMA1_D0_Y_MODIFY(val)    bfin_write16(MDMA1_D0_Y_MODIFY,val)
+#define bfin_read_MDMA1_D0_CURR_DESC_PTR()   bfin_read32(MDMA1_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D0_CURR_DESC_PTR(val) bfin_write32(MDMA1_D0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA1_D0_CURR_ADDR()       bfin_read32(MDMA1_D0_CURR_ADDR)
+#define bfin_write_MDMA1_D0_CURR_ADDR(val)   bfin_write32(MDMA1_D0_CURR_ADDR,val)
+#define bfin_read_MDMA1_D0_CURR_X_COUNT()    bfin_read16(MDMA1_D0_CURR_X_COUNT)
+#define bfin_write_MDMA1_D0_CURR_X_COUNT(val) bfin_write16(MDMA1_D0_CURR_X_COUNT,val)
+#define bfin_read_MDMA1_D0_CURR_Y_COUNT()    bfin_read16(MDMA1_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D0_CURR_Y_COUNT(val) bfin_write16(MDMA1_D0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA1_D0_IRQ_STATUS()      bfin_read16(MDMA1_D0_IRQ_STATUS)
+#define bfin_write_MDMA1_D0_IRQ_STATUS(val)  bfin_write16(MDMA1_D0_IRQ_STATUS,val)
+#define bfin_read_MDMA1_D0_PERIPHERAL_MAP()  bfin_read16(MDMA1_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA1_S0_CONFIG()          bfin_read16(MDMA1_S0_CONFIG)
+#define bfin_write_MDMA1_S0_CONFIG(val)      bfin_write16(MDMA1_S0_CONFIG,val)
+#define bfin_read_MDMA1_S0_NEXT_DESC_PTR()   bfin_read32(MDMA1_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA1_S0_START_ADDR()      bfin_read32(MDMA1_S0_START_ADDR)
+#define bfin_write_MDMA1_S0_START_ADDR(val)  bfin_write32(MDMA1_S0_START_ADDR,val)
+#define bfin_read_MDMA1_S0_X_COUNT()         bfin_read16(MDMA1_S0_X_COUNT)
+#define bfin_write_MDMA1_S0_X_COUNT(val)     bfin_write16(MDMA1_S0_X_COUNT,val)
+#define bfin_read_MDMA1_S0_Y_COUNT()         bfin_read16(MDMA1_S0_Y_COUNT)
+#define bfin_write_MDMA1_S0_Y_COUNT(val)     bfin_write16(MDMA1_S0_Y_COUNT,val)
+#define bfin_read_MDMA1_S0_X_MODIFY()        bfin_read16(MDMA1_S0_X_MODIFY)
+#define bfin_write_MDMA1_S0_X_MODIFY(val)    bfin_write16(MDMA1_S0_X_MODIFY,val)
+#define bfin_read_MDMA1_S0_Y_MODIFY()        bfin_read16(MDMA1_S0_Y_MODIFY)
+#define bfin_write_MDMA1_S0_Y_MODIFY(val)    bfin_write16(MDMA1_S0_Y_MODIFY,val)
+#define bfin_read_MDMA1_S0_CURR_DESC_PTR()   bfin_read32(MDMA1_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S0_CURR_DESC_PTR(val) bfin_write32(MDMA1_S0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA1_S0_CURR_ADDR()       bfin_read32(MDMA1_S0_CURR_ADDR)
+#define bfin_write_MDMA1_S0_CURR_ADDR(val)   bfin_write32(MDMA1_S0_CURR_ADDR,val)
+#define bfin_read_MDMA1_S0_CURR_X_COUNT()    bfin_read16(MDMA1_S0_CURR_X_COUNT)
+#define bfin_write_MDMA1_S0_CURR_X_COUNT(val) bfin_write16(MDMA1_S0_CURR_X_COUNT,val)
+#define bfin_read_MDMA1_S0_CURR_Y_COUNT()    bfin_read16(MDMA1_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S0_CURR_Y_COUNT(val) bfin_write16(MDMA1_S0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA1_S0_IRQ_STATUS()      bfin_read16(MDMA1_S0_IRQ_STATUS)
+#define bfin_write_MDMA1_S0_IRQ_STATUS(val)  bfin_write16(MDMA1_S0_IRQ_STATUS,val)
+#define bfin_read_MDMA1_S0_PERIPHERAL_MAP()  bfin_read16(MDMA1_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA1_D1_CONFIG()          bfin_read16(MDMA1_D1_CONFIG)
+#define bfin_write_MDMA1_D1_CONFIG(val)      bfin_write16(MDMA1_D1_CONFIG,val)
+#define bfin_read_MDMA1_D1_NEXT_DESC_PTR()   bfin_read32(MDMA1_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_D1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA1_D1_START_ADDR()      bfin_read32(MDMA1_D1_START_ADDR)
+#define bfin_write_MDMA1_D1_START_ADDR(val)  bfin_write32(MDMA1_D1_START_ADDR,val)
+#define bfin_read_MDMA1_D1_X_COUNT()         bfin_read16(MDMA1_D1_X_COUNT)
+#define bfin_write_MDMA1_D1_X_COUNT(val)     bfin_write16(MDMA1_D1_X_COUNT,val)
+#define bfin_read_MDMA1_D1_Y_COUNT()         bfin_read16(MDMA1_D1_Y_COUNT)
+#define bfin_write_MDMA1_D1_Y_COUNT(val)     bfin_write16(MDMA1_D1_Y_COUNT,val)
+#define bfin_read_MDMA1_D1_X_MODIFY()        bfin_read16(MDMA1_D1_X_MODIFY)
+#define bfin_write_MDMA1_D1_X_MODIFY(val)    bfin_write16(MDMA1_D1_X_MODIFY,val)
+#define bfin_read_MDMA1_D1_Y_MODIFY()        bfin_read16(MDMA1_D1_Y_MODIFY)
+#define bfin_write_MDMA1_D1_Y_MODIFY(val)    bfin_write16(MDMA1_D1_Y_MODIFY,val)
+#define bfin_read_MDMA1_D1_CURR_DESC_PTR()   bfin_read32(MDMA1_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_D1_CURR_DESC_PTR(val) bfin_write32(MDMA1_D1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA1_D1_CURR_ADDR()       bfin_read32(MDMA1_D1_CURR_ADDR)
+#define bfin_write_MDMA1_D1_CURR_ADDR(val)   bfin_write32(MDMA1_D1_CURR_ADDR,val)
+#define bfin_read_MDMA1_D1_CURR_X_COUNT()    bfin_read16(MDMA1_D1_CURR_X_COUNT)
+#define bfin_write_MDMA1_D1_CURR_X_COUNT(val) bfin_write16(MDMA1_D1_CURR_X_COUNT,val)
+#define bfin_read_MDMA1_D1_CURR_Y_COUNT()    bfin_read16(MDMA1_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_D1_CURR_Y_COUNT(val) bfin_write16(MDMA1_D1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA1_D1_IRQ_STATUS()      bfin_read16(MDMA1_D1_IRQ_STATUS)
+#define bfin_write_MDMA1_D1_IRQ_STATUS(val)  bfin_write16(MDMA1_D1_IRQ_STATUS,val)
+#define bfin_read_MDMA1_D1_PERIPHERAL_MAP()  bfin_read16(MDMA1_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_D1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA1_S1_CONFIG()          bfin_read16(MDMA1_S1_CONFIG)
+#define bfin_write_MDMA1_S1_CONFIG(val)      bfin_write16(MDMA1_S1_CONFIG,val)
+#define bfin_read_MDMA1_S1_NEXT_DESC_PTR()   bfin_read32(MDMA1_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA1_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA1_S1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA1_S1_START_ADDR()      bfin_read32(MDMA1_S1_START_ADDR)
+#define bfin_write_MDMA1_S1_START_ADDR(val)  bfin_write32(MDMA1_S1_START_ADDR,val)
+#define bfin_read_MDMA1_S1_X_COUNT()         bfin_read16(MDMA1_S1_X_COUNT)
+#define bfin_write_MDMA1_S1_X_COUNT(val)     bfin_write16(MDMA1_S1_X_COUNT,val)
+#define bfin_read_MDMA1_S1_Y_COUNT()         bfin_read16(MDMA1_S1_Y_COUNT)
+#define bfin_write_MDMA1_S1_Y_COUNT(val)     bfin_write16(MDMA1_S1_Y_COUNT,val)
+#define bfin_read_MDMA1_S1_X_MODIFY()        bfin_read16(MDMA1_S1_X_MODIFY)
+#define bfin_write_MDMA1_S1_X_MODIFY(val)    bfin_write16(MDMA1_S1_X_MODIFY,val)
+#define bfin_read_MDMA1_S1_Y_MODIFY()        bfin_read16(MDMA1_S1_Y_MODIFY)
+#define bfin_write_MDMA1_S1_Y_MODIFY(val)    bfin_write16(MDMA1_S1_Y_MODIFY,val)
+#define bfin_read_MDMA1_S1_CURR_DESC_PTR()   bfin_read32(MDMA1_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA1_S1_CURR_DESC_PTR(val) bfin_write32(MDMA1_S1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA1_S1_CURR_ADDR()       bfin_read32(MDMA1_S1_CURR_ADDR)
+#define bfin_write_MDMA1_S1_CURR_ADDR(val)   bfin_write32(MDMA1_S1_CURR_ADDR,val)
+#define bfin_read_MDMA1_S1_CURR_X_COUNT()    bfin_read16(MDMA1_S1_CURR_X_COUNT)
+#define bfin_write_MDMA1_S1_CURR_X_COUNT(val) bfin_write16(MDMA1_S1_CURR_X_COUNT,val)
+#define bfin_read_MDMA1_S1_CURR_Y_COUNT()    bfin_read16(MDMA1_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA1_S1_CURR_Y_COUNT(val) bfin_write16(MDMA1_S1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA1_S1_IRQ_STATUS()      bfin_read16(MDMA1_S1_IRQ_STATUS)
+#define bfin_write_MDMA1_S1_IRQ_STATUS(val)  bfin_write16(MDMA1_S1_IRQ_STATUS,val)
+#define bfin_read_MDMA1_S1_PERIPHERAL_MAP()  bfin_read16(MDMA1_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA1_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA1_S1_PERIPHERAL_MAP,val)
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define bfin_read_DMA2_0_CONFIG()            bfin_read16(DMA2_0_CONFIG)
+#define bfin_write_DMA2_0_CONFIG(val)        bfin_write16(DMA2_0_CONFIG,val)
+#define bfin_read_DMA2_0_NEXT_DESC_PTR()     bfin_read32(DMA2_0_NEXT_DESC_PTR)
+#define bfin_write_DMA2_0_NEXT_DESC_PTR(val) bfin_write32(DMA2_0_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_0_START_ADDR()        bfin_read32(DMA2_0_START_ADDR)
+#define bfin_write_DMA2_0_START_ADDR(val)    bfin_write32(DMA2_0_START_ADDR,val)
+#define bfin_read_DMA2_0_X_COUNT()           bfin_read16(DMA2_0_X_COUNT)
+#define bfin_write_DMA2_0_X_COUNT(val)       bfin_write16(DMA2_0_X_COUNT,val)
+#define bfin_read_DMA2_0_Y_COUNT()           bfin_read16(DMA2_0_Y_COUNT)
+#define bfin_write_DMA2_0_Y_COUNT(val)       bfin_write16(DMA2_0_Y_COUNT,val)
+#define bfin_read_DMA2_0_X_MODIFY()          bfin_read16(DMA2_0_X_MODIFY)
+#define bfin_write_DMA2_0_X_MODIFY(val)      bfin_write16(DMA2_0_X_MODIFY,val)
+#define bfin_read_DMA2_0_Y_MODIFY()          bfin_read16(DMA2_0_Y_MODIFY)
+#define bfin_write_DMA2_0_Y_MODIFY(val)      bfin_write16(DMA2_0_Y_MODIFY,val)
+#define bfin_read_DMA2_0_CURR_DESC_PTR()     bfin_read32(DMA2_0_CURR_DESC_PTR)
+#define bfin_write_DMA2_0_CURR_DESC_PTR(val) bfin_write32(DMA2_0_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_0_CURR_ADDR()         bfin_read32(DMA2_0_CURR_ADDR)
+#define bfin_write_DMA2_0_CURR_ADDR(val)     bfin_write32(DMA2_0_CURR_ADDR,val)
+#define bfin_read_DMA2_0_CURR_X_COUNT()      bfin_read16(DMA2_0_CURR_X_COUNT)
+#define bfin_write_DMA2_0_CURR_X_COUNT(val)  bfin_write16(DMA2_0_CURR_X_COUNT,val)
+#define bfin_read_DMA2_0_CURR_Y_COUNT()      bfin_read16(DMA2_0_CURR_Y_COUNT)
+#define bfin_write_DMA2_0_CURR_Y_COUNT(val)  bfin_write16(DMA2_0_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_0_IRQ_STATUS()        bfin_read16(DMA2_0_IRQ_STATUS)
+#define bfin_write_DMA2_0_IRQ_STATUS(val)    bfin_write16(DMA2_0_IRQ_STATUS,val)
+#define bfin_read_DMA2_0_PERIPHERAL_MAP()    bfin_read16(DMA2_0_PERIPHERAL_MAP)
+#define bfin_write_DMA2_0_PERIPHERAL_MAP(val) bfin_write16(DMA2_0_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_1_CONFIG()            bfin_read16(DMA2_1_CONFIG)
+#define bfin_write_DMA2_1_CONFIG(val)        bfin_write16(DMA2_1_CONFIG,val)
+#define bfin_read_DMA2_1_NEXT_DESC_PTR()     bfin_read32(DMA2_1_NEXT_DESC_PTR)
+#define bfin_write_DMA2_1_NEXT_DESC_PTR(val) bfin_write32(DMA2_1_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_1_START_ADDR()        bfin_read32(DMA2_1_START_ADDR)
+#define bfin_write_DMA2_1_START_ADDR(val)    bfin_write32(DMA2_1_START_ADDR,val)
+#define bfin_read_DMA2_1_X_COUNT()           bfin_read16(DMA2_1_X_COUNT)
+#define bfin_write_DMA2_1_X_COUNT(val)       bfin_write16(DMA2_1_X_COUNT,val)
+#define bfin_read_DMA2_1_Y_COUNT()           bfin_read16(DMA2_1_Y_COUNT)
+#define bfin_write_DMA2_1_Y_COUNT(val)       bfin_write16(DMA2_1_Y_COUNT,val)
+#define bfin_read_DMA2_1_X_MODIFY()          bfin_read16(DMA2_1_X_MODIFY)
+#define bfin_write_DMA2_1_X_MODIFY(val)      bfin_write16(DMA2_1_X_MODIFY,val)
+#define bfin_read_DMA2_1_Y_MODIFY()          bfin_read16(DMA2_1_Y_MODIFY)
+#define bfin_write_DMA2_1_Y_MODIFY(val)      bfin_write16(DMA2_1_Y_MODIFY,val)
+#define bfin_read_DMA2_1_CURR_DESC_PTR()     bfin_read32(DMA2_1_CURR_DESC_PTR)
+#define bfin_write_DMA2_1_CURR_DESC_PTR(val) bfin_write32(DMA2_1_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_1_CURR_ADDR()         bfin_read32(DMA2_1_CURR_ADDR)
+#define bfin_write_DMA2_1_CURR_ADDR(val)     bfin_write32(DMA2_1_CURR_ADDR,val)
+#define bfin_read_DMA2_1_CURR_X_COUNT()      bfin_read16(DMA2_1_CURR_X_COUNT)
+#define bfin_write_DMA2_1_CURR_X_COUNT(val)  bfin_write16(DMA2_1_CURR_X_COUNT,val)
+#define bfin_read_DMA2_1_CURR_Y_COUNT()      bfin_read16(DMA2_1_CURR_Y_COUNT)
+#define bfin_write_DMA2_1_CURR_Y_COUNT(val)  bfin_write16(DMA2_1_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_1_IRQ_STATUS()        bfin_read16(DMA2_1_IRQ_STATUS)
+#define bfin_write_DMA2_1_IRQ_STATUS(val)    bfin_write16(DMA2_1_IRQ_STATUS,val)
+#define bfin_read_DMA2_1_PERIPHERAL_MAP()    bfin_read16(DMA2_1_PERIPHERAL_MAP)
+#define bfin_write_DMA2_1_PERIPHERAL_MAP(val) bfin_write16(DMA2_1_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_2_CONFIG()            bfin_read16(DMA2_2_CONFIG)
+#define bfin_write_DMA2_2_CONFIG(val)        bfin_write16(DMA2_2_CONFIG,val)
+#define bfin_read_DMA2_2_NEXT_DESC_PTR()     bfin_read32(DMA2_2_NEXT_DESC_PTR)
+#define bfin_write_DMA2_2_NEXT_DESC_PTR(val) bfin_write32(DMA2_2_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_2_START_ADDR()        bfin_read32(DMA2_2_START_ADDR)
+#define bfin_write_DMA2_2_START_ADDR(val)    bfin_write32(DMA2_2_START_ADDR,val)
+#define bfin_read_DMA2_2_X_COUNT()           bfin_read16(DMA2_2_X_COUNT)
+#define bfin_write_DMA2_2_X_COUNT(val)       bfin_write16(DMA2_2_X_COUNT,val)
+#define bfin_read_DMA2_2_Y_COUNT()           bfin_read16(DMA2_2_Y_COUNT)
+#define bfin_write_DMA2_2_Y_COUNT(val)       bfin_write16(DMA2_2_Y_COUNT,val)
+#define bfin_read_DMA2_2_X_MODIFY()          bfin_read16(DMA2_2_X_MODIFY)
+#define bfin_write_DMA2_2_X_MODIFY(val)      bfin_write16(DMA2_2_X_MODIFY,val)
+#define bfin_read_DMA2_2_Y_MODIFY()          bfin_read16(DMA2_2_Y_MODIFY)
+#define bfin_write_DMA2_2_Y_MODIFY(val)      bfin_write16(DMA2_2_Y_MODIFY,val)
+#define bfin_read_DMA2_2_CURR_DESC_PTR()     bfin_read32(DMA2_2_CURR_DESC_PTR)
+#define bfin_write_DMA2_2_CURR_DESC_PTR(val) bfin_write32(DMA2_2_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_2_CURR_ADDR()         bfin_read32(DMA2_2_CURR_ADDR)
+#define bfin_write_DMA2_2_CURR_ADDR(val)     bfin_write32(DMA2_2_CURR_ADDR,val)
+#define bfin_read_DMA2_2_CURR_X_COUNT()      bfin_read16(DMA2_2_CURR_X_COUNT)
+#define bfin_write_DMA2_2_CURR_X_COUNT(val)  bfin_write16(DMA2_2_CURR_X_COUNT,val)
+#define bfin_read_DMA2_2_CURR_Y_COUNT()      bfin_read16(DMA2_2_CURR_Y_COUNT)
+#define bfin_write_DMA2_2_CURR_Y_COUNT(val)  bfin_write16(DMA2_2_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_2_IRQ_STATUS()        bfin_read16(DMA2_2_IRQ_STATUS)
+#define bfin_write_DMA2_2_IRQ_STATUS(val)    bfin_write16(DMA2_2_IRQ_STATUS,val)
+#define bfin_read_DMA2_2_PERIPHERAL_MAP()    bfin_read16(DMA2_2_PERIPHERAL_MAP)
+#define bfin_write_DMA2_2_PERIPHERAL_MAP(val) bfin_write16(DMA2_2_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_3_CONFIG()            bfin_read16(DMA2_3_CONFIG)
+#define bfin_write_DMA2_3_CONFIG(val)        bfin_write16(DMA2_3_CONFIG,val)
+#define bfin_read_DMA2_3_NEXT_DESC_PTR()     bfin_read32(DMA2_3_NEXT_DESC_PTR)
+#define bfin_write_DMA2_3_NEXT_DESC_PTR(val) bfin_write32(DMA2_3_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_3_START_ADDR()        bfin_read32(DMA2_3_START_ADDR)
+#define bfin_write_DMA2_3_START_ADDR(val)    bfin_write32(DMA2_3_START_ADDR,val)
+#define bfin_read_DMA2_3_X_COUNT()           bfin_read16(DMA2_3_X_COUNT)
+#define bfin_write_DMA2_3_X_COUNT(val)       bfin_write16(DMA2_3_X_COUNT,val)
+#define bfin_read_DMA2_3_Y_COUNT()           bfin_read16(DMA2_3_Y_COUNT)
+#define bfin_write_DMA2_3_Y_COUNT(val)       bfin_write16(DMA2_3_Y_COUNT,val)
+#define bfin_read_DMA2_3_X_MODIFY()          bfin_read16(DMA2_3_X_MODIFY)
+#define bfin_write_DMA2_3_X_MODIFY(val)      bfin_write16(DMA2_3_X_MODIFY,val)
+#define bfin_read_DMA2_3_Y_MODIFY()          bfin_read16(DMA2_3_Y_MODIFY)
+#define bfin_write_DMA2_3_Y_MODIFY(val)      bfin_write16(DMA2_3_Y_MODIFY,val)
+#define bfin_read_DMA2_3_CURR_DESC_PTR()     bfin_read32(DMA2_3_CURR_DESC_PTR)
+#define bfin_write_DMA2_3_CURR_DESC_PTR(val) bfin_write32(DMA2_3_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_3_CURR_ADDR()         bfin_read32(DMA2_3_CURR_ADDR)
+#define bfin_write_DMA2_3_CURR_ADDR(val)     bfin_write32(DMA2_3_CURR_ADDR,val)
+#define bfin_read_DMA2_3_CURR_X_COUNT()      bfin_read16(DMA2_3_CURR_X_COUNT)
+#define bfin_write_DMA2_3_CURR_X_COUNT(val)  bfin_write16(DMA2_3_CURR_X_COUNT,val)
+#define bfin_read_DMA2_3_CURR_Y_COUNT()      bfin_read16(DMA2_3_CURR_Y_COUNT)
+#define bfin_write_DMA2_3_CURR_Y_COUNT(val)  bfin_write16(DMA2_3_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_3_IRQ_STATUS()        bfin_read16(DMA2_3_IRQ_STATUS)
+#define bfin_write_DMA2_3_IRQ_STATUS(val)    bfin_write16(DMA2_3_IRQ_STATUS,val)
+#define bfin_read_DMA2_3_PERIPHERAL_MAP()    bfin_read16(DMA2_3_PERIPHERAL_MAP)
+#define bfin_write_DMA2_3_PERIPHERAL_MAP(val) bfin_write16(DMA2_3_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_4_CONFIG()            bfin_read16(DMA2_4_CONFIG)
+#define bfin_write_DMA2_4_CONFIG(val)        bfin_write16(DMA2_4_CONFIG,val)
+#define bfin_read_DMA2_4_NEXT_DESC_PTR()     bfin_read32(DMA2_4_NEXT_DESC_PTR)
+#define bfin_write_DMA2_4_NEXT_DESC_PTR(val) bfin_write32(DMA2_4_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_4_START_ADDR()        bfin_read32(DMA2_4_START_ADDR)
+#define bfin_write_DMA2_4_START_ADDR(val)    bfin_write32(DMA2_4_START_ADDR,val)
+#define bfin_read_DMA2_4_X_COUNT()           bfin_read16(DMA2_4_X_COUNT)
+#define bfin_write_DMA2_4_X_COUNT(val)       bfin_write16(DMA2_4_X_COUNT,val)
+#define bfin_read_DMA2_4_Y_COUNT()           bfin_read16(DMA2_4_Y_COUNT)
+#define bfin_write_DMA2_4_Y_COUNT(val)       bfin_write16(DMA2_4_Y_COUNT,val)
+#define bfin_read_DMA2_4_X_MODIFY()          bfin_read16(DMA2_4_X_MODIFY)
+#define bfin_write_DMA2_4_X_MODIFY(val)      bfin_write16(DMA2_4_X_MODIFY,val)
+#define bfin_read_DMA2_4_Y_MODIFY()          bfin_read16(DMA2_4_Y_MODIFY)
+#define bfin_write_DMA2_4_Y_MODIFY(val)      bfin_write16(DMA2_4_Y_MODIFY,val)
+#define bfin_read_DMA2_4_CURR_DESC_PTR()     bfin_read32(DMA2_4_CURR_DESC_PTR)
+#define bfin_write_DMA2_4_CURR_DESC_PTR(val) bfin_write32(DMA2_4_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_4_CURR_ADDR()         bfin_read32(DMA2_4_CURR_ADDR)
+#define bfin_write_DMA2_4_CURR_ADDR(val)     bfin_write32(DMA2_4_CURR_ADDR,val)
+#define bfin_read_DMA2_4_CURR_X_COUNT()      bfin_read16(DMA2_4_CURR_X_COUNT)
+#define bfin_write_DMA2_4_CURR_X_COUNT(val)  bfin_write16(DMA2_4_CURR_X_COUNT,val)
+#define bfin_read_DMA2_4_CURR_Y_COUNT()      bfin_read16(DMA2_4_CURR_Y_COUNT)
+#define bfin_write_DMA2_4_CURR_Y_COUNT(val)  bfin_write16(DMA2_4_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_4_IRQ_STATUS()        bfin_read16(DMA2_4_IRQ_STATUS)
+#define bfin_write_DMA2_4_IRQ_STATUS(val)    bfin_write16(DMA2_4_IRQ_STATUS,val)
+#define bfin_read_DMA2_4_PERIPHERAL_MAP()    bfin_read16(DMA2_4_PERIPHERAL_MAP)
+#define bfin_write_DMA2_4_PERIPHERAL_MAP(val) bfin_write16(DMA2_4_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_5_CONFIG()            bfin_read16(DMA2_5_CONFIG)
+#define bfin_write_DMA2_5_CONFIG(val)        bfin_write16(DMA2_5_CONFIG,val)
+#define bfin_read_DMA2_5_NEXT_DESC_PTR()     bfin_read32(DMA2_5_NEXT_DESC_PTR)
+#define bfin_write_DMA2_5_NEXT_DESC_PTR(val) bfin_write32(DMA2_5_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_5_START_ADDR()        bfin_read32(DMA2_5_START_ADDR)
+#define bfin_write_DMA2_5_START_ADDR(val)    bfin_write32(DMA2_5_START_ADDR,val)
+#define bfin_read_DMA2_5_X_COUNT()           bfin_read16(DMA2_5_X_COUNT)
+#define bfin_write_DMA2_5_X_COUNT(val)       bfin_write16(DMA2_5_X_COUNT,val)
+#define bfin_read_DMA2_5_Y_COUNT()           bfin_read16(DMA2_5_Y_COUNT)
+#define bfin_write_DMA2_5_Y_COUNT(val)       bfin_write16(DMA2_5_Y_COUNT,val)
+#define bfin_read_DMA2_5_X_MODIFY()          bfin_read16(DMA2_5_X_MODIFY)
+#define bfin_write_DMA2_5_X_MODIFY(val)      bfin_write16(DMA2_5_X_MODIFY,val)
+#define bfin_read_DMA2_5_Y_MODIFY()          bfin_read16(DMA2_5_Y_MODIFY)
+#define bfin_write_DMA2_5_Y_MODIFY(val)      bfin_write16(DMA2_5_Y_MODIFY,val)
+#define bfin_read_DMA2_5_CURR_DESC_PTR()     bfin_read32(DMA2_5_CURR_DESC_PTR)
+#define bfin_write_DMA2_5_CURR_DESC_PTR(val) bfin_write32(DMA2_5_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_5_CURR_ADDR()         bfin_read32(DMA2_5_CURR_ADDR)
+#define bfin_write_DMA2_5_CURR_ADDR(val)     bfin_write32(DMA2_5_CURR_ADDR,val)
+#define bfin_read_DMA2_5_CURR_X_COUNT()      bfin_read16(DMA2_5_CURR_X_COUNT)
+#define bfin_write_DMA2_5_CURR_X_COUNT(val)  bfin_write16(DMA2_5_CURR_X_COUNT,val)
+#define bfin_read_DMA2_5_CURR_Y_COUNT()      bfin_read16(DMA2_5_CURR_Y_COUNT)
+#define bfin_write_DMA2_5_CURR_Y_COUNT(val)  bfin_write16(DMA2_5_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_5_IRQ_STATUS()        bfin_read16(DMA2_5_IRQ_STATUS)
+#define bfin_write_DMA2_5_IRQ_STATUS(val)    bfin_write16(DMA2_5_IRQ_STATUS,val)
+#define bfin_read_DMA2_5_PERIPHERAL_MAP()    bfin_read16(DMA2_5_PERIPHERAL_MAP)
+#define bfin_write_DMA2_5_PERIPHERAL_MAP(val) bfin_write16(DMA2_5_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_6_CONFIG()            bfin_read16(DMA2_6_CONFIG)
+#define bfin_write_DMA2_6_CONFIG(val)        bfin_write16(DMA2_6_CONFIG,val)
+#define bfin_read_DMA2_6_NEXT_DESC_PTR()     bfin_read32(DMA2_6_NEXT_DESC_PTR)
+#define bfin_write_DMA2_6_NEXT_DESC_PTR(val) bfin_write32(DMA2_6_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_6_START_ADDR()        bfin_read32(DMA2_6_START_ADDR)
+#define bfin_write_DMA2_6_START_ADDR(val)    bfin_write32(DMA2_6_START_ADDR,val)
+#define bfin_read_DMA2_6_X_COUNT()           bfin_read16(DMA2_6_X_COUNT)
+#define bfin_write_DMA2_6_X_COUNT(val)       bfin_write16(DMA2_6_X_COUNT,val)
+#define bfin_read_DMA2_6_Y_COUNT()           bfin_read16(DMA2_6_Y_COUNT)
+#define bfin_write_DMA2_6_Y_COUNT(val)       bfin_write16(DMA2_6_Y_COUNT,val)
+#define bfin_read_DMA2_6_X_MODIFY()          bfin_read16(DMA2_6_X_MODIFY)
+#define bfin_write_DMA2_6_X_MODIFY(val)      bfin_write16(DMA2_6_X_MODIFY,val)
+#define bfin_read_DMA2_6_Y_MODIFY()          bfin_read16(DMA2_6_Y_MODIFY)
+#define bfin_write_DMA2_6_Y_MODIFY(val)      bfin_write16(DMA2_6_Y_MODIFY,val)
+#define bfin_read_DMA2_6_CURR_DESC_PTR()     bfin_read32(DMA2_6_CURR_DESC_PTR)
+#define bfin_write_DMA2_6_CURR_DESC_PTR(val) bfin_write32(DMA2_6_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_6_CURR_ADDR()         bfin_read32(DMA2_6_CURR_ADDR)
+#define bfin_write_DMA2_6_CURR_ADDR(val)     bfin_write32(DMA2_6_CURR_ADDR,val)
+#define bfin_read_DMA2_6_CURR_X_COUNT()      bfin_read16(DMA2_6_CURR_X_COUNT)
+#define bfin_write_DMA2_6_CURR_X_COUNT(val)  bfin_write16(DMA2_6_CURR_X_COUNT,val)
+#define bfin_read_DMA2_6_CURR_Y_COUNT()      bfin_read16(DMA2_6_CURR_Y_COUNT)
+#define bfin_write_DMA2_6_CURR_Y_COUNT(val)  bfin_write16(DMA2_6_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_6_IRQ_STATUS()        bfin_read16(DMA2_6_IRQ_STATUS)
+#define bfin_write_DMA2_6_IRQ_STATUS(val)    bfin_write16(DMA2_6_IRQ_STATUS,val)
+#define bfin_read_DMA2_6_PERIPHERAL_MAP()    bfin_read16(DMA2_6_PERIPHERAL_MAP)
+#define bfin_write_DMA2_6_PERIPHERAL_MAP(val) bfin_write16(DMA2_6_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_7_CONFIG()            bfin_read16(DMA2_7_CONFIG)
+#define bfin_write_DMA2_7_CONFIG(val)        bfin_write16(DMA2_7_CONFIG,val)
+#define bfin_read_DMA2_7_NEXT_DESC_PTR()     bfin_read32(DMA2_7_NEXT_DESC_PTR)
+#define bfin_write_DMA2_7_NEXT_DESC_PTR(val) bfin_write32(DMA2_7_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_7_START_ADDR()        bfin_read32(DMA2_7_START_ADDR)
+#define bfin_write_DMA2_7_START_ADDR(val)    bfin_write32(DMA2_7_START_ADDR,val)
+#define bfin_read_DMA2_7_X_COUNT()           bfin_read16(DMA2_7_X_COUNT)
+#define bfin_write_DMA2_7_X_COUNT(val)       bfin_write16(DMA2_7_X_COUNT,val)
+#define bfin_read_DMA2_7_Y_COUNT()           bfin_read16(DMA2_7_Y_COUNT)
+#define bfin_write_DMA2_7_Y_COUNT(val)       bfin_write16(DMA2_7_Y_COUNT,val)
+#define bfin_read_DMA2_7_X_MODIFY()          bfin_read16(DMA2_7_X_MODIFY)
+#define bfin_write_DMA2_7_X_MODIFY(val)      bfin_write16(DMA2_7_X_MODIFY,val)
+#define bfin_read_DMA2_7_Y_MODIFY()          bfin_read16(DMA2_7_Y_MODIFY)
+#define bfin_write_DMA2_7_Y_MODIFY(val)      bfin_write16(DMA2_7_Y_MODIFY,val)
+#define bfin_read_DMA2_7_CURR_DESC_PTR()     bfin_read32(DMA2_7_CURR_DESC_PTR)
+#define bfin_write_DMA2_7_CURR_DESC_PTR(val) bfin_write32(DMA2_7_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_7_CURR_ADDR()         bfin_read32(DMA2_7_CURR_ADDR)
+#define bfin_write_DMA2_7_CURR_ADDR(val)     bfin_write32(DMA2_7_CURR_ADDR,val)
+#define bfin_read_DMA2_7_CURR_X_COUNT()      bfin_read16(DMA2_7_CURR_X_COUNT)
+#define bfin_write_DMA2_7_CURR_X_COUNT(val)  bfin_write16(DMA2_7_CURR_X_COUNT,val)
+#define bfin_read_DMA2_7_CURR_Y_COUNT()      bfin_read16(DMA2_7_CURR_Y_COUNT)
+#define bfin_write_DMA2_7_CURR_Y_COUNT(val)  bfin_write16(DMA2_7_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_7_IRQ_STATUS()        bfin_read16(DMA2_7_IRQ_STATUS)
+#define bfin_write_DMA2_7_IRQ_STATUS(val)    bfin_write16(DMA2_7_IRQ_STATUS,val)
+#define bfin_read_DMA2_7_PERIPHERAL_MAP()    bfin_read16(DMA2_7_PERIPHERAL_MAP)
+#define bfin_write_DMA2_7_PERIPHERAL_MAP(val) bfin_write16(DMA2_7_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_8_CONFIG()            bfin_read16(DMA2_8_CONFIG)
+#define bfin_write_DMA2_8_CONFIG(val)        bfin_write16(DMA2_8_CONFIG,val)
+#define bfin_read_DMA2_8_NEXT_DESC_PTR()     bfin_read32(DMA2_8_NEXT_DESC_PTR)
+#define bfin_write_DMA2_8_NEXT_DESC_PTR(val) bfin_write32(DMA2_8_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_8_START_ADDR()        bfin_read32(DMA2_8_START_ADDR)
+#define bfin_write_DMA2_8_START_ADDR(val)    bfin_write32(DMA2_8_START_ADDR,val)
+#define bfin_read_DMA2_8_X_COUNT()           bfin_read16(DMA2_8_X_COUNT)
+#define bfin_write_DMA2_8_X_COUNT(val)       bfin_write16(DMA2_8_X_COUNT,val)
+#define bfin_read_DMA2_8_Y_COUNT()           bfin_read16(DMA2_8_Y_COUNT)
+#define bfin_write_DMA2_8_Y_COUNT(val)       bfin_write16(DMA2_8_Y_COUNT,val)
+#define bfin_read_DMA2_8_X_MODIFY()          bfin_read16(DMA2_8_X_MODIFY)
+#define bfin_write_DMA2_8_X_MODIFY(val)      bfin_write16(DMA2_8_X_MODIFY,val)
+#define bfin_read_DMA2_8_Y_MODIFY()          bfin_read16(DMA2_8_Y_MODIFY)
+#define bfin_write_DMA2_8_Y_MODIFY(val)      bfin_write16(DMA2_8_Y_MODIFY,val)
+#define bfin_read_DMA2_8_CURR_DESC_PTR()     bfin_read32(DMA2_8_CURR_DESC_PTR)
+#define bfin_write_DMA2_8_CURR_DESC_PTR(val) bfin_write32(DMA2_8_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_8_CURR_ADDR()         bfin_read32(DMA2_8_CURR_ADDR)
+#define bfin_write_DMA2_8_CURR_ADDR(val)     bfin_write32(DMA2_8_CURR_ADDR,val)
+#define bfin_read_DMA2_8_CURR_X_COUNT()      bfin_read16(DMA2_8_CURR_X_COUNT)
+#define bfin_write_DMA2_8_CURR_X_COUNT(val)  bfin_write16(DMA2_8_CURR_X_COUNT,val)
+#define bfin_read_DMA2_8_CURR_Y_COUNT()      bfin_read16(DMA2_8_CURR_Y_COUNT)
+#define bfin_write_DMA2_8_CURR_Y_COUNT(val)  bfin_write16(DMA2_8_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_8_IRQ_STATUS()        bfin_read16(DMA2_8_IRQ_STATUS)
+#define bfin_write_DMA2_8_IRQ_STATUS(val)    bfin_write16(DMA2_8_IRQ_STATUS,val)
+#define bfin_read_DMA2_8_PERIPHERAL_MAP()    bfin_read16(DMA2_8_PERIPHERAL_MAP)
+#define bfin_write_DMA2_8_PERIPHERAL_MAP(val) bfin_write16(DMA2_8_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_9_CONFIG()            bfin_read16(DMA2_9_CONFIG)
+#define bfin_write_DMA2_9_CONFIG(val)        bfin_write16(DMA2_9_CONFIG,val)
+#define bfin_read_DMA2_9_NEXT_DESC_PTR()     bfin_read32(DMA2_9_NEXT_DESC_PTR)
+#define bfin_write_DMA2_9_NEXT_DESC_PTR(val) bfin_write32(DMA2_9_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_9_START_ADDR()        bfin_read32(DMA2_9_START_ADDR)
+#define bfin_write_DMA2_9_START_ADDR(val)    bfin_write32(DMA2_9_START_ADDR,val)
+#define bfin_read_DMA2_9_X_COUNT()           bfin_read16(DMA2_9_X_COUNT)
+#define bfin_write_DMA2_9_X_COUNT(val)       bfin_write16(DMA2_9_X_COUNT,val)
+#define bfin_read_DMA2_9_Y_COUNT()           bfin_read16(DMA2_9_Y_COUNT)
+#define bfin_write_DMA2_9_Y_COUNT(val)       bfin_write16(DMA2_9_Y_COUNT,val)
+#define bfin_read_DMA2_9_X_MODIFY()          bfin_read16(DMA2_9_X_MODIFY)
+#define bfin_write_DMA2_9_X_MODIFY(val)      bfin_write16(DMA2_9_X_MODIFY,val)
+#define bfin_read_DMA2_9_Y_MODIFY()          bfin_read16(DMA2_9_Y_MODIFY)
+#define bfin_write_DMA2_9_Y_MODIFY(val)      bfin_write16(DMA2_9_Y_MODIFY,val)
+#define bfin_read_DMA2_9_CURR_DESC_PTR()     bfin_read32(DMA2_9_CURR_DESC_PTR)
+#define bfin_write_DMA2_9_CURR_DESC_PTR(val) bfin_write32(DMA2_9_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_9_CURR_ADDR()         bfin_read32(DMA2_9_CURR_ADDR)
+#define bfin_write_DMA2_9_CURR_ADDR(val)     bfin_write32(DMA2_9_CURR_ADDR,val)
+#define bfin_read_DMA2_9_CURR_X_COUNT()      bfin_read16(DMA2_9_CURR_X_COUNT)
+#define bfin_write_DMA2_9_CURR_X_COUNT(val)  bfin_write16(DMA2_9_CURR_X_COUNT,val)
+#define bfin_read_DMA2_9_CURR_Y_COUNT()      bfin_read16(DMA2_9_CURR_Y_COUNT)
+#define bfin_write_DMA2_9_CURR_Y_COUNT(val)  bfin_write16(DMA2_9_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_9_IRQ_STATUS()        bfin_read16(DMA2_9_IRQ_STATUS)
+#define bfin_write_DMA2_9_IRQ_STATUS(val)    bfin_write16(DMA2_9_IRQ_STATUS,val)
+#define bfin_read_DMA2_9_PERIPHERAL_MAP()    bfin_read16(DMA2_9_PERIPHERAL_MAP)
+#define bfin_write_DMA2_9_PERIPHERAL_MAP(val) bfin_write16(DMA2_9_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_10_CONFIG()           bfin_read16(DMA2_10_CONFIG)
+#define bfin_write_DMA2_10_CONFIG(val)       bfin_write16(DMA2_10_CONFIG,val)
+#define bfin_read_DMA2_10_NEXT_DESC_PTR()    bfin_read32(DMA2_10_NEXT_DESC_PTR)
+#define bfin_write_DMA2_10_NEXT_DESC_PTR(val) bfin_write32(DMA2_10_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_10_START_ADDR()       bfin_read32(DMA2_10_START_ADDR)
+#define bfin_write_DMA2_10_START_ADDR(val)   bfin_write32(DMA2_10_START_ADDR,val)
+#define bfin_read_DMA2_10_X_COUNT()          bfin_read16(DMA2_10_X_COUNT)
+#define bfin_write_DMA2_10_X_COUNT(val)      bfin_write16(DMA2_10_X_COUNT,val)
+#define bfin_read_DMA2_10_Y_COUNT()          bfin_read16(DMA2_10_Y_COUNT)
+#define bfin_write_DMA2_10_Y_COUNT(val)      bfin_write16(DMA2_10_Y_COUNT,val)
+#define bfin_read_DMA2_10_X_MODIFY()         bfin_read16(DMA2_10_X_MODIFY)
+#define bfin_write_DMA2_10_X_MODIFY(val)     bfin_write16(DMA2_10_X_MODIFY,val)
+#define bfin_read_DMA2_10_Y_MODIFY()         bfin_read16(DMA2_10_Y_MODIFY)
+#define bfin_write_DMA2_10_Y_MODIFY(val)     bfin_write16(DMA2_10_Y_MODIFY,val)
+#define bfin_read_DMA2_10_CURR_DESC_PTR()    bfin_read32(DMA2_10_CURR_DESC_PTR)
+#define bfin_write_DMA2_10_CURR_DESC_PTR(val) bfin_write32(DMA2_10_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_10_CURR_ADDR()        bfin_read32(DMA2_10_CURR_ADDR)
+#define bfin_write_DMA2_10_CURR_ADDR(val)    bfin_write32(DMA2_10_CURR_ADDR,val)
+#define bfin_read_DMA2_10_CURR_X_COUNT()     bfin_read16(DMA2_10_CURR_X_COUNT)
+#define bfin_write_DMA2_10_CURR_X_COUNT(val) bfin_write16(DMA2_10_CURR_X_COUNT,val)
+#define bfin_read_DMA2_10_CURR_Y_COUNT()     bfin_read16(DMA2_10_CURR_Y_COUNT)
+#define bfin_write_DMA2_10_CURR_Y_COUNT(val) bfin_write16(DMA2_10_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_10_IRQ_STATUS()       bfin_read16(DMA2_10_IRQ_STATUS)
+#define bfin_write_DMA2_10_IRQ_STATUS(val)   bfin_write16(DMA2_10_IRQ_STATUS,val)
+#define bfin_read_DMA2_10_PERIPHERAL_MAP()   bfin_read16(DMA2_10_PERIPHERAL_MAP)
+#define bfin_write_DMA2_10_PERIPHERAL_MAP(val) bfin_write16(DMA2_10_PERIPHERAL_MAP,val)
+#define bfin_read_DMA2_11_CONFIG()           bfin_read16(DMA2_11_CONFIG)
+#define bfin_write_DMA2_11_CONFIG(val)       bfin_write16(DMA2_11_CONFIG,val)
+#define bfin_read_DMA2_11_NEXT_DESC_PTR()    bfin_read32(DMA2_11_NEXT_DESC_PTR)
+#define bfin_write_DMA2_11_NEXT_DESC_PTR(val) bfin_write32(DMA2_11_NEXT_DESC_PTR,val)
+#define bfin_read_DMA2_11_START_ADDR()       bfin_read32(DMA2_11_START_ADDR)
+#define bfin_write_DMA2_11_START_ADDR(val)   bfin_write32(DMA2_11_START_ADDR,val)
+#define bfin_read_DMA2_11_X_COUNT()          bfin_read16(DMA2_11_X_COUNT)
+#define bfin_write_DMA2_11_X_COUNT(val)      bfin_write16(DMA2_11_X_COUNT,val)
+#define bfin_read_DMA2_11_Y_COUNT()          bfin_read16(DMA2_11_Y_COUNT)
+#define bfin_write_DMA2_11_Y_COUNT(val)      bfin_write16(DMA2_11_Y_COUNT,val)
+#define bfin_read_DMA2_11_X_MODIFY()         bfin_read16(DMA2_11_X_MODIFY)
+#define bfin_write_DMA2_11_X_MODIFY(val)     bfin_write16(DMA2_11_X_MODIFY,val)
+#define bfin_read_DMA2_11_Y_MODIFY()         bfin_read16(DMA2_11_Y_MODIFY)
+#define bfin_write_DMA2_11_Y_MODIFY(val)     bfin_write16(DMA2_11_Y_MODIFY,val)
+#define bfin_read_DMA2_11_CURR_DESC_PTR()    bfin_read32(DMA2_11_CURR_DESC_PTR)
+#define bfin_write_DMA2_11_CURR_DESC_PTR(val) bfin_write32(DMA2_11_CURR_DESC_PTR,val)
+#define bfin_read_DMA2_11_CURR_ADDR()        bfin_read32(DMA2_11_CURR_ADDR)
+#define bfin_write_DMA2_11_CURR_ADDR(val)    bfin_write32(DMA2_11_CURR_ADDR,val)
+#define bfin_read_DMA2_11_CURR_X_COUNT()     bfin_read16(DMA2_11_CURR_X_COUNT)
+#define bfin_write_DMA2_11_CURR_X_COUNT(val) bfin_write16(DMA2_11_CURR_X_COUNT,val)
+#define bfin_read_DMA2_11_CURR_Y_COUNT()     bfin_read16(DMA2_11_CURR_Y_COUNT)
+#define bfin_write_DMA2_11_CURR_Y_COUNT(val) bfin_write16(DMA2_11_CURR_Y_COUNT,val)
+#define bfin_read_DMA2_11_IRQ_STATUS()       bfin_read16(DMA2_11_IRQ_STATUS)
+#define bfin_write_DMA2_11_IRQ_STATUS(val)   bfin_write16(DMA2_11_IRQ_STATUS,val)
+#define bfin_read_DMA2_11_PERIPHERAL_MAP()   bfin_read16(DMA2_11_PERIPHERAL_MAP)
+#define bfin_write_DMA2_11_PERIPHERAL_MAP(val) bfin_write16(DMA2_11_PERIPHERAL_MAP,val)
+/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
+#define bfin_read_MDMA2_D0_CONFIG()          bfin_read16(MDMA2_D0_CONFIG)
+#define bfin_write_MDMA2_D0_CONFIG(val)      bfin_write16(MDMA2_D0_CONFIG,val)
+#define bfin_read_MDMA2_D0_NEXT_DESC_PTR()   bfin_read32(MDMA2_D0_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA2_D0_START_ADDR()      bfin_read32(MDMA2_D0_START_ADDR)
+#define bfin_write_MDMA2_D0_START_ADDR(val)  bfin_write32(MDMA2_D0_START_ADDR,val)
+#define bfin_read_MDMA2_D0_X_COUNT()         bfin_read16(MDMA2_D0_X_COUNT)
+#define bfin_write_MDMA2_D0_X_COUNT(val)     bfin_write16(MDMA2_D0_X_COUNT,val)
+#define bfin_read_MDMA2_D0_Y_COUNT()         bfin_read16(MDMA2_D0_Y_COUNT)
+#define bfin_write_MDMA2_D0_Y_COUNT(val)     bfin_write16(MDMA2_D0_Y_COUNT,val)
+#define bfin_read_MDMA2_D0_X_MODIFY()        bfin_read16(MDMA2_D0_X_MODIFY)
+#define bfin_write_MDMA2_D0_X_MODIFY(val)    bfin_write16(MDMA2_D0_X_MODIFY,val)
+#define bfin_read_MDMA2_D0_Y_MODIFY()        bfin_read16(MDMA2_D0_Y_MODIFY)
+#define bfin_write_MDMA2_D0_Y_MODIFY(val)    bfin_write16(MDMA2_D0_Y_MODIFY,val)
+#define bfin_read_MDMA2_D0_CURR_DESC_PTR()   bfin_read32(MDMA2_D0_CURR_DESC_PTR)
+#define bfin_write_MDMA2_D0_CURR_DESC_PTR(val) bfin_write32(MDMA2_D0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA2_D0_CURR_ADDR()       bfin_read32(MDMA2_D0_CURR_ADDR)
+#define bfin_write_MDMA2_D0_CURR_ADDR(val)   bfin_write32(MDMA2_D0_CURR_ADDR,val)
+#define bfin_read_MDMA2_D0_CURR_X_COUNT()    bfin_read16(MDMA2_D0_CURR_X_COUNT)
+#define bfin_write_MDMA2_D0_CURR_X_COUNT(val) bfin_write16(MDMA2_D0_CURR_X_COUNT,val)
+#define bfin_read_MDMA2_D0_CURR_Y_COUNT()    bfin_read16(MDMA2_D0_CURR_Y_COUNT)
+#define bfin_write_MDMA2_D0_CURR_Y_COUNT(val) bfin_write16(MDMA2_D0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA2_D0_IRQ_STATUS()      bfin_read16(MDMA2_D0_IRQ_STATUS)
+#define bfin_write_MDMA2_D0_IRQ_STATUS(val)  bfin_write16(MDMA2_D0_IRQ_STATUS,val)
+#define bfin_read_MDMA2_D0_PERIPHERAL_MAP()  bfin_read16(MDMA2_D0_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA2_S0_CONFIG()          bfin_read16(MDMA2_S0_CONFIG)
+#define bfin_write_MDMA2_S0_CONFIG(val)      bfin_write16(MDMA2_S0_CONFIG,val)
+#define bfin_read_MDMA2_S0_NEXT_DESC_PTR()   bfin_read32(MDMA2_S0_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S0_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA2_S0_START_ADDR()      bfin_read32(MDMA2_S0_START_ADDR)
+#define bfin_write_MDMA2_S0_START_ADDR(val)  bfin_write32(MDMA2_S0_START_ADDR,val)
+#define bfin_read_MDMA2_S0_X_COUNT()         bfin_read16(MDMA2_S0_X_COUNT)
+#define bfin_write_MDMA2_S0_X_COUNT(val)     bfin_write16(MDMA2_S0_X_COUNT,val)
+#define bfin_read_MDMA2_S0_Y_COUNT()         bfin_read16(MDMA2_S0_Y_COUNT)
+#define bfin_write_MDMA2_S0_Y_COUNT(val)     bfin_write16(MDMA2_S0_Y_COUNT,val)
+#define bfin_read_MDMA2_S0_X_MODIFY()        bfin_read16(MDMA2_S0_X_MODIFY)
+#define bfin_write_MDMA2_S0_X_MODIFY(val)    bfin_write16(MDMA2_S0_X_MODIFY,val)
+#define bfin_read_MDMA2_S0_Y_MODIFY()        bfin_read16(MDMA2_S0_Y_MODIFY)
+#define bfin_write_MDMA2_S0_Y_MODIFY(val)    bfin_write16(MDMA2_S0_Y_MODIFY,val)
+#define bfin_read_MDMA2_S0_CURR_DESC_PTR()   bfin_read32(MDMA2_S0_CURR_DESC_PTR)
+#define bfin_write_MDMA2_S0_CURR_DESC_PTR(val) bfin_write32(MDMA2_S0_CURR_DESC_PTR,val)
+#define bfin_read_MDMA2_S0_CURR_ADDR()       bfin_read32(MDMA2_S0_CURR_ADDR)
+#define bfin_write_MDMA2_S0_CURR_ADDR(val)   bfin_write32(MDMA2_S0_CURR_ADDR,val)
+#define bfin_read_MDMA2_S0_CURR_X_COUNT()    bfin_read16(MDMA2_S0_CURR_X_COUNT)
+#define bfin_write_MDMA2_S0_CURR_X_COUNT(val) bfin_write16(MDMA2_S0_CURR_X_COUNT,val)
+#define bfin_read_MDMA2_S0_CURR_Y_COUNT()    bfin_read16(MDMA2_S0_CURR_Y_COUNT)
+#define bfin_write_MDMA2_S0_CURR_Y_COUNT(val) bfin_write16(MDMA2_S0_CURR_Y_COUNT,val)
+#define bfin_read_MDMA2_S0_IRQ_STATUS()      bfin_read16(MDMA2_S0_IRQ_STATUS)
+#define bfin_write_MDMA2_S0_IRQ_STATUS(val)  bfin_write16(MDMA2_S0_IRQ_STATUS,val)
+#define bfin_read_MDMA2_S0_PERIPHERAL_MAP()  bfin_read16(MDMA2_S0_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S0_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA2_D1_CONFIG()          bfin_read16(MDMA2_D1_CONFIG)
+#define bfin_write_MDMA2_D1_CONFIG(val)      bfin_write16(MDMA2_D1_CONFIG,val)
+#define bfin_read_MDMA2_D1_NEXT_DESC_PTR()   bfin_read32(MDMA2_D1_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_D1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA2_D1_START_ADDR()      bfin_read32(MDMA2_D1_START_ADDR)
+#define bfin_write_MDMA2_D1_START_ADDR(val)  bfin_write32(MDMA2_D1_START_ADDR,val)
+#define bfin_read_MDMA2_D1_X_COUNT()         bfin_read16(MDMA2_D1_X_COUNT)
+#define bfin_write_MDMA2_D1_X_COUNT(val)     bfin_write16(MDMA2_D1_X_COUNT,val)
+#define bfin_read_MDMA2_D1_Y_COUNT()         bfin_read16(MDMA2_D1_Y_COUNT)
+#define bfin_write_MDMA2_D1_Y_COUNT(val)     bfin_write16(MDMA2_D1_Y_COUNT,val)
+#define bfin_read_MDMA2_D1_X_MODIFY()        bfin_read16(MDMA2_D1_X_MODIFY)
+#define bfin_write_MDMA2_D1_X_MODIFY(val)    bfin_write16(MDMA2_D1_X_MODIFY,val)
+#define bfin_read_MDMA2_D1_Y_MODIFY()        bfin_read16(MDMA2_D1_Y_MODIFY)
+#define bfin_write_MDMA2_D1_Y_MODIFY(val)    bfin_write16(MDMA2_D1_Y_MODIFY,val)
+#define bfin_read_MDMA2_D1_CURR_DESC_PTR()   bfin_read32(MDMA2_D1_CURR_DESC_PTR)
+#define bfin_write_MDMA2_D1_CURR_DESC_PTR(val) bfin_write32(MDMA2_D1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA2_D1_CURR_ADDR()       bfin_read32(MDMA2_D1_CURR_ADDR)
+#define bfin_write_MDMA2_D1_CURR_ADDR(val)   bfin_write32(MDMA2_D1_CURR_ADDR,val)
+#define bfin_read_MDMA2_D1_CURR_X_COUNT()    bfin_read16(MDMA2_D1_CURR_X_COUNT)
+#define bfin_write_MDMA2_D1_CURR_X_COUNT(val) bfin_write16(MDMA2_D1_CURR_X_COUNT,val)
+#define bfin_read_MDMA2_D1_CURR_Y_COUNT()    bfin_read16(MDMA2_D1_CURR_Y_COUNT)
+#define bfin_write_MDMA2_D1_CURR_Y_COUNT(val) bfin_write16(MDMA2_D1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA2_D1_IRQ_STATUS()      bfin_read16(MDMA2_D1_IRQ_STATUS)
+#define bfin_write_MDMA2_D1_IRQ_STATUS(val)  bfin_write16(MDMA2_D1_IRQ_STATUS,val)
+#define bfin_read_MDMA2_D1_PERIPHERAL_MAP()  bfin_read16(MDMA2_D1_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_D1_PERIPHERAL_MAP,val)
+#define bfin_read_MDMA2_S1_CONFIG()          bfin_read16(MDMA2_S1_CONFIG)
+#define bfin_write_MDMA2_S1_CONFIG(val)      bfin_write16(MDMA2_S1_CONFIG,val)
+#define bfin_read_MDMA2_S1_NEXT_DESC_PTR()   bfin_read32(MDMA2_S1_NEXT_DESC_PTR)
+#define bfin_write_MDMA2_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA2_S1_NEXT_DESC_PTR,val)
+#define bfin_read_MDMA2_S1_START_ADDR()      bfin_read32(MDMA2_S1_START_ADDR)
+#define bfin_write_MDMA2_S1_START_ADDR(val)  bfin_write32(MDMA2_S1_START_ADDR,val)
+#define bfin_read_MDMA2_S1_X_COUNT()         bfin_read16(MDMA2_S1_X_COUNT)
+#define bfin_write_MDMA2_S1_X_COUNT(val)     bfin_write16(MDMA2_S1_X_COUNT,val)
+#define bfin_read_MDMA2_S1_Y_COUNT()         bfin_read16(MDMA2_S1_Y_COUNT)
+#define bfin_write_MDMA2_S1_Y_COUNT(val)     bfin_write16(MDMA2_S1_Y_COUNT,val)
+#define bfin_read_MDMA2_S1_X_MODIFY()        bfin_read16(MDMA2_S1_X_MODIFY)
+#define bfin_write_MDMA2_S1_X_MODIFY(val)    bfin_write16(MDMA2_S1_X_MODIFY,val)
+#define bfin_read_MDMA2_S1_Y_MODIFY()        bfin_read16(MDMA2_S1_Y_MODIFY)
+#define bfin_write_MDMA2_S1_Y_MODIFY(val)    bfin_write16(MDMA2_S1_Y_MODIFY,val)
+#define bfin_read_MDMA2_S1_CURR_DESC_PTR()   bfin_read32(MDMA2_S1_CURR_DESC_PTR)
+#define bfin_write_MDMA2_S1_CURR_DESC_PTR(val) bfin_write32(MDMA2_S1_CURR_DESC_PTR,val)
+#define bfin_read_MDMA2_S1_CURR_ADDR()       bfin_read32(MDMA2_S1_CURR_ADDR)
+#define bfin_write_MDMA2_S1_CURR_ADDR(val)   bfin_write32(MDMA2_S1_CURR_ADDR,val)
+#define bfin_read_MDMA2_S1_CURR_X_COUNT()    bfin_read16(MDMA2_S1_CURR_X_COUNT)
+#define bfin_write_MDMA2_S1_CURR_X_COUNT(val) bfin_write16(MDMA2_S1_CURR_X_COUNT,val)
+#define bfin_read_MDMA2_S1_CURR_Y_COUNT()    bfin_read16(MDMA2_S1_CURR_Y_COUNT)
+#define bfin_write_MDMA2_S1_CURR_Y_COUNT(val) bfin_write16(MDMA2_S1_CURR_Y_COUNT,val)
+#define bfin_read_MDMA2_S1_IRQ_STATUS()      bfin_read16(MDMA2_S1_IRQ_STATUS)
+#define bfin_write_MDMA2_S1_IRQ_STATUS(val)  bfin_write16(MDMA2_S1_IRQ_STATUS,val)
+#define bfin_read_MDMA2_S1_PERIPHERAL_MAP()  bfin_read16(MDMA2_S1_PERIPHERAL_MAP)
+#define bfin_write_MDMA2_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA2_S1_PERIPHERAL_MAP,val)
+/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
+#define bfin_read_IMDMA_D0_CONFIG()          bfin_read16(IMDMA_D0_CONFIG)
+#define bfin_write_IMDMA_D0_CONFIG(val)      bfin_write16(IMDMA_D0_CONFIG,val)
+#define bfin_read_IMDMA_D0_NEXT_DESC_PTR()   bfin_read32(IMDMA_D0_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_D0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D0_NEXT_DESC_PTR,val)
+#define bfin_read_IMDMA_D0_START_ADDR()      bfin_read32(IMDMA_D0_START_ADDR)
+#define bfin_write_IMDMA_D0_START_ADDR(val)  bfin_write32(IMDMA_D0_START_ADDR,val)
+#define bfin_read_IMDMA_D0_X_COUNT()         bfin_read16(IMDMA_D0_X_COUNT)
+#define bfin_write_IMDMA_D0_X_COUNT(val)     bfin_write16(IMDMA_D0_X_COUNT,val)
+#define bfin_read_IMDMA_D0_Y_COUNT()         bfin_read16(IMDMA_D0_Y_COUNT)
+#define bfin_write_IMDMA_D0_Y_COUNT(val)     bfin_write16(IMDMA_D0_Y_COUNT,val)
+#define bfin_read_IMDMA_D0_X_MODIFY()        bfin_read16(IMDMA_D0_X_MODIFY)
+#define bfin_write_IMDMA_D0_X_MODIFY(val)    bfin_write16(IMDMA_D0_X_MODIFY,val)
+#define bfin_read_IMDMA_D0_Y_MODIFY()        bfin_read16(IMDMA_D0_Y_MODIFY)
+#define bfin_write_IMDMA_D0_Y_MODIFY(val)    bfin_write16(IMDMA_D0_Y_MODIFY,val)
+#define bfin_read_IMDMA_D0_CURR_DESC_PTR()   bfin_read32(IMDMA_D0_CURR_DESC_PTR)
+#define bfin_write_IMDMA_D0_CURR_DESC_PTR(val) bfin_write32(IMDMA_D0_CURR_DESC_PTR,val)
+#define bfin_read_IMDMA_D0_CURR_ADDR()       bfin_read32(IMDMA_D0_CURR_ADDR)
+#define bfin_write_IMDMA_D0_CURR_ADDR(val)   bfin_write32(IMDMA_D0_CURR_ADDR,val)
+#define bfin_read_IMDMA_D0_CURR_X_COUNT()    bfin_read16(IMDMA_D0_CURR_X_COUNT)
+#define bfin_write_IMDMA_D0_CURR_X_COUNT(val) bfin_write16(IMDMA_D0_CURR_X_COUNT,val)
+#define bfin_read_IMDMA_D0_CURR_Y_COUNT()    bfin_read16(IMDMA_D0_CURR_Y_COUNT)
+#define bfin_write_IMDMA_D0_CURR_Y_COUNT(val) bfin_write16(IMDMA_D0_CURR_Y_COUNT,val)
+#define bfin_read_IMDMA_D0_IRQ_STATUS()      bfin_read16(IMDMA_D0_IRQ_STATUS)
+#define bfin_write_IMDMA_D0_IRQ_STATUS(val)  bfin_write16(IMDMA_D0_IRQ_STATUS,val)
+#define bfin_read_IMDMA_S0_CONFIG()          bfin_read16(IMDMA_S0_CONFIG)
+#define bfin_write_IMDMA_S0_CONFIG(val)      bfin_write16(IMDMA_S0_CONFIG,val)
+#define bfin_read_IMDMA_S0_NEXT_DESC_PTR()   bfin_read32(IMDMA_S0_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_S0_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S0_NEXT_DESC_PTR,val)
+#define bfin_read_IMDMA_S0_START_ADDR()      bfin_read32(IMDMA_S0_START_ADDR)
+#define bfin_write_IMDMA_S0_START_ADDR(val)  bfin_write32(IMDMA_S0_START_ADDR,val)
+#define bfin_read_IMDMA_S0_X_COUNT()         bfin_read16(IMDMA_S0_X_COUNT)
+#define bfin_write_IMDMA_S0_X_COUNT(val)     bfin_write16(IMDMA_S0_X_COUNT,val)
+#define bfin_read_IMDMA_S0_Y_COUNT()         bfin_read16(IMDMA_S0_Y_COUNT)
+#define bfin_write_IMDMA_S0_Y_COUNT(val)     bfin_write16(IMDMA_S0_Y_COUNT,val)
+#define bfin_read_IMDMA_S0_X_MODIFY()        bfin_read16(IMDMA_S0_X_MODIFY)
+#define bfin_write_IMDMA_S0_X_MODIFY(val)    bfin_write16(IMDMA_S0_X_MODIFY,val)
+#define bfin_read_IMDMA_S0_Y_MODIFY()        bfin_read16(IMDMA_S0_Y_MODIFY)
+#define bfin_write_IMDMA_S0_Y_MODIFY(val)    bfin_write16(IMDMA_S0_Y_MODIFY,val)
+#define bfin_read_IMDMA_S0_CURR_DESC_PTR()   bfin_read32(IMDMA_S0_CURR_DESC_PTR)
+#define bfin_write_IMDMA_S0_CURR_DESC_PTR(val) bfin_write32(IMDMA_S0_CURR_DESC_PTR,val)
+#define bfin_read_IMDMA_S0_CURR_ADDR()       bfin_read32(IMDMA_S0_CURR_ADDR)
+#define bfin_write_IMDMA_S0_CURR_ADDR(val)   bfin_write32(IMDMA_S0_CURR_ADDR,val)
+#define bfin_read_IMDMA_S0_CURR_X_COUNT()    bfin_read16(IMDMA_S0_CURR_X_COUNT)
+#define bfin_write_IMDMA_S0_CURR_X_COUNT(val) bfin_write16(IMDMA_S0_CURR_X_COUNT,val)
+#define bfin_read_IMDMA_S0_CURR_Y_COUNT()    bfin_read16(IMDMA_S0_CURR_Y_COUNT)
+#define bfin_write_IMDMA_S0_CURR_Y_COUNT(val) bfin_write16(IMDMA_S0_CURR_Y_COUNT,val)
+#define bfin_read_IMDMA_S0_IRQ_STATUS()      bfin_read16(IMDMA_S0_IRQ_STATUS)
+#define bfin_write_IMDMA_S0_IRQ_STATUS(val)  bfin_write16(IMDMA_S0_IRQ_STATUS,val)
+#define bfin_read_IMDMA_D1_CONFIG()          bfin_read16(IMDMA_D1_CONFIG)
+#define bfin_write_IMDMA_D1_CONFIG(val)      bfin_write16(IMDMA_D1_CONFIG,val)
+#define bfin_read_IMDMA_D1_NEXT_DESC_PTR()   bfin_read32(IMDMA_D1_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_D1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_D1_NEXT_DESC_PTR,val)
+#define bfin_read_IMDMA_D1_START_ADDR()      bfin_read32(IMDMA_D1_START_ADDR)
+#define bfin_write_IMDMA_D1_START_ADDR(val)  bfin_write32(IMDMA_D1_START_ADDR,val)
+#define bfin_read_IMDMA_D1_X_COUNT()         bfin_read16(IMDMA_D1_X_COUNT)
+#define bfin_write_IMDMA_D1_X_COUNT(val)     bfin_write16(IMDMA_D1_X_COUNT,val)
+#define bfin_read_IMDMA_D1_Y_COUNT()         bfin_read16(IMDMA_D1_Y_COUNT)
+#define bfin_write_IMDMA_D1_Y_COUNT(val)     bfin_write16(IMDMA_D1_Y_COUNT,val)
+#define bfin_read_IMDMA_D1_X_MODIFY()        bfin_read16(IMDMA_D1_X_MODIFY)
+#define bfin_write_IMDMA_D1_X_MODIFY(val)    bfin_write16(IMDMA_D1_X_MODIFY,val)
+#define bfin_read_IMDMA_D1_Y_MODIFY()        bfin_read16(IMDMA_D1_Y_MODIFY)
+#define bfin_write_IMDMA_D1_Y_MODIFY(val)    bfin_write16(IMDMA_D1_Y_MODIFY,val)
+#define bfin_read_IMDMA_D1_CURR_DESC_PTR()   bfin_read32(IMDMA_D1_CURR_DESC_PTR)
+#define bfin_write_IMDMA_D1_CURR_DESC_PTR(val) bfin_write32(IMDMA_D1_CURR_DESC_PTR,val)
+#define bfin_read_IMDMA_D1_CURR_ADDR()       bfin_read32(IMDMA_D1_CURR_ADDR)
+#define bfin_write_IMDMA_D1_CURR_ADDR(val)   bfin_write32(IMDMA_D1_CURR_ADDR,val)
+#define bfin_read_IMDMA_D1_CURR_X_COUNT()    bfin_read16(IMDMA_D1_CURR_X_COUNT)
+#define bfin_write_IMDMA_D1_CURR_X_COUNT(val) bfin_write16(IMDMA_D1_CURR_X_COUNT,val)
+#define bfin_read_IMDMA_D1_CURR_Y_COUNT()    bfin_read16(IMDMA_D1_CURR_Y_COUNT)
+#define bfin_write_IMDMA_D1_CURR_Y_COUNT(val) bfin_write16(IMDMA_D1_CURR_Y_COUNT,val)
+#define bfin_read_IMDMA_D1_IRQ_STATUS()      bfin_read16(IMDMA_D1_IRQ_STATUS)
+#define bfin_write_IMDMA_D1_IRQ_STATUS(val)  bfin_write16(IMDMA_D1_IRQ_STATUS,val)
+#define bfin_read_IMDMA_S1_CONFIG()          bfin_read16(IMDMA_S1_CONFIG)
+#define bfin_write_IMDMA_S1_CONFIG(val)      bfin_write16(IMDMA_S1_CONFIG,val)
+#define bfin_read_IMDMA_S1_NEXT_DESC_PTR()   bfin_read32(IMDMA_S1_NEXT_DESC_PTR)
+#define bfin_write_IMDMA_S1_NEXT_DESC_PTR(val) bfin_write32(IMDMA_S1_NEXT_DESC_PTR,val)
+#define bfin_read_IMDMA_S1_START_ADDR()      bfin_read32(IMDMA_S1_START_ADDR)
+#define bfin_write_IMDMA_S1_START_ADDR(val)  bfin_write32(IMDMA_S1_START_ADDR,val)
+#define bfin_read_IMDMA_S1_X_COUNT()         bfin_read16(IMDMA_S1_X_COUNT)
+#define bfin_write_IMDMA_S1_X_COUNT(val)     bfin_write16(IMDMA_S1_X_COUNT,val)
+#define bfin_read_IMDMA_S1_Y_COUNT()         bfin_read16(IMDMA_S1_Y_COUNT)
+#define bfin_write_IMDMA_S1_Y_COUNT(val)     bfin_write16(IMDMA_S1_Y_COUNT,val)
+#define bfin_read_IMDMA_S1_X_MODIFY()        bfin_read16(IMDMA_S1_X_MODIFY)
+#define bfin_write_IMDMA_S1_X_MODIFY(val)    bfin_write16(IMDMA_S1_X_MODIFY,val)
+#define bfin_read_IMDMA_S1_Y_MODIFY()        bfin_read16(IMDMA_S1_Y_MODIFY)
+#define bfin_write_IMDMA_S1_Y_MODIFY(val)    bfin_write16(IMDMA_S1_Y_MODIFY,val)
+#define bfin_read_IMDMA_S1_CURR_DESC_PTR()   bfin_read32(IMDMA_S1_CURR_DESC_PTR)
+#define bfin_write_IMDMA_S1_CURR_DESC_PTR(val) bfin_write32(IMDMA_S1_CURR_DESC_PTR,val)
+#define bfin_read_IMDMA_S1_CURR_ADDR()       bfin_read32(IMDMA_S1_CURR_ADDR)
+#define bfin_write_IMDMA_S1_CURR_ADDR(val)   bfin_write32(IMDMA_S1_CURR_ADDR,val)
+#define bfin_read_IMDMA_S1_CURR_X_COUNT()    bfin_read16(IMDMA_S1_CURR_X_COUNT)
+#define bfin_write_IMDMA_S1_CURR_X_COUNT(val) bfin_write16(IMDMA_S1_CURR_X_COUNT,val)
+#define bfin_read_IMDMA_S1_CURR_Y_COUNT()    bfin_read16(IMDMA_S1_CURR_Y_COUNT)
+#define bfin_write_IMDMA_S1_CURR_Y_COUNT(val) bfin_write16(IMDMA_S1_CURR_Y_COUNT,val)
+#define bfin_read_IMDMA_S1_IRQ_STATUS()      bfin_read16(IMDMA_S1_IRQ_STATUS)
+#define bfin_write_IMDMA_S1_IRQ_STATUS(val)  bfin_write16(IMDMA_S1_IRQ_STATUS,val)
+
+#define bfin_read_MDMA_S0_CONFIG()  bfin_read_MDMA1_S0_CONFIG()
+#define bfin_write_MDMA_S0_CONFIG(val) bfin_write_MDMA1_S0_CONFIG(val)
+#define bfin_read_MDMA_S0_IRQ_STATUS()  bfin_read_MDMA1_S0_IRQ_STATUS()
+#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write_MDMA1_S0_IRQ_STATUS(val)
+#define bfin_read_MDMA_S0_X_MODIFY()  bfin_read_MDMA1_S0_X_MODIFY()
+#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write_MDMA1_S0_X_MODIFY(val)
+#define bfin_read_MDMA_S0_Y_MODIFY()  bfin_read_MDMA1_S0_Y_MODIFY()
+#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write_MDMA1_S0_Y_MODIFY(val)
+#define bfin_read_MDMA_S0_X_COUNT()  bfin_read_MDMA1_S0_X_COUNT()
+#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write_MDMA1_S0_X_COUNT(val)
+#define bfin_read_MDMA_S0_Y_COUNT()  bfin_read_MDMA1_S0_Y_COUNT()
+#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write_MDMA1_S0_Y_COUNT(val)
+#define bfin_read_MDMA_S0_START_ADDR()  bfin_read_MDMA1_S0_START_ADDR()
+#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write_MDMA1_S0_START_ADDR(val)
+#define bfin_read_MDMA_D0_CONFIG()  bfin_read_MDMA1_D0_CONFIG()
+#define bfin_write_MDMA_D0_CONFIG(val) bfin_write_MDMA1_D0_CONFIG(val)
+#define bfin_read_MDMA_D0_IRQ_STATUS()  bfin_read_MDMA1_D0_IRQ_STATUS()
+#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write_MDMA1_D0_IRQ_STATUS(val)
+#define bfin_read_MDMA_D0_X_MODIFY()  bfin_read_MDMA1_D0_X_MODIFY()
+#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write_MDMA1_D0_X_MODIFY(val)
+#define bfin_read_MDMA_D0_Y_MODIFY()  bfin_read_MDMA1_D0_Y_MODIFY()
+#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write_MDMA1_D0_Y_MODIFY(val)
+#define bfin_read_MDMA_D0_X_COUNT()  bfin_read_MDMA1_D0_X_COUNT()
+#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write_MDMA1_D0_X_COUNT(val)
+#define bfin_read_MDMA_D0_Y_COUNT()  bfin_read_MDMA1_D0_Y_COUNT()
+#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write_MDMA1_D0_Y_COUNT(val)
+#define bfin_read_MDMA_D0_START_ADDR()  bfin_read_MDMA1_D0_START_ADDR()
+#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write_MDMA1_D0_START_ADDR(val)
+
+#endif                          /* _CDEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/defBF561.h b/include/asm-blackfin/mach-bf561/defBF561.h
new file mode 100644
index 000000000000..a6de4c69ba55
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/defBF561.h
@@ -0,0 +1,1717 @@
+
+/*
+ * File:         include/asm-blackfin/mach-bf561/defBF561.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ * SYSTEM MMR REGISTER AND MEMORY MAP FOR ADSP-BF561
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _DEF_BF561_H
+#define _DEF_BF561_H
+/*
+#if !defined(__ADSPBF561__)
+#warning defBF561.h should only be included for BF561 chip.
+#endif
+*/
+/* include all Core registers and bit definitions */
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/*********************************************************************************** */
+/* System MMR Register Map */
+/*********************************************************************************** */
+
+/* Clock and System Control (0xFFC00000 - 0xFFC000FF) */
+
+#define PLL_CTL                0xFFC00000       /* PLL Control register (16-bit) */
+#define PLL_DIV                         0xFFC00004      /* PLL Divide Register (16-bit) */
+#define VR_CTL                          0xFFC00008      /* Voltage Regulator Control Register (16-bit) */
+#define PLL_STAT               0xFFC0000C       /* PLL Status register (16-bit) */
+#define PLL_LOCKCNT            0xFFC00010       /* PLL Lock Count register (16-bit) */
+#define CHIPID                 0xFFC00014       /* Chip ID Register */
+
+/* System Reset and Interrupt Controller registers for core A (0xFFC0 0100-0xFFC0 01FF) */
+#define SICA_SWRST              0xFFC00100      /* Software Reset register */
+#define SICA_SYSCR              0xFFC00104      /* System Reset Configuration register */
+#define SICA_RVECT              0xFFC00108      /* SIC Reset Vector Address Register */
+#define SICA_IMASK              0xFFC0010C      /* SIC Interrupt Mask register 0 - hack to fix old tests */
+#define SICA_IMASK0             0xFFC0010C      /* SIC Interrupt Mask register 0 */
+#define SICA_IMASK1             0xFFC00110      /* SIC Interrupt Mask register 1 */
+#define SICA_IAR0               0xFFC00124      /* SIC Interrupt Assignment Register 0 */
+#define SICA_IAR1               0xFFC00128      /* SIC Interrupt Assignment Register 1 */
+#define SICA_IAR2               0xFFC0012C      /* SIC Interrupt Assignment Register 2 */
+#define SICA_IAR3               0xFFC00130      /* SIC Interrupt Assignment Register 3 */
+#define SICA_IAR4               0xFFC00134      /* SIC Interrupt Assignment Register 4 */
+#define SICA_IAR5               0xFFC00138      /* SIC Interrupt Assignment Register 5 */
+#define SICA_IAR6               0xFFC0013C      /* SIC Interrupt Assignment Register 6 */
+#define SICA_IAR7               0xFFC00140      /* SIC Interrupt Assignment Register 7 */
+#define SICA_ISR0               0xFFC00114      /* SIC Interrupt Status register 0 */
+#define SICA_ISR1               0xFFC00118      /* SIC Interrupt Status register 1 */
+#define SICA_IWR0               0xFFC0011C      /* SIC Interrupt Wakeup-Enable register 0 */
+#define SICA_IWR1               0xFFC00120      /* SIC Interrupt Wakeup-Enable register 1 */
+
+/* System Reset and Interrupt Controller registers for Core B (0xFFC0 1100-0xFFC0 11FF) */
+#define SICB_SWRST              0xFFC01100      /* reserved */
+#define SICB_SYSCR              0xFFC01104      /* reserved */
+#define SICB_RVECT              0xFFC01108      /* SIC Reset Vector Address Register */
+#define SICB_IMASK0             0xFFC0110C      /* SIC Interrupt Mask register 0 */
+#define SICB_IMASK1             0xFFC01110      /* SIC Interrupt Mask register 1 */
+#define SICB_IAR0               0xFFC01124      /* SIC Interrupt Assignment Register 0 */
+#define SICB_IAR1               0xFFC01128      /* SIC Interrupt Assignment Register 1 */
+#define SICB_IAR2               0xFFC0112C      /* SIC Interrupt Assignment Register 2 */
+#define SICB_IAR3               0xFFC01130      /* SIC Interrupt Assignment Register 3 */
+#define SICB_IAR4               0xFFC01134      /* SIC Interrupt Assignment Register 4 */
+#define SICB_IAR5               0xFFC01138      /* SIC Interrupt Assignment Register 5 */
+#define SICB_IAR6               0xFFC0113C      /* SIC Interrupt Assignment Register 6 */
+#define SICB_IAR7               0xFFC01140      /* SIC Interrupt Assignment Register 7 */
+#define SICB_ISR0               0xFFC01114      /* SIC Interrupt Status register 0 */
+#define SICB_ISR1               0xFFC01118      /* SIC Interrupt Status register 1 */
+#define SICB_IWR0               0xFFC0111C      /* SIC Interrupt Wakeup-Enable register 0 */
+#define SICB_IWR1               0xFFC01120      /* SIC Interrupt Wakeup-Enable register 1 */
+
+/* Watchdog Timer registers for Core A (0xFFC0 0200-0xFFC0 02FF) */
+#define WDOGA_CTL                               0xFFC00200      /* Watchdog Control register */
+#define WDOGA_CNT                               0xFFC00204      /* Watchdog Count register */
+#define WDOGA_STAT                              0xFFC00208      /* Watchdog Status register */
+
+/* Watchdog Timer registers for Core B (0xFFC0 1200-0xFFC0 12FF) */
+#define WDOGB_CTL                               0xFFC01200      /* Watchdog Control register */
+#define WDOGB_CNT                               0xFFC01204      /* Watchdog Count register */
+#define WDOGB_STAT                              0xFFC01208      /* Watchdog Status register */
+
+/* UART Controller (0xFFC00400 - 0xFFC004FF) */
+#define UART_THR                0xFFC00400      /* Transmit Holding register */
+#define UART_RBR                0xFFC00400      /* Receive Buffer register */
+#define UART_DLL                0xFFC00400      /* Divisor Latch (Low-Byte) */
+#define UART_IER                0xFFC00404      /* Interrupt Enable Register */
+#define UART_DLH                0xFFC00404      /* Divisor Latch (High-Byte) */
+#define UART_IIR                0xFFC00408      /* Interrupt Identification Register */
+#define UART_LCR                0xFFC0040C      /* Line Control Register */
+#define UART_MCR                                0xFFC00410      /* Modem Control Register */
+#define UART_LSR                0xFFC00414      /* Line Status Register */
+#define UART_MSR                0xFFC00418      /* Modem Status Register */
+#define UART_SCR                0xFFC0041C      /* SCR Scratch Register */
+#define UART_GCTL               0xFFC00424      /* Global Control Register */
+
+/* SPI Controller (0xFFC00500 - 0xFFC005FF) */
+#define SPI_CTL                         0xFFC00500      /* SPI Control Register */
+#define SPI_FLG                         0xFFC00504      /* SPI Flag register */
+#define SPI_STAT                        0xFFC00508      /* SPI Status register */
+#define SPI_TDBR                        0xFFC0050C      /* SPI Transmit Data Buffer Register */
+#define SPI_RDBR                        0xFFC00510      /* SPI Receive Data Buffer Register */
+#define SPI_BAUD                        0xFFC00514      /* SPI Baud rate Register */
+#define SPI_SHADOW                      0xFFC00518      /* SPI_RDBR Shadow Register */
+
+/* Timer 0-7 registers (0xFFC0 0600-0xFFC0 06FF) */
+#define TIMER0_CONFIG                           0xFFC00600      /* Timer0 Configuration register */
+#define TIMER0_COUNTER                          0xFFC00604      /* Timer0 Counter register */
+#define TIMER0_PERIOD                           0xFFC00608      /* Timer0 Period register */
+#define TIMER0_WIDTH                            0xFFC0060C      /* Timer0 Width register */
+
+#define TIMER1_CONFIG                           0xFFC00610      /* Timer1 Configuration register */
+#define TIMER1_COUNTER                          0xFFC00614      /* Timer1 Counter register */
+#define TIMER1_PERIOD                           0xFFC00618      /* Timer1 Period register */
+#define TIMER1_WIDTH                            0xFFC0061C      /* Timer1 Width register */
+
+#define TIMER2_CONFIG                           0xFFC00620      /* Timer2 Configuration register */
+#define TIMER2_COUNTER                          0xFFC00624      /* Timer2 Counter register */
+#define TIMER2_PERIOD                           0xFFC00628      /* Timer2 Period register */
+#define TIMER2_WIDTH                            0xFFC0062C      /* Timer2 Width register */
+
+#define TIMER3_CONFIG                           0xFFC00630      /* Timer3 Configuration register */
+#define TIMER3_COUNTER                          0xFFC00634      /* Timer3 Counter register */
+#define TIMER3_PERIOD                           0xFFC00638      /* Timer3 Period register */
+#define TIMER3_WIDTH                            0xFFC0063C      /* Timer3 Width register */
+
+#define TIMER4_CONFIG                           0xFFC00640      /* Timer4 Configuration register */
+#define TIMER4_COUNTER                          0xFFC00644      /* Timer4 Counter register */
+#define TIMER4_PERIOD                           0xFFC00648      /* Timer4 Period register */
+#define TIMER4_WIDTH                            0xFFC0064C      /* Timer4 Width register */
+
+#define TIMER5_CONFIG                           0xFFC00650      /* Timer5 Configuration register */
+#define TIMER5_COUNTER                          0xFFC00654      /* Timer5 Counter register */
+#define TIMER5_PERIOD                           0xFFC00658      /* Timer5 Period register */
+#define TIMER5_WIDTH                            0xFFC0065C      /* Timer5 Width register */
+
+#define TIMER6_CONFIG                           0xFFC00660      /* Timer6 Configuration register */
+#define TIMER6_COUNTER                          0xFFC00664      /* Timer6 Counter register */
+#define TIMER6_PERIOD                           0xFFC00668      /* Timer6 Period register */
+#define TIMER6_WIDTH                            0xFFC0066C      /* Timer6 Width register */
+
+#define TIMER7_CONFIG                           0xFFC00670      /* Timer7 Configuration register */
+#define TIMER7_COUNTER                          0xFFC00674      /* Timer7 Counter register */
+#define TIMER7_PERIOD                           0xFFC00678      /* Timer7 Period register */
+#define TIMER7_WIDTH                            0xFFC0067C      /* Timer7 Width register */
+
+#define TMRS8_ENABLE                            0xFFC00680      /* Timer Enable Register */
+#define TMRS8_DISABLE                           0xFFC00684      /* Timer Disable register */
+#define TMRS8_STATUS                            0xFFC00688      /* Timer Status register */
+
+/* Timer registers 8-11 (0xFFC0 1600-0xFFC0 16FF) */
+#define TIMER8_CONFIG                           0xFFC01600      /* Timer8 Configuration register */
+#define TIMER8_COUNTER                          0xFFC01604      /* Timer8 Counter register */
+#define TIMER8_PERIOD                           0xFFC01608      /* Timer8 Period register */
+#define TIMER8_WIDTH                            0xFFC0160C      /* Timer8 Width register */
+
+#define TIMER9_CONFIG                           0xFFC01610      /* Timer9 Configuration register */
+#define TIMER9_COUNTER                          0xFFC01614      /* Timer9 Counter register */
+#define TIMER9_PERIOD                           0xFFC01618      /* Timer9 Period register */
+#define TIMER9_WIDTH                            0xFFC0161C      /* Timer9 Width register */
+
+#define TIMER10_CONFIG                          0xFFC01620      /* Timer10 Configuration register */
+#define TIMER10_COUNTER                         0xFFC01624      /* Timer10 Counter register */
+#define TIMER10_PERIOD                          0xFFC01628      /* Timer10 Period register */
+#define TIMER10_WIDTH                           0xFFC0162C      /* Timer10 Width register */
+
+#define TIMER11_CONFIG                          0xFFC01630      /* Timer11 Configuration register */
+#define TIMER11_COUNTER                         0xFFC01634      /* Timer11 Counter register */
+#define TIMER11_PERIOD                          0xFFC01638      /* Timer11 Period register */
+#define TIMER11_WIDTH                           0xFFC0163C      /* Timer11 Width register */
+
+#define TMRS4_ENABLE                            0xFFC01640      /* Timer Enable Register */
+#define TMRS4_DISABLE                           0xFFC01644      /* Timer Disable register */
+#define TMRS4_STATUS                            0xFFC01648      /* Timer Status register */
+
+/* Programmable Flag 0 registers (0xFFC0 0700-0xFFC0 07FF) */
+#define FIO0_FLAG_D                             0xFFC00700      /* Flag Data register */
+#define FIO0_FLAG_C                             0xFFC00704      /* Flag Clear register */
+#define FIO0_FLAG_S                             0xFFC00708      /* Flag Set register */
+#define FIO0_FLAG_T                             0xFFC0070C      /* Flag Toggle register */
+#define FIO0_MASKA_D                            0xFFC00710      /* Flag Mask Interrupt A Data register */
+#define FIO0_MASKA_C                            0xFFC00714      /* Flag Mask Interrupt A Clear register */
+#define FIO0_MASKA_S                            0xFFC00718      /* Flag Mask Interrupt A Set register */
+#define FIO0_MASKA_T                            0xFFC0071C      /* Flag Mask Interrupt A Toggle register */
+#define FIO0_MASKB_D                            0xFFC00720      /* Flag Mask Interrupt B Data register */
+#define FIO0_MASKB_C                            0xFFC00724      /* Flag Mask Interrupt B Clear register */
+#define FIO0_MASKB_S                            0xFFC00728      /* Flag Mask Interrupt B Set register */
+#define FIO0_MASKB_T                            0xFFC0072C      /* Flag Mask Interrupt B Toggle register */
+#define FIO0_DIR                                        0xFFC00730      /* Flag Direction register */
+#define FIO0_POLAR                                      0xFFC00734      /* Flag Polarity register */
+#define FIO0_EDGE                                       0xFFC00738      /* Flag Interrupt Sensitivity register */
+#define FIO0_BOTH                                       0xFFC0073C      /* Flag Set on Both Edges register */
+#define FIO0_INEN                                       0xFFC00740      /* Flag Input Enable register */
+
+/* Programmable Flag 1 registers (0xFFC0 1500-0xFFC0 15FF) */
+#define FIO1_FLAG_D                             0xFFC01500      /* Flag Data register (mask used to directly */
+#define FIO1_FLAG_C                             0xFFC01504      /* Flag Clear register */
+#define FIO1_FLAG_S                             0xFFC01508      /* Flag Set register */
+#define FIO1_FLAG_T                             0xFFC0150C      /* Flag Toggle register (mask used to */
+#define FIO1_MASKA_D                            0xFFC01510      /* Flag Mask Interrupt A Data register */
+#define FIO1_MASKA_C                            0xFFC01514      /* Flag Mask Interrupt A Clear register */
+#define FIO1_MASKA_S                            0xFFC01518      /* Flag Mask Interrupt A Set register */
+#define FIO1_MASKA_T                            0xFFC0151C      /* Flag Mask Interrupt A Toggle register */
+#define FIO1_MASKB_D                            0xFFC01520      /* Flag Mask Interrupt B Data register */
+#define FIO1_MASKB_C                            0xFFC01524      /* Flag Mask Interrupt B Clear register */
+#define FIO1_MASKB_S                            0xFFC01528      /* Flag Mask Interrupt B Set register */
+#define FIO1_MASKB_T                            0xFFC0152C      /* Flag Mask Interrupt B Toggle register */
+#define FIO1_DIR                                        0xFFC01530      /* Flag Direction register */
+#define FIO1_POLAR                                      0xFFC01534      /* Flag Polarity register */
+#define FIO1_EDGE                                       0xFFC01538      /* Flag Interrupt Sensitivity register */
+#define FIO1_BOTH                                       0xFFC0153C      /* Flag Set on Both Edges register */
+#define FIO1_INEN                                       0xFFC01540      /* Flag Input Enable register */
+
+/* Programmable Flag registers (0xFFC0 1700-0xFFC0 17FF) */
+#define FIO2_FLAG_D                             0xFFC01700      /* Flag Data register (mask used to directly */
+#define FIO2_FLAG_C                             0xFFC01704      /* Flag Clear register */
+#define FIO2_FLAG_S                             0xFFC01708      /* Flag Set register */
+#define FIO2_FLAG_T                             0xFFC0170C      /* Flag Toggle register (mask used to */
+#define FIO2_MASKA_D                            0xFFC01710      /* Flag Mask Interrupt A Data register */
+#define FIO2_MASKA_C                            0xFFC01714      /* Flag Mask Interrupt A Clear register */
+#define FIO2_MASKA_S                            0xFFC01718      /* Flag Mask Interrupt A Set register */
+#define FIO2_MASKA_T                            0xFFC0171C      /* Flag Mask Interrupt A Toggle register */
+#define FIO2_MASKB_D                            0xFFC01720      /* Flag Mask Interrupt B Data register */
+#define FIO2_MASKB_C                            0xFFC01724      /* Flag Mask Interrupt B Clear register */
+#define FIO2_MASKB_S                            0xFFC01728      /* Flag Mask Interrupt B Set register */
+#define FIO2_MASKB_T                            0xFFC0172C      /* Flag Mask Interrupt B Toggle register */
+#define FIO2_DIR                                        0xFFC01730      /* Flag Direction register */
+#define FIO2_POLAR                                      0xFFC01734      /* Flag Polarity register */
+#define FIO2_EDGE                                       0xFFC01738      /* Flag Interrupt Sensitivity register */
+#define FIO2_BOTH                                       0xFFC0173C      /* Flag Set on Both Edges register */
+#define FIO2_INEN                                       0xFFC01740      /* Flag Input Enable register */
+
+/* SPORT0 Controller (0xFFC00800 - 0xFFC008FF) */
+#define SPORT0_TCR1                     0xFFC00800      /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_TCR2                     0xFFC00804      /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_TCLKDIV                  0xFFC00808      /* SPORT0 Transmit Clock Divider */
+#define SPORT0_TFSDIV                   0xFFC0080C      /* SPORT0 Transmit Frame Sync Divider */
+#define SPORT0_TX                       0xFFC00810      /* SPORT0 TX Data Register */
+#define SPORT0_RX                       0xFFC00818      /* SPORT0 RX Data Register */
+#define SPORT0_RCR1                             0xFFC00820      /* SPORT0 Transmit Configuration 1 Register */
+#define SPORT0_RCR2                             0xFFC00824      /* SPORT0 Transmit Configuration 2 Register */
+#define SPORT0_RCLKDIV                  0xFFC00828      /* SPORT0 Receive Clock Divider */
+#define SPORT0_RFSDIV                   0xFFC0082C      /* SPORT0 Receive Frame Sync Divider */
+#define SPORT0_STAT                     0xFFC00830      /* SPORT0 Status Register */
+#define SPORT0_CHNL                     0xFFC00834      /* SPORT0 Current Channel Register */
+#define SPORT0_MCMC1                    0xFFC00838      /* SPORT0 Multi-Channel Configuration Register 1 */
+#define SPORT0_MCMC2                    0xFFC0083C      /* SPORT0 Multi-Channel Configuration Register 2 */
+#define SPORT0_MTCS0                    0xFFC00840      /* SPORT0 Multi-Channel Transmit Select Register 0 */
+#define SPORT0_MTCS1                    0xFFC00844      /* SPORT0 Multi-Channel Transmit Select Register 1 */
+#define SPORT0_MTCS2                    0xFFC00848      /* SPORT0 Multi-Channel Transmit Select Register 2 */
+#define SPORT0_MTCS3                    0xFFC0084C      /* SPORT0 Multi-Channel Transmit Select Register 3 */
+#define SPORT0_MRCS0                    0xFFC00850      /* SPORT0 Multi-Channel Receive Select Register 0 */
+#define SPORT0_MRCS1                    0xFFC00854      /* SPORT0 Multi-Channel Receive Select Register 1 */
+#define SPORT0_MRCS2                    0xFFC00858      /* SPORT0 Multi-Channel Receive Select Register 2 */
+#define SPORT0_MRCS3                    0xFFC0085C      /* SPORT0 Multi-Channel Receive Select Register 3 */
+
+/* SPORT1 Controller (0xFFC00900 - 0xFFC009FF) */
+#define SPORT1_TCR1                             0xFFC00900      /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_TCR2                             0xFFC00904      /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_TCLKDIV                  0xFFC00908      /* SPORT1 Transmit Clock Divider */
+#define SPORT1_TFSDIV                   0xFFC0090C      /* SPORT1 Transmit Frame Sync Divider */
+#define SPORT1_TX                       0xFFC00910      /* SPORT1 TX Data Register */
+#define SPORT1_RX                       0xFFC00918      /* SPORT1 RX Data Register */
+#define SPORT1_RCR1                             0xFFC00920      /* SPORT1 Transmit Configuration 1 Register */
+#define SPORT1_RCR2                             0xFFC00924      /* SPORT1 Transmit Configuration 2 Register */
+#define SPORT1_RCLKDIV                  0xFFC00928      /* SPORT1 Receive Clock Divider */
+#define SPORT1_RFSDIV                   0xFFC0092C      /* SPORT1 Receive Frame Sync Divider */
+#define SPORT1_STAT                     0xFFC00930      /* SPORT1 Status Register */
+#define SPORT1_CHNL                     0xFFC00934      /* SPORT1 Current Channel Register */
+#define SPORT1_MCMC1                    0xFFC00938      /* SPORT1 Multi-Channel Configuration Register 1 */
+#define SPORT1_MCMC2                    0xFFC0093C      /* SPORT1 Multi-Channel Configuration Register 2 */
+#define SPORT1_MTCS0                    0xFFC00940      /* SPORT1 Multi-Channel Transmit Select Register 0 */
+#define SPORT1_MTCS1                    0xFFC00944      /* SPORT1 Multi-Channel Transmit Select Register 1 */
+#define SPORT1_MTCS2                    0xFFC00948      /* SPORT1 Multi-Channel Transmit Select Register 2 */
+#define SPORT1_MTCS3                    0xFFC0094C      /* SPORT1 Multi-Channel Transmit Select Register 3 */
+#define SPORT1_MRCS0                    0xFFC00950      /* SPORT1 Multi-Channel Receive Select Register 0 */
+#define SPORT1_MRCS1                    0xFFC00954      /* SPORT1 Multi-Channel Receive Select Register 1 */
+#define SPORT1_MRCS2                    0xFFC00958      /* SPORT1 Multi-Channel Receive Select Register 2 */
+#define SPORT1_MRCS3                    0xFFC0095C      /* SPORT1 Multi-Channel Receive Select Register 3 */
+
+/* Asynchronous Memory Controller - External Bus Interface Unit  */
+#define EBIU_AMGCTL                                     0xFFC00A00      /* Asynchronous Memory Global Control Register */
+#define EBIU_AMBCTL0                            0xFFC00A04      /* Asynchronous Memory Bank Control Register 0 */
+#define EBIU_AMBCTL1                            0xFFC00A08      /* Asynchronous Memory Bank Control Register 1 */
+
+/* SDRAM Controller External Bus Interface Unit (0xFFC00A00 - 0xFFC00AFF) */
+#define EBIU_SDGCTL                                     0xFFC00A10      /* SDRAM Global Control Register */
+#define EBIU_SDBCTL                                     0xFFC00A14      /* SDRAM Bank Control Register */
+#define EBIU_SDRRC                                      0xFFC00A18      /* SDRAM Refresh Rate Control Register */
+#define EBIU_SDSTAT                                     0xFFC00A1C      /* SDRAM Status Register */
+
+/* Parallel Peripheral Interface (PPI) 0 registers (0xFFC0 1000-0xFFC0 10FF) */
+#define PPI0_CONTROL                            0xFFC01000      /* PPI0 Control register */
+#define PPI0_STATUS                             0xFFC01004      /* PPI0 Status register */
+#define PPI0_COUNT                                      0xFFC01008      /* PPI0 Transfer Count register */
+#define PPI0_DELAY                                      0xFFC0100C      /* PPI0 Delay Count register */
+#define PPI0_FRAME                                      0xFFC01010      /* PPI0 Frame Length register */
+
+/*Parallel Peripheral Interface (PPI) 1 registers (0xFFC0 1300-0xFFC0 13FF) */
+#define PPI1_CONTROL                            0xFFC01300      /* PPI1 Control register */
+#define PPI1_STATUS                             0xFFC01304      /* PPI1 Status register */
+#define PPI1_COUNT                                      0xFFC01308      /* PPI1 Transfer Count register */
+#define PPI1_DELAY                                      0xFFC0130C      /* PPI1 Delay Count register */
+#define PPI1_FRAME                                      0xFFC01310      /* PPI1 Frame Length register */
+
+/*DMA traffic control registers */
+#define DMA1_TC_PER  0xFFC01B0C /* Traffic control periods */
+#define DMA1_TC_CNT  0xFFC01B10 /* Traffic control current counts */
+#define DMA2_TC_PER  0xFFC00B0C /* Traffic control periods */
+#define DMA2_TC_CNT  0xFFC00B10 /* Traffic control current counts        */
+
+/* DMA1 Controller registers (0xFFC0 1C00-0xFFC0 1FFF) */
+#define DMA1_0_CONFIG 0xFFC01C08        /* DMA1 Channel 0 Configuration register */
+#define DMA1_0_NEXT_DESC_PTR 0xFFC01C00 /* DMA1 Channel 0 Next Descripter Ptr Reg */
+#define DMA1_0_START_ADDR 0xFFC01C04    /* DMA1 Channel 0 Start Address */
+#define DMA1_0_X_COUNT 0xFFC01C10       /* DMA1 Channel 0 Inner Loop Count */
+#define DMA1_0_Y_COUNT 0xFFC01C18       /* DMA1 Channel 0 Outer Loop Count */
+#define DMA1_0_X_MODIFY 0xFFC01C14      /* DMA1 Channel 0 Inner Loop Addr Increment */
+#define DMA1_0_Y_MODIFY 0xFFC01C1C      /* DMA1 Channel 0 Outer Loop Addr Increment */
+#define DMA1_0_CURR_DESC_PTR 0xFFC01C20 /* DMA1 Channel 0 Current Descriptor Pointer */
+#define DMA1_0_CURR_ADDR 0xFFC01C24     /* DMA1 Channel 0 Current Address Pointer */
+#define DMA1_0_CURR_X_COUNT 0xFFC01C30  /* DMA1 Channel 0 Current Inner Loop Count */
+#define DMA1_0_CURR_Y_COUNT 0xFFC01C38  /* DMA1 Channel 0 Current Outer Loop Count */
+#define DMA1_0_IRQ_STATUS 0xFFC01C28    /* DMA1 Channel 0 Interrupt/Status Register */
+#define DMA1_0_PERIPHERAL_MAP 0xFFC01C2C        /* DMA1 Channel 0 Peripheral Map Register */
+
+#define DMA1_1_CONFIG 0xFFC01C48        /* DMA1 Channel 1 Configuration register */
+#define DMA1_1_NEXT_DESC_PTR 0xFFC01C40 /* DMA1 Channel 1 Next Descripter Ptr Reg */
+#define DMA1_1_START_ADDR 0xFFC01C44    /* DMA1 Channel 1 Start Address */
+#define DMA1_1_X_COUNT 0xFFC01C50       /* DMA1 Channel 1 Inner Loop Count */
+#define DMA1_1_Y_COUNT 0xFFC01C58       /* DMA1 Channel 1 Outer Loop Count */
+#define DMA1_1_X_MODIFY 0xFFC01C54      /* DMA1 Channel 1 Inner Loop Addr Increment */
+#define DMA1_1_Y_MODIFY 0xFFC01C5C      /* DMA1 Channel 1 Outer Loop Addr Increment */
+#define DMA1_1_CURR_DESC_PTR 0xFFC01C60 /* DMA1 Channel 1 Current Descriptor Pointer */
+#define DMA1_1_CURR_ADDR 0xFFC01C64     /* DMA1 Channel 1 Current Address Pointer */
+#define DMA1_1_CURR_X_COUNT 0xFFC01C70  /* DMA1 Channel 1 Current Inner Loop Count */
+#define DMA1_1_CURR_Y_COUNT 0xFFC01C78  /* DMA1 Channel 1 Current Outer Loop Count */
+#define DMA1_1_IRQ_STATUS 0xFFC01C68    /* DMA1 Channel 1 Interrupt/Status Register */
+#define DMA1_1_PERIPHERAL_MAP 0xFFC01C6C        /* DMA1 Channel 1 Peripheral Map Register */
+
+#define DMA1_2_CONFIG 0xFFC01C88        /* DMA1 Channel 2 Configuration register */
+#define DMA1_2_NEXT_DESC_PTR 0xFFC01C80 /* DMA1 Channel 2 Next Descripter Ptr Reg */
+#define DMA1_2_START_ADDR 0xFFC01C84    /* DMA1 Channel 2 Start Address */
+#define DMA1_2_X_COUNT 0xFFC01C90       /* DMA1 Channel 2 Inner Loop Count */
+#define DMA1_2_Y_COUNT 0xFFC01C98       /* DMA1 Channel 2 Outer Loop Count */
+#define DMA1_2_X_MODIFY 0xFFC01C94      /* DMA1 Channel 2 Inner Loop Addr Increment */
+#define DMA1_2_Y_MODIFY 0xFFC01C9C      /* DMA1 Channel 2 Outer Loop Addr Increment */
+#define DMA1_2_CURR_DESC_PTR 0xFFC01CA0 /* DMA1 Channel 2 Current Descriptor Pointer */
+#define DMA1_2_CURR_ADDR 0xFFC01CA4     /* DMA1 Channel 2 Current Address Pointer */
+#define DMA1_2_CURR_X_COUNT 0xFFC01CB0  /* DMA1 Channel 2 Current Inner Loop Count */
+#define DMA1_2_CURR_Y_COUNT 0xFFC01CB8  /* DMA1 Channel 2 Current Outer Loop Count */
+#define DMA1_2_IRQ_STATUS 0xFFC01CA8    /* DMA1 Channel 2 Interrupt/Status Register */
+#define DMA1_2_PERIPHERAL_MAP 0xFFC01CAC        /* DMA1 Channel 2 Peripheral Map Register */
+
+#define DMA1_3_CONFIG 0xFFC01CC8        /* DMA1 Channel 3 Configuration register */
+#define DMA1_3_NEXT_DESC_PTR 0xFFC01CC0 /* DMA1 Channel 3 Next Descripter Ptr Reg */
+#define DMA1_3_START_ADDR 0xFFC01CC4    /* DMA1 Channel 3 Start Address */
+#define DMA1_3_X_COUNT 0xFFC01CD0       /* DMA1 Channel 3 Inner Loop Count */
+#define DMA1_3_Y_COUNT 0xFFC01CD8       /* DMA1 Channel 3 Outer Loop Count */
+#define DMA1_3_X_MODIFY 0xFFC01CD4      /* DMA1 Channel 3 Inner Loop Addr Increment */
+#define DMA1_3_Y_MODIFY 0xFFC01CDC      /* DMA1 Channel 3 Outer Loop Addr Increment */
+#define DMA1_3_CURR_DESC_PTR 0xFFC01CE0 /* DMA1 Channel 3 Current Descriptor Pointer */
+#define DMA1_3_CURR_ADDR 0xFFC01CE4     /* DMA1 Channel 3 Current Address Pointer */
+#define DMA1_3_CURR_X_COUNT 0xFFC01CF0  /* DMA1 Channel 3 Current Inner Loop Count */
+#define DMA1_3_CURR_Y_COUNT 0xFFC01CF8  /* DMA1 Channel 3 Current Outer Loop Count */
+#define DMA1_3_IRQ_STATUS 0xFFC01CE8    /* DMA1 Channel 3 Interrupt/Status Register */
+#define DMA1_3_PERIPHERAL_MAP 0xFFC01CEC        /* DMA1 Channel 3 Peripheral Map Register */
+
+#define DMA1_4_CONFIG 0xFFC01D08        /* DMA1 Channel 4 Configuration register */
+#define DMA1_4_NEXT_DESC_PTR 0xFFC01D00 /* DMA1 Channel 4 Next Descripter Ptr Reg */
+#define DMA1_4_START_ADDR 0xFFC01D04    /* DMA1 Channel 4 Start Address */
+#define DMA1_4_X_COUNT 0xFFC01D10       /* DMA1 Channel 4 Inner Loop Count */
+#define DMA1_4_Y_COUNT 0xFFC01D18       /* DMA1 Channel 4 Outer Loop Count */
+#define DMA1_4_X_MODIFY 0xFFC01D14      /* DMA1 Channel 4 Inner Loop Addr Increment */
+#define DMA1_4_Y_MODIFY 0xFFC01D1C      /* DMA1 Channel 4 Outer Loop Addr Increment */
+#define DMA1_4_CURR_DESC_PTR 0xFFC01D20 /* DMA1 Channel 4 Current Descriptor Pointer */
+#define DMA1_4_CURR_ADDR 0xFFC01D24     /* DMA1 Channel 4 Current Address Pointer */
+#define DMA1_4_CURR_X_COUNT 0xFFC01D30  /* DMA1 Channel 4 Current Inner Loop Count */
+#define DMA1_4_CURR_Y_COUNT 0xFFC01D38  /* DMA1 Channel 4 Current Outer Loop Count */
+#define DMA1_4_IRQ_STATUS 0xFFC01D28    /* DMA1 Channel 4 Interrupt/Status Register */
+#define DMA1_4_PERIPHERAL_MAP 0xFFC01D2C        /* DMA1 Channel 4 Peripheral Map Register */
+
+#define DMA1_5_CONFIG 0xFFC01D48        /* DMA1 Channel 5 Configuration register */
+#define DMA1_5_NEXT_DESC_PTR 0xFFC01D40 /* DMA1 Channel 5 Next Descripter Ptr Reg */
+#define DMA1_5_START_ADDR 0xFFC01D44    /* DMA1 Channel 5 Start Address */
+#define DMA1_5_X_COUNT 0xFFC01D50       /* DMA1 Channel 5 Inner Loop Count */
+#define DMA1_5_Y_COUNT 0xFFC01D58       /* DMA1 Channel 5 Outer Loop Count */
+#define DMA1_5_X_MODIFY 0xFFC01D54      /* DMA1 Channel 5 Inner Loop Addr Increment */
+#define DMA1_5_Y_MODIFY 0xFFC01D5C      /* DMA1 Channel 5 Outer Loop Addr Increment */
+#define DMA1_5_CURR_DESC_PTR 0xFFC01D60 /* DMA1 Channel 5 Current Descriptor Pointer */
+#define DMA1_5_CURR_ADDR 0xFFC01D64     /* DMA1 Channel 5 Current Address Pointer */
+#define DMA1_5_CURR_X_COUNT 0xFFC01D70  /* DMA1 Channel 5 Current Inner Loop Count */
+#define DMA1_5_CURR_Y_COUNT 0xFFC01D78  /* DMA1 Channel 5 Current Outer Loop Count */
+#define DMA1_5_IRQ_STATUS 0xFFC01D68    /* DMA1 Channel 5 Interrupt/Status Register */
+#define DMA1_5_PERIPHERAL_MAP 0xFFC01D6C        /* DMA1 Channel 5 Peripheral Map Register */
+
+#define DMA1_6_CONFIG 0xFFC01D88        /* DMA1 Channel 6 Configuration register */
+#define DMA1_6_NEXT_DESC_PTR 0xFFC01D80 /* DMA1 Channel 6 Next Descripter Ptr Reg */
+#define DMA1_6_START_ADDR 0xFFC01D84    /* DMA1 Channel 6 Start Address */
+#define DMA1_6_X_COUNT 0xFFC01D90       /* DMA1 Channel 6 Inner Loop Count */
+#define DMA1_6_Y_COUNT 0xFFC01D98       /* DMA1 Channel 6 Outer Loop Count */
+#define DMA1_6_X_MODIFY 0xFFC01D94      /* DMA1 Channel 6 Inner Loop Addr Increment */
+#define DMA1_6_Y_MODIFY 0xFFC01D9C      /* DMA1 Channel 6 Outer Loop Addr Increment */
+#define DMA1_6_CURR_DESC_PTR 0xFFC01DA0 /* DMA1 Channel 6 Current Descriptor Pointer */
+#define DMA1_6_CURR_ADDR 0xFFC01DA4     /* DMA1 Channel 6 Current Address Pointer */
+#define DMA1_6_CURR_X_COUNT 0xFFC01DB0  /* DMA1 Channel 6 Current Inner Loop Count */
+#define DMA1_6_CURR_Y_COUNT 0xFFC01DB8  /* DMA1 Channel 6 Current Outer Loop Count */
+#define DMA1_6_IRQ_STATUS 0xFFC01DA8    /* DMA1 Channel 6 Interrupt/Status Register */
+#define DMA1_6_PERIPHERAL_MAP 0xFFC01DAC        /* DMA1 Channel 6 Peripheral Map Register */
+
+#define DMA1_7_CONFIG 0xFFC01DC8        /* DMA1 Channel 7 Configuration register */
+#define DMA1_7_NEXT_DESC_PTR 0xFFC01DC0 /* DMA1 Channel 7 Next Descripter Ptr Reg */
+#define DMA1_7_START_ADDR 0xFFC01DC4    /* DMA1 Channel 7 Start Address */
+#define DMA1_7_X_COUNT 0xFFC01DD0       /* DMA1 Channel 7 Inner Loop Count */
+#define DMA1_7_Y_COUNT 0xFFC01DD8       /* DMA1 Channel 7 Outer Loop Count */
+#define DMA1_7_X_MODIFY 0xFFC01DD4      /* DMA1 Channel 7 Inner Loop Addr Increment */
+#define DMA1_7_Y_MODIFY 0xFFC01DDC      /* DMA1 Channel 7 Outer Loop Addr Increment */
+#define DMA1_7_CURR_DESC_PTR 0xFFC01DE0 /* DMA1 Channel 7 Current Descriptor Pointer */
+#define DMA1_7_CURR_ADDR 0xFFC01DE4     /* DMA1 Channel 7 Current Address Pointer */
+#define DMA1_7_CURR_X_COUNT 0xFFC01DF0  /* DMA1 Channel 7 Current Inner Loop Count */
+#define DMA1_7_CURR_Y_COUNT 0xFFC01DF8  /* DMA1 Channel 7 Current Outer Loop Count */
+#define DMA1_7_IRQ_STATUS 0xFFC01DE8    /* DMA1 Channel 7 Interrupt/Status Register */
+#define DMA1_7_PERIPHERAL_MAP 0xFFC01DEC        /* DMA1 Channel 7 Peripheral Map Register */
+
+#define DMA1_8_CONFIG 0xFFC01E08        /* DMA1 Channel 8 Configuration register */
+#define DMA1_8_NEXT_DESC_PTR 0xFFC01E00 /* DMA1 Channel 8 Next Descripter Ptr Reg */
+#define DMA1_8_START_ADDR 0xFFC01E04    /* DMA1 Channel 8 Start Address */
+#define DMA1_8_X_COUNT 0xFFC01E10       /* DMA1 Channel 8 Inner Loop Count */
+#define DMA1_8_Y_COUNT 0xFFC01E18       /* DMA1 Channel 8 Outer Loop Count */
+#define DMA1_8_X_MODIFY 0xFFC01E14      /* DMA1 Channel 8 Inner Loop Addr Increment */
+#define DMA1_8_Y_MODIFY 0xFFC01E1C      /* DMA1 Channel 8 Outer Loop Addr Increment */
+#define DMA1_8_CURR_DESC_PTR 0xFFC01E20 /* DMA1 Channel 8 Current Descriptor Pointer */
+#define DMA1_8_CURR_ADDR 0xFFC01E24     /* DMA1 Channel 8 Current Address Pointer */
+#define DMA1_8_CURR_X_COUNT 0xFFC01E30  /* DMA1 Channel 8 Current Inner Loop Count */
+#define DMA1_8_CURR_Y_COUNT 0xFFC01E38  /* DMA1 Channel 8 Current Outer Loop Count */
+#define DMA1_8_IRQ_STATUS 0xFFC01E28    /* DMA1 Channel 8 Interrupt/Status Register */
+#define DMA1_8_PERIPHERAL_MAP 0xFFC01E2C        /* DMA1 Channel 8 Peripheral Map Register */
+
+#define DMA1_9_CONFIG 0xFFC01E48        /* DMA1 Channel 9 Configuration register */
+#define DMA1_9_NEXT_DESC_PTR 0xFFC01E40 /* DMA1 Channel 9 Next Descripter Ptr Reg */
+#define DMA1_9_START_ADDR 0xFFC01E44    /* DMA1 Channel 9 Start Address */
+#define DMA1_9_X_COUNT 0xFFC01E50       /* DMA1 Channel 9 Inner Loop Count */
+#define DMA1_9_Y_COUNT 0xFFC01E58       /* DMA1 Channel 9 Outer Loop Count */
+#define DMA1_9_X_MODIFY 0xFFC01E54      /* DMA1 Channel 9 Inner Loop Addr Increment */
+#define DMA1_9_Y_MODIFY 0xFFC01E5C      /* DMA1 Channel 9 Outer Loop Addr Increment */
+#define DMA1_9_CURR_DESC_PTR 0xFFC01E60 /* DMA1 Channel 9 Current Descriptor Pointer */
+#define DMA1_9_CURR_ADDR 0xFFC01E64     /* DMA1 Channel 9 Current Address Pointer */
+#define DMA1_9_CURR_X_COUNT 0xFFC01E70  /* DMA1 Channel 9 Current Inner Loop Count */
+#define DMA1_9_CURR_Y_COUNT 0xFFC01E78  /* DMA1 Channel 9 Current Outer Loop Count */
+#define DMA1_9_IRQ_STATUS 0xFFC01E68    /* DMA1 Channel 9 Interrupt/Status Register */
+#define DMA1_9_PERIPHERAL_MAP 0xFFC01E6C        /* DMA1 Channel 9 Peripheral Map Register */
+
+#define DMA1_10_CONFIG 0xFFC01E88       /* DMA1 Channel 10 Configuration register */
+#define DMA1_10_NEXT_DESC_PTR 0xFFC01E80        /* DMA1 Channel 10 Next Descripter Ptr Reg */
+#define DMA1_10_START_ADDR 0xFFC01E84   /* DMA1 Channel 10 Start Address */
+#define DMA1_10_X_COUNT 0xFFC01E90      /* DMA1 Channel 10 Inner Loop Count */
+#define DMA1_10_Y_COUNT 0xFFC01E98      /* DMA1 Channel 10 Outer Loop Count */
+#define DMA1_10_X_MODIFY 0xFFC01E94     /* DMA1 Channel 10 Inner Loop Addr Increment */
+#define DMA1_10_Y_MODIFY 0xFFC01E9C     /* DMA1 Channel 10 Outer Loop Addr Increment */
+#define DMA1_10_CURR_DESC_PTR 0xFFC01EA0        /* DMA1 Channel 10 Current Descriptor Pointer */
+#define DMA1_10_CURR_ADDR 0xFFC01EA4    /* DMA1 Channel 10 Current Address Pointer */
+#define DMA1_10_CURR_X_COUNT 0xFFC01EB0 /* DMA1 Channel 10 Current Inner Loop Count */
+#define DMA1_10_CURR_Y_COUNT 0xFFC01EB8 /* DMA1 Channel 10 Current Outer Loop Count */
+#define DMA1_10_IRQ_STATUS 0xFFC01EA8   /* DMA1 Channel 10 Interrupt/Status Register */
+#define DMA1_10_PERIPHERAL_MAP 0xFFC01EAC       /* DMA1 Channel 10 Peripheral Map Register */
+
+#define DMA1_11_CONFIG 0xFFC01EC8       /* DMA1 Channel 11 Configuration register */
+#define DMA1_11_NEXT_DESC_PTR 0xFFC01EC0        /* DMA1 Channel 11 Next Descripter Ptr Reg */
+#define DMA1_11_START_ADDR 0xFFC01EC4   /* DMA1 Channel 11 Start Address */
+#define DMA1_11_X_COUNT 0xFFC01ED0      /* DMA1 Channel 11 Inner Loop Count */
+#define DMA1_11_Y_COUNT 0xFFC01ED8      /* DMA1 Channel 11 Outer Loop Count */
+#define DMA1_11_X_MODIFY 0xFFC01ED4     /* DMA1 Channel 11 Inner Loop Addr Increment */
+#define DMA1_11_Y_MODIFY 0xFFC01EDC     /* DMA1 Channel 11 Outer Loop Addr Increment */
+#define DMA1_11_CURR_DESC_PTR 0xFFC01EE0        /* DMA1 Channel 11 Current Descriptor Pointer */
+#define DMA1_11_CURR_ADDR 0xFFC01EE4    /* DMA1 Channel 11 Current Address Pointer */
+#define DMA1_11_CURR_X_COUNT 0xFFC01EF0 /* DMA1 Channel 11 Current Inner Loop Count */
+#define DMA1_11_CURR_Y_COUNT 0xFFC01EF8 /* DMA1 Channel 11 Current Outer Loop Count */
+#define DMA1_11_IRQ_STATUS 0xFFC01EE8   /* DMA1 Channel 11 Interrupt/Status Register */
+#define DMA1_11_PERIPHERAL_MAP 0xFFC01EEC       /* DMA1 Channel 11 Peripheral Map Register */
+
+/* Memory DMA1 Controller registers (0xFFC0 1E80-0xFFC0 1FFF) */
+#define MDMA1_D0_CONFIG 0xFFC01F08      /*MemDMA1 Stream 0 Destination Configuration */
+#define MDMA1_D0_NEXT_DESC_PTR 0xFFC01F00       /*MemDMA1 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA1_D0_START_ADDR 0xFFC01F04  /*MemDMA1 Stream 0 Destination Start Address */
+#define MDMA1_D0_X_COUNT 0xFFC01F10     /*MemDMA1 Stream 0 Destination Inner-Loop Count */
+#define MDMA1_D0_Y_COUNT 0xFFC01F18     /*MemDMA1 Stream 0 Destination Outer-Loop Count */
+#define MDMA1_D0_X_MODIFY 0xFFC01F14    /*MemDMA1 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA1_D0_Y_MODIFY 0xFFC01F1C    /*MemDMA1 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA1_D0_CURR_DESC_PTR 0xFFC01F20       /*MemDMA1 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA1_D0_CURR_ADDR 0xFFC01F24   /*MemDMA1 Stream 0 Destination Current Address */
+#define MDMA1_D0_CURR_X_COUNT 0xFFC01F30        /*MemDMA1 Stream 0 Dest Current Inner-Loop Count */
+#define MDMA1_D0_CURR_Y_COUNT 0xFFC01F38        /*MemDMA1 Stream 0 Dest Current Outer-Loop Count */
+#define MDMA1_D0_IRQ_STATUS 0xFFC01F28  /*MemDMA1 Stream 0 Destination Interrupt/Status */
+#define MDMA1_D0_PERIPHERAL_MAP 0xFFC01F2C      /*MemDMA1 Stream 0 Destination Peripheral Map */
+
+#define MDMA1_S0_CONFIG 0xFFC01F48      /*MemDMA1 Stream 0 Source Configuration */
+#define MDMA1_S0_NEXT_DESC_PTR 0xFFC01F40       /*MemDMA1 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA1_S0_START_ADDR 0xFFC01F44  /*MemDMA1 Stream 0 Source Start Address */
+#define MDMA1_S0_X_COUNT 0xFFC01F50     /*MemDMA1 Stream 0 Source Inner-Loop Count */
+#define MDMA1_S0_Y_COUNT 0xFFC01F58     /*MemDMA1 Stream 0 Source Outer-Loop Count */
+#define MDMA1_S0_X_MODIFY 0xFFC01F54    /*MemDMA1 Stream 0 Source Inner-Loop Address-Increment */
+#define MDMA1_S0_Y_MODIFY 0xFFC01F5C    /*MemDMA1 Stream 0 Source Outer-Loop Address-Increment */
+#define MDMA1_S0_CURR_DESC_PTR 0xFFC01F60       /*MemDMA1 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA1_S0_CURR_ADDR 0xFFC01F64   /*MemDMA1 Stream 0 Source Current Address */
+#define MDMA1_S0_CURR_X_COUNT 0xFFC01F70        /*MemDMA1 Stream 0 Source Current Inner-Loop Count */
+#define MDMA1_S0_CURR_Y_COUNT 0xFFC01F78        /*MemDMA1 Stream 0 Source Current Outer-Loop Count */
+#define MDMA1_S0_IRQ_STATUS 0xFFC01F68  /*MemDMA1 Stream 0 Source Interrupt/Status */
+#define MDMA1_S0_PERIPHERAL_MAP 0xFFC01F6C      /*MemDMA1 Stream 0 Source Peripheral Map */
+
+#define MDMA1_D1_CONFIG 0xFFC01F88      /*MemDMA1 Stream 1 Destination Configuration */
+#define MDMA1_D1_NEXT_DESC_PTR 0xFFC01F80       /*MemDMA1 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA1_D1_START_ADDR 0xFFC01F84  /*MemDMA1 Stream 1 Destination Start Address */
+#define MDMA1_D1_X_COUNT 0xFFC01F90     /*MemDMA1 Stream 1 Destination Inner-Loop Count */
+#define MDMA1_D1_Y_COUNT 0xFFC01F98     /*MemDMA1 Stream 1 Destination Outer-Loop Count */
+#define MDMA1_D1_X_MODIFY 0xFFC01F94    /*MemDMA1 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA1_D1_Y_MODIFY 0xFFC01F9C    /*MemDMA1 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA1_D1_CURR_DESC_PTR 0xFFC01FA0       /*MemDMA1 Stream 1 Dest Current Descriptor Ptr reg */
+#define MDMA1_D1_CURR_ADDR 0xFFC01FA4   /*MemDMA1 Stream 1 Dest Current Address */
+#define MDMA1_D1_CURR_X_COUNT 0xFFC01FB0        /*MemDMA1 Stream 1 Dest Current Inner-Loop Count */
+#define MDMA1_D1_CURR_Y_COUNT 0xFFC01FB8        /*MemDMA1 Stream 1 Dest Current Outer-Loop Count */
+#define MDMA1_D1_IRQ_STATUS 0xFFC01FA8  /*MemDMA1 Stream 1 Dest Interrupt/Status */
+#define MDMA1_D1_PERIPHERAL_MAP 0xFFC01FAC      /*MemDMA1 Stream 1 Dest Peripheral Map */
+
+#define MDMA1_S1_CONFIG 0xFFC01FC8      /*MemDMA1 Stream 1 Source Configuration */
+#define MDMA1_S1_NEXT_DESC_PTR 0xFFC01FC0       /*MemDMA1 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA1_S1_START_ADDR 0xFFC01FC4  /*MemDMA1 Stream 1 Source Start Address */
+#define MDMA1_S1_X_COUNT 0xFFC01FD0     /*MemDMA1 Stream 1 Source Inner-Loop Count */
+#define MDMA1_S1_Y_COUNT 0xFFC01FD8     /*MemDMA1 Stream 1 Source Outer-Loop Count */
+#define MDMA1_S1_X_MODIFY 0xFFC01FD4    /*MemDMA1 Stream 1 Source Inner-Loop Address-Increment */
+#define MDMA1_S1_Y_MODIFY 0xFFC01FDC    /*MemDMA1 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA1_S1_CURR_DESC_PTR 0xFFC01FE0       /*MemDMA1 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA1_S1_CURR_ADDR 0xFFC01FE4   /*MemDMA1 Stream 1 Source Current Address */
+#define MDMA1_S1_CURR_X_COUNT 0xFFC01FF0        /*MemDMA1 Stream 1 Source Current Inner-Loop Count */
+#define MDMA1_S1_CURR_Y_COUNT 0xFFC01FF8        /*MemDMA1 Stream 1 Source Current Outer-Loop Count */
+#define MDMA1_S1_IRQ_STATUS 0xFFC01FE8  /*MemDMA1 Stream 1 Source Interrupt/Status */
+#define MDMA1_S1_PERIPHERAL_MAP 0xFFC01FEC      /*MemDMA1 Stream 1 Source Peripheral Map */
+
+/* DMA2 Controller registers (0xFFC0 0C00-0xFFC0 0DFF) */
+#define DMA2_0_CONFIG 0xFFC00C08        /* DMA2 Channel 0 Configuration register */
+#define DMA2_0_NEXT_DESC_PTR 0xFFC00C00 /* DMA2 Channel 0 Next Descripter Ptr Reg */
+#define DMA2_0_START_ADDR 0xFFC00C04    /* DMA2 Channel 0 Start Address */
+#define DMA2_0_X_COUNT 0xFFC00C10       /* DMA2 Channel 0 Inner Loop Count */
+#define DMA2_0_Y_COUNT 0xFFC00C18       /* DMA2 Channel 0 Outer Loop Count */
+#define DMA2_0_X_MODIFY 0xFFC00C14      /* DMA2 Channel 0 Inner Loop Addr Increment */
+#define DMA2_0_Y_MODIFY 0xFFC00C1C      /* DMA2 Channel 0 Outer Loop Addr Increment */
+#define DMA2_0_CURR_DESC_PTR 0xFFC00C20 /* DMA2 Channel 0 Current Descriptor Pointer */
+#define DMA2_0_CURR_ADDR 0xFFC00C24     /* DMA2 Channel 0 Current Address Pointer */
+#define DMA2_0_CURR_X_COUNT 0xFFC00C30  /* DMA2 Channel 0 Current Inner Loop Count */
+#define DMA2_0_CURR_Y_COUNT 0xFFC00C38  /* DMA2 Channel 0 Current Outer Loop Count */
+#define DMA2_0_IRQ_STATUS 0xFFC00C28    /* DMA2 Channel 0 Interrupt/Status Register */
+#define DMA2_0_PERIPHERAL_MAP 0xFFC00C2C        /* DMA2 Channel 0 Peripheral Map Register */
+
+#define DMA2_1_CONFIG 0xFFC00C48        /* DMA2 Channel 1 Configuration register */
+#define DMA2_1_NEXT_DESC_PTR 0xFFC00C40 /* DMA2 Channel 1 Next Descripter Ptr Reg */
+#define DMA2_1_START_ADDR 0xFFC00C44    /* DMA2 Channel 1 Start Address */
+#define DMA2_1_X_COUNT 0xFFC00C50       /* DMA2 Channel 1 Inner Loop Count */
+#define DMA2_1_Y_COUNT 0xFFC00C58       /* DMA2 Channel 1 Outer Loop Count */
+#define DMA2_1_X_MODIFY 0xFFC00C54      /* DMA2 Channel 1 Inner Loop Addr Increment */
+#define DMA2_1_Y_MODIFY 0xFFC00C5C      /* DMA2 Channel 1 Outer Loop Addr Increment */
+#define DMA2_1_CURR_DESC_PTR 0xFFC00C60 /* DMA2 Channel 1 Current Descriptor Pointer */
+#define DMA2_1_CURR_ADDR 0xFFC00C64     /* DMA2 Channel 1 Current Address Pointer */
+#define DMA2_1_CURR_X_COUNT 0xFFC00C70  /* DMA2 Channel 1 Current Inner Loop Count */
+#define DMA2_1_CURR_Y_COUNT 0xFFC00C78  /* DMA2 Channel 1 Current Outer Loop Count */
+#define DMA2_1_IRQ_STATUS 0xFFC00C68    /* DMA2 Channel 1 Interrupt/Status Register */
+#define DMA2_1_PERIPHERAL_MAP 0xFFC00C6C        /* DMA2 Channel 1 Peripheral Map Register */
+
+#define DMA2_2_CONFIG 0xFFC00C88        /* DMA2 Channel 2 Configuration register */
+#define DMA2_2_NEXT_DESC_PTR 0xFFC00C80 /* DMA2 Channel 2 Next Descripter Ptr Reg */
+#define DMA2_2_START_ADDR 0xFFC00C84    /* DMA2 Channel 2 Start Address */
+#define DMA2_2_X_COUNT 0xFFC00C90       /* DMA2 Channel 2 Inner Loop Count */
+#define DMA2_2_Y_COUNT 0xFFC00C98       /* DMA2 Channel 2 Outer Loop Count */
+#define DMA2_2_X_MODIFY 0xFFC00C94      /* DMA2 Channel 2 Inner Loop Addr Increment */
+#define DMA2_2_Y_MODIFY 0xFFC00C9C      /* DMA2 Channel 2 Outer Loop Addr Increment */
+#define DMA2_2_CURR_DESC_PTR 0xFFC00CA0 /* DMA2 Channel 2 Current Descriptor Pointer */
+#define DMA2_2_CURR_ADDR 0xFFC00CA4     /* DMA2 Channel 2 Current Address Pointer */
+#define DMA2_2_CURR_X_COUNT 0xFFC00CB0  /* DMA2 Channel 2 Current Inner Loop Count */
+#define DMA2_2_CURR_Y_COUNT 0xFFC00CB8  /* DMA2 Channel 2 Current Outer Loop Count */
+#define DMA2_2_IRQ_STATUS 0xFFC00CA8    /* DMA2 Channel 2 Interrupt/Status Register */
+#define DMA2_2_PERIPHERAL_MAP 0xFFC00CAC        /* DMA2 Channel 2 Peripheral Map Register */
+
+#define DMA2_3_CONFIG 0xFFC00CC8        /* DMA2 Channel 3 Configuration register */
+#define DMA2_3_NEXT_DESC_PTR 0xFFC00CC0 /* DMA2 Channel 3 Next Descripter Ptr Reg */
+#define DMA2_3_START_ADDR 0xFFC00CC4    /* DMA2 Channel 3 Start Address */
+#define DMA2_3_X_COUNT 0xFFC00CD0       /* DMA2 Channel 3 Inner Loop Count */
+#define DMA2_3_Y_COUNT 0xFFC00CD8       /* DMA2 Channel 3 Outer Loop Count */
+#define DMA2_3_X_MODIFY 0xFFC00CD4      /* DMA2 Channel 3 Inner Loop Addr Increment */
+#define DMA2_3_Y_MODIFY 0xFFC00CDC      /* DMA2 Channel 3 Outer Loop Addr Increment */
+#define DMA2_3_CURR_DESC_PTR 0xFFC00CE0 /* DMA2 Channel 3 Current Descriptor Pointer */
+#define DMA2_3_CURR_ADDR 0xFFC00CE4     /* DMA2 Channel 3 Current Address Pointer */
+#define DMA2_3_CURR_X_COUNT 0xFFC00CF0  /* DMA2 Channel 3 Current Inner Loop Count */
+#define DMA2_3_CURR_Y_COUNT 0xFFC00CF8  /* DMA2 Channel 3 Current Outer Loop Count */
+#define DMA2_3_IRQ_STATUS 0xFFC00CE8    /* DMA2 Channel 3 Interrupt/Status Register */
+#define DMA2_3_PERIPHERAL_MAP 0xFFC00CEC        /* DMA2 Channel 3 Peripheral Map Register */
+
+#define DMA2_4_CONFIG 0xFFC00D08        /* DMA2 Channel 4 Configuration register */
+#define DMA2_4_NEXT_DESC_PTR 0xFFC00D00 /* DMA2 Channel 4 Next Descripter Ptr Reg */
+#define DMA2_4_START_ADDR 0xFFC00D04    /* DMA2 Channel 4 Start Address */
+#define DMA2_4_X_COUNT 0xFFC00D10       /* DMA2 Channel 4 Inner Loop Count */
+#define DMA2_4_Y_COUNT 0xFFC00D18       /* DMA2 Channel 4 Outer Loop Count */
+#define DMA2_4_X_MODIFY 0xFFC00D14      /* DMA2 Channel 4 Inner Loop Addr Increment */
+#define DMA2_4_Y_MODIFY 0xFFC00D1C      /* DMA2 Channel 4 Outer Loop Addr Increment */
+#define DMA2_4_CURR_DESC_PTR 0xFFC00D20 /* DMA2 Channel 4 Current Descriptor Pointer */
+#define DMA2_4_CURR_ADDR 0xFFC00D24     /* DMA2 Channel 4 Current Address Pointer */
+#define DMA2_4_CURR_X_COUNT 0xFFC00D30  /* DMA2 Channel 4 Current Inner Loop Count */
+#define DMA2_4_CURR_Y_COUNT 0xFFC00D38  /* DMA2 Channel 4 Current Outer Loop Count */
+#define DMA2_4_IRQ_STATUS 0xFFC00D28    /* DMA2 Channel 4 Interrupt/Status Register */
+#define DMA2_4_PERIPHERAL_MAP 0xFFC00D2C        /* DMA2 Channel 4 Peripheral Map Register */
+
+#define DMA2_5_CONFIG 0xFFC00D48        /* DMA2 Channel 5 Configuration register */
+#define DMA2_5_NEXT_DESC_PTR 0xFFC00D40 /* DMA2 Channel 5 Next Descripter Ptr Reg */
+#define DMA2_5_START_ADDR 0xFFC00D44    /* DMA2 Channel 5 Start Address */
+#define DMA2_5_X_COUNT 0xFFC00D50       /* DMA2 Channel 5 Inner Loop Count */
+#define DMA2_5_Y_COUNT 0xFFC00D58       /* DMA2 Channel 5 Outer Loop Count */
+#define DMA2_5_X_MODIFY 0xFFC00D54      /* DMA2 Channel 5 Inner Loop Addr Increment */
+#define DMA2_5_Y_MODIFY 0xFFC00D5C      /* DMA2 Channel 5 Outer Loop Addr Increment */
+#define DMA2_5_CURR_DESC_PTR 0xFFC00D60 /* DMA2 Channel 5 Current Descriptor Pointer */
+#define DMA2_5_CURR_ADDR 0xFFC00D64     /* DMA2 Channel 5 Current Address Pointer */
+#define DMA2_5_CURR_X_COUNT 0xFFC00D70  /* DMA2 Channel 5 Current Inner Loop Count */
+#define DMA2_5_CURR_Y_COUNT 0xFFC00D78  /* DMA2 Channel 5 Current Outer Loop Count */
+#define DMA2_5_IRQ_STATUS 0xFFC00D68    /* DMA2 Channel 5 Interrupt/Status Register */
+#define DMA2_5_PERIPHERAL_MAP 0xFFC00D6C        /* DMA2 Channel 5 Peripheral Map Register */
+
+#define DMA2_6_CONFIG 0xFFC00D88        /* DMA2 Channel 6 Configuration register */
+#define DMA2_6_NEXT_DESC_PTR 0xFFC00D80 /* DMA2 Channel 6 Next Descripter Ptr Reg */
+#define DMA2_6_START_ADDR 0xFFC00D84    /* DMA2 Channel 6 Start Address */
+#define DMA2_6_X_COUNT 0xFFC00D90       /* DMA2 Channel 6 Inner Loop Count */
+#define DMA2_6_Y_COUNT 0xFFC00D98       /* DMA2 Channel 6 Outer Loop Count */
+#define DMA2_6_X_MODIFY 0xFFC00D94      /* DMA2 Channel 6 Inner Loop Addr Increment */
+#define DMA2_6_Y_MODIFY 0xFFC00D9C      /* DMA2 Channel 6 Outer Loop Addr Increment */
+#define DMA2_6_CURR_DESC_PTR 0xFFC00DA0 /* DMA2 Channel 6 Current Descriptor Pointer */
+#define DMA2_6_CURR_ADDR 0xFFC00DA4     /* DMA2 Channel 6 Current Address Pointer */
+#define DMA2_6_CURR_X_COUNT 0xFFC00DB0  /* DMA2 Channel 6 Current Inner Loop Count */
+#define DMA2_6_CURR_Y_COUNT 0xFFC00DB8  /* DMA2 Channel 6 Current Outer Loop Count */
+#define DMA2_6_IRQ_STATUS 0xFFC00DA8    /* DMA2 Channel 6 Interrupt/Status Register */
+#define DMA2_6_PERIPHERAL_MAP 0xFFC00DAC        /* DMA2 Channel 6 Peripheral Map Register */
+
+#define DMA2_7_CONFIG 0xFFC00DC8        /* DMA2 Channel 7 Configuration register */
+#define DMA2_7_NEXT_DESC_PTR 0xFFC00DC0 /* DMA2 Channel 7 Next Descripter Ptr Reg */
+#define DMA2_7_START_ADDR 0xFFC00DC4    /* DMA2 Channel 7 Start Address */
+#define DMA2_7_X_COUNT 0xFFC00DD0       /* DMA2 Channel 7 Inner Loop Count */
+#define DMA2_7_Y_COUNT 0xFFC00DD8       /* DMA2 Channel 7 Outer Loop Count */
+#define DMA2_7_X_MODIFY 0xFFC00DD4      /* DMA2 Channel 7 Inner Loop Addr Increment */
+#define DMA2_7_Y_MODIFY 0xFFC00DDC      /* DMA2 Channel 7 Outer Loop Addr Increment */
+#define DMA2_7_CURR_DESC_PTR 0xFFC00DE0 /* DMA2 Channel 7 Current Descriptor Pointer */
+#define DMA2_7_CURR_ADDR 0xFFC00DE4     /* DMA2 Channel 7 Current Address Pointer */
+#define DMA2_7_CURR_X_COUNT 0xFFC00DF0  /* DMA2 Channel 7 Current Inner Loop Count */
+#define DMA2_7_CURR_Y_COUNT 0xFFC00DF8  /* DMA2 Channel 7 Current Outer Loop Count */
+#define DMA2_7_IRQ_STATUS 0xFFC00DE8    /* DMA2 Channel 7 Interrupt/Status Register */
+#define DMA2_7_PERIPHERAL_MAP 0xFFC00DEC        /* DMA2 Channel 7 Peripheral Map Register */
+
+#define DMA2_8_CONFIG 0xFFC00E08        /* DMA2 Channel 8 Configuration register */
+#define DMA2_8_NEXT_DESC_PTR 0xFFC00E00 /* DMA2 Channel 8 Next Descripter Ptr Reg */
+#define DMA2_8_START_ADDR 0xFFC00E04    /* DMA2 Channel 8 Start Address */
+#define DMA2_8_X_COUNT 0xFFC00E10       /* DMA2 Channel 8 Inner Loop Count */
+#define DMA2_8_Y_COUNT 0xFFC00E18       /* DMA2 Channel 8 Outer Loop Count */
+#define DMA2_8_X_MODIFY 0xFFC00E14      /* DMA2 Channel 8 Inner Loop Addr Increment */
+#define DMA2_8_Y_MODIFY 0xFFC00E1C      /* DMA2 Channel 8 Outer Loop Addr Increment */
+#define DMA2_8_CURR_DESC_PTR 0xFFC00E20 /* DMA2 Channel 8 Current Descriptor Pointer */
+#define DMA2_8_CURR_ADDR 0xFFC00E24     /* DMA2 Channel 8 Current Address Pointer */
+#define DMA2_8_CURR_X_COUNT 0xFFC00E30  /* DMA2 Channel 8 Current Inner Loop Count */
+#define DMA2_8_CURR_Y_COUNT 0xFFC00E38  /* DMA2 Channel 8 Current Outer Loop Count */
+#define DMA2_8_IRQ_STATUS 0xFFC00E28    /* DMA2 Channel 8 Interrupt/Status Register */
+#define DMA2_8_PERIPHERAL_MAP 0xFFC00E2C        /* DMA2 Channel 8 Peripheral Map Register */
+
+#define DMA2_9_CONFIG 0xFFC00E48        /* DMA2 Channel 9 Configuration register */
+#define DMA2_9_NEXT_DESC_PTR 0xFFC00E40 /* DMA2 Channel 9 Next Descripter Ptr Reg */
+#define DMA2_9_START_ADDR 0xFFC00E44    /* DMA2 Channel 9 Start Address */
+#define DMA2_9_X_COUNT 0xFFC00E50       /* DMA2 Channel 9 Inner Loop Count */
+#define DMA2_9_Y_COUNT 0xFFC00E58       /* DMA2 Channel 9 Outer Loop Count */
+#define DMA2_9_X_MODIFY 0xFFC00E54      /* DMA2 Channel 9 Inner Loop Addr Increment */
+#define DMA2_9_Y_MODIFY 0xFFC00E5C      /* DMA2 Channel 9 Outer Loop Addr Increment */
+#define DMA2_9_CURR_DESC_PTR 0xFFC00E60 /* DMA2 Channel 9 Current Descriptor Pointer */
+#define DMA2_9_CURR_ADDR 0xFFC00E64     /* DMA2 Channel 9 Current Address Pointer */
+#define DMA2_9_CURR_X_COUNT 0xFFC00E70  /* DMA2 Channel 9 Current Inner Loop Count */
+#define DMA2_9_CURR_Y_COUNT 0xFFC00E78  /* DMA2 Channel 9 Current Outer Loop Count */
+#define DMA2_9_IRQ_STATUS 0xFFC00E68    /* DMA2 Channel 9 Interrupt/Status Register */
+#define DMA2_9_PERIPHERAL_MAP 0xFFC00E6C        /* DMA2 Channel 9 Peripheral Map Register */
+
+#define DMA2_10_CONFIG 0xFFC00E88       /* DMA2 Channel 10 Configuration register */
+#define DMA2_10_NEXT_DESC_PTR 0xFFC00E80        /* DMA2 Channel 10 Next Descripter Ptr Reg */
+#define DMA2_10_START_ADDR 0xFFC00E84   /* DMA2 Channel 10 Start Address */
+#define DMA2_10_X_COUNT 0xFFC00E90      /* DMA2 Channel 10 Inner Loop Count */
+#define DMA2_10_Y_COUNT 0xFFC00E98      /* DMA2 Channel 10 Outer Loop Count */
+#define DMA2_10_X_MODIFY 0xFFC00E94     /* DMA2 Channel 10 Inner Loop Addr Increment */
+#define DMA2_10_Y_MODIFY 0xFFC00E9C     /* DMA2 Channel 10 Outer Loop Addr Increment */
+#define DMA2_10_CURR_DESC_PTR 0xFFC00EA0        /* DMA2 Channel 10 Current Descriptor Pointer */
+#define DMA2_10_CURR_ADDR 0xFFC00EA4    /* DMA2 Channel 10 Current Address Pointer */
+#define DMA2_10_CURR_X_COUNT 0xFFC00EB0 /* DMA2 Channel 10 Current Inner Loop Count */
+#define DMA2_10_CURR_Y_COUNT 0xFFC00EB8 /* DMA2 Channel 10 Current Outer Loop Count */
+#define DMA2_10_IRQ_STATUS 0xFFC00EA8   /* DMA2 Channel 10 Interrupt/Status Register */
+#define DMA2_10_PERIPHERAL_MAP 0xFFC00EAC       /* DMA2 Channel 10 Peripheral Map Register */
+
+#define DMA2_11_CONFIG 0xFFC00EC8       /* DMA2 Channel 11 Configuration register */
+#define DMA2_11_NEXT_DESC_PTR 0xFFC00EC0        /* DMA2 Channel 11 Next Descripter Ptr Reg */
+#define DMA2_11_START_ADDR 0xFFC00EC4   /* DMA2 Channel 11 Start Address */
+#define DMA2_11_X_COUNT 0xFFC00ED0      /* DMA2 Channel 11 Inner Loop Count */
+#define DMA2_11_Y_COUNT 0xFFC00ED8      /* DMA2 Channel 11 Outer Loop Count */
+#define DMA2_11_X_MODIFY 0xFFC00ED4     /* DMA2 Channel 11 Inner Loop Addr Increment */
+#define DMA2_11_Y_MODIFY 0xFFC00EDC     /* DMA2 Channel 11 Outer Loop Addr Increment */
+#define DMA2_11_CURR_DESC_PTR 0xFFC00EE0        /* DMA2 Channel 11 Current Descriptor Pointer */
+#define DMA2_11_CURR_ADDR 0xFFC00EE4    /* DMA2 Channel 11 Current Address Pointer */
+#define DMA2_11_CURR_X_COUNT 0xFFC00EF0 /* DMA2 Channel 11 Current Inner Loop Count */
+#define DMA2_11_CURR_Y_COUNT 0xFFC00EF8 /* DMA2 Channel 11 Current Outer Loop Count */
+#define DMA2_11_IRQ_STATUS 0xFFC00EE8   /* DMA2 Channel 11 Interrupt/Status Register */
+#define DMA2_11_PERIPHERAL_MAP 0xFFC00EEC       /* DMA2 Channel 11 Peripheral Map Register */
+
+/* Memory DMA2 Controller registers (0xFFC0 0E80-0xFFC0 0FFF) */
+#define MDMA2_D0_CONFIG 0xFFC00F08      /*MemDMA2 Stream 0 Destination Configuration register */
+#define MDMA2_D0_NEXT_DESC_PTR 0xFFC00F00       /*MemDMA2 Stream 0 Destination Next Descriptor Ptr Reg */
+#define MDMA2_D0_START_ADDR 0xFFC00F04  /*MemDMA2 Stream 0 Destination Start Address */
+#define MDMA2_D0_X_COUNT 0xFFC00F10     /*MemDMA2 Stream 0 Dest Inner-Loop Count register */
+#define MDMA2_D0_Y_COUNT 0xFFC00F18     /*MemDMA2 Stream 0 Dest Outer-Loop Count register */
+#define MDMA2_D0_X_MODIFY 0xFFC00F14    /*MemDMA2 Stream 0 Dest Inner-Loop Address-Increment */
+#define MDMA2_D0_Y_MODIFY 0xFFC00F1C    /*MemDMA2 Stream 0 Dest Outer-Loop Address-Increment */
+#define MDMA2_D0_CURR_DESC_PTR 0xFFC00F20       /*MemDMA2 Stream 0 Dest Current Descriptor Ptr reg */
+#define MDMA2_D0_CURR_ADDR 0xFFC00F24   /*MemDMA2 Stream 0 Destination Current Address */
+#define MDMA2_D0_CURR_X_COUNT 0xFFC00F30        /*MemDMA2 Stream 0 Dest Current Inner-Loop Count reg */
+#define MDMA2_D0_CURR_Y_COUNT 0xFFC00F38        /*MemDMA2 Stream 0 Dest Current Outer-Loop Count reg */
+#define MDMA2_D0_IRQ_STATUS 0xFFC00F28  /*MemDMA2 Stream 0 Dest Interrupt/Status Register */
+#define MDMA2_D0_PERIPHERAL_MAP 0xFFC00F2C      /*MemDMA2 Stream 0 Destination Peripheral Map register */
+
+#define MDMA2_S0_CONFIG 0xFFC00F48      /*MemDMA2 Stream 0 Source Configuration register */
+#define MDMA2_S0_NEXT_DESC_PTR 0xFFC00F40       /*MemDMA2 Stream 0 Source Next Descriptor Ptr Reg */
+#define MDMA2_S0_START_ADDR 0xFFC00F44  /*MemDMA2 Stream 0 Source Start Address */
+#define MDMA2_S0_X_COUNT 0xFFC00F50     /*MemDMA2 Stream 0 Source Inner-Loop Count register */
+#define MDMA2_S0_Y_COUNT 0xFFC00F58     /*MemDMA2 Stream 0 Source Outer-Loop Count register */
+#define MDMA2_S0_X_MODIFY 0xFFC00F54    /*MemDMA2 Stream 0 Src Inner-Loop Addr-Increment reg */
+#define MDMA2_S0_Y_MODIFY 0xFFC00F5C    /*MemDMA2 Stream 0 Src Outer-Loop Addr-Increment reg */
+#define MDMA2_S0_CURR_DESC_PTR 0xFFC00F60       /*MemDMA2 Stream 0 Source Current Descriptor Ptr reg */
+#define MDMA2_S0_CURR_ADDR 0xFFC00F64   /*MemDMA2 Stream 0 Source Current Address */
+#define MDMA2_S0_CURR_X_COUNT 0xFFC00F70        /*MemDMA2 Stream 0 Src Current Inner-Loop Count reg */
+#define MDMA2_S0_CURR_Y_COUNT 0xFFC00F78        /*MemDMA2 Stream 0 Src Current Outer-Loop Count reg */
+#define MDMA2_S0_IRQ_STATUS 0xFFC00F68  /*MemDMA2 Stream 0 Source Interrupt/Status Register */
+#define MDMA2_S0_PERIPHERAL_MAP 0xFFC00F6C      /*MemDMA2 Stream 0 Source Peripheral Map register */
+
+#define MDMA2_D1_CONFIG 0xFFC00F88      /*MemDMA2 Stream 1 Destination Configuration register */
+#define MDMA2_D1_NEXT_DESC_PTR 0xFFC00F80       /*MemDMA2 Stream 1 Destination Next Descriptor Ptr Reg */
+#define MDMA2_D1_START_ADDR 0xFFC00F84  /*MemDMA2 Stream 1 Destination Start Address */
+#define MDMA2_D1_X_COUNT 0xFFC00F90     /*MemDMA2 Stream 1 Dest Inner-Loop Count register */
+#define MDMA2_D1_Y_COUNT 0xFFC00F98     /*MemDMA2 Stream 1 Dest Outer-Loop Count register */
+#define MDMA2_D1_X_MODIFY 0xFFC00F94    /*MemDMA2 Stream 1 Dest Inner-Loop Address-Increment */
+#define MDMA2_D1_Y_MODIFY 0xFFC00F9C    /*MemDMA2 Stream 1 Dest Outer-Loop Address-Increment */
+#define MDMA2_D1_CURR_DESC_PTR 0xFFC00FA0       /*MemDMA2 Stream 1 Destination Current Descriptor Ptr */
+#define MDMA2_D1_CURR_ADDR 0xFFC00FA4   /*MemDMA2 Stream 1 Destination Current Address reg */
+#define MDMA2_D1_CURR_X_COUNT 0xFFC00FB0        /*MemDMA2 Stream 1 Dest Current Inner-Loop Count reg */
+#define MDMA2_D1_CURR_Y_COUNT 0xFFC00FB8        /*MemDMA2 Stream 1 Dest Current Outer-Loop Count reg */
+#define MDMA2_D1_IRQ_STATUS 0xFFC00FA8  /*MemDMA2 Stream 1 Destination Interrupt/Status Reg */
+#define MDMA2_D1_PERIPHERAL_MAP 0xFFC00FAC      /*MemDMA2 Stream 1 Destination Peripheral Map register */
+
+#define MDMA2_S1_CONFIG 0xFFC00FC8      /*MemDMA2 Stream 1 Source Configuration register */
+#define MDMA2_S1_NEXT_DESC_PTR 0xFFC00FC0       /*MemDMA2 Stream 1 Source Next Descriptor Ptr Reg */
+#define MDMA2_S1_START_ADDR 0xFFC00FC4  /*MemDMA2 Stream 1 Source Start Address */
+#define MDMA2_S1_X_COUNT 0xFFC00FD0     /*MemDMA2 Stream 1 Source Inner-Loop Count register */
+#define MDMA2_S1_Y_COUNT 0xFFC00FD8     /*MemDMA2 Stream 1 Source Outer-Loop Count register */
+#define MDMA2_S1_X_MODIFY 0xFFC00FD4    /*MemDMA2 Stream 1 Src Inner-Loop Address-Increment */
+#define MDMA2_S1_Y_MODIFY 0xFFC00FDC    /*MemDMA2 Stream 1 Source Outer-Loop Address-Increment */
+#define MDMA2_S1_CURR_DESC_PTR 0xFFC00FE0       /*MemDMA2 Stream 1 Source Current Descriptor Ptr reg */
+#define MDMA2_S1_CURR_ADDR 0xFFC00FE4   /*MemDMA2 Stream 1 Source Current Address */
+#define MDMA2_S1_CURR_X_COUNT 0xFFC00FF0        /*MemDMA2 Stream 1 Source Current Inner-Loop Count */
+#define MDMA2_S1_CURR_Y_COUNT 0xFFC00FF8        /*MemDMA2 Stream 1 Source Current Outer-Loop Count */
+#define MDMA2_S1_IRQ_STATUS 0xFFC00FE8  /*MemDMA2 Stream 1 Source Interrupt/Status Register */
+#define MDMA2_S1_PERIPHERAL_MAP 0xFFC00FEC      /*MemDMA2 Stream 1 Source Peripheral Map register */
+
+/* Internal Memory DMA Registers (0xFFC0_1800 - 0xFFC0_19FF) */
+#define IMDMA_D0_CONFIG 0xFFC01808      /*IMDMA Stream 0 Destination Configuration */
+#define IMDMA_D0_NEXT_DESC_PTR 0xFFC01800       /*IMDMA Stream 0 Destination Next Descriptor Ptr Reg */
+#define IMDMA_D0_START_ADDR 0xFFC01804  /*IMDMA Stream 0 Destination Start Address */
+#define IMDMA_D0_X_COUNT 0xFFC01810     /*IMDMA Stream 0 Destination Inner-Loop Count */
+#define IMDMA_D0_Y_COUNT 0xFFC01818     /*IMDMA Stream 0 Destination Outer-Loop Count */
+#define IMDMA_D0_X_MODIFY 0xFFC01814    /*IMDMA Stream 0 Dest Inner-Loop Address-Increment */
+#define IMDMA_D0_Y_MODIFY 0xFFC0181C    /*IMDMA Stream 0 Dest Outer-Loop Address-Increment */
+#define IMDMA_D0_CURR_DESC_PTR 0xFFC01820       /*IMDMA Stream 0 Destination Current Descriptor Ptr */
+#define IMDMA_D0_CURR_ADDR 0xFFC01824   /*IMDMA Stream 0 Destination Current Address */
+#define IMDMA_D0_CURR_X_COUNT 0xFFC01830        /*IMDMA Stream 0 Destination Current Inner-Loop Count */
+#define IMDMA_D0_CURR_Y_COUNT 0xFFC01838        /*IMDMA Stream 0 Destination Current Outer-Loop Count */
+#define IMDMA_D0_IRQ_STATUS 0xFFC01828  /*IMDMA Stream 0 Destination Interrupt/Status */
+
+#define IMDMA_S0_CONFIG 0xFFC01848      /*IMDMA Stream 0 Source Configuration */
+#define IMDMA_S0_NEXT_DESC_PTR 0xFFC01840       /*IMDMA Stream 0 Source Next Descriptor Ptr Reg */
+#define IMDMA_S0_START_ADDR 0xFFC01844  /*IMDMA Stream 0 Source Start Address */
+#define IMDMA_S0_X_COUNT 0xFFC01850     /*IMDMA Stream 0 Source Inner-Loop Count */
+#define IMDMA_S0_Y_COUNT 0xFFC01858     /*IMDMA Stream 0 Source Outer-Loop Count */
+#define IMDMA_S0_X_MODIFY 0xFFC01854    /*IMDMA Stream 0 Source Inner-Loop Address-Increment */
+#define IMDMA_S0_Y_MODIFY 0xFFC0185C    /*IMDMA Stream 0 Source Outer-Loop Address-Increment */
+#define IMDMA_S0_CURR_DESC_PTR 0xFFC01860       /*IMDMA Stream 0 Source Current Descriptor Ptr reg */
+#define IMDMA_S0_CURR_ADDR 0xFFC01864   /*IMDMA Stream 0 Source Current Address */
+#define IMDMA_S0_CURR_X_COUNT 0xFFC01870        /*IMDMA Stream 0 Source Current Inner-Loop Count */
+#define IMDMA_S0_CURR_Y_COUNT 0xFFC01878        /*IMDMA Stream 0 Source Current Outer-Loop Count */
+#define IMDMA_S0_IRQ_STATUS 0xFFC01868  /*IMDMA Stream 0 Source Interrupt/Status */
+
+#define IMDMA_D1_CONFIG 0xFFC01888      /*IMDMA Stream 1 Destination Configuration */
+#define IMDMA_D1_NEXT_DESC_PTR 0xFFC01880       /*IMDMA Stream 1 Destination Next Descriptor Ptr Reg */
+#define IMDMA_D1_START_ADDR 0xFFC01884  /*IMDMA Stream 1 Destination Start Address */
+#define IMDMA_D1_X_COUNT 0xFFC01890     /*IMDMA Stream 1 Destination Inner-Loop Count */
+#define IMDMA_D1_Y_COUNT 0xFFC01898     /*IMDMA Stream 1 Destination Outer-Loop Count */
+#define IMDMA_D1_X_MODIFY 0xFFC01894    /*IMDMA Stream 1 Dest Inner-Loop Address-Increment */
+#define IMDMA_D1_Y_MODIFY 0xFFC0189C    /*IMDMA Stream 1 Dest Outer-Loop Address-Increment */
+#define IMDMA_D1_CURR_DESC_PTR 0xFFC018A0       /*IMDMA Stream 1 Destination Current Descriptor Ptr */
+#define IMDMA_D1_CURR_ADDR 0xFFC018A4   /*IMDMA Stream 1 Destination Current Address */
+#define IMDMA_D1_CURR_X_COUNT 0xFFC018B0        /*IMDMA Stream 1 Destination Current Inner-Loop Count */
+#define IMDMA_D1_CURR_Y_COUNT 0xFFC018B8        /*IMDMA Stream 1 Destination Current Outer-Loop Count */
+#define IMDMA_D1_IRQ_STATUS 0xFFC018A8  /*IMDMA Stream 1 Destination Interrupt/Status */
+
+#define IMDMA_S1_CONFIG 0xFFC018C8      /*IMDMA Stream 1 Source Configuration */
+#define IMDMA_S1_NEXT_DESC_PTR 0xFFC018C0       /*IMDMA Stream 1 Source Next Descriptor Ptr Reg */
+#define IMDMA_S1_START_ADDR 0xFFC018C4  /*IMDMA Stream 1 Source Start Address */
+#define IMDMA_S1_X_COUNT 0xFFC018D0     /*IMDMA Stream 1 Source Inner-Loop Count */
+#define IMDMA_S1_Y_COUNT 0xFFC018D8     /*IMDMA Stream 1 Source Outer-Loop Count */
+#define IMDMA_S1_X_MODIFY 0xFFC018D4    /*IMDMA Stream 1 Source Inner-Loop Address-Increment */
+#define IMDMA_S1_Y_MODIFY 0xFFC018DC    /*IMDMA Stream 1 Source Outer-Loop Address-Increment */
+#define IMDMA_S1_CURR_DESC_PTR 0xFFC018E0       /*IMDMA Stream 1 Source Current Descriptor Ptr reg */
+#define IMDMA_S1_CURR_ADDR 0xFFC018E4   /*IMDMA Stream 1 Source Current Address */
+#define IMDMA_S1_CURR_X_COUNT 0xFFC018F0        /*IMDMA Stream 1 Source Current Inner-Loop Count */
+#define IMDMA_S1_CURR_Y_COUNT 0xFFC018F8        /*IMDMA Stream 1 Source Current Outer-Loop Count */
+#define IMDMA_S1_IRQ_STATUS 0xFFC018E8  /*IMDMA Stream 1 Source Interrupt/Status */
+
+/*********************************************************************************** */
+/* System MMR Register Bits */
+/******************************************************************************* */
+
+/* ********************* PLL AND RESET MASKS ************************ */
+
+/* PLL_CTL Masks */
+#define PLL_CLKIN              0x00000000       /* Pass CLKIN to PLL */
+#define PLL_CLKIN_DIV2         0x00000001       /* Pass CLKIN/2 to PLL */
+#define PLL_OFF                0x00000002       /* Shut off PLL clocks */
+#define STOPCK_OFF             0x00000008       /* Core clock off */
+#define PDWN                   0x00000020       /* Put the PLL in a Deep Sleep state */
+#define BYPASS                 0x00000100       /* Bypass the PLL */
+
+/* CHIPID Masks */
+#define CHIPID_VERSION         0xF0000000
+#define CHIPID_FAMILY          0x0FFFF000
+#define CHIPID_MANUFACTURE     0x00000FFE
+
+/* PLL_DIV Masks */
+#define SCLK_DIV(x)  (x)        /* SCLK = VCO / x */
+
+#define CCLK_DIV1              0x00000000       /* CCLK = VCO / 1 */
+#define CCLK_DIV2              0x00000010       /* CCLK = VCO / 2 */
+#define CCLK_DIV4              0x00000020       /* CCLK = VCO / 4 */
+#define CCLK_DIV8              0x00000030       /* CCLK = VCO / 8 */
+
+/* PLL_STAT Masks                                                                                                                                       */
+#define ACTIVE_PLLENABLED       0x0001  /* Processor In Active Mode With PLL Enabled    */
+#define FULL_ON                         0x0002  /* Processor In Full On Mode                                    */
+#define ACTIVE_PLLDISABLED      0x0004  /* Processor In Active Mode With PLL Disabled   */
+#define PLL_LOCKED                      0x0020  /* PLL_LOCKCNT Has Been Reached                                 */
+
+/* SWRST Mask */
+#define SYSTEM_RESET           0x00000007       /* Initiates a system software reset */
+#define SWRST_DBL_FAULT_B      0x00000800       /* SWRST Core B Double Fault */
+#define SWRST_DBL_FAULT_A      0x00001000       /* SWRST Core A Double Fault */
+#define SWRST_WDT_B                    0x00002000       /* SWRST Watchdog B */
+#define SWRST_WDT_A                    0x00004000       /* SWRST Watchdog A */
+#define SWRST_OCCURRED         0x00008000       /* SWRST Status */
+
+/* *************  SYSTEM INTERRUPT CONTROLLER MASKS ***************** */
+
+/* SICu_IARv Masks       */
+/* u = A or B */
+/* v = 0 to 7 */
+/* w = 0 or 1 */
+
+/* Per_number = 0 to 63 */
+/* IVG_number = 7 to 15   */
+#define Peripheral_IVG(Per_number, IVG_number)    \
+    ((IVG_number) - 7) << (((Per_number) % 8) * 4)      /* Peripheral #Per_number assigned IVG #IVG_number  */
+    /* Usage: r0.l = lo(Peripheral_IVG(62, 10)); */
+    /*        r0.h = hi(Peripheral_IVG(62, 10)); */
+
+/* SICx_IMASKw Masks */
+/* masks are 32 bit wide, so two writes reguired for "64 bit" wide registers  */
+#define SIC_UNMASK_ALL         0x00000000       /* Unmask all peripheral interrupts */
+#define SIC_MASK_ALL           0xFFFFFFFF       /* Mask all peripheral interrupts */
+#define SIC_MASK(x)            (1 << (x))       /* Mask Peripheral #x interrupt */
+#define SIC_UNMASK(x) (0xFFFFFFFF ^ (1 << (x))) /* Unmask Peripheral #x interrupt */
+
+/* SIC_IWR Masks */
+#define IWR_DISABLE_ALL        0x00000000       /* Wakeup Disable all peripherals */
+#define IWR_ENABLE_ALL         0xFFFFFFFF       /* Wakeup Enable all peripherals */
+/* x = pos 0 to 31, for 32-63 use value-32 */
+#define IWR_ENABLE(x)          (1 << (x))       /* Wakeup Enable Peripheral #x */
+#define IWR_DISABLE(x) (0xFFFFFFFF ^ (1 << (x)))        /* Wakeup Disable Peripheral #x */
+
+/* *********  WATCHDOG TIMER MASKS  ********************8 */
+
+/* Watchdog Timer WDOG_CTL Register */
+#define ICTL(x) ((x<<1) & 0x0006)
+#define ENABLE_RESET     0x00000000     /* Set Watchdog Timer to generate reset */
+#define ENABLE_NMI       0x00000002     /* Set Watchdog Timer to generate non-maskable interrupt */
+#define ENABLE_GPI       0x00000004     /* Set Watchdog Timer to generate general-purpose interrupt */
+#define DISABLE_EVT      0x00000006     /* Disable Watchdog Timer interrupts */
+
+#define TMR_EN          0x0000
+#define TMR_DIS         0x0AD0
+#define TRO             0x8000
+
+#define ICTL_P0         0x01
+#define ICTL_P1         0x02
+#define TRO_P           0x0F
+
+/* ***************************** UART CONTROLLER MASKS ********************** */
+
+/* UART_LCR Register */
+
+#define DLAB    0x80
+#define SB      0x40
+#define STP      0x20
+#define EPS     0x10
+#define PEN     0x08
+#define STB     0x04
+#define WLS(x)  ((x-5) & 0x03)
+
+#define DLAB_P  0x07
+#define SB_P    0x06
+#define STP_P   0x05
+#define EPS_P   0x04
+#define PEN_P   0x03
+#define STB_P   0x02
+#define WLS_P1  0x01
+#define WLS_P0  0x00
+
+/* UART_MCR Register */
+#define LOOP_ENA        0x10
+#define LOOP_ENA_P      0x04
+
+/* UART_LSR Register */
+#define TEMT    0x40
+#define THRE    0x20
+#define BI      0x10
+#define FE      0x08
+#define PE      0x04
+#define OE      0x02
+#define DR      0x01
+
+#define TEMP_P  0x06
+#define THRE_P  0x05
+#define BI_P    0x04
+#define FE_P    0x03
+#define PE_P    0x02
+#define OE_P    0x01
+#define DR_P    0x00
+
+/* UART_IER Register */
+#define ELSI    0x04
+#define ETBEI   0x02
+#define ERBFI   0x01
+
+#define ELSI_P  0x02
+#define ETBEI_P 0x01
+#define ERBFI_P 0x00
+
+/* UART_IIR Register */
+#define STATUS(x)       ((x << 1) & 0x06)
+#define NINT            0x01
+#define STATUS_P1       0x02
+#define STATUS_P0       0x01
+#define NINT_P          0x00
+#define IIR_TX_READY    0x02    /* UART_THR empty                               */
+#define IIR_RX_READY    0x04    /* Receive data ready                           */
+#define IIR_LINE_CHANGE 0x06    /* Receive line status                          */
+#define IIR_STATUS      0x06
+
+/* UART_GCTL Register */
+#define FFE     0x20
+#define FPE     0x10
+#define RPOLC   0x08
+#define TPOLC   0x04
+#define IREN    0x02
+#define UCEN    0x01
+
+#define FFE_P   0x05
+#define FPE_P   0x04
+#define RPOLC_P 0x03
+#define TPOLC_P 0x02
+#define IREN_P  0x01
+#define UCEN_P  0x00
+
+/* **********  SERIAL PORT MASKS  ********************** */
+
+/* SPORTx_TCR1 Masks */
+#define TSPEN    0x0001         /* TX enable  */
+#define ITCLK    0x0002         /* Internal TX Clock Select  */
+#define TDTYPE   0x000C         /* TX Data Formatting Select */
+#define TLSBIT   0x0010         /* TX Bit Order */
+#define ITFS     0x0200         /* Internal TX Frame Sync Select  */
+#define TFSR     0x0400         /* TX Frame Sync Required Select  */
+#define DITFS    0x0800         /* Data Independent TX Frame Sync Select  */
+#define LTFS     0x1000         /* Low TX Frame Sync Select  */
+#define LATFS    0x2000         /* Late TX Frame Sync Select  */
+#define TCKFE    0x4000         /* TX Clock Falling Edge Select  */
+
+/* SPORTx_TCR2 Masks */
+#define SLEN        0x001F      /*TX Word Length  */
+#define TXSE        0x0100      /*TX Secondary Enable */
+#define TSFSE       0x0200      /*TX Stereo Frame Sync Enable */
+#define TRFST       0x0400      /*TX Right-First Data Order  */
+
+/* SPORTx_RCR1 Masks */
+#define RSPEN    0x0001         /* RX enable  */
+#define IRCLK    0x0002         /* Internal RX Clock Select  */
+#define RDTYPE   0x000C         /* RX Data Formatting Select */
+#define RULAW    0x0008         /* u-Law enable  */
+#define RALAW    0x000C         /* A-Law enable  */
+#define RLSBIT   0x0010         /* RX Bit Order */
+#define IRFS     0x0200         /* Internal RX Frame Sync Select  */
+#define RFSR     0x0400         /* RX Frame Sync Required Select  */
+#define LRFS     0x1000         /* Low RX Frame Sync Select  */
+#define LARFS    0x2000         /* Late RX Frame Sync Select  */
+#define RCKFE    0x4000         /* RX Clock Falling Edge Select  */
+
+/* SPORTx_RCR2 Masks */
+#define SLEN        0x001F      /*RX Word Length  */
+#define RXSE        0x0100      /*RX Secondary Enable */
+#define RSFSE       0x0200      /*RX Stereo Frame Sync Enable */
+#define RRFST       0x0400      /*Right-First Data Order  */
+
+/*SPORTx_STAT Masks */
+#define RXNE            0x0001  /*RX FIFO Not Empty Status */
+#define RUVF            0x0002  /*RX Underflow Status */
+#define ROVF            0x0004  /*RX Overflow Status */
+#define TXF             0x0008  /*TX FIFO Full Status */
+#define TUVF            0x0010  /*TX Underflow Status */
+#define TOVF            0x0020  /*TX Overflow Status */
+#define TXHRE           0x0040  /*TX Hold Register Empty */
+
+/*SPORTx_MCMC1 Masks */
+#define SP_WSIZE                0x0000F000      /*Multichannel Window Size Field */
+#define SP_WOFF         0x000003FF      /*Multichannel Window Offset Field */
+
+/*SPORTx_MCMC2 Masks */
+#define MCCRM           0x00000003      /*Multichannel Clock Recovery Mode */
+#define MCDTXPE         0x00000004      /*Multichannel DMA Transmit Packing */
+#define MCDRXPE         0x00000008      /*Multichannel DMA Receive Packing */
+#define MCMEN           0x00000010      /*Multichannel Frame Mode Enable */
+#define FSDR            0x00000080      /*Multichannel Frame Sync to Data Relationship */
+#define MFD             0x0000F000      /*Multichannel Frame Delay    */
+
+/*  *********  PARALLEL PERIPHERAL INTERFACE (PPI) MASKS ****************   */
+
+/*  PPI_CONTROL Masks         */
+#define PORT_EN              0x00000001 /* PPI Port Enable  */
+#define PORT_DIR             0x00000002 /* PPI Port Direction       */
+#define XFR_TYPE             0x0000000C /* PPI Transfer Type  */
+#define PORT_CFG             0x00000030 /* PPI Port Configuration */
+#define FLD_SEL              0x00000040 /* PPI Active Field Select */
+#define PACK_EN              0x00000080 /* PPI Packing Mode */
+#define DMA32                0x00000100 /* PPI 32-bit DMA Enable */
+#define SKIP_EN              0x00000200 /* PPI Skip Element Enable */
+#define SKIP_EO              0x00000400 /* PPI Skip Even/Odd Elements */
+#define DLENGTH              0x00003800 /* PPI Data Length  */
+#define DLEN_8               0x0        /* PPI Data Length mask for DLEN=8 */
+#define DLEN(x) (((x-9) & 0x07) << 11)  /* PPI Data Length (only works for x=10-->x=16) */
+#define POL                  0x0000C000 /* PPI Signal Polarities       */
+
+/* PPI_STATUS Masks */
+#define FLD                  0x00000400 /* Field Indicator   */
+#define FT_ERR               0x00000800 /* Frame Track Error */
+#define OVR                  0x00001000 /* FIFO Overflow Error */
+#define UNDR                 0x00002000 /* FIFO Underrun Error */
+#define ERR_DET              0x00004000 /* Error Detected Indicator */
+#define ERR_NCOR             0x00008000 /* Error Not Corrected Indicator */
+
+/* **********  DMA CONTROLLER MASKS  *********************8 */
+
+/* DMAx_CONFIG, MDMA_yy_CONFIG, IMDMA_yy_CONFIG Masks */
+#define DMAEN           0x00000001      /* Channel Enable */
+#define WNR             0x00000002      /* Channel Direction (W/R*) */
+#define WDSIZE_8        0x00000000      /* Word Size 8 bits */
+#define WDSIZE_16       0x00000004      /* Word Size 16 bits */
+#define WDSIZE_32       0x00000008      /* Word Size 32 bits */
+#define DMA2D           0x00000010      /* 2D/1D* Mode */
+#define RESTART         0x00000020      /* Restart */
+#define DI_SEL          0x00000040      /* Data Interrupt Select */
+#define DI_EN           0x00000080      /* Data Interrupt Enable */
+#define NDSIZE_0                0x0000  /* Next Descriptor Size = 0 (Stop/Autobuffer)   */
+#define NDSIZE_1                0x0100  /* Next Descriptor Size = 1                                             */
+#define NDSIZE_2                0x0200  /* Next Descriptor Size = 2                                             */
+#define NDSIZE_3                0x0300  /* Next Descriptor Size = 3                                             */
+#define NDSIZE_4                0x0400  /* Next Descriptor Size = 4                                             */
+#define NDSIZE_5                0x0500  /* Next Descriptor Size = 5                                             */
+#define NDSIZE_6                0x0600  /* Next Descriptor Size = 6                                             */
+#define NDSIZE_7                0x0700  /* Next Descriptor Size = 7                                             */
+#define NDSIZE_8                0x0800  /* Next Descriptor Size = 8                                             */
+#define NDSIZE_9                0x0900  /* Next Descriptor Size = 9                                             */
+#define NDSIZE          0x00000900      /* Next Descriptor Size */
+#define DMAFLOW         0x00007000      /* Flow Control */
+#define DMAFLOW_STOP            0x0000  /* Stop Mode */
+#define DMAFLOW_AUTO            0x1000  /* Autobuffer Mode */
+#define DMAFLOW_ARRAY           0x4000  /* Descriptor Array Mode */
+#define DMAFLOW_SMALL           0x6000  /* Small Model Descriptor List Mode */
+#define DMAFLOW_LARGE           0x7000  /* Large Model Descriptor List Mode */
+
+#define DMAEN_P                 0       /* Channel Enable */
+#define WNR_P                   1       /* Channel Direction (W/R*) */
+#define DMA2D_P                 4       /* 2D/1D* Mode */
+#define RESTART_P               5       /* Restart */
+#define DI_SEL_P                6       /* Data Interrupt Select */
+#define DI_EN_P                 7       /* Data Interrupt Enable */
+
+/* DMAx_IRQ_STATUS, MDMA_yy_IRQ_STATUS, IMDMA_yy_IRQ_STATUS Masks */
+
+#define DMA_DONE                0x00000001      /* DMA Done Indicator */
+#define DMA_ERR                 0x00000002      /* DMA Error Indicator */
+#define DFETCH                  0x00000004      /* Descriptor Fetch Indicator */
+#define DMA_RUN                 0x00000008      /* DMA Running Indicator */
+
+#define DMA_DONE_P              0       /* DMA Done Indicator */
+#define DMA_ERR_P               1       /* DMA Error Indicator */
+#define DFETCH_P                2       /* Descriptor Fetch Indicator */
+#define DMA_RUN_P               3       /* DMA Running Indicator */
+
+/* DMAx_PERIPHERAL_MAP, MDMA_yy_PERIPHERAL_MAP, IMDMA_yy_PERIPHERAL_MAP Masks */
+
+#define CTYPE               0x00000040  /* DMA Channel Type Indicator */
+#define CTYPE_P             6   /* DMA Channel Type Indicator BIT POSITION */
+#define PCAP8               0x00000080  /* DMA 8-bit Operation Indicator   */
+#define PCAP16              0x00000100  /* DMA 16-bit Operation Indicator */
+#define PCAP32              0x00000200  /* DMA 32-bit Operation Indicator */
+#define PCAPWR              0x00000400  /* DMA Write Operation Indicator */
+#define PCAPRD              0x00000800  /* DMA Read Operation Indicator */
+#define PMAP                0x00007000  /* DMA Peripheral Map Field */
+
+/*  *************  GENERAL PURPOSE TIMER MASKS  ******************** */
+
+/* PWM Timer bit definitions */
+
+/* TIMER_ENABLE Register */
+#define TIMEN0  0x0001
+#define TIMEN1  0x0002
+#define TIMEN2  0x0004
+#define TIMEN3  0x0008
+#define TIMEN4  0x0010
+#define TIMEN5  0x0020
+#define TIMEN6  0x0040
+#define TIMEN7  0x0080
+#define TIMEN8  0x0001
+#define TIMEN9  0x0002
+#define TIMEN10 0x0004
+#define TIMEN11 0x0008
+
+#define TIMEN0_P        0x00
+#define TIMEN1_P        0x01
+#define TIMEN2_P        0x02
+#define TIMEN3_P        0x03
+#define TIMEN4_P        0x04
+#define TIMEN5_P        0x05
+#define TIMEN6_P        0x06
+#define TIMEN7_P        0x07
+#define TIMEN8_P        0x00
+#define TIMEN9_P        0x01
+#define TIMEN10_P       0x02
+#define TIMEN11_P       0x03
+
+/* TIMER_DISABLE Register */
+#define TIMDIS0         0x0001
+#define TIMDIS1         0x0002
+#define TIMDIS2         0x0004
+#define TIMDIS3         0x0008
+#define TIMDIS4         0x0010
+#define TIMDIS5         0x0020
+#define TIMDIS6         0x0040
+#define TIMDIS7         0x0080
+#define TIMDIS8         0x0001
+#define TIMDIS9         0x0002
+#define TIMDIS10        0x0004
+#define TIMDIS11        0x0008
+
+#define TIMDIS0_P       0x00
+#define TIMDIS1_P       0x01
+#define TIMDIS2_P       0x02
+#define TIMDIS3_P       0x03
+#define TIMDIS4_P       0x04
+#define TIMDIS5_P       0x05
+#define TIMDIS6_P       0x06
+#define TIMDIS7_P       0x07
+#define TIMDIS8_P       0x00
+#define TIMDIS9_P       0x01
+#define TIMDIS10_P      0x02
+#define TIMDIS11_P      0x03
+
+/* TIMER_STATUS Register */
+#define TIMIL0          0x00000001
+#define TIMIL1          0x00000002
+#define TIMIL2          0x00000004
+#define TIMIL3          0x00000008
+#define TIMIL4          0x00010000
+#define TIMIL5          0x00020000
+#define TIMIL6          0x00040000
+#define TIMIL7          0x00080000
+#define TIMIL8          0x0001
+#define TIMIL9          0x0002
+#define TIMIL10         0x0004
+#define TIMIL11         0x0008
+#define TOVL_ERR0       0x00000010
+#define TOVL_ERR1       0x00000020
+#define TOVL_ERR2       0x00000040
+#define TOVL_ERR3       0x00000080
+#define TOVL_ERR4       0x00100000
+#define TOVL_ERR5       0x00200000
+#define TOVL_ERR6       0x00400000
+#define TOVL_ERR7       0x00800000
+#define TOVL_ERR8       0x0010
+#define TOVL_ERR9       0x0020
+#define TOVL_ERR10      0x0040
+#define TOVL_ERR11      0x0080
+#define TRUN0           0x00001000
+#define TRUN1           0x00002000
+#define TRUN2           0x00004000
+#define TRUN3           0x00008000
+#define TRUN4           0x10000000
+#define TRUN5           0x20000000
+#define TRUN6           0x40000000
+#define TRUN7           0x80000000
+#define TRUN8           0x1000
+#define TRUN9           0x2000
+#define TRUN10          0x4000
+#define TRUN11          0x8000
+
+#define TIMIL0_P        0x00
+#define TIMIL1_P        0x01
+#define TIMIL2_P        0x02
+#define TIMIL3_P        0x03
+#define TIMIL4_P        0x10
+#define TIMIL5_P        0x11
+#define TIMIL6_P        0x12
+#define TIMIL7_P        0x13
+#define TIMIL8_P        0x00
+#define TIMIL9_P        0x01
+#define TIMIL10_P       0x02
+#define TIMIL11_P       0x03
+#define TOVL_ERR0_P     0x04
+#define TOVL_ERR1_P     0x05
+#define TOVL_ERR2_P     0x06
+#define TOVL_ERR3_P     0x07
+#define TOVL_ERR4_P     0x14
+#define TOVL_ERR5_P     0x15
+#define TOVL_ERR6_P     0x16
+#define TOVL_ERR7_P     0x17
+#define TOVL_ERR8_P     0x04
+#define TOVL_ERR9_P     0x05
+#define TOVL_ERR10_P    0x06
+#define TOVL_ERR11_P    0x07
+#define TRUN0_P         0x0C
+#define TRUN1_P         0x0D
+#define TRUN2_P         0x0E
+#define TRUN3_P         0x0F
+#define TRUN4_P         0x1C
+#define TRUN5_P         0x1D
+#define TRUN6_P         0x1E
+#define TRUN7_P         0x1F
+#define TRUN8_P         0x0C
+#define TRUN9_P         0x0D
+#define TRUN10_P        0x0E
+#define TRUN11_P        0x0F
+
+/* TIMERx_CONFIG Registers */
+#define PWM_OUT         0x0001
+#define WDTH_CAP        0x0002
+#define EXT_CLK         0x0003
+#define PULSE_HI        0x0004
+#define PERIOD_CNT      0x0008
+#define IRQ_ENA         0x0010
+#define TIN_SEL         0x0020
+#define OUT_DIS         0x0040
+#define CLK_SEL         0x0080
+#define TOGGLE_HI       0x0100
+#define EMU_RUN         0x0200
+#define ERR_TYP(x)      ((x & 0x03) << 14)
+
+#define TMODE_P0                0x00
+#define TMODE_P1                0x01
+#define PULSE_HI_P              0x02
+#define PERIOD_CNT_P            0x03
+#define IRQ_ENA_P               0x04
+#define TIN_SEL_P               0x05
+#define OUT_DIS_P               0x06
+#define CLK_SEL_P               0x07
+#define TOGGLE_HI_P             0x08
+#define EMU_RUN_P               0x09
+#define ERR_TYP_P0              0x0E
+#define ERR_TYP_P1              0x0F
+
+/*/ ******************   PROGRAMMABLE FLAG MASKS  ********************* */
+
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  Masks */
+#define PF0         0x0001
+#define PF1         0x0002
+#define PF2         0x0004
+#define PF3         0x0008
+#define PF4         0x0010
+#define PF5         0x0020
+#define PF6         0x0040
+#define PF7         0x0080
+#define PF8         0x0100
+#define PF9         0x0200
+#define PF10        0x0400
+#define PF11        0x0800
+#define PF12        0x1000
+#define PF13        0x2000
+#define PF14        0x4000
+#define PF15        0x8000
+
+/*  General Purpose IO (0xFFC00700 - 0xFFC007FF)  BIT POSITIONS */
+#define PF0_P         0
+#define PF1_P         1
+#define PF2_P         2
+#define PF3_P         3
+#define PF4_P         4
+#define PF5_P         5
+#define PF6_P         6
+#define PF7_P         7
+#define PF8_P         8
+#define PF9_P         9
+#define PF10_P        10
+#define PF11_P        11
+#define PF12_P        12
+#define PF13_P        13
+#define PF14_P        14
+#define PF15_P        15
+
+/* ***********  SERIAL PERIPHERAL INTERFACE (SPI) MASKS  **************** */
+
+/* SPI_CTL Masks */
+#define TIMOD                  0x00000003       /* Transfer initiation mode and interrupt generation */
+#define SZ                     0x00000004       /* Send Zero (=0) or last (=1) word when TDBR empty. */
+#define GM                     0x00000008       /* When RDBR full, get more (=1) data or discard (=0) incoming Data */
+#define PSSE                   0x00000010       /* Enable (=1) Slave-Select input for Master. */
+#define EMISO                  0x00000020       /* Enable (=1) MISO pin as an output. */
+#define SIZE                   0x00000100       /* Word length (0 => 8 bits, 1 => 16 bits) */
+#define LSBF                   0x00000200       /* Data format (0 => MSB sent/received first 1 => LSB sent/received first) */
+#define CPHA                   0x00000400       /* Clock phase (0 => SPICLK starts toggling in middle of xfer, 1 => SPICLK toggles at the beginning of xfer. */
+#define CPOL                   0x00000800       /* Clock polarity (0 => active-high, 1 => active-low) */
+#define MSTR                   0x00001000       /* Configures SPI as master (=1) or slave (=0) */
+#define WOM                    0x00002000       /* Open drain (=1) data output enable (for MOSI and MISO) */
+#define SPE                    0x00004000       /* SPI module enable (=1), disable (=0) */
+
+/* SPI_FLG Masks */
+#define FLS1                   0x00000002       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2                   0x00000004       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3                   0x00000008       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4                   0x00000010       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5                   0x00000020       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6                   0x00000040       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7                   0x00000080       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1                   0x00000200       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
+#define FLG2                   0x00000400       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3                   0x00000800       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
+#define FLG4                   0x00001000       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
+#define FLG5                   0x00002000       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
+#define FLG6                   0x00004000       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
+#define FLG7                   0x00008000       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_FLG Bit Positions */
+#define FLS1_P                 0x00000001       /* Enables (=1) SPI_FLOUT1 as flag output for SPI Slave-select */
+#define FLS2_P                 0x00000002       /* Enables (=1) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLS3_P                 0x00000003       /* Enables (=1) SPI_FLOUT3 as flag output for SPI Slave-select */
+#define FLS4_P                 0x00000004       /* Enables (=1) SPI_FLOUT4 as flag output for SPI Slave-select */
+#define FLS5_P                 0x00000005       /* Enables (=1) SPI_FLOUT5 as flag output for SPI Slave-select */
+#define FLS6_P                 0x00000006       /* Enables (=1) SPI_FLOUT6 as flag output for SPI Slave-select */
+#define FLS7_P                 0x00000007       /* Enables (=1) SPI_FLOUT7 as flag output for SPI Slave-select */
+#define FLG1_P                 0x00000009       /* Activates (=0) SPI_FLOUT1 as flag output for SPI Slave-select  */
+#define FLG2_P                 0x0000000A       /* Activates (=0) SPI_FLOUT2 as flag output for SPI Slave-select */
+#define FLG3_P                 0x0000000B       /* Activates (=0) SPI_FLOUT3 as flag output for SPI Slave-select  */
+#define FLG4_P                 0x0000000C       /* Activates (=0) SPI_FLOUT4 as flag output for SPI Slave-select  */
+#define FLG5_P                 0x0000000D       /* Activates (=0) SPI_FLOUT5 as flag output for SPI Slave-select  */
+#define FLG6_P                 0x0000000E       /* Activates (=0) SPI_FLOUT6 as flag output for SPI Slave-select  */
+#define FLG7_P                 0x0000000F       /* Activates (=0) SPI_FLOUT7 as flag output for SPI Slave-select */
+
+/* SPI_STAT Masks */
+#define SPIF                   0x00000001       /* Set (=1) when SPI single-word transfer complete */
+#define MODF                   0x00000002       /* Set (=1) in a master device when some other device tries to become master */
+#define TXE                    0x00000004       /* Set (=1) when transmission occurs with no new data in SPI_TDBR */
+#define TXS                    0x00000008       /* SPI_TDBR Data Buffer Status (0=Empty, 1=Full) */
+#define RBSY                   0x00000010       /* Set (=1) when data is received with RDBR full */
+#define RXS                    0x00000020       /* SPI_RDBR Data Buffer Status (0=Empty, 1=Full)  */
+#define TXCOL                  0x00000040       /* When set (=1), corrupt data may have been transmitted  */
+
+/* *********************  ASYNCHRONOUS MEMORY CONTROLLER MASKS  ************* */
+
+/* AMGCTL Masks */
+#define AMCKEN                  0x0001  /* Enable CLKOUT */
+#define AMBEN_B0                0x0002  /* Enable Asynchronous Memory Bank 0 only */
+#define AMBEN_B0_B1             0x0004  /* Enable Asynchronous Memory Banks 0 & 1 only */
+#define AMBEN_B0_B1_B2  0x0006  /* Enable Asynchronous Memory Banks 0, 1, and 2 */
+#define AMBEN_ALL               0x0008  /* Enable Asynchronous Memory Banks (all) 0, 1, 2, and 3 */
+#define B0_PEN                  0x0010  /* Enable 16-bit packing Bank 0  */
+#define B1_PEN                  0x0020  /* Enable 16-bit packing Bank 1  */
+#define B2_PEN                  0x0040  /* Enable 16-bit packing Bank 2  */
+#define B3_PEN                  0x0080  /* Enable 16-bit packing Bank 3  */
+
+/* AMGCTL Bit Positions */
+#define AMCKEN_P                0x00000000      /* Enable CLKOUT */
+#define AMBEN_P0                0x00000001      /* Asynchronous Memory Enable, 000 - banks 0-3 disabled, 001 - Bank 0 enabled */
+#define AMBEN_P1                0x00000002      /* Asynchronous Memory Enable, 010 - banks 0&1 enabled,  011 - banks 0-3 enabled */
+#define AMBEN_P2                0x00000003      /* Asynchronous Memory Enable, 1xx - All banks (bank 0, 1, 2, and 3) enabled */
+#define B0_PEN_P                        0x004   /* Enable 16-bit packing Bank 0  */
+#define B1_PEN_P                        0x005   /* Enable 16-bit packing Bank 1  */
+#define B2_PEN_P                        0x006   /* Enable 16-bit packing Bank 2  */
+#define B3_PEN_P                        0x007   /* Enable 16-bit packing Bank 3  */
+
+/* AMBCTL0 Masks */
+#define B0RDYEN 0x00000001      /* Bank 0 RDY Enable, 0=disable, 1=enable */
+#define B0RDYPOL 0x00000002     /* Bank 0 RDY Active high, 0=active low, 1=active high */
+#define B0TT_1  0x00000004      /* Bank 0 Transition Time from Read to Write = 1 cycle */
+#define B0TT_2  0x00000008      /* Bank 0 Transition Time from Read to Write = 2 cycles */
+#define B0TT_3  0x0000000C      /* Bank 0 Transition Time from Read to Write = 3 cycles */
+#define B0TT_4  0x00000000      /* Bank 0 Transition Time from Read to Write = 4 cycles */
+#define B0ST_1  0x00000010      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=1 cycle */
+#define B0ST_2  0x00000020      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=2 cycles */
+#define B0ST_3  0x00000030      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=3 cycles */
+#define B0ST_4  0x00000000      /* Bank 0 Setup Time from AOE asserted to Read/Write asserted=4 cycles */
+#define B0HT_1  0x00000040      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 1 cycle */
+#define B0HT_2  0x00000080      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 2 cycles */
+#define B0HT_3  0x000000C0      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 3 cycles */
+#define B0HT_0  0x00000000      /* Bank 0 Hold Time from Read/Write deasserted to AOE deasserted = 0 cycles */
+#define B0RAT_1                 0x00000100      /* Bank 0 Read Access Time = 1 cycle */
+#define B0RAT_2                 0x00000200      /* Bank 0 Read Access Time = 2 cycles */
+#define B0RAT_3                 0x00000300      /* Bank 0 Read Access Time = 3 cycles */
+#define B0RAT_4                 0x00000400      /* Bank 0 Read Access Time = 4 cycles */
+#define B0RAT_5                 0x00000500      /* Bank 0 Read Access Time = 5 cycles */
+#define B0RAT_6                 0x00000600      /* Bank 0 Read Access Time = 6 cycles */
+#define B0RAT_7                 0x00000700      /* Bank 0 Read Access Time = 7 cycles */
+#define B0RAT_8                 0x00000800      /* Bank 0 Read Access Time = 8 cycles */
+#define B0RAT_9                 0x00000900      /* Bank 0 Read Access Time = 9 cycles */
+#define B0RAT_10                0x00000A00      /* Bank 0 Read Access Time = 10 cycles */
+#define B0RAT_11                0x00000B00      /* Bank 0 Read Access Time = 11 cycles */
+#define B0RAT_12                0x00000C00      /* Bank 0 Read Access Time = 12 cycles */
+#define B0RAT_13                0x00000D00      /* Bank 0 Read Access Time = 13 cycles */
+#define B0RAT_14                0x00000E00      /* Bank 0 Read Access Time = 14 cycles */
+#define B0RAT_15                0x00000F00      /* Bank 0 Read Access Time = 15 cycles */
+#define B0WAT_1                 0x00001000      /* Bank 0 Write Access Time = 1 cycle */
+#define B0WAT_2                 0x00002000      /* Bank 0 Write Access Time = 2 cycles */
+#define B0WAT_3                 0x00003000      /* Bank 0 Write Access Time = 3 cycles */
+#define B0WAT_4                 0x00004000      /* Bank 0 Write Access Time = 4 cycles */
+#define B0WAT_5                 0x00005000      /* Bank 0 Write Access Time = 5 cycles */
+#define B0WAT_6                 0x00006000      /* Bank 0 Write Access Time = 6 cycles */
+#define B0WAT_7                 0x00007000      /* Bank 0 Write Access Time = 7 cycles */
+#define B0WAT_8                 0x00008000      /* Bank 0 Write Access Time = 8 cycles */
+#define B0WAT_9                 0x00009000      /* Bank 0 Write Access Time = 9 cycles */
+#define B0WAT_10                0x0000A000      /* Bank 0 Write Access Time = 10 cycles */
+#define B0WAT_11                0x0000B000      /* Bank 0 Write Access Time = 11 cycles */
+#define B0WAT_12                0x0000C000      /* Bank 0 Write Access Time = 12 cycles */
+#define B0WAT_13                0x0000D000      /* Bank 0 Write Access Time = 13 cycles */
+#define B0WAT_14                0x0000E000      /* Bank 0 Write Access Time = 14 cycles */
+#define B0WAT_15                0x0000F000      /* Bank 0 Write Access Time = 15 cycles */
+#define B1RDYEN                 0x00010000      /* Bank 1 RDY enable, 0=disable, 1=enable */
+#define B1RDYPOL                0x00020000      /* Bank 1 RDY Active high, 0=active low, 1=active high */
+#define B1TT_1                  0x00040000      /* Bank 1 Transition Time from Read to Write = 1 cycle */
+#define B1TT_2                  0x00080000      /* Bank 1 Transition Time from Read to Write = 2 cycles */
+#define B1TT_3                  0x000C0000      /* Bank 1 Transition Time from Read to Write = 3 cycles */
+#define B1TT_4                  0x00000000      /* Bank 1 Transition Time from Read to Write = 4 cycles */
+#define B1ST_1                  0x00100000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B1ST_2                  0x00200000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B1ST_3                  0x00300000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B1ST_4                  0x00000000      /* Bank 1 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B1HT_1                  0x00400000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B1HT_2                  0x00800000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B1HT_3                  0x00C00000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B1HT_0                  0x00000000      /* Bank 1 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B1RAT_1                 0x01000000      /* Bank 1 Read Access Time = 1 cycle */
+#define B1RAT_2                 0x02000000      /* Bank 1 Read Access Time = 2 cycles */
+#define B1RAT_3                 0x03000000      /* Bank 1 Read Access Time = 3 cycles */
+#define B1RAT_4                 0x04000000      /* Bank 1 Read Access Time = 4 cycles */
+#define B1RAT_5                 0x05000000      /* Bank 1 Read Access Time = 5 cycles */
+#define B1RAT_6                 0x06000000      /* Bank 1 Read Access Time = 6 cycles */
+#define B1RAT_7                 0x07000000      /* Bank 1 Read Access Time = 7 cycles */
+#define B1RAT_8                 0x08000000      /* Bank 1 Read Access Time = 8 cycles */
+#define B1RAT_9                 0x09000000      /* Bank 1 Read Access Time = 9 cycles */
+#define B1RAT_10                0x0A000000      /* Bank 1 Read Access Time = 10 cycles */
+#define B1RAT_11                0x0B000000      /* Bank 1 Read Access Time = 11 cycles */
+#define B1RAT_12                0x0C000000      /* Bank 1 Read Access Time = 12 cycles */
+#define B1RAT_13                0x0D000000      /* Bank 1 Read Access Time = 13 cycles */
+#define B1RAT_14                0x0E000000      /* Bank 1 Read Access Time = 14 cycles */
+#define B1RAT_15                0x0F000000      /* Bank 1 Read Access Time = 15 cycles */
+#define B1WAT_1                 0x10000000      /* Bank 1 Write Access Time = 1 cycle */
+#define B1WAT_2                 0x20000000      /* Bank 1 Write Access Time = 2 cycles */
+#define B1WAT_3                 0x30000000      /* Bank 1 Write Access Time = 3 cycles */
+#define B1WAT_4                 0x40000000      /* Bank 1 Write Access Time = 4 cycles */
+#define B1WAT_5                 0x50000000      /* Bank 1 Write Access Time = 5 cycles */
+#define B1WAT_6                 0x60000000      /* Bank 1 Write Access Time = 6 cycles */
+#define B1WAT_7                 0x70000000      /* Bank 1 Write Access Time = 7 cycles */
+#define B1WAT_8                 0x80000000      /* Bank 1 Write Access Time = 8 cycles */
+#define B1WAT_9                 0x90000000      /* Bank 1 Write Access Time = 9 cycles */
+#define B1WAT_10                0xA0000000      /* Bank 1 Write Access Time = 10 cycles */
+#define B1WAT_11                0xB0000000      /* Bank 1 Write Access Time = 11 cycles */
+#define B1WAT_12                0xC0000000      /* Bank 1 Write Access Time = 12 cycles */
+#define B1WAT_13                0xD0000000      /* Bank 1 Write Access Time = 13 cycles */
+#define B1WAT_14                0xE0000000      /* Bank 1 Write Access Time = 14 cycles */
+#define B1WAT_15                0xF0000000      /* Bank 1 Write Access Time = 15 cycles */
+
+/* AMBCTL1 Masks */
+#define B2RDYEN                 0x00000001      /* Bank 2 RDY Enable, 0=disable, 1=enable */
+#define B2RDYPOL                0x00000002      /* Bank 2 RDY Active high, 0=active low, 1=active high */
+#define B2TT_1                  0x00000004      /* Bank 2 Transition Time from Read to Write = 1 cycle */
+#define B2TT_2                  0x00000008      /* Bank 2 Transition Time from Read to Write = 2 cycles */
+#define B2TT_3                  0x0000000C      /* Bank 2 Transition Time from Read to Write = 3 cycles */
+#define B2TT_4                  0x00000000      /* Bank 2 Transition Time from Read to Write = 4 cycles */
+#define B2ST_1                  0x00000010      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B2ST_2                  0x00000020      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B2ST_3                  0x00000030      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B2ST_4                  0x00000000      /* Bank 2 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B2HT_1                  0x00000040      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B2HT_2                  0x00000080      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B2HT_3                  0x000000C0      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B2HT_0                  0x00000000      /* Bank 2 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B2RAT_1                 0x00000100      /* Bank 2 Read Access Time = 1 cycle */
+#define B2RAT_2                 0x00000200      /* Bank 2 Read Access Time = 2 cycles */
+#define B2RAT_3                 0x00000300      /* Bank 2 Read Access Time = 3 cycles */
+#define B2RAT_4                 0x00000400      /* Bank 2 Read Access Time = 4 cycles */
+#define B2RAT_5                 0x00000500      /* Bank 2 Read Access Time = 5 cycles */
+#define B2RAT_6                 0x00000600      /* Bank 2 Read Access Time = 6 cycles */
+#define B2RAT_7                 0x00000700      /* Bank 2 Read Access Time = 7 cycles */
+#define B2RAT_8                 0x00000800      /* Bank 2 Read Access Time = 8 cycles */
+#define B2RAT_9                 0x00000900      /* Bank 2 Read Access Time = 9 cycles */
+#define B2RAT_10                0x00000A00      /* Bank 2 Read Access Time = 10 cycles */
+#define B2RAT_11                0x00000B00      /* Bank 2 Read Access Time = 11 cycles */
+#define B2RAT_12                0x00000C00      /* Bank 2 Read Access Time = 12 cycles */
+#define B2RAT_13                0x00000D00      /* Bank 2 Read Access Time = 13 cycles */
+#define B2RAT_14                0x00000E00      /* Bank 2 Read Access Time = 14 cycles */
+#define B2RAT_15                0x00000F00      /* Bank 2 Read Access Time = 15 cycles */
+#define B2WAT_1                 0x00001000      /* Bank 2 Write Access Time = 1 cycle */
+#define B2WAT_2                 0x00002000      /* Bank 2 Write Access Time = 2 cycles */
+#define B2WAT_3                 0x00003000      /* Bank 2 Write Access Time = 3 cycles */
+#define B2WAT_4                 0x00004000      /* Bank 2 Write Access Time = 4 cycles */
+#define B2WAT_5                 0x00005000      /* Bank 2 Write Access Time = 5 cycles */
+#define B2WAT_6                 0x00006000      /* Bank 2 Write Access Time = 6 cycles */
+#define B2WAT_7                 0x00007000      /* Bank 2 Write Access Time = 7 cycles */
+#define B2WAT_8                 0x00008000      /* Bank 2 Write Access Time = 8 cycles */
+#define B2WAT_9                 0x00009000      /* Bank 2 Write Access Time = 9 cycles */
+#define B2WAT_10                0x0000A000      /* Bank 2 Write Access Time = 10 cycles */
+#define B2WAT_11                0x0000B000      /* Bank 2 Write Access Time = 11 cycles */
+#define B2WAT_12                0x0000C000      /* Bank 2 Write Access Time = 12 cycles */
+#define B2WAT_13                0x0000D000      /* Bank 2 Write Access Time = 13 cycles */
+#define B2WAT_14                0x0000E000      /* Bank 2 Write Access Time = 14 cycles */
+#define B2WAT_15                0x0000F000      /* Bank 2 Write Access Time = 15 cycles */
+#define B3RDYEN                 0x00010000      /* Bank 3 RDY enable, 0=disable, 1=enable */
+#define B3RDYPOL                0x00020000      /* Bank 3 RDY Active high, 0=active low, 1=active high */
+#define B3TT_1                  0x00040000      /* Bank 3 Transition Time from Read to Write = 1 cycle */
+#define B3TT_2                  0x00080000      /* Bank 3 Transition Time from Read to Write = 2 cycles */
+#define B3TT_3                  0x000C0000      /* Bank 3 Transition Time from Read to Write = 3 cycles */
+#define B3TT_4                  0x00000000      /* Bank 3 Transition Time from Read to Write = 4 cycles */
+#define B3ST_1                  0x00100000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 1 cycle */
+#define B3ST_2                  0x00200000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 2 cycles */
+#define B3ST_3                  0x00300000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 3 cycles */
+#define B3ST_4                  0x00000000      /* Bank 3 Setup Time from AOE asserted to Read or Write asserted = 4 cycles */
+#define B3HT_1                  0x00400000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 1 cycle */
+#define B3HT_2                  0x00800000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 2 cycles */
+#define B3HT_3                  0x00C00000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 3 cycles */
+#define B3HT_0                  0x00000000      /* Bank 3 Hold Time from Read or Write deasserted to AOE deasserted = 0 cycles */
+#define B3RAT_1                 0x01000000      /* Bank 3 Read Access Time = 1 cycle */
+#define B3RAT_2                 0x02000000      /* Bank 3 Read Access Time = 2 cycles */
+#define B3RAT_3                 0x03000000      /* Bank 3 Read Access Time = 3 cycles */
+#define B3RAT_4                 0x04000000      /* Bank 3 Read Access Time = 4 cycles */
+#define B3RAT_5                 0x05000000      /* Bank 3 Read Access Time = 5 cycles */
+#define B3RAT_6                 0x06000000      /* Bank 3 Read Access Time = 6 cycles */
+#define B3RAT_7                 0x07000000      /* Bank 3 Read Access Time = 7 cycles */
+#define B3RAT_8                 0x08000000      /* Bank 3 Read Access Time = 8 cycles */
+#define B3RAT_9                 0x09000000      /* Bank 3 Read Access Time = 9 cycles */
+#define B3RAT_10                0x0A000000      /* Bank 3 Read Access Time = 10 cycles */
+#define B3RAT_11                0x0B000000      /* Bank 3 Read Access Time = 11 cycles */
+#define B3RAT_12                0x0C000000      /* Bank 3 Read Access Time = 12 cycles */
+#define B3RAT_13                0x0D000000      /* Bank 3 Read Access Time = 13 cycles */
+#define B3RAT_14                0x0E000000      /* Bank 3 Read Access Time = 14 cycles */
+#define B3RAT_15                0x0F000000      /* Bank 3 Read Access Time = 15 cycles */
+#define B3WAT_1                 0x10000000      /* Bank 3 Write Access Time = 1 cycle */
+#define B3WAT_2                 0x20000000      /* Bank 3 Write Access Time = 2 cycles */
+#define B3WAT_3                 0x30000000      /* Bank 3 Write Access Time = 3 cycles */
+#define B3WAT_4                 0x40000000      /* Bank 3 Write Access Time = 4 cycles */
+#define B3WAT_5                 0x50000000      /* Bank 3 Write Access Time = 5 cycles */
+#define B3WAT_6                 0x60000000      /* Bank 3 Write Access Time = 6 cycles */
+#define B3WAT_7                 0x70000000      /* Bank 3 Write Access Time = 7 cycles */
+#define B3WAT_8                 0x80000000      /* Bank 3 Write Access Time = 8 cycles */
+#define B3WAT_9                 0x90000000      /* Bank 3 Write Access Time = 9 cycles */
+#define B3WAT_10                0xA0000000      /* Bank 3 Write Access Time = 10 cycles */
+#define B3WAT_11                0xB0000000      /* Bank 3 Write Access Time = 11 cycles */
+#define B3WAT_12                0xC0000000      /* Bank 3 Write Access Time = 12 cycles */
+#define B3WAT_13                0xD0000000      /* Bank 3 Write Access Time = 13 cycles */
+#define B3WAT_14                0xE0000000      /* Bank 3 Write Access Time = 14 cycles */
+#define B3WAT_15                0xF0000000      /* Bank 3 Write Access Time = 15 cycles */
+
+/* **********************  SDRAM CONTROLLER MASKS  *************************** */
+
+/* EBIU_SDGCTL Masks */
+#define SCTLE                   0x00000001      /* Enable SCLK[0], /SRAS, /SCAS, /SWE, SDQM[3:0] */
+#define CL_2                    0x00000008      /* SDRAM CAS latency = 2 cycles */
+#define CL_3                    0x0000000C      /* SDRAM CAS latency = 3 cycles */
+#define PFE                     0x00000010      /* Enable SDRAM prefetch */
+#define PFP                     0x00000020      /* Prefetch has priority over AMC requests */
+#define TRAS_1                  0x00000040      /* SDRAM tRAS = 1 cycle */
+#define TRAS_2                  0x00000080      /* SDRAM tRAS = 2 cycles */
+#define TRAS_3                  0x000000C0      /* SDRAM tRAS = 3 cycles */
+#define TRAS_4                  0x00000100      /* SDRAM tRAS = 4 cycles */
+#define TRAS_5                  0x00000140      /* SDRAM tRAS = 5 cycles */
+#define TRAS_6                  0x00000180      /* SDRAM tRAS = 6 cycles */
+#define TRAS_7                  0x000001C0      /* SDRAM tRAS = 7 cycles */
+#define TRAS_8                  0x00000200      /* SDRAM tRAS = 8 cycles */
+#define TRAS_9                  0x00000240      /* SDRAM tRAS = 9 cycles */
+#define TRAS_10                 0x00000280      /* SDRAM tRAS = 10 cycles */
+#define TRAS_11                 0x000002C0      /* SDRAM tRAS = 11 cycles */
+#define TRAS_12                 0x00000300      /* SDRAM tRAS = 12 cycles */
+#define TRAS_13                 0x00000340      /* SDRAM tRAS = 13 cycles */
+#define TRAS_14                 0x00000380      /* SDRAM tRAS = 14 cycles */
+#define TRAS_15                 0x000003C0      /* SDRAM tRAS = 15 cycles */
+#define TRP_1                   0x00000800      /* SDRAM tRP = 1 cycle */
+#define TRP_2                   0x00001000      /* SDRAM tRP = 2 cycles */
+#define TRP_3                   0x00001800      /* SDRAM tRP = 3 cycles */
+#define TRP_4                   0x00002000      /* SDRAM tRP = 4 cycles */
+#define TRP_5                   0x00002800      /* SDRAM tRP = 5 cycles */
+#define TRP_6                   0x00003000      /* SDRAM tRP = 6 cycles */
+#define TRP_7                   0x00003800      /* SDRAM tRP = 7 cycles */
+#define TRCD_1                  0x00008000      /* SDRAM tRCD = 1 cycle */
+#define TRCD_2                  0x00010000      /* SDRAM tRCD = 2 cycles */
+#define TRCD_3                  0x00018000      /* SDRAM tRCD = 3 cycles */
+#define TRCD_4                  0x00020000      /* SDRAM tRCD = 4 cycles */
+#define TRCD_5                  0x00028000      /* SDRAM tRCD = 5 cycles */
+#define TRCD_6                  0x00030000      /* SDRAM tRCD = 6 cycles */
+#define TRCD_7                  0x00038000      /* SDRAM tRCD = 7 cycles */
+#define TWR_1                   0x00080000      /* SDRAM tWR = 1 cycle */
+#define TWR_2                   0x00100000      /* SDRAM tWR = 2 cycles */
+#define TWR_3                   0x00180000      /* SDRAM tWR = 3 cycles */
+#define PUPSD                   0x00200000      /*Power-up start delay */
+#define PSM                     0x00400000      /* SDRAM power-up sequence = Precharge, mode register set, 8 CBR refresh cycles */
+#define PSS                             0x00800000      /* enable SDRAM power-up sequence on next SDRAM access */
+#define SRFS                    0x01000000      /* Start SDRAM self-refresh mode */
+#define EBUFE                   0x02000000      /* Enable external buffering timing */
+#define FBBRW                   0x04000000      /* Fast back-to-back read write enable */
+#define EMREN                   0x10000000      /* Extended mode register enable */
+#define TCSR                    0x20000000      /* Temp compensated self refresh value 85 deg C */
+#define CDDBG                   0x40000000      /* Tristate SDRAM controls during bus grant */
+
+/* EBIU_SDBCTL Masks */
+#define EB0_E                           0x00000001      /* Enable SDRAM external bank 0 */
+#define EB0_SZ_16                       0x00000000      /* SDRAM external bank size = 16MB */
+#define EB0_SZ_32                       0x00000002      /* SDRAM external bank size = 32MB */
+#define EB0_SZ_64                       0x00000004      /* SDRAM external bank size = 64MB */
+#define EB0_SZ_128                      0x00000006      /* SDRAM external bank size = 128MB */
+#define EB0_CAW_8                       0x00000000      /* SDRAM external bank column address width = 8 bits */
+#define EB0_CAW_9                       0x00000010      /* SDRAM external bank column address width = 9 bits */
+#define EB0_CAW_10                      0x00000020      /* SDRAM external bank column address width = 9 bits */
+#define EB0_CAW_11                      0x00000030      /* SDRAM external bank column address width = 9 bits */
+
+#define EB1_E                           0x00000100      /* Enable SDRAM external bank 1 */
+#define EB1__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
+#define EB1__SZ_32                      0x00000200      /* SDRAM external bank size = 32MB */
+#define EB1__SZ_64                      0x00000400      /* SDRAM external bank size = 64MB */
+#define EB1__SZ_128                     0x00000600      /* SDRAM external bank size = 128MB */
+#define EB1__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
+#define EB1__CAW_9                      0x00001000      /* SDRAM external bank column address width = 9 bits */
+#define EB1__CAW_10                     0x00002000      /* SDRAM external bank column address width = 9 bits */
+#define EB1__CAW_11                     0x00003000      /* SDRAM external bank column address width = 9 bits */
+
+#define EB2__E                          0x00010000      /* Enable SDRAM external bank 2 */
+#define EB2__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
+#define EB2__SZ_32                      0x00020000      /* SDRAM external bank size = 32MB */
+#define EB2__SZ_64                      0x00040000      /* SDRAM external bank size = 64MB */
+#define EB2__SZ_128                     0x00060000      /* SDRAM external bank size = 128MB */
+#define EB2__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
+#define EB2__CAW_9                      0x00100000      /* SDRAM external bank column address width = 9 bits */
+#define EB2__CAW_10                     0x00200000      /* SDRAM external bank column address width = 9 bits */
+#define EB2__CAW_11                     0x00300000      /* SDRAM external bank column address width = 9 bits */
+
+#define EB3__E                          0x01000000      /* Enable SDRAM external bank 3 */
+#define EB3__SZ_16                      0x00000000      /* SDRAM external bank size = 16MB */
+#define EB3__SZ_32                      0x02000000      /* SDRAM external bank size = 32MB */
+#define EB3__SZ_64                      0x04000000      /* SDRAM external bank size = 64MB */
+#define EB3__SZ_128                     0x06000000      /* SDRAM external bank size = 128MB */
+#define EB3__CAW_8                      0x00000000      /* SDRAM external bank column address width = 8 bits */
+#define EB3__CAW_9                      0x10000000      /* SDRAM external bank column address width = 9 bits */
+#define EB3__CAW_10                     0x20000000      /* SDRAM external bank column address width = 9 bits */
+#define EB3__CAW_11                     0x30000000      /* SDRAM external bank column address width = 9 bits */
+
+/* EBIU_SDSTAT Masks */
+#define SDCI                    0x00000001      /* SDRAM controller is idle  */
+#define SDSRA                   0x00000002      /* SDRAM SDRAM self refresh is active */
+#define SDPUA                   0x00000004      /* SDRAM power up active  */
+#define SDRS                    0x00000008      /* SDRAM is in reset state */
+#define SDEASE              0x00000010  /* SDRAM EAB sticky error status - W1C */
+#define BGSTAT                  0x00000020      /* Bus granted */
+
+/*VR_CTL Masks*/
+#define WAKE                    0x100
+#define VLEV_6                  0x60
+#define VLEV_7                  0x70
+#define VLEV_8                  0x80
+#define VLEV_9                  0x90
+#define VLEV_10                 0xA0
+#define VLEV_11                 0xB0
+#define VLEV_12                 0xC0
+#define VLEV_13                 0xD0
+#define VLEV_14                 0xE0
+#define VLEV_15                 0xF0
+#define FREQ_3                  0x03
+
+#endif                          /* _DEF_BF561_H */
diff --git a/include/asm-blackfin/mach-bf561/dma.h b/include/asm-blackfin/mach-bf561/dma.h
new file mode 100644
index 000000000000..21d982003e75
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/dma.h
@@ -0,0 +1,35 @@
+/*****************************************************************************
+*
+*        BF-533/2/1 Specific Declarations
+*
+****************************************************************************/
+
+#ifndef _MACH_DMA_H_
+#define _MACH_DMA_H_
+
+#define MAX_BLACKFIN_DMA_CHANNEL 36
+
+#define CH_PPI0                 0
+#define CH_PPI                  (CH_PPI0)
+#define CH_PPI1                 1
+#define CH_SPORT0_RX            12
+#define CH_SPORT0_TX            13
+#define CH_SPORT1_RX            14
+#define CH_SPORT1_TX            15
+#define CH_SPI                  16
+#define CH_UART_RX              17
+#define CH_UART_TX              18
+#define CH_MEM_STREAM0_DEST     24       /* TX */
+#define CH_MEM_STREAM0_SRC      25       /* RX */
+#define CH_MEM_STREAM1_DEST     26       /* TX */
+#define CH_MEM_STREAM1_SRC      27       /* RX */
+#define CH_MEM_STREAM2_DEST     28
+#define CH_MEM_STREAM2_SRC      29
+#define CH_MEM_STREAM3_SRC      30
+#define CH_MEM_STREAM3_DEST     31
+#define CH_IMEM_STREAM0_DEST    32
+#define CH_IMEM_STREAM0_SRC     33
+#define CH_IMEM_STREAM1_SRC     34
+#define CH_IMEM_STREAM1_DEST    35
+
+#endif
diff --git a/include/asm-blackfin/mach-bf561/irq.h b/include/asm-blackfin/mach-bf561/irq.h
new file mode 100644
index 000000000000..a753ce720d74
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/irq.h
@@ -0,0 +1,450 @@
+
+/*
+ * File:         include/asm-blackfin/mach-bf561/irq.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BF561_IRQ_H_
+#define _BF561_IRQ_H_
+
+/***********************************************************************
+ * Interrupt source definitions:
+             Event Source               Core Event Name     IRQ No
+                                                (highest priority)
+            Emulation Events                    EMU         0
+            Reset                               RST         1
+            NMI                                 NMI         2
+            Exception                           EVX         3
+            Reserved                            --          4
+            Hardware Error                      IVHW        5
+            Core Timer                          IVTMR       6 *
+
+            PLL Wakeup Interrupt                IVG7        7
+            DMA1 Error (generic)                IVG7        8
+            DMA2 Error (generic)                IVG7        9
+            IMDMA Error (generic)               IVG7        10
+            PPI1 Error Interrupt                IVG7        11
+            PPI2 Error Interrupt                IVG7        12
+            SPORT0 Error Interrupt              IVG7        13
+            SPORT1 Error Interrupt              IVG7        14
+            SPI Error Interrupt                 IVG7        15
+            UART Error Interrupt                IVG7        16
+            Reserved Interrupt                  IVG7        17
+
+            DMA1 0  Interrupt(PPI1)             IVG8        18
+            DMA1 1  Interrupt(PPI2)             IVG8        19
+            DMA1 2  Interrupt                   IVG8        20
+            DMA1 3  Interrupt                   IVG8        21
+            DMA1 4  Interrupt                   IVG8        22
+            DMA1 5  Interrupt                   IVG8        23
+            DMA1 6  Interrupt                   IVG8        24
+            DMA1 7  Interrupt                   IVG8        25
+            DMA1 8  Interrupt                   IVG8        26
+            DMA1 9  Interrupt                   IVG8        27
+            DMA1 10 Interrupt                   IVG8        28
+            DMA1 11 Interrupt                   IVG8        29
+
+            DMA2 0  (SPORT0 RX)                 IVG9        30
+            DMA2 1  (SPORT0 TX)                 IVG9        31
+            DMA2 2  (SPORT1 RX)                 IVG9        32
+            DMA2 3  (SPORT2 TX)                 IVG9        33
+            DMA2 4  (SPI)                       IVG9        34
+            DMA2 5  (UART RX)                   IVG9        35
+            DMA2 6  (UART TX)                   IVG9        36
+            DMA2 7  Interrupt                   IVG9        37
+            DMA2 8  Interrupt                   IVG9        38
+            DMA2 9  Interrupt                   IVG9        39
+            DMA2 10 Interrupt                   IVG9        40
+            DMA2 11 Interrupt                   IVG9        41
+
+            TIMER 0  Interrupt                  IVG10       42
+            TIMER 1  Interrupt                  IVG10       43
+            TIMER 2  Interrupt                  IVG10       44
+            TIMER 3  Interrupt                  IVG10       45
+            TIMER 4  Interrupt                  IVG10       46
+            TIMER 5  Interrupt                  IVG10       47
+            TIMER 6  Interrupt                  IVG10       48
+            TIMER 7  Interrupt                  IVG10       49
+            TIMER 8  Interrupt                  IVG10       50
+            TIMER 9  Interrupt                  IVG10       51
+            TIMER 10 Interrupt                  IVG10       52
+            TIMER 11 Interrupt                  IVG10       53
+
+            Programmable Flags0 A (8)           IVG11       54
+            Programmable Flags0 B (8)           IVG11       55
+            Programmable Flags1 A (8)           IVG11       56
+            Programmable Flags1 B (8)           IVG11       57
+            Programmable Flags2 A (8)           IVG11       58
+            Programmable Flags2 B (8)           IVG11       59
+
+            MDMA1 0 write/read INT              IVG8        60
+            MDMA1 1 write/read INT              IVG8        61
+
+            MDMA2 0 write/read INT              IVG9        62
+            MDMA2 1 write/read INT              IVG9        63
+
+            IMDMA 0 write/read INT              IVG12       64
+            IMDMA 1 write/read INT              IVG12       65
+
+            Watch Dog Timer                     IVG13       66
+
+            Reserved interrupt                  IVG7        67
+            Reserved interrupt                  IVG7        68
+            Supplemental interrupt 0            IVG7        69
+            supplemental interrupt 1            IVG7        70
+
+            Software Interrupt 1                IVG14       71
+            Software Interrupt 2                IVG15       72 *
+                                                (lowest priority)
+ **********************************************************************/
+
+#define SYS_IRQS                72
+#define NR_PERI_INTS            64
+
+/*
+ * The ABSTRACT IRQ definitions
+ *  the first seven of the following are fixed,
+ *  the rest you change if you need to.
+ */
+/* IVG 0-6*/
+#define IRQ_EMU                 0       /* Emulation                */
+#define IRQ_RST                 1       /* Reset                    */
+#define IRQ_NMI                 2       /* Non Maskable Interrupt   */
+#define IRQ_EVX                 3       /* Exception                */
+#define IRQ_UNUSED              4       /* Reserved interrupt       */
+#define IRQ_HWERR               5       /* Hardware Error           */
+#define IRQ_CORETMR             6       /* Core timer               */
+
+#define IVG_BASE                7
+/* IVG 7  */
+#define IRQ_PLL_WAKEUP          (IVG_BASE + 0)  /* PLL Wakeup Interrupt     */
+#define IRQ_DMA1_ERROR          (IVG_BASE + 1)  /* DMA1   Error (general)   */
+#define IRQ_DMA_ERROR           IRQ_DMA1_ERROR  /* DMA1   Error (general)   */
+#define IRQ_DMA2_ERROR          (IVG_BASE + 2)  /* DMA2   Error (general)   */
+#define IRQ_IMDMA_ERROR         (IVG_BASE + 3)  /* IMDMA  Error Interrupt   */
+#define IRQ_PPI1_ERROR          (IVG_BASE + 4)  /* PPI1   Error Interrupt   */
+#define IRQ_PPI_ERROR           IRQ_PPI1_ERROR  /* PPI1   Error Interrupt   */
+#define IRQ_PPI2_ERROR          (IVG_BASE + 5)  /* PPI2   Error Interrupt   */
+#define IRQ_SPORT0_ERROR        (IVG_BASE + 6)  /* SPORT0 Error Interrupt   */
+#define IRQ_SPORT1_ERROR        (IVG_BASE + 7)  /* SPORT1 Error Interrupt   */
+#define IRQ_SPI_ERROR           (IVG_BASE + 8)  /* SPI    Error Interrupt   */
+#define IRQ_UART_ERROR          (IVG_BASE + 9)  /* UART   Error Interrupt   */
+#define IRQ_RESERVED_ERROR      (IVG_BASE + 10) /* Reversed     Interrupt   */
+/* IVG 8  */
+#define IRQ_DMA1_0              (IVG_BASE + 11) /* DMA1 0  Interrupt(PPI1)  */
+#define IRQ_PPI                 IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
+#define IRQ_PPI0                IRQ_DMA1_0      /* DMA1 0  Interrupt(PPI1)  */
+#define IRQ_DMA1_1              (IVG_BASE + 12) /* DMA1 1  Interrupt(PPI2)  */
+#define IRQ_PPI1                IRQ_DMA1_1      /* DMA1 1  Interrupt(PPI2)  */
+#define IRQ_DMA1_2              (IVG_BASE + 13) /* DMA1 2  Interrupt        */
+#define IRQ_DMA1_3              (IVG_BASE + 14) /* DMA1 3  Interrupt        */
+#define IRQ_DMA1_4              (IVG_BASE + 15) /* DMA1 4  Interrupt        */
+#define IRQ_DMA1_5              (IVG_BASE + 16) /* DMA1 5  Interrupt        */
+#define IRQ_DMA1_6              (IVG_BASE + 17) /* DMA1 6  Interrupt        */
+#define IRQ_DMA1_7              (IVG_BASE + 18) /* DMA1 7  Interrupt        */
+#define IRQ_DMA1_8              (IVG_BASE + 19) /* DMA1 8  Interrupt        */
+#define IRQ_DMA1_9              (IVG_BASE + 20) /* DMA1 9  Interrupt        */
+#define IRQ_DMA1_10             (IVG_BASE + 21) /* DMA1 10 Interrupt        */
+#define IRQ_DMA1_11             (IVG_BASE + 22) /* DMA1 11 Interrupt        */
+/* IVG 9  */
+#define IRQ_DMA2_0              (IVG_BASE + 23) /* DMA2 0  (SPORT0 RX)      */
+#define IRQ_SPORT0_RX           IRQ_DMA2_0      /* DMA2 0  (SPORT0 RX)      */
+#define IRQ_DMA2_1              (IVG_BASE + 24) /* DMA2 1  (SPORT0 TX)      */
+#define IRQ_SPORT0_TX           IRQ_DMA2_1      /* DMA2 1  (SPORT0 TX)      */
+#define IRQ_DMA2_2              (IVG_BASE + 25) /* DMA2 2  (SPORT1 RX)      */
+#define IRQ_SPORT1_RX           IRQ_DMA2_2      /* DMA2 2  (SPORT1 RX)      */
+#define IRQ_DMA2_3              (IVG_BASE + 26) /* DMA2 3  (SPORT2 TX)      */
+#define IRQ_SPORT1_TX           IRQ_DMA2_3      /* DMA2 3  (SPORT2 TX)      */
+#define IRQ_DMA2_4              (IVG_BASE + 27) /* DMA2 4  (SPI)            */
+#define IRQ_SPI                 IRQ_DMA2_4      /* DMA2 4  (SPI)            */
+#define IRQ_DMA2_5              (IVG_BASE + 28) /* DMA2 5  (UART RX)        */
+#define IRQ_UART_RX             IRQ_DMA2_5      /* DMA2 5  (UART RX)        */
+#define IRQ_DMA2_6              (IVG_BASE + 29) /* DMA2 6  (UART TX)        */
+#define IRQ_UART_TX             IRQ_DMA2_6      /* DMA2 6  (UART TX)        */
+#define IRQ_DMA2_7              (IVG_BASE + 30) /* DMA2 7  Interrupt        */
+#define IRQ_DMA2_8              (IVG_BASE + 31) /* DMA2 8  Interrupt        */
+#define IRQ_DMA2_9              (IVG_BASE + 32) /* DMA2 9  Interrupt        */
+#define IRQ_DMA2_10             (IVG_BASE + 33) /* DMA2 10 Interrupt        */
+#define IRQ_DMA2_11             (IVG_BASE + 34) /* DMA2 11 Interrupt        */
+/* IVG 10 */
+#define IRQ_TIMER0              (IVG_BASE + 35) /* TIMER 0  Interrupt       */
+#define IRQ_TIMER1              (IVG_BASE + 36) /* TIMER 1  Interrupt       */
+#define IRQ_TIMER2              (IVG_BASE + 37) /* TIMER 2  Interrupt       */
+#define IRQ_TIMER3              (IVG_BASE + 38) /* TIMER 3  Interrupt       */
+#define IRQ_TIMER4              (IVG_BASE + 39) /* TIMER 4  Interrupt       */
+#define IRQ_TIMER5              (IVG_BASE + 40) /* TIMER 5  Interrupt       */
+#define IRQ_TIMER6              (IVG_BASE + 41) /* TIMER 6  Interrupt       */
+#define IRQ_TIMER7              (IVG_BASE + 42) /* TIMER 7  Interrupt       */
+#define IRQ_TIMER8              (IVG_BASE + 43) /* TIMER 8  Interrupt       */
+#define IRQ_TIMER9              (IVG_BASE + 44) /* TIMER 9  Interrupt       */
+#define IRQ_TIMER10             (IVG_BASE + 45) /* TIMER 10 Interrupt       */
+#define IRQ_TIMER11             (IVG_BASE + 46) /* TIMER 11 Interrupt       */
+/* IVG 11 */
+#define IRQ_PROG0_INTA          (IVG_BASE + 47) /* Programmable Flags0 A (8) */
+#define IRQ_PROG_INTA           IRQ_PROG0_INTA  /* Programmable Flags0 A (8) */
+#define IRQ_PROG0_INTB          (IVG_BASE + 48) /* Programmable Flags0 B (8) */
+#define IRQ_PROG_INTB           IRQ_PROG0_INTB  /* Programmable Flags0 B (8) */
+#define IRQ_PROG1_INTA          (IVG_BASE + 49) /* Programmable Flags1 A (8) */
+#define IRQ_PROG1_INTB          (IVG_BASE + 50) /* Programmable Flags1 B (8) */
+#define IRQ_PROG2_INTA          (IVG_BASE + 51) /* Programmable Flags2 A (8) */
+#define IRQ_PROG2_INTB          (IVG_BASE + 52) /* Programmable Flags2 B (8) */
+/* IVG 8  */
+#define IRQ_DMA1_WRRD0          (IVG_BASE + 53) /* MDMA1 0 write/read INT   */
+#define IRQ_DMA_WRRD0           IRQ_DMA1_WRRD0  /* MDMA1 0 write/read INT   */
+#define IRQ_MEM_DMA0            IRQ_DMA1_WRRD0
+#define IRQ_DMA1_WRRD1          (IVG_BASE + 54) /* MDMA1 1 write/read INT   */
+#define IRQ_DMA_WRRD1           IRQ_DMA1_WRRD1  /* MDMA1 1 write/read INT   */
+#define IRQ_MEM_DMA1            IRQ_DMA1_WRRD1
+/* IVG 9  */
+#define IRQ_DMA2_WRRD0          (IVG_BASE + 55) /* MDMA2 0 write/read INT   */
+#define IRQ_MEM_DMA2            IRQ_DMA2_WRRD0
+#define IRQ_DMA2_WRRD1          (IVG_BASE + 56) /* MDMA2 1 write/read INT   */
+#define IRQ_MEM_DMA3            IRQ_DMA2_WRRD1
+/* IVG 12 */
+#define IRQ_IMDMA_WRRD0         (IVG_BASE + 57) /* IMDMA 0 write/read INT   */
+#define IRQ_IMEM_DMA0           IRQ_IMDMA_WRRD0
+#define IRQ_IMDMA_WRRD1         (IVG_BASE + 58) /* IMDMA 1 write/read INT   */
+#define IRQ_IMEM_DMA1           IRQ_IMDMA_WRRD1
+/* IVG 13 */
+#define IRQ_WATCH               (IVG_BASE + 59) /* Watch Dog Timer          */
+/* IVG 7  */
+#define IRQ_RESERVED_1          (IVG_BASE + 60) /* Reserved interrupt       */
+#define IRQ_RESERVED_2          (IVG_BASE + 61) /* Reserved interrupt       */
+#define IRQ_SUPPLE_0            (IVG_BASE + 62) /* Supplemental interrupt 0 */
+#define IRQ_SUPPLE_1            (IVG_BASE + 63) /* supplemental interrupt 1 */
+#define IRQ_SW_INT1             71      /* Software Interrupt 1     */
+#define IRQ_SW_INT2             72      /* Software Interrupt 2     */
+                                                /* reserved for SYSCALL */
+#define IRQ_PF0                 73
+#define IRQ_PF1                 74
+#define IRQ_PF2                 75
+#define IRQ_PF3                 76
+#define IRQ_PF4                 77
+#define IRQ_PF5                 78
+#define IRQ_PF6                 79
+#define IRQ_PF7                 80
+#define IRQ_PF8                 81
+#define IRQ_PF9                 82
+#define IRQ_PF10                83
+#define IRQ_PF11                84
+#define IRQ_PF12                85
+#define IRQ_PF13                86
+#define IRQ_PF14                87
+#define IRQ_PF15                88
+#define IRQ_PF16                89
+#define IRQ_PF17                90
+#define IRQ_PF18                91
+#define IRQ_PF19                92
+#define IRQ_PF20                93
+#define IRQ_PF21                94
+#define IRQ_PF22                95
+#define IRQ_PF23                96
+#define IRQ_PF24                97
+#define IRQ_PF25                98
+#define IRQ_PF26                99
+#define IRQ_PF27                100
+#define IRQ_PF28                101
+#define IRQ_PF29                102
+#define IRQ_PF30                103
+#define IRQ_PF31                104
+#define IRQ_PF32                105
+#define IRQ_PF33                106
+#define IRQ_PF34                107
+#define IRQ_PF35                108
+#define IRQ_PF36                109
+#define IRQ_PF37                110
+#define IRQ_PF38                111
+#define IRQ_PF39                112
+#define IRQ_PF40                113
+#define IRQ_PF41                114
+#define IRQ_PF42                115
+#define IRQ_PF43                116
+#define IRQ_PF44                117
+#define IRQ_PF45                118
+#define IRQ_PF46                119
+#define IRQ_PF47                120
+
+#ifdef CONFIG_IRQCHIP_DEMUX_GPIO
+#define NR_IRQS                 (IRQ_PF47 + 1)
+#else
+#define NR_IRQS                 SYS_IRQS
+#endif
+
+#define IVG7                    7
+#define IVG8                    8
+#define IVG9                    9
+#define IVG10                   10
+#define IVG11                   11
+#define IVG12                   12
+#define IVG13                   13
+#define IVG14                   14
+#define IVG15                   15
+
+/*
+ * DEFAULT PRIORITIES:
+ */
+
+#define CONFIG_DEF_PLL_WAKEUP           7
+#define CONFIG_DEF_DMA1_ERROR           7
+#define CONFIG_DEF_DMA2_ERROR           7
+#define CONFIG_DEF_IMDMA_ERROR          7
+#define CONFIG_DEF_PPI1_ERROR           7
+#define CONFIG_DEF_PPI2_ERROR           7
+#define CONFIG_DEF_SPORT0_ERROR         7
+#define CONFIG_DEF_SPORT1_ERROR         7
+#define CONFIG_DEF_SPI_ERROR            7
+#define CONFIG_DEF_UART_ERROR           7
+#define CONFIG_DEF_RESERVED_ERROR       7
+#define CONFIG_DEF_DMA1_0               8
+#define CONFIG_DEF_DMA1_1               8
+#define CONFIG_DEF_DMA1_2               8
+#define CONFIG_DEF_DMA1_3               8
+#define CONFIG_DEF_DMA1_4               8
+#define CONFIG_DEF_DMA1_5               8
+#define CONFIG_DEF_DMA1_6               8
+#define CONFIG_DEF_DMA1_7               8
+#define CONFIG_DEF_DMA1_8               8
+#define CONFIG_DEF_DMA1_9               8
+#define CONFIG_DEF_DMA1_10              8
+#define CONFIG_DEF_DMA1_11              8
+#define CONFIG_DEF_DMA2_0               9
+#define CONFIG_DEF_DMA2_1               9
+#define CONFIG_DEF_DMA2_2               9
+#define CONFIG_DEF_DMA2_3               9
+#define CONFIG_DEF_DMA2_4               9
+#define CONFIG_DEF_DMA2_5               9
+#define CONFIG_DEF_DMA2_6               9
+#define CONFIG_DEF_DMA2_7               9
+#define CONFIG_DEF_DMA2_8               9
+#define CONFIG_DEF_DMA2_9               9
+#define CONFIG_DEF_DMA2_10              9
+#define CONFIG_DEF_DMA2_11              9
+#define CONFIG_DEF_TIMER0               10
+#define CONFIG_DEF_TIMER1               10
+#define CONFIG_DEF_TIMER2               10
+#define CONFIG_DEF_TIMER3               10
+#define CONFIG_DEF_TIMER4               10
+#define CONFIG_DEF_TIMER5               10
+#define CONFIG_DEF_TIMER6               10
+#define CONFIG_DEF_TIMER7               10
+#define CONFIG_DEF_TIMER8               10
+#define CONFIG_DEF_TIMER9               10
+#define CONFIG_DEF_TIMER10              10
+#define CONFIG_DEF_TIMER11              10
+#define CONFIG_DEF_PROG0_INTA           11
+#define CONFIG_DEF_PROG0_INTB           11
+#define CONFIG_DEF_PROG1_INTA           11
+#define CONFIG_DEF_PROG1_INTB           11
+#define CONFIG_DEF_PROG2_INTA           11
+#define CONFIG_DEF_PROG2_INTB           11
+#define CONFIG_DEF_DMA1_WRRD0           8
+#define CONFIG_DEF_DMA1_WRRD1           8
+#define CONFIG_DEF_DMA2_WRRD0           9
+#define CONFIG_DEF_DMA2_WRRD1           9
+#define CONFIG_DEF_IMDMA_WRRD0          12
+#define CONFIG_DEF_IMDMA_WRRD1          12
+#define CONFIG_DEF_WATCH                13
+#define CONFIG_DEF_RESERVED_1           7
+#define CONFIG_DEF_RESERVED_2           7
+#define CONFIG_DEF_SUPPLE_0             7
+#define CONFIG_DEF_SUPPLE_1             7
+
+/* IAR0 BIT FIELDS */
+#define IRQ_PLL_WAKEUP_POS                      0
+#define IRQ_DMA1_ERROR_POS                      4
+#define IRQ_DMA2_ERROR_POS                      8
+#define IRQ_IMDMA_ERROR_POS                     12
+#define IRQ_PPI0_ERROR_POS                      16
+#define IRQ_PPI1_ERROR_POS                      20
+#define IRQ_SPORT0_ERROR_POS            24
+#define IRQ_SPORT1_ERROR_POS            28
+/* IAR1 BIT FIELDS */
+#define IRQ_SPI_ERROR_POS                       0
+#define IRQ_UART_ERROR_POS                      4
+#define IRQ_RESERVED_ERROR_POS          8
+#define IRQ_DMA1_0_POS                  12
+#define IRQ_DMA1_1_POS                  16
+#define IRQ_DMA1_2_POS                  20
+#define IRQ_DMA1_3_POS                  24
+#define IRQ_DMA1_4_POS                  28
+/* IAR2 BIT FIELDS */
+#define IRQ_DMA1_5_POS                  0
+#define IRQ_DMA1_6_POS                  4
+#define IRQ_DMA1_7_POS                  8
+#define IRQ_DMA1_8_POS                  12
+#define IRQ_DMA1_9_POS                  16
+#define IRQ_DMA1_10_POS                 20
+#define IRQ_DMA1_11_POS                 24
+#define IRQ_DMA2_0_POS                  28
+/* IAR3 BIT FIELDS */
+#define IRQ_DMA2_1_POS                  0
+#define IRQ_DMA2_2_POS                  4
+#define IRQ_DMA2_3_POS                  8
+#define IRQ_DMA2_4_POS                  12
+#define IRQ_DMA2_5_POS                  16
+#define IRQ_DMA2_6_POS                  20
+#define IRQ_DMA2_7_POS                  24
+#define IRQ_DMA2_8_POS                  28
+/* IAR4 BIT FIELDS */
+#define IRQ_DMA2_9_POS                  0
+#define IRQ_DMA2_10_POS                 4
+#define IRQ_DMA2_11_POS                 8
+#define IRQ_TIMER0_POS                  12
+#define IRQ_TIMER1_POS                  16
+#define IRQ_TIMER2_POS                  20
+#define IRQ_TIMER3_POS                  24
+#define IRQ_TIMER4_POS                  28
+/* IAR5 BIT FIELDS */
+#define IRQ_TIMER5_POS                  0
+#define IRQ_TIMER6_POS                  4
+#define IRQ_TIMER7_POS                  8
+#define IRQ_TIMER8_POS                  12
+#define IRQ_TIMER9_POS                  16
+#define IRQ_TIMER10_POS                 20
+#define IRQ_TIMER11_POS                 24
+#define IRQ_PROG0_INTA_POS                      28
+/* IAR6 BIT FIELDS */
+#define IRQ_PROG0_INTB_POS                      0
+#define IRQ_PROG1_INTA_POS                      4
+#define IRQ_PROG1_INTB_POS                      8
+#define IRQ_PROG2_INTA_POS                      12
+#define IRQ_PROG2_INTB_POS                      16
+#define IRQ_DMA1_WRRD0_POS                      20
+#define IRQ_DMA1_WRRD1_POS                      24
+#define IRQ_DMA2_WRRD0_POS                      28
+/* IAR7 BIT FIELDS */
+#define IRQ_DMA2_WRRD1_POS                      0
+#define IRQ_IMDMA_WRRD0_POS                     4
+#define IRQ_IMDMA_WRRD1_POS                     8
+#define IRQ_WDTIMER_POS                 12
+#define IRQ_RESERVED_1_POS                      16
+#define IRQ_RESERVED_2_POS                      20
+#define IRQ_SUPPLE_0_POS                        24
+#define IRQ_SUPPLE_1_POS                        28
+
+#endif                          /* _BF561_IRQ_H_ */
diff --git a/include/asm-blackfin/mach-bf561/mem_init.h b/include/asm-blackfin/mach-bf561/mem_init.h
new file mode 100644
index 000000000000..439a5895b346
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/mem_init.h
@@ -0,0 +1,322 @@
+/*
+ * File:         include/asm-blackfin/mach-bf561/mem_init.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Rev:
+ *
+ * Modified:
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75 || CONFIG_MEM_MT48LC64M4A2FB_7E || CONFIG_MEM_GENERIC_BOARD || CONFIG_MEM_MT48LC8M32B2B5_7)
+#if (CONFIG_SCLK_HZ > 119402985)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_7
+#define SDRAM_tRAS_num  7
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 104477612) && (CONFIG_SCLK_HZ <= 119402985)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_6
+#define SDRAM_tRAS_num  6
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 89552239) && (CONFIG_SCLK_HZ <= 104477612)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_5
+#define SDRAM_tRAS_num  5
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 74626866) && (CONFIG_SCLK_HZ <= 89552239)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_4
+#define SDRAM_tRAS_num  4
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 66666667) && (CONFIG_SCLK_HZ <= 74626866)
+#define SDRAM_tRP       TRP_2
+#define SDRAM_tRP_num   2
+#define SDRAM_tRAS      TRAS_3
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_2
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 59701493) && (CONFIG_SCLK_HZ <= 66666667)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_4
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 44776119) && (CONFIG_SCLK_HZ <= 59701493)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_3
+#define SDRAM_tRAS_num  3
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ > 29850746) && (CONFIG_SCLK_HZ <= 44776119)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_2
+#define SDRAM_tRAS_num  2
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#if (CONFIG_SCLK_HZ <= 29850746)
+#define SDRAM_tRP       TRP_1
+#define SDRAM_tRP_num   1
+#define SDRAM_tRAS      TRAS_1
+#define SDRAM_tRAS_num  1
+#define SDRAM_tRCD      TRCD_1
+#define SDRAM_tWR       TWR_2
+#endif
+#endif
+
+#if (CONFIG_MEM_MT48LC16M16A2TG_75)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC64M4A2FB_7E)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_MT48LC8M32B2B5_7)
+  /*SDRAM INFORMATION: */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   4096        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_GENERIC_BOARD)
+  /*SDRAM INFORMATION: Modify this for your board */
+#define SDRAM_Tref  64          /* Refresh period in milliseconds   */
+#define SDRAM_NRA   8192        /* Number of row addresses in SDRAM */
+#define SDRAM_CL    CL_3
+#endif
+
+#if (CONFIG_MEM_SIZE == 128)
+#define SDRAM_SIZE      EB0_SZ_128
+#endif
+#if (CONFIG_MEM_SIZE == 64)
+#define SDRAM_SIZE      EB0_SZ_64
+#endif
+#if ( CONFIG_MEM_SIZE == 32)
+#define SDRAM_SIZE      EB0_SZ_32
+#endif
+#if (CONFIG_MEM_SIZE == 16)
+#define SDRAM_SIZE      EB0_SZ_16
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 11)
+#define SDRAM_WIDTH     EB0_CAW_11
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 10)
+#define SDRAM_WIDTH     EB0_CAW_10
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 9)
+#define SDRAM_WIDTH     EB0_CAW_9
+#endif
+#if (CONFIG_MEM_ADD_WIDTH == 8)
+#define SDRAM_WIDTH     EB0_CAW_8
+#endif
+
+#define mem_SDBCTL      (SDRAM_WIDTH | SDRAM_SIZE | EB0_E)
+
+/* Equation from section 17 (p17-46) of BF533 HRM */
+#define mem_SDRRC       (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num)
+
+/* Enable SCLK Out */
+#define mem_SDGCTL        (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS)
+
+#if defined CONFIG_CLKIN_HALF
+#define CLKIN_HALF       1
+#else
+#define CLKIN_HALF       0
+#endif
+
+#if defined CONFIG_PLL_BYPASS
+#define PLL_BYPASS      1
+#else
+#define PLL_BYPASS       0
+#endif
+
+/***************************************Currently Not Being Used *********************************/
+#define flash_EBIU_AMBCTL_WAT  ((CONFIG_FLASH_SPEED_BWAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_RAT  ((CONFIG_FLASH_SPEED_BRAT * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_HT   ((CONFIG_FLASH_SPEED_BHT  * 4) / (4000000000 / CONFIG_SCLK_HZ))
+#define flash_EBIU_AMBCTL_ST   ((CONFIG_FLASH_SPEED_BST  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+#define flash_EBIU_AMBCTL_TT   ((CONFIG_FLASH_SPEED_BTT  * 4) / (4000000000 / CONFIG_SCLK_HZ)) + 1
+
+#if (flash_EBIU_AMBCTL_TT > 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_4
+#endif
+#if (flash_EBIU_AMBCTL_TT == 3)
+#define flash_EBIU_AMBCTL0_TT   B0TT_3
+#endif
+#if (flash_EBIU_AMBCTL_TT == 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_2
+#endif
+#if (flash_EBIU_AMBCTL_TT < 2)
+#define flash_EBIU_AMBCTL0_TT   B0TT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_ST > 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_4
+#endif
+#if (flash_EBIU_AMBCTL_ST == 3)
+#define flash_EBIU_AMBCTL0_ST   B0ST_3
+#endif
+#if (flash_EBIU_AMBCTL_ST == 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_2
+#endif
+#if (flash_EBIU_AMBCTL_ST < 2)
+#define flash_EBIU_AMBCTL0_ST   B0ST_1
+#endif
+
+#if (flash_EBIU_AMBCTL_HT > 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_3
+#endif
+#if (flash_EBIU_AMBCTL_HT == 2)
+#define flash_EBIU_AMBCTL0_HT   B0HT_2
+#endif
+#if (flash_EBIU_AMBCTL_HT == 1)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT == 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_0
+#endif
+#if (flash_EBIU_AMBCTL_HT == 0 && CONFIG_FLASH_SPEED_BHT != 0)
+#define flash_EBIU_AMBCTL0_HT   B0HT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_WAT > 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_15
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 14)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_14
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 13)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_13
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 12)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_12
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 11)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_11
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 10)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_10
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 9)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_9
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 8)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_8
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 7)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_7
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 6)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_6
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 5)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_5
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 4)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_4
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 3)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_3
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 2)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_2
+#endif
+#if (flash_EBIU_AMBCTL_WAT == 1)
+#define flash_EBIU_AMBCTL0_WAT  B0WAT_1
+#endif
+
+#if (flash_EBIU_AMBCTL_RAT > 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_15
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 14)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_14
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 13)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_13
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 12)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_12
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 11)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_11
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 10)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_10
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 9)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_9
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 8)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_8
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 7)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_7
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 6)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_6
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 5)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_5
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 4)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_4
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 3)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_3
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 2)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_2
+#endif
+#if (flash_EBIU_AMBCTL_RAT == 1)
+#define flash_EBIU_AMBCTL0_RAT  B0RAT_1
+#endif
+
+#define flash_EBIU_AMBCTL0  \
+        (flash_EBIU_AMBCTL0_WAT | flash_EBIU_AMBCTL0_RAT | flash_EBIU_AMBCTL0_HT | \
+         flash_EBIU_AMBCTL0_ST | flash_EBIU_AMBCTL0_TT | CONFIG_FLASH_SPEED_RDYEN)
diff --git a/include/asm-blackfin/mach-bf561/mem_map.h b/include/asm-blackfin/mach-bf561/mem_map.h
new file mode 100644
index 000000000000..ebac9a8d838d
--- /dev/null
+++ b/include/asm-blackfin/mach-bf561/mem_map.h
@@ -0,0 +1,75 @@
+/*
+ * Memory MAP
+ * Common header file for blackfin BF561 of processors.
+ */
+
+#ifndef _MEM_MAP_561_H_
+#define _MEM_MAP_561_H_
+
+#define COREMMR_BASE           0xFFE00000        /* Core MMRs */
+#define SYSMMR_BASE            0xFFC00000        /* System MMRs */
+
+/* Async Memory Banks */
+#define ASYNC_BANK3_BASE        0x2C000000       /* Async Bank 3 */
+#define ASYNC_BANK3_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK2_BASE        0x28000000       /* Async Bank 2 */
+#define ASYNC_BANK2_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK1_BASE        0x24000000       /* Async Bank 1 */
+#define ASYNC_BANK1_SIZE        0x04000000      /* 64M */
+#define ASYNC_BANK0_BASE        0x20000000       /* Async Bank 0 */
+#define ASYNC_BANK0_SIZE        0x04000000      /* 64M */
+
+/* Level 1 Memory */
+
+#ifdef CONFIG_BLKFIN_CACHE
+#define BLKFIN_ICACHESIZE       (16*1024)
+#else
+#define BLKFIN_ICACHESIZE       (0*1024)
+#endif
+
+/* Memory Map for ADSP-BF561 processors */
+
+#ifdef CONFIG_BF561
+#define L1_CODE_START     0xFFA00000
+#define L1_DATA_A_START     0xFF800000
+#define L1_DATA_B_START     0xFF900000
+
+#define L1_CODE_LENGTH      0x4000
+
+#ifdef CONFIG_BLKFIN_DCACHE
+
+#ifdef CONFIG_BLKFIN_DCACHE_BANKA
+#define DMEM_CNTR (ACACHE_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (16*1024)
+#define BLKFIN_DSUPBANKS        1
+#else
+#define DMEM_CNTR (ACACHE_BCACHE | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      (0x8000 - 0x4000)
+#define L1_DATA_B_LENGTH      (0x8000 - 0x4000)
+#define BLKFIN_DCACHESIZE       (32*1024)
+#define BLKFIN_DSUPBANKS        2
+#endif
+
+#else
+#define DMEM_CNTR (ASRAM_BSRAM | ENDCPLB | PORT_PREF0)
+#define L1_DATA_A_LENGTH      0x8000
+#define L1_DATA_B_LENGTH      0x8000
+#define BLKFIN_DCACHESIZE       (0*1024)
+#define BLKFIN_DSUPBANKS        0
+#endif /*CONFIG_BLKFIN_DCACHE*/
+#endif
+
+/* Level 2 Memory */
+#define L2_START                0xFEB00000
+#define L2_LENGTH               0x20000
+
+/* Scratch Pad Memory */
+
+#if defined(CONFIG_BF561)
+#define L1_SCRATCH_START        0xFFB00000
+#define L1_SCRATCH_LENGTH       0x1000
+#endif
+
+#endif                          /* _MEM_MAP_533_H_ */
diff --git a/include/asm-blackfin/mach-common/cdef_LPBlackfin.h b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
new file mode 100644
index 000000000000..22aa5e637993
--- /dev/null
+++ b/include/asm-blackfin/mach-common/cdef_LPBlackfin.h
@@ -0,0 +1,471 @@
+ /*
+  * File:        include/asm-blackfin/mach-common/cdef_LPBlackfin.h
+  * Based on:
+  * Author:      unknown
+  *              COPYRIGHT 2005 Analog Devices
+  * Created:     ?
+  * Description:
+  *
+  * Modified:
+  *
+  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2, or (at your option)
+  * any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; see the file COPYING.
+  * If not, write to the Free Software Foundation,
+  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+  */
+
+#ifndef _CDEF_LPBLACKFIN_H
+#define _CDEF_LPBLACKFIN_H
+
+/*#if !defined(__ADSPLPBLACKFIN__)
+#warning cdef_LPBlackfin.h should only be included for 532 compatible chips.
+#endif
+*/
+#include <asm/mach-common/def_LPBlackfin.h>
+
+/*Cache & SRAM Memory*/
+#define pSRAM_BASE_ADDRESS ((volatile void **)SRAM_BASE_ADDRESS)
+#define bfin_read_SRAM_BASE_ADDRESS()        bfin_read32(SRAM_BASE_ADDRESS)
+#define bfin_write_SRAM_BASE_ADDRESS(val)    bfin_write32(SRAM_BASE_ADDRESS,val)
+#define pDMEM_CONTROL ((volatile unsigned long *)DMEM_CONTROL)
+#define bfin_read_DMEM_CONTROL()             bfin_read32(DMEM_CONTROL)
+#define bfin_write_DMEM_CONTROL(val)         bfin_write32(DMEM_CONTROL,val)
+#define pDCPLB_STATUS ((volatile unsigned long *)DCPLB_STATUS)
+#define bfin_read_DCPLB_STATUS()             bfin_read32(DCPLB_STATUS)
+#define bfin_write_DCPLB_STATUS(val)         bfin_write32(DCPLB_STATUS,val)
+#define pDCPLB_FAULT_ADDR ((volatile void **)DCPLB_FAULT_ADDR)
+#define bfin_read_DCPLB_FAULT_ADDR()         bfin_read32(DCPLB_FAULT_ADDR)
+#define bfin_write_DCPLB_FAULT_ADDR(val)     bfin_write32(DCPLB_FAULT_ADDR,val)
+/*
+#define MMR_TIMEOUT            0xFFE00010
+*/
+#define pDCPLB_ADDR0 ((volatile void **)DCPLB_ADDR0)
+#define bfin_read_DCPLB_ADDR0()              bfin_read32(DCPLB_ADDR0)
+#define bfin_write_DCPLB_ADDR0(val)          bfin_write32(DCPLB_ADDR0,val)
+#define pDCPLB_ADDR1 ((volatile void **)DCPLB_ADDR1)
+#define bfin_read_DCPLB_ADDR1()              bfin_read32(DCPLB_ADDR1)
+#define bfin_write_DCPLB_ADDR1(val)          bfin_write32(DCPLB_ADDR1,val)
+#define pDCPLB_ADDR2 ((volatile void **)DCPLB_ADDR2)
+#define bfin_read_DCPLB_ADDR2()              bfin_read32(DCPLB_ADDR2)
+#define bfin_write_DCPLB_ADDR2(val)          bfin_write32(DCPLB_ADDR2,val)
+#define pDCPLB_ADDR3 ((volatile void **)DCPLB_ADDR3)
+#define bfin_read_DCPLB_ADDR3()              bfin_read32(DCPLB_ADDR3)
+#define bfin_write_DCPLB_ADDR3(val)          bfin_write32(DCPLB_ADDR3,val)
+#define pDCPLB_ADDR4 ((volatile void **)DCPLB_ADDR4)
+#define bfin_read_DCPLB_ADDR4()              bfin_read32(DCPLB_ADDR4)
+#define bfin_write_DCPLB_ADDR4(val)          bfin_write32(DCPLB_ADDR4,val)
+#define pDCPLB_ADDR5 ((volatile void **)DCPLB_ADDR5)
+#define bfin_read_DCPLB_ADDR5()              bfin_read32(DCPLB_ADDR5)
+#define bfin_write_DCPLB_ADDR5(val)          bfin_write32(DCPLB_ADDR5,val)
+#define pDCPLB_ADDR6 ((volatile void **)DCPLB_ADDR6)
+#define bfin_read_DCPLB_ADDR6()              bfin_read32(DCPLB_ADDR6)
+#define bfin_write_DCPLB_ADDR6(val)          bfin_write32(DCPLB_ADDR6,val)
+#define pDCPLB_ADDR7 ((volatile void **)DCPLB_ADDR7)
+#define bfin_read_DCPLB_ADDR7()              bfin_read32(DCPLB_ADDR7)
+#define bfin_write_DCPLB_ADDR7(val)          bfin_write32(DCPLB_ADDR7,val)
+#define pDCPLB_ADDR8 ((volatile void **)DCPLB_ADDR8)
+#define bfin_read_DCPLB_ADDR8()              bfin_read32(DCPLB_ADDR8)
+#define bfin_write_DCPLB_ADDR8(val)          bfin_write32(DCPLB_ADDR8,val)
+#define pDCPLB_ADDR9 ((volatile void **)DCPLB_ADDR9)
+#define bfin_read_DCPLB_ADDR9()              bfin_read32(DCPLB_ADDR9)
+#define bfin_write_DCPLB_ADDR9(val)          bfin_write32(DCPLB_ADDR9,val)
+#define pDCPLB_ADDR10 ((volatile void **)DCPLB_ADDR10)
+#define bfin_read_DCPLB_ADDR10()             bfin_read32(DCPLB_ADDR10)
+#define bfin_write_DCPLB_ADDR10(val)         bfin_write32(DCPLB_ADDR10,val)
+#define pDCPLB_ADDR11 ((volatile void **)DCPLB_ADDR11)
+#define bfin_read_DCPLB_ADDR11()             bfin_read32(DCPLB_ADDR11)
+#define bfin_write_DCPLB_ADDR11(val)         bfin_write32(DCPLB_ADDR11,val)
+#define pDCPLB_ADDR12 ((volatile void **)DCPLB_ADDR12)
+#define bfin_read_DCPLB_ADDR12()             bfin_read32(DCPLB_ADDR12)
+#define bfin_write_DCPLB_ADDR12(val)         bfin_write32(DCPLB_ADDR12,val)
+#define pDCPLB_ADDR13 ((volatile void **)DCPLB_ADDR13)
+#define bfin_read_DCPLB_ADDR13()             bfin_read32(DCPLB_ADDR13)
+#define bfin_write_DCPLB_ADDR13(val)         bfin_write32(DCPLB_ADDR13,val)
+#define pDCPLB_ADDR14 ((volatile void **)DCPLB_ADDR14)
+#define bfin_read_DCPLB_ADDR14()             bfin_read32(DCPLB_ADDR14)
+#define bfin_write_DCPLB_ADDR14(val)         bfin_write32(DCPLB_ADDR14,val)
+#define pDCPLB_ADDR15 ((volatile void **)DCPLB_ADDR15)
+#define bfin_read_DCPLB_ADDR15()             bfin_read32(DCPLB_ADDR15)
+#define bfin_write_DCPLB_ADDR15(val)         bfin_write32(DCPLB_ADDR15,val)
+#define pDCPLB_DATA0 ((volatile unsigned long *)DCPLB_DATA0)
+#define bfin_read_DCPLB_DATA0()              bfin_read32(DCPLB_DATA0)
+#define bfin_write_DCPLB_DATA0(val)          bfin_write32(DCPLB_DATA0,val)
+#define pDCPLB_DATA1 ((volatile unsigned long *)DCPLB_DATA1)
+#define bfin_read_DCPLB_DATA1()              bfin_read32(DCPLB_DATA1)
+#define bfin_write_DCPLB_DATA1(val)          bfin_write32(DCPLB_DATA1,val)
+#define pDCPLB_DATA2 ((volatile unsigned long *)DCPLB_DATA2)
+#define bfin_read_DCPLB_DATA2()              bfin_read32(DCPLB_DATA2)
+#define bfin_write_DCPLB_DATA2(val)          bfin_write32(DCPLB_DATA2,val)
+#define pDCPLB_DATA3 ((volatile unsigned long *)DCPLB_DATA3)
+#define bfin_read_DCPLB_DATA3()              bfin_read32(DCPLB_DATA3)
+#define bfin_write_DCPLB_DATA3(val)          bfin_write32(DCPLB_DATA3,val)
+#define pDCPLB_DATA4 ((volatile unsigned long *)DCPLB_DATA4)
+#define bfin_read_DCPLB_DATA4()              bfin_read32(DCPLB_DATA4)
+#define bfin_write_DCPLB_DATA4(val)          bfin_write32(DCPLB_DATA4,val)
+#define pDCPLB_DATA5 ((volatile unsigned long *)DCPLB_DATA5)
+#define bfin_read_DCPLB_DATA5()              bfin_read32(DCPLB_DATA5)
+#define bfin_write_DCPLB_DATA5(val)          bfin_write32(DCPLB_DATA5,val)
+#define pDCPLB_DATA6 ((volatile unsigned long *)DCPLB_DATA6)
+#define bfin_read_DCPLB_DATA6()              bfin_read32(DCPLB_DATA6)
+#define bfin_write_DCPLB_DATA6(val)          bfin_write32(DCPLB_DATA6,val)
+#define pDCPLB_DATA7 ((volatile unsigned long *)DCPLB_DATA7)
+#define bfin_read_DCPLB_DATA7()              bfin_read32(DCPLB_DATA7)
+#define bfin_write_DCPLB_DATA7(val)          bfin_write32(DCPLB_DATA7,val)
+#define pDCPLB_DATA8 ((volatile unsigned long *)DCPLB_DATA8)
+#define bfin_read_DCPLB_DATA8()              bfin_read32(DCPLB_DATA8)
+#define bfin_write_DCPLB_DATA8(val)          bfin_write32(DCPLB_DATA8,val)
+#define pDCPLB_DATA9 ((volatile unsigned long *)DCPLB_DATA9)
+#define bfin_read_DCPLB_DATA9()              bfin_read32(DCPLB_DATA9)
+#define bfin_write_DCPLB_DATA9(val)          bfin_write32(DCPLB_DATA9,val)
+#define pDCPLB_DATA10 ((volatile unsigned long *)DCPLB_DATA10)
+#define bfin_read_DCPLB_DATA10()             bfin_read32(DCPLB_DATA10)
+#define bfin_write_DCPLB_DATA10(val)         bfin_write32(DCPLB_DATA10,val)
+#define pDCPLB_DATA11 ((volatile unsigned long *)DCPLB_DATA11)
+#define bfin_read_DCPLB_DATA11()             bfin_read32(DCPLB_DATA11)
+#define bfin_write_DCPLB_DATA11(val)         bfin_write32(DCPLB_DATA11,val)
+#define pDCPLB_DATA12 ((volatile unsigned long *)DCPLB_DATA12)
+#define bfin_read_DCPLB_DATA12()             bfin_read32(DCPLB_DATA12)
+#define bfin_write_DCPLB_DATA12(val)         bfin_write32(DCPLB_DATA12,val)
+#define pDCPLB_DATA13 ((volatile unsigned long *)DCPLB_DATA13)
+#define bfin_read_DCPLB_DATA13()             bfin_read32(DCPLB_DATA13)
+#define bfin_write_DCPLB_DATA13(val)         bfin_write32(DCPLB_DATA13,val)
+#define pDCPLB_DATA14 ((volatile unsigned long *)DCPLB_DATA14)
+#define bfin_read_DCPLB_DATA14()             bfin_read32(DCPLB_DATA14)
+#define bfin_write_DCPLB_DATA14(val)         bfin_write32(DCPLB_DATA14,val)
+#define pDCPLB_DATA15 ((volatile unsigned long *)DCPLB_DATA15)
+#define bfin_read_DCPLB_DATA15()             bfin_read32(DCPLB_DATA15)
+#define bfin_write_DCPLB_DATA15(val)         bfin_write32(DCPLB_DATA15,val)
+#define pDTEST_COMMAND ((volatile unsigned long *)DTEST_COMMAND)
+#define bfin_read_DTEST_COMMAND()            bfin_read32(DTEST_COMMAND)
+#define bfin_write_DTEST_COMMAND(val)        bfin_write32(DTEST_COMMAND,val)
+/*
+#define DTEST_INDEX            0xFFE00304
+*/
+#define pDTEST_DATA0 ((volatile unsigned long *)DTEST_DATA0)
+#define bfin_read_DTEST_DATA0()              bfin_read32(DTEST_DATA0)
+#define bfin_write_DTEST_DATA0(val)          bfin_write32(DTEST_DATA0,val)
+#define pDTEST_DATA1 ((volatile unsigned long *)DTEST_DATA1)
+#define bfin_read_DTEST_DATA1()              bfin_read32(DTEST_DATA1)
+#define bfin_write_DTEST_DATA1(val)          bfin_write32(DTEST_DATA1,val)
+/*
+#define DTEST_DATA2            0xFFE00408
+#define DTEST_DATA3            0xFFE0040C
+*/
+#define pIMEM_CONTROL ((volatile unsigned long *)IMEM_CONTROL)
+#define bfin_read_IMEM_CONTROL()             bfin_read32(IMEM_CONTROL)
+#define bfin_write_IMEM_CONTROL(val)         bfin_write32(IMEM_CONTROL,val)
+#define pICPLB_STATUS ((volatile unsigned long *)ICPLB_STATUS)
+#define bfin_read_ICPLB_STATUS()             bfin_read32(ICPLB_STATUS)
+#define bfin_write_ICPLB_STATUS(val)         bfin_write32(ICPLB_STATUS,val)
+#define pICPLB_FAULT_ADDR ((volatile void **)ICPLB_FAULT_ADDR)
+#define bfin_read_ICPLB_FAULT_ADDR()         bfin_read32(ICPLB_FAULT_ADDR)
+#define bfin_write_ICPLB_FAULT_ADDR(val)     bfin_write32(ICPLB_FAULT_ADDR,val)
+#define pICPLB_ADDR0 ((volatile void **)ICPLB_ADDR0)
+#define bfin_read_ICPLB_ADDR0()              bfin_read32(ICPLB_ADDR0)
+#define bfin_write_ICPLB_ADDR0(val)          bfin_write32(ICPLB_ADDR0,val)
+#define pICPLB_ADDR1 ((volatile void **)ICPLB_ADDR1)
+#define bfin_read_ICPLB_ADDR1()              bfin_read32(ICPLB_ADDR1)
+#define bfin_write_ICPLB_ADDR1(val)          bfin_write32(ICPLB_ADDR1,val)
+#define pICPLB_ADDR2 ((volatile void **)ICPLB_ADDR2)
+#define bfin_read_ICPLB_ADDR2()              bfin_read32(ICPLB_ADDR2)
+#define bfin_write_ICPLB_ADDR2(val)          bfin_write32(ICPLB_ADDR2,val)
+#define pICPLB_ADDR3 ((volatile void **)ICPLB_ADDR3)
+#define bfin_read_ICPLB_ADDR3()              bfin_read32(ICPLB_ADDR3)
+#define bfin_write_ICPLB_ADDR3(val)          bfin_write32(ICPLB_ADDR3,val)
+#define pICPLB_ADDR4 ((volatile void **)ICPLB_ADDR4)
+#define bfin_read_ICPLB_ADDR4()              bfin_read32(ICPLB_ADDR4)
+#define bfin_write_ICPLB_ADDR4(val)          bfin_write32(ICPLB_ADDR4,val)
+#define pICPLB_ADDR5 ((volatile void **)ICPLB_ADDR5)
+#define bfin_read_ICPLB_ADDR5()              bfin_read32(ICPLB_ADDR5)
+#define bfin_write_ICPLB_ADDR5(val)          bfin_write32(ICPLB_ADDR5,val)
+#define pICPLB_ADDR6 ((volatile void **)ICPLB_ADDR6)
+#define bfin_read_ICPLB_ADDR6()              bfin_read32(ICPLB_ADDR6)
+#define bfin_write_ICPLB_ADDR6(val)          bfin_write32(ICPLB_ADDR6,val)
+#define pICPLB_ADDR7 ((volatile void **)ICPLB_ADDR7)
+#define bfin_read_ICPLB_ADDR7()              bfin_read32(ICPLB_ADDR7)
+#define bfin_write_ICPLB_ADDR7(val)          bfin_write32(ICPLB_ADDR7,val)
+#define pICPLB_ADDR8 ((volatile void **)ICPLB_ADDR8)
+#define bfin_read_ICPLB_ADDR8()              bfin_read32(ICPLB_ADDR8)
+#define bfin_write_ICPLB_ADDR8(val)          bfin_write32(ICPLB_ADDR8,val)
+#define pICPLB_ADDR9 ((volatile void **)ICPLB_ADDR9)
+#define bfin_read_ICPLB_ADDR9()              bfin_read32(ICPLB_ADDR9)
+#define bfin_write_ICPLB_ADDR9(val)          bfin_write32(ICPLB_ADDR9,val)
+#define pICPLB_ADDR10 ((volatile void **)ICPLB_ADDR10)
+#define bfin_read_ICPLB_ADDR10()             bfin_read32(ICPLB_ADDR10)
+#define bfin_write_ICPLB_ADDR10(val)         bfin_write32(ICPLB_ADDR10,val)
+#define pICPLB_ADDR11 ((volatile void **)ICPLB_ADDR11)
+#define bfin_read_ICPLB_ADDR11()             bfin_read32(ICPLB_ADDR11)
+#define bfin_write_ICPLB_ADDR11(val)         bfin_write32(ICPLB_ADDR11,val)
+#define pICPLB_ADDR12 ((volatile void **)ICPLB_ADDR12)
+#define bfin_read_ICPLB_ADDR12()             bfin_read32(ICPLB_ADDR12)
+#define bfin_write_ICPLB_ADDR12(val)         bfin_write32(ICPLB_ADDR12,val)
+#define pICPLB_ADDR13 ((volatile void **)ICPLB_ADDR13)
+#define bfin_read_ICPLB_ADDR13()             bfin_read32(ICPLB_ADDR13)
+#define bfin_write_ICPLB_ADDR13(val)         bfin_write32(ICPLB_ADDR13,val)
+#define pICPLB_ADDR14 ((volatile void **)ICPLB_ADDR14)
+#define bfin_read_ICPLB_ADDR14()             bfin_read32(ICPLB_ADDR14)
+#define bfin_write_ICPLB_ADDR14(val)         bfin_write32(ICPLB_ADDR14,val)
+#define pICPLB_ADDR15 ((volatile void **)ICPLB_ADDR15)
+#define bfin_read_ICPLB_ADDR15()             bfin_read32(ICPLB_ADDR15)
+#define bfin_write_ICPLB_ADDR15(val)         bfin_write32(ICPLB_ADDR15,val)
+#define pICPLB_DATA0 ((volatile unsigned long *)ICPLB_DATA0)
+#define bfin_read_ICPLB_DATA0()              bfin_read32(ICPLB_DATA0)
+#define bfin_write_ICPLB_DATA0(val)          bfin_write32(ICPLB_DATA0,val)
+#define pICPLB_DATA1 ((volatile unsigned long *)ICPLB_DATA1)
+#define bfin_read_ICPLB_DATA1()              bfin_read32(ICPLB_DATA1)
+#define bfin_write_ICPLB_DATA1(val)          bfin_write32(ICPLB_DATA1,val)
+#define pICPLB_DATA2 ((volatile unsigned long *)ICPLB_DATA2)
+#define bfin_read_ICPLB_DATA2()              bfin_read32(ICPLB_DATA2)
+#define bfin_write_ICPLB_DATA2(val)          bfin_write32(ICPLB_DATA2,val)
+#define pICPLB_DATA3 ((volatile unsigned long *)ICPLB_DATA3)
+#define bfin_read_ICPLB_DATA3()              bfin_read32(ICPLB_DATA3)
+#define bfin_write_ICPLB_DATA3(val)          bfin_write32(ICPLB_DATA3,val)
+#define pICPLB_DATA4 ((volatile unsigned long *)ICPLB_DATA4)
+#define bfin_read_ICPLB_DATA4()              bfin_read32(ICPLB_DATA4)
+#define bfin_write_ICPLB_DATA4(val)          bfin_write32(ICPLB_DATA4,val)
+#define pICPLB_DATA5 ((volatile unsigned long *)ICPLB_DATA5)
+#define bfin_read_ICPLB_DATA5()              bfin_read32(ICPLB_DATA5)
+#define bfin_write_ICPLB_DATA5(val)          bfin_write32(ICPLB_DATA5,val)
+#define pICPLB_DATA6 ((volatile unsigned long *)ICPLB_DATA6)
+#define bfin_read_ICPLB_DATA6()              bfin_read32(ICPLB_DATA6)
+#define bfin_write_ICPLB_DATA6(val)          bfin_write32(ICPLB_DATA6,val)
+#define pICPLB_DATA7 ((volatile unsigned long *)ICPLB_DATA7)
+#define bfin_read_ICPLB_DATA7()              bfin_read32(ICPLB_DATA7)
+#define bfin_write_ICPLB_DATA7(val)          bfin_write32(ICPLB_DATA7,val)
+#define pICPLB_DATA8 ((volatile unsigned long *)ICPLB_DATA8)
+#define bfin_read_ICPLB_DATA8()              bfin_read32(ICPLB_DATA8)
+#define bfin_write_ICPLB_DATA8(val)          bfin_write32(ICPLB_DATA8,val)
+#define pICPLB_DATA9 ((volatile unsigned long *)ICPLB_DATA9)
+#define bfin_read_ICPLB_DATA9()              bfin_read32(ICPLB_DATA9)
+#define bfin_write_ICPLB_DATA9(val)          bfin_write32(ICPLB_DATA9,val)
+#define pICPLB_DATA10 ((volatile unsigned long *)ICPLB_DATA10)
+#define bfin_read_ICPLB_DATA10()             bfin_read32(ICPLB_DATA10)
+#define bfin_write_ICPLB_DATA10(val)         bfin_write32(ICPLB_DATA10,val)
+#define pICPLB_DATA11 ((volatile unsigned long *)ICPLB_DATA11)
+#define bfin_read_ICPLB_DATA11()             bfin_read32(ICPLB_DATA11)
+#define bfin_write_ICPLB_DATA11(val)         bfin_write32(ICPLB_DATA11,val)
+#define pICPLB_DATA12 ((volatile unsigned long *)ICPLB_DATA12)
+#define bfin_read_ICPLB_DATA12()             bfin_read32(ICPLB_DATA12)
+#define bfin_write_ICPLB_DATA12(val)         bfin_write32(ICPLB_DATA12,val)
+#define pICPLB_DATA13 ((volatile unsigned long *)ICPLB_DATA13)
+#define bfin_read_ICPLB_DATA13()             bfin_read32(ICPLB_DATA13)
+#define bfin_write_ICPLB_DATA13(val)         bfin_write32(ICPLB_DATA13,val)
+#define pICPLB_DATA14 ((volatile unsigned long *)ICPLB_DATA14)
+#define bfin_read_ICPLB_DATA14()             bfin_read32(ICPLB_DATA14)
+#define bfin_write_ICPLB_DATA14(val)         bfin_write32(ICPLB_DATA14,val)
+#define pICPLB_DATA15 ((volatile unsigned long *)ICPLB_DATA15)
+#define bfin_read_ICPLB_DATA15()             bfin_read32(ICPLB_DATA15)
+#define bfin_write_ICPLB_DATA15(val)         bfin_write32(ICPLB_DATA15,val)
+#define pITEST_COMMAND ((volatile unsigned long *)ITEST_COMMAND)
+#define bfin_read_ITEST_COMMAND()            bfin_read32(ITEST_COMMAND)
+#define bfin_write_ITEST_COMMAND(val)        bfin_write32(ITEST_COMMAND,val)
+#if 0
+#define ITEST_INDEX            0xFFE01304   /* Instruction Test Index Register */
+#endif
+#define pITEST_DATA0 ((volatile unsigned long *)ITEST_DATA0)
+#define bfin_read_ITEST_DATA0()              bfin_read32(ITEST_DATA0)
+#define bfin_write_ITEST_DATA0(val)          bfin_write32(ITEST_DATA0,val)
+#define pITEST_DATA1 ((volatile unsigned long *)ITEST_DATA1)
+#define bfin_read_ITEST_DATA1()              bfin_read32(ITEST_DATA1)
+#define bfin_write_ITEST_DATA1(val)          bfin_write32(ITEST_DATA1,val)
+
+/* Event/Interrupt Registers*/
+
+#define pEVT0 ((volatile void **)EVT0)
+#define bfin_read_EVT0()                     bfin_read32(EVT0)
+#define bfin_write_EVT0(val)                 bfin_write32(EVT0,val)
+#define pEVT1 ((volatile void **)EVT1)
+#define bfin_read_EVT1()                     bfin_read32(EVT1)
+#define bfin_write_EVT1(val)                 bfin_write32(EVT1,val)
+#define pEVT2 ((volatile void **)EVT2)
+#define bfin_read_EVT2()                     bfin_read32(EVT2)
+#define bfin_write_EVT2(val)                 bfin_write32(EVT2,val)
+#define pEVT3 ((volatile void **)EVT3)
+#define bfin_read_EVT3()                     bfin_read32(EVT3)
+#define bfin_write_EVT3(val)                 bfin_write32(EVT3,val)
+#define pEVT4 ((volatile void **)EVT4)
+#define bfin_read_EVT4()                     bfin_read32(EVT4)
+#define bfin_write_EVT4(val)                 bfin_write32(EVT4,val)
+#define pEVT5 ((volatile void **)EVT5)
+#define bfin_read_EVT5()                     bfin_read32(EVT5)
+#define bfin_write_EVT5(val)                 bfin_write32(EVT5,val)
+#define pEVT6 ((volatile void **)EVT6)
+#define bfin_read_EVT6()                     bfin_read32(EVT6)
+#define bfin_write_EVT6(val)                 bfin_write32(EVT6,val)
+#define pEVT7 ((volatile void **)EVT7)
+#define bfin_read_EVT7()                     bfin_read32(EVT7)
+#define bfin_write_EVT7(val)                 bfin_write32(EVT7,val)
+#define pEVT8 ((volatile void **)EVT8)
+#define bfin_read_EVT8()                     bfin_read32(EVT8)
+#define bfin_write_EVT8(val)                 bfin_write32(EVT8,val)
+#define pEVT9 ((volatile void **)EVT9)
+#define bfin_read_EVT9()                     bfin_read32(EVT9)
+#define bfin_write_EVT9(val)                 bfin_write32(EVT9,val)
+#define pEVT10 ((volatile void **)EVT10)
+#define bfin_read_EVT10()                    bfin_read32(EVT10)
+#define bfin_write_EVT10(val)                bfin_write32(EVT10,val)
+#define pEVT11 ((volatile void **)EVT11)
+#define bfin_read_EVT11()                    bfin_read32(EVT11)
+#define bfin_write_EVT11(val)                bfin_write32(EVT11,val)
+#define pEVT12 ((volatile void **)EVT12)
+#define bfin_read_EVT12()                    bfin_read32(EVT12)
+#define bfin_write_EVT12(val)                bfin_write32(EVT12,val)
+#define pEVT13 ((volatile void **)EVT13)
+#define bfin_read_EVT13()                    bfin_read32(EVT13)
+#define bfin_write_EVT13(val)                bfin_write32(EVT13,val)
+#define pEVT14 ((volatile void **)EVT14)
+#define bfin_read_EVT14()                    bfin_read32(EVT14)
+#define bfin_write_EVT14(val)                bfin_write32(EVT14,val)
+#define pEVT15 ((volatile void **)EVT15)
+#define bfin_read_EVT15()                    bfin_read32(EVT15)
+#define bfin_write_EVT15(val)                bfin_write32(EVT15,val)
+#define pIMASK ((volatile unsigned long *)IMASK)
+#define bfin_read_IMASK()                    bfin_read32(IMASK)
+#define bfin_write_IMASK(val)                bfin_write32(IMASK,val)
+#define pIPEND ((volatile unsigned long *)IPEND)
+#define bfin_read_IPEND()                    bfin_read32(IPEND)
+#define bfin_write_IPEND(val)                bfin_write32(IPEND,val)
+#define pILAT ((volatile unsigned long *)ILAT)
+#define bfin_read_ILAT()                     bfin_read32(ILAT)
+#define bfin_write_ILAT(val)                 bfin_write32(ILAT,val)
+
+/*Core Timer Registers*/
+#define pTCNTL ((volatile unsigned long *)TCNTL)
+#define bfin_read_TCNTL()                    bfin_read32(TCNTL)
+#define bfin_write_TCNTL(val)                bfin_write32(TCNTL,val)
+#define pTPERIOD ((volatile unsigned long *)TPERIOD)
+#define bfin_read_TPERIOD()                  bfin_read32(TPERIOD)
+#define bfin_write_TPERIOD(val)              bfin_write32(TPERIOD,val)
+#define pTSCALE ((volatile unsigned long *)TSCALE)
+#define bfin_read_TSCALE()                   bfin_read32(TSCALE)
+#define bfin_write_TSCALE(val)               bfin_write32(TSCALE,val)
+#define pTCOUNT ((volatile unsigned long *)TCOUNT)
+#define bfin_read_TCOUNT()                   bfin_read32(TCOUNT)
+#define bfin_write_TCOUNT(val)               bfin_write32(TCOUNT,val)
+
+/*Debug/MP/Emulation Registers*/
+#define pDSPID ((volatile unsigned long *)DSPID)
+#define bfin_read_DSPID()                    bfin_read32(DSPID)
+#define bfin_write_DSPID(val)                bfin_write32(DSPID,val)
+#define pDBGCTL ((volatile unsigned long *)DBGCTL)
+#define bfin_read_DBGCTL()                   bfin_read32(DBGCTL)
+#define bfin_write_DBGCTL(val)               bfin_write32(DBGCTL,val)
+#define pDBGSTAT ((volatile unsigned long *)DBGSTAT)
+#define bfin_read_DBGSTAT()                  bfin_read32(DBGSTAT)
+#define bfin_write_DBGSTAT(val)              bfin_write32(DBGSTAT,val)
+#define pEMUDAT ((volatile unsigned long *)EMUDAT)
+#define bfin_read_EMUDAT()                   bfin_read32(EMUDAT)
+#define bfin_write_EMUDAT(val)               bfin_write32(EMUDAT,val)
+
+/*Trace Buffer Registers*/
+#define pTBUFCTL ((volatile unsigned long *)TBUFCTL)
+#define bfin_read_TBUFCTL()                  bfin_read32(TBUFCTL)
+#define bfin_write_TBUFCTL(val)              bfin_write32(TBUFCTL,val)
+#define pTBUFSTAT ((volatile unsigned long *)TBUFSTAT)
+#define bfin_read_TBUFSTAT()                 bfin_read32(TBUFSTAT)
+#define bfin_write_TBUFSTAT(val)             bfin_write32(TBUFSTAT,val)
+#define pTBUF ((volatile void **)TBUF)
+#define bfin_read_TBUF()                     bfin_read32(TBUF)
+#define bfin_write_TBUF(val)                 bfin_write32(TBUF,val)
+
+/*Watch Point Control Registers*/
+#define pWPIACTL ((volatile unsigned long *)WPIACTL)
+#define bfin_read_WPIACTL()                  bfin_read32(WPIACTL)
+#define bfin_write_WPIACTL(val)              bfin_write32(WPIACTL,val)
+#define pWPIA0 ((volatile void **)WPIA0)
+#define bfin_read_WPIA0()                    bfin_read32(WPIA0)
+#define bfin_write_WPIA0(val)                bfin_write32(WPIA0,val)
+#define pWPIA1 ((volatile void **)WPIA1)
+#define bfin_read_WPIA1()                    bfin_read32(WPIA1)
+#define bfin_write_WPIA1(val)                bfin_write32(WPIA1,val)
+#define pWPIA2 ((volatile void **)WPIA2)
+#define bfin_read_WPIA2()                    bfin_read32(WPIA2)
+#define bfin_write_WPIA2(val)                bfin_write32(WPIA2,val)
+#define pWPIA3 ((volatile void **)WPIA3)
+#define bfin_read_WPIA3()                    bfin_read32(WPIA3)
+#define bfin_write_WPIA3(val)                bfin_write32(WPIA3,val)
+#define pWPIA4 ((volatile void **)WPIA4)
+#define bfin_read_WPIA4()                    bfin_read32(WPIA4)
+#define bfin_write_WPIA4(val)                bfin_write32(WPIA4,val)
+#define pWPIA5 ((volatile void **)WPIA5)
+#define bfin_read_WPIA5()                    bfin_read32(WPIA5)
+#define bfin_write_WPIA5(val)                bfin_write32(WPIA5,val)
+#define pWPIACNT0 ((volatile unsigned long *)WPIACNT0)
+#define bfin_read_WPIACNT0()                 bfin_read32(WPIACNT0)
+#define bfin_write_WPIACNT0(val)             bfin_write32(WPIACNT0,val)
+#define pWPIACNT1 ((volatile unsigned long *)WPIACNT1)
+#define bfin_read_WPIACNT1()                 bfin_read32(WPIACNT1)
+#define bfin_write_WPIACNT1(val)             bfin_write32(WPIACNT1,val)
+#define pWPIACNT2 ((volatile unsigned long *)WPIACNT2)
+#define bfin_read_WPIACNT2()                 bfin_read32(WPIACNT2)
+#define bfin_write_WPIACNT2(val)             bfin_write32(WPIACNT2,val)
+#define pWPIACNT3 ((volatile unsigned long *)WPIACNT3)
+#define bfin_read_WPIACNT3()                 bfin_read32(WPIACNT3)
+#define bfin_write_WPIACNT3(val)             bfin_write32(WPIACNT3,val)
+#define pWPIACNT4 ((volatile unsigned long *)WPIACNT4)
+#define bfin_read_WPIACNT4()                 bfin_read32(WPIACNT4)
+#define bfin_write_WPIACNT4(val)             bfin_write32(WPIACNT4,val)
+#define pWPIACNT5 ((volatile unsigned long *)WPIACNT5)
+#define bfin_read_WPIACNT5()                 bfin_read32(WPIACNT5)
+#define bfin_write_WPIACNT5(val)             bfin_write32(WPIACNT5,val)
+#define pWPDACTL ((volatile unsigned long *)WPDACTL)
+#define bfin_read_WPDACTL()                  bfin_read32(WPDACTL)
+#define bfin_write_WPDACTL(val)              bfin_write32(WPDACTL,val)
+#define pWPDA0 ((volatile void **)WPDA0)
+#define bfin_read_WPDA0()                    bfin_read32(WPDA0)
+#define bfin_write_WPDA0(val)                bfin_write32(WPDA0,val)
+#define pWPDA1 ((volatile void **)WPDA1)
+#define bfin_read_WPDA1()                    bfin_read32(WPDA1)
+#define bfin_write_WPDA1(val)                bfin_write32(WPDA1,val)
+#define pWPDACNT0 ((volatile unsigned long *)WPDACNT0)
+#define bfin_read_WPDACNT0()                 bfin_read32(WPDACNT0)
+#define bfin_write_WPDACNT0(val)             bfin_write32(WPDACNT0,val)
+#define pWPDACNT1 ((volatile unsigned long *)WPDACNT1)
+#define bfin_read_WPDACNT1()                 bfin_read32(WPDACNT1)
+#define bfin_write_WPDACNT1(val)             bfin_write32(WPDACNT1,val)
+#define pWPSTAT ((volatile unsigned long *)WPSTAT)
+#define bfin_read_WPSTAT()                   bfin_read32(WPSTAT)
+#define bfin_write_WPSTAT(val)               bfin_write32(WPSTAT,val)
+
+/*Performance Monitor Registers*/
+#define pPFCTL ((volatile unsigned long *)PFCTL)
+#define bfin_read_PFCTL()                    bfin_read32(PFCTL)
+#define bfin_write_PFCTL(val)                bfin_write32(PFCTL,val)
+#define pPFCNTR0 ((volatile unsigned long *)PFCNTR0)
+#define bfin_read_PFCNTR0()                  bfin_read32(PFCNTR0)
+#define bfin_write_PFCNTR0(val)              bfin_write32(PFCNTR0,val)
+#define pPFCNTR1 ((volatile unsigned long *)PFCNTR1)
+#define bfin_read_PFCNTR1()                  bfin_read32(PFCNTR1)
+#define bfin_write_PFCNTR1(val)              bfin_write32(PFCNTR1,val)
+
+/*
+#define IPRIO                  0xFFE02110
+*/
+
+#if defined(CONFIG_BFIN_ALIVE_LED)
+#define pCONFIG_BFIN_ALIVE_LED_DPORT \
+        (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_DPORT
+#define pCONFIG_BFIN_ALIVE_LED_PORT \
+        (volatile unsigned short *)CONFIG_BFIN_ALIVE_LED_PORT
+#endif
+
+#if defined(CONFIG_BFIN_IDLE_LED)
+#define pCONFIG_BFIN_IDLE_LED_DPORT \
+        (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_DPORT
+#define pCONFIG_BFIN_IDLE_LED_PORT \
+        (volatile unsigned short *)CONFIG_BFIN_IDLE_LED_PORT
+#endif
+
+#endif                          /* _CDEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/mach-common/context.S b/include/asm-blackfin/mach-common/context.S
new file mode 100644
index 000000000000..fd0ebe1862b8
--- /dev/null
+++ b/include/asm-blackfin/mach-common/context.S
@@ -0,0 +1,350 @@
+/*
+ * File:         arch/blackfin/kernel/context.S
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2007 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+/*
+ * Code to save processor context.
+ *  We even save the register which are preserved by a function call
+ *       - r4, r5, r6, r7, p3, p4, p5
+ */
+.macro save_context_with_interrupts
+        [--sp] = SYSCFG;
+
+        [--sp] = P0;    /*orig_p0*/
+        [--sp] = R0;    /*orig_r0*/
+
+        [--sp] = ( R7:0, P5:0 );
+        [--sp] = fp;
+        [--sp] = usp;
+
+        [--sp] = i0;
+        [--sp] = i1;
+        [--sp] = i2;
+        [--sp] = i3;
+
+        [--sp] = m0;
+        [--sp] = m1;
+        [--sp] = m2;
+        [--sp] = m3;
+
+        [--sp] = l0;
+        [--sp] = l1;
+        [--sp] = l2;
+        [--sp] = l3;
+
+        [--sp] = b0;
+        [--sp] = b1;
+        [--sp] = b2;
+        [--sp] = b3;
+        [--sp] = a0.x;
+        [--sp] = a0.w;
+        [--sp] = a1.x;
+        [--sp] = a1.w;
+
+        [--sp] = LC0;
+        [--sp] = LC1;
+        [--sp] = LT0;
+        [--sp] = LT1;
+        [--sp] = LB0;
+        [--sp] = LB1;
+
+        [--sp] = ASTAT;
+
+        [--sp] = r0;    /* Skip reserved */
+        [--sp] = RETS;
+        r0 = RETI;
+        [--sp] = r0;
+        [--sp] = RETX;
+        [--sp] = RETN;
+        [--sp] = RETE;
+        [--sp] = SEQSTAT;
+        [--sp] = r0;    /* Skip IPEND as well. */
+        /* Switch to other method of keeping interrupts disabled.  */
+#ifdef CONFIG_DEBUG_HWERR
+        r0 = 0x3f;
+        sti r0;
+#else
+        cli r0;
+#endif
+        [--sp] = RETI;  /*orig_pc*/
+        /* Clear all L registers.  */
+        r0 = 0 (x);
+        l0 = r0;
+        l1 = r0;
+        l2 = r0;
+        l3 = r0;
+.endm
+
+.macro save_context_syscall
+        [--sp] = SYSCFG;
+
+        [--sp] = P0;    /*orig_p0*/
+        [--sp] = R0;    /*orig_r0*/
+        [--sp] = ( R7:0, P5:0 );
+        [--sp] = fp;
+        [--sp] = usp;
+
+        [--sp] = i0;
+        [--sp] = i1;
+        [--sp] = i2;
+        [--sp] = i3;
+
+        [--sp] = m0;
+        [--sp] = m1;
+        [--sp] = m2;
+        [--sp] = m3;
+
+        [--sp] = l0;
+        [--sp] = l1;
+        [--sp] = l2;
+        [--sp] = l3;
+
+        [--sp] = b0;
+        [--sp] = b1;
+        [--sp] = b2;
+        [--sp] = b3;
+        [--sp] = a0.x;
+        [--sp] = a0.w;
+        [--sp] = a1.x;
+        [--sp] = a1.w;
+
+        [--sp] = LC0;
+        [--sp] = LC1;
+        [--sp] = LT0;
+        [--sp] = LT1;
+        [--sp] = LB0;
+        [--sp] = LB1;
+
+        [--sp] = ASTAT;
+
+        [--sp] = r0;    /* Skip reserved */
+        [--sp] = RETS;
+        r0 = RETI;
+        [--sp] = r0;
+        [--sp] = RETX;
+        [--sp] = RETN;
+        [--sp] = RETE;
+        [--sp] = SEQSTAT;
+        [--sp] = r0;    /* Skip IPEND as well. */
+        [--sp] = RETI;  /*orig_pc*/
+        /* Clear all L registers.  */
+        r0 = 0 (x);
+        l0 = r0;
+        l1 = r0;
+        l2 = r0;
+        l3 = r0;
+.endm
+
+.macro save_context_no_interrupts
+        [--sp] = SYSCFG;
+        [--sp] = P0;    /* orig_p0 */
+        [--sp] = R0;    /* orig_r0 */
+        [--sp] = ( R7:0, P5:0 );
+        [--sp] = fp;
+        [--sp] = usp;
+
+        [--sp] = i0;
+        [--sp] = i1;
+        [--sp] = i2;
+        [--sp] = i3;
+
+        [--sp] = m0;
+        [--sp] = m1;
+        [--sp] = m2;
+        [--sp] = m3;
+
+        [--sp] = l0;
+        [--sp] = l1;
+        [--sp] = l2;
+        [--sp] = l3;
+
+        [--sp] = b0;
+        [--sp] = b1;
+        [--sp] = b2;
+        [--sp] = b3;
+        [--sp] = a0.x;
+        [--sp] = a0.w;
+        [--sp] = a1.x;
+        [--sp] = a1.w;
+
+        [--sp] = LC0;
+        [--sp] = LC1;
+        [--sp] = LT0;
+        [--sp] = LT1;
+        [--sp] = LB0;
+        [--sp] = LB1;
+
+        [--sp] = ASTAT;
+
+#ifdef CONFIG_KGDB
+        fp     = 0(Z);
+        r1     = sp;
+        r1    += 60;
+        r1    += 60;
+        r1    += 60;
+        [--sp] = r1;
+#else
+        [--sp] = r0;    /* Skip reserved */
+#endif
+        [--sp] = RETS;
+        r0 = RETI;
+        [--sp] = r0;
+        [--sp] = RETX;
+        [--sp] = RETN;
+        [--sp] = RETE;
+        [--sp] = SEQSTAT;
+#ifdef CONFIG_KGDB
+        r1.l = lo(IPEND);
+        r1.h = hi(IPEND);
+        [--sp] = r1;
+#else
+        [--sp] = r0;    /* Skip IPEND as well. */
+#endif
+        [--sp] = r0;  /*orig_pc*/
+        /* Clear all L registers.  */
+        r0 = 0 (x);
+        l0 = r0;
+        l1 = r0;
+        l2 = r0;
+        l3 = r0;
+.endm
+
+.macro restore_context_no_interrupts
+        sp += 4;        /* Skip orig_pc */
+        sp += 4;        /* Skip IPEND */
+        SEQSTAT = [sp++];
+        RETE = [sp++];
+        RETN = [sp++];
+        RETX = [sp++];
+        r0 = [sp++];
+        RETI = r0;      /* Restore RETI indirectly when in exception */
+        RETS = [sp++];
+
+        sp += 4;        /* Skip Reserved */
+
+        ASTAT = [sp++];
+
+        LB1 = [sp++];
+        LB0 = [sp++];
+        LT1 = [sp++];
+        LT0 = [sp++];
+        LC1 = [sp++];
+        LC0 = [sp++];
+
+        a1.w = [sp++];
+        a1.x = [sp++];
+        a0.w = [sp++];
+        a0.x = [sp++];
+        b3 = [sp++];
+        b2 = [sp++];
+        b1 = [sp++];
+        b0 = [sp++];
+
+        l3 = [sp++];
+        l2 = [sp++];
+        l1 = [sp++];
+        l0 = [sp++];
+
+        m3 = [sp++];
+        m2 = [sp++];
+        m1 = [sp++];
+        m0 = [sp++];
+
+        i3 = [sp++];
+        i2 = [sp++];
+        i1 = [sp++];
+        i0 = [sp++];
+
+        sp += 4;
+        fp = [sp++];
+
+        ( R7 : 0, P5 : 0) = [ SP ++ ];
+        sp += 8;        /* Skip orig_r0/orig_p0 */
+        SYSCFG = [sp++];
+.endm
+
+.macro restore_context_with_interrupts
+        sp += 4;        /* Skip orig_pc */
+        sp += 4;        /* Skip IPEND */
+        SEQSTAT = [sp++];
+        RETE = [sp++];
+        RETN = [sp++];
+        RETX = [sp++];
+        RETI = [sp++];
+        RETS = [sp++];
+
+        p0.h = _irq_flags;
+        p0.l = _irq_flags;
+        r0 = [p0];
+        sti r0;
+
+        sp += 4;        /* Skip Reserved */
+
+        ASTAT = [sp++];
+
+        LB1 = [sp++];
+        LB0 = [sp++];
+        LT1 = [sp++];
+        LT0 = [sp++];
+        LC1 = [sp++];
+        LC0 = [sp++];
+
+        a1.w = [sp++];
+        a1.x = [sp++];
+        a0.w = [sp++];
+        a0.x = [sp++];
+        b3 = [sp++];
+        b2 = [sp++];
+        b1 = [sp++];
+        b0 = [sp++];
+
+        l3 = [sp++];
+        l2 = [sp++];
+        l1 = [sp++];
+        l0 = [sp++];
+
+        m3 = [sp++];
+        m2 = [sp++];
+        m1 = [sp++];
+        m0 = [sp++];
+
+        i3 = [sp++];
+        i2 = [sp++];
+        i1 = [sp++];
+        i0 = [sp++];
+
+        sp += 4;
+        fp = [sp++];
+
+        ( R7 : 0, P5 : 0) = [ SP ++ ];
+        sp += 8;        /* Skip orig_r0/orig_p0 */
+        csync;
+        SYSCFG = [sp++];
+        csync;
+.endm
+
diff --git a/include/asm-blackfin/mach-common/def_LPBlackfin.h b/include/asm-blackfin/mach-common/def_LPBlackfin.h
new file mode 100644
index 000000000000..76103526aec1
--- /dev/null
+++ b/include/asm-blackfin/mach-common/def_LPBlackfin.h
@@ -0,0 +1,691 @@
+ /*
+  * File:        include/asm-blackfin/mach-common/def_LPBlackfin.h
+  * Based on:
+  * Author:      unknown
+  *              COPYRIGHT 2005 Analog Devices
+  * Created:     ?
+  * Description:
+  *
+  * Modified:
+  *
+  * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+  *
+  * This program is free software; you can redistribute it and/or modify
+  * it under the terms of the GNU General Public License as published by
+  * the Free Software Foundation; either version 2, or (at your option)
+  * any later version.
+  *
+  * This program is distributed in the hope that it will be useful,
+  * but WITHOUT ANY WARRANTY; without even the implied warranty of
+  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  * GNU General Public License for more details.
+  *
+  * You should have received a copy of the GNU General Public License
+  * along with this program; see the file COPYING.
+  * If not, write to the Free Software Foundation,
+  * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+  */
+
+/* LP Blackfin CORE REGISTER BIT & ADDRESS DEFINITIONS FOR ADSP-BF532/33 */
+
+#ifndef _DEF_LPBLACKFIN_H
+#define _DEF_LPBLACKFIN_H
+
+#include <asm/mach/anomaly.h>
+
+/*#if !defined(__ADSPLPBLACKFIN__)
+#warning def_LPBlackfin.h should only be included for 532 compatible chips.
+#endif
+*/
+
+#define MK_BMSK_(x) (1<<x)
+
+#if defined(ANOMALY_05000198)
+
+#define bfin_read16(addr) ({ unsigned __v; \
+                       __asm__ __volatile__ ("NOP;\n\t"\
+                                                                "%0 = w[%1] (z);\n\t"\
+  : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
+
+#define bfin_read32(addr) ({ unsigned __v; \
+                      __asm__ __volatile__ ("NOP;\n\t"\
+                                            "%0 = [%1];\n\t"\
+  : "=d"(__v) : "a"(addr)); __v; })
+
+#define bfin_write16(addr,val) ({\
+                      __asm__ __volatile__ ("NOP;\n\t"\
+                                            "w[%0] = %1;\n\t"\
+  : : "a"(addr) , "d"(val) : "memory");})
+
+#define bfin_write32(addr,val) ({\
+                      __asm__ __volatile__ ("NOP;\n\t"\
+                                            "[%0] = %1;\n\t"\
+  : : "a"(addr) , "d"(val) : "memory");})
+
+#else
+
+#define bfin_read16(addr) ({ unsigned __v; \
+                       __asm__ __volatile__ (\
+                                                                "%0 = w[%1] (z);\n\t"\
+  : "=d"(__v) : "a"(addr)); (unsigned short)__v; })
+
+#define bfin_read32(addr) ({ unsigned __v; \
+                      __asm__ __volatile__ (\
+                                            "%0 = [%1];\n\t"\
+  : "=d"(__v) : "a"(addr)); __v; })
+
+#define bfin_write16(addr,val) ({\
+                      __asm__ __volatile__ (\
+                                            "w[%0] = %1;\n\t"\
+  : : "a"(addr) , "d"(val) : "memory");})
+
+#define bfin_write32(addr,val) ({\
+                      __asm__ __volatile__ (\
+                                            "[%0] = %1;\n\t"\
+  : : "a"(addr) , "d"(val) : "memory");})
+
+#endif
+
+/**************************************************
+ * System Register Bits
+ **************************************************/
+
+/**************************************************
+ * ASTAT register
+ **************************************************/
+
+/* definitions of ASTAT bit positions*/
+
+/*Result of last ALU0 or shifter operation is zero*/
+#define ASTAT_AZ_P         0x00000000
+/*Result of last ALU0 or shifter operation is negative*/
+#define ASTAT_AN_P         0x00000001
+/*Condition Code, used for holding comparison results*/
+#define ASTAT_CC_P         0x00000005
+/*Quotient Bit*/
+#define ASTAT_AQ_P         0x00000006
+/*Rounding mode, set for biased, clear for unbiased*/
+#define ASTAT_RND_MOD_P    0x00000008
+/*Result of last ALU0 operation generated a carry*/
+#define ASTAT_AC0_P        0x0000000C
+/*Result of last ALU0 operation generated a carry*/
+#define ASTAT_AC0_COPY_P   0x00000002
+/*Result of last ALU1 operation generated a carry*/
+#define ASTAT_AC1_P        0x0000000D
+/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
+#define ASTAT_AV0_P        0x00000010
+/*Sticky version of ASTAT_AV0 */
+#define ASTAT_AV0S_P       0x00000011
+/*Result of last MAC1 operation overflowed, sticky for MAC*/
+#define ASTAT_AV1_P        0x00000012
+/*Sticky version of ASTAT_AV1 */
+#define ASTAT_AV1S_P       0x00000013
+/*Result of last ALU0 or MAC0 operation overflowed*/
+#define ASTAT_V_P          0x00000018
+/*Result of last ALU0 or MAC0 operation overflowed*/
+#define ASTAT_V_COPY_P     0x00000003
+/*Sticky version of ASTAT_V*/
+#define ASTAT_VS_P         0x00000019
+
+/* Masks */
+
+/*Result of last ALU0 or shifter operation is zero*/
+#define ASTAT_AZ           MK_BMSK_(ASTAT_AZ_P)
+/*Result of last ALU0 or shifter operation is negative*/
+#define ASTAT_AN           MK_BMSK_(ASTAT_AN_P)
+/*Result of last ALU0 operation generated a carry*/
+#define ASTAT_AC0          MK_BMSK_(ASTAT_AC0_P)
+/*Result of last ALU0 operation generated a carry*/
+#define ASTAT_AC0_COPY     MK_BMSK_(ASTAT_AC0_COPY_P)
+/*Result of last ALU0 operation generated a carry*/
+#define ASTAT_AC1          MK_BMSK_(ASTAT_AC1_P)
+/*Result of last ALU0 or MAC0 operation overflowed, sticky for MAC*/
+#define ASTAT_AV0          MK_BMSK_(ASTAT_AV0_P)
+/*Result of last MAC1 operation overflowed, sticky for MAC*/
+#define ASTAT_AV1          MK_BMSK_(ASTAT_AV1_P)
+/*Condition Code, used for holding comparison results*/
+#define ASTAT_CC           MK_BMSK_(ASTAT_CC_P)
+/*Quotient Bit*/
+#define ASTAT_AQ           MK_BMSK_(ASTAT_AQ_P)
+/*Rounding mode, set for biased, clear for unbiased*/
+#define ASTAT_RND_MOD      MK_BMSK_(ASTAT_RND_MOD_P)
+/*Overflow Bit*/
+#define ASTAT_V            MK_BMSK_(ASTAT_V_P)
+/*Overflow Bit*/
+#define ASTAT_V_COPY       MK_BMSK_(ASTAT_V_COPY_P)
+
+/**************************************************
+ *   SEQSTAT register
+ **************************************************/
+
+/* Bit Positions  */
+#define SEQSTAT_EXCAUSE0_P      0x00000000      /* Last exception cause bit 0 */
+#define SEQSTAT_EXCAUSE1_P      0x00000001      /* Last exception cause bit 1 */
+#define SEQSTAT_EXCAUSE2_P      0x00000002      /* Last exception cause bit 2 */
+#define SEQSTAT_EXCAUSE3_P      0x00000003      /* Last exception cause bit 3 */
+#define SEQSTAT_EXCAUSE4_P      0x00000004      /* Last exception cause bit 4 */
+#define SEQSTAT_EXCAUSE5_P      0x00000005      /* Last exception cause bit 5 */
+#define SEQSTAT_IDLE_REQ_P      0x0000000C      /* Pending idle mode request,
+                                                 * set by IDLE instruction.
+                                                 */
+#define SEQSTAT_SFTRESET_P      0x0000000D      /* Indicates whether the last
+                                                 * reset was a software reset
+                                                 * (=1)
+                                                 */
+#define SEQSTAT_HWERRCAUSE0_P   0x0000000E      /* Last hw error cause bit 0 */
+#define SEQSTAT_HWERRCAUSE1_P   0x0000000F      /* Last hw error cause bit 1 */
+#define SEQSTAT_HWERRCAUSE2_P   0x00000010      /* Last hw error cause bit 2 */
+#define SEQSTAT_HWERRCAUSE3_P   0x00000011      /* Last hw error cause bit 3 */
+#define SEQSTAT_HWERRCAUSE4_P   0x00000012      /* Last hw error cause bit 4 */
+/* Masks */
+/* Exception cause */
+#define SEQSTAT_EXCAUSE        (MK_BMSK_(SEQSTAT_EXCAUSE0_P) | \
+                                MK_BMSK_(SEQSTAT_EXCAUSE1_P) | \
+                                MK_BMSK_(SEQSTAT_EXCAUSE2_P) | \
+                                MK_BMSK_(SEQSTAT_EXCAUSE3_P) | \
+                                MK_BMSK_(SEQSTAT_EXCAUSE4_P) | \
+                                MK_BMSK_(SEQSTAT_EXCAUSE5_P) | \
+                                0)
+
+/* Indicates whether the last reset was a software reset (=1) */
+#define SEQSTAT_SFTRESET       (MK_BMSK_(SEQSTAT_SFTRESET_P))
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE     (MK_BMSK_(SEQSTAT_HWERRCAUSE0_P) | \
+                                MK_BMSK_(SEQSTAT_HWERRCAUSE1_P) | \
+                                MK_BMSK_(SEQSTAT_HWERRCAUSE2_P) | \
+                                MK_BMSK_(SEQSTAT_HWERRCAUSE3_P) | \
+                                MK_BMSK_(SEQSTAT_HWERRCAUSE4_P) | \
+                                0)
+
+/* Translate bits to something useful */
+
+/* Last hw error cause */
+#define SEQSTAT_HWERRCAUSE_SHIFT         (14)
+#define SEQSTAT_HWERRCAUSE_SYSTEM_MMR    (0x02 << SEQSTAT_HWERRCAUSE_SHIFT)
+#define SEQSTAT_HWERRCAUSE_EXTERN_ADDR   (0x03 << SEQSTAT_HWERRCAUSE_SHIFT)
+#define SEQSTAT_HWERRCAUSE_PERF_FLOW     (0x12 << SEQSTAT_HWERRCAUSE_SHIFT)
+#define SEQSTAT_HWERRCAUSE_RAISE_5       (0x18 << SEQSTAT_HWERRCAUSE_SHIFT)
+
+/**************************************************
+ *   SYSCFG register
+ **************************************************/
+
+/* Bit Positions */
+#define SYSCFG_SSSTEP_P     0x00000000  /* Supervisor single step, when
+                                         * set it forces an exception
+                                         * for each instruction executed
+                                         */
+#define SYSCFG_CCEN_P       0x00000001  /* Enable cycle counter (=1) */
+#define SYSCFG_SNEN_P       0x00000002  /* Self nesting Interrupt Enable */
+
+/* Masks */
+
+/* Supervisor single step, when set it forces an exception for each
+ *instruction executed
+ */
+#define SYSCFG_SSSTEP         MK_BMSK_(SYSCFG_SSSTEP_P )
+/* Enable cycle counter (=1) */
+#define SYSCFG_CCEN           MK_BMSK_(SYSCFG_CCEN_P )
+/* Self Nesting Interrupt Enable */
+#define SYSCFG_SNEN            MK_BMSK_(SYSCFG_SNEN_P)
+/* Backward-compatibility for typos in prior releases */
+#define SYSCFG_SSSSTEP         SYSCFG_SSSTEP
+#define SYSCFG_CCCEN           SYSCFG_CCEN
+
+/****************************************************
+ * Core MMR Register Map
+ ****************************************************/
+
+/* Data Cache & SRAM Memory  (0xFFE00000 - 0xFFE00404) */
+
+#define SRAM_BASE_ADDRESS  0xFFE00000   /* SRAM Base Address Register */
+#define DMEM_CONTROL       0xFFE00004   /* Data memory control */
+#define DCPLB_STATUS       0xFFE00008   /* Data Cache Programmable Look-Aside
+                                         * Buffer Status
+                                         */
+#define DCPLB_FAULT_STATUS 0xFFE00008   /* "" (older define) */
+#define DCPLB_FAULT_ADDR   0xFFE0000C   /* Data Cache Programmable Look-Aside
+                                         * Buffer Fault Address
+                                         */
+#define DCPLB_ADDR0        0xFFE00100   /* Data Cache Protection Lookaside
+                                         * Buffer 0
+                                         */
+#define DCPLB_ADDR1        0xFFE00104   /* Data Cache Protection Lookaside
+                                         * Buffer 1
+                                         */
+#define DCPLB_ADDR2        0xFFE00108   /* Data Cache Protection Lookaside
+                                         * Buffer 2
+                                         */
+#define DCPLB_ADDR3        0xFFE0010C   /* Data Cacheability Protection
+                                         * Lookaside Buffer 3
+                                         */
+#define DCPLB_ADDR4        0xFFE00110   /* Data Cacheability Protection
+                                         * Lookaside Buffer 4
+                                         */
+#define DCPLB_ADDR5        0xFFE00114   /* Data Cacheability Protection
+                                         * Lookaside Buffer 5
+                                         */
+#define DCPLB_ADDR6        0xFFE00118   /* Data Cacheability Protection
+                                         * Lookaside Buffer 6
+                                         */
+#define DCPLB_ADDR7        0xFFE0011C   /* Data Cacheability Protection
+                                         * Lookaside Buffer 7
+                                         */
+#define DCPLB_ADDR8        0xFFE00120   /* Data Cacheability Protection
+                                         * Lookaside Buffer 8
+                                         */
+#define DCPLB_ADDR9        0xFFE00124   /* Data Cacheability Protection
+                                         * Lookaside Buffer 9
+                                         */
+#define DCPLB_ADDR10       0xFFE00128   /* Data Cacheability Protection
+                                         * Lookaside Buffer 10
+                                         */
+#define DCPLB_ADDR11       0xFFE0012C   /* Data Cacheability Protection
+                                         * Lookaside Buffer 11
+                                         */
+#define DCPLB_ADDR12       0xFFE00130   /* Data Cacheability Protection
+                                         * Lookaside Buffer 12
+                                         */
+#define DCPLB_ADDR13       0xFFE00134   /* Data Cacheability Protection
+                                         * Lookaside Buffer 13
+                                         */
+#define DCPLB_ADDR14       0xFFE00138   /* Data Cacheability Protection
+                                         * Lookaside Buffer 14
+                                         */
+#define DCPLB_ADDR15       0xFFE0013C   /* Data Cacheability Protection
+                                         * Lookaside Buffer 15
+                                         */
+#define DCPLB_DATA0        0xFFE00200   /* Data Cache 0 Status */
+#define DCPLB_DATA1        0xFFE00204   /* Data Cache 1 Status */
+#define DCPLB_DATA2        0xFFE00208   /* Data Cache 2 Status */
+#define DCPLB_DATA3        0xFFE0020C   /* Data Cache 3 Status */
+#define DCPLB_DATA4        0xFFE00210   /* Data Cache 4 Status */
+#define DCPLB_DATA5        0xFFE00214   /* Data Cache 5 Status */
+#define DCPLB_DATA6        0xFFE00218   /* Data Cache 6 Status */
+#define DCPLB_DATA7        0xFFE0021C   /* Data Cache 7 Status */
+#define DCPLB_DATA8        0xFFE00220   /* Data Cache 8 Status */
+#define DCPLB_DATA9        0xFFE00224   /* Data Cache 9 Status */
+#define DCPLB_DATA10       0xFFE00228   /* Data Cache 10 Status */
+#define DCPLB_DATA11       0xFFE0022C   /* Data Cache 11 Status */
+#define DCPLB_DATA12       0xFFE00230   /* Data Cache 12 Status */
+#define DCPLB_DATA13       0xFFE00234   /* Data Cache 13 Status */
+#define DCPLB_DATA14       0xFFE00238   /* Data Cache 14 Status */
+#define DCPLB_DATA15       0xFFE0023C   /* Data Cache 15 Status */
+#define DCPLB_DATA16       0xFFE00240   /* Extra Dummy entry */
+
+#define DTEST_COMMAND      0xFFE00300   /* Data Test Command Register */
+#define DTEST_DATA0        0xFFE00400   /* Data Test Data Register */
+#define DTEST_DATA1        0xFFE00404   /* Data Test Data Register */
+
+/* Instruction Cache & SRAM Memory  (0xFFE01004 - 0xFFE01404) */
+
+#define IMEM_CONTROL       0xFFE01004   /* Instruction Memory Control */
+#define ICPLB_STATUS       0xFFE01008   /* Instruction Cache miss status */
+#define CODE_FAULT_STATUS  0xFFE01008   /* "" (older define) */
+#define ICPLB_FAULT_ADDR   0xFFE0100C   /* Instruction Cache miss address */
+#define CODE_FAULT_ADDR    0xFFE0100C   /* "" (older define) */
+#define ICPLB_ADDR0        0xFFE01100   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 0
+                                         */
+#define ICPLB_ADDR1        0xFFE01104   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 1
+                                         */
+#define ICPLB_ADDR2        0xFFE01108   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 2
+                                         */
+#define ICPLB_ADDR3        0xFFE0110C   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 3
+                                         */
+#define ICPLB_ADDR4        0xFFE01110   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 4
+                                         */
+#define ICPLB_ADDR5        0xFFE01114   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 5
+                                         */
+#define ICPLB_ADDR6        0xFFE01118   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 6
+                                         */
+#define ICPLB_ADDR7        0xFFE0111C   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 7
+                                         */
+#define ICPLB_ADDR8        0xFFE01120   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 8
+                                         */
+#define ICPLB_ADDR9        0xFFE01124   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 9
+                                         */
+#define ICPLB_ADDR10       0xFFE01128   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 10
+                                         */
+#define ICPLB_ADDR11       0xFFE0112C   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 11
+                                         */
+#define ICPLB_ADDR12       0xFFE01130   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 12
+                                         */
+#define ICPLB_ADDR13       0xFFE01134   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 13
+                                         */
+#define ICPLB_ADDR14       0xFFE01138   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 14
+                                         */
+#define ICPLB_ADDR15       0xFFE0113C   /* Instruction Cacheability
+                                         * Protection Lookaside Buffer 15
+                                         */
+#define ICPLB_DATA0        0xFFE01200   /* Instruction Cache 0 Status */
+#define ICPLB_DATA1        0xFFE01204   /* Instruction Cache 1 Status */
+#define ICPLB_DATA2        0xFFE01208   /* Instruction Cache 2 Status */
+#define ICPLB_DATA3        0xFFE0120C   /* Instruction Cache 3 Status */
+#define ICPLB_DATA4        0xFFE01210   /* Instruction Cache 4 Status */
+#define ICPLB_DATA5        0xFFE01214   /* Instruction Cache 5 Status */
+#define ICPLB_DATA6        0xFFE01218   /* Instruction Cache 6 Status */
+#define ICPLB_DATA7        0xFFE0121C   /* Instruction Cache 7 Status */
+#define ICPLB_DATA8        0xFFE01220   /* Instruction Cache 8 Status */
+#define ICPLB_DATA9        0xFFE01224   /* Instruction Cache 9 Status */
+#define ICPLB_DATA10       0xFFE01228   /* Instruction Cache 10 Status */
+#define ICPLB_DATA11       0xFFE0122C   /* Instruction Cache 11 Status */
+#define ICPLB_DATA12       0xFFE01230   /* Instruction Cache 12 Status */
+#define ICPLB_DATA13       0xFFE01234   /* Instruction Cache 13 Status */
+#define ICPLB_DATA14       0xFFE01238   /* Instruction Cache 14 Status */
+#define ICPLB_DATA15       0xFFE0123C   /* Instruction Cache 15 Status */
+#define ITEST_COMMAND      0xFFE01300   /* Instruction Test Command Register */
+#define ITEST_DATA0        0xFFE01400   /* Instruction Test Data Register */
+#define ITEST_DATA1        0xFFE01404   /* Instruction Test Data Register */
+
+/* Event/Interrupt Controller Registers   (0xFFE02000 - 0xFFE02110) */
+
+#define EVT0               0xFFE02000   /* Event Vector 0 ESR Address */
+#define EVT1               0xFFE02004   /* Event Vector 1 ESR Address */
+#define EVT2               0xFFE02008   /* Event Vector 2 ESR Address */
+#define EVT3               0xFFE0200C   /* Event Vector 3 ESR Address */
+#define EVT4               0xFFE02010   /* Event Vector 4 ESR Address */
+#define EVT5               0xFFE02014   /* Event Vector 5 ESR Address */
+#define EVT6               0xFFE02018   /* Event Vector 6 ESR Address */
+#define EVT7               0xFFE0201C   /* Event Vector 7 ESR Address */
+#define EVT8               0xFFE02020   /* Event Vector 8 ESR Address */
+#define EVT9               0xFFE02024   /* Event Vector 9 ESR Address */
+#define EVT10              0xFFE02028   /* Event Vector 10 ESR Address */
+#define EVT11              0xFFE0202C   /* Event Vector 11 ESR Address */
+#define EVT12              0xFFE02030   /* Event Vector 12 ESR Address */
+#define EVT13              0xFFE02034   /* Event Vector 13 ESR Address */
+#define EVT14              0xFFE02038   /* Event Vector 14 ESR Address */
+#define EVT15              0xFFE0203C   /* Event Vector 15 ESR Address */
+#define IMASK              0xFFE02104   /* Interrupt Mask Register */
+#define IPEND              0xFFE02108   /* Interrupt Pending Register */
+#define ILAT               0xFFE0210C   /* Interrupt Latch Register */
+#define IPRIO              0xFFE02110   /* Core Interrupt Priority Register */
+
+/* Core Timer Registers     (0xFFE03000 - 0xFFE0300C) */
+
+#define TCNTL              0xFFE03000   /* Core Timer Control Register */
+#define TPERIOD            0xFFE03004   /* Core Timer Period Register */
+#define TSCALE             0xFFE03008   /* Core Timer Scale Register */
+#define TCOUNT             0xFFE0300C   /* Core Timer Count Register */
+
+/* Debug/MP/Emulation Registers     (0xFFE05000 - 0xFFE05008) */
+#define DSPID              0xFFE05000   /* DSP Processor ID Register for
+                                         * MP implementations
+                                         */
+
+#define DBGSTAT            0xFFE05008   /* Debug Status Register */
+
+/* Trace Buffer Registers     (0xFFE06000 - 0xFFE06100) */
+
+#define TBUFCTL            0xFFE06000   /* Trace Buffer Control Register */
+#define TBUFSTAT           0xFFE06004   /* Trace Buffer Status Register */
+#define TBUF               0xFFE06100   /* Trace Buffer */
+
+/* Watchpoint Control Registers (0xFFE07000 - 0xFFE07200) */
+
+/* Watchpoint Instruction Address Control Register */
+#define WPIACTL            0xFFE07000
+/* Watchpoint Instruction Address Register 0 */
+#define WPIA0              0xFFE07040
+/* Watchpoint Instruction Address Register 1 */
+#define WPIA1              0xFFE07044
+/* Watchpoint Instruction Address Register 2 */
+#define WPIA2              0xFFE07048
+/* Watchpoint Instruction Address Register 3 */
+#define WPIA3              0xFFE0704C
+/* Watchpoint Instruction Address Register 4 */
+#define WPIA4              0xFFE07050
+/* Watchpoint Instruction Address Register 5 */
+#define WPIA5              0xFFE07054
+/* Watchpoint Instruction Address Count Register 0 */
+#define WPIACNT0           0xFFE07080
+/* Watchpoint Instruction Address Count Register 1 */
+#define WPIACNT1           0xFFE07084
+/* Watchpoint Instruction Address Count Register 2 */
+#define WPIACNT2           0xFFE07088
+/* Watchpoint Instruction Address Count Register 3 */
+#define WPIACNT3           0xFFE0708C
+/* Watchpoint Instruction Address Count Register 4 */
+#define WPIACNT4           0xFFE07090
+/* Watchpoint Instruction Address Count Register 5 */
+#define WPIACNT5           0xFFE07094
+/* Watchpoint Data Address Control Register */
+#define WPDACTL            0xFFE07100
+/* Watchpoint Data Address Register 0 */
+#define WPDA0              0xFFE07140
+/* Watchpoint Data Address Register 1 */
+#define WPDA1              0xFFE07144
+/* Watchpoint Data Address Count Value Register 0 */
+#define WPDACNT0           0xFFE07180
+/* Watchpoint Data Address Count Value Register 1 */
+#define WPDACNT1           0xFFE07184
+/* Watchpoint Status Register */
+#define WPSTAT             0xFFE07200
+
+/* Performance Monitor Registers    (0xFFE08000 - 0xFFE08104) */
+
+/* Performance Monitor Control Register */
+#define PFCTL              0xFFE08000
+/* Performance Monitor Counter Register 0 */
+#define PFCNTR0            0xFFE08100
+/* Performance Monitor Counter Register 1 */
+#define PFCNTR1            0xFFE08104
+
+/****************************************************
+ * Core MMR Register Bits
+ ****************************************************/
+
+/**************************************************
+ * EVT registers (ILAT, IMASK, and IPEND).
+ **************************************************/
+
+/* Bit Positions */
+#define EVT_EMU_P        0x00000000     /* Emulator interrupt bit position */
+#define EVT_RST_P        0x00000001     /* Reset interrupt bit position */
+#define EVT_NMI_P        0x00000002     /* Non Maskable interrupt bit position */
+#define EVT_EVX_P        0x00000003     /* Exception bit position */
+#define EVT_IRPTEN_P     0x00000004     /* Global interrupt enable bit position */
+#define EVT_IVHW_P       0x00000005     /* Hardware Error interrupt bit position */
+#define EVT_IVTMR_P      0x00000006     /* Timer interrupt bit position */
+#define EVT_IVG7_P       0x00000007     /* IVG7 interrupt bit position */
+#define EVT_IVG8_P       0x00000008     /* IVG8 interrupt bit position */
+#define EVT_IVG9_P       0x00000009     /* IVG9 interrupt bit position */
+#define EVT_IVG10_P      0x0000000a     /* IVG10 interrupt bit position */
+#define EVT_IVG11_P      0x0000000b     /* IVG11 interrupt bit position */
+#define EVT_IVG12_P      0x0000000c     /* IVG12 interrupt bit position */
+#define EVT_IVG13_P      0x0000000d     /* IVG13 interrupt bit position */
+#define EVT_IVG14_P      0x0000000e     /* IVG14 interrupt bit position */
+#define EVT_IVG15_P      0x0000000f     /* IVG15 interrupt bit position */
+
+/* Masks */
+#define EVT_EMU       MK_BMSK_(EVT_EMU_P   )    /* Emulator interrupt mask */
+#define EVT_RST       MK_BMSK_(EVT_RST_P   )    /* Reset interrupt mask */
+#define EVT_NMI       MK_BMSK_(EVT_NMI_P   )    /* Non Maskable interrupt mask */
+#define EVT_EVX       MK_BMSK_(EVT_EVX_P   )    /* Exception mask */
+#define EVT_IRPTEN    MK_BMSK_(EVT_IRPTEN_P)    /* Global interrupt enable mask */
+#define EVT_IVHW      MK_BMSK_(EVT_IVHW_P  )    /* Hardware Error interrupt mask */
+#define EVT_IVTMR     MK_BMSK_(EVT_IVTMR_P )    /* Timer interrupt mask */
+#define EVT_IVG7      MK_BMSK_(EVT_IVG7_P  )    /* IVG7 interrupt mask */
+#define EVT_IVG8      MK_BMSK_(EVT_IVG8_P  )    /* IVG8 interrupt mask */
+#define EVT_IVG9      MK_BMSK_(EVT_IVG9_P  )    /* IVG9 interrupt mask */
+#define EVT_IVG10     MK_BMSK_(EVT_IVG10_P )    /* IVG10 interrupt mask */
+#define EVT_IVG11     MK_BMSK_(EVT_IVG11_P )    /* IVG11 interrupt mask */
+#define EVT_IVG12     MK_BMSK_(EVT_IVG12_P )    /* IVG12 interrupt mask */
+#define EVT_IVG13     MK_BMSK_(EVT_IVG13_P )    /* IVG13 interrupt mask */
+#define EVT_IVG14     MK_BMSK_(EVT_IVG14_P )    /* IVG14 interrupt mask */
+#define EVT_IVG15     MK_BMSK_(EVT_IVG15_P )    /* IVG15 interrupt mask */
+
+/**************************************************
+ *  DMEM_CONTROL Register
+ **************************************************/
+/* Bit Positions */
+#define ENDM_P                  0x00    /* (doesn't really exist) Enable
+                                         *Data Memory L1
+                                         */
+#define DMCTL_ENDM_P            ENDM_P  /* "" (older define) */
+
+#define ENDCPLB_P               0x01    /* Enable DCPLBS */
+#define DMCTL_ENDCPLB_P         ENDCPLB_P       /* "" (older define) */
+#define DMC0_P                  0x02    /* L1 Data Memory Configure bit 0 */
+#define DMCTL_DMC0_P            DMC0_P  /* "" (older define) */
+#define DMC1_P                  0x03    /* L1 Data Memory Configure bit 1 */
+#define DMCTL_DMC1_P            DMC1_P  /* "" (older define) */
+#define DCBS_P                  0x04    /* L1 Data Cache Bank Select */
+#define PORT_PREF0_P            0x12    /* DAG0 Port Preference */
+#define PORT_PREF1_P            0x13    /* DAG1 Port Preference */
+
+/* Masks */
+#define ENDM               0x00000001   /* (doesn't really exist) Enable
+                                         * Data Memory L1
+                                         */
+#define ENDCPLB            0x00000002   /* Enable DCPLB */
+#define ASRAM_BSRAM        0x00000000
+#define ACACHE_BSRAM       0x00000008
+#define ACACHE_BCACHE      0x0000000C
+#define DCBS               0x00000010   /*  L1 Data Cache Bank Select */
+#define PORT_PREF0         0x00001000   /* DAG0 Port Preference */
+#define PORT_PREF1         0x00002000   /* DAG1 Port Preference */
+
+/* IMEM_CONTROL Register */
+/* Bit Positions */
+#define ENIM_P                  0x00    /* Enable L1 Code Memory  */
+#define IMCTL_ENIM_P            0x00    /* "" (older define) */
+#define ENICPLB_P               0x01    /* Enable ICPLB */
+#define IMCTL_ENICPLB_P         0x01    /* "" (older define) */
+#define IMC_P                   0x02    /* Enable  */
+#define IMCTL_IMC_P             0x02    /* Configure L1 code memory as
+                                         * cache (0=SRAM)
+                                         */
+#define ILOC0_P                 0x03    /* Lock Way 0 */
+#define ILOC1_P                 0x04    /* Lock Way 1 */
+#define ILOC2_P                 0x05    /* Lock Way 2 */
+#define ILOC3_P                 0x06    /* Lock Way 3 */
+#define LRUPRIORST_P            0x0D    /* Least Recently Used Replacement
+                                         * Priority
+                                         */
+/* Masks */
+#define ENIM               0x00000001   /* Enable L1 Code Memory */
+#define ENICPLB            0x00000002   /* Enable ICPLB */
+#define IMC                0x00000004   /* Configure L1 code memory as
+                                         * cache (0=SRAM)
+                                         */
+#define ILOC0              0x00000008   /* Lock Way 0 */
+#define ILOC1              0x00000010   /* Lock Way 1 */
+#define ILOC2              0x00000020   /* Lock Way 2 */
+#define ILOC3              0x00000040   /* Lock Way 3 */
+#define LRUPRIORST         0x00002000   /* Least Recently Used Replacement
+                                         * Priority
+                                         */
+
+/* TCNTL Masks */
+#define TMPWR              0x00000001   /* Timer Low Power Control,
+                                         * 0=low power mode, 1=active state
+                                         */
+#define TMREN              0x00000002   /* Timer enable, 0=disable, 1=enable */
+#define TAUTORLD           0x00000004   /* Timer auto reload */
+#define TINT               0x00000008   /* Timer generated interrupt 0=no
+                                         * interrupt has been generated,
+                                         * 1=interrupt has been generated
+                                         * (sticky)
+                                         */
+
+/* DCPLB_DATA and ICPLB_DATA Registers */
+/* Bit Positions */
+#define CPLB_VALID_P       0x00000000   /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK_P        0x00000001   /* 0=entry may be replaced, 1=entry
+                                         * locked
+                                         */
+#define CPLB_USER_RD_P     0x00000002   /* 0=no read access, 1=read access
+                                         * allowed (user mode)
+                                         */
+/* Masks */
+#define CPLB_VALID         0x00000001   /* 0=invalid entry, 1=valid entry */
+#define CPLB_LOCK          0x00000002   /* 0=entry may be replaced, 1=entry
+                                         * locked
+                                         */
+#define CPLB_USER_RD       0x00000004   /* 0=no read access, 1=read access
+                                         * allowed (user mode)
+                                         */
+#define PAGE_SIZE_1KB      0x00000000   /* 1 KB page size */
+#define PAGE_SIZE_4KB      0x00010000   /* 4 KB page size */
+#define PAGE_SIZE_1MB      0x00020000   /* 1 MB page size */
+#define PAGE_SIZE_4MB      0x00030000   /* 4 MB page size */
+#define CPLB_L1SRAM        0x00000020   /* 0=SRAM mapped in L1, 0=SRAM not
+                                         * mapped to L1
+                                         */
+#define CPLB_PORTPRIO      0x00000200   /* 0=low priority port, 1= high
+                                         * priority port
+                                         */
+#define CPLB_L1_CHBL       0x00001000   /* 0=non-cacheable in L1, 1=cacheable
+                                         * in L1
+                                         */
+/* ICPLB_DATA only */
+#define CPLB_LRUPRIO       0x00000100   /* 0=can be replaced by any line,
+                                         * 1=priority for non-replacement
+                                         */
+/* DCPLB_DATA only */
+#define CPLB_USER_WR       0x00000008   /* 0=no write access, 0=write
+                                         * access allowed (user mode)
+                                         */
+#define CPLB_SUPV_WR       0x00000010   /* 0=no write access, 0=write
+                                         * access allowed (supervisor mode)
+                                         */
+#define CPLB_DIRTY         0x00000080   /* 1=dirty, 0=clean */
+#define CPLB_L1_AOW        0x00008000   /* 0=do not allocate cache lines on
+                                         * write-through writes,
+                                         * 1= allocate cache lines on
+                                         * write-through writes.
+                                         */
+#define CPLB_WT            0x00004000   /* 0=write-back, 1=write-through */
+
+/* TBUFCTL Masks */
+#define TBUFPWR            0x0001
+#define TBUFEN             0x0002
+#define TBUFOVF            0x0004
+#define TBUFCMPLP_SINGLE   0x0008
+#define TBUFCMPLP_DOUBLE   0x0010
+#define TBUFCMPLP          (TBUFCMPLP_SINGLE | TBUFCMPLP_DOUBLE)
+
+/* TBUFSTAT Masks */
+#define TBUFCNT            0x001F
+
+/* ITEST_COMMAND and DTEST_COMMAND Registers */
+/* Masks */
+#define TEST_READ          0x00000000   /* Read Access */
+#define TEST_WRITE         0x00000002   /* Write Access */
+#define TEST_TAG           0x00000000   /* Access TAG */
+#define TEST_DATA          0x00000004   /* Access DATA */
+#define TEST_DW0           0x00000000   /* Select Double Word 0 */
+#define TEST_DW1           0x00000008   /* Select Double Word 1 */
+#define TEST_DW2           0x00000010   /* Select Double Word 2 */
+#define TEST_DW3           0x00000018   /* Select Double Word 3 */
+#define TEST_MB0           0x00000000   /* Select Mini-Bank 0 */
+#define TEST_MB1           0x00010000   /* Select Mini-Bank 1 */
+#define TEST_MB2           0x00020000   /* Select Mini-Bank 2 */
+#define TEST_MB3           0x00030000   /* Select Mini-Bank 3 */
+#define TEST_SET(x)        ((x << 5) & 0x03E0)  /* Set Index 0->31 */
+#define TEST_WAY0          0x00000000   /* Access Way0 */
+#define TEST_WAY1          0x04000000   /* Access Way1 */
+/* ITEST_COMMAND only */
+#define TEST_WAY2          0x08000000   /* Access Way2 */
+#define TEST_WAY3          0x0C000000   /* Access Way3 */
+/* DTEST_COMMAND only */
+#define TEST_BNKSELA       0x00000000   /* Access SuperBank A */
+#define TEST_BNKSELB       0x00800000   /* Access SuperBank B */
+
+#endif                          /* _DEF_LPBLACKFIN_H */
diff --git a/include/asm-blackfin/macros.h b/include/asm-blackfin/macros.h
new file mode 100644
index 000000000000..c0c04a2f2dd5
--- /dev/null
+++ b/include/asm-blackfin/macros.h
@@ -0,0 +1,95 @@
+/************************************************************************
+ *
+ * macros.h
+ *
+ * (c) Copyright 2001-2003 Analog Devices, Inc.  All rights reserved.
+ *
+ ************************************************************************/
+
+/* Defines various assembly macros. */
+
+#ifndef _MACROS_H
+#define _MACROS_H
+
+#define LO(con32) ((con32) & 0xFFFF)
+#define lo(con32) ((con32) & 0xFFFF)
+#define HI(con32) (((con32) >> 16) & 0xFFFF)
+#define hi(con32) (((con32) >> 16) & 0xFFFF)
+
+/*
+ * Set the corresponding bits in a System Register (SR);
+ * All bits set in "mask" will be set in the system register
+ * specified by "sys_reg" bitset_SR(sys_reg, mask), where
+ * sys_reg is the system register and mask are the bits to be set.
+ */
+#define bitset_SR(sys_reg, mask)\
+                [--SP] = (R7:6);\
+                r7 = sys_reg;\
+                r6.l = (mask) & 0xffff;\
+                r6.h = (mask) >> 16;\
+                r7 = r7 | r6;\
+                sys_reg = r7;\
+                csync;\
+                (R7:6) = [SP++]
+
+/*
+ * Clear the corresponding bits in a System Register (SR);
+ * All bits set in "mask" will be cleared in the SR
+ * specified by "sys_reg" bitclr_SR(sys_reg, mask), where
+ * sys_reg is the SR and mask are the bits to be cleared.
+ */
+#define bitclr_SR(sys_reg, mask)\
+                [--SP] = (R7:6);\
+                r7 = sys_reg;\
+                r7 =~ r7;\
+                r6.l = (mask) & 0xffff;\
+                r6.h = (mask) >> 16;\
+                r7 = r7 | r6;\
+                r7 =~ r7;\
+                sys_reg = r7;\
+                csync;\
+                (R7:6) = [SP++]
+
+/*
+ * Set the corresponding bits in a Memory Mapped Register (MMR);
+ * All bits set in "mask" will be set in the MMR specified by "mmr_reg"
+ * bitset_MMR(mmr_reg, mask), where mmr_reg is the MMR and mask are
+ * the bits to be set.
+ */
+#define bitset_MMR(mmr_reg, mask)\
+                [--SP] = (R7:6);\
+                [--SP] = P5;\
+                p5.l = mmr_reg & 0xffff;\
+                p5.h = mmr_reg >> 16;\
+                r7 = [p5];\
+                r6.l = (mask) & 0xffff;\
+                r6.h = (mask) >> 16;\
+                r7 = r7 | r6;\
+                [p5] = r7;\
+                csync;\
+                p5 = [SP++];\
+                (R7:6) = [SP++]
+
+/*
+ * Clear the corresponding bits in a Memory Mapped Register (MMR);
+ * All bits set in "mask" will be cleared in the MMR specified by "mmr_reg"
+ * bitclr_MMRreg(mmr_reg, mask), where sys_reg is the MMR and mask are
+ * the bits to be cleared.
+ */
+#define bitclr_MMR(mmr_reg, mask)\
+                [--SP] = (R7:6);\
+                [--SP] = P5;\
+                p5.l = mmr_reg & 0xffff;\
+                p5.h = mmr_reg >> 16;\
+                r7 = [p5];\
+                r7 =~ r7;\
+                r6.l = (mask) & 0xffff;\
+                r6.h = (mask) >> 16;\
+                r7 = r7 | r6;\
+                r7 =~ r7;\
+                [p5] = r7;\
+                csync;\
+                p5 = [SP++];\
+                (R7:6) = [SP++]
+
+#endif                          /* _MACROS_H */
diff --git a/include/asm-blackfin/mem_map.h b/include/asm-blackfin/mem_map.h
new file mode 100644
index 000000000000..42d1f37f6d9c
--- /dev/null
+++ b/include/asm-blackfin/mem_map.h
@@ -0,0 +1,12 @@
+/*
+ * mem_map.h
+ * Common header file for blackfin family of processors.
+ *
+ */
+
+#ifndef _MEM_MAP_H_
+#define _MEM_MAP_H_
+
+#include <asm/mach/mem_map.h>
+
+#endif                          /* _MEM_MAP_H_ */
diff --git a/include/asm-blackfin/mman.h b/include/asm-blackfin/mman.h
new file mode 100644
index 000000000000..4d504f908c0c
--- /dev/null
+++ b/include/asm-blackfin/mman.h
@@ -0,0 +1,45 @@
+#ifndef __BFIN_MMAN_H__
+#define __BFIN_MMAN_H__
+
+#define PROT_READ       0x1     /* page can be read */
+#define PROT_WRITE      0x2     /* page can be written */
+#define PROT_EXEC       0x4     /* page can be executed */
+#define PROT_SEM        0x8     /* page may be used for atomic ops */
+#define PROT_NONE       0x0     /* page can not be accessed */
+#define PROT_GROWSDOWN  0x01000000      /* mprotect flag: extend change to start of growsdown vma */
+#define PROT_GROWSUP    0x02000000      /* mprotect flag: extend change to end of growsup vma */
+
+#define MAP_SHARED      0x01    /* Share changes */
+#define MAP_PRIVATE     0x02    /* Changes are private */
+#define MAP_TYPE        0x0f    /* Mask for type of mapping */
+#define MAP_FIXED       0x10    /* Interpret addr exactly */
+#define MAP_ANONYMOUS   0x20    /* don't use a file */
+
+#define MAP_GROWSDOWN   0x0100  /* stack-like segment */
+#define MAP_DENYWRITE   0x0800  /* ETXTBSY */
+#define MAP_EXECUTABLE  0x1000  /* mark it as an executable */
+#define MAP_LOCKED      0x2000  /* pages are locked */
+#define MAP_NORESERVE   0x4000  /* don't check for reservations */
+#define MAP_POPULATE    0x8000  /* populate (prefault) pagetables */
+#define MAP_NONBLOCK    0x10000 /* do not block on IO */
+#define MAP_UNINITIALIZE 0x4000000  /* For anonymous mmap, memory could
+                                    be uninitialized. */
+
+#define MS_ASYNC        1       /* sync memory asynchronously */
+#define MS_INVALIDATE   2       /* invalidate the caches */
+#define MS_SYNC         4       /* synchronous memory sync */
+
+#define MCL_CURRENT     1       /* lock all current mappings */
+#define MCL_FUTURE      2       /* lock all future mappings */
+
+#define MADV_NORMAL     0x0     /* default page-in behavior */
+#define MADV_RANDOM     0x1     /* page-in minimum required */
+#define MADV_SEQUENTIAL 0x2     /* read-ahead aggressively */
+#define MADV_WILLNEED   0x3     /* pre-fault pages */
+#define MADV_DONTNEED   0x4     /* discard these pages */
+
+/* compatibility flags */
+#define MAP_ANON        MAP_ANONYMOUS
+#define MAP_FILE        0
+
+#endif                          /* __BFIN_MMAN_H__ */
diff --git a/include/asm-blackfin/mmu.h b/include/asm-blackfin/mmu.h
new file mode 100644
index 000000000000..11d52f1167d0
--- /dev/null
+++ b/include/asm-blackfin/mmu.h
@@ -0,0 +1,30 @@
+#ifndef __MMU_H
+#define __MMU_H
+
+/* Copyright (C) 2002, David McCullough <davidm@snapgear.com> */
+
+struct sram_list_struct {
+        struct sram_list_struct *next;
+        void *addr;
+        size_t length;
+};
+
+typedef struct {
+        struct vm_list_struct *vmlist;
+        unsigned long end_brk;
+        unsigned long stack_start;
+
+        /* Points to the location in SDRAM where the L1 stack is normally
+           saved, or NULL if the stack is always in SDRAM.  */
+        void *l1_stack_save;
+
+        struct sram_list_struct *sram_list;
+
+#ifdef CONFIG_BINFMT_ELF_FDPIC
+        unsigned long   exec_fdpic_loadmap;
+        unsigned long   interp_fdpic_loadmap;
+#endif
+
+} mm_context_t;
+
+#endif
diff --git a/include/asm-blackfin/mmu_context.h b/include/asm-blackfin/mmu_context.h
new file mode 100644
index 000000000000..c5c71a6aaf19
--- /dev/null
+++ b/include/asm-blackfin/mmu_context.h
@@ -0,0 +1,129 @@
+/*
+ * File:         include/asm-blackfin/mmu_context.h
+ * Based on:
+ * Author:
+ *
+ * Created:
+ * Description:
+ *
+ * Modified:
+ *               Copyright 2004-2006 Analog Devices Inc.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, see the file COPYING, or write
+ * to the Free Software Foundation, Inc.,
+ * 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+ */
+
+#ifndef __BLACKFIN_MMU_CONTEXT_H__
+#define __BLACKFIN_MMU_CONTEXT_H__
+
+#include <asm/setup.h>
+#include <asm/page.h>
+#include <asm/pgalloc.h>
+
+extern void *current_l1_stack_save;
+extern int nr_l1stack_tasks;
+extern void *l1_stack_base;
+extern unsigned long l1_stack_len;
+
+extern int l1sram_free(const void*);
+extern void *l1sram_alloc_max(void*);
+
+static inline void enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
+{
+}
+
+/* Called when creating a new context during fork() or execve().  */
+static inline int
+init_new_context(struct task_struct *tsk, struct mm_struct *mm)
+{
+        return 0;
+}
+
+static inline void free_l1stack(void)
+{
+        nr_l1stack_tasks--;
+        if (nr_l1stack_tasks == 0)
+                l1sram_free(l1_stack_base);
+}
+static inline void destroy_context(struct mm_struct *mm)
+{
+        struct sram_list_struct *tmp;
+
+        if (current_l1_stack_save == mm->context.l1_stack_save)
+                current_l1_stack_save = 0;
+        if (mm->context.l1_stack_save)
+                free_l1stack();
+
+        while ((tmp = mm->context.sram_list)) {
+                mm->context.sram_list = tmp->next;
+                sram_free(tmp->addr);
+                kfree(tmp);
+        }
+}
+
+static inline unsigned long
+alloc_l1stack(unsigned long length, unsigned long *stack_base)
+{
+        if (nr_l1stack_tasks == 0) {
+                l1_stack_base = l1sram_alloc_max(&l1_stack_len);
+                if (!l1_stack_base)
+                        return 0;
+        }
+
+        if (l1_stack_len < length) {
+                if (nr_l1stack_tasks == 0)
+                        l1sram_free(l1_stack_base);
+                return 0;
+        }
+        *stack_base = (unsigned long)l1_stack_base;
+        nr_l1stack_tasks++;
+        return l1_stack_len;
+}
+
+static inline int
+activate_l1stack(struct mm_struct *mm, unsigned long sp_base)
+{
+        if (current_l1_stack_save)
+                memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
+        mm->context.l1_stack_save = current_l1_stack_save = (void*)sp_base;
+        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
+        return 1;
+}
+
+#define deactivate_mm(tsk,mm)   do { } while (0)
+
+static inline void activate_mm(struct mm_struct *prev_mm,
+                               struct mm_struct *next_mm)
+{
+        if (!next_mm->context.l1_stack_save)
+                return;
+        if (next_mm->context.l1_stack_save == current_l1_stack_save)
+                return;
+        if (current_l1_stack_save) {
+                memcpy(current_l1_stack_save, l1_stack_base, l1_stack_len);
+        }
+        current_l1_stack_save = next_mm->context.l1_stack_save;
+        memcpy(l1_stack_base, current_l1_stack_save, l1_stack_len);
+}
+
+static inline void switch_mm(struct mm_struct *prev, struct mm_struct *next,
+                             struct task_struct *tsk)
+{
+        activate_mm(prev, next);
+}
+
+#endif
diff --git a/include/asm-blackfin/module.h b/include/asm-blackfin/module.h
new file mode 100644
index 000000000000..3c7ce1644280
--- /dev/null
+++ b/include/asm-blackfin/module.h
@@ -0,0 +1,19 @@
+#ifndef _ASM_BFIN_MODULE_H
+#define _ASM_BFIN_MODULE_H
+
+#define MODULE_SYMBOL_PREFIX "_"
+
+#define Elf_Shdr        Elf32_Shdr
+#define Elf_Sym         Elf32_Sym
+#define Elf_Ehdr        Elf32_Ehdr
+#define FLG_CODE_IN_L1  0x10
+#define FLG_DATA_IN_L1  0x20
+
+struct mod_arch_specific {
+        Elf_Shdr        *text_l1;
+        Elf_Shdr        *data_a_l1;
+        Elf_Shdr        *bss_a_l1;
+        Elf_Shdr        *data_b_l1;
+        Elf_Shdr        *bss_b_l1;
+};
+#endif                          /* _ASM_BFIN_MODULE_H */
diff --git a/include/asm-blackfin/msgbuf.h b/include/asm-blackfin/msgbuf.h
new file mode 100644
index 000000000000..6fcbe8cd801d
--- /dev/null
+++ b/include/asm-blackfin/msgbuf.h
@@ -0,0 +1,31 @@
+#ifndef _BFIN_MSGBUF_H
+#define _BFIN_MSGBUF_H
+
+/*
+ * The msqid64_ds structure for bfin architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct msqid64_ds {
+        struct ipc64_perm msg_perm;
+        __kernel_time_t msg_stime;      /* last msgsnd time */
+        unsigned long __unused1;
+        __kernel_time_t msg_rtime;      /* last msgrcv time */
+        unsigned long __unused2;
+        __kernel_time_t msg_ctime;      /* last change time */
+        unsigned long __unused3;
+        unsigned long msg_cbytes;       /* current number of bytes on queue */
+        unsigned long msg_qnum; /* number of messages in queue */
+        unsigned long msg_qbytes;       /* max number of bytes on queue */
+        __kernel_pid_t msg_lspid;       /* pid of last msgsnd */
+        __kernel_pid_t msg_lrpid;       /* last receive pid */
+        unsigned long __unused4;
+        unsigned long __unused5;
+};
+
+#endif                          /* _BFIN_MSGBUF_H */
diff --git a/include/asm-blackfin/mutex.h b/include/asm-blackfin/mutex.h
new file mode 100644
index 000000000000..458c1f7fbc18
--- /dev/null
+++ b/include/asm-blackfin/mutex.h
@@ -0,0 +1,9 @@
+/*
+ * Pull in the generic implementation for the mutex fastpath.
+ *
+ * TODO: implement optimized primitives instead, or leave the generic
+ * implementation in place, or pick the atomic_xchg() based generic
+ * implementation. (see asm-generic/mutex-xchg.h for details)
+ */
+
+#include <asm-generic/mutex-dec.h>
diff --git a/include/asm-blackfin/namei.h b/include/asm-blackfin/namei.h
new file mode 100644
index 000000000000..8b89a2d65cb4
--- /dev/null
+++ b/include/asm-blackfin/namei.h
@@ -0,0 +1,19 @@
+/*
+ * linux/include/asm/namei.h
+ *
+ * Included from linux/fs/namei.c
+ *
+ * Changes made by Lineo Inc.    May 2001
+ */
+
+#ifndef __BFIN_NAMEI_H
+#define __BFIN_NAMEI_H
+
+/* This dummy routine maybe changed to something useful
+ * for /usr/gnemul/ emulation stuff.
+ * Look at asm-sparc/namei.h for details.
+ */
+
+#define __emul_prefix() NULL
+
+#endif
diff --git a/include/asm-blackfin/page.h b/include/asm-blackfin/page.h
new file mode 100644
index 000000000000..ffad947f1b2a
--- /dev/null
+++ b/include/asm-blackfin/page.h
@@ -0,0 +1,89 @@
+#ifndef _BLACKFIN_PAGE_H
+#define _BLACKFIN_PAGE_H
+
+/* PAGE_SHIFT determines the page size */
+
+#define PAGE_SHIFT      12
+#define PAGE_SIZE       (1UL << PAGE_SHIFT)
+#define PAGE_MASK       (~(PAGE_SIZE-1))
+
+#ifdef __KERNEL__
+
+#include <asm/setup.h>
+
+#ifndef __ASSEMBLY__
+
+#define get_user_page(vaddr)            __get_free_page(GFP_KERNEL)
+#define free_user_page(page, addr)      free_page(addr)
+
+#define clear_page(page)        memset((page), 0, PAGE_SIZE)
+#define copy_page(to,from)      memcpy((to), (from), PAGE_SIZE)
+
+#define clear_user_page(page, vaddr,pg) clear_page(page)
+#define copy_user_page(to, from, vaddr,pg)      copy_page(to, from)
+
+/*
+ * These are used to make use of C type-checking..
+ */
+typedef struct {
+        unsigned long pte;
+} pte_t;
+typedef struct {
+        unsigned long pmd[16];
+} pmd_t;
+typedef struct {
+        unsigned long pgd;
+} pgd_t;
+typedef struct {
+        unsigned long pgprot;
+} pgprot_t;
+
+#define pte_val(x)      ((x).pte)
+#define pmd_val(x)      ((&x)->pmd[0])
+#define pgd_val(x)      ((x).pgd)
+#define pgprot_val(x)   ((x).pgprot)
+
+#define __pte(x)        ((pte_t) { (x) } )
+#define __pmd(x)        ((pmd_t) { (x) } )
+#define __pgd(x)        ((pgd_t) { (x) } )
+#define __pgprot(x)     ((pgprot_t) { (x) } )
+
+/* to align the pointer to the (next) page boundary */
+#define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
+
+extern unsigned long memory_start;
+extern unsigned long memory_end;
+
+#endif                          /* !__ASSEMBLY__ */
+
+#include <asm/page_offset.h>
+#include <asm/io.h>
+
+#define PAGE_OFFSET             (PAGE_OFFSET_RAW)
+
+#ifndef __ASSEMBLY__
+
+#define __pa(vaddr)             virt_to_phys((void *)(vaddr))
+#define __va(paddr)             phys_to_virt((unsigned long)(paddr))
+
+#define MAP_NR(addr)            (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
+
+#define virt_to_pfn(kaddr)      (__pa(kaddr) >> PAGE_SHIFT)
+#define pfn_to_virt(pfn)        __va((pfn) << PAGE_SHIFT)
+#define virt_to_page(addr)      (mem_map + (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT))
+#define page_to_virt(page)      ((((page) - mem_map) << PAGE_SHIFT) + PAGE_OFFSET)
+#define VALID_PAGE(page)        ((page - mem_map) < max_mapnr)
+
+#define pfn_to_page(pfn)        virt_to_page(pfn_to_virt(pfn))
+#define page_to_pfn(page)       virt_to_pfn(page_to_virt(page))
+#define pfn_valid(pfn)          ((pfn) < max_mapnr)
+
+#define virt_addr_valid(kaddr)  (((void *)(kaddr) >= (void *)PAGE_OFFSET) && \
+                                ((void *)(kaddr) < (void *)memory_end))
+
+#include <asm-generic/page.h>
+
+#endif                          /* __ASSEMBLY__ */
+#endif                          /* __KERNEL__ */
+
+#endif                          /* _BLACKFIN_PAGE_H */
diff --git a/include/asm-blackfin/page_offset.h b/include/asm-blackfin/page_offset.h
new file mode 100644
index 000000000000..3b671d5fd70d
--- /dev/null
+++ b/include/asm-blackfin/page_offset.h
@@ -0,0 +1,6 @@
+
+/* This handles the memory map.. */
+
+#ifdef CONFIG_BFIN
+#define PAGE_OFFSET_RAW         0x00000000
+#endif
diff --git a/include/asm-blackfin/param.h b/include/asm-blackfin/param.h
new file mode 100644
index 000000000000..41564a6347f8
--- /dev/null
+++ b/include/asm-blackfin/param.h
@@ -0,0 +1,22 @@
+#ifndef _BLACKFIN_PARAM_H
+#define _BLACKFIN_PARAM_H
+
+#ifdef __KERNEL__
+#define HZ              CONFIG_HZ
+#define USER_HZ         100
+#define CLOCKS_PER_SEC  (USER_HZ)
+#endif
+
+#ifndef HZ
+#define HZ 100
+#endif
+
+#define EXEC_PAGESIZE   4096
+
+#ifndef NOGROUP
+#define NOGROUP         (-1)
+#endif
+
+#define MAXHOSTNAMELEN  64      /* max length of hostname */
+
+#endif                          /* _BLACKFIN_PARAM_H */
diff --git a/include/asm-blackfin/pci.h b/include/asm-blackfin/pci.h
new file mode 100644
index 000000000000..61277358c865
--- /dev/null
+++ b/include/asm-blackfin/pci.h
@@ -0,0 +1,148 @@
+/* Changed from asm-m68k version, Lineo Inc.    May 2001        */
+
+#ifndef _ASM_BFIN_PCI_H
+#define _ASM_BFIN_PCI_H
+
+#include <asm/scatterlist.h>
+
+/*
+ *
+ * Written by Wout Klaren.
+ */
+
+/* Added by Chang Junxiao */
+#define PCIBIOS_MIN_IO 0x00001000
+#define PCIBIOS_MIN_MEM 0x10000000
+
+#define PCI_DMA_BUS_IS_PHYS       (1)
+struct pci_ops;
+
+/*
+ * Structure with hardware dependent information and functions of the
+ * PCI bus.
+ */
+struct pci_bus_info {
+
+        /*
+         * Resources of the PCI bus.
+         */
+        struct resource mem_space;
+        struct resource io_space;
+
+        /*
+         * System dependent functions.
+         */
+        struct pci_ops *bfin_pci_ops;
+        void (*fixup) (int pci_modify);
+        void (*conf_device) (unsigned char bus, unsigned char device_fn);
+};
+
+#define pcibios_assign_all_busses()     0
+static inline void pcibios_set_master(struct pci_dev *dev)
+{
+
+        /* No special bus mastering setup handling */
+}
+static inline void pcibios_penalize_isa_irq(int irq)
+{
+
+        /* We don't do dynamic PCI IRQ allocation */
+}
+static inline dma_addr_t pci_map_single(struct pci_dev *hwdev, void *ptr,
+                                        size_t size, int direction)
+{
+        if (direction == PCI_DMA_NONE)
+                BUG();
+
+         /* return virt_to_bus(ptr); */
+        return (dma_addr_t) ptr;
+}
+
+/* Unmap a single streaming mode DMA translation.  The dma_addr and size
+ * must match what was provided for in a previous pci_map_single call.  All
+ * other usages are undefined.
+ *
+ * After this call, reads by the cpu to the buffer are guarenteed to see
+ * whatever the device wrote there.
+ */
+static inline void pci_unmap_single(struct pci_dev *hwdev, dma_addr_t dma_addr,
+                                    size_t size, int direction)
+{
+        if (direction == PCI_DMA_NONE)
+                BUG();
+
+        /* Nothing to do */
+}
+
+/* Map a set of buffers described by scatterlist in streaming
+ * mode for DMA.  This is the scather-gather version of the
+ * above pci_map_single interface.  Here the scatter gather list
+ * elements are each tagged with the appropriate dma address
+ * and length.  They are obtained via sg_dma_{address,length}(SG).
+ *
+ * NOTE: An implementation may be able to use a smaller number of
+ *       DMA address/length pairs than there are SG table elements.
+ *       (for example via virtual mapping capabilities)
+ *       The routine returns the number of addr/length pairs actually
+ *       used, at most nents.
+ *
+ * Device ownership issues as mentioned above for pci_map_single are
+ * the same here.
+ */
+static inline int pci_map_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+                             int nents, int direction)
+{
+        if (direction == PCI_DMA_NONE)
+                BUG();
+        return nents;
+}
+
+/* Unmap a set of streaming mode DMA translations.
+ * Again, cpu read rules concerning calls here are the same as for
+ * pci_unmap_single() above.
+ */
+static inline void pci_unmap_sg(struct pci_dev *hwdev, struct scatterlist *sg,
+                                int nents, int direction)
+{
+        if (direction == PCI_DMA_NONE)
+                BUG();
+
+        /* Nothing to do */
+}
+
+/* Make physical memory consistent for a single
+ * streaming mode DMA translation after a transfer.
+ *
+ * If you perform a pci_map_single() but wish to interrogate the
+ * buffer using the cpu, yet do not wish to teardown the PCI dma
+ * mapping, you must call this function before doing so.  At the
+ * next point you give the PCI dma address back to the card, the
+ * device again owns the buffer.
+ */
+static inline void pci_dma_sync_single(struct pci_dev *hwdev,
+                                       dma_addr_t dma_handle, size_t size,
+                                       int direction)
+{
+        if (direction == PCI_DMA_NONE)
+                BUG();
+
+        /* Nothing to do */
+}
+
+/* Make physical memory consistent for a set of streaming
+ * mode DMA translations after a transfer.
+ *
+ * The same as pci_dma_sync_single but for a scatter-gather list,
+ * same rules and usage.
+ */
+static inline void pci_dma_sync_sg(struct pci_dev *hwdev,
+                                   struct scatterlist *sg, int nelems,
+                                   int direction)
+{
+        if (direction == PCI_DMA_NONE)
+                BUG();
+
+        /* Nothing to do */
+}
+
+#endif                          /* _ASM_BFIN_PCI_H */
diff --git a/include/asm-blackfin/percpu.h b/include/asm-blackfin/percpu.h
new file mode 100644
index 000000000000..78dd61f6b39f
--- /dev/null
+++ b/include/asm-blackfin/percpu.h
@@ -0,0 +1,6 @@
+#ifndef __ARCH_BLACKFIN_PERCPU__
+#define __ARCH_BLACKFIN_PERCPU__
+
+#include <asm-generic/percpu.h>
+
+#endif                          /* __ARCH_BLACKFIN_PERCPU__ */
diff --git a/include/asm-blackfin/pgalloc.h b/include/asm-blackfin/pgalloc.h
new file mode 100644
index 000000000000..c686e0542fd0
--- /dev/null
+++ b/include/asm-blackfin/pgalloc.h
@@ -0,0 +1,8 @@
+#ifndef _BLACKFIN_PGALLOC_H
+#define _BLACKFIN_PGALLOC_H
+
+#include <asm/setup.h>
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif                          /* _BLACKFIN_PGALLOC_H */
diff --git a/include/asm-blackfin/pgtable.h b/include/asm-blackfin/pgtable.h
new file mode 100644
index 000000000000..5a8f9e431c40
--- /dev/null
+++ b/include/asm-blackfin/pgtable.h
@@ -0,0 +1,96 @@
+#ifndef _BLACKFIN_PGTABLE_H
+#define _BLACKFIN_PGTABLE_H
+
+#include <asm-generic/4level-fixup.h>
+
+#include <asm/page.h>
+#include <asm/cplb.h>
+
+typedef pte_t *pte_addr_t;
+/*
+* Trivial page table functions.
+*/
+#define pgd_present(pgd)        (1)
+#define pgd_none(pgd)           (0)
+#define pgd_bad(pgd)            (0)
+#define pgd_clear(pgdp)
+#define kern_addr_valid(addr)   (1)
+
+#define pmd_offset(a, b)        ((void *)0)
+#define pmd_none(x)             (!pmd_val(x))
+#define pmd_present(x)          (pmd_val(x))
+#define pmd_clear(xp)           do { set_pmd(xp, __pmd(0)); } while (0)
+#define pmd_bad(x)              (pmd_val(x) & ~PAGE_MASK)
+
+#define kern_addr_valid(addr) (1)
+
+#define PAGE_NONE               __pgprot(0)     /* these mean nothing to NO_MM */
+#define PAGE_SHARED             __pgprot(0)     /* these mean nothing to NO_MM */
+#define PAGE_COPY               __pgprot(0)     /* these mean nothing to NO_MM */
+#define PAGE_READONLY           __pgprot(0)     /* these mean nothing to NO_MM */
+#define PAGE_KERNEL             __pgprot(0)     /* these mean nothing to NO_MM */
+
+extern void paging_init(void);
+
+#define __swp_type(x)           (0)
+#define __swp_offset(x)         (0)
+#define __swp_entry(typ,off)    ((swp_entry_t) { ((typ) | ((off) << 7)) })
+#define __pte_to_swp_entry(pte) ((swp_entry_t) { pte_val(pte) })
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val })
+
+static inline int pte_file(pte_t pte)
+{
+        return 0;
+}
+
+#define set_pte(pteptr, pteval) (*(pteptr) = pteval)
+#define set_pte_at(mm, addr, ptep, pteval) set_pte(ptep, pteval)
+
+/*
+ * Page assess control based on Blackfin CPLB management
+ */
+#define _PAGE_RD        (CPLB_USER_RD)
+#define _PAGE_WR        (CPLB_USER_WR)
+#define _PAGE_USER      (CPLB_USER_RD | CPLB_USER_WR)
+#define _PAGE_ACCESSED  CPLB_ALL_ACCESS
+#define _PAGE_DIRTY     (CPLB_DIRTY)
+
+#define PTE_BIT_FUNC(fn, op) \
+        static inline pte_t pte_##fn(pte_t _pte) { _pte.pte op; return _pte; }
+
+PTE_BIT_FUNC(rdprotect, &= ~_PAGE_RD);
+PTE_BIT_FUNC(mkread, |= _PAGE_RD);
+PTE_BIT_FUNC(wrprotect, &= ~_PAGE_WR);
+PTE_BIT_FUNC(mkwrite, |= _PAGE_WR);
+PTE_BIT_FUNC(exprotect, &= ~_PAGE_USER);
+PTE_BIT_FUNC(mkexec, |= _PAGE_USER);
+PTE_BIT_FUNC(mkclean, &= ~_PAGE_DIRTY);
+PTE_BIT_FUNC(mkdirty, |= _PAGE_DIRTY);
+PTE_BIT_FUNC(mkold, &= ~_PAGE_ACCESSED);
+PTE_BIT_FUNC(mkyoung, |= _PAGE_ACCESSED);
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+#define ZERO_PAGE(vaddr)        (virt_to_page(0))
+
+extern unsigned int kobjsize(const void *objp);
+
+#define swapper_pg_dir ((pgd_t *) 0)
+/*
+ * No page table caches to initialise.
+ */
+#define pgtable_cache_init()    do { } while (0)
+#define io_remap_pfn_range      remap_pfn_range
+
+/*
+ * All 32bit addresses are effectively valid for vmalloc...
+ * Sort of meaningless for non-VM targets.
+ */
+#define VMALLOC_START   0
+#define VMALLOC_END     0xffffffff
+
+#include <asm-generic/pgtable.h>
+
+#endif                          /* _BLACKFIN_PGTABLE_H */
diff --git a/include/asm-blackfin/poll.h b/include/asm-blackfin/poll.h
new file mode 100644
index 000000000000..94cc2636e0e2
--- /dev/null
+++ b/include/asm-blackfin/poll.h
@@ -0,0 +1,24 @@
+#ifndef __BFIN_POLL_H
+#define __BFIN_POLL_H
+
+#define POLLIN            1
+#define POLLPRI           2
+#define POLLOUT           4
+#define POLLERR           8
+#define POLLHUP          16
+#define POLLNVAL         32
+#define POLLRDNORM       64
+#define POLLWRNORM      POLLOUT
+#define POLLRDBAND      128
+#define POLLWRBAND      256
+#define POLLMSG         0x0400
+#define POLLREMOVE      0x1000
+#define POLLRDHUP       0x2000
+
+struct pollfd {
+        int fd;
+        short events;
+        short revents;
+};
+
+#endif                          /* __BFIN_POLL_H */
diff --git a/include/asm-blackfin/posix_types.h b/include/asm-blackfin/posix_types.h
new file mode 100644
index 000000000000..c3fa50fa50b8
--- /dev/null
+++ b/include/asm-blackfin/posix_types.h
@@ -0,0 +1,65 @@
+#ifndef __ARCH_BFIN_POSIX_TYPES_H
+#define __ARCH_BFIN_POSIX_TYPES_H
+
+/*
+ * This file is generally used by user-level software, so you need to
+ * be a little careful about namespace pollution etc.  Also, we cannot
+ * assume GCC is being used.
+ */
+
+typedef unsigned long __kernel_ino_t;
+typedef unsigned short __kernel_mode_t;
+typedef unsigned short __kernel_nlink_t;
+typedef long __kernel_off_t;
+typedef int __kernel_pid_t;
+typedef unsigned int __kernel_ipc_pid_t;
+typedef unsigned int __kernel_uid_t;
+typedef unsigned int __kernel_gid_t;
+typedef unsigned long __kernel_size_t;
+typedef long __kernel_ssize_t;
+typedef int __kernel_ptrdiff_t;
+typedef long __kernel_time_t;
+typedef long __kernel_suseconds_t;
+typedef long __kernel_clock_t;
+typedef int __kernel_timer_t;
+typedef int __kernel_clockid_t;
+typedef int __kernel_daddr_t;
+typedef char *__kernel_caddr_t;
+typedef unsigned short __kernel_uid16_t;
+typedef unsigned short __kernel_gid16_t;
+typedef unsigned int __kernel_uid32_t;
+typedef unsigned int __kernel_gid32_t;
+
+typedef unsigned short __kernel_old_uid_t;
+typedef unsigned short __kernel_old_gid_t;
+typedef unsigned short __kernel_old_dev_t;
+
+#ifdef __GNUC__
+typedef long long __kernel_loff_t;
+#endif
+
+typedef struct {
+#if defined(__KERNEL__) || defined(__USE_ALL)
+        int val[2];
+#else                           /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+        int __val[2];
+#endif                          /* !defined(__KERNEL__) && !defined(__USE_ALL) */
+} __kernel_fsid_t;
+
+#if defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2)
+
+#undef  __FD_SET
+#define __FD_SET(d, set)        ((set)->fds_bits[__FDELT(d)] |= __FDMASK(d))
+
+#undef  __FD_CLR
+#define __FD_CLR(d, set)        ((set)->fds_bits[__FDELT(d)] &= ~__FDMASK(d))
+
+#undef  __FD_ISSET
+#define __FD_ISSET(d, set)      ((set)->fds_bits[__FDELT(d)] & __FDMASK(d))
+
+#undef  __FD_ZERO
+#define __FD_ZERO(fdsetp) (memset (fdsetp, 0, sizeof(*(fd_set *)fdsetp)))
+
+#endif                          /* defined(__KERNEL__) || !defined(__GLIBC__) || (__GLIBC__ < 2) */
+
+#endif
diff --git a/include/asm-blackfin/processor.h b/include/asm-blackfin/processor.h
new file mode 100644
index 000000000000..997465c93e82
--- /dev/null
+++ b/include/asm-blackfin/processor.h
@@ -0,0 +1,130 @@
+#ifndef __ASM_BFIN_PROCESSOR_H
+#define __ASM_BFIN_PROCESSOR_H
+
+/*
+ * Default implementation of macro that returns current
+ * instruction pointer ("program counter").
+ */
+#define current_text_addr() ({ __label__ _l; _l: &&_l;})
+
+#include <asm/blackfin.h>
+#include <asm/segment.h>
+#include <linux/compiler.h>
+
+static inline unsigned long rdusp(void)
+{
+        unsigned long usp;
+
+        __asm__ __volatile__("%0 = usp;\n\t":"=da"(usp));
+        return usp;
+}
+
+static inline void wrusp(unsigned long usp)
+{
+        __asm__ __volatile__("usp = %0;\n\t"::"da"(usp));
+}
+
+/*
+ * User space process size: 1st byte beyond user address space.
+ */
+extern unsigned long memory_end;
+#define TASK_SIZE       (memory_end)
+
+#define TASK_UNMAPPED_BASE      0
+
+struct thread_struct {
+        unsigned long ksp;      /* kernel stack pointer */
+        unsigned long usp;      /* user stack pointer */
+        unsigned short seqstat; /* saved status register */
+        unsigned long esp0;     /* points to SR of stack frame pt_regs */
+        unsigned long pc;       /* instruction pointer */
+        void *        debuggerinfo;
+};
+
+#define INIT_THREAD  {                                          \
+        sizeof(init_stack) + (unsigned long) init_stack, 0,     \
+        PS_S, 0, 0                                              \
+}
+
+/*
+ * Do necessary setup to start up a newly executed thread.
+ *
+ * pass the data segment into user programs if it exists,
+ * it can't hurt anything as far as I can tell
+ */
+#define start_thread(_regs, _pc, _usp)                                  \
+do {                                                                    \
+        set_fs(USER_DS);                                                \
+        (_regs)->pc = (_pc);                                            \
+        if (current->mm)                                                \
+                (_regs)->p5 = current->mm->start_data;                  \
+        current->thread_info->l1_task_info.stack_start                  \
+                = (void *)current->mm->context.stack_start;             \
+        current->thread_info->l1_task_info.lowest_sp = (void *)(_usp);          \
+        memcpy(L1_SCRATCH_TASK_INFO, &current->thread_info->l1_task_info,       \
+                sizeof(*L1_SCRATCH_TASK_INFO));                         \
+        wrusp(_usp);                                                    \
+} while(0)
+
+/* Forward declaration, a strange C thing */
+struct task_struct;
+
+/* Free all resources held by a thread. */
+static inline void release_thread(struct task_struct *dead_task)
+{
+}
+
+#define prepare_to_copy(tsk)    do { } while (0)
+
+extern int kernel_thread(int (*fn) (void *), void *arg, unsigned long flags);
+
+/*
+ * Free current thread data structures etc..
+ */
+static inline void exit_thread(void)
+{
+}
+
+/*
+ * Return saved PC of a blocked thread.
+ */
+#define thread_saved_pc(tsk)    (tsk->thread.pc)
+
+unsigned long get_wchan(struct task_struct *p);
+
+#define KSTK_EIP(tsk)                                                   \
+    ({                                                                  \
+        unsigned long eip = 0;                                          \
+        if ((tsk)->thread.esp0 > PAGE_SIZE &&                           \
+            MAP_NR((tsk)->thread.esp0) < max_mapnr)                     \
+              eip = ((struct pt_regs *) (tsk)->thread.esp0)->pc;        \
+        eip; })
+#define KSTK_ESP(tsk)   ((tsk) == current ? rdusp() : (tsk)->thread.usp)
+
+#define cpu_relax()     barrier()
+
+/* Get the Silicon Revision of the chip */
+static inline uint32_t bfin_revid(void)
+{
+        /* stored in the upper 4 bits */
+        return bfin_read_CHIPID() >> 28;
+}
+
+static inline uint32_t bfin_compiled_revid(void)
+{
+#if defined(CONFIG_BF_REV_0_0)
+        return 0;
+#elif defined(CONFIG_BF_REV_0_1)
+        return 1;
+#elif defined(CONFIG_BF_REV_0_2)
+        return 2;
+#elif defined(CONFIG_BF_REV_0_3)
+        return 3;
+#elif defined(CONFIG_BF_REV_0_4)
+        return 4;
+#elif defined(CONFIG_BF_REV_0_5)
+        return 5;
+#endif
+}
+
+#endif
diff --git a/include/asm-blackfin/ptrace.h b/include/asm-blackfin/ptrace.h
new file mode 100644
index 000000000000..b8346cd3a6f6
--- /dev/null
+++ b/include/asm-blackfin/ptrace.h
@@ -0,0 +1,166 @@
+#ifndef _BFIN_PTRACE_H
+#define _BFIN_PTRACE_H
+
+/*
+ * GCC defines register number like this:
+ * -----------------------------
+ *       0 - 7 are data registers R0-R7
+ *       8 - 15 are address registers P0-P7
+ *      16 - 31 dsp registers I/B/L0 -- I/B/L3 & M0--M3
+ *      32 - 33 A registers A0 & A1
+ *      34 -    status register
+ * -----------------------------
+ *
+ * We follows above, except:
+ *      32-33 --- Low 32-bit of A0&1
+ *      34-35 --- High 8-bit of A0&1
+ */
+
+#ifndef __ASSEMBLY__
+
+/* this struct defines the way the registers are stored on the
+   stack during a system call. */
+
+struct pt_regs {
+        long orig_pc;
+        long ipend;
+        long seqstat;
+        long rete;
+        long retn;
+        long retx;
+        long pc;                /* PC == RETI */
+        long rets;
+        long reserved;          /* Used as scratch during system calls */
+        long astat;
+        long lb1;
+        long lb0;
+        long lt1;
+        long lt0;
+        long lc1;
+        long lc0;
+        long a1w;
+        long a1x;
+        long a0w;
+        long a0x;
+        long b3;
+        long b2;
+        long b1;
+        long b0;
+        long l3;
+        long l2;
+        long l1;
+        long l0;
+        long m3;
+        long m2;
+        long m1;
+        long m0;
+        long i3;
+        long i2;
+        long i1;
+        long i0;
+        long usp;
+        long fp;
+        long p5;
+        long p4;
+        long p3;
+        long p2;
+        long p1;
+        long p0;
+        long r7;
+        long r6;
+        long r5;
+        long r4;
+        long r3;
+        long r2;
+        long r1;
+        long r0;
+        long orig_r0;
+        long orig_p0;
+        long syscfg;
+};
+
+/* Arbitrarily choose the same ptrace numbers as used by the Sparc code. */
+#define PTRACE_GETREGS            12
+#define PTRACE_SETREGS            13    /* ptrace signal  */
+
+#ifdef CONFIG_BINFMT_ELF_FDPIC
+#define PTRACE_GETFDPIC           31
+#define PTRACE_GETFDPIC_EXEC      0
+#define PTRACE_GETFDPIC_INTERP    1
+#endif
+
+#define PS_S  (0x0002)
+
+/* user_mode returns true if only one bit is set in IPEND, other than the
+   master interrupt enable.  */
+#define user_mode(regs) (!(((regs)->ipend & ~0x10) & (((regs)->ipend & ~0x10) - 1)))
+#define instruction_pointer(regs) ((regs)->pc)
+#define profile_pc(regs) instruction_pointer(regs)
+extern void show_regs(struct pt_regs *);
+
+#endif                          /* __ASSEMBLY__ */
+
+/*
+ * Offsets used by 'ptrace' system call interface.
+ */
+
+#define PT_R0 204
+#define PT_R1 200
+#define PT_R2 196
+#define PT_R3 192
+#define PT_R4 188
+#define PT_R5 184
+#define PT_R6 180
+#define PT_R7 176
+#define PT_P0 172
+#define PT_P1 168
+#define PT_P2 164
+#define PT_P3 160
+#define PT_P4 156
+#define PT_P5 152
+#define PT_FP 148
+#define PT_USP 144
+#define PT_I0 140
+#define PT_I1 136
+#define PT_I2 132
+#define PT_I3 128
+#define PT_M0 124
+#define PT_M1 120
+#define PT_M2 116
+#define PT_M3 112
+#define PT_L0 108
+#define PT_L1 104
+#define PT_L2 100
+#define PT_L3 96
+#define PT_B0 92
+#define PT_B1 88
+#define PT_B2 84
+#define PT_B3 80
+#define PT_A0X 76
+#define PT_A0W 72
+#define PT_A1X 68
+#define PT_A1W 64
+#define PT_LC0 60
+#define PT_LC1 56
+#define PT_LT0 52
+#define PT_LT1 48
+#define PT_LB0 44
+#define PT_LB1 40
+#define PT_ASTAT 36
+#define PT_RESERVED 32
+#define PT_RETS 28
+#define PT_PC 24
+#define PT_RETX 20
+#define PT_RETN 16
+#define PT_RETE 12
+#define PT_SEQSTAT 8
+#define PT_IPEND 4
+
+#define PT_SYSCFG 216
+#define PT_TEXT_ADDR 220
+#define PT_TEXT_END_ADDR 224
+#define PT_DATA_ADDR 228
+#define PT_FDPIC_EXEC 232
+#define PT_FDPIC_INTERP 236
+
+#endif                          /* _BFIN_PTRACE_H */
diff --git a/include/asm-blackfin/resource.h b/include/asm-blackfin/resource.h
new file mode 100644
index 000000000000..091355ab3495
--- /dev/null
+++ b/include/asm-blackfin/resource.h
@@ -0,0 +1,6 @@
+#ifndef _BFIN_RESOURCE_H
+#define _BFIN_RESOURCE_H
+
+#include <asm-generic/resource.h>
+
+#endif                          /* _BFIN_RESOURCE_H */
diff --git a/include/asm-blackfin/scatterlist.h b/include/asm-blackfin/scatterlist.h
new file mode 100644
index 000000000000..60e07b92044c
--- /dev/null
+++ b/include/asm-blackfin/scatterlist.h
@@ -0,0 +1,26 @@
+#ifndef _BLACKFIN_SCATTERLIST_H
+#define _BLACKFIN_SCATTERLIST_H
+
+#include <linux/mm.h>
+
+struct scatterlist {
+        struct page *page;
+        unsigned int offset;
+        dma_addr_t dma_address;
+        unsigned int length;
+};
+
+/*
+ * These macros should be used after a pci_map_sg call has been done
+ * to get bus addresses of each of the SG entries and their lengths.
+ * You should only work with the number of sg entries pci_map_sg
+ * returns, or alternatively stop on the first sg_dma_len(sg) which
+ * is 0.
+ */
+#define sg_address(sg) (page_address((sg)->page) + (sg)->offset)
+#define sg_dma_address(sg)      ((sg)->dma_address)
+#define sg_dma_len(sg)          ((sg)->length)
+
+#define ISA_DMA_THRESHOLD       (0xffffffff)
+
+#endif                          /* !(_BLACKFIN_SCATTERLIST_H) */
diff --git a/include/asm-blackfin/sections.h b/include/asm-blackfin/sections.h
new file mode 100644
index 000000000000..1443c3353a8c
--- /dev/null
+++ b/include/asm-blackfin/sections.h
@@ -0,0 +1,7 @@
+#ifndef _BLACKFIN_SECTIONS_H
+#define _BLACKFIN_SECTIONS_H
+
+/* nothing to see, move along */
+#include <asm-generic/sections.h>
+
+#endif
diff --git a/include/asm-blackfin/segment.h b/include/asm-blackfin/segment.h
new file mode 100644
index 000000000000..02cfd09b5a99
--- /dev/null
+++ b/include/asm-blackfin/segment.h
@@ -0,0 +1,7 @@
+#ifndef _BFIN_SEGMENT_H
+#define _BFIN_SEGMENT_H
+
+#define KERNEL_DS   (0x5)
+#define USER_DS     (0x1)
+
+#endif                          /* _BFIN_SEGMENT_H */
diff --git a/include/asm-blackfin/semaphore-helper.h b/include/asm-blackfin/semaphore-helper.h
new file mode 100644
index 000000000000..9082b0dc3eb5
--- /dev/null
+++ b/include/asm-blackfin/semaphore-helper.h
@@ -0,0 +1,82 @@
+/* Based on M68K version,       Lineo Inc.      May 2001 */
+
+#ifndef _BFIN_SEMAPHORE_HELPER_H
+#define _BFIN_SEMAPHORE_HELPER_H
+
+/*
+ * SMP- and interrupt-safe semaphores helper functions.
+ *
+ * (C) Copyright 1996 Linus Torvalds
+ *
+ */
+
+#include <asm/errno.h>
+
+/*
+ * These two _must_ execute atomically wrt each other.
+ */
+static inline void wake_one_more(struct semaphore *sem)
+{
+        atomic_inc(&sem->waking);
+}
+
+static inline int waking_non_zero(struct semaphore *sem)
+{
+        int ret;
+        unsigned long flags = 0;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        ret = 0;
+        if (atomic_read(&sem->waking) > 0) {
+                atomic_dec(&sem->waking);
+                ret = 1;
+        }
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+        return ret;
+}
+
+/*
+ * waking_non_zero_interruptible:
+ *      1       got the lock
+ *      0       go to sleep
+ *      -EINTR  interrupted
+ */
+static inline int waking_non_zero_interruptible(struct semaphore *sem,
+                                                struct task_struct *tsk)
+{
+        int ret = 0;
+        unsigned long flags = 0;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        if (atomic_read(&sem->waking) > 0) {
+                atomic_dec(&sem->waking);
+                ret = 1;
+        } else if (signal_pending(tsk)) {
+                atomic_inc(&sem->count);
+                ret = -EINTR;
+        }
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+        return ret;
+}
+
+/*
+ * waking_non_zero_trylock:
+ *      1       failed to lock
+ *      0       got the lock
+ */
+static inline int waking_non_zero_trylock(struct semaphore *sem)
+{
+        int ret = 1;
+        unsigned long flags = 0;
+
+        spin_lock_irqsave(&semaphore_wake_lock, flags);
+        if (atomic_read(&sem->waking) > 0) {
+                atomic_dec(&sem->waking);
+                ret = 0;
+        } else
+                atomic_inc(&sem->count);
+        spin_unlock_irqrestore(&semaphore_wake_lock, flags);
+        return ret;
+}
+
+#endif                          /* _BFIN_SEMAPHORE_HELPER_H */
diff --git a/include/asm-blackfin/semaphore.h b/include/asm-blackfin/semaphore.h
new file mode 100644
index 000000000000..94c04d7ab23e
--- /dev/null
+++ b/include/asm-blackfin/semaphore.h
@@ -0,0 +1,106 @@
+#ifndef _BFIN_SEMAPHORE_H
+#define _BFIN_SEMAPHORE_H
+
+#ifndef __ASSEMBLY__
+
+#include <linux/linkage.h>
+#include <linux/wait.h>
+#include <linux/spinlock.h>
+#include <linux/rwsem.h>
+#include <asm/atomic.h>
+
+/*
+ * Interrupt-safe semaphores..
+ *
+ * (C) Copyright 1996 Linus Torvalds
+ *
+ * BFIN version by akbar hussain Lineo Inc  April 2001
+ *
+ */
+
+struct semaphore {
+        atomic_t count;
+        int sleepers;
+        wait_queue_head_t wait;
+};
+
+#define __SEMAPHORE_INITIALIZER(name, n)                                \
+{                                                                       \
+        .count          = ATOMIC_INIT(n),                               \
+        .sleepers       = 0,                                            \
+        .wait           = __WAIT_QUEUE_HEAD_INITIALIZER((name).wait)    \
+}
+
+#define __DECLARE_SEMAPHORE_GENERIC(name,count) \
+        struct semaphore name = __SEMAPHORE_INITIALIZER(name,count)
+
+#define DECLARE_MUTEX(name) __DECLARE_SEMAPHORE_GENERIC(name,1)
+#define DECLARE_MUTEX_LOCKED(name) __DECLARE_SEMAPHORE_GENERIC(name,0)
+
+static inline void sema_init(struct semaphore *sem, int val)
+{
+        *sem = (struct semaphore)__SEMAPHORE_INITIALIZER(*sem, val);
+}
+
+static inline void init_MUTEX(struct semaphore *sem)
+{
+        sema_init(sem, 1);
+}
+
+static inline void init_MUTEX_LOCKED(struct semaphore *sem)
+{
+        sema_init(sem, 0);
+}
+
+asmlinkage void __down(struct semaphore *sem);
+asmlinkage int __down_interruptible(struct semaphore *sem);
+asmlinkage int __down_trylock(struct semaphore *sem);
+asmlinkage void __up(struct semaphore *sem);
+
+extern spinlock_t semaphore_wake_lock;
+
+/*
+ * This is ugly, but we want the default case to fall through.
+ * "down_failed" is a special asm handler that calls the C
+ * routine that actually waits.
+ */
+static inline void down(struct semaphore *sem)
+{
+        might_sleep();
+        if (atomic_dec_return(&sem->count) < 0)
+                __down(sem);
+}
+
+static inline int down_interruptible(struct semaphore *sem)
+{
+        int ret = 0;
+
+        might_sleep();
+        if (atomic_dec_return(&sem->count) < 0)
+                ret = __down_interruptible(sem);
+        return (ret);
+}
+
+static inline int down_trylock(struct semaphore *sem)
+{
+        int ret = 0;
+
+        if (atomic_dec_return(&sem->count) < 0)
+                ret = __down_trylock(sem);
+        return ret;
+}
+
+/*
+ * Note! This is subtle. We jump to wake people up only if
+ * the semaphore was negative (== somebody was waiting on it).
+ * The default case (no contention) will result in NO
+ * jumps for both down() and up().
+ */
+static inline void up(struct semaphore *sem)
+{
+        if (atomic_inc_return(&sem->count) <= 0)
+                __up(sem);
+}
+
+#endif                          /* __ASSEMBLY__ */
+#endif                          /* _BFIN_SEMAPHORE_H */
diff --git a/include/asm-blackfin/sembuf.h b/include/asm-blackfin/sembuf.h
new file mode 100644
index 000000000000..18deb5c7fa5d
--- /dev/null
+++ b/include/asm-blackfin/sembuf.h
@@ -0,0 +1,25 @@
+#ifndef _BFIN_SEMBUF_H
+#define _BFIN_SEMBUF_H
+
+/*
+ * The semid64_ds structure for bfin architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct semid64_ds {
+        struct ipc64_perm sem_perm;     /* permissions .. see ipc.h */
+        __kernel_time_t sem_otime;      /* last semop time */
+        unsigned long __unused1;
+        __kernel_time_t sem_ctime;      /* last change time */
+        unsigned long __unused2;
+        unsigned long sem_nsems;        /* no. of semaphores in array */
+        unsigned long __unused3;
+        unsigned long __unused4;
+};
+
+#endif                          /* _BFIN_SEMBUF_H */
diff --git a/include/asm-blackfin/setup.h b/include/asm-blackfin/setup.h
new file mode 100644
index 000000000000..01c8c6cbe6fc
--- /dev/null
+++ b/include/asm-blackfin/setup.h
@@ -0,0 +1,17 @@
+/*
+** asm/setup.h -- Definition of the Linux/bfin setup information
+**
+** This file is subject to the terms and conditions of the GNU General Public
+** License.  See the file COPYING in the main directory of this archive
+** for more details.
+**
+** Copyright Lineo, Inc 2001          Tony Kou
+**
+*/
+
+#ifndef _BFIN_SETUP_H
+#define _BFIN_SETUP_H
+
+#define COMMAND_LINE_SIZE       512
+
+#endif                          /* _BFIN_SETUP_H */
diff --git a/include/asm-blackfin/shmbuf.h b/include/asm-blackfin/shmbuf.h
new file mode 100644
index 000000000000..612436303e89
--- /dev/null
+++ b/include/asm-blackfin/shmbuf.h
@@ -0,0 +1,42 @@
+#ifndef _BFIN_SHMBUF_H
+#define _BFIN_SHMBUF_H
+
+/*
+ * The shmid64_ds structure for bfin architecture.
+ * Note extra padding because this structure is passed back and forth
+ * between kernel and user space.
+ *
+ * Pad space is left for:
+ * - 64-bit time_t to solve y2038 problem
+ * - 2 miscellaneous 32-bit values
+ */
+
+struct shmid64_ds {
+        struct ipc64_perm shm_perm;     /* operation perms */
+        size_t shm_segsz;       /* size of segment (bytes) */
+        __kernel_time_t shm_atime;      /* last attach time */
+        unsigned long __unused1;
+        __kernel_time_t shm_dtime;      /* last detach time */
+        unsigned long __unused2;
+        __kernel_time_t shm_ctime;      /* last change time */
+        unsigned long __unused3;
+        __kernel_pid_t shm_cpid;        /* pid of creator */
+        __kernel_pid_t shm_lpid;        /* pid of last operator */
+        unsigned long shm_nattch;       /* no. of current attaches */
+        unsigned long __unused4;
+        unsigned long __unused5;
+};
+
+struct shminfo64 {
+        unsigned long shmmax;
+        unsigned long shmmin;
+        unsigned long shmmni;
+        unsigned long shmseg;
+        unsigned long shmall;
+        unsigned long __unused1;
+        unsigned long __unused2;
+        unsigned long __unused3;
+        unsigned long __unused4;
+};
+
+#endif                          /* _BFIN_SHMBUF_H */
diff --git a/include/asm-blackfin/shmparam.h b/include/asm-blackfin/shmparam.h
new file mode 100644
index 000000000000..3c03906b7664
--- /dev/null
+++ b/include/asm-blackfin/shmparam.h
@@ -0,0 +1,6 @@
+#ifndef _BFIN_SHMPARAM_H
+#define _BFIN_SHMPARAM_H
+
+#define SHMLBA PAGE_SIZE        /* attach addr a multiple of this */
+
+#endif                          /* _BFIN_SHMPARAM_H */
diff --git a/include/asm-blackfin/sigcontext.h b/include/asm-blackfin/sigcontext.h
new file mode 100644
index 000000000000..ce00b03c2775
--- /dev/null
+++ b/include/asm-blackfin/sigcontext.h
@@ -0,0 +1,55 @@
+#ifndef _ASM_BLACKFIN_SIGCONTEXT_H
+#define _ASM_BLACKFIN_SIGCONTEXT_H
+
+/* Add new entries at the end of the structure only.  */
+struct sigcontext {
+        unsigned long sc_r0;
+        unsigned long sc_r1;
+        unsigned long sc_r2;
+        unsigned long sc_r3;
+        unsigned long sc_r4;
+        unsigned long sc_r5;
+        unsigned long sc_r6;
+        unsigned long sc_r7;
+        unsigned long sc_p0;
+        unsigned long sc_p1;
+        unsigned long sc_p2;
+        unsigned long sc_p3;
+        unsigned long sc_p4;
+        unsigned long sc_p5;
+        unsigned long sc_usp;
+        unsigned long sc_a0w;
+        unsigned long sc_a1w;
+        unsigned long sc_a0x;
+        unsigned long sc_a1x;
+        unsigned long sc_astat;
+        unsigned long sc_rets;
+        unsigned long sc_pc;
+        unsigned long sc_retx;
+        unsigned long sc_fp;
+        unsigned long sc_i0;
+        unsigned long sc_i1;
+        unsigned long sc_i2;
+        unsigned long sc_i3;
+        unsigned long sc_m0;
+        unsigned long sc_m1;
+        unsigned long sc_m2;
+        unsigned long sc_m3;
+        unsigned long sc_l0;
+        unsigned long sc_l1;
+        unsigned long sc_l2;
+        unsigned long sc_l3;
+        unsigned long sc_b0;
+        unsigned long sc_b1;
+        unsigned long sc_b2;
+        unsigned long sc_b3;
+        unsigned long sc_lc0;
+        unsigned long sc_lc1;
+        unsigned long sc_lt0;
+        unsigned long sc_lt1;
+        unsigned long sc_lb0;
+        unsigned long sc_lb1;
+        unsigned long sc_seqstat;
+};
+
+#endif
diff --git a/include/asm-blackfin/siginfo.h b/include/asm-blackfin/siginfo.h
new file mode 100644
index 000000000000..eca4565cea37
--- /dev/null
+++ b/include/asm-blackfin/siginfo.h
@@ -0,0 +1,35 @@
+#ifndef _BFIN_SIGINFO_H
+#define _BFIN_SIGINFO_H
+
+#include <linux/types.h>
+#include <asm-generic/siginfo.h>
+
+#define UID16_SIGINFO_COMPAT_NEEDED
+
+#define si_uid16        _sifields._kill._uid
+
+#define ILL_ILLPARAOP   (__SI_FAULT|2)  /* illegal opcode combine ********** */
+#define ILL_ILLEXCPT    (__SI_FAULT|4)  /* unrecoverable exception ********** */
+#define ILL_CPLB_VI     (__SI_FAULT|9)  /* D/I CPLB protect violation ******** */
+#define ILL_CPLB_MISS   (__SI_FAULT|10) /* D/I CPLB miss ******** */
+#define ILL_CPLB_MULHIT (__SI_FAULT|11) /* D/I CPLB multiple hit ******** */
+
+/*
+ * SIGBUS si_codes
+ */
+#define BUS_OPFETCH     (__SI_FAULT|4)  /* error from instruction fetch ******** */
+
+/*
+ * SIGTRAP si_codes
+ */
+#define TRAP_STEP       (__SI_FAULT|1)  /* single-step breakpoint************* */
+#define TRAP_TRACEFLOW  (__SI_FAULT|2)  /* trace buffer overflow ************* */
+#define TRAP_WATCHPT    (__SI_FAULT|3)  /* watchpoint match      ************* */
+#define TRAP_ILLTRAP    (__SI_FAULT|4)  /* illegal trap          ************* */
+
+/*
+ * SIGSEGV si_codes
+ */
+#define SEGV_STACKFLOW  (__SI_FAULT|3)  /* stack overflow */
+
+#endif
diff --git a/include/asm-blackfin/signal.h b/include/asm-blackfin/signal.h
new file mode 100644
index 000000000000..0250429b736a
--- /dev/null
+++ b/include/asm-blackfin/signal.h
@@ -0,0 +1,160 @@
+#ifndef _BLACKFIN_SIGNAL_H
+#define _BLACKFIN_SIGNAL_H
+
+#include <linux/types.h>
+
+/* Avoid too many header ordering problems.  */
+struct siginfo;
+
+#ifdef __KERNEL__
+/* Most things should be clean enough to redefine this at will, if care
+   is taken to make libc match.  */
+
+#define _NSIG           64
+#define _NSIG_BPW       32
+#define _NSIG_WORDS     (_NSIG / _NSIG_BPW)
+
+typedef unsigned long old_sigset_t;     /* at least 32 bits */
+
+typedef struct {
+        unsigned long sig[_NSIG_WORDS];
+} sigset_t;
+
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+#define NSIG            32
+typedef unsigned long sigset_t;
+
+#endif                          /* __KERNEL__ */
+
+#define SIGHUP           1
+#define SIGINT           2
+#define SIGQUIT          3
+#define SIGILL           4
+#define SIGTRAP          5
+#define SIGABRT          6
+#define SIGIOT           6
+#define SIGBUS           7
+#define SIGFPE           8
+#define SIGKILL          9
+#define SIGUSR1         10
+#define SIGSEGV         11
+#define SIGUSR2         12
+#define SIGPIPE         13
+#define SIGALRM         14
+#define SIGTERM         15
+#define SIGSTKFLT       16
+#define SIGCHLD         17
+#define SIGCONT         18
+#define SIGSTOP         19
+#define SIGTSTP         20
+#define SIGTTIN         21
+#define SIGTTOU         22
+#define SIGURG          23
+#define SIGXCPU         24
+#define SIGXFSZ         25
+#define SIGVTALRM       26
+#define SIGPROF         27
+#define SIGWINCH        28
+#define SIGIO           29
+#define SIGPOLL         SIGIO
+/*
+#define SIGLOST         29
+*/
+#define SIGPWR          30
+#define SIGSYS          31
+#define SIGUNUSED       31
+
+/* These should not be considered constants from userland.  */
+#define SIGRTMIN        32
+#define SIGRTMAX        _NSIG
+
+/*
+ * SA_FLAGS values:
+ *
+ * SA_ONSTACK indicates that a registered stack_t will be used.
+ * SA_INTERRUPT is a no-op, but left due to historical reasons. Use the
+ * SA_RESTART flag to get restarting signals (which were the default long ago)
+ * SA_NOCLDSTOP flag to turn off SIGCHLD when children stop.
+ * SA_RESETHAND clears the handler when the signal is delivered.
+ * SA_NOCLDWAIT flag on SIGCHLD to inhibit zombies.
+ * SA_NODEFER prevents the current signal from being masked in the handler.
+ *
+ * SA_ONESHOT and SA_NOMASK are the historical Linux names for the Single
+ * Unix names RESETHAND and NODEFER respectively.
+ */
+#define SA_NOCLDSTOP    0x00000001
+#define SA_NOCLDWAIT    0x00000002      /* not supported yet */
+#define SA_SIGINFO      0x00000004
+#define SA_ONSTACK      0x08000000
+#define SA_RESTART      0x10000000
+#define SA_NODEFER      0x40000000
+#define SA_RESETHAND    0x80000000
+
+#define SA_NOMASK       SA_NODEFER
+#define SA_ONESHOT      SA_RESETHAND
+
+/*
+ * sigaltstack controls
+ */
+#define SS_ONSTACK      1
+#define SS_DISABLE      2
+
+#define MINSIGSTKSZ     2048
+#define SIGSTKSZ        8192
+
+#include <asm-generic/signal.h>
+
+#ifdef __KERNEL__
+struct old_sigaction {
+        __sighandler_t sa_handler;
+        old_sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer) (void);
+};
+
+struct sigaction {
+        __sighandler_t sa_handler;
+        unsigned long sa_flags;
+        void (*sa_restorer) (void);
+        sigset_t sa_mask;       /* mask last for extensibility */
+};
+
+struct k_sigaction {
+        struct sigaction sa;
+};
+#else
+/* Here we must cater to libcs that poke about in kernel headers.  */
+
+struct sigaction {
+        union {
+                __sighandler_t _sa_handler;
+                void (*_sa_sigaction) (int, struct siginfo *, void *);
+        } _u;
+        sigset_t sa_mask;
+        unsigned long sa_flags;
+        void (*sa_restorer) (void);
+};
+
+#define sa_handler      _u._sa_handler
+#define sa_sigaction    _u._sa_sigaction
+
+#endif                          /* __KERNEL__ */
+
+typedef struct sigaltstack {
+        void *ss_sp;
+        int ss_flags;
+        size_t ss_size;
+} stack_t;
+
+#ifdef __KERNEL__
+
+#include <asm/sigcontext.h>
+#undef __HAVE_ARCH_SIG_BITOPS
+
+#define ptrace_signal_deliver(regs, cookie) do { } while (0)
+
+#endif                          /* __KERNEL__ */
+
+#endif                          /* _BLACKFIN_SIGNAL_H */
diff --git a/include/asm-blackfin/socket.h b/include/asm-blackfin/socket.h
new file mode 100644
index 000000000000..5213c9652186
--- /dev/null
+++ b/include/asm-blackfin/socket.h
@@ -0,0 +1,53 @@
+#ifndef _ASM_SOCKET_H
+#define _ASM_SOCKET_H
+
+#include <asm/sockios.h>
+
+/* For setsockoptions(2) */
+#define SOL_SOCKET      1
+
+#define SO_DEBUG        1
+#define SO_REUSEADDR    2
+#define SO_TYPE         3
+#define SO_ERROR        4
+#define SO_DONTROUTE    5
+#define SO_BROADCAST    6
+#define SO_SNDBUF       7
+#define SO_RCVBUF       8
+#define SO_SNDBUFFORCE  32
+#define SO_RCVBUFFORCE  33
+#define SO_KEEPALIVE    9
+#define SO_OOBINLINE    10
+#define SO_NO_CHECK     11
+#define SO_PRIORITY     12
+#define SO_LINGER       13
+#define SO_BSDCOMPAT    14
+/* To add :#define SO_REUSEPORT 15 */
+#define SO_PASSCRED     16
+#define SO_PEERCRED     17
+#define SO_RCVLOWAT     18
+#define SO_SNDLOWAT     19
+#define SO_RCVTIMEO     20
+#define SO_SNDTIMEO     21
+
+/* Security levels - as per NRL IPv6 - don't actually do anything */
+#define SO_SECURITY_AUTHENTICATION              22
+#define SO_SECURITY_ENCRYPTION_TRANSPORT        23
+#define SO_SECURITY_ENCRYPTION_NETWORK          24
+
+#define SO_BINDTODEVICE 25
+
+/* Socket filtering */
+#define SO_ATTACH_FILTER        26
+#define SO_DETACH_FILTER        27
+
+#define SO_PEERNAME             28
+#define SO_TIMESTAMP            29
+#define SCM_TIMESTAMP           SO_TIMESTAMP
+
+#define SO_ACCEPTCONN           30
+#define SO_PEERSEC              31
+#define SO_PASSSEC              34
+#define SO_TIMESTAMPNS          35
+#define SCM_TIMESTAMPNS         SO_TIMESTAMPNS
+#endif                          /* _ASM_SOCKET_H */
diff --git a/include/asm-blackfin/sockios.h b/include/asm-blackfin/sockios.h
new file mode 100644
index 000000000000..426b89bfaa8b
--- /dev/null
+++ b/include/asm-blackfin/sockios.h
@@ -0,0 +1,13 @@
+#ifndef __ARCH_BFIN_SOCKIOS__
+#define __ARCH_BFIN_SOCKIOS__
+
+/* Socket-level I/O control calls. */
+#define FIOSETOWN       0x8901
+#define SIOCSPGRP       0x8902
+#define FIOGETOWN       0x8903
+#define SIOCGPGRP       0x8904
+#define SIOCATMARK      0x8905
+#define SIOCGSTAMP      0x8906  /* Get stamp (timeval) */
+#define SIOCGSTAMPNS    0x8907  /* Get stamp (timespec) */
+
+#endif                          /* __ARCH_BFIN_SOCKIOS__ */
diff --git a/include/asm-blackfin/spinlock.h b/include/asm-blackfin/spinlock.h
new file mode 100644
index 000000000000..64e908a50646
--- /dev/null
+++ b/include/asm-blackfin/spinlock.h
@@ -0,0 +1,6 @@
+#ifndef __BFIN_SPINLOCK_H
+#define __BFIN_SPINLOCK_H
+
+#error blackfin architecture does not support SMP spin lock yet
+
+#endif
diff --git a/include/asm-blackfin/stat.h b/include/asm-blackfin/stat.h
new file mode 100644
index 000000000000..d2b6f11ec231
--- /dev/null
+++ b/include/asm-blackfin/stat.h
@@ -0,0 +1,63 @@
+#ifndef _BFIN_STAT_H
+#define _BFIN_STAT_H
+
+struct stat {
+        unsigned short st_dev;
+        unsigned short __pad1;
+        unsigned long st_ino;
+        unsigned short st_mode;
+        unsigned short st_nlink;
+        unsigned short st_uid;
+        unsigned short st_gid;
+        unsigned short st_rdev;
+        unsigned short __pad2;
+        unsigned long st_size;
+        unsigned long st_blksize;
+        unsigned long st_blocks;
+        unsigned long st_atime;
+        unsigned long __unused1;
+        unsigned long st_mtime;
+        unsigned long __unused2;
+        unsigned long st_ctime;
+        unsigned long __unused3;
+        unsigned long __unused4;
+        unsigned long __unused5;
+};
+
+/* This matches struct stat64 in glibc2.1, hence the absolutely
+ * insane amounts of padding around dev_t's.
+ */
+struct stat64 {
+        unsigned long long st_dev;
+        unsigned char __pad1[4];
+
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long __st_ino;
+
+        unsigned int st_mode;
+        unsigned int st_nlink;
+
+        unsigned long st_uid;
+        unsigned long st_gid;
+
+        unsigned long long st_rdev;
+        unsigned char __pad2[4];
+
+        long long st_size;
+        unsigned long st_blksize;
+
+        long long st_blocks;    /* Number 512-byte blocks allocated. */
+
+        unsigned long st_atime;
+        unsigned long st_atime_nsec;
+
+        unsigned long st_mtime;
+        unsigned long st_mtime_nsec;
+
+        unsigned long st_ctime;
+        unsigned long st_ctime_nsec;
+
+        unsigned long long st_ino;
+};
+
+#endif                          /* _BFIN_STAT_H */
diff --git a/include/asm-blackfin/statfs.h b/include/asm-blackfin/statfs.h
new file mode 100644
index 000000000000..350672091ba3
--- /dev/null
+++ b/include/asm-blackfin/statfs.h
@@ -0,0 +1,6 @@
+#ifndef _BFIN_STATFS_H
+#define _BFIN_STATFS_H
+
+#include <asm-generic/statfs.h>
+
+#endif                          /* _BFIN_STATFS_H */
diff --git a/include/asm-blackfin/string.h b/include/asm-blackfin/string.h
new file mode 100644
index 000000000000..6f1eb7d6d3cb
--- /dev/null
+++ b/include/asm-blackfin/string.h
@@ -0,0 +1,104 @@
+#ifndef _BLACKFIN_STRING_H_
+#define _BLACKFIN_STRING_H_
+
+#ifdef __KERNEL__               /* only set these up for kernel code */
+
+#define __HAVE_ARCH_STRCPY
+extern inline char *strcpy(char *dest, const char *src)
+{
+        char *xdest = dest;
+        char temp = 0;
+
+        __asm__ __volatile__
+            ("1:\t%2 = B [%1++] (Z);\n\t"
+             "B [%0++] = %2;\n\t"
+             "CC = %2;\n\t"
+        "if cc jump 1b (bp);\n"
+        : "+&a" (dest), "+&a" (src), "=&d" (temp)
+             ::"memory", "CC");
+        return xdest;
+}
+
+#define __HAVE_ARCH_STRNCPY
+extern inline char *strncpy(char *dest, const char *src, size_t n)
+{
+        char *xdest = dest;
+        char temp = 0;
+
+        if (n == 0)
+                return xdest;
+
+        __asm__ __volatile__
+            ("1:\t%3 = B [%1++] (Z);\n\t"
+             "B [%0++] = %3;\n\t"
+             "CC = %3;\n\t"
+             "if ! cc jump 2f;\n\t"
+             "%2 += -1;\n\t"
+             "CC = %2 == 0;\n\t"
+             "if ! cc jump 1b (bp);\n"
+        "2:\n"
+        : "+&a" (dest), "+&a" (src), "+&da" (n), "=&d" (temp)
+             ::"memory", "CC");
+        return xdest;
+}
+
+#define __HAVE_ARCH_STRCMP
+extern inline int strcmp(const char *cs, const char *ct)
+{
+        char __res1, __res2;
+
+        __asm__
+       ("1:\t%2 = B[%0++] (Z);\n\t" /* get *cs */
+                "%3 = B[%1++] (Z);\n\t" /* get *ct */
+                "CC = %2 == %3;\n\t"    /* compare a byte */
+                "if ! cc jump 2f;\n\t"  /* not equal, break out */
+                "CC = %2;\n\t"  /* at end of cs? */
+                "if cc jump 1b (bp);\n\t"       /* no, keep going */
+                "jump.s 3f;\n"  /* strings are equal */
+                "2:\t%2 = %2 - %3;\n"   /* *cs - *ct */
+        "3:\n"
+        : "+&a" (cs), "+&a" (ct), "=&d" (__res1), "=&d" (__res2)
+      : :       "CC");
+
+        return __res1;
+}
+
+#define __HAVE_ARCH_STRNCMP
+extern inline int strncmp(const char *cs, const char *ct, size_t count)
+{
+        char __res1, __res2;
+
+        if (!count)
+                return 0;
+        __asm__
+       ("1:\t%3 = B[%0++] (Z);\n\t"        /* get *cs */
+                "%4 = B[%1++] (Z);\n\t" /* get *ct */
+                "CC = %3 == %4;\n\t"    /* compare a byte */
+                "if ! cc jump 3f;\n\t"  /* not equal, break out */
+                "CC = %3;\n\t"  /* at end of cs? */
+                "if ! cc jump 4f;\n\t"  /* yes, all done */
+                "%2 += -1;\n\t" /* no, adjust count */
+        "CC = %2 == 0;\n\t"
+        "if ! cc jump 1b;\n"                 /* more to do, keep going */
+                "2:\t%3 = 0;\n\t"       /* strings are equal */
+        "jump.s    4f;\n"
+        "3:\t%3 = %3 - %4;\n"          /* *cs - *ct */
+        "4:"
+        : "+&a" (cs), "+&a" (ct), "+&da" (count), "=&d" (__res1), "=&d" (__res2)
+      : :       "CC");
+        return __res1;
+}
+
+#define __HAVE_ARCH_MEMSET
+extern void *memset(void *s, int c, size_t count);
+#define __HAVE_ARCH_MEMCPY
+extern void *memcpy(void *d, const void *s, size_t count);
+#define __HAVE_ARCH_MEMCMP
+extern int memcmp(const void *, const void *, __kernel_size_t);
+#define __HAVE_ARCH_MEMCHR
+extern void *memchr(const void *s, int c, size_t n);
+#define __HAVE_ARCH_MEMMOVE
+extern void *memmove(void *dest, const void *src, size_t count);
+
+#endif /*__KERNEL__*/
+#endif                          /* _BLACKFIN_STRING_H_ */
diff --git a/include/asm-blackfin/system.h b/include/asm-blackfin/system.h
new file mode 100644
index 000000000000..b5bf6e7cb5e8
--- /dev/null
+++ b/include/asm-blackfin/system.h
@@ -0,0 +1,249 @@
+/*
+ * File:        include/asm/system.h
+ * Based on:
+ * Author:      Tony Kou (tonyko@lineo.ca)
+ *              Copyright (c) 2002 Arcturus Networks Inc.
+ *                    (www.arcturusnetworks.com)
+ *              Copyright (c) 2003 Metrowerks (www.metrowerks.com)
+ *              Copyright (c) 2004 Analog Device Inc.
+ * Created:     25Jan2001 - Tony Kou
+ * Description: system.h include file
+ *
+ * Modified:     22Sep2006 - Robin Getz
+ *                - move include blackfin.h down, so I can get access to
+ *                   irq functions in other include files.
+ *
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _BLACKFIN_SYSTEM_H
+#define _BLACKFIN_SYSTEM_H
+
+#include <linux/linkage.h>
+#include <linux/compiler.h>
+
+/*
+ * Interrupt configuring macros.
+ */
+
+extern unsigned long irq_flags;
+
+#define local_irq_enable() do {         \
+        __asm__ __volatile__ (          \
+                "sti %0;"               \
+                ::"d"(irq_flags));      \
+} while (0)
+
+#define local_irq_disable() do {        \
+        int _tmp_dummy;                 \
+        __asm__ __volatile__ (          \
+                "cli %0;"               \
+                :"=d" (_tmp_dummy):);   \
+} while (0)
+
+#if defined(ANOMALY_05000244) && defined (CONFIG_BLKFIN_CACHE)
+#define idle_with_irq_disabled() do {   \
+        __asm__ __volatile__ (          \
+                "nop; nop;\n"           \
+                ".align 8;\n"           \
+                "sti %0; idle;\n"       \
+                ::"d" (irq_flags));     \
+} while (0)
+#else
+#define idle_with_irq_disabled() do {   \
+        __asm__ __volatile__ (          \
+                ".align 8;\n"           \
+                "sti %0; idle;\n"       \
+                ::"d" (irq_flags));     \
+} while (0)
+#endif
+
+#ifdef CONFIG_DEBUG_HWERR
+#define __save_and_cli(x) do {                  \
+        __asm__ __volatile__ (                  \
+                "cli %0;\n\tsti %1;"            \
+                :"=&d"(x): "d" (0x3F));         \
+} while (0)
+#else
+#define __save_and_cli(x) do {          \
+        __asm__ __volatile__ (          \
+                "cli %0;"               \
+                :"=&d"(x):);            \
+} while (0)
+#endif
+
+#define local_save_flags(x) asm volatile ("cli %0;"     \
+                                          "sti %0;"     \
+                                          :"=d"(x):);
+
+#ifdef CONFIG_DEBUG_HWERR
+#define irqs_enabled_from_flags(x) (((x) & ~0x3f) != 0)
+#else
+#define irqs_enabled_from_flags(x) ((x) != 0x1f)
+#endif
+
+#define local_irq_restore(x) do {                       \
+        if (irqs_enabled_from_flags(x))                 \
+                local_irq_enable ();                    \
+} while (0)
+
+/* For spinlocks etc */
+#define local_irq_save(x) __save_and_cli(x)
+
+#define irqs_disabled()                         \
+({                                              \
+        unsigned long flags;                    \
+        local_save_flags(flags);                \
+        !irqs_enabled_from_flags(flags);        \
+})
+
+/*
+ * Force strict CPU ordering.
+ */
+#define nop()  asm volatile ("nop;\n\t"::)
+#define mb()   asm volatile (""   : : :"memory")
+#define rmb()  asm volatile (""   : : :"memory")
+#define wmb()  asm volatile (""   : : :"memory")
+#define set_rmb(var, value)    do { (void) xchg(&var, value); } while (0)
+#define set_mb(var, value)     set_rmb(var, value)
+#define set_wmb(var, value)    do { var = value; wmb(); } while (0)
+
+#define read_barrier_depends()          do { } while(0)
+
+#ifdef CONFIG_SMP
+#define smp_mb()        mb()
+#define smp_rmb()       rmb()
+#define smp_wmb()       wmb()
+#define smp_read_barrier_depends()      read_barrier_depends()
+#else
+#define smp_mb()        barrier()
+#define smp_rmb()       barrier()
+#define smp_wmb()       barrier()
+#define smp_read_barrier_depends()      do { } while(0)
+#endif
+
+#define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
+
+struct __xchg_dummy {
+        unsigned long a[100];
+};
+#define __xg(x) ((volatile struct __xchg_dummy *)(x))
+
+static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
+                                   int size)
+{
+        unsigned long tmp = 0;
+        unsigned long flags = 0;
+
+        local_irq_save(flags);
+
+        switch (size) {
+        case 1:
+                __asm__ __volatile__
+                        ("%0 = b%2 (z);\n\t"
+                         "b%2 = %1;\n\t"
+                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        case 2:
+                __asm__ __volatile__
+                        ("%0 = w%2 (z);\n\t"
+                         "w%2 = %1;\n\t"
+                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        case 4:
+                __asm__ __volatile__
+                        ("%0 = %2;\n\t"
+                         "%2 = %1;\n\t"
+                         : "=&d" (tmp) : "d" (x), "m" (*__xg(ptr)) : "memory");
+                break;
+        }
+        local_irq_restore(flags);
+        return tmp;
+}
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+                                      unsigned long new, int size)
+{
+        unsigned long tmp = 0;
+        unsigned long flags = 0;
+
+        local_irq_save(flags);
+
+        switch (size) {
+        case 1:
+                __asm__ __volatile__
+                        ("%0 = b%3 (z);\n\t"
+                         "CC = %1 == %0;\n\t"
+                         "IF !CC JUMP 1f;\n\t"
+                         "b%3 = %2;\n\t"
+                         "1:\n\t"
+                         : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
+                break;
+        case 2:
+                __asm__ __volatile__
+                        ("%0 = w%3 (z);\n\t"
+                         "CC = %1 == %0;\n\t"
+                         "IF !CC JUMP 1f;\n\t"
+                         "w%3 = %2;\n\t"
+                         "1:\n\t"
+                         : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
+                break;
+        case 4:
+                __asm__ __volatile__
+                        ("%0 = %3;\n\t"
+                         "CC = %1 == %0;\n\t"
+                         "IF !CC JUMP 1f;\n\t"
+                         "%3 = %2;\n\t"
+                         "1:\n\t"
+                         : "=&d" (tmp) : "d" (old), "d" (new), "m" (*__xg(ptr)) : "memory");
+                break;
+        }
+        local_irq_restore(flags);
+        return tmp;
+}
+
+#define cmpxchg(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
+                                        (unsigned long)(n),sizeof(*(ptr))))
+
+#define prepare_to_switch()     do { } while(0)
+
+/*
+ * switch_to(n) should switch tasks to task ptr, first checking that
+ * ptr isn't the current task, in which case it does nothing.
+ */
+
+#include <asm/blackfin.h>
+
+asmlinkage struct task_struct *resume(struct task_struct *prev, struct task_struct *next);
+
+#define switch_to(prev,next,last) \
+do {    \
+        memcpy (&prev->thread_info->l1_task_info, L1_SCRATCH_TASK_INFO, \
+                sizeof *L1_SCRATCH_TASK_INFO); \
+        memcpy (L1_SCRATCH_TASK_INFO, &next->thread_info->l1_task_info, \
+                sizeof *L1_SCRATCH_TASK_INFO); \
+        (last) = resume (prev, next);   \
+} while (0)
+
+#endif                          /* _BLACKFIN_SYSTEM_H */
diff --git a/include/asm-blackfin/termbits.h b/include/asm-blackfin/termbits.h
new file mode 100644
index 000000000000..2fd9dabdba77
--- /dev/null
+++ b/include/asm-blackfin/termbits.h
@@ -0,0 +1,184 @@
+#ifndef __ARCH_BFIN_TERMBITS_H__
+#define __ARCH_BFIN_TERMBITS_H__
+
+#include <linux/posix_types.h>
+
+typedef unsigned char cc_t;
+typedef unsigned int speed_t;
+typedef unsigned int tcflag_t;
+
+#define NCCS 19
+struct termios {
+        tcflag_t c_iflag;       /* input mode flags */
+        tcflag_t c_oflag;       /* output mode flags */
+        tcflag_t c_cflag;       /* control mode flags */
+        tcflag_t c_lflag;       /* local mode flags */
+        cc_t c_line;            /* line discipline */
+        cc_t c_cc[NCCS];        /* control characters */
+};
+
+struct ktermios {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
+/* c_cc characters */
+#define VINTR 0
+#define VQUIT 1
+#define VERASE 2
+#define VKILL 3
+#define VEOF 4
+#define VTIME 5
+#define VMIN 6
+#define VSWTC 7
+#define VSTART 8
+#define VSTOP 9
+#define VSUSP 10
+#define VEOL 11
+#define VREPRINT 12
+#define VDISCARD 13
+#define VWERASE 14
+#define VLNEXT 15
+#define VEOL2 16
+
+/* c_iflag bits */
+#define IGNBRK  0000001
+#define BRKINT  0000002
+#define IGNPAR  0000004
+#define PARMRK  0000010
+#define INPCK   0000020
+#define ISTRIP  0000040
+#define INLCR   0000100
+#define IGNCR   0000200
+#define ICRNL   0000400
+#define IUCLC   0001000
+#define IXON    0002000
+#define IXANY   0004000
+#define IXOFF   0010000
+#define IMAXBEL 0020000
+#define IUTF8   0040000
+
+/* c_oflag bits */
+#define OPOST   0000001
+#define OLCUC   0000002
+#define ONLCR   0000004
+#define OCRNL   0000010
+#define ONOCR   0000020
+#define ONLRET  0000040
+#define OFILL   0000100
+#define OFDEL   0000200
+#define NLDLY   0000400
+#define   NL0   0000000
+#define   NL1   0000400
+#define CRDLY   0003000
+#define   CR0   0000000
+#define   CR1   0001000
+#define   CR2   0002000
+#define   CR3   0003000
+#define TABDLY  0014000
+#define   TAB0  0000000
+#define   TAB1  0004000
+#define   TAB2  0010000
+#define   TAB3  0014000
+#define   XTABS 0014000
+#define BSDLY   0020000
+#define   BS0   0000000
+#define   BS1   0020000
+#define VTDLY   0040000
+#define   VT0   0000000
+#define   VT1   0040000
+#define FFDLY   0100000
+#define   FF0   0000000
+#define   FF1   0100000
+
+/* c_cflag bit meaning */
+#define CBAUD   0010017
+#define  B0     0000000         /* hang up */
+#define  B50    0000001
+#define  B75    0000002
+#define  B110   0000003
+#define  B134   0000004
+#define  B150   0000005
+#define  B200   0000006
+#define  B300   0000007
+#define  B600   0000010
+#define  B1200  0000011
+#define  B1800  0000012
+#define  B2400  0000013
+#define  B4800  0000014
+#define  B9600  0000015
+#define  B19200 0000016
+#define  B38400 0000017
+#define EXTA B19200
+#define EXTB B38400
+#define CSIZE   0000060
+#define   CS5   0000000
+#define   CS6   0000020
+#define   CS7   0000040
+#define   CS8   0000060
+#define CSTOPB  0000100
+#define CREAD   0000200
+#define PARENB  0000400
+#define PARODD  0001000
+#define HUPCL   0002000
+#define CLOCAL  0004000
+#define CBAUDEX 0010000
+#define    B57600 0010001
+#define   B115200 0010002
+#define   B230400 0010003
+#define   B460800 0010004
+#define   B500000 0010005
+#define   B576000 0010006
+#define   B921600 0010007
+#define  B1000000 0010010
+#define  B1152000 0010011
+#define  B1500000 0010012
+#define  B2000000 0010013
+#define  B2500000 0010014
+#define  B3000000 0010015
+#define  B3500000 0010016
+#define  B4000000 0010017
+#define CIBAUD    002003600000  /* input baud rate (not used) */
+#define CMSPAR    010000000000  /* mark or space (stick) parity */
+#define CRTSCTS   020000000000  /* flow control */
+
+/* c_lflag bits */
+#define ISIG    0000001
+#define ICANON  0000002
+#define XCASE   0000004
+#define ECHO    0000010
+#define ECHOE   0000020
+#define ECHOK   0000040
+#define ECHONL  0000100
+#define NOFLSH  0000200
+#define TOSTOP  0000400
+#define ECHOCTL 0001000
+#define ECHOPRT 0002000
+#define ECHOKE  0004000
+#define FLUSHO  0010000
+#define PENDIN  0040000
+#define IEXTEN  0100000
+
+/* tcflow() and TCXONC use these */
+#define TCOOFF          0
+#define TCOON           1
+#define TCIOFF          2
+#define TCION           3
+
+/* tcflush() and TCFLSH use these */
+#define TCIFLUSH        0
+#define TCOFLUSH        1
+#define TCIOFLUSH       2
+
+/* tcsetattr uses these */
+#define TCSANOW         0
+#define TCSADRAIN       1
+#define TCSAFLUSH       2
+
+#endif                          /* __ARCH_BFIN_TERMBITS_H__ */
diff --git a/include/asm-blackfin/termios.h b/include/asm-blackfin/termios.h
new file mode 100644
index 000000000000..5c41478a51c6
--- /dev/null
+++ b/include/asm-blackfin/termios.h
@@ -0,0 +1,106 @@
+#ifndef __BFIN_TERMIOS_H__
+#define __BFIN_TERMIOS_H__
+
+#include <asm/termbits.h>
+#include <asm/ioctls.h>
+
+struct winsize {
+        unsigned short ws_row;
+        unsigned short ws_col;
+        unsigned short ws_xpixel;
+        unsigned short ws_ypixel;
+};
+
+#define NCC 8
+struct termio {
+        unsigned short c_iflag; /* input mode flags */
+        unsigned short c_oflag; /* output mode flags */
+        unsigned short c_cflag; /* control mode flags */
+        unsigned short c_lflag; /* local mode flags */
+        unsigned char c_line;   /* line discipline */
+        unsigned char c_cc[NCC];        /* control characters */
+};
+
+/* modem lines */
+#define TIOCM_LE        0x001
+#define TIOCM_DTR       0x002
+#define TIOCM_RTS       0x004
+#define TIOCM_ST        0x008
+#define TIOCM_SR        0x010
+#define TIOCM_CTS       0x020
+#define TIOCM_CAR       0x040
+#define TIOCM_RNG       0x080
+#define TIOCM_DSR       0x100
+#define TIOCM_CD        TIOCM_CAR
+#define TIOCM_RI        TIOCM_RNG
+#define TIOCM_OUT1      0x2000
+#define TIOCM_OUT2      0x4000
+#define TIOCM_LOOP      0x8000
+
+/* ioctl (fd, TIOCSERGETLSR, &result) where result may be as below */
+
+/* line disciplines */
+#define N_TTY           0
+#define N_SLIP          1
+#define N_MOUSE         2
+#define N_PPP           3
+#define N_STRIP         4
+#define N_AX25          5
+#define N_X25           6       /* X.25 async */
+#define N_6PACK         7
+#define N_MASC          8       /* Reserved for Mobitex module <kaz@cafe.net> */
+#define N_R3964         9       /* Reserved for Simatic R3964 module */
+#define N_PROFIBUS_FDL  10      /* Reserved for Profibus <Dave@mvhi.com> */
+#define N_IRDA          11      /* Linux IR - http://irda.sourceforge.net/ */
+#define N_SMSBLOCK      12      /* SMS block mode - for talking to GSM data cards about SMS messages */
+#define N_HDLC          13      /* synchronous HDLC */
+#define N_SYNC_PPP      14      /* synchronous PPP */
+#define N_HCI           15      /* Bluetooth HCI UART */
+
+#ifdef __KERNEL__
+
+/*      intr=^C         quit=^\         erase=del       kill=^U
+        eof=^D          vtime=\0        vmin=\1         sxtc=\0
+        start=^Q        stop=^S         susp=^Z         eol=\0
+        reprint=^R      discard=^U      werase=^W       lnext=^V
+        eol2=\0
+*/
+#define INIT_C_CC "\003\034\177\025\004\0\1\0\021\023\032\0\022\017\027\026\0"
+
+/*
+ * Translate a "termio" structure into a "termios". Ugh.
+ */
+#define SET_LOW_TERMIOS_BITS(termios, termio, x) { \
+        unsigned short __tmp; \
+        get_user(__tmp,&(termio)->x); \
+        *(unsigned short *) &(termios)->x = __tmp; \
+}
+
+#define user_termio_to_kernel_termios(termios, termio) \
+({ \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_iflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_oflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_cflag); \
+        SET_LOW_TERMIOS_BITS(termios, termio, c_lflag); \
+        copy_from_user((termios)->c_cc, (termio)->c_cc, NCC); \
+})
+
+/*
+ * Translate a "termios" structure into a "termio". Ugh.
+ */
+#define kernel_termios_to_user_termio(termio, termios) \
+({ \
+        put_user((termios)->c_iflag, &(termio)->c_iflag); \
+        put_user((termios)->c_oflag, &(termio)->c_oflag); \
+        put_user((termios)->c_cflag, &(termio)->c_cflag); \
+        put_user((termios)->c_lflag, &(termio)->c_lflag); \
+        put_user((termios)->c_line,  &(termio)->c_line); \
+        copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
+})
+
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+
+#endif                          /* __KERNEL__ */
+
+#endif                          /* __BFIN_TERMIOS_H__ */
diff --git a/include/asm-blackfin/thread_info.h b/include/asm-blackfin/thread_info.h
new file mode 100644
index 000000000000..fa8f08cf283e
--- /dev/null
+++ b/include/asm-blackfin/thread_info.h
@@ -0,0 +1,143 @@
+/*
+ * File:         include/asm-blackfin/thread_info.h
+ * Based on:     include/asm-m68knommu/thread_info.h
+ * Author:       LG Soft India
+ *               Copyright (C) 2004-2005 Analog Devices Inc.
+ * Created:      Tue Sep 21 2004
+ * Description:  Blackfin low-level thread information
+ * Modified:
+ * Bugs:         Enter bugs at http://blackfin.uclinux.org/
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2, or (at your option)
+ * any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; see the file COPYING.
+ * If not, write to the Free Software Foundation,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#ifndef _ASM_THREAD_INFO_H
+#define _ASM_THREAD_INFO_H
+
+#include <asm/page.h>
+#include <asm/entry.h>
+#include <asm/l1layout.h>
+#include <linux/compiler.h>
+
+#ifdef __KERNEL__
+
+/* Thread Align Mask to reach to the top of the stack
+ * for any process
+ */
+#define ALIGN_PAGE_MASK         0xffffe000
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long mm_segment_t;
+
+/*
+ * low level task data.
+ * If you change this, change the TI_* offsets below to match.
+ */
+
+struct thread_info {
+        struct task_struct *task;       /* main task structure */
+        struct exec_domain *exec_domain;        /* execution domain */
+        unsigned long flags;    /* low level flags */
+        int cpu;                /* cpu we're on */
+        int preempt_count;      /* 0 => preemptable, <0 => BUG */
+        mm_segment_t addr_limit;        /* address limit */
+        struct restart_block restart_block;
+        struct l1_scratch_task_info l1_task_info;
+};
+
+/*
+ * macros/functions for gaining access to the thread information structure
+ */
+#define INIT_THREAD_INFO(tsk)                   \
+{                                               \
+        .task           = &tsk,                 \
+        .exec_domain    = &default_exec_domain, \
+        .flags          = 0,                    \
+        .cpu            = 0,                    \
+        .preempt_count  = 1,                    \
+        .restart_block  = {                     \
+                .fn = do_no_restart_syscall,    \
+        },                                      \
+}
+#define init_thread_info        (init_thread_union.thread_info)
+#define init_stack              (init_thread_union.stack)
+
+/*
+ * Size of kernel stack for each process. This must be a power of 2...
+ */
+#define THREAD_SIZE             8192    /* 2 pages */
+
+/* How to get the thread information struct from C */
+
+static inline struct thread_info *current_thread_info(void)
+    __attribute__ ((__const__));
+
+/* Given a task stack pointer, you can find it's task structure
+ * just by masking it to the 8K boundary.
+ */
+static inline struct thread_info *current_thread_info(void)
+{
+        struct thread_info *ti;
+      __asm__("%0 = sp;": "=&d"(ti):
+        );
+        return (struct thread_info *)((long)ti & ~8191UL);
+}
+
+/* thread information allocation */
+#define alloc_thread_info(tsk) ((struct thread_info *) \
+                                __get_free_pages(GFP_KERNEL, 1))
+#define free_thread_info(ti)    free_pages((unsigned long) (ti), 1)
+#endif                          /* __ASSEMBLY__ */
+
+/*
+ * Offsets in thread_info structure, used in assembly code
+ */
+#define TI_TASK         0
+#define TI_EXECDOMAIN   4
+#define TI_FLAGS        8
+#define TI_CPU          12
+#define TI_PREEMPT      16
+
+#define PREEMPT_ACTIVE  0x4000000
+
+/*
+ * thread information flag bit numbers
+ */
+#define TIF_SYSCALL_TRACE       0       /* syscall trace active */
+#define TIF_NOTIFY_RESUME       1       /* resumption notification requested */
+#define TIF_SIGPENDING          2       /* signal pending */
+#define TIF_NEED_RESCHED        3       /* rescheduling necessary */
+#define TIF_POLLING_NRFLAG      4       /* true if poll_idle() is polling
+                                           TIF_NEED_RESCHED */
+#define TIF_MEMDIE              5
+#define TIF_RESTORE_SIGMASK     6       /* restore signal mask in do_signal() */
+#define TIF_FREEZE              7       /* is freezing for suspend */
+
+/* as above, but as bit values */
+#define _TIF_SYSCALL_TRACE      (1<<TIF_SYSCALL_TRACE)
+#define _TIF_NOTIFY_RESUME      (1<<TIF_NOTIFY_RESUME)
+#define _TIF_SIGPENDING         (1<<TIF_SIGPENDING)
+#define _TIF_NEED_RESCHED       (1<<TIF_NEED_RESCHED)
+#define _TIF_POLLING_NRFLAG     (1<<TIF_POLLING_NRFLAG)
+#define _TIF_RESTORE_SIGMASK    (1<<TIF_RESTORE_SIGMASK)
+#define _TIF_FREEZE             (1<<TIF_FREEZE)
+
+#define _TIF_WORK_MASK          0x0000FFFE      /* work to do on interrupt/exception return */
+
+#endif                          /* __KERNEL__ */
+
+#endif                          /* _ASM_THREAD_INFO_H */
diff --git a/include/asm-blackfin/timex.h b/include/asm-blackfin/timex.h
new file mode 100644
index 000000000000..828590117f51
--- /dev/null
+++ b/include/asm-blackfin/timex.h
@@ -0,0 +1,18 @@
+/* blackfin architecture timex specifications: Lineo Inc. 2001
+ *
+ * Based on: include/asm-m68knommu/timex.h
+ */
+
+#ifndef _ASMBLACKFIN_TIMEX_H
+#define _ASMBLACKFIN_TIMEX_H
+
+#define CLOCK_TICK_RATE 1000000 /* Underlying HZ */
+
+typedef unsigned long cycles_t;
+
+static inline cycles_t get_cycles(void)
+{
+        return 0;
+}
+
+#endif
diff --git a/include/asm-blackfin/tlb.h b/include/asm-blackfin/tlb.h
new file mode 100644
index 000000000000..89a12ee916d8
--- /dev/null
+++ b/include/asm-blackfin/tlb.h
@@ -0,0 +1,16 @@
+#ifndef _BLACKFIN_TLB_H
+#define _BLACKFIN_TLB_H
+
+#define tlb_start_vma(tlb, vma) do { } while (0)
+#define tlb_end_vma(tlb, vma)   do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address)      do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it
+ * fills up.
+ */
+#define tlb_flush(tlb)          flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif                          /* _BLACKFIN_TLB_H */
diff --git a/include/asm-blackfin/tlbflush.h b/include/asm-blackfin/tlbflush.h
new file mode 100644
index 000000000000..10a07ba1e011
--- /dev/null
+++ b/include/asm-blackfin/tlbflush.h
@@ -0,0 +1,62 @@
+#ifndef _BLACKFIN_TLBFLUSH_H
+#define _BLACKFIN_TLBFLUSH_H
+
+/*
+ * Copyright (C) 2000 Lineo, David McCullough <davidm@uclinux.org>
+ * Copyright (C) 2000-2002, Greg Ungerer <gerg@snapgear.com>
+ */
+
+#include <asm/setup.h>
+
+/*
+ * flush all user-space atc entries.
+ */
+static inline void __flush_tlb(void)
+{
+        BUG();
+}
+
+static inline void __flush_tlb_one(unsigned long addr)
+{
+        BUG();
+}
+
+#define flush_tlb() __flush_tlb()
+
+/*
+ * flush all atc entries (both kernel and user-space entries).
+ */
+static inline void flush_tlb_all(void)
+{
+        BUG();
+}
+
+static inline void flush_tlb_mm(struct mm_struct *mm)
+{
+        BUG();
+}
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                  unsigned long addr)
+{
+        BUG();
+}
+
+static inline void flush_tlb_range(struct mm_struct *mm,
+                                   unsigned long start, unsigned long end)
+{
+        BUG();
+}
+
+static inline void flush_tlb_kernel_page(unsigned long addr)
+{
+        BUG();
+}
+
+static inline void flush_tlb_pgtables(struct mm_struct *mm,
+                                      unsigned long start, unsigned long end)
+{
+        BUG();
+}
+
+#endif
diff --git a/include/asm-blackfin/topology.h b/include/asm-blackfin/topology.h
new file mode 100644
index 000000000000..acee23987897
--- /dev/null
+++ b/include/asm-blackfin/topology.h
@@ -0,0 +1,6 @@
+#ifndef _ASM_BLACKFIN_TOPOLOGY_H
+#define _ASM_BLACKFIN_TOPOLOGY_H
+
+#include <asm-generic/topology.h>
+
+#endif                          /* _ASM_BLACKFIN_TOPOLOGY_H */
diff --git a/include/asm-blackfin/traps.h b/include/asm-blackfin/traps.h
new file mode 100644
index 000000000000..fe365b1b7ca8
--- /dev/null
+++ b/include/asm-blackfin/traps.h
@@ -0,0 +1,75 @@
+/*
+ *  linux/include/asm/traps.h
+ *
+ *  Copyright (C) 1993        Hamish Macdonald
+ *
+ *  Lineo, Inc    Jul 2001    Tony Kou
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file COPYING in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef _BFIN_TRAPS_H
+#define _BFIN_TRAPS_H
+
+#define VEC_SYS         (0)
+#define VEC_EXCPT01     (1)
+#define VEC_EXCPT02     (2)
+#define VEC_EXCPT03     (3)
+#define VEC_EXCPT04     (4)
+#define VEC_EXCPT05     (5)
+#define VEC_EXCPT06     (6)
+#define VEC_EXCPT07     (7)
+#define VEC_EXCPT08     (8)
+#define VEC_EXCPT09     (9)
+#define VEC_EXCPT10     (10)
+#define VEC_EXCPT11     (11)
+#define VEC_EXCPT12     (12)
+#define VEC_EXCPT13     (13)
+#define VEC_EXCPT14     (14)
+#define VEC_EXCPT15     (15)
+#define VEC_STEP        (16)
+#define VEC_OVFLOW      (17)
+#define VEC_UNDEF_I     (33)
+#define VEC_ILGAL_I     (34)
+#define VEC_CPLB_VL     (35)
+#define VEC_MISALI_D    (36)
+#define VEC_UNCOV       (37)
+#define VEC_CPLB_M      (38)
+#define VEC_CPLB_MHIT   (39)
+#define VEC_WATCH       (40)
+#define VEC_ISTRU_VL    (41)    /*ADSP-BF535 only (MH) */
+#define VEC_MISALI_I    (42)
+#define VEC_CPLB_I_VL   (43)
+#define VEC_CPLB_I_M    (44)
+#define VEC_CPLB_I_MHIT (45)
+#define VEC_ILL_RES     (46)    /* including unvalid supervisor mode insn */
+
+#ifndef __ASSEMBLY__
+
+#define HWC_x2 "System MMR Error\nAn error occurred due to an invalid access to an System MMR location\nPossible reason: a 32-bit register is accessed with a 16-bit instruction,\nor a 16-bit register is accessed with a 32-bit instruction.\n"
+#define HWC_x3 "External Memory Addressing Error\n"
+#define HWC_x12 "Performance Monitor Overflow\n"
+#define HWC_x18 "RAISE 5 instruction\n Software issued a RAISE 5 instruction to invoke the Hardware\n"
+#define HWC_default "Reserved\n"
+
+#define EXC_0x03 "Application stack overflow\n - Please increase the stack size of the application using elf2flt -s option,\n and/or reduce the stack use of the application.\n"
+#define EXC_0x10 "Single step\n - When the processor is in single step mode, every instruction\n generates an exception. Primarily used for debugging.\n"
+#define EXC_0x11 "Exception caused by a trace buffer full condition\n - The processor takes this exception when the trace\n buffer overflows (only when enabled by the Trace Unit Control register).\n"
+#define EXC_0x21 "Undefined instruction\n - May be used to emulate instructions that are not defined for\n a particular processor implementation.\n"
+#define EXC_0x22 "Illegal instruction combination\n - See section for multi-issue rules in the ADSP-BF53x Blackfin\n Processor Instruction Set Reference.\n"
+#define EXC_0x23 "Data access CPLB protection violation\n - Attempted read or write to Supervisor resource,\n or illegal data memory access. \n"
+#define EXC_0x24 "Data access misaligned address violation\n - Attempted misaligned data memory or data cache access.\n"
+#define EXC_0x25 "Unrecoverable event\n - For example, an exception generated while processing a previous exception.\n"
+#define EXC_0x26 "Data access CPLB miss\n - Used by the MMU to signal a CPLB miss on a data access.\n"
+#define EXC_0x27 "Data access multiple CPLB hits\n - More than one CPLB entry matches data fetch address.\n"
+#define EXC_0x28 "Program Sequencer Exception caused by an emulation watchpoint match\n - There is a watchpoint match, and one of the EMUSW\n bits in the Watchpoint Instruction Address Control register (WPIACTL) is set.\n"
+#define EXC_0x2A "Instruction fetch misaligned address violation\n - Attempted misaligned instruction cache fetch. On a misaligned instruction fetch exception,\n the return address provided in RETX is the destination address which is misaligned, rather than the address of the offending instruction.\n"
+#define EXC_0x2B "CPLB protection violation\n - Illegal instruction fetch access (memory protection violation).\n"
+#define EXC_0x2C "Instruction fetch CPLB miss\n - CPLB miss on an instruction fetch.\n"
+#define EXC_0x2D "Instruction fetch multiple CPLB hits\n - More than one CPLB entry matches instruction fetch address.\n"
+#define EXC_0x2E "Illegal use of supervisor resource\n - Attempted to use a Supervisor register or instruction from User mode.\n Supervisor resources are registers and instructions that are reserved\n for Supervisor use: Supervisor only registers, all MMRs, and Supervisor\n only instructions.\n"
+
+#endif                          /* __ASSEMBLY__ */
+#endif                          /* _BFIN_TRAPS_H */
diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h
new file mode 100644
index 000000000000..36f8dc8c52ba
--- /dev/null
+++ b/include/asm-blackfin/types.h
@@ -0,0 +1,66 @@
+#ifndef _BFIN_TYPES_H
+#define _BFIN_TYPES_H
+
+/*
+ * This file is never included by application software unless
+ * explicitly requested (e.g., via linux/types.h) in which case the
+ * application is Linux specific so (user-) name space pollution is
+ * not a major issue.  However, for interoperability, libraries still
+ * need to be careful to avoid a name clashes.
+ */
+#ifndef __ASSEMBLY__
+
+typedef unsigned short umode_t;
+
+/*
+ * __xx is ok: it doesn't pollute the POSIX namespace. Use these in the
+ * header files exported to user space
+ */
+
+typedef __signed__ char __s8;
+typedef unsigned char __u8;
+
+typedef __signed__ short __s16;
+typedef unsigned short __u16;
+
+typedef __signed__ int __s32;
+typedef unsigned int __u32;
+
+/* HK0617   -- Changes to unsigned long temporarily */
+#if defined(__GNUC__) && !defined(__STRICT_ANSI__)
+typedef __signed__ long long __s64;
+typedef unsigned long long __u64;
+#endif
+
+#endif                          /* __ASSEMBLY__ */
+/*
+ * These aren't exported outside the kernel to avoid name space clashes
+ */
+#ifdef __KERNEL__
+
+#define BITS_PER_LONG 32
+
+#ifndef __ASSEMBLY__
+
+typedef signed char s8;
+typedef unsigned char u8;
+
+typedef signed short s16;
+typedef unsigned short u16;
+
+typedef signed int s32;
+typedef unsigned int u32;
+
+typedef signed long long s64;
+typedef unsigned long long u64;
+
+/* Dma addresses are 32-bits wide.  */
+
+typedef u32 dma_addr_t;
+typedef u64 dma64_addr_t;
+
+#endif                          /* __ASSEMBLY__ */
+
+#endif                          /* __KERNEL__ */
+
+#endif                          /* _BFIN_TYPES_H */
diff --git a/include/asm-blackfin/uaccess.h b/include/asm-blackfin/uaccess.h
new file mode 100644
index 000000000000..bfcb6794c672
--- /dev/null
+++ b/include/asm-blackfin/uaccess.h
@@ -0,0 +1,271 @@
+/* Changes made by Lineo Inc.    May 2001
+ *
+ * Based on: include/asm-m68knommu/uaccess.h
+ */
+
+#ifndef __BLACKFIN_UACCESS_H
+#define __BLACKFIN_UACCESS_H
+
+/*
+ * User space memory access functions
+ */
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <linux/string.h>
+
+#include <asm/segment.h>
+#ifndef CONFIG_NO_ACCESS_CHECK
+# include <asm/bfin-global.h>
+#endif
+
+#define get_ds()        (KERNEL_DS)
+#define get_fs()        (current_thread_info()->addr_limit)
+
+static inline void set_fs(mm_segment_t fs)
+{
+        current_thread_info()->addr_limit = fs;
+}
+
+#define segment_eq(a,b) ((a) == (b))
+
+#define VERIFY_READ     0
+#define VERIFY_WRITE    1
+
+#define access_ok(type,addr,size) _access_ok((unsigned long)(addr),(size))
+
+static inline int is_in_rom(unsigned long addr)
+{
+        /*
+         * What we are really trying to do is determine if addr is
+         * in an allocated kernel memory region. If not then assume
+         * we cannot free it or otherwise de-allocate it. Ideally
+         * we could restrict this to really being in a ROM or flash,
+         * but that would need to be done on a board by board basis,
+         * not globally.
+         */
+        if ((addr < _ramstart) || (addr >= _ramend))
+                return (1);
+
+        /* Default case, not in ROM */
+        return (0);
+}
+
+/*
+ * The fs value determines whether argument validity checking should be
+ * performed or not.  If get_fs() == USER_DS, checking is performed, with
+ * get_fs() == KERNEL_DS, checking is bypassed.
+ */
+
+#ifdef CONFIG_NO_ACCESS_CHECK
+static inline int _access_ok(unsigned long addr, unsigned long size) { return 1; }
+#else
+#ifdef CONFIG_ACCESS_OK_L1
+extern int _access_ok(unsigned long addr, unsigned long size)__attribute__((l1_text));
+#else
+extern int _access_ok(unsigned long addr, unsigned long size);
+#endif
+#endif
+
+/*
+ * The exception table consists of pairs of addresses: the first is the
+ * address of an instruction that is allowed to fault, and the second is
+ * the address at which the program should continue.  No registers are
+ * modified, so it is entirely up to the continuation code to figure out
+ * what to do.
+ *
+ * All the routines below use bits of fixup code that are out of line
+ * with the main instruction path.  This means when everything is well,
+ * we don't even have to jump over them.  Further, they do not intrude
+ * on our cache or tlb entries.
+ */
+
+struct exception_table_entry {
+        unsigned long insn, fixup;
+};
+
+/* Returns 0 if exception not found and fixup otherwise.  */
+extern unsigned long search_exception_table(unsigned long);
+
+/*
+ * These are the main single-value transfer routines.  They automatically
+ * use the right size if we just have the right pointer type.
+ */
+
+#define put_user(x,p)                                           \
+        ({                                                      \
+                int _err = 0;                                   \
+                typeof(*(p)) _x = (x);                          \
+                typeof(*(p)) *_p = (p);                         \
+                if (!access_ok(VERIFY_WRITE, _p, sizeof(*(_p)))) {\
+                        _err = -EFAULT;                         \
+                }                                               \
+                else {                                          \
+                switch (sizeof (*(_p))) {                       \
+                case 1:                                         \
+                        __put_user_asm(_x, _p, B);              \
+                        break;                                  \
+                case 2:                                         \
+                        __put_user_asm(_x, _p, W);              \
+                        break;                                  \
+                case 4:                                         \
+                        __put_user_asm(_x, _p,  );              \
+                        break;                                  \
+                case 8: {                                       \
+                        long _xl, _xh;                          \
+                        _xl = ((long *)&_x)[0];                 \
+                        _xh = ((long *)&_x)[1];                 \
+                        __put_user_asm(_xl, ((long *)_p)+0, );  \
+                        __put_user_asm(_xh, ((long *)_p)+1, );  \
+                } break;                                        \
+                default:                                        \
+                        _err = __put_user_bad();                \
+                        break;                                  \
+                }                                               \
+                }                                               \
+                _err;                                           \
+        })
+
+#define __put_user(x,p) put_user(x,p)
+static inline int bad_user_access_length(void)
+{
+        panic("bad_user_access_length");
+        return -1;
+}
+
+#define __put_user_bad() (printk(KERN_INFO "put_user_bad %s:%d %s\n",\
+                           __FILE__, __LINE__, __FUNCTION__),\
+                           bad_user_access_length(), (-EFAULT))
+
+/*
+ * Tell gcc we read from memory instead of writing: this is because
+ * we do not write to any memory gcc knows about, so there are no
+ * aliasing issues.
+ */
+
+#define __ptr(x) ((unsigned long *)(x))
+
+#define __put_user_asm(x,p,bhw)                         \
+        __asm__ (#bhw"[%1] = %0;\n\t"                   \
+                 : /* no outputs */                     \
+                 :"d" (x),"a" (__ptr(p)) : "memory")
+
+#define get_user(x,p)                                                   \
+        ({                                                              \
+                int _err = 0;                                           \
+                typeof(*(p)) *_p = (p);                                 \
+                if (!access_ok(VERIFY_READ, _p, sizeof(*(_p)))) {       \
+                        _err = -EFAULT;                                 \
+                }                                                       \
+                else {                                                  \
+                switch (sizeof(*(_p))) {                                \
+                case 1:                                                 \
+                        __get_user_asm(x, _p, B,(Z));                   \
+                        break;                                          \
+                case 2:                                                 \
+                        __get_user_asm(x, _p, W,(Z));                   \
+                        break;                                          \
+                case 4:                                                 \
+                        __get_user_asm(x, _p,  , );                     \
+                        break;                                          \
+                case 8: {                                               \
+                        unsigned long _xl, _xh;                         \
+                        __get_user_asm(_xl, ((unsigned long *)_p)+0,  , ); \
+                        __get_user_asm(_xh, ((unsigned long *)_p)+1,  , ); \
+                        ((unsigned long *)&x)[0] = _xl;                 \
+                        ((unsigned long *)&x)[1] = _xh;                 \
+                } break;                                                \
+                default:                                                \
+                        x = 0;                                          \
+                        printk(KERN_INFO "get_user_bad: %s:%d %s\n",    \
+                               __FILE__, __LINE__, __FUNCTION__);       \
+                        _err = __get_user_bad();                        \
+                        break;                                          \
+                }                                                       \
+                }                                                       \
+                _err;                                                   \
+        })
+
+#define __get_user(x,p) get_user(x,p)
+
+#define __get_user_bad() (bad_user_access_length(), (-EFAULT))
+
+#define __get_user_asm(x,p,bhw,option)                          \
+        {                                                       \
+                unsigned long _tmp;                             \
+                __asm__ ("%0 =" #bhw "[%1]"#option";\n\t"       \
+                         : "=d" (_tmp)                          \
+                         : "a" (__ptr(p)));                     \
+                (x) = (__typeof__(*(p))) _tmp;                  \
+        }
+
+#define __copy_from_user(to, from, n) copy_from_user(to, from, n)
+#define __copy_to_user(to, from, n) copy_to_user(to, from, n)
+#define __copy_to_user_inatomic __copy_to_user
+#define __copy_from_user_inatomic __copy_from_user
+
+#define copy_to_user_ret(to,from,n,retval) ({ if (copy_to_user(to,from,n))\
+                                                 return retval; })
+
+#define copy_from_user_ret(to,from,n,retval) ({ if (copy_from_user(to,from,n))\
+                                                   return retval; })
+
+static inline long copy_from_user(void *to,
+                                  const void __user * from, unsigned long n)
+{
+        if (access_ok(VERIFY_READ, from, n))
+                memcpy(to, from, n);
+        else
+                return n;
+        return 0;
+}
+
+static inline long copy_to_user(void *to,
+                                const void __user * from, unsigned long n)
+{
+        if (access_ok(VERIFY_WRITE, to, n))
+                memcpy(to, from, n);
+        else
+                return n;
+        return 0;
+}
+
+/*
+ * Copy a null terminated string from userspace.
+ */
+
+static inline long strncpy_from_user(char *dst,
+                                     const char *src, long count)
+{
+        char *tmp;
+        if (!access_ok(VERIFY_READ, src, 1))
+                return -EFAULT;
+        strncpy(dst, src, count);
+        for (tmp = dst; *tmp && count > 0; tmp++, count--) ;
+        return (tmp - dst);
+}
+
+/*
+ * Return the size of a string (including the ending 0)
+ *
+ * Return 0 on exception, a value greater than N if too long
+ */
+static inline long strnlen_user(const char *src, long n)
+{
+        return (strlen(src) + 1);
+}
+
+#define strlen_user(str) strnlen_user(str, 32767)
+
+/*
+ * Zero Userspace
+ */
+
+static inline unsigned long __clear_user(void *to, unsigned long n)
+{
+        memset(to, 0, n);
+        return 0;
+}
+
+#define clear_user(to, n) __clear_user(to, n)
+
+#endif                          /* _BLACKFIN_UACCESS_H */
diff --git a/include/asm-blackfin/ucontext.h b/include/asm-blackfin/ucontext.h
new file mode 100644
index 000000000000..4a4e3856beba
--- /dev/null
+++ b/include/asm-blackfin/ucontext.h
@@ -0,0 +1,17 @@
+/** Changes made by Tony Kou   Lineo Inc.    May 2001
+ *
+ *  Based on: include/m68knommu/ucontext.h
+ */
+
+#ifndef _BLACKFIN_UCONTEXT_H
+#define _BLACKFIN_UCONTEXT_H
+
+struct ucontext {
+        unsigned long uc_flags; /* the others are necessary */
+        struct ucontext *uc_link;
+        stack_t uc_stack;
+        struct sigcontext uc_mcontext;
+        sigset_t uc_sigmask;    /* mask last for extensibility */
+};
+
+#endif                          /* _BLACKFIN_UCONTEXT_H */
diff --git a/include/asm-blackfin/unaligned.h b/include/asm-blackfin/unaligned.h
new file mode 100644
index 000000000000..10081dc241ef
--- /dev/null
+++ b/include/asm-blackfin/unaligned.h
@@ -0,0 +1,6 @@
+#ifndef __BFIN_UNALIGNED_H
+#define __BFIN_UNALIGNED_H
+
+#include <asm-generic/unaligned.h>
+
+#endif                          /* __BFIN_UNALIGNED_H */
diff --git a/include/asm-blackfin/unistd.h b/include/asm-blackfin/unistd.h
new file mode 100644
index 000000000000..4df8790a67d5
--- /dev/null
+++ b/include/asm-blackfin/unistd.h
@@ -0,0 +1,382 @@
+#ifndef __ASM_BFIN_UNISTD_H
+#define __ASM_BFIN_UNISTD_H
+/*
+ * This file contains the system call numbers.
+ */
+#define __NR_exit                 1
+#define __NR_fork                 2
+#define __NR_read                 3
+#define __NR_write                4
+#define __NR_open                 5
+#define __NR_close                6
+                                /* 7 __NR_waitpid obsolete */
+#define __NR_creat                8
+#define __NR_link                 9
+#define __NR_unlink              10
+#define __NR_execve              11
+#define __NR_chdir               12
+#define __NR_time                13
+#define __NR_mknod               14
+#define __NR_chmod               15
+#define __NR_chown               16
+                                /* 17 __NR_break obsolete */
+                                /* 18 __NR_oldstat obsolete */
+#define __NR_lseek               19
+#define __NR_getpid              20
+#define __NR_mount               21
+                                /* 22 __NR_umount obsolete */
+#define __NR_setuid              23
+#define __NR_getuid              24
+#define __NR_stime               25
+#define __NR_ptrace              26
+#define __NR_alarm               27
+                                /* 28 __NR_oldfstat obsolete */
+#define __NR_pause               29
+                                /* 30 __NR_utime obsolete */
+                                /* 31 __NR_stty obsolete */
+                                /* 32 __NR_gtty obsolete */
+#define __NR_access              33
+#define __NR_nice                34
+                                /* 35 __NR_ftime obsolete */
+#define __NR_sync                36
+#define __NR_kill                37
+#define __NR_rename              38
+#define __NR_mkdir               39
+#define __NR_rmdir               40
+#define __NR_dup                 41
+#define __NR_pipe                42
+#define __NR_times               43
+                                /* 44 __NR_prof obsolete */
+#define __NR_brk                 45
+#define __NR_setgid              46
+#define __NR_getgid              47
+                                /* 48 __NR_signal obsolete */
+#define __NR_geteuid             49
+#define __NR_getegid             50
+#define __NR_acct                51
+#define __NR_umount2             52
+                                /* 53 __NR_lock obsolete */
+#define __NR_ioctl               54
+#define __NR_fcntl               55
+                                /* 56 __NR_mpx obsolete */
+#define __NR_setpgid             57
+                                /* 58 __NR_ulimit obsolete */
+                                /* 59 __NR_oldolduname obsolete */
+#define __NR_umask               60
+#define __NR_chroot              61
+#define __NR_ustat               62
+#define __NR_dup2                63
+#define __NR_getppid             64
+#define __NR_getpgrp             65
+#define __NR_setsid              66
+                                /* 67 __NR_sigaction obsolete */
+#define __NR_sgetmask            68
+#define __NR_ssetmask            69
+#define __NR_setreuid            70
+#define __NR_setregid            71
+                                /* 72 __NR_sigsuspend obsolete */
+                                /* 73 __NR_sigpending obsolete */
+#define __NR_sethostname         74
+#define __NR_setrlimit           75
+                                /* 76 __NR_old_getrlimit obsolete */
+#define __NR_getrusage           77
+#define __NR_gettimeofday        78
+#define __NR_settimeofday        79
+#define __NR_getgroups           80
+#define __NR_setgroups           81
+                                /* 82 __NR_select obsolete */
+#define __NR_symlink             83
+                                /* 84 __NR_oldlstat obsolete */
+#define __NR_readlink            85
+                                /* 86 __NR_uselib obsolete */
+                                /* 87 __NR_swapon obsolete */
+#define __NR_reboot              88
+                                /* 89 __NR_readdir obsolete */
+                                /* 90 __NR_mmap obsolete */
+#define __NR_munmap              91
+#define __NR_truncate            92
+#define __NR_ftruncate           93
+#define __NR_fchmod              94
+#define __NR_fchown              95
+#define __NR_getpriority         96
+#define __NR_setpriority         97
+                                /* 98 __NR_profil obsolete */
+#define __NR_statfs              99
+#define __NR_fstatfs            100
+                                /* 101 __NR_ioperm */
+                                /* 102 __NR_socketcall obsolete */
+#define __NR_syslog             103
+#define __NR_setitimer          104
+#define __NR_getitimer          105
+#define __NR_stat               106
+#define __NR_lstat              107
+#define __NR_fstat              108
+                                /* 109 __NR_olduname obsolete */
+                                /* 110 __NR_iopl obsolete */
+#define __NR_vhangup            111
+                                /* 112 __NR_idle obsolete */
+                                /* 113 __NR_vm86old */
+#define __NR_wait4              114
+                                /* 115 __NR_swapoff obsolete */
+#define __NR_sysinfo            116
+                                /* 117 __NR_ipc oboslete */
+#define __NR_fsync              118
+                                /* 119 __NR_sigreturn obsolete */
+#define __NR_clone              120
+#define __NR_setdomainname      121
+#define __NR_uname              122
+                                /* 123 __NR_modify_ldt obsolete */
+#define __NR_adjtimex           124
+#define __NR_mprotect           125
+                                /* 126 __NR_sigprocmask obsolete */
+                                /* 127 __NR_create_module obsolete */
+#define __NR_init_module        128
+#define __NR_delete_module      129
+                                /* 130 __NR_get_kernel_syms obsolete */
+#define __NR_quotactl           131
+#define __NR_getpgid            132
+#define __NR_fchdir             133
+#define __NR_bdflush            134
+                                /* 135 was sysfs */
+#define __NR_personality        136
+                                /* 137 __NR_afs_syscall */
+#define __NR_setfsuid           138
+#define __NR_setfsgid           139
+#define __NR__llseek            140
+#define __NR_getdents           141
+                                /* 142 __NR__newselect obsolete */
+#define __NR_flock              143
+                                /* 144 __NR_msync obsolete */
+#define __NR_readv              145
+#define __NR_writev             146
+#define __NR_getsid             147
+#define __NR_fdatasync          148
+#define __NR__sysctl            149
+                                /* 150 __NR_mlock */
+                                /* 151 __NR_munlock */
+                                /* 152 __NR_mlockall */
+                                /* 153 __NR_munlockall */
+#define __NR_sched_setparam             154
+#define __NR_sched_getparam             155
+#define __NR_sched_setscheduler         156
+#define __NR_sched_getscheduler         157
+#define __NR_sched_yield                158
+#define __NR_sched_get_priority_max     159
+#define __NR_sched_get_priority_min     160
+#define __NR_sched_rr_get_interval      161
+#define __NR_nanosleep          162
+                                /* 163 __NR_mremap */
+#define __NR_setresuid          164
+#define __NR_getresuid          165
+                                /* 166 __NR_vm86 */
+                                /* 167 __NR_query_module */
+                                /* 168 __NR_poll */
+                                /* 169 __NR_nfsservctl */
+#define __NR_setresgid          170
+#define __NR_getresgid          171
+#define __NR_prctl              172
+#define __NR_rt_sigreturn       173
+#define __NR_rt_sigaction       174
+#define __NR_rt_sigprocmask     175
+#define __NR_rt_sigpending      176
+#define __NR_rt_sigtimedwait    177
+#define __NR_rt_sigqueueinfo    178
+#define __NR_rt_sigsuspend      179
+#define __NR_pread              180
+#define __NR_pwrite             181
+#define __NR_lchown             182
+#define __NR_getcwd             183
+#define __NR_capget             184
+#define __NR_capset             185
+#define __NR_sigaltstack        186
+#define __NR_sendfile           187
+                                /* 188 __NR_getpmsg */
+                                /* 189 __NR_putpmsg */
+#define __NR_vfork              190
+#define __NR_getrlimit          191
+#define __NR_mmap2              192
+#define __NR_truncate64         193
+#define __NR_ftruncate64        194
+#define __NR_stat64             195
+#define __NR_lstat64            196
+#define __NR_fstat64            197
+#define __NR_chown32            198
+#define __NR_getuid32           199
+#define __NR_getgid32           200
+#define __NR_geteuid32          201
+#define __NR_getegid32          202
+#define __NR_setreuid32         203
+#define __NR_setregid32         204
+#define __NR_getgroups32        205
+#define __NR_setgroups32        206
+#define __NR_fchown32           207
+#define __NR_setresuid32        208
+#define __NR_getresuid32        209
+#define __NR_setresgid32        210
+#define __NR_getresgid32        211
+#define __NR_lchown32           212
+#define __NR_setuid32           213
+#define __NR_setgid32           214
+#define __NR_setfsuid32         215
+#define __NR_setfsgid32         216
+#define __NR_pivot_root         217
+                                /* 218 __NR_mincore */
+                                /* 219 __NR_madvise */
+#define __NR_getdents64         220
+#define __NR_fcntl64            221
+                                /* 222 reserved for TUX */
+                                /* 223 reserved for TUX */
+#define __NR_gettid             224
+                                /* 225 __NR_readahead */
+#define __NR_setxattr           226
+#define __NR_lsetxattr          227
+#define __NR_fsetxattr          228
+#define __NR_getxattr           229
+#define __NR_lgetxattr          230
+#define __NR_fgetxattr          231
+#define __NR_listxattr          232
+#define __NR_llistxattr         233
+#define __NR_flistxattr         234
+#define __NR_removexattr        235
+#define __NR_lremovexattr       236
+#define __NR_fremovexattr       237
+#define __NR_tkill              238
+#define __NR_sendfile64         239
+#define __NR_futex              240
+#define __NR_sched_setaffinity  241
+#define __NR_sched_getaffinity  242
+                                /* 243 __NR_set_thread_area */
+                                /* 244 __NR_get_thread_area */
+#define __NR_io_setup           245
+#define __NR_io_destroy         246
+#define __NR_io_getevents       247
+#define __NR_io_submit          248
+#define __NR_io_cancel          249
+                                /* 250 __NR_alloc_hugepages */
+                                /* 251 __NR_free_hugepages */
+#define __NR_exit_group         252
+#define __NR_lookup_dcookie     253
+#define __NR_bfin_spinlock      254
+
+#define __NR_epoll_create       255
+#define __NR_epoll_ctl          256
+#define __NR_epoll_wait         257
+                                /* 258 __NR_remap_file_pages */
+#define __NR_set_tid_address    259
+#define __NR_timer_create       260
+#define __NR_timer_settime      (__NR_timer_create+1)
+#define __NR_timer_gettime      (__NR_timer_create+2)
+#define __NR_timer_getoverrun   (__NR_timer_create+3)
+#define __NR_timer_delete       (__NR_timer_create+4)
+#define __NR_clock_settime      (__NR_timer_create+5)
+#define __NR_clock_gettime      (__NR_timer_create+6)
+#define __NR_clock_getres       (__NR_timer_create+7)
+#define __NR_clock_nanosleep    (__NR_timer_create+8)
+#define __NR_statfs64           269
+#define __NR_fstatfs64          270
+#define __NR_tgkill             271
+#define __NR_utimes             272
+#define __NR_fadvise64_64       273
+                                /* 274 __NR_vserver */
+                                /* 275 __NR_mbind */
+                                /* 276 __NR_get_mempolicy */
+                                /* 277 __NR_set_mempolicy */
+#define __NR_mq_open            278
+#define __NR_mq_unlink          (__NR_mq_open+1)
+#define __NR_mq_timedsend       (__NR_mq_open+2)
+#define __NR_mq_timedreceive    (__NR_mq_open+3)
+#define __NR_mq_notify          (__NR_mq_open+4)
+#define __NR_mq_getsetattr      (__NR_mq_open+5)
+                                /* 284 __NR_sys_kexec_load */
+#define __NR_waitid             285
+#define __NR_add_key            286
+#define __NR_request_key        287
+#define __NR_keyctl             288
+#define __NR_ioprio_set         289
+#define __NR_ioprio_get         290
+#define __NR_inotify_init       291
+#define __NR_inotify_add_watch  292
+#define __NR_inotify_rm_watch   293
+                                /* 294 __NR_migrate_pages */
+#define __NR_openat             295
+#define __NR_mkdirat            296
+#define __NR_mknodat            297
+#define __NR_fchownat           298
+#define __NR_futimesat          299
+#define __NR_fstatat64          300
+#define __NR_unlinkat           301
+#define __NR_renameat           302
+#define __NR_linkat             303
+#define __NR_symlinkat          304
+#define __NR_readlinkat         305
+#define __NR_fchmodat           306
+#define __NR_faccessat          307
+#define __NR_pselect6           308
+#define __NR_ppoll              309
+#define __NR_unshare            310
+
+/* Blackfin private syscalls */
+#define __NR_sram_alloc         311
+#define __NR_sram_free          312
+#define __NR_dma_memcpy         313
+
+/* socket syscalls */
+#define __NR_accept             314
+#define __NR_bind               315
+#define __NR_connect            316
+#define __NR_getpeername        317
+#define __NR_getsockname        318
+#define __NR_getsockopt         319
+#define __NR_listen             320
+#define __NR_recv               321
+#define __NR_recvfrom           322
+#define __NR_recvmsg            323
+#define __NR_send               324
+#define __NR_sendmsg            325
+#define __NR_sendto             326
+#define __NR_setsockopt         327
+#define __NR_shutdown           328
+#define __NR_socket             329
+#define __NR_socketpair         330
+
+/* sysv ipc syscalls */
+#define __NR_semctl             331
+#define __NR_semget             332
+#define __NR_semop              333
+#define __NR_msgctl             334
+#define __NR_msgget             335
+#define __NR_msgrcv             336
+#define __NR_msgsnd             337
+#define __NR_shmat              338
+#define __NR_shmctl             339
+#define __NR_shmdt              340
+#define __NR_shmget             341
+
+#define __NR_syscall            342
+#define NR_syscalls             __NR_syscall
+
+#ifdef __KERNEL__
+#define __ARCH_WANT_IPC_PARSE_VERSION
+#define __ARCH_WANT_STAT64
+#define __ARCH_WANT_SYS_ALARM
+#define __ARCH_WANT_SYS_GETHOSTNAME
+#define __ARCH_WANT_SYS_PAUSE
+#define __ARCH_WANT_SYS_SGETMASK
+#define __ARCH_WANT_SYS_TIME
+#define __ARCH_WANT_SYS_FADVISE64
+#define __ARCH_WANT_SYS_GETPGRP
+#define __ARCH_WANT_SYS_LLSEEK
+#define __ARCH_WANT_SYS_NICE
+#define __ARCH_WANT_SYS_RT_SIGACTION
+#define __ARCH_WANT_SYS_RT_SIGSUSPEND
+#endif
+
+/*
+ * "Conditional" syscalls
+ *
+ * What we want is __attribute__((weak,alias("sys_ni_syscall"))),
+ * but it doesn't work on all toolchains, so we just do it by hand
+ */
+#define cond_syscall(x) asm(".weak\t_" #x "\n\t.set\t_" #x ",_sys_ni_syscall");
+
+#endif                          /* __ASM_BFIN_UNISTD_H */
diff --git a/include/asm-blackfin/user.h b/include/asm-blackfin/user.h
new file mode 100644
index 000000000000..abc34629bd59
--- /dev/null
+++ b/include/asm-blackfin/user.h
@@ -0,0 +1,89 @@
+#ifndef _BFIN_USER_H
+#define _BFIN_USER_H
+
+/* Changes by Tony Kou   Lineo, Inc.  July, 2001
+ *
+ * Based include/asm-m68knommu/user.h
+ *
+ */
+
+/* Core file format: The core file is written in such a way that gdb
+   can understand it and provide useful information to the user (under
+   linux we use the 'trad-core' bfd).  There are quite a number of
+   obstacles to being able to view the contents of the floating point
+   registers, and until these are solved you will not be able to view the
+   contents of them.  Actually, you can read in the core file and look at
+   the contents of the user struct to find out what the floating point
+   registers contain.
+   The actual file contents are as follows:
+   UPAGE: 1 page consisting of a user struct that tells gdb what is present
+   in the file.  Directly after this is a copy of the task_struct, which
+   is currently not used by gdb, but it may come in useful at some point.
+   All of the registers are stored as part of the upage.  The upage should
+   always be only one page.
+   DATA: The data area is stored.  We use current->end_text to
+   current->brk to pick up all of the user variables, plus any memory
+   that may have been malloced.  No attempt is made to determine if a page
+   is demand-zero or if a page is totally unused, we just cover the entire
+   range.  All of the addresses are rounded in such a way that an integral
+   number of pages is written.
+   STACK: We need the stack information in order to get a meaningful
+   backtrace.  We need to write the data from (esp) to
+   current->start_stack, so we round each of these off in order to be able
+   to write an integer number of pages.
+   The minimum core file size is 3 pages, or 12288 bytes.
+*/
+struct user_bfinfp_struct {
+};
+
+/* This is the old layout of "struct pt_regs" as of Linux 1.x, and
+   is still the layout used by user (the new pt_regs doesn't have
+   all registers). */
+struct user_regs_struct {
+        long r0, r1, r2, r3, r4, r5, r6, r7;
+        long p0, p1, p2, p3, p4, p5, usp, fp;
+        long i0, i1, i2, i3;
+        long l0, l1, l2, l3;
+        long b0, b1, b2, b3;
+        long m0, m1, m2, m3;
+        long a0w, a1w;
+        long a0x, a1x;
+        unsigned long rets;
+        unsigned long astat;
+        unsigned long pc;
+        unsigned long orig_p0;
+};
+
+/* When the kernel dumps core, it starts by dumping the user struct -
+   this will be used by gdb to figure out where the data and stack segments
+   are within the file, and what virtual addresses to use. */
+
+struct user {
+/* We start with the registers, to mimic the way that "memory" is returned
+   from the ptrace(3,...) function.  */
+
+        struct user_regs_struct regs;   /* Where the registers are actually stored */
+
+/* The rest of this junk is to help gdb figure out what goes where */
+        unsigned long int u_tsize;      /* Text segment size (pages). */
+        unsigned long int u_dsize;      /* Data segment size (pages). */
+        unsigned long int u_ssize;      /* Stack segment size (pages). */
+        unsigned long start_code;       /* Starting virtual address of text. */
+        unsigned long start_stack;      /* Starting virtual address of stack area.
+                                           This is actually the bottom of the stack,
+                                           the top of the stack is always found in the
+                                           esp register.  */
+        long int signal;        /* Signal that caused the core dump. */
+        int reserved;           /* No longer used */
+        struct user_regs_struct *u_ar0;
+        /* Used by gdb to help find the values for */
+        /* the registers. */
+        unsigned long magic;    /* To uniquely identify a core file */
+        char u_comm[32];        /* User command that was responsible */
+};
+#define NBPG PAGE_SIZE
+#define UPAGES 1
+#define HOST_TEXT_START_ADDR (u.start_code)
+#define HOST_STACK_END_ADDR (u.start_stack + u.u_ssize * NBPG)
+
+#endif
diff --git a/include/asm-cris/kdebug.h b/include/asm-cris/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-cris/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-frv/atomic.h b/include/asm-frv/atomic.h
index 066386ac238e..d425d8d0ad77 100644
--- a/include/asm-frv/atomic.h
+++ b/include/asm-frv/atomic.h
@@ -16,6 +16,7 @@
 
 #include <linux/types.h>
 #include <asm/spr-regs.h>
+#include <asm/system.h>
 
 #ifdef CONFIG_SMP
 #error not SMP safe
@@ -258,85 +259,23 @@ extern uint32_t __xchg_32(uint32_t i, volatile void *v);
 
 #define tas(ptr) (xchg((ptr), 1))
 
-/*****************************************************************************/
-/*
- * compare and conditionally exchange value with memory
- * - if (*ptr == test) then orig = *ptr; *ptr = test;
- * - if (*ptr != test) then orig = *ptr;
- */
-#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
-
-#define cmpxchg(ptr, test, new)                                                 \
-({                                                                              \
-        __typeof__(ptr) __xg_ptr = (ptr);                                       \
-        __typeof__(*(ptr)) __xg_orig, __xg_tmp;                                 \
-        __typeof__(*(ptr)) __xg_test = (test);                                  \
-        __typeof__(*(ptr)) __xg_new = (new);                                    \
-                                                                                \
-        switch (sizeof(__xg_orig)) {                                            \
-        case 4:                                                                 \
-                asm volatile(                                                   \
-                        "0:                                             \n"     \
-                        "       orcc            gr0,gr0,gr0,icc3        \n"     \
-                        "       ckeq            icc3,cc7                \n"     \
-                        "       ld.p            %M0,%1                  \n"     \
-                        "       orcr            cc7,cc7,cc3             \n"     \
-                        "       sub%I4cc        %1,%4,%2,icc0           \n"     \
-                        "       bne             icc0,#0,1f              \n"     \
-                        "       cst.p           %3,%M0          ,cc3,#1 \n"     \
-                        "       corcc           gr29,gr29,gr0   ,cc3,#1 \n"     \
-                        "       beq             icc3,#0,0b              \n"     \
-                        "1:                                             \n"     \
-                        : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp)    \
-                        : "r"(__xg_new), "NPr"(__xg_test)                       \
-                        : "memory", "cc7", "cc3", "icc3", "icc0"                \
-                        );                                                      \
-                break;                                                          \
-                                                                                \
-        default:                                                                \
-                __xg_orig = 0;                                                  \
-                asm volatile("break");                                          \
-                break;                                                          \
-        }                                                                       \
-                                                                                \
-        __xg_orig;                                                              \
-})
-
-#else
-
-extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
-
-#define cmpxchg(ptr, test, new)                                                 \
-({                                                                              \
-        __typeof__(ptr) __xg_ptr = (ptr);                                       \
-        __typeof__(*(ptr)) __xg_orig;                                           \
-        __typeof__(*(ptr)) __xg_test = (test);                                  \
-        __typeof__(*(ptr)) __xg_new = (new);                                    \
-                                                                                \
-        switch (sizeof(__xg_orig)) {                                            \
-        case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
-        default:                                                                \
-                __xg_orig = 0;                                                  \
-                asm volatile("break");                                          \
-                break;                                                          \
-        }                                                                       \
-                                                                                \
-        __xg_orig;                                                              \
-})
-
-#endif
-
 #define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
 
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
diff --git a/include/asm-frv/kdebug.h b/include/asm-frv/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-frv/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-frv/pgtable.h b/include/asm-frv/pgtable.h
index 8a05aa168616..2687c7715120 100644
--- a/include/asm-frv/pgtable.h
+++ b/include/asm-frv/pgtable.h
@@ -509,10 +509,6 @@ static inline int pte_file(pte_t pte)
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
diff --git a/include/asm-frv/semaphore.h b/include/asm-frv/semaphore.h
index 907c5c3643cc..09586528e007 100644
--- a/include/asm-frv/semaphore.h
+++ b/include/asm-frv/semaphore.h
@@ -20,8 +20,6 @@
 #include <linux/spinlock.h>
 #include <linux/rwsem.h>
 
-#define SEMAPHORE_DEBUG         0
-
 /*
  * the semaphore definition
  * - if counter is >0 then there are tokens available on the semaphore for down to collect
@@ -32,12 +30,12 @@ struct semaphore {
         unsigned                counter;
         spinlock_t              wait_lock;
         struct list_head        wait_list;
-#if SEMAPHORE_DEBUG
+#ifdef CONFIG_DEBUG_SEMAPHORE
         unsigned                __magic;
 #endif
 };
 
-#if SEMAPHORE_DEBUG
+#ifdef CONFIG_DEBUG_SEMAPHORE
 # define __SEM_DEBUG_INIT(name) , (long)&(name).__magic
 #else
 # define __SEM_DEBUG_INIT(name)
@@ -76,7 +74,7 @@ static inline void down(struct semaphore *sem)
 {
         unsigned long flags;
 
-#if SEMAPHORE_DEBUG
+#ifdef CONFIG_DEBUG_SEMAPHORE
         CHECK_MAGIC(sem->__magic);
 #endif
 
@@ -95,7 +93,7 @@ static inline int down_interruptible(struct semaphore *sem)
         unsigned long flags;
         int ret = 0;
 
-#if SEMAPHORE_DEBUG
+#ifdef CONFIG_DEBUG_SEMAPHORE
         CHECK_MAGIC(sem->__magic);
 #endif
 
@@ -119,7 +117,7 @@ static inline int down_trylock(struct semaphore *sem)
         unsigned long flags;
         int success = 0;
 
-#if SEMAPHORE_DEBUG
+#ifdef CONFIG_DEBUG_SEMAPHORE
         CHECK_MAGIC(sem->__magic);
 #endif
 
@@ -136,7 +134,7 @@ static inline void up(struct semaphore *sem)
 {
         unsigned long flags;
 
-#if SEMAPHORE_DEBUG
+#ifdef CONFIG_DEBUG_SEMAPHORE
         CHECK_MAGIC(sem->__magic);
 #endif
 
diff --git a/include/asm-frv/system.h b/include/asm-frv/system.h
index 1166899317d7..be303b3eef40 100644
--- a/include/asm-frv/system.h
+++ b/include/asm-frv/system.h
@@ -13,7 +13,6 @@
 #define _ASM_SYSTEM_H
 
 #include <linux/linkage.h>
-#include <asm/atomic.h>
 
 struct thread_struct;
 
@@ -197,4 +196,73 @@ extern void free_initmem(void);
 
 #define arch_align_stack(x) (x)
 
+/*****************************************************************************/
+/*
+ * compare and conditionally exchange value with memory
+ * - if (*ptr == test) then orig = *ptr; *ptr = test;
+ * - if (*ptr != test) then orig = *ptr;
+ */
+#ifndef CONFIG_FRV_OUTOFLINE_ATOMIC_OPS
+
+#define cmpxchg(ptr, test, new)                                                 \
+({                                                                              \
+        __typeof__(ptr) __xg_ptr = (ptr);                                       \
+        __typeof__(*(ptr)) __xg_orig, __xg_tmp;                                 \
+        __typeof__(*(ptr)) __xg_test = (test);                                  \
+        __typeof__(*(ptr)) __xg_new = (new);                                    \
+                                                                                \
+        switch (sizeof(__xg_orig)) {                                            \
+        case 4:                                                                 \
+                asm volatile(                                                   \
+                        "0:                                             \n"     \
+                        "       orcc            gr0,gr0,gr0,icc3        \n"     \
+                        "       ckeq            icc3,cc7                \n"     \
+                        "       ld.p            %M0,%1                  \n"     \
+                        "       orcr            cc7,cc7,cc3             \n"     \
+                        "       sub%I4cc        %1,%4,%2,icc0           \n"     \
+                        "       bne             icc0,#0,1f              \n"     \
+                        "       cst.p           %3,%M0          ,cc3,#1 \n"     \
+                        "       corcc           gr29,gr29,gr0   ,cc3,#1 \n"     \
+                        "       beq             icc3,#0,0b              \n"     \
+                        "1:                                             \n"     \
+                        : "+U"(*__xg_ptr), "=&r"(__xg_orig), "=&r"(__xg_tmp)    \
+                        : "r"(__xg_new), "NPr"(__xg_test)                       \
+                        : "memory", "cc7", "cc3", "icc3", "icc0"                \
+                        );                                                      \
+                break;                                                          \
+                                                                                \
+        default:                                                                \
+                __xg_orig = 0;                                                  \
+                asm volatile("break");                                          \
+                break;                                                          \
+        }                                                                       \
+                                                                                \
+        __xg_orig;                                                              \
+})
+
+#else
+
+extern uint32_t __cmpxchg_32(uint32_t *v, uint32_t test, uint32_t new);
+
+#define cmpxchg(ptr, test, new)                                                 \
+({                                                                              \
+        __typeof__(ptr) __xg_ptr = (ptr);                                       \
+        __typeof__(*(ptr)) __xg_orig;                                           \
+        __typeof__(*(ptr)) __xg_test = (test);                                  \
+        __typeof__(*(ptr)) __xg_new = (new);                                    \
+                                                                                \
+        switch (sizeof(__xg_orig)) {                                            \
+        case 4: __xg_orig = __cmpxchg_32(__xg_ptr, __xg_test, __xg_new); break; \
+        default:                                                                \
+                __xg_orig = 0;                                                  \
+                asm volatile("break");                                          \
+                break;                                                          \
+        }                                                                       \
+                                                                                \
+        __xg_orig;                                                              \
+})
+
+#endif
+
+
 #endif /* _ASM_SYSTEM_H */
diff --git a/include/asm-generic/atomic.h b/include/asm-generic/atomic.h
index b7e4a0467cb1..85fd0aa27a8c 100644
--- a/include/asm-generic/atomic.h
+++ b/include/asm-generic/atomic.h
@@ -66,6 +66,76 @@ static inline void atomic_long_sub(long i, atomic_long_t *l)
         atomic64_sub(i, v);
 }
 
+static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return atomic64_sub_and_test(i, v);
+}
+
+static inline int atomic_long_dec_and_test(atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return atomic64_dec_and_test(v);
+}
+
+static inline int atomic_long_inc_and_test(atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return atomic64_inc_and_test(v);
+}
+
+static inline int atomic_long_add_negative(long i, atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return atomic64_add_negative(i, v);
+}
+
+static inline long atomic_long_add_return(long i, atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return (long)atomic64_add_return(i, v);
+}
+
+static inline long atomic_long_sub_return(long i, atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return (long)atomic64_sub_return(i, v);
+}
+
+static inline long atomic_long_inc_return(atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return (long)atomic64_inc_return(v);
+}
+
+static inline long atomic_long_dec_return(atomic_long_t *l)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return (long)atomic64_dec_return(v);
+}
+
+static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
+{
+        atomic64_t *v = (atomic64_t *)l;
+
+        return (long)atomic64_add_unless(v, a, u);
+}
+
+#define atomic_long_inc_not_zero(l) atomic64_inc_not_zero((atomic64_t *)(l))
+
+#define atomic_long_cmpxchg(l, old, new) \
+        (atomic_cmpxchg((atomic64_t *)(l), (old), (new)))
+#define atomic_long_xchg(v, new) \
+        (atomic_xchg((atomic64_t *)(l), (new)))
+
 #else  /*  BITS_PER_LONG == 64  */
 
 typedef atomic_t atomic_long_t;
@@ -113,6 +183,76 @@ static inline void atomic_long_sub(long i, atomic_long_t *l)
         atomic_sub(i, v);
 }
 
+static inline int atomic_long_sub_and_test(long i, atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return atomic_sub_and_test(i, v);
+}
+
+static inline int atomic_long_dec_and_test(atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return atomic_dec_and_test(v);
+}
+
+static inline int atomic_long_inc_and_test(atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return atomic_inc_and_test(v);
+}
+
+static inline int atomic_long_add_negative(long i, atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return atomic_add_negative(i, v);
+}
+
+static inline long atomic_long_add_return(long i, atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return (long)atomic_add_return(i, v);
+}
+
+static inline long atomic_long_sub_return(long i, atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return (long)atomic_sub_return(i, v);
+}
+
+static inline long atomic_long_inc_return(atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return (long)atomic_inc_return(v);
+}
+
+static inline long atomic_long_dec_return(atomic_long_t *l)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return (long)atomic_dec_return(v);
+}
+
+static inline long atomic_long_add_unless(atomic_long_t *l, long a, long u)
+{
+        atomic_t *v = (atomic_t *)l;
+
+        return (long)atomic_add_unless(v, a, u);
+}
+
+#define atomic_long_inc_not_zero(l) atomic_inc_not_zero((atomic_t *)(l))
+
+#define atomic_long_cmpxchg(l, old, new) \
+        (atomic_cmpxchg((atomic_t *)(l), (old), (new)))
+#define atomic_long_xchg(v, new) \
+        (atomic_xchg((atomic_t *)(l), (new)))
+
 #endif  /*  BITS_PER_LONG == 64  */
 
 #endif  /*  _ASM_GENERIC_ATOMIC_H  */
diff --git a/include/asm-generic/kdebug.h b/include/asm-generic/kdebug.h
new file mode 100644
index 000000000000..2b799c90b2d4
--- /dev/null
+++ b/include/asm-generic/kdebug.h
@@ -0,0 +1,8 @@
+#ifndef _ASM_GENERIC_KDEBUG_H
+#define _ASM_GENERIC_KDEBUG_H
+
+enum die_val {
+        DIE_UNUSED,
+};
+
+#endif /* _ASM_GENERIC_KDEBUG_H */
diff --git a/include/asm-generic/local.h b/include/asm-generic/local.h
index ab469297272c..33d7d04e4119 100644
--- a/include/asm-generic/local.h
+++ b/include/asm-generic/local.h
@@ -33,6 +33,19 @@ typedef struct
 #define local_add(i,l)  atomic_long_add((i),(&(l)->a))
 #define local_sub(i,l)  atomic_long_sub((i),(&(l)->a))
 
+#define local_sub_and_test(i, l) atomic_long_sub_and_test((i), (&(l)->a))
+#define local_dec_and_test(l) atomic_long_dec_and_test(&(l)->a)
+#define local_inc_and_test(l) atomic_long_inc_and_test(&(l)->a)
+#define local_add_negative(i, l) atomic_long_add_negative((i), (&(l)->a))
+#define local_add_return(i, l) atomic_long_add_return((i), (&(l)->a))
+#define local_sub_return(i, l) atomic_long_sub_return((i), (&(l)->a))
+#define local_inc_return(l) atomic_long_inc_return(&(l)->a)
+
+#define local_cmpxchg(l, o, n) atomic_long_cmpxchg((&(l)->a), (o), (n))
+#define local_xchg(l, n) atomic_long_xchg((&(l)->a), (n))
+#define local_add_unless(l, a, u) atomic_long_add_unless((&(l)->a), (a), (u))
+#define local_inc_not_zero(l) atomic_long_inc_not_zero(&(l)->a)
+
 /* Non-atomic variants, ie. preemption disabled and won't be touched
  * in interrupt, etc.  Some archs can optimize this case well. */
 #define __local_inc(l)          local_set((l), local_read(l) + 1)
@@ -44,19 +57,19 @@ typedef struct
  * much more efficient than these naive implementations.  Note they take
  * a variable (eg. mystruct.foo), not an address.
  */
-#define cpu_local_read(v)       local_read(&__get_cpu_var(v))
-#define cpu_local_set(v, i)     local_set(&__get_cpu_var(v), (i))
-#define cpu_local_inc(v)        local_inc(&__get_cpu_var(v))
-#define cpu_local_dec(v)        local_dec(&__get_cpu_var(v))
-#define cpu_local_add(i, v)     local_add((i), &__get_cpu_var(v))
-#define cpu_local_sub(i, v)     local_sub((i), &__get_cpu_var(v))
+#define cpu_local_read(l)       local_read(&__get_cpu_var(l))
+#define cpu_local_set(l, i)     local_set(&__get_cpu_var(l), (i))
+#define cpu_local_inc(l)        local_inc(&__get_cpu_var(l))
+#define cpu_local_dec(l)        local_dec(&__get_cpu_var(l))
+#define cpu_local_add(i, l)     local_add((i), &__get_cpu_var(l))
+#define cpu_local_sub(i, l)     local_sub((i), &__get_cpu_var(l))
 
 /* Non-atomic increments, ie. preemption disabled and won't be touched
  * in interrupt, etc.  Some archs can optimize this case well.
  */
-#define __cpu_local_inc(v)      __local_inc(&__get_cpu_var(v))
-#define __cpu_local_dec(v)      __local_dec(&__get_cpu_var(v))
-#define __cpu_local_add(i, v)   __local_add((i), &__get_cpu_var(v))
-#define __cpu_local_sub(i, v)   __local_sub((i), &__get_cpu_var(v))
+#define __cpu_local_inc(l)      __local_inc(&__get_cpu_var(l))
+#define __cpu_local_dec(l)      __local_dec(&__get_cpu_var(l))
+#define __cpu_local_add(i, l)   __local_add((i), &__get_cpu_var(l))
+#define __cpu_local_sub(i, l)   __local_sub((i), &__get_cpu_var(l))
 
 #endif /* _ASM_GENERIC_LOCAL_H */
diff --git a/include/asm-h8300/irq.h b/include/asm-h8300/irq.h
index 42a3ac424a9e..41be646c3514 100644
--- a/include/asm-h8300/irq.h
+++ b/include/asm-h8300/irq.h
@@ -61,6 +61,5 @@ static __inline__ int irq_canonicalize(int irq)
 
 extern void enable_irq(unsigned int);
 extern void disable_irq(unsigned int);
-#define disable_irq_nosync(x)   disable_irq(x)
 
 #endif /* _H8300_IRQ_H_ */
diff --git a/include/asm-h8300/irq_regs.h b/include/asm-h8300/irq_regs.h
new file mode 100644
index 000000000000..3dd9c0b70270
--- /dev/null
+++ b/include/asm-h8300/irq_regs.h
@@ -0,0 +1 @@
+#include <asm-generic/irq_regs.h>
diff --git a/include/asm-h8300/kdebug.h b/include/asm-h8300/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-h8300/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-h8300/pgtable.h b/include/asm-h8300/pgtable.h
index 8b7c6857998b..a09230a08e02 100644
--- a/include/asm-h8300/pgtable.h
+++ b/include/asm-h8300/pgtable.h
@@ -55,10 +55,6 @@ extern int is_in_rom(unsigned long);
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /*
  * All 32bit addresses are effectively valid for vmalloc...
  * Sort of meaningless for non-VM targets.
@@ -73,4 +69,5 @@ extern int is_in_rom(unsigned long);
 #define VMALLOC_START   0
 #define VMALLOC_END     0xffffffff
 
+#define arch_enter_lazy_cpu_mode()    do {} while (0)
 #endif /* _H8300_PGTABLE_H */
diff --git a/include/asm-h8300/system.h b/include/asm-h8300/system.h
index 5084a9d42922..7807018f8500 100644
--- a/include/asm-h8300/system.h
+++ b/include/asm-h8300/system.h
@@ -98,7 +98,6 @@ asmlinkage void resume(void);
 #endif
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
diff --git a/include/asm-i386/atomic.h b/include/asm-i386/atomic.h
index 4dd272331361..0baa2f89463c 100644
--- a/include/asm-i386/atomic.h
+++ b/include/asm-i386/atomic.h
@@ -3,6 +3,7 @@
 
 #include <linux/compiler.h>
 #include <asm/processor.h>
+#include <asm/cmpxchg.h>
 
 /*
  * Atomic operations that C can't guarantee us.  Useful for
@@ -51,7 +52,7 @@ static __inline__ void atomic_add(int i, atomic_t *v)
 }
 
 /**
- * atomic_sub - subtract the atomic variable
+ * atomic_sub - subtract integer from atomic variable
  * @i: integer value to subtract
  * @v: pointer of type atomic_t
  * 
@@ -170,7 +171,7 @@ static __inline__ int atomic_add_negative(int i, atomic_t *v)
 }
 
 /**
- * atomic_add_return - add and return
+ * atomic_add_return - add integer and return
  * @v: pointer of type atomic_t
  * @i: integer value to add
  *
@@ -202,13 +203,20 @@ no_xadd: /* Legacy 386 processor */
 #endif
 }
 
+/**
+ * atomic_sub_return - subtract integer and return
+ * @v: pointer of type atomic_t
+ * @i: integer value to subtract
+ *
+ * Atomically subtracts @i from @v and returns @v - @i
+ */
 static __inline__ int atomic_sub_return(int i, atomic_t *v)
 {
         return atomic_add_return(-i,v);
 }
 
-#define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), (old), (new)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
 
 /**
  * atomic_add_unless - add unless the number is already a given value
@@ -219,20 +227,21 @@ static __inline__ int atomic_sub_return(int i, atomic_t *v)
  * Atomically adds @a to @v, so long as @v was not already @u.
  * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        for (;;) {                                              \
-                if (unlikely(c == (u)))                         \
-                        break;                                  \
-                old = atomic_cmpxchg((v), c, c + (a));          \
-                if (likely(old == c))                           \
-                        break;                                  \
-                c = old;                                        \
-        }                                                       \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 #define atomic_inc_return(v)  (atomic_add_return(1,v))
diff --git a/include/asm-i386/cmpxchg.h b/include/asm-i386/cmpxchg.h
new file mode 100644
index 000000000000..7adcef0cd53b
--- /dev/null
+++ b/include/asm-i386/cmpxchg.h
@@ -0,0 +1,293 @@
+#ifndef __ASM_CMPXCHG_H
+#define __ASM_CMPXCHG_H
+
+#include <linux/bitops.h> /* for LOCK_PREFIX */
+
+#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
+
+struct __xchg_dummy { unsigned long a[100]; };
+#define __xg(x) ((struct __xchg_dummy *)(x))
+
+
+#ifdef CONFIG_X86_CMPXCHG64
+
+/*
+ * The semantics of XCHGCMP8B are a bit strange, this is why
+ * there is a loop and the loading of %%eax and %%edx has to
+ * be inside. This inlines well in most cases, the cached
+ * cost is around ~38 cycles. (in the future we might want
+ * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
+ * might have an implicit FPU-save as a cost, so it's not
+ * clear which path to go.)
+ *
+ * cmpxchg8b must be used with the lock prefix here to allow
+ * the instruction to be executed atomically, see page 3-102
+ * of the instruction set reference 24319102.pdf. We need
+ * the reader side to see the coherent 64bit value.
+ */
+static inline void __set_64bit (unsigned long long * ptr,
+                unsigned int low, unsigned int high)
+{
+        __asm__ __volatile__ (
+                "\n1:\t"
+                "movl (%0), %%eax\n\t"
+                "movl 4(%0), %%edx\n\t"
+                "lock cmpxchg8b (%0)\n\t"
+                "jnz 1b"
+                : /* no outputs */
+                :       "D"(ptr),
+                        "b"(low),
+                        "c"(high)
+                :       "ax","dx","memory");
+}
+
+static inline void __set_64bit_constant (unsigned long long *ptr,
+                                                 unsigned long long value)
+{
+        __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
+}
+#define ll_low(x)       *(((unsigned int*)&(x))+0)
+#define ll_high(x)      *(((unsigned int*)&(x))+1)
+
+static inline void __set_64bit_var (unsigned long long *ptr,
+                         unsigned long long value)
+{
+        __set_64bit(ptr,ll_low(value), ll_high(value));
+}
+
+#define set_64bit(ptr,value) \
+(__builtin_constant_p(value) ? \
+ __set_64bit_constant(ptr, value) : \
+ __set_64bit_var(ptr, value) )
+
+#define _set_64bit(ptr,value) \
+(__builtin_constant_p(value) ? \
+ __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
+ __set_64bit(ptr, ll_low(value), ll_high(value)) )
+
+#endif
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ *        but generally the primitive is invalid, *ptr is output argument. --ANK
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+                case 1:
+                        __asm__ __volatile__("xchgb %b0,%1"
+                                :"=q" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+                case 2:
+                        __asm__ __volatile__("xchgw %w0,%1"
+                                :"=r" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+                case 4:
+                        __asm__ __volatile__("xchgl %0,%1"
+                                :"=r" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+        }
+        return x;
+}
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#ifdef CONFIG_X86_CMPXCHG
+#define __HAVE_ARCH_CMPXCHG 1
+#define cmpxchg(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
+                                        (unsigned long)(n),sizeof(*(ptr))))
+#define sync_cmpxchg(ptr,o,n)\
+        ((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
+                                        (unsigned long)(n),sizeof(*(ptr))))
+#define cmpxchg_local(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg_local((ptr),(unsigned long)(o),\
+                                        (unsigned long)(n),sizeof(*(ptr))))
+#endif
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+                                      unsigned long new, int size)
+{
+        unsigned long prev;
+        switch (size) {
+        case 1:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
+                                     : "=a"(prev)
+                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 2:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 4:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        }
+        return old;
+}
+
+/*
+ * Always use locked operations when touching memory shared with a
+ * hypervisor, since the system may be SMP even if the guest kernel
+ * isn't.
+ */
+static inline unsigned long __sync_cmpxchg(volatile void *ptr,
+                                            unsigned long old,
+                                            unsigned long new, int size)
+{
+        unsigned long prev;
+        switch (size) {
+        case 1:
+                __asm__ __volatile__("lock; cmpxchgb %b1,%2"
+                                     : "=a"(prev)
+                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 2:
+                __asm__ __volatile__("lock; cmpxchgw %w1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 4:
+                __asm__ __volatile__("lock; cmpxchgl %1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        }
+        return old;
+}
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+                        unsigned long old, unsigned long new, int size)
+{
+        unsigned long prev;
+        switch (size) {
+        case 1:
+                __asm__ __volatile__("cmpxchgb %b1,%2"
+                                     : "=a"(prev)
+                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 2:
+                __asm__ __volatile__("cmpxchgw %w1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 4:
+                __asm__ __volatile__("cmpxchgl %1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        }
+        return old;
+}
+
+#ifndef CONFIG_X86_CMPXCHG
+/*
+ * Building a kernel capable running on 80386. It may be necessary to
+ * simulate the cmpxchg on the 80386 CPU. For that purpose we define
+ * a function for each of the sizes we support.
+ */
+
+extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
+extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
+extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
+
+static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
+                                      unsigned long new, int size)
+{
+        switch (size) {
+        case 1:
+                return cmpxchg_386_u8(ptr, old, new);
+        case 2:
+                return cmpxchg_386_u16(ptr, old, new);
+        case 4:
+                return cmpxchg_386_u32(ptr, old, new);
+        }
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)                                                \
+({                                                                      \
+        __typeof__(*(ptr)) __ret;                                       \
+        if (likely(boot_cpu_data.x86 > 3))                              \
+                __ret = __cmpxchg((ptr), (unsigned long)(o),            \
+                                        (unsigned long)(n), sizeof(*(ptr))); \
+        else                                                            \
+                __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
+                                        (unsigned long)(n), sizeof(*(ptr))); \
+        __ret;                                                          \
+})
+#define cmpxchg_local(ptr,o,n)                                          \
+({                                                                      \
+        __typeof__(*(ptr)) __ret;                                       \
+        if (likely(boot_cpu_data.x86 > 3))                              \
+                __ret = __cmpxchg_local((ptr), (unsigned long)(o),      \
+                                        (unsigned long)(n), sizeof(*(ptr))); \
+        else                                                            \
+                __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
+                                        (unsigned long)(n), sizeof(*(ptr))); \
+        __ret;                                                          \
+})
+#endif
+
+#ifdef CONFIG_X86_CMPXCHG64
+
+static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
+                                      unsigned long long new)
+{
+        unsigned long long prev;
+        __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
+                             : "=A"(prev)
+                             : "b"((unsigned long)new),
+                               "c"((unsigned long)(new >> 32)),
+                               "m"(*__xg(ptr)),
+                               "0"(old)
+                             : "memory");
+        return prev;
+}
+
+static inline unsigned long long __cmpxchg64_local(volatile void *ptr,
+                        unsigned long long old, unsigned long long new)
+{
+        unsigned long long prev;
+        __asm__ __volatile__("cmpxchg8b %3"
+                             : "=A"(prev)
+                             : "b"((unsigned long)new),
+                               "c"((unsigned long)(new >> 32)),
+                               "m"(*__xg(ptr)),
+                               "0"(old)
+                             : "memory");
+        return prev;
+}
+
+#define cmpxchg64(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
+                                        (unsigned long long)(n)))
+#define cmpxchg64_local(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg64_local((ptr),(unsigned long long)(o),\
+                                        (unsigned long long)(n)))
+#endif
+
+#endif
diff --git a/include/asm-i386/elf.h b/include/asm-i386/elf.h
index d304ab4161ff..b32df3a332da 100644
--- a/include/asm-i386/elf.h
+++ b/include/asm-i386/elf.h
@@ -9,8 +9,6 @@
 #include <asm/user.h>
 #include <asm/auxvec.h>
 
-#include <linux/utsname.h>
-
 #define R_386_NONE      0
 #define R_386_32        1
 #define R_386_PC32      2
diff --git a/include/asm-i386/ioctls.h b/include/asm-i386/ioctls.h
index f962fadab0fa..ef5878762dc9 100644
--- a/include/asm-i386/ioctls.h
+++ b/include/asm-i386/ioctls.h
@@ -47,6 +47,10 @@
 #define TIOCSBRK        0x5427  /* BSD compatibility */
 #define TIOCCBRK        0x5428  /* BSD compatibility */
 #define TIOCGSID        0x5429  /* Return the session ID of FD */
+#define TCGETS2         _IOR('T',0x2A, struct termios2)
+#define TCSETS2         _IOW('T',0x2B, struct termios2)
+#define TCSETSW2        _IOW('T',0x2C, struct termios2)
+#define TCSETSF2        _IOW('T',0x2D, struct termios2)
 #define TIOCGPTN        _IOR('T',0x30, unsigned int) /* Get Pty Number (of pty-mux device) */
 #define TIOCSPTLCK      _IOW('T',0x31, int)  /* Lock/unlock Pty */
 
diff --git a/include/asm-i386/kdebug.h b/include/asm-i386/kdebug.h
index d18cdb9fc9a6..05c3117788b9 100644
--- a/include/asm-i386/kdebug.h
+++ b/include/asm-i386/kdebug.h
@@ -9,19 +9,8 @@
 
 struct pt_regs;
 
-struct die_args {
-        struct pt_regs *regs;
-        const char *str;
-        long err;
-        int trapnr;
-        int signr;
-};
-
-extern int register_die_notifier(struct notifier_block *);
-extern int unregister_die_notifier(struct notifier_block *);
 extern int register_page_fault_notifier(struct notifier_block *);
 extern int unregister_page_fault_notifier(struct notifier_block *);
-extern struct atomic_notifier_head i386die_chain;
 
 
 /* Grossly misnamed. */
@@ -38,20 +27,8 @@ enum die_val {
         DIE_GPF,
         DIE_CALL,
         DIE_NMI_IPI,
+        DIE_NMI_POST,
         DIE_PAGE_FAULT,
 };
 
-static inline int notify_die(enum die_val val, const char *str,
-                        struct pt_regs *regs, long err, int trap, int sig)
-{
-        struct die_args args = {
-                .regs = regs,
-                .str = str,
-                .err = err,
-                .trapnr = trap,
-                .signr = sig
-        };
-        return atomic_notifier_call_chain(&i386die_chain, val, &args);
-}
-
 #endif
diff --git a/include/asm-i386/kexec.h b/include/asm-i386/kexec.h
index bcb5b21de2d2..4b9dc9e6b701 100644
--- a/include/asm-i386/kexec.h
+++ b/include/asm-i386/kexec.h
@@ -45,8 +45,6 @@
 /* We can also handle crash dumps from 64 bit kernel. */
 #define vmcore_elf_check_arch_cross(x) ((x)->e_machine == EM_X86_64)
 
-#define MAX_NOTE_BYTES 1024
-
 /* CPU does not save ss and esp on stack if execution is already
  * running in kernel mode at the time of NMI occurrence. This code
  * fixes it.
diff --git a/include/asm-i386/local.h b/include/asm-i386/local.h
index 12060e22f7e2..e13d3e98823f 100644
--- a/include/asm-i386/local.h
+++ b/include/asm-i386/local.h
@@ -2,47 +2,198 @@
 #define _ARCH_I386_LOCAL_H
 
 #include <linux/percpu.h>
+#include <asm/system.h>
+#include <asm/atomic.h>
 
 typedef struct
 {
-        volatile long counter;
+        atomic_long_t a;
 } local_t;
 
-#define LOCAL_INIT(i)   { (i) }
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
 
-#define local_read(v)   ((v)->counter)
-#define local_set(v,i)  (((v)->counter) = (i))
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
 
-static __inline__ void local_inc(local_t *v)
+static __inline__ void local_inc(local_t *l)
 {
         __asm__ __volatile__(
                 "incl %0"
-                :"+m" (v->counter));
+                :"+m" (l->a.counter));
 }
 
-static __inline__ void local_dec(local_t *v)
+static __inline__ void local_dec(local_t *l)
 {
         __asm__ __volatile__(
                 "decl %0"
-                :"+m" (v->counter));
+                :"+m" (l->a.counter));
 }
 
-static __inline__ void local_add(long i, local_t *v)
+static __inline__ void local_add(long i, local_t *l)
 {
         __asm__ __volatile__(
                 "addl %1,%0"
-                :"+m" (v->counter)
+                :"+m" (l->a.counter)
                 :"ir" (i));
 }
 
-static __inline__ void local_sub(long i, local_t *v)
+static __inline__ void local_sub(long i, local_t *l)
 {
         __asm__ __volatile__(
                 "subl %1,%0"
-                :"+m" (v->counter)
+                :"+m" (l->a.counter)
                 :"ir" (i));
 }
 
+/**
+ * local_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @l: pointer of type local_t
+ *
+ * Atomically subtracts @i from @l and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+static __inline__ int local_sub_and_test(long i, local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "subl %2,%0; sete %1"
+                :"+m" (l->a.counter), "=qm" (c)
+                :"ir" (i) : "memory");
+        return c;
+}
+
+/**
+ * local_dec_and_test - decrement and test
+ * @l: pointer of type local_t
+ *
+ * Atomically decrements @l by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+static __inline__ int local_dec_and_test(local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "decl %0; sete %1"
+                :"+m" (l->a.counter), "=qm" (c)
+                : : "memory");
+        return c != 0;
+}
+
+/**
+ * local_inc_and_test - increment and test
+ * @l: pointer of type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+static __inline__ int local_inc_and_test(local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "incl %0; sete %1"
+                :"+m" (l->a.counter), "=qm" (c)
+                : : "memory");
+        return c != 0;
+}
+
+/**
+ * local_add_negative - add and test if negative
+ * @l: pointer of type local_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @l and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+static __inline__ int local_add_negative(long i, local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "addl %2,%0; sets %1"
+                :"+m" (l->a.counter), "=qm" (c)
+                :"ir" (i) : "memory");
+        return c;
+}
+
+/**
+ * local_add_return - add and return
+ * @l: pointer of type local_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @l and returns @i + @l
+ */
+static __inline__ long local_add_return(long i, local_t *l)
+{
+        long __i;
+#ifdef CONFIG_M386
+        unsigned long flags;
+        if(unlikely(boot_cpu_data.x86==3))
+                goto no_xadd;
+#endif
+        /* Modern 486+ processor */
+        __i = i;
+        __asm__ __volatile__(
+                "xaddl %0, %1;"
+                :"+r" (i), "+m" (l->a.counter)
+                : : "memory");
+        return i + __i;
+
+#ifdef CONFIG_M386
+no_xadd: /* Legacy 386 processor */
+        local_irq_save(flags);
+        __i = local_read(l);
+        local_set(l, i + __i);
+        local_irq_restore(flags);
+        return i + __i;
+#endif
+}
+
+static __inline__ long local_sub_return(long i, local_t *l)
+{
+        return local_add_return(-i,l);
+}
+
+#define local_inc_return(l)  (local_add_return(1,l))
+#define local_dec_return(l)  (local_sub_return(1,l))
+
+#define local_cmpxchg(l, o, n) \
+        (cmpxchg_local(&((l)->a.counter), (o), (n)))
+/* Always has a lock prefix */
+#define local_xchg(l, n) (xchg(&((l)->a.counter), (n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to l...
+ * @u: ...unless l is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+#define local_add_unless(l, a, u)                               \
+({                                                              \
+        long c, old;                                            \
+        c = local_read(l);                                      \
+        for (;;) {                                              \
+                if (unlikely(c == (u)))                         \
+                        break;                                  \
+                old = local_cmpxchg((l), c, c + (a));   \
+                if (likely(old == c))                           \
+                        break;                                  \
+                c = old;                                        \
+        }                                                       \
+        c != (u);                                               \
+})
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
 /* On x86, these are no better than the atomic variants. */
 #define __local_inc(l)          local_inc(l)
 #define __local_dec(l)          local_dec(l)
@@ -56,27 +207,27 @@ static __inline__ void local_sub(long i, local_t *v)
 
 /* Need to disable preemption for the cpu local counters otherwise we could
    still access a variable of a previous CPU in a non atomic way. */
-#define cpu_local_wrap_v(v)             \
+#define cpu_local_wrap_v(l)             \
         ({ local_t res__;               \
            preempt_disable();           \
-           res__ = (v);                 \
+           res__ = (l);                 \
            preempt_enable();            \
            res__; })
-#define cpu_local_wrap(v)               \
+#define cpu_local_wrap(l)               \
         ({ preempt_disable();           \
-           v;                           \
+           l;                           \
            preempt_enable(); })         \
 
-#define cpu_local_read(v)    cpu_local_wrap_v(local_read(&__get_cpu_var(v)))
-#define cpu_local_set(v, i)  cpu_local_wrap(local_set(&__get_cpu_var(v), (i)))
-#define cpu_local_inc(v)     cpu_local_wrap(local_inc(&__get_cpu_var(v)))
-#define cpu_local_dec(v)     cpu_local_wrap(local_dec(&__get_cpu_var(v)))
-#define cpu_local_add(i, v)  cpu_local_wrap(local_add((i), &__get_cpu_var(v)))
-#define cpu_local_sub(i, v)  cpu_local_wrap(local_sub((i), &__get_cpu_var(v)))
-
-#define __cpu_local_inc(v)      cpu_local_inc(v)
-#define __cpu_local_dec(v)      cpu_local_dec(v)
-#define __cpu_local_add(i, v)   cpu_local_add((i), (v))
-#define __cpu_local_sub(i, v)   cpu_local_sub((i), (v))
+#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
+#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
+#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
+#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
+#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
+#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
+
+#define __cpu_local_inc(l)      cpu_local_inc(l)
+#define __cpu_local_dec(l)      cpu_local_dec(l)
+#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
+#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
 
 #endif /* _ARCH_I386_LOCAL_H */
diff --git a/include/asm-i386/msr.h b/include/asm-i386/msr.h
index 9559894c7658..26861df52cc4 100644
--- a/include/asm-i386/msr.h
+++ b/include/asm-i386/msr.h
@@ -77,7 +77,7 @@ static inline unsigned long long native_read_pmc(void)
 #ifdef CONFIG_PARAVIRT
 #include <asm/paravirt.h>
 #else
-
+#include <linux/errno.h>
 /*
  * Access to machine-specific registers (available on 586 and better only)
  * Note: the rd* operations modify the parameters directly (without using
@@ -148,6 +148,8 @@ static inline void wrmsrl (unsigned long msr, unsigned long long val)
 #ifdef CONFIG_SMP
 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 #else  /*  CONFIG_SMP  */
 static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
@@ -157,6 +159,14 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
         wrmsr(msr_no, l, h);
 }
+static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+{
+        return rdmsr_safe(msr_no, l, h);
+}
+static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+{
+        return wrmsr_safe(msr_no, l, h);
+}
 #endif  /*  CONFIG_SMP  */
 #endif
 #endif
diff --git a/include/asm-i386/pgtable.h b/include/asm-i386/pgtable.h
index c6b8b944120c..edce9d51a676 100644
--- a/include/asm-i386/pgtable.h
+++ b/include/asm-i386/pgtable.h
@@ -243,8 +243,6 @@ static inline pte_t pte_mkyoung(pte_t pte)	{ (pte).pte_low |= _PAGE_ACCESSED; re
 static inline pte_t pte_mkwrite(pte_t pte)      { (pte).pte_low |= _PAGE_RW; return pte; }
 static inline pte_t pte_mkhuge(pte_t pte)       { (pte).pte_low |= _PAGE_PSE; return pte; }
 
-extern void vmalloc_sync_all(void);
-
 #ifdef CONFIG_X86_PAE
 # include <asm/pgtable-3level.h>
 #else
@@ -296,12 +294,25 @@ do {									\
         }                                                               \
 } while (0)
 
-/*
- * We don't actually have these, but we want to advertise them so that
- * we can encompass the flush here.
- */
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+#define ptep_test_and_clear_dirty(vma, addr, ptep) ({                   \
+        int ret = 0;                                                    \
+        if (pte_dirty(*ptep))                                           \
+                ret = test_and_clear_bit(_PAGE_BIT_DIRTY, &ptep->pte_low); \
+        if (ret)                                                        \
+                pte_update_defer(vma->vm_mm, addr, ptep);               \
+        ret;                                                            \
+})
+
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define ptep_test_and_clear_young(vma, addr, ptep) ({                   \
+        int ret = 0;                                                    \
+        if (pte_young(*ptep))                                           \
+                ret = test_and_clear_bit(_PAGE_BIT_ACCESSED, &ptep->pte_low); \
+        if (ret)                                                        \
+                pte_update_defer(vma->vm_mm, addr, ptep);               \
+        ret;                                                            \
+})
 
 /*
  * Rules for using ptep_establish: the pte MUST be a user pte, and
@@ -318,12 +329,9 @@ do {									\
 #define ptep_clear_flush_dirty(vma, address, ptep)                      \
 ({                                                                      \
         int __dirty;                                                    \
-        __dirty = pte_dirty(*(ptep));                                   \
-        if (__dirty) {                                                  \
-                clear_bit(_PAGE_BIT_DIRTY, &(ptep)->pte_low);           \
-                pte_update_defer((vma)->vm_mm, (address), (ptep));      \
+        __dirty = ptep_test_and_clear_dirty((vma), (address), (ptep));  \
+        if (__dirty)                                                    \
                 flush_tlb_page(vma, address);                           \
-        }                                                               \
         __dirty;                                                        \
 })
 
@@ -331,12 +339,9 @@ do {									\
 #define ptep_clear_flush_young(vma, address, ptep)                      \
 ({                                                                      \
         int __young;                                                    \
-        __young = pte_young(*(ptep));                                   \
-        if (__young) {                                                  \
-                clear_bit(_PAGE_BIT_ACCESSED, &(ptep)->pte_low);        \
-                pte_update_defer((vma)->vm_mm, (address), (ptep));      \
+        __young = ptep_test_and_clear_young((vma), (address), (ptep));  \
+        if (__young)                                                    \
                 flush_tlb_page(vma, address);                           \
-        }                                                               \
         __young;                                                        \
 })
 
@@ -537,10 +542,6 @@ static inline void paravirt_pagetable_setup_done(pgd_t *base)
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #include <asm-generic/pgtable.h>
 
 #endif /* _I386_PGTABLE_H */
diff --git a/include/asm-i386/serial.h b/include/asm-i386/serial.h
index bd67480ca109..57a4306cdf63 100644
--- a/include/asm-i386/serial.h
+++ b/include/asm-i386/serial.h
@@ -11,19 +11,3 @@
  * megabits/second; but this requires the faster clock.
  */
 #define BASE_BAUD ( 1843200 / 16 )
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-
-#define SERIAL_PORT_DFNS                        \
-        /* UART CLK   PORT IRQ     FLAGS        */                      \
-        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
-        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
-        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
-        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
diff --git a/include/asm-i386/system.h b/include/asm-i386/system.h
index c3a58c08c495..94ed3686a5f3 100644
--- a/include/asm-i386/system.h
+++ b/include/asm-i386/system.h
@@ -4,7 +4,7 @@
 #include <linux/kernel.h>
 #include <asm/segment.h>
 #include <asm/cpufeature.h>
-#include <linux/bitops.h> /* for LOCK_PREFIX */
+#include <asm/cmpxchg.h>
 
 #ifdef __KERNEL__
 
@@ -195,238 +195,6 @@ static inline unsigned long get_limit(unsigned long segment)
 
 #define nop() __asm__ __volatile__ ("nop")
 
-#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
-
-#define tas(ptr) (xchg((ptr),1))
-
-struct __xchg_dummy { unsigned long a[100]; };
-#define __xg(x) ((struct __xchg_dummy *)(x))
-
-
-#ifdef CONFIG_X86_CMPXCHG64
-
-/*
- * The semantics of XCHGCMP8B are a bit strange, this is why
- * there is a loop and the loading of %%eax and %%edx has to
- * be inside. This inlines well in most cases, the cached
- * cost is around ~38 cycles. (in the future we might want
- * to do an SIMD/3DNOW!/MMX/FPU 64-bit store here, but that
- * might have an implicit FPU-save as a cost, so it's not
- * clear which path to go.)
- *
- * cmpxchg8b must be used with the lock prefix here to allow
- * the instruction to be executed atomically, see page 3-102
- * of the instruction set reference 24319102.pdf. We need
- * the reader side to see the coherent 64bit value.
- */
-static inline void __set_64bit (unsigned long long * ptr,
-                unsigned int low, unsigned int high)
-{
-        __asm__ __volatile__ (
-                "\n1:\t"
-                "movl (%0), %%eax\n\t"
-                "movl 4(%0), %%edx\n\t"
-                "lock cmpxchg8b (%0)\n\t"
-                "jnz 1b"
-                : /* no outputs */
-                :       "D"(ptr),
-                        "b"(low),
-                        "c"(high)
-                :       "ax","dx","memory");
-}
-
-static inline void __set_64bit_constant (unsigned long long *ptr,
-                                                 unsigned long long value)
-{
-        __set_64bit(ptr,(unsigned int)(value), (unsigned int)((value)>>32ULL));
-}
-#define ll_low(x)       *(((unsigned int*)&(x))+0)
-#define ll_high(x)      *(((unsigned int*)&(x))+1)
-
-static inline void __set_64bit_var (unsigned long long *ptr,
-                         unsigned long long value)
-{
-        __set_64bit(ptr,ll_low(value), ll_high(value));
-}
-
-#define set_64bit(ptr,value) \
-(__builtin_constant_p(value) ? \
- __set_64bit_constant(ptr, value) : \
- __set_64bit_var(ptr, value) )
-
-#define _set_64bit(ptr,value) \
-(__builtin_constant_p(value) ? \
- __set_64bit(ptr, (unsigned int)(value), (unsigned int)((value)>>32ULL) ) : \
- __set_64bit(ptr, ll_low(value), ll_high(value)) )
-
-#endif
-
-/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *        but generally the primitive is invalid, *ptr is output argument. --ANK
- */
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-        switch (size) {
-                case 1:
-                        __asm__ __volatile__("xchgb %b0,%1"
-                                :"=q" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-                case 2:
-                        __asm__ __volatile__("xchgw %w0,%1"
-                                :"=r" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-                case 4:
-                        __asm__ __volatile__("xchgl %0,%1"
-                                :"=r" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-        }
-        return x;
-}
-
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-
-#ifdef CONFIG_X86_CMPXCHG
-#define __HAVE_ARCH_CMPXCHG 1
-#define cmpxchg(ptr,o,n)\
-        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
-                                        (unsigned long)(n),sizeof(*(ptr))))
-#define sync_cmpxchg(ptr,o,n)\
-        ((__typeof__(*(ptr)))__sync_cmpxchg((ptr),(unsigned long)(o),\
-                                        (unsigned long)(n),sizeof(*(ptr))))
-#endif
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-                                      unsigned long new, int size)
-{
-        unsigned long prev;
-        switch (size) {
-        case 1:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
-                                     : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 2:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 4:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        }
-        return old;
-}
-
-/*
- * Always use locked operations when touching memory shared with a
- * hypervisor, since the system may be SMP even if the guest kernel
- * isn't.
- */
-static inline unsigned long __sync_cmpxchg(volatile void *ptr,
-                                            unsigned long old,
-                                            unsigned long new, int size)
-{
-        unsigned long prev;
-        switch (size) {
-        case 1:
-                __asm__ __volatile__("lock; cmpxchgb %b1,%2"
-                                     : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 2:
-                __asm__ __volatile__("lock; cmpxchgw %w1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 4:
-                __asm__ __volatile__("lock; cmpxchgl %1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        }
-        return old;
-}
-
-#ifndef CONFIG_X86_CMPXCHG
-/*
- * Building a kernel capable running on 80386. It may be necessary to
- * simulate the cmpxchg on the 80386 CPU. For that purpose we define
- * a function for each of the sizes we support.
- */
-
-extern unsigned long cmpxchg_386_u8(volatile void *, u8, u8);
-extern unsigned long cmpxchg_386_u16(volatile void *, u16, u16);
-extern unsigned long cmpxchg_386_u32(volatile void *, u32, u32);
-
-static inline unsigned long cmpxchg_386(volatile void *ptr, unsigned long old,
-                                      unsigned long new, int size)
-{
-        switch (size) {
-        case 1:
-                return cmpxchg_386_u8(ptr, old, new);
-        case 2:
-                return cmpxchg_386_u16(ptr, old, new);
-        case 4:
-                return cmpxchg_386_u32(ptr, old, new);
-        }
-        return old;
-}
-
-#define cmpxchg(ptr,o,n)                                                \
-({                                                                      \
-        __typeof__(*(ptr)) __ret;                                       \
-        if (likely(boot_cpu_data.x86 > 3))                              \
-                __ret = __cmpxchg((ptr), (unsigned long)(o),            \
-                                        (unsigned long)(n), sizeof(*(ptr))); \
-        else                                                            \
-                __ret = cmpxchg_386((ptr), (unsigned long)(o),          \
-                                        (unsigned long)(n), sizeof(*(ptr))); \
-        __ret;                                                          \
-})
-#endif
-
-#ifdef CONFIG_X86_CMPXCHG64
-
-static inline unsigned long long __cmpxchg64(volatile void *ptr, unsigned long long old,
-                                      unsigned long long new)
-{
-        unsigned long long prev;
-        __asm__ __volatile__(LOCK_PREFIX "cmpxchg8b %3"
-                             : "=A"(prev)
-                             : "b"((unsigned long)new),
-                               "c"((unsigned long)(new >> 32)),
-                               "m"(*__xg(ptr)),
-                               "0"(old)
-                             : "memory");
-        return prev;
-}
-
-#define cmpxchg64(ptr,o,n)\
-        ((__typeof__(*(ptr)))__cmpxchg64((ptr),(unsigned long long)(o),\
-                                        (unsigned long long)(n)))
-
-#endif
-    
 /*
  * Force strict CPU ordering.
  * And yes, this is required on UP too when we're talking
diff --git a/include/asm-i386/termbits.h b/include/asm-i386/termbits.h
index 2e6237693814..a21700352e7b 100644
--- a/include/asm-i386/termbits.h
+++ b/include/asm-i386/termbits.h
@@ -17,6 +17,17 @@ struct termios {
         cc_t c_cc[NCCS];                /* control characters */
 };
 
+struct termios2 {
+        tcflag_t c_iflag;               /* input mode flags */
+        tcflag_t c_oflag;               /* output mode flags */
+        tcflag_t c_cflag;               /* control mode flags */
+        tcflag_t c_lflag;               /* local mode flags */
+        cc_t c_line;                    /* line discipline */
+        cc_t c_cc[NCCS];                /* control characters */
+        speed_t c_ispeed;               /* input speed */
+        speed_t c_ospeed;               /* output speed */
+};
+
 struct ktermios {
         tcflag_t c_iflag;               /* input mode flags */
         tcflag_t c_oflag;               /* output mode flags */
@@ -129,6 +140,7 @@ struct ktermios {
 #define HUPCL   0002000
 #define CLOCAL  0004000
 #define CBAUDEX 0010000
+#define   BOTHER  0010000
 #define    B57600 0010001
 #define   B115200 0010002
 #define   B230400 0010003
@@ -148,6 +160,8 @@ struct ktermios {
 #define CMSPAR    010000000000          /* mark or space (stick) parity */
 #define CRTSCTS   020000000000          /* flow control */
 
+#define IBSHIFT   16            /* Shift from CBAUD to CIBAUD */
+
 /* c_lflag bits */
 #define ISIG    0000001
 #define ICANON  0000002
diff --git a/include/asm-i386/termios.h b/include/asm-i386/termios.h
index 7c99678a8f86..f520b7c16fa2 100644
--- a/include/asm-i386/termios.h
+++ b/include/asm-i386/termios.h
@@ -81,8 +81,10 @@ struct termio {
         copy_to_user((termio)->c_cc, (termios)->c_cc, NCC); \
 })
 
-#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios))
-#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios))
+#define user_termios_to_kernel_termios(k, u) copy_from_user(k, u, sizeof(struct termios2))
+#define kernel_termios_to_user_termios(u, k) copy_to_user(u, k, sizeof(struct termios2))
+#define user_termios_to_kernel_termios_1(k, u) copy_from_user(k, u, sizeof(struct termios))
+#define kernel_termios_to_user_termios_1(u, k) copy_to_user(u, k, sizeof(struct termios))
 
 #endif  /* __KERNEL__ */
 
diff --git a/include/asm-i386/thread_info.h b/include/asm-i386/thread_info.h
index 4b187bb377b4..bf01d4b342bd 100644
--- a/include/asm-i386/thread_info.h
+++ b/include/asm-i386/thread_info.h
@@ -95,12 +95,14 @@ static inline struct thread_info *current_thread_info(void)
 
 /* thread information allocation */
 #ifdef CONFIG_DEBUG_STACK_USAGE
-#define alloc_thread_info(tsk) kzalloc(THREAD_SIZE, GFP_KERNEL)
+#define alloc_thread_info(tsk) ((struct thread_info *) \
+        __get_free_pages(GFP_KERNEL| __GFP_ZERO, get_order(THREAD_SIZE)))
 #else
-#define alloc_thread_info(tsk) kmalloc(THREAD_SIZE, GFP_KERNEL)
+#define alloc_thread_info(tsk) ((struct thread_info *) \
+        __get_free_pages(GFP_KERNEL, get_order(THREAD_SIZE)))
 #endif
 
-#define free_thread_info(info)  kfree(info)
+#define free_thread_info(info)  free_pages((unsigned long)(info), get_order(THREAD_SIZE))
 
 #else /* !__ASSEMBLY__ */
 
diff --git a/include/asm-i386/unistd.h b/include/asm-i386/unistd.h
index 833fa1704ff9..bd21e795197c 100644
--- a/include/asm-i386/unistd.h
+++ b/include/asm-i386/unistd.h
@@ -325,10 +325,11 @@
 #define __NR_move_pages         317
 #define __NR_getcpu             318
 #define __NR_epoll_pwait        319
+#define __NR_utimensat          320
 
 #ifdef __KERNEL__
 
-#define NR_syscalls 320
+#define NR_syscalls 321
 
 #define __ARCH_WANT_IPC_PARSE_VERSION
 #define __ARCH_WANT_OLD_READDIR
diff --git a/include/asm-ia64/asmmacro.h b/include/asm-ia64/asmmacro.h
index c22b4658fc61..c1642fd64029 100644
--- a/include/asm-ia64/asmmacro.h
+++ b/include/asm-ia64/asmmacro.h
@@ -104,6 +104,16 @@ name:
 #endif
 
 /*
+ * If physical stack register size is different from DEF_NUM_STACK_REG,
+ * dynamically patch the kernel for correct size.
+ */
+        .section ".data.patch.phys_stack_reg", "a"
+        .previous
+#define LOAD_PHYS_STACK_REG_SIZE(reg)                   \
+[1:]    adds reg=IA64_NUM_PHYS_STACK_REG*8+8,r0;        \
+        .xdata4 ".data.patch.phys_stack_reg", 1b-.
+
+/*
  * Up until early 2004, use of .align within a function caused bad unwind info.
  * TEXT_ALIGN(n) expands into ".align n" if a fixed GAS is available or into nothing
  * otherwise.
diff --git a/include/asm-ia64/atomic.h b/include/asm-ia64/atomic.h
index 569ec7574baf..1fc3b83325da 100644
--- a/include/asm-ia64/atomic.h
+++ b/include/asm-ia64/atomic.h
@@ -15,6 +15,7 @@
 #include <linux/types.h>
 
 #include <asm/intrinsics.h>
+#include <asm/system.h>
 
 /*
  * On IA-64, counter must always be volatile to ensure that that the
@@ -88,25 +89,47 @@ ia64_atomic64_sub (__s64 i, atomic64_t *v)
         return new;
 }
 
-#define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new))
+#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        for (;;) {                                              \
-                if (unlikely(c == (u)))                         \
-                        break;                                  \
-                old = atomic_cmpxchg((v), c, c + (a));          \
-                if (likely(old == c))                           \
-                        break;                                  \
-                c = old;                                        \
-        }                                                       \
-        c != (u);                                               \
-})
+#define atomic64_cmpxchg(v, old, new) \
+        (cmpxchg(&((v)->counter), old, new))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
 #define atomic_add_return(i,v)                                          \
 ({                                                                      \
         int __ia64_aar_i = (i);                                         \
diff --git a/include/asm-ia64/io.h b/include/asm-ia64/io.h
index 6311e168cd34..eb17a8692967 100644
--- a/include/asm-ia64/io.h
+++ b/include/asm-ia64/io.h
@@ -421,11 +421,7 @@ __writeq (unsigned long val, volatile void __iomem *addr)
 
 extern void __iomem * ioremap(unsigned long offset, unsigned long size);
 extern void __iomem * ioremap_nocache (unsigned long offset, unsigned long size);
-
-static inline void
-iounmap (volatile void __iomem *addr)
-{
-}
+extern void iounmap (volatile void __iomem *addr);
 
 /* Use normal IO mappings for DMI */
 #define dmi_ioremap ioremap
diff --git a/include/asm-ia64/kdebug.h b/include/asm-ia64/kdebug.h
index aed7142f9e4a..ba211e011a1d 100644
--- a/include/asm-ia64/kdebug.h
+++ b/include/asm-ia64/kdebug.h
@@ -28,21 +28,8 @@
  */
 #include <linux/notifier.h>
 
-struct pt_regs;
-
-struct die_args {
-        struct pt_regs *regs;
-        const char *str;
-        long err;
-        int trapnr;
-        int signr;
-};
-
-extern int register_die_notifier(struct notifier_block *);
-extern int unregister_die_notifier(struct notifier_block *);
 extern int register_page_fault_notifier(struct notifier_block *);
 extern int unregister_page_fault_notifier(struct notifier_block *);
-extern struct atomic_notifier_head ia64die_chain;
 
 enum die_val {
         DIE_BREAK = 1,
@@ -74,18 +61,4 @@ enum die_val {
         DIE_KDUMP_LEAVE,
 };
 
-static inline int notify_die(enum die_val val, char *str, struct pt_regs *regs,
-                             long err, int trap, int sig)
-{
-        struct die_args args = {
-                .regs   = regs,
-                .str    = str,
-                .err    = err,
-                .trapnr = trap,
-                .signr  = sig
-        };
-
-        return atomic_notifier_call_chain(&ia64die_chain, val, &args);
-}
-
 #endif
diff --git a/include/asm-ia64/kexec.h b/include/asm-ia64/kexec.h
index 41299ddfee30..541be835fc5a 100644
--- a/include/asm-ia64/kexec.h
+++ b/include/asm-ia64/kexec.h
@@ -14,8 +14,6 @@
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_IA_64
 
-#define MAX_NOTE_BYTES 1024
-
 #define kexec_flush_icache_page(page) do { \
                 unsigned long page_addr = (unsigned long)page_address(page); \
                 flush_icache_range(page_addr, page_addr + PAGE_SIZE); \
diff --git a/include/asm-ia64/kregs.h b/include/asm-ia64/kregs.h
index 221b5cb564b2..7e55a584975c 100644
--- a/include/asm-ia64/kregs.h
+++ b/include/asm-ia64/kregs.h
@@ -29,8 +29,7 @@
  */
 #define IA64_TR_KERNEL          0       /* itr0, dtr0: maps kernel image (code & data) */
 #define IA64_TR_PALCODE         1       /* itr1: maps PALcode as required by EFI */
-#define IA64_TR_PERCPU_DATA     1       /* dtr1: percpu data */
-#define IA64_TR_CURRENT_STACK   2       /* dtr2: maps kernel's memory- & register-stacks */
+#define IA64_TR_CURRENT_STACK   1       /* dtr1: maps kernel's memory- & register-stacks */
 
 /* Processor status register bits: */
 #define IA64_PSR_BE_BIT         1
diff --git a/include/asm-ia64/local.h b/include/asm-ia64/local.h
index dc519092ef4d..c11c530f74d0 100644
--- a/include/asm-ia64/local.h
+++ b/include/asm-ia64/local.h
@@ -1,50 +1 @@
-#ifndef _ASM_IA64_LOCAL_H
-#define _ASM_IA64_LOCAL_H
-
-/*
- * Copyright (C) 2003 Hewlett-Packard Co
- *      David Mosberger-Tang <davidm@hpl.hp.com>
- */
-
-#include <linux/percpu.h>
-
-typedef struct {
-        atomic64_t val;
-} local_t;
-
-#define LOCAL_INIT(i)   ((local_t) { { (i) } })
-#define local_read(l)   atomic64_read(&(l)->val)
-#define local_set(l, i) atomic64_set(&(l)->val, i)
-#define local_inc(l)    atomic64_inc(&(l)->val)
-#define local_dec(l)    atomic64_dec(&(l)->val)
-#define local_add(i, l) atomic64_add((i), &(l)->val)
-#define local_sub(i, l) atomic64_sub((i), &(l)->val)
-
-/* Non-atomic variants, i.e., preemption disabled and won't be touched in interrupt, etc.  */
-
-#define __local_inc(l)          (++(l)->val.counter)
-#define __local_dec(l)          (--(l)->val.counter)
-#define __local_add(i,l)        ((l)->val.counter += (i))
-#define __local_sub(i,l)        ((l)->val.counter -= (i))
-
-/*
- * Use these for per-cpu local_t variables.  Note they take a variable (eg. mystruct.foo),
- * not an address.
- */
-#define cpu_local_read(v)       local_read(&__ia64_per_cpu_var(v))
-#define cpu_local_set(v, i)     local_set(&__ia64_per_cpu_var(v), (i))
-#define cpu_local_inc(v)        local_inc(&__ia64_per_cpu_var(v))
-#define cpu_local_dec(v)        local_dec(&__ia64_per_cpu_var(v))
-#define cpu_local_add(i, v)     local_add((i), &__ia64_per_cpu_var(v))
-#define cpu_local_sub(i, v)     local_sub((i), &__ia64_per_cpu_var(v))
-
-/*
- * Non-atomic increments, i.e., preemption disabled and won't be touched in interrupt,
- * etc.
- */
-#define __cpu_local_inc(v)      __local_inc(&__ia64_per_cpu_var(v))
-#define __cpu_local_dec(v)      __local_dec(&__ia64_per_cpu_var(v))
-#define __cpu_local_add(i, v)   __local_add((i), &__ia64_per_cpu_var(v))
-#define __cpu_local_sub(i, v)   __local_sub((i), &__ia64_per_cpu_var(v))
-
-#endif /* _ASM_IA64_LOCAL_H */
+#include <asm-generic/local.h>
diff --git a/include/asm-ia64/pal.h b/include/asm-ia64/pal.h
index 67656ce767c2..abfcb3a2588f 100644
--- a/include/asm-ia64/pal.h
+++ b/include/asm-ia64/pal.h
@@ -89,6 +89,8 @@
 #define PAL_GET_PSTATE_TYPE_AVGNORESET  2
 #define PAL_GET_PSTATE_TYPE_INSTANT     3
 
+#define PAL_MC_ERROR_INJECT     276     /* Injects processor error or returns injection capabilities */
+
 #ifndef __ASSEMBLY__
 
 #include <linux/types.h>
@@ -1235,6 +1237,37 @@ ia64_pal_mc_error_info (u64 info_index, u64 type_index, u64 *size, u64 *error_in
         return iprv.status;
 }
 
+/* Injects the requested processor error or returns info on
+ * supported injection capabilities for current processor implementation
+ */
+static inline s64
+ia64_pal_mc_error_inject_phys (u64 err_type_info, u64 err_struct_info,
+                        u64 err_data_buffer, u64 *capabilities, u64 *resources)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_PHYS_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
+                          err_struct_info, err_data_buffer);
+        if (capabilities)
+                *capabilities= iprv.v0;
+        if (resources)
+                *resources= iprv.v1;
+        return iprv.status;
+}
+
+static inline s64
+ia64_pal_mc_error_inject_virt (u64 err_type_info, u64 err_struct_info,
+                        u64 err_data_buffer, u64 *capabilities, u64 *resources)
+{
+        struct ia64_pal_retval iprv;
+        PAL_CALL_STK(iprv, PAL_MC_ERROR_INJECT, err_type_info,
+                          err_struct_info, err_data_buffer);
+        if (capabilities)
+                *capabilities= iprv.v0;
+        if (resources)
+                *resources= iprv.v1;
+        return iprv.status;
+}
+
 /* Inform PALE_CHECK whether a machine check is expected so that PALE_CHECK willnot
  * attempt to correct any expected machine checks.
  */
diff --git a/include/asm-ia64/patch.h b/include/asm-ia64/patch.h
index 4797f3535e6d..a71543084fb4 100644
--- a/include/asm-ia64/patch.h
+++ b/include/asm-ia64/patch.h
@@ -20,6 +20,7 @@ extern void ia64_patch_imm60 (u64 insn_addr, u64 val);		/* patch "brl" w/ip-rel
 
 extern void ia64_patch_mckinley_e9 (unsigned long start, unsigned long end);
 extern void ia64_patch_vtop (unsigned long start, unsigned long end);
+extern void ia64_patch_phys_stack_reg(unsigned long val);
 extern void ia64_patch_gate (void);
 
 #endif /* _ASM_IA64_PATCH_H */
diff --git a/include/asm-ia64/pgtable.h b/include/asm-ia64/pgtable.h
index 553182747722..670b706411b8 100644
--- a/include/asm-ia64/pgtable.h
+++ b/include/asm-ia64/pgtable.h
@@ -485,10 +485,6 @@ extern void paging_init (void);
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /*
  * ZERO_PAGE is a global shared page that is always zero: used
  * for zero-mapped memory areas etc..
diff --git a/include/asm-ia64/processor.h b/include/asm-ia64/processor.h
index 4f4ee1c2db2f..db81ba406cef 100644
--- a/include/asm-ia64/processor.h
+++ b/include/asm-ia64/processor.h
@@ -19,6 +19,7 @@
 #include <asm/ptrace.h>
 #include <asm/ustack.h>
 
+#define IA64_NUM_PHYS_STACK_REG 96
 #define IA64_NUM_DBG_REGS       8
 
 #define DEFAULT_MAP_BASE        __IA64_UL_CONST(0x2000000000000000)
diff --git a/include/asm-ia64/sections.h b/include/asm-ia64/sections.h
index e9eb7f62d32b..dc42a359894f 100644
--- a/include/asm-ia64/sections.h
+++ b/include/asm-ia64/sections.h
@@ -11,6 +11,7 @@
 extern char __per_cpu_start[], __per_cpu_end[], __phys_per_cpu_start[];
 extern char __start___vtop_patchlist[], __end___vtop_patchlist[];
 extern char __start___mckinley_e9_bundles[], __end___mckinley_e9_bundles[];
+extern char __start___phys_stack_reg_patchlist[], __end___phys_stack_reg_patchlist[];
 extern char __start_gate_section[];
 extern char __start_gate_mckinley_e9_patchlist[], __end_gate_mckinley_e9_patchlist[];
 extern char __start_gate_vtop_patchlist[], __end_gate_vtop_patchlist[];
diff --git a/include/asm-m32r/atomic.h b/include/asm-m32r/atomic.h
index f5a7d7301c72..3a38ffe4a4f4 100644
--- a/include/asm-m32r/atomic.h
+++ b/include/asm-m32r/atomic.h
@@ -253,14 +253,21 @@ static __inline__ int atomic_dec_return(atomic_t *v)
  * Atomically adds @a to @v, so long as it was not @u.
  * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 static __inline__ void atomic_clear_mask(unsigned long  mask, atomic_t *addr)
diff --git a/include/asm-m32r/kdebug.h b/include/asm-m32r/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-m32r/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-m32r/pgtable.h b/include/asm-m32r/pgtable.h
index 1c15ba7ce319..8b2a2f17e695 100644
--- a/include/asm-m32r/pgtable.h
+++ b/include/asm-m32r/pgtable.h
@@ -381,10 +381,6 @@ static inline void pmd_set(pmd_t * pmdp, pte_t * ptep)
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot) \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
 #define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
 #define __HAVE_ARCH_PTEP_GET_AND_CLEAR
diff --git a/include/asm-m32r/system.h b/include/asm-m32r/system.h
index 99ee09889ff7..06cdece35865 100644
--- a/include/asm-m32r/system.h
+++ b/include/asm-m32r/system.h
@@ -122,8 +122,6 @@ static inline void local_irq_disable(void)
 #define xchg(ptr,x) \
         ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
-#define tas(ptr)        (xchg((ptr),1))
-
 #ifdef CONFIG_SMP
 extern void  __xchg_called_with_bad_pointer(void);
 #endif
diff --git a/include/asm-m68k/atomic.h b/include/asm-m68k/atomic.h
index d5eed64cb833..4915294fea63 100644
--- a/include/asm-m68k/atomic.h
+++ b/include/asm-m68k/atomic.h
@@ -2,7 +2,7 @@
 #define __ARCH_M68K_ATOMIC__
 
 
-#include <asm/system.h> /* local_irq_XXX() */
+#include <asm/system.h>
 
 /*
  * Atomic operations that C can't guarantee us.  Useful for
@@ -170,20 +170,21 @@ static inline void atomic_set_mask(unsigned long mask, unsigned long *v)
         __asm__ __volatile__("orl %1,%0" : "+m" (*v) : "id" (mask));
 }
 
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        for (;;) {                                              \
-                if (unlikely(c == (u)))                         \
-                        break;                                  \
-                old = atomic_cmpxchg((v), c, c + (a));          \
-                if (likely(old == c))                           \
-                        break;                                  \
-                c = old;                                        \
-        }                                                       \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 /* Atomic operations are already serializing */
diff --git a/include/asm-m68k/kdebug.h b/include/asm-m68k/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-m68k/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-m68k/pgtable.h b/include/asm-m68k/pgtable.h
index f3aa05377987..555b87a1f7e3 100644
--- a/include/asm-m68k/pgtable.h
+++ b/include/asm-m68k/pgtable.h
@@ -143,10 +143,6 @@ static inline void update_mmu_cache(struct vm_area_struct *vma,
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /* MMU-specific headers */
 
 #ifdef CONFIG_SUN3
diff --git a/include/asm-m68k/system.h b/include/asm-m68k/system.h
index 243dd13e6bfc..198878b53a61 100644
--- a/include/asm-m68k/system.h
+++ b/include/asm-m68k/system.h
@@ -88,7 +88,6 @@ static inline int irqs_disabled(void)
 
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
diff --git a/include/asm-m68knommu/atomic.h b/include/asm-m68knommu/atomic.h
index 6c4e4b63e454..d5632a305dae 100644
--- a/include/asm-m68knommu/atomic.h
+++ b/include/asm-m68knommu/atomic.h
@@ -1,7 +1,7 @@
 #ifndef __ARCH_M68KNOMMU_ATOMIC__
 #define __ARCH_M68KNOMMU_ATOMIC__
 
-#include <asm/system.h> /* local_irq_XXX() */
+#include <asm/system.h>
 
 /*
  * Atomic operations that C can't guarantee us.  Useful for
@@ -131,14 +131,21 @@ static inline int atomic_sub_return(int i, atomic_t * v)
 #define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 #define atomic_dec_return(v) atomic_sub_return(1,(v))
diff --git a/include/asm-m68knommu/kdebug.h b/include/asm-m68knommu/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-m68knommu/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-m68knommu/pgtable.h b/include/asm-m68knommu/pgtable.h
index 549ad231efad..9dfbbc24aa71 100644
--- a/include/asm-m68knommu/pgtable.h
+++ b/include/asm-m68knommu/pgtable.h
@@ -59,10 +59,6 @@ extern int is_in_rom(unsigned long);
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /*
  * All 32bit addresses are effectively valid for vmalloc...
  * Sort of meaningless for non-VM targets.
diff --git a/include/asm-m68knommu/system.h b/include/asm-m68knommu/system.h
index 2a814498672d..5e5ed18bb78f 100644
--- a/include/asm-m68knommu/system.h
+++ b/include/asm-m68knommu/system.h
@@ -120,7 +120,6 @@ asmlinkage void resume(void);
 #endif
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 struct __xchg_dummy { unsigned long a[100]; };
 #define __xg(x) ((volatile struct __xchg_dummy *)(x))
diff --git a/include/asm-mips/atomic.h b/include/asm-mips/atomic.h
index 1ac50b6c47ad..62daa746a9c9 100644
--- a/include/asm-mips/atomic.h
+++ b/include/asm-mips/atomic.h
@@ -18,6 +18,7 @@
 #include <asm/barrier.h>
 #include <asm/cpu-features.h>
 #include <asm/war.h>
+#include <asm/system.h>
 
 typedef struct { volatile int counter; } atomic_t;
 
@@ -306,8 +307,8 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
         return result;
 }
 
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
-#define atomic_xchg(v, new) (xchg(&((v)->counter), new))
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_xchg(v, new) (xchg(&((v)->counter), (new)))
 
 /**
  * atomic_add_unless - add unless the number is a given value
@@ -318,14 +319,20 @@ static __inline__ int atomic_sub_if_positive(int i, atomic_t * v)
  * Atomically adds @a to @v, so long as it was not @u.
  * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 #define atomic_dec_return(v) atomic_sub_return(1,(v))
@@ -681,6 +688,36 @@ static __inline__ long atomic64_sub_if_positive(long i, atomic64_t * v)
         return result;
 }
 
+#define atomic64_cmpxchg(v, o, n) \
+        (((__typeof__((v)->counter)))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), (new)))
+
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
 #define atomic64_dec_return(v) atomic64_sub_return(1,(v))
 #define atomic64_inc_return(v) atomic64_add_return(1,(v))
 
diff --git a/include/asm-mips/kdebug.h b/include/asm-mips/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-mips/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-mips/kexec.h b/include/asm-mips/kexec.h
index b25267ebcb09..cdbab43b7d3a 100644
--- a/include/asm-mips/kexec.h
+++ b/include/asm-mips/kexec.h
@@ -21,8 +21,6 @@
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_MIPS
 
-#define MAX_NOTE_BYTES 1024
-
 static inline void crash_setup_regs(struct pt_regs *newregs,
                                     struct pt_regs *oldregs)
 {
diff --git a/include/asm-mips/local.h b/include/asm-mips/local.h
index 9e2d43bae388..ed882c88e0ca 100644
--- a/include/asm-mips/local.h
+++ b/include/asm-mips/local.h
@@ -1,60 +1,288 @@
-#ifndef _ASM_LOCAL_H
-#define _ASM_LOCAL_H
+#ifndef _ARCH_MIPS_LOCAL_H
+#define _ARCH_MIPS_LOCAL_H
 
 #include <linux/percpu.h>
+#include <linux/bitops.h>
 #include <asm/atomic.h>
+#include <asm/war.h>
 
-#ifdef CONFIG_32BIT
+typedef struct
+{
+        atomic_long_t a;
+} local_t;
 
-typedef atomic_t local_t;
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
 
-#define LOCAL_INIT(i)   ATOMIC_INIT(i)
-#define local_read(v)   atomic_read(v)
-#define local_set(v,i)  atomic_set(v,i)
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
 
-#define local_inc(v)    atomic_inc(v)
-#define local_dec(v)    atomic_dec(v)
-#define local_add(i, v) atomic_add(i, v)
-#define local_sub(i, v) atomic_sub(i, v)
+#define local_add(i,l)  atomic_long_add((i),(&(l)->a))
+#define local_sub(i,l)  atomic_long_sub((i),(&(l)->a))
+#define local_inc(l)    atomic_long_inc(&(l)->a)
+#define local_dec(l)    atomic_long_dec(&(l)->a)
 
-#endif
+/*
+ * Same as above, but return the result value
+ */
+static __inline__ long local_add_return(long i, local_t * l)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_add_return      \n"
+                "       addu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_add_return      \n"
+                "       addu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                "       addu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
 
-#ifdef CONFIG_64BIT
+                local_irq_save(flags);
+                result = l->a.counter;
+                result += i;
+                l->a.counter = result;
+                local_irq_restore(flags);
+        }
 
-typedef atomic64_t local_t;
+        return result;
+}
 
-#define LOCAL_INIT(i)   ATOMIC64_INIT(i)
-#define local_read(v)   atomic64_read(v)
-#define local_set(v,i)  atomic64_set(v,i)
+static __inline__ long local_sub_return(long i, local_t * l)
+{
+        unsigned long result;
 
-#define local_inc(v)    atomic64_inc(v)
-#define local_dec(v)    atomic64_dec(v)
-#define local_add(i, v) atomic64_add(i, v)
-#define local_sub(i, v) atomic64_sub(i, v)
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
 
-#endif
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_return      \n"
+                "       subu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqzl   %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
 
-#define __local_inc(v)          ((v)->counter++)
-#define __local_dec(v)          ((v)->counter--)
-#define __local_add(i,v)        ((v)->counter+=(i))
-#define __local_sub(i,v)        ((v)->counter-=(i))
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_return      \n"
+                "       subu    %0, %1, %3                              \n"
+                        __SC    "%0, %2                                 \n"
+                "       beqz    %0, 1b                                  \n"
+                "       subu    %0, %1, %3                              \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                result = l->a.counter;
+                result -= i;
+                l->a.counter = result;
+                local_irq_restore(flags);
+        }
+
+        return result;
+}
 
 /*
- * Use these for per-cpu local_t variables: on some archs they are
+ * local_sub_if_positive - conditionally subtract integer from atomic variable
+ * @i: integer value to subtract
+ * @l: pointer of type local_t
+ *
+ * Atomically test @l and subtract @i if @l is greater or equal than @i.
+ * The function returns the old value of @l minus @i.
+ */
+static __inline__ long local_sub_if_positive(long i, local_t * l)
+{
+        unsigned long result;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_if_positive\n"
+                "       dsubu   %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                        __SC    "%0, %2                                 \n"
+                "       .set    noreorder                               \n"
+                "       beqzl   %0, 1b                                  \n"
+                "        dsubu  %0, %1, %3                              \n"
+                "       .set    reorder                                 \n"
+                "1:                                                     \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                unsigned long temp;
+
+                __asm__ __volatile__(
+                "       .set    mips3                                   \n"
+                "1:"    __LL    "%1, %2         # local_sub_if_positive\n"
+                "       dsubu   %0, %1, %3                              \n"
+                "       bltz    %0, 1f                                  \n"
+                        __SC    "%0, %2                                 \n"
+                "       .set    noreorder                               \n"
+                "       beqz    %0, 1b                                  \n"
+                "        dsubu  %0, %1, %3                              \n"
+                "       .set    reorder                                 \n"
+                "1:                                                     \n"
+                "       .set    mips0                                   \n"
+                : "=&r" (result), "=&r" (temp), "=m" (l->a.counter)
+                : "Ir" (i), "m" (l->a.counter)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                result = l->a.counter;
+                result -= i;
+                if (result >= 0)
+                        l->a.counter = result;
+                local_irq_restore(flags);
+        }
+
+        return result;
+}
+
+#define local_cmpxchg(l, o, n) \
+        ((long)cmpxchg_local(&((l)->a.counter), (o), (n)))
+#define local_xchg(l, n) (xchg_local(&((l)->a.counter),(n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to l...
+ * @u: ...unless l is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+#define local_add_unless(l, a, u)                               \
+({                                                              \
+        long c, old;                                            \
+        c = local_read(l);                                      \
+        while (c != (u) && (old = local_cmpxchg((l), c, c + (a))) != c) \
+                c = old;                                        \
+        c != (u);                                               \
+})
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
+#define local_dec_return(l) local_sub_return(1,(l))
+#define local_inc_return(l) local_add_return(1,(l))
+
+/*
+ * local_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @l: pointer of type local_t
+ *
+ * Atomically subtracts @i from @l and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_sub_and_test(i,l) (local_sub_return((i), (l)) == 0)
+
+/*
+ * local_inc_and_test - increment and test
+ * @l: pointer of type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_inc_and_test(l) (local_inc_return(l) == 0)
+
+/*
+ * local_dec_and_test - decrement by 1 and test
+ * @l: pointer of type local_t
+ *
+ * Atomically decrements @l by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+#define local_dec_and_test(l) (local_sub_return(1, (l)) == 0)
+
+/*
+ * local_dec_if_positive - decrement by 1 if old value positive
+ * @l: pointer of type local_t
+ */
+#define local_dec_if_positive(l)        local_sub_if_positive(1, l)
+
+/*
+ * local_add_negative - add and test if negative
+ * @l: pointer of type local_t
+ * @i: integer value to add
+ *
+ * Atomically adds @i to @l and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+#define local_add_negative(i,l) (local_add_return(i, (l)) < 0)
+
+/* Use these for per-cpu local_t variables: on some archs they are
  * much more efficient than these naive implementations.  Note they take
  * a variable, not an address.
  */
-#define cpu_local_read(v)       local_read(&__get_cpu_var(v))
-#define cpu_local_set(v, i)     local_set(&__get_cpu_var(v), (i))
 
-#define cpu_local_inc(v)        local_inc(&__get_cpu_var(v))
-#define cpu_local_dec(v)        local_dec(&__get_cpu_var(v))
-#define cpu_local_add(i, v)     local_add((i), &__get_cpu_var(v))
-#define cpu_local_sub(i, v)     local_sub((i), &__get_cpu_var(v))
+#define __local_inc(l)          ((l)->a.counter++)
+#define __local_dec(l)          ((l)->a.counter++)
+#define __local_add(i,l)        ((l)->a.counter+=(i))
+#define __local_sub(i,l)        ((l)->a.counter-=(i))
+
+/* Need to disable preemption for the cpu local counters otherwise we could
+   still access a variable of a previous CPU in a non atomic way. */
+#define cpu_local_wrap_v(l)             \
+        ({ local_t res__;               \
+           preempt_disable();           \
+           res__ = (l);                 \
+           preempt_enable();            \
+           res__; })
+#define cpu_local_wrap(l)               \
+        ({ preempt_disable();           \
+           l;                           \
+           preempt_enable(); })         \
+
+#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
+#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
+#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
+#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
+#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
+#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
 
-#define __cpu_local_inc(v)      __local_inc(&__get_cpu_var(v))
-#define __cpu_local_dec(v)      __local_dec(&__get_cpu_var(v))
-#define __cpu_local_add(i, v)   __local_add((i), &__get_cpu_var(v))
-#define __cpu_local_sub(i, v)   __local_sub((i), &__get_cpu_var(v))
+#define __cpu_local_inc(l)      cpu_local_inc(l)
+#define __cpu_local_dec(l)      cpu_local_dec(l)
+#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
+#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
 
-#endif /* _ASM_LOCAL_H */
+#endif /* _ARCH_MIPS_LOCAL_H */
diff --git a/include/asm-mips/mach-au1x00/au1550_spi.h b/include/asm-mips/mach-au1x00/au1550_spi.h
new file mode 100644
index 000000000000..c2f0466523ec
--- /dev/null
+++ b/include/asm-mips/mach-au1x00/au1550_spi.h
@@ -0,0 +1,16 @@
+/*
+ * au1550_spi.h - au1550 psc spi controller driver - platform data struct
+ */
+
+#ifndef _AU1550_SPI_H_
+#define _AU1550_SPI_H_
+
+struct au1550_spi_info {
+        s16 bus_num;            /* defines which PSC and IRQ to use */
+        u32 mainclk_hz;         /* main input clock frequency of PSC */
+        u16 num_chipselect;     /* number of chipselects supported */
+        void (*activate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
+        void (*deactivate_cs)(struct au1550_spi_info *spi, int cs, int polarity);
+};
+
+#endif
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 0d3295f57a95..27d77d981937 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -387,10 +387,6 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 #endif
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #include <asm-generic/pgtable.h>
 
 /*
diff --git a/include/asm-mips/system.h b/include/asm-mips/system.h
index 290887077e44..30f23a2b46ca 100644
--- a/include/asm-mips/system.h
+++ b/include/asm-mips/system.h
@@ -201,7 +201,6 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 }
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 #define __HAVE_ARCH_CMPXCHG 1
 
@@ -262,6 +261,58 @@ static inline unsigned long __cmpxchg_u32(volatile int * m, unsigned long old,
         return retval;
 }
 
+static inline unsigned long __cmpxchg_u32_local(volatile int * m,
+        unsigned long old, unsigned long new)
+{
+        __u32 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       .set    mips0                                   \n"
+                "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "       sc      $1, %1                                  \n"
+                "       beqzl   $1, 1b                                  \n"
+                "2:                                                     \n"
+                "       .set    pop                                     \n"
+                : "=&r" (retval), "=R" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
+                "1:     ll      %0, %2                  # __cmpxchg_u32 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       .set    mips0                                   \n"
+                "       move    $1, %z4                                 \n"
+                "       .set    mips3                                   \n"
+                "       sc      $1, %1                                  \n"
+                "       beqz    $1, 1b                                  \n"
+                "2:                                                     \n"
+                "       .set    pop                                     \n"
+                : "=&r" (retval), "=R" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                retval = *m;
+                if (retval == old)
+                        *m = new;
+                local_irq_restore(flags);       /* implies memory barrier  */
+        }
+
+        return retval;
+}
+
 #ifdef CONFIG_64BIT
 static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
         unsigned long new)
@@ -315,10 +366,62 @@ static inline unsigned long __cmpxchg_u64(volatile int * m, unsigned long old,
 
         return retval;
 }
+
+static inline unsigned long __cmpxchg_u64_local(volatile int * m,
+        unsigned long old, unsigned long new)
+{
+        __u64 retval;
+
+        if (cpu_has_llsc && R10000_LLSC_WAR) {
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       move    $1, %z4                                 \n"
+                "       scd     $1, %1                                  \n"
+                "       beqzl   $1, 1b                                  \n"
+                "2:                                                     \n"
+                "       .set    pop                                     \n"
+                : "=&r" (retval), "=R" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else if (cpu_has_llsc) {
+                __asm__ __volatile__(
+                "       .set    push                                    \n"
+                "       .set    noat                                    \n"
+                "       .set    mips3                                   \n"
+                "1:     lld     %0, %2                  # __cmpxchg_u64 \n"
+                "       bne     %0, %z3, 2f                             \n"
+                "       move    $1, %z4                                 \n"
+                "       scd     $1, %1                                  \n"
+                "       beqz    $1, 1b                                  \n"
+                "2:                                                     \n"
+                "       .set    pop                                     \n"
+                : "=&r" (retval), "=R" (*m)
+                : "R" (*m), "Jr" (old), "Jr" (new)
+                : "memory");
+        } else {
+                unsigned long flags;
+
+                local_irq_save(flags);
+                retval = *m;
+                if (retval == old)
+                        *m = new;
+                local_irq_restore(flags);       /* implies memory barrier  */
+        }
+
+        return retval;
+}
+
 #else
 extern unsigned long __cmpxchg_u64_unsupported_on_32bit_kernels(
         volatile int * m, unsigned long old, unsigned long new);
 #define __cmpxchg_u64 __cmpxchg_u64_unsupported_on_32bit_kernels
+extern unsigned long __cmpxchg_u64_local_unsupported_on_32bit_kernels(
+        volatile int * m, unsigned long old, unsigned long new);
+#define __cmpxchg_u64_local __cmpxchg_u64_local_unsupported_on_32bit_kernels
 #endif
 
 /* This function doesn't exist, so you'll get a linker error
@@ -338,7 +441,26 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
         return old;
 }
 
-#define cmpxchg(ptr,old,new) ((__typeof__(*(ptr)))__cmpxchg((ptr), (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
+static inline unsigned long __cmpxchg_local(volatile void * ptr,
+        unsigned long old, unsigned long new, int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32_local(ptr, old, new);
+        case 8:
+                return __cmpxchg_u64_local(ptr, old, new);
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
+#define cmpxchg(ptr,old,new) \
+        ((__typeof__(*(ptr)))__cmpxchg((ptr), \
+                (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
+
+#define cmpxchg_local(ptr,old,new) \
+        ((__typeof__(*(ptr)))__cmpxchg_local((ptr), \
+                (unsigned long)(old), (unsigned long)(new),sizeof(*(ptr))))
 
 extern void set_handler (unsigned long offset, void *addr, unsigned long len);
 extern void set_uncached_handler (unsigned long offset, void *addr, unsigned long len);
diff --git a/include/asm-parisc/atomic.h b/include/asm-parisc/atomic.h
index 7d57d34fcca8..e894ee35074b 100644
--- a/include/asm-parisc/atomic.h
+++ b/include/asm-parisc/atomic.h
@@ -163,7 +163,7 @@ static __inline__ int atomic_read(const atomic_t *v)
 }
 
 /* exported interface */
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
 /**
@@ -175,14 +175,21 @@ static __inline__ int atomic_read(const atomic_t *v)
  * Atomically adds @a to @v, so long as it was not @u.
  * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 #define atomic_add(i,v) ((void)(__atomic_add_return( ((int)i),(v))))
@@ -270,6 +277,37 @@ atomic64_read(const atomic64_t *v)
 #define atomic64_dec_and_test(v)        (atomic64_dec_return(v) == 0)
 #define atomic64_sub_and_test(i,v)      (atomic64_sub_return((i),(v)) == 0)
 
+/* exported interface */
+#define atomic64_cmpxchg(v, o, n) \
+        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
 #endif /* CONFIG_64BIT */
 
 #include <asm-generic/atomic.h>
diff --git a/include/asm-parisc/kdebug.h b/include/asm-parisc/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-parisc/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-parisc/local.h b/include/asm-parisc/local.h
index d0f550912755..c11c530f74d0 100644
--- a/include/asm-parisc/local.h
+++ b/include/asm-parisc/local.h
@@ -1,40 +1 @@
-#ifndef _ARCH_PARISC_LOCAL_H
-#define _ARCH_PARISC_LOCAL_H
-
-#include <linux/percpu.h>
-#include <asm/atomic.h>
-
-typedef atomic_long_t local_t;
-
-#define LOCAL_INIT(i)   ATOMIC_LONG_INIT(i)
-#define local_read(v)   atomic_long_read(v)
-#define local_set(v,i)  atomic_long_set(v,i)
-
-#define local_inc(v)    atomic_long_inc(v)
-#define local_dec(v)    atomic_long_dec(v)
-#define local_add(i, v) atomic_long_add(i, v)
-#define local_sub(i, v) atomic_long_sub(i, v)
-
-#define __local_inc(v)          ((v)->counter++)
-#define __local_dec(v)          ((v)->counter--)
-#define __local_add(i,v)        ((v)->counter+=(i))
-#define __local_sub(i,v)        ((v)->counter-=(i))
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations.  Note they take
- * a variable, not an address.
- */
-#define cpu_local_read(v)       local_read(&__get_cpu_var(v))
-#define cpu_local_set(v, i)     local_set(&__get_cpu_var(v), (i))
-
-#define cpu_local_inc(v)        local_inc(&__get_cpu_var(v))
-#define cpu_local_dec(v)        local_dec(&__get_cpu_var(v))
-#define cpu_local_add(i, v)     local_add((i), &__get_cpu_var(v))
-#define cpu_local_sub(i, v)     local_sub((i), &__get_cpu_var(v))
-
-#define __cpu_local_inc(v)      __local_inc(&__get_cpu_var(v))
-#define __cpu_local_dec(v)      __local_dec(&__get_cpu_var(v))
-#define __cpu_local_add(i, v)   __local_add((i), &__get_cpu_var(v))
-#define __cpu_local_sub(i, v)   __local_sub((i), &__get_cpu_var(v))
-
-#endif /* _ARCH_PARISC_LOCAL_H */
+#include <asm-generic/local.h>
diff --git a/include/asm-parisc/pgtable.h b/include/asm-parisc/pgtable.h
index d7e1b10da5c6..beb2adb979d9 100644
--- a/include/asm-parisc/pgtable.h
+++ b/include/asm-parisc/pgtable.h
@@ -528,10 +528,6 @@ static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
 
 #define pgprot_noncached(prot) __pgprot(pgprot_val(prot) | _PAGE_NO_CACHE)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /* We provide our own get_unmapped_area to provide cache coherency */
 
 #define HAVE_ARCH_UNMAPPED_AREA
diff --git a/include/asm-powerpc/atomic.h b/include/asm-powerpc/atomic.h
index 2ce4b6b7b348..c44810b9d322 100644
--- a/include/asm-powerpc/atomic.h
+++ b/include/asm-powerpc/atomic.h
@@ -11,6 +11,7 @@ typedef struct { volatile int counter; } atomic_t;
 #include <linux/compiler.h>
 #include <asm/synch.h>
 #include <asm/asm-compat.h>
+#include <asm/system.h>
 
 #define ATOMIC_INIT(i)          { (i) }
 
@@ -165,8 +166,7 @@ static __inline__ int atomic_dec_return(atomic_t *v)
         return t;
 }
 
-#define atomic_cmpxchg(v, o, n) \
-        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
 /**
@@ -414,8 +414,7 @@ static __inline__ long atomic64_dec_if_positive(atomic64_t *v)
         return t;
 }
 
-#define atomic64_cmpxchg(v, o, n) \
-        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
 #define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
 
 /**
diff --git a/include/asm-powerpc/bitops.h b/include/asm-powerpc/bitops.h
index 8f757f6246e4..8144a2788db6 100644
--- a/include/asm-powerpc/bitops.h
+++ b/include/asm-powerpc/bitops.h
@@ -39,7 +39,6 @@
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
-#include <asm/atomic.h>
 #include <asm/asm-compat.h>
 #include <asm/synch.h>
 
diff --git a/include/asm-powerpc/iommu.h b/include/asm-powerpc/iommu.h
index b2e56b30306a..870967e47204 100644
--- a/include/asm-powerpc/iommu.h
+++ b/include/asm-powerpc/iommu.h
@@ -26,6 +26,7 @@
 #include <linux/spinlock.h>
 #include <linux/device.h>
 #include <linux/dma-mapping.h>
+#include <asm/machdep.h>
 #include <asm/types.h>
 #include <asm/bitops.h>
 
@@ -109,6 +110,19 @@ static inline void pci_iommu_init(void) { }
 #endif
 
 extern void alloc_dart_table(void);
+#if defined(CONFIG_PPC64) && defined(CONFIG_PM)
+static inline void iommu_save(void)
+{
+        if (ppc_md.iommu_save)
+                ppc_md.iommu_save();
+}
+
+static inline void iommu_restore(void)
+{
+        if (ppc_md.iommu_restore)
+                ppc_md.iommu_restore();
+}
+#endif
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_IOMMU_H */
diff --git a/include/asm-powerpc/kdebug.h b/include/asm-powerpc/kdebug.h
index 532bfee934f4..295f0162c608 100644
--- a/include/asm-powerpc/kdebug.h
+++ b/include/asm-powerpc/kdebug.h
@@ -6,20 +6,19 @@
 
 #include <linux/notifier.h>
 
-struct pt_regs;
-
-struct die_args {
-        struct pt_regs *regs;
-        const char *str;
-        long err;
-        int trapnr;
-        int signr;
-};
-
-extern int register_die_notifier(struct notifier_block *);
-extern int unregister_die_notifier(struct notifier_block *);
-extern int register_page_fault_notifier(struct notifier_block *);
-extern int unregister_page_fault_notifier(struct notifier_block *);
+/*
+ * These are only here because kprobes.c wants them to implement a
+ * blatant layering violation.  Will hopefully go away soon once all
+ * architectures are updated.
+ */
+static inline int register_page_fault_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
+static inline int unregister_page_fault_notifier(struct notifier_block *nb)
+{
+        return 0;
+}
 extern struct atomic_notifier_head powerpc_die_chain;
 
 /* Grossly misnamed. */
@@ -29,14 +28,7 @@ enum die_val {
         DIE_DABR_MATCH,
         DIE_BPT,
         DIE_SSTEP,
-        DIE_PAGE_FAULT,
 };
 
-static inline int notify_die(enum die_val val,char *str,struct pt_regs *regs,long err,int trap, int sig)
-{
-        struct die_args args = { .regs=regs, .str=str, .err=err, .trapnr=trap,.signr=sig };
-        return atomic_notifier_call_chain(&powerpc_die_chain, val, &args);
-}
-
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_KDEBUG_H */
diff --git a/include/asm-powerpc/kexec.h b/include/asm-powerpc/kexec.h
index 11cbdf81fd2e..b6f817b8ba3d 100644
--- a/include/asm-powerpc/kexec.h
+++ b/include/asm-powerpc/kexec.h
@@ -108,8 +108,6 @@ static inline void crash_setup_regs(struct pt_regs *newregs,
                                         struct pt_regs *oldregs) { }
 #endif /* !__powerpc64 __ */
 
-#define MAX_NOTE_BYTES 1024
-
 extern void kexec_smp_wait(void);       /* get and clear naca physid, wait for
                                           master to copy new code to 0 */
 extern int crashing_cpu;
diff --git a/include/asm-powerpc/kprobes.h b/include/asm-powerpc/kprobes.h
index f850ca7020ed..b0e40ff32ee0 100644
--- a/include/asm-powerpc/kprobes.h
+++ b/include/asm-powerpc/kprobes.h
@@ -64,6 +64,12 @@ typedef unsigned int kprobe_opcode_t;
                                 addr = *(kprobe_opcode_t **)addr;       \
                 } else if (name[0] != '.')                              \
                         addr = *(kprobe_opcode_t **)addr;               \
+        } else {                                                        \
+                char dot_name[KSYM_NAME_LEN+1];                         \
+                dot_name[0] = '.';                                      \
+                dot_name[1] = '\0';                                     \
+                strncat(dot_name, name, KSYM_NAME_LEN);                 \
+                addr = (kprobe_opcode_t *)kallsyms_lookup_name(dot_name); \
         }                                                               \
 }
 
@@ -110,5 +116,6 @@ struct kprobe_ctlblk {
 
 extern int kprobe_exceptions_notify(struct notifier_block *self,
                                         unsigned long val, void *data);
+extern int kprobe_fault_handler(struct pt_regs *regs, int trapnr);
 #endif /* __KERNEL__ */
 #endif  /* _ASM_POWERPC_KPROBES_H */
diff --git a/include/asm-powerpc/local.h b/include/asm-powerpc/local.h
index c11c530f74d0..612d83276653 100644
--- a/include/asm-powerpc/local.h
+++ b/include/asm-powerpc/local.h
@@ -1 +1,200 @@
-#include <asm-generic/local.h>
+#ifndef _ARCH_POWERPC_LOCAL_H
+#define _ARCH_POWERPC_LOCAL_H
+
+#include <linux/percpu.h>
+#include <asm/atomic.h>
+
+typedef struct
+{
+        atomic_long_t a;
+} local_t;
+
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
+
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
+
+#define local_add(i,l)  atomic_long_add((i),(&(l)->a))
+#define local_sub(i,l)  atomic_long_sub((i),(&(l)->a))
+#define local_inc(l)    atomic_long_inc(&(l)->a)
+#define local_dec(l)    atomic_long_dec(&(l)->a)
+
+static __inline__ long local_add_return(long a, local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%2                # local_add_return\n\
+        add     %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+        PPC_STLCX       "%0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (a), "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+#define local_add_negative(a, l)        (local_add_return((a), (l)) < 0)
+
+static __inline__ long local_sub_return(long a, local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%2                # local_sub_return\n\
+        subf    %0,%1,%0\n"
+        PPC405_ERR77(0,%2)
+        PPC_STLCX       "%0,0,%2 \n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (a), "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+static __inline__ long local_inc_return(local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%1                # local_inc_return\n\
+        addic   %0,%0,1\n"
+        PPC405_ERR77(0,%1)
+        PPC_STLCX       "%0,0,%1 \n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+/*
+ * local_inc_and_test - increment and test
+ * @l: pointer of type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+#define local_inc_and_test(l) (local_inc_return(l) == 0)
+
+static __inline__ long local_dec_return(local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%1                # local_dec_return\n\
+        addic   %0,%0,-1\n"
+        PPC405_ERR77(0,%1)
+        PPC_STLCX       "%0,0,%1\n\
+        bne-    1b"
+        : "=&r" (t)
+        : "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+#define local_cmpxchg(l, o, n) \
+        (cmpxchg_local(&((l)->a.counter), (o), (n)))
+#define local_xchg(l, n) (xchg_local(&((l)->a.counter), (n)))
+
+/**
+ * local_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+static __inline__ int local_add_unless(local_t *l, long a, long u)
+{
+        long t;
+
+        __asm__ __volatile__ (
+"1:"    PPC_LLARX       "%0,0,%1                # local_add_unless\n\
+        cmpw    0,%0,%3 \n\
+        beq-    2f \n\
+        add     %0,%2,%0 \n"
+        PPC405_ERR77(0,%2)
+        PPC_STLCX       "%0,0,%1 \n\
+        bne-    1b \n"
+"       subf    %0,%2,%0 \n\
+2:"
+        : "=&r" (t)
+        : "r" (&(l->a.counter)), "r" (a), "r" (u)
+        : "cc", "memory");
+
+        return t != u;
+}
+
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
+#define local_sub_and_test(a, l)        (local_sub_return((a), (l)) == 0)
+#define local_dec_and_test(l)           (local_dec_return((l)) == 0)
+
+/*
+ * Atomically test *l and decrement if it is greater than 0.
+ * The function returns the old value of *l minus 1.
+ */
+static __inline__ long local_dec_if_positive(local_t *l)
+{
+        long t;
+
+        __asm__ __volatile__(
+"1:"    PPC_LLARX       "%0,0,%1                # local_dec_if_positive\n\
+        cmpwi   %0,1\n\
+        addi    %0,%0,-1\n\
+        blt-    2f\n"
+        PPC405_ERR77(0,%1)
+        PPC_STLCX       "%0,0,%1\n\
+        bne-    1b"
+        "\n\
+2:"     : "=&b" (t)
+        : "r" (&(l->a.counter))
+        : "cc", "memory");
+
+        return t;
+}
+
+/* Use these for per-cpu local_t variables: on some archs they are
+ * much more efficient than these naive implementations.  Note they take
+ * a variable, not an address.
+ */
+
+#define __local_inc(l)          ((l)->a.counter++)
+#define __local_dec(l)          ((l)->a.counter++)
+#define __local_add(i,l)        ((l)->a.counter+=(i))
+#define __local_sub(i,l)        ((l)->a.counter-=(i))
+
+/* Need to disable preemption for the cpu local counters otherwise we could
+   still access a variable of a previous CPU in a non atomic way. */
+#define cpu_local_wrap_v(l)             \
+        ({ local_t res__;               \
+           preempt_disable();           \
+           res__ = (l);                 \
+           preempt_enable();            \
+           res__; })
+#define cpu_local_wrap(l)               \
+        ({ preempt_disable();           \
+           l;                           \
+           preempt_enable(); })         \
+
+#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
+#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
+#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
+#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
+#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
+#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
+
+#define __cpu_local_inc(l)      cpu_local_inc(l)
+#define __cpu_local_dec(l)      cpu_local_dec(l)
+#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
+#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
+
+#endif /* _ARCH_POWERPC_LOCAL_H */
diff --git a/include/asm-powerpc/machdep.h b/include/asm-powerpc/machdep.h
index b204926ce913..6cf1a831f550 100644
--- a/include/asm-powerpc/machdep.h
+++ b/include/asm-powerpc/machdep.h
@@ -91,6 +91,11 @@ struct machdep_calls {
         void __iomem *  (*ioremap)(phys_addr_t addr, unsigned long size,
                                    unsigned long flags);
         void            (*iounmap)(volatile void __iomem *token);
+
+#ifdef CONFIG_PM
+        void            (*iommu_save)(void);
+        void            (*iommu_restore)(void);
+#endif
 #endif /* CONFIG_PPC64 */
 
         int             (*probe)(void);
@@ -115,6 +120,14 @@ struct machdep_calls {
         /* To setup PHBs when using automatic OF platform driver for PCI */
         int             (*pci_setup_phb)(struct pci_controller *host);
 
+#ifdef CONFIG_PCI_MSI
+        int             (*msi_check_device)(struct pci_dev* dev,
+                                            int nvec, int type);
+        int             (*setup_msi_irqs)(struct pci_dev *dev,
+                                          int nvec, int type);
+        void            (*teardown_msi_irqs)(struct pci_dev *dev);
+#endif
+
         void            (*restart)(char *cmd);
         void            (*power_off)(void);
         void            (*halt)(void);
@@ -240,14 +253,10 @@ struct machdep_calls {
          */
         void (*machine_kexec)(struct kimage *image);
 #endif /* CONFIG_KEXEC */
-
-#ifdef CONFIG_PCI_MSI
-        int (*enable_msi)(struct pci_dev *pdev);
-        void (*disable_msi)(struct pci_dev *pdev);
-#endif /* CONFIG_PCI_MSI */
 };
 
 extern void power4_idle(void);
+extern void power4_cpu_offline_powersave(void);
 extern void ppc6xx_idle(void);
 
 /*
diff --git a/include/asm-powerpc/mmu-44x.h b/include/asm-powerpc/mmu-44x.h
new file mode 100644
index 000000000000..d5ce7a8dfe9f
--- /dev/null
+++ b/include/asm-powerpc/mmu-44x.h
@@ -0,0 +1,78 @@
+#ifndef _ASM_POWERPC_MMU_44X_H_
+#define _ASM_POWERPC_MMU_44X_H_
+/*
+ * PPC440 support
+ */
+
+#define PPC44x_MMUCR_TID        0x000000ff
+#define PPC44x_MMUCR_STS        0x00010000
+
+#define PPC44x_TLB_PAGEID       0
+#define PPC44x_TLB_XLAT         1
+#define PPC44x_TLB_ATTRIB       2
+
+/* Page identification fields */
+#define PPC44x_TLB_EPN_MASK     0xfffffc00      /* Effective Page Number */
+#define PPC44x_TLB_VALID        0x00000200      /* Valid flag */
+#define PPC44x_TLB_TS           0x00000100      /* Translation address space */
+#define PPC44x_TLB_1K           0x00000000      /* Page sizes */
+#define PPC44x_TLB_4K           0x00000010
+#define PPC44x_TLB_16K          0x00000020
+#define PPC44x_TLB_64K          0x00000030
+#define PPC44x_TLB_256K         0x00000040
+#define PPC44x_TLB_1M           0x00000050
+#define PPC44x_TLB_16M          0x00000070
+#define PPC44x_TLB_256M         0x00000090
+
+/* Translation fields */
+#define PPC44x_TLB_RPN_MASK     0xfffffc00      /* Real Page Number */
+#define PPC44x_TLB_ERPN_MASK    0x0000000f
+
+/* Storage attribute and access control fields */
+#define PPC44x_TLB_ATTR_MASK    0x0000ff80
+#define PPC44x_TLB_U0           0x00008000      /* User 0 */
+#define PPC44x_TLB_U1           0x00004000      /* User 1 */
+#define PPC44x_TLB_U2           0x00002000      /* User 2 */
+#define PPC44x_TLB_U3           0x00001000      /* User 3 */
+#define PPC44x_TLB_W            0x00000800      /* Caching is write-through */
+#define PPC44x_TLB_I            0x00000400      /* Caching is inhibited */
+#define PPC44x_TLB_M            0x00000200      /* Memory is coherent */
+#define PPC44x_TLB_G            0x00000100      /* Memory is guarded */
+#define PPC44x_TLB_E            0x00000080      /* Memory is guarded */
+
+#define PPC44x_TLB_PERM_MASK    0x0000003f
+#define PPC44x_TLB_UX           0x00000020      /* User execution */
+#define PPC44x_TLB_UW           0x00000010      /* User write */
+#define PPC44x_TLB_UR           0x00000008      /* User read */
+#define PPC44x_TLB_SX           0x00000004      /* Super execution */
+#define PPC44x_TLB_SW           0x00000002      /* Super write */
+#define PPC44x_TLB_SR           0x00000001      /* Super read */
+
+/* Number of TLB entries */
+#define PPC44x_TLB_SIZE         64
+
+#ifndef __ASSEMBLY__
+
+typedef unsigned long long phys_addr_t;
+
+extern phys_addr_t fixup_bigphys_addr(phys_addr_t, phys_addr_t);
+
+typedef struct {
+        unsigned long id;
+        unsigned long vdso_base;
+} mm_context_t;
+
+#endif /* !__ASSEMBLY__ */
+
+#ifndef CONFIG_PPC_EARLY_DEBUG_44x
+#define PPC44x_EARLY_TLBS       1
+#else
+#define PPC44x_EARLY_TLBS       2
+#define PPC44x_EARLY_DEBUG_VIRTADDR     (ASM_CONST(0xf0000000) \
+        | (ASM_CONST(CONFIG_PPC_EARLY_DEBUG_44x_PHYSLOW) & 0xffff))
+#endif
+
+/* Size of the TLBs used for pinning in lowmem */
+#define PPC_PIN_SIZE    (1 << 28)       /* 256M */
+
+#endif /* _ASM_POWERPC_MMU_44X_H_ */
diff --git a/include/asm-powerpc/mmu.h b/include/asm-powerpc/mmu.h
index 06b3e6d336cb..fe510fff8907 100644
--- a/include/asm-powerpc/mmu.h
+++ b/include/asm-powerpc/mmu.h
@@ -5,9 +5,12 @@
 #ifdef CONFIG_PPC64
 /* 64-bit classic hash table MMU */
 #  include <asm/mmu-hash64.h>
+#elif defined(CONFIG_44x)
+/* 44x-style software loaded TLB */
+#  include <asm/mmu-44x.h>
 #else
-/* 32-bit.  FIXME: split up the 32-bit MMU types, and revise for
- * arch/powerpc */
+/* Other 32-bit.  FIXME: split up the other 32-bit MMU types, and
+ * revise for arch/powerpc */
 #  include <asm-ppc/mmu.h>
 #endif
 
diff --git a/include/asm-powerpc/mpc52xx.h b/include/asm-powerpc/mpc52xx.h
index 7afd5bf94528..c4631f6dd4f9 100644
--- a/include/asm-powerpc/mpc52xx.h
+++ b/include/asm-powerpc/mpc52xx.h
@@ -253,5 +253,16 @@ extern int __init mpc52xx_add_bridge(struct device_node *node);
 
 #endif /* __ASSEMBLY__ */
 
+#ifdef CONFIG_PM
+struct mpc52xx_suspend {
+        void (*board_suspend_prepare)(void __iomem *mbar);
+        void (*board_resume_finish)(void __iomem *mbar);
+};
+
+extern struct mpc52xx_suspend mpc52xx_suspend;
+extern int __init mpc52xx_pm_init(void);
+extern int mpc52xx_set_wakeup_gpio(u8 pin, u8 level);
+#endif /* CONFIG_PM */
+
 #endif /* __ASM_POWERPC_MPC52xx_H__ */
 
diff --git a/include/asm-powerpc/mpic.h b/include/asm-powerpc/mpic.h
index e4d5fc5362a0..2ffb06abe881 100644
--- a/include/asm-powerpc/mpic.h
+++ b/include/asm-powerpc/mpic.h
@@ -3,6 +3,7 @@
 #ifdef __KERNEL__
 
 #include <linux/irq.h>
+#include <linux/sysdev.h>
 #include <asm/dcr.h>
 
 /*
@@ -228,6 +229,14 @@ struct mpic_reg_bank {
 #endif /* CONFIG_PPC_DCR */
 };
 
+struct mpic_irq_save {
+        u32             vecprio,
+                        dest;
+#ifdef CONFIG_MPIC_U3_HT_IRQS
+        u32             fixup_data;
+#endif
+};
+
 /* The instance data of a given MPIC */
 struct mpic
 {
@@ -292,8 +301,19 @@ struct mpic
         u32                     *hw_set;
 #endif
 
+#ifdef CONFIG_PCI_MSI
+        spinlock_t              bitmap_lock;
+        unsigned long           *hwirq_bitmap;
+#endif
+
         /* link */
         struct mpic             *next;
+
+        struct sys_device       sysdev;
+
+#ifdef CONFIG_PM
+        struct mpic_irq_save    *save_data;
+#endif
 };
 
 /*
diff --git a/include/asm-powerpc/of_device.h b/include/asm-powerpc/of_device.h
index 4f1aabe0ce73..e9af49eb1aa8 100644
--- a/include/asm-powerpc/of_device.h
+++ b/include/asm-powerpc/of_device.h
@@ -32,6 +32,8 @@ extern int of_device_register(struct of_device *ofdev);
 extern void of_device_unregister(struct of_device *ofdev);
 extern void of_release_dev(struct device *dev);
 
+extern ssize_t of_device_get_modalias(struct of_device *ofdev,
+                                        char *str, ssize_t len);
 extern int of_device_uevent(struct device *dev,
         char **envp, int num_envp, char *buffer, int buffer_size);
 
diff --git a/include/asm-powerpc/page.h b/include/asm-powerpc/page.h
index b4d38b0b15f8..10c51f457d48 100644
--- a/include/asm-powerpc/page.h
+++ b/include/asm-powerpc/page.h
@@ -121,6 +121,7 @@ typedef struct { pte_t pte; } real_pte_t;
 #endif
 
 /* PMD level */
+#ifdef CONFIG_PPC64
 typedef struct { unsigned long pmd; } pmd_t;
 #define pmd_val(x)      ((x).pmd)
 #define __pmd(x)        ((pmd_t) { (x) })
@@ -130,7 +131,8 @@ typedef struct { unsigned long pmd; } pmd_t;
 typedef struct { unsigned long pud; } pud_t;
 #define pud_val(x)      ((x).pud)
 #define __pud(x)        ((pud_t) { (x) })
-#endif
+#endif /* !CONFIG_PPC_64K_PAGES */
+#endif /* CONFIG_PPC64 */
 
 /* PGD level */
 typedef struct { unsigned long pgd; } pgd_t;
@@ -159,15 +161,17 @@ typedef unsigned long real_pte_t;
 #endif
 
 
+#ifdef CONFIG_PPC64
 typedef unsigned long pmd_t;
 #define pmd_val(x)      (x)
 #define __pmd(x)        (x)
 
-#if defined(CONFIG_PPC64) && !defined(CONFIG_PPC_64K_PAGES)
+#ifndef CONFIG_PPC_64K_PAGES
 typedef unsigned long pud_t;
 #define pud_val(x)      (x)
 #define __pud(x)        (x)
-#endif
+#endif /* !CONFIG_PPC_64K_PAGES */
+#endif /* CONFIG_PPC64 */
 
 typedef unsigned long pgd_t;
 #define pgd_val(x)      (x)
diff --git a/include/asm-powerpc/page_32.h b/include/asm-powerpc/page_32.h
index 07f6d3cf5e5a..374d0db37e1c 100644
--- a/include/asm-powerpc/page_32.h
+++ b/include/asm-powerpc/page_32.h
@@ -14,11 +14,9 @@
 #ifdef CONFIG_PTE_64BIT
 typedef unsigned long long pte_basic_t;
 #define PTE_SHIFT       (PAGE_SHIFT - 3)        /* 512 ptes per page */
-#define PTE_FMT         "%16Lx"
 #else
 typedef unsigned long pte_basic_t;
 #define PTE_SHIFT       (PAGE_SHIFT - 2)        /* 1024 ptes per page */
-#define PTE_FMT         "%.8lx"
 #endif
 
 struct page;
diff --git a/include/asm-powerpc/parport.h b/include/asm-powerpc/parport.h
index b37b81e37278..414c50e2e881 100644
--- a/include/asm-powerpc/parport.h
+++ b/include/asm-powerpc/parport.h
@@ -12,11 +12,6 @@
 
 #include <asm/prom.h>
 
-extern struct parport *parport_pc_probe_port (unsigned long int base,
-                                              unsigned long int base_hi,
-                                              int irq, int dma,
-                                              struct pci_dev *dev);
-
 static int __devinit parport_pc_find_nonpci_ports (int autoirq, int autodma)
 {
         struct device_node *np;
diff --git a/include/asm-powerpc/pgalloc-32.h b/include/asm-powerpc/pgalloc-32.h
new file mode 100644
index 000000000000..e1307432163c
--- /dev/null
+++ b/include/asm-powerpc/pgalloc-32.h
@@ -0,0 +1,41 @@
+#ifndef _ASM_POWERPC_PGALLOC_32_H
+#define _ASM_POWERPC_PGALLOC_32_H
+
+#include <linux/threads.h>
+
+extern void __bad_pte(pmd_t *pmd);
+
+extern pgd_t *pgd_alloc(struct mm_struct *mm);
+extern void pgd_free(pgd_t *pgd);
+
+/*
+ * We don't have any real pmd's, and this code never triggers because
+ * the pgd will always be present..
+ */
+/* #define pmd_alloc_one(mm,address)       ({ BUG(); ((pmd_t *)2); }) */
+#define pmd_free(x)                     do { } while (0)
+#define __pmd_free_tlb(tlb,x)           do { } while (0)
+/* #define pgd_populate(mm, pmd, pte)      BUG() */
+
+#ifndef CONFIG_BOOKE
+#define pmd_populate_kernel(mm, pmd, pte)       \
+                (pmd_val(*(pmd)) = __pa(pte) | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte)      \
+                (pmd_val(*(pmd)) = (page_to_pfn(pte) << PAGE_SHIFT) | _PMD_PRESENT)
+#else
+#define pmd_populate_kernel(mm, pmd, pte)       \
+                (pmd_val(*(pmd)) = (unsigned long)pte | _PMD_PRESENT)
+#define pmd_populate(mm, pmd, pte)      \
+                (pmd_val(*(pmd)) = (unsigned long)lowmem_page_address(pte) | _PMD_PRESENT)
+#endif
+
+extern pte_t *pte_alloc_one_kernel(struct mm_struct *mm, unsigned long addr);
+extern struct page *pte_alloc_one(struct mm_struct *mm, unsigned long addr);
+extern void pte_free_kernel(pte_t *pte);
+extern void pte_free(struct page *pte);
+
+#define __pte_free_tlb(tlb, pte)        pte_free((pte))
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif /* _ASM_POWERPC_PGALLOC_32_H */
diff --git a/include/asm-powerpc/pgalloc-64.h b/include/asm-powerpc/pgalloc-64.h
new file mode 100644
index 000000000000..30b50cf56e2c
--- /dev/null
+++ b/include/asm-powerpc/pgalloc-64.h
@@ -0,0 +1,152 @@
+#ifndef _ASM_POWERPC_PGALLOC_64_H
+#define _ASM_POWERPC_PGALLOC_64_H
+/*
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+
+#include <linux/mm.h>
+#include <linux/slab.h>
+#include <linux/cpumask.h>
+#include <linux/percpu.h>
+
+extern struct kmem_cache *pgtable_cache[];
+
+#ifdef CONFIG_PPC_64K_PAGES
+#define PTE_CACHE_NUM   0
+#define PMD_CACHE_NUM   1
+#define PGD_CACHE_NUM   2
+#define HUGEPTE_CACHE_NUM 3
+#else
+#define PTE_CACHE_NUM   0
+#define PMD_CACHE_NUM   1
+#define PUD_CACHE_NUM   1
+#define PGD_CACHE_NUM   0
+#define HUGEPTE_CACHE_NUM 2
+#endif
+
+static inline pgd_t *pgd_alloc(struct mm_struct *mm)
+{
+        return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
+}
+
+static inline void pgd_free(pgd_t *pgd)
+{
+        kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
+}
+
+#ifndef CONFIG_PPC_64K_PAGES
+
+#define pgd_populate(MM, PGD, PUD)      pgd_set(PGD, PUD)
+
+static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pud_free(pud_t *pud)
+{
+        kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
+}
+
+static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
+{
+        pud_set(pud, (unsigned long)pmd);
+}
+
+#define pmd_populate(mm, pmd, pte_page) \
+        pmd_populate_kernel(mm, pmd, page_address(pte_page))
+#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
+
+
+#else /* CONFIG_PPC_64K_PAGES */
+
+#define pud_populate(mm, pud, pmd)      pud_set(pud, (unsigned long)pmd)
+
+static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
+                                       pte_t *pte)
+{
+        pmd_set(pmd, (unsigned long)pte);
+}
+
+#define pmd_populate(mm, pmd, pte_page) \
+        pmd_populate_kernel(mm, pmd, page_address(pte_page))
+
+#endif /* CONFIG_PPC_64K_PAGES */
+
+static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
+{
+        return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline void pmd_free(pmd_t *pmd)
+{
+        kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
+}
+
+static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
+                                          unsigned long address)
+{
+        return kmem_cache_alloc(pgtable_cache[PTE_CACHE_NUM],
+                                GFP_KERNEL|__GFP_REPEAT);
+}
+
+static inline struct page *pte_alloc_one(struct mm_struct *mm,
+                                         unsigned long address)
+{
+        return virt_to_page(pte_alloc_one_kernel(mm, address));
+}
+
+static inline void pte_free_kernel(pte_t *pte)
+{
+        kmem_cache_free(pgtable_cache[PTE_CACHE_NUM], pte);
+}
+
+static inline void pte_free(struct page *ptepage)
+{
+        pte_free_kernel(page_address(ptepage));
+}
+
+#define PGF_CACHENUM_MASK       0x3
+
+typedef struct pgtable_free {
+        unsigned long val;
+} pgtable_free_t;
+
+static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
+                                                unsigned long mask)
+{
+        BUG_ON(cachenum > PGF_CACHENUM_MASK);
+
+        return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
+}
+
+static inline void pgtable_free(pgtable_free_t pgf)
+{
+        void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
+        int cachenum = pgf.val & PGF_CACHENUM_MASK;
+
+        kmem_cache_free(pgtable_cache[cachenum], p);
+}
+
+extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
+
+#define __pte_free_tlb(tlb, ptepage)    \
+        pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
+                PTE_CACHE_NUM, PTE_TABLE_SIZE-1))
+#define __pmd_free_tlb(tlb, pmd)        \
+        pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
+                PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
+#ifndef CONFIG_PPC_64K_PAGES
+#define __pud_free_tlb(tlb, pud)        \
+        pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
+                PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
+#endif /* CONFIG_PPC_64K_PAGES */
+
+#define check_pgt_cache()       do { } while (0)
+
+#endif /* _ASM_POWERPC_PGALLOC_64_H */
diff --git a/include/asm-powerpc/pgalloc.h b/include/asm-powerpc/pgalloc.h
index b0830db68f8a..b4505ed0f0f2 100644
--- a/include/asm-powerpc/pgalloc.h
+++ b/include/asm-powerpc/pgalloc.h
@@ -2,159 +2,11 @@
 #define _ASM_POWERPC_PGALLOC_H
 #ifdef __KERNEL__
 
-#ifndef CONFIG_PPC64
-#include <asm-ppc/pgalloc.h>
+#ifdef CONFIG_PPC64
+#include <asm/pgalloc-64.h>
 #else
-
-#include <linux/mm.h>
-#include <linux/slab.h>
-#include <linux/cpumask.h>
-#include <linux/percpu.h>
-
-extern struct kmem_cache *pgtable_cache[];
-
-#ifdef CONFIG_PPC_64K_PAGES
-#define PTE_CACHE_NUM   0
-#define PMD_CACHE_NUM   1
-#define PGD_CACHE_NUM   2
-#define HUGEPTE_CACHE_NUM 3
-#else
-#define PTE_CACHE_NUM   0
-#define PMD_CACHE_NUM   1
-#define PUD_CACHE_NUM   1
-#define PGD_CACHE_NUM   0
-#define HUGEPTE_CACHE_NUM 2
+#include <asm/pgalloc-32.h>
 #endif
 
-/*
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * as published by the Free Software Foundation; either version
- * 2 of the License, or (at your option) any later version.
- */
-
-static inline pgd_t *pgd_alloc(struct mm_struct *mm)
-{
-        return kmem_cache_alloc(pgtable_cache[PGD_CACHE_NUM], GFP_KERNEL);
-}
-
-static inline void pgd_free(pgd_t *pgd)
-{
-        kmem_cache_free(pgtable_cache[PGD_CACHE_NUM], pgd);
-}
-
-#ifndef CONFIG_PPC_64K_PAGES
-
-#define pgd_populate(MM, PGD, PUD)      pgd_set(PGD, PUD)
-
-static inline pud_t *pud_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
-        return kmem_cache_alloc(pgtable_cache[PUD_CACHE_NUM],
-                                GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pud_free(pud_t *pud)
-{
-        kmem_cache_free(pgtable_cache[PUD_CACHE_NUM], pud);
-}
-
-static inline void pud_populate(struct mm_struct *mm, pud_t *pud, pmd_t *pmd)
-{
-        pud_set(pud, (unsigned long)pmd);
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
-        pmd_populate_kernel(mm, pmd, page_address(pte_page))
-#define pmd_populate_kernel(mm, pmd, pte) pmd_set(pmd, (unsigned long)(pte))
-
-
-#else /* CONFIG_PPC_64K_PAGES */
-
-#define pud_populate(mm, pud, pmd)      pud_set(pud, (unsigned long)pmd)
-
-static inline void pmd_populate_kernel(struct mm_struct *mm, pmd_t *pmd,
-                                       pte_t *pte)
-{
-        pmd_set(pmd, (unsigned long)pte);
-}
-
-#define pmd_populate(mm, pmd, pte_page) \
-        pmd_populate_kernel(mm, pmd, page_address(pte_page))
-
-#endif /* CONFIG_PPC_64K_PAGES */
-
-static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
-{
-        return kmem_cache_alloc(pgtable_cache[PMD_CACHE_NUM],
-                                GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline void pmd_free(pmd_t *pmd)
-{
-        kmem_cache_free(pgtable_cache[PMD_CACHE_NUM], pmd);
-}
-
-static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
-                                          unsigned long address)
-{
-        return kmem_cache_alloc(pgtable_cache[PTE_CACHE_NUM],
-                                GFP_KERNEL|__GFP_REPEAT);
-}
-
-static inline struct page *pte_alloc_one(struct mm_struct *mm,
-                                         unsigned long address)
-{
-        return virt_to_page(pte_alloc_one_kernel(mm, address));
-}
-                
-static inline void pte_free_kernel(pte_t *pte)
-{
-        kmem_cache_free(pgtable_cache[PTE_CACHE_NUM], pte);
-}
-
-static inline void pte_free(struct page *ptepage)
-{
-        pte_free_kernel(page_address(ptepage));
-}
-
-#define PGF_CACHENUM_MASK       0x3
-
-typedef struct pgtable_free {
-        unsigned long val;
-} pgtable_free_t;
-
-static inline pgtable_free_t pgtable_free_cache(void *p, int cachenum,
-                                                unsigned long mask)
-{
-        BUG_ON(cachenum > PGF_CACHENUM_MASK);
-
-        return (pgtable_free_t){.val = ((unsigned long) p & ~mask) | cachenum};
-}
-
-static inline void pgtable_free(pgtable_free_t pgf)
-{
-        void *p = (void *)(pgf.val & ~PGF_CACHENUM_MASK);
-        int cachenum = pgf.val & PGF_CACHENUM_MASK;
-
-        kmem_cache_free(pgtable_cache[cachenum], p);
-}
-
-extern void pgtable_free_tlb(struct mmu_gather *tlb, pgtable_free_t pgf);
-
-#define __pte_free_tlb(tlb, ptepage)    \
-        pgtable_free_tlb(tlb, pgtable_free_cache(page_address(ptepage), \
-                PTE_CACHE_NUM, PTE_TABLE_SIZE-1))
-#define __pmd_free_tlb(tlb, pmd)        \
-        pgtable_free_tlb(tlb, pgtable_free_cache(pmd, \
-                PMD_CACHE_NUM, PMD_TABLE_SIZE-1))
-#ifndef CONFIG_PPC_64K_PAGES
-#define __pud_free_tlb(tlb, pud)        \
-        pgtable_free_tlb(tlb, pgtable_free_cache(pud, \
-                PUD_CACHE_NUM, PUD_TABLE_SIZE-1))
-#endif /* CONFIG_PPC_64K_PAGES */
-
-#define check_pgt_cache()       do { } while (0)
-
-#endif /* CONFIG_PPC64 */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PGALLOC_H */
diff --git a/include/asm-powerpc/pgtable-4k.h b/include/asm-powerpc/pgtable-4k.h
index a28fa8bc01da..1744d6ac12a2 100644
--- a/include/asm-powerpc/pgtable-4k.h
+++ b/include/asm-powerpc/pgtable-4k.h
@@ -1,3 +1,5 @@
+#ifndef _ASM_POWERPC_PGTABLE_4K_H
+#define _ASM_POWERPC_PGTABLE_4K_H
 /*
  * Entries per page directory level.  The PTE level must use a 64b record
  * for each page table entry.  The PMD and PGD level use a 32b record for
@@ -100,3 +102,4 @@
 
 #define remap_4k_pfn(vma, addr, pfn, prot)      \
         remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE, (prot))
+#endif /* _ASM_POWERPC_PGTABLE_4K_H */
diff --git a/include/asm-powerpc/pgtable-64k.h b/include/asm-powerpc/pgtable-64k.h
index 5e84f070eaf7..16ef4978520d 100644
--- a/include/asm-powerpc/pgtable-64k.h
+++ b/include/asm-powerpc/pgtable-64k.h
@@ -1,6 +1,5 @@
 #ifndef _ASM_POWERPC_PGTABLE_64K_H
 #define _ASM_POWERPC_PGTABLE_64K_H
-#ifdef __KERNEL__
 
 #include <asm-generic/pgtable-nopud.h>
 
@@ -65,8 +64,6 @@
 /* Bits to mask out from a PGD/PUD to get to the PMD page */
 #define PUD_MASKED_BITS         0x1ff
 
-#ifndef __ASSEMBLY__
-
 /* Manipulate "rpte" values */
 #define __real_pte(e,p)         ((real_pte_t) { \
         (e), pte_val(*((p) + PTRS_PER_PTE)) })
@@ -98,6 +95,4 @@
         remap_pfn_range((vma), (addr), (pfn), PAGE_SIZE,                \
                         __pgprot(pgprot_val((prot)) | _PAGE_4K_PFN))
 
-#endif /*  __ASSEMBLY__ */
-#endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PGTABLE_64K_H */
diff --git a/include/asm-powerpc/pgtable-ppc32.h b/include/asm-powerpc/pgtable-ppc32.h
new file mode 100644
index 000000000000..09662a24f226
--- /dev/null
+++ b/include/asm-powerpc/pgtable-ppc32.h
@@ -0,0 +1,813 @@
+#ifndef _ASM_POWERPC_PGTABLE_PPC32_H
+#define _ASM_POWERPC_PGTABLE_PPC32_H
+
+#include <asm-generic/pgtable-nopmd.h>
+
+#ifndef __ASSEMBLY__
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <asm/processor.h>              /* For TASK_SIZE */
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/io.h>                     /* For sub-arch specific PPC_PIN_SIZE */
+struct mm_struct;
+
+extern unsigned long va_to_phys(unsigned long address);
+extern pte_t *va_to_pte(unsigned long address);
+extern unsigned long ioremap_bot, ioremap_base;
+#endif /* __ASSEMBLY__ */
+
+/*
+ * The PowerPC MMU uses a hash table containing PTEs, together with
+ * a set of 16 segment registers (on 32-bit implementations), to define
+ * the virtual to physical address mapping.
+ *
+ * We use the hash table as an extended TLB, i.e. a cache of currently
+ * active mappings.  We maintain a two-level page table tree, much
+ * like that used by the i386, for the sake of the Linux memory
+ * management code.  Low-level assembler code in hashtable.S
+ * (procedure hash_page) is responsible for extracting ptes from the
+ * tree and putting them into the hash table when necessary, and
+ * updating the accessed and modified bits in the page table tree.
+ */
+
+/*
+ * The PowerPC MPC8xx uses a TLB with hardware assisted, software tablewalk.
+ * We also use the two level tables, but we can put the real bits in them
+ * needed for the TLB and tablewalk.  These definitions require Mx_CTR.PPM = 0,
+ * Mx_CTR.PPCS = 0, and MD_CTR.TWAM = 1.  The level 2 descriptor has
+ * additional page protection (when Mx_CTR.PPCS = 1) that allows TLB hit
+ * based upon user/super access.  The TLB does not have accessed nor write
+ * protect.  We assume that if the TLB get loaded with an entry it is
+ * accessed, and overload the changed bit for write protect.  We use
+ * two bits in the software pte that are supposed to be set to zero in
+ * the TLB entry (24 and 25) for these indicators.  Although the level 1
+ * descriptor contains the guarded and writethrough/copyback bits, we can
+ * set these at the page level since they get copied from the Mx_TWC
+ * register when the TLB entry is loaded.  We will use bit 27 for guard, since
+ * that is where it exists in the MD_TWC, and bit 26 for writethrough.
+ * These will get masked from the level 2 descriptor at TLB load time, and
+ * copied to the MD_TWC before it gets loaded.
+ * Large page sizes added.  We currently support two sizes, 4K and 8M.
+ * This also allows a TLB hander optimization because we can directly
+ * load the PMD into MD_TWC.  The 8M pages are only used for kernel
+ * mapping of well known areas.  The PMD (PGD) entries contain control
+ * flags in addition to the address, so care must be taken that the
+ * software no longer assumes these are only pointers.
+ */
+
+/*
+ * At present, all PowerPC 400-class processors share a similar TLB
+ * architecture. The instruction and data sides share a unified,
+ * 64-entry, fully-associative TLB which is maintained totally under
+ * software control. In addition, the instruction side has a
+ * hardware-managed, 4-entry, fully-associative TLB which serves as a
+ * first level to the shared TLB. These two TLBs are known as the UTLB
+ * and ITLB, respectively (see "mmu.h" for definitions).
+ */
+
+/*
+ * The normal case is that PTEs are 32-bits and we have a 1-page
+ * 1024-entry pgdir pointing to 1-page 1024-entry PTE pages.  -- paulus
+ *
+ * For any >32-bit physical address platform, we can use the following
+ * two level page table layout where the pgdir is 8KB and the MS 13 bits
+ * are an index to the second level table.  The combined pgdir/pmd first
+ * level has 2048 entries and the second level has 512 64-bit PTE entries.
+ * -Matt
+ */
+/* PGDIR_SHIFT determines what a top-level page table entry can map */
+#define PGDIR_SHIFT     (PAGE_SHIFT + PTE_SHIFT)
+#define PGDIR_SIZE      (1UL << PGDIR_SHIFT)
+#define PGDIR_MASK      (~(PGDIR_SIZE-1))
+
+/*
+ * entries per page directory level: our page-table tree is two-level, so
+ * we don't really have any PMD directory.
+ */
+#define PTRS_PER_PTE    (1 << PTE_SHIFT)
+#define PTRS_PER_PMD    1
+#define PTRS_PER_PGD    (1 << (32 - PGDIR_SHIFT))
+
+#define USER_PTRS_PER_PGD       (TASK_SIZE / PGDIR_SIZE)
+#define FIRST_USER_ADDRESS      0
+
+#define USER_PGD_PTRS (PAGE_OFFSET >> PGDIR_SHIFT)
+#define KERNEL_PGD_PTRS (PTRS_PER_PGD-USER_PGD_PTRS)
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
+                (unsigned long long)pte_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+/*
+ * Just any arbitrary offset to the start of the vmalloc VM area: the
+ * current 64MB value just means that there will be a 64MB "hole" after the
+ * physical memory until the kernel virtual memory starts.  That means that
+ * any out-of-bounds memory accesses will hopefully be caught.
+ * The vmalloc() routines leaves a hole of 4kB between each vmalloced
+ * area for the same reason. ;)
+ *
+ * We no longer map larger than phys RAM with the BATs so we don't have
+ * to worry about the VMALLOC_OFFSET causing problems.  We do have to worry
+ * about clashes between our early calls to ioremap() that start growing down
+ * from ioremap_base being run into the VM area allocations (growing upwards
+ * from VMALLOC_START).  For this reason we have ioremap_bot to check when
+ * we actually run into our mappings setup in the early boot with the VM
+ * system.  This really does become a problem for machines with good amounts
+ * of RAM.  -- Cort
+ */
+#define VMALLOC_OFFSET (0x1000000) /* 16M */
+#ifdef PPC_PIN_SIZE
+#define VMALLOC_START (((_ALIGN((long)high_memory, PPC_PIN_SIZE) + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#else
+#define VMALLOC_START ((((long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1)))
+#endif
+#define VMALLOC_END     ioremap_bot
+
+/*
+ * Bits in a linux-style PTE.  These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible.
+ */
+
+#if defined(CONFIG_40x)
+
+/* There are several potential gotchas here.  The 40x hardware TLBLO
+   field looks like this:
+
+   0  1  2  3  4  ... 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+   RPN.....................  0  0 EX WR ZSEL.......  W  I  M  G
+
+   Where possible we make the Linux PTE bits match up with this
+
+   - bits 20 and 21 must be cleared, because we use 4k pages (40x can
+     support down to 1k pages), this is done in the TLBMiss exception
+     handler.
+   - We use only zones 0 (for kernel pages) and 1 (for user pages)
+     of the 16 available.  Bit 24-26 of the TLB are cleared in the TLB
+     miss handler.  Bit 27 is PAGE_USER, thus selecting the correct
+     zone.
+   - PRESENT *must* be in the bottom two bits because swap cache
+     entries use the top 30 bits.  Because 40x doesn't support SMP
+     anyway, M is irrelevant so we borrow it for PAGE_PRESENT.  Bit 30
+     is cleared in the TLB miss handler before the TLB entry is loaded.
+   - All other bits of the PTE are loaded into TLBLO without
+     modification, leaving us only the bits 20, 21, 24, 25, 26, 30 for
+     software PTE bits.  We actually use use bits 21, 24, 25, and
+     30 respectively for the software bits: ACCESSED, DIRTY, RW, and
+     PRESENT.
+*/
+
+/* Definitions for 40x embedded chips. */
+#define _PAGE_GUARDED   0x001   /* G: page is guarded from prefetch */
+#define _PAGE_FILE      0x001   /* when !present: nonlinear file mapping */
+#define _PAGE_PRESENT   0x002   /* software: PTE contains a translation */
+#define _PAGE_NO_CACHE  0x004   /* I: caching is inhibited */
+#define _PAGE_WRITETHRU 0x008   /* W: caching is write-through */
+#define _PAGE_USER      0x010   /* matches one of the zone permission bits */
+#define _PAGE_RW        0x040   /* software: Writes permitted */
+#define _PAGE_DIRTY     0x080   /* software: dirty page */
+#define _PAGE_HWWRITE   0x100   /* hardware: Dirty & RW, set in exception */
+#define _PAGE_HWEXEC    0x200   /* hardware: EX permission */
+#define _PAGE_ACCESSED  0x400   /* software: R: page referenced */
+
+#define _PMD_PRESENT    0x400   /* PMD points to page of PTEs */
+#define _PMD_BAD        0x802
+#define _PMD_SIZE       0x0e0   /* size field, != 0 for large-page PMD entry */
+#define _PMD_SIZE_4M    0x0c0
+#define _PMD_SIZE_16M   0x0e0
+#define PMD_PAGE_SIZE(pmdval)   (1024 << (((pmdval) & _PMD_SIZE) >> 4))
+
+#elif defined(CONFIG_44x)
+/*
+ * Definitions for PPC440
+ *
+ * Because of the 3 word TLB entries to support 36-bit addressing,
+ * the attribute are difficult to map in such a fashion that they
+ * are easily loaded during exception processing.  I decided to
+ * organize the entry so the ERPN is the only portion in the
+ * upper word of the PTE and the attribute bits below are packed
+ * in as sensibly as they can be in the area below a 4KB page size
+ * oriented RPN.  This at least makes it easy to load the RPN and
+ * ERPN fields in the TLB. -Matt
+ *
+ * Note that these bits preclude future use of a page size
+ * less than 4KB.
+ *
+ *
+ * PPC 440 core has following TLB attribute fields;
+ *
+ *   TLB1:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   RPN.................................  -  -  -  -  -  - ERPN.......
+ *
+ *   TLB2:
+ *   0  1  2  3  4  ... 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
+ *   -  -  -  -  -    - U0 U1 U2 U3 W  I  M  G  E   - UX UW UR SX SW SR
+ *
+ * There are some constrains and options, to decide mapping software bits
+ * into TLB entry.
+ *
+ *   - PRESENT *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - FILE *must* be in the bottom three bits because swap cache
+ *     entries use the top 29 bits for TLB2.
+ *
+ *   - CACHE COHERENT bit (M) has no effect on PPC440 core, because it
+ *     doesn't support SMP. So we can use this as software bit, like
+ *     DIRTY.
+ *
+ * With the PPC 44x Linux implementation, the 0-11th LSBs of the PTE are used
+ * for memory protection related functions (see PTE structure in
+ * include/asm-ppc/mmu.h).  The _PAGE_XXX definitions in this file map to the
+ * above bits.  Note that the bit values are CPU specific, not architecture
+ * specific.
+ *
+ * The kernel PTE entry holds an arch-dependent swp_entry structure under
+ * certain situations. In other words, in such situations some portion of
+ * the PTE bits are used as a swp_entry. In the PPC implementation, the
+ * 3-24th LSB are shared with swp_entry, however the 0-2nd three LSB still
+ * hold protection values. That means the three protection bits are
+ * reserved for both PTE and SWAP entry at the most significant three
+ * LSBs.
+ *
+ * There are three protection bits available for SWAP entry:
+ *      _PAGE_PRESENT
+ *      _PAGE_FILE
+ *      _PAGE_HASHPTE (if HW has)
+ *
+ * So those three bits have to be inside of 0-2nd LSB of PTE.
+ *
+ */
+
+#define _PAGE_PRESENT   0x00000001              /* S: PTE valid */
+#define _PAGE_RW        0x00000002              /* S: Write permission */
+#define _PAGE_FILE      0x00000004              /* S: nonlinear file mapping */
+#define _PAGE_ACCESSED  0x00000008              /* S: Page referenced */
+#define _PAGE_HWWRITE   0x00000010              /* H: Dirty & RW */
+#define _PAGE_HWEXEC    0x00000020              /* H: Execute permission */
+#define _PAGE_USER      0x00000040              /* S: User page */
+#define _PAGE_ENDIAN    0x00000080              /* H: E bit */
+#define _PAGE_GUARDED   0x00000100              /* H: G bit */
+#define _PAGE_DIRTY     0x00000200              /* S: Page dirty */
+#define _PAGE_NO_CACHE  0x00000400              /* H: I bit */
+#define _PAGE_WRITETHRU 0x00000800              /* H: W bit */
+
+/* TODO: Add large page lowmem mapping support */
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK  0xffffffff00000000ULL
+
+#elif defined(CONFIG_FSL_BOOKE)
+/*
+   MMU Assist Register 3:
+
+   32 33 34 35 36  ... 50 51 52 53 54 55 56 57 58 59 60 61 62 63
+   RPN......................  0  0 U0 U1 U2 U3 UX SX UW SW UR SR
+
+   - PRESENT *must* be in the bottom three bits because swap cache
+     entries use the top 29 bits.
+
+   - FILE *must* be in the bottom three bits because swap cache
+     entries use the top 29 bits.
+*/
+
+/* Definitions for FSL Book-E Cores */
+#define _PAGE_PRESENT   0x00001 /* S: PTE contains a translation */
+#define _PAGE_USER      0x00002 /* S: User page (maps to UR) */
+#define _PAGE_FILE      0x00002 /* S: when !present: nonlinear file mapping */
+#define _PAGE_ACCESSED  0x00004 /* S: Page referenced */
+#define _PAGE_HWWRITE   0x00008 /* H: Dirty & RW, set in exception */
+#define _PAGE_RW        0x00010 /* S: Write permission */
+#define _PAGE_HWEXEC    0x00020 /* H: UX permission */
+
+#define _PAGE_ENDIAN    0x00040 /* H: E bit */
+#define _PAGE_GUARDED   0x00080 /* H: G bit */
+#define _PAGE_COHERENT  0x00100 /* H: M bit */
+#define _PAGE_NO_CACHE  0x00200 /* H: I bit */
+#define _PAGE_WRITETHRU 0x00400 /* H: W bit */
+
+#ifdef CONFIG_PTE_64BIT
+#define _PAGE_DIRTY     0x08000 /* S: Page dirty */
+
+/* ERPN in a PTE never gets cleared, ignore it */
+#define _PTE_NONE_MASK  0xffffffffffff0000ULL
+#else
+#define _PAGE_DIRTY     0x00800 /* S: Page dirty */
+#endif
+
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+
+#elif defined(CONFIG_8xx)
+/* Definitions for 8xx embedded chips. */
+#define _PAGE_PRESENT   0x0001  /* Page is valid */
+#define _PAGE_FILE      0x0002  /* when !present: nonlinear file mapping */
+#define _PAGE_NO_CACHE  0x0002  /* I: cache inhibit */
+#define _PAGE_SHARED    0x0004  /* No ASID (context) compare */
+
+/* These five software bits must be masked out when the entry is loaded
+ * into the TLB.
+ */
+#define _PAGE_EXEC      0x0008  /* software: i-cache coherency required */
+#define _PAGE_GUARDED   0x0010  /* software: guarded access */
+#define _PAGE_DIRTY     0x0020  /* software: page changed */
+#define _PAGE_RW        0x0040  /* software: user write access allowed */
+#define _PAGE_ACCESSED  0x0080  /* software: page referenced */
+
+/* Setting any bits in the nibble with the follow two controls will
+ * require a TLB exception handler change.  It is assumed unused bits
+ * are always zero.
+ */
+#define _PAGE_HWWRITE   0x0100  /* h/w write enable: never set in Linux PTE */
+#define _PAGE_USER      0x0800  /* One of the PP bits, the other is USER&~RW */
+
+#define _PMD_PRESENT    0x0001
+#define _PMD_BAD        0x0ff0
+#define _PMD_PAGE_MASK  0x000c
+#define _PMD_PAGE_8M    0x000c
+
+/*
+ * The 8xx TLB miss handler allegedly sets _PAGE_ACCESSED in the PTE
+ * for an address even if _PAGE_PRESENT is not set, as a performance
+ * optimization.  This is a bug if you ever want to use swap unless
+ * _PAGE_ACCESSED is 2, which it isn't, or unless you have 8xx-specific
+ * definitions for __swp_entry etc. below, which would be gross.
+ *  -- paulus
+ */
+#define _PTE_NONE_MASK _PAGE_ACCESSED
+
+#else /* CONFIG_6xx */
+/* Definitions for 60x, 740/750, etc. */
+#define _PAGE_PRESENT   0x001   /* software: pte contains a translation */
+#define _PAGE_HASHPTE   0x002   /* hash_page has made an HPTE for this pte */
+#define _PAGE_FILE      0x004   /* when !present: nonlinear file mapping */
+#define _PAGE_USER      0x004   /* usermode access allowed */
+#define _PAGE_GUARDED   0x008   /* G: prohibit speculative access */
+#define _PAGE_COHERENT  0x010   /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE  0x020   /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x040   /* W: cache write-through */
+#define _PAGE_DIRTY     0x080   /* C: page changed */
+#define _PAGE_ACCESSED  0x100   /* R: page referenced */
+#define _PAGE_EXEC      0x200   /* software: i-cache coherency required */
+#define _PAGE_RW        0x400   /* software: user write access allowed */
+
+#define _PTE_NONE_MASK  _PAGE_HASHPTE
+
+#define _PMD_PRESENT    0
+#define _PMD_PRESENT_MASK (PAGE_MASK)
+#define _PMD_BAD        (~PAGE_MASK)
+#endif
+
+/*
+ * Some bits are only used on some cpu families...
+ */
+#ifndef _PAGE_HASHPTE
+#define _PAGE_HASHPTE   0
+#endif
+#ifndef _PTE_NONE_MASK
+#define _PTE_NONE_MASK 0
+#endif
+#ifndef _PAGE_SHARED
+#define _PAGE_SHARED    0
+#endif
+#ifndef _PAGE_HWWRITE
+#define _PAGE_HWWRITE   0
+#endif
+#ifndef _PAGE_HWEXEC
+#define _PAGE_HWEXEC    0
+#endif
+#ifndef _PAGE_EXEC
+#define _PAGE_EXEC      0
+#endif
+#ifndef _PMD_PRESENT_MASK
+#define _PMD_PRESENT_MASK       _PMD_PRESENT
+#endif
+#ifndef _PMD_SIZE
+#define _PMD_SIZE       0
+#define PMD_PAGE_SIZE(pmd)      bad_call_to_PMD_PAGE_SIZE()
+#endif
+
+#define _PAGE_CHG_MASK  (PAGE_MASK | _PAGE_ACCESSED | _PAGE_DIRTY)
+
+/*
+ * Note: the _PAGE_COHERENT bit automatically gets set in the hardware
+ * PTE if CONFIG_SMP is defined (hash_page does this); there is no need
+ * to have it in the Linux PTE, and in fact the bit could be reused for
+ * another purpose.  -- paulus.
+ */
+
+#ifdef CONFIG_44x
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_GUARDED)
+#else
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED)
+#endif
+#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY | _PAGE_HWWRITE)
+#define _PAGE_KERNEL    (_PAGE_BASE | _PAGE_SHARED | _PAGE_WRENABLE)
+
+#ifdef CONFIG_PPC_STD_MMU
+/* On standard PPC MMU, no user access implies kernel read/write access,
+ * so to write-protect kernel memory we must turn on user access */
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED | _PAGE_USER)
+#else
+#define _PAGE_KERNEL_RO (_PAGE_BASE | _PAGE_SHARED)
+#endif
+
+#define _PAGE_IO        (_PAGE_KERNEL | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define _PAGE_RAM       (_PAGE_KERNEL | _PAGE_HWEXEC)
+
+#if defined(CONFIG_KGDB) || defined(CONFIG_XMON) || defined(CONFIG_BDI_SWITCH)
+/* We want the debuggers to be able to set breakpoints anywhere, so
+ * don't write protect the kernel text */
+#define _PAGE_RAM_TEXT  _PAGE_RAM
+#else
+#define _PAGE_RAM_TEXT  (_PAGE_KERNEL_RO | _PAGE_HWEXEC)
+#endif
+
+#define PAGE_NONE       __pgprot(_PAGE_BASE)
+#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW)
+#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_RW | _PAGE_EXEC)
+#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+
+#define PAGE_KERNEL             __pgprot(_PAGE_RAM)
+#define PAGE_KERNEL_NOCACHE     __pgprot(_PAGE_IO)
+
+/*
+ * The PowerPC can only do execute protection on a segment (256MB) basis,
+ * not on a page basis.  So we consider execute permission the same as read.
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY_X
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY_X
+#define __P100  PAGE_READONLY
+#define __P101  PAGE_READONLY_X
+#define __P110  PAGE_COPY
+#define __P111  PAGE_COPY_X
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY_X
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED_X
+#define __S100  PAGE_READONLY
+#define __S101  PAGE_READONLY_X
+#define __S110  PAGE_SHARED
+#define __S111  PAGE_SHARED_X
+
+#ifndef __ASSEMBLY__
+/* Make sure we get a link error if PMD_PAGE_SIZE is ever called on a
+ * kernel without large page PMD support */
+extern unsigned long bad_call_to_PMD_PAGE_SIZE(void);
+
+/*
+ * Conversions between PTE values and page frame numbers.
+ */
+
+/* in some case we want to additionaly adjust where the pfn is in the pte to
+ * allow room for more flags */
+#if defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
+#define PFN_SHIFT_OFFSET        (PAGE_SHIFT + 8)
+#else
+#define PFN_SHIFT_OFFSET        (PAGE_SHIFT)
+#endif
+
+#define pte_pfn(x)              (pte_val(x) >> PFN_SHIFT_OFFSET)
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#define pfn_pte(pfn, prot)      __pte(((pte_basic_t)(pfn) << PFN_SHIFT_OFFSET) |\
+                                        pgprot_val(prot))
+#define mk_pte(page, prot)      pfn_pte(page_to_pfn(page), prot)
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[1024];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+
+#endif /* __ASSEMBLY__ */
+
+#define pte_none(pte)           ((pte_val(pte) & ~_PTE_NONE_MASK) == 0)
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+#define pte_clear(mm,addr,ptep) do { set_pte_at((mm), (addr), (ptep), __pte(0)); } while (0)
+
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_bad(pmd)            (pmd_val(pmd) & _PMD_BAD)
+#define pmd_present(pmd)        (pmd_val(pmd) & _PMD_PRESENT_MASK)
+#define pmd_clear(pmdp)         do { pmd_val(*(pmdp)) = 0; } while (0)
+
+#ifndef __ASSEMBLY__
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_read(pte_t pte)           { return pte_val(pte) & _PAGE_USER; }
+static inline int pte_write(pte_t pte)          { return pte_val(pte) & _PAGE_RW; }
+static inline int pte_exec(pte_t pte)           { return pte_val(pte) & _PAGE_EXEC; }
+static inline int pte_dirty(pte_t pte)          { return pte_val(pte) & _PAGE_DIRTY; }
+static inline int pte_young(pte_t pte)          { return pte_val(pte) & _PAGE_ACCESSED; }
+static inline int pte_file(pte_t pte)           { return pte_val(pte) & _PAGE_FILE; }
+
+static inline void pte_uncache(pte_t pte)       { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte)         { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_rdprotect(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_USER; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_RW | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_exprotect(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_EXEC; return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_DIRTY | _PAGE_HWWRITE); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_mkread(pte_t pte) {
+        pte_val(pte) |= _PAGE_USER; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) {
+        pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) {
+        pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+        pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+
+static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
+{
+        pte_val(pte) = (pte_val(pte) & _PAGE_CHG_MASK) | pgprot_val(newprot);
+        return pte;
+}
+
+/*
+ * When flushing the tlb entry for a page, we also need to flush the hash
+ * table entry.  flush_hash_pages is assembler (for speed) in hashtable.S.
+ */
+extern int flush_hash_pages(unsigned context, unsigned long va,
+                            unsigned long pmdval, int count);
+
+/* Add an HPTE to the hash table */
+extern void add_hash_page(unsigned context, unsigned long va,
+                          unsigned long pmdval);
+
+/*
+ * Atomic PTE updates.
+ *
+ * pte_update clears and sets bit atomically, and returns
+ * the old pte value.  In the 64-bit PTE case we lock around the
+ * low PTE word since we expect ALL flag bits to be there
+ */
+#ifndef CONFIG_PTE_64BIT
+static inline unsigned long pte_update(pte_t *p, unsigned long clr,
+                                       unsigned long set)
+{
+        unsigned long old, tmp;
+
+        __asm__ __volatile__("\
+1:      lwarx   %0,0,%3\n\
+        andc    %1,%0,%4\n\
+        or      %1,%1,%5\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %1,0,%3\n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*p)
+        : "r" (p), "r" (clr), "r" (set), "m" (*p)
+        : "cc" );
+        return old;
+}
+#else
+static inline unsigned long long pte_update(pte_t *p, unsigned long clr,
+                                       unsigned long set)
+{
+        unsigned long long old;
+        unsigned long tmp;
+
+        __asm__ __volatile__("\
+1:      lwarx   %L0,0,%4\n\
+        lwzx    %0,0,%3\n\
+        andc    %1,%L0,%5\n\
+        or      %1,%1,%6\n"
+        PPC405_ERR77(0,%3)
+"       stwcx.  %1,0,%4\n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*p)
+        : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
+        : "cc" );
+        return old;
+}
+#endif
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ * On machines which use an MMU hash table we avoid changing the
+ * _PAGE_HASHPTE bit.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pte)
+{
+#if _PAGE_HASHPTE != 0
+        pte_update(ptep, ~_PAGE_HASHPTE, pte_val(pte) & ~_PAGE_HASHPTE);
+#else
+        *ptep = pte;
+#endif
+}
+
+/*
+ * 2.6 calles this without flushing the TLB entry, this is wrong
+ * for our hash-based implementation, we fix that up here
+ */
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+static inline int __ptep_test_and_clear_young(unsigned int context, unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+        old = pte_update(ptep, _PAGE_ACCESSED, 0);
+#if _PAGE_HASHPTE != 0
+        if (old & _PAGE_HASHPTE) {
+                unsigned long ptephys = __pa(ptep) & PAGE_MASK;
+                flush_hash_pages(context, addr, ptephys, 1);
+        }
+#endif
+        return (old & _PAGE_ACCESSED) != 0;
+}
+#define ptep_test_and_clear_young(__vma, __addr, __ptep) \
+        __ptep_test_and_clear_young((__vma)->vm_mm->context.id, __addr, __ptep)
+
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+static inline int ptep_test_and_clear_dirty(struct vm_area_struct *vma,
+                                            unsigned long addr, pte_t *ptep)
+{
+        return (pte_update(ptep, (_PAGE_DIRTY | _PAGE_HWWRITE), 0) & _PAGE_DIRTY) != 0;
+}
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm, unsigned long addr,
+                                       pte_t *ptep)
+{
+        return __pte(pte_update(ptep, ~_PAGE_HASHPTE, 0));
+}
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+                                      pte_t *ptep)
+{
+        pte_update(ptep, (_PAGE_RW | _PAGE_HWWRITE), 0);
+}
+
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+        unsigned long bits = pte_val(entry) &
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW);
+        pte_update(ptep, 0, bits);
+}
+
+#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+        do {                                                               \
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        } while(0)
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HASHPTE) == 0)
+
+/*
+ * Note that on Book E processors, the pmd contains the kernel virtual
+ * (lowmem) address of the pte page.  The physical address is less useful
+ * because everything runs with translation enabled (even the TLB miss
+ * handler).  On everything else the pmd contains the physical address
+ * of the pte page.  -- paulus
+ */
+#ifndef CONFIG_BOOKE
+#define pmd_page_vaddr(pmd)     \
+        ((unsigned long) __va(pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd)           \
+        (mem_map + (pmd_val(pmd) >> PAGE_SHIFT))
+#else
+#define pmd_page_vaddr(pmd)     \
+        ((unsigned long) (pmd_val(pmd) & PAGE_MASK))
+#define pmd_page(pmd)           \
+        (mem_map + (__pa(pmd_val(pmd)) >> PAGE_SHIFT))
+#endif
+
+/* to find an entry in a kernel page-table-directory */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/* to find an entry in a page-table-directory */
+#define pgd_index(address)       ((address) >> PGDIR_SHIFT)
+#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
+
+/* Find an entry in the third-level page table.. */
+#define pte_index(address)              \
+        (((address) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1))
+#define pte_offset_kernel(dir, addr)    \
+        ((pte_t *) pmd_page_vaddr(*(dir)) + pte_index(addr))
+#define pte_offset_map(dir, addr)               \
+        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE0) + pte_index(addr))
+#define pte_offset_map_nested(dir, addr)        \
+        ((pte_t *) kmap_atomic(pmd_page(*(dir)), KM_PTE1) + pte_index(addr))
+
+#define pte_unmap(pte)          kunmap_atomic(pte, KM_PTE0)
+#define pte_unmap_nested(pte)   kunmap_atomic(pte, KM_PTE1)
+
+extern pgd_t swapper_pg_dir[PTRS_PER_PGD];
+
+extern void paging_init(void);
+
+/*
+ * Encode and decode a swap entry.
+ * Note that the bits we use in a PTE for representing a swap entry
+ * must not include the _PAGE_PRESENT bit, the _PAGE_FILE bit, or the
+ *_PAGE_HASHPTE bit (if used).  -- paulus
+ */
+#define __swp_type(entry)               ((entry).val & 0x1f)
+#define __swp_offset(entry)             ((entry).val >> 5)
+#define __swp_entry(type, offset)       ((swp_entry_t) { (type) | ((offset) << 5) })
+#define __pte_to_swp_entry(pte)         ((swp_entry_t) { pte_val(pte) >> 3 })
+#define __swp_entry_to_pte(x)           ((pte_t) { (x).val << 3 })
+
+/* Encode and decode a nonlinear file mapping entry */
+#define PTE_FILE_MAX_BITS       29
+#define pte_to_pgoff(pte)       (pte_val(pte) >> 3)
+#define pgoff_to_pte(off)       ((pte_t) { ((off) << 3) | _PAGE_FILE })
+
+/* CONFIG_APUS */
+/* For virtual address to physical address conversion */
+extern void cache_clear(__u32 addr, int length);
+extern void cache_push(__u32 addr, int length);
+extern int mm_end_of_chunk (unsigned long addr, int len);
+extern unsigned long iopa(unsigned long addr);
+extern unsigned long mm_ptov(unsigned long addr) __attribute_const__;
+
+/* Values for nocacheflag and cmode */
+/* These are not used by the APUS kernel_map, but prevents
+   compilation errors. */
+#define KERNELMAP_FULL_CACHING          0
+#define KERNELMAP_NOCACHE_SER           1
+#define KERNELMAP_NOCACHE_NONSER        2
+#define KERNELMAP_NO_COPYBACK           3
+
+/*
+ * Map some physical address range into the kernel address space.
+ */
+extern unsigned long kernel_map(unsigned long paddr, unsigned long size,
+                                int nocacheflag, unsigned long *memavailp );
+
+/*
+ * Set cache mode of (kernel space) address range.
+ */
+extern void kernel_set_cachemode (unsigned long address, unsigned long size,
+                                 unsigned int cmode);
+
+/* Needs to be defined here and not in linux/mm.h, as it is arch dependent */
+#define kern_addr_valid(addr)   (1)
+
+#ifdef CONFIG_PHYS_64BIT
+extern int remap_pfn_range(struct vm_area_struct *vma, unsigned long from,
+                        unsigned long paddr, unsigned long size, pgprot_t prot);
+
+static inline int io_remap_pfn_range(struct vm_area_struct *vma,
+                                        unsigned long vaddr,
+                                        unsigned long pfn,
+                                        unsigned long size,
+                                        pgprot_t prot)
+{
+        phys_addr_t paddr64 = fixup_bigphys_addr(pfn << PAGE_SHIFT, size);
+        return remap_pfn_range(vma, vaddr, paddr64 >> PAGE_SHIFT, size, prot);
+}
+#else
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+#endif
+
+/*
+ * No page table caches to initialise
+ */
+#define pgtable_cache_init()    do { } while (0)
+
+extern int get_pteptr(struct mm_struct *mm, unsigned long addr, pte_t **ptep,
+                      pmd_t **pmdp);
+
+#endif /* !__ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PGTABLE_PPC32_H */
diff --git a/include/asm-powerpc/pgtable-ppc64.h b/include/asm-powerpc/pgtable-ppc64.h
new file mode 100644
index 000000000000..704c4e669fe0
--- /dev/null
+++ b/include/asm-powerpc/pgtable-ppc64.h
@@ -0,0 +1,492 @@
+#ifndef _ASM_POWERPC_PGTABLE_PPC64_H_
+#define _ASM_POWERPC_PGTABLE_PPC64_H_
+/*
+ * This file contains the functions and defines necessary to modify and use
+ * the ppc64 hashed page table.
+ */
+
+#ifndef __ASSEMBLY__
+#include <linux/stddef.h>
+#include <asm/processor.h>              /* For TASK_SIZE */
+#include <asm/mmu.h>
+#include <asm/page.h>
+#include <asm/tlbflush.h>
+struct mm_struct;
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_PPC_64K_PAGES
+#include <asm/pgtable-64k.h>
+#else
+#include <asm/pgtable-4k.h>
+#endif
+
+#define FIRST_USER_ADDRESS      0
+
+/*
+ * Size of EA range mapped by our pagetables.
+ */
+#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
+                            PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
+#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
+
+#if TASK_SIZE_USER64 > PGTABLE_RANGE
+#error TASK_SIZE_USER64 exceeds pagetable range
+#endif
+
+#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
+#error TASK_SIZE_USER64 exceeds user VSID range
+#endif
+
+/*
+ * Define the address range of the vmalloc VM area.
+ */
+#define VMALLOC_START ASM_CONST(0xD000000000000000)
+#define VMALLOC_SIZE  ASM_CONST(0x80000000000)
+#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
+
+/*
+ * Define the address range of the imalloc VM area.
+ */
+#define PHBS_IO_BASE    VMALLOC_END
+#define IMALLOC_BASE    (PHBS_IO_BASE + 0x80000000ul)   /* Reserve 2 gigs for PHBs */
+#define IMALLOC_END     (VMALLOC_START + PGTABLE_RANGE)
+
+/*
+ * Region IDs
+ */
+#define REGION_SHIFT            60UL
+#define REGION_MASK             (0xfUL << REGION_SHIFT)
+#define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
+
+#define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
+#define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
+#define USER_REGION_ID          (0UL)
+
+/*
+ * Common bits in a linux-style PTE.  These match the bits in the
+ * (hardware-defined) PowerPC PTE as closely as possible. Additional
+ * bits may be defined in pgtable-*.h
+ */
+#define _PAGE_PRESENT   0x0001 /* software: pte contains a translation */
+#define _PAGE_USER      0x0002 /* matches one of the PP bits */
+#define _PAGE_FILE      0x0002 /* (!present only) software: pte holds file offset */
+#define _PAGE_EXEC      0x0004 /* No execute on POWER4 and newer (we invert) */
+#define _PAGE_GUARDED   0x0008
+#define _PAGE_COHERENT  0x0010 /* M: enforce memory coherence (SMP systems) */
+#define _PAGE_NO_CACHE  0x0020 /* I: cache inhibit */
+#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
+#define _PAGE_DIRTY     0x0080 /* C: page changed */
+#define _PAGE_ACCESSED  0x0100 /* R: page referenced */
+#define _PAGE_RW        0x0200 /* software: user write access allowed */
+#define _PAGE_HASHPTE   0x0400 /* software: pte has an associated HPTE */
+#define _PAGE_BUSY      0x0800 /* software: PTE & hash are busy */
+
+#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
+
+#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY)
+
+/* __pgprot defined in asm-powerpc/page.h */
+#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
+
+#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
+#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
+#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
+#define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
+#define PAGE_KERNEL_CI  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
+                               _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
+#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
+
+#define PAGE_AGP        __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
+#define HAVE_PAGE_AGP
+
+/* PTEIDX nibble */
+#define _PTEIDX_SECONDARY       0x8
+#define _PTEIDX_GROUP_IX        0x7
+
+
+/*
+ * POWER4 and newer have per page execute protection, older chips can only
+ * do this on a segment (256MB) basis.
+ *
+ * Also, write permissions imply read permissions.
+ * This is the closest we can get..
+ *
+ * Note due to the way vm flags are laid out, the bits are XWR
+ */
+#define __P000  PAGE_NONE
+#define __P001  PAGE_READONLY
+#define __P010  PAGE_COPY
+#define __P011  PAGE_COPY
+#define __P100  PAGE_READONLY_X
+#define __P101  PAGE_READONLY_X
+#define __P110  PAGE_COPY_X
+#define __P111  PAGE_COPY_X
+
+#define __S000  PAGE_NONE
+#define __S001  PAGE_READONLY
+#define __S010  PAGE_SHARED
+#define __S011  PAGE_SHARED
+#define __S100  PAGE_READONLY_X
+#define __S101  PAGE_READONLY_X
+#define __S110  PAGE_SHARED_X
+#define __S111  PAGE_SHARED_X
+
+#ifndef __ASSEMBLY__
+
+/*
+ * ZERO_PAGE is a global shared page that is always zero: used
+ * for zero-mapped memory areas etc..
+ */
+extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
+#endif /* __ASSEMBLY__ */
+
+#ifdef CONFIG_HUGETLB_PAGE
+
+#define HAVE_ARCH_UNMAPPED_AREA
+#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
+
+#endif
+
+#ifndef __ASSEMBLY__
+
+/*
+ * Conversion functions: convert a page and protection to a page entry,
+ * and a page entry and page directory to the page they refer to.
+ *
+ * mk_pte takes a (struct page *) as input
+ */
+#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
+
+static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
+{
+        pte_t pte;
+
+
+        pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
+        return pte;
+}
+
+#define pte_modify(_pte, newprot) \
+  (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
+
+#define pte_none(pte)           ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
+#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
+
+/* pte_clear moved to later in this file */
+
+#define pte_pfn(x)              ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
+#define pte_page(x)             pfn_to_page(pte_pfn(x))
+
+#define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
+#define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
+
+#define pmd_set(pmdp, pmdval)   (pmd_val(*(pmdp)) = (pmdval))
+#define pmd_none(pmd)           (!pmd_val(pmd))
+#define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
+                                 || (pmd_val(pmd) & PMD_BAD_BITS))
+#define pmd_present(pmd)        (pmd_val(pmd) != 0)
+#define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
+#define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
+#define pmd_page(pmd)           virt_to_page(pmd_page_vaddr(pmd))
+
+#define pud_set(pudp, pudval)   (pud_val(*(pudp)) = (pudval))
+#define pud_none(pud)           (!pud_val(pud))
+#define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
+                                 || (pud_val(pud) & PUD_BAD_BITS))
+#define pud_present(pud)        (pud_val(pud) != 0)
+#define pud_clear(pudp)         (pud_val(*(pudp)) = 0)
+#define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
+#define pud_page(pud)           virt_to_page(pud_page_vaddr(pud))
+
+#define pgd_set(pgdp, pudp)     ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
+
+/*
+ * Find an entry in a page-table-directory.  We combine the address region
+ * (the high order N bits) and the pgd portion of the address.
+ */
+/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
+#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
+
+#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
+
+#define pmd_offset(pudp,addr) \
+  (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
+
+#define pte_offset_kernel(dir,addr) \
+  (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
+
+#define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
+#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
+#define pte_unmap(pte)                  do { } while(0)
+#define pte_unmap_nested(pte)           do { } while(0)
+
+/* to find an entry in a kernel page-table-directory */
+/* This now only contains the vmalloc pages */
+#define pgd_offset_k(address) pgd_offset(&init_mm, address)
+
+/*
+ * The following only work if pte_present() is true.
+ * Undefined behaviour if not..
+ */
+static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER;}
+static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
+static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC;}
+static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
+static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
+static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
+
+static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
+static inline void pte_cache(pte_t pte)   { pte_val(pte) &= ~_PAGE_NO_CACHE; }
+
+static inline pte_t pte_rdprotect(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_USER; return pte; }
+static inline pte_t pte_exprotect(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_EXEC; return pte; }
+static inline pte_t pte_wrprotect(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_RW); return pte; }
+static inline pte_t pte_mkclean(pte_t pte) {
+        pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
+static inline pte_t pte_mkold(pte_t pte) {
+        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkread(pte_t pte) {
+        pte_val(pte) |= _PAGE_USER; return pte; }
+static inline pte_t pte_mkexec(pte_t pte) {
+        pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
+static inline pte_t pte_mkwrite(pte_t pte) {
+        pte_val(pte) |= _PAGE_RW; return pte; }
+static inline pte_t pte_mkdirty(pte_t pte) {
+        pte_val(pte) |= _PAGE_DIRTY; return pte; }
+static inline pte_t pte_mkyoung(pte_t pte) {
+        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
+static inline pte_t pte_mkhuge(pte_t pte) {
+        return pte; }
+
+/* Atomic PTE updates */
+static inline unsigned long pte_update(struct mm_struct *mm,
+                                       unsigned long addr,
+                                       pte_t *ptep, unsigned long clr,
+                                       int huge)
+{
+        unsigned long old, tmp;
+
+        __asm__ __volatile__(
+        "1:     ldarx   %0,0,%3         # pte_update\n\
+        andi.   %1,%0,%6\n\
+        bne-    1b \n\
+        andc    %1,%0,%4 \n\
+        stdcx.  %1,0,%3 \n\
+        bne-    1b"
+        : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
+        : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
+        : "cc" );
+
+        if (old & _PAGE_HASHPTE)
+                hpte_need_flush(mm, addr, ptep, old, huge);
+        return old;
+}
+
+static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
+                                              unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+
+        if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
+                return 0;
+        old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
+        return (old & _PAGE_ACCESSED) != 0;
+}
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
+#define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
+({                                                                         \
+        int __r;                                                           \
+        __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
+        __r;                                                               \
+})
+
+/*
+ * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
+ * moment we always flush but we need to fix hpte_update and test if the
+ * optimisation is worth it.
+ */
+static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
+                                              unsigned long addr, pte_t *ptep)
+{
+        unsigned long old;
+
+        if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
+                return 0;
+        old = pte_update(mm, addr, ptep, _PAGE_DIRTY, 0);
+        return (old & _PAGE_DIRTY) != 0;
+}
+#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
+#define ptep_test_and_clear_dirty(__vma, __addr, __ptep)                   \
+({                                                                         \
+        int __r;                                                           \
+        __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
+        __r;                                                               \
+})
+
+#define __HAVE_ARCH_PTEP_SET_WRPROTECT
+static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
+                                      pte_t *ptep)
+{
+        unsigned long old;
+
+        if ((pte_val(*ptep) & _PAGE_RW) == 0)
+                return;
+        old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
+}
+
+/*
+ * We currently remove entries from the hashtable regardless of whether
+ * the entry was young or dirty. The generic routines only flush if the
+ * entry was young or dirty which is not good enough.
+ *
+ * We should be more intelligent about this but for the moment we override
+ * these functions and force a tlb flush unconditionally
+ */
+#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
+#define ptep_clear_flush_young(__vma, __address, __ptep)                \
+({                                                                      \
+        int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
+                                                  __ptep);              \
+        __young;                                                        \
+})
+
+#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
+#define ptep_clear_flush_dirty(__vma, __address, __ptep)                \
+({                                                                      \
+        int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
+                                                  __ptep);              \
+        __dirty;                                                        \
+})
+
+#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
+static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
+                                       unsigned long addr, pte_t *ptep)
+{
+        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
+        return __pte(old);
+}
+
+static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
+                             pte_t * ptep)
+{
+        pte_update(mm, addr, ptep, ~0UL, 0);
+}
+
+/*
+ * set_pte stores a linux PTE into the linux page table.
+ */
+static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
+                              pte_t *ptep, pte_t pte)
+{
+        if (pte_present(*ptep))
+                pte_clear(mm, addr, ptep);
+        pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
+        *ptep = pte;
+}
+
+/* Set the dirty and/or accessed bits atomically in a linux PTE, this
+ * function doesn't need to flush the hash entry
+ */
+#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
+static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
+{
+        unsigned long bits = pte_val(entry) &
+                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
+        unsigned long old, tmp;
+
+        __asm__ __volatile__(
+        "1:     ldarx   %0,0,%4\n\
+                andi.   %1,%0,%6\n\
+                bne-    1b \n\
+                or      %0,%3,%0\n\
+                stdcx.  %0,0,%4\n\
+                bne-    1b"
+        :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
+        :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
+        :"cc");
+}
+#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
+        do {                                                               \
+                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
+                flush_tlb_page_nohash(__vma, __address);                   \
+        } while(0)
+
+/*
+ * Macro to mark a page protection value as "uncacheable".
+ */
+#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
+
+struct file;
+extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
+                                     unsigned long size, pgprot_t vma_prot);
+#define __HAVE_PHYS_MEM_ACCESS_PROT
+
+#define __HAVE_ARCH_PTE_SAME
+#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
+
+#define pte_ERROR(e) \
+        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
+#define pmd_ERROR(e) \
+        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
+#define pgd_ERROR(e) \
+        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
+
+extern pgd_t swapper_pg_dir[];
+
+extern void paging_init(void);
+
+/* Encode and de-code a swap entry */
+#define __swp_type(entry)       (((entry).val >> 1) & 0x3f)
+#define __swp_offset(entry)     ((entry).val >> 8)
+#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
+#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
+#define __swp_entry_to_pte(x)   ((pte_t) { (x).val << PTE_RPN_SHIFT })
+#define pte_to_pgoff(pte)       (pte_val(pte) >> PTE_RPN_SHIFT)
+#define pgoff_to_pte(off)       ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
+#define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_RPN_SHIFT)
+
+/*
+ * kern_addr_valid is intended to indicate whether an address is a valid
+ * kernel address.  Most 32-bit archs define it as always true (like this)
+ * but most 64-bit archs actually perform a test.  What should we do here?
+ * The only use is in fs/ncpfs/dir.c
+ */
+#define kern_addr_valid(addr)   (1)
+
+#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
+                remap_pfn_range(vma, vaddr, pfn, size, prot)
+
+void pgtable_cache_init(void);
+
+/*
+ * find_linux_pte returns the address of a linux pte for a given
+ * effective address and directory.  If not found, it returns zero.
+ */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
+{
+        pgd_t *pg;
+        pud_t *pu;
+        pmd_t *pm;
+        pte_t *pt = NULL;
+
+        pg = pgdir + pgd_index(ea);
+        if (!pgd_none(*pg)) {
+                pu = pud_offset(pg, ea);
+                if (!pud_none(*pu)) {
+                        pm = pmd_offset(pu, ea);
+                        if (pmd_present(*pm))
+                                pt = pte_offset_kernel(pm, ea);
+                }
+        }
+        return pt;
+}
+
+#endif /* __ASSEMBLY__ */
+
+#endif /* _ASM_POWERPC_PGTABLE_PPC64_H_ */
diff --git a/include/asm-powerpc/pgtable.h b/include/asm-powerpc/pgtable.h
index 19edb6982b81..78bf4ae712a6 100644
--- a/include/asm-powerpc/pgtable.h
+++ b/include/asm-powerpc/pgtable.h
@@ -2,502 +2,15 @@
 #define _ASM_POWERPC_PGTABLE_H
 #ifdef __KERNEL__
 
-#ifndef CONFIG_PPC64
-#include <asm-ppc/pgtable.h>
+#if defined(CONFIG_PPC64)
+#  include <asm/pgtable-ppc64.h>
 #else
-
-/*
- * This file contains the functions and defines necessary to modify and use
- * the ppc64 hashed page table.
- */
-
-#ifndef __ASSEMBLY__
-#include <linux/stddef.h>
-#include <asm/processor.h>              /* For TASK_SIZE */
-#include <asm/mmu.h>
-#include <asm/page.h>
-#include <asm/tlbflush.h>
-struct mm_struct;
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_PPC_64K_PAGES
-#include <asm/pgtable-64k.h>
-#else
-#include <asm/pgtable-4k.h>
-#endif
-
-#define FIRST_USER_ADDRESS      0
-
-/*
- * Size of EA range mapped by our pagetables.
- */
-#define PGTABLE_EADDR_SIZE (PTE_INDEX_SIZE + PMD_INDEX_SIZE + \
-                            PUD_INDEX_SIZE + PGD_INDEX_SIZE + PAGE_SHIFT)
-#define PGTABLE_RANGE (1UL << PGTABLE_EADDR_SIZE)
-
-#if TASK_SIZE_USER64 > PGTABLE_RANGE
-#error TASK_SIZE_USER64 exceeds pagetable range
-#endif
-
-#if TASK_SIZE_USER64 > (1UL << (USER_ESID_BITS + SID_SHIFT))
-#error TASK_SIZE_USER64 exceeds user VSID range
+#  include <asm/pgtable-ppc32.h>
 #endif
 
-/*
- * Define the address range of the vmalloc VM area.
- */
-#define VMALLOC_START ASM_CONST(0xD000000000000000)
-#define VMALLOC_SIZE  ASM_CONST(0x80000000000)
-#define VMALLOC_END   (VMALLOC_START + VMALLOC_SIZE)
-
-/*
- * Define the address range of the imalloc VM area.
- */
-#define PHBS_IO_BASE    VMALLOC_END
-#define IMALLOC_BASE    (PHBS_IO_BASE + 0x80000000ul)   /* Reserve 2 gigs for PHBs */
-#define IMALLOC_END     (VMALLOC_START + PGTABLE_RANGE)
-
-/*
- * Region IDs
- */
-#define REGION_SHIFT            60UL
-#define REGION_MASK             (0xfUL << REGION_SHIFT)
-#define REGION_ID(ea)           (((unsigned long)(ea)) >> REGION_SHIFT)
-
-#define VMALLOC_REGION_ID       (REGION_ID(VMALLOC_START))
-#define KERNEL_REGION_ID        (REGION_ID(PAGE_OFFSET))
-#define USER_REGION_ID          (0UL)
-
-/*
- * Common bits in a linux-style PTE.  These match the bits in the
- * (hardware-defined) PowerPC PTE as closely as possible. Additional
- * bits may be defined in pgtable-*.h
- */
-#define _PAGE_PRESENT   0x0001 /* software: pte contains a translation */
-#define _PAGE_USER      0x0002 /* matches one of the PP bits */
-#define _PAGE_FILE      0x0002 /* (!present only) software: pte holds file offset */
-#define _PAGE_EXEC      0x0004 /* No execute on POWER4 and newer (we invert) */
-#define _PAGE_GUARDED   0x0008
-#define _PAGE_COHERENT  0x0010 /* M: enforce memory coherence (SMP systems) */
-#define _PAGE_NO_CACHE  0x0020 /* I: cache inhibit */
-#define _PAGE_WRITETHRU 0x0040 /* W: cache write-through */
-#define _PAGE_DIRTY     0x0080 /* C: page changed */
-#define _PAGE_ACCESSED  0x0100 /* R: page referenced */
-#define _PAGE_RW        0x0200 /* software: user write access allowed */
-#define _PAGE_HASHPTE   0x0400 /* software: pte has an associated HPTE */
-#define _PAGE_BUSY      0x0800 /* software: PTE & hash are busy */ 
-
-#define _PAGE_BASE      (_PAGE_PRESENT | _PAGE_ACCESSED | _PAGE_COHERENT)
-
-#define _PAGE_WRENABLE  (_PAGE_RW | _PAGE_DIRTY)
-
-/* __pgprot defined in asm-powerpc/page.h */
-#define PAGE_NONE       __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED)
-
-#define PAGE_SHARED     __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER)
-#define PAGE_SHARED_X   __pgprot(_PAGE_BASE | _PAGE_RW | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_COPY       __pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_COPY_X     __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_READONLY   __pgprot(_PAGE_BASE | _PAGE_USER)
-#define PAGE_READONLY_X __pgprot(_PAGE_BASE | _PAGE_USER | _PAGE_EXEC)
-#define PAGE_KERNEL     __pgprot(_PAGE_BASE | _PAGE_WRENABLE)
-#define PAGE_KERNEL_CI  __pgprot(_PAGE_PRESENT | _PAGE_ACCESSED | \
-                               _PAGE_WRENABLE | _PAGE_NO_CACHE | _PAGE_GUARDED)
-#define PAGE_KERNEL_EXEC __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_EXEC)
-
-#define PAGE_AGP        __pgprot(_PAGE_BASE | _PAGE_WRENABLE | _PAGE_NO_CACHE)
-#define HAVE_PAGE_AGP
-
-/* PTEIDX nibble */
-#define _PTEIDX_SECONDARY       0x8
-#define _PTEIDX_GROUP_IX        0x7
-
-
-/*
- * POWER4 and newer have per page execute protection, older chips can only
- * do this on a segment (256MB) basis.
- *
- * Also, write permissions imply read permissions.
- * This is the closest we can get..
- *
- * Note due to the way vm flags are laid out, the bits are XWR
- */
-#define __P000  PAGE_NONE
-#define __P001  PAGE_READONLY
-#define __P010  PAGE_COPY
-#define __P011  PAGE_COPY
-#define __P100  PAGE_READONLY_X
-#define __P101  PAGE_READONLY_X
-#define __P110  PAGE_COPY_X
-#define __P111  PAGE_COPY_X
-
-#define __S000  PAGE_NONE
-#define __S001  PAGE_READONLY
-#define __S010  PAGE_SHARED
-#define __S011  PAGE_SHARED
-#define __S100  PAGE_READONLY_X
-#define __S101  PAGE_READONLY_X
-#define __S110  PAGE_SHARED_X
-#define __S111  PAGE_SHARED_X
-
 #ifndef __ASSEMBLY__
-
-/*
- * ZERO_PAGE is a global shared page that is always zero: used
- * for zero-mapped memory areas etc..
- */
-extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
-#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
-#endif /* __ASSEMBLY__ */
-
-#ifdef CONFIG_HUGETLB_PAGE
-
-#define HAVE_ARCH_UNMAPPED_AREA
-#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
-
-#endif
-
-#ifndef __ASSEMBLY__
-
-/*
- * Conversion functions: convert a page and protection to a page entry,
- * and a page entry and page directory to the page they refer to.
- *
- * mk_pte takes a (struct page *) as input
- */
-#define mk_pte(page, pgprot)    pfn_pte(page_to_pfn(page), (pgprot))
-
-static inline pte_t pfn_pte(unsigned long pfn, pgprot_t pgprot)
-{
-        pte_t pte;
-
-
-        pte_val(pte) = (pfn << PTE_RPN_SHIFT) | pgprot_val(pgprot);
-        return pte;
-}
-
-#define pte_modify(_pte, newprot) \
-  (__pte((pte_val(_pte) & _PAGE_CHG_MASK) | pgprot_val(newprot)))
-
-#define pte_none(pte)           ((pte_val(pte) & ~_PAGE_HPTEFLAGS) == 0)
-#define pte_present(pte)        (pte_val(pte) & _PAGE_PRESENT)
-
-/* pte_clear moved to later in this file */
-
-#define pte_pfn(x)              ((unsigned long)((pte_val(x)>>PTE_RPN_SHIFT)))
-#define pte_page(x)             pfn_to_page(pte_pfn(x))
-
-#define PMD_BAD_BITS            (PTE_TABLE_SIZE-1)
-#define PUD_BAD_BITS            (PMD_TABLE_SIZE-1)
-
-#define pmd_set(pmdp, pmdval)   (pmd_val(*(pmdp)) = (pmdval))
-#define pmd_none(pmd)           (!pmd_val(pmd))
-#define pmd_bad(pmd)            (!is_kernel_addr(pmd_val(pmd)) \
-                                 || (pmd_val(pmd) & PMD_BAD_BITS))
-#define pmd_present(pmd)        (pmd_val(pmd) != 0)
-#define pmd_clear(pmdp)         (pmd_val(*(pmdp)) = 0)
-#define pmd_page_vaddr(pmd)     (pmd_val(pmd) & ~PMD_MASKED_BITS)
-#define pmd_page(pmd)           virt_to_page(pmd_page_vaddr(pmd))
-
-#define pud_set(pudp, pudval)   (pud_val(*(pudp)) = (pudval))
-#define pud_none(pud)           (!pud_val(pud))
-#define pud_bad(pud)            (!is_kernel_addr(pud_val(pud)) \
-                                 || (pud_val(pud) & PUD_BAD_BITS))
-#define pud_present(pud)        (pud_val(pud) != 0)
-#define pud_clear(pudp)         (pud_val(*(pudp)) = 0)
-#define pud_page_vaddr(pud)     (pud_val(pud) & ~PUD_MASKED_BITS)
-#define pud_page(pud)           virt_to_page(pud_page_vaddr(pud))
-
-#define pgd_set(pgdp, pudp)     ({pgd_val(*(pgdp)) = (unsigned long)(pudp);})
-
-/* 
- * Find an entry in a page-table-directory.  We combine the address region 
- * (the high order N bits) and the pgd portion of the address.
- */
-/* to avoid overflow in free_pgtables we don't use PTRS_PER_PGD here */
-#define pgd_index(address) (((address) >> (PGDIR_SHIFT)) & 0x1ff)
-
-#define pgd_offset(mm, address)  ((mm)->pgd + pgd_index(address))
-
-#define pmd_offset(pudp,addr) \
-  (((pmd_t *) pud_page_vaddr(*(pudp))) + (((addr) >> PMD_SHIFT) & (PTRS_PER_PMD - 1)))
-
-#define pte_offset_kernel(dir,addr) \
-  (((pte_t *) pmd_page_vaddr(*(dir))) + (((addr) >> PAGE_SHIFT) & (PTRS_PER_PTE - 1)))
-
-#define pte_offset_map(dir,addr)        pte_offset_kernel((dir), (addr))
-#define pte_offset_map_nested(dir,addr) pte_offset_kernel((dir), (addr))
-#define pte_unmap(pte)                  do { } while(0)
-#define pte_unmap_nested(pte)           do { } while(0)
-
-/* to find an entry in a kernel page-table-directory */
-/* This now only contains the vmalloc pages */
-#define pgd_offset_k(address) pgd_offset(&init_mm, address)
-
-/*
- * The following only work if pte_present() is true.
- * Undefined behaviour if not..
- */
-static inline int pte_read(pte_t pte)  { return pte_val(pte) & _PAGE_USER;}
-static inline int pte_write(pte_t pte) { return pte_val(pte) & _PAGE_RW;}
-static inline int pte_exec(pte_t pte)  { return pte_val(pte) & _PAGE_EXEC;}
-static inline int pte_dirty(pte_t pte) { return pte_val(pte) & _PAGE_DIRTY;}
-static inline int pte_young(pte_t pte) { return pte_val(pte) & _PAGE_ACCESSED;}
-static inline int pte_file(pte_t pte) { return pte_val(pte) & _PAGE_FILE;}
-
-static inline void pte_uncache(pte_t pte) { pte_val(pte) |= _PAGE_NO_CACHE; }
-static inline void pte_cache(pte_t pte)   { pte_val(pte) &= ~_PAGE_NO_CACHE; }
-
-static inline pte_t pte_rdprotect(pte_t pte) {
-        pte_val(pte) &= ~_PAGE_USER; return pte; }
-static inline pte_t pte_exprotect(pte_t pte) {
-        pte_val(pte) &= ~_PAGE_EXEC; return pte; }
-static inline pte_t pte_wrprotect(pte_t pte) {
-        pte_val(pte) &= ~(_PAGE_RW); return pte; }
-static inline pte_t pte_mkclean(pte_t pte) {
-        pte_val(pte) &= ~(_PAGE_DIRTY); return pte; }
-static inline pte_t pte_mkold(pte_t pte) {
-        pte_val(pte) &= ~_PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkread(pte_t pte) {
-        pte_val(pte) |= _PAGE_USER; return pte; }
-static inline pte_t pte_mkexec(pte_t pte) {
-        pte_val(pte) |= _PAGE_USER | _PAGE_EXEC; return pte; }
-static inline pte_t pte_mkwrite(pte_t pte) {
-        pte_val(pte) |= _PAGE_RW; return pte; }
-static inline pte_t pte_mkdirty(pte_t pte) {
-        pte_val(pte) |= _PAGE_DIRTY; return pte; }
-static inline pte_t pte_mkyoung(pte_t pte) {
-        pte_val(pte) |= _PAGE_ACCESSED; return pte; }
-static inline pte_t pte_mkhuge(pte_t pte) {
-        return pte; }
-
-/* Atomic PTE updates */
-static inline unsigned long pte_update(struct mm_struct *mm,
-                                       unsigned long addr,
-                                       pte_t *ptep, unsigned long clr,
-                                       int huge)
-{
-        unsigned long old, tmp;
-
-        __asm__ __volatile__(
-        "1:     ldarx   %0,0,%3         # pte_update\n\
-        andi.   %1,%0,%6\n\
-        bne-    1b \n\
-        andc    %1,%0,%4 \n\
-        stdcx.  %1,0,%3 \n\
-        bne-    1b"
-        : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
-        : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY)
-        : "cc" );
-
-        if (old & _PAGE_HASHPTE)
-                hpte_need_flush(mm, addr, ptep, old, huge);
-        return old;
-}
-
-static inline int __ptep_test_and_clear_young(struct mm_struct *mm,
-                                              unsigned long addr, pte_t *ptep)
-{
-        unsigned long old;
-
-        if ((pte_val(*ptep) & (_PAGE_ACCESSED | _PAGE_HASHPTE)) == 0)
-                return 0;
-        old = pte_update(mm, addr, ptep, _PAGE_ACCESSED, 0);
-        return (old & _PAGE_ACCESSED) != 0;
-}
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_YOUNG
-#define ptep_test_and_clear_young(__vma, __addr, __ptep)                   \
-({                                                                         \
-        int __r;                                                           \
-        __r = __ptep_test_and_clear_young((__vma)->vm_mm, __addr, __ptep); \
-        __r;                                                               \
-})
-
-/*
- * On RW/DIRTY bit transitions we can avoid flushing the hpte. For the
- * moment we always flush but we need to fix hpte_update and test if the
- * optimisation is worth it.
- */
-static inline int __ptep_test_and_clear_dirty(struct mm_struct *mm,
-                                              unsigned long addr, pte_t *ptep)
-{
-        unsigned long old;
-
-        if ((pte_val(*ptep) & _PAGE_DIRTY) == 0)
-                return 0;
-        old = pte_update(mm, addr, ptep, _PAGE_DIRTY, 0);
-        return (old & _PAGE_DIRTY) != 0;
-}
-#define __HAVE_ARCH_PTEP_TEST_AND_CLEAR_DIRTY
-#define ptep_test_and_clear_dirty(__vma, __addr, __ptep)                   \
-({                                                                         \
-        int __r;                                                           \
-        __r = __ptep_test_and_clear_dirty((__vma)->vm_mm, __addr, __ptep); \
-        __r;                                                               \
-})
-
-#define __HAVE_ARCH_PTEP_SET_WRPROTECT
-static inline void ptep_set_wrprotect(struct mm_struct *mm, unsigned long addr,
-                                      pte_t *ptep)
-{
-        unsigned long old;
-
-        if ((pte_val(*ptep) & _PAGE_RW) == 0)
-                return;
-        old = pte_update(mm, addr, ptep, _PAGE_RW, 0);
-}
-
-/*
- * We currently remove entries from the hashtable regardless of whether
- * the entry was young or dirty. The generic routines only flush if the
- * entry was young or dirty which is not good enough.
- *
- * We should be more intelligent about this but for the moment we override
- * these functions and force a tlb flush unconditionally
- */
-#define __HAVE_ARCH_PTEP_CLEAR_YOUNG_FLUSH
-#define ptep_clear_flush_young(__vma, __address, __ptep)                \
-({                                                                      \
-        int __young = __ptep_test_and_clear_young((__vma)->vm_mm, __address, \
-                                                  __ptep);              \
-        __young;                                                        \
-})
-
-#define __HAVE_ARCH_PTEP_CLEAR_DIRTY_FLUSH
-#define ptep_clear_flush_dirty(__vma, __address, __ptep)                \
-({                                                                      \
-        int __dirty = __ptep_test_and_clear_dirty((__vma)->vm_mm, __address, \
-                                                  __ptep);              \
-        __dirty;                                                        \
-})
-
-#define __HAVE_ARCH_PTEP_GET_AND_CLEAR
-static inline pte_t ptep_get_and_clear(struct mm_struct *mm,
-                                       unsigned long addr, pte_t *ptep)
-{
-        unsigned long old = pte_update(mm, addr, ptep, ~0UL, 0);
-        return __pte(old);
-}
-
-static inline void pte_clear(struct mm_struct *mm, unsigned long addr,
-                             pte_t * ptep)
-{
-        pte_update(mm, addr, ptep, ~0UL, 0);
-}
-
-/*
- * set_pte stores a linux PTE into the linux page table.
- */
-static inline void set_pte_at(struct mm_struct *mm, unsigned long addr,
-                              pte_t *ptep, pte_t pte)
-{
-        if (pte_present(*ptep))
-                pte_clear(mm, addr, ptep);
-        pte = __pte(pte_val(pte) & ~_PAGE_HPTEFLAGS);
-        *ptep = pte;
-}
-
-/* Set the dirty and/or accessed bits atomically in a linux PTE, this
- * function doesn't need to flush the hash entry
- */
-#define __HAVE_ARCH_PTEP_SET_ACCESS_FLAGS
-static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry, int dirty)
-{
-        unsigned long bits = pte_val(entry) &
-                (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
-        unsigned long old, tmp;
-
-        __asm__ __volatile__(
-        "1:     ldarx   %0,0,%4\n\
-                andi.   %1,%0,%6\n\
-                bne-    1b \n\
-                or      %0,%3,%0\n\
-                stdcx.  %0,0,%4\n\
-                bne-    1b"
-        :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
-        :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
-        :"cc");
-}
-#define  ptep_set_access_flags(__vma, __address, __ptep, __entry, __dirty) \
-        do {                                                               \
-                __ptep_set_access_flags(__ptep, __entry, __dirty);         \
-                flush_tlb_page_nohash(__vma, __address);                   \
-        } while(0)
-
-/*
- * Macro to mark a page protection value as "uncacheable".
- */
-#define pgprot_noncached(prot)  (__pgprot(pgprot_val(prot) | _PAGE_NO_CACHE | _PAGE_GUARDED))
-
-struct file;
-extern pgprot_t phys_mem_access_prot(struct file *file, unsigned long pfn,
-                                     unsigned long size, pgprot_t vma_prot);
-#define __HAVE_PHYS_MEM_ACCESS_PROT
-
-#define __HAVE_ARCH_PTE_SAME
-#define pte_same(A,B)   (((pte_val(A) ^ pte_val(B)) & ~_PAGE_HPTEFLAGS) == 0)
-
-#define pte_ERROR(e) \
-        printk("%s:%d: bad pte %08lx.\n", __FILE__, __LINE__, pte_val(e))
-#define pmd_ERROR(e) \
-        printk("%s:%d: bad pmd %08lx.\n", __FILE__, __LINE__, pmd_val(e))
-#define pgd_ERROR(e) \
-        printk("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
-
-extern pgd_t swapper_pg_dir[];
-
-extern void paging_init(void);
-
-/* Encode and de-code a swap entry */
-#define __swp_type(entry)       (((entry).val >> 1) & 0x3f)
-#define __swp_offset(entry)     ((entry).val >> 8)
-#define __swp_entry(type, offset) ((swp_entry_t){((type)<< 1)|((offset)<<8)})
-#define __pte_to_swp_entry(pte) ((swp_entry_t){pte_val(pte) >> PTE_RPN_SHIFT})
-#define __swp_entry_to_pte(x)   ((pte_t) { (x).val << PTE_RPN_SHIFT })
-#define pte_to_pgoff(pte)       (pte_val(pte) >> PTE_RPN_SHIFT)
-#define pgoff_to_pte(off)       ((pte_t) {((off) << PTE_RPN_SHIFT)|_PAGE_FILE})
-#define PTE_FILE_MAX_BITS       (BITS_PER_LONG - PTE_RPN_SHIFT)
-
-/*
- * kern_addr_valid is intended to indicate whether an address is a valid
- * kernel address.  Most 32-bit archs define it as always true (like this)
- * but most 64-bit archs actually perform a test.  What should we do here?
- * The only use is in fs/ncpfs/dir.c
- */
-#define kern_addr_valid(addr)   (1)
-
-#define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
-                remap_pfn_range(vma, vaddr, pfn, size, prot)
-
-void pgtable_cache_init(void);
-
-/*
- * find_linux_pte returns the address of a linux pte for a given 
- * effective address and directory.  If not found, it returns zero.
- */static inline pte_t *find_linux_pte(pgd_t *pgdir, unsigned long ea)
-{
-        pgd_t *pg;
-        pud_t *pu;
-        pmd_t *pm;
-        pte_t *pt = NULL;
-
-        pg = pgdir + pgd_index(ea);
-        if (!pgd_none(*pg)) {
-                pu = pud_offset(pg, ea);
-                if (!pud_none(*pu)) {
-                        pm = pmd_offset(pu, ea);
-                        if (pmd_present(*pm))
-                                pt = pte_offset_kernel(pm, ea);
-                }
-        }
-        return pt;
-}
-
-
 #include <asm-generic/pgtable.h>
-
 #endif /* __ASSEMBLY__ */
 
-#endif /* CONFIG_PPC64 */
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_PGTABLE_H */
diff --git a/include/asm-powerpc/pmac_feature.h b/include/asm-powerpc/pmac_feature.h
index d3599cc9aa74..d43d91beba9b 100644
--- a/include/asm-powerpc/pmac_feature.h
+++ b/include/asm-powerpc/pmac_feature.h
@@ -146,7 +146,7 @@ struct device_node;
 static inline long pmac_call_feature(int selector, struct device_node* node,
                                         long param, long value)
 {
-        if (!ppc_md.feature_call)
+        if (!ppc_md.feature_call || !machine_is(powermac))
                 return -ENODEV;
         return ppc_md.feature_call(selector, node, param, value);
 }
diff --git a/include/asm-powerpc/prom.h b/include/asm-powerpc/prom.h
index ec400f608e16..6845af93ba91 100644
--- a/include/asm-powerpc/prom.h
+++ b/include/asm-powerpc/prom.h
@@ -20,7 +20,6 @@
 #include <linux/platform_device.h>
 #include <asm/irq.h>
 #include <asm/atomic.h>
-#include <asm/io.h>
 
 /* Definitions used by the flattened device tree */
 #define OF_DT_HEADER            0xd00dfeed      /* marker */
@@ -334,30 +333,17 @@ extern int of_irq_map_one(struct device_node *device, int index,
 struct pci_dev;
 extern int of_irq_map_pci(struct pci_dev *pdev, struct of_irq *out_irq);
 
-static inline int of_irq_to_resource(struct device_node *dev, int index, struct resource *r)
-{
-        int irq = irq_of_parse_and_map(dev, index);
-
-        /* Only dereference the resource if both the
-         * resource and the irq are valid. */
-        if (r && irq != NO_IRQ) {
-                r->start = r->end = irq;
-                r->flags = IORESOURCE_IRQ;
-        }
-
-        return irq;
-}
-
-static inline void __iomem *of_iomap(struct device_node *np, int index)
-{
-        struct resource res;
-
-        if (of_address_to_resource(np, index, &res))
-                return NULL;
-
-        return ioremap(res.start, 1 + res.end - res.start);
-}
+extern int of_irq_to_resource(struct device_node *dev, int index,
+                        struct resource *r);
 
+/**
+ * of_iomap - Maps the memory mapped IO for a given device_node
+ * @device:     the device whose io range will be mapped
+ * @index:      index of the io range
+ *
+ * Returns a pointer to the mapped memory
+ */
+extern void __iomem *of_iomap(struct device_node *device, int index);
 
 #endif /* __KERNEL__ */
 #endif /* _POWERPC_PROM_H */
diff --git a/include/asm-powerpc/ps3.h b/include/asm-powerpc/ps3.h
index 821581a8b643..13c372df99e8 100644
--- a/include/asm-powerpc/ps3.h
+++ b/include/asm-powerpc/ps3.h
@@ -167,26 +167,31 @@ enum ps3_cpu_binding {
         PS3_BINDING_CPU_1 = 1,
 };
 
-int ps3_alloc_io_irq(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
+int ps3_virq_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
         unsigned int *virq);
-int ps3_free_io_irq(unsigned int virq);
-int ps3_alloc_event_irq(enum ps3_cpu_binding cpu, unsigned int *virq);
-int ps3_free_event_irq(unsigned int virq);
+int ps3_virq_destroy(unsigned int virq);
+int ps3_irq_plug_setup(enum ps3_cpu_binding cpu, unsigned long outlet,
+        unsigned int *virq);
+int ps3_irq_plug_destroy(unsigned int virq);
+int ps3_event_receive_port_setup(enum ps3_cpu_binding cpu, unsigned int *virq);
+int ps3_event_receive_port_destroy(unsigned int virq);
 int ps3_send_event_locally(unsigned int virq);
-int ps3_connect_event_irq(enum ps3_cpu_binding cpu,
-        const struct ps3_device_id *did, unsigned int interrupt_id,
+
+int ps3_io_irq_setup(enum ps3_cpu_binding cpu, unsigned int interrupt_id,
         unsigned int *virq);
-int ps3_disconnect_event_irq(const struct ps3_device_id *did,
-        unsigned int interrupt_id, unsigned int virq);
-int ps3_alloc_vuart_irq(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
+int ps3_io_irq_destroy(unsigned int virq);
+int ps3_vuart_irq_setup(enum ps3_cpu_binding cpu, void* virt_addr_bmp,
         unsigned int *virq);
-int ps3_free_vuart_irq(unsigned int virq);
-int ps3_alloc_spe_irq(enum ps3_cpu_binding cpu, unsigned long spe_id,
+int ps3_vuart_irq_destroy(unsigned int virq);
+int ps3_spe_irq_setup(enum ps3_cpu_binding cpu, unsigned long spe_id,
         unsigned int class, unsigned int *virq);
-int ps3_free_spe_irq(unsigned int virq);
-int ps3_alloc_irq(enum ps3_cpu_binding cpu, unsigned long outlet,
+int ps3_spe_irq_destroy(unsigned int virq);
+
+int ps3_sb_event_receive_port_setup(enum ps3_cpu_binding cpu,
+        const struct ps3_device_id *did, unsigned int interrupt_id,
         unsigned int *virq);
-int ps3_free_irq(unsigned int virq);
+int ps3_sb_event_receive_port_destroy(const struct ps3_device_id *did,
+        unsigned int interrupt_id, unsigned int virq);
 
 /* lv1 result codes */
 
diff --git a/include/asm-powerpc/suspend.h b/include/asm-powerpc/suspend.h
new file mode 100644
index 000000000000..cbf2c9404c37
--- /dev/null
+++ b/include/asm-powerpc/suspend.h
@@ -0,0 +1,9 @@
+#ifndef __ASM_POWERPC_SUSPEND_H
+#define __ASM_POWERPC_SUSPEND_H
+
+static inline int arch_prepare_suspend(void) { return 0; }
+
+void save_processor_state(void);
+void restore_processor_state(void);
+
+#endif /* __ASM_POWERPC_SUSPEND_H */
diff --git a/include/asm-powerpc/system.h b/include/asm-powerpc/system.h
index d3e0906ff2bc..09621f611dbc 100644
--- a/include/asm-powerpc/system.h
+++ b/include/asm-powerpc/system.h
@@ -7,7 +7,6 @@
 #include <linux/kernel.h>
 
 #include <asm/hw_irq.h>
-#include <asm/atomic.h>
 
 /*
  * Memory barrier.
@@ -227,6 +226,29 @@ __xchg_u32(volatile void *p, unsigned long val)
         return prev;
 }
 
+/*
+ * Atomic exchange
+ *
+ * Changes the memory location '*ptr' to be val and returns
+ * the previous value stored there.
+ */
+static __inline__ unsigned long
+__xchg_u32_local(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+"1:     lwarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %3,0,%2 \n\
+        bne-    1b"
+        : "=&r" (prev), "+m" (*(volatile unsigned int *)p)
+        : "r" (p), "r" (val)
+        : "cc", "memory");
+
+        return prev;
+}
+
 #ifdef CONFIG_PPC64
 static __inline__ unsigned long
 __xchg_u64(volatile void *p, unsigned long val)
@@ -246,6 +268,23 @@ __xchg_u64(volatile void *p, unsigned long val)
 
         return prev;
 }
+
+static __inline__ unsigned long
+__xchg_u64_local(volatile void *p, unsigned long val)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__(
+"1:     ldarx   %0,0,%2 \n"
+        PPC405_ERR77(0,%2)
+"       stdcx.  %3,0,%2 \n\
+        bne-    1b"
+        : "=&r" (prev), "+m" (*(volatile unsigned long *)p)
+        : "r" (p), "r" (val)
+        : "cc", "memory");
+
+        return prev;
+}
 #endif
 
 /*
@@ -269,13 +308,32 @@ __xchg(volatile void *ptr, unsigned long x, unsigned int size)
         return x;
 }
 
+static __inline__ unsigned long
+__xchg_local(volatile void *ptr, unsigned long x, unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __xchg_u32_local(ptr, x);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __xchg_u64_local(ptr, x);
+#endif
+        }
+        __xchg_called_with_bad_pointer();
+        return x;
+}
 #define xchg(ptr,x)                                                          \
   ({                                                                         \
      __typeof__(*(ptr)) _x_ = (x);                                           \
      (__typeof__(*(ptr))) __xchg((ptr), (unsigned long)_x_, sizeof(*(ptr))); \
   })
 
-#define tas(ptr) (xchg((ptr),1))
+#define xchg_local(ptr,x)                                                    \
+  ({                                                                         \
+     __typeof__(*(ptr)) _x_ = (x);                                           \
+     (__typeof__(*(ptr))) __xchg_local((ptr),                                \
+                (unsigned long)_x_, sizeof(*(ptr)));                         \
+  })
 
 /*
  * Compare and exchange - if *p == old, set it to new,
@@ -306,6 +364,28 @@ __cmpxchg_u32(volatile unsigned int *p, unsigned long old, unsigned long new)
         return prev;
 }
 
+static __inline__ unsigned long
+__cmpxchg_u32_local(volatile unsigned int *p, unsigned long old,
+                        unsigned long new)
+{
+        unsigned int prev;
+
+        __asm__ __volatile__ (
+"1:     lwarx   %0,0,%2         # __cmpxchg_u32\n\
+        cmpw    0,%0,%3\n\
+        bne-    2f\n"
+        PPC405_ERR77(0,%2)
+"       stwcx.  %4,0,%2\n\
+        bne-    1b"
+        "\n\
+2:"
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
+        : "cc", "memory");
+
+        return prev;
+}
+
 #ifdef CONFIG_PPC64
 static __inline__ unsigned long
 __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
@@ -328,6 +408,27 @@ __cmpxchg_u64(volatile unsigned long *p, unsigned long old, unsigned long new)
 
         return prev;
 }
+
+static __inline__ unsigned long
+__cmpxchg_u64_local(volatile unsigned long *p, unsigned long old,
+                        unsigned long new)
+{
+        unsigned long prev;
+
+        __asm__ __volatile__ (
+"1:     ldarx   %0,0,%2         # __cmpxchg_u64\n\
+        cmpd    0,%0,%3\n\
+        bne-    2f\n\
+        stdcx.  %4,0,%2\n\
+        bne-    1b"
+        "\n\
+2:"
+        : "=&r" (prev), "+m" (*p)
+        : "r" (p), "r" (old), "r" (new)
+        : "cc", "memory");
+
+        return prev;
+}
 #endif
 
 /* This function doesn't exist, so you'll get a linker error
@@ -350,6 +451,22 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
         return old;
 }
 
+static __inline__ unsigned long
+__cmpxchg_local(volatile void *ptr, unsigned long old, unsigned long new,
+          unsigned int size)
+{
+        switch (size) {
+        case 4:
+                return __cmpxchg_u32_local(ptr, old, new);
+#ifdef CONFIG_PPC64
+        case 8:
+                return __cmpxchg_u64_local(ptr, old, new);
+#endif
+        }
+        __cmpxchg_called_with_bad_pointer();
+        return old;
+}
+
 #define cmpxchg(ptr,o,n)                                                 \
   ({                                                                     \
      __typeof__(*(ptr)) _o_ = (o);                                       \
@@ -358,6 +475,15 @@ __cmpxchg(volatile void *ptr, unsigned long old, unsigned long new,
                                     (unsigned long)_n_, sizeof(*(ptr))); \
   })
 
+
+#define cmpxchg_local(ptr,o,n)                                           \
+  ({                                                                     \
+     __typeof__(*(ptr)) _o_ = (o);                                       \
+     __typeof__(*(ptr)) _n_ = (n);                                       \
+     (__typeof__(*(ptr))) __cmpxchg_local((ptr), (unsigned long)_o_,     \
+                                    (unsigned long)_n_, sizeof(*(ptr))); \
+  })
+
 #ifdef CONFIG_PPC64
 /*
  * We handle most unaligned accesses in hardware. On the other hand 
diff --git a/include/asm-powerpc/tsi108.h b/include/asm-powerpc/tsi108.h
index 4e95d153be84..f8b60793b7a9 100644
--- a/include/asm-powerpc/tsi108.h
+++ b/include/asm-powerpc/tsi108.h
@@ -68,8 +68,17 @@
 #define TSI108_PB_ERRCS_ES              (1 << 1)
 #define TSI108_PB_ISR_PBS_RD_ERR        (1 << 8)
 
-#define TSI108_PCI_CFG_BASE_PHYS        (0xfb000000)
 #define TSI108_PCI_CFG_SIZE             (0x01000000)
+
+/*
+ * PHY Configuration Options
+ *
+ * Specify "bcm54xx" in the compatible property of your device tree phy
+ * nodes if your board uses the Broadcom PHYs
+ */
+#define TSI108_PHY_MV88E        0       /* Marvel 88Exxxx PHY */
+#define TSI108_PHY_BCM54XX      1       /* Broardcom BCM54xx PHY */
+
 /* Global variables */
 
 extern u32 tsi108_pci_cfg_base;
@@ -93,6 +102,7 @@ typedef struct {
         u16 phy;                /* phy address */
         u16 irq_num;            /* irq number */
         u8 mac_addr[6];         /* phy mac address */
+        u16 phy_type;   /* type of phy on board */
 } hw_info;
 
 extern u32 get_vir_csrbase(void);
diff --git a/include/asm-powerpc/tsi108_pci.h b/include/asm-powerpc/tsi108_pci.h
new file mode 100644
index 000000000000..a9f92f73232c
--- /dev/null
+++ b/include/asm-powerpc/tsi108_pci.h
@@ -0,0 +1,45 @@
+/*
+ * Copyright 2007 IBM Corp
+ *
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of
+ * the License, or (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * MA 02111-1307 USA
+ */
+
+#ifndef _ASM_PPC_TSI108_PCI_H
+#define _ASM_PPC_TSI108_PCI_H
+
+#include <asm/tsi108.h>
+
+/* Register definitions */
+#define TSI108_PCI_P2O_BAR0 (TSI108_PCI_OFFSET + 0x10)
+#define TSI108_PCI_P2O_BAR0_UPPER (TSI108_PCI_OFFSET + 0x14)
+#define TSI108_PCI_P2O_BAR2 (TSI108_PCI_OFFSET + 0x18)
+#define TSI108_PCI_P2O_BAR2_UPPER (TSI108_PCI_OFFSET + 0x1c)
+#define TSI108_PCI_P2O_PAGE_SIZES (TSI108_PCI_OFFSET + 0x4c)
+#define TSI108_PCI_PFAB_BAR0 (TSI108_PCI_OFFSET + 0x204)
+#define TSI108_PCI_PFAB_BAR0_UPPER (TSI108_PCI_OFFSET + 0x208)
+#define TSI108_PCI_PFAB_IO (TSI108_PCI_OFFSET + 0x20c)
+#define TSI108_PCI_PFAB_IO_UPPER (TSI108_PCI_OFFSET + 0x210)
+#define TSI108_PCI_PFAB_MEM32 (TSI108_PCI_OFFSET + 0x214)
+#define TSI108_PCI_PFAB_PFM3 (TSI108_PCI_OFFSET + 0x220)
+#define TSI108_PCI_PFAB_PFM4 (TSI108_PCI_OFFSET + 0x230)
+
+extern int tsi108_setup_pci(struct device_node *dev, u32 cfg_phys, int primary);
+extern void tsi108_pci_int_init(struct device_node *node);
+extern void tsi108_irq_cascade(unsigned int irq, struct irq_desc *desc);
+extern void tsi108_clear_pci_cfg_error(void);
+
+#endif                          /*  _ASM_PPC_TSI108_PCI_H */
diff --git a/include/asm-powerpc/udbg.h b/include/asm-powerpc/udbg.h
index d03d8557f706..ce9d82fb7b68 100644
--- a/include/asm-powerpc/udbg.h
+++ b/include/asm-powerpc/udbg.h
@@ -47,6 +47,7 @@ extern void __init udbg_init_rtas_panel(void);
 extern void __init udbg_init_rtas_console(void);
 extern void __init udbg_init_debug_beat(void);
 extern void __init udbg_init_btext(void);
+extern void __init udbg_init_44x_as1(void);
 
 #endif /* __KERNEL__ */
 #endif /* _ASM_POWERPC_UDBG_H */
diff --git a/include/asm-ppc/kdebug.h b/include/asm-ppc/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-ppc/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-ppc/pgtable.h b/include/asm-ppc/pgtable.h
index b1fdbf40dba2..bed452d4a5f0 100644
--- a/include/asm-ppc/pgtable.h
+++ b/include/asm-ppc/pgtable.h
@@ -827,10 +827,6 @@ static inline int io_remap_pfn_range(struct vm_area_struct *vma,
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 #endif
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 /*
  * No page table caches to initialise
  */
diff --git a/include/asm-ppc/system.h b/include/asm-ppc/system.h
index 738943584c01..d84a3cf4d033 100644
--- a/include/asm-ppc/system.h
+++ b/include/asm-ppc/system.h
@@ -6,7 +6,6 @@
 
 #include <linux/kernel.h>
 
-#include <asm/atomic.h>
 #include <asm/hw_irq.h>
 
 /*
@@ -170,7 +169,6 @@ xchg_u32(volatile void *p, unsigned long val)
 extern void __xchg_called_with_bad_pointer(void);
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 static inline unsigned long __xchg(unsigned long x, volatile void *ptr, int size)
 {
diff --git a/include/asm-s390/dma-mapping.h b/include/asm-s390/dma-mapping.h
index 09bb7b04f967..3f8c12fde0f0 100644
--- a/include/asm-s390/dma-mapping.h
+++ b/include/asm-s390/dma-mapping.h
@@ -9,6 +9,4 @@
 #ifndef _ASM_DMA_MAPPING_H
 #define _ASM_DMA_MAPPING_H
 
-#include <asm-generic/dma-mapping-broken.h>
-
 #endif /* _ASM_DMA_MAPPING_H */
diff --git a/include/asm-s390/kdebug.h b/include/asm-s390/kdebug.h
index d2d7ad276148..04418af08f85 100644
--- a/include/asm-s390/kdebug.h
+++ b/include/asm-s390/kdebug.h
@@ -8,21 +8,6 @@
 
 struct pt_regs;
 
-struct die_args {
-        struct pt_regs *regs;
-        const char *str;
-        long err;
-        int trapnr;
-        int signr;
-};
-
-/* Note - you should never unregister because that can race with NMIs.
- * If you really want to do it first unregister - then synchronize_sched
- *  - then free.
- */
-extern int register_die_notifier(struct notifier_block *);
-extern int unregister_die_notifier(struct notifier_block *);
-
 /*
  * These are only here because kprobes.c wants them to implement a
  * blatant layering violation. Will hopefully go away soon once all
@@ -37,8 +22,6 @@ static inline int unregister_page_fault_notifier(struct notifier_block *nb)
         return 0;
 }
 
-extern struct atomic_notifier_head s390die_chain;
-
 enum die_val {
         DIE_OOPS = 1,
         DIE_BPT,
@@ -54,19 +37,6 @@ enum die_val {
         DIE_NMI_IPI,
 };
 
-static inline int notify_die(enum die_val val, const char *str,
-                        struct pt_regs *regs, long err, int trap, int sig)
-{
-        struct die_args args = {
-                .regs = regs,
-                .str = str,
-                .err = err,
-                .trapnr = trap,
-                .signr = sig
-        };
-        return atomic_notifier_call_chain(&s390die_chain, val, &args);
-}
-
 extern void die(const char *, struct pt_regs *, long);
 
 #endif
diff --git a/include/asm-s390/kexec.h b/include/asm-s390/kexec.h
index 9c35c8ad1afd..7592af708b41 100644
--- a/include/asm-s390/kexec.h
+++ b/include/asm-s390/kexec.h
@@ -34,8 +34,6 @@
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_S390
 
-#define MAX_NOTE_BYTES 1024
-
 /* Provide a dummy definition to avoid build failures. */
 static inline void crash_setup_regs(struct pt_regs *newregs,
                                         struct pt_regs *oldregs) { }
diff --git a/include/asm-s390/qdio.h b/include/asm-s390/qdio.h
index 127f72e77419..74db1dc10a7d 100644
--- a/include/asm-s390/qdio.h
+++ b/include/asm-s390/qdio.h
@@ -120,6 +120,7 @@ extern unsigned long qdio_get_status(int irq);
 #define QDIO_FLAG_NO_INPUT_INTERRUPT_CONTEXT 0x08 /* no effect on
                                                      adapter interrupts */
 #define QDIO_FLAG_DONT_SIGA 0x10
+#define QDIO_FLAG_PCI_OUT   0x20
 
 extern int do_QDIO(struct ccw_device*, unsigned int flags, 
                    unsigned int queue_number,
diff --git a/include/asm-sh/bug.h b/include/asm-sh/bug.h
index 2f89dd06d0cd..794c36daf06d 100644
--- a/include/asm-sh/bug.h
+++ b/include/asm-sh/bug.h
@@ -2,50 +2,80 @@
 #define __ASM_SH_BUG_H
 
 #ifdef CONFIG_BUG
-
-struct bug_frame {
-        unsigned short  opcode;
-        unsigned short  line;
-        const char      *file;
-        const char      *func;
-};
-
-struct pt_regs;
-
-extern void handle_BUG(struct pt_regs *);
+#define HAVE_ARCH_BUG
+#define HAVE_ARCH_WARN_ON
 
 #define TRAPA_BUG_OPCODE        0xc33e  /* trapa #0x3e */
 
+/**
+ * _EMIT_BUG_ENTRY
+ * %1 - __FILE__
+ * %2 - __LINE__
+ * %3 - trap type
+ * %4 - sizeof(struct bug_entry)
+ *
+ * The trapa opcode itself sits in %0.
+ * The %O notation is used to avoid # generation.
+ *
+ * The offending file and line are encoded in the __bug_table section.
+ */
 #ifdef CONFIG_DEBUG_BUGVERBOSE
+#define _EMIT_BUG_ENTRY                         \
+        "\t.pushsection __bug_table,\"a\"\n"    \
+        "2:\t.long 1b, %O1\n"                   \
+        "\t.short %O2, %O3\n"                   \
+        "\t.org 2b+%O4\n"                       \
+        "\t.popsection\n"
+#else
+#define _EMIT_BUG_ENTRY                         \
+        "\t.pushsection __bug_table,\"a\"\n"    \
+        "2:\t.long 1b\n"                        \
+        "\t.short %O3\n"                        \
+        "\t.org 2b+%O4\n"                       \
+        "\t.popsection\n"
+#endif
 
 #define BUG()                                           \
 do {                                                    \
         __asm__ __volatile__ (                          \
-                ".align 2\n\t"                          \
-                ".short %O0\n\t"                        \
-                ".short %O1\n\t"                        \
-                ".long  %O2\n\t"                        \
-                ".long  %O3\n\t"                        \
-                :                                       \
-                : "n" (TRAPA_BUG_OPCODE),               \
-                  "i" (__LINE__), "X" (__FILE__),       \
-                  "X" (__FUNCTION__));                  \
+                "1:\t.short %O0\n"                      \
+                _EMIT_BUG_ENTRY                         \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__), "i" (0),             \
+                   "i" (sizeof(struct bug_entry)));     \
 } while (0)
 
-#else
-
-#define BUG()                                   \
-do {                                            \
-        __asm__ __volatile__ (                  \
-                ".align 2\n\t"                  \
-                ".short %O0\n\t"                \
-                :                               \
-                : "n" (TRAPA_BUG_OPCODE));      \
+#define __WARN()                                        \
+do {                                                    \
+        __asm__ __volatile__ (                          \
+                "1:\t.short %O0\n"                      \
+                 _EMIT_BUG_ENTRY                        \
+                 :                                      \
+                 : "n" (TRAPA_BUG_OPCODE),              \
+                   "i" (__FILE__),                      \
+                   "i" (__LINE__),                      \
+                   "i" (BUGFLAG_WARNING),               \
+                   "i" (sizeof(struct bug_entry)));     \
 } while (0)
 
-#endif /* CONFIG_DEBUG_BUGVERBOSE */
+#define WARN_ON(x) ({                                           \
+        typeof(x) __ret_warn_on = (x);                          \
+        if (__builtin_constant_p(__ret_warn_on)) {              \
+                if (__ret_warn_on)                              \
+                        __WARN();                               \
+        } else {                                                \
+                if (unlikely(__ret_warn_on))                    \
+                        __WARN();                               \
+        }                                                       \
+        unlikely(__ret_warn_on);                                \
+})
 
-#define HAVE_ARCH_BUG
+struct pt_regs;
+
+/* arch/sh/kernel/traps.c */
+void handle_BUG(struct pt_regs *);
 
 #endif /* CONFIG_BUG */
 
diff --git a/include/asm-sh/clock.h b/include/asm-sh/clock.h
index 1df92807f8c5..386d797d86b7 100644
--- a/include/asm-sh/clock.h
+++ b/include/asm-sh/clock.h
@@ -13,7 +13,7 @@ struct clk_ops {
         void (*enable)(struct clk *clk);
         void (*disable)(struct clk *clk);
         void (*recalc)(struct clk *clk);
-        int (*set_rate)(struct clk *clk, unsigned long rate);
+        int (*set_rate)(struct clk *clk, unsigned long rate, int algo_id);
 };
 
 struct clk {
@@ -48,6 +48,34 @@ void clk_recalc_rate(struct clk *);
 int clk_register(struct clk *);
 void clk_unregister(struct clk *);
 
-int show_clocks(struct seq_file *m);
+/* the exported API, in addition to clk_set_rate */
+/**
+ * clk_set_rate_ex - set the clock rate for a clock source, with additional parameter
+ * @clk: clock source
+ * @rate: desired clock rate in Hz
+ * @algo_id: algorithm id to be passed down to ops->set_rate
+ *
+ * Returns success (0) or negative errno.
+ */
+int clk_set_rate_ex(struct clk *clk, unsigned long rate, int algo_id);
 
+enum clk_sh_algo_id {
+        NO_CHANGE = 0,
+
+        IUS_N1_N1,
+        IUS_322,
+        IUS_522,
+        IUS_N11,
+
+        SB_N1,
+
+        SB3_N1,
+        SB3_32,
+        SB3_43,
+        SB3_54,
+
+        BP_N1,
+
+        IP_N1,
+};
 #endif /* __ASM_SH_CLOCK_H */
diff --git a/include/asm-sh/cpu-sh3/mmu_context.h b/include/asm-sh/cpu-sh3/mmu_context.h
index bccb7ddb438b..4704e86dff5b 100644
--- a/include/asm-sh/cpu-sh3/mmu_context.h
+++ b/include/asm-sh/cpu-sh3/mmu_context.h
@@ -32,6 +32,7 @@
     defined(CONFIG_CPU_SUBTYPE_SH7706) || \
     defined(CONFIG_CPU_SUBTYPE_SH7300) || \
     defined(CONFIG_CPU_SUBTYPE_SH7705) || \
+    defined(CONFIG_CPU_SUBTYPE_SH7712) || \
     defined(CONFIG_CPU_SUBTYPE_SH7710)
 #define INTEVT  0xa4000000      /* INTEVTE2(0xa4000000) */
 #else
diff --git a/include/asm-sh/cpu-sh4/freq.h b/include/asm-sh/cpu-sh4/freq.h
index 602d061ca2dc..86564e7a26ae 100644
--- a/include/asm-sh/cpu-sh4/freq.h
+++ b/include/asm-sh/cpu-sh4/freq.h
@@ -12,8 +12,16 @@
 
 #if defined(CONFIG_CPU_SUBTYPE_SH73180) || defined(CONFIG_CPU_SUBTYPE_SH7722)
 #define FRQCR                   0xa4150000
+#define VCLKCR                  0xa4150004
+#define SCLKACR                 0xa4150008
+#define SCLKBCR                 0xa415000c
+#define IrDACLKCR               0xa4150010
 #elif defined(CONFIG_CPU_SUBTYPE_SH7780)
 #define FRQCR                   0xffc80000
+#elif defined(CONFIG_CPU_SUBTYPE_SH7785)
+#define FRQCR0                  0xffc80000
+#define FRQCR1                  0xffc80004
+#define FRQMR1                  0xffc80014
 #else
 #define FRQCR                   0xffc00000
 #endif
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h
index afe188f0ad5f..e81bf21c801e 100644
--- a/include/asm-sh/irq.h
+++ b/include/asm-sh/irq.h
@@ -2,94 +2,13 @@
 #define __ASM_SH_IRQ_H
 
 #include <asm/machvec.h>
-#include <asm/ptrace.h>         /* for pt_regs */
 
-/* NR_IRQS is made from three components:
- *   1. ONCHIP_NR_IRQS - number of IRLS + on-chip peripherial modules
- *   2. PINT_NR_IRQS   - number of PINT interrupts
- *   3. OFFCHIP_NR_IRQS - numbe of IRQs from off-chip peripherial modules
+/*
+ * A sane default based on a reasonable vector table size, platforms are
+ * advised to cap this at the hard limit that they're interested in
+ * through the machvec.
  */
-
-/* 1. ONCHIP_NR_IRQS */
-#if defined(CONFIG_CPU_SUBTYPE_SH7604)
-# define ONCHIP_NR_IRQS 24      // Actually 21
-#elif defined(CONFIG_CPU_SUBTYPE_SH7707)
-# define ONCHIP_NR_IRQS 64
-# define PINT_NR_IRQS   16
-#elif defined(CONFIG_CPU_SUBTYPE_SH7708)
-# define ONCHIP_NR_IRQS 32
-#elif defined(CONFIG_CPU_SUBTYPE_SH7709) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7706) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7705)
-# define ONCHIP_NR_IRQS 64      // Actually 61
-# define PINT_NR_IRQS   16
-#elif defined(CONFIG_CPU_SUBTYPE_SH7710)
-# define ONCHIP_NR_IRQS 104
-#elif defined(CONFIG_CPU_SUBTYPE_SH7750)
-# define ONCHIP_NR_IRQS 48      // Actually 44
-#elif defined(CONFIG_CPU_SUBTYPE_SH7751)
-# define ONCHIP_NR_IRQS 72
-#elif defined(CONFIG_CPU_SUBTYPE_SH7760)
-# define ONCHIP_NR_IRQS 112     /* XXX */
-#elif defined(CONFIG_CPU_SUBTYPE_SH4_202)
-# define ONCHIP_NR_IRQS 72
-#elif defined(CONFIG_CPU_SUBTYPE_ST40STB1)
-# define ONCHIP_NR_IRQS 144
-#elif defined(CONFIG_CPU_SUBTYPE_SH7300) || \
-      defined(CONFIG_CPU_SUBTYPE_SH73180) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7343) || \
-      defined(CONFIG_CPU_SUBTYPE_SH7722)
-# define ONCHIP_NR_IRQS 109
-#elif defined(CONFIG_CPU_SUBTYPE_SH7780)
-# define ONCHIP_NR_IRQS 111
-#elif defined(CONFIG_CPU_SUBTYPE_SH7206)
-# define ONCHIP_NR_IRQS 256
-#elif defined(CONFIG_CPU_SUBTYPE_SH7619)
-# define ONCHIP_NR_IRQS 128
-#elif defined(CONFIG_SH_UNKNOWN)        /* Most be last */
-# define ONCHIP_NR_IRQS 144
-#endif
-
-/* 2. PINT_NR_IRQS */
-#ifdef CONFIG_SH_UNKNOWN
-# define PINT_NR_IRQS 16
-#else
-# ifndef PINT_NR_IRQS
-#  define PINT_NR_IRQS 0
-# endif
-#endif
-
-#if PINT_NR_IRQS > 0
-# define PINT_IRQ_BASE  ONCHIP_NR_IRQS
-#endif
-
-/* 3. OFFCHIP_NR_IRQS */
-#if defined(CONFIG_HD64461)
-# define OFFCHIP_NR_IRQS 18
-#elif defined(CONFIG_HD64465)
-# define OFFCHIP_NR_IRQS 16
-#elif defined (CONFIG_SH_DREAMCAST)
-# define OFFCHIP_NR_IRQS 96
-#elif defined (CONFIG_SH_TITAN)
-# define OFFCHIP_NR_IRQS 4
-#elif defined(CONFIG_SH_R7780RP)
-# define OFFCHIP_NR_IRQS 16
-#elif defined(CONFIG_SH_7343_SOLUTION_ENGINE)
-# define OFFCHIP_NR_IRQS 12
-#elif defined(CONFIG_SH_7722_SOLUTION_ENGINE)
-# define OFFCHIP_NR_IRQS 14
-#elif defined(CONFIG_SH_UNKNOWN)
-# define OFFCHIP_NR_IRQS 16     /* Must also be last */
-#else
-# define OFFCHIP_NR_IRQS 0
-#endif
-
-#if OFFCHIP_NR_IRQS > 0
-# define OFFCHIP_IRQ_BASE (ONCHIP_NR_IRQS + PINT_NR_IRQS)
-#endif
-
-/* NR_IRQS. 1+2+3 */
-#define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS)
+#define NR_IRQS 256
 
 /*
  * Convert back and forth between INTEVT and IRQ values.
diff --git a/include/asm-sh/kdebug.h b/include/asm-sh/kdebug.h
new file mode 100644
index 000000000000..493c20629747
--- /dev/null
+++ b/include/asm-sh/kdebug.h
@@ -0,0 +1,36 @@
+#ifndef __ASM_SH_KDEBUG_H
+#define __ASM_SH_KDEBUG_H
+
+#include <linux/notifier.h>
+#include <asm-generic/kdebug.h>
+
+struct pt_regs;
+
+struct die_args {
+        struct pt_regs *regs;
+        int trapnr;
+};
+
+int register_die_notifier(struct notifier_block *nb);
+int unregister_die_notifier(struct notifier_block *nb);
+int register_page_fault_notifier(struct notifier_block *nb);
+int unregister_page_fault_notifier(struct notifier_block *nb);
+extern struct atomic_notifier_head shdie_chain;
+
+/* Grossly misnamed. */
+enum die_val {
+        DIE_TRAP,
+        DIE_PAGE_FAULT,
+};
+
+static inline int notify_die(enum die_val val, struct pt_regs *regs,
+                             int trap, int sig)
+{
+        struct die_args args = {
+                .regs = regs,
+                .trapnr = trap,
+        };
+
+        return atomic_notifier_call_chain(&shdie_chain, val, &args);
+}
+#endif /* __ASM_SH_KDEBUG_H */
diff --git a/include/asm-sh/kexec.h b/include/asm-sh/kexec.h
index 9d235af20cdd..00f4260ef09b 100644
--- a/include/asm-sh/kexec.h
+++ b/include/asm-sh/kexec.h
@@ -1,5 +1,8 @@
-#ifndef _SH_KEXEC_H
-#define _SH_KEXEC_H
+#ifndef __ASM_SH_KEXEC_H
+#define __ASM_SH_KEXEC_H
+
+#include <asm/ptrace.h>
+#include <asm/string.h>
 
 /*
  * KEXEC_SOURCE_MEMORY_LIMIT maximum page get_free_page can return.
@@ -23,10 +26,37 @@
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_SH
 
-#define MAX_NOTE_BYTES 1024
-
-/* Provide a dummy definition to avoid build failures. */
 static inline void crash_setup_regs(struct pt_regs *newregs,
-                                        struct pt_regs *oldregs) { }
+                                    struct pt_regs *oldregs)
+{
+        if (oldregs)
+                memcpy(newregs, oldregs, sizeof(*newregs));
+        else {
+                __asm__ __volatile__ ("mov r0, %0" : "=r" (newregs->regs[0]));
+                __asm__ __volatile__ ("mov r1, %0" : "=r" (newregs->regs[1]));
+                __asm__ __volatile__ ("mov r2, %0" : "=r" (newregs->regs[2]));
+                __asm__ __volatile__ ("mov r3, %0" : "=r" (newregs->regs[3]));
+                __asm__ __volatile__ ("mov r4, %0" : "=r" (newregs->regs[4]));
+                __asm__ __volatile__ ("mov r5, %0" : "=r" (newregs->regs[5]));
+                __asm__ __volatile__ ("mov r6, %0" : "=r" (newregs->regs[6]));
+                __asm__ __volatile__ ("mov r7, %0" : "=r" (newregs->regs[7]));
+                __asm__ __volatile__ ("mov r8, %0" : "=r" (newregs->regs[8]));
+                __asm__ __volatile__ ("mov r9, %0" : "=r" (newregs->regs[9]));
+                __asm__ __volatile__ ("mov r10, %0" : "=r" (newregs->regs[10]));
+                __asm__ __volatile__ ("mov r11, %0" : "=r" (newregs->regs[11]));
+                __asm__ __volatile__ ("mov r12, %0" : "=r" (newregs->regs[12]));
+                __asm__ __volatile__ ("mov r13, %0" : "=r" (newregs->regs[13]));
+                __asm__ __volatile__ ("mov r14, %0" : "=r" (newregs->regs[14]));
+                __asm__ __volatile__ ("mov r15, %0" : "=r" (newregs->regs[15]));
+
+                __asm__ __volatile__ ("sts pr, %0" : "=r" (newregs->pr));
+                __asm__ __volatile__ ("sts macl, %0" : "=r" (newregs->macl));
+                __asm__ __volatile__ ("sts mach, %0" : "=r" (newregs->mach));
+
+                __asm__ __volatile__ ("stc gbr, %0" : "=r" (newregs->gbr));
+                __asm__ __volatile__ ("stc sr, %0" : "=r" (newregs->sr));
 
-#endif /* _SH_KEXEC_H */
+                newregs->pc = (unsigned long)current_text_addr();
+        }
+}
+#endif /* __ASM_SH_KEXEC_H */
diff --git a/include/asm-sh/kgdb.h b/include/asm-sh/kgdb.h
index 0095c665d272..74bd0953e5ce 100644
--- a/include/asm-sh/kgdb.h
+++ b/include/asm-sh/kgdb.h
@@ -17,6 +17,7 @@
 #define __KGDB_H
 
 #include <asm/ptrace.h>
+#include <asm/cacheflush.h>
 
 struct console;
 
@@ -45,35 +46,21 @@ extern int kgdb_portnum;
 extern int kgdb_baud;
 extern char kgdb_parity;
 extern char kgdb_bits;
-extern int kgdb_console_setup(struct console *, char *);
 
 /* Init and interface stuff */
 extern int kgdb_init(void);
-extern int (*kgdb_serial_setup)(void);
 extern int (*kgdb_getchar)(void);
 extern void (*kgdb_putchar)(int);
 
-struct kgdb_sermap {
-        char *name;
-        int namelen;
-        int (*setup_fn)(struct console *, char *);
-        struct kgdb_sermap *next;
-};
-extern void kgdb_register_sermap(struct kgdb_sermap *map);
-extern struct kgdb_sermap *kgdb_porttype;
-
 /* Trap functions */
-typedef void (kgdb_debug_hook_t)(struct pt_regs *regs); 
+typedef void (kgdb_debug_hook_t)(struct pt_regs *regs);
 typedef void (kgdb_bus_error_hook_t)(void);
 extern kgdb_debug_hook_t  *kgdb_debug_hook;
 extern kgdb_bus_error_hook_t *kgdb_bus_err_hook;
 
-extern void breakpoint(void);
-
 /* Console */
-struct console;
 void kgdb_console_write(struct console *co, const char *s, unsigned count);
-void kgdb_console_init(void);
+extern int kgdb_console_setup(struct console *, char *);
 
 /* Prototypes for jmp fns */
 #define _JBLEN 9
@@ -81,11 +68,8 @@ typedef        int jmp_buf[_JBLEN];
 extern void    longjmp(jmp_buf __jmpb, int __retval);
 extern int     setjmp(jmp_buf __jmpb);
 
-/* Variadic macro to print our own message to the console */
-#define KGDB_PRINTK(...) printk("KGDB: " __VA_ARGS__)
-
 /* Forced breakpoint */
-#define BREAKPOINT()                                    \
+#define breakpoint()                                    \
 do {                                                    \
         if (kgdb_enabled)                               \
                 __asm__ __volatile__("trapa   #0x3c");  \
@@ -95,7 +79,6 @@ do {							\
 #if defined(CONFIG_CPU_SH4)
 #define kgdb_flush_icache_range(start, end) \
 {                                                                       \
-        extern void __flush_purge_region(void *, int);                  \
         __flush_purge_region((void*)(start), (int)(end) - (int)(start));\
         flush_icache_range((start), (end));                             \
 }
@@ -103,31 +86,6 @@ do {							\
 #define kgdb_flush_icache_range(start, end)     do { } while (0)
 #endif
 
-/* Kernel assert macros */
-#ifdef CONFIG_KGDB_KERNEL_ASSERTS
-
-/* Predefined conditions */
-#define KA_VALID_ERRNO(errno) ((errno) > 0 && (errno) <= EMEDIUMTYPE)
-#define KA_VALID_PTR_ERR(ptr) KA_VALID_ERRNO(-PTR_ERR(ptr))
-#define KA_VALID_KPTR(ptr)  (!(ptr) || \
-              ((void *)(ptr) >= (void *)PAGE_OFFSET &&  \
-               (void *)(ptr) < ERR_PTR(-EMEDIUMTYPE)))
-#define KA_VALID_PTRORERR(errptr) \
-               (KA_VALID_KPTR(errptr) || KA_VALID_PTR_ERR(errptr))
-#define KA_HELD_GKL()  (current->lock_depth >= 0)
-
-/* The actual assert */
-#define KGDB_ASSERT(condition, message) do {                   \
-       if (!(condition) && (kgdb_enabled)) {                   \
-               KGDB_PRINTK("Assertion failed at %s:%d: %s\n",  \
-                                  __FILE__, __LINE__, message);\
-               BREAKPOINT();                                   \
-       }                                                       \
-} while (0)
-#else
-#define KGDB_ASSERT(condition, message)
-#endif
-
 /* Taken from sh-stub.c of GDB 4.18 */
 static const char hexchars[] = "0123456789abcdef";
 
@@ -142,5 +100,4 @@ static inline char lowhex(const int x)
 {
         return hexchars[x & 0xf];
 }
-
 #endif
diff --git a/include/asm-sh/lboxre2.h b/include/asm-sh/lboxre2.h
new file mode 100644
index 000000000000..e6d160504923
--- /dev/null
+++ b/include/asm-sh/lboxre2.h
@@ -0,0 +1,27 @@
+#ifndef __ASM_SH_LBOXRE2_H
+#define __ASM_SH_LBOXRE2_H
+
+/*
+ * Copyright (C) 2007 Nobuhiro Iwamatsu
+ *
+ * NTT COMWARE L-BOX RE2 support
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+
+#define IRQ_CF1         9       /* CF1 */
+#define IRQ_CF0         10      /* CF0 */
+#define IRQ_INTD        11      /* INTD */
+#define IRQ_ETH1        12      /* Ether1 */
+#define IRQ_ETH0        13      /* Ether0 */
+#define IRQ_INTA        14      /* INTA */
+
+void init_lboxre2_IRQ(void);
+
+#define __IO_PREFIX     lboxre2
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_LBOXRE2_H */
diff --git a/include/asm-sh/mmu_context.h b/include/asm-sh/mmu_context.h
index 01acaaae9751..199662bb35c6 100644
--- a/include/asm-sh/mmu_context.h
+++ b/include/asm-sh/mmu_context.h
@@ -169,6 +169,8 @@ enter_lazy_tlb(struct mm_struct *mm, struct task_struct *tsk)
 #define destroy_context(mm)             do { } while (0)
 #define set_asid(asid)                  do { } while (0)
 #define get_asid()                      (0)
+#define set_TTB(pgd)                    do { } while (0)
+#define get_TTB()                       (0)
 #define activate_context(mm,cpu)        do { } while (0)
 #define switch_mm(prev,next,tsk)        do { } while (0)
 #define deactivate_mm(tsk,mm)           do { } while (0)
@@ -211,8 +213,8 @@ static inline void disable_mmu(void)
  * MMU control handlers for processors lacking memory
  * management hardware.
  */
-#define enable_mmu()    do { BUG(); } while (0)
-#define disable_mmu()   do { BUG(); } while (0)
+#define enable_mmu()    do { } while (0)
+#define disable_mmu()   do { } while (0)
 #endif
 
 #endif /* __KERNEL__ */
diff --git a/include/asm-sh/page.h b/include/asm-sh/page.h
index ac4b4677f28c..7464de4ba07d 100644
--- a/include/asm-sh/page.h
+++ b/include/asm-sh/page.h
@@ -59,6 +59,7 @@ extern void (*clear_page)(void *to);
 extern void (*copy_page)(void *to, void *from);
 
 extern unsigned long shm_align_mask;
+extern unsigned long max_low_pfn, min_low_pfn;
 
 #ifdef CONFIG_MMU
 extern void clear_page_slow(void *to);
@@ -124,17 +125,16 @@ typedef struct { unsigned long pgd; } pgd_t;
 #define PAGE_OFFSET             CONFIG_PAGE_OFFSET
 #define __pa(x)                 ((unsigned long)(x)-PAGE_OFFSET)
 #define __va(x)                 ((void *)((unsigned long)(x)+PAGE_OFFSET))
+#define pfn_to_kaddr(pfn)       __va((pfn) << PAGE_SHIFT)
 
-#define MAP_NR(addr)            (((unsigned long)(addr)-PAGE_OFFSET) >> PAGE_SHIFT)
-
-#define phys_to_page(phys)      (mem_map + (((phys)-__MEMORY_START) >> PAGE_SHIFT))
-#define page_to_phys(page)      (((page - mem_map) << PAGE_SHIFT) + __MEMORY_START)
+#define phys_to_page(phys)      (pfn_to_page(phys >> PAGE_SHIFT))
+#define page_to_phys(page)      (page_to_pfn(page) << PAGE_SHIFT)
 
 /* PFN start number, because of __MEMORY_START */
 #define PFN_START               (__MEMORY_START >> PAGE_SHIFT)
 #define ARCH_PFN_OFFSET         (PFN_START)
 #define virt_to_page(kaddr)     pfn_to_page(__pa(kaddr) >> PAGE_SHIFT)
-#define pfn_valid(pfn)          (((pfn) - PFN_START) < max_mapnr)
+#define pfn_valid(pfn)          ((pfn) >= min_low_pfn && (pfn) < max_low_pfn)
 #define virt_addr_valid(kaddr)  pfn_valid(__pa(kaddr) >> PAGE_SHIFT)
 
 #define VM_DATA_DEFAULT_FLAGS   (VM_READ | VM_WRITE | VM_EXEC | \
diff --git a/include/asm-sh/param.h b/include/asm-sh/param.h
index ce13064fec21..1012296e07ab 100644
--- a/include/asm-sh/param.h
+++ b/include/asm-sh/param.h
@@ -5,7 +5,7 @@
 # ifdef CONFIG_SH_WDT
 #  define HZ            1000            /* Needed for high-res WOVF */
 # else
-#  define HZ            100
+#  define HZ            CONFIG_HZ
 # endif
 # define USER_HZ        100             /* User interfaces are in "ticks" */
 # define CLOCKS_PER_SEC (USER_HZ)       /* frequency at which times() counts */
diff --git a/include/asm-sh/pci.h b/include/asm-sh/pci.h
index 6ccc948fe216..b1f9a9e0231e 100644
--- a/include/asm-sh/pci.h
+++ b/include/asm-sh/pci.h
@@ -35,7 +35,7 @@ extern struct pci_channel board_pci_channels[];
 /*
  * I/O routine helpers
  */
-#ifdef CONFIG_CPU_SUBTYPE_SH7780
+#if defined(CONFIG_CPU_SUBTYPE_SH7780) || defined(CONFIG_CPU_SUBTYPE_SH7785)
 #define PCI_IO_AREA             0xFE400000
 #define PCI_IO_SIZE             0x00400000
 #else
diff --git a/include/asm-sh/pgtable.h b/include/asm-sh/pgtable.h
index 184d7fcaaf10..5b523c7e7d99 100644
--- a/include/asm-sh/pgtable.h
+++ b/include/asm-sh/pgtable.h
@@ -568,10 +568,6 @@ typedef pte_t *pte_addr_t;
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 struct mm_struct;
 
 /*
diff --git a/include/asm-sh/processor.h b/include/asm-sh/processor.h
index 3e46a7afe764..d42f68e724fa 100644
--- a/include/asm-sh/processor.h
+++ b/include/asm-sh/processor.h
@@ -44,7 +44,7 @@ enum cpu_type {
         /* SH-3 types */
         CPU_SH7705, CPU_SH7706, CPU_SH7707,
         CPU_SH7708, CPU_SH7708S, CPU_SH7708R,
-        CPU_SH7709, CPU_SH7709A, CPU_SH7710,
+        CPU_SH7709, CPU_SH7709A, CPU_SH7710, CPU_SH7712,
         CPU_SH7729, CPU_SH7300,
 
         /* SH-4 types */
diff --git a/include/asm-sh/r7780rp.h b/include/asm-sh/r7780rp.h
index c18f648a7995..4083b5949928 100644
--- a/include/asm-sh/r7780rp.h
+++ b/include/asm-sh/r7780rp.h
@@ -1,17 +1,11 @@
 #ifndef __ASM_SH_RENESAS_R7780RP_H
 #define __ASM_SH_RENESAS_R7780RP_H
 
-/*
- * linux/include/asm-sh/r7780rp.h
- *
- * Copyright (C) 2000  Atom Create Engineering Co., Ltd.
- *
- * Renesas Solutions Highlander R7780RP support
- */
-
 /* Box specific addresses.  */
 #if defined(CONFIG_SH_R7780MP)
 #define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW        (-1)
+
 #define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
 #define PA_IRLMON       (PA_BCR+0x0002) /* Interrupt Status control */
 #define PA_IRLPRI1      (PA_BCR+0x0004) /* Interrupt Priorty 1 */
@@ -70,18 +64,12 @@
 #define PA_POFF         (PA_BCR+0x0800) /* System Power Off control */
 #define PA_PMR          (PA_BCR+0x0900) /*  */
 
-#define PA_AX88796L     0xa4100400      /* AX88796L Area */
-#define PA_SC1602BSLB   0xa6000000      /* SC1602BSLB Area */
-#define PA_IDE_OFFSET   0x1f0           /* CF IDE Offset */
-#define AX88796L_IO_BASE        0x1000  /* AX88796L IO Base Address */
-
 #define IRLCNTR1        (PA_BCR + 0)    /* Interrupt Control Register1 */
 
 #define IRQ_PCISLOT1    65              /* PCI Slot #1 IRQ */
 #define IRQ_PCISLOT2    66              /* PCI Slot #2 IRQ */
 #define IRQ_PCISLOT3    67              /* PCI Slot #3 IRQ */
 #define IRQ_PCISLOT4    68              /* PCI Slot #4 IRQ */
-// #define IRQ_CFINST   0               /* CF Card Insert IRQ */
 #define IRQ_TP          2               /* Touch Panel IRQ */
 #define IRQ_SCI1        3               /* SCI1 IRQ */
 #define IRQ_SCI0        4               /* SCI0 IRQ */
@@ -95,7 +83,10 @@
 #define IRQ_ONETH       13              /* On board Ethernet IRQ */
 #define IRQ_PSW         14              /* Push Switch IRQ */
 
-#else /* R7780RP */
+#define IVDR_CK_ON      8               /* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7780RP)
+#define PA_POFF         (-1)
 
 #define PA_BCR          0xa5000000      /* FPGA */
 #define PA_IRLMSK       (PA_BCR+0x0000) /* Interrupt Mask control */
@@ -163,7 +154,60 @@
 #define IRQ_PSW         13              /* Push Switch IRQ */
 #define IRQ_ZIGBEE      14              /* Ziggbee IO IRQ */
 
-#endif  /* CONFIG_SH_R7780MP */
+#define IVDR_CK_ON      8               /* iVDR Clock ON */
+
+#elif defined(CONFIG_SH_R7785RP)
+#define PA_BCR          0xa4000000      /* FPGA */
+#define PA_SDPOW        (-1)
+
+#define PA_PCISCR       (PA_BCR+0x0000)
+#define PA_IRLPRA       (PA_BCR+0x0002)
+#define PA_IRLPRB       (PA_BCR+0x0004)
+#define PA_IRLPRC       (PA_BCR+0x0006)
+#define PA_IRLPRD       (PA_BCR+0x0008)
+#define IRLCNTR1        (PA_BCR+0x0010)
+#define PA_IRLPRE       (PA_BCR+0x000a)
+#define PA_IRLPRF       (PA_BCR+0x000c)
+#define PA_EXIRLCR      (PA_BCR+0x000e)
+#define PA_IRLMCR1      (PA_BCR+0x0010)
+#define PA_IRLMCR2      (PA_BCR+0x0012)
+#define PA_IRLSSR1      (PA_BCR+0x0014)
+#define PA_IRLSSR2      (PA_BCR+0x0016)
+#define PA_CFTCR        (PA_BCR+0x0100)
+#define PA_CFPCR        (PA_BCR+0x0102)
+#define PA_PCICR        (PA_BCR+0x0110)
+#define PA_IVDRCTL      (PA_BCR+0x0112)
+#define PA_IVDRSR       (PA_BCR+0x0114)
+#define PA_PDRSTCR      (PA_BCR+0x0116)
+#define PA_POFF         (PA_BCR+0x0120)
+#define PA_LCDCR        (PA_BCR+0x0130)
+#define PA_TPCR         (PA_BCR+0x0140)
+#define PA_TPCKCR       (PA_BCR+0x0142)
+#define PA_TPRSTR       (PA_BCR+0x0144)
+#define PA_TPXPDR       (PA_BCR+0x0146)
+#define PA_TPYPDR       (PA_BCR+0x0148)
+#define PA_GPIOPFR      (PA_BCR+0x0150)
+#define PA_GPIODR       (PA_BCR+0x0152)
+#define PA_OBLED        (PA_BCR+0x0154)
+#define PA_SWSR         (PA_BCR+0x0156)
+#define PA_VERREG       (PA_BCR+0x0158)
+#define PA_SMCR         (PA_BCR+0x0200)
+#define PA_SMSMADR      (PA_BCR+0x0202)
+#define PA_SMMR         (PA_BCR+0x0204)
+#define PA_SMSADR1      (PA_BCR+0x0206)
+#define PA_SMSADR32     (PA_BCR+0x0244)
+#define PA_SMTRDR1      (PA_BCR+0x0246)
+#define PA_SMTRDR16     (PA_BCR+0x0264)
+#define PA_CU3MDR       (PA_BCR+0x0300)
+#define PA_CU5MDR       (PA_BCR+0x0302)
+#define PA_MMSR         (PA_BCR+0x0400)
+
+#define IVDR_CK_ON      4               /* iVDR Clock ON */
+
+#endif
+
+void make_r7780rp_irq(unsigned int irq);
+void highlander_init_irq(void);
 
 #define __IO_PREFIX     r7780rp
 #include <asm/io_generic.h>
diff --git a/include/asm-sh/se.h b/include/asm-sh/se.h
index a1832154a3aa..bd2596c014a9 100644
--- a/include/asm-sh/se.h
+++ b/include/asm-sh/se.h
@@ -69,9 +69,11 @@
 #define BCR_ILCRG       (PA_BCR + 12)
 
 #if defined(CONFIG_CPU_SUBTYPE_SH7705)
-#define IRQ_STNIC   12
+#define IRQ_STNIC       12
+#define IRQ_CFCARD      14
 #else
 #define IRQ_STNIC       10
+#define IRQ_CFCARD      7
 #endif
 
 #define __IO_PREFIX     se
diff --git a/include/asm-sh/se7722.h b/include/asm-sh/se7722.h
new file mode 100644
index 000000000000..b3b31e4725c6
--- /dev/null
+++ b/include/asm-sh/se7722.h
@@ -0,0 +1,118 @@
+#ifndef __ASM_SH_SE7722_H
+#define __ASM_SH_SE7722_H
+
+/*
+ * linux/include/asm-sh/se7722.h
+ *
+ * Copyright (C) 2007  Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7722 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ *
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00200000      /* EPROM size 2M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SDRAM        0xaC000000      /* DDR-SDRAM(Area3) 64MB */
+#define PA_SDRAM_SIZE   0x04000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+
+#define PA_PERIPHERAL   0xB0000000
+
+#define PA_PCIC         PA_PERIPHERAL                   /* MR-SHPC-01 PCMCIA */
+#define PA_MRSHPC       (PA_PERIPHERAL + 0x003fffe0)    /* MR-SHPC-01 PCMCIA controller */
+#define PA_MRSHPC_MW1   (PA_PERIPHERAL + 0x00400000)    /* MR-SHPC-01 memory window base */
+#define PA_MRSHPC_MW2   (PA_PERIPHERAL + 0x00500000)    /* MR-SHPC-01 attribute window base */
+#define PA_MRSHPC_IO    (PA_PERIPHERAL + 0x00600000)    /* MR-SHPC-01 I/O window base */
+#define MRSHPC_OPTION   (PA_MRSHPC + 6)
+#define MRSHPC_CSR      (PA_MRSHPC + 8)
+#define MRSHPC_ISR      (PA_MRSHPC + 10)
+#define MRSHPC_ICR      (PA_MRSHPC + 12)
+#define MRSHPC_CPWCR    (PA_MRSHPC + 14)
+#define MRSHPC_MW0CR1   (PA_MRSHPC + 16)
+#define MRSHPC_MW1CR1   (PA_MRSHPC + 18)
+#define MRSHPC_IOWCR1   (PA_MRSHPC + 20)
+#define MRSHPC_MW0CR2   (PA_MRSHPC + 22)
+#define MRSHPC_MW1CR2   (PA_MRSHPC + 24)
+#define MRSHPC_IOWCR2   (PA_MRSHPC + 26)
+#define MRSHPC_CDCR     (PA_MRSHPC + 28)
+#define MRSHPC_PCIC_INFO (PA_MRSHPC + 30)
+
+#define PA_LED          (PA_PERIPHERAL + 0x00800000)    /* 8bit LED */
+#define PA_FPGA         (PA_PERIPHERAL + 0x01800000)    /* FPGA base address */
+
+#define PA_LAN          (PA_AREA6_IO + 0)               /* SMC LAN91C111 */
+/* GPIO */
+#define MSTPCR0         0xA4150030UL
+#define MSTPCR1         0xA4150034UL
+#define MSTPCR2         0xA4150038UL
+
+#define FPGA_IN         0xb1840000UL
+#define FPGA_OUT        0xb1840004UL
+
+#define PORT_PECR       0xA4050108UL
+#define PORT_PJCR       0xA4050110UL
+#define PORT_PSELD      0xA4050154UL
+#define PORT_PSELB      0xA4050150UL
+
+#define PORT_PSELC      0xA4050152UL
+#define PORT_PKCR       0xA4050112UL
+#define PORT_PHCR       0xA405010EUL
+#define PORT_PLCR       0xA4050114UL
+#define PORT_PMCR       0xA4050116UL
+#define PORT_PRCR       0xA405011CUL
+#define PORT_PXCR       0xA4050148UL
+#define PORT_PSELA      0xA405014EUL
+#define PORT_PYCR       0xA405014AUL
+#define PORT_PZCR       0xA405014CUL
+
+/* IRQ */
+#define IRQ0_IRQ        32
+#define IRQ1_IRQ        33
+#define INTC_ICR0       0xA4140000UL
+#define INTC_ICR1       0xA414001CUL
+
+#define INTMSK0         0xa4140044
+#define INTMSKCLR0      0xa4140064
+#define INTC_INTPRI0    0xa4140010
+
+#define IRQ01_MODE      0xb1800000
+#define IRQ01_STS       0xb1800004
+#define IRQ01_MASK      0xb1800008
+#define EXT_BIT         (0x3fc0)        /* SH IRQ1 */
+#define MRSHPC_BIT0     (0x0004)        /* SH IRQ1 */
+#define MRSHPC_BIT1     (0x0008)        /* SH IRQ1 */
+#define MRSHPC_BIT2     (0x0010)        /* SH IRQ1 */
+#define MRSHPC_BIT3     (0x0020)        /* SH IRQ1 */
+#define SMC_BIT         (0x0002)        /* SH IRQ0 */
+#define USB_BIT         (0x0001)        /* SH IRQ0 */
+
+#define MRSHPC_IRQ3     11
+#define MRSHPC_IRQ2     12
+#define MRSHPC_IRQ1     13
+#define MRSHPC_IRQ0     14
+#define SMC_IRQ         10
+#define EXT_IRQ         5
+#define USB_IRQ         6
+
+
+/* arch/sh/boards/se/7722/irq.c */
+void init_se7722_IRQ(void);
+int se7722_irq_demux(int);
+
+#define __IO_PREFIX             se7722
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7722_H */
diff --git a/include/asm-sh/se7751.h b/include/asm-sh/se7751.h
index 88cd379d9084..02ca9347f043 100644
--- a/include/asm-sh/se7751.h
+++ b/include/asm-sh/se7751.h
@@ -65,6 +65,8 @@
 
 #define IRQ_79C973      13
 
+void init_7751se_IRQ(void);
+
 #define __IO_PREFIX     sh7751se
 #include <asm/io_generic.h>
 
diff --git a/include/asm-sh/se7780.h b/include/asm-sh/se7780.h
new file mode 100644
index 000000000000..40e9b41458cd
--- /dev/null
+++ b/include/asm-sh/se7780.h
@@ -0,0 +1,108 @@
+#ifndef __ASM_SH_SE7780_H
+#define __ASM_SH_SE7780_H
+
+/*
+ * linux/include/asm-sh/se7780.h
+ *
+ * Copyright (C) 2006,2007  Nobuhiro Iwamatsu
+ *
+ * Hitachi UL SolutionEngine 7780 Support.
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License.  See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+#include <asm/addrspace.h>
+
+/* Box specific addresses.  */
+#define SE_AREA0_WIDTH  4               /* Area0: 32bit */
+#define PA_ROM          0xa0000000      /* EPROM */
+#define PA_ROM_SIZE     0x00400000      /* EPROM size 4M byte */
+#define PA_FROM         0xa1000000      /* Flash-ROM */
+#define PA_FROM_SIZE    0x01000000      /* Flash-ROM size 16M byte */
+#define PA_EXT1         0xa4000000
+#define PA_EXT1_SIZE    0x04000000
+#define PA_SM501        PA_EXT1         /* Graphic IC (SM501) */
+#define PA_SM501_SIZE   PA_EXT1_SIZE    /* Graphic IC (SM501) */
+#define PA_SDRAM        0xa8000000      /* DDR-SDRAM(Area2/3) 128MB */
+#define PA_SDRAM_SIZE   0x08000000
+
+#define PA_EXT4         0xb0000000
+#define PA_EXT4_SIZE    0x04000000
+#define PA_EXT_FLASH    PA_EXT4         /* Expansion Flash-ROM */
+
+#define PA_PERIPHERAL   PA_AREA6_IO     /* SW6-6=ON */
+
+#define PA_LAN          (PA_PERIPHERAL + 0)             /* SMC LAN91C111 */
+#define PA_LED_DISP     (PA_PERIPHERAL + 0x02000000)    /* 8words LED Display */
+#define DISP_CHAR_RAM   (7 << 3)
+#define DISP_SEL0_ADDR  (DISP_CHAR_RAM + 0)
+#define DISP_SEL1_ADDR  (DISP_CHAR_RAM + 1)
+#define DISP_SEL2_ADDR  (DISP_CHAR_RAM + 2)
+#define DISP_SEL3_ADDR  (DISP_CHAR_RAM + 3)
+#define DISP_SEL4_ADDR  (DISP_CHAR_RAM + 4)
+#define DISP_SEL5_ADDR  (DISP_CHAR_RAM + 5)
+#define DISP_SEL6_ADDR  (DISP_CHAR_RAM + 6)
+#define DISP_SEL7_ADDR  (DISP_CHAR_RAM + 7)
+
+#define DISP_UDC_RAM    (5 << 3)
+#define PA_FPGA         (PA_PERIPHERAL + 0x03000000) /* FPGA base address */
+
+/* FPGA register address and bit */
+#define FPGA_SFTRST             (PA_FPGA + 0)   /* Soft reset register */
+#define FPGA_INTMSK1            (PA_FPGA + 2)   /* Interrupt Mask register 1 */
+#define FPGA_INTMSK2            (PA_FPGA + 4)   /* Interrupt Mask register 2 */
+#define FPGA_INTSEL1            (PA_FPGA + 6)   /* Interrupt select register 1 */
+#define FPGA_INTSEL2            (PA_FPGA + 8)   /* Interrupt select register 2 */
+#define FPGA_INTSEL3            (PA_FPGA + 10)  /* Interrupt select register 3 */
+#define FPGA_PCI_INTSEL1        (PA_FPGA + 12)  /* PCI Interrupt select register 1 */
+#define FPGA_PCI_INTSEL2        (PA_FPGA + 14)  /* PCI Interrupt select register 2 */
+#define FPGA_INTSET             (PA_FPGA + 16)  /* IRQ/IRL select register */
+#define FPGA_INTSTS1            (PA_FPGA + 18)  /* Interrupt status register 1 */
+#define FPGA_INTSTS2            (PA_FPGA + 20)  /* Interrupt status register 2 */
+#define FPGA_REQSEL             (PA_FPGA + 22)  /* REQ/GNT select register */
+#define FPGA_DBG_LED            (PA_FPGA + 32)  /* Debug LED(D-LED[8:1] */
+#define PA_LED                  FPGA_DBG_LED
+#define FPGA_IVDRID             (PA_FPGA + 36)  /* iVDR ID Register */
+#define FPGA_IVDRPW             (PA_FPGA + 38)  /* iVDR Power ON Register */
+#define FPGA_MMCID              (PA_FPGA + 40)  /* MMC ID Register */
+
+/* FPGA INTSEL position */
+/* INTSEL1 */
+#define IRQPOS_SMC91CX          (0 * 4)
+#define IRQPOS_SM501            (1 * 4)
+/* INTSEL2 */
+#define IRQPOS_EXTINT1          (0 * 4)
+#define IRQPOS_EXTINT2          (1 * 4)
+#define IRQPOS_EXTINT3          (2 * 4)
+#define IRQPOS_EXTINT4          (3 * 4)
+/* INTSEL3 */
+#define IRQPOS_PCCPW            (0 * 4)
+
+/* IDE interrupt */
+#define IRQ_IDE0                67 /* iVDR */
+
+/* SMC interrupt */
+#define SMC_IRQ                 8
+
+/* SM501 interrupt */
+#define SM501_IRQ               0
+
+/* interrupt pin */
+#define IRQPIN_EXTINT1          0 /* IRQ0 pin */
+#define IRQPIN_EXTINT2          1 /* IRQ1 pin */
+#define IRQPIN_EXTINT3          2 /* IRQ2 pin */
+#define IRQPIN_SMC91CX          3 /* IRQ3 pin */
+#define IRQPIN_EXTINT4          4 /* IRQ4 pin */
+#define IRQPIN_PCC0             5 /* IRQ5 pin */
+#define IRQPIN_PCC2             6 /* IRQ6 pin */
+#define IRQPIN_SM501            7 /* IRQ7 pin */
+#define IRQPIN_PCCPW            7 /* IRQ7 pin */
+
+/* arch/sh/boards/se/7780/irq.c */
+void init_se7780_IRQ(void);
+
+#define __IO_PREFIX             se7780
+#include <asm/io_generic.h>
+
+#endif  /* __ASM_SH_SE7780_H */
diff --git a/include/asm-sh/stat.h b/include/asm-sh/stat.h
index 6c41a60657f1..6d6ad26e3a2a 100644
--- a/include/asm-sh/stat.h
+++ b/include/asm-sh/stat.h
@@ -16,15 +16,13 @@ struct __old_kernel_stat {
 };
 
 struct stat {
-        unsigned short st_dev;
-        unsigned short __pad1;
-        unsigned long st_ino;
+        unsigned long  st_dev;
+        unsigned long  st_ino;
         unsigned short st_mode;
         unsigned short st_nlink;
         unsigned short st_uid;
         unsigned short st_gid;
-        unsigned short st_rdev;
-        unsigned short __pad2;
+        unsigned long  st_rdev;
         unsigned long  st_size;
         unsigned long  st_blksize;
         unsigned long  st_blocks;
@@ -38,8 +36,6 @@ struct stat {
         unsigned long  __unused5;
 };
 
-#define STAT_HAVE_NSEC 1
-
 /* This matches struct stat64 in glibc2.1, hence the absolutely
  * insane amounts of padding around dev_t's.
  */
@@ -47,7 +43,9 @@ struct stat64 {
         unsigned long long      st_dev;
         unsigned char   __pad0[4];
 
-        unsigned long   st_ino;
+#define STAT64_HAS_BROKEN_ST_INO        1
+        unsigned long   __st_ino;
+
         unsigned int    st_mode;
         unsigned int    st_nlink;
 
@@ -71,8 +69,9 @@ struct stat64 {
         unsigned long   st_ctime;
         unsigned long   st_ctime_nsec; 
 
-        unsigned long   __unused1;
-        unsigned long   __unused2;
+        unsigned long long      st_ino;
 };
 
+#define STAT_HAVE_NSEC 1
+
 #endif /* __ASM_SH_STAT_H */
diff --git a/include/asm-sh/system.h b/include/asm-sh/system.h
index 4a6a19f4f8a4..e7e96ee0c8a5 100644
--- a/include/asm-sh/system.h
+++ b/include/asm-sh/system.h
@@ -9,6 +9,7 @@
 #include <linux/irqflags.h>
 #include <linux/compiler.h>
 #include <asm/types.h>
+#include <asm/ptrace.h>
 
 /*
  *      switch_to() should switch tasks to task nr n, first
@@ -81,16 +82,6 @@ static inline void sched_cacheflush(void)
 }
 #endif
 
-static inline unsigned long tas(volatile int *m)
-{
-        unsigned long retval;
-
-        __asm__ __volatile__ ("tas.b    @%1\n\t"
-                              "movt     %0"
-                              : "=r" (retval): "r" (m): "t", "memory");
-        return retval;
-}
-
 /*
  * A brief note on ctrl_barrier(), the control register write barrier.
  *
@@ -255,6 +246,8 @@ static inline unsigned long __cmpxchg(volatile void * ptr, unsigned long old,
                                     (unsigned long)_n_, sizeof(*(ptr))); \
   })
 
+extern void die(const char *str, struct pt_regs *regs, long err) __attribute__ ((noreturn));
+
 extern void *set_exception_table_vec(unsigned int vec, void *handler);
 
 static inline void *set_exception_table_evt(unsigned int evt, void *handler)
diff --git a/include/asm-sh64/kdebug.h b/include/asm-sh64/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-sh64/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-sh64/pgtable.h b/include/asm-sh64/pgtable.h
index 6b97c4cb1d64..b875482eb592 100644
--- a/include/asm-sh64/pgtable.h
+++ b/include/asm-sh64/pgtable.h
@@ -485,10 +485,6 @@ extern void update_mmu_cache(struct vm_area_struct * vma,
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #endif /* !__ASSEMBLY__ */
 
 /*
diff --git a/include/asm-sh64/system.h b/include/asm-sh64/system.h
index b1598c26fcb0..5ff94644e8c8 100644
--- a/include/asm-sh64/system.h
+++ b/include/asm-sh64/system.h
@@ -43,8 +43,6 @@ extern struct task_struct *sh64_switch_to(struct task_struct *prev,
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
-#define tas(ptr) (xchg((ptr), 1))
-
 extern void __xchg_called_with_bad_pointer(void);
 
 #define mb()    __asm__ __volatile__ ("synco": : :"memory")
diff --git a/include/asm-sparc/kdebug.h b/include/asm-sparc/kdebug.h
index fba92485fdba..404d80767323 100644
--- a/include/asm-sparc/kdebug.h
+++ b/include/asm-sparc/kdebug.h
@@ -66,4 +66,8 @@ static inline void sp_enter_debugger(void)
 #define KDEBUG_DUNNO2_OFF   0x8
 #define KDEBUG_TEACH_OFF    0xc
 
+enum die_val {
+        DIE_UNUSED,
+};
+
 #endif /* !(_SPARC_KDEBUG_H) */
diff --git a/include/asm-sparc/system.h b/include/asm-sparc/system.h
index 100c3eaf3c1f..8b6d9c9c8b93 100644
--- a/include/asm-sparc/system.h
+++ b/include/asm-sparc/system.h
@@ -241,7 +241,6 @@ static inline unsigned long xchg_u32(__volatile__ unsigned long *m, unsigned lon
 }
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 extern void __xchg_called_with_bad_pointer(void);
 
diff --git a/include/asm-sparc64/Kbuild b/include/asm-sparc64/Kbuild
index a7f44408c93b..854fd3a65acf 100644
--- a/include/asm-sparc64/Kbuild
+++ b/include/asm-sparc64/Kbuild
@@ -8,7 +8,6 @@ header-y += apb.h
 header-y += asi.h
 header-y += bbc.h
 header-y += bpp.h
-header-y += const.h
 header-y += display7seg.h
 header-y += envctrl.h
 header-y += ipc.h
diff --git a/include/asm-sparc64/atomic.h b/include/asm-sparc64/atomic.h
index 2f0bec26a695..3fb4e1f7f186 100644
--- a/include/asm-sparc64/atomic.h
+++ b/include/asm-sparc64/atomic.h
@@ -9,6 +9,7 @@
 #define __ARCH_SPARC64_ATOMIC__
 
 #include <linux/types.h>
+#include <asm/system.h>
 
 typedef struct { volatile int counter; } atomic_t;
 typedef struct { volatile __s64 counter; } atomic64_t;
@@ -70,25 +71,47 @@ extern int atomic64_sub_ret(int, atomic64_t *);
 #define atomic_add_negative(i, v) (atomic_add_ret(i, v) < 0)
 #define atomic64_add_negative(i, v) (atomic64_add_ret(i, v) < 0)
 
-#define atomic_cmpxchg(v, o, n) ((int)cmpxchg(&((v)->counter), (o), (n)))
+#define atomic_cmpxchg(v, o, n) (cmpxchg(&((v)->counter), (o), (n)))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        for (;;) {                                              \
-                if (unlikely(c == (u)))                         \
-                        break;                                  \
-                old = atomic_cmpxchg((v), c, c + (a));          \
-                if (likely(old == c))                           \
-                        break;                                  \
-                c = old;                                        \
-        }                                                       \
-        likely(c != (u));                                       \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
+#define atomic64_cmpxchg(v, o, n) \
+        ((__typeof__((v)->counter))cmpxchg(&((v)->counter), (o), (n)))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
 /* Atomic operations are already serializing */
 #ifdef CONFIG_SMP
 #define smp_mb__before_atomic_dec()     membar_storeload_loadload();
diff --git a/include/asm-sparc64/const.h b/include/asm-sparc64/const.h
deleted file mode 100644
index 8ad902b2ce04..000000000000
--- a/include/asm-sparc64/const.h
+++ /dev/null
@@ -1,19 +0,0 @@
-/* const.h: Macros for dealing with constants.  */
-
-#ifndef _SPARC64_CONST_H
-#define _SPARC64_CONST_H
-
-/* Some constant macros are used in both assembler and
- * C code.  Therefore we cannot annotate them always with
- * 'UL' and other type specificers unilaterally.  We
- * use the following macros to deal with this.
- */
-
-#ifdef __ASSEMBLY__
-#define _AC(X,Y)        X
-#else
-#define _AC(X,Y)        (X##Y)
-#endif
-
-
-#endif /* !(_SPARC64_CONST_H) */
diff --git a/include/asm-sparc64/iommu.h b/include/asm-sparc64/iommu.h
index e199594a1e9b..0b1813f41045 100644
--- a/include/asm-sparc64/iommu.h
+++ b/include/asm-sparc64/iommu.h
@@ -32,6 +32,7 @@ struct iommu {
         unsigned long           iommu_control;
         unsigned long           iommu_tsbbase;
         unsigned long           iommu_flush;
+        unsigned long           iommu_flushinv;
         unsigned long           iommu_ctxflush;
         unsigned long           write_complete_reg;
         unsigned long           dummy_page;
diff --git a/include/asm-sparc64/kdebug.h b/include/asm-sparc64/kdebug.h
index 11251bdd00cb..f8032e73f384 100644
--- a/include/asm-sparc64/kdebug.h
+++ b/include/asm-sparc64/kdebug.h
@@ -7,19 +7,8 @@
 
 struct pt_regs;
 
-struct die_args {
-        struct pt_regs *regs;
-        const char *str;
-        long err;
-        int trapnr;
-        int signr;
-};
-
-extern int register_die_notifier(struct notifier_block *);
-extern int unregister_die_notifier(struct notifier_block *);
 extern int register_page_fault_notifier(struct notifier_block *);
 extern int unregister_page_fault_notifier(struct notifier_block *);
-extern struct atomic_notifier_head sparc64die_chain;
 
 extern void bad_trap(struct pt_regs *, long);
 
@@ -36,16 +25,4 @@ enum die_val {
         DIE_PAGE_FAULT,
 };
 
-static inline int notify_die(enum die_val val,char *str, struct pt_regs *regs,
-                             long err, int trap, int sig)
-{
-        struct die_args args = { .regs          = regs,
-                                 .str           = str,
-                                 .err           = err,
-                                 .trapnr        = trap,
-                                 .signr         = sig };
-
-        return atomic_notifier_call_chain(&sparc64die_chain, val, &args);
-}
-
 #endif
diff --git a/include/asm-sparc64/local.h b/include/asm-sparc64/local.h
index dfde115ac892..c11c530f74d0 100644
--- a/include/asm-sparc64/local.h
+++ b/include/asm-sparc64/local.h
@@ -1,40 +1 @@
-#ifndef _ARCH_SPARC64_LOCAL_H
-#define _ARCH_SPARC64_LOCAL_H
-
-#include <linux/percpu.h>
-#include <asm/atomic.h>
-
-typedef atomic64_t local_t;
-
-#define LOCAL_INIT(i)   ATOMIC64_INIT(i)
-#define local_read(v)   atomic64_read(v)
-#define local_set(v,i)  atomic64_set(v,i)
-
-#define local_inc(v)    atomic64_inc(v)
-#define local_dec(v)    atomic64_dec(v)
-#define local_add(i, v) atomic64_add(i, v)
-#define local_sub(i, v) atomic64_sub(i, v)
-
-#define __local_inc(v)          ((v)->counter++)
-#define __local_dec(v)          ((v)->counter--)
-#define __local_add(i,v)        ((v)->counter+=(i))
-#define __local_sub(i,v)        ((v)->counter-=(i))
-
-/* Use these for per-cpu local_t variables: on some archs they are
- * much more efficient than these naive implementations.  Note they take
- * a variable, not an address.
- */
-#define cpu_local_read(v)       local_read(&__get_cpu_var(v))
-#define cpu_local_set(v, i)     local_set(&__get_cpu_var(v), (i))
-
-#define cpu_local_inc(v)        local_inc(&__get_cpu_var(v))
-#define cpu_local_dec(v)        local_dec(&__get_cpu_var(v))
-#define cpu_local_add(i, v)     local_add((i), &__get_cpu_var(v))
-#define cpu_local_sub(i, v)     local_sub((i), &__get_cpu_var(v))
-
-#define __cpu_local_inc(v)      __local_inc(&__get_cpu_var(v))
-#define __cpu_local_dec(v)      __local_dec(&__get_cpu_var(v))
-#define __cpu_local_add(i, v)   __local_add((i), &__get_cpu_var(v))
-#define __cpu_local_sub(i, v)   __local_sub((i), &__get_cpu_var(v))
-
-#endif /* _ARCH_SPARC64_LOCAL_H */
+#include <asm-generic/local.h>
diff --git a/include/asm-sparc64/lsu.h b/include/asm-sparc64/lsu.h
index e5329c7f5833..79f109840c39 100644
--- a/include/asm-sparc64/lsu.h
+++ b/include/asm-sparc64/lsu.h
@@ -2,7 +2,7 @@
 #ifndef _SPARC64_LSU_H
 #define _SPARC64_LSU_H
 
-#include <asm/const.h>
+#include <linux/const.h>
 
 /* LSU Control Register */
 #define LSU_CONTROL_PM _AC(0x000001fe00000000,UL) /* Phys-watchpoint byte mask*/
diff --git a/include/asm-sparc64/mmu.h b/include/asm-sparc64/mmu.h
index 70af4b6ce136..8abc58f0f9d7 100644
--- a/include/asm-sparc64/mmu.h
+++ b/include/asm-sparc64/mmu.h
@@ -1,8 +1,8 @@
 #ifndef __MMU_H
 #define __MMU_H
 
+#include <linux/const.h>
 #include <asm/page.h>
-#include <asm/const.h>
 #include <asm/hypervisor.h>
 
 #define CTX_NR_BITS             13
diff --git a/include/asm-sparc64/page.h b/include/asm-sparc64/page.h
index ff736eafa64d..7af1077451ff 100644
--- a/include/asm-sparc64/page.h
+++ b/include/asm-sparc64/page.h
@@ -5,7 +5,7 @@
 
 #ifdef __KERNEL__
 
-#include <asm/const.h>
+#include <linux/const.h>
 
 #if defined(CONFIG_SPARC64_PAGE_SIZE_8KB)
 #define PAGE_SHIFT   13
diff --git a/include/asm-sparc64/pgalloc.h b/include/asm-sparc64/pgalloc.h
index 5891ff7ba760..5d66b858a965 100644
--- a/include/asm-sparc64/pgalloc.h
+++ b/include/asm-sparc64/pgalloc.h
@@ -6,6 +6,7 @@
 #include <linux/sched.h>
 #include <linux/mm.h>
 #include <linux/slab.h>
+#include <linux/quicklist.h>
 
 #include <asm/spitfire.h>
 #include <asm/cpudata.h>
@@ -13,52 +14,50 @@
 #include <asm/page.h>
 
 /* Page table allocation/freeing. */
-extern struct kmem_cache *pgtable_cache;
 
 static inline pgd_t *pgd_alloc(struct mm_struct *mm)
 {
-        return kmem_cache_alloc(pgtable_cache, GFP_KERNEL);
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
 }
 
 static inline void pgd_free(pgd_t *pgd)
 {
-        kmem_cache_free(pgtable_cache, pgd);
+        quicklist_free(0, NULL, pgd);
 }
 
 #define pud_populate(MM, PUD, PMD)      pud_set(PUD, PMD)
 
 static inline pmd_t *pmd_alloc_one(struct mm_struct *mm, unsigned long addr)
 {
-        return kmem_cache_alloc(pgtable_cache,
-                                GFP_KERNEL|__GFP_REPEAT);
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
 }
 
 static inline void pmd_free(pmd_t *pmd)
 {
-        kmem_cache_free(pgtable_cache, pmd);
+        quicklist_free(0, NULL, pmd);
 }
 
 static inline pte_t *pte_alloc_one_kernel(struct mm_struct *mm,
                                           unsigned long address)
 {
-        return kmem_cache_alloc(pgtable_cache,
-                                GFP_KERNEL|__GFP_REPEAT);
+        return quicklist_alloc(0, GFP_KERNEL, NULL);
 }
 
 static inline struct page *pte_alloc_one(struct mm_struct *mm,
                                          unsigned long address)
 {
-        return virt_to_page(pte_alloc_one_kernel(mm, address));
+        void *pg = quicklist_alloc(0, GFP_KERNEL, NULL);
+        return pg ? virt_to_page(pg) : NULL;
 }
                 
 static inline void pte_free_kernel(pte_t *pte)
 {
-        kmem_cache_free(pgtable_cache, pte);
+        quicklist_free(0, NULL, pte);
 }
 
 static inline void pte_free(struct page *ptepage)
 {
-        pte_free_kernel(page_address(ptepage));
+        quicklist_free_page(0, NULL, ptepage);
 }
 
 
@@ -66,6 +65,9 @@ static inline void pte_free(struct page *ptepage)
 #define pmd_populate(MM,PMD,PTE_PAGE)           \
         pmd_populate_kernel(MM,PMD,page_address(PTE_PAGE))
 
-#define check_pgt_cache()       do { } while (0)
+static inline void check_pgt_cache(void)
+{
+        quicklist_trim(0, NULL, 25, 16);
+}
 
 #endif /* _SPARC64_PGALLOC_H */
diff --git a/include/asm-sparc64/pgtable.h b/include/asm-sparc64/pgtable.h
index 46705ef47d27..9e80ad43b29c 100644
--- a/include/asm-sparc64/pgtable.h
+++ b/include/asm-sparc64/pgtable.h
@@ -15,13 +15,13 @@
 #include <asm-generic/pgtable-nopud.h>
 
 #include <linux/compiler.h>
+#include <linux/const.h>
 #include <asm/types.h>
 #include <asm/spitfire.h>
 #include <asm/asi.h>
 #include <asm/system.h>
 #include <asm/page.h>
 #include <asm/processor.h>
-#include <asm/const.h>
 
 /* The kernel image occupies 0x4000000 to 0x1000000 (4MB --> 32MB).
  * The page copy blockops can use 0x2000000 to 0x4000000.
diff --git a/include/asm-sparc64/pstate.h b/include/asm-sparc64/pstate.h
index 49a7924a89ab..f3c45484c636 100644
--- a/include/asm-sparc64/pstate.h
+++ b/include/asm-sparc64/pstate.h
@@ -2,7 +2,7 @@
 #ifndef _SPARC64_PSTATE_H
 #define _SPARC64_PSTATE_H
 
-#include <asm/const.h>
+#include <linux/const.h>
 
 /* The V9 PSTATE Register (with SpitFire extensions).
  *
diff --git a/include/asm-sparc64/sfafsr.h b/include/asm-sparc64/sfafsr.h
index 2f792c20b53c..e96137b04a4f 100644
--- a/include/asm-sparc64/sfafsr.h
+++ b/include/asm-sparc64/sfafsr.h
@@ -1,7 +1,7 @@
 #ifndef _SPARC64_SFAFSR_H
 #define _SPARC64_SFAFSR_H
 
-#include <asm/const.h>
+#include <linux/const.h>
 
 /* Spitfire Asynchronous Fault Status register, ASI=0x4C VA<63:0>=0x0 */
 
diff --git a/include/asm-sparc64/system.h b/include/asm-sparc64/system.h
index 32281acb878b..8ba380ec6daa 100644
--- a/include/asm-sparc64/system.h
+++ b/include/asm-sparc64/system.h
@@ -253,7 +253,6 @@ static inline unsigned long xchg64(__volatile__ unsigned long *m, unsigned long
 }
 
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
-#define tas(ptr) (xchg((ptr),1))
 
 extern void __xchg_called_with_bad_pointer(void);
 
diff --git a/include/asm-um/cmpxchg.h b/include/asm-um/cmpxchg.h
new file mode 100644
index 000000000000..529376a99885
--- /dev/null
+++ b/include/asm-um/cmpxchg.h
@@ -0,0 +1,6 @@
+#ifndef __UM_CMPXCHG_H
+#define __UM_CMPXCHG_H
+
+#include "asm/arch/cmpxchg.h"
+
+#endif
diff --git a/include/asm-um/kdebug.h b/include/asm-um/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-um/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-um/page.h b/include/asm-um/page.h
index 4296d3135aa9..8e310d81e5b4 100644
--- a/include/asm-um/page.h
+++ b/include/asm-um/page.h
@@ -114,9 +114,6 @@ extern unsigned long uml_physmem;
 extern struct page *arch_validate(struct page *page, gfp_t mask, int order);
 #define HAVE_ARCH_VALIDATE
 
-extern void arch_free_page(struct page *page, int order);
-#define HAVE_ARCH_FREE_PAGE
-
 #include <asm-generic/memory_model.h>
 #include <asm-generic/page.h>
 
diff --git a/include/asm-um/tlbflush.h b/include/asm-um/tlbflush.h
index 522aa30f7eaa..e78c28c1f350 100644
--- a/include/asm-um/tlbflush.h
+++ b/include/asm-um/tlbflush.h
@@ -7,6 +7,7 @@
 #define __UM_TLBFLUSH_H
 
 #include <linux/mm.h>
+#include "choose-mode.h"
 
 /*
  * TLB flushing:
@@ -24,6 +25,18 @@ extern void flush_tlb_all(void);
 extern void flush_tlb_mm(struct mm_struct *mm);
 extern void flush_tlb_range(struct vm_area_struct *vma, unsigned long start, 
                             unsigned long end);
+extern void flush_tlb_page_skas(struct vm_area_struct *vma,
+                                unsigned long address);
+
+static inline void flush_tlb_page(struct vm_area_struct *vma,
+                                  unsigned long address)
+{
+        address &= PAGE_MASK;
+
+        CHOOSE_MODE(flush_tlb_range(vma, address, address + PAGE_SIZE),
+                    flush_tlb_page_skas(vma, address));
+}
+
 extern void flush_tlb_page(struct vm_area_struct *vma, unsigned long vmaddr);
 extern void flush_tlb_kernel_vm(void);
 extern void flush_tlb_kernel_range(unsigned long start, unsigned long end);
@@ -35,14 +48,3 @@ static inline void flush_tlb_pgtables(struct mm_struct *mm,
 }
 
 #endif
-
-/*
- * Overrides for Emacs so that we follow Linus's tabbing style.
- * Emacs will notice this stuff at the end of the file and automatically
- * adjust the settings for this buffer only.  This must remain at the end
- * of the file.
- * ---------------------------------------------------------------------------
- * Local variables:
- * c-file-style: "linux"
- * End:
- */
diff --git a/include/asm-v850/kdebug.h b/include/asm-v850/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-v850/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-v850/system.h b/include/asm-v850/system.h
index da39916f10b0..0de2481fd990 100644
--- a/include/asm-v850/system.h
+++ b/include/asm-v850/system.h
@@ -76,7 +76,6 @@ static inline int irqs_disabled (void)
 
 #define xchg(ptr, with) \
   ((__typeof__ (*(ptr)))__xchg ((unsigned long)(with), (ptr), sizeof (*(ptr))))
-#define tas(ptr) (xchg ((ptr), 1))
 
 static inline unsigned long __xchg (unsigned long with,
                                     __volatile__ void *ptr, int size)
diff --git a/include/asm-x86_64/Kbuild b/include/asm-x86_64/Kbuild
index 89ad1fc27c8b..75a2deffca68 100644
--- a/include/asm-x86_64/Kbuild
+++ b/include/asm-x86_64/Kbuild
@@ -19,4 +19,3 @@ unifdef-y += mce.h
 unifdef-y += msr.h
 unifdef-y += mtrr.h
 unifdef-y += vsyscall.h
-unifdef-y += const.h
diff --git a/include/asm-x86_64/atomic.h b/include/asm-x86_64/atomic.h
index 706ca4b60000..f2e64634fa48 100644
--- a/include/asm-x86_64/atomic.h
+++ b/include/asm-x86_64/atomic.h
@@ -2,6 +2,7 @@
 #define __ARCH_X86_64_ATOMIC__
 
 #include <asm/alternative.h>
+#include <asm/cmpxchg.h>
 
 /* atomic_t should be 32 bit signed type */
 
@@ -375,8 +376,8 @@ static __inline__ long atomic64_add_return(long i, atomic64_t *v)
         long __i = i;
         __asm__ __volatile__(
                 LOCK_PREFIX "xaddq %0, %1;"
-                :"=r"(i)
-                :"m"(v->counter), "0"(i));
+                :"+r" (i), "+m" (v->counter)
+                : : "memory");
         return i + __i;
 }
 
@@ -388,7 +389,10 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t *v)
 #define atomic64_inc_return(v)  (atomic64_add_return(1,v))
 #define atomic64_dec_return(v)  (atomic64_sub_return(1,v))
 
-#define atomic_cmpxchg(v, old, new) ((int)cmpxchg(&((v)->counter), old, new))
+#define atomic64_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
+#define atomic64_xchg(v, new) (xchg(&((v)->counter), new))
+
+#define atomic_cmpxchg(v, old, new) (cmpxchg(&((v)->counter), old, new))
 #define atomic_xchg(v, new) (xchg(&((v)->counter), new))
 
 /**
@@ -400,22 +404,49 @@ static __inline__ long atomic64_sub_return(long i, atomic64_t *v)
  * Atomically adds @a to @v, so long as it was not @u.
  * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        for (;;) {                                              \
-                if (unlikely(c == (u)))                         \
-                        break;                                  \
-                old = atomic_cmpxchg((v), c, c + (a));          \
-                if (likely(old == c))                           \
-                        break;                                  \
-                c = old;                                        \
-        }                                                       \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
+/**
+ * atomic64_add_unless - add unless the number is a given value
+ * @v: pointer of type atomic64_t
+ * @a: the amount to add to v...
+ * @u: ...unless v is equal to u.
+ *
+ * Atomically adds @a to @v, so long as it was not @u.
+ * Returns non-zero if @v was not @u, and zero otherwise.
+ */
+static __inline__ int atomic64_add_unless(atomic64_t *v, long a, long u)
+{
+        long c, old;
+        c = atomic64_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic64_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
+#define atomic64_inc_not_zero(v) atomic64_add_unless((v), 1, 0)
+
 /* These are x86-specific, used by some header files */
 #define atomic_clear_mask(mask, addr) \
 __asm__ __volatile__(LOCK_PREFIX "andl %0,%1" \
diff --git a/include/asm-x86_64/cmpxchg.h b/include/asm-x86_64/cmpxchg.h
new file mode 100644
index 000000000000..09a6b6b6b74d
--- /dev/null
+++ b/include/asm-x86_64/cmpxchg.h
@@ -0,0 +1,134 @@
+#ifndef __ASM_CMPXCHG_H
+#define __ASM_CMPXCHG_H
+
+#include <asm/alternative.h> /* Provides LOCK_PREFIX */
+
+#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
+
+#define __xg(x) ((volatile long *)(x))
+
+static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
+{
+        *ptr = val;
+}
+
+#define _set_64bit set_64bit
+
+/*
+ * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
+ * Note 2: xchg has side effect, so that attribute volatile is necessary,
+ *        but generally the primitive is invalid, *ptr is output argument. --ANK
+ */
+static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
+{
+        switch (size) {
+                case 1:
+                        __asm__ __volatile__("xchgb %b0,%1"
+                                :"=q" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+                case 2:
+                        __asm__ __volatile__("xchgw %w0,%1"
+                                :"=r" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+                case 4:
+                        __asm__ __volatile__("xchgl %k0,%1"
+                                :"=r" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+                case 8:
+                        __asm__ __volatile__("xchgq %0,%1"
+                                :"=r" (x)
+                                :"m" (*__xg(ptr)), "0" (x)
+                                :"memory");
+                        break;
+        }
+        return x;
+}
+
+/*
+ * Atomic compare and exchange.  Compare OLD with MEM, if identical,
+ * store NEW in MEM.  Return the initial value in MEM.  Success is
+ * indicated by comparing RETURN with OLD.
+ */
+
+#define __HAVE_ARCH_CMPXCHG 1
+
+static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
+                                      unsigned long new, int size)
+{
+        unsigned long prev;
+        switch (size) {
+        case 1:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
+                                     : "=a"(prev)
+                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 2:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 4:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 8:
+                __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        }
+        return old;
+}
+
+static inline unsigned long __cmpxchg_local(volatile void *ptr,
+                        unsigned long old, unsigned long new, int size)
+{
+        unsigned long prev;
+        switch (size) {
+        case 1:
+                __asm__ __volatile__("cmpxchgb %b1,%2"
+                                     : "=a"(prev)
+                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 2:
+                __asm__ __volatile__("cmpxchgw %w1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 4:
+                __asm__ __volatile__("cmpxchgl %k1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        case 8:
+                __asm__ __volatile__("cmpxchgq %1,%2"
+                                     : "=a"(prev)
+                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
+                                     : "memory");
+                return prev;
+        }
+        return old;
+}
+
+#define cmpxchg(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
+                                        (unsigned long)(n),sizeof(*(ptr))))
+#define cmpxchg_local(ptr,o,n)\
+        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
+                                        (unsigned long)(n),sizeof(*(ptr))))
+
+#endif
diff --git a/include/asm-x86_64/kdebug.h b/include/asm-x86_64/kdebug.h
index 2b0c088e2957..74feae945a26 100644
--- a/include/asm-x86_64/kdebug.h
+++ b/include/asm-x86_64/kdebug.h
@@ -5,19 +5,8 @@
 
 struct pt_regs;
 
-struct die_args {
-        struct pt_regs *regs;
-        const char *str;
-        long err;
-        int trapnr;
-        int signr;
-};
-
-extern int register_die_notifier(struct notifier_block *);
-extern int unregister_die_notifier(struct notifier_block *);
 extern int register_page_fault_notifier(struct notifier_block *);
 extern int unregister_page_fault_notifier(struct notifier_block *);
-extern struct atomic_notifier_head die_chain;
 
 /* Grossly misnamed. */
 enum die_val {
@@ -33,22 +22,10 @@ enum die_val {
         DIE_GPF,
         DIE_CALL,
         DIE_NMI_IPI,
+        DIE_NMI_POST,
         DIE_PAGE_FAULT,
 };
 
-static inline int notify_die(enum die_val val, const char *str,
-                        struct pt_regs *regs, long err, int trap, int sig)
-{
-        struct die_args args = {
-                .regs = regs,
-                .str = str,
-                .err = err,
-                .trapnr = trap,
-                .signr = sig
-        };
-        return atomic_notifier_call_chain(&die_chain, val, &args);
-} 
-
 extern void printk_address(unsigned long address);
 extern void die(const char *,struct pt_regs *,long);
 extern void __die(const char *,struct pt_regs *,long);
diff --git a/include/asm-x86_64/kexec.h b/include/asm-x86_64/kexec.h
index 5fab957e1091..738e581b67f8 100644
--- a/include/asm-x86_64/kexec.h
+++ b/include/asm-x86_64/kexec.h
@@ -48,8 +48,6 @@
 /* The native architecture */
 #define KEXEC_ARCH KEXEC_ARCH_X86_64
 
-#define MAX_NOTE_BYTES 1024
-
 /*
  * Saving the registers of the cpu on which panic occured in
  * crash_kexec to save a valid sp. The registers of other cpus
diff --git a/include/asm-x86_64/local.h b/include/asm-x86_64/local.h
index e769e6200225..e87492bb0693 100644
--- a/include/asm-x86_64/local.h
+++ b/include/asm-x86_64/local.h
@@ -2,49 +2,183 @@
 #define _ARCH_X8664_LOCAL_H
 
 #include <linux/percpu.h>
+#include <asm/atomic.h>
 
 typedef struct
 {
-        volatile long counter;
+        atomic_long_t a;
 } local_t;
 
-#define LOCAL_INIT(i)   { (i) }
+#define LOCAL_INIT(i)   { ATOMIC_LONG_INIT(i) }
 
-#define local_read(v)   ((v)->counter)
-#define local_set(v,i)  (((v)->counter) = (i))
+#define local_read(l)   atomic_long_read(&(l)->a)
+#define local_set(l,i)  atomic_long_set(&(l)->a, (i))
 
-static inline void local_inc(local_t *v)
+static inline void local_inc(local_t *l)
 {
         __asm__ __volatile__(
                 "incq %0"
-                :"=m" (v->counter)
-                :"m" (v->counter));
+                :"=m" (l->a.counter)
+                :"m" (l->a.counter));
 }
 
-static inline void local_dec(local_t *v)
+static inline void local_dec(local_t *l)
 {
         __asm__ __volatile__(
                 "decq %0"
-                :"=m" (v->counter)
-                :"m" (v->counter));
+                :"=m" (l->a.counter)
+                :"m" (l->a.counter));
 }
 
-static inline void local_add(long i, local_t *v)
+static inline void local_add(long i, local_t *l)
 {
         __asm__ __volatile__(
                 "addq %1,%0"
-                :"=m" (v->counter)
-                :"ir" (i), "m" (v->counter));
+                :"=m" (l->a.counter)
+                :"ir" (i), "m" (l->a.counter));
 }
 
-static inline void local_sub(long i, local_t *v)
+static inline void local_sub(long i, local_t *l)
 {
         __asm__ __volatile__(
                 "subq %1,%0"
-                :"=m" (v->counter)
-                :"ir" (i), "m" (v->counter));
+                :"=m" (l->a.counter)
+                :"ir" (i), "m" (l->a.counter));
 }
 
+/**
+ * local_sub_and_test - subtract value from variable and test result
+ * @i: integer value to subtract
+ * @l: pointer to type local_t
+ *
+ * Atomically subtracts @i from @l and returns
+ * true if the result is zero, or false for all
+ * other cases.
+ */
+static __inline__ int local_sub_and_test(long i, local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "subq %2,%0; sete %1"
+                :"=m" (l->a.counter), "=qm" (c)
+                :"ir" (i), "m" (l->a.counter) : "memory");
+        return c;
+}
+
+/**
+ * local_dec_and_test - decrement and test
+ * @l: pointer to type local_t
+ *
+ * Atomically decrements @l by 1 and
+ * returns true if the result is 0, or false for all other
+ * cases.
+ */
+static __inline__ int local_dec_and_test(local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "decq %0; sete %1"
+                :"=m" (l->a.counter), "=qm" (c)
+                :"m" (l->a.counter) : "memory");
+        return c != 0;
+}
+
+/**
+ * local_inc_and_test - increment and test
+ * @l: pointer to type local_t
+ *
+ * Atomically increments @l by 1
+ * and returns true if the result is zero, or false for all
+ * other cases.
+ */
+static __inline__ int local_inc_and_test(local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "incq %0; sete %1"
+                :"=m" (l->a.counter), "=qm" (c)
+                :"m" (l->a.counter) : "memory");
+        return c != 0;
+}
+
+/**
+ * local_add_negative - add and test if negative
+ * @i: integer value to add
+ * @l: pointer to type local_t
+ *
+ * Atomically adds @i to @l and returns true
+ * if the result is negative, or false when
+ * result is greater than or equal to zero.
+ */
+static __inline__ int local_add_negative(long i, local_t *l)
+{
+        unsigned char c;
+
+        __asm__ __volatile__(
+                "addq %2,%0; sets %1"
+                :"=m" (l->a.counter), "=qm" (c)
+                :"ir" (i), "m" (l->a.counter) : "memory");
+        return c;
+}
+
+/**
+ * local_add_return - add and return
+ * @i: integer value to add
+ * @l: pointer to type local_t
+ *
+ * Atomically adds @i to @l and returns @i + @l
+ */
+static __inline__ long local_add_return(long i, local_t *l)
+{
+        long __i = i;
+        __asm__ __volatile__(
+                "xaddq %0, %1;"
+                :"+r" (i), "+m" (l->a.counter)
+                : : "memory");
+        return i + __i;
+}
+
+static __inline__ long local_sub_return(long i, local_t *l)
+{
+        return local_add_return(-i,l);
+}
+
+#define local_inc_return(l)  (local_add_return(1,l))
+#define local_dec_return(l)  (local_sub_return(1,l))
+
+#define local_cmpxchg(l, o, n) \
+        (cmpxchg_local(&((l)->a.counter), (o), (n)))
+/* Always has a lock prefix */
+#define local_xchg(l, n) (xchg(&((l)->a.counter), (n)))
+
+/**
+ * atomic_up_add_unless - add unless the number is a given value
+ * @l: pointer of type local_t
+ * @a: the amount to add to l...
+ * @u: ...unless l is equal to u.
+ *
+ * Atomically adds @a to @l, so long as it was not @u.
+ * Returns non-zero if @l was not @u, and zero otherwise.
+ */
+#define local_add_unless(l, a, u)                               \
+({                                                              \
+        long c, old;                                            \
+        c = local_read(l);                                      \
+        for (;;) {                                              \
+                if (unlikely(c == (u)))                         \
+                        break;                                  \
+                old = local_cmpxchg((l), c, c + (a));   \
+                if (likely(old == c))                           \
+                        break;                                  \
+                c = old;                                        \
+        }                                                       \
+        c != (u);                                               \
+})
+#define local_inc_not_zero(l) local_add_unless((l), 1, 0)
+
 /* On x86-64 these are better than the atomic variants on SMP kernels
    because they dont use a lock prefix. */
 #define __local_inc(l)          local_inc(l)
@@ -62,27 +196,27 @@ static inline void local_sub(long i, local_t *v)
 
 /* Need to disable preemption for the cpu local counters otherwise we could
    still access a variable of a previous CPU in a non atomic way. */
-#define cpu_local_wrap_v(v)             \
+#define cpu_local_wrap_v(l)             \
         ({ local_t res__;               \
            preempt_disable();           \
-           res__ = (v);                 \
+           res__ = (l);                 \
            preempt_enable();            \
            res__; })
-#define cpu_local_wrap(v)               \
+#define cpu_local_wrap(l)               \
         ({ preempt_disable();           \
-           v;                           \
+           l;                           \
            preempt_enable(); })         \
 
-#define cpu_local_read(v)    cpu_local_wrap_v(local_read(&__get_cpu_var(v)))
-#define cpu_local_set(v, i)  cpu_local_wrap(local_set(&__get_cpu_var(v), (i)))
-#define cpu_local_inc(v)     cpu_local_wrap(local_inc(&__get_cpu_var(v)))
-#define cpu_local_dec(v)     cpu_local_wrap(local_dec(&__get_cpu_var(v)))
-#define cpu_local_add(i, v)  cpu_local_wrap(local_add((i), &__get_cpu_var(v)))
-#define cpu_local_sub(i, v)  cpu_local_wrap(local_sub((i), &__get_cpu_var(v)))
+#define cpu_local_read(l)    cpu_local_wrap_v(local_read(&__get_cpu_var(l)))
+#define cpu_local_set(l, i)  cpu_local_wrap(local_set(&__get_cpu_var(l), (i)))
+#define cpu_local_inc(l)     cpu_local_wrap(local_inc(&__get_cpu_var(l)))
+#define cpu_local_dec(l)     cpu_local_wrap(local_dec(&__get_cpu_var(l)))
+#define cpu_local_add(i, l)  cpu_local_wrap(local_add((i), &__get_cpu_var(l)))
+#define cpu_local_sub(i, l)  cpu_local_wrap(local_sub((i), &__get_cpu_var(l)))
 
-#define __cpu_local_inc(v)      cpu_local_inc(v)
-#define __cpu_local_dec(v)      cpu_local_dec(v)
-#define __cpu_local_add(i, v)   cpu_local_add((i), (v))
-#define __cpu_local_sub(i, v)   cpu_local_sub((i), (v))
+#define __cpu_local_inc(l)      cpu_local_inc(l)
+#define __cpu_local_dec(l)      cpu_local_dec(l)
+#define __cpu_local_add(i, l)   cpu_local_add((i), (l))
+#define __cpu_local_sub(i, l)   cpu_local_sub((i), (l))
 
-#endif /* _ARCH_I386_LOCAL_H */
+#endif /* _ARCH_X8664_LOCAL_H */
diff --git a/include/asm-x86_64/msr.h b/include/asm-x86_64/msr.h
index a524f0325673..d5c55b80da54 100644
--- a/include/asm-x86_64/msr.h
+++ b/include/asm-x86_64/msr.h
@@ -4,6 +4,7 @@
 #include <asm/msr-index.h>
 
 #ifndef __ASSEMBLY__
+#include <linux/errno.h>
 /*
  * Access to machine-specific registers (available on 586 and better only)
  * Note: the rd* operations modify the parameters directly (without using
@@ -162,6 +163,8 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #ifdef CONFIG_SMP
 void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
 void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
+int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h);
+int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h);
 #else  /*  CONFIG_SMP  */
 static inline void rdmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
 {
@@ -171,6 +174,14 @@ static inline void wrmsr_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
 {
         wrmsr(msr_no, l, h);
 }
+static inline int rdmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 *l, u32 *h)
+{
+        return rdmsr_safe(msr_no, l, h);
+}
+static inline int wrmsr_safe_on_cpu(unsigned int cpu, u32 msr_no, u32 l, u32 h)
+{
+        return wrmsr_safe(msr_no, l, h);
+}
 #endif  /* CONFIG_SMP */
 #endif /* __ASSEMBLY__ */
 #endif  /* X86_64_MSR_H */
diff --git a/include/asm-x86_64/page.h b/include/asm-x86_64/page.h
index b17fc16ec2eb..dee632fa457d 100644
--- a/include/asm-x86_64/page.h
+++ b/include/asm-x86_64/page.h
@@ -1,7 +1,7 @@
 #ifndef _X86_64_PAGE_H
 #define _X86_64_PAGE_H
 
-#include <asm/const.h>
+#include <linux/const.h>
 
 /* PAGE_SHIFT determines the page size */
 #define PAGE_SHIFT      12
@@ -79,9 +79,10 @@ extern unsigned long phys_base;
 
 #define __PHYSICAL_START        CONFIG_PHYSICAL_START
 #define __KERNEL_ALIGN          0x200000
+
 #define __START_KERNEL          (__START_KERNEL_map + __PHYSICAL_START)
-#define __START_KERNEL_map      0xffffffff80000000
-#define __PAGE_OFFSET           0xffff810000000000
+#define __START_KERNEL_map      _AC(0xffffffff80000000, UL)
+#define __PAGE_OFFSET           _AC(0xffff810000000000, UL)
 
 /* to align the pointer to the (next) page boundary */
 #define PAGE_ALIGN(addr)        (((addr)+PAGE_SIZE-1)&PAGE_MASK)
@@ -93,27 +94,23 @@ extern unsigned long phys_base;
 #define __VIRTUAL_MASK          ((_AC(1,UL) << __VIRTUAL_MASK_SHIFT) - 1)
 
 #define KERNEL_TEXT_SIZE  (40*1024*1024)
-#define KERNEL_TEXT_START 0xffffffff80000000
+#define KERNEL_TEXT_START _AC(0xffffffff80000000, UL)
+#define PAGE_OFFSET             __PAGE_OFFSET
 
 #ifndef __ASSEMBLY__
 
 #include <asm/bug.h>
 
-#endif /* __ASSEMBLY__ */
+extern unsigned long __phys_addr(unsigned long);
 
-#define PAGE_OFFSET             __PAGE_OFFSET
+#endif /* __ASSEMBLY__ */
 
-/* Note: __pa(&symbol_visible_to_c) should be always replaced with __pa_symbol.
-   Otherwise you risk miscompilation. */
-#define __pa(x)                 ((unsigned long)(x) - PAGE_OFFSET)
-/* __pa_symbol should be used for C visible symbols.
-   This seems to be the official gcc blessed way to do such arithmetic. */ 
-#define __pa_symbol(x)          \
-        ({unsigned long v;  \
-          asm("" : "=r" (v) : "0" (x)); \
-          ((v - __START_KERNEL_map) + phys_base); })
+#define __pa(x)         __phys_addr((unsigned long)(x))
+#define __pa_symbol(x)  __phys_addr((unsigned long)(x))
 
 #define __va(x)                 ((void *)((unsigned long)(x)+PAGE_OFFSET))
+#define __boot_va(x)            __va(x)
+#define __boot_pa(x)            __pa(x)
 #ifdef CONFIG_FLATMEM
 #define pfn_valid(pfn)          ((pfn) < end_pfn)
 #endif
diff --git a/include/asm-x86_64/pgtable.h b/include/asm-x86_64/pgtable.h
index 599993f6ba84..08b9831f2e14 100644
--- a/include/asm-x86_64/pgtable.h
+++ b/include/asm-x86_64/pgtable.h
@@ -1,7 +1,7 @@
 #ifndef _X86_64_PGTABLE_H
 #define _X86_64_PGTABLE_H
 
-#include <asm/const.h>
+#include <linux/const.h>
 #ifndef __ASSEMBLY__
 
 /*
@@ -19,7 +19,7 @@ extern pmd_t level2_kernel_pgt[512];
 extern pgd_t init_level4_pgt[];
 extern unsigned long __supported_pte_mask;
 
-#define swapper_pg_dir ((pgd_t *)NULL)
+#define swapper_pg_dir init_level4_pgt
 
 extern void paging_init(void);
 extern void clear_kernel_mapping(unsigned long addr, unsigned long size);
@@ -29,7 +29,7 @@ extern void clear_kernel_mapping(unsigned long addr, unsigned long size);
  * for zero-mapped memory areas etc..
  */
 extern unsigned long empty_zero_page[PAGE_SIZE/sizeof(unsigned long)];
-#define ZERO_PAGE(vaddr) (pfn_to_page(__pa_symbol(&empty_zero_page) >> PAGE_SHIFT))
+#define ZERO_PAGE(vaddr) (virt_to_page(empty_zero_page))
 
 #endif /* !__ASSEMBLY__ */
 
@@ -134,11 +134,11 @@ static inline pte_t ptep_get_and_clear_full(struct mm_struct *mm, unsigned long
 #define USER_PTRS_PER_PGD       ((TASK_SIZE-1)/PGDIR_SIZE+1)
 #define FIRST_USER_ADDRESS      0
 
-#define MAXMEM           0x3fffffffffff
-#define VMALLOC_START    0xffffc20000000000
-#define VMALLOC_END      0xffffe1ffffffffff
-#define MODULES_VADDR    0xffffffff88000000
-#define MODULES_END      0xfffffffffff00000
+#define MAXMEM           _AC(0x3fffffffffff, UL)
+#define VMALLOC_START    _AC(0xffffc20000000000, UL)
+#define VMALLOC_END      _AC(0xffffe1ffffffffff, UL)
+#define MODULES_VADDR    _AC(0xffffffff88000000, UL)
+#define MODULES_END      _AC(0xfffffffffff00000, UL)
 #define MODULES_LEN   (MODULES_END - MODULES_VADDR)
 
 #define _PAGE_BIT_PRESENT       0
@@ -411,17 +411,12 @@ static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
 
 extern spinlock_t pgd_lock;
 extern struct list_head pgd_list;
-void vmalloc_sync_all(void);
 
 extern int kern_addr_valid(unsigned long addr); 
 
 #define io_remap_pfn_range(vma, vaddr, pfn, size, prot)         \
                 remap_pfn_range(vma, vaddr, pfn, size, prot)
 
-#define MK_IOSPACE_PFN(space, pfn)      (pfn)
-#define GET_IOSPACE(pfn)                0
-#define GET_PFN(pfn)                    (pfn)
-
 #define HAVE_ARCH_UNMAPPED_AREA
 
 #define pgtable_cache_init()   do { } while (0)
diff --git a/include/asm-x86_64/serial.h b/include/asm-x86_64/serial.h
index b0496e0d72a6..8ebd765c674a 100644
--- a/include/asm-x86_64/serial.h
+++ b/include/asm-x86_64/serial.h
@@ -11,19 +11,3 @@
  * megabits/second; but this requires the faster clock.
  */
 #define BASE_BAUD ( 1843200 / 16 )
-
-/* Standard COM flags (except for COM4, because of the 8514 problem) */
-#ifdef CONFIG_SERIAL_DETECT_IRQ
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST | ASYNC_AUTO_IRQ)
-#define STD_COM4_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_AUTO_IRQ)
-#else
-#define STD_COM_FLAGS (ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST)
-#define STD_COM4_FLAGS ASYNC_BOOT_AUTOCONF
-#endif
-
-#define SERIAL_PORT_DFNS                        \
-        /* UART CLK   PORT IRQ     FLAGS        */                      \
-        { 0, BASE_BAUD, 0x3F8, 4, STD_COM_FLAGS },      /* ttyS0 */     \
-        { 0, BASE_BAUD, 0x2F8, 3, STD_COM_FLAGS },      /* ttyS1 */     \
-        { 0, BASE_BAUD, 0x3E8, 4, STD_COM_FLAGS },      /* ttyS2 */     \
-        { 0, BASE_BAUD, 0x2E8, 3, STD_COM4_FLAGS },     /* ttyS3 */
diff --git a/include/asm-x86_64/system.h b/include/asm-x86_64/system.h
index 213b7fe5d998..b7b8021e8c43 100644
--- a/include/asm-x86_64/system.h
+++ b/include/asm-x86_64/system.h
@@ -3,7 +3,7 @@
 
 #include <linux/kernel.h>
 #include <asm/segment.h>
-#include <asm/alternative.h>
+#include <asm/cmpxchg.h>
 
 #ifdef __KERNEL__
 
@@ -124,100 +124,6 @@ static inline void sched_cacheflush(void)
 
 #define nop() __asm__ __volatile__ ("nop")
 
-#define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
-
-#define tas(ptr) (xchg((ptr),1))
-
-#define __xg(x) ((volatile long *)(x))
-
-static inline void set_64bit(volatile unsigned long *ptr, unsigned long val)
-{
-        *ptr = val;
-}
-
-#define _set_64bit set_64bit
-
-/*
- * Note: no "lock" prefix even on SMP: xchg always implies lock anyway
- * Note 2: xchg has side effect, so that attribute volatile is necessary,
- *        but generally the primitive is invalid, *ptr is output argument. --ANK
- */
-static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int size)
-{
-        switch (size) {
-                case 1:
-                        __asm__ __volatile__("xchgb %b0,%1"
-                                :"=q" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-                case 2:
-                        __asm__ __volatile__("xchgw %w0,%1"
-                                :"=r" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-                case 4:
-                        __asm__ __volatile__("xchgl %k0,%1"
-                                :"=r" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-                case 8:
-                        __asm__ __volatile__("xchgq %0,%1"
-                                :"=r" (x)
-                                :"m" (*__xg(ptr)), "0" (x)
-                                :"memory");
-                        break;
-        }
-        return x;
-}
-
-/*
- * Atomic compare and exchange.  Compare OLD with MEM, if identical,
- * store NEW in MEM.  Return the initial value in MEM.  Success is
- * indicated by comparing RETURN with OLD.
- */
-
-#define __HAVE_ARCH_CMPXCHG 1
-
-static inline unsigned long __cmpxchg(volatile void *ptr, unsigned long old,
-                                      unsigned long new, int size)
-{
-        unsigned long prev;
-        switch (size) {
-        case 1:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgb %b1,%2"
-                                     : "=a"(prev)
-                                     : "q"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 2:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgw %w1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 4:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgl %k1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        case 8:
-                __asm__ __volatile__(LOCK_PREFIX "cmpxchgq %1,%2"
-                                     : "=a"(prev)
-                                     : "r"(new), "m"(*__xg(ptr)), "0"(old)
-                                     : "memory");
-                return prev;
-        }
-        return old;
-}
-
-#define cmpxchg(ptr,o,n)\
-        ((__typeof__(*(ptr)))__cmpxchg((ptr),(unsigned long)(o),\
-                                        (unsigned long)(n),sizeof(*(ptr))))
-
 #ifdef CONFIG_SMP
 #define smp_mb()        mb()
 #define smp_rmb()       rmb()
diff --git a/include/asm-x86_64/termbits.h b/include/asm-x86_64/termbits.h
index 6cfc3bb10c1a..7405756dd41b 100644
--- a/include/asm-x86_64/termbits.h
+++ b/include/asm-x86_64/termbits.h
@@ -160,7 +160,7 @@ struct ktermios {
 #define CMSPAR    010000000000          /* mark or space (stick) parity */
 #define CRTSCTS   020000000000          /* flow control */
 
-#define IBSHIFT   8             /* Shift from CBAUD to CIBAUD */
+#define IBSHIFT   16            /* Shift from CBAUD to CIBAUD */
 
 /* c_lflag bits */
 #define ISIG    0000001
diff --git a/include/asm-x86_64/unistd.h b/include/asm-x86_64/unistd.h
index 26e23e01c54a..595703949df3 100644
--- a/include/asm-x86_64/unistd.h
+++ b/include/asm-x86_64/unistd.h
@@ -619,6 +619,8 @@ __SYSCALL(__NR_sync_file_range, sys_sync_file_range)
 __SYSCALL(__NR_vmsplice, sys_vmsplice)
 #define __NR_move_pages         279
 __SYSCALL(__NR_move_pages, sys_move_pages)
+#define __NR_utimensat          280
+__SYSCALL(__NR_utimensat, sys_utimensat)
 
 #ifndef __NO_STUBS
 #define __ARCH_WANT_OLD_READDIR
diff --git a/include/asm-xtensa/atomic.h b/include/asm-xtensa/atomic.h
index 5c2672021068..b3b23540f14d 100644
--- a/include/asm-xtensa/atomic.h
+++ b/include/asm-xtensa/atomic.h
@@ -234,14 +234,21 @@ static inline int atomic_sub_return(int i, atomic_t * v)
  * Atomically adds @a to @v, so long as it was not @u.
  * Returns non-zero if @v was not @u, and zero otherwise.
  */
-#define atomic_add_unless(v, a, u)                              \
-({                                                              \
-        int c, old;                                             \
-        c = atomic_read(v);                                     \
-        while (c != (u) && (old = atomic_cmpxchg((v), c, c + (a))) != c) \
-                c = old;                                        \
-        c != (u);                                               \
-})
+static __inline__ int atomic_add_unless(atomic_t *v, int a, int u)
+{
+        int c, old;
+        c = atomic_read(v);
+        for (;;) {
+                if (unlikely(c == (u)))
+                        break;
+                old = atomic_cmpxchg((v), c, c + (a));
+                if (likely(old == c))
+                        break;
+                c = old;
+        }
+        return c != (u);
+}
+
 #define atomic_inc_not_zero(v) atomic_add_unless((v), 1, 0)
 
 static inline void atomic_clear_mask(unsigned int mask, atomic_t *v)
diff --git a/include/asm-xtensa/kdebug.h b/include/asm-xtensa/kdebug.h
new file mode 100644
index 000000000000..6ece1b037665
--- /dev/null
+++ b/include/asm-xtensa/kdebug.h
@@ -0,0 +1 @@
+#include <asm-generic/kdebug.h>
diff --git a/include/asm-xtensa/system.h b/include/asm-xtensa/system.h
index 4aaed7fe6cfe..ddc970847ae9 100644
--- a/include/asm-xtensa/system.h
+++ b/include/asm-xtensa/system.h
@@ -183,8 +183,6 @@ static inline unsigned long xchg_u32(volatile int * m, unsigned long val)
   return tmp;
 }
 
-#define tas(ptr) (xchg((ptr),1))
-
 #define xchg(ptr,x) ((__typeof__(*(ptr)))__xchg((unsigned long)(x),(ptr),sizeof(*(ptr))))
 
 /*
diff --git a/include/linux/Kbuild b/include/linux/Kbuild
index 4ff0f57d0add..94cc04a143f2 100644
--- a/include/linux/Kbuild
+++ b/include/linux/Kbuild
@@ -4,6 +4,7 @@ header-y += hdlc/
 header-y += isdn/
 header-y += nfsd/
 header-y += raid/
+header-y += spi/
 header-y += sunrpc/
 header-y += tc_act/
 header-y += netfilter/
@@ -33,7 +34,6 @@ header-y += atmsvc.h
 header-y += atm_zatm.h
 header-y += auto_fs4.h
 header-y += auxvec.h
-header-y += awe_voice.h
 header-y += ax25.h
 header-y += b1lli.h
 header-y += baycom.h
@@ -46,6 +46,7 @@ header-y += coda_psdev.h
 header-y += coff.h
 header-y += comstats.h
 header-y += consolemap.h
+header-y += const.h
 header-y += cycx_cfm.h
 header-y += dlm_device.h
 header-y += dm-ioctl.h
@@ -91,11 +92,11 @@ header-y += ip_mp_alg.h
 header-y += ipsec.h
 header-y += ipx.h
 header-y += irda.h
-header-y += isdn_divertif.h
 header-y += iso_fs.h
 header-y += ixjuser.h
 header-y += jffs2.h
 header-y += keyctl.h
+header-y += kvm.h
 header-y += limits.h
 header-y += lock_dlm_plock.h
 header-y += magic.h
@@ -120,6 +121,7 @@ header-y += pci_regs.h
 header-y += personality.h
 header-y += pfkeyv2.h
 header-y += pg.h
+header-y += phantom.h
 header-y += pkt_cls.h
 header-y += pkt_sched.h
 header-y += posix_types.h
@@ -139,6 +141,7 @@ header-y += sockios.h
 header-y += som.h
 header-y += sound.h
 header-y += synclink.h
+header-y += taskstats.h
 header-y += telephony.h
 header-y += termios.h
 header-y += ticable.h
@@ -238,6 +241,7 @@ unifdef-y += ipv6.h
 unifdef-y += ipv6_route.h
 unifdef-y += isdn.h
 unifdef-y += isdnif.h
+unifdef-y += isdn_divertif.h
 unifdef-y += isdn_ppp.h
 unifdef-y += isicom.h
 unifdef-y += jbd.h
diff --git a/include/linux/awe_voice.h b/include/linux/awe_voice.h
deleted file mode 100644
index bf33f17bea99..000000000000
--- a/include/linux/awe_voice.h
+++ /dev/null
@@ -1,525 +0,0 @@
-/*
- * include/linux/awe_voice.h
- *
- * Voice information definitions for the low level driver for the 
- * AWE32/SB32/AWE64 wave table synth.
- *   version 0.4.4; Jan. 4, 2000
- *
- * Copyright (C) 1996-2000 Takashi Iwai
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
- */
-
-#ifndef AWE_VOICE_H
-#define AWE_VOICE_H
-
-#ifndef SAMPLE_TYPE_AWE32
-#define SAMPLE_TYPE_AWE32       0x20
-#endif
-
-#define _LINUX_PATCHKEY_H_INDIRECT
-#include <linux/patchkey.h>
-#undef _LINUX_PATCHKEY_H_INDIRECT
-
-/*----------------------------------------------------------------
- * patch information record
- *----------------------------------------------------------------*/
-
-/* patch interface header: 16 bytes */
-typedef struct awe_patch_info {
-        short key;                      /* use AWE_PATCH here */
-#define AWE_PATCH       _PATCHKEY(0x07)
-
-        short device_no;                /* synthesizer number */
-        unsigned short sf_id;           /* file id (should be zero) */
-        short optarg;                   /* optional argument */
-        int len;                        /* data length (without this header) */
-
-        short type;                     /* patch operation type */
-#define AWE_LOAD_INFO           0       /* awe_voice_rec */
-#define AWE_LOAD_DATA           1       /* awe_sample_info */
-#define AWE_OPEN_PATCH          2       /* awe_open_parm */
-#define AWE_CLOSE_PATCH         3       /* none */
-#define AWE_UNLOAD_PATCH        4       /* none */
-#define AWE_REPLACE_DATA        5       /* awe_sample_info (optarg=#channels)*/
-#define AWE_MAP_PRESET          6       /* awe_voice_map */
-/*#define AWE_PROBE_INFO        7*/     /* awe_voice_map (pat only) */
-#define AWE_PROBE_DATA          8       /* optarg=sample */
-#define AWE_REMOVE_INFO         9       /* optarg=(bank<<8)|instr */
-#define AWE_LOAD_CHORUS_FX      0x10    /* awe_chorus_fx_rec (optarg=mode) */
-#define AWE_LOAD_REVERB_FX      0x11    /* awe_reverb_fx_rec (optarg=mode) */
-
-        short reserved;                 /* word alignment data */
-
-        /* the actual patch data begins after this */
-#if defined(AWE_COMPAT_030) && AWE_COMPAT_030
-        char data[0];
-#endif
-} awe_patch_info;
-
-/*#define AWE_PATCH_INFO_SIZE   16*/
-#define AWE_PATCH_INFO_SIZE     sizeof(awe_patch_info)
-
-
-/*----------------------------------------------------------------
- * open patch
- *----------------------------------------------------------------*/
-
-#define AWE_PATCH_NAME_LEN      32
-
-typedef struct _awe_open_parm {
-        unsigned short type;            /* sample type */
-#define AWE_PAT_TYPE_MISC       0
-#define AWE_PAT_TYPE_GM         1
-#define AWE_PAT_TYPE_GS         2
-#define AWE_PAT_TYPE_MT32       3
-#define AWE_PAT_TYPE_XG         4
-#define AWE_PAT_TYPE_SFX        5
-#define AWE_PAT_TYPE_GUS        6
-#define AWE_PAT_TYPE_MAP        7
-
-#define AWE_PAT_LOCKED          0x100   /* lock the samples */
-#define AWE_PAT_SHARED          0x200   /* sample is shared */
-
-        short reserved;
-        char name[AWE_PATCH_NAME_LEN];
-} awe_open_parm;
-
-/*#define AWE_OPEN_PARM_SIZE    28*/
-#define AWE_OPEN_PARM_SIZE      sizeof(awe_open_parm)
-
-
-/*----------------------------------------------------------------
- * raw voice information record
- *----------------------------------------------------------------*/
-
-/* wave table envelope & effect parameters to control EMU8000 */
-typedef struct _awe_voice_parm {
-        unsigned short moddelay;        /* modulation delay (0x8000) */
-        unsigned short modatkhld;       /* modulation attack & hold time (0x7f7f) */
-        unsigned short moddcysus;       /* modulation decay & sustain (0x7f7f) */
-        unsigned short modrelease;      /* modulation release time (0x807f) */
-        short modkeyhold, modkeydecay;  /* envelope change per key (not used) */
-        unsigned short voldelay;        /* volume delay (0x8000) */
-        unsigned short volatkhld;       /* volume attack & hold time (0x7f7f) */
-        unsigned short voldcysus;       /* volume decay & sustain (0x7f7f) */
-        unsigned short volrelease;      /* volume release time (0x807f) */
-        short volkeyhold, volkeydecay;  /* envelope change per key (not used) */
-        unsigned short lfo1delay;       /* LFO1 delay (0x8000) */
-        unsigned short lfo2delay;       /* LFO2 delay (0x8000) */
-        unsigned short pefe;            /* modulation pitch & cutoff (0x0000) */
-        unsigned short fmmod;           /* LFO1 pitch & cutoff (0x0000) */
-        unsigned short tremfrq;         /* LFO1 volume & freq (0x0000) */
-        unsigned short fm2frq2;         /* LFO2 pitch & freq (0x0000) */
-        unsigned char cutoff;           /* initial cutoff (0xff) */
-        unsigned char filterQ;          /* initial filter Q [0-15] (0x0) */
-        unsigned char chorus;           /* chorus send (0x00) */
-        unsigned char reverb;           /* reverb send (0x00) */
-        unsigned short reserved[4];     /* not used */
-} awe_voice_parm;
-
-typedef struct _awe_voice_parm_block {
-        unsigned short moddelay;        /* modulation delay (0x8000) */
-        unsigned char modatk, modhld;
-        unsigned char moddcy, modsus;
-        unsigned char modrel, moddummy;
-        short modkeyhold, modkeydecay;  /* envelope change per key (not used) */
-        unsigned short voldelay;        /* volume delay (0x8000) */
-        unsigned char volatk, volhld;
-        unsigned char voldcy, volsus;
-        unsigned char volrel, voldummy;
-        short volkeyhold, volkeydecay;  /* envelope change per key (not used) */
-        unsigned short lfo1delay;       /* LFO1 delay (0x8000) */
-        unsigned short lfo2delay;       /* LFO2 delay (0x8000) */
-        unsigned char env1fc, env1pit;
-        unsigned char lfo1fc, lfo1pit;
-        unsigned char lfo1freq, lfo1vol;
-        unsigned char lfo2freq, lfo2pit;
-        unsigned char cutoff;           /* initial cutoff (0xff) */
-        unsigned char filterQ;          /* initial filter Q [0-15] (0x0) */
-        unsigned char chorus;           /* chorus send (0x00) */
-        unsigned char reverb;           /* reverb send (0x00) */
-        unsigned short reserved[4];     /* not used */
-} awe_voice_parm_block;
-
-#define AWE_VOICE_PARM_SIZE     48
-
-
-/* wave table parameters: 92 bytes */
-typedef struct _awe_voice_info {
-        unsigned short sf_id;           /* file id (should be zero) */
-        unsigned short sample;          /* sample id */
-        int start, end;                 /* sample offset correction */
-        int loopstart, loopend;         /* loop offset correction */
-        short rate_offset;              /* sample rate pitch offset */
-        unsigned short mode;            /* sample mode */
-#define AWE_MODE_ROMSOUND               0x8000
-#define AWE_MODE_STEREO                 1
-#define AWE_MODE_LOOPING                2
-#define AWE_MODE_NORELEASE              4       /* obsolete */
-#define AWE_MODE_INIT_PARM              8
-
-        short root;                     /* midi root key */
-        short tune;                     /* pitch tuning (in cents) */
-        signed char low, high;          /* key note range */
-        signed char vellow, velhigh;    /* velocity range */
-        signed char fixkey, fixvel;     /* fixed key, velocity */
-        signed char pan, fixpan;        /* panning, fixed panning */
-        short exclusiveClass;           /* exclusive class (0 = none) */
-        unsigned char amplitude;        /* sample volume (127 max) */
-        unsigned char attenuation;      /* attenuation (0.375dB) */
-        short scaleTuning;              /* pitch scale tuning(%), normally 100 */
-        awe_voice_parm parm;            /* voice envelope parameters */
-        short index;                    /* internal index (set by driver) */
-} awe_voice_info;
-
-/*#define AWE_VOICE_INFO_SIZE   92*/
-#define AWE_VOICE_INFO_SIZE     sizeof(awe_voice_info)
-
-/*----------------------------------------------------------------*/
-
-/* The info entry of awe_voice_rec is changed from 0 to 1
- * for some compilers refusing zero size array.
- * Due to this change, sizeof(awe_voice_rec) becomes different
- * from older versions.
- * Use AWE_VOICE_REC_SIZE instead.
- */
-
-/* instrument info header: 4 bytes */
-typedef struct _awe_voice_rec_hdr {
-        unsigned char bank;             /* midi bank number */
-        unsigned char instr;            /* midi preset number */
-        char nvoices;                   /* number of voices */
-        char write_mode;                /* write mode; normally 0 */
-#define AWE_WR_APPEND           0       /* append anyway */
-#define AWE_WR_EXCLUSIVE        1       /* skip if already exists */
-#define AWE_WR_REPLACE          2       /* replace if already exists */
-} awe_voice_rec_hdr;
-
-/*#define AWE_VOICE_REC_SIZE    4*/
-#define AWE_VOICE_REC_SIZE      sizeof(awe_voice_rec_hdr)
-
-/* the standard patch structure for one sample */
-typedef struct _awe_voice_rec_patch {
-        awe_patch_info          patch;
-        awe_voice_rec_hdr       hdr;
-        awe_voice_info          info;
-} awe_voice_rec_patch;
-
-
-/* obsolete data type */
-#if defined(AWE_COMPAT_030) && AWE_COMPAT_030
-#define AWE_INFOARRAY_SIZE      0
-#else
-#define AWE_INFOARRAY_SIZE      1
-#endif
-
-typedef struct _awe_voice_rec {
-        unsigned char bank;             /* midi bank number */
-        unsigned char instr;            /* midi preset number */
-        short nvoices;                  /* number of voices */
-        /* voice information follows here */
-        awe_voice_info info[AWE_INFOARRAY_SIZE];
-} awe_voice_rec;
-
-
-/*----------------------------------------------------------------
- * sample wave information
- *----------------------------------------------------------------*/
-
-/* wave table sample header: 32 bytes */
-typedef struct awe_sample_info {
-        unsigned short sf_id;           /* file id (should be zero) */
-        unsigned short sample;          /* sample id */
-        int start, end;                 /* start & end offset */
-        int loopstart, loopend;         /* loop start & end offset */
-        int size;                       /* size (0 = ROM) */
-        short checksum_flag;            /* use check sum = 1 */
-        unsigned short mode_flags;      /* mode flags */
-#define AWE_SAMPLE_8BITS        1       /* wave data is 8bits */
-#define AWE_SAMPLE_UNSIGNED     2       /* wave data is unsigned */
-#define AWE_SAMPLE_NO_BLANK     4       /* no blank loop is attached */
-#define AWE_SAMPLE_SINGLESHOT   8       /* single-shot w/o loop */
-#define AWE_SAMPLE_BIDIR_LOOP   16      /* bidirectional looping */
-#define AWE_SAMPLE_STEREO_LEFT  32      /* stereo left sound */
-#define AWE_SAMPLE_STEREO_RIGHT 64      /* stereo right sound */
-#define AWE_SAMPLE_REVERSE_LOOP 128     /* reverse looping */
-        unsigned int checksum;          /* check sum */
-#if defined(AWE_COMPAT_030) && AWE_COMPAT_030
-        unsigned short data[0];         /* sample data follows here */
-#endif
-} awe_sample_info;
-
-/*#define AWE_SAMPLE_INFO_SIZE  32*/
-#define AWE_SAMPLE_INFO_SIZE    sizeof(awe_sample_info)
-
-
-/*----------------------------------------------------------------
- * voice preset mapping
- *----------------------------------------------------------------*/
-
-typedef struct awe_voice_map {
-        int map_bank, map_instr, map_key;       /* key = -1 means all keys */
-        int src_bank, src_instr, src_key;
-} awe_voice_map;
-
-#define AWE_VOICE_MAP_SIZE      sizeof(awe_voice_map)
-
-
-/*----------------------------------------------------------------
- * awe hardware controls
- *----------------------------------------------------------------*/
-
-#define _AWE_DEBUG_MODE                 0x00
-#define _AWE_REVERB_MODE                0x01
-#define _AWE_CHORUS_MODE                0x02
-#define _AWE_REMOVE_LAST_SAMPLES        0x03
-#define _AWE_INITIALIZE_CHIP            0x04
-#define _AWE_SEND_EFFECT                0x05
-#define _AWE_TERMINATE_CHANNEL          0x06
-#define _AWE_TERMINATE_ALL              0x07
-#define _AWE_INITIAL_VOLUME             0x08
-#define _AWE_INITIAL_ATTEN      _AWE_INITIAL_VOLUME
-#define _AWE_RESET_CHANNEL              0x09
-#define _AWE_CHANNEL_MODE               0x0a
-#define _AWE_DRUM_CHANNELS              0x0b
-#define _AWE_MISC_MODE                  0x0c
-#define _AWE_RELEASE_ALL                0x0d
-#define _AWE_NOTEOFF_ALL                0x0e
-#define _AWE_CHN_PRESSURE               0x0f
-/*#define _AWE_GET_CURRENT_MODE         0x10*/
-#define _AWE_EQUALIZER                  0x11
-/*#define _AWE_GET_MISC_MODE            0x12*/
-/*#define _AWE_GET_FONTINFO             0x13*/
-
-#define _AWE_MODE_FLAG                  0x80
-#define _AWE_COOKED_FLAG                0x40    /* not supported */
-#define _AWE_MODE_VALUE_MASK            0x3F
-
-/*----------------------------------------------------------------*/
-
-#define _AWE_SET_CMD(p,dev,voice,cmd,p1,p2) \
-{((char*)(p))[0] = SEQ_PRIVATE;\
- ((char*)(p))[1] = dev;\
- ((char*)(p))[2] = _AWE_MODE_FLAG|(cmd);\
- ((char*)(p))[3] = voice;\
- ((unsigned short*)(p))[2] = p1;\
- ((unsigned short*)(p))[3] = p2;}
-
-/* buffered access */
-#define _AWE_CMD(dev, voice, cmd, p1, p2) \
-{_SEQ_NEEDBUF(8);\
- _AWE_SET_CMD(_seqbuf + _seqbufptr, dev, voice, cmd, p1, p2);\
- _SEQ_ADVBUF(8);}
-
-/* direct access */
-#define _AWE_CMD_NOW(seqfd,dev,voice,cmd,p1,p2) \
-{struct seq_event_rec tmp;\
- _AWE_SET_CMD(&tmp, dev, voice, cmd, p1, p2);\
- ioctl(seqfd, SNDCTL_SEQ_OUTOFBAND, &tmp);}
-
-/*----------------------------------------------------------------*/
-
-/* set debugging mode */
-#define AWE_DEBUG_MODE(dev,p1)  _AWE_CMD(dev, 0, _AWE_DEBUG_MODE, p1, 0)
-/* set reverb mode; from 0 to 7 */
-#define AWE_REVERB_MODE(dev,p1) _AWE_CMD(dev, 0, _AWE_REVERB_MODE, p1, 0)
-/* set chorus mode; from 0 to 7 */
-#define AWE_CHORUS_MODE(dev,p1) _AWE_CMD(dev, 0, _AWE_CHORUS_MODE, p1, 0)
-
-/* reset channel */
-#define AWE_RESET_CHANNEL(dev,ch) _AWE_CMD(dev, ch, _AWE_RESET_CHANNEL, 0, 0)
-#define AWE_RESET_CONTROL(dev,ch) _AWE_CMD(dev, ch, _AWE_RESET_CHANNEL, 1, 0)
-
-/* send an effect to all layers */
-#define AWE_SEND_EFFECT(dev,voice,type,value) _AWE_CMD(dev,voice,_AWE_SEND_EFFECT,type,value)
-#define AWE_ADD_EFFECT(dev,voice,type,value) _AWE_CMD(dev,voice,_AWE_SEND_EFFECT,((type)|0x80),value)
-#define AWE_UNSET_EFFECT(dev,voice,type) _AWE_CMD(dev,voice,_AWE_SEND_EFFECT,((type)|0x40),0)
-/* send an effect to a layer */
-#define AWE_SEND_LAYER_EFFECT(dev,voice,layer,type,value) _AWE_CMD(dev,voice,_AWE_SEND_EFFECT,((layer+1)<<8|(type)),value)
-#define AWE_ADD_LAYER_EFFECT(dev,voice,layer,type,value) _AWE_CMD(dev,voice,_AWE_SEND_EFFECT,((layer+1)<<8|(type)|0x80),value)
-#define AWE_UNSET_LAYER_EFFECT(dev,voice,layer,type) _AWE_CMD(dev,voice,_AWE_SEND_EFFECT,((layer+1)<<8|(type)|0x40),0)
-
-/* terminate sound on the channel/voice */
-#define AWE_TERMINATE_CHANNEL(dev,voice) _AWE_CMD(dev,voice,_AWE_TERMINATE_CHANNEL,0,0)
-/* terminate all sounds */
-#define AWE_TERMINATE_ALL(dev) _AWE_CMD(dev, 0, _AWE_TERMINATE_ALL, 0, 0)
-/* release all sounds (w/o sustain effect) */
-#define AWE_RELEASE_ALL(dev) _AWE_CMD(dev, 0, _AWE_RELEASE_ALL, 0, 0)
-/* note off all sounds (w sustain effect) */
-#define AWE_NOTEOFF_ALL(dev) _AWE_CMD(dev, 0, _AWE_NOTEOFF_ALL, 0, 0)
-
-/* set initial attenuation */
-#define AWE_INITIAL_VOLUME(dev,atten) _AWE_CMD(dev, 0, _AWE_INITIAL_VOLUME, atten, 0)
-#define AWE_INITIAL_ATTEN  AWE_INITIAL_VOLUME
-/* relative attenuation */
-#define AWE_SET_ATTEN(dev,atten)  _AWE_CMD(dev, 0, _AWE_INITIAL_VOLUME, atten, 1)
-
-/* set channel playing mode; mode=0/1/2 */
-#define AWE_SET_CHANNEL_MODE(dev,mode) _AWE_CMD(dev, 0, _AWE_CHANNEL_MODE, mode, 0)
-#define AWE_PLAY_INDIRECT       0       /* indirect voice mode (default) */
-#define AWE_PLAY_MULTI          1       /* multi note voice mode */
-#define AWE_PLAY_DIRECT         2       /* direct single voice mode */
-#define AWE_PLAY_MULTI2         3       /* sequencer2 mode; used internally */
-
-/* set drum channel mask; channels is 32bit long value */
-#define AWE_DRUM_CHANNELS(dev,channels) _AWE_CMD(dev, 0, _AWE_DRUM_CHANNELS, ((channels) & 0xffff), ((channels) >> 16))
-
-/* set bass and treble control; values are from 0 to 11 */
-#define AWE_EQUALIZER(dev,bass,treble) _AWE_CMD(dev, 0, _AWE_EQUALIZER, bass, treble)
-
-/* remove last loaded samples */
-#define AWE_REMOVE_LAST_SAMPLES(seqfd,dev) _AWE_CMD_NOW(seqfd, dev, 0, _AWE_REMOVE_LAST_SAMPLES, 0, 0)
-/* initialize emu8000 chip */
-#define AWE_INITIALIZE_CHIP(seqfd,dev) _AWE_CMD_NOW(seqfd, dev, 0, _AWE_INITIALIZE_CHIP, 0, 0)
-
-/* set miscellaneous modes; meta command */
-#define AWE_MISC_MODE(dev,mode,value) _AWE_CMD(dev, 0, _AWE_MISC_MODE, mode, value)
-/* exclusive sound off; 1=off */
-#define AWE_EXCLUSIVE_SOUND(dev,mode) AWE_MISC_MODE(dev,AWE_MD_EXCLUSIVE_SOUND,mode)
-/* default GUS bank number */
-#define AWE_SET_GUS_BANK(dev,bank) AWE_MISC_MODE(dev,AWE_MD_GUS_BANK,bank)
-/* change panning position in realtime; 0=don't 1=do */
-#define AWE_REALTIME_PAN(dev,mode) AWE_MISC_MODE(dev,AWE_MD_REALTIME_PAN,mode)
-
-/* extended pressure controls; not portable with other sound drivers */
-#define AWE_KEY_PRESSURE(dev,ch,note,vel) SEQ_START_NOTE(dev,ch,(note)+128,vel)
-#define AWE_CHN_PRESSURE(dev,ch,vel) _AWE_CMD(dev,ch,_AWE_CHN_PRESSURE,vel,0)
-
-/*----------------------------------------------------------------*/
-
-/* reverb mode parameters */
-#define AWE_REVERB_ROOM1        0
-#define AWE_REVERB_ROOM2        1
-#define AWE_REVERB_ROOM3        2
-#define AWE_REVERB_HALL1        3
-#define AWE_REVERB_HALL2        4
-#define AWE_REVERB_PLATE        5
-#define AWE_REVERB_DELAY        6
-#define AWE_REVERB_PANNINGDELAY 7
-#define AWE_REVERB_PREDEFINED   8
-/* user can define reverb modes up to 32 */
-#define AWE_REVERB_NUMBERS      32
-
-typedef struct awe_reverb_fx_rec {
-        unsigned short parms[28];
-} awe_reverb_fx_rec;
-
-/*----------------------------------------------------------------*/
-
-/* chorus mode parameters */
-#define AWE_CHORUS_1            0
-#define AWE_CHORUS_2            1
-#define AWE_CHORUS_3            2
-#define AWE_CHORUS_4            3
-#define AWE_CHORUS_FEEDBACK     4
-#define AWE_CHORUS_FLANGER      5
-#define AWE_CHORUS_SHORTDELAY   6
-#define AWE_CHORUS_SHORTDELAY2  7
-#define AWE_CHORUS_PREDEFINED   8
-/* user can define chorus modes up to 32 */
-#define AWE_CHORUS_NUMBERS      32
-
-typedef struct awe_chorus_fx_rec {
-        unsigned short feedback;        /* feedback level (0xE600-0xE6FF) */
-        unsigned short delay_offset;    /* delay (0-0x0DA3) [1/44100 sec] */
-        unsigned short lfo_depth;       /* LFO depth (0xBC00-0xBCFF) */
-        unsigned int delay;     /* right delay (0-0xFFFFFFFF) [1/256/44100 sec] */
-        unsigned int lfo_freq;          /* LFO freq LFO freq (0-0xFFFFFFFF) */
-} awe_chorus_fx_rec;
-
-/*----------------------------------------------------------------*/
-
-/* misc mode types */
-enum {
-/* 0*/  AWE_MD_EXCLUSIVE_OFF,   /* obsolete */
-/* 1*/  AWE_MD_EXCLUSIVE_ON,    /* obsolete */
-/* 2*/  AWE_MD_VERSION,         /* read only */
-/* 3*/  AWE_MD_EXCLUSIVE_SOUND, /* 0/1: exclusive note on (default=1) */
-/* 4*/  AWE_MD_REALTIME_PAN,    /* 0/1: do realtime pan change (default=1) */
-/* 5*/  AWE_MD_GUS_BANK,        /* bank number for GUS patches (default=0) */
-/* 6*/  AWE_MD_KEEP_EFFECT,     /* 0/1: keep effect values, (default=0) */
-/* 7*/  AWE_MD_ZERO_ATTEN,      /* attenuation of max volume (default=32) */
-/* 8*/  AWE_MD_CHN_PRIOR,       /* 0/1: set MIDI channel priority mode (default=1) */
-/* 9*/  AWE_MD_MOD_SENSE,       /* integer: modwheel sensitivity (def=18) */
-/*10*/  AWE_MD_DEF_PRESET,      /* integer: default preset number (def=0) */
-/*11*/  AWE_MD_DEF_BANK,        /* integer: default bank number (def=0) */
-/*12*/  AWE_MD_DEF_DRUM,        /* integer: default drumset number (def=0) */
-/*13*/  AWE_MD_TOGGLE_DRUM_BANK, /* 0/1: toggle drum flag with bank# (def=0) */
-/*14*/  AWE_MD_NEW_VOLUME_CALC, /* 0/1: volume calculation mode (def=1) */
-/*15*/  AWE_MD_CHORUS_MODE,     /* integer: chorus mode (def=2) */
-/*16*/  AWE_MD_REVERB_MODE,     /* integer: chorus mode (def=4) */
-/*17*/  AWE_MD_BASS_LEVEL,      /* integer: bass level (def=5) */
-/*18*/  AWE_MD_TREBLE_LEVEL,    /* integer: treble level (def=9) */
-/*19*/  AWE_MD_DEBUG_MODE,      /* integer: debug level (def=0) */
-/*20*/  AWE_MD_PAN_EXCHANGE,    /* 0/1: exchange panning direction (def=0) */
-        AWE_MD_END,
-};
-
-/*----------------------------------------------------------------*/
-
-/* effect parameters */
-enum {
-
-/* modulation envelope parameters */
-/* 0*/  AWE_FX_ENV1_DELAY,      /* WORD: ENVVAL */
-/* 1*/  AWE_FX_ENV1_ATTACK,     /* BYTE: up ATKHLD */
-/* 2*/  AWE_FX_ENV1_HOLD,       /* BYTE: lw ATKHLD */
-/* 3*/  AWE_FX_ENV1_DECAY,      /* BYTE: lw DCYSUS */
-/* 4*/  AWE_FX_ENV1_RELEASE,    /* BYTE: lw DCYSUS */
-/* 5*/  AWE_FX_ENV1_SUSTAIN,    /* BYTE: up DCYSUS */
-/* 6*/  AWE_FX_ENV1_PITCH,      /* BYTE: up PEFE */
-/* 7*/  AWE_FX_ENV1_CUTOFF,     /* BYTE: lw PEFE */
-
-/* volume envelope parameters */
-/* 8*/  AWE_FX_ENV2_DELAY,      /* WORD: ENVVOL */
-/* 9*/  AWE_FX_ENV2_ATTACK,     /* BYTE: up ATKHLDV */
-/*10*/  AWE_FX_ENV2_HOLD,       /* BYTE: lw ATKHLDV */
-/*11*/  AWE_FX_ENV2_DECAY,      /* BYTE: lw DCYSUSV */
-/*12*/  AWE_FX_ENV2_RELEASE,    /* BYTE: lw DCYSUSV */
-/*13*/  AWE_FX_ENV2_SUSTAIN,    /* BYTE: up DCYSUSV */
-        
-/* LFO1 (tremolo & vibrato) parameters */
-/*14*/  AWE_FX_LFO1_DELAY,      /* WORD: LFO1VAL */
-/*15*/  AWE_FX_LFO1_FREQ,       /* BYTE: lo TREMFRQ */
-/*16*/  AWE_FX_LFO1_VOLUME,     /* BYTE: up TREMFRQ */
-/*17*/  AWE_FX_LFO1_PITCH,      /* BYTE: up FMMOD */
-/*18*/  AWE_FX_LFO1_CUTOFF,     /* BYTE: lo FMMOD */
-
-/* LFO2 (vibrato) parameters */
-/*19*/  AWE_FX_LFO2_DELAY,      /* WORD: LFO2VAL */
-/*20*/  AWE_FX_LFO2_FREQ,       /* BYTE: lo FM2FRQ2 */
-/*21*/  AWE_FX_LFO2_PITCH,      /* BYTE: up FM2FRQ2 */
-
-/* Other overall effect parameters */
-/*22*/  AWE_FX_INIT_PITCH,      /* SHORT: pitch offset */
-/*23*/  AWE_FX_CHORUS,          /* BYTE: chorus effects send (0-255) */
-/*24*/  AWE_FX_REVERB,          /* BYTE: reverb effects send (0-255) */
-/*25*/  AWE_FX_CUTOFF,          /* BYTE: up IFATN */
-/*26*/  AWE_FX_FILTERQ,         /* BYTE: up CCCA */
-
-/* Sample / loop offset changes */
-/*27*/  AWE_FX_SAMPLE_START,    /* SHORT: offset */
-/*28*/  AWE_FX_LOOP_START,      /* SHORT: offset */
-/*29*/  AWE_FX_LOOP_END,        /* SHORT: offset */
-/*30*/  AWE_FX_COARSE_SAMPLE_START,     /* SHORT: upper word offset */
-/*31*/  AWE_FX_COARSE_LOOP_START,       /* SHORT: upper word offset */
-/*32*/  AWE_FX_COARSE_LOOP_END,         /* SHORT: upper word offset */
-/*33*/  AWE_FX_ATTEN,           /* BYTE: lo IFATN */
-
-        AWE_FX_END,
-};
-
-#endif /* AWE_VOICE_H */
diff --git a/include/linux/buffer_head.h b/include/linux/buffer_head.h
index dd27b1c7227f..5c6e12853a9b 100644
--- a/include/linux/buffer_head.h
+++ b/include/linux/buffer_head.h
@@ -165,7 +165,7 @@ int sync_mapping_buffers(struct address_space *mapping);
 void unmap_underlying_metadata(struct block_device *bdev, sector_t block);
 
 void mark_buffer_async_write(struct buffer_head *bh);
-void invalidate_bdev(struct block_device *, int);
+void invalidate_bdev(struct block_device *);
 int sync_blockdev(struct block_device *bdev);
 void __wait_on_buffer(struct buffer_head *);
 wait_queue_head_t *bh_waitq_head(struct buffer_head *bh);
@@ -182,6 +182,7 @@ void __brelse(struct buffer_head *);
 void __bforget(struct buffer_head *);
 void __breadahead(struct block_device *, sector_t block, unsigned int size);
 struct buffer_head *__bread(struct block_device *, sector_t block, unsigned size);
+void invalidate_bh_lrus(void);
 struct buffer_head *alloc_buffer_head(gfp_t gfp_flags);
 void free_buffer_head(struct buffer_head * bh);
 void FASTCALL(unlock_buffer(struct buffer_head *bh));
@@ -319,7 +320,7 @@ static inline int inode_has_buffers(struct inode *inode) { return 0; }
 static inline void invalidate_inode_buffers(struct inode *inode) {}
 static inline int remove_inode_buffers(struct inode *inode) { return 1; }
 static inline int sync_mapping_buffers(struct address_space *mapping) { return 0; }
-static inline void invalidate_bdev(struct block_device *bdev, int destroy_dirty_buffers) {}
+static inline void invalidate_bdev(struct block_device *bdev) {}
 
 
 #endif /* CONFIG_BLOCK */
diff --git a/include/linux/byteorder/generic.h b/include/linux/byteorder/generic.h
index e86e4a938373..3dc715b02500 100644
--- a/include/linux/byteorder/generic.h
+++ b/include/linux/byteorder/generic.h
@@ -124,19 +124,8 @@
 #define be32_to_cpus __be32_to_cpus
 #define cpu_to_be16s __cpu_to_be16s
 #define be16_to_cpus __be16_to_cpus
-#endif
 
-
-#if defined(__KERNEL__)
 /*
- * Handle ntohl and suches. These have various compatibility
- * issues - like we want to give the prototype even though we
- * also have a macro for them in case some strange program
- * wants to take the address of the thing or something..
- *
- * Note that these used to return a "long" in libc5, even though
- * long is often 64-bit these days.. Thus the casts.
- *
  * They have to be macros in order to do the constant folding
  * correctly - if the argument passed into a inline function
  * it is no longer constant according to gcc..
@@ -147,17 +136,6 @@
 #undef htonl
 #undef htons
 
-/*
- * Do the prototypes. Somebody might want to take the
- * address or some such sick thing..
- */
-extern __u32                    ntohl(__be32);
-extern __be32                   htonl(__u32);
-extern __u16                    ntohs(__be16);
-extern __be16                   htons(__u16);
-
-#if defined(__GNUC__) && defined(__OPTIMIZE__)
-
 #define ___htonl(x) __cpu_to_be32(x)
 #define ___htons(x) __cpu_to_be16(x)
 #define ___ntohl(x) __be32_to_cpu(x)
@@ -168,9 +146,6 @@ extern __be16			htons(__u16);
 #define htons(x) ___htons(x)
 #define ntohs(x) ___ntohs(x)
 
-#endif /* OPTIMIZE */
-
 #endif /* KERNEL */
 
-
 #endif /* _LINUX_BYTEORDER_GENERIC_H */
diff --git a/include/linux/byteorder/swab.h b/include/linux/byteorder/swab.h
index 25f7f32883ec..142134ff1645 100644
--- a/include/linux/byteorder/swab.h
+++ b/include/linux/byteorder/swab.h
@@ -10,6 +10,10 @@
  *    separated swab functions from cpu_to_XX,
  *    to clean up support for bizarre-endian architectures.
  *
+ * Trent Piepho <xyzzy@speakeasy.org> 2007114
+ *    make constant-folding work, provide C versions that
+ *    gcc can optimize better, explain different versions
+ *
  * See asm-i386/byteorder.h and suches for examples of how to provide
  * architecture-dependent optimized versions
  *
@@ -17,40 +21,66 @@
 
 #include <linux/compiler.h>
 
+/* Functions/macros defined, there are a lot:
+ *
+ * ___swabXX
+ *    Generic C versions of the swab functions.
+ *
+ * ___constant_swabXX
+ *    C versions that gcc can fold into a compile-time constant when
+ *    the argument is a compile-time constant.
+ *
+ * __arch__swabXX[sp]?
+ *    Architecture optimized versions of all the swab functions
+ *    (including the s and p versions).  These can be defined in
+ *    asm-arch/byteorder.h.  Any which are not, are defined here.
+ *    __arch__swabXXs() is defined in terms of __arch__swabXXp(), which
+ *    is defined in terms of __arch__swabXX(), which is in turn defined
+ *    in terms of ___swabXX(x).
+ *    These must be macros.  They may be unsafe for arguments with
+ *    side-effects.
+ *
+ * __fswabXX
+ *    Inline function versions of the __arch__ macros.  These _are_ safe
+ *    if the arguments have side-effects.  Note there are no s and p
+ *    versions of these.
+ *
+ * __swabXX[sb]
+ *    There are the ones you should actually use.  The __swabXX versions
+ *    will be a constant given a constant argument and use the arch
+ *    specific code (if any) for non-constant arguments.  The s and p
+ *    versions always use the arch specific code (constant folding
+ *    doesn't apply).  They are safe to use with arguments with
+ *    side-effects.
+ *
+ * swabXX[sb]
+ *    Nicknames for __swabXX[sb] to use in the kernel.
+ */
+
 /* casts are necessary for constants, because we never know how for sure
  * how U/UL/ULL map to __u16, __u32, __u64. At least not in a portable way.
  */
-#define ___swab16(x) \
-({ \
-        __u16 __x = (x); \
-        ((__u16)( \
-                (((__u16)(__x) & (__u16)0x00ffU) << 8) | \
-                (((__u16)(__x) & (__u16)0xff00U) >> 8) )); \
-})
 
-#define ___swab32(x) \
-({ \
-        __u32 __x = (x); \
-        ((__u32)( \
-                (((__u32)(__x) & (__u32)0x000000ffUL) << 24) | \
-                (((__u32)(__x) & (__u32)0x0000ff00UL) <<  8) | \
-                (((__u32)(__x) & (__u32)0x00ff0000UL) >>  8) | \
-                (((__u32)(__x) & (__u32)0xff000000UL) >> 24) )); \
-})
-
-#define ___swab64(x) \
-({ \
-        __u64 __x = (x); \
-        ((__u64)( \
-                (__u64)(((__u64)(__x) & (__u64)0x00000000000000ffULL) << 56) | \
-                (__u64)(((__u64)(__x) & (__u64)0x000000000000ff00ULL) << 40) | \
-                (__u64)(((__u64)(__x) & (__u64)0x0000000000ff0000ULL) << 24) | \
-                (__u64)(((__u64)(__x) & (__u64)0x00000000ff000000ULL) <<  8) | \
-                (__u64)(((__u64)(__x) & (__u64)0x000000ff00000000ULL) >>  8) | \
-                (__u64)(((__u64)(__x) & (__u64)0x0000ff0000000000ULL) >> 24) | \
-                (__u64)(((__u64)(__x) & (__u64)0x00ff000000000000ULL) >> 40) | \
-                (__u64)(((__u64)(__x) & (__u64)0xff00000000000000ULL) >> 56) )); \
-})
+static __inline__ __attribute_const__ __u16 ___swab16(__u16 x)
+{
+        return x<<8 | x>>8;
+}
+static __inline__ __attribute_const__ __u32 ___swab32(__u32 x)
+{
+        return x<<24 | x>>24 |
+                (x & (__u32)0x0000ff00UL)<<8 |
+                (x & (__u32)0x00ff0000UL)>>8;
+}
+static __inline__ __attribute_const__ __u64 ___swab64(__u64 x)
+{
+        return x<<56 | x>>56 |
+                (x & (__u64)0x000000000000ff00ULL)<<40 |
+                (x & (__u64)0x0000000000ff0000ULL)<<24 |
+                (x & (__u64)0x00000000ff000000ULL)<< 8 |
+                (x & (__u64)0x000000ff00000000ULL)>> 8 |
+                (x & (__u64)0x0000ff0000000000ULL)>>24 |
+                (x & (__u64)0x00ff000000000000ULL)>>40;
+}
 
 #define ___constant_swab16(x) \
         ((__u16)( \
@@ -77,13 +107,13 @@
  * provide defaults when no architecture-specific optimization is detected
  */
 #ifndef __arch__swab16
-#  define __arch__swab16(x) ({ __u16 __tmp = (x) ; ___swab16(__tmp); })
+#  define __arch__swab16(x) ___swab16(x)
 #endif
 #ifndef __arch__swab32
-#  define __arch__swab32(x) ({ __u32 __tmp = (x) ; ___swab32(__tmp); })
+#  define __arch__swab32(x) ___swab32(x)
 #endif
 #ifndef __arch__swab64
-#  define __arch__swab64(x) ({ __u64 __tmp = (x) ; ___swab64(__tmp); })
+#  define __arch__swab64(x) ___swab64(x)
 #endif
 
 #ifndef __arch__swab16p
@@ -97,13 +127,13 @@
 #endif
 
 #ifndef __arch__swab16s
-#  define __arch__swab16s(x) do { *(x) = __arch__swab16p((x)); } while (0)
+#  define __arch__swab16s(x) ((void)(*(x) = __arch__swab16p(x)))
 #endif
 #ifndef __arch__swab32s
-#  define __arch__swab32s(x) do { *(x) = __arch__swab32p((x)); } while (0)
+#  define __arch__swab32s(x) ((void)(*(x) = __arch__swab32p(x)))
 #endif
 #ifndef __arch__swab64s
-#  define __arch__swab64s(x) do { *(x) = __arch__swab64p((x)); } while (0)
+#  define __arch__swab64s(x) ((void)(*(x) = __arch__swab64p(x)))
 #endif
 
 
@@ -113,15 +143,15 @@
 #if defined(__GNUC__) && defined(__OPTIMIZE__)
 #  define __swab16(x) \
 (__builtin_constant_p((__u16)(x)) ? \
- ___swab16((x)) : \
+ ___constant_swab16((x)) : \
  __fswab16((x)))
 #  define __swab32(x) \
 (__builtin_constant_p((__u32)(x)) ? \
- ___swab32((x)) : \
+ ___constant_swab32((x)) : \
  __fswab32((x)))
 #  define __swab64(x) \
 (__builtin_constant_p((__u64)(x)) ? \
- ___swab64((x)) : \
+ ___constant_swab64((x)) : \
  __fswab64((x)))
 #else
 #  define __swab16(x) __fswab16(x)
diff --git a/include/linux/clockchips.h b/include/linux/clockchips.h
index 4ea7e7bcfafe..8486e78f7335 100644
--- a/include/linux/clockchips.h
+++ b/include/linux/clockchips.h
@@ -54,17 +54,17 @@ enum clock_event_nofitiers {
 /**
  * struct clock_event_device - clock event device descriptor
  * @name:               ptr to clock event name
- * @hints:              usage hints
+ * @features:           features
  * @max_delta_ns:       maximum delta value in ns
  * @min_delta_ns:       minimum delta value in ns
  * @mult:               nanosecond to cycles multiplier
  * @shift:              nanoseconds to cycles divisor (power of two)
  * @rating:             variable to rate clock event devices
- * @irq:                irq number (only for non cpu local devices)
- * @cpumask:            cpumask to indicate for which cpus this device works
- * @set_next_event:     set next event
+ * @irq:                IRQ number (only for non CPU local devices)
+ * @cpumask:            cpumask to indicate for which CPUs this device works
+ * @set_next_event:     set next event function
  * @set_mode:           set mode function
- * @evthandler:         Assigned by the framework to be called by the low
+ * @event_handler:      Assigned by the framework to be called by the low
  *                      level handler of the event source
  * @broadcast:          function to broadcast events
  * @list:               list head for the management code
diff --git a/include/linux/clocksource.h b/include/linux/clocksource.h
index daa4940cc0f1..2665ca04cf8f 100644
--- a/include/linux/clocksource.h
+++ b/include/linux/clocksource.h
@@ -12,6 +12,7 @@
 #include <linux/timex.h>
 #include <linux/time.h>
 #include <linux/list.h>
+#include <linux/cache.h>
 #include <linux/timer.h>
 #include <asm/div64.h>
 #include <asm/io.h>
@@ -52,6 +53,9 @@ struct clocksource;
  * @xtime_interval:     Used internally by timekeeping core, please ignore.
  */
 struct clocksource {
+        /*
+         * First part of structure is read mostly
+         */
         char *name;
         struct list_head list;
         int rating;
@@ -63,8 +67,15 @@ struct clocksource {
         cycle_t (*vread)(void);
 
         /* timekeeping specific data, ignore */
-        cycle_t cycle_last, cycle_interval;
-        u64 xtime_nsec, xtime_interval;
+        cycle_t cycle_interval;
+        u64     xtime_interval;
+        /*
+         * Second part is written at each timer interrupt
+         * Keep it in a different cache line to dirty no
+         * more than one cache line.
+         */
+        cycle_t cycle_last ____cacheline_aligned_in_smp;
+        u64 xtime_nsec;
         s64 error;
 
 #ifdef CONFIG_CLOCKSOURCE_WATCHDOG
diff --git a/include/linux/compat_ioctl.h b/include/linux/compat_ioctl.h
deleted file mode 100644
index c26c3adcfacf..000000000000
--- a/include/linux/compat_ioctl.h
+++ /dev/null
@@ -1,830 +0,0 @@
-/* List here explicitly which ioctl's are known to have
- * compatible types passed or none at all... Please include
- * only stuff that is compatible on *all architectures*.
- */
-
-COMPATIBLE_IOCTL(0x4B50)   /* KDGHWCLK - not in the kernel, but don't complain */
-COMPATIBLE_IOCTL(0x4B51)   /* KDSHWCLK - not in the kernel, but don't complain */
-
-/* Big T */
-COMPATIBLE_IOCTL(TCGETA)
-COMPATIBLE_IOCTL(TCSETA)
-COMPATIBLE_IOCTL(TCSETAW)
-COMPATIBLE_IOCTL(TCSETAF)
-COMPATIBLE_IOCTL(TCSBRK)
-ULONG_IOCTL(TCSBRKP)
-COMPATIBLE_IOCTL(TCXONC)
-COMPATIBLE_IOCTL(TCFLSH)
-COMPATIBLE_IOCTL(TCGETS)
-COMPATIBLE_IOCTL(TCSETS)
-COMPATIBLE_IOCTL(TCSETSW)
-COMPATIBLE_IOCTL(TCSETSF)
-COMPATIBLE_IOCTL(TIOCLINUX)
-COMPATIBLE_IOCTL(TIOCSBRK)
-COMPATIBLE_IOCTL(TIOCCBRK)
-ULONG_IOCTL(TIOCMIWAIT)
-COMPATIBLE_IOCTL(TIOCGICOUNT)
-/* Little t */
-COMPATIBLE_IOCTL(TIOCGETD)
-COMPATIBLE_IOCTL(TIOCSETD)
-COMPATIBLE_IOCTL(TIOCEXCL)
-COMPATIBLE_IOCTL(TIOCNXCL)
-COMPATIBLE_IOCTL(TIOCCONS)
-COMPATIBLE_IOCTL(TIOCGSOFTCAR)
-COMPATIBLE_IOCTL(TIOCSSOFTCAR)
-COMPATIBLE_IOCTL(TIOCSWINSZ)
-COMPATIBLE_IOCTL(TIOCGWINSZ)
-COMPATIBLE_IOCTL(TIOCMGET)
-COMPATIBLE_IOCTL(TIOCMBIC)
-COMPATIBLE_IOCTL(TIOCMBIS)
-COMPATIBLE_IOCTL(TIOCMSET)
-COMPATIBLE_IOCTL(TIOCPKT)
-COMPATIBLE_IOCTL(TIOCNOTTY)
-COMPATIBLE_IOCTL(TIOCSTI)
-COMPATIBLE_IOCTL(TIOCOUTQ)
-COMPATIBLE_IOCTL(TIOCSPGRP)
-COMPATIBLE_IOCTL(TIOCGPGRP)
-ULONG_IOCTL(TIOCSCTTY)
-COMPATIBLE_IOCTL(TIOCGPTN)
-COMPATIBLE_IOCTL(TIOCSPTLCK)
-COMPATIBLE_IOCTL(TIOCSERGETLSR)
-/* Little f */
-COMPATIBLE_IOCTL(FIOCLEX)
-COMPATIBLE_IOCTL(FIONCLEX)
-COMPATIBLE_IOCTL(FIOASYNC)
-COMPATIBLE_IOCTL(FIONBIO)
-COMPATIBLE_IOCTL(FIONREAD)  /* This is also TIOCINQ */
-/* 0x00 */
-COMPATIBLE_IOCTL(FIBMAP)
-COMPATIBLE_IOCTL(FIGETBSZ)
-/* 0x03 -- HD/IDE ioctl's used by hdparm and friends.
- *         Some need translations, these do not.
- */
-COMPATIBLE_IOCTL(HDIO_GET_IDENTITY)
-COMPATIBLE_IOCTL(HDIO_DRIVE_TASK)
-COMPATIBLE_IOCTL(HDIO_DRIVE_CMD)
-ULONG_IOCTL(HDIO_SET_MULTCOUNT)
-ULONG_IOCTL(HDIO_SET_UNMASKINTR)
-ULONG_IOCTL(HDIO_SET_KEEPSETTINGS)
-ULONG_IOCTL(HDIO_SET_32BIT)
-ULONG_IOCTL(HDIO_SET_NOWERR)
-ULONG_IOCTL(HDIO_SET_DMA)
-ULONG_IOCTL(HDIO_SET_PIO_MODE)
-ULONG_IOCTL(HDIO_SET_NICE)
-ULONG_IOCTL(HDIO_SET_WCACHE)
-ULONG_IOCTL(HDIO_SET_ACOUSTIC)
-ULONG_IOCTL(HDIO_SET_BUSSTATE)
-ULONG_IOCTL(HDIO_SET_ADDRESS)
-COMPATIBLE_IOCTL(HDIO_SCAN_HWIF)
-/* 0x330 is reserved -- it used to be HDIO_GETGEO_BIG */
-COMPATIBLE_IOCTL(0x330)
-/* 0x02 -- Floppy ioctls */
-COMPATIBLE_IOCTL(FDMSGON)
-COMPATIBLE_IOCTL(FDMSGOFF)
-COMPATIBLE_IOCTL(FDSETEMSGTRESH)
-COMPATIBLE_IOCTL(FDFLUSH)
-COMPATIBLE_IOCTL(FDWERRORCLR)
-COMPATIBLE_IOCTL(FDSETMAXERRS)
-COMPATIBLE_IOCTL(FDGETMAXERRS)
-COMPATIBLE_IOCTL(FDGETDRVTYP)
-COMPATIBLE_IOCTL(FDEJECT)
-COMPATIBLE_IOCTL(FDCLRPRM)
-COMPATIBLE_IOCTL(FDFMTBEG)
-COMPATIBLE_IOCTL(FDFMTEND)
-COMPATIBLE_IOCTL(FDRESET)
-COMPATIBLE_IOCTL(FDTWADDLE)
-COMPATIBLE_IOCTL(FDFMTTRK)
-COMPATIBLE_IOCTL(FDRAWCMD)
-/* 0x12 */
-#ifdef CONFIG_BLOCK
-COMPATIBLE_IOCTL(BLKRASET)
-COMPATIBLE_IOCTL(BLKROSET)
-COMPATIBLE_IOCTL(BLKROGET)
-COMPATIBLE_IOCTL(BLKRRPART)
-COMPATIBLE_IOCTL(BLKFLSBUF)
-COMPATIBLE_IOCTL(BLKSECTSET)
-COMPATIBLE_IOCTL(BLKSSZGET)
-COMPATIBLE_IOCTL(BLKTRACESTART)
-COMPATIBLE_IOCTL(BLKTRACESTOP)
-COMPATIBLE_IOCTL(BLKTRACESETUP)
-COMPATIBLE_IOCTL(BLKTRACETEARDOWN)
-ULONG_IOCTL(BLKRASET)
-ULONG_IOCTL(BLKFRASET)
-#endif
-/* RAID */
-COMPATIBLE_IOCTL(RAID_VERSION)
-COMPATIBLE_IOCTL(GET_ARRAY_INFO)
-COMPATIBLE_IOCTL(GET_DISK_INFO)
-COMPATIBLE_IOCTL(PRINT_RAID_DEBUG)
-COMPATIBLE_IOCTL(RAID_AUTORUN)
-COMPATIBLE_IOCTL(CLEAR_ARRAY)
-COMPATIBLE_IOCTL(ADD_NEW_DISK)
-ULONG_IOCTL(HOT_REMOVE_DISK)
-COMPATIBLE_IOCTL(SET_ARRAY_INFO)
-COMPATIBLE_IOCTL(SET_DISK_INFO)
-COMPATIBLE_IOCTL(WRITE_RAID_INFO)
-COMPATIBLE_IOCTL(UNPROTECT_ARRAY)
-COMPATIBLE_IOCTL(PROTECT_ARRAY)
-ULONG_IOCTL(HOT_ADD_DISK)
-ULONG_IOCTL(SET_DISK_FAULTY)
-COMPATIBLE_IOCTL(RUN_ARRAY)
-COMPATIBLE_IOCTL(STOP_ARRAY)
-COMPATIBLE_IOCTL(STOP_ARRAY_RO)
-COMPATIBLE_IOCTL(RESTART_ARRAY_RW)
-COMPATIBLE_IOCTL(GET_BITMAP_FILE)
-ULONG_IOCTL(SET_BITMAP_FILE)
-/* DM */
-COMPATIBLE_IOCTL(DM_VERSION_32)
-COMPATIBLE_IOCTL(DM_REMOVE_ALL_32)
-COMPATIBLE_IOCTL(DM_LIST_DEVICES_32)
-COMPATIBLE_IOCTL(DM_DEV_CREATE_32)
-COMPATIBLE_IOCTL(DM_DEV_REMOVE_32)
-COMPATIBLE_IOCTL(DM_DEV_RENAME_32)
-COMPATIBLE_IOCTL(DM_DEV_SUSPEND_32)
-COMPATIBLE_IOCTL(DM_DEV_STATUS_32)
-COMPATIBLE_IOCTL(DM_DEV_WAIT_32)
-COMPATIBLE_IOCTL(DM_TABLE_LOAD_32)
-COMPATIBLE_IOCTL(DM_TABLE_CLEAR_32)
-COMPATIBLE_IOCTL(DM_TABLE_DEPS_32)
-COMPATIBLE_IOCTL(DM_TABLE_STATUS_32)
-COMPATIBLE_IOCTL(DM_LIST_VERSIONS_32)
-COMPATIBLE_IOCTL(DM_TARGET_MSG_32)
-COMPATIBLE_IOCTL(DM_DEV_SET_GEOMETRY_32)
-COMPATIBLE_IOCTL(DM_VERSION)
-COMPATIBLE_IOCTL(DM_REMOVE_ALL)
-COMPATIBLE_IOCTL(DM_LIST_DEVICES)
-COMPATIBLE_IOCTL(DM_DEV_CREATE)
-COMPATIBLE_IOCTL(DM_DEV_REMOVE)
-COMPATIBLE_IOCTL(DM_DEV_RENAME)
-COMPATIBLE_IOCTL(DM_DEV_SUSPEND)
-COMPATIBLE_IOCTL(DM_DEV_STATUS)
-COMPATIBLE_IOCTL(DM_DEV_WAIT)
-COMPATIBLE_IOCTL(DM_TABLE_LOAD)
-COMPATIBLE_IOCTL(DM_TABLE_CLEAR)
-COMPATIBLE_IOCTL(DM_TABLE_DEPS)
-COMPATIBLE_IOCTL(DM_TABLE_STATUS)
-COMPATIBLE_IOCTL(DM_LIST_VERSIONS)
-COMPATIBLE_IOCTL(DM_TARGET_MSG)
-COMPATIBLE_IOCTL(DM_DEV_SET_GEOMETRY)
-/* Big K */
-COMPATIBLE_IOCTL(PIO_FONT)
-COMPATIBLE_IOCTL(GIO_FONT)
-ULONG_IOCTL(KDSIGACCEPT)
-COMPATIBLE_IOCTL(KDGETKEYCODE)
-COMPATIBLE_IOCTL(KDSETKEYCODE)
-ULONG_IOCTL(KIOCSOUND)
-ULONG_IOCTL(KDMKTONE)
-COMPATIBLE_IOCTL(KDGKBTYPE)
-ULONG_IOCTL(KDSETMODE)
-COMPATIBLE_IOCTL(KDGETMODE)
-ULONG_IOCTL(KDSKBMODE)
-COMPATIBLE_IOCTL(KDGKBMODE)
-ULONG_IOCTL(KDSKBMETA)
-COMPATIBLE_IOCTL(KDGKBMETA)
-COMPATIBLE_IOCTL(KDGKBENT)
-COMPATIBLE_IOCTL(KDSKBENT)
-COMPATIBLE_IOCTL(KDGKBSENT)
-COMPATIBLE_IOCTL(KDSKBSENT)
-COMPATIBLE_IOCTL(KDGKBDIACR)
-COMPATIBLE_IOCTL(KDSKBDIACR)
-COMPATIBLE_IOCTL(KDKBDREP)
-COMPATIBLE_IOCTL(KDGKBLED)
-ULONG_IOCTL(KDSKBLED)
-COMPATIBLE_IOCTL(KDGETLED)
-ULONG_IOCTL(KDSETLED)
-COMPATIBLE_IOCTL(GIO_SCRNMAP)
-COMPATIBLE_IOCTL(PIO_SCRNMAP)
-COMPATIBLE_IOCTL(GIO_UNISCRNMAP)
-COMPATIBLE_IOCTL(PIO_UNISCRNMAP)
-COMPATIBLE_IOCTL(PIO_FONTRESET)
-COMPATIBLE_IOCTL(PIO_UNIMAPCLR)
-/* Big S */
-COMPATIBLE_IOCTL(SCSI_IOCTL_GET_IDLUN)
-COMPATIBLE_IOCTL(SCSI_IOCTL_DOORLOCK)
-COMPATIBLE_IOCTL(SCSI_IOCTL_DOORUNLOCK)
-COMPATIBLE_IOCTL(SCSI_IOCTL_TEST_UNIT_READY)
-COMPATIBLE_IOCTL(SCSI_IOCTL_GET_BUS_NUMBER)
-COMPATIBLE_IOCTL(SCSI_IOCTL_SEND_COMMAND)
-COMPATIBLE_IOCTL(SCSI_IOCTL_PROBE_HOST)
-COMPATIBLE_IOCTL(SCSI_IOCTL_GET_PCI)
-/* Big T */
-COMPATIBLE_IOCTL(TUNSETNOCSUM)
-COMPATIBLE_IOCTL(TUNSETDEBUG)
-COMPATIBLE_IOCTL(TUNSETPERSIST)
-COMPATIBLE_IOCTL(TUNSETOWNER)
-/* Big V */
-COMPATIBLE_IOCTL(VT_SETMODE)
-COMPATIBLE_IOCTL(VT_GETMODE)
-COMPATIBLE_IOCTL(VT_GETSTATE)
-COMPATIBLE_IOCTL(VT_OPENQRY)
-ULONG_IOCTL(VT_ACTIVATE)
-ULONG_IOCTL(VT_WAITACTIVE)
-ULONG_IOCTL(VT_RELDISP)
-ULONG_IOCTL(VT_DISALLOCATE)
-COMPATIBLE_IOCTL(VT_RESIZE)
-COMPATIBLE_IOCTL(VT_RESIZEX)
-COMPATIBLE_IOCTL(VT_LOCKSWITCH)
-COMPATIBLE_IOCTL(VT_UNLOCKSWITCH)
-COMPATIBLE_IOCTL(VT_GETHIFONTMASK)
-/* Little p (/dev/rtc, /dev/envctrl, etc.) */
-COMPATIBLE_IOCTL(RTC_AIE_ON)
-COMPATIBLE_IOCTL(RTC_AIE_OFF)
-COMPATIBLE_IOCTL(RTC_UIE_ON)
-COMPATIBLE_IOCTL(RTC_UIE_OFF)
-COMPATIBLE_IOCTL(RTC_PIE_ON)
-COMPATIBLE_IOCTL(RTC_PIE_OFF)
-COMPATIBLE_IOCTL(RTC_WIE_ON)
-COMPATIBLE_IOCTL(RTC_WIE_OFF)
-COMPATIBLE_IOCTL(RTC_ALM_SET)
-COMPATIBLE_IOCTL(RTC_ALM_READ)
-COMPATIBLE_IOCTL(RTC_RD_TIME)
-COMPATIBLE_IOCTL(RTC_SET_TIME)
-COMPATIBLE_IOCTL(RTC_WKALM_SET)
-COMPATIBLE_IOCTL(RTC_WKALM_RD)
-/*
- * These two are only for the sbus rtc driver, but
- * hwclock tries them on every rtc device first when
- * running on sparc.  On other architectures the entries
- * are useless but harmless.
- */
-COMPATIBLE_IOCTL(_IOR('p', 20, int[7])) /* RTCGET */
-COMPATIBLE_IOCTL(_IOW('p', 21, int[7])) /* RTCSET */
-/* Little m */
-COMPATIBLE_IOCTL(MTIOCTOP)
-/* Socket level stuff */
-COMPATIBLE_IOCTL(FIOQSIZE)
-COMPATIBLE_IOCTL(FIOSETOWN)
-COMPATIBLE_IOCTL(SIOCSPGRP)
-COMPATIBLE_IOCTL(FIOGETOWN)
-COMPATIBLE_IOCTL(SIOCGPGRP)
-COMPATIBLE_IOCTL(SIOCATMARK)
-COMPATIBLE_IOCTL(SIOCSIFLINK)
-COMPATIBLE_IOCTL(SIOCSIFENCAP)
-COMPATIBLE_IOCTL(SIOCGIFENCAP)
-COMPATIBLE_IOCTL(SIOCSIFNAME)
-COMPATIBLE_IOCTL(SIOCSARP)
-COMPATIBLE_IOCTL(SIOCGARP)
-COMPATIBLE_IOCTL(SIOCDARP)
-COMPATIBLE_IOCTL(SIOCSRARP)
-COMPATIBLE_IOCTL(SIOCGRARP)
-COMPATIBLE_IOCTL(SIOCDRARP)
-COMPATIBLE_IOCTL(SIOCADDDLCI)
-COMPATIBLE_IOCTL(SIOCDELDLCI)
-COMPATIBLE_IOCTL(SIOCGMIIPHY)
-COMPATIBLE_IOCTL(SIOCGMIIREG)
-COMPATIBLE_IOCTL(SIOCSMIIREG)
-COMPATIBLE_IOCTL(SIOCGIFVLAN)
-COMPATIBLE_IOCTL(SIOCSIFVLAN)
-COMPATIBLE_IOCTL(SIOCBRADDBR)
-COMPATIBLE_IOCTL(SIOCBRDELBR)
-/* SG stuff */
-COMPATIBLE_IOCTL(SG_SET_TIMEOUT)
-COMPATIBLE_IOCTL(SG_GET_TIMEOUT)
-COMPATIBLE_IOCTL(SG_EMULATED_HOST)
-ULONG_IOCTL(SG_SET_TRANSFORM)
-COMPATIBLE_IOCTL(SG_GET_TRANSFORM)
-COMPATIBLE_IOCTL(SG_SET_RESERVED_SIZE)
-COMPATIBLE_IOCTL(SG_GET_RESERVED_SIZE)
-COMPATIBLE_IOCTL(SG_GET_SCSI_ID)
-COMPATIBLE_IOCTL(SG_SET_FORCE_LOW_DMA)
-COMPATIBLE_IOCTL(SG_GET_LOW_DMA)
-COMPATIBLE_IOCTL(SG_SET_FORCE_PACK_ID)
-COMPATIBLE_IOCTL(SG_GET_PACK_ID)
-COMPATIBLE_IOCTL(SG_GET_NUM_WAITING)
-COMPATIBLE_IOCTL(SG_SET_DEBUG)
-COMPATIBLE_IOCTL(SG_GET_SG_TABLESIZE)
-COMPATIBLE_IOCTL(SG_GET_COMMAND_Q)
-COMPATIBLE_IOCTL(SG_SET_COMMAND_Q)
-COMPATIBLE_IOCTL(SG_GET_VERSION_NUM)
-COMPATIBLE_IOCTL(SG_NEXT_CMD_LEN)
-COMPATIBLE_IOCTL(SG_SCSI_RESET)
-COMPATIBLE_IOCTL(SG_GET_REQUEST_TABLE)
-COMPATIBLE_IOCTL(SG_SET_KEEP_ORPHAN)
-COMPATIBLE_IOCTL(SG_GET_KEEP_ORPHAN)
-/* PPP stuff */
-COMPATIBLE_IOCTL(PPPIOCGFLAGS)
-COMPATIBLE_IOCTL(PPPIOCSFLAGS)
-COMPATIBLE_IOCTL(PPPIOCGASYNCMAP)
-COMPATIBLE_IOCTL(PPPIOCSASYNCMAP)
-COMPATIBLE_IOCTL(PPPIOCGUNIT)
-COMPATIBLE_IOCTL(PPPIOCGRASYNCMAP)
-COMPATIBLE_IOCTL(PPPIOCSRASYNCMAP)
-COMPATIBLE_IOCTL(PPPIOCGMRU)
-COMPATIBLE_IOCTL(PPPIOCSMRU)
-COMPATIBLE_IOCTL(PPPIOCSMAXCID)
-COMPATIBLE_IOCTL(PPPIOCGXASYNCMAP)
-COMPATIBLE_IOCTL(PPPIOCSXASYNCMAP)
-COMPATIBLE_IOCTL(PPPIOCXFERUNIT)
-/* PPPIOCSCOMPRESS is translated */
-COMPATIBLE_IOCTL(PPPIOCGNPMODE)
-COMPATIBLE_IOCTL(PPPIOCSNPMODE)
-COMPATIBLE_IOCTL(PPPIOCGDEBUG)
-COMPATIBLE_IOCTL(PPPIOCSDEBUG)
-/* PPPIOCSPASS is translated */
-/* PPPIOCSACTIVE is translated */
-/* PPPIOCGIDLE is translated */
-COMPATIBLE_IOCTL(PPPIOCNEWUNIT)
-COMPATIBLE_IOCTL(PPPIOCATTACH)
-COMPATIBLE_IOCTL(PPPIOCDETACH)
-COMPATIBLE_IOCTL(PPPIOCSMRRU)
-COMPATIBLE_IOCTL(PPPIOCCONNECT)
-COMPATIBLE_IOCTL(PPPIOCDISCONN)
-COMPATIBLE_IOCTL(PPPIOCATTCHAN)
-COMPATIBLE_IOCTL(PPPIOCGCHAN)
-/* PPPOX */
-COMPATIBLE_IOCTL(PPPOEIOCSFWD)
-COMPATIBLE_IOCTL(PPPOEIOCDFWD)
-/* LP */
-COMPATIBLE_IOCTL(LPGETSTATUS)
-/* ppdev */
-COMPATIBLE_IOCTL(PPSETMODE)
-COMPATIBLE_IOCTL(PPRSTATUS)
-COMPATIBLE_IOCTL(PPRCONTROL)
-COMPATIBLE_IOCTL(PPWCONTROL)
-COMPATIBLE_IOCTL(PPFCONTROL)
-COMPATIBLE_IOCTL(PPRDATA)
-COMPATIBLE_IOCTL(PPWDATA)
-COMPATIBLE_IOCTL(PPCLAIM)
-COMPATIBLE_IOCTL(PPRELEASE)
-COMPATIBLE_IOCTL(PPYIELD)
-COMPATIBLE_IOCTL(PPEXCL)
-COMPATIBLE_IOCTL(PPDATADIR)
-COMPATIBLE_IOCTL(PPNEGOT)
-COMPATIBLE_IOCTL(PPWCTLONIRQ)
-COMPATIBLE_IOCTL(PPCLRIRQ)
-COMPATIBLE_IOCTL(PPSETPHASE)
-COMPATIBLE_IOCTL(PPGETMODES)
-COMPATIBLE_IOCTL(PPGETMODE)
-COMPATIBLE_IOCTL(PPGETPHASE)
-COMPATIBLE_IOCTL(PPGETFLAGS)
-COMPATIBLE_IOCTL(PPSETFLAGS)
-/* CDROM stuff */
-COMPATIBLE_IOCTL(CDROMPAUSE)
-COMPATIBLE_IOCTL(CDROMRESUME)
-COMPATIBLE_IOCTL(CDROMPLAYMSF)
-COMPATIBLE_IOCTL(CDROMPLAYTRKIND)
-COMPATIBLE_IOCTL(CDROMREADTOCHDR)
-COMPATIBLE_IOCTL(CDROMREADTOCENTRY)
-COMPATIBLE_IOCTL(CDROMSTOP)
-COMPATIBLE_IOCTL(CDROMSTART)
-COMPATIBLE_IOCTL(CDROMEJECT)
-COMPATIBLE_IOCTL(CDROMVOLCTRL)
-COMPATIBLE_IOCTL(CDROMSUBCHNL)
-ULONG_IOCTL(CDROMEJECT_SW)
-COMPATIBLE_IOCTL(CDROMMULTISESSION)
-COMPATIBLE_IOCTL(CDROM_GET_MCN)
-COMPATIBLE_IOCTL(CDROMRESET)
-COMPATIBLE_IOCTL(CDROMVOLREAD)
-COMPATIBLE_IOCTL(CDROMSEEK)
-COMPATIBLE_IOCTL(CDROMPLAYBLK)
-COMPATIBLE_IOCTL(CDROMCLOSETRAY)
-ULONG_IOCTL(CDROM_SET_OPTIONS)
-ULONG_IOCTL(CDROM_CLEAR_OPTIONS)
-ULONG_IOCTL(CDROM_SELECT_SPEED)
-ULONG_IOCTL(CDROM_SELECT_DISC)
-ULONG_IOCTL(CDROM_MEDIA_CHANGED)
-ULONG_IOCTL(CDROM_DRIVE_STATUS)
-COMPATIBLE_IOCTL(CDROM_DISC_STATUS)
-COMPATIBLE_IOCTL(CDROM_CHANGER_NSLOTS)
-ULONG_IOCTL(CDROM_LOCKDOOR)
-ULONG_IOCTL(CDROM_DEBUG)
-COMPATIBLE_IOCTL(CDROM_GET_CAPABILITY)
-/* Ignore cdrom.h about these next 5 ioctls, they absolutely do
- * not take a struct cdrom_read, instead they take a struct cdrom_msf
- * which is compatible.
- */
-COMPATIBLE_IOCTL(CDROMREADMODE2)
-COMPATIBLE_IOCTL(CDROMREADMODE1)
-COMPATIBLE_IOCTL(CDROMREADRAW)
-COMPATIBLE_IOCTL(CDROMREADCOOKED)
-COMPATIBLE_IOCTL(CDROMREADALL)
-/* DVD ioctls */
-COMPATIBLE_IOCTL(DVD_READ_STRUCT)
-COMPATIBLE_IOCTL(DVD_WRITE_STRUCT)
-COMPATIBLE_IOCTL(DVD_AUTH)
-/* pktcdvd */
-COMPATIBLE_IOCTL(PACKET_CTRL_CMD)
-/* Big A */
-/* sparc only */
-/* Big Q for sound/OSS */
-COMPATIBLE_IOCTL(SNDCTL_SEQ_RESET)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_SYNC)
-COMPATIBLE_IOCTL(SNDCTL_SYNTH_INFO)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_CTRLRATE)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_GETOUTCOUNT)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_GETINCOUNT)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_PERCMODE)
-COMPATIBLE_IOCTL(SNDCTL_FM_LOAD_INSTR)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_TESTMIDI)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_RESETSAMPLES)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_NRSYNTHS)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_NRMIDIS)
-COMPATIBLE_IOCTL(SNDCTL_MIDI_INFO)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_THRESHOLD)
-COMPATIBLE_IOCTL(SNDCTL_SYNTH_MEMAVL)
-COMPATIBLE_IOCTL(SNDCTL_FM_4OP_ENABLE)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_PANIC)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_OUTOFBAND)
-COMPATIBLE_IOCTL(SNDCTL_SEQ_GETTIME)
-COMPATIBLE_IOCTL(SNDCTL_SYNTH_ID)
-COMPATIBLE_IOCTL(SNDCTL_SYNTH_CONTROL)
-COMPATIBLE_IOCTL(SNDCTL_SYNTH_REMOVESAMPLE)
-/* Big T for sound/OSS */
-COMPATIBLE_IOCTL(SNDCTL_TMR_TIMEBASE)
-COMPATIBLE_IOCTL(SNDCTL_TMR_START)
-COMPATIBLE_IOCTL(SNDCTL_TMR_STOP)
-COMPATIBLE_IOCTL(SNDCTL_TMR_CONTINUE)
-COMPATIBLE_IOCTL(SNDCTL_TMR_TEMPO)
-COMPATIBLE_IOCTL(SNDCTL_TMR_SOURCE)
-COMPATIBLE_IOCTL(SNDCTL_TMR_METRONOME)
-COMPATIBLE_IOCTL(SNDCTL_TMR_SELECT)
-/* Little m for sound/OSS */
-COMPATIBLE_IOCTL(SNDCTL_MIDI_PRETIME)
-COMPATIBLE_IOCTL(SNDCTL_MIDI_MPUMODE)
-COMPATIBLE_IOCTL(SNDCTL_MIDI_MPUCMD)
-/* Big P for sound/OSS */
-COMPATIBLE_IOCTL(SNDCTL_DSP_RESET)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SYNC)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SPEED)
-COMPATIBLE_IOCTL(SNDCTL_DSP_STEREO)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETBLKSIZE)
-COMPATIBLE_IOCTL(SNDCTL_DSP_CHANNELS)
-COMPATIBLE_IOCTL(SOUND_PCM_WRITE_FILTER)
-COMPATIBLE_IOCTL(SNDCTL_DSP_POST)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SUBDIVIDE)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SETFRAGMENT)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETFMTS)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SETFMT)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETOSPACE)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETISPACE)
-COMPATIBLE_IOCTL(SNDCTL_DSP_NONBLOCK)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETCAPS)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETTRIGGER)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SETTRIGGER)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETIPTR)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETOPTR)
-/* SNDCTL_DSP_MAPINBUF,  XXX needs translation */
-/* SNDCTL_DSP_MAPOUTBUF,  XXX needs translation */
-COMPATIBLE_IOCTL(SNDCTL_DSP_SETSYNCRO)
-COMPATIBLE_IOCTL(SNDCTL_DSP_SETDUPLEX)
-COMPATIBLE_IOCTL(SNDCTL_DSP_GETODELAY)
-COMPATIBLE_IOCTL(SNDCTL_DSP_PROFILE)
-COMPATIBLE_IOCTL(SOUND_PCM_READ_RATE)
-COMPATIBLE_IOCTL(SOUND_PCM_READ_CHANNELS)
-COMPATIBLE_IOCTL(SOUND_PCM_READ_BITS)
-COMPATIBLE_IOCTL(SOUND_PCM_READ_FILTER)
-/* Big C for sound/OSS */
-COMPATIBLE_IOCTL(SNDCTL_COPR_RESET)
-COMPATIBLE_IOCTL(SNDCTL_COPR_LOAD)
-COMPATIBLE_IOCTL(SNDCTL_COPR_RDATA)
-COMPATIBLE_IOCTL(SNDCTL_COPR_RCODE)
-COMPATIBLE_IOCTL(SNDCTL_COPR_WDATA)
-COMPATIBLE_IOCTL(SNDCTL_COPR_WCODE)
-COMPATIBLE_IOCTL(SNDCTL_COPR_RUN)
-COMPATIBLE_IOCTL(SNDCTL_COPR_HALT)
-COMPATIBLE_IOCTL(SNDCTL_COPR_SENDMSG)
-COMPATIBLE_IOCTL(SNDCTL_COPR_RCVMSG)
-/* Big M for sound/OSS */
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_VOLUME)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_BASS)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_TREBLE)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_SYNTH)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_PCM)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_SPEAKER)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_LINE)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_MIC)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_CD)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_IMIX)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_ALTPCM)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_RECLEV)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_IGAIN)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_OGAIN)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_LINE1)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_LINE2)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_LINE3)
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_DIGITAL1))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_DIGITAL2))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_DIGITAL3))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_PHONEIN))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_PHONEOUT))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_VIDEO))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_RADIO))
-COMPATIBLE_IOCTL(MIXER_READ(SOUND_MIXER_MONITOR))
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_MUTE)
-/* SOUND_MIXER_READ_ENHANCE,  same value as READ_MUTE */
-/* SOUND_MIXER_READ_LOUD,  same value as READ_MUTE */
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_RECSRC)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_DEVMASK)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_RECMASK)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_STEREODEVS)
-COMPATIBLE_IOCTL(SOUND_MIXER_READ_CAPS)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_VOLUME)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_BASS)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_TREBLE)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_SYNTH)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_PCM)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_SPEAKER)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_LINE)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_MIC)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_CD)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_IMIX)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_ALTPCM)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_RECLEV)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_IGAIN)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_OGAIN)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_LINE1)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_LINE2)
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_LINE3)
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_DIGITAL1))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_DIGITAL2))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_DIGITAL3))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_PHONEIN))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_PHONEOUT))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_VIDEO))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_RADIO))
-COMPATIBLE_IOCTL(MIXER_WRITE(SOUND_MIXER_MONITOR))
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_MUTE)
-/* SOUND_MIXER_WRITE_ENHANCE,  same value as WRITE_MUTE */
-/* SOUND_MIXER_WRITE_LOUD,  same value as WRITE_MUTE */
-COMPATIBLE_IOCTL(SOUND_MIXER_WRITE_RECSRC)
-COMPATIBLE_IOCTL(SOUND_MIXER_INFO)
-COMPATIBLE_IOCTL(SOUND_OLD_MIXER_INFO)
-COMPATIBLE_IOCTL(SOUND_MIXER_ACCESS)
-COMPATIBLE_IOCTL(SOUND_MIXER_AGC)
-COMPATIBLE_IOCTL(SOUND_MIXER_3DSE)
-COMPATIBLE_IOCTL(SOUND_MIXER_PRIVATE1)
-COMPATIBLE_IOCTL(SOUND_MIXER_PRIVATE2)
-COMPATIBLE_IOCTL(SOUND_MIXER_PRIVATE3)
-COMPATIBLE_IOCTL(SOUND_MIXER_PRIVATE4)
-COMPATIBLE_IOCTL(SOUND_MIXER_PRIVATE5)
-COMPATIBLE_IOCTL(SOUND_MIXER_GETLEVELS)
-COMPATIBLE_IOCTL(SOUND_MIXER_SETLEVELS)
-COMPATIBLE_IOCTL(OSS_GETVERSION)
-/* AUTOFS */
-ULONG_IOCTL(AUTOFS_IOC_READY)
-ULONG_IOCTL(AUTOFS_IOC_FAIL)
-COMPATIBLE_IOCTL(AUTOFS_IOC_CATATONIC)
-COMPATIBLE_IOCTL(AUTOFS_IOC_PROTOVER)
-COMPATIBLE_IOCTL(AUTOFS_IOC_EXPIRE)
-COMPATIBLE_IOCTL(AUTOFS_IOC_EXPIRE_MULTI)
-COMPATIBLE_IOCTL(AUTOFS_IOC_PROTOSUBVER)
-COMPATIBLE_IOCTL(AUTOFS_IOC_ASKREGHOST)
-COMPATIBLE_IOCTL(AUTOFS_IOC_TOGGLEREGHOST)
-COMPATIBLE_IOCTL(AUTOFS_IOC_ASKUMOUNT)
-/* Raw devices */
-COMPATIBLE_IOCTL(RAW_SETBIND)
-COMPATIBLE_IOCTL(RAW_GETBIND)
-/* SMB ioctls which do not need any translations */
-COMPATIBLE_IOCTL(SMB_IOC_NEWCONN)
-/* Little a */
-COMPATIBLE_IOCTL(ATMSIGD_CTRL)
-COMPATIBLE_IOCTL(ATMARPD_CTRL)
-COMPATIBLE_IOCTL(ATMLEC_CTRL)
-COMPATIBLE_IOCTL(ATMLEC_MCAST)
-COMPATIBLE_IOCTL(ATMLEC_DATA)
-COMPATIBLE_IOCTL(ATM_SETSC)
-COMPATIBLE_IOCTL(SIOCSIFATMTCP)
-COMPATIBLE_IOCTL(SIOCMKCLIP)
-COMPATIBLE_IOCTL(ATMARP_MKIP)
-COMPATIBLE_IOCTL(ATMARP_SETENTRY)
-COMPATIBLE_IOCTL(ATMARP_ENCAP)
-COMPATIBLE_IOCTL(ATMTCP_CREATE)
-COMPATIBLE_IOCTL(ATMTCP_REMOVE)
-COMPATIBLE_IOCTL(ATMMPC_CTRL)
-COMPATIBLE_IOCTL(ATMMPC_DATA)
-/* Watchdog */
-COMPATIBLE_IOCTL(WDIOC_GETSUPPORT)
-COMPATIBLE_IOCTL(WDIOC_GETSTATUS)
-COMPATIBLE_IOCTL(WDIOC_GETBOOTSTATUS)
-COMPATIBLE_IOCTL(WDIOC_GETTEMP)
-COMPATIBLE_IOCTL(WDIOC_SETOPTIONS)
-COMPATIBLE_IOCTL(WDIOC_KEEPALIVE)
-COMPATIBLE_IOCTL(WDIOC_SETTIMEOUT)
-COMPATIBLE_IOCTL(WDIOC_GETTIMEOUT)
-/* Big R */
-COMPATIBLE_IOCTL(RNDGETENTCNT)
-COMPATIBLE_IOCTL(RNDADDTOENTCNT)
-COMPATIBLE_IOCTL(RNDGETPOOL)
-COMPATIBLE_IOCTL(RNDADDENTROPY)
-COMPATIBLE_IOCTL(RNDZAPENTCNT)
-COMPATIBLE_IOCTL(RNDCLEARPOOL)
-/* Bluetooth */
-COMPATIBLE_IOCTL(HCIDEVUP)
-COMPATIBLE_IOCTL(HCIDEVDOWN)
-COMPATIBLE_IOCTL(HCIDEVRESET)
-COMPATIBLE_IOCTL(HCIDEVRESTAT)
-COMPATIBLE_IOCTL(HCIGETDEVLIST)
-COMPATIBLE_IOCTL(HCIGETDEVINFO)
-COMPATIBLE_IOCTL(HCIGETCONNLIST)
-COMPATIBLE_IOCTL(HCIGETCONNINFO)
-COMPATIBLE_IOCTL(HCISETRAW)
-COMPATIBLE_IOCTL(HCISETSCAN)
-COMPATIBLE_IOCTL(HCISETAUTH)
-COMPATIBLE_IOCTL(HCISETENCRYPT)
-COMPATIBLE_IOCTL(HCISETPTYPE)
-COMPATIBLE_IOCTL(HCISETLINKPOL)
-COMPATIBLE_IOCTL(HCISETLINKMODE)
-COMPATIBLE_IOCTL(HCISETACLMTU)
-COMPATIBLE_IOCTL(HCISETSCOMTU)
-COMPATIBLE_IOCTL(HCIINQUIRY)
-COMPATIBLE_IOCTL(HCIUARTSETPROTO)
-COMPATIBLE_IOCTL(HCIUARTGETPROTO)
-COMPATIBLE_IOCTL(RFCOMMCREATEDEV)
-COMPATIBLE_IOCTL(RFCOMMRELEASEDEV)
-COMPATIBLE_IOCTL(RFCOMMGETDEVLIST)
-COMPATIBLE_IOCTL(RFCOMMGETDEVINFO)
-COMPATIBLE_IOCTL(RFCOMMSTEALDLC)
-COMPATIBLE_IOCTL(BNEPCONNADD)
-COMPATIBLE_IOCTL(BNEPCONNDEL)
-COMPATIBLE_IOCTL(BNEPGETCONNLIST)
-COMPATIBLE_IOCTL(BNEPGETCONNINFO)
-COMPATIBLE_IOCTL(CMTPCONNADD)
-COMPATIBLE_IOCTL(CMTPCONNDEL)
-COMPATIBLE_IOCTL(CMTPGETCONNLIST)
-COMPATIBLE_IOCTL(CMTPGETCONNINFO)
-COMPATIBLE_IOCTL(HIDPCONNADD)
-COMPATIBLE_IOCTL(HIDPCONNDEL)
-COMPATIBLE_IOCTL(HIDPGETCONNLIST)
-COMPATIBLE_IOCTL(HIDPGETCONNINFO)
-/* CAPI */
-COMPATIBLE_IOCTL(CAPI_REGISTER)
-COMPATIBLE_IOCTL(CAPI_GET_MANUFACTURER)
-COMPATIBLE_IOCTL(CAPI_GET_VERSION)
-COMPATIBLE_IOCTL(CAPI_GET_SERIAL)
-COMPATIBLE_IOCTL(CAPI_GET_PROFILE)
-COMPATIBLE_IOCTL(CAPI_MANUFACTURER_CMD)
-COMPATIBLE_IOCTL(CAPI_GET_ERRCODE)
-COMPATIBLE_IOCTL(CAPI_INSTALLED)
-COMPATIBLE_IOCTL(CAPI_GET_FLAGS)
-COMPATIBLE_IOCTL(CAPI_SET_FLAGS)
-COMPATIBLE_IOCTL(CAPI_CLR_FLAGS)
-COMPATIBLE_IOCTL(CAPI_NCCI_OPENCOUNT)
-COMPATIBLE_IOCTL(CAPI_NCCI_GETUNIT)
-/* Siemens Gigaset */
-COMPATIBLE_IOCTL(GIGASET_REDIR)
-COMPATIBLE_IOCTL(GIGASET_CONFIG)
-COMPATIBLE_IOCTL(GIGASET_BRKCHARS)
-COMPATIBLE_IOCTL(GIGASET_VERSION)
-/* Misc. */
-COMPATIBLE_IOCTL(0x41545900)            /* ATYIO_CLKR */
-COMPATIBLE_IOCTL(0x41545901)            /* ATYIO_CLKW */
-COMPATIBLE_IOCTL(PCIIOC_CONTROLLER)
-COMPATIBLE_IOCTL(PCIIOC_MMAP_IS_IO)
-COMPATIBLE_IOCTL(PCIIOC_MMAP_IS_MEM)
-COMPATIBLE_IOCTL(PCIIOC_WRITE_COMBINE)
-/* USB */
-COMPATIBLE_IOCTL(USBDEVFS_RESETEP)
-COMPATIBLE_IOCTL(USBDEVFS_SETINTERFACE)
-COMPATIBLE_IOCTL(USBDEVFS_SETCONFIGURATION)
-COMPATIBLE_IOCTL(USBDEVFS_GETDRIVER)
-COMPATIBLE_IOCTL(USBDEVFS_DISCARDURB)
-COMPATIBLE_IOCTL(USBDEVFS_CLAIMINTERFACE)
-COMPATIBLE_IOCTL(USBDEVFS_RELEASEINTERFACE)
-COMPATIBLE_IOCTL(USBDEVFS_CONNECTINFO)
-COMPATIBLE_IOCTL(USBDEVFS_HUB_PORTINFO)
-COMPATIBLE_IOCTL(USBDEVFS_RESET)
-COMPATIBLE_IOCTL(USBDEVFS_SUBMITURB32)
-COMPATIBLE_IOCTL(USBDEVFS_REAPURB32)
-COMPATIBLE_IOCTL(USBDEVFS_REAPURBNDELAY32)
-COMPATIBLE_IOCTL(USBDEVFS_CLEAR_HALT)
-/* MTD */
-COMPATIBLE_IOCTL(MEMGETINFO)
-COMPATIBLE_IOCTL(MEMERASE)
-COMPATIBLE_IOCTL(MEMLOCK)
-COMPATIBLE_IOCTL(MEMUNLOCK)
-COMPATIBLE_IOCTL(MEMGETREGIONCOUNT)
-COMPATIBLE_IOCTL(MEMGETREGIONINFO)
-COMPATIBLE_IOCTL(MEMGETBADBLOCK)
-COMPATIBLE_IOCTL(MEMSETBADBLOCK)
-/* NBD */
-ULONG_IOCTL(NBD_SET_SOCK)
-ULONG_IOCTL(NBD_SET_BLKSIZE)
-ULONG_IOCTL(NBD_SET_SIZE)
-COMPATIBLE_IOCTL(NBD_DO_IT)
-COMPATIBLE_IOCTL(NBD_CLEAR_SOCK)
-COMPATIBLE_IOCTL(NBD_CLEAR_QUE)
-COMPATIBLE_IOCTL(NBD_PRINT_DEBUG)
-ULONG_IOCTL(NBD_SET_SIZE_BLOCKS)
-COMPATIBLE_IOCTL(NBD_DISCONNECT)
-/* i2c */
-COMPATIBLE_IOCTL(I2C_SLAVE)
-COMPATIBLE_IOCTL(I2C_SLAVE_FORCE)
-COMPATIBLE_IOCTL(I2C_TENBIT)
-COMPATIBLE_IOCTL(I2C_PEC)
-COMPATIBLE_IOCTL(I2C_RETRIES)
-COMPATIBLE_IOCTL(I2C_TIMEOUT)
-/* wireless */
-COMPATIBLE_IOCTL(SIOCSIWCOMMIT)
-COMPATIBLE_IOCTL(SIOCGIWNAME)
-COMPATIBLE_IOCTL(SIOCSIWNWID)
-COMPATIBLE_IOCTL(SIOCGIWNWID)
-COMPATIBLE_IOCTL(SIOCSIWFREQ)
-COMPATIBLE_IOCTL(SIOCGIWFREQ)
-COMPATIBLE_IOCTL(SIOCSIWMODE)
-COMPATIBLE_IOCTL(SIOCGIWMODE)
-COMPATIBLE_IOCTL(SIOCSIWSENS)
-COMPATIBLE_IOCTL(SIOCGIWSENS)
-COMPATIBLE_IOCTL(SIOCSIWRANGE)
-COMPATIBLE_IOCTL(SIOCSIWPRIV)
-COMPATIBLE_IOCTL(SIOCGIWPRIV)
-COMPATIBLE_IOCTL(SIOCSIWSTATS)
-COMPATIBLE_IOCTL(SIOCGIWSTATS)
-COMPATIBLE_IOCTL(SIOCSIWAP)
-COMPATIBLE_IOCTL(SIOCGIWAP)
-COMPATIBLE_IOCTL(SIOCSIWSCAN)
-COMPATIBLE_IOCTL(SIOCSIWRATE)
-COMPATIBLE_IOCTL(SIOCGIWRATE)
-COMPATIBLE_IOCTL(SIOCSIWRTS)
-COMPATIBLE_IOCTL(SIOCGIWRTS)
-COMPATIBLE_IOCTL(SIOCSIWFRAG)
-COMPATIBLE_IOCTL(SIOCGIWFRAG)
-COMPATIBLE_IOCTL(SIOCSIWTXPOW)
-COMPATIBLE_IOCTL(SIOCGIWTXPOW)
-COMPATIBLE_IOCTL(SIOCSIWRETRY)
-COMPATIBLE_IOCTL(SIOCGIWRETRY)
-COMPATIBLE_IOCTL(SIOCSIWPOWER)
-COMPATIBLE_IOCTL(SIOCGIWPOWER)
-/* hiddev */
-COMPATIBLE_IOCTL(HIDIOCGVERSION)
-COMPATIBLE_IOCTL(HIDIOCAPPLICATION)
-COMPATIBLE_IOCTL(HIDIOCGDEVINFO)
-COMPATIBLE_IOCTL(HIDIOCGSTRING)
-COMPATIBLE_IOCTL(HIDIOCINITREPORT)
-COMPATIBLE_IOCTL(HIDIOCGREPORT)
-COMPATIBLE_IOCTL(HIDIOCSREPORT)
-COMPATIBLE_IOCTL(HIDIOCGREPORTINFO)
-COMPATIBLE_IOCTL(HIDIOCGFIELDINFO)
-COMPATIBLE_IOCTL(HIDIOCGUSAGE)
-COMPATIBLE_IOCTL(HIDIOCSUSAGE)
-COMPATIBLE_IOCTL(HIDIOCGUCODE)
-COMPATIBLE_IOCTL(HIDIOCGFLAG)
-COMPATIBLE_IOCTL(HIDIOCSFLAG)
-COMPATIBLE_IOCTL(HIDIOCGCOLLECTIONINDEX)
-COMPATIBLE_IOCTL(HIDIOCGCOLLECTIONINFO)
-/* dvb */
-COMPATIBLE_IOCTL(AUDIO_STOP)
-COMPATIBLE_IOCTL(AUDIO_PLAY)
-COMPATIBLE_IOCTL(AUDIO_PAUSE)
-COMPATIBLE_IOCTL(AUDIO_CONTINUE)
-COMPATIBLE_IOCTL(AUDIO_SELECT_SOURCE)
-COMPATIBLE_IOCTL(AUDIO_SET_MUTE)
-COMPATIBLE_IOCTL(AUDIO_SET_AV_SYNC)
-COMPATIBLE_IOCTL(AUDIO_SET_BYPASS_MODE)
-COMPATIBLE_IOCTL(AUDIO_CHANNEL_SELECT)
-COMPATIBLE_IOCTL(AUDIO_GET_STATUS)
-COMPATIBLE_IOCTL(AUDIO_GET_CAPABILITIES)
-COMPATIBLE_IOCTL(AUDIO_CLEAR_BUFFER)
-COMPATIBLE_IOCTL(AUDIO_SET_ID)
-COMPATIBLE_IOCTL(AUDIO_SET_MIXER)
-COMPATIBLE_IOCTL(AUDIO_SET_STREAMTYPE)
-COMPATIBLE_IOCTL(AUDIO_SET_EXT_ID)
-COMPATIBLE_IOCTL(AUDIO_SET_ATTRIBUTES)
-COMPATIBLE_IOCTL(AUDIO_SET_KARAOKE)
-COMPATIBLE_IOCTL(DMX_START)
-COMPATIBLE_IOCTL(DMX_STOP)
-COMPATIBLE_IOCTL(DMX_SET_FILTER)
-COMPATIBLE_IOCTL(DMX_SET_PES_FILTER)
-COMPATIBLE_IOCTL(DMX_SET_BUFFER_SIZE)
-COMPATIBLE_IOCTL(DMX_GET_PES_PIDS)
-COMPATIBLE_IOCTL(DMX_GET_CAPS)
-COMPATIBLE_IOCTL(DMX_SET_SOURCE)
-COMPATIBLE_IOCTL(DMX_GET_STC)
-COMPATIBLE_IOCTL(FE_GET_INFO)
-COMPATIBLE_IOCTL(FE_DISEQC_RESET_OVERLOAD)
-COMPATIBLE_IOCTL(FE_DISEQC_SEND_MASTER_CMD)
-COMPATIBLE_IOCTL(FE_DISEQC_RECV_SLAVE_REPLY)
-COMPATIBLE_IOCTL(FE_DISEQC_SEND_BURST)
-COMPATIBLE_IOCTL(FE_SET_TONE)
-COMPATIBLE_IOCTL(FE_SET_VOLTAGE)
-COMPATIBLE_IOCTL(FE_ENABLE_HIGH_LNB_VOLTAGE)
-COMPATIBLE_IOCTL(FE_READ_STATUS)
-COMPATIBLE_IOCTL(FE_READ_BER)
-COMPATIBLE_IOCTL(FE_READ_SIGNAL_STRENGTH)
-COMPATIBLE_IOCTL(FE_READ_SNR)
-COMPATIBLE_IOCTL(FE_READ_UNCORRECTED_BLOCKS)
-COMPATIBLE_IOCTL(FE_SET_FRONTEND)
-COMPATIBLE_IOCTL(FE_GET_FRONTEND)
-COMPATIBLE_IOCTL(FE_GET_EVENT)
-COMPATIBLE_IOCTL(FE_DISHNETWORK_SEND_LEGACY_CMD)
-COMPATIBLE_IOCTL(VIDEO_STOP)
-COMPATIBLE_IOCTL(VIDEO_PLAY)
-COMPATIBLE_IOCTL(VIDEO_FREEZE)
-COMPATIBLE_IOCTL(VIDEO_CONTINUE)
-COMPATIBLE_IOCTL(VIDEO_SELECT_SOURCE)
-COMPATIBLE_IOCTL(VIDEO_SET_BLANK)
-COMPATIBLE_IOCTL(VIDEO_GET_STATUS)
-COMPATIBLE_IOCTL(VIDEO_SET_DISPLAY_FORMAT)
-COMPATIBLE_IOCTL(VIDEO_FAST_FORWARD)
-COMPATIBLE_IOCTL(VIDEO_SLOWMOTION)
-COMPATIBLE_IOCTL(VIDEO_GET_CAPABILITIES)
-COMPATIBLE_IOCTL(VIDEO_CLEAR_BUFFER)
-COMPATIBLE_IOCTL(VIDEO_SET_ID)
-COMPATIBLE_IOCTL(VIDEO_SET_STREAMTYPE)
-COMPATIBLE_IOCTL(VIDEO_SET_FORMAT)
-COMPATIBLE_IOCTL(VIDEO_SET_SYSTEM)
-COMPATIBLE_IOCTL(VIDEO_SET_HIGHLIGHT)
-COMPATIBLE_IOCTL(VIDEO_SET_SPU)
-COMPATIBLE_IOCTL(VIDEO_GET_NAVI)
-COMPATIBLE_IOCTL(VIDEO_SET_ATTRIBUTES)
-COMPATIBLE_IOCTL(VIDEO_GET_SIZE)
-COMPATIBLE_IOCTL(VIDEO_GET_FRAME_RATE)
diff --git a/include/linux/compiler-gcc.h b/include/linux/compiler-gcc.h
index 9008eabb9c3d..a9f794716a81 100644
--- a/include/linux/compiler-gcc.h
+++ b/include/linux/compiler-gcc.h
@@ -22,6 +22,9 @@
     __asm__ ("" : "=r"(__ptr) : "0"(ptr));              \
     (typeof(ptr)) (__ptr + (off)); })
 
+/* &a[0] degrades to a pointer: a different type from an array */
+#define __must_be_array(a) \
+  BUILD_BUG_ON_ZERO(__builtin_types_compatible_p(typeof(a), typeof(&a[0])))
 
 #define inline          inline          __attribute__((always_inline))
 #define __inline__      __inline__      __attribute__((always_inline))
diff --git a/include/linux/compiler-gcc3.h b/include/linux/compiler-gcc3.h
index 1698b845761f..ecd621fd27d2 100644
--- a/include/linux/compiler-gcc3.h
+++ b/include/linux/compiler-gcc3.h
@@ -13,4 +13,10 @@
 #define __must_check            __attribute__((warn_unused_result))
 #endif
 
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
+
 #define __always_inline         inline __attribute__((always_inline))
diff --git a/include/linux/compiler-gcc4.h b/include/linux/compiler-gcc4.h
index 6f5cc6f0e7a6..fd0cc7c4a636 100644
--- a/include/linux/compiler-gcc4.h
+++ b/include/linux/compiler-gcc4.h
@@ -16,3 +16,9 @@
 #define __must_check            __attribute__((warn_unused_result))
 #define __compiler_offsetof(a,b) __builtin_offsetof(a,b)
 #define __always_inline         inline __attribute__((always_inline))
+
+/*
+ * A trick to suppress uninitialized variable warning without generating any
+ * code
+ */
+#define uninitialized_var(x) x = x
diff --git a/include/linux/compiler-intel.h b/include/linux/compiler-intel.h
index 1d1c3ceaff4e..b769961e6f23 100644
--- a/include/linux/compiler-intel.h
+++ b/include/linux/compiler-intel.h
@@ -21,4 +21,9 @@
      __ptr = (unsigned long) (ptr);                             \
     (typeof(ptr)) (__ptr + (off)); })
 
+/* Intel ECC compiler doesn't support __builtin_types_compatible_p() */
+#define __must_be_array(a) 0
+
 #endif
+
+#define uninitialized_var(x) x
diff --git a/include/linux/console.h b/include/linux/console.h
index de25ee3b7919..62ef6e11d0d2 100644
--- a/include/linux/console.h
+++ b/include/linux/console.h
@@ -51,7 +51,7 @@ struct consw {
         int     (*con_scrolldelta)(struct vc_data *, int);
         int     (*con_set_origin)(struct vc_data *);
         void    (*con_save_screen)(struct vc_data *);
-        u8      (*con_build_attr)(struct vc_data *, u8, u8, u8, u8, u8);
+        u8      (*con_build_attr)(struct vc_data *, u8, u8, u8, u8, u8, u8);
         void    (*con_invert_region)(struct vc_data *, u16 *, int);
         u16    *(*con_screen_pos)(struct vc_data *, int);
         unsigned long (*con_getxy)(struct vc_data *, unsigned long, int *, int *);
@@ -92,9 +92,8 @@ void give_up_console(const struct consw *sw);
 #define CON_BOOT        (8)
 #define CON_ANYTIME     (16) /* Safe to call when cpu is offline */
 
-struct console
-{
-        char    name[8];
+struct console {
+        char    name[16];
         void    (*write)(struct console *, const char *, unsigned);
         int     (*read)(struct console *, char *, unsigned);
         struct tty_driver *(*device)(struct console *, int *);
diff --git a/include/linux/console_struct.h b/include/linux/console_struct.h
index a86162b26c0d..a461f76fb004 100644
--- a/include/linux/console_struct.h
+++ b/include/linux/console_struct.h
@@ -37,6 +37,7 @@ struct vc_data {
         unsigned char   vc_color;               /* Foreground & background */
         unsigned char   vc_s_color;             /* Saved foreground & background */
         unsigned char   vc_ulcolor;             /* Color for underline mode */
+        unsigned char   vc_itcolor;
         unsigned char   vc_halfcolor;           /* Color for half intensity mode */
         /* cursor */
         unsigned int    vc_cursor_type;
@@ -71,10 +72,12 @@ struct vc_data {
         unsigned int    vc_deccolm      : 1;    /* 80/132 Column Mode */
         /* attribute flags */
         unsigned int    vc_intensity    : 2;    /* 0=half-bright, 1=normal, 2=bold */
+        unsigned int    vc_italic:1;
         unsigned int    vc_underline    : 1;
         unsigned int    vc_blink        : 1;
         unsigned int    vc_reverse      : 1;
         unsigned int    vc_s_intensity  : 2;    /* saved rendition */
+        unsigned int    vc_s_italic:1;
         unsigned int    vc_s_underline  : 1;
         unsigned int    vc_s_blink      : 1;
         unsigned int    vc_s_reverse    : 1;
diff --git a/include/asm-x86_64/const.h b/include/linux/const.h
index 54fb08f3db9b..07b300bfe34b 100644
--- a/include/asm-x86_64/const.h
+++ b/include/linux/const.h
@@ -1,11 +1,11 @@
 /* const.h: Macros for dealing with constants.  */
 
-#ifndef _X86_64_CONST_H
-#define _X86_64_CONST_H
+#ifndef _LINUX_CONST_H
+#define _LINUX_CONST_H
 
 /* Some constant macros are used in both assembler and
  * C code.  Therefore we cannot annotate them always with
- * 'UL' and other type specificers unilaterally.  We
+ * 'UL' and other type specifiers unilaterally.  We
  * use the following macros to deal with this.
  */
 
@@ -16,5 +16,4 @@
 #define _AC(X,Y)        __AC(X,Y)
 #endif
 
-
-#endif /* !(_X86_64_CONST_H) */
+#endif /* !(_LINUX_CONST_H) */
diff --git a/include/linux/cpu.h b/include/linux/cpu.h
index c22b0dfcbcd2..3b2df2523f1d 100644
--- a/include/linux/cpu.h
+++ b/include/linux/cpu.h
@@ -41,6 +41,9 @@ extern void cpu_remove_sysdev_attr(struct sysdev_attribute *attr);
 extern int cpu_add_sysdev_attr_group(struct attribute_group *attrs);
 extern void cpu_remove_sysdev_attr_group(struct attribute_group *attrs);
 
+extern struct sysdev_attribute attr_sched_mc_power_savings;
+extern struct sysdev_attribute attr_sched_smt_power_savings;
+extern int sched_create_sysfs_power_savings_entries(struct sysdev_class *cls);
 
 #ifdef CONFIG_HOTPLUG_CPU
 extern void unregister_cpu(struct cpu *cpu);
diff --git a/include/linux/cyclades.h b/include/linux/cyclades.h
index 46d8254c1a79..72aa00cc4b2d 100644
--- a/include/linux/cyclades.h
+++ b/include/linux/cyclades.h
@@ -67,6 +67,8 @@
 #ifndef _LINUX_CYCLADES_H
 #define _LINUX_CYCLADES_H
 
+#include <linux/types.h>
+
 struct cyclades_monitor {
         unsigned long           int_count;
         unsigned long           char_count;
@@ -108,7 +110,6 @@ struct cyclades_idle_stats {
 #define CYZSETPOLLCYCLE         0x43590e
 #define CYZGETPOLLCYCLE         0x43590f
 #define CYGETCD1400VER          0x435910
-#define CYGETCARDINFO           0x435911
 #define CYSETWAIT               0x435912
 #define CYGETWAIT               0x435913
 
@@ -149,14 +150,12 @@ struct CYZ_BOOT_CTRL {
  *      architectures and compilers.
  */
 
-#if defined(__alpha__)
-typedef unsigned long   ucdouble;       /* 64 bits, unsigned */
-typedef unsigned int    uclong;         /* 32 bits, unsigned */
-#else
-typedef unsigned long   uclong;         /* 32 bits, unsigned */
-#endif
-typedef unsigned short  ucshort;        /* 16 bits, unsigned */
-typedef unsigned char   ucchar;         /* 8 bits, unsigned */
+#include <asm/types.h>
+
+typedef __u64  ucdouble;                /* 64 bits, unsigned */
+typedef __u32  uclong;                  /* 32 bits, unsigned */
+typedef __u16  ucshort;         /* 16 bits, unsigned */
+typedef __u8   ucchar;                  /* 8 bits, unsigned */
 
 /*
  *      Memory Window Sizes
@@ -174,24 +173,24 @@ typedef unsigned char	ucchar;		/* 8 bits, unsigned */
  */
 
 struct  CUSTOM_REG {
-        uclong  fpga_id;                /* FPGA Identification Register */
-        uclong  fpga_version;           /* FPGA Version Number Register */
-        uclong  cpu_start;              /* CPU start Register (write) */
-        uclong  cpu_stop;               /* CPU stop Register (write) */
-        uclong  misc_reg;               /* Miscelaneous Register */
-        uclong  idt_mode;               /* IDT mode Register */
-        uclong  uart_irq_status;        /* UART IRQ status Register */
-        uclong  clear_timer0_irq;       /* Clear timer interrupt Register */
-        uclong  clear_timer1_irq;       /* Clear timer interrupt Register */
-        uclong  clear_timer2_irq;       /* Clear timer interrupt Register */
-        uclong  test_register;          /* Test Register */
-        uclong  test_count;             /* Test Count Register */
-        uclong  timer_select;           /* Timer select register */
-        uclong  pr_uart_irq_status;     /* Prioritized UART IRQ stat Reg */
-        uclong  ram_wait_state;         /* RAM wait-state Register */
-        uclong  uart_wait_state;        /* UART wait-state Register */
-        uclong  timer_wait_state;       /* timer wait-state Register */
-        uclong  ack_wait_state;         /* ACK wait State Register */
+        __u32   fpga_id;                /* FPGA Identification Register */
+        __u32   fpga_version;           /* FPGA Version Number Register */
+        __u32   cpu_start;              /* CPU start Register (write) */
+        __u32   cpu_stop;               /* CPU stop Register (write) */
+        __u32   misc_reg;               /* Miscelaneous Register */
+        __u32   idt_mode;               /* IDT mode Register */
+        __u32   uart_irq_status;        /* UART IRQ status Register */
+        __u32   clear_timer0_irq;       /* Clear timer interrupt Register */
+        __u32   clear_timer1_irq;       /* Clear timer interrupt Register */
+        __u32   clear_timer2_irq;       /* Clear timer interrupt Register */
+        __u32   test_register;          /* Test Register */
+        __u32   test_count;             /* Test Count Register */
+        __u32   timer_select;           /* Timer select register */
+        __u32   pr_uart_irq_status;     /* Prioritized UART IRQ stat Reg */
+        __u32   ram_wait_state;         /* RAM wait-state Register */
+        __u32   uart_wait_state;        /* UART wait-state Register */
+        __u32   timer_wait_state;       /* timer wait-state Register */
+        __u32   ack_wait_state;         /* ACK wait State Register */
 };
 
 /*
@@ -201,34 +200,34 @@ struct	CUSTOM_REG {
  */
 
 struct RUNTIME_9060 {
-        uclong  loc_addr_range; /* 00h - Local Address Range */
-        uclong  loc_addr_base;  /* 04h - Local Address Base */
-        uclong  loc_arbitr;     /* 08h - Local Arbitration */
-        uclong  endian_descr;   /* 0Ch - Big/Little Endian Descriptor */
-        uclong  loc_rom_range;  /* 10h - Local ROM Range */
-        uclong  loc_rom_base;   /* 14h - Local ROM Base */
-        uclong  loc_bus_descr;  /* 18h - Local Bus descriptor */
-        uclong  loc_range_mst;  /* 1Ch - Local Range for Master to PCI */
-        uclong  loc_base_mst;   /* 20h - Local Base for Master PCI */
-        uclong  loc_range_io;   /* 24h - Local Range for Master IO */
-        uclong  pci_base_mst;   /* 28h - PCI Base for Master PCI */
-        uclong  pci_conf_io;    /* 2Ch - PCI configuration for Master IO */
-        uclong  filler1;        /* 30h */
-        uclong  filler2;        /* 34h */
-        uclong  filler3;        /* 38h */
-        uclong  filler4;        /* 3Ch */
-        uclong  mail_box_0;     /* 40h - Mail Box 0 */
-        uclong  mail_box_1;     /* 44h - Mail Box 1 */
-        uclong  mail_box_2;     /* 48h - Mail Box 2 */
-        uclong  mail_box_3;     /* 4Ch - Mail Box 3 */
-        uclong  filler5;        /* 50h */
-        uclong  filler6;        /* 54h */
-        uclong  filler7;        /* 58h */
-        uclong  filler8;        /* 5Ch */
-        uclong  pci_doorbell;   /* 60h - PCI to Local Doorbell */
-        uclong  loc_doorbell;   /* 64h - Local to PCI Doorbell */
-        uclong  intr_ctrl_stat; /* 68h - Interrupt Control/Status */
-        uclong  init_ctrl;      /* 6Ch - EEPROM control, Init Control, etc */
+        __u32   loc_addr_range; /* 00h - Local Address Range */
+        __u32   loc_addr_base;  /* 04h - Local Address Base */
+        __u32   loc_arbitr;     /* 08h - Local Arbitration */
+        __u32   endian_descr;   /* 0Ch - Big/Little Endian Descriptor */
+        __u32   loc_rom_range;  /* 10h - Local ROM Range */
+        __u32   loc_rom_base;   /* 14h - Local ROM Base */
+        __u32   loc_bus_descr;  /* 18h - Local Bus descriptor */
+        __u32   loc_range_mst;  /* 1Ch - Local Range for Master to PCI */
+        __u32   loc_base_mst;   /* 20h - Local Base for Master PCI */
+        __u32   loc_range_io;   /* 24h - Local Range for Master IO */
+        __u32   pci_base_mst;   /* 28h - PCI Base for Master PCI */
+        __u32   pci_conf_io;    /* 2Ch - PCI configuration for Master IO */
+        __u32   filler1;        /* 30h */
+        __u32   filler2;        /* 34h */
+        __u32   filler3;        /* 38h */
+        __u32   filler4;        /* 3Ch */
+        __u32   mail_box_0;     /* 40h - Mail Box 0 */
+        __u32   mail_box_1;     /* 44h - Mail Box 1 */
+        __u32   mail_box_2;     /* 48h - Mail Box 2 */
+        __u32   mail_box_3;     /* 4Ch - Mail Box 3 */
+        __u32   filler5;        /* 50h */
+        __u32   filler6;        /* 54h */
+        __u32   filler7;        /* 58h */
+        __u32   filler8;        /* 5Ch */
+        __u32   pci_doorbell;   /* 60h - PCI to Local Doorbell */
+        __u32   loc_doorbell;   /* 64h - Local to PCI Doorbell */
+        __u32   intr_ctrl_stat; /* 68h - Interrupt Control/Status */
+        __u32   init_ctrl;      /* 6Ch - EEPROM control, Init Control, etc */
 };
 
 /* Values for the Local Base Address re-map register */
@@ -270,8 +269,8 @@ struct RUNTIME_9060 {
 #define ZF_TINACT       ZF_TINACT_DEF
 
 struct  FIRM_ID {
-        uclong  signature;              /* ZFIRM/U signature */
-        uclong  zfwctrl_addr;           /* pointer to ZFW_CTRL structure */
+        __u32   signature;              /* ZFIRM/U signature */
+        __u32   zfwctrl_addr;           /* pointer to ZFW_CTRL structure */
 };
 
 /* Op. System id */
@@ -408,24 +407,24 @@ struct	FIRM_ID {
  */
 
 struct CH_CTRL {
-        uclong  op_mode;        /* operation mode */
-        uclong  intr_enable;    /* interrupt masking */
-        uclong  sw_flow;        /* SW flow control */
-        uclong  flow_status;    /* output flow status */
-        uclong  comm_baud;      /* baud rate  - numerically specified */
-        uclong  comm_parity;    /* parity */
-        uclong  comm_data_l;    /* data length/stop */
-        uclong  comm_flags;     /* other flags */
-        uclong  hw_flow;        /* HW flow control */
-        uclong  rs_control;     /* RS-232 outputs */
-        uclong  rs_status;      /* RS-232 inputs */
-        uclong  flow_xon;       /* xon char */
-        uclong  flow_xoff;      /* xoff char */
-        uclong  hw_overflow;    /* hw overflow counter */
-        uclong  sw_overflow;    /* sw overflow counter */
-        uclong  comm_error;     /* frame/parity error counter */
-        uclong ichar;
-        uclong filler[7];
+        __u32   op_mode;        /* operation mode */
+        __u32   intr_enable;    /* interrupt masking */
+        __u32   sw_flow;        /* SW flow control */
+        __u32   flow_status;    /* output flow status */
+        __u32   comm_baud;      /* baud rate  - numerically specified */
+        __u32   comm_parity;    /* parity */
+        __u32   comm_data_l;    /* data length/stop */
+        __u32   comm_flags;     /* other flags */
+        __u32   hw_flow;        /* HW flow control */
+        __u32   rs_control;     /* RS-232 outputs */
+        __u32   rs_status;      /* RS-232 inputs */
+        __u32   flow_xon;       /* xon char */
+        __u32   flow_xoff;      /* xoff char */
+        __u32   hw_overflow;    /* hw overflow counter */
+        __u32   sw_overflow;    /* sw overflow counter */
+        __u32   comm_error;     /* frame/parity error counter */
+        __u32 ichar;
+        __u32 filler[7];
 };
 
 
@@ -435,18 +434,18 @@ struct CH_CTRL {
  */
 
 struct  BUF_CTRL        {
-        uclong  flag_dma;       /* buffers are in Host memory */
-        uclong  tx_bufaddr;     /* address of the tx buffer */
-        uclong  tx_bufsize;     /* tx buffer size */
-        uclong  tx_threshold;   /* tx low water mark */
-        uclong  tx_get;         /* tail index tx buf */
-        uclong  tx_put;         /* head index tx buf */
-        uclong  rx_bufaddr;     /* address of the rx buffer */
-        uclong  rx_bufsize;     /* rx buffer size */
-        uclong  rx_threshold;   /* rx high water mark */
-        uclong  rx_get;         /* tail index rx buf */
-        uclong  rx_put;         /* head index rx buf */
-        uclong  filler[5];      /* filler to align structures */
+        __u32   flag_dma;       /* buffers are in Host memory */
+        __u32   tx_bufaddr;     /* address of the tx buffer */
+        __u32   tx_bufsize;     /* tx buffer size */
+        __u32   tx_threshold;   /* tx low water mark */
+        __u32   tx_get;         /* tail index tx buf */
+        __u32   tx_put;         /* head index tx buf */
+        __u32   rx_bufaddr;     /* address of the rx buffer */
+        __u32   rx_bufsize;     /* rx buffer size */
+        __u32   rx_threshold;   /* rx high water mark */
+        __u32   rx_get;         /* tail index rx buf */
+        __u32   rx_put;         /* head index rx buf */
+        __u32   filler[5];      /* filler to align structures */
 };
 
 /*
@@ -457,27 +456,27 @@ struct	BUF_CTRL	{
 struct BOARD_CTRL {
 
         /* static info provided by the on-board CPU */
-        uclong  n_channel;      /* number of channels */
-        uclong  fw_version;     /* firmware version */
+        __u32   n_channel;      /* number of channels */
+        __u32   fw_version;     /* firmware version */
 
         /* static info provided by the driver */
-        uclong  op_system;      /* op_system id */
-        uclong  dr_version;     /* driver version */
+        __u32   op_system;      /* op_system id */
+        __u32   dr_version;     /* driver version */
 
         /* board control area */
-        uclong  inactivity;     /* inactivity control */
+        __u32   inactivity;     /* inactivity control */
 
         /* host to FW commands */
-        uclong  hcmd_channel;   /* channel number */
-        uclong  hcmd_param;     /* pointer to parameters */
+        __u32   hcmd_channel;   /* channel number */
+        __u32   hcmd_param;     /* pointer to parameters */
 
         /* FW to Host commands */
-        uclong  fwcmd_channel;  /* channel number */
-        uclong  fwcmd_param;    /* pointer to parameters */
-        uclong  zf_int_queue_addr; /* offset for INT_QUEUE structure */
+        __u32   fwcmd_channel;  /* channel number */
+        __u32   fwcmd_param;    /* pointer to parameters */
+        __u32   zf_int_queue_addr; /* offset for INT_QUEUE structure */
 
         /* filler so the structures are aligned */
-        uclong  filler[6];
+        __u32   filler[6];
 };
 
 /* Host Interrupt Queue */
@@ -506,11 +505,10 @@ struct ZFW_CTRL {
 /****************** ****************** *******************/
 #endif
 
+#ifdef __KERNEL__
+
 /* Per card data structure */
-struct resource;
 struct cyclades_card {
-    unsigned long base_phys;
-    unsigned long ctl_phys;
     void __iomem *base_addr;
     void __iomem *ctl_addr;
     int irq;
@@ -519,33 +517,18 @@ struct cyclades_card {
     int nports;         /* Number of ports in the card */
     int bus_index;      /* address shift - 0 for ISA, 1 for PCI */
     int intr_enabled;   /* FW Interrupt flag - 0 disabled, 1 enabled */
-    struct pci_dev *pdev;
-#ifdef __KERNEL__
     spinlock_t card_lock;
-#else
-    unsigned long filler;
-#endif
+    struct cyclades_port *ports;
 };
 
-struct cyclades_chip {
-  int filler;
-};
-
-
-#ifdef __KERNEL__
-
 /***************************************
  * Memory access functions/macros      *
  * (required to support Alpha systems) *
  ***************************************/
 
-#define cy_writeb(port,val)     {writeb((val),(port)); mb();}
-#define cy_writew(port,val)     {writew((val),(port)); mb();}
-#define cy_writel(port,val)     {writel((val),(port)); mb();}
-
-#define cy_readb(port)  readb(port)
-#define cy_readw(port)  readw(port)
-#define cy_readl(port)  readl(port)
+#define cy_writeb(port,val)     do { writeb((val), (port)); mb(); } while (0)
+#define cy_writew(port,val)     do { writew((val), (port)); mb(); } while (0)
+#define cy_writel(port,val)     do { writel((val), (port)); mb(); } while (0)
 
 /*
  * Statistics counters
@@ -567,7 +550,7 @@ struct cyclades_icount {
 
 struct cyclades_port {
         int                     magic;
-        int                     card;
+        struct cyclades_card    *card;
         int                     line;
         int                     flags;          /* defined in tty.h */
         int                     type;           /* UART type */
@@ -587,7 +570,6 @@ struct cyclades_port {
         int                     close_delay;
         unsigned short          closing_wait;
         unsigned long           event;
-        unsigned long           last_active;
         int                     count;  /* # of fd on device */
         int                     breakon;
         int                     breakoff;
@@ -598,7 +580,6 @@ struct cyclades_port {
         int                     xmit_cnt;
         int                     default_threshold;
         int                     default_timeout;
-        unsigned long           jiffies[3];
         unsigned long           rflush_count;
         struct cyclades_monitor mon;
         struct cyclades_idle_stats      idle_stats;
@@ -606,7 +587,7 @@ struct cyclades_port {
         struct work_struct      tqueue;
         wait_queue_head_t       open_wait;
         wait_queue_head_t       close_wait;
-        wait_queue_head_t       shutdown_wait;
+        struct completion       shutdown_wait;
         wait_queue_head_t       delta_msr_wait;
         int throttle;
 };
diff --git a/include/linux/dcache.h b/include/linux/dcache.h
index 63f64a9a5bf7..aab53df4fafa 100644
--- a/include/linux/dcache.h
+++ b/include/linux/dcache.h
@@ -133,6 +133,7 @@ struct dentry_operations {
         int (*d_delete)(struct dentry *);
         void (*d_release)(struct dentry *);
         void (*d_iput)(struct dentry *, struct inode *);
+        char *(*d_dname)(struct dentry *, char *, int);
 };
 
 /* the dentry parameter passed to d_hash and d_compare is the parent
@@ -293,6 +294,11 @@ extern struct dentry * d_hash_and_lookup(struct dentry *, struct qstr *);
 /* validate "insecure" dentry pointer */
 extern int d_validate(struct dentry *, struct dentry *);
 
+/*
+ * helper function for dentry_operations.d_dname() members
+ */
+extern char *dynamic_dname(struct dentry *, char *, int, const char *, ...);
+
 extern char * d_path(struct dentry *, struct vfsmount *, char *, int);
   
 /* Allocation counts.. */
diff --git a/include/linux/device.h b/include/linux/device.h
index 6579068134d1..2e1a2988b7e1 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -412,12 +412,13 @@ struct device {
         struct klist_node       knode_parent;           /* node in sibling list */
         struct klist_node       knode_driver;
         struct klist_node       knode_bus;
-        struct device   * parent;
+        struct device           *parent;
 
         struct kobject kobj;
         char    bus_id[BUS_ID_SIZE];    /* position on parent bus */
         struct device_type      *type;
         unsigned                is_registered:1;
+        unsigned                uevent_suppress:1;
         struct device_attribute uevent_attr;
         struct device_attribute *devt_attr;
 
@@ -458,7 +459,6 @@ struct device {
         struct class            *class;
         dev_t                   devt;           /* dev_t, creates the sysfs "dev" */
         struct attribute_group  **groups;       /* optional groups */
-        int                     uevent_suppress;
 
         void    (*release)(struct device * dev);
 };
diff --git a/include/linux/display.h b/include/linux/display.h
new file mode 100644
index 000000000000..3bf70d639728
--- /dev/null
+++ b/include/linux/display.h
@@ -0,0 +1,61 @@
+/*
+ *  Copyright (C) 2006 James Simmons <jsimmons@infradead.org>
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or (at
+ *  your option) any later version.
+ *
+ *  This program is distributed in the hope that it will be useful, but
+ *  WITHOUT ANY WARRANTY; without even the implied warranty of
+ *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ *  General Public License for more details.
+ *
+ *  You should have received a copy of the GNU General Public License along
+ *  with this program; if not, write to the Free Software Foundation, Inc.,
+ *  59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
+ *
+ * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+ */
+
+#ifndef _LINUX_DISPLAY_H
+#define _LINUX_DISPLAY_H
+
+#include <linux/device.h>
+
+struct display_device;
+
+/* This structure defines all the properties of a Display. */
+struct display_driver {
+        int  (*set_contrast)(struct display_device *, unsigned int);
+        int  (*get_contrast)(struct display_device *);
+        void (*suspend)(struct display_device *, pm_message_t state);
+        void (*resume)(struct display_device *);
+        int  (*probe)(struct display_device *, void *);
+        int  (*remove)(struct display_device *);
+        int  max_contrast;
+};
+
+struct display_device {
+        struct module *owner;                   /* Owner module */
+        struct display_driver *driver;
+        struct device *parent;                  /* This is the parent */
+        struct device *dev;                     /* This is this display device */
+        struct mutex lock;
+        void *priv_data;
+        char type[16];
+        char *name;
+        int idx;
+};
+
+extern struct display_device *display_device_register(struct display_driver *driver,
+                                        struct device *dev, void *devdata);
+extern void display_device_unregister(struct display_device *dev);
+
+extern int probe_edid(struct display_device *dev, void *devdata);
+
+#define to_display_device(obj) container_of(obj, struct display_device, class_dev)
+
+#endif
diff --git a/include/linux/dlm_device.h b/include/linux/dlm_device.h
index 2a2dd189b9fd..c2735cab2ebf 100644
--- a/include/linux/dlm_device.h
+++ b/include/linux/dlm_device.h
@@ -19,7 +19,7 @@
 
 /* Version of the device interface */
 #define DLM_DEVICE_VERSION_MAJOR 5
-#define DLM_DEVICE_VERSION_MINOR 0
+#define DLM_DEVICE_VERSION_MINOR 1
 #define DLM_DEVICE_VERSION_PATCH 0
 
 /* struct passed to the lock write */
@@ -44,6 +44,11 @@ struct dlm_lspace_params {
         char name[0];
 };
 
+struct dlm_purge_params {
+        __u32 nodeid;
+        __u32 pid;
+};
+
 struct dlm_write_request {
         __u32 version[3];
         __u8 cmd;
@@ -53,6 +58,7 @@ struct dlm_write_request {
         union  {
                 struct dlm_lock_params   lock;
                 struct dlm_lspace_params lspace;
+                struct dlm_purge_params  purge;
         } i;
 };
 
@@ -76,6 +82,7 @@ struct dlm_lock_result {
 #define DLM_USER_QUERY        3
 #define DLM_USER_CREATE_LOCKSPACE  4
 #define DLM_USER_REMOVE_LOCKSPACE  5
+#define DLM_USER_PURGE        6
 
 /* Arbitrary length restriction */
 #define MAX_LS_NAME_LEN 64
diff --git a/include/linux/ds1wm.h b/include/linux/ds1wm.h
new file mode 100644
index 000000000000..31f6e3c427fb
--- /dev/null
+++ b/include/linux/ds1wm.h
@@ -0,0 +1,11 @@
+/* platform data for the DS1WM driver */
+
+struct ds1wm_platform_data {
+        int bus_shift;      /* number of shifts needed to calculate the
+                             * offset between DS1WM registers;
+                             * e.g. on h5xxx and h2200 this is 2
+                             * (registers aligned to 4-byte boundaries),
+                             * while on hx4700 this is 1 */
+        void (*enable)(struct platform_device *pdev);
+        void (*disable)(struct platform_device *pdev);
+};
diff --git a/include/linux/efi.h b/include/linux/efi.h
index f8ebd7c1ddb3..0b9579a4cd42 100644
--- a/include/linux/efi.h
+++ b/include/linux/efi.h
@@ -213,7 +213,6 @@ typedef struct {
 } efi_config_table_t;
 
 #define EFI_SYSTEM_TABLE_SIGNATURE ((u64)0x5453595320494249ULL)
-#define EFI_SYSTEM_TABLE_REVISION  ((1 << 16) | 00)
 
 typedef struct {
         efi_table_hdr_t hdr;
diff --git a/include/linux/elf-em.h b/include/linux/elf-em.h
index 666e0a5f00fc..0311bad838b1 100644
--- a/include/linux/elf-em.h
+++ b/include/linux/elf-em.h
@@ -30,6 +30,7 @@
 #define EM_V850         87      /* NEC v850 */
 #define EM_M32R         88      /* Renesas M32R */
 #define EM_H8_300       46      /* Renesas H8/300,300H,H8S */
+#define EM_BLACKFIN     106     /* ADI Blackfin Processor */
 #define EM_FRV          0x5441  /* Fujitsu FR-V */
 #define EM_AVR32        0x18ad  /* Atmel AVR32 */
 
diff --git a/include/linux/etherdevice.h b/include/linux/etherdevice.h
index 745c988359c0..071c67abed86 100644
--- a/include/linux/etherdevice.h
+++ b/include/linux/etherdevice.h
@@ -71,6 +71,18 @@ static inline int is_multicast_ether_addr(const u8 *addr)
 }
 
 /**
+ * is_local_ether_addr - Determine if the Ethernet address is locally-assigned
+ * one (IEEE 802).
+ * @addr: Pointer to a six-byte array containing the Ethernet address
+ *
+ * Return true if the address is a local address.
+ */
+static inline int is_local_ether_addr(const u8 *addr)
+{
+        return (0x02 & addr[0]);
+}
+
+/**
  * is_broadcast_ether_addr - Determine if the Ethernet address is broadcast
  * @addr: Pointer to a six-byte array containing the Ethernet address
  *
diff --git a/include/linux/ext3_fs.h b/include/linux/ext3_fs.h
index 4eb18ac510ae..ece49a804fe1 100644
--- a/include/linux/ext3_fs.h
+++ b/include/linux/ext3_fs.h
@@ -824,6 +824,7 @@ extern int ext3_change_inode_journal_flag(struct inode *, int);
 extern int ext3_get_inode_loc(struct inode *, struct ext3_iloc *);
 extern void ext3_truncate (struct inode *);
 extern void ext3_set_inode_flags(struct inode *);
+extern void ext3_get_inode_flags(struct ext3_inode_info *);
 extern void ext3_set_aops(struct inode *inode);
 
 /* ioctl.c */
diff --git a/include/linux/fb.h b/include/linux/fb.h
index be913ec87169..dff7a728948c 100644
--- a/include/linux/fb.h
+++ b/include/linux/fb.h
@@ -4,6 +4,8 @@
 #include <asm/types.h>
 #include <linux/i2c.h>
 
+struct dentry;
+
 /* Definitions of frame buffers                                         */
 
 #define FB_MAJOR                29
@@ -525,12 +527,20 @@ struct fb_cursor_user {
 #define FB_EVENT_MODE_CHANGE_ALL        0x0B
 /*      A software display blank change occured */
 #define FB_EVENT_CONBLANK               0x0C
+/*      Get drawing requirements        */
+#define FB_EVENT_GET_REQ                0x0D
 
 struct fb_event {
         struct fb_info *info;
         void *data;
 };
 
+struct fb_blit_caps {
+        u32 x;
+        u32 y;
+        u32 len;
+        u32 flags;
+};
 
 extern int fb_register_client(struct notifier_block *nb);
 extern int fb_unregister_client(struct notifier_block *nb);
@@ -556,11 +566,25 @@ struct fb_pixmap {
         u32 scan_align;         /* alignment per scanline               */
         u32 access_align;       /* alignment per read/write (bits)      */
         u32 flags;              /* see FB_PIXMAP_*                      */
+        u32 blit_x;             /* supported bit block dimensions (1-32)*/
+        u32 blit_y;             /* Format: blit_x = 1 << (width - 1)    */
+                                /*         blit_y = 1 << (height - 1)   */
+                                /* if 0, will be set to 0xffffffff (all)*/
         /* access methods */
         void (*writeio)(struct fb_info *info, void __iomem *dst, void *src, unsigned int size);
         void (*readio) (struct fb_info *info, void *dst, void __iomem *src, unsigned int size);
 };
 
+#ifdef CONFIG_FB_DEFERRED_IO
+struct fb_deferred_io {
+        /* delay between mkwrite and deferred handler */
+        unsigned long delay;
+        struct mutex lock; /* mutex that protects the page list */
+        struct list_head pagelist; /* list of touched pages */
+        /* callback */
+        void (*deferred_io)(struct fb_info *info, struct list_head *pagelist);
+};
+#endif
 
 /*
  * Frame buffer operations
@@ -579,8 +603,10 @@ struct fb_ops {
         /* For framebuffers with strange non linear layouts or that do not
          * work with normal memory mapped access
          */
-        ssize_t (*fb_read)(struct file *file, char __user *buf, size_t count, loff_t *ppos);
-        ssize_t (*fb_write)(struct file *file, const char __user *buf, size_t count, loff_t *ppos);
+        ssize_t (*fb_read)(struct fb_info *info, char __user *buf,
+                           size_t count, loff_t *ppos);
+        ssize_t (*fb_write)(struct fb_info *info, const char __user *buf,
+                            size_t count, loff_t *ppos);
 
         /* checks var and eventually tweaks it to something supported,
          * DO NOT MODIFY PAR */
@@ -634,10 +660,13 @@ struct fb_ops {
 
         /* restore saved state */
         void (*fb_restore_state)(struct fb_info *info);
+
+        /* get capability given var */
+        void (*fb_get_caps)(struct fb_info *info, struct fb_blit_caps *caps,
+                            struct fb_var_screeninfo *var);
 };
 
 #ifdef CONFIG_FB_TILEBLITTING
-
 #define FB_TILE_CURSOR_NONE        0
 #define FB_TILE_CURSOR_UNDERLINE   1
 #define FB_TILE_CURSOR_LOWER_THIRD 2
@@ -709,6 +738,8 @@ struct fb_tile_ops {
         /* cursor */
         void (*fb_tilecursor)(struct fb_info *info,
                               struct fb_tilecursor *cursor);
+        /* get maximum length of the tile map */
+        int (*fb_get_tilemax)(struct fb_info *info);
 };
 #endif /* CONFIG_FB_TILEBLITTING */
 
@@ -778,6 +809,10 @@ struct fb_info {
         struct mutex bl_curve_mutex;    
         u8 bl_curve[FB_BACKLIGHT_LEVELS];
 #endif
+#ifdef CONFIG_FB_DEFERRED_IO
+        struct delayed_work deferred_work;
+        struct fb_deferred_io *fbdefio;
+#endif
 
         struct fb_ops *fbops;
         struct device *device;          /* This is the parent */
@@ -879,6 +914,16 @@ extern int fb_blank(struct fb_info *info, int blank);
 extern void cfb_fillrect(struct fb_info *info, const struct fb_fillrect *rect); 
 extern void cfb_copyarea(struct fb_info *info, const struct fb_copyarea *area); 
 extern void cfb_imageblit(struct fb_info *info, const struct fb_image *image);
+/*
+ * Drawing operations where framebuffer is in system RAM
+ */
+extern void sys_fillrect(struct fb_info *info, const struct fb_fillrect *rect);
+extern void sys_copyarea(struct fb_info *info, const struct fb_copyarea *area);
+extern void sys_imageblit(struct fb_info *info, const struct fb_image *image);
+extern ssize_t fb_sys_read(struct fb_info *info, char __user *buf,
+                           size_t count, loff_t *ppos);
+extern ssize_t fb_sys_write(struct fb_info *info, const char __user *buf,
+                            size_t count, loff_t *ppos);
 
 /* drivers/video/fbmem.c */
 extern int register_framebuffer(struct fb_info *fb_info);
@@ -913,6 +958,12 @@ static inline void __fb_pad_aligned_buffer(u8 *dst, u32 d_pitch,
         }
 }
 
+/* drivers/video/fb_defio.c */
+extern void fb_deferred_io_init(struct fb_info *info);
+extern void fb_deferred_io_cleanup(struct fb_info *info);
+extern int fb_deferred_io_fsync(struct file *file, struct dentry *dentry,
+                                int datasync);
+
 /* drivers/video/fbsysfs.c */
 extern struct fb_info *framebuffer_alloc(size_t size, struct device *dev);
 extern void framebuffer_release(struct fb_info *info);
diff --git a/include/linux/fcntl.h b/include/linux/fcntl.h
index 996f5611cd59..40b93265d4ba 100644
--- a/include/linux/fcntl.h
+++ b/include/linux/fcntl.h
@@ -3,6 +3,10 @@
 
 #include <asm/fcntl.h>
 
+/* Cancel a blocking posix lock; internal use only until we expose an
+ * asynchronous lock api to userspace: */
+#define F_CANCELLK      (F_LINUX_SPECIFIC_BASE+5)
+
 #define F_SETLEASE      (F_LINUX_SPECIFIC_BASE+0)
 #define F_GETLEASE      (F_LINUX_SPECIFIC_BASE+1)
 
diff --git a/include/linux/font.h b/include/linux/font.h
index 53b129f07f6f..40a24ab41b36 100644
--- a/include/linux/font.h
+++ b/include/linux/font.h
@@ -49,7 +49,8 @@ extern const struct font_desc *find_font(const char *name);
 
 /* Get the default font for a specific screen size */
 
-extern const struct font_desc *get_default_font(int xres, int yres);
+extern const struct font_desc *get_default_font(int xres, int yres,
+                                                u32 font_w, u32 font_h);
 
 /* Max. length for the name of a predefined font */
 #define MAX_FONT_NAME   32
diff --git a/include/linux/fs.h b/include/linux/fs.h
index 7c0077f06e24..7cf0c54a46a7 100644
--- a/include/linux/fs.h
+++ b/include/linux/fs.h
@@ -30,6 +30,7 @@
 #define SEEK_SET        0       /* seek relative to beginning of file */
 #define SEEK_CUR        1       /* seek relative to current file position */
 #define SEEK_END        2       /* seek relative to end of file */
+#define SEEK_MAX        SEEK_END
 
 /* And dynamically-tunable limits and defaults: */
 struct files_stat_struct {
@@ -91,6 +92,7 @@ extern int dir_notify_enable;
 /* public flags for file_system_type */
 #define FS_REQUIRES_DEV 1 
 #define FS_BINARY_MOUNTDATA 2
+#define FS_HAS_SUBTYPE 4
 #define FS_REVAL_DOT    16384   /* Check the paths ".", ".." for staleness */
 #define FS_RENAME_DOES_D_MOVE   32768   /* FS will handle d_move()
                                          * during rename() internally.
@@ -696,12 +698,13 @@ struct file_ra_state {
         unsigned long size;
         unsigned long flags;            /* ra flags RA_FLAG_xxx*/
         unsigned long cache_hit;        /* cache hit count*/
-        unsigned long prev_page;        /* Cache last read() position */
+        unsigned long prev_index;       /* Cache last read() position */
         unsigned long ahead_start;      /* Ahead window */
         unsigned long ahead_size;
         unsigned long ra_pages;         /* Maximum readahead window */
         unsigned long mmap_hit;         /* Cache hit stat for mmap accesses */
         unsigned long mmap_miss;        /* Cache miss stat for mmap accesses */
+        unsigned int prev_offset;       /* Offset where last read() ended in a page */
 };
 #define RA_FLAG_MISS 0x01       /* a cache miss occured against this file */
 #define RA_FLAG_INCACHE 0x02    /* file is already in cache */
@@ -785,6 +788,7 @@ struct file_lock_operations {
 struct lock_manager_operations {
         int (*fl_compare_owner)(struct file_lock *, struct file_lock *);
         void (*fl_notify)(struct file_lock *);  /* unblock callback */
+        int (*fl_grant)(struct file_lock *, struct file_lock *, int);
         void (*fl_copy_lock)(struct file_lock *, struct file_lock *);
         void (*fl_release_private)(struct file_lock *);
         void (*fl_break)(struct file_lock *);
@@ -845,22 +849,19 @@ extern int fcntl_getlease(struct file *filp);
 /* fs/sync.c */
 extern int do_sync_mapping_range(struct address_space *mapping, loff_t offset,
                         loff_t endbyte, unsigned int flags);
-static inline int do_sync_file_range(struct file *file, loff_t offset,
-                        loff_t endbyte, unsigned int flags)
-{
-        return do_sync_mapping_range(file->f_mapping, offset, endbyte, flags);
-}
 
 /* fs/locks.c */
 extern void locks_init_lock(struct file_lock *);
 extern void locks_copy_lock(struct file_lock *, struct file_lock *);
 extern void locks_remove_posix(struct file *, fl_owner_t);
 extern void locks_remove_flock(struct file *);
-extern int posix_test_lock(struct file *, struct file_lock *, struct file_lock *);
-extern int posix_lock_file_conf(struct file *, struct file_lock *, struct file_lock *);
-extern int posix_lock_file(struct file *, struct file_lock *);
+extern int posix_test_lock(struct file *, struct file_lock *);
+extern int posix_lock_file(struct file *, struct file_lock *, struct file_lock *);
 extern int posix_lock_file_wait(struct file *, struct file_lock *);
 extern int posix_unblock_lock(struct file *, struct file_lock *);
+extern int vfs_test_lock(struct file *, struct file_lock *);
+extern int vfs_lock_file(struct file *, unsigned int, struct file_lock *, struct file_lock *);
+extern int vfs_cancel_lock(struct file *filp, struct file_lock *fl);
 extern int flock_lock_file_wait(struct file *filp, struct file_lock *fl);
 extern int __break_lease(struct inode *inode, unsigned int flags);
 extern void lease_get_mtime(struct inode *, struct timespec *time);
@@ -956,6 +957,12 @@ struct super_block {
         /* Granularity of c/m/atime in ns.
            Cannot be worse than a second */
         u32                s_time_gran;
+
+        /*
+         * Filesystem subtype.  If non-empty the filesystem type field
+         * in /proc/mounts will be "type.subtype"
+         */
+        char *s_subtype;
 };
 
 extern struct timespec current_fs_time(struct super_block *sb);
@@ -1731,6 +1738,8 @@ extern ssize_t generic_file_sendfile(struct file *, loff_t *, size_t, read_actor
 extern void do_generic_mapping_read(struct address_space *mapping,
                                     struct file_ra_state *, struct file *,
                                     loff_t *, read_descriptor_t *, read_actor_t);
+extern int generic_segment_checks(const struct iovec *iov,
+                unsigned long *nr_segs, size_t *count, int access_flags);
 
 /* fs/splice.c */
 extern ssize_t generic_file_splice_read(struct file *, loff_t *,
diff --git a/include/linux/futex.h b/include/linux/futex.h
index 3f153b4e156c..820125c628c1 100644
--- a/include/linux/futex.h
+++ b/include/linux/futex.h
@@ -100,6 +100,35 @@ long do_futex(u32 __user *uaddr, int op, u32 val, unsigned long timeout,
 extern int
 handle_futex_death(u32 __user *uaddr, struct task_struct *curr, int pi);
 
+/*
+ * Futexes are matched on equal values of this key.
+ * The key type depends on whether it's a shared or private mapping.
+ * Don't rearrange members without looking at hash_futex().
+ *
+ * offset is aligned to a multiple of sizeof(u32) (== 4) by definition.
+ * We set bit 0 to indicate if it's an inode-based key.
+ */
+union futex_key {
+        struct {
+                unsigned long pgoff;
+                struct inode *inode;
+                int offset;
+        } shared;
+        struct {
+                unsigned long address;
+                struct mm_struct *mm;
+                int offset;
+        } private;
+        struct {
+                unsigned long word;
+                void *ptr;
+                int offset;
+        } both;
+};
+int get_futex_key(u32 __user *uaddr, union futex_key *key);
+void get_futex_key_refs(union futex_key *key);
+void drop_futex_key_refs(union futex_key *key);
+
 #ifdef CONFIG_FUTEX
 extern void exit_robust_list(struct task_struct *curr);
 extern void exit_pi_state_list(struct task_struct *curr);
diff --git a/include/linux/gfp.h b/include/linux/gfp.h
index 2a7d15bcde46..97a36c3d96e2 100644
--- a/include/linux/gfp.h
+++ b/include/linux/gfp.h
@@ -40,7 +40,6 @@ struct vm_area_struct;
 #define __GFP_REPEAT    ((__force gfp_t)0x400u) /* Retry the allocation.  Might fail */
 #define __GFP_NOFAIL    ((__force gfp_t)0x800u) /* Retry for ever.  Cannot fail */
 #define __GFP_NORETRY   ((__force gfp_t)0x1000u)/* Do not retry.  Might fail */
-#define __GFP_NO_GROW   ((__force gfp_t)0x2000u)/* Slab internal usage */
 #define __GFP_COMP      ((__force gfp_t)0x4000u)/* Add compound page metadata */
 #define __GFP_ZERO      ((__force gfp_t)0x8000u)/* Return zeroed page on success */
 #define __GFP_NOMEMALLOC ((__force gfp_t)0x10000u) /* Don't use emergency reserves */
@@ -53,7 +52,7 @@ struct vm_area_struct;
 /* if you forget to add the bitmask here kernel will crash, period */
 #define GFP_LEVEL_MASK (__GFP_WAIT|__GFP_HIGH|__GFP_IO|__GFP_FS| \
                         __GFP_COLD|__GFP_NOWARN|__GFP_REPEAT| \
-                        __GFP_NOFAIL|__GFP_NORETRY|__GFP_NO_GROW|__GFP_COMP| \
+                        __GFP_NOFAIL|__GFP_NORETRY|__GFP_COMP| \
                         __GFP_NOMEMALLOC|__GFP_HARDWALL|__GFP_THISNODE)
 
 /* This equals 0, but use constants in case they ever change */
diff --git a/include/linux/hugetlb.h b/include/linux/hugetlb.h
index 3f3e7a648da3..b4570b62ab85 100644
--- a/include/linux/hugetlb.h
+++ b/include/linux/hugetlb.h
@@ -189,4 +189,10 @@ static inline void set_file_hugepages(struct file *file)
 
 #endif /* !CONFIG_HUGETLBFS */
 
+#ifdef HAVE_ARCH_HUGETLB_UNMAPPED_AREA
+unsigned long hugetlb_get_unmapped_area(struct file *file, unsigned long addr,
+                                        unsigned long len, unsigned long pgoff,
+                                        unsigned long flags);
+#endif /* HAVE_ARCH_HUGETLB_UNMAPPED_AREA */
+
 #endif /* _LINUX_HUGETLB_H */
diff --git a/include/linux/init.h b/include/linux/init.h
index 9abf120ec9f8..8bc32bb2fce2 100644
--- a/include/linux/init.h
+++ b/include/linux/init.h
@@ -77,7 +77,8 @@ extern char *saved_command_line;
 extern unsigned int reset_devices;
 
 /* used by init/main.c */
-extern void setup_arch(char **);
+void setup_arch(char **);
+void prepare_namespace(void);
 
 #endif
   
@@ -233,7 +234,7 @@ void __init parse_early_param(void);
 #define __obsolete_setup(str)                   /* nothing */
 #endif
 
-/* Data marked not to be saved by software_suspend() */
+/* Data marked not to be saved by software suspend */
 #define __nosavedata __attribute__ ((__section__ (".data.nosave")))
 
 /* This means "can be init if no module support, otherwise module load
diff --git a/include/linux/init_task.h b/include/linux/init_task.h
index a2d95ff50e9b..795102309bf1 100644
--- a/include/linux/init_task.h
+++ b/include/linux/init_task.h
@@ -138,7 +138,7 @@ extern struct group_info init_groups;
         .journal_info   = NULL,                                         \
         .cpu_timers     = INIT_CPU_TIMERS(tsk.cpu_timers),              \
         .fs_excl        = ATOMIC_INIT(0),                               \
-        .pi_lock        = SPIN_LOCK_UNLOCKED,                           \
+        .pi_lock        = __SPIN_LOCK_UNLOCKED(tsk.pi_lock),            \
         INIT_TRACE_IRQFLAGS                                             \
         INIT_LOCKDEP                                                    \
 }
diff --git a/include/linux/input.h b/include/linux/input.h
index 439954d09752..be2bf3a2b031 100644
--- a/include/linux/input.h
+++ b/include/linux/input.h
@@ -990,6 +990,10 @@ struct input_dev {
 #error "EV_MAX and INPUT_DEVICE_ID_EV_MAX do not match"
 #endif
 
+#if KEY_MIN_INTERESTING != INPUT_DEVICE_ID_KEY_MIN_INTERESTING
+#error "KEY_MIN_INTERESTING and INPUT_DEVICE_ID_KEY_MIN_INTERESTING do not match"
+#endif
+
 #if KEY_MAX != INPUT_DEVICE_ID_KEY_MAX
 #error "KEY_MAX and INPUT_DEVICE_ID_KEY_MAX do not match"
 #endif
diff --git a/include/linux/interrupt.h b/include/linux/interrupt.h
index 0319f665dd3f..f7b01b9a35b3 100644
--- a/include/linux/interrupt.h
+++ b/include/linux/interrupt.h
@@ -44,6 +44,9 @@
  * IRQF_TIMER - Flag to mark this interrupt as timer interrupt
  * IRQF_PERCPU - Interrupt is per cpu
  * IRQF_NOBALANCING - Flag to exclude this interrupt from irq balancing
+ * IRQF_IRQPOLL - Interrupt is used for polling (only the interrupt that is
+ *                registered first in an shared interrupt is considered for
+ *                performance reasons)
  */
 #define IRQF_DISABLED           0x00000020
 #define IRQF_SAMPLE_RANDOM      0x00000040
@@ -52,22 +55,29 @@
 #define IRQF_TIMER              0x00000200
 #define IRQF_PERCPU             0x00000400
 #define IRQF_NOBALANCING        0x00000800
+#define IRQF_IRQPOLL            0x00001000
 
 /*
- * Migration helpers. Scheduled for removal in 1/2007
+ * Migration helpers. Scheduled for removal in 9/2007
  * Do not use for new code !
  */
-#define SA_INTERRUPT            IRQF_DISABLED
-#define SA_SAMPLE_RANDOM        IRQF_SAMPLE_RANDOM
-#define SA_SHIRQ                IRQF_SHARED
-#define SA_PROBEIRQ             IRQF_PROBE_SHARED
-#define SA_PERCPU               IRQF_PERCPU
-
-#define SA_TRIGGER_LOW          IRQF_TRIGGER_LOW
-#define SA_TRIGGER_HIGH         IRQF_TRIGGER_HIGH
-#define SA_TRIGGER_FALLING      IRQF_TRIGGER_FALLING
-#define SA_TRIGGER_RISING       IRQF_TRIGGER_RISING
-#define SA_TRIGGER_MASK         IRQF_TRIGGER_MASK
+static inline
+unsigned long __deprecated deprecated_irq_flag(unsigned long flag)
+{
+        return flag;
+}
+
+#define SA_INTERRUPT            deprecated_irq_flag(IRQF_DISABLED)
+#define SA_SAMPLE_RANDOM        deprecated_irq_flag(IRQF_SAMPLE_RANDOM)
+#define SA_SHIRQ                deprecated_irq_flag(IRQF_SHARED)
+#define SA_PROBEIRQ             deprecated_irq_flag(IRQF_PROBE_SHARED)
+#define SA_PERCPU               deprecated_irq_flag(IRQF_PERCPU)
+
+#define SA_TRIGGER_LOW          deprecated_irq_flag(IRQF_TRIGGER_LOW)
+#define SA_TRIGGER_HIGH         deprecated_irq_flag(IRQF_TRIGGER_HIGH)
+#define SA_TRIGGER_FALLING      deprecated_irq_flag(IRQF_TRIGGER_FALLING)
+#define SA_TRIGGER_RISING       deprecated_irq_flag(IRQF_TRIGGER_RISING)
+#define SA_TRIGGER_MASK         deprecated_irq_flag(IRQF_TRIGGER_MASK)
 
 typedef irqreturn_t (*irq_handler_t)(int, void *);
 
@@ -83,11 +93,11 @@ struct irqaction {
 };
 
 extern irqreturn_t no_action(int cpl, void *dev_id);
-extern int request_irq(unsigned int, irq_handler_t handler,
+extern int __must_check request_irq(unsigned int, irq_handler_t handler,
                        unsigned long, const char *, void *);
 extern void free_irq(unsigned int, void *);
 
-extern int devm_request_irq(struct device *dev, unsigned int irq,
+extern int __must_check devm_request_irq(struct device *dev, unsigned int irq,
                             irq_handler_t handler, unsigned long irqflags,
                             const char *devname, void *dev_id);
 extern void devm_free_irq(struct device *dev, unsigned int irq, void *dev_id);
diff --git a/include/linux/ioctl32.h b/include/linux/ioctl32.h
deleted file mode 100644
index 948809d99917..000000000000
--- a/include/linux/ioctl32.h
+++ /dev/null
@@ -1,17 +0,0 @@
-#ifndef IOCTL32_H
-#define IOCTL32_H 1
-
-#include <linux/compiler.h>     /* for __deprecated */
-
-struct file;
-
-typedef int (*ioctl_trans_handler_t)(unsigned int, unsigned int,
-                                        unsigned long, struct file *);
-
-struct ioctl_trans {
-        unsigned long cmd;
-        ioctl_trans_handler_t handler;
-        struct ioctl_trans *next;
-};
-
-#endif
diff --git a/include/linux/ipc.h b/include/linux/ipc.h
index 6da6772c19ff..1980867a64a4 100644
--- a/include/linux/ipc.h
+++ b/include/linux/ipc.h
@@ -92,16 +92,19 @@ extern struct ipc_namespace init_ipc_ns;
 
 #ifdef CONFIG_SYSVIPC
 #define INIT_IPC_NS(ns)         .ns             = &init_ipc_ns,
-extern int copy_ipcs(unsigned long flags, struct task_struct *tsk);
+extern struct ipc_namespace *copy_ipcs(unsigned long flags,
+                                                struct ipc_namespace *ns);
 #else
 #define INIT_IPC_NS(ns)
-static inline int copy_ipcs(unsigned long flags, struct task_struct *tsk)
-{ return 0; }
+static inline struct ipc_namespace *copy_ipcs(unsigned long flags,
+                                                struct ipc_namespace *ns)
+{
+        return ns;
+}
 #endif
 
 #ifdef CONFIG_IPC_NS
 extern void free_ipc_ns(struct kref *kref);
-extern int unshare_ipcs(unsigned long flags, struct ipc_namespace **ns);
 #endif
 
 static inline struct ipc_namespace *get_ipc_ns(struct ipc_namespace *ns)
diff --git a/include/linux/irq.h b/include/linux/irq.h
index a6899402b522..1695054e8c63 100644
--- a/include/linux/irq.h
+++ b/include/linux/irq.h
@@ -147,8 +147,6 @@ struct irq_chip {
  * @dir:                /proc/irq/ procfs entry
  * @affinity_entry:     /proc/irq/smp_affinity procfs entry on SMP
  * @name:               flow handler name for /proc/interrupts output
- *
- * Pad this out to 32 bytes for cache and indexing reasons.
  */
 struct irq_desc {
         irq_flow_handler_t      handle_irq;
@@ -175,7 +173,7 @@ struct irq_desc {
         struct proc_dir_entry   *dir;
 #endif
         const char              *name;
-} ____cacheline_aligned;
+} ____cacheline_internodealigned_in_smp;
 
 extern struct irq_desc irq_desc[NR_IRQS];
 
diff --git a/include/linux/isdn/capiutil.h b/include/linux/isdn/capiutil.h
index 63bd9cf821a7..5a52f2c94f3f 100644
--- a/include/linux/isdn/capiutil.h
+++ b/include/linux/isdn/capiutil.h
@@ -187,7 +187,6 @@ typedef struct {
 #define CDEBUG_SIZE     1024
 #define CDEBUG_GSIZE    4096
 
-_cdebbuf *cdebbuf_alloc(void);
 void cdebbuf_free(_cdebbuf *cdb);
 int cdebug_init(void);
 void cdebug_exit(void);
diff --git a/include/linux/isdn_divertif.h b/include/linux/isdn_divertif.h
index 0e7e44ce8301..07821ca5955f 100644
--- a/include/linux/isdn_divertif.h
+++ b/include/linux/isdn_divertif.h
@@ -24,6 +24,10 @@
 #define DIVERT_REL_ERR  0x04  /* module not registered */
 #define DIVERT_REG_NAME isdn_register_divert
 
+#ifdef __KERNEL__
+#include <linux/isdnif.h>
+#include <linux/types.h>
+
 /***************************************************************/
 /* structure exchanging data between isdn hl and divert module */
 /***************************************************************/ 
@@ -40,3 +44,4 @@ typedef struct
 /* function register */
 /*********************/
 extern int DIVERT_REG_NAME(isdn_divert_if *);
+#endif
diff --git a/include/linux/kallsyms.h b/include/linux/kallsyms.h
index 3e3b92dabe3b..12178d2c882b 100644
--- a/include/linux/kallsyms.h
+++ b/include/linux/kallsyms.h
@@ -30,6 +30,9 @@ extern int sprint_symbol(char *buffer, unsigned long address);
 /* Look up a kernel symbol and print it to the kernel messages. */
 extern void __print_symbol(const char *fmt, unsigned long address);
 
+int lookup_symbol_name(unsigned long addr, char *symname);
+int lookup_symbol_attrs(unsigned long addr, unsigned long *size, unsigned long *offset, char *modname, char *name);
+
 #else /* !CONFIG_KALLSYMS */
 
 static inline unsigned long kallsyms_lookup_name(const char *name)
@@ -58,6 +61,16 @@ static inline int sprint_symbol(char *buffer, unsigned long addr)
         return 0;
 }
 
+static inline int lookup_symbol_name(unsigned long addr, char *symname)
+{
+        return -ERANGE;
+}
+
+static inline int lookup_symbol_attrs(unsigned long addr, unsigned long *size, unsigned long *offset, char *modname, char *name)
+{
+        return -ERANGE;
+}
+
 /* Stupid that this does nothing, but I didn't create this mess. */
 #define __print_symbol(fmt, addr)
 #endif /*CONFIG_KALLSYMS*/
diff --git a/include/linux/kdebug.h b/include/linux/kdebug.h
new file mode 100644
index 000000000000..5db38d6d8b92
--- /dev/null
+++ b/include/linux/kdebug.h
@@ -0,0 +1,20 @@
+#ifndef _LINUX_KDEBUG_H
+#define _LINUX_KDEBUG_H
+
+#include <asm/kdebug.h>
+
+struct die_args {
+        struct pt_regs *regs;
+        const char *str;
+        long err;
+        int trapnr;
+        int signr;
+};
+
+int register_die_notifier(struct notifier_block *nb);
+int unregister_die_notifier(struct notifier_block *nb);
+
+int notify_die(enum die_val val, const char *str,
+               struct pt_regs *regs, long err, int trap, int sig);
+
+#endif /* _LINUX_KDEBUG_H */
diff --git a/include/linux/kernel.h b/include/linux/kernel.h
index e2f41b051b12..144b615f3a89 100644
--- a/include/linux/kernel.h
+++ b/include/linux/kernel.h
@@ -35,7 +35,8 @@ extern const char linux_proc_banner[];
 #define ALIGN(x,a)              __ALIGN_MASK(x,(typeof(x))(a)-1)
 #define __ALIGN_MASK(x,mask)    (((x)+(mask))&~(mask))
 
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#define ARRAY_SIZE(arr) (sizeof(arr) / sizeof((arr)[0]) + __must_be_array(arr))
+
 #define FIELD_SIZEOF(t, f) (sizeof(((t*)0)->f))
 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
 #define roundup(x, y) ((((x) + ((y) - 1)) / (y)) * (y))
diff --git a/include/linux/kexec.h b/include/linux/kexec.h
index 696e5ec63f77..8c2c7fcd58ce 100644
--- a/include/linux/kexec.h
+++ b/include/linux/kexec.h
@@ -7,6 +7,8 @@
 #include <linux/linkage.h>
 #include <linux/compat.h>
 #include <linux/ioport.h>
+#include <linux/elfcore.h>
+#include <linux/elf.h>
 #include <asm/kexec.h>
 
 /* Verify architecture specific macros are defined */
@@ -31,6 +33,19 @@
 #error KEXEC_ARCH not defined
 #endif
 
+#define KEXEC_NOTE_HEAD_BYTES ALIGN(sizeof(struct elf_note), 4)
+#define KEXEC_CORE_NOTE_NAME "CORE"
+#define KEXEC_CORE_NOTE_NAME_BYTES ALIGN(sizeof(KEXEC_CORE_NOTE_NAME), 4)
+#define KEXEC_CORE_NOTE_DESC_BYTES ALIGN(sizeof(struct elf_prstatus), 4)
+/*
+ * The per-cpu notes area is a list of notes terminated by a "NULL"
+ * note header.  For kdump, the code in vmcore.c runs in the context
+ * of the second kernel to combine them into one note.
+ */
+#define KEXEC_NOTE_BYTES ( (KEXEC_NOTE_HEAD_BYTES * 2) +                \
+                            KEXEC_CORE_NOTE_NAME_BYTES +                \
+                            KEXEC_CORE_NOTE_DESC_BYTES )
+
 /*
  * This structure is used to hold the arguments that are used when loading
  * kernel binaries.
@@ -136,7 +151,7 @@ extern struct kimage *kexec_crash_image;
 /* Location of a reserved region to hold the crash kernel.
  */
 extern struct resource crashk_res;
-typedef u32 note_buf_t[MAX_NOTE_BYTES/4];
+typedef u32 note_buf_t[KEXEC_NOTE_BYTES/4];
 extern note_buf_t *crash_notes;
 
 
diff --git a/include/linux/kprobes.h b/include/linux/kprobes.h
index 769be39b9681..23adf6075ae4 100644
--- a/include/linux/kprobes.h
+++ b/include/linux/kprobes.h
@@ -78,7 +78,7 @@ struct kprobe {
         kprobe_opcode_t *addr;
 
         /* Allow user to indicate symbol name of the probe point */
-        char *symbol_name;
+        const char *symbol_name;
 
         /* Offset into the symbol */
         unsigned int offset;
@@ -123,12 +123,18 @@ DECLARE_PER_CPU(struct kprobe *, current_kprobe);
 DECLARE_PER_CPU(struct kprobe_ctlblk, kprobe_ctlblk);
 
 #ifdef ARCH_SUPPORTS_KRETPROBES
-extern void arch_prepare_kretprobe(struct kretprobe *rp, struct pt_regs *regs);
+extern void arch_prepare_kretprobe(struct kretprobe_instance *ri,
+                                   struct pt_regs *regs);
+extern int arch_trampoline_kprobe(struct kprobe *p);
 #else /* ARCH_SUPPORTS_KRETPROBES */
 static inline void arch_prepare_kretprobe(struct kretprobe *rp,
                                         struct pt_regs *regs)
 {
 }
+static inline int arch_trampoline_kprobe(struct kprobe *p)
+{
+        return 0;
+}
 #endif /* ARCH_SUPPORTS_KRETPROBES */
 /*
  * Function-return probe -
@@ -157,6 +163,16 @@ struct kretprobe_instance {
         struct task_struct *task;
 };
 
+static inline void kretprobe_assert(struct kretprobe_instance *ri,
+        unsigned long orig_ret_address, unsigned long trampoline_address)
+{
+        if (!orig_ret_address || (orig_ret_address == trampoline_address)) {
+                printk("kretprobe BUG!: Processing kretprobe %p @ %p\n",
+                                ri->rp, ri->rp->kp.addr);
+                BUG();
+        }
+}
+
 extern spinlock_t kretprobe_lock;
 extern struct mutex kprobe_mutex;
 extern int arch_prepare_kprobe(struct kprobe *p);
@@ -199,8 +215,6 @@ void jprobe_return(void);
 int register_kretprobe(struct kretprobe *rp);
 void unregister_kretprobe(struct kretprobe *rp);
 
-struct kretprobe_instance *get_free_rp_inst(struct kretprobe *rp);
-void add_rp_inst(struct kretprobe_instance *ri);
 void kprobe_flush_task(struct task_struct *tk);
 void recycle_rp_inst(struct kretprobe_instance *ri, struct hlist_head *head);
 #else /* CONFIG_KPROBES */
diff --git a/include/linux/kvm.h b/include/linux/kvm.h
index 275354ffa1cb..e6edca81ab84 100644
--- a/include/linux/kvm.h
+++ b/include/linux/kvm.h
@@ -11,7 +11,7 @@
 #include <asm/types.h>
 #include <linux/ioctl.h>
 
-#define KVM_API_VERSION 4
+#define KVM_API_VERSION 12
 
 /*
  * Architectural interrupt line count, and the size of the bitmap needed
@@ -33,37 +33,39 @@ struct kvm_memory_region {
 /* for kvm_memory_region::flags */
 #define KVM_MEM_LOG_DIRTY_PAGES  1UL
 
-
-#define KVM_EXIT_TYPE_FAIL_ENTRY 1
-#define KVM_EXIT_TYPE_VM_EXIT    2
+struct kvm_memory_alias {
+        __u32 slot;  /* this has a different namespace than memory slots */
+        __u32 flags;
+        __u64 guest_phys_addr;
+        __u64 memory_size;
+        __u64 target_phys_addr;
+};
 
 enum kvm_exit_reason {
         KVM_EXIT_UNKNOWN          = 0,
         KVM_EXIT_EXCEPTION        = 1,
         KVM_EXIT_IO               = 2,
-        KVM_EXIT_CPUID            = 3,
+        KVM_EXIT_HYPERCALL        = 3,
         KVM_EXIT_DEBUG            = 4,
         KVM_EXIT_HLT              = 5,
         KVM_EXIT_MMIO             = 6,
         KVM_EXIT_IRQ_WINDOW_OPEN  = 7,
         KVM_EXIT_SHUTDOWN         = 8,
+        KVM_EXIT_FAIL_ENTRY       = 9,
+        KVM_EXIT_INTR             = 10,
 };
 
-/* for KVM_RUN */
+/* for KVM_RUN, returned by mmap(vcpu_fd, offset=0) */
 struct kvm_run {
         /* in */
-        __u32 emulated;  /* skip current instruction */
-        __u32 mmio_completed; /* mmio request completed */
         __u8 request_interrupt_window;
         __u8 padding1[7];
 
         /* out */
-        __u32 exit_type;
         __u32 exit_reason;
-        __u32 instruction_length;
         __u8 ready_for_interrupt_injection;
         __u8 if_flag;
-        __u16 padding2;
+        __u8 padding2[2];
 
         /* in (pre_kvm_run), out (post_kvm_run) */
         __u64 cr8;
@@ -72,29 +74,26 @@ struct kvm_run {
         union {
                 /* KVM_EXIT_UNKNOWN */
                 struct {
-                        __u32 hardware_exit_reason;
+                        __u64 hardware_exit_reason;
                 } hw;
+                /* KVM_EXIT_FAIL_ENTRY */
+                struct {
+                        __u64 hardware_entry_failure_reason;
+                } fail_entry;
                 /* KVM_EXIT_EXCEPTION */
                 struct {
                         __u32 exception;
                         __u32 error_code;
                 } ex;
                 /* KVM_EXIT_IO */
-                struct {
+                struct kvm_io {
 #define KVM_EXIT_IO_IN  0
 #define KVM_EXIT_IO_OUT 1
                         __u8 direction;
                         __u8 size; /* bytes */
-                        __u8 string;
-                        __u8 string_down;
-                        __u8 rep;
-                        __u8 pad;
                         __u16 port;
-                        __u64 count;
-                        union {
-                                __u64 address;
-                                __u32 value;
-                        };
+                        __u32 count;
+                        __u64 data_offset; /* relative to kvm_run start */
                 } io;
                 struct {
                 } debug;
@@ -105,6 +104,13 @@ struct kvm_run {
                         __u32 len;
                         __u8  is_write;
                 } mmio;
+                /* KVM_EXIT_HYPERCALL */
+                struct {
+                        __u64 args[6];
+                        __u64 ret;
+                        __u32 longmode;
+                        __u32 pad;
+                } hypercall;
         };
 };
 
@@ -118,6 +124,21 @@ struct kvm_regs {
         __u64 rip, rflags;
 };
 
+/* for KVM_GET_FPU and KVM_SET_FPU */
+struct kvm_fpu {
+        __u8  fpr[8][16];
+        __u16 fcw;
+        __u16 fsw;
+        __u8  ftwx;  /* in fxsave format */
+        __u8  pad1;
+        __u16 last_opcode;
+        __u64 last_ip;
+        __u64 last_dp;
+        __u8  xmm[16][16];
+        __u32 mxcsr;
+        __u32 pad2;
+};
+
 struct kvm_segment {
         __u64 base;
         __u32 limit;
@@ -210,38 +231,74 @@ struct kvm_dirty_log {
         };
 };
 
+struct kvm_cpuid_entry {
+        __u32 function;
+        __u32 eax;
+        __u32 ebx;
+        __u32 ecx;
+        __u32 edx;
+        __u32 padding;
+};
+
+/* for KVM_SET_CPUID */
+struct kvm_cpuid {
+        __u32 nent;
+        __u32 padding;
+        struct kvm_cpuid_entry entries[0];
+};
+
+/* for KVM_SET_SIGNAL_MASK */
+struct kvm_signal_mask {
+        __u32 len;
+        __u8  sigset[0];
+};
+
 #define KVMIO 0xAE
 
 /*
  * ioctls for /dev/kvm fds:
  */
-#define KVM_GET_API_VERSION       _IO(KVMIO, 1)
-#define KVM_CREATE_VM             _IO(KVMIO, 2) /* returns a VM fd */
-#define KVM_GET_MSR_INDEX_LIST    _IOWR(KVMIO, 15, struct kvm_msr_list)
+#define KVM_GET_API_VERSION       _IO(KVMIO,   0x00)
+#define KVM_CREATE_VM             _IO(KVMIO,   0x01) /* returns a VM fd */
+#define KVM_GET_MSR_INDEX_LIST    _IOWR(KVMIO, 0x02, struct kvm_msr_list)
+/*
+ * Check if a kvm extension is available.  Argument is extension number,
+ * return is 1 (yes) or 0 (no, sorry).
+ */
+#define KVM_CHECK_EXTENSION       _IO(KVMIO,   0x03)
+/*
+ * Get size for mmap(vcpu_fd)
+ */
+#define KVM_GET_VCPU_MMAP_SIZE    _IO(KVMIO,   0x04) /* in bytes */
 
 /*
  * ioctls for VM fds
  */
-#define KVM_SET_MEMORY_REGION     _IOW(KVMIO, 10, struct kvm_memory_region)
+#define KVM_SET_MEMORY_REGION     _IOW(KVMIO, 0x40, struct kvm_memory_region)
 /*
  * KVM_CREATE_VCPU receives as a parameter the vcpu slot, and returns
  * a vcpu fd.
  */
-#define KVM_CREATE_VCPU           _IOW(KVMIO, 11, int)
-#define KVM_GET_DIRTY_LOG         _IOW(KVMIO, 12, struct kvm_dirty_log)
+#define KVM_CREATE_VCPU           _IO(KVMIO,  0x41)
+#define KVM_GET_DIRTY_LOG         _IOW(KVMIO, 0x42, struct kvm_dirty_log)
+#define KVM_SET_MEMORY_ALIAS      _IOW(KVMIO, 0x43, struct kvm_memory_alias)
 
 /*
  * ioctls for vcpu fds
  */
-#define KVM_RUN                   _IOWR(KVMIO, 2, struct kvm_run)
-#define KVM_GET_REGS              _IOR(KVMIO, 3, struct kvm_regs)
-#define KVM_SET_REGS              _IOW(KVMIO, 4, struct kvm_regs)
-#define KVM_GET_SREGS             _IOR(KVMIO, 5, struct kvm_sregs)
-#define KVM_SET_SREGS             _IOW(KVMIO, 6, struct kvm_sregs)
-#define KVM_TRANSLATE             _IOWR(KVMIO, 7, struct kvm_translation)
-#define KVM_INTERRUPT             _IOW(KVMIO, 8, struct kvm_interrupt)
-#define KVM_DEBUG_GUEST           _IOW(KVMIO, 9, struct kvm_debug_guest)
-#define KVM_GET_MSRS              _IOWR(KVMIO, 13, struct kvm_msrs)
-#define KVM_SET_MSRS              _IOW(KVMIO, 14, struct kvm_msrs)
+#define KVM_RUN                   _IO(KVMIO,   0x80)
+#define KVM_GET_REGS              _IOR(KVMIO,  0x81, struct kvm_regs)
+#define KVM_SET_REGS              _IOW(KVMIO,  0x82, struct kvm_regs)
+#define KVM_GET_SREGS             _IOR(KVMIO,  0x83, struct kvm_sregs)
+#define KVM_SET_SREGS             _IOW(KVMIO,  0x84, struct kvm_sregs)
+#define KVM_TRANSLATE             _IOWR(KVMIO, 0x85, struct kvm_translation)
+#define KVM_INTERRUPT             _IOW(KVMIO,  0x86, struct kvm_interrupt)
+#define KVM_DEBUG_GUEST           _IOW(KVMIO,  0x87, struct kvm_debug_guest)
+#define KVM_GET_MSRS              _IOWR(KVMIO, 0x88, struct kvm_msrs)
+#define KVM_SET_MSRS              _IOW(KVMIO,  0x89, struct kvm_msrs)
+#define KVM_SET_CPUID             _IOW(KVMIO,  0x8a, struct kvm_cpuid)
+#define KVM_SET_SIGNAL_MASK       _IOW(KVMIO,  0x8b, struct kvm_signal_mask)
+#define KVM_GET_FPU               _IOR(KVMIO,  0x8c, struct kvm_fpu)
+#define KVM_SET_FPU               _IOW(KVMIO,  0x8d, struct kvm_fpu)
 
 #endif
diff --git a/include/linux/libata.h b/include/linux/libata.h
index d8cfc72ea9c1..7906d750aa77 100644
--- a/include/linux/libata.h
+++ b/include/linux/libata.h
@@ -296,18 +296,8 @@ enum {
 
         /* how hard are we gonna try to probe/recover devices */
         ATA_PROBE_MAX_TRIES     = 3,
-        ATA_EH_RESET_TRIES      = 3,
         ATA_EH_DEV_TRIES        = 3,
 
-        /* Drive spinup time (time from power-on to the first D2H FIS)
-         * in msecs - 8s currently.  Failing to get ready in this time
-         * isn't critical.  It will result in reset failure for
-         * controllers which can't wait for the first D2H FIS.  libata
-         * will retry, so it just has to be long enough to spin up
-         * most devices.
-         */
-        ATA_SPINUP_WAIT         = 8000,
-
         /* Horkage types. May be set by libata or controller on drives
            (some horkage may be drive/controller pair dependant */
 
@@ -348,8 +338,9 @@ struct ata_queued_cmd;
 
 /* typedefs */
 typedef void (*ata_qc_cb_t) (struct ata_queued_cmd *qc);
-typedef int (*ata_prereset_fn_t)(struct ata_port *ap);
-typedef int (*ata_reset_fn_t)(struct ata_port *ap, unsigned int *classes);
+typedef int (*ata_prereset_fn_t)(struct ata_port *ap, unsigned long deadline);
+typedef int (*ata_reset_fn_t)(struct ata_port *ap, unsigned int *classes,
+                              unsigned long deadline);
 typedef void (*ata_postreset_fn_t)(struct ata_port *ap, unsigned int *classes);
 
 struct ata_ioports {
@@ -494,7 +485,6 @@ struct ata_eh_info {
         unsigned int            dev_action[ATA_MAX_DEVICES]; /* dev EH action */
         unsigned int            flags;          /* ATA_EHI_* flags */
 
-        unsigned long           hotplug_timestamp;
         unsigned int            probe_mask;
 
         char                    desc[ATA_EH_DESC_LEN];
@@ -688,13 +678,17 @@ extern void __sata_phy_reset(struct ata_port *ap);
 extern void sata_phy_reset(struct ata_port *ap);
 extern void ata_bus_reset(struct ata_port *ap);
 extern int sata_set_spd(struct ata_port *ap);
-extern int sata_phy_debounce(struct ata_port *ap, const unsigned long *param);
-extern int sata_phy_resume(struct ata_port *ap, const unsigned long *param);
-extern int ata_std_prereset(struct ata_port *ap);
-extern int ata_std_softreset(struct ata_port *ap, unsigned int *classes);
-extern int sata_port_hardreset(struct ata_port *ap,
-                               const unsigned long *timing);
-extern int sata_std_hardreset(struct ata_port *ap, unsigned int *class);
+extern int sata_phy_debounce(struct ata_port *ap, const unsigned long *param,
+                             unsigned long deadline);
+extern int sata_phy_resume(struct ata_port *ap, const unsigned long *param,
+                           unsigned long deadline);
+extern int ata_std_prereset(struct ata_port *ap, unsigned long deadline);
+extern int ata_std_softreset(struct ata_port *ap, unsigned int *classes,
+                             unsigned long deadline);
+extern int sata_port_hardreset(struct ata_port *ap, const unsigned long *timing,
+                               unsigned long deadline);
+extern int sata_std_hardreset(struct ata_port *ap, unsigned int *class,
+                              unsigned long deadline);
 extern void ata_std_postreset(struct ata_port *ap, unsigned int *classes);
 extern void ata_port_disable(struct ata_port *);
 extern void ata_std_ports(struct ata_ioports *ioaddr);
@@ -750,6 +744,7 @@ extern void ata_host_resume(struct ata_host *host);
 extern int ata_ratelimit(void);
 extern int ata_busy_sleep(struct ata_port *ap,
                           unsigned long timeout_pat, unsigned long timeout);
+extern int ata_wait_ready(struct ata_port *ap, unsigned long deadline);
 extern void ata_port_queue_task(struct ata_port *ap, work_func_t fn,
                                 void *data, unsigned long delay);
 extern u32 ata_wait_register(void __iomem *reg, u32 mask, u32 val,
@@ -919,12 +914,7 @@ extern void ata_do_eh(struct ata_port *ap, ata_prereset_fn_t prereset,
 
 static inline void __ata_ehi_hotplugged(struct ata_eh_info *ehi)
 {
-        if (ehi->flags & ATA_EHI_HOTPLUGGED)
-                return;
-
         ehi->flags |= ATA_EHI_HOTPLUGGED | ATA_EHI_RESUME_LINK;
-        ehi->hotplug_timestamp = jiffies;
-
         ehi->action |= ATA_EH_SOFTRESET;
         ehi->probe_mask |= (1 << ATA_MAX_DEVICES) - 1;
 }
diff --git a/include/linux/list.h b/include/linux/list.h
index f9d71eab05ee..9202703be2a4 100644
--- a/include/linux/list.h
+++ b/include/linux/list.h
@@ -426,6 +426,17 @@ static inline void list_splice_init_rcu(struct list_head *list,
         container_of(ptr, type, member)
 
 /**
+ * list_first_entry - get the first element from a list
+ * @ptr:        the list head to take the element from.
+ * @type:       the type of the struct this is embedded in.
+ * @member:     the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define list_first_entry(ptr, type, member) \
+        list_entry((ptr)->next, type, member)
+
+/**
  * list_for_each        -       iterate over a list
  * @pos:        the &struct list_head to use as a loop cursor.
  * @head:       the head for your list.
diff --git a/include/linux/lockd/lockd.h b/include/linux/lockd/lockd.h
index f6a81e0b1b93..05707e2fccae 100644
--- a/include/linux/lockd/lockd.h
+++ b/include/linux/lockd/lockd.h
@@ -119,6 +119,9 @@ struct nlm_file {
  * couldn't be granted because of a conflicting lock).
  */
 #define NLM_NEVER               (~(unsigned long) 0)
+/* timeout on non-blocking call: */
+#define NLM_TIMEOUT             (7 * HZ)
+
 struct nlm_block {
         struct kref             b_count;        /* Reference count */
         struct list_head        b_list;         /* linked list of all blocks */
@@ -130,6 +133,13 @@ struct nlm_block {
         unsigned int            b_id;           /* block id */
         unsigned char           b_granted;      /* VFS granted lock */
         struct nlm_file *       b_file;         /* file in question */
+        struct cache_req *      b_cache_req;    /* deferred request handling */
+        struct file_lock *      b_fl;           /* set for GETLK */
+        struct cache_deferred_req * b_deferred_req;
+        unsigned int            b_flags;        /* block flags */
+#define B_QUEUED                1       /* lock queued */
+#define B_GOT_CALLBACK          2       /* got lock or conflicting lock */
+#define B_TIMED_OUT             4       /* filesystem too slow to respond */
 };
 
 /*
@@ -185,8 +195,8 @@ typedef int	  (*nlm_host_match_fn_t)(struct nlm_host *cur, struct nlm_host *ref)
 __be32            nlmsvc_lock(struct svc_rqst *, struct nlm_file *,
                                         struct nlm_lock *, int, struct nlm_cookie *);
 __be32            nlmsvc_unlock(struct nlm_file *, struct nlm_lock *);
-__be32            nlmsvc_testlock(struct nlm_file *, struct nlm_lock *,
-                                        struct nlm_lock *);
+__be32            nlmsvc_testlock(struct svc_rqst *, struct nlm_file *,
+                        struct nlm_lock *, struct nlm_lock *, struct nlm_cookie *);
 __be32            nlmsvc_cancel_blocked(struct nlm_file *, struct nlm_lock *);
 unsigned long     nlmsvc_retry_blocked(void);
 void              nlmsvc_traverse_blocks(struct nlm_host *, struct nlm_file *,
diff --git a/include/linux/loop.h b/include/linux/loop.h
index 191a595055f0..0b99b31f017b 100644
--- a/include/linux/loop.h
+++ b/include/linux/loop.h
@@ -64,6 +64,8 @@ struct loop_device {
         wait_queue_head_t       lo_event;
 
         request_queue_t         *lo_queue;
+        struct gendisk          *lo_disk;
+        struct list_head        lo_list;
 };
 
 #endif /* __KERNEL__ */
diff --git a/include/linux/mc146818rtc.h b/include/linux/mc146818rtc.h
index bdc01127dced..580b3f4956ee 100644
--- a/include/linux/mc146818rtc.h
+++ b/include/linux/mc146818rtc.h
@@ -22,8 +22,15 @@ extern spinlock_t rtc_lock;		/* serialize CMOS RAM access */
 /* Some RTCs extend the mc146818 register set to support alarms of more
  * than 24 hours in the future; or dates that include a century code.
  * This platform_data structure can pass this information to the driver.
+ *
+ * Also, some platforms need suspend()/resume() hooks to kick in special
+ * handling of wake alarms, e.g. activating ACPI BIOS hooks or setting up
+ * a separate wakeup alarm used by some almost-clone chips.
  */
 struct cmos_rtc_board_info {
+        void    (*wake_on)(struct device *dev);
+        void    (*wake_off)(struct device *dev);
+
         u8      rtc_day_alarm;          /* zero, or register index */
         u8      rtc_mon_alarm;          /* zero, or register index */
         u8      rtc_century;            /* zero, or register index */
diff --git a/include/linux/migrate.h b/include/linux/migrate.h
index 75e55dcdeb18..e10a90a93b5d 100644
--- a/include/linux/migrate.h
+++ b/include/linux/migrate.h
@@ -2,18 +2,29 @@
 #define _LINUX_MIGRATE_H
 
 #include <linux/mm.h>
+#include <linux/mempolicy.h>
+#include <linux/pagemap.h>
 
 typedef struct page *new_page_t(struct page *, unsigned long private, int **);
 
+#ifdef CONFIG_MIGRATION
 /* Check if a vma is migratable */
 static inline int vma_migratable(struct vm_area_struct *vma)
 {
         if (vma->vm_flags & (VM_IO|VM_HUGETLB|VM_PFNMAP|VM_RESERVED))
                 return 0;
+        /*
+         * Migration allocates pages in the highest zone. If we cannot
+         * do so then migration (at least from node to node) is not
+         * possible.
+         */
+        if (vma->vm_file &&
+                gfp_zone(mapping_gfp_mask(vma->vm_file->f_mapping))
+                                                                < policy_zone)
+                        return 0;
         return 1;
 }
 
-#ifdef CONFIG_MIGRATION
 extern int isolate_lru_page(struct page *p, struct list_head *pagelist);
 extern int putback_lru_pages(struct list_head *l);
 extern int migrate_page(struct address_space *,
@@ -28,6 +39,8 @@ extern int migrate_vmas(struct mm_struct *mm,
                 const nodemask_t *from, const nodemask_t *to,
                 unsigned long flags);
 #else
+static inline int vma_migratable(struct vm_area_struct *vma)
+                                        { return 0; }
 
 static inline int isolate_lru_page(struct page *p, struct list_head *list)
                                         { return -ENOSYS; }
diff --git a/include/linux/miscdevice.h b/include/linux/miscdevice.h
index 326da7d500c7..dff9ea32606a 100644
--- a/include/linux/miscdevice.h
+++ b/include/linux/miscdevice.h
@@ -29,6 +29,7 @@
 
 #define TUN_MINOR            200
 #define HPET_MINOR           228
+#define KVM_MINOR            232
 
 struct device;
 
diff --git a/include/linux/mm.h b/include/linux/mm.h
index 60e0e4a592d2..4670ebd1f622 100644
--- a/include/linux/mm.h
+++ b/include/linux/mm.h
@@ -267,21 +267,31 @@ static inline int get_page_unless_zero(struct page *page)
         return atomic_inc_not_zero(&page->_count);
 }
 
+static inline struct page *compound_head(struct page *page)
+{
+        if (unlikely(PageTail(page)))
+                return page->first_page;
+        return page;
+}
+
 static inline int page_count(struct page *page)
 {
-        if (unlikely(PageCompound(page)))
-                page = (struct page *)page_private(page);
-        return atomic_read(&page->_count);
+        return atomic_read(&compound_head(page)->_count);
 }
 
 static inline void get_page(struct page *page)
 {
-        if (unlikely(PageCompound(page)))
-                page = (struct page *)page_private(page);
+        page = compound_head(page);
         VM_BUG_ON(atomic_read(&page->_count) == 0);
         atomic_inc(&page->_count);
 }
 
+static inline struct page *virt_to_head_page(const void *x)
+{
+        struct page *page = virt_to_page(x);
+        return compound_head(page);
+}
+
 /*
  * Setup the page count before being freed into the page allocator for
  * the first time (boot or memory hotplug)
@@ -314,6 +324,18 @@ static inline compound_page_dtor *get_compound_page_dtor(struct page *page)
         return (compound_page_dtor *)page[1].lru.next;
 }
 
+static inline int compound_order(struct page *page)
+{
+        if (!PageHead(page))
+                return 0;
+        return (unsigned long)page[1].lru.prev;
+}
+
+static inline void set_compound_order(struct page *page, unsigned long order)
+{
+        page[1].lru.prev = (void *)order;
+}
+
 /*
  * Multiple processes may "see" the same page. E.g. for untouched
  * mappings of /dev/null, all processes see the same page full of
@@ -850,8 +872,26 @@ static inline int vma_wants_writenotify(struct vm_area_struct *vma)
 
 extern pte_t *FASTCALL(get_locked_pte(struct mm_struct *mm, unsigned long addr, spinlock_t **ptl));
 
+#ifdef __PAGETABLE_PUD_FOLDED
+static inline int __pud_alloc(struct mm_struct *mm, pgd_t *pgd,
+                                                unsigned long address)
+{
+        return 0;
+}
+#else
 int __pud_alloc(struct mm_struct *mm, pgd_t *pgd, unsigned long address);
+#endif
+
+#ifdef __PAGETABLE_PMD_FOLDED
+static inline int __pmd_alloc(struct mm_struct *mm, pud_t *pud,
+                                                unsigned long address)
+{
+        return 0;
+}
+#else
 int __pmd_alloc(struct mm_struct *mm, pud_t *pud, unsigned long address);
+#endif
+
 int __pte_alloc(struct mm_struct *mm, pmd_t *pmd, unsigned long address);
 int __pte_alloc_kernel(pmd_t *pmd, unsigned long address);
 
@@ -1130,6 +1170,11 @@ struct page *follow_page(struct vm_area_struct *, unsigned long address,
 #define FOLL_GET        0x04    /* do get_page on page */
 #define FOLL_ANON       0x08    /* give ZERO_PAGE if no pgtable */
 
+typedef int (*pte_fn_t)(pte_t *pte, struct page *pmd_page, unsigned long addr,
+                        void *data);
+extern int apply_to_page_range(struct mm_struct *mm, unsigned long address,
+                               unsigned long size, pte_fn_t fn, void *data);
+
 #ifdef CONFIG_PROC_FS
 void vm_stat_account(struct mm_struct *, unsigned long, struct file *, long);
 #else
diff --git a/include/linux/mm_types.h b/include/linux/mm_types.h
index c3852fd4a1cc..e30687bad075 100644
--- a/include/linux/mm_types.h
+++ b/include/linux/mm_types.h
@@ -19,10 +19,16 @@ struct page {
         unsigned long flags;            /* Atomic flags, some possibly
                                          * updated asynchronously */
         atomic_t _count;                /* Usage count, see below. */
-        atomic_t _mapcount;             /* Count of ptes mapped in mms,
+        union {
+                atomic_t _mapcount;     /* Count of ptes mapped in mms,
                                          * to show when page is mapped
                                          * & limit reverse map searches.
                                          */
+                struct {        /* SLUB uses */
+                        short unsigned int inuse;
+                        short unsigned int offset;
+                };
+        };
         union {
             struct {
                 unsigned long private;          /* Mapping-private opaque data:
@@ -43,8 +49,15 @@ struct page {
 #if NR_CPUS >= CONFIG_SPLIT_PTLOCK_CPUS
             spinlock_t ptl;
 #endif
+            struct {                    /* SLUB uses */
+                struct page *first_page;        /* Compound pages */
+                struct kmem_cache *slab;        /* Pointer to slab */
+            };
+        };
+        union {
+                pgoff_t index;          /* Our offset within mapping. */
+                void *freelist;         /* SLUB: pointer to free object */
         };
-        pgoff_t index;                  /* Our offset within mapping. */
         struct list_head lru;           /* Pageout list, eg. active_list
                                          * protected by zone->lru_lock !
                                          */
diff --git a/include/linux/mmzone.h b/include/linux/mmzone.h
index ee9e3143df4f..2f1544e83042 100644
--- a/include/linux/mmzone.h
+++ b/include/linux/mmzone.h
@@ -784,6 +784,18 @@ void sparse_init(void);
 void memory_present(int nid, unsigned long start, unsigned long end);
 unsigned long __init node_memmap_size_bytes(int, unsigned long, unsigned long);
 
+/*
+ * If it is possible to have holes within a MAX_ORDER_NR_PAGES, then we
+ * need to check pfn validility within that MAX_ORDER_NR_PAGES block.
+ * pfn_valid_within() should be used in this case; we optimise this away
+ * when we have no holes within a MAX_ORDER_NR_PAGES block.
+ */
+#ifdef CONFIG_HOLES_IN_ZONE
+#define pfn_valid_within(pfn) pfn_valid(pfn)
+#else
+#define pfn_valid_within(pfn) (1)
+#endif
+
 #endif /* !__ASSEMBLY__ */
 #endif /* __KERNEL__ */
 #endif /* _LINUX_MMZONE_H */
diff --git a/include/linux/mnt_namespace.h b/include/linux/mnt_namespace.h
index 4af0b1fc282a..1fa4d9813b31 100644
--- a/include/linux/mnt_namespace.h
+++ b/include/linux/mnt_namespace.h
@@ -14,10 +14,9 @@ struct mnt_namespace {
         int event;
 };
 
-extern int copy_mnt_ns(int, struct task_struct *);
-extern void __put_mnt_ns(struct mnt_namespace *ns);
-extern struct mnt_namespace *dup_mnt_ns(struct task_struct *,
+extern struct mnt_namespace *copy_mnt_ns(int, struct mnt_namespace *,
                 struct fs_struct *);
+extern void __put_mnt_ns(struct mnt_namespace *ns);
 
 static inline void put_mnt_ns(struct mnt_namespace *ns)
 {
diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetable.h
index e96b2dee10bb..af04a555b52c 100644
--- a/include/linux/mod_devicetable.h
+++ b/include/linux/mod_devicetable.h
@@ -262,6 +262,7 @@ struct i2c_device_id {
 
 /* Input */
 #define INPUT_DEVICE_ID_EV_MAX          0x1f
+#define INPUT_DEVICE_ID_KEY_MIN_INTERESTING     0x71
 #define INPUT_DEVICE_ID_KEY_MAX         0x1ff
 #define INPUT_DEVICE_ID_REL_MAX         0x0f
 #define INPUT_DEVICE_ID_ABS_MAX         0x3f
diff --git a/include/linux/module.h b/include/linux/module.h
index f0b0faf42d5d..6d3dc9c4ff96 100644
--- a/include/linux/module.h
+++ b/include/linux/module.h
@@ -370,16 +370,14 @@ struct module *module_text_address(unsigned long addr);
 struct module *__module_text_address(unsigned long addr);
 int is_module_address(unsigned long addr);
 
-/* Returns module and fills in value, defined and namebuf, or NULL if
+/* Returns 0 and fills in value, defined and namebuf, or -ERANGE if
    symnum out of range. */
-struct module *module_get_kallsym(unsigned int symnum, unsigned long *value,
-                                char *type, char *name, size_t namelen);
+int module_get_kallsym(unsigned int symnum, unsigned long *value, char *type,
+                        char *name, char *module_name, int *exported);
 
 /* Look for this name: can be of form module:name. */
 unsigned long module_kallsyms_lookup_name(const char *name);
 
-int is_exported(const char *name, const struct module *mod);
-
 extern void __module_put_and_exit(struct module *mod, long code)
         __attribute__((noreturn));
 #define module_put_and_exit(code) __module_put_and_exit(THIS_MODULE, code);
@@ -456,6 +454,8 @@ const char *module_address_lookup(unsigned long addr,
                                   unsigned long *symbolsize,
                                   unsigned long *offset,
                                   char **modname);
+int lookup_module_symbol_name(unsigned long addr, char *symname);
+int lookup_module_symbol_attrs(unsigned long addr, unsigned long *size, unsigned long *offset, char *modname, char *name);
 
 /* For extable.c to search modules' exception tables. */
 const struct exception_table_entry *search_module_extables(unsigned long addr);
@@ -527,20 +527,24 @@ static inline const char *module_address_lookup(unsigned long addr,
         return NULL;
 }
 
-static inline struct module *module_get_kallsym(unsigned int symnum,
-                                                unsigned long *value,
-                                                char *type, char *name,
-                                                size_t namelen)
+static inline int lookup_module_symbol_name(unsigned long addr, char *symname)
 {
-        return NULL;
+        return -ERANGE;
 }
 
-static inline unsigned long module_kallsyms_lookup_name(const char *name)
+static inline int lookup_module_symbol_attrs(unsigned long addr, unsigned long *size, unsigned long *offset, char *modname, char *name)
 {
-        return 0;
+        return -ERANGE;
 }
 
-static inline int is_exported(const char *name, const struct module *mod)
+static inline int module_get_kallsym(unsigned int symnum, unsigned long *value,
+                                        char *type, char *name,
+                                        char *module_name, int *exported)
+{
+        return -ERANGE;
+}
+
+static inline unsigned long module_kallsyms_lookup_name(const char *name)
 {
         return 0;
 }
diff --git a/include/linux/msdos_fs.h b/include/linux/msdos_fs.h
index fa253fa73aa3..0e09c005dda8 100644
--- a/include/linux/msdos_fs.h
+++ b/include/linux/msdos_fs.h
@@ -205,7 +205,8 @@ struct fat_mount_options {
                  numtail:1,       /* Does first alias have a numeric '~1' type tail? */
                  atari:1,         /* Use Atari GEMDOS variation of MS-DOS fs */
                  flush:1,         /* write things quickly */
-                 nocase:1;        /* Does this need case conversion? 0=need case conversion*/
+                 nocase:1,        /* Does this need case conversion? 0=need case conversion*/
+                 usefree:1;       /* Use free_clusters for FAT32 */
 };
 
 #define FAT_HASH_BITS   8
diff --git a/include/linux/nfs_fs_sb.h b/include/linux/nfs_fs_sb.h
index c95d5e642548..52b4378311c8 100644
--- a/include/linux/nfs_fs_sb.h
+++ b/include/linux/nfs_fs_sb.h
@@ -82,7 +82,7 @@ struct nfs_server {
         struct rpc_clnt *       client_acl;     /* ACL RPC client handle */
         struct nfs_iostats *    io_stats;       /* I/O statistics */
         struct backing_dev_info backing_dev_info;
-        atomic_t                writeback;      /* number of writeback pages */
+        atomic_long_t           writeback;      /* number of writeback pages */
         int                     flags;          /* various flags */
         unsigned int            caps;           /* server capabilities */
         unsigned int            rsize;          /* read size */
diff --git a/include/linux/nsproxy.h b/include/linux/nsproxy.h
index 0b9f0dc30d61..189e0dc993ab 100644
--- a/include/linux/nsproxy.h
+++ b/include/linux/nsproxy.h
@@ -31,10 +31,11 @@ struct nsproxy {
 };
 extern struct nsproxy init_nsproxy;
 
-struct nsproxy *dup_namespaces(struct nsproxy *orig);
 int copy_namespaces(int flags, struct task_struct *tsk);
 void get_task_namespaces(struct task_struct *tsk);
 void free_nsproxy(struct nsproxy *ns);
+int unshare_nsproxy_namespaces(unsigned long, struct nsproxy **,
+        struct fs_struct *);
 
 static inline void put_nsproxy(struct nsproxy *ns)
 {
diff --git a/include/linux/page-flags.h b/include/linux/page-flags.h
index 96326594e55d..ae2d79f2107e 100644
--- a/include/linux/page-flags.h
+++ b/include/linux/page-flags.h
@@ -6,6 +6,7 @@
 #define PAGE_FLAGS_H
 
 #include <linux/types.h>
+#include <linux/mm_types.h>
 
 /*
  * Various page->flags bits:
@@ -82,13 +83,11 @@
 #define PG_private              11      /* If pagecache, has fs-private data */
 
 #define PG_writeback            12      /* Page is under writeback */
-#define PG_nosave               13      /* Used for system suspend/resume */
 #define PG_compound             14      /* Part of a compound page */
 #define PG_swapcache            15      /* Swap page: swp_entry_t in private */
 
 #define PG_mappedtodisk         16      /* Has blocks allocated on-disk */
 #define PG_reclaim              17      /* To be reclaimed asap */
-#define PG_nosave_free          18      /* Used for system suspend/resume */
 #define PG_buddy                19      /* Page is free, on buddy lists */
 
 /* PG_owner_priv_1 users should have descriptive aliases */
@@ -214,16 +213,6 @@ static inline void SetPageUptodate(struct page *page)
                 ret;                                                    \
         })
 
-#define PageNosave(page)        test_bit(PG_nosave, &(page)->flags)
-#define SetPageNosave(page)     set_bit(PG_nosave, &(page)->flags)
-#define TestSetPageNosave(page) test_and_set_bit(PG_nosave, &(page)->flags)
-#define ClearPageNosave(page)           clear_bit(PG_nosave, &(page)->flags)
-#define TestClearPageNosave(page)       test_and_clear_bit(PG_nosave, &(page)->flags)
-
-#define PageNosaveFree(page)    test_bit(PG_nosave_free, &(page)->flags)
-#define SetPageNosaveFree(page) set_bit(PG_nosave_free, &(page)->flags)
-#define ClearPageNosaveFree(page)               clear_bit(PG_nosave_free, &(page)->flags)
-
 #define PageBuddy(page)         test_bit(PG_buddy, &(page)->flags)
 #define __SetPageBuddy(page)    __set_bit(PG_buddy, &(page)->flags)
 #define __ClearPageBuddy(page)  __clear_bit(PG_buddy, &(page)->flags)
@@ -241,6 +230,34 @@ static inline void SetPageUptodate(struct page *page)
 #define __SetPageCompound(page) __set_bit(PG_compound, &(page)->flags)
 #define __ClearPageCompound(page) __clear_bit(PG_compound, &(page)->flags)
 
+/*
+ * PG_reclaim is used in combination with PG_compound to mark the
+ * head and tail of a compound page
+ *
+ * PG_compound & PG_reclaim     => Tail page
+ * PG_compound & ~PG_reclaim    => Head page
+ */
+
+#define PG_head_tail_mask ((1L << PG_compound) | (1L << PG_reclaim))
+
+#define PageTail(page)  ((page->flags & PG_head_tail_mask) \
+                                == PG_head_tail_mask)
+
+static inline void __SetPageTail(struct page *page)
+{
+        page->flags |= PG_head_tail_mask;
+}
+
+static inline void __ClearPageTail(struct page *page)
+{
+        page->flags &= ~PG_head_tail_mask;
+}
+
+#define PageHead(page)  ((page->flags & PG_head_tail_mask) \
+                                == (1L << PG_compound))
+#define __SetPageHead(page)     __SetPageCompound(page)
+#define __ClearPageHead(page)   __ClearPageCompound(page)
+
 #ifdef CONFIG_SWAP
 #define PageSwapCache(page)     test_bit(PG_swapcache, &(page)->flags)
 #define SetPageSwapCache(page)  set_bit(PG_swapcache, &(page)->flags)
diff --git a/include/linux/pagemap.h b/include/linux/pagemap.h
index 7a8dcb82a699..8a83537d6978 100644
--- a/include/linux/pagemap.h
+++ b/include/linux/pagemap.h
@@ -11,6 +11,7 @@
 #include <linux/compiler.h>
 #include <asm/uaccess.h>
 #include <linux/gfp.h>
+#include <linux/bitops.h>
 
 /*
  * Bits in mapping->flags.  The lower __GFP_BITS_SHIFT bits are the page
@@ -19,6 +20,16 @@
 #define AS_EIO          (__GFP_BITS_SHIFT + 0)  /* IO error on async write */
 #define AS_ENOSPC       (__GFP_BITS_SHIFT + 1)  /* ENOSPC on async write */
 
+static inline void mapping_set_error(struct address_space *mapping, int error)
+{
+        if (error) {
+                if (error == -ENOSPC)
+                        set_bit(AS_ENOSPC, &mapping->flags);
+                else
+                        set_bit(AS_EIO, &mapping->flags);
+        }
+}
+
 static inline gfp_t mapping_gfp_mask(struct address_space * mapping)
 {
         return (__force gfp_t)mapping->flags & __GFP_BITS_MASK;
@@ -95,12 +106,23 @@ static inline struct page *grab_cache_page(struct address_space *mapping, unsign
 
 extern struct page * grab_cache_page_nowait(struct address_space *mapping,
                                 unsigned long index);
+extern struct page * read_cache_page_async(struct address_space *mapping,
+                                unsigned long index, filler_t *filler,
+                                void *data);
 extern struct page * read_cache_page(struct address_space *mapping,
                                 unsigned long index, filler_t *filler,
                                 void *data);
 extern int read_cache_pages(struct address_space *mapping,
                 struct list_head *pages, filler_t *filler, void *data);
 
+static inline struct page *read_mapping_page_async(
+                                                struct address_space *mapping,
+                                             unsigned long index, void *data)
+{
+        filler_t *filler = (filler_t *)mapping->a_ops->readpage;
+        return read_cache_page_async(mapping, index, filler, data);
+}
+
 static inline struct page *read_mapping_page(struct address_space *mapping,
                                              unsigned long index, void *data)
 {
diff --git a/include/linux/parport.h b/include/linux/parport.h
index 80682aaa8f18..9cdd6943e01b 100644
--- a/include/linux/parport.h
+++ b/include/linux/parport.h
@@ -279,6 +279,10 @@ struct parport {
         int dma;
         int muxport;            /* which muxport (if any) this is */
         int portnum;            /* which physical parallel port (not mux) */
+        struct device *dev;     /* Physical device associated with IO/DMA.
+                                 * This may unfortulately be null if the
+                                 * port has a legacy driver.
+                                 */
 
         struct parport *physport;
                                 /* If this is a non-default mux
@@ -289,7 +293,7 @@ struct parport {
                                    following structure members are
                                    meaningless: devices, cad, muxsel,
                                    waithead, waittail, flags, pdir,
-                                   ieee1284, *_lock.
+                                   dev, ieee1284, *_lock.
 
                                    It this is a default mux parport, or
                                    there is no mux involved, this points to
@@ -302,7 +306,7 @@ struct parport {
 
         struct pardevice *waithead;
         struct pardevice *waittail;
-        
+
         struct list_head list;
         unsigned int flags;
 
diff --git a/include/linux/parport_pc.h b/include/linux/parport_pc.h
index 1cc0f6b1a49a..ea8c6d84996d 100644
--- a/include/linux/parport_pc.h
+++ b/include/linux/parport_pc.h
@@ -38,7 +38,6 @@ struct parport_pc_private {
         /* buffer suitable for DMA, if DMA enabled */
         char *dma_buf;
         dma_addr_t dma_handle;
-        struct pci_dev *dev;
         struct list_head list;
         struct parport *port;
 };
@@ -232,7 +231,7 @@ extern int parport_pc_claim_resources(struct parport *p);
 extern struct parport *parport_pc_probe_port (unsigned long base,
                                               unsigned long base_hi,
                                               int irq, int dma,
-                                              struct pci_dev *dev);
+                                              struct device *dev);
 extern void parport_pc_unregister_port (struct parport *p);
 
 #endif
diff --git a/include/linux/phantom.h b/include/linux/phantom.h
new file mode 100644
index 000000000000..d3ebbfae6903
--- /dev/null
+++ b/include/linux/phantom.h
@@ -0,0 +1,42 @@
+/*
+ *  Copyright (C) 2005-2007 Jiri Slaby <jirislaby@gmail.com>
+ *
+ *  This program is free software; you can redistribute it and/or modify
+ *  it under the terms of the GNU General Public License as published by
+ *  the Free Software Foundation; either version 2 of the License, or
+ *  (at your option) any later version.
+ */
+
+#ifndef __PHANTOM_H
+#define __PHANTOM_H
+
+#include <asm/types.h>
+
+/* PHN_(G/S)ET_REG param */
+struct phm_reg {
+        __u32 reg;
+        __u32 value;
+};
+
+/* PHN_(G/S)ET_REGS param */
+struct phm_regs {
+        __u32 count;
+        __u32 mask;
+        __u32 values[8];
+};
+
+#define PH_IOC_MAGIC            'p'
+#define PHN_GET_REG             _IOWR(PH_IOC_MAGIC, 0, struct phm_reg *)
+#define PHN_SET_REG             _IOW (PH_IOC_MAGIC, 1, struct phm_reg *)
+#define PHN_GET_REGS            _IOWR(PH_IOC_MAGIC, 2, struct phm_regs *)
+#define PHN_SET_REGS            _IOW (PH_IOC_MAGIC, 3, struct phm_regs *)
+#define PH_IOC_MAXNR            3
+
+#define PHN_CONTROL             0x6     /* control byte in iaddr space */
+#define PHN_CTL_AMP             0x1     /*   switch after torques change */
+#define PHN_CTL_BUT             0x2     /*   is button switched */
+#define PHN_CTL_IRQ             0x10    /*   is irq enabled */
+
+#define PHN_ZERO_FORCE          2048    /* zero torque on motor */
+
+#endif
diff --git a/include/linux/pid_namespace.h b/include/linux/pid_namespace.h
index 2833806d42c6..169c6c24209b 100644
--- a/include/linux/pid_namespace.h
+++ b/include/linux/pid_namespace.h
@@ -29,7 +29,7 @@ static inline void get_pid_ns(struct pid_namespace *ns)
         kref_get(&ns->kref);
 }
 
-extern int copy_pid_ns(int flags, struct task_struct *tsk);
+extern struct pid_namespace *copy_pid_ns(int flags, struct pid_namespace *ns);
 extern void free_pid_ns(struct kref *kref);
 
 static inline void put_pid_ns(struct pid_namespace *ns)
diff --git a/include/linux/pmu.h b/include/linux/pmu.h
index b0952e532ed5..37ca57392add 100644
--- a/include/linux/pmu.h
+++ b/include/linux/pmu.h
@@ -225,4 +225,12 @@ extern unsigned int pmu_power_flags;
 /* Backlight */
 extern void pmu_backlight_init(void);
 
+/* some code needs to know if the PMU was suspended for hibernation */
+#ifdef CONFIG_PM
+extern int pmu_sys_suspended;
+#else
+/* if power management is not configured it can't be suspended */
+#define pmu_sys_suspended       0
+#endif
+
 #endif  /* __KERNEL__ */
diff --git a/include/linux/pnp.h b/include/linux/pnp.h
index 9a5226f0f169..2a1897e6f937 100644
--- a/include/linux/pnp.h
+++ b/include/linux/pnp.h
@@ -177,6 +177,7 @@ static inline void pnp_set_card_drvdata (struct pnp_card_link *pcard, void *data
 
 struct pnp_dev {
         struct device dev;              /* Driver Model device interface */
+        u64 dma_mask;
         unsigned char number;           /* used as an index, must be unique */
         int status;
 
@@ -363,6 +364,7 @@ int pnp_add_device(struct pnp_dev *dev);
 int pnp_device_attach(struct pnp_dev *pnp_dev);
 void pnp_device_detach(struct pnp_dev *pnp_dev);
 extern struct list_head pnp_global;
+extern int pnp_platform_devices;
 
 /* multidevice card support */
 int pnp_add_card(struct pnp_card *card);
@@ -410,6 +412,7 @@ static inline int pnp_init_device(struct pnp_dev *dev) { return -ENODEV; }
 static inline int pnp_add_device(struct pnp_dev *dev) { return -ENODEV; }
 static inline int pnp_device_attach(struct pnp_dev *pnp_dev) { return -ENODEV; }
 static inline void pnp_device_detach(struct pnp_dev *pnp_dev) { ; }
+#define pnp_platform_devices 0
 
 /* multidevice card support */
 static inline int pnp_add_card(struct pnp_card *card) { return -ENODEV; }
diff --git a/include/linux/poison.h b/include/linux/poison.h
index 89580b764959..d93c300a3449 100644
--- a/include/linux/poison.h
+++ b/include/linux/poison.h
@@ -15,8 +15,11 @@
  * Magic nums for obj red zoning.
  * Placed in the first word before and the first word after an obj.
  */
-#define RED_INACTIVE    0x5A2CF071UL    /* when obj is inactive */
-#define RED_ACTIVE      0x170FC2A5UL    /* when obj is active */
+#define RED_INACTIVE    0x09F911029D74E35BULL   /* when obj is inactive */
+#define RED_ACTIVE      0xD84156C5635688C0ULL   /* when obj is active */
+
+#define SLUB_RED_INACTIVE       0xbb
+#define SLUB_RED_ACTIVE         0xcc
 
 /* ...and for poisoning */
 #define POISON_INUSE    0x5a    /* for use-uninitialised poisoning */
diff --git a/include/linux/proc_fs.h b/include/linux/proc_fs.h
index be4652a0545a..3469f96bc8b2 100644
--- a/include/linux/proc_fs.h
+++ b/include/linux/proc_fs.h
@@ -104,6 +104,10 @@ int proc_pid_readdir(struct file * filp, void * dirent, filldir_t filldir);
 unsigned long task_vsize(struct mm_struct *);
 int task_statm(struct mm_struct *, int *, int *, int *, int *);
 char *task_mem(struct mm_struct *, char *);
+void clear_refs_smap(struct mm_struct *mm);
+
+struct proc_dir_entry *de_get(struct proc_dir_entry *de);
+void de_put(struct proc_dir_entry *de);
 
 extern struct proc_dir_entry *create_proc_entry(const char *name, mode_t mode,
                                                 struct proc_dir_entry *parent);
diff --git a/include/linux/quicklist.h b/include/linux/quicklist.h
new file mode 100644
index 000000000000..9371c6116df3
--- /dev/null
+++ b/include/linux/quicklist.h
@@ -0,0 +1,94 @@
+#ifndef LINUX_QUICKLIST_H
+#define LINUX_QUICKLIST_H
+/*
+ * Fast allocations and disposal of pages. Pages must be in the condition
+ * as needed after allocation when they are freed. Per cpu lists of pages
+ * are kept that only contain node local pages.
+ *
+ * (C) 2007, SGI. Christoph Lameter <clameter@sgi.com>
+ */
+#include <linux/kernel.h>
+#include <linux/gfp.h>
+#include <linux/percpu.h>
+
+#ifdef CONFIG_QUICKLIST
+
+struct quicklist {
+        void *page;
+        int nr_pages;
+};
+
+DECLARE_PER_CPU(struct quicklist, quicklist)[CONFIG_NR_QUICK];
+
+/*
+ * The two key functions quicklist_alloc and quicklist_free are inline so
+ * that they may be custom compiled for the platform.
+ * Specifying a NULL ctor can remove constructor support. Specifying
+ * a constant quicklist allows the determination of the exact address
+ * in the per cpu area.
+ *
+ * The fast patch in quicklist_alloc touched only a per cpu cacheline and
+ * the first cacheline of the page itself. There is minmal overhead involved.
+ */
+static inline void *quicklist_alloc(int nr, gfp_t flags, void (*ctor)(void *))
+{
+        struct quicklist *q;
+        void **p = NULL;
+
+        q =&get_cpu_var(quicklist)[nr];
+        p = q->page;
+        if (likely(p)) {
+                q->page = p[0];
+                p[0] = NULL;
+                q->nr_pages--;
+        }
+        put_cpu_var(quicklist);
+        if (likely(p))
+                return p;
+
+        p = (void *)__get_free_page(flags | __GFP_ZERO);
+        if (ctor && p)
+                ctor(p);
+        return p;
+}
+
+static inline void __quicklist_free(int nr, void (*dtor)(void *), void *p,
+        struct page *page)
+{
+        struct quicklist *q;
+        int nid = page_to_nid(page);
+
+        if (unlikely(nid != numa_node_id())) {
+                if (dtor)
+                        dtor(p);
+                __free_page(page);
+                return;
+        }
+
+        q = &get_cpu_var(quicklist)[nr];
+        *(void **)p = q->page;
+        q->page = p;
+        q->nr_pages++;
+        put_cpu_var(quicklist);
+}
+
+static inline void quicklist_free(int nr, void (*dtor)(void *), void *pp)
+{
+        __quicklist_free(nr, dtor, pp, virt_to_page(pp));
+}
+
+static inline void quicklist_free_page(int nr, void (*dtor)(void *),
+                                                        struct page *page)
+{
+        __quicklist_free(nr, dtor, page_address(page), page);
+}
+
+void quicklist_trim(int nr, void (*dtor)(void *),
+        unsigned long min_pages, unsigned long max_free);
+
+unsigned long quicklist_total_size(void);
+
+#endif
+
+#endif /* LINUX_QUICKLIST_H */
+
diff --git a/include/linux/quota.h b/include/linux/quota.h
index 77db80a953d6..62439828395e 100644
--- a/include/linux/quota.h
+++ b/include/linux/quota.h
@@ -44,8 +44,6 @@
 typedef __kernel_uid32_t qid_t; /* Type in which we store ids in memory */
 typedef __u64 qsize_t;          /* Type in which we store sizes */
 
-extern spinlock_t dq_data_lock;
-
 /* Size of blocks in which are counted size limits */
 #define QUOTABLOCK_BITS 10
 #define QUOTABLOCK_SIZE (1 << QUOTABLOCK_BITS)
@@ -139,6 +137,8 @@ struct if_dqinfo {
 #include <linux/dqblk_v1.h>
 #include <linux/dqblk_v2.h>
 
+extern spinlock_t dq_data_lock;
+
 /* Maximal numbers of writes for quota operation (insert/delete/update)
  * (over VFS all formats) */
 #define DQUOT_INIT_ALLOC max(V1_INIT_ALLOC, V2_INIT_ALLOC)
diff --git a/include/linux/quotaops.h b/include/linux/quotaops.h
index 90c23f690c0d..5110201a4159 100644
--- a/include/linux/quotaops.h
+++ b/include/linux/quotaops.h
@@ -37,9 +37,6 @@ extern int dquot_release(struct dquot *dquot);
 extern int dquot_commit_info(struct super_block *sb, int type);
 extern int dquot_mark_dquot_dirty(struct dquot *dquot);
 
-int remove_inode_dquot_ref(struct inode *inode, int type,
-                           struct list_head *tofree_head);
-
 extern int vfs_quota_on(struct super_block *sb, int type, int format_id, char *path);
 extern int vfs_quota_on_mount(struct super_block *sb, char *qf_name,
                 int format_id, int type);
diff --git a/include/linux/reiserfs_fs_sb.h b/include/linux/reiserfs_fs_sb.h
index 3a28742d86f9..1e5488ede037 100644
--- a/include/linux/reiserfs_fs_sb.h
+++ b/include/linux/reiserfs_fs_sb.h
@@ -401,9 +401,10 @@ struct reiserfs_sb_info {
         int reserved_blocks;    /* amount of blocks reserved for further allocations */
         spinlock_t bitmap_lock; /* this lock on now only used to protect reserved_blocks variable */
         struct dentry *priv_root;       /* root of /.reiserfs_priv */
+#ifdef CONFIG_REISERFS_FS_XATTR
         struct dentry *xattr_root;      /* root of /.reiserfs_priv/.xa */
         struct rw_semaphore xattr_dir_sem;
-
+#endif
         int j_errno;
 #ifdef CONFIG_QUOTA
         char *s_qf_names[MAXQUOTAS];
diff --git a/include/linux/rfkill.h b/include/linux/rfkill.h
new file mode 100644
index 000000000000..7c1ffbab7865
--- /dev/null
+++ b/include/linux/rfkill.h
@@ -0,0 +1,89 @@
+#ifndef __RFKILL_H
+#define __RFKILL_H
+
+/*
+ * Copyright (C) 2006 Ivo van Doorn
+ * Copyright (C) 2007 Dmitry Torokhov
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the
+ * Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
+ */
+
+#include <linux/types.h>
+#include <linux/kernel.h>
+#include <linux/list.h>
+#include <linux/mutex.h>
+#include <linux/device.h>
+
+/**
+ * enum rfkill_type - type of rfkill switch.
+ * RFKILL_TYPE_WLAN: switch is no a Wireless network devices.
+ * RFKILL_TYPE_BlUETOOTH: switch is on a bluetooth device.
+ * RFKILL_TYPE_IRDA: switch is on an infrared devices.
+ */
+enum rfkill_type {
+        RFKILL_TYPE_WLAN = 0,
+        RFKILL_TYPE_BLUETOOTH = 1,
+        RFKILL_TYPE_IRDA = 2,
+        RFKILL_TYPE_MAX = 3,
+};
+
+enum rfkill_state {
+        RFKILL_STATE_OFF        = 0,
+        RFKILL_STATE_ON         = 1,
+};
+
+/**
+ * struct rfkill - rfkill control structure.
+ * @name: Name of the switch.
+ * @type: Radio type which the button controls, the value stored
+ *      here should be a value from enum rfkill_type.
+ * @state: State of the switch (on/off).
+ * @user_claim: Set when the switch is controlled exlusively by userspace.
+ * @mutex: Guards switch state transitions
+ * @data: Pointer to the RF button drivers private data which will be
+ *      passed along when toggling radio state.
+ * @toggle_radio(): Mandatory handler to control state of the radio.
+ * @dev: Device structure integrating the switch into device tree.
+ * @node: Used to place switch into list of all switches known to the
+ *      the system.
+ *
+ * This structure represents a RF switch located on a network device.
+ */
+struct rfkill {
+        char *name;
+        enum rfkill_type type;
+
+        enum rfkill_state state;
+        bool user_claim;
+
+        struct mutex mutex;
+
+        void *data;
+        int (*toggle_radio)(void *data, enum rfkill_state state);
+
+        struct device dev;
+        struct list_head node;
+};
+#define to_rfkill(d)    container_of(d, struct rfkill, dev)
+
+struct rfkill *rfkill_allocate(struct device *parent, enum rfkill_type type);
+void rfkill_free(struct rfkill *rfkill);
+int rfkill_register(struct rfkill *rfkill);
+void rfkill_unregister(struct rfkill *rfkill);
+
+void rfkill_switch_all(enum rfkill_type type, enum rfkill_state state);
+
+#endif /* RFKILL_H */
diff --git a/include/linux/rtc.h b/include/linux/rtc.h
index 5e22d4510d11..6d5e4a46781e 100644
--- a/include/linux/rtc.h
+++ b/include/linux/rtc.h
@@ -4,7 +4,7 @@
  * service. It is used with both the legacy mc146818 and also  EFI
  * Struct rtc_time and first 12 ioctl by Paul Gortmaker, 1996 - separated out
  * from <linux/mc146818rtc.h> to this file for 2.4 kernels.
- * 
+ *
  * Copyright (C) 1999 Hewlett-Packard Co.
  * Copyright (C) 1999 Stephane Eranian <eranian@hpl.hp.com>
  */
@@ -13,7 +13,7 @@
 
 /*
  * The struct used to pass data via the following ioctl. Similar to the
- * struct tm in <time.h>, but it needs to be here so that the kernel 
+ * struct tm in <time.h>, but it needs to be here so that the kernel
  * source is self contained, allowing cross-compiles, etc. etc.
  */
 
@@ -50,7 +50,7 @@ struct rtc_wkalrm {
  *   pll_value*pll_posmult/pll_clock
  * -ve pll_value means clock will run slower by
  *   pll_value*pll_negmult/pll_clock
- */ 
+ */
 
 struct rtc_pll_info {
         int pll_ctrl;       /* placeholder for fancier control */
@@ -106,7 +106,6 @@ extern int rtc_year_days(unsigned int day, unsigned int month, unsigned int year
 extern int rtc_valid_tm(struct rtc_time *tm);
 extern int rtc_tm_to_time(struct rtc_time *tm, unsigned long *time);
 extern void rtc_time_to_tm(unsigned long time, struct rtc_time *tm);
-extern void rtc_merge_alarm(struct rtc_time *now, struct rtc_time *alarm);
 
 #include <linux/device.h>
 #include <linux/seq_file.h>
@@ -136,7 +135,7 @@ struct rtc_task;
 
 struct rtc_device
 {
-        struct class_device class_dev;
+        struct device dev;
         struct module *owner;
 
         int id;
@@ -145,7 +144,6 @@ struct rtc_device
         const struct rtc_class_ops *ops;
         struct mutex ops_lock;
 
-        struct class_device *rtc_dev;
         struct cdev char_dev;
         struct mutex char_lock;
 
@@ -169,35 +167,34 @@ struct rtc_device
         unsigned int uie_timer_active:1;
 #endif
 };
-#define to_rtc_device(d) container_of(d, struct rtc_device, class_dev)
+#define to_rtc_device(d) container_of(d, struct rtc_device, dev)
 
 extern struct rtc_device *rtc_device_register(const char *name,
                                         struct device *dev,
                                         const struct rtc_class_ops *ops,
                                         struct module *owner);
-extern void rtc_device_unregister(struct rtc_device *rdev);
-extern int rtc_interface_register(struct class_interface *intf);
+extern void rtc_device_unregister(struct rtc_device *rtc);
 
-extern int rtc_read_time(struct class_device *class_dev, struct rtc_time *tm);
-extern int rtc_set_time(struct class_device *class_dev, struct rtc_time *tm);
-extern int rtc_set_mmss(struct class_device *class_dev, unsigned long secs);
-extern int rtc_read_alarm(struct class_device *class_dev,
+extern int rtc_read_time(struct rtc_device *rtc, struct rtc_time *tm);
+extern int rtc_set_time(struct rtc_device *rtc, struct rtc_time *tm);
+extern int rtc_set_mmss(struct rtc_device *rtc, unsigned long secs);
+extern int rtc_read_alarm(struct rtc_device *rtc,
                         struct rtc_wkalrm *alrm);
-extern int rtc_set_alarm(struct class_device *class_dev,
+extern int rtc_set_alarm(struct rtc_device *rtc,
                                 struct rtc_wkalrm *alrm);
-extern void rtc_update_irq(struct class_device *class_dev,
+extern void rtc_update_irq(struct rtc_device *rtc,
                         unsigned long num, unsigned long events);
 
-extern struct class_device *rtc_class_open(char *name);
-extern void rtc_class_close(struct class_device *class_dev);
+extern struct rtc_device *rtc_class_open(char *name);
+extern void rtc_class_close(struct rtc_device *rtc);
 
-extern int rtc_irq_register(struct class_device *class_dev,
+extern int rtc_irq_register(struct rtc_device *rtc,
                                 struct rtc_task *task);
-extern void rtc_irq_unregister(struct class_device *class_dev,
+extern void rtc_irq_unregister(struct rtc_device *rtc,
                                 struct rtc_task *task);
-extern int rtc_irq_set_state(struct class_device *class_dev,
+extern int rtc_irq_set_state(struct rtc_device *rtc,
                                 struct rtc_task *task, int enabled);
-extern int rtc_irq_set_freq(struct class_device *class_dev,
+extern int rtc_irq_set_freq(struct rtc_device *rtc,
                                 struct rtc_task *task, int freq);
 
 typedef struct rtc_task {
diff --git a/include/linux/sched.h b/include/linux/sched.h
index a1707583de49..3d95c480f58d 100644
--- a/include/linux/sched.h
+++ b/include/linux/sched.h
@@ -194,6 +194,14 @@ extern void sched_init_smp(void);
 extern void init_idle(struct task_struct *idle, int cpu);
 
 extern cpumask_t nohz_cpu_mask;
+#if defined(CONFIG_SMP) && defined(CONFIG_NO_HZ)
+extern int select_nohz_load_balancer(int cpu);
+#else
+static inline int select_nohz_load_balancer(int cpu)
+{
+        return 0;
+}
+#endif
 
 /*
  * Only dump TASK_* tasks. (0 for all tasks)
@@ -226,6 +234,7 @@ extern void scheduler_tick(void);
 extern void softlockup_tick(void);
 extern void spawn_softlockup_task(void);
 extern void touch_softlockup_watchdog(void);
+extern void touch_all_softlockup_watchdogs(void);
 #else
 static inline void softlockup_tick(void)
 {
@@ -236,6 +245,9 @@ static inline void spawn_softlockup_task(void)
 static inline void touch_softlockup_watchdog(void)
 {
 }
+static inline void touch_all_softlockup_watchdogs(void)
+{
+}
 #endif
 
 
@@ -668,8 +680,14 @@ struct sched_group {
         /*
          * CPU power of this group, SCHED_LOAD_SCALE being max power for a
          * single CPU. This is read only (except for setup, hotplug CPU).
+         * Note : Never change cpu_power without recompute its reciprocal
+         */
+        unsigned int __cpu_power;
+        /*
+         * reciprocal value of cpu_power to avoid expensive divides
+         * (see include/linux/reciprocal_div.h)
          */
-        unsigned long cpu_power;
+        u32 reciprocal_cpu_power;
 };
 
 struct sched_domain {
@@ -801,8 +819,8 @@ struct task_struct {
         volatile long state;    /* -1 unrunnable, 0 runnable, >0 stopped */
         struct thread_info *thread_info;
         atomic_t usage;
-        unsigned long flags;    /* per process flags, defined below */
-        unsigned long ptrace;
+        unsigned int flags;     /* per process flags, defined below */
+        unsigned int ptrace;
 
         int lock_depth;         /* BKL lock depth */
 
@@ -825,7 +843,7 @@ struct task_struct {
         unsigned long long sched_time; /* sched_clock time spent running */
         enum sleep_type sleep_type;
 
-        unsigned long policy;
+        unsigned int policy;
         cpumask_t cpus_allowed;
         unsigned int time_slice, first_time_slice;
 
@@ -845,11 +863,11 @@ struct task_struct {
 
 /* task state */
         struct linux_binfmt *binfmt;
-        long exit_state;
+        int exit_state;
         int exit_code, exit_signal;
         int pdeath_signal;  /*  The signal sent when the parent dies  */
         /* ??? */
-        unsigned long personality;
+        unsigned int personality;
         unsigned did_exec:1;
         pid_t pid;
         pid_t tgid;
@@ -881,7 +899,7 @@ struct task_struct {
         int __user *set_child_tid;              /* CLONE_CHILD_SETTID */
         int __user *clear_child_tid;            /* CLONE_CHILD_CLEARTID */
 
-        unsigned long rt_priority;
+        unsigned int rt_priority;
         cputime_t utime, stime;
         unsigned long nvcsw, nivcsw; /* context switch counts */
         struct timespec start_time;
@@ -1641,10 +1659,7 @@ static inline void arch_pick_mmap_layout(struct mm_struct *mm)
 extern long sched_setaffinity(pid_t pid, cpumask_t new_mask);
 extern long sched_getaffinity(pid_t pid, cpumask_t *mask);
 
-#include <linux/sysdev.h>
 extern int sched_mc_power_savings, sched_smt_power_savings;
-extern struct sysdev_attribute attr_sched_mc_power_savings, attr_sched_smt_power_savings;
-extern int sched_create_sysfs_power_savings_entries(struct sysdev_class *cls);
 
 extern void normalize_rt_tasks(void);
 
diff --git a/include/linux/serial_core.h b/include/linux/serial_core.h
index 586aaba91720..aa2653a159f4 100644
--- a/include/linux/serial_core.h
+++ b/include/linux/serial_core.h
@@ -39,7 +39,8 @@
 #define PORT_RSA        13
 #define PORT_NS16550A   14
 #define PORT_XSCALE     15
-#define PORT_MAX_8250   15      /* max port ID */
+#define PORT_RM9000     16      /* PMC-Sierra RM9xxx internal UART */
+#define PORT_MAX_8250   16      /* max port ID */
 
 /*
  * ARM specific type numbers.  These are not currently guaranteed
@@ -135,6 +136,9 @@
 /* Xilinx uartlite */
 #define PORT_UARTLITE   74
 
+/* Blackfin bf5xx */
+#define PORT_BFIN       75
+
 #ifdef __KERNEL__
 
 #include <linux/compiler.h>
@@ -230,6 +234,8 @@ struct uart_port {
 #define UPIO_MEM32              (3)
 #define UPIO_AU                 (4)                     /* Au1x00 type IO */
 #define UPIO_TSI                (5)                     /* Tsi108/109 type IO */
+#define UPIO_DWAPB              (6)                     /* DesignWare APB UART */
+#define UPIO_RM9000             (7)                     /* RM9000 type IO */
 
         unsigned int            read_status_mask;       /* driver specific */
         unsigned int            ignore_status_mask;     /* driver specific */
@@ -260,6 +266,7 @@ struct uart_port {
 #define UPF_CONS_FLOW           ((__force upf_t) (1 << 23))
 #define UPF_SHARE_IRQ           ((__force upf_t) (1 << 24))
 #define UPF_BOOT_AUTOCONF       ((__force upf_t) (1 << 28))
+#define UPF_FIXED_PORT          ((__force upf_t) (1 << 29))
 #define UPF_DEAD                ((__force upf_t) (1 << 30))
 #define UPF_IOREMAP             ((__force upf_t) (1 << 31))
 
@@ -276,6 +283,7 @@ struct uart_port {
         struct device           *dev;                   /* parent device */
         unsigned char           hub6;                   /* this should be in the 8250 driver */
         unsigned char           unused[3];
+        void                    *private_data;          /* generic platform data pointer */
 };
 
 /*
diff --git a/include/linux/serial_reg.h b/include/linux/serial_reg.h
index 3c8a6aa77415..1c5ed7d92b0f 100644
--- a/include/linux/serial_reg.h
+++ b/include/linux/serial_reg.h
@@ -38,6 +38,8 @@
 #define UART_IIR_RDI            0x04 /* Receiver data interrupt */
 #define UART_IIR_RLSI           0x06 /* Receiver line status interrupt */
 
+#define UART_IIR_BUSY           0x07 /* DesignWare APB Busy Detect */
+
 #define UART_FCR        2       /* Out: FIFO Control Register */
 #define UART_FCR_ENABLE_FIFO    0x01 /* Enable the FIFO */
 #define UART_FCR_CLEAR_RCVR     0x02 /* Clear the RCVR FIFO */
diff --git a/include/linux/slab.h b/include/linux/slab.h
index 1ef822e31c77..71829efc40ba 100644
--- a/include/linux/slab.h
+++ b/include/linux/slab.h
@@ -21,28 +21,25 @@ typedef struct kmem_cache kmem_cache_t __deprecated;
  * The ones marked DEBUG are only valid if CONFIG_SLAB_DEBUG is set.
  */
 #define SLAB_DEBUG_FREE         0x00000100UL    /* DEBUG: Perform (expensive) checks on free */
-#define SLAB_DEBUG_INITIAL      0x00000200UL    /* DEBUG: Call constructor (as verifier) */
 #define SLAB_RED_ZONE           0x00000400UL    /* DEBUG: Red zone objs in a cache */
 #define SLAB_POISON             0x00000800UL    /* DEBUG: Poison objects */
 #define SLAB_HWCACHE_ALIGN      0x00002000UL    /* Align objs on cache lines */
 #define SLAB_CACHE_DMA          0x00004000UL    /* Use GFP_DMA memory */
-#define SLAB_MUST_HWCACHE_ALIGN 0x00008000UL    /* Force alignment even if debuggin is active */
 #define SLAB_STORE_USER         0x00010000UL    /* DEBUG: Store the last owner for bug hunting */
 #define SLAB_RECLAIM_ACCOUNT    0x00020000UL    /* Objects are reclaimable */
 #define SLAB_PANIC              0x00040000UL    /* Panic if kmem_cache_create() fails */
 #define SLAB_DESTROY_BY_RCU     0x00080000UL    /* Defer freeing slabs to RCU */
 #define SLAB_MEM_SPREAD         0x00100000UL    /* Spread some memory over cpuset */
+#define SLAB_TRACE              0x00200000UL    /* Trace allocations and frees */
 
 /* Flags passed to a constructor functions */
 #define SLAB_CTOR_CONSTRUCTOR   0x001UL         /* If not set, then deconstructor */
-#define SLAB_CTOR_ATOMIC        0x002UL         /* Tell constructor it can't sleep */
-#define SLAB_CTOR_VERIFY        0x004UL         /* Tell constructor it's a verify call */
 
 /*
  * struct kmem_cache related prototypes
  */
 void __init kmem_cache_init(void);
-extern int slab_is_available(void);
+int slab_is_available(void);
 
 struct kmem_cache *kmem_cache_create(const char *, size_t, size_t,
                         unsigned long,
@@ -57,6 +54,18 @@ unsigned int kmem_cache_size(struct kmem_cache *);
 const char *kmem_cache_name(struct kmem_cache *);
 int kmem_ptr_validate(struct kmem_cache *cachep, const void *ptr);
 
+/*
+ * Please use this macro to create slab caches. Simply specify the
+ * name of the structure and maybe some flags that are listed above.
+ *
+ * The alignment of the struct determines object alignment. If you
+ * f.e. add ____cacheline_aligned_in_smp to the struct declaration
+ * then the objects will be properly aligned in SMP configurations.
+ */
+#define KMEM_CACHE(__struct, __flags) kmem_cache_create(#__struct,\
+                sizeof(struct __struct), __alignof__(struct __struct),\
+                (__flags), NULL, NULL)
+
 #ifdef CONFIG_NUMA
 extern void *kmem_cache_alloc_node(struct kmem_cache *, gfp_t flags, int node);
 #else
@@ -72,8 +81,9 @@ static inline void *kmem_cache_alloc_node(struct kmem_cache *cachep,
  */
 void *__kmalloc(size_t, gfp_t);
 void *__kzalloc(size_t, gfp_t);
+void * __must_check krealloc(const void *, size_t, gfp_t);
 void kfree(const void *);
-unsigned int ksize(const void *);
+size_t ksize(const void *);
 
 /**
  * kcalloc - allocate memory for an array. The memory is set to zero.
@@ -94,9 +104,14 @@ static inline void *kcalloc(size_t n, size_t size, gfp_t flags)
  * the appropriate general cache at compile time.
  */
 
-#ifdef CONFIG_SLAB
+#if defined(CONFIG_SLAB) || defined(CONFIG_SLUB)
+#ifdef CONFIG_SLUB
+#include <linux/slub_def.h>
+#else
 #include <linux/slab_def.h>
+#endif /* !CONFIG_SLUB */
 #else
+
 /*
  * Fallback definitions for an allocator not wanting to provide
  * its own optimized kmalloc definitions (like SLOB).
@@ -183,7 +198,7 @@ static inline void *__kmalloc_node(size_t size, gfp_t flags, int node)
  * allocator where we care about the real place the memory allocation
  * request comes from.
  */
-#ifdef CONFIG_DEBUG_SLAB
+#if defined(CONFIG_DEBUG_SLAB) || defined(CONFIG_SLUB)
 extern void *__kmalloc_track_caller(size_t, gfp_t, void*);
 #define kmalloc_track_caller(size, flags) \
         __kmalloc_track_caller(size, flags, __builtin_return_address(0))
@@ -201,7 +216,7 @@ extern void *__kmalloc_track_caller(size_t, gfp_t, void*);
  * standard allocator where we care about the real place the memory
  * allocation request comes from.
  */
-#ifdef CONFIG_DEBUG_SLAB
+#if defined(CONFIG_DEBUG_SLAB) || defined(CONFIG_SLUB)
 extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, void *);
 #define kmalloc_node_track_caller(size, flags, node) \
         __kmalloc_node_track_caller(size, flags, node, \
@@ -218,6 +233,9 @@ extern void *__kmalloc_node_track_caller(size_t, gfp_t, int, void *);
 
 #endif /* DEBUG_SLAB */
 
+extern const struct seq_operations slabinfo_op;
+ssize_t slabinfo_write(struct file *, const char __user *, size_t, loff_t *);
+
 #endif  /* __KERNEL__ */
 #endif  /* _LINUX_SLAB_H */
 
diff --git a/include/linux/slub_def.h b/include/linux/slub_def.h
new file mode 100644
index 000000000000..ea27065e80e6
--- /dev/null
+++ b/include/linux/slub_def.h
@@ -0,0 +1,206 @@
+#ifndef _LINUX_SLUB_DEF_H
+#define _LINUX_SLUB_DEF_H
+
+/*
+ * SLUB : A Slab allocator without object queues.
+ *
+ * (C) 2007 SGI, Christoph Lameter <clameter@sgi.com>
+ */
+#include <linux/types.h>
+#include <linux/gfp.h>
+#include <linux/workqueue.h>
+#include <linux/kobject.h>
+
+struct kmem_cache_node {
+        spinlock_t list_lock;   /* Protect partial list and nr_partial */
+        unsigned long nr_partial;
+        atomic_long_t nr_slabs;
+        struct list_head partial;
+        struct list_head full;
+};
+
+/*
+ * Slab cache management.
+ */
+struct kmem_cache {
+        /* Used for retriving partial slabs etc */
+        unsigned long flags;
+        int size;               /* The size of an object including meta data */
+        int objsize;            /* The size of an object without meta data */
+        int offset;             /* Free pointer offset. */
+        unsigned int order;
+
+        /*
+         * Avoid an extra cache line for UP, SMP and for the node local to
+         * struct kmem_cache.
+         */
+        struct kmem_cache_node local_node;
+
+        /* Allocation and freeing of slabs */
+        int objects;            /* Number of objects in slab */
+        int refcount;           /* Refcount for slab cache destroy */
+        void (*ctor)(void *, struct kmem_cache *, unsigned long);
+        void (*dtor)(void *, struct kmem_cache *, unsigned long);
+        int inuse;              /* Offset to metadata */
+        int align;              /* Alignment */
+        const char *name;       /* Name (only for display!) */
+        struct list_head list;  /* List of slab caches */
+        struct kobject kobj;    /* For sysfs */
+
+#ifdef CONFIG_NUMA
+        int defrag_ratio;
+        struct kmem_cache_node *node[MAX_NUMNODES];
+#endif
+        struct page *cpu_slab[NR_CPUS];
+};
+
+/*
+ * Kmalloc subsystem.
+ */
+#define KMALLOC_SHIFT_LOW 3
+
+#ifdef CONFIG_LARGE_ALLOCS
+#define KMALLOC_SHIFT_HIGH 25
+#else
+#if !defined(CONFIG_MMU) || NR_CPUS > 512 || MAX_NUMNODES > 256
+#define KMALLOC_SHIFT_HIGH 20
+#else
+#define KMALLOC_SHIFT_HIGH 18
+#endif
+#endif
+
+/*
+ * We keep the general caches in an array of slab caches that are used for
+ * 2^x bytes of allocations.
+ */
+extern struct kmem_cache kmalloc_caches[KMALLOC_SHIFT_HIGH + 1];
+
+/*
+ * Sorry that the following has to be that ugly but some versions of GCC
+ * have trouble with constant propagation and loops.
+ */
+static inline int kmalloc_index(int size)
+{
+        /*
+         * We should return 0 if size == 0 but we use the smallest object
+         * here for SLAB legacy reasons.
+         */
+        WARN_ON_ONCE(size == 0);
+
+        if (size > 64 && size <= 96)
+                return 1;
+        if (size > 128 && size <= 192)
+                return 2;
+        if (size <=          8) return 3;
+        if (size <=         16) return 4;
+        if (size <=         32) return 5;
+        if (size <=         64) return 6;
+        if (size <=        128) return 7;
+        if (size <=        256) return 8;
+        if (size <=        512) return 9;
+        if (size <=       1024) return 10;
+        if (size <=   2 * 1024) return 11;
+        if (size <=   4 * 1024) return 12;
+        if (size <=   8 * 1024) return 13;
+        if (size <=  16 * 1024) return 14;
+        if (size <=  32 * 1024) return 15;
+        if (size <=  64 * 1024) return 16;
+        if (size <= 128 * 1024) return 17;
+        if (size <= 256 * 1024) return 18;
+#if KMALLOC_SHIFT_HIGH > 18
+        if (size <=  512 * 1024) return 19;
+        if (size <= 1024 * 1024) return 20;
+#endif
+#if KMALLOC_SHIFT_HIGH > 20
+        if (size <=  2 * 1024 * 1024) return 21;
+        if (size <=  4 * 1024 * 1024) return 22;
+        if (size <=  8 * 1024 * 1024) return 23;
+        if (size <= 16 * 1024 * 1024) return 24;
+        if (size <= 32 * 1024 * 1024) return 25;
+#endif
+        return -1;
+
+/*
+ * What we really wanted to do and cannot do because of compiler issues is:
+ *      int i;
+ *      for (i = KMALLOC_SHIFT_LOW; i <= KMALLOC_SHIFT_HIGH; i++)
+ *              if (size <= (1 << i))
+ *                      return i;
+ */
+}
+
+/*
+ * Find the slab cache for a given combination of allocation flags and size.
+ *
+ * This ought to end up with a global pointer to the right cache
+ * in kmalloc_caches.
+ */
+static inline struct kmem_cache *kmalloc_slab(size_t size)
+{
+        int index = kmalloc_index(size);
+
+        if (index == 0)
+                return NULL;
+
+        if (index < 0) {
+                /*
+                 * Generate a link failure. Would be great if we could
+                 * do something to stop the compile here.
+                 */
+                extern void __kmalloc_size_too_large(void);
+                __kmalloc_size_too_large();
+        }
+        return &kmalloc_caches[index];
+}
+
+#ifdef CONFIG_ZONE_DMA
+#define SLUB_DMA __GFP_DMA
+#else
+/* Disable DMA functionality */
+#define SLUB_DMA 0
+#endif
+
+static inline void *kmalloc(size_t size, gfp_t flags)
+{
+        if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) {
+                struct kmem_cache *s = kmalloc_slab(size);
+
+                if (!s)
+                        return NULL;
+
+                return kmem_cache_alloc(s, flags);
+        } else
+                return __kmalloc(size, flags);
+}
+
+static inline void *kzalloc(size_t size, gfp_t flags)
+{
+        if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) {
+                struct kmem_cache *s = kmalloc_slab(size);
+
+                if (!s)
+                        return NULL;
+
+                return kmem_cache_zalloc(s, flags);
+        } else
+                return __kzalloc(size, flags);
+}
+
+#ifdef CONFIG_NUMA
+extern void *__kmalloc_node(size_t size, gfp_t flags, int node);
+
+static inline void *kmalloc_node(size_t size, gfp_t flags, int node)
+{
+        if (__builtin_constant_p(size) && !(flags & SLUB_DMA)) {
+                struct kmem_cache *s = kmalloc_slab(size);
+
+                if (!s)
+                        return NULL;
+
+                return kmem_cache_alloc_node(s, flags, node);
+        } else
+                return __kmalloc_node(size, flags, node);
+}
+#endif
+
+#endif /* _LINUX_SLUB_DEF_H */
diff --git a/include/linux/spi/Kbuild b/include/linux/spi/Kbuild
new file mode 100644
index 000000000000..d375a082986e
--- /dev/null
+++ b/include/linux/spi/Kbuild
@@ -0,0 +1 @@
+header-y += spidev.h
diff --git a/include/linux/spi/ad7877.h b/include/linux/spi/ad7877.h
new file mode 100644
index 000000000000..cdbed816f25e
--- /dev/null
+++ b/include/linux/spi/ad7877.h
@@ -0,0 +1,24 @@
+/* linux/spi/ad7877.h */
+
+/* Touchscreen characteristics vary between boards and models.  The
+ * platform_data for the device's "struct device" holds this information.
+ *
+ * It's OK if the min/max values are zero.
+ */
+struct ad7877_platform_data {
+        u16     model;                  /* 7877 */
+        u16     vref_delay_usecs;       /* 0 for external vref; etc */
+        u16     x_plate_ohms;
+        u16     y_plate_ohms;
+
+        u16     x_min, x_max;
+        u16     y_min, y_max;
+        u16     pressure_min, pressure_max;
+
+        u8      stopacq_polarity;       /* 1 = Active HIGH, 0 = Active LOW */
+        u8      first_conversion_delay; /* 0 = 0.5us, 1 = 128us, 2 = 1ms, 3 = 8ms */
+        u8      acquisition_time;       /* 0 = 2us, 1 = 4us, 2 = 8us, 3 = 16us */
+        u8      averaging;              /* 0 = 1, 1 = 4, 2 = 8, 3 = 16 */
+        u8      pen_down_acc_interval;  /* 0 = covert once, 1 = every 0.5 ms,
+                                           2 = ever 1 ms,   3 = every 8 ms,*/
+};
diff --git a/include/linux/spi/spi.h b/include/linux/spi/spi.h
index 4f0f8c2e58a5..b6bedc3ee95c 100644
--- a/include/linux/spi/spi.h
+++ b/include/linux/spi/spi.h
@@ -32,11 +32,12 @@ extern struct bus_type spi_bus_type;
  * @max_speed_hz: Maximum clock rate to be used with this chip
  *      (on this board); may be changed by the device's driver.
  *      The spi_transfer.speed_hz can override this for each transfer.
- * @chip-select: Chipselect, distinguishing chips handled by "master".
+ * @chip_select: Chipselect, distinguishing chips handled by @master.
  * @mode: The spi mode defines how data is clocked out and in.
  *      This may be changed by the device's driver.
- *      The "active low" default for chipselect mode can be overridden,
- *      as can the "MSB first" default for each word in a transfer.
+ *      The "active low" default for chipselect mode can be overridden
+ *      (by specifying SPI_CS_HIGH) as can the "MSB first" default for
+ *      each word in a transfer (by specifying SPI_LSB_FIRST).
  * @bits_per_word: Data transfers involve one or more words; word sizes
  *      like eight or 12 bits are common.  In-memory wordsizes are
  *      powers of two bytes (e.g. 20 bit samples use 32 bits).
@@ -48,14 +49,18 @@ extern struct bus_type spi_bus_type;
  * @controller_state: Controller's runtime state
  * @controller_data: Board-specific definitions for controller, such as
  *      FIFO initialization parameters; from board_info.controller_data
+ * @modalias: Name of the driver to use with this device, or an alias
+ *      for that name.  This appears in the sysfs "modalias" attribute
+ *      for driver coldplugging, and in uevents used for hotplugging
  *
- * An spi_device is used to interchange data between an SPI slave
+ * A @spi_device is used to interchange data between an SPI slave
  * (usually a discrete chip) and CPU memory.
  *
- * In "dev", the platform_data is used to hold information about this
+ * In @dev, the platform_data is used to hold information about this
  * device that's meaningful to the device's protocol driver, but not
  * to its controller.  One example might be an identifier for a chip
- * variant with slightly different functionality.
+ * variant with slightly different functionality; another might be
+ * information about how this particular board wires the chip's pins.
  */
 struct spi_device {
         struct device           dev;
@@ -77,13 +82,15 @@ struct spi_device {
         void                    *controller_data;
         const char              *modalias;
 
-        // likely need more hooks for more protocol options affecting how
-        // the controller talks to each chip, like:
-        //  - memory packing (12 bit samples into low bits, others zeroed)
-        //  - priority
-        //  - drop chipselect after each word
-        //  - chipselect delays
-        //  - ...
+        /*
+         * likely need more hooks for more protocol options affecting how
+         * the controller talks to each chip, like:
+         *  - memory packing (12 bit samples into low bits, others zeroed)
+         *  - priority
+         *  - drop chipselect after each word
+         *  - chipselect delays
+         *  - ...
+         */
 };
 
 static inline struct spi_device *to_spi_device(struct device *dev)
@@ -146,6 +153,11 @@ static inline struct spi_driver *to_spi_driver(struct device_driver *drv)
 
 extern int spi_register_driver(struct spi_driver *sdrv);
 
+/**
+ * spi_unregister_driver - reverse effect of spi_register_driver
+ * @sdrv: the driver to unregister
+ * Context: can sleep
+ */
 static inline void spi_unregister_driver(struct spi_driver *sdrv)
 {
         if (sdrv)
@@ -165,18 +177,20 @@ static inline void spi_unregister_driver(struct spi_driver *sdrv)
  * @setup: updates the device mode and clocking records used by a
  *      device's SPI controller; protocol code may call this.  This
  *      must fail if an unrecognized or unsupported mode is requested.
+ *      It's always safe to call this unless transfers are pending on
+ *      the device whose settings are being modified.
  * @transfer: adds a message to the controller's transfer queue.
  * @cleanup: frees controller-specific state
  *
- * Each SPI master controller can communicate with one or more spi_device
+ * Each SPI master controller can communicate with one or more @spi_device
  * children.  These make a small bus, sharing MOSI, MISO and SCK signals
  * but not chip select signals.  Each device may be configured to use a
  * different clock rate, since those shared signals are ignored unless
  * the chip is selected.
  *
  * The driver for an SPI controller manages access to those devices through
- * a queue of spi_message transactions, copyin data between CPU memory and
- * an SPI slave device).  For each such message it queues, it calls the
+ * a queue of spi_message transactions, copying data between CPU memory and
+ * an SPI slave device.  For each such message it queues, it calls the
  * message's completion function when the transaction completes.
  */
 struct spi_master {
@@ -280,27 +294,27 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
  * struct spi_transfer - a read/write buffer pair
  * @tx_buf: data to be written (dma-safe memory), or NULL
  * @rx_buf: data to be read (dma-safe memory), or NULL
- * @tx_dma: DMA address of tx_buf, if spi_message.is_dma_mapped
- * @rx_dma: DMA address of rx_buf, if spi_message.is_dma_mapped
+ * @tx_dma: DMA address of tx_buf, if @spi_message.is_dma_mapped
+ * @rx_dma: DMA address of rx_buf, if @spi_message.is_dma_mapped
  * @len: size of rx and tx buffers (in bytes)
  * @speed_hz: Select a speed other then the device default for this
- *      transfer. If 0 the default (from spi_device) is used.
+ *      transfer. If 0 the default (from @spi_device) is used.
  * @bits_per_word: select a bits_per_word other then the device default
- *      for this transfer. If 0 the default (from spi_device) is used.
+ *      for this transfer. If 0 the default (from @spi_device) is used.
  * @cs_change: affects chipselect after this transfer completes
  * @delay_usecs: microseconds to delay after this transfer before
  *      (optionally) changing the chipselect status, then starting
- *      the next transfer or completing this spi_message.
- * @transfer_list: transfers are sequenced through spi_message.transfers
+ *      the next transfer or completing this @spi_message.
+ * @transfer_list: transfers are sequenced through @spi_message.transfers
  *
  * SPI transfers always write the same number of bytes as they read.
- * Protocol drivers should always provide rx_buf and/or tx_buf.
+ * Protocol drivers should always provide @rx_buf and/or @tx_buf.
  * In some cases, they may also want to provide DMA addresses for
  * the data being transferred; that may reduce overhead, when the
  * underlying driver uses dma.
  *
  * If the transmit buffer is null, zeroes will be shifted out
- * while filling rx_buf.  If the receive buffer is null, the data
+ * while filling @rx_buf.  If the receive buffer is null, the data
  * shifted in will be discarded.  Only "len" bytes shift out (or in).
  * It's an error to try to shift out a partial word.  (For example, by
  * shifting out three bytes with word size of sixteen or twenty bits;
@@ -309,7 +323,7 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
  * In-memory data values are always in native CPU byte order, translated
  * from the wire byte order (big-endian except with SPI_LSB_FIRST).  So
  * for example when bits_per_word is sixteen, buffers are 2N bytes long
- * and hold N sixteen bit words in CPU byte order.
+ * (@len = 2N) and hold N sixteen bit words in CPU byte order.
  *
  * When the word size of the SPI transfer is not a power-of-two multiple
  * of eight bits, those in-memory words include extra bits.  In-memory
@@ -318,7 +332,7 @@ extern struct spi_master *spi_busnum_to_master(u16 busnum);
  *
  * All SPI transfers start with the relevant chipselect active.  Normally
  * it stays selected until after the last transfer in a message.  Drivers
- * can affect the chipselect signal using cs_change:
+ * can affect the chipselect signal using cs_change.
  *
  * (i) If the transfer isn't the last one in the message, this flag is
  * used to make the chipselect briefly go inactive in the middle of the
@@ -372,7 +386,7 @@ struct spi_transfer {
  * @queue: for use by whichever driver currently owns the message
  * @state: for use by whichever driver currently owns the message
  *
- * An spi_message is used to execute an atomic sequence of data transfers,
+ * A @spi_message is used to execute an atomic sequence of data transfers,
  * each represented by a struct spi_transfer.  The sequence is "atomic"
  * in the sense that no other spi_message may use that SPI bus until that
  * sequence completes.  On some systems, many such sequences can execute as
@@ -464,8 +478,9 @@ static inline void spi_message_free(struct spi_message *m)
 }
 
 /**
- * spi_setup -- setup SPI mode and clock rate
+ * spi_setup - setup SPI mode and clock rate
  * @spi: the device whose settings are being modified
+ * Context: can sleep
  *
  * SPI protocol drivers may need to update the transfer mode if the
  * device doesn't work with the mode 0 default.  They may likewise need
@@ -474,7 +489,7 @@ static inline void spi_message_free(struct spi_message *m)
  * The changes take effect the next time the device is selected and data
  * is transferred to or from it.
  *
- * Note that this call wil fail if the protocol driver specifies an option
+ * Note that this call will fail if the protocol driver specifies an option
  * that the underlying controller or its driver does not support.  For
  * example, not all hardware supports wire transfers using nine bit words,
  * LSB-first wire encoding, or active-high chipselects.
@@ -487,9 +502,10 @@ spi_setup(struct spi_device *spi)
 
 
 /**
- * spi_async -- asynchronous SPI transfer
+ * spi_async - asynchronous SPI transfer
  * @spi: device with which data will be exchanged
  * @message: describes the data transfers, including completion callback
+ * Context: any (irqs may be blocked, etc)
  *
  * This call may be used in_irq and other contexts which can't sleep,
  * as well as from task contexts which can sleep.
@@ -535,6 +551,7 @@ extern int spi_sync(struct spi_device *spi, struct spi_message *message);
  * @spi: device to which data will be written
  * @buf: data buffer
  * @len: data buffer size
+ * Context: can sleep
  *
  * This writes the buffer and returns zero or a negative error code.
  * Callable only from contexts that can sleep.
@@ -558,8 +575,9 @@ spi_write(struct spi_device *spi, const u8 *buf, size_t len)
  * @spi: device from which data will be read
  * @buf: data buffer
  * @len: data buffer size
+ * Context: can sleep
  *
- * This writes the buffer and returns zero or a negative error code.
+ * This reads the buffer and returns zero or a negative error code.
  * Callable only from contexts that can sleep.
  */
 static inline int
@@ -585,6 +603,7 @@ extern int spi_write_then_read(struct spi_device *spi,
  * spi_w8r8 - SPI synchronous 8 bit write followed by 8 bit read
  * @spi: device with which data will be exchanged
  * @cmd: command to be written before data is read back
+ * Context: can sleep
  *
  * This returns the (unsigned) eight bit number returned by the
  * device, or else a negative error code.  Callable only from
@@ -605,6 +624,7 @@ static inline ssize_t spi_w8r8(struct spi_device *spi, u8 cmd)
  * spi_w8r16 - SPI synchronous 8 bit write followed by 16 bit read
  * @spi: device with which data will be exchanged
  * @cmd: command to be written before data is read back
+ * Context: can sleep
  *
  * This returns the (unsigned) sixteen bit number returned by the
  * device, or else a negative error code.  Callable only from
diff --git a/include/linux/spi/spidev.h b/include/linux/spi/spidev.h
new file mode 100644
index 000000000000..7d700be57490
--- /dev/null
+++ b/include/linux/spi/spidev.h
@@ -0,0 +1,124 @@
+/*
+ * include/linux/spi/spidev.h
+ *
+ * Copyright (C) 2006 SWAPP
+ *      Andrea Paterniani <a.paterniani@swapp-eng.it>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
+  */
+
+#ifndef SPIDEV_H
+#define SPIDEV_H
+
+
+/* User space versions of kernel symbols for SPI clocking modes,
+ * matching <linux/spi/spi.h>
+ */
+
+#define SPI_CPHA                0x01
+#define SPI_CPOL                0x02
+
+#define SPI_MODE_0              (0|0)
+#define SPI_MODE_1              (0|SPI_CPHA)
+#define SPI_MODE_2              (SPI_CPOL|0)
+#define SPI_MODE_3              (SPI_CPOL|SPI_CPHA)
+
+
+/*---------------------------------------------------------------------------*/
+
+/* IOCTL commands */
+
+#define SPI_IOC_MAGIC                   'k'
+
+/**
+ * struct spi_ioc_transfer - describes a single SPI transfer
+ * @tx_buf: Holds pointer to userspace buffer with transmit data, or null.
+ *      If no data is provided, zeroes are shifted out.
+ * @rx_buf: Holds pointer to userspace buffer for receive data, or null.
+ * @len: Length of tx and rx buffers, in bytes.
+ * @speed_hz: Temporary override of the device's bitrate.
+ * @bits_per_word: Temporary override of the device's wordsize.
+ * @delay_usecs: If nonzero, how long to delay after the last bit transfer
+ *      before optionally deselecting the device before the next transfer.
+ * @cs_change: True to deselect device before starting the next transfer.
+ *
+ * This structure is mapped directly to the kernel spi_transfer structure;
+ * the fields have the same meanings, except of course that the pointers
+ * are in a different address space (and may be of different sizes in some
+ * cases, such as 32-bit i386 userspace over a 64-bit x86_64 kernel).
+ * Zero-initialize the structure, including currently unused fields, to
+ * accomodate potential future updates.
+ *
+ * SPI_IOC_MESSAGE gives userspace the equivalent of kernel spi_sync().
+ * Pass it an array of related transfers, they'll execute together.
+ * Each transfer may be half duplex (either direction) or full duplex.
+ *
+ *      struct spi_ioc_transfer mesg[4];
+ *      ...
+ *      status = ioctl(fd, SPI_IOC_MESSAGE(4), mesg);
+ *
+ * So for example one transfer might send a nine bit command (right aligned
+ * in a 16-bit word), the next could read a block of 8-bit data before
+ * terminating that command by temporarily deselecting the chip; the next
+ * could send a different nine bit command (re-selecting the chip), and the
+ * last transfer might write some register values.
+ */
+struct spi_ioc_transfer {
+        __u64           tx_buf;
+        __u64           rx_buf;
+
+        __u32           len;
+        __u32           speed_hz;
+
+        __u16           delay_usecs;
+        __u8            bits_per_word;
+        __u8            cs_change;
+        __u32           pad;
+
+        /* If the contents of 'struct spi_ioc_transfer' ever change
+         * incompatibly, then the ioctl number (currently 0) must change;
+         * ioctls with constant size fields get a bit more in the way of
+         * error checking than ones (like this) where that field varies.
+         *
+         * NOTE: struct layout is the same in 64bit and 32bit userspace.
+         */
+};
+
+/* not all platforms use <asm-generic/ioctl.h> or _IOC_TYPECHECK() ... */
+#define SPI_MSGSIZE(N) \
+        ((((N)*(sizeof (struct spi_ioc_transfer))) < (1 << _IOC_SIZEBITS)) \
+                ? ((N)*(sizeof (struct spi_ioc_transfer))) : 0)
+#define SPI_IOC_MESSAGE(N) _IOW(SPI_IOC_MAGIC, 0, char[SPI_MSGSIZE(N)])
+
+
+/* Read / Write of SPI mode (SPI_MODE_0..SPI_MODE_3) */
+#define SPI_IOC_RD_MODE                 _IOR(SPI_IOC_MAGIC, 1, __u8)
+#define SPI_IOC_WR_MODE                 _IOW(SPI_IOC_MAGIC, 1, __u8)
+
+/* Read / Write SPI bit justification */
+#define SPI_IOC_RD_LSB_FIRST            _IOR(SPI_IOC_MAGIC, 2, __u8)
+#define SPI_IOC_WR_LSB_FIRST            _IOW(SPI_IOC_MAGIC, 2, __u8)
+
+/* Read / Write SPI device word length (1..N) */
+#define SPI_IOC_RD_BITS_PER_WORD        _IOR(SPI_IOC_MAGIC, 3, __u8)
+#define SPI_IOC_WR_BITS_PER_WORD        _IOW(SPI_IOC_MAGIC, 3, __u8)
+
+/* Read / Write SPI device default max speed hz */
+#define SPI_IOC_RD_MAX_SPEED_HZ         _IOR(SPI_IOC_MAGIC, 4, __u32)
+#define SPI_IOC_WR_MAX_SPEED_HZ         _IOW(SPI_IOC_MAGIC, 4, __u32)
+
+
+
+#endif /* SPIDEV_H */
diff --git a/include/linux/spinlock_types.h b/include/linux/spinlock_types.h
index dc5fb69e4de9..210549ba4ef4 100644
--- a/include/linux/spinlock_types.h
+++ b/include/linux/spinlock_types.h
@@ -85,6 +85,12 @@ typedef struct {
                                 RW_DEP_MAP_INIT(lockname) }
 #endif
 
+/*
+ * SPIN_LOCK_UNLOCKED and RW_LOCK_UNLOCKED defeat lockdep state tracking and
+ * are hence deprecated.
+ * Please use DEFINE_SPINLOCK()/DEFINE_RWLOCK() or
+ * __SPIN_LOCK_UNLOCKED()/__RW_LOCK_UNLOCKED() as appropriate.
+ */
 #define SPIN_LOCK_UNLOCKED      __SPIN_LOCK_UNLOCKED(old_style_spin_init)
 #define RW_LOCK_UNLOCKED        __RW_LOCK_UNLOCKED(old_style_rw_init)
 
diff --git a/include/linux/stacktrace.h b/include/linux/stacktrace.h
index 50e2b01e517c..1d2b084c0185 100644
--- a/include/linux/stacktrace.h
+++ b/include/linux/stacktrace.h
@@ -6,15 +6,13 @@ struct stack_trace {
         unsigned int nr_entries, max_entries;
         unsigned long *entries;
         int skip;       /* input argument: How many entries to skip */
-        int all_contexts; /* input argument: if true do than one stack */
 };
 
-extern void save_stack_trace(struct stack_trace *trace,
-                             struct task_struct *task);
+extern void save_stack_trace(struct stack_trace *trace);
 
 extern void print_stack_trace(struct stack_trace *trace, int spaces);
 #else
-# define save_stack_trace(trace, task)                  do { } while (0)
+# define save_stack_trace(trace)                        do { } while (0)
 # define print_stack_trace(trace)                       do { } while (0)
 #endif
 
diff --git a/include/linux/stat.h b/include/linux/stat.h
index 679ef0d70b6b..611c398dab72 100644
--- a/include/linux/stat.h
+++ b/include/linux/stat.h
@@ -53,6 +53,9 @@
 #define S_IWUGO         (S_IWUSR|S_IWGRP|S_IWOTH)
 #define S_IXUGO         (S_IXUSR|S_IXGRP|S_IXOTH)
 
+#define UTIME_NOW       ((1l << 30) - 1l)
+#define UTIME_OMIT      ((1l << 30) - 2l)
+
 #include <linux/types.h>
 #include <linux/time.h>
 
diff --git a/include/linux/suspend.h b/include/linux/suspend.h
index bf99bd49f8ef..9d2aa1a12aa0 100644
--- a/include/linux/suspend.h
+++ b/include/linux/suspend.h
@@ -1,13 +1,14 @@
 #ifndef _LINUX_SWSUSP_H
 #define _LINUX_SWSUSP_H
 
-#if defined(CONFIG_X86) || defined(CONFIG_FRV) || defined(CONFIG_PPC32)
+#if defined(CONFIG_X86) || defined(CONFIG_FRV) || defined(CONFIG_PPC32) || defined(CONFIG_PPC64)
 #include <asm/suspend.h>
 #endif
 #include <linux/swap.h>
 #include <linux/notifier.h>
 #include <linux/init.h>
 #include <linux/pm.h>
+#include <linux/mm.h>
 
 /* struct pbe is used for creating lists of pages that should be restored
  * atomically during the resume from disk, because the page frames they have
@@ -23,36 +24,32 @@ struct pbe {
 extern void drain_local_pages(void);
 extern void mark_free_pages(struct zone *zone);
 
-#ifdef CONFIG_PM
-/* kernel/power/swsusp.c */
-extern int software_suspend(void);
-
-#if defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE)
+#if defined(CONFIG_PM) && defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE)
 extern int pm_prepare_console(void);
 extern void pm_restore_console(void);
 #else
 static inline int pm_prepare_console(void) { return 0; }
 static inline void pm_restore_console(void) {}
-#endif /* defined(CONFIG_VT) && defined(CONFIG_VT_CONSOLE) */
+#endif
+
+#if defined(CONFIG_PM) && defined(CONFIG_SOFTWARE_SUSPEND)
+/* kernel/power/snapshot.c */
+extern void __init register_nosave_region(unsigned long, unsigned long);
+extern int swsusp_page_is_forbidden(struct page *);
+extern void swsusp_set_page_free(struct page *);
+extern void swsusp_unset_page_free(struct page *);
+extern unsigned long get_safe_page(gfp_t gfp_mask);
 #else
-static inline int software_suspend(void)
-{
-        printk("Warning: fake suspend called\n");
-        return -ENOSYS;
-}
-#endif /* CONFIG_PM */
+static inline void register_nosave_region(unsigned long b, unsigned long e) {}
+static inline int swsusp_page_is_forbidden(struct page *p) { return 0; }
+static inline void swsusp_set_page_free(struct page *p) {}
+static inline void swsusp_unset_page_free(struct page *p) {}
+#endif /* defined(CONFIG_PM) && defined(CONFIG_SOFTWARE_SUSPEND) */
 
 void save_processor_state(void);
 void restore_processor_state(void);
 struct saved_context;
 void __save_processor_state(struct saved_context *ctxt);
 void __restore_processor_state(struct saved_context *ctxt);
-unsigned long get_safe_page(gfp_t gfp_mask);
-
-/*
- * XXX: We try to keep some more pages free so that I/O operations succeed
- * without paging. Might this be more?
- */
-#define PAGES_FOR_IO    1024
 
 #endif /* _LINUX_SWSUSP_H */
diff --git a/include/linux/svga.h b/include/linux/svga.h
index eadb981bb37c..e1cc552e04fe 100644
--- a/include/linux/svga.h
+++ b/include/linux/svga.h
@@ -112,6 +112,7 @@ void svga_tilecopy(struct fb_info *info, struct fb_tilearea *area);
 void svga_tilefill(struct fb_info *info, struct fb_tilerect *rect);
 void svga_tileblit(struct fb_info *info, struct fb_tileblit *blit);
 void svga_tilecursor(struct fb_info *info, struct fb_tilecursor *cursor);
+int svga_get_tilemax(struct fb_info *info);
 
 int svga_compute_pll(const struct svga_pll *pll, u32 f_wanted, u16 *m, u16 *n, u16 *r, int node);
 int svga_check_timings(const struct svga_timing_regs *tm, struct fb_var_screeninfo *var, int node);
diff --git a/include/linux/sysdev.h b/include/linux/sysdev.h
index 389ccf858d37..e699ab279c2c 100644
--- a/include/linux/sysdev.h
+++ b/include/linux/sysdev.h
@@ -22,6 +22,7 @@
 #define _SYSDEV_H_
 
 #include <linux/kobject.h>
+#include <linux/module.h>
 #include <linux/pm.h>
 
 
diff --git a/include/linux/tifm.h b/include/linux/tifm.h
index 2a196982601f..6b3a31805c72 100644
--- a/include/linux/tifm.h
+++ b/include/linux/tifm.h
@@ -63,6 +63,7 @@ enum {
 
 #define TIFM_CTRL_LED             0x00000040
 #define TIFM_CTRL_FAST_CLK        0x00000100
+#define TIFM_CTRL_POWER_MASK      0x00000007
 
 #define TIFM_SOCK_STATE_OCCUPIED  0x00000008
 #define TIFM_SOCK_STATE_POWERED   0x00000080
diff --git a/include/linux/time.h b/include/linux/time.h
index 8ea8dea713c7..dda9be685ab6 100644
--- a/include/linux/time.h
+++ b/include/linux/time.h
@@ -109,7 +109,7 @@ extern void do_gettimeofday(struct timeval *tv);
 extern int do_settimeofday(struct timespec *tv);
 extern int do_sys_settimeofday(struct timespec *tv, struct timezone *tz);
 #define do_posix_clock_monotonic_gettime(ts) ktime_get_ts(ts)
-extern long do_utimes(int dfd, char __user *filename, struct timeval *times);
+extern long do_utimes(int dfd, char __user *filename, struct timespec *times, int flags);
 struct itimerval;
 extern int do_setitimer(int which, struct itimerval *value,
                         struct itimerval *ovalue);
@@ -119,6 +119,7 @@ extern void getnstimeofday(struct timespec *tv);
 
 extern struct timespec timespec_trunc(struct timespec t, unsigned gran);
 extern int timekeeping_is_continuous(void);
+extern void update_wall_time(void);
 
 /**
  * timespec_to_ns - Convert timespec to nanoseconds
diff --git a/include/linux/timer.h b/include/linux/timer.h
index 719113b652dd..e0c5c16c992f 100644
--- a/include/linux/timer.h
+++ b/include/linux/timer.h
@@ -37,6 +37,7 @@ extern struct tvec_t_base_s boot_tvec_bases;
                 TIMER_INITIALIZER(_function, _expires, _data)
 
 void fastcall init_timer(struct timer_list * timer);
+void fastcall init_timer_deferrable(struct timer_list *timer);
 
 static inline void setup_timer(struct timer_list * timer,
                                 void (*function)(unsigned long),
diff --git a/include/linux/tty.h b/include/linux/tty.h
index dee72b9a20fb..bb4576085203 100644
--- a/include/linux/tty.h
+++ b/include/linux/tty.h
@@ -313,6 +313,7 @@ extern int tty_hung_up_p(struct file * filp);
 extern void do_SAK(struct tty_struct *tty);
 extern void __do_SAK(struct tty_struct *tty);
 extern void disassociate_ctty(int priv);
+extern void no_tty(void);
 extern void tty_flip_buffer_push(struct tty_struct *tty);
 extern speed_t tty_get_baud_rate(struct tty_struct *tty);
 extern speed_t tty_termios_baud_rate(struct ktermios *termios);
@@ -333,7 +334,6 @@ extern int tty_ioctl(struct inode *inode, struct file *file, unsigned int cmd,
 
 extern dev_t tty_devnum(struct tty_struct *tty);
 extern void proc_clear_tty(struct task_struct *p);
-extern void proc_set_tty(struct task_struct *tsk, struct tty_struct *tty);
 extern struct tty_struct *get_current_tty(void);
 
 extern struct mutex tty_mutex;
diff --git a/include/linux/uinput.h b/include/linux/uinput.h
index 1fd61eeed664..a6c1e8eed226 100644
--- a/include/linux/uinput.h
+++ b/include/linux/uinput.h
@@ -32,6 +32,8 @@
  *              - first public version
  */
 
+#include <linux/input.h>
+
 #define UINPUT_VERSION          3
 
 #ifdef __KERNEL__
diff --git a/include/linux/usb_sl811.h b/include/linux/usb_sl811.h
new file mode 100644
index 000000000000..4f2d012d7309
--- /dev/null
+++ b/include/linux/usb_sl811.h
@@ -0,0 +1,26 @@
+
+/*
+ * board initialization should put one of these into dev->platform_data
+ * and place the sl811hs onto platform_bus named "sl811-hcd".
+ */
+
+struct sl811_platform_data {
+        unsigned        can_wakeup:1;
+
+        /* given port_power, msec/2 after power on till power good */
+        u8              potpg;
+
+        /* mA/2 power supplied on this port (max = default = 250) */
+        u8              power;
+
+        /* sl811 relies on an external source of VBUS current */
+        void            (*port_power)(struct device *dev, int is_on);
+
+        /* pulse sl811 nRST (probably with a GPIO) */
+        void            (*reset)(struct device *dev);
+
+        // some boards need something like these:
+        // int          (*check_overcurrent)(struct device *dev);
+        // void         (*clock_enable)(struct device *dev, int is_on);
+};
+
diff --git a/include/linux/utsname.h b/include/linux/utsname.h
index e10267d402c5..f8d3b326e93a 100644
--- a/include/linux/utsname.h
+++ b/include/linux/utsname.h
@@ -49,9 +49,7 @@ static inline void get_uts_ns(struct uts_namespace *ns)
 }
 
 #ifdef CONFIG_UTS_NS
-extern int unshare_utsname(unsigned long unshare_flags,
-                                struct uts_namespace **new_uts);
-extern int copy_utsname(int flags, struct task_struct *tsk);
+extern struct uts_namespace *copy_utsname(int flags, struct uts_namespace *ns);
 extern void free_uts_ns(struct kref *kref);
 
 static inline void put_uts_ns(struct uts_namespace *ns)
@@ -59,21 +57,12 @@ static inline void put_uts_ns(struct uts_namespace *ns)
         kref_put(&ns->kref, free_uts_ns);
 }
 #else
-static inline int unshare_utsname(unsigned long unshare_flags,
-                        struct uts_namespace **new_uts)
+static inline struct uts_namespace *copy_utsname(int flags,
+                                                struct uts_namespace *ns)
 {
-        if (unshare_flags & CLONE_NEWUTS)
-                return -EINVAL;
-
-        return 0;
+        return ns;
 }
 
-static inline int copy_utsname(int flags, struct task_struct *tsk)
-{
-        if (flags & CLONE_NEWUTS)
-                return -EINVAL;
-        return 0;
-}
 static inline void put_uts_ns(struct uts_namespace *ns)
 {
 }
diff --git a/include/linux/vmalloc.h b/include/linux/vmalloc.h
index 924e502905d4..4b7ee83787c1 100644
--- a/include/linux/vmalloc.h
+++ b/include/linux/vmalloc.h
@@ -53,6 +53,7 @@ extern void vunmap(void *addr);
 
 extern int remap_vmalloc_range(struct vm_area_struct *vma, void *addr,
                                                         unsigned long pgoff);
+void vmalloc_sync_all(void);
  
 /*
  *      Lowlevel-APIs (not for driver use!)
diff --git a/include/linux/vt_kern.h b/include/linux/vt_kern.h
index e0db669998f3..d961635d0e61 100644
--- a/include/linux/vt_kern.h
+++ b/include/linux/vt_kern.h
@@ -9,6 +9,7 @@
 #include <linux/vt.h>
 #include <linux/kd.h>
 #include <linux/tty.h>
+#include <linux/mutex.h>
 #include <linux/console_struct.h>
 #include <linux/mm.h>
 
@@ -82,7 +83,7 @@ void reset_vc(struct vc_data *vc);
 
 #define CON_BUF_SIZE (CONFIG_BASE_SMALL ? 256 : PAGE_SIZE)
 extern char con_buf[CON_BUF_SIZE];
-extern struct semaphore con_buf_sem;
+extern struct mutex con_buf_mtx;
 extern char vt_dont_switch;
 
 struct vt_spawn_console {
diff --git a/include/linux/workqueue.h b/include/linux/workqueue.h
index b8abfc74d038..f16ba1e0687d 100644
--- a/include/linux/workqueue.h
+++ b/include/linux/workqueue.h
@@ -121,6 +121,12 @@ struct execute_work {
                 init_timer(&(_work)->timer);                    \
         } while (0)
 
+#define INIT_DELAYED_WORK_DEFERRABLE(_work, _func)                      \
+        do {                                                    \
+                INIT_WORK(&(_work)->work, (_func));             \
+                init_timer_deferrable(&(_work)->timer);         \
+        } while (0)
+
 /**
  * work_pending - Find out whether a work item is currently pending
  * @work: The work item in question
diff --git a/include/math-emu/extended.h b/include/math-emu/extended.h
deleted file mode 100644
index 84770fceb53e..000000000000
--- a/include/math-emu/extended.h
+++ /dev/null
@@ -1,396 +0,0 @@
-/* Software floating-point emulation.
-   Definitions for IEEE Extended Precision.
-   Copyright (C) 1999 Free Software Foundation, Inc.
-   This file is part of the GNU C Library.
-   Contributed by Jakub Jelinek (jj@ultra.linux.cz).
-
-   The GNU C Library is free software; you can redistribute it and/or
-   modify it under the terms of the GNU Library General Public License as
-   published by the Free Software Foundation; either version 2 of the
-   License, or (at your option) any later version.
-
-   The GNU C Library is distributed in the hope that it will be useful,
-   but WITHOUT ANY WARRANTY; without even the implied warranty of
-   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
-   Library General Public License for more details.
-
-   You should have received a copy of the GNU Library General Public
-   License along with the GNU C Library; see the file COPYING.LIB.  If
-   not, write to the Free Software Foundation, Inc.,
-   59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
-
-
-#ifndef    __MATH_EMU_EXTENDED_H__
-#define    __MATH_EMU_EXTENDED_H__
-
-#if _FP_W_TYPE_SIZE < 32
-#error "Here's a nickel, kid. Go buy yourself a real computer."
-#endif
-
-#if _FP_W_TYPE_SIZE < 64
-#define _FP_FRACTBITS_E         (4*_FP_W_TYPE_SIZE)
-#else
-#define _FP_FRACTBITS_E         (2*_FP_W_TYPE_SIZE)
-#endif
-
-#define _FP_FRACBITS_E          64
-#define _FP_FRACXBITS_E         (_FP_FRACTBITS_E - _FP_FRACBITS_E)
-#define _FP_WFRACBITS_E         (_FP_WORKBITS + _FP_FRACBITS_E)
-#define _FP_WFRACXBITS_E        (_FP_FRACTBITS_E - _FP_WFRACBITS_E)
-#define _FP_EXPBITS_E           15
-#define _FP_EXPBIAS_E           16383
-#define _FP_EXPMAX_E            32767
-
-#define _FP_QNANBIT_E           \
-        ((_FP_W_TYPE)1 << (_FP_FRACBITS_E-2) % _FP_W_TYPE_SIZE)
-#define _FP_IMPLBIT_E           \
-        ((_FP_W_TYPE)1 << (_FP_FRACBITS_E-1) % _FP_W_TYPE_SIZE)
-#define _FP_OVERFLOW_E          \
-        ((_FP_W_TYPE)1 << (_FP_WFRACBITS_E % _FP_W_TYPE_SIZE))
-
-#if _FP_W_TYPE_SIZE < 64
-
-union _FP_UNION_E
-{
-   long double flt;
-   struct 
-   {
-#if __BYTE_ORDER == __BIG_ENDIAN
-      unsigned long pad1 : _FP_W_TYPE_SIZE;
-      unsigned long pad2 : (_FP_W_TYPE_SIZE - 1 - _FP_EXPBITS_E);
-      unsigned long sign : 1;
-      unsigned long exp : _FP_EXPBITS_E;
-      unsigned long frac1 : _FP_W_TYPE_SIZE;
-      unsigned long frac0 : _FP_W_TYPE_SIZE;
-#else
-      unsigned long frac0 : _FP_W_TYPE_SIZE;
-      unsigned long frac1 : _FP_W_TYPE_SIZE;
-      unsigned exp : _FP_EXPBITS_E;
-      unsigned sign : 1;
-#endif /* not bigendian */
-   } bits __attribute__((packed));
-};
-
-
-#define FP_DECL_E(X)            _FP_DECL(4,X)
-
-#define FP_UNPACK_RAW_E(X, val)                         \
-  do {                                                  \
-    union _FP_UNION_E _flo; _flo.flt = (val);           \
-                                                        \
-    X##_f[2] = 0; X##_f[3] = 0;                         \
-    X##_f[0] = _flo.bits.frac0;                         \
-    X##_f[1] = _flo.bits.frac1;                         \
-    X##_e  = _flo.bits.exp;                             \
-    X##_s  = _flo.bits.sign;                            \
-    if (!X##_e && (X##_f[1] || X##_f[0])                \
-        && !(X##_f[1] & _FP_IMPLBIT_E))                 \
-      {                                                 \
-        X##_e++;                                        \
-        FP_SET_EXCEPTION(FP_EX_DENORM);                 \
-      }                                                 \
-  } while (0)
-
-#define FP_UNPACK_RAW_EP(X, val)                        \
-  do {                                                  \
-    union _FP_UNION_E *_flo =                           \
-    (union _FP_UNION_E *)(val);                         \
-                                                        \
-    X##_f[2] = 0; X##_f[3] = 0;                         \
-    X##_f[0] = _flo->bits.frac0;                        \
-    X##_f[1] = _flo->bits.frac1;                        \
-    X##_e  = _flo->bits.exp;                            \
-    X##_s  = _flo->bits.sign;                           \
-    if (!X##_e && (X##_f[1] || X##_f[0])                \
-        && !(X##_f[1] & _FP_IMPLBIT_E))                 \
-      {                                                 \
-        X##_e++;                                        \
-        FP_SET_EXCEPTION(FP_EX_DENORM);                 \
-      }                                                 \
-  } while (0)
-
-#define FP_PACK_RAW_E(val, X)                           \
-  do {                                                  \
-    union _FP_UNION_E _flo;                             \
-                                                        \
-    if (X##_e) X##_f[1] |= _FP_IMPLBIT_E;               \
-    else X##_f[1] &= ~(_FP_IMPLBIT_E);                  \
-    _flo.bits.frac0 = X##_f[0];                         \
-    _flo.bits.frac1 = X##_f[1];                         \
-    _flo.bits.exp   = X##_e;                            \
-    _flo.bits.sign  = X##_s;                            \
-                                                        \
-    (val) = _flo.flt;                                   \
-  } while (0)
-
-#define FP_PACK_RAW_EP(val, X)                          \
-  do {                                                  \
-    if (!FP_INHIBIT_RESULTS)                            \
-      {                                                 \
-        union _FP_UNION_E *_flo =                       \
-          (union _FP_UNION_E *)(val);                   \
-                                                        \
-        if (X##_e) X##_f[1] |= _FP_IMPLBIT_E;           \
-        else X##_f[1] &= ~(_FP_IMPLBIT_E);              \
-        _flo->bits.frac0 = X##_f[0];                    \
-        _flo->bits.frac1 = X##_f[1];                    \
-        _flo->bits.exp   = X##_e;                       \
-        _flo->bits.sign  = X##_s;                       \
-      }                                                 \
-  } while (0)
-
-#define FP_UNPACK_E(X,val)              \
-  do {                                  \
-    FP_UNPACK_RAW_E(X,val);             \
-    _FP_UNPACK_CANONICAL(E,4,X);        \
-  } while (0)
-
-#define FP_UNPACK_EP(X,val)             \
-  do {                                  \
-    FP_UNPACK_RAW_2_P(X,val);           \
-    _FP_UNPACK_CANONICAL(E,4,X);        \
-  } while (0)
-
-#define FP_PACK_E(val,X)                \
-  do {                                  \
-    _FP_PACK_CANONICAL(E,4,X);          \
-    FP_PACK_RAW_E(val,X);               \
-  } while (0)
-
-#define FP_PACK_EP(val,X)               \
-  do {                                  \
-    _FP_PACK_CANONICAL(E,4,X);          \
-    FP_PACK_RAW_EP(val,X);              \
-  } while (0)
-
-#define FP_ISSIGNAN_E(X)        _FP_ISSIGNAN(E,4,X)
-#define FP_NEG_E(R,X)           _FP_NEG(E,4,R,X)
-#define FP_ADD_E(R,X,Y)         _FP_ADD(E,4,R,X,Y)
-#define FP_SUB_E(R,X,Y)         _FP_SUB(E,4,R,X,Y)
-#define FP_MUL_E(R,X,Y)         _FP_MUL(E,4,R,X,Y)
-#define FP_DIV_E(R,X,Y)         _FP_DIV(E,4,R,X,Y)
-#define FP_SQRT_E(R,X)          _FP_SQRT(E,4,R,X)
-
-/*
- * Square root algorithms:
- * We have just one right now, maybe Newton approximation
- * should be added for those machines where division is fast.
- * This has special _E version because standard _4 square
- * root would not work (it has to start normally with the
- * second word and not the first), but as we have to do it
- * anyway, we optimize it by doing most of the calculations
- * in two UWtype registers instead of four.
- */
- 
-#define _FP_SQRT_MEAT_E(R, S, T, X, q)                  \
-  do {                                                  \
-    q = (_FP_W_TYPE)1 << (_FP_W_TYPE_SIZE - 1);         \
-    _FP_FRAC_SRL_4(X, (_FP_WORKBITS));                  \
-    while (q)                                           \
-      {                                                 \
-        T##_f[1] = S##_f[1] + q;                        \
-        if (T##_f[1] <= X##_f[1])                       \
-          {                                             \
-            S##_f[1] = T##_f[1] + q;                    \
-            X##_f[1] -= T##_f[1];                       \
-            R##_f[1] += q;                              \
-          }                                             \
-        _FP_FRAC_SLL_2(X, 1);                           \
-        q >>= 1;                                        \
-      }                                                 \
-    q = (_FP_W_TYPE)1 << (_FP_W_TYPE_SIZE - 1);         \
-    while (q)                                           \
-      {                                                 \
-        T##_f[0] = S##_f[0] + q;                        \
-        T##_f[1] = S##_f[1];                            \
-        if (T##_f[1] < X##_f[1] ||                      \
-            (T##_f[1] == X##_f[1] &&                    \
-             T##_f[0] <= X##_f[0]))                     \
-          {                                             \
-            S##_f[0] = T##_f[0] + q;                    \
-            S##_f[1] += (T##_f[0] > S##_f[0]);          \
-            _FP_FRAC_DEC_2(X, T);                       \
-            R##_f[0] += q;                              \
-          }                                             \
-        _FP_FRAC_SLL_2(X, 1);                           \
-        q >>= 1;                                        \
-      }                                                 \
-    _FP_FRAC_SLL_4(R, (_FP_WORKBITS));                  \
-    if (X##_f[0] | X##_f[1])                            \
-      {                                                 \
-        if (S##_f[1] < X##_f[1] ||                      \
-            (S##_f[1] == X##_f[1] &&                    \
-             S##_f[0] < X##_f[0]))                      \
-          R##_f[0] |= _FP_WORK_ROUND;                   \
-        R##_f[0] |= _FP_WORK_STICKY;                    \
-      }                                                 \
-  } while (0)
-
-#define FP_CMP_E(r,X,Y,un)      _FP_CMP(E,4,r,X,Y,un)
-#define FP_CMP_EQ_E(r,X,Y)      _FP_CMP_EQ(E,4,r,X,Y)
-
-#define FP_TO_INT_E(r,X,rsz,rsg)        _FP_TO_INT(E,4,r,X,rsz,rsg)
-#define FP_TO_INT_ROUND_E(r,X,rsz,rsg)  _FP_TO_INT_ROUND(E,4,r,X,rsz,rsg)
-#define FP_FROM_INT_E(X,r,rs,rt)        _FP_FROM_INT(E,4,X,r,rs,rt)
-
-#define _FP_FRAC_HIGH_E(X)      (X##_f[2])
-#define _FP_FRAC_HIGH_RAW_E(X)  (X##_f[1])
-
-#else   /* not _FP_W_TYPE_SIZE < 64 */
-union _FP_UNION_E
-{
-  long double flt /* __attribute__((mode(TF))) */ ;
-  struct {
-#if __BYTE_ORDER == __BIG_ENDIAN
-    unsigned long pad : (_FP_W_TYPE_SIZE - 1 - _FP_EXPBITS_E);
-    unsigned sign  : 1;
-    unsigned exp   : _FP_EXPBITS_E;
-    unsigned long frac : _FP_W_TYPE_SIZE;
-#else
-    unsigned long frac : _FP_W_TYPE_SIZE;
-    unsigned exp   : _FP_EXPBITS_E;
-    unsigned sign  : 1;
-#endif
-  } bits;
-};
-
-#define FP_DECL_E(X)            _FP_DECL(2,X)
-
-#define FP_UNPACK_RAW_E(X, val)                                 \
-  do {                                                          \
-    union _FP_UNION_E _flo; _flo.flt = (val);                   \
-                                                                \
-    X##_f0 = _flo.bits.frac;                                    \
-    X##_f1 = 0;                                                 \
-    X##_e = _flo.bits.exp;                                      \
-    X##_s = _flo.bits.sign;                                     \
-    if (!X##_e && X##_f0 && !(X##_f0 & _FP_IMPLBIT_E))          \
-      {                                                         \
-        X##_e++;                                                \
-        FP_SET_EXCEPTION(FP_EX_DENORM);                         \
-      }                                                         \
-  } while (0)
-
-#define FP_UNPACK_RAW_EP(X, val)                                \
-  do {                                                          \
-    union _FP_UNION_E *_flo =                                   \
-      (union _FP_UNION_E *)(val);                               \
-                                                                \
-    X##_f0 = _flo->bits.frac;                                   \
-    X##_f1 = 0;                                                 \
-    X##_e = _flo->bits.exp;                                     \
-    X##_s = _flo->bits.sign;                                    \
-    if (!X##_e && X##_f0 && !(X##_f0 & _FP_IMPLBIT_E))          \
-      {                                                         \
-        X##_e++;                                                \
-        FP_SET_EXCEPTION(FP_EX_DENORM);                         \
-      }                                                         \
-  } while (0)
-
-#define FP_PACK_RAW_E(val, X)                                   \
-  do {                                                          \
-    union _FP_UNION_E _flo;                                     \
-                                                                \
-    if (X##_e) X##_f0 |= _FP_IMPLBIT_E;                         \
-    else X##_f0 &= ~(_FP_IMPLBIT_E);                            \
-    _flo.bits.frac = X##_f0;                                    \
-    _flo.bits.exp  = X##_e;                                     \
-    _flo.bits.sign = X##_s;                                     \
-                                                                \
-    (val) = _flo.flt;                                           \
-  } while (0)
-
-#define FP_PACK_RAW_EP(fs, val, X)                              \
-  do {                                                          \
-    if (!FP_INHIBIT_RESULTS)                                    \
-      {                                                         \
-        union _FP_UNION_E *_flo =                               \
-          (union _FP_UNION_E *)(val);                           \
-                                                                \
-        if (X##_e) X##_f0 |= _FP_IMPLBIT_E;                     \
-        else X##_f0 &= ~(_FP_IMPLBIT_E);                        \
-        _flo->bits.frac = X##_f0;                               \
-        _flo->bits.exp  = X##_e;                                \
-        _flo->bits.sign = X##_s;                                \
-      }                                                         \
-  } while (0)
-
-
-#define FP_UNPACK_E(X,val)              \
-  do {                                  \
-    FP_UNPACK_RAW_E(X,val);             \
-    _FP_UNPACK_CANONICAL(E,2,X);        \
-  } while (0)
-
-#define FP_UNPACK_EP(X,val)             \
-  do {                                  \
-    FP_UNPACK_RAW_EP(X,val);            \
-    _FP_UNPACK_CANONICAL(E,2,X);        \
-  } while (0)
-
-#define FP_PACK_E(val,X)                \
-  do {                                  \
-    _FP_PACK_CANONICAL(E,2,X);          \
-    FP_PACK_RAW_E(val,X);               \
-  } while (0)
-
-#define FP_PACK_EP(val,X)               \
-  do {                                  \
-    _FP_PACK_CANONICAL(E,2,X);          \
-    FP_PACK_RAW_EP(val,X);              \
-  } while (0)
-
-#define FP_ISSIGNAN_E(X)        _FP_ISSIGNAN(E,2,X)
-#define FP_NEG_E(R,X)           _FP_NEG(E,2,R,X)
-#define FP_ADD_E(R,X,Y)         _FP_ADD(E,2,R,X,Y)
-#define FP_SUB_E(R,X,Y)         _FP_SUB(E,2,R,X,Y)
-#define FP_MUL_E(R,X,Y)         _FP_MUL(E,2,R,X,Y)
-#define FP_DIV_E(R,X,Y)         _FP_DIV(E,2,R,X,Y)
-#define FP_SQRT_E(R,X)          _FP_SQRT(E,2,R,X)
-
-/*
- * Square root algorithms:
- * We have just one right now, maybe Newton approximation
- * should be added for those machines where division is fast.
- * We optimize it by doing most of the calculations
- * in one UWtype registers instead of two, although we don't
- * have to.
- */
-#define _FP_SQRT_MEAT_E(R, S, T, X, q)                  \
-  do {                                                  \
-    q = (_FP_W_TYPE)1 << (_FP_W_TYPE_SIZE - 1);         \
-    _FP_FRAC_SRL_2(X, (_FP_WORKBITS));                  \
-    while (q)                                           \
-      {                                                 \
-        T##_f0 = S##_f0 + q;                            \
-        if (T##_f0 <= X##_f0)                           \
-          {                                             \
-            S##_f0 = T##_f0 + q;                        \
-            X##_f0 -= T##_f0;                           \
-            R##_f0 += q;                                \
-          }                                             \
-        _FP_FRAC_SLL_1(X, 1);                           \
-        q >>= 1;                                        \
-      }                                                 \
-    _FP_FRAC_SLL_2(R, (_FP_WORKBITS));                  \
-    if (X##_f0)                                         \
-      {                                                 \
-        if (S##_f0 < X##_f0)                            \
-          R##_f0 |= _FP_WORK_ROUND;                     \
-        R##_f0 |= _FP_WORK_STICKY;                      \
-      }                                                 \
-  } while (0)
- 
-#define FP_CMP_E(r,X,Y,un)      _FP_CMP(E,2,r,X,Y,un)
-#define FP_CMP_EQ_E(r,X,Y)      _FP_CMP_EQ(E,2,r,X,Y)
-
-#define FP_TO_INT_E(r,X,rsz,rsg)        _FP_TO_INT(E,2,r,X,rsz,rsg)
-#define FP_TO_INT_ROUND_E(r,X,rsz,rsg)  _FP_TO_INT_ROUND(E,2,r,X,rsz,rsg)
-#define FP_FROM_INT_E(X,r,rs,rt)        _FP_FROM_INT(E,2,X,r,rs,rt)
-
-#define _FP_FRAC_HIGH_E(X)      (X##_f1)
-#define _FP_FRAC_HIGH_RAW_E(X)  (X##_f0)
-
-#endif /* not _FP_W_TYPE_SIZE < 64 */
-
-#endif /* __MATH_EMU_EXTENDED_H__ */
diff --git a/include/net/sock.h b/include/net/sock.h
index 25c37e34bfdc..689b886038da 100644
--- a/include/net/sock.h
+++ b/include/net/sock.h
@@ -1361,15 +1361,6 @@ static inline void sock_valbool_flag(struct sock *sk, int bit, int valbool)
 extern __u32 sysctl_wmem_max;
 extern __u32 sysctl_rmem_max;
 
-#ifdef CONFIG_NET
-int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg);
-#else
-static inline int siocdevprivate_ioctl(unsigned int fd, unsigned int cmd, unsigned long arg)
-{
-        return -ENODEV;
-}
-#endif
-
 extern void sk_init(void);
 
 #ifdef CONFIG_SYSCTL
diff --git a/include/pcmcia/ds.h b/include/pcmcia/ds.h
index 8c339f5678cf..90ef552c42dd 100644
--- a/include/pcmcia/ds.h
+++ b/include/pcmcia/ds.h
@@ -108,6 +108,11 @@ typedef struct dev_node_t {
 struct pcmcia_socket;
 struct config_t;
 
+struct pcmcia_dynids {
+        spinlock_t              lock;
+        struct list_head        list;
+};
+
 struct pcmcia_driver {
         int (*probe)            (struct pcmcia_device *dev);
         void (*remove)          (struct pcmcia_device *dev);
@@ -118,6 +123,7 @@ struct pcmcia_driver {
         struct module           *owner;
         struct pcmcia_device_id *id_table;
         struct device_driver    drv;
+        struct pcmcia_dynids    dynids;
 };
 
 /* driver registration */
diff --git a/include/rdma/ib_verbs.h b/include/rdma/ib_verbs.h
index 765589f4d166..5342ac64ed1a 100644
--- a/include/rdma/ib_verbs.h
+++ b/include/rdma/ib_verbs.h
@@ -431,9 +431,11 @@ struct ib_wc {
         u8                      port_num;       /* valid only for DR SMPs on switches */
 };
 
-enum ib_cq_notify {
-        IB_CQ_SOLICITED,
-        IB_CQ_NEXT_COMP
+enum ib_cq_notify_flags {
+        IB_CQ_SOLICITED                 = 1 << 0,
+        IB_CQ_NEXT_COMP                 = 1 << 1,
+        IB_CQ_SOLICITED_MASK            = IB_CQ_SOLICITED | IB_CQ_NEXT_COMP,
+        IB_CQ_REPORT_MISSED_EVENTS      = 1 << 2,
 };
 
 enum ib_srq_attr_mask {
@@ -912,6 +914,8 @@ struct ib_device {
 
         u32                           flags;
 
+        int                           num_comp_vectors;
+
         struct iw_cm_verbs           *iwcm;
 
         int                        (*query_device)(struct ib_device *device,
@@ -978,6 +982,7 @@ struct ib_device {
                                                 struct ib_recv_wr *recv_wr,
                                                 struct ib_recv_wr **bad_recv_wr);
         struct ib_cq *             (*create_cq)(struct ib_device *device, int cqe,
+                                                int comp_vector,
                                                 struct ib_ucontext *context,
                                                 struct ib_udata *udata);
         int                        (*destroy_cq)(struct ib_cq *cq);
@@ -987,7 +992,7 @@ struct ib_device {
                                               struct ib_wc *wc);
         int                        (*peek_cq)(struct ib_cq *cq, int wc_cnt);
         int                        (*req_notify_cq)(struct ib_cq *cq,
-                                                    enum ib_cq_notify cq_notify);
+                                                    enum ib_cq_notify_flags flags);
         int                        (*req_ncomp_notif)(struct ib_cq *cq,
                                                       int wc_cnt);
         struct ib_mr *             (*get_dma_mr)(struct ib_pd *pd,
@@ -1358,13 +1363,15 @@ static inline int ib_post_recv(struct ib_qp *qp,
  * @cq_context: Context associated with the CQ returned to the user via
  *   the associated completion and event handlers.
  * @cqe: The minimum size of the CQ.
+ * @comp_vector - Completion vector used to signal completion events.
+ *     Must be >= 0 and < context->num_comp_vectors.
  *
  * Users can examine the cq structure to determine the actual CQ size.
  */
 struct ib_cq *ib_create_cq(struct ib_device *device,
                            ib_comp_handler comp_handler,
                            void (*event_handler)(struct ib_event *, void *),
-                           void *cq_context, int cqe);
+                           void *cq_context, int cqe, int comp_vector);
 
 /**
  * ib_resize_cq - Modifies the capacity of the CQ.
@@ -1414,14 +1421,34 @@ int ib_peek_cq(struct ib_cq *cq, int wc_cnt);
 /**
  * ib_req_notify_cq - Request completion notification on a CQ.
  * @cq: The CQ to generate an event for.
- * @cq_notify: If set to %IB_CQ_SOLICITED, completion notification will
- *   occur on the next solicited event. If set to %IB_CQ_NEXT_COMP,
- *   notification will occur on the next completion.
+ * @flags:
+ *   Must contain exactly one of %IB_CQ_SOLICITED or %IB_CQ_NEXT_COMP
+ *   to request an event on the next solicited event or next work
+ *   completion at any type, respectively. %IB_CQ_REPORT_MISSED_EVENTS
+ *   may also be |ed in to request a hint about missed events, as
+ *   described below.
+ *
+ * Return Value:
+ *    < 0 means an error occurred while requesting notification
+ *   == 0 means notification was requested successfully, and if
+ *        IB_CQ_REPORT_MISSED_EVENTS was passed in, then no events
+ *        were missed and it is safe to wait for another event.  In
+ *        this case is it guaranteed that any work completions added
+ *        to the CQ since the last CQ poll will trigger a completion
+ *        notification event.
+ *    > 0 is only returned if IB_CQ_REPORT_MISSED_EVENTS was passed
+ *        in.  It means that the consumer must poll the CQ again to
+ *        make sure it is empty to avoid missing an event because of a
+ *        race between requesting notification and an entry being
+ *        added to the CQ.  This return value means it is possible
+ *        (but not guaranteed) that a work completion has been added
+ *        to the CQ since the last poll without triggering a
+ *        completion notification event.
  */
 static inline int ib_req_notify_cq(struct ib_cq *cq,
-                                   enum ib_cq_notify cq_notify)
+                                   enum ib_cq_notify_flags flags)
 {
-        return cq->device->req_notify_cq(cq, cq_notify);
+        return cq->device->req_notify_cq(cq, flags);
 }
 
 /**
diff --git a/include/video/mach64.h b/include/video/mach64.h
index 09a7f4a7289f..a8332e528ec1 100644
--- a/include/video/mach64.h
+++ b/include/video/mach64.h
@@ -885,6 +885,7 @@
 #define SDRAM                   4
 #define SGRAM                   5
 #define WRAM                    6
+#define SDRAM32                 6
 
 #define DAC_INTERNAL            0x00
 #define DAC_IBMRGB514           0x01
diff --git a/include/video/permedia2.h b/include/video/permedia2.h
index b95d36289336..9e49c9571ec3 100644
--- a/include/video/permedia2.h
+++ b/include/video/permedia2.h
@@ -154,6 +154,10 @@
 #define PM2VI_RD_CLK1_PRESCALE                          0x204
 #define PM2VI_RD_CLK1_FEEDBACK                          0x205
 #define PM2VI_RD_CLK1_POSTSCALE                         0x206
+#define PM2VI_RD_MCLK_CONTROL                           0x20D
+#define PM2VI_RD_MCLK_PRESCALE                          0x20E
+#define PM2VI_RD_MCLK_FEEDBACK                          0x20F
+#define PM2VI_RD_MCLK_POSTSCALE                         0x210
 #define PM2VI_RD_CURSOR_PALETTE                         0x303
 #define PM2VI_RD_CURSOR_PATTERN                         0x400
 
diff --git a/include/video/tgafb.h b/include/video/tgafb.h
index be2b3e94e251..03d0dbe293a8 100644
--- a/include/video/tgafb.h
+++ b/include/video/tgafb.h
@@ -39,6 +39,7 @@
 #define TGA_RASTEROP_REG                0x0034
 #define TGA_PIXELSHIFT_REG              0x0038
 #define TGA_DEEP_REG                    0x0050
+#define TGA_START_REG                   0x0054
 #define TGA_PIXELMASK_REG               0x005c
 #define TGA_CURSOR_BASE_REG             0x0060
 #define TGA_HORIZ_REG                   0x0064
@@ -140,7 +141,7 @@
 
 
 /*
- * Useful defines for managing the BT463 on the 24-plane TGAs
+ * Useful defines for managing the BT463 on the 24-plane TGAs/SFB+s
  */
 
 #define BT463_ADDR_LO           0x0
@@ -168,12 +169,35 @@
 #define BT463_WINDOW_TYPE_BASE  0x0300
 
 /*
+ * Useful defines for managing the BT459 on the 8-plane SFB+s
+ */
+
+#define BT459_ADDR_LO           0x0
+#define BT459_ADDR_HI           0x1
+#define BT459_REG_ACC           0x2
+#define BT459_PALETTE           0x3
+
+#define BT459_CUR_CLR_1         0x0181
+#define BT459_CUR_CLR_2         0x0182
+#define BT459_CUR_CLR_3         0x0183
+
+#define BT459_CMD_REG_0         0x0201
+#define BT459_CMD_REG_1         0x0202
+#define BT459_CMD_REG_2         0x0203
+
+#define BT459_READ_MASK         0x0204
+
+#define BT459_BLINK_MASK        0x0206
+
+#define BT459_CUR_CMD_REG       0x0300
+
+/*
  * The framebuffer driver private data.
  */
 
 struct tga_par {
-        /* PCI device.  */
-        struct pci_dev *pdev;
+        /* PCI/TC device.  */
+        struct device *dev;
 
         /* Device dependent information.  */
         void __iomem *tga_mem_base;
@@ -235,4 +259,21 @@ BT463_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
         TGA_WRITE_REG(par, m << 10 | v, TGA_RAMDAC_REG);
 }
 
+static inline void
+BT459_LOAD_ADDR(struct tga_par *par, u16 a)
+{
+        TGA_WRITE_REG(par, BT459_ADDR_LO << 2, TGA_RAMDAC_SETUP_REG);
+        TGA_WRITE_REG(par, a & 0xff, TGA_RAMDAC_REG);
+        TGA_WRITE_REG(par, BT459_ADDR_HI << 2, TGA_RAMDAC_SETUP_REG);
+        TGA_WRITE_REG(par, a >> 8, TGA_RAMDAC_REG);
+}
+
+static inline void
+BT459_WRITE(struct tga_par *par, u32 m, u16 a, u8 v)
+{
+        BT459_LOAD_ADDR(par, a);
+        TGA_WRITE_REG(par, m << 2, TGA_RAMDAC_SETUP_REG);
+        TGA_WRITE_REG(par, v, TGA_RAMDAC_REG);
+}
+
 #endif /* TGAFB_H */