1 files changed, 497 insertions, 0 deletions
diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h
new file mode 100644
index 000000000000..4ab2162db13b
--- /dev/null
+++ b/include/linux/mfd/asic3.h
@@ -0,0 +1,497 @@
+/*
+ * include/linux/mfd/asic3.h
+ *
+ * Compaq ASIC3 headers.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * Copyright 2001 Compaq Computer Corporation.
+ * Copyright 2007 OpendHand.
+ */
+#ifndef __ASIC3_H__
+#define __ASIC3_H__
+#include <linux/types.h>
+struct asic3 {
+        void __iomem *mapping;
+        unsigned int bus_shift;
+        unsigned int irq_nr;
+        unsigned int irq_base;
+        spinlock_t lock;
+        u16 irq_bothedge[4];
+        struct device *dev;
+};
+struct asic3_platform_data {
+        struct {
+                u32 dir;
+                u32 init;
+                u32 sleep_mask;
+                u32 sleep_out;
+                u32 batt_fault_out;
+                u32 sleep_conf;
+                u32 alt_function;
+        } gpio_a, gpio_b, gpio_c, gpio_d;
+        unsigned int bus_shift;
+        unsigned int irq_base;
+        struct platform_device **children;
+        unsigned int n_children;
+};
+int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio);
+void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
+#define ASIC3_NUM_GPIO_BANKS    4
+#define ASIC3_GPIOS_PER_BANK    16
+#define ASIC3_NUM_GPIOS         64
+#define ASIC3_NR_IRQS           ASIC3_NUM_GPIOS + 6
+#define ASIC3_GPIO_BANK_A       0
+#define ASIC3_GPIO_BANK_B       1
+#define ASIC3_GPIO_BANK_C       2
+#define ASIC3_GPIO_BANK_D       3
+#define ASIC3_GPIO(bank, gpio) \
+        ((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
+#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
+/* All offsets below are specified with this address bus shift */
+#define ASIC3_DEFAULT_ADDR_SHIFT 2
+#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
+#define ASIC3_GPIO_OFFSET(base, reg) \
+        (ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
+#define ASIC3_GPIO_A_Base      0x0000
+#define ASIC3_GPIO_B_Base      0x0100
+#define ASIC3_GPIO_C_Base      0x0200
+#define ASIC3_GPIO_D_Base      0x0300
+#define ASIC3_GPIO_Mask          0x00    /* R/W 0:don't mask */
+#define ASIC3_GPIO_Direction     0x04    /* R/W 0:input */
+#define ASIC3_GPIO_Out           0x08    /* R/W 0:output low */
+#define ASIC3_GPIO_TriggerType   0x0c    /* R/W 0:level */
+#define ASIC3_GPIO_EdgeTrigger   0x10    /* R/W 0:falling */
+#define ASIC3_GPIO_LevelTrigger  0x14    /* R/W 0:low level detect */
+#define ASIC3_GPIO_SleepMask     0x18    /* R/W 0:don't mask in sleep mode */
+#define ASIC3_GPIO_SleepOut      0x1c    /* R/W level 0:low in sleep mode */
+#define ASIC3_GPIO_BattFaultOut  0x20    /* R/W level 0:low in batt_fault */
+#define ASIC3_GPIO_IntStatus     0x24    /* R/W 0:none, 1:detect */
+#define ASIC3_GPIO_AltFunction   0x28    /* R/W 1:LED register control */
+#define ASIC3_GPIO_SleepConf     0x2c    /*
+                                          * R/W bit 1: autosleep
+                                          * 0: disable gposlpout in normal mode,
+                                          * enable gposlpout in sleep mode.
+                                          */
+#define ASIC3_GPIO_Status        0x30    /* R   Pin status */
+#define ASIC3_SPI_Base                0x0400
+#define ASIC3_SPI_Control               0x0000
+#define ASIC3_SPI_TxData                0x0004
+#define ASIC3_SPI_RxData                0x0008
+#define ASIC3_SPI_Int                   0x000c
+#define ASIC3_SPI_Status                0x0010
+#define SPI_CONTROL_SPR(clk)      ((clk) & 0x0f)  /* Clock rate */
+#define ASIC3_PWM_0_Base                0x0500
+#define ASIC3_PWM_1_Base                0x0600
+#define ASIC3_PWM_TimeBase              0x0000
+#define ASIC3_PWM_PeriodTime            0x0004
+#define ASIC3_PWM_DutyTime              0x0008
+#define PWM_TIMEBASE_VALUE(x)    ((x)&0xf)   /* Low 4 bits sets time base */
+#define PWM_TIMEBASE_ENABLE     (1 << 4)   /* Enable clock */
+#define ASIC3_LED_0_Base                0x0700
+#define ASIC3_LED_1_Base                0x0800
+#define ASIC3_LED_2_Base                      0x0900
+#define ASIC3_LED_TimeBase              0x0000    /* R/W  7 bits */
+#define ASIC3_LED_PeriodTime            0x0004    /* R/W 12 bits */
+#define ASIC3_LED_DutyTime              0x0008    /* R/W 12 bits */
+#define ASIC3_LED_AutoStopCount         0x000c    /* R/W 16 bits */
+/* LED TimeBase bits - match ASIC2 */
+#define LED_TBS         0x0f /* Low 4 bits sets time base, max = 13 */
+                             /* Note: max = 5 on hx4700 */
+                             /* 0: maximum time base */
+                             /* 1: maximum time base / 2 */
+                             /* n: maximum time base / 2^n */
+#define LED_EN          (1 << 4) /* LED ON/OFF 0:off, 1:on */
+#define LED_AUTOSTOP    (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
+#define LED_ALWAYS      (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
+#define ASIC3_CLOCK_Base                0x0A00
+#define ASIC3_CLOCK_CDEX           0x00
+#define ASIC3_CLOCK_SEL            0x04
+#define CLOCK_CDEX_SOURCE       (1 << 0)  /* 2 bits */
+#define CLOCK_CDEX_SOURCE0      (1 << 0)
+#define CLOCK_CDEX_SOURCE1      (1 << 1)
+#define CLOCK_CDEX_SPI          (1 << 2)
+#define CLOCK_CDEX_OWM          (1 << 3)
+#define CLOCK_CDEX_PWM0         (1 << 4)
+#define CLOCK_CDEX_PWM1         (1 << 5)
+#define CLOCK_CDEX_LED0         (1 << 6)
+#define CLOCK_CDEX_LED1         (1 << 7)
+#define CLOCK_CDEX_LED2         (1 << 8)
+/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
+#define CLOCK_CDEX_SD_HOST      (1 << 9)   /* R/W: SD host clock source */
+#define CLOCK_CDEX_SD_BUS       (1 << 10)  /* R/W: SD bus clock source ctrl */
+#define CLOCK_CDEX_SMBUS        (1 << 11)
+#define CLOCK_CDEX_CONTROL_CX   (1 << 12)
+#define CLOCK_CDEX_EX0          (1 << 13)  /* R/W: 32.768 kHz crystal */
+#define CLOCK_CDEX_EX1          (1 << 14)  /* R/W: 24.576 MHz crystal */
+#define CLOCK_SEL_SD_HCLK_SEL   (1 << 0)   /* R/W: SDIO host clock select */
+#define CLOCK_SEL_SD_BCLK_SEL   (1 << 1)   /* R/W: SDIO bus clock select */
+/* R/W: INT clock source control (32.768 kHz) */
+#define CLOCK_SEL_CX            (1 << 2)
+#define ASIC3_INTR_Base         0x0B00
+#define ASIC3_INTR_IntMask       0x00  /* Interrupt mask control */
+#define ASIC3_INTR_PIntStat      0x04  /* Peripheral interrupt status */
+#define ASIC3_INTR_IntCPS        0x08  /* Interrupt timer clock pre-scale */
+#define ASIC3_INTR_IntTBS        0x0c  /* Interrupt timer set */
+#define ASIC3_INTMASK_GINTMASK    (1 << 0)  /* Global INTs mask 1:enable */
+#define ASIC3_INTMASK_GINTEL      (1 << 1)  /* 1: rising edge, 0: hi level */
+#define ASIC3_INTMASK_MASK0       (1 << 2)
+#define ASIC3_INTMASK_MASK1       (1 << 3)
+#define ASIC3_INTMASK_MASK2       (1 << 4)
+#define ASIC3_INTMASK_MASK3       (1 << 5)
+#define ASIC3_INTMASK_MASK4       (1 << 6)
+#define ASIC3_INTMASK_MASK5       (1 << 7)
+#define ASIC3_INTR_PERIPHERAL_A   (1 << 0)
+#define ASIC3_INTR_PERIPHERAL_B   (1 << 1)
+#define ASIC3_INTR_PERIPHERAL_C   (1 << 2)
+#define ASIC3_INTR_PERIPHERAL_D   (1 << 3)
+#define ASIC3_INTR_LED0           (1 << 4)
+#define ASIC3_INTR_LED1           (1 << 5)
+#define ASIC3_INTR_LED2           (1 << 6)
+#define ASIC3_INTR_SPI            (1 << 7)
+#define ASIC3_INTR_SMBUS          (1 << 8)
+#define ASIC3_INTR_OWM            (1 << 9)
+#define ASIC3_INTR_CPS(x)         ((x)&0x0f)    /* 4 bits, max 14 */
+#define ASIC3_INTR_CPS_SET        (1 << 4)    /* Time base enable */
+/* Basic control of the SD ASIC */
+#define ASIC3_SDHWCTRL_Base     0x0E00
+#define ASIC3_SDHWCTRL_SDConf    0x00
+#define ASIC3_SDHWCTRL_SUSPEND    (1 << 0)  /* 1=suspend all SD operations */
+#define ASIC3_SDHWCTRL_CLKSEL     (1 << 1)  /* 1=SDICK, 0=HCLK */
+#define ASIC3_SDHWCTRL_PCLR       (1 << 2)  /* All registers of SDIO cleared */
+#define ASIC3_SDHWCTRL_LEVCD      (1 << 3)  /* SD card detection: 0:low */
+/* SD card write protection: 0=high */
+#define ASIC3_SDHWCTRL_LEVWP      (1 << 4)
+#define ASIC3_SDHWCTRL_SDLED      (1 << 5)  /* SD card LED signal 0=disable */
+/* SD card power supply ctrl 1=enable */
+#define ASIC3_SDHWCTRL_SDPWR      (1 << 6)
+#define ASIC3_EXTCF_Base                0x1100
+#define ASIC3_EXTCF_Select         0x00
+#define ASIC3_EXTCF_Reset          0x04
+#define ASIC3_EXTCF_SMOD0                (1 << 0)  /* slot number of mode 0 */
+#define ASIC3_EXTCF_SMOD1                (1 << 1)  /* slot number of mode 1 */
+#define ASIC3_EXTCF_SMOD2                (1 << 2)  /* slot number of mode 2 */
+#define ASIC3_EXTCF_OWM_EN               (1 << 4)  /* enable onewire module */
+#define ASIC3_EXTCF_OWM_SMB              (1 << 5)  /* OWM bus selection */
+#define ASIC3_EXTCF_OWM_RESET            (1 << 6)  /* ?? used by OWM and CF */
+#define ASIC3_EXTCF_CF0_SLEEP_MODE       (1 << 7)  /* CF0 sleep state */
+#define ASIC3_EXTCF_CF1_SLEEP_MODE       (1 << 8)  /* CF1 sleep state */
+#define ASIC3_EXTCF_CF0_PWAIT_EN         (1 << 10) /* CF0 PWAIT_n control */
+#define ASIC3_EXTCF_CF1_PWAIT_EN         (1 << 11) /* CF1 PWAIT_n control */
+#define ASIC3_EXTCF_CF0_BUF_EN           (1 << 12) /* CF0 buffer control */
+#define ASIC3_EXTCF_CF1_BUF_EN           (1 << 13) /* CF1 buffer control */
+#define ASIC3_EXTCF_SD_MEM_ENABLE        (1 << 14)
+#define ASIC3_EXTCF_CF_SLEEP             (1 << 15) /* CF sleep mode control */
+/*********************************************
+ *  The Onewire interface registers
+ *
+ *  OWM_CMD
+ *  OWM_DAT
+ *  OWM_INTR
+ *  OWM_INTEN
+ *  OWM_CLKDIV
+ *
+ *********************************************/
+#define ASIC3_OWM_Base          0xC00
+#define ASIC3_OWM_CMD         0x00
+#define ASIC3_OWM_DAT         0x04
+#define ASIC3_OWM_INTR        0x08
+#define ASIC3_OWM_INTEN       0x0C
+#define ASIC3_OWM_CLKDIV      0x10
+#define ASIC3_OWM_CMD_ONEWR         (1 << 0)
+#define ASIC3_OWM_CMD_SRA           (1 << 1)
+#define ASIC3_OWM_CMD_DQO           (1 << 2)
+#define ASIC3_OWM_CMD_DQI           (1 << 3)
+#define ASIC3_OWM_INTR_PD          (1 << 0)
+#define ASIC3_OWM_INTR_PDR         (1 << 1)
+#define ASIC3_OWM_INTR_TBE         (1 << 2)
+#define ASIC3_OWM_INTR_TEMP        (1 << 3)
+#define ASIC3_OWM_INTR_RBF         (1 << 4)
+#define ASIC3_OWM_INTEN_EPD        (1 << 0)
+#define ASIC3_OWM_INTEN_IAS        (1 << 1)
+#define ASIC3_OWM_INTEN_ETBE       (1 << 2)
+#define ASIC3_OWM_INTEN_ETMT       (1 << 3)
+#define ASIC3_OWM_INTEN_ERBF       (1 << 4)
+#define ASIC3_OWM_CLKDIV_PRE       (3 << 0) /* two bits wide at bit 0 */
+#define ASIC3_OWM_CLKDIV_DIV       (7 << 2) /* 3 bits wide at bit 2 */
+/*****************************************************************************
+ *  The SD configuration registers are at a completely different location
+ *  in memory.  They are divided into three sets of registers:
+ *
+ *  SD_CONFIG         Core configuration register
+ *  SD_CTRL           Control registers for SD operations
+ *  SDIO_CTRL         Control registers for SDIO operations
+ *
+ *****************************************************************************/
+#define ASIC3_SD_CONFIG_Base            0x0400 /* Assumes 32 bit addressing */
+#define ASIC3_SD_CONFIG_Command           0x08   /* R/W: Command */
+/* [0:8] SD Control Register Base Address */
+#define ASIC3_SD_CONFIG_Addr0             0x20
+/* [9:31] SD Control Register Base Address */
+#define ASIC3_SD_CONFIG_Addr1             0x24
+/* R/O: interrupt assigned to pin */
+#define ASIC3_SD_CONFIG_IntPin            0x78
+/*
+ * Set to 0x1f to clock SD controller, 0 otherwise.
+ * At 0x82 - Gated Clock Ctrl
+ */
+#define ASIC3_SD_CONFIG_ClkStop           0x80
+/* Control clock of SD controller */
+#define ASIC3_SD_CONFIG_ClockMode         0x84
+#define ASIC3_SD_CONFIG_SDHC_PinStatus    0x88   /* R/0: SD pins status */
+#define ASIC3_SD_CONFIG_SDHC_Power1       0x90   /* Power1 - manual pwr ctrl */
+/* auto power up after card inserted */
+#define ASIC3_SD_CONFIG_SDHC_Power2       0x92
+/* auto power down when card removed */
+#define ASIC3_SD_CONFIG_SDHC_Power3       0x94
+#define ASIC3_SD_CONFIG_SDHC_CardDetect   0x98
+#define ASIC3_SD_CONFIG_SDHC_Slot         0xA0   /* R/O: support slot number */
+#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1  0x1E0  /* Not used */
+#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2  0x1E2  /* Not used*/
+/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
+#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable  0x1E8
+#define ASIC3_SD_CONFIG_SDHC_GPIO_Status  0x1EC  /* GPIO Status Reg. */
+/* Bit 1: double buffer/single buffer */
+#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3  0x1F0
+/* Memory access enable (set to 1 to access SD Controller) */
+#define SD_CONFIG_COMMAND_MAE                (1<<1)
+#define SD_CONFIG_CLK_ENABLE_ALL             0x1f
+#define SD_CONFIG_POWER1_PC_33V              0x0200    /* Set for 3.3 volts */
+#define SD_CONFIG_POWER1_PC_OFF              0x0000    /* Turn off power */
+ /* two bits - number of cycles for card detection */
+#define SD_CONFIG_CARDDETECTMODE_CLK           ((x) & 0x3)
+#define ASIC3_SD_CTRL_Base            0x1000
+#define ASIC3_SD_CTRL_Cmd                  0x00
+#define ASIC3_SD_CTRL_Arg0                 0x08
+#define ASIC3_SD_CTRL_Arg1                 0x0C
+#define ASIC3_SD_CTRL_StopInternal         0x10
+#define ASIC3_SD_CTRL_TransferSectorCount  0x14
+#define ASIC3_SD_CTRL_Response0            0x18
+#define ASIC3_SD_CTRL_Response1            0x1C
+#define ASIC3_SD_CTRL_Response2            0x20
+#define ASIC3_SD_CTRL_Response3            0x24
+#define ASIC3_SD_CTRL_Response4            0x28
+#define ASIC3_SD_CTRL_Response5            0x2C
+#define ASIC3_SD_CTRL_Response6            0x30
+#define ASIC3_SD_CTRL_Response7            0x34
+#define ASIC3_SD_CTRL_CardStatus           0x38
+#define ASIC3_SD_CTRL_BufferCtrl           0x3C
+#define ASIC3_SD_CTRL_IntMaskCard          0x40
+#define ASIC3_SD_CTRL_IntMaskBuffer        0x44
+#define ASIC3_SD_CTRL_CardClockCtrl        0x48
+#define ASIC3_SD_CTRL_MemCardXferDataLen   0x4C
+#define ASIC3_SD_CTRL_MemCardOptionSetup   0x50
+#define ASIC3_SD_CTRL_ErrorStatus0         0x58
+#define ASIC3_SD_CTRL_ErrorStatus1         0x5C
+#define ASIC3_SD_CTRL_DataPort             0x60
+#define ASIC3_SD_CTRL_TransactionCtrl      0x68
+#define ASIC3_SD_CTRL_SoftwareReset        0x1C0
+#define SD_CTRL_SOFTWARE_RESET_CLEAR            (1<<0)
+#define SD_CTRL_TRANSACTIONCONTROL_SET          (1<<8)
+#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD    (1<<15)
+#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK   (1<<8)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512    (1<<7)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256    (1<<6)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128    (1<<5)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64     (1<<4)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32     (1<<3)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16     (1<<2)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8      (1<<1)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4      (1<<0)
+#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2      (0<<0)
+#define MEM_CARD_OPTION_REQUIRED                   0x000e
+#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x)   (((x) & 0x0f) << 4)
+#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT      (1<<14)
+#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1           (1<<15)
+#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4           0
+#define SD_CTRL_COMMAND_INDEX(x)                   ((x) & 0x3f)
+#define SD_CTRL_COMMAND_TYPE_CMD                   (0 << 6)
+#define SD_CTRL_COMMAND_TYPE_ACMD                  (1 << 6)
+#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION        (2 << 6)
+#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL       (0 << 8)
+#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1       (4 << 8)
+#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B      (5 << 8)
+#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2       (6 << 8)
+#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3       (7 << 8)
+#define SD_CTRL_COMMAND_DATA_PRESENT               (1 << 11)
+#define SD_CTRL_COMMAND_TRANSFER_READ              (1 << 12)
+#define SD_CTRL_COMMAND_TRANSFER_WRITE             (0 << 12)
+#define SD_CTRL_COMMAND_MULTI_BLOCK                (1 << 13)
+#define SD_CTRL_COMMAND_SECURITY_CMD               (1 << 14)
+#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12         (1 << 0)
+#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12     (1 << 8)
+#define SD_CTRL_CARDSTATUS_RESPONSE_END            (1 << 0)
+#define SD_CTRL_CARDSTATUS_RW_END                  (1 << 2)
+#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0          (1 << 3)
+#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0         (1 << 4)
+#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0  (1 << 5)
+#define SD_CTRL_CARDSTATUS_WRITE_PROTECT           (1 << 7)
+#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3          (1 << 8)
+#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3         (1 << 9)
+#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3  (1 << 10)
+#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR       (1 << 0)
+#define SD_CTRL_BUFFERSTATUS_CRC_ERROR             (1 << 1)
+#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR    (1 << 2)
+#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT          (1 << 3)
+#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW       (1 << 4)
+#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW      (1 << 5)
+#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT           (1 << 6)
+#define SD_CTRL_BUFFERSTATUS_UNK7                  (1 << 7)
+#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE    (1 << 8)
+#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE   (1 << 9)
+#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION      (1 << 13)
+#define SD_CTRL_BUFFERSTATUS_CMD_BUSY              (1 << 14)
+#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS        (1 << 15)
+#define SD_CTRL_INTMASKCARD_RESPONSE_END           (1 << 0)
+#define SD_CTRL_INTMASKCARD_RW_END                 (1 << 2)
+#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0         (1 << 3)
+#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0        (1 << 4)
+#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
+#define SD_CTRL_INTMASKCARD_UNK6                   (1 << 6)
+#define SD_CTRL_INTMASKCARD_WRITE_PROTECT          (1 << 7)
+#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3         (1 << 8)
+#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3        (1 << 9)
+#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
+#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR      (1 << 0)
+#define SD_CTRL_INTMASKBUFFER_CRC_ERROR            (1 << 1)
+#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR   (1 << 2)
+#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT         (1 << 3)
+#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW      (1 << 4)
+#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW     (1 << 5)
+#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT          (1 << 6)
+#define SD_CTRL_INTMASKBUFFER_UNK7                 (1 << 7)
+#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE   (1 << 8)
+#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE  (1 << 9)
+#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION     (1 << 13)
+#define SD_CTRL_INTMASKBUFFER_CMD_BUSY             (1 << 14)
+#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS       (1 << 15)
+#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR                   (1 << 0)
+#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
+#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12     (1 << 3)
+#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA          (1 << 4)
+#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS   (1 << 5)
+#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12     (1 << 8)
+#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12         (1 << 9)
+#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA              (1 << 10)
+#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD              (1 << 11)
+#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE                      (1 << 0)
+#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA                    (1 << 4)
+#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS                   (1 << 5)
+#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY                     (1 << 6)
+#define ASIC3_SDIO_CTRL_Base          0x1200
+#define ASIC3_SDIO_CTRL_Cmd                  0x00
+#define ASIC3_SDIO_CTRL_CardPortSel          0x04
+#define ASIC3_SDIO_CTRL_Arg0                 0x08
+#define ASIC3_SDIO_CTRL_Arg1                 0x0C
+#define ASIC3_SDIO_CTRL_TransferBlockCount   0x14
+#define ASIC3_SDIO_CTRL_Response0            0x18
+#define ASIC3_SDIO_CTRL_Response1            0x1C
+#define ASIC3_SDIO_CTRL_Response2            0x20
+#define ASIC3_SDIO_CTRL_Response3            0x24
+#define ASIC3_SDIO_CTRL_Response4            0x28
+#define ASIC3_SDIO_CTRL_Response5            0x2C
+#define ASIC3_SDIO_CTRL_Response6            0x30
+#define ASIC3_SDIO_CTRL_Response7            0x34
+#define ASIC3_SDIO_CTRL_CardStatus           0x38
+#define ASIC3_SDIO_CTRL_BufferCtrl           0x3C
+#define ASIC3_SDIO_CTRL_IntMaskCard          0x40
+#define ASIC3_SDIO_CTRL_IntMaskBuffer        0x44
+#define ASIC3_SDIO_CTRL_CardXferDataLen      0x4C
+#define ASIC3_SDIO_CTRL_CardOptionSetup      0x50
+#define ASIC3_SDIO_CTRL_ErrorStatus0         0x54
+#define ASIC3_SDIO_CTRL_ErrorStatus1         0x58
+#define ASIC3_SDIO_CTRL_DataPort             0x60
+#define ASIC3_SDIO_CTRL_TransactionCtrl      0x68
+#define ASIC3_SDIO_CTRL_CardIntCtrl          0x6C
+#define ASIC3_SDIO_CTRL_ClocknWaitCtrl       0x70
+#define ASIC3_SDIO_CTRL_HostInformation      0x74
+#define ASIC3_SDIO_CTRL_ErrorCtrl            0x78
+#define ASIC3_SDIO_CTRL_LEDCtrl              0x7C
+#define ASIC3_SDIO_CTRL_SoftwareReset        0x1C0
+#define ASIC3_MAP_SIZE                       0x2000
+#endif /* __ASIC3_H__ */

diff --git a/include/linux/mfd/asic3.h b/include/linux/mfd/asic3.h new file mode 100644 index 000000000000..4ab2162db13b --- /dev/null +++ b/include/linux/mfd/asic3.h
@@ -0,0 +1,497 @@
	1	/*
	2	* include/linux/mfd/asic3.h
	3	*
	4	* Compaq ASIC3 headers.
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License version 2 as
	8	* published by the Free Software Foundation.
	9	*
	10	* Copyright 2001 Compaq Computer Corporation.
	11	* Copyright 2007 OpendHand.
	12	*/
	13
	14	#ifndef __ASIC3_H__
	15	#define __ASIC3_H__
	16
	17	#include <linux/types.h>
	18
	19	struct asic3 {
	20	void __iomem *mapping;
	21	unsigned int bus_shift;
	22	unsigned int irq_nr;
	23	unsigned int irq_base;
	24	spinlock_t lock;
	25	u16 irq_bothedge[4];
	26	struct device *dev;
	27	};
	28
	29	struct asic3_platform_data {
	30	struct {
	31	u32 dir;
	32	u32 init;
	33	u32 sleep_mask;
	34	u32 sleep_out;
	35	u32 batt_fault_out;
	36	u32 sleep_conf;
	37	u32 alt_function;
	38	} gpio_a, gpio_b, gpio_c, gpio_d;
	39
	40	unsigned int bus_shift;
	41
	42	unsigned int irq_base;
	43
	44	struct platform_device **children;
	45	unsigned int n_children;
	46	};
	47
	48	int asic3_gpio_get_value(struct asic3 *asic, unsigned gpio);
	49	void asic3_gpio_set_value(struct asic3 *asic, unsigned gpio, int val);
	50
	51	#define ASIC3_NUM_GPIO_BANKS 4
	52	#define ASIC3_GPIOS_PER_BANK 16
	53	#define ASIC3_NUM_GPIOS 64
	54	#define ASIC3_NR_IRQS ASIC3_NUM_GPIOS + 6
	55
	56	#define ASIC3_GPIO_BANK_A 0
	57	#define ASIC3_GPIO_BANK_B 1
	58	#define ASIC3_GPIO_BANK_C 2
	59	#define ASIC3_GPIO_BANK_D 3
	60
	61	#define ASIC3_GPIO(bank, gpio) \
	62	((ASIC3_GPIOS_PER_BANK * ASIC3_GPIO_BANK_##bank) + (gpio))
	63	#define ASIC3_GPIO_bit(gpio) (1 << (gpio & 0xf))
	64	/* All offsets below are specified with this address bus shift */
	65	#define ASIC3_DEFAULT_ADDR_SHIFT 2
	66
	67	#define ASIC3_OFFSET(base, reg) (ASIC3_##base##_Base + ASIC3_##base##_##reg)
	68	#define ASIC3_GPIO_OFFSET(base, reg) \
	69	(ASIC3_GPIO_##base##_Base + ASIC3_GPIO_##reg)
	70
	71	#define ASIC3_GPIO_A_Base 0x0000
	72	#define ASIC3_GPIO_B_Base 0x0100
	73	#define ASIC3_GPIO_C_Base 0x0200
	74	#define ASIC3_GPIO_D_Base 0x0300
	75
	76	#define ASIC3_GPIO_Mask 0x00 /* R/W 0:don't mask */
	77	#define ASIC3_GPIO_Direction 0x04 /* R/W 0:input */
	78	#define ASIC3_GPIO_Out 0x08 /* R/W 0:output low */
	79	#define ASIC3_GPIO_TriggerType 0x0c /* R/W 0:level */
	80	#define ASIC3_GPIO_EdgeTrigger 0x10 /* R/W 0:falling */
	81	#define ASIC3_GPIO_LevelTrigger 0x14 /* R/W 0:low level detect */
	82	#define ASIC3_GPIO_SleepMask 0x18 /* R/W 0:don't mask in sleep mode */
	83	#define ASIC3_GPIO_SleepOut 0x1c /* R/W level 0:low in sleep mode */
	84	#define ASIC3_GPIO_BattFaultOut 0x20 /* R/W level 0:low in batt_fault */
	85	#define ASIC3_GPIO_IntStatus 0x24 /* R/W 0:none, 1:detect */
	86	#define ASIC3_GPIO_AltFunction 0x28 /* R/W 1:LED register control */
	87	#define ASIC3_GPIO_SleepConf 0x2c /*
	88	* R/W bit 1: autosleep
	89	* 0: disable gposlpout in normal mode,
	90	* enable gposlpout in sleep mode.
	91	*/
	92	#define ASIC3_GPIO_Status 0x30 /* R Pin status */
	93
	94	#define ASIC3_SPI_Base 0x0400
	95	#define ASIC3_SPI_Control 0x0000
	96	#define ASIC3_SPI_TxData 0x0004
	97	#define ASIC3_SPI_RxData 0x0008
	98	#define ASIC3_SPI_Int 0x000c
	99	#define ASIC3_SPI_Status 0x0010
	100
	101	#define SPI_CONTROL_SPR(clk) ((clk) & 0x0f) /* Clock rate */
	102
	103	#define ASIC3_PWM_0_Base 0x0500
	104	#define ASIC3_PWM_1_Base 0x0600
	105	#define ASIC3_PWM_TimeBase 0x0000
	106	#define ASIC3_PWM_PeriodTime 0x0004
	107	#define ASIC3_PWM_DutyTime 0x0008
	108
	109	#define PWM_TIMEBASE_VALUE(x) ((x)&0xf) /* Low 4 bits sets time base */
	110	#define PWM_TIMEBASE_ENABLE (1 << 4) /* Enable clock */
	111
	112	#define ASIC3_LED_0_Base 0x0700
	113	#define ASIC3_LED_1_Base 0x0800
	114	#define ASIC3_LED_2_Base 0x0900
	115	#define ASIC3_LED_TimeBase 0x0000 /* R/W 7 bits */
	116	#define ASIC3_LED_PeriodTime 0x0004 /* R/W 12 bits */
	117	#define ASIC3_LED_DutyTime 0x0008 /* R/W 12 bits */
	118	#define ASIC3_LED_AutoStopCount 0x000c /* R/W 16 bits */
	119
	120	/* LED TimeBase bits - match ASIC2 */
	121	#define LED_TBS 0x0f /* Low 4 bits sets time base, max = 13 */
	122	/* Note: max = 5 on hx4700 */
	123	/* 0: maximum time base */
	124	/* 1: maximum time base / 2 */
	125	/* n: maximum time base / 2^n */
	126
	127	#define LED_EN (1 << 4) /* LED ON/OFF 0:off, 1:on */
	128	#define LED_AUTOSTOP (1 << 5) /* LED ON/OFF auto stop 0:disable, 1:enable */
	129	#define LED_ALWAYS (1 << 6) /* LED Interrupt Mask 0:No mask, 1:mask */
	130
	131	#define ASIC3_CLOCK_Base 0x0A00
	132	#define ASIC3_CLOCK_CDEX 0x00
	133	#define ASIC3_CLOCK_SEL 0x04
	134
	135	#define CLOCK_CDEX_SOURCE (1 << 0) /* 2 bits */
	136	#define CLOCK_CDEX_SOURCE0 (1 << 0)
	137	#define CLOCK_CDEX_SOURCE1 (1 << 1)
	138	#define CLOCK_CDEX_SPI (1 << 2)
	139	#define CLOCK_CDEX_OWM (1 << 3)
	140	#define CLOCK_CDEX_PWM0 (1 << 4)
	141	#define CLOCK_CDEX_PWM1 (1 << 5)
	142	#define CLOCK_CDEX_LED0 (1 << 6)
	143	#define CLOCK_CDEX_LED1 (1 << 7)
	144	#define CLOCK_CDEX_LED2 (1 << 8)
	145
	146	/* Clocks settings: 1 for 24.576 MHz, 0 for 12.288Mhz */
	147	#define CLOCK_CDEX_SD_HOST (1 << 9) /* R/W: SD host clock source */
	148	#define CLOCK_CDEX_SD_BUS (1 << 10) /* R/W: SD bus clock source ctrl */
	149	#define CLOCK_CDEX_SMBUS (1 << 11)
	150	#define CLOCK_CDEX_CONTROL_CX (1 << 12)
	151
	152	#define CLOCK_CDEX_EX0 (1 << 13) /* R/W: 32.768 kHz crystal */
	153	#define CLOCK_CDEX_EX1 (1 << 14) /* R/W: 24.576 MHz crystal */
	154
	155	#define CLOCK_SEL_SD_HCLK_SEL (1 << 0) /* R/W: SDIO host clock select */
	156	#define CLOCK_SEL_SD_BCLK_SEL (1 << 1) /* R/W: SDIO bus clock select */
	157
	158	/* R/W: INT clock source control (32.768 kHz) */
	159	#define CLOCK_SEL_CX (1 << 2)
	160
	161
	162	#define ASIC3_INTR_Base 0x0B00
	163
	164	#define ASIC3_INTR_IntMask 0x00 /* Interrupt mask control */
	165	#define ASIC3_INTR_PIntStat 0x04 /* Peripheral interrupt status */
	166	#define ASIC3_INTR_IntCPS 0x08 /* Interrupt timer clock pre-scale */
	167	#define ASIC3_INTR_IntTBS 0x0c /* Interrupt timer set */
	168
	169	#define ASIC3_INTMASK_GINTMASK (1 << 0) /* Global INTs mask 1:enable */
	170	#define ASIC3_INTMASK_GINTEL (1 << 1) /* 1: rising edge, 0: hi level */
	171	#define ASIC3_INTMASK_MASK0 (1 << 2)
	172	#define ASIC3_INTMASK_MASK1 (1 << 3)
	173	#define ASIC3_INTMASK_MASK2 (1 << 4)
	174	#define ASIC3_INTMASK_MASK3 (1 << 5)
	175	#define ASIC3_INTMASK_MASK4 (1 << 6)
	176	#define ASIC3_INTMASK_MASK5 (1 << 7)
	177
	178	#define ASIC3_INTR_PERIPHERAL_A (1 << 0)
	179	#define ASIC3_INTR_PERIPHERAL_B (1 << 1)
	180	#define ASIC3_INTR_PERIPHERAL_C (1 << 2)
	181	#define ASIC3_INTR_PERIPHERAL_D (1 << 3)
	182	#define ASIC3_INTR_LED0 (1 << 4)
	183	#define ASIC3_INTR_LED1 (1 << 5)
	184	#define ASIC3_INTR_LED2 (1 << 6)
	185	#define ASIC3_INTR_SPI (1 << 7)
	186	#define ASIC3_INTR_SMBUS (1 << 8)
	187	#define ASIC3_INTR_OWM (1 << 9)
	188
	189	#define ASIC3_INTR_CPS(x) ((x)&0x0f) /* 4 bits, max 14 */
	190	#define ASIC3_INTR_CPS_SET (1 << 4) /* Time base enable */
	191
	192
	193	/* Basic control of the SD ASIC */
	194	#define ASIC3_SDHWCTRL_Base 0x0E00
	195	#define ASIC3_SDHWCTRL_SDConf 0x00
	196
	197	#define ASIC3_SDHWCTRL_SUSPEND (1 << 0) /* 1=suspend all SD operations */
	198	#define ASIC3_SDHWCTRL_CLKSEL (1 << 1) /* 1=SDICK, 0=HCLK */
	199	#define ASIC3_SDHWCTRL_PCLR (1 << 2) /* All registers of SDIO cleared */
	200	#define ASIC3_SDHWCTRL_LEVCD (1 << 3) /* SD card detection: 0:low */
	201
	202	/* SD card write protection: 0=high */
	203	#define ASIC3_SDHWCTRL_LEVWP (1 << 4)
	204	#define ASIC3_SDHWCTRL_SDLED (1 << 5) /* SD card LED signal 0=disable */
	205
	206	/* SD card power supply ctrl 1=enable */
	207	#define ASIC3_SDHWCTRL_SDPWR (1 << 6)
	208
	209	#define ASIC3_EXTCF_Base 0x1100
	210
	211	#define ASIC3_EXTCF_Select 0x00
	212	#define ASIC3_EXTCF_Reset 0x04
	213
	214	#define ASIC3_EXTCF_SMOD0 (1 << 0) /* slot number of mode 0 */
	215	#define ASIC3_EXTCF_SMOD1 (1 << 1) /* slot number of mode 1 */
	216	#define ASIC3_EXTCF_SMOD2 (1 << 2) /* slot number of mode 2 */
	217	#define ASIC3_EXTCF_OWM_EN (1 << 4) /* enable onewire module */
	218	#define ASIC3_EXTCF_OWM_SMB (1 << 5) /* OWM bus selection */
	219	#define ASIC3_EXTCF_OWM_RESET (1 << 6) /* ?? used by OWM and CF */
	220	#define ASIC3_EXTCF_CF0_SLEEP_MODE (1 << 7) /* CF0 sleep state */
	221	#define ASIC3_EXTCF_CF1_SLEEP_MODE (1 << 8) /* CF1 sleep state */
	222	#define ASIC3_EXTCF_CF0_PWAIT_EN (1 << 10) /* CF0 PWAIT_n control */
	223	#define ASIC3_EXTCF_CF1_PWAIT_EN (1 << 11) /* CF1 PWAIT_n control */
	224	#define ASIC3_EXTCF_CF0_BUF_EN (1 << 12) /* CF0 buffer control */
	225	#define ASIC3_EXTCF_CF1_BUF_EN (1 << 13) /* CF1 buffer control */
	226	#define ASIC3_EXTCF_SD_MEM_ENABLE (1 << 14)
	227	#define ASIC3_EXTCF_CF_SLEEP (1 << 15) /* CF sleep mode control */
	228
	229	/*********************************************
	230	* The Onewire interface registers
	231	*
	232	* OWM_CMD
	233	* OWM_DAT
	234	* OWM_INTR
	235	* OWM_INTEN
	236	* OWM_CLKDIV
	237	*
	238	*********************************************/
	239
	240	#define ASIC3_OWM_Base 0xC00
	241
	242	#define ASIC3_OWM_CMD 0x00
	243	#define ASIC3_OWM_DAT 0x04
	244	#define ASIC3_OWM_INTR 0x08
	245	#define ASIC3_OWM_INTEN 0x0C
	246	#define ASIC3_OWM_CLKDIV 0x10
	247
	248	#define ASIC3_OWM_CMD_ONEWR (1 << 0)
	249	#define ASIC3_OWM_CMD_SRA (1 << 1)
	250	#define ASIC3_OWM_CMD_DQO (1 << 2)
	251	#define ASIC3_OWM_CMD_DQI (1 << 3)
	252
	253	#define ASIC3_OWM_INTR_PD (1 << 0)
	254	#define ASIC3_OWM_INTR_PDR (1 << 1)
	255	#define ASIC3_OWM_INTR_TBE (1 << 2)
	256	#define ASIC3_OWM_INTR_TEMP (1 << 3)
	257	#define ASIC3_OWM_INTR_RBF (1 << 4)
	258
	259	#define ASIC3_OWM_INTEN_EPD (1 << 0)
	260	#define ASIC3_OWM_INTEN_IAS (1 << 1)
	261	#define ASIC3_OWM_INTEN_ETBE (1 << 2)
	262	#define ASIC3_OWM_INTEN_ETMT (1 << 3)
	263	#define ASIC3_OWM_INTEN_ERBF (1 << 4)
	264
	265	#define ASIC3_OWM_CLKDIV_PRE (3 << 0) /* two bits wide at bit 0 */
	266	#define ASIC3_OWM_CLKDIV_DIV (7 << 2) /* 3 bits wide at bit 2 */
	267
	268
	269	/*****************************************************************************
	270	* The SD configuration registers are at a completely different location
	271	* in memory. They are divided into three sets of registers:
	272	*
	273	* SD_CONFIG Core configuration register
	274	* SD_CTRL Control registers for SD operations
	275	* SDIO_CTRL Control registers for SDIO operations
	276	*
	277	*****************************************************************************/
	278	#define ASIC3_SD_CONFIG_Base 0x0400 /* Assumes 32 bit addressing */
	279
	280	#define ASIC3_SD_CONFIG_Command 0x08 /* R/W: Command */
	281
	282	/* [0:8] SD Control Register Base Address */
	283	#define ASIC3_SD_CONFIG_Addr0 0x20
	284
	285	/* [9:31] SD Control Register Base Address */
	286	#define ASIC3_SD_CONFIG_Addr1 0x24
	287
	288	/* R/O: interrupt assigned to pin */
	289	#define ASIC3_SD_CONFIG_IntPin 0x78
	290
	291	/*
	292	* Set to 0x1f to clock SD controller, 0 otherwise.
	293	* At 0x82 - Gated Clock Ctrl
	294	*/
	295	#define ASIC3_SD_CONFIG_ClkStop 0x80
	296
	297	/* Control clock of SD controller */
	298	#define ASIC3_SD_CONFIG_ClockMode 0x84
	299	#define ASIC3_SD_CONFIG_SDHC_PinStatus 0x88 /* R/0: SD pins status */
	300	#define ASIC3_SD_CONFIG_SDHC_Power1 0x90 /* Power1 - manual pwr ctrl */
	301
	302	/* auto power up after card inserted */
	303	#define ASIC3_SD_CONFIG_SDHC_Power2 0x92
	304
	305	/* auto power down when card removed */
	306	#define ASIC3_SD_CONFIG_SDHC_Power3 0x94
	307	#define ASIC3_SD_CONFIG_SDHC_CardDetect 0x98
	308	#define ASIC3_SD_CONFIG_SDHC_Slot 0xA0 /* R/O: support slot number */
	309	#define ASIC3_SD_CONFIG_SDHC_ExtGateClk1 0x1E0 /* Not used */
	310	#define ASIC3_SD_CONFIG_SDHC_ExtGateClk2 0x1E2 /* Not used*/
	311
	312	/* GPIO Output Reg. , at 0x1EA - GPIO Output Enable Reg. */
	313	#define ASIC3_SD_CONFIG_SDHC_GPIO_OutAndEnable 0x1E8
	314	#define ASIC3_SD_CONFIG_SDHC_GPIO_Status 0x1EC /* GPIO Status Reg. */
	315
	316	/* Bit 1: double buffer/single buffer */
	317	#define ASIC3_SD_CONFIG_SDHC_ExtGateClk3 0x1F0
	318
	319	/* Memory access enable (set to 1 to access SD Controller) */
	320	#define SD_CONFIG_COMMAND_MAE (1<<1)
	321
	322	#define SD_CONFIG_CLK_ENABLE_ALL 0x1f
	323
	324	#define SD_CONFIG_POWER1_PC_33V 0x0200 /* Set for 3.3 volts */
	325	#define SD_CONFIG_POWER1_PC_OFF 0x0000 /* Turn off power */
	326
	327	/* two bits - number of cycles for card detection */
	328	#define SD_CONFIG_CARDDETECTMODE_CLK ((x) & 0x3)
	329
	330
	331	#define ASIC3_SD_CTRL_Base 0x1000
	332
	333	#define ASIC3_SD_CTRL_Cmd 0x00
	334	#define ASIC3_SD_CTRL_Arg0 0x08
	335	#define ASIC3_SD_CTRL_Arg1 0x0C
	336	#define ASIC3_SD_CTRL_StopInternal 0x10
	337	#define ASIC3_SD_CTRL_TransferSectorCount 0x14
	338	#define ASIC3_SD_CTRL_Response0 0x18
	339	#define ASIC3_SD_CTRL_Response1 0x1C
	340	#define ASIC3_SD_CTRL_Response2 0x20
	341	#define ASIC3_SD_CTRL_Response3 0x24
	342	#define ASIC3_SD_CTRL_Response4 0x28
	343	#define ASIC3_SD_CTRL_Response5 0x2C
	344	#define ASIC3_SD_CTRL_Response6 0x30
	345	#define ASIC3_SD_CTRL_Response7 0x34
	346	#define ASIC3_SD_CTRL_CardStatus 0x38
	347	#define ASIC3_SD_CTRL_BufferCtrl 0x3C
	348	#define ASIC3_SD_CTRL_IntMaskCard 0x40
	349	#define ASIC3_SD_CTRL_IntMaskBuffer 0x44
	350	#define ASIC3_SD_CTRL_CardClockCtrl 0x48
	351	#define ASIC3_SD_CTRL_MemCardXferDataLen 0x4C
	352	#define ASIC3_SD_CTRL_MemCardOptionSetup 0x50
	353	#define ASIC3_SD_CTRL_ErrorStatus0 0x58
	354	#define ASIC3_SD_CTRL_ErrorStatus1 0x5C
	355	#define ASIC3_SD_CTRL_DataPort 0x60
	356	#define ASIC3_SD_CTRL_TransactionCtrl 0x68
	357	#define ASIC3_SD_CTRL_SoftwareReset 0x1C0
	358
	359	#define SD_CTRL_SOFTWARE_RESET_CLEAR (1<<0)
	360
	361	#define SD_CTRL_TRANSACTIONCONTROL_SET (1<<8)
	362
	363	#define SD_CTRL_CARDCLOCKCONTROL_FOR_SD_CARD (1<<15)
	364	#define SD_CTRL_CARDCLOCKCONTROL_ENABLE_CLOCK (1<<8)
	365	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_512 (1<<7)
	366	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_256 (1<<6)
	367	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_128 (1<<5)
	368	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_64 (1<<4)
	369	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_32 (1<<3)
	370	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_16 (1<<2)
	371	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_8 (1<<1)
	372	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_4 (1<<0)
	373	#define SD_CTRL_CARDCLOCKCONTROL_CLK_DIV_2 (0<<0)
	374
	375	#define MEM_CARD_OPTION_REQUIRED 0x000e
	376	#define MEM_CARD_OPTION_DATA_RESPONSE_TIMEOUT(x) (((x) & 0x0f) << 4)
	377	#define MEM_CARD_OPTION_C2_MODULE_NOT_PRESENT (1<<14)
	378	#define MEM_CARD_OPTION_DATA_XFR_WIDTH_1 (1<<15)
	379	#define MEM_CARD_OPTION_DATA_XFR_WIDTH_4 0
	380
	381	#define SD_CTRL_COMMAND_INDEX(x) ((x) & 0x3f)
	382	#define SD_CTRL_COMMAND_TYPE_CMD (0 << 6)
	383	#define SD_CTRL_COMMAND_TYPE_ACMD (1 << 6)
	384	#define SD_CTRL_COMMAND_TYPE_AUTHENTICATION (2 << 6)
	385	#define SD_CTRL_COMMAND_RESPONSE_TYPE_NORMAL (0 << 8)
	386	#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1 (4 << 8)
	387	#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R1B (5 << 8)
	388	#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R2 (6 << 8)
	389	#define SD_CTRL_COMMAND_RESPONSE_TYPE_EXT_R3 (7 << 8)
	390	#define SD_CTRL_COMMAND_DATA_PRESENT (1 << 11)
	391	#define SD_CTRL_COMMAND_TRANSFER_READ (1 << 12)
	392	#define SD_CTRL_COMMAND_TRANSFER_WRITE (0 << 12)
	393	#define SD_CTRL_COMMAND_MULTI_BLOCK (1 << 13)
	394	#define SD_CTRL_COMMAND_SECURITY_CMD (1 << 14)
	395
	396	#define SD_CTRL_STOP_INTERNAL_ISSSUE_CMD12 (1 << 0)
	397	#define SD_CTRL_STOP_INTERNAL_AUTO_ISSUE_CMD12 (1 << 8)
	398
	399	#define SD_CTRL_CARDSTATUS_RESPONSE_END (1 << 0)
	400	#define SD_CTRL_CARDSTATUS_RW_END (1 << 2)
	401	#define SD_CTRL_CARDSTATUS_CARD_REMOVED_0 (1 << 3)
	402	#define SD_CTRL_CARDSTATUS_CARD_INSERTED_0 (1 << 4)
	403	#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_0 (1 << 5)
	404	#define SD_CTRL_CARDSTATUS_WRITE_PROTECT (1 << 7)
	405	#define SD_CTRL_CARDSTATUS_CARD_REMOVED_3 (1 << 8)
	406	#define SD_CTRL_CARDSTATUS_CARD_INSERTED_3 (1 << 9)
	407	#define SD_CTRL_CARDSTATUS_SIGNAL_STATE_PRESENT_3 (1 << 10)
	408
	409	#define SD_CTRL_BUFFERSTATUS_CMD_INDEX_ERROR (1 << 0)
	410	#define SD_CTRL_BUFFERSTATUS_CRC_ERROR (1 << 1)
	411	#define SD_CTRL_BUFFERSTATUS_STOP_BIT_END_ERROR (1 << 2)
	412	#define SD_CTRL_BUFFERSTATUS_DATA_TIMEOUT (1 << 3)
	413	#define SD_CTRL_BUFFERSTATUS_BUFFER_OVERFLOW (1 << 4)
	414	#define SD_CTRL_BUFFERSTATUS_BUFFER_UNDERFLOW (1 << 5)
	415	#define SD_CTRL_BUFFERSTATUS_CMD_TIMEOUT (1 << 6)
	416	#define SD_CTRL_BUFFERSTATUS_UNK7 (1 << 7)
	417	#define SD_CTRL_BUFFERSTATUS_BUFFER_READ_ENABLE (1 << 8)
	418	#define SD_CTRL_BUFFERSTATUS_BUFFER_WRITE_ENABLE (1 << 9)
	419	#define SD_CTRL_BUFFERSTATUS_ILLEGAL_FUNCTION (1 << 13)
	420	#define SD_CTRL_BUFFERSTATUS_CMD_BUSY (1 << 14)
	421	#define SD_CTRL_BUFFERSTATUS_ILLEGAL_ACCESS (1 << 15)
	422
	423	#define SD_CTRL_INTMASKCARD_RESPONSE_END (1 << 0)
	424	#define SD_CTRL_INTMASKCARD_RW_END (1 << 2)
	425	#define SD_CTRL_INTMASKCARD_CARD_REMOVED_0 (1 << 3)
	426	#define SD_CTRL_INTMASKCARD_CARD_INSERTED_0 (1 << 4)
	427	#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_0 (1 << 5)
	428	#define SD_CTRL_INTMASKCARD_UNK6 (1 << 6)
	429	#define SD_CTRL_INTMASKCARD_WRITE_PROTECT (1 << 7)
	430	#define SD_CTRL_INTMASKCARD_CARD_REMOVED_3 (1 << 8)
	431	#define SD_CTRL_INTMASKCARD_CARD_INSERTED_3 (1 << 9)
	432	#define SD_CTRL_INTMASKCARD_SIGNAL_STATE_PRESENT_3 (1 << 10)
	433
	434	#define SD_CTRL_INTMASKBUFFER_CMD_INDEX_ERROR (1 << 0)
	435	#define SD_CTRL_INTMASKBUFFER_CRC_ERROR (1 << 1)
	436	#define SD_CTRL_INTMASKBUFFER_STOP_BIT_END_ERROR (1 << 2)
	437	#define SD_CTRL_INTMASKBUFFER_DATA_TIMEOUT (1 << 3)
	438	#define SD_CTRL_INTMASKBUFFER_BUFFER_OVERFLOW (1 << 4)
	439	#define SD_CTRL_INTMASKBUFFER_BUFFER_UNDERFLOW (1 << 5)
	440	#define SD_CTRL_INTMASKBUFFER_CMD_TIMEOUT (1 << 6)
	441	#define SD_CTRL_INTMASKBUFFER_UNK7 (1 << 7)
	442	#define SD_CTRL_INTMASKBUFFER_BUFFER_READ_ENABLE (1 << 8)
	443	#define SD_CTRL_INTMASKBUFFER_BUFFER_WRITE_ENABLE (1 << 9)
	444	#define SD_CTRL_INTMASKBUFFER_ILLEGAL_FUNCTION (1 << 13)
	445	#define SD_CTRL_INTMASKBUFFER_CMD_BUSY (1 << 14)
	446	#define SD_CTRL_INTMASKBUFFER_ILLEGAL_ACCESS (1 << 15)
	447
	448	#define SD_CTRL_DETAIL0_RESPONSE_CMD_ERROR (1 << 0)
	449	#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 2)
	450	#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_RESPONSE_CMD12 (1 << 3)
	451	#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_READ_DATA (1 << 4)
	452	#define SD_CTRL_DETAIL0_END_BIT_ERROR_FOR_WRITE_CRC_STATUS (1 << 5)
	453	#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_NON_CMD12 (1 << 8)
	454	#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_RESPONSE_CMD12 (1 << 9)
	455	#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_READ_DATA (1 << 10)
	456	#define SD_CTRL_DETAIL0_CRC_ERROR_FOR_WRITE_CMD (1 << 11)
	457
	458	#define SD_CTRL_DETAIL1_NO_CMD_RESPONSE (1 << 0)
	459	#define SD_CTRL_DETAIL1_TIMEOUT_READ_DATA (1 << 4)
	460	#define SD_CTRL_DETAIL1_TIMEOUT_CRS_STATUS (1 << 5)
	461	#define SD_CTRL_DETAIL1_TIMEOUT_CRC_BUSY (1 << 6)
	462
	463	#define ASIC3_SDIO_CTRL_Base 0x1200
	464
	465	#define ASIC3_SDIO_CTRL_Cmd 0x00
	466	#define ASIC3_SDIO_CTRL_CardPortSel 0x04
	467	#define ASIC3_SDIO_CTRL_Arg0 0x08
	468	#define ASIC3_SDIO_CTRL_Arg1 0x0C
	469	#define ASIC3_SDIO_CTRL_TransferBlockCount 0x14
	470	#define ASIC3_SDIO_CTRL_Response0 0x18
	471	#define ASIC3_SDIO_CTRL_Response1 0x1C
	472	#define ASIC3_SDIO_CTRL_Response2 0x20
	473	#define ASIC3_SDIO_CTRL_Response3 0x24
	474	#define ASIC3_SDIO_CTRL_Response4 0x28
	475	#define ASIC3_SDIO_CTRL_Response5 0x2C
	476	#define ASIC3_SDIO_CTRL_Response6 0x30
	477	#define ASIC3_SDIO_CTRL_Response7 0x34
	478	#define ASIC3_SDIO_CTRL_CardStatus 0x38
	479	#define ASIC3_SDIO_CTRL_BufferCtrl 0x3C
	480	#define ASIC3_SDIO_CTRL_IntMaskCard 0x40
	481	#define ASIC3_SDIO_CTRL_IntMaskBuffer 0x44
	482	#define ASIC3_SDIO_CTRL_CardXferDataLen 0x4C
	483	#define ASIC3_SDIO_CTRL_CardOptionSetup 0x50
	484	#define ASIC3_SDIO_CTRL_ErrorStatus0 0x54
	485	#define ASIC3_SDIO_CTRL_ErrorStatus1 0x58
	486	#define ASIC3_SDIO_CTRL_DataPort 0x60
	487	#define ASIC3_SDIO_CTRL_TransactionCtrl 0x68
	488	#define ASIC3_SDIO_CTRL_CardIntCtrl 0x6C
	489	#define ASIC3_SDIO_CTRL_ClocknWaitCtrl 0x70
	490	#define ASIC3_SDIO_CTRL_HostInformation 0x74
	491	#define ASIC3_SDIO_CTRL_ErrorCtrl 0x78
	492	#define ASIC3_SDIO_CTRL_LEDCtrl 0x7C
	493	#define ASIC3_SDIO_CTRL_SoftwareReset 0x1C0
	494
	495	#define ASIC3_MAP_SIZE 0x2000
	496
	497	#endif /* __ASIC3_H__ */