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-rw-r--r--include/asm-generic/device.h3
-rw-r--r--include/linux/device.h9
-rw-r--r--include/linux/platform_device.h5
-rw-r--r--include/linux/pm.h101
-rw-r--r--include/linux/pm_runtime.h114
-rw-r--r--include/linux/sh_intc.h1
-rw-r--r--include/linux/usb/m66592.h44
-rw-r--r--include/linux/usb/r8a66597.h375
8 files changed, 640 insertions, 12 deletions
diff --git a/include/asm-generic/device.h b/include/asm-generic/device.h
index c17c9600f220..d7c76bba640d 100644
--- a/include/asm-generic/device.h
+++ b/include/asm-generic/device.h
@@ -9,4 +9,7 @@
9struct dev_archdata { 9struct dev_archdata {
10}; 10};
11 11
12struct pdev_archdata {
13};
14
12#endif /* _ASM_GENERIC_DEVICE_H */ 15#endif /* _ASM_GENERIC_DEVICE_H */
diff --git a/include/linux/device.h b/include/linux/device.h
index aebb81036db2..a28642975053 100644
--- a/include/linux/device.h
+++ b/include/linux/device.h
@@ -62,7 +62,7 @@ struct bus_type {
62 int (*suspend)(struct device *dev, pm_message_t state); 62 int (*suspend)(struct device *dev, pm_message_t state);
63 int (*resume)(struct device *dev); 63 int (*resume)(struct device *dev);
64 64
65 struct dev_pm_ops *pm; 65 const struct dev_pm_ops *pm;
66 66
67 struct bus_type_private *p; 67 struct bus_type_private *p;
68}; 68};
@@ -132,7 +132,7 @@ struct device_driver {
132 int (*resume) (struct device *dev); 132 int (*resume) (struct device *dev);
133 struct attribute_group **groups; 133 struct attribute_group **groups;
134 134
135 struct dev_pm_ops *pm; 135 const struct dev_pm_ops *pm;
136 136
137 struct driver_private *p; 137 struct driver_private *p;
138}; 138};
@@ -200,7 +200,8 @@ struct class {
200 int (*suspend)(struct device *dev, pm_message_t state); 200 int (*suspend)(struct device *dev, pm_message_t state);
201 int (*resume)(struct device *dev); 201 int (*resume)(struct device *dev);
202 202
203 struct dev_pm_ops *pm; 203 const struct dev_pm_ops *pm;
204
204 struct class_private *p; 205 struct class_private *p;
205}; 206};
206 207
@@ -291,7 +292,7 @@ struct device_type {
291 char *(*nodename)(struct device *dev); 292 char *(*nodename)(struct device *dev);
292 void (*release)(struct device *dev); 293 void (*release)(struct device *dev);
293 294
294 struct dev_pm_ops *pm; 295 const struct dev_pm_ops *pm;
295}; 296};
296 297
297/* interface for exporting device attributes */ 298/* interface for exporting device attributes */
diff --git a/include/linux/platform_device.h b/include/linux/platform_device.h
index 8dc5123b6305..3c6675c2444b 100644
--- a/include/linux/platform_device.h
+++ b/include/linux/platform_device.h
@@ -22,6 +22,9 @@ struct platform_device {
22 struct resource * resource; 22 struct resource * resource;
23 23
24 struct platform_device_id *id_entry; 24 struct platform_device_id *id_entry;
25
26 /* arch specific additions */
27 struct pdev_archdata archdata;
25}; 28};
26 29
27#define platform_get_device_id(pdev) ((pdev)->id_entry) 30#define platform_get_device_id(pdev) ((pdev)->id_entry)
@@ -57,8 +60,6 @@ struct platform_driver {
57 int (*remove)(struct platform_device *); 60 int (*remove)(struct platform_device *);
58 void (*shutdown)(struct platform_device *); 61 void (*shutdown)(struct platform_device *);
59 int (*suspend)(struct platform_device *, pm_message_t state); 62 int (*suspend)(struct platform_device *, pm_message_t state);
60 int (*suspend_late)(struct platform_device *, pm_message_t state);
61 int (*resume_early)(struct platform_device *);
62 int (*resume)(struct platform_device *); 63 int (*resume)(struct platform_device *);
63 struct device_driver driver; 64 struct device_driver driver;
64 struct platform_device_id *id_table; 65 struct platform_device_id *id_table;
diff --git a/include/linux/pm.h b/include/linux/pm.h
index b3f74764a586..2b6e20df0e52 100644
--- a/include/linux/pm.h
+++ b/include/linux/pm.h
@@ -22,6 +22,10 @@
22#define _LINUX_PM_H 22#define _LINUX_PM_H
23 23
24#include <linux/list.h> 24#include <linux/list.h>
25#include <linux/workqueue.h>
26#include <linux/spinlock.h>
27#include <linux/wait.h>
28#include <linux/timer.h>
25 29
26/* 30/*
27 * Callbacks for platform drivers to implement. 31 * Callbacks for platform drivers to implement.
@@ -165,6 +169,28 @@ typedef struct pm_message {
165 * It is allowed to unregister devices while the above callbacks are being 169 * It is allowed to unregister devices while the above callbacks are being
166 * executed. However, it is not allowed to unregister a device from within any 170 * executed. However, it is not allowed to unregister a device from within any
167 * of its own callbacks. 171 * of its own callbacks.
172 *
173 * There also are the following callbacks related to run-time power management
174 * of devices:
175 *
176 * @runtime_suspend: Prepare the device for a condition in which it won't be
177 * able to communicate with the CPU(s) and RAM due to power management.
178 * This need not mean that the device should be put into a low power state.
179 * For example, if the device is behind a link which is about to be turned
180 * off, the device may remain at full power. If the device does go to low
181 * power and if device_may_wakeup(dev) is true, remote wake-up (i.e., a
182 * hardware mechanism allowing the device to request a change of its power
183 * state, such as PCI PME) should be enabled for it.
184 *
185 * @runtime_resume: Put the device into the fully active state in response to a
186 * wake-up event generated by hardware or at the request of software. If
187 * necessary, put the device into the full power state and restore its
188 * registers, so that it is fully operational.
189 *
190 * @runtime_idle: Device appears to be inactive and it might be put into a low
191 * power state if all of the necessary conditions are satisfied. Check
192 * these conditions and handle the device as appropriate, possibly queueing
193 * a suspend request for it. The return value is ignored by the PM core.
168 */ 194 */
169 195
170struct dev_pm_ops { 196struct dev_pm_ops {
@@ -182,6 +208,9 @@ struct dev_pm_ops {
182 int (*thaw_noirq)(struct device *dev); 208 int (*thaw_noirq)(struct device *dev);
183 int (*poweroff_noirq)(struct device *dev); 209 int (*poweroff_noirq)(struct device *dev);
184 int (*restore_noirq)(struct device *dev); 210 int (*restore_noirq)(struct device *dev);
211 int (*runtime_suspend)(struct device *dev);
212 int (*runtime_resume)(struct device *dev);
213 int (*runtime_idle)(struct device *dev);
185}; 214};
186 215
187/** 216/**
@@ -315,14 +344,80 @@ enum dpm_state {
315 DPM_OFF_IRQ, 344 DPM_OFF_IRQ,
316}; 345};
317 346
347/**
348 * Device run-time power management status.
349 *
350 * These status labels are used internally by the PM core to indicate the
351 * current status of a device with respect to the PM core operations. They do
352 * not reflect the actual power state of the device or its status as seen by the
353 * driver.
354 *
355 * RPM_ACTIVE Device is fully operational. Indicates that the device
356 * bus type's ->runtime_resume() callback has completed
357 * successfully.
358 *
359 * RPM_SUSPENDED Device bus type's ->runtime_suspend() callback has
360 * completed successfully. The device is regarded as
361 * suspended.
362 *
363 * RPM_RESUMING Device bus type's ->runtime_resume() callback is being
364 * executed.
365 *
366 * RPM_SUSPENDING Device bus type's ->runtime_suspend() callback is being
367 * executed.
368 */
369
370enum rpm_status {
371 RPM_ACTIVE = 0,
372 RPM_RESUMING,
373 RPM_SUSPENDED,
374 RPM_SUSPENDING,
375};
376
377/**
378 * Device run-time power management request types.
379 *
380 * RPM_REQ_NONE Do nothing.
381 *
382 * RPM_REQ_IDLE Run the device bus type's ->runtime_idle() callback
383 *
384 * RPM_REQ_SUSPEND Run the device bus type's ->runtime_suspend() callback
385 *
386 * RPM_REQ_RESUME Run the device bus type's ->runtime_resume() callback
387 */
388
389enum rpm_request {
390 RPM_REQ_NONE = 0,
391 RPM_REQ_IDLE,
392 RPM_REQ_SUSPEND,
393 RPM_REQ_RESUME,
394};
395
318struct dev_pm_info { 396struct dev_pm_info {
319 pm_message_t power_state; 397 pm_message_t power_state;
320 unsigned can_wakeup:1; 398 unsigned int can_wakeup:1;
321 unsigned should_wakeup:1; 399 unsigned int should_wakeup:1;
322 enum dpm_state status; /* Owned by the PM core */ 400 enum dpm_state status; /* Owned by the PM core */
323#ifdef CONFIG_PM_SLEEP 401#ifdef CONFIG_PM_SLEEP
324 struct list_head entry; 402 struct list_head entry;
325#endif 403#endif
404#ifdef CONFIG_PM_RUNTIME
405 struct timer_list suspend_timer;
406 unsigned long timer_expires;
407 struct work_struct work;
408 wait_queue_head_t wait_queue;
409 spinlock_t lock;
410 atomic_t usage_count;
411 atomic_t child_count;
412 unsigned int disable_depth:3;
413 unsigned int ignore_children:1;
414 unsigned int idle_notification:1;
415 unsigned int request_pending:1;
416 unsigned int deferred_resume:1;
417 enum rpm_request request;
418 enum rpm_status runtime_status;
419 int runtime_error;
420#endif
326}; 421};
327 422
328/* 423/*
diff --git a/include/linux/pm_runtime.h b/include/linux/pm_runtime.h
new file mode 100644
index 000000000000..44087044910f
--- /dev/null
+++ b/include/linux/pm_runtime.h
@@ -0,0 +1,114 @@
1/*
2 * pm_runtime.h - Device run-time power management helper functions.
3 *
4 * Copyright (C) 2009 Rafael J. Wysocki <rjw@sisk.pl>
5 *
6 * This file is released under the GPLv2.
7 */
8
9#ifndef _LINUX_PM_RUNTIME_H
10#define _LINUX_PM_RUNTIME_H
11
12#include <linux/device.h>
13#include <linux/pm.h>
14
15#ifdef CONFIG_PM_RUNTIME
16
17extern struct workqueue_struct *pm_wq;
18
19extern int pm_runtime_idle(struct device *dev);
20extern int pm_runtime_suspend(struct device *dev);
21extern int pm_runtime_resume(struct device *dev);
22extern int pm_request_idle(struct device *dev);
23extern int pm_schedule_suspend(struct device *dev, unsigned int delay);
24extern int pm_request_resume(struct device *dev);
25extern int __pm_runtime_get(struct device *dev, bool sync);
26extern int __pm_runtime_put(struct device *dev, bool sync);
27extern int __pm_runtime_set_status(struct device *dev, unsigned int status);
28extern int pm_runtime_barrier(struct device *dev);
29extern void pm_runtime_enable(struct device *dev);
30extern void __pm_runtime_disable(struct device *dev, bool check_resume);
31
32static inline bool pm_children_suspended(struct device *dev)
33{
34 return dev->power.ignore_children
35 || !atomic_read(&dev->power.child_count);
36}
37
38static inline void pm_suspend_ignore_children(struct device *dev, bool enable)
39{
40 dev->power.ignore_children = enable;
41}
42
43static inline void pm_runtime_get_noresume(struct device *dev)
44{
45 atomic_inc(&dev->power.usage_count);
46}
47
48static inline void pm_runtime_put_noidle(struct device *dev)
49{
50 atomic_add_unless(&dev->power.usage_count, -1, 0);
51}
52
53#else /* !CONFIG_PM_RUNTIME */
54
55static inline int pm_runtime_idle(struct device *dev) { return -ENOSYS; }
56static inline int pm_runtime_suspend(struct device *dev) { return -ENOSYS; }
57static inline int pm_runtime_resume(struct device *dev) { return 0; }
58static inline int pm_request_idle(struct device *dev) { return -ENOSYS; }
59static inline int pm_schedule_suspend(struct device *dev, unsigned int delay)
60{
61 return -ENOSYS;
62}
63static inline int pm_request_resume(struct device *dev) { return 0; }
64static inline int __pm_runtime_get(struct device *dev, bool sync) { return 1; }
65static inline int __pm_runtime_put(struct device *dev, bool sync) { return 0; }
66static inline int __pm_runtime_set_status(struct device *dev,
67 unsigned int status) { return 0; }
68static inline int pm_runtime_barrier(struct device *dev) { return 0; }
69static inline void pm_runtime_enable(struct device *dev) {}
70static inline void __pm_runtime_disable(struct device *dev, bool c) {}
71
72static inline bool pm_children_suspended(struct device *dev) { return false; }
73static inline void pm_suspend_ignore_children(struct device *dev, bool en) {}
74static inline void pm_runtime_get_noresume(struct device *dev) {}
75static inline void pm_runtime_put_noidle(struct device *dev) {}
76
77#endif /* !CONFIG_PM_RUNTIME */
78
79static inline int pm_runtime_get(struct device *dev)
80{
81 return __pm_runtime_get(dev, false);
82}
83
84static inline int pm_runtime_get_sync(struct device *dev)
85{
86 return __pm_runtime_get(dev, true);
87}
88
89static inline int pm_runtime_put(struct device *dev)
90{
91 return __pm_runtime_put(dev, false);
92}
93
94static inline int pm_runtime_put_sync(struct device *dev)
95{
96 return __pm_runtime_put(dev, true);
97}
98
99static inline int pm_runtime_set_active(struct device *dev)
100{
101 return __pm_runtime_set_status(dev, RPM_ACTIVE);
102}
103
104static inline void pm_runtime_set_suspended(struct device *dev)
105{
106 __pm_runtime_set_status(dev, RPM_SUSPENDED);
107}
108
109static inline void pm_runtime_disable(struct device *dev)
110{
111 __pm_runtime_disable(dev, true);
112}
113
114#endif
diff --git a/include/linux/sh_intc.h b/include/linux/sh_intc.h
index eb1423a0078d..68e212ff9dde 100644
--- a/include/linux/sh_intc.h
+++ b/include/linux/sh_intc.h
@@ -85,7 +85,6 @@ struct intc_desc symbol __initdata = { \
85} 85}
86#endif 86#endif
87 87
88unsigned int intc_evt2irq(unsigned int vector);
89void __init register_intc_controller(struct intc_desc *desc); 88void __init register_intc_controller(struct intc_desc *desc);
90int intc_set_priority(unsigned int irq, unsigned int prio); 89int intc_set_priority(unsigned int irq, unsigned int prio);
91 90
diff --git a/include/linux/usb/m66592.h b/include/linux/usb/m66592.h
new file mode 100644
index 000000000000..cda9625e7df0
--- /dev/null
+++ b/include/linux/usb/m66592.h
@@ -0,0 +1,44 @@
1/*
2 * M66592 driver platform data
3 *
4 * Copyright (C) 2009 Renesas Solutions Corp.
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
18 *
19 */
20
21#ifndef __LINUX_USB_M66592_H
22#define __LINUX_USB_M66592_H
23
24#define M66592_PLATDATA_XTAL_12MHZ 0x01
25#define M66592_PLATDATA_XTAL_24MHZ 0x02
26#define M66592_PLATDATA_XTAL_48MHZ 0x03
27
28struct m66592_platdata {
29 /* one = on chip controller, zero = external controller */
30 unsigned on_chip:1;
31
32 /* one = big endian, zero = little endian */
33 unsigned endian:1;
34
35 /* (external controller only) M66592_PLATDATA_XTAL_nnMHZ */
36 unsigned xtal:2;
37
38 /* (external controller only) one = 3.3V, zero = 1.5V */
39 unsigned vif:1;
40
41};
42
43#endif /* __LINUX_USB_M66592_H */
44
diff --git a/include/linux/usb/r8a66597.h b/include/linux/usb/r8a66597.h
index e9f0384fa20c..26d216734057 100644
--- a/include/linux/usb/r8a66597.h
+++ b/include/linux/usb/r8a66597.h
@@ -28,9 +28,12 @@
28#define R8A66597_PLATDATA_XTAL_48MHZ 0x03 28#define R8A66597_PLATDATA_XTAL_48MHZ 0x03
29 29
30struct r8a66597_platdata { 30struct r8a66597_platdata {
31 /* This ops can controll port power instead of DVSTCTR register. */ 31 /* This callback can control port power instead of DVSTCTR register. */
32 void (*port_power)(int port, int power); 32 void (*port_power)(int port, int power);
33 33
34 /* set one = on chip controller, set zero = external controller */
35 unsigned on_chip:1;
36
34 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */ 37 /* (external controller only) set R8A66597_PLATDATA_XTAL_nnMHZ */
35 unsigned xtal:2; 38 unsigned xtal:2;
36 39
@@ -40,5 +43,373 @@ struct r8a66597_platdata {
40 /* set one = big endian, set zero = little endian */ 43 /* set one = big endian, set zero = little endian */
41 unsigned endian:1; 44 unsigned endian:1;
42}; 45};
43#endif 46
47/* Register definitions */
48#define SYSCFG0 0x00
49#define SYSCFG1 0x02
50#define SYSSTS0 0x04
51#define SYSSTS1 0x06
52#define DVSTCTR0 0x08
53#define DVSTCTR1 0x0A
54#define TESTMODE 0x0C
55#define PINCFG 0x0E
56#define DMA0CFG 0x10
57#define DMA1CFG 0x12
58#define CFIFO 0x14
59#define D0FIFO 0x18
60#define D1FIFO 0x1C
61#define CFIFOSEL 0x20
62#define CFIFOCTR 0x22
63#define CFIFOSIE 0x24
64#define D0FIFOSEL 0x28
65#define D0FIFOCTR 0x2A
66#define D1FIFOSEL 0x2C
67#define D1FIFOCTR 0x2E
68#define INTENB0 0x30
69#define INTENB1 0x32
70#define INTENB2 0x34
71#define BRDYENB 0x36
72#define NRDYENB 0x38
73#define BEMPENB 0x3A
74#define SOFCFG 0x3C
75#define INTSTS0 0x40
76#define INTSTS1 0x42
77#define INTSTS2 0x44
78#define BRDYSTS 0x46
79#define NRDYSTS 0x48
80#define BEMPSTS 0x4A
81#define FRMNUM 0x4C
82#define UFRMNUM 0x4E
83#define USBADDR 0x50
84#define USBREQ 0x54
85#define USBVAL 0x56
86#define USBINDX 0x58
87#define USBLENG 0x5A
88#define DCPCFG 0x5C
89#define DCPMAXP 0x5E
90#define DCPCTR 0x60
91#define PIPESEL 0x64
92#define PIPECFG 0x68
93#define PIPEBUF 0x6A
94#define PIPEMAXP 0x6C
95#define PIPEPERI 0x6E
96#define PIPE1CTR 0x70
97#define PIPE2CTR 0x72
98#define PIPE3CTR 0x74
99#define PIPE4CTR 0x76
100#define PIPE5CTR 0x78
101#define PIPE6CTR 0x7A
102#define PIPE7CTR 0x7C
103#define PIPE8CTR 0x7E
104#define PIPE9CTR 0x80
105#define PIPE1TRE 0x90
106#define PIPE1TRN 0x92
107#define PIPE2TRE 0x94
108#define PIPE2TRN 0x96
109#define PIPE3TRE 0x98
110#define PIPE3TRN 0x9A
111#define PIPE4TRE 0x9C
112#define PIPE4TRN 0x9E
113#define PIPE5TRE 0xA0
114#define PIPE5TRN 0xA2
115#define DEVADD0 0xD0
116#define DEVADD1 0xD2
117#define DEVADD2 0xD4
118#define DEVADD3 0xD6
119#define DEVADD4 0xD8
120#define DEVADD5 0xDA
121#define DEVADD6 0xDC
122#define DEVADD7 0xDE
123#define DEVADD8 0xE0
124#define DEVADD9 0xE2
125#define DEVADDA 0xE4
126
127/* System Configuration Control Register */
128#define XTAL 0xC000 /* b15-14: Crystal selection */
129#define XTAL48 0x8000 /* 48MHz */
130#define XTAL24 0x4000 /* 24MHz */
131#define XTAL12 0x0000 /* 12MHz */
132#define XCKE 0x2000 /* b13: External clock enable */
133#define PLLC 0x0800 /* b11: PLL control */
134#define SCKE 0x0400 /* b10: USB clock enable */
135#define PCSDIS 0x0200 /* b9: not CS wakeup */
136#define LPSME 0x0100 /* b8: Low power sleep mode */
137#define HSE 0x0080 /* b7: Hi-speed enable */
138#define DCFM 0x0040 /* b6: Controller function select */
139#define DRPD 0x0020 /* b5: D+/- pull down control */
140#define DPRPU 0x0010 /* b4: D+ pull up control */
141#define USBE 0x0001 /* b0: USB module operation enable */
142
143/* System Configuration Status Register */
144#define OVCBIT 0x8000 /* b15-14: Over-current bit */
145#define OVCMON 0xC000 /* b15-14: Over-current monitor */
146#define SOFEA 0x0020 /* b5: SOF monitor */
147#define IDMON 0x0004 /* b3: ID-pin monitor */
148#define LNST 0x0003 /* b1-0: D+, D- line status */
149#define SE1 0x0003 /* SE1 */
150#define FS_KSTS 0x0002 /* Full-Speed K State */
151#define FS_JSTS 0x0001 /* Full-Speed J State */
152#define LS_JSTS 0x0002 /* Low-Speed J State */
153#define LS_KSTS 0x0001 /* Low-Speed K State */
154#define SE0 0x0000 /* SE0 */
155
156/* Device State Control Register */
157#define EXTLP0 0x0400 /* b10: External port */
158#define VBOUT 0x0200 /* b9: VBUS output */
159#define WKUP 0x0100 /* b8: Remote wakeup */
160#define RWUPE 0x0080 /* b7: Remote wakeup sense */
161#define USBRST 0x0040 /* b6: USB reset enable */
162#define RESUME 0x0020 /* b5: Resume enable */
163#define UACT 0x0010 /* b4: USB bus enable */
164#define RHST 0x0007 /* b1-0: Reset handshake status */
165#define HSPROC 0x0004 /* HS handshake is processing */
166#define HSMODE 0x0003 /* Hi-Speed mode */
167#define FSMODE 0x0002 /* Full-Speed mode */
168#define LSMODE 0x0001 /* Low-Speed mode */
169#define UNDECID 0x0000 /* Undecided */
170
171/* Test Mode Register */
172#define UTST 0x000F /* b3-0: Test select */
173#define H_TST_PACKET 0x000C /* HOST TEST Packet */
174#define H_TST_SE0_NAK 0x000B /* HOST TEST SE0 NAK */
175#define H_TST_K 0x000A /* HOST TEST K */
176#define H_TST_J 0x0009 /* HOST TEST J */
177#define H_TST_NORMAL 0x0000 /* HOST Normal Mode */
178#define P_TST_PACKET 0x0004 /* PERI TEST Packet */
179#define P_TST_SE0_NAK 0x0003 /* PERI TEST SE0 NAK */
180#define P_TST_K 0x0002 /* PERI TEST K */
181#define P_TST_J 0x0001 /* PERI TEST J */
182#define P_TST_NORMAL 0x0000 /* PERI Normal Mode */
183
184/* Data Pin Configuration Register */
185#define LDRV 0x8000 /* b15: Drive Current Adjust */
186#define VIF1 0x0000 /* VIF = 1.8V */
187#define VIF3 0x8000 /* VIF = 3.3V */
188#define INTA 0x0001 /* b1: USB INT-pin active */
189
190/* DMAx Pin Configuration Register */
191#define DREQA 0x4000 /* b14: Dreq active select */
192#define BURST 0x2000 /* b13: Burst mode */
193#define DACKA 0x0400 /* b10: Dack active select */
194#define DFORM 0x0380 /* b9-7: DMA mode select */
195#define CPU_ADR_RD_WR 0x0000 /* Address + RD/WR mode (CPU bus) */
196#define CPU_DACK_RD_WR 0x0100 /* DACK + RD/WR mode (CPU bus) */
197#define CPU_DACK_ONLY 0x0180 /* DACK only mode (CPU bus) */
198#define SPLIT_DACK_ONLY 0x0200 /* DACK only mode (SPLIT bus) */
199#define DENDA 0x0040 /* b6: Dend active select */
200#define PKTM 0x0020 /* b5: Packet mode */
201#define DENDE 0x0010 /* b4: Dend enable */
202#define OBUS 0x0004 /* b2: OUTbus mode */
203
204/* CFIFO/DxFIFO Port Select Register */
205#define RCNT 0x8000 /* b15: Read count mode */
206#define REW 0x4000 /* b14: Buffer rewind */
207#define DCLRM 0x2000 /* b13: DMA buffer clear mode */
208#define DREQE 0x1000 /* b12: DREQ output enable */
209#define MBW_8 0x0000 /* 8bit */
210#define MBW_16 0x0400 /* 16bit */
211#define MBW_32 0x0800 /* 32bit */
212#define BIGEND 0x0100 /* b8: Big endian mode */
213#define BYTE_LITTLE 0x0000 /* little dendian */
214#define BYTE_BIG 0x0100 /* big endifan */
215#define ISEL 0x0020 /* b5: DCP FIFO port direction select */
216#define CURPIPE 0x000F /* b2-0: PIPE select */
217
218/* CFIFO/DxFIFO Port Control Register */
219#define BVAL 0x8000 /* b15: Buffer valid flag */
220#define BCLR 0x4000 /* b14: Buffer clear */
221#define FRDY 0x2000 /* b13: FIFO ready */
222#define DTLN 0x0FFF /* b11-0: FIFO received data length */
223
224/* Interrupt Enable Register 0 */
225#define VBSE 0x8000 /* b15: VBUS interrupt */
226#define RSME 0x4000 /* b14: Resume interrupt */
227#define SOFE 0x2000 /* b13: Frame update interrupt */
228#define DVSE 0x1000 /* b12: Device state transition interrupt */
229#define CTRE 0x0800 /* b11: Control transfer stage transition interrupt */
230#define BEMPE 0x0400 /* b10: Buffer empty interrupt */
231#define NRDYE 0x0200 /* b9: Buffer not ready interrupt */
232#define BRDYE 0x0100 /* b8: Buffer ready interrupt */
233
234/* Interrupt Enable Register 1 */
235#define OVRCRE 0x8000 /* b15: Over-current interrupt */
236#define BCHGE 0x4000 /* b14: USB us chenge interrupt */
237#define DTCHE 0x1000 /* b12: Detach sense interrupt */
238#define ATTCHE 0x0800 /* b11: Attach sense interrupt */
239#define EOFERRE 0x0040 /* b6: EOF error interrupt */
240#define SIGNE 0x0020 /* b5: SETUP IGNORE interrupt */
241#define SACKE 0x0010 /* b4: SETUP ACK interrupt */
242
243/* BRDY Interrupt Enable/Status Register */
244#define BRDY9 0x0200 /* b9: PIPE9 */
245#define BRDY8 0x0100 /* b8: PIPE8 */
246#define BRDY7 0x0080 /* b7: PIPE7 */
247#define BRDY6 0x0040 /* b6: PIPE6 */
248#define BRDY5 0x0020 /* b5: PIPE5 */
249#define BRDY4 0x0010 /* b4: PIPE4 */
250#define BRDY3 0x0008 /* b3: PIPE3 */
251#define BRDY2 0x0004 /* b2: PIPE2 */
252#define BRDY1 0x0002 /* b1: PIPE1 */
253#define BRDY0 0x0001 /* b1: PIPE0 */
254
255/* NRDY Interrupt Enable/Status Register */
256#define NRDY9 0x0200 /* b9: PIPE9 */
257#define NRDY8 0x0100 /* b8: PIPE8 */
258#define NRDY7 0x0080 /* b7: PIPE7 */
259#define NRDY6 0x0040 /* b6: PIPE6 */
260#define NRDY5 0x0020 /* b5: PIPE5 */
261#define NRDY4 0x0010 /* b4: PIPE4 */
262#define NRDY3 0x0008 /* b3: PIPE3 */
263#define NRDY2 0x0004 /* b2: PIPE2 */
264#define NRDY1 0x0002 /* b1: PIPE1 */
265#define NRDY0 0x0001 /* b1: PIPE0 */
266
267/* BEMP Interrupt Enable/Status Register */
268#define BEMP9 0x0200 /* b9: PIPE9 */
269#define BEMP8 0x0100 /* b8: PIPE8 */
270#define BEMP7 0x0080 /* b7: PIPE7 */
271#define BEMP6 0x0040 /* b6: PIPE6 */
272#define BEMP5 0x0020 /* b5: PIPE5 */
273#define BEMP4 0x0010 /* b4: PIPE4 */
274#define BEMP3 0x0008 /* b3: PIPE3 */
275#define BEMP2 0x0004 /* b2: PIPE2 */
276#define BEMP1 0x0002 /* b1: PIPE1 */
277#define BEMP0 0x0001 /* b0: PIPE0 */
278
279/* SOF Pin Configuration Register */
280#define TRNENSEL 0x0100 /* b8: Select transaction enable period */
281#define BRDYM 0x0040 /* b6: BRDY clear timing */
282#define INTL 0x0020 /* b5: Interrupt sense select */
283#define EDGESTS 0x0010 /* b4: */
284#define SOFMODE 0x000C /* b3-2: SOF pin select */
285#define SOF_125US 0x0008 /* SOF OUT 125us Frame Signal */
286#define SOF_1MS 0x0004 /* SOF OUT 1ms Frame Signal */
287#define SOF_DISABLE 0x0000 /* SOF OUT Disable */
288
289/* Interrupt Status Register 0 */
290#define VBINT 0x8000 /* b15: VBUS interrupt */
291#define RESM 0x4000 /* b14: Resume interrupt */
292#define SOFR 0x2000 /* b13: SOF frame update interrupt */
293#define DVST 0x1000 /* b12: Device state transition interrupt */
294#define CTRT 0x0800 /* b11: Control transfer stage transition interrupt */
295#define BEMP 0x0400 /* b10: Buffer empty interrupt */
296#define NRDY 0x0200 /* b9: Buffer not ready interrupt */
297#define BRDY 0x0100 /* b8: Buffer ready interrupt */
298#define VBSTS 0x0080 /* b7: VBUS input port */
299#define DVSQ 0x0070 /* b6-4: Device state */
300#define DS_SPD_CNFG 0x0070 /* Suspend Configured */
301#define DS_SPD_ADDR 0x0060 /* Suspend Address */
302#define DS_SPD_DFLT 0x0050 /* Suspend Default */
303#define DS_SPD_POWR 0x0040 /* Suspend Powered */
304#define DS_SUSP 0x0040 /* Suspend */
305#define DS_CNFG 0x0030 /* Configured */
306#define DS_ADDS 0x0020 /* Address */
307#define DS_DFLT 0x0010 /* Default */
308#define DS_POWR 0x0000 /* Powered */
309#define DVSQS 0x0030 /* b5-4: Device state */
310#define VALID 0x0008 /* b3: Setup packet detected flag */
311#define CTSQ 0x0007 /* b2-0: Control transfer stage */
312#define CS_SQER 0x0006 /* Sequence error */
313#define CS_WRND 0x0005 /* Control write nodata status stage */
314#define CS_WRSS 0x0004 /* Control write status stage */
315#define CS_WRDS 0x0003 /* Control write data stage */
316#define CS_RDSS 0x0002 /* Control read status stage */
317#define CS_RDDS 0x0001 /* Control read data stage */
318#define CS_IDST 0x0000 /* Idle or setup stage */
319
320/* Interrupt Status Register 1 */
321#define OVRCR 0x8000 /* b15: Over-current interrupt */
322#define BCHG 0x4000 /* b14: USB bus chenge interrupt */
323#define DTCH 0x1000 /* b12: Detach sense interrupt */
324#define ATTCH 0x0800 /* b11: Attach sense interrupt */
325#define EOFERR 0x0040 /* b6: EOF-error interrupt */
326#define SIGN 0x0020 /* b5: Setup ignore interrupt */
327#define SACK 0x0010 /* b4: Setup acknowledge interrupt */
328
329/* Frame Number Register */
330#define OVRN 0x8000 /* b15: Overrun error */
331#define CRCE 0x4000 /* b14: Received data error */
332#define FRNM 0x07FF /* b10-0: Frame number */
333
334/* Micro Frame Number Register */
335#define UFRNM 0x0007 /* b2-0: Micro frame number */
336
337/* Default Control Pipe Maxpacket Size Register */
338/* Pipe Maxpacket Size Register */
339#define DEVSEL 0xF000 /* b15-14: Device address select */
340#define MAXP 0x007F /* b6-0: Maxpacket size of default control pipe */
341
342/* Default Control Pipe Control Register */
343#define BSTS 0x8000 /* b15: Buffer status */
344#define SUREQ 0x4000 /* b14: Send USB request */
345#define CSCLR 0x2000 /* b13: complete-split status clear */
346#define CSSTS 0x1000 /* b12: complete-split status */
347#define SUREQCLR 0x0800 /* b11: stop setup request */
348#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
349#define SQSET 0x0080 /* b7: Sequence toggle bit set */
350#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
351#define PBUSY 0x0020 /* b5: pipe busy */
352#define PINGE 0x0010 /* b4: ping enable */
353#define CCPL 0x0004 /* b2: Enable control transfer complete */
354#define PID 0x0003 /* b1-0: Response PID */
355#define PID_STALL11 0x0003 /* STALL */
356#define PID_STALL 0x0002 /* STALL */
357#define PID_BUF 0x0001 /* BUF */
358#define PID_NAK 0x0000 /* NAK */
359
360/* Pipe Window Select Register */
361#define PIPENM 0x0007 /* b2-0: Pipe select */
362
363/* Pipe Configuration Register */
364#define R8A66597_TYP 0xC000 /* b15-14: Transfer type */
365#define R8A66597_ISO 0xC000 /* Isochronous */
366#define R8A66597_INT 0x8000 /* Interrupt */
367#define R8A66597_BULK 0x4000 /* Bulk */
368#define R8A66597_BFRE 0x0400 /* b10: Buffer ready interrupt mode select */
369#define R8A66597_DBLB 0x0200 /* b9: Double buffer mode select */
370#define R8A66597_CNTMD 0x0100 /* b8: Continuous transfer mode select */
371#define R8A66597_SHTNAK 0x0080 /* b7: Transfer end NAK */
372#define R8A66597_DIR 0x0010 /* b4: Transfer direction select */
373#define R8A66597_EPNUM 0x000F /* b3-0: Eendpoint number select */
374
375/* Pipe Buffer Configuration Register */
376#define BUFSIZE 0x7C00 /* b14-10: Pipe buffer size */
377#define BUFNMB 0x007F /* b6-0: Pipe buffer number */
378#define PIPE0BUF 256
379#define PIPExBUF 64
380
381/* Pipe Maxpacket Size Register */
382#define MXPS 0x07FF /* b10-0: Maxpacket size */
383
384/* Pipe Cycle Configuration Register */
385#define IFIS 0x1000 /* b12: Isochronous in-buffer flush mode select */
386#define IITV 0x0007 /* b2-0: Isochronous interval */
387
388/* Pipex Control Register */
389#define BSTS 0x8000 /* b15: Buffer status */
390#define INBUFM 0x4000 /* b14: IN buffer monitor (Only for PIPE1 to 5) */
391#define CSCLR 0x2000 /* b13: complete-split status clear */
392#define CSSTS 0x1000 /* b12: complete-split status */
393#define ATREPM 0x0400 /* b10: Auto repeat mode */
394#define ACLRM 0x0200 /* b9: Out buffer auto clear mode */
395#define SQCLR 0x0100 /* b8: Sequence toggle bit clear */
396#define SQSET 0x0080 /* b7: Sequence toggle bit set */
397#define SQMON 0x0040 /* b6: Sequence toggle bit monitor */
398#define PBUSY 0x0020 /* b5: pipe busy */
399#define PID 0x0003 /* b1-0: Response PID */
400
401/* PIPExTRE */
402#define TRENB 0x0200 /* b9: Transaction counter enable */
403#define TRCLR 0x0100 /* b8: Transaction counter clear */
404
405/* PIPExTRN */
406#define TRNCNT 0xFFFF /* b15-0: Transaction counter */
407
408/* DEVADDx */
409#define UPPHUB 0x7800
410#define HUBPORT 0x0700
411#define USBSPD 0x00C0
412#define RTPORT 0x0001
413
414#endif /* __LINUX_USB_R8A66597_H */
44 415
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-10 05:10:31 -0500