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-rw-r--r--include/asm-mips/bootinfo.h2
-rw-r--r--include/asm-mips/cpu.h3
-rw-r--r--include/asm-mips/mach-au1x00/au1000.h556
-rw-r--r--include/asm-mips/mach-au1x00/au1xxx_dbdma.h124
-rw-r--r--include/asm-mips/mach-db1x00/db1200.h214
-rw-r--r--include/asm-mips/mach-pb1x00/pb1200.h244
6 files changed, 1066 insertions, 77 deletions
diff --git a/include/asm-mips/bootinfo.h b/include/asm-mips/bootinfo.h
index b1e57d783604..404856e6b82d 100644
--- a/include/asm-mips/bootinfo.h
+++ b/include/asm-mips/bootinfo.h
@@ -177,6 +177,8 @@
177#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */ 177#define MACH_MTX1 7 /* 4G MTX-1 Au1500-based board */
178#define MACH_PB1550 8 /* Au1550-based eval board */ 178#define MACH_PB1550 8 /* Au1550-based eval board */
179#define MACH_DB1550 9 /* Au1550-based eval board */ 179#define MACH_DB1550 9 /* Au1550-based eval board */
180#define MACH_PB1200 10 /* Au1200-based eval board */
181#define MACH_DB1200 11 /* Au1200-based eval board */
180 182
181/* 183/*
182 * Valid machtype for group NEC_VR41XX 184 * Valid machtype for group NEC_VR41XX
diff --git a/include/asm-mips/cpu.h b/include/asm-mips/cpu.h
index c60281799801..8e167bfd40b1 100644
--- a/include/asm-mips/cpu.h
+++ b/include/asm-mips/cpu.h
@@ -182,7 +182,8 @@
182#define CPU_VR4133 56 182#define CPU_VR4133 56
183#define CPU_AU1550 57 183#define CPU_AU1550 57
184#define CPU_24K 58 184#define CPU_24K 58
185#define CPU_LAST 58 185#define CPU_AU1200 59
186#define CPU_LAST 59
186 187
187/* 188/*
188 * ISA Level encodings 189 * ISA Level encodings
diff --git a/include/asm-mips/mach-au1x00/au1000.h b/include/asm-mips/mach-au1x00/au1000.h
index 148bae2fa7d3..28b04a5f67cf 100644
--- a/include/asm-mips/mach-au1x00/au1000.h
+++ b/include/asm-mips/mach-au1x00/au1000.h
@@ -162,27 +162,355 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5) 162#define ALLINTS (IE_IRQ0 | IE_IRQ1 | IE_IRQ2 | IE_IRQ3 | IE_IRQ4 | IE_IRQ5)
163#endif 163#endif
164 164
165/* SDRAM Controller */ 165/*
166 * SDRAM Register Offsets
167 */
166#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100) 168#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
167#define MEM_SDMODE0 0xB4000000 169#define MEM_SDMODE0 (0x0000)
168#define MEM_SDMODE1 0xB4000004 170#define MEM_SDMODE1 (0x0004)
169#define MEM_SDMODE2 0xB4000008 171#define MEM_SDMODE2 (0x0008)
172#define MEM_SDADDR0 (0x000C)
173#define MEM_SDADDR1 (0x0010)
174#define MEM_SDADDR2 (0x0014)
175#define MEM_SDREFCFG (0x0018)
176#define MEM_SDPRECMD (0x001C)
177#define MEM_SDAUTOREF (0x0020)
178#define MEM_SDWRMD0 (0x0024)
179#define MEM_SDWRMD1 (0x0028)
180#define MEM_SDWRMD2 (0x002C)
181#define MEM_SDSLEEP (0x0030)
182#define MEM_SDSMCKE (0x0034)
183
184#ifndef ASSEMBLER
185/*typedef volatile struct
186{
187 uint32 sdmode0;
188 uint32 sdmode1;
189 uint32 sdmode2;
190 uint32 sdaddr0;
191 uint32 sdaddr1;
192 uint32 sdaddr2;
193 uint32 sdrefcfg;
194 uint32 sdautoref;
195 uint32 sdwrmd0;
196 uint32 sdwrmd1;
197 uint32 sdwrmd2;
198 uint32 sdsleep;
199 uint32 sdsmcke;
200
201} AU1X00_SDRAM;*/
202#endif
203
204/*
205 * MEM_SDMODE register content definitions
206 */
207#define MEM_SDMODE_F (1<<22)
208#define MEM_SDMODE_SR (1<<21)
209#define MEM_SDMODE_BS (1<<20)
210#define MEM_SDMODE_RS (3<<18)
211#define MEM_SDMODE_CS (7<<15)
212#define MEM_SDMODE_TRAS (15<<11)
213#define MEM_SDMODE_TMRD (3<<9)
214#define MEM_SDMODE_TWR (3<<7)
215#define MEM_SDMODE_TRP (3<<5)
216#define MEM_SDMODE_TRCD (3<<3)
217#define MEM_SDMODE_TCL (7<<0)
218
219#define MEM_SDMODE_BS_2Bank (0<<20)
220#define MEM_SDMODE_BS_4Bank (1<<20)
221#define MEM_SDMODE_RS_11Row (0<<18)
222#define MEM_SDMODE_RS_12Row (1<<18)
223#define MEM_SDMODE_RS_13Row (2<<18)
224#define MEM_SDMODE_RS_N(N) ((N)<<18)
225#define MEM_SDMODE_CS_7Col (0<<15)
226#define MEM_SDMODE_CS_8Col (1<<15)
227#define MEM_SDMODE_CS_9Col (2<<15)
228#define MEM_SDMODE_CS_10Col (3<<15)
229#define MEM_SDMODE_CS_11Col (4<<15)
230#define MEM_SDMODE_CS_N(N) ((N)<<15)
231#define MEM_SDMODE_TRAS_N(N) ((N)<<11)
232#define MEM_SDMODE_TMRD_N(N) ((N)<<9)
233#define MEM_SDMODE_TWR_N(N) ((N)<<7)
234#define MEM_SDMODE_TRP_N(N) ((N)<<5)
235#define MEM_SDMODE_TRCD_N(N) ((N)<<3)
236#define MEM_SDMODE_TCL_N(N) ((N)<<0)
237
238/*
239 * MEM_SDADDR register contents definitions
240 */
241#define MEM_SDADDR_E (1<<20)
242#define MEM_SDADDR_CSBA (0x03FF<<10)
243#define MEM_SDADDR_CSMASK (0x03FF<<0)
244#define MEM_SDADDR_CSBA_N(N) ((N)&(0x03FF<<22)>>12)
245#define MEM_SDADDR_CSMASK_N(N) ((N)&(0x03FF<<22)>>22)
246
247/*
248 * MEM_SDREFCFG register content definitions
249 */
250#define MEM_SDREFCFG_TRC (15<<28)
251#define MEM_SDREFCFG_TRPM (3<<26)
252#define MEM_SDREFCFG_E (1<<25)
253#define MEM_SDREFCFG_RE (0x1ffffff<<0)
254#define MEM_SDREFCFG_TRC_N(N) ((N)<<MEM_SDREFCFG_TRC)
255#define MEM_SDREFCFG_TRPM_N(N) ((N)<<MEM_SDREFCFG_TRPM)
256#define MEM_SDREFCFG_REF_N(N) (N)
257#endif
170 258
171#define MEM_SDADDR0 0xB400000C 259/***********************************************************************/
172#define MEM_SDADDR1 0xB4000010
173#define MEM_SDADDR2 0xB4000014
174 260
175#define MEM_SDREFCFG 0xB4000018 261/*
176#define MEM_SDPRECMD 0xB400001C 262 * Au1550 SDRAM Register Offsets
177#define MEM_SDAUTOREF 0xB4000020 263 */
178 264
179#define MEM_SDWRMD0 0xB4000024 265/***********************************************************************/
180#define MEM_SDWRMD1 0xB4000028
181#define MEM_SDWRMD2 0xB400002C
182 266
183#define MEM_SDSLEEP 0xB4000030 267#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
184#define MEM_SDSMCKE 0xB4000034 268#define MEM_SDMODE0 (0x0800)
269#define MEM_SDMODE1 (0x0808)
270#define MEM_SDMODE2 (0x0810)
271#define MEM_SDADDR0 (0x0820)
272#define MEM_SDADDR1 (0x0828)
273#define MEM_SDADDR2 (0x0830)
274#define MEM_SDCONFIGA (0x0840)
275#define MEM_SDCONFIGB (0x0848)
276#define MEM_SDSTAT (0x0850)
277#define MEM_SDERRADDR (0x0858)
278#define MEM_SDSTRIDE0 (0x0860)
279#define MEM_SDSTRIDE1 (0x0868)
280#define MEM_SDSTRIDE2 (0x0870)
281#define MEM_SDWRMD0 (0x0880)
282#define MEM_SDWRMD1 (0x0888)
283#define MEM_SDWRMD2 (0x0890)
284#define MEM_SDPRECMD (0x08C0)
285#define MEM_SDAUTOREF (0x08C8)
286#define MEM_SDSREF (0x08D0)
287#define MEM_SDSLEEP MEM_SDSREF
288
289#ifndef ASSEMBLER
290/*typedef volatile struct
291{
292 uint32 sdmode0;
293 uint32 reserved0;
294 uint32 sdmode1;
295 uint32 reserved1;
296 uint32 sdmode2;
297 uint32 reserved2[3];
298 uint32 sdaddr0;
299 uint32 reserved3;
300 uint32 sdaddr1;
301 uint32 reserved4;
302 uint32 sdaddr2;
303 uint32 reserved5[3];
304 uint32 sdconfiga;
305 uint32 reserved6;
306 uint32 sdconfigb;
307 uint32 reserved7;
308 uint32 sdstat;
309 uint32 reserved8;
310 uint32 sderraddr;
311 uint32 reserved9;
312 uint32 sdstride0;
313 uint32 reserved10;
314 uint32 sdstride1;
315 uint32 reserved11;
316 uint32 sdstride2;
317 uint32 reserved12[3];
318 uint32 sdwrmd0;
319 uint32 reserved13;
320 uint32 sdwrmd1;
321 uint32 reserved14;
322 uint32 sdwrmd2;
323 uint32 reserved15[11];
324 uint32 sdprecmd;
325 uint32 reserved16;
326 uint32 sdautoref;
327 uint32 reserved17;
328 uint32 sdsref;
329
330} AU1550_SDRAM;*/
185#endif 331#endif
332#endif
333
334/*
335 * Physical base addresses for integrated peripherals
336 */
337
338#ifdef CONFIG_SOC_AU1000
339#define MEM_PHYS_ADDR 0x14000000
340#define STATIC_MEM_PHYS_ADDR 0x14001000
341#define DMA0_PHYS_ADDR 0x14002000
342#define DMA1_PHYS_ADDR 0x14002100
343#define DMA2_PHYS_ADDR 0x14002200
344#define DMA3_PHYS_ADDR 0x14002300
345#define DMA4_PHYS_ADDR 0x14002400
346#define DMA5_PHYS_ADDR 0x14002500
347#define DMA6_PHYS_ADDR 0x14002600
348#define DMA7_PHYS_ADDR 0x14002700
349#define IC0_PHYS_ADDR 0x10400000
350#define IC1_PHYS_ADDR 0x11800000
351#define AC97_PHYS_ADDR 0x10000000
352#define USBH_PHYS_ADDR 0x10100000
353#define USBD_PHYS_ADDR 0x10200000
354#define IRDA_PHYS_ADDR 0x10300000
355#define MAC0_PHYS_ADDR 0x10500000
356#define MAC1_PHYS_ADDR 0x10510000
357#define MACEN_PHYS_ADDR 0x10520000
358#define MACDMA0_PHYS_ADDR 0x14004000
359#define MACDMA1_PHYS_ADDR 0x14004200
360#define I2S_PHYS_ADDR 0x11000000
361#define UART0_PHYS_ADDR 0x11100000
362#define UART1_PHYS_ADDR 0x11200000
363#define UART2_PHYS_ADDR 0x11300000
364#define UART3_PHYS_ADDR 0x11400000
365#define SSI0_PHYS_ADDR 0x11600000
366#define SSI1_PHYS_ADDR 0x11680000
367#define SYS_PHYS_ADDR 0x11900000
368#define PCMCIA_IO_PHYS_ADDR 0xF00000000
369#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
370#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
371#endif
372
373/********************************************************************/
374
375#ifdef CONFIG_SOC_AU1500
376#define MEM_PHYS_ADDR 0x14000000
377#define STATIC_MEM_PHYS_ADDR 0x14001000
378#define DMA0_PHYS_ADDR 0x14002000
379#define DMA1_PHYS_ADDR 0x14002100
380#define DMA2_PHYS_ADDR 0x14002200
381#define DMA3_PHYS_ADDR 0x14002300
382#define DMA4_PHYS_ADDR 0x14002400
383#define DMA5_PHYS_ADDR 0x14002500
384#define DMA6_PHYS_ADDR 0x14002600
385#define DMA7_PHYS_ADDR 0x14002700
386#define IC0_PHYS_ADDR 0x10400000
387#define IC1_PHYS_ADDR 0x11800000
388#define AC97_PHYS_ADDR 0x10000000
389#define USBH_PHYS_ADDR 0x10100000
390#define USBD_PHYS_ADDR 0x10200000
391#define PCI_PHYS_ADDR 0x14005000
392#define MAC0_PHYS_ADDR 0x11500000
393#define MAC1_PHYS_ADDR 0x11510000
394#define MACEN_PHYS_ADDR 0x11520000
395#define MACDMA0_PHYS_ADDR 0x14004000
396#define MACDMA1_PHYS_ADDR 0x14004200
397#define I2S_PHYS_ADDR 0x11000000
398#define UART0_PHYS_ADDR 0x11100000
399#define UART3_PHYS_ADDR 0x11400000
400#define GPIO2_PHYS_ADDR 0x11700000
401#define SYS_PHYS_ADDR 0x11900000
402#define PCI_MEM_PHYS_ADDR 0x400000000
403#define PCI_IO_PHYS_ADDR 0x500000000
404#define PCI_CONFIG0_PHYS_ADDR 0x600000000
405#define PCI_CONFIG1_PHYS_ADDR 0x680000000
406#define PCMCIA_IO_PHYS_ADDR 0xF00000000
407#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
408#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
409#endif
410
411/********************************************************************/
412
413#ifdef CONFIG_SOC_AU1100
414#define MEM_PHYS_ADDR 0x14000000
415#define STATIC_MEM_PHYS_ADDR 0x14001000
416#define DMA0_PHYS_ADDR 0x14002000
417#define DMA1_PHYS_ADDR 0x14002100
418#define DMA2_PHYS_ADDR 0x14002200
419#define DMA3_PHYS_ADDR 0x14002300
420#define DMA4_PHYS_ADDR 0x14002400
421#define DMA5_PHYS_ADDR 0x14002500
422#define DMA6_PHYS_ADDR 0x14002600
423#define DMA7_PHYS_ADDR 0x14002700
424#define IC0_PHYS_ADDR 0x10400000
425#define SD0_PHYS_ADDR 0x10600000
426#define SD1_PHYS_ADDR 0x10680000
427#define IC1_PHYS_ADDR 0x11800000
428#define AC97_PHYS_ADDR 0x10000000
429#define USBH_PHYS_ADDR 0x10100000
430#define USBD_PHYS_ADDR 0x10200000
431#define IRDA_PHYS_ADDR 0x10300000
432#define MAC0_PHYS_ADDR 0x10500000
433#define MACEN_PHYS_ADDR 0x10520000
434#define MACDMA0_PHYS_ADDR 0x14004000
435#define MACDMA1_PHYS_ADDR 0x14004200
436#define I2S_PHYS_ADDR 0x11000000
437#define UART0_PHYS_ADDR 0x11100000
438#define UART1_PHYS_ADDR 0x11200000
439#define UART3_PHYS_ADDR 0x11400000
440#define SSI0_PHYS_ADDR 0x11600000
441#define SSI1_PHYS_ADDR 0x11680000
442#define GPIO2_PHYS_ADDR 0x11700000
443#define SYS_PHYS_ADDR 0x11900000
444#define LCD_PHYS_ADDR 0x15000000
445#define PCMCIA_IO_PHYS_ADDR 0xF00000000
446#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
447#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
448#endif
449
450/***********************************************************************/
451
452#ifdef CONFIG_SOC_AU1550
453#define MEM_PHYS_ADDR 0x14000000
454#define STATIC_MEM_PHYS_ADDR 0x14001000
455#define IC0_PHYS_ADDR 0x10400000
456#define IC1_PHYS_ADDR 0x11800000
457#define USBH_PHYS_ADDR 0x14020000
458#define USBD_PHYS_ADDR 0x10200000
459#define PCI_PHYS_ADDR 0x14005000
460#define MAC0_PHYS_ADDR 0x10500000
461#define MAC1_PHYS_ADDR 0x10510000
462#define MACEN_PHYS_ADDR 0x10520000
463#define MACDMA0_PHYS_ADDR 0x14004000
464#define MACDMA1_PHYS_ADDR 0x14004200
465#define UART0_PHYS_ADDR 0x11100000
466#define UART1_PHYS_ADDR 0x11200000
467#define UART3_PHYS_ADDR 0x11400000
468#define GPIO2_PHYS_ADDR 0x11700000
469#define SYS_PHYS_ADDR 0x11900000
470#define DDMA_PHYS_ADDR 0x14002000
471#define PE_PHYS_ADDR 0x14008000
472#define PSC0_PHYS_ADDR 0x11A00000
473#define PSC1_PHYS_ADDR 0x11B00000
474#define PSC2_PHYS_ADDR 0x10A00000
475#define PSC3_PHYS_ADDR 0x10B00000
476#define PCI_MEM_PHYS_ADDR 0x400000000
477#define PCI_IO_PHYS_ADDR 0x500000000
478#define PCI_CONFIG0_PHYS_ADDR 0x600000000
479#define PCI_CONFIG1_PHYS_ADDR 0x680000000
480#define PCMCIA_IO_PHYS_ADDR 0xF00000000
481#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
482#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
483#endif
484
485/***********************************************************************/
486
487#ifdef CONFIG_SOC_AU1200
488#define MEM_PHYS_ADDR 0x14000000
489#define STATIC_MEM_PHYS_ADDR 0x14001000
490#define AES_PHYS_ADDR 0x10300000
491#define CIM_PHYS_ADDR 0x14004000
492#define IC0_PHYS_ADDR 0x10400000
493#define IC1_PHYS_ADDR 0x11800000
494#define USBM_PHYS_ADDR 0x14020000
495#define USBH_PHYS_ADDR 0x14020100
496#define UART0_PHYS_ADDR 0x11100000
497#define UART1_PHYS_ADDR 0x11200000
498#define GPIO2_PHYS_ADDR 0x11700000
499#define SYS_PHYS_ADDR 0x11900000
500#define DDMA_PHYS_ADDR 0x14002000
501#define PSC0_PHYS_ADDR 0x11A00000
502#define PSC1_PHYS_ADDR 0x11B00000
503#define PCMCIA_IO_PHYS_ADDR 0xF00000000
504#define PCMCIA_ATTR_PHYS_ADDR 0xF40000000
505#define PCMCIA_MEM_PHYS_ADDR 0xF80000000
506#define SD0_PHYS_ADDR 0x10600000
507#define SD1_PHYS_ADDR 0x10680000
508#define LCD_PHYS_ADDR 0x15000000
509#define SWCNT_PHYS_ADDR 0x1110010C
510#define MAEFE_PHYS_ADDR 0x14012000
511#define MAEBE_PHYS_ADDR 0x14010000
512#endif
513
186 514
187/* Static Bus Controller */ 515/* Static Bus Controller */
188#define MEM_STCFG0 0xB4001000 516#define MEM_STCFG0 0xB4001000
@@ -369,7 +697,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
369#define AU1000_MAC0_ENABLE 0xB0520000 697#define AU1000_MAC0_ENABLE 0xB0520000
370#define AU1000_MAC1_ENABLE 0xB0520004 698#define AU1000_MAC1_ENABLE 0xB0520004
371#define NUM_ETH_INTERFACES 2 699#define NUM_ETH_INTERFACES 2
372#endif // CONFIG_SOC_AU1000 700#endif /* CONFIG_SOC_AU1000 */
373 701
374/* Au1500 */ 702/* Au1500 */
375#ifdef CONFIG_SOC_AU1500 703#ifdef CONFIG_SOC_AU1500
@@ -440,7 +768,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
440#define AU1500_MAC0_ENABLE 0xB1520000 768#define AU1500_MAC0_ENABLE 0xB1520000
441#define AU1500_MAC1_ENABLE 0xB1520004 769#define AU1500_MAC1_ENABLE 0xB1520004
442#define NUM_ETH_INTERFACES 2 770#define NUM_ETH_INTERFACES 2
443#endif // CONFIG_SOC_AU1500 771#endif /* CONFIG_SOC_AU1500 */
444 772
445/* Au1100 */ 773/* Au1100 */
446#ifdef CONFIG_SOC_AU1100 774#ifdef CONFIG_SOC_AU1100
@@ -485,6 +813,22 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
485#define AU1000_GPIO_13 45 813#define AU1000_GPIO_13 45
486#define AU1000_GPIO_14 46 814#define AU1000_GPIO_14 46
487#define AU1000_GPIO_15 47 815#define AU1000_GPIO_15 47
816#define AU1000_GPIO_16 48
817#define AU1000_GPIO_17 49
818#define AU1000_GPIO_18 50
819#define AU1000_GPIO_19 51
820#define AU1000_GPIO_20 52
821#define AU1000_GPIO_21 53
822#define AU1000_GPIO_22 54
823#define AU1000_GPIO_23 55
824#define AU1000_GPIO_24 56
825#define AU1000_GPIO_25 57
826#define AU1000_GPIO_26 58
827#define AU1000_GPIO_27 59
828#define AU1000_GPIO_28 60
829#define AU1000_GPIO_29 61
830#define AU1000_GPIO_30 62
831#define AU1000_GPIO_31 63
488 832
489#define UART0_ADDR 0xB1100000 833#define UART0_ADDR 0xB1100000
490#define UART1_ADDR 0xB1200000 834#define UART1_ADDR 0xB1200000
@@ -496,7 +840,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
496#define AU1100_ETH0_BASE 0xB0500000 840#define AU1100_ETH0_BASE 0xB0500000
497#define AU1100_MAC0_ENABLE 0xB0520000 841#define AU1100_MAC0_ENABLE 0xB0520000
498#define NUM_ETH_INTERFACES 1 842#define NUM_ETH_INTERFACES 1
499#endif // CONFIG_SOC_AU1100 843#endif /* CONFIG_SOC_AU1100 */
500 844
501#ifdef CONFIG_SOC_AU1550 845#ifdef CONFIG_SOC_AU1550
502#define AU1550_UART0_INT 0 846#define AU1550_UART0_INT 0
@@ -513,14 +857,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
513#define AU1550_PSC1_INT 11 857#define AU1550_PSC1_INT 11
514#define AU1550_PSC2_INT 12 858#define AU1550_PSC2_INT 12
515#define AU1550_PSC3_INT 13 859#define AU1550_PSC3_INT 13
516#define AU1550_TOY_INT 14 860#define AU1000_TOY_INT 14
517#define AU1550_TOY_MATCH0_INT 15 861#define AU1000_TOY_MATCH0_INT 15
518#define AU1550_TOY_MATCH1_INT 16 862#define AU1000_TOY_MATCH1_INT 16
519#define AU1550_TOY_MATCH2_INT 17 863#define AU1000_TOY_MATCH2_INT 17
520#define AU1550_RTC_INT 18 864#define AU1000_RTC_INT 18
521#define AU1550_RTC_MATCH0_INT 19 865#define AU1000_RTC_MATCH0_INT 19
522#define AU1550_RTC_MATCH1_INT 20 866#define AU1000_RTC_MATCH1_INT 20
523#define AU1550_RTC_MATCH2_INT 21 867#define AU1000_RTC_MATCH2_INT 21
524#define AU1550_NAND_INT 23 868#define AU1550_NAND_INT 23
525#define AU1550_USB_DEV_REQ_INT 24 869#define AU1550_USB_DEV_REQ_INT 24
526#define AU1550_USB_DEV_SUS_INT 25 870#define AU1550_USB_DEV_SUS_INT 25
@@ -575,7 +919,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
575#define AU1550_MAC0_ENABLE 0xB0520000 919#define AU1550_MAC0_ENABLE 0xB0520000
576#define AU1550_MAC1_ENABLE 0xB0520004 920#define AU1550_MAC1_ENABLE 0xB0520004
577#define NUM_ETH_INTERFACES 2 921#define NUM_ETH_INTERFACES 2
578#endif // CONFIG_SOC_AU1550 922#endif /* CONFIG_SOC_AU1550 */
579 923
580#ifdef CONFIG_SOC_AU1200 924#ifdef CONFIG_SOC_AU1200
581#define AU1200_UART0_INT 0 925#define AU1200_UART0_INT 0
@@ -592,14 +936,14 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
592#define AU1200_PSC1_INT 11 936#define AU1200_PSC1_INT 11
593#define AU1200_AES_INT 12 937#define AU1200_AES_INT 12
594#define AU1200_CAMERA_INT 13 938#define AU1200_CAMERA_INT 13
595#define AU1200_TOY_INT 14 939#define AU1000_TOY_INT 14
596#define AU1200_TOY_MATCH0_INT 15 940#define AU1000_TOY_MATCH0_INT 15
597#define AU1200_TOY_MATCH1_INT 16 941#define AU1000_TOY_MATCH1_INT 16
598#define AU1200_TOY_MATCH2_INT 17 942#define AU1000_TOY_MATCH2_INT 17
599#define AU1200_RTC_INT 18 943#define AU1000_RTC_INT 18
600#define AU1200_RTC_MATCH0_INT 19 944#define AU1000_RTC_MATCH0_INT 19
601#define AU1200_RTC_MATCH1_INT 20 945#define AU1000_RTC_MATCH1_INT 20
602#define AU1200_RTC_MATCH2_INT 21 946#define AU1000_RTC_MATCH2_INT 21
603#define AU1200_NAND_INT 23 947#define AU1200_NAND_INT 23
604#define AU1200_GPIO_204 24 948#define AU1200_GPIO_204 24
605#define AU1200_GPIO_205 25 949#define AU1200_GPIO_205 25
@@ -607,6 +951,7 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
607#define AU1200_GPIO_207 27 951#define AU1200_GPIO_207 27
608#define AU1200_GPIO_208_215 28 // Logical OR of 208:215 952#define AU1200_GPIO_208_215 28 // Logical OR of 208:215
609#define AU1200_USB_INT 29 953#define AU1200_USB_INT 29
954#define AU1000_USB_HOST_INT AU1200_USB_INT
610#define AU1200_LCD_INT 30 955#define AU1200_LCD_INT 30
611#define AU1200_MAE_BOTH_INT 31 956#define AU1200_MAE_BOTH_INT 31
612#define AU1000_GPIO_0 32 957#define AU1000_GPIO_0 32
@@ -645,21 +990,36 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
645#define UART0_ADDR 0xB1100000 990#define UART0_ADDR 0xB1100000
646#define UART1_ADDR 0xB1200000 991#define UART1_ADDR 0xB1200000
647 992
648#define USB_OHCI_BASE 0x14020000 // phys addr for ioremap 993#define USB_UOC_BASE 0x14020020
649#define USB_HOST_CONFIG 0xB4027ffc 994#define USB_UOC_LEN 0x20
650 995#define USB_OHCI_BASE 0x14020100
651// these are here for prototyping on au1550 (do not exist on au1200) 996#define USB_OHCI_LEN 0x100
652#define AU1200_ETH0_BASE 0xB0500000 997#define USB_EHCI_BASE 0x14020200
653#define AU1200_ETH1_BASE 0xB0510000 998#define USB_EHCI_LEN 0x100
654#define AU1200_MAC0_ENABLE 0xB0520000 999#define USB_UDC_BASE 0x14022000
655#define AU1200_MAC1_ENABLE 0xB0520004 1000#define USB_UDC_LEN 0x2000
656#define NUM_ETH_INTERFACES 2 1001#define USB_MSR_BASE 0xB4020000
657#endif // CONFIG_SOC_AU1200 1002#define USB_MSR_MCFG 4
1003#define USBMSRMCFG_OMEMEN 0
1004#define USBMSRMCFG_OBMEN 1
1005#define USBMSRMCFG_EMEMEN 2
1006#define USBMSRMCFG_EBMEN 3
1007#define USBMSRMCFG_DMEMEN 4
1008#define USBMSRMCFG_DBMEN 5
1009#define USBMSRMCFG_GMEMEN 6
1010#define USBMSRMCFG_OHCCLKEN 16
1011#define USBMSRMCFG_EHCCLKEN 17
1012#define USBMSRMCFG_UDCCLKEN 18
1013#define USBMSRMCFG_PHYPLLEN 19
1014#define USBMSRMCFG_RDCOMB 30
1015#define USBMSRMCFG_PFEN 31
1016
1017#endif /* CONFIG_SOC_AU1200 */
658 1018
659#define AU1000_LAST_INTC0_INT 31 1019#define AU1000_LAST_INTC0_INT 31
1020#define AU1000_LAST_INTC1_INT 63
660#define AU1000_MAX_INTR 63 1021#define AU1000_MAX_INTR 63
661 1022
662
663/* Programmable Counters 0 and 1 */ 1023/* Programmable Counters 0 and 1 */
664#define SYS_BASE 0xB1900000 1024#define SYS_BASE 0xB1900000
665#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14) 1025#define SYS_COUNTER_CNTRL (SYS_BASE + 0x14)
@@ -730,6 +1090,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
730 #define I2S_CONTROL_D (1<<1) 1090 #define I2S_CONTROL_D (1<<1)
731 #define I2S_CONTROL_CE (1<<0) 1091 #define I2S_CONTROL_CE (1<<0)
732 1092
1093#ifndef CONFIG_SOC_AU1200
1094
733/* USB Host Controller */ 1095/* USB Host Controller */
734#define USB_OHCI_LEN 0x00100000 1096#define USB_OHCI_LEN 0x00100000
735 1097
@@ -775,6 +1137,8 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
775 #define USBDEV_ENABLE (1<<1) 1137 #define USBDEV_ENABLE (1<<1)
776 #define USBDEV_CE (1<<0) 1138 #define USBDEV_CE (1<<0)
777 1139
1140#endif /* !CONFIG_SOC_AU1200 */
1141
778/* Ethernet Controllers */ 1142/* Ethernet Controllers */
779 1143
780/* 4 byte offsets from AU1000_ETH_BASE */ 1144/* 4 byte offsets from AU1000_ETH_BASE */
@@ -1173,6 +1537,37 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1173 #define SYS_PF_PSC1_S1 (1 << 1) 1537 #define SYS_PF_PSC1_S1 (1 << 1)
1174 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2)) 1538 #define SYS_PF_MUST_BE_SET ((1 << 5) | (1 << 2))
1175 1539
1540/* Au1200 Only */
1541#ifdef CONFIG_SOC_AU1200
1542#define SYS_PINFUNC_DMA (1<<31)
1543#define SYS_PINFUNC_S0A (1<<30)
1544#define SYS_PINFUNC_S1A (1<<29)
1545#define SYS_PINFUNC_LP0 (1<<28)
1546#define SYS_PINFUNC_LP1 (1<<27)
1547#define SYS_PINFUNC_LD16 (1<<26)
1548#define SYS_PINFUNC_LD8 (1<<25)
1549#define SYS_PINFUNC_LD1 (1<<24)
1550#define SYS_PINFUNC_LD0 (1<<23)
1551#define SYS_PINFUNC_P1A (3<<21)
1552#define SYS_PINFUNC_P1B (1<<20)
1553#define SYS_PINFUNC_FS3 (1<<19)
1554#define SYS_PINFUNC_P0A (3<<17)
1555#define SYS_PINFUNC_CS (1<<16)
1556#define SYS_PINFUNC_CIM (1<<15)
1557#define SYS_PINFUNC_P1C (1<<14)
1558#define SYS_PINFUNC_U1T (1<<12)
1559#define SYS_PINFUNC_U1R (1<<11)
1560#define SYS_PINFUNC_EX1 (1<<10)
1561#define SYS_PINFUNC_EX0 (1<<9)
1562#define SYS_PINFUNC_U0R (1<<8)
1563#define SYS_PINFUNC_MC (1<<7)
1564#define SYS_PINFUNC_S0B (1<<6)
1565#define SYS_PINFUNC_S0C (1<<5)
1566#define SYS_PINFUNC_P0B (1<<4)
1567#define SYS_PINFUNC_U0T (1<<3)
1568#define SYS_PINFUNC_S1B (1<<2)
1569#endif
1570
1176#define SYS_TRIOUTRD 0xB1900100 1571#define SYS_TRIOUTRD 0xB1900100
1177#define SYS_TRIOUTCLR 0xB1900100 1572#define SYS_TRIOUTCLR 0xB1900100
1178#define SYS_OUTPUTRD 0xB1900108 1573#define SYS_OUTPUTRD 0xB1900108
@@ -1300,7 +1695,6 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1300#define SD1_XMIT_FIFO 0xB0680000 1695#define SD1_XMIT_FIFO 0xB0680000
1301#define SD1_RECV_FIFO 0xB0680004 1696#define SD1_RECV_FIFO 0xB0680004
1302 1697
1303
1304#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550) 1698#if defined (CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
1305/* Au1500 PCI Controller */ 1699/* Au1500 PCI Controller */
1306#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr 1700#define Au1500_CFG_BASE 0xB4005000 // virtual, kseg0 addr
@@ -1363,36 +1757,77 @@ extern au1xxx_irq_map_t au1xxx_irq_map[];
1363 _ctl_; }) 1757 _ctl_; })
1364 1758
1365 1759
1366#else /* Au1000 and Au1100 */ 1760#else /* Au1000 and Au1100 and Au1200 */
1367 1761
1368/* don't allow any legacy ports probing */ 1762/* don't allow any legacy ports probing */
1369#define IOPORT_RESOURCE_START 0x10000000; 1763#define IOPORT_RESOURCE_START 0x10000000
1370#define IOPORT_RESOURCE_END 0xffffffff 1764#define IOPORT_RESOURCE_END 0xffffffff
1371#define IOMEM_RESOURCE_START 0x10000000 1765#define IOMEM_RESOURCE_START 0x10000000
1372#define IOMEM_RESOURCE_END 0xffffffff 1766#define IOMEM_RESOURCE_END 0xffffffff
1373 1767
1374#ifdef CONFIG_MIPS_PB1000
1375#define PCI_IO_START 0x10000000
1376#define PCI_IO_END 0x1000ffff
1377#define PCI_MEM_START 0x18000000
1378#define PCI_MEM_END 0x18ffffff
1379#define PCI_FIRST_DEVFN 0
1380#define PCI_LAST_DEVFN 1
1381#else
1382/* no PCI bus controller */
1383#define PCI_IO_START 0 1768#define PCI_IO_START 0
1384#define PCI_IO_END 0 1769#define PCI_IO_END 0
1385#define PCI_MEM_START 0 1770#define PCI_MEM_START 0
1386#define PCI_MEM_END 0 1771#define PCI_MEM_END 0
1387#define PCI_FIRST_DEVFN 0 1772#define PCI_FIRST_DEVFN 0
1388#define PCI_LAST_DEVFN 0 1773#define PCI_LAST_DEVFN 0
1389#endif
1390 1774
1391#endif 1775#endif
1392 1776
1777#ifndef _LANGUAGE_ASSEMBLY
1778typedef volatile struct
1779{
1780 /* 0x0000 */ u32 toytrim;
1781 /* 0x0004 */ u32 toywrite;
1782 /* 0x0008 */ u32 toymatch0;
1783 /* 0x000C */ u32 toymatch1;
1784 /* 0x0010 */ u32 toymatch2;
1785 /* 0x0014 */ u32 cntrctrl;
1786 /* 0x0018 */ u32 scratch0;
1787 /* 0x001C */ u32 scratch1;
1788 /* 0x0020 */ u32 freqctrl0;
1789 /* 0x0024 */ u32 freqctrl1;
1790 /* 0x0028 */ u32 clksrc;
1791 /* 0x002C */ u32 pinfunc;
1792 /* 0x0030 */ u32 reserved0;
1793 /* 0x0034 */ u32 wakemsk;
1794 /* 0x0038 */ u32 endian;
1795 /* 0x003C */ u32 powerctrl;
1796 /* 0x0040 */ u32 toyread;
1797 /* 0x0044 */ u32 rtctrim;
1798 /* 0x0048 */ u32 rtcwrite;
1799 /* 0x004C */ u32 rtcmatch0;
1800 /* 0x0050 */ u32 rtcmatch1;
1801 /* 0x0054 */ u32 rtcmatch2;
1802 /* 0x0058 */ u32 rtcread;
1803 /* 0x005C */ u32 wakesrc;
1804 /* 0x0060 */ u32 cpupll;
1805 /* 0x0064 */ u32 auxpll;
1806 /* 0x0068 */ u32 reserved1;
1807 /* 0x006C */ u32 reserved2;
1808 /* 0x0070 */ u32 reserved3;
1809 /* 0x0074 */ u32 reserved4;
1810 /* 0x0078 */ u32 slppwr;
1811 /* 0x007C */ u32 sleep;
1812 /* 0x0080 */ u32 reserved5[32];
1813 /* 0x0100 */ u32 trioutrd;
1814#define trioutclr trioutrd
1815 /* 0x0104 */ u32 reserved6;
1816 /* 0x0108 */ u32 outputrd;
1817#define outputset outputrd
1818 /* 0x010C */ u32 outputclr;
1819 /* 0x0110 */ u32 pinstaterd;
1820#define pininputen pinstaterd
1821
1822} AU1X00_SYS;
1823
1824static AU1X00_SYS* const sys = (AU1X00_SYS *)SYS_BASE;
1825
1826#endif
1393/* Processor information base on prid. 1827/* Processor information base on prid.
1394 * Copied from PowerPC. 1828 * Copied from PowerPC.
1395 */ 1829 */
1830#ifndef _LANGUAGE_ASSEMBLY
1396struct cpu_spec { 1831struct cpu_spec {
1397 /* CPU is matched via (PRID & prid_mask) == prid_value */ 1832 /* CPU is matched via (PRID & prid_mask) == prid_value */
1398 unsigned int prid_mask; 1833 unsigned int prid_mask;
@@ -1406,3 +1841,6 @@ struct cpu_spec {
1406extern struct cpu_spec cpu_specs[]; 1841extern struct cpu_spec cpu_specs[];
1407extern struct cpu_spec *cur_cpu_spec[]; 1842extern struct cpu_spec *cur_cpu_spec[];
1408#endif 1843#endif
1844
1845#endif
1846
diff --git a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
index d5eb88cd7d51..ddbd9f5a2489 100644
--- a/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
+++ b/include/asm-mips/mach-au1x00/au1xxx_dbdma.h
@@ -45,7 +45,7 @@
45#define DDMA_GLOBAL_BASE 0xb4003000 45#define DDMA_GLOBAL_BASE 0xb4003000
46#define DDMA_CHANNEL_BASE 0xb4002000 46#define DDMA_CHANNEL_BASE 0xb4002000
47 47
48typedef struct dbdma_global { 48typedef volatile struct dbdma_global {
49 u32 ddma_config; 49 u32 ddma_config;
50 u32 ddma_intstat; 50 u32 ddma_intstat;
51 u32 ddma_throttle; 51 u32 ddma_throttle;
@@ -62,7 +62,7 @@ typedef struct dbdma_global {
62 62
63/* The structure of a DMA Channel. 63/* The structure of a DMA Channel.
64*/ 64*/
65typedef struct au1xxx_dma_channel { 65typedef volatile struct au1xxx_dma_channel {
66 u32 ddma_cfg; /* See below */ 66 u32 ddma_cfg; /* See below */
67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */ 67 u32 ddma_desptr; /* 32-byte aligned pointer to descriptor */
68 u32 ddma_statptr; /* word aligned pointer to status word */ 68 u32 ddma_statptr; /* word aligned pointer to status word */
@@ -98,7 +98,7 @@ typedef struct au1xxx_dma_channel {
98/* "Standard" DDMA Descriptor. 98/* "Standard" DDMA Descriptor.
99 * Must be 32-byte aligned. 99 * Must be 32-byte aligned.
100 */ 100 */
101typedef struct au1xxx_ddma_desc { 101typedef volatile struct au1xxx_ddma_desc {
102 u32 dscr_cmd0; /* See below */ 102 u32 dscr_cmd0; /* See below */
103 u32 dscr_cmd1; /* See below */ 103 u32 dscr_cmd1; /* See below */
104 u32 dscr_source0; /* source phys address */ 104 u32 dscr_source0; /* source phys address */
@@ -107,6 +107,12 @@ typedef struct au1xxx_ddma_desc {
107 u32 dscr_dest1; /* See below */ 107 u32 dscr_dest1; /* See below */
108 u32 dscr_stat; /* completion status */ 108 u32 dscr_stat; /* completion status */
109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */ 109 u32 dscr_nxtptr; /* Next descriptor pointer (mostly) */
110 /* First 32bytes are HW specific!!!
111 Lets have some SW data following.. make sure its 32bytes
112 */
113 u32 sw_status;
114 u32 sw_context;
115 u32 sw_reserved[6];
110} au1x_ddma_desc_t; 116} au1x_ddma_desc_t;
111 117
112#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */ 118#define DSCR_CMD0_V (1 << 31) /* Descriptor valid */
@@ -125,8 +131,11 @@ typedef struct au1xxx_ddma_desc {
125#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */ 131#define DSCR_CMD0_CV (0x1 << 2) /* Clear Valid when done */
126#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */ 132#define DSCR_CMD0_ST_MASK (0x3 << 0) /* Status instruction */
127 133
134#define SW_STATUS_INUSE (1<<0)
135
128/* Command 0 device IDs. 136/* Command 0 device IDs.
129*/ 137*/
138#ifdef CONFIG_SOC_AU1550
130#define DSCR_CMD0_UART0_TX 0 139#define DSCR_CMD0_UART0_TX 0
131#define DSCR_CMD0_UART0_RX 1 140#define DSCR_CMD0_UART0_RX 1
132#define DSCR_CMD0_UART3_TX 2 141#define DSCR_CMD0_UART3_TX 2
@@ -155,9 +164,45 @@ typedef struct au1xxx_ddma_desc {
155#define DSCR_CMD0_MAC0_TX 25 164#define DSCR_CMD0_MAC0_TX 25
156#define DSCR_CMD0_MAC1_RX 26 165#define DSCR_CMD0_MAC1_RX 26
157#define DSCR_CMD0_MAC1_TX 27 166#define DSCR_CMD0_MAC1_TX 27
167#endif /* CONFIG_SOC_AU1550 */
168
169#ifdef CONFIG_SOC_AU1200
170#define DSCR_CMD0_UART0_TX 0
171#define DSCR_CMD0_UART0_RX 1
172#define DSCR_CMD0_UART1_TX 2
173#define DSCR_CMD0_UART1_RX 3
174#define DSCR_CMD0_DMA_REQ0 4
175#define DSCR_CMD0_DMA_REQ1 5
176#define DSCR_CMD0_MAE_BE 6
177#define DSCR_CMD0_MAE_FE 7
178#define DSCR_CMD0_SDMS_TX0 8
179#define DSCR_CMD0_SDMS_RX0 9
180#define DSCR_CMD0_SDMS_TX1 10
181#define DSCR_CMD0_SDMS_RX1 11
182#define DSCR_CMD0_AES_TX 13
183#define DSCR_CMD0_AES_RX 12
184#define DSCR_CMD0_PSC0_TX 14
185#define DSCR_CMD0_PSC0_RX 15
186#define DSCR_CMD0_PSC1_TX 16
187#define DSCR_CMD0_PSC1_RX 17
188#define DSCR_CMD0_CIM_RXA 18
189#define DSCR_CMD0_CIM_RXB 19
190#define DSCR_CMD0_CIM_RXC 20
191#define DSCR_CMD0_MAE_BOTH 21
192#define DSCR_CMD0_LCD 22
193#define DSCR_CMD0_NAND_FLASH 23
194#define DSCR_CMD0_PSC0_SYNC 24
195#define DSCR_CMD0_PSC1_SYNC 25
196#define DSCR_CMD0_CIM_SYNC 26
197#endif /* CONFIG_SOC_AU1200 */
198
158#define DSCR_CMD0_THROTTLE 30 199#define DSCR_CMD0_THROTTLE 30
159#define DSCR_CMD0_ALWAYS 31 200#define DSCR_CMD0_ALWAYS 31
160#define DSCR_NDEV_IDS 32 201#define DSCR_NDEV_IDS 32
202/* THis macro is used to find/create custom device types */
203#define DSCR_DEV2CUSTOM_ID(x,d) (((((x)&0xFFFF)<<8)|0x32000000)|((d)&0xFF))
204#define DSCR_CUSTOM2DEV_ID(x) ((x)&0xFF)
205
161 206
162#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25) 207#define DSCR_CMD0_SID(x) (((x) & 0x1f) << 25)
163#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20) 208#define DSCR_CMD0_DID(x) (((x) & 0x1f) << 20)
@@ -246,6 +291,43 @@ typedef struct au1xxx_ddma_desc {
246*/ 291*/
247#define NUM_DBDMA_CHANS 16 292#define NUM_DBDMA_CHANS 16
248 293
294/*
295 * Ddma API definitions
296 * FIXME: may not fit to this header file
297 */
298typedef struct dbdma_device_table {
299 u32 dev_id;
300 u32 dev_flags;
301 u32 dev_tsize;
302 u32 dev_devwidth;
303 u32 dev_physaddr; /* If FIFO */
304 u32 dev_intlevel;
305 u32 dev_intpolarity;
306} dbdev_tab_t;
307
308
309typedef struct dbdma_chan_config {
310 spinlock_t lock;
311
312 u32 chan_flags;
313 u32 chan_index;
314 dbdev_tab_t *chan_src;
315 dbdev_tab_t *chan_dest;
316 au1x_dma_chan_t *chan_ptr;
317 au1x_ddma_desc_t *chan_desc_base;
318 au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
319 void *chan_callparam;
320 void (*chan_callback)(int, void *, struct pt_regs *);
321} chan_tab_t;
322
323#define DEV_FLAGS_INUSE (1 << 0)
324#define DEV_FLAGS_ANYUSE (1 << 1)
325#define DEV_FLAGS_OUT (1 << 2)
326#define DEV_FLAGS_IN (1 << 3)
327#define DEV_FLAGS_BURSTABLE (1 << 4)
328#define DEV_FLAGS_SYNC (1 << 5)
329/* end Ddma API definitions */
330
249/* External functions for drivers to use. 331/* External functions for drivers to use.
250*/ 332*/
251/* Use this to allocate a dbdma channel. The device ids are one of the 333/* Use this to allocate a dbdma channel. The device ids are one of the
@@ -258,18 +340,6 @@ u32 au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
258 340
259#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS 341#define DBDMA_MEM_CHAN DSCR_CMD0_ALWAYS
260 342
261/* ACK! These should be in a board specific description file.
262*/
263#ifdef CONFIG_MIPS_PB1550
264#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
265#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
266#endif
267#ifdef CONFIG_MIPS_DB1550
268#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
269#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
270#endif
271
272
273/* Set the device width of a in/out fifo. 343/* Set the device width of a in/out fifo.
274*/ 344*/
275u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits); 345u32 au1xxx_dbdma_set_devwidth(u32 chanid, int bits);
@@ -280,8 +350,8 @@ u32 au1xxx_dbdma_ring_alloc(u32 chanid, int entries);
280 350
281/* Put buffers on source/destination descriptors. 351/* Put buffers on source/destination descriptors.
282*/ 352*/
283u32 au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes); 353u32 _au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes, u32 flags);
284u32 au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes); 354u32 _au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes, u32 flags);
285 355
286/* Get a buffer from the destination descriptor. 356/* Get a buffer from the destination descriptor.
287*/ 357*/
@@ -295,5 +365,25 @@ u32 au1xxx_get_dma_residue(u32 chanid);
295void au1xxx_dbdma_chan_free(u32 chanid); 365void au1xxx_dbdma_chan_free(u32 chanid);
296void au1xxx_dbdma_dump(u32 chanid); 366void au1xxx_dbdma_dump(u32 chanid);
297 367
368u32 au1xxx_dbdma_put_dscr(u32 chanid, au1x_ddma_desc_t *dscr );
369
370u32 au1xxx_ddma_add_device( dbdev_tab_t *dev );
371
372/*
373 Some compatibilty macros --
374 Needed to make changes to API without breaking existing drivers
375*/
376#define au1xxx_dbdma_put_source(chanid,buf,nbytes)_au1xxx_dbdma_put_source(chanid, buf, nbytes, DDMA_FLAGS_IE)
377#define au1xxx_dbdma_put_source_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_source(chanid, buf, nbytes, flags)
378
379#define au1xxx_dbdma_put_dest(chanid,buf,nbytes) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, DDMA_FLAGS_IE)
380#define au1xxx_dbdma_put_dest_flags(chanid,buf,nbytes,flags) _au1xxx_dbdma_put_dest(chanid, buf, nbytes, flags)
381
382/*
383 * Flags for the put_source/put_dest functions.
384 */
385#define DDMA_FLAGS_IE (1<<0)
386#define DDMA_FLAGS_NOIE (1<<1)
387
298#endif /* _LANGUAGE_ASSEMBLY */ 388#endif /* _LANGUAGE_ASSEMBLY */
299#endif /* _AU1000_DBDMA_H_ */ 389#endif /* _AU1000_DBDMA_H_ */
diff --git a/include/asm-mips/mach-db1x00/db1200.h b/include/asm-mips/mach-db1x00/db1200.h
new file mode 100644
index 000000000000..6d1ddf43d290
--- /dev/null
+++ b/include/asm-mips/mach-db1x00/db1200.h
@@ -0,0 +1,214 @@
1/*
2 * AMD Alchemy DB1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_DB1200_H
25#define __ASM_DB1200_H
26
27#include <linux/types.h>
28
29// This is defined in au1000.h with bogus value
30#undef AU1X00_EXTERNAL_INT
31
32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36
37/* SPI and SMB are muxed on the Pb1200 board.
38 Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/* AC97 and I2S are muxed on the Pb1200 board.
43 Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xB9800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_U0RXD 0x1000
106#define BCSR_STATUS_U1RXD 0x2000
107
108#define BCSR_SWITCHES_OCTAL 0x00FF
109#define BCSR_SWITCHES_DIP_1 0x0080
110#define BCSR_SWITCHES_DIP_2 0x0040
111#define BCSR_SWITCHES_DIP_3 0x0020
112#define BCSR_SWITCHES_DIP_4 0x0010
113#define BCSR_SWITCHES_DIP_5 0x0008
114#define BCSR_SWITCHES_DIP_6 0x0004
115#define BCSR_SWITCHES_DIP_7 0x0002
116#define BCSR_SWITCHES_DIP_8 0x0001
117#define BCSR_SWITCHES_ROTARY 0x0F00
118
119#define BCSR_RESETS_ETH 0x0001
120#define BCSR_RESETS_CAMERA 0x0002
121#define BCSR_RESETS_DC 0x0004
122#define BCSR_RESETS_IDE 0x0008
123#define BCSR_RESETS_TV 0x0010
124/* not resets but in the same register */
125#define BCSR_RESETS_PWMR1mUX 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129
130#define BCSR_PCMCIA_PC0VPP 0x0003
131#define BCSR_PCMCIA_PC0VCC 0x000C
132#define BCSR_PCMCIA_PC0DRVEN 0x0010
133#define BCSR_PCMCIA_PC0RST 0x0080
134#define BCSR_PCMCIA_PC1VPP 0x0300
135#define BCSR_PCMCIA_PC1VCC 0x0C00
136#define BCSR_PCMCIA_PC1DRVEN 0x1000
137#define BCSR_PCMCIA_PC1RST 0x8000
138
139#define BCSR_BOARD_LCDVEE 0x0001
140#define BCSR_BOARD_LCDVDD 0x0002
141#define BCSR_BOARD_LCDBL 0x0004
142#define BCSR_BOARD_CAMSNAP 0x0010
143#define BCSR_BOARD_CAMPWR 0x0020
144#define BCSR_BOARD_SD0PWR 0x0040
145
146#define BCSR_LEDS_DECIMALS 0x0003
147#define BCSR_LEDS_LED0 0x0100
148#define BCSR_LEDS_LED1 0x0200
149#define BCSR_LEDS_LED2 0x0400
150#define BCSR_LEDS_LED3 0x0800
151
152#define BCSR_SYSTEM_POWEROFF 0x4000
153#define BCSR_SYSTEM_RESET 0x8000
154
155/* Bit positions for the different interrupt sources */
156#define BCSR_INT_IDE 0x0001
157#define BCSR_INT_ETH 0x0002
158#define BCSR_INT_PC0 0x0004
159#define BCSR_INT_PC0STSCHG 0x0008
160#define BCSR_INT_PC1 0x0010
161#define BCSR_INT_PC1STSCHG 0x0020
162#define BCSR_INT_DC 0x0040
163#define BCSR_INT_FLASHBUSY 0x0080
164#define BCSR_INT_PC0INSERT 0x0100
165#define BCSR_INT_PC0EJECT 0x0200
166#define BCSR_INT_PC1INSERT 0x0400
167#define BCSR_INT_PC1EJECT 0x0800
168#define BCSR_INT_SD0INSERT 0x1000
169#define BCSR_INT_SD0EJECT 0x2000
170
171#define AU1XXX_SMC91111_PHYS_ADDR (0x19000300)
172#define AU1XXX_SMC91111_IRQ DB1200_ETH_INT
173
174#define AU1XXX_ATA_PHYS_ADDR (0x18800000)
175#define AU1XXX_ATA_PHYS_LEN (0x100)
176#define AU1XXX_ATA_REG_OFFSET (5)
177#define AU1XXX_ATA_INT DB1200_IDE_INT
178#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
179#define AU1XXX_ATA_RQSIZE 128
180
181#define NAND_PHYS_ADDR 0x20000000
182
183/*
184 * External Interrupts for Pb1200 as of 8/6/2004.
185 * Bit positions in the CPLD registers can be calculated by taking
186 * the interrupt define and subtracting the DB1200_INT_BEGIN value.
187 * *example: IDE bis pos is = 64 - 64
188 ETH bit pos is = 65 - 64
189 */
190#define DB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
191#define DB1200_IDE_INT (DB1200_INT_BEGIN + 0)
192#define DB1200_ETH_INT (DB1200_INT_BEGIN + 1)
193#define DB1200_PC0_INT (DB1200_INT_BEGIN + 2)
194#define DB1200_PC0_STSCHG_INT (DB1200_INT_BEGIN + 3)
195#define DB1200_PC1_INT (DB1200_INT_BEGIN + 4)
196#define DB1200_PC1_STSCHG_INT (DB1200_INT_BEGIN + 5)
197#define DB1200_DC_INT (DB1200_INT_BEGIN + 6)
198#define DB1200_FLASHBUSY_INT (DB1200_INT_BEGIN + 7)
199#define DB1200_PC0_INSERT_INT (DB1200_INT_BEGIN + 8)
200#define DB1200_PC0_EJECT_INT (DB1200_INT_BEGIN + 9)
201#define DB1200_PC1_INSERT_INT (DB1200_INT_BEGIN + 10)
202#define DB1200_PC1_EJECT_INT (DB1200_INT_BEGIN + 11)
203#define DB1200_SD0_INSERT_INT (DB1200_INT_BEGIN + 12)
204#define DB1200_SD0_EJECT_INT (DB1200_INT_BEGIN + 13)
205
206#define DB1200_INT_END (DB1200_INT_BEGIN + 15)
207
208/* For drivers/pcmcia/au1000_db1x00.c */
209#define BOARD_PC0_INT DB1200_PC0_INT
210#define BOARD_PC1_INT DB1200_PC1_INT
211#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
212
213#endif /* __ASM_DB1200_H */
214
diff --git a/include/asm-mips/mach-pb1x00/pb1200.h b/include/asm-mips/mach-pb1x00/pb1200.h
new file mode 100644
index 000000000000..0f6646335e90
--- /dev/null
+++ b/include/asm-mips/mach-pb1x00/pb1200.h
@@ -0,0 +1,244 @@
1/*
2 * AMD Alchemy PB1200 Referrence Board
3 * Board Registers defines.
4 *
5 * ########################################################################
6 *
7 * This program is free software; you can distribute it and/or modify it
8 * under the terms of the GNU General Public License (Version 2) as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope it will be useful, but WITHOUT
12 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
13 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
14 * for more details.
15 *
16 * You should have received a copy of the GNU General Public License along
17 * with this program; if not, write to the Free Software Foundation, Inc.,
18 * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
19 *
20 * ########################################################################
21 *
22 *
23 */
24#ifndef __ASM_PB1200_H
25#define __ASM_PB1200_H
26
27#include <linux/types.h>
28
29// This is defined in au1000.h with bogus value
30#undef AU1X00_EXTERNAL_INT
31
32#define DBDMA_AC97_TX_CHAN DSCR_CMD0_PSC1_TX
33#define DBDMA_AC97_RX_CHAN DSCR_CMD0_PSC1_RX
34#define DBDMA_I2S_TX_CHAN DSCR_CMD0_PSC1_TX
35#define DBDMA_I2S_RX_CHAN DSCR_CMD0_PSC1_RX
36
37/* SPI and SMB are muxed on the Pb1200 board.
38 Refer to board documentation.
39 */
40#define SPI_PSC_BASE PSC0_BASE_ADDR
41#define SMBUS_PSC_BASE PSC0_BASE_ADDR
42/* AC97 and I2S are muxed on the Pb1200 board.
43 Refer to board documentation.
44 */
45#define AC97_PSC_BASE PSC1_BASE_ADDR
46#define I2S_PSC_BASE PSC1_BASE_ADDR
47
48#define BCSR_KSEG1_ADDR 0xAD800000
49
50typedef volatile struct
51{
52 /*00*/ u16 whoami;
53 u16 reserved0;
54 /*04*/ u16 status;
55 u16 reserved1;
56 /*08*/ u16 switches;
57 u16 reserved2;
58 /*0C*/ u16 resets;
59 u16 reserved3;
60
61 /*10*/ u16 pcmcia;
62 u16 reserved4;
63 /*14*/ u16 board;
64 u16 reserved5;
65 /*18*/ u16 disk_leds;
66 u16 reserved6;
67 /*1C*/ u16 system;
68 u16 reserved7;
69
70 /*20*/ u16 intclr;
71 u16 reserved8;
72 /*24*/ u16 intset;
73 u16 reserved9;
74 /*28*/ u16 intclr_mask;
75 u16 reserved10;
76 /*2C*/ u16 intset_mask;
77 u16 reserved11;
78
79 /*30*/ u16 sig_status;
80 u16 reserved12;
81 /*34*/ u16 int_status;
82 u16 reserved13;
83 /*38*/ u16 reserved14;
84 u16 reserved15;
85 /*3C*/ u16 reserved16;
86 u16 reserved17;
87
88} BCSR;
89
90static BCSR * const bcsr = (BCSR *)BCSR_KSEG1_ADDR;
91
92/*
93 * Register bit definitions for the BCSRs
94 */
95#define BCSR_WHOAMI_DCID 0x000F
96#define BCSR_WHOAMI_CPLD 0x00F0
97#define BCSR_WHOAMI_BOARD 0x0F00
98
99#define BCSR_STATUS_PCMCIA0VS 0x0003
100#define BCSR_STATUS_PCMCIA1VS 0x000C
101#define BCSR_STATUS_SWAPBOOT 0x0040
102#define BCSR_STATUS_FLASHBUSY 0x0100
103#define BCSR_STATUS_IDECBLID 0x0200
104#define BCSR_STATUS_SD0WP 0x0400
105#define BCSR_STATUS_SD1WP 0x0800
106#define BCSR_STATUS_U0RXD 0x1000
107#define BCSR_STATUS_U1RXD 0x2000
108
109#define BCSR_SWITCHES_OCTAL 0x00FF
110#define BCSR_SWITCHES_DIP_1 0x0080
111#define BCSR_SWITCHES_DIP_2 0x0040
112#define BCSR_SWITCHES_DIP_3 0x0020
113#define BCSR_SWITCHES_DIP_4 0x0010
114#define BCSR_SWITCHES_DIP_5 0x0008
115#define BCSR_SWITCHES_DIP_6 0x0004
116#define BCSR_SWITCHES_DIP_7 0x0002
117#define BCSR_SWITCHES_DIP_8 0x0001
118#define BCSR_SWITCHES_ROTARY 0x0F00
119
120#define BCSR_RESETS_ETH 0x0001
121#define BCSR_RESETS_CAMERA 0x0002
122#define BCSR_RESETS_DC 0x0004
123#define BCSR_RESETS_IDE 0x0008
124/* not resets but in the same register */
125#define BCSR_RESETS_WSCFSM 0x0800
126#define BCSR_RESETS_PCS0MUX 0x1000
127#define BCSR_RESETS_PCS1MUX 0x2000
128#define BCSR_RESETS_SPISEL 0x4000
129#define BCSR_RESETS_SD1MUX 0x8000
130
131#define BCSR_PCMCIA_PC0VPP 0x0003
132#define BCSR_PCMCIA_PC0VCC 0x000C
133#define BCSR_PCMCIA_PC0DRVEN 0x0010
134#define BCSR_PCMCIA_PC0RST 0x0080
135#define BCSR_PCMCIA_PC1VPP 0x0300
136#define BCSR_PCMCIA_PC1VCC 0x0C00
137#define BCSR_PCMCIA_PC1DRVEN 0x1000
138#define BCSR_PCMCIA_PC1RST 0x8000
139
140#define BCSR_BOARD_LCDVEE 0x0001
141#define BCSR_BOARD_LCDVDD 0x0002
142#define BCSR_BOARD_LCDBL 0x0004
143#define BCSR_BOARD_CAMSNAP 0x0010
144#define BCSR_BOARD_CAMPWR 0x0020
145#define BCSR_BOARD_SD0PWR 0x0040
146#define BCSR_BOARD_SD1PWR 0x0080
147
148#define BCSR_LEDS_DECIMALS 0x00FF
149#define BCSR_LEDS_LED0 0x0100
150#define BCSR_LEDS_LED1 0x0200
151#define BCSR_LEDS_LED2 0x0400
152#define BCSR_LEDS_LED3 0x0800
153
154#define BCSR_SYSTEM_VDDI 0x001F
155#define BCSR_SYSTEM_POWEROFF 0x4000
156#define BCSR_SYSTEM_RESET 0x8000
157
158/* Bit positions for the different interrupt sources */
159#define BCSR_INT_IDE 0x0001
160#define BCSR_INT_ETH 0x0002
161#define BCSR_INT_PC0 0x0004
162#define BCSR_INT_PC0STSCHG 0x0008
163#define BCSR_INT_PC1 0x0010
164#define BCSR_INT_PC1STSCHG 0x0020
165#define BCSR_INT_DC 0x0040
166#define BCSR_INT_FLASHBUSY 0x0080
167#define BCSR_INT_PC0INSERT 0x0100
168#define BCSR_INT_PC0EJECT 0x0200
169#define BCSR_INT_PC1INSERT 0x0400
170#define BCSR_INT_PC1EJECT 0x0800
171#define BCSR_INT_SD0INSERT 0x1000
172#define BCSR_INT_SD0EJECT 0x2000
173#define BCSR_INT_SD1INSERT 0x4000
174#define BCSR_INT_SD1EJECT 0x8000
175
176#define AU1XXX_SMC91111_PHYS_ADDR (0x0D000300)
177#define AU1XXX_SMC91111_IRQ PB1200_ETH_INT
178
179#define AU1XXX_ATA_PHYS_ADDR (0x0C800000)
180#define AU1XXX_ATA_PHYS_LEN (0x100)
181#define AU1XXX_ATA_REG_OFFSET (5)
182#define AU1XXX_ATA_INT PB1200_IDE_INT
183#define AU1XXX_ATA_DDMA_REQ DSCR_CMD0_DMA_REQ1;
184#define AU1XXX_ATA_RQSIZE 128
185
186#define NAND_PHYS_ADDR 0x1C000000
187
188/* Timing values as described in databook, * ns value stripped of
189 * lower 2 bits.
190 * These defines are here rather than an SOC1200 generic file because
191 * the parts chosen on another board may be different and may require
192 * different timings.
193 */
194#define NAND_T_H (18 >> 2)
195#define NAND_T_PUL (30 >> 2)
196#define NAND_T_SU (30 >> 2)
197#define NAND_T_WH (30 >> 2)
198
199/* Bitfield shift amounts */
200#define NAND_T_H_SHIFT 0
201#define NAND_T_PUL_SHIFT 4
202#define NAND_T_SU_SHIFT 8
203#define NAND_T_WH_SHIFT 12
204
205#define NAND_TIMING ((NAND_T_H & 0xF) << NAND_T_H_SHIFT) | \
206 ((NAND_T_PUL & 0xF) << NAND_T_PUL_SHIFT) | \
207 ((NAND_T_SU & 0xF) << NAND_T_SU_SHIFT) | \
208 ((NAND_T_WH & 0xF) << NAND_T_WH_SHIFT)
209
210
211/*
212 * External Interrupts for Pb1200 as of 8/6/2004.
213 * Bit positions in the CPLD registers can be calculated by taking
214 * the interrupt define and subtracting the PB1200_INT_BEGIN value.
215 * *example: IDE bis pos is = 64 - 64
216 ETH bit pos is = 65 - 64
217 */
218#define PB1200_INT_BEGIN (AU1000_LAST_INTC1_INT + 1)
219#define PB1200_IDE_INT (PB1200_INT_BEGIN + 0)
220#define PB1200_ETH_INT (PB1200_INT_BEGIN + 1)
221#define PB1200_PC0_INT (PB1200_INT_BEGIN + 2)
222#define PB1200_PC0_STSCHG_INT (PB1200_INT_BEGIN + 3)
223#define PB1200_PC1_INT (PB1200_INT_BEGIN + 4)
224#define PB1200_PC1_STSCHG_INT (PB1200_INT_BEGIN + 5)
225#define PB1200_DC_INT (PB1200_INT_BEGIN + 6)
226#define PB1200_FLASHBUSY_INT (PB1200_INT_BEGIN + 7)
227#define PB1200_PC0_INSERT_INT (PB1200_INT_BEGIN + 8)
228#define PB1200_PC0_EJECT_INT (PB1200_INT_BEGIN + 9)
229#define PB1200_PC1_INSERT_INT (PB1200_INT_BEGIN + 10)
230#define PB1200_PC1_EJECT_INT (PB1200_INT_BEGIN + 11)
231#define PB1200_SD0_INSERT_INT (PB1200_INT_BEGIN + 12)
232#define PB1200_SD0_EJECT_INT (PB1200_INT_BEGIN + 13)
233#define PB1200_SD1_INSERT_INT (PB1200_INT_BEGIN + 14)
234#define PB1200_SD1_EJECT_INT (PB1200_INT_BEGIN + 15)
235
236#define PB1200_INT_END (PB1200_INT_BEGIN + 15)
237
238/* For drivers/pcmcia/au1000_db1x00.c */
239#define BOARD_PC0_INT PB1200_PC0_INT
240#define BOARD_PC1_INT PB1200_PC1_INT
241#define BOARD_CARD_INSERTED(SOCKET) bcsr->sig_status & (1<<(8+(2*SOCKET)))
242
243#endif /* __ASM_PB1200_H */
244
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