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-rw-r--r--include/asm-arm/arch-at91rm9200/at91rm9200_sys.h100
-rw-r--r--include/asm-arm/assembler.h27
-rw-r--r--include/asm-arm/pgalloc.h5
-rw-r--r--include/asm-arm/pgtable-hwdef.h88
-rw-r--r--include/asm-arm/pgtable.h80
-rw-r--r--include/asm-arm/tlb.h9
-rw-r--r--include/asm-arm/tlbflush.h9
-rw-r--r--include/linux/clk.h4
8 files changed, 234 insertions, 88 deletions
diff --git a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
index 9bfffdbf1e0b..2910d359f919 100644
--- a/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
+++ b/include/asm-arm/arch-at91rm9200/at91rm9200_sys.h
@@ -172,6 +172,7 @@
172#define AT91_PMC_MDIV_4 (3 << 8) 172#define AT91_PMC_MDIV_4 (3 << 8)
173 173
174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */ 174#define AT91_PMC_PCKR(n) (AT91_PMC + 0x40 + ((n) * 4)) /* Programmable Clock 0-3 Registers */
175
175#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */ 176#define AT91_PMC_IER (AT91_PMC + 0x60) /* Interrupt Enable Register */
176#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */ 177#define AT91_PMC_IDR (AT91_PMC + 0x64) /* Interrupt Disable Register */
177#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */ 178#define AT91_PMC_SR (AT91_PMC + 0x68) /* Status Register */
@@ -286,8 +287,32 @@
286#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */ 287#define AT91_MC_RCB (1 << 0) /* Remap Command Bit */
287 288
288#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */ 289#define AT91_MC_ASR (AT91_MC + 0x04) /* MC Abort Status Register */
290#define AT91_MC_UNADD (1 << 0) /* Undefined Address Abort Status */
291#define AT91_MC_MISADD (1 << 1) /* Misaligned Address Abort Status */
292#define AT91_MC_ABTSZ (3 << 8) /* Abort Size Status */
293#define AT91_MC_ABTSZ_BYTE (0 << 8)
294#define AT91_MC_ABTSZ_HALFWORD (1 << 8)
295#define AT91_MC_ABTSZ_WORD (2 << 8)
296#define AT91_MC_ABTTYP (3 << 10) /* Abort Type Status */
297#define AT91_MC_ABTTYP_DATAREAD (0 << 10)
298#define AT91_MC_ABTTYP_DATAWRITE (1 << 10)
299#define AT91_MC_ABTTYP_FETCH (2 << 10)
300#define AT91_MC_MST0 (1 << 16) /* ARM920T Abort Source */
301#define AT91_MC_MST1 (1 << 17) /* PDC Abort Source */
302#define AT91_MC_MST2 (1 << 18) /* UHP Abort Source */
303#define AT91_MC_MST3 (1 << 19) /* EMAC Abort Source */
304#define AT91_MC_SVMST0 (1 << 24) /* Saved ARM920T Abort Source */
305#define AT91_MC_SVMST1 (1 << 25) /* Saved PDC Abort Source */
306#define AT91_MC_SVMST2 (1 << 26) /* Saved UHP Abort Source */
307#define AT91_MC_SVMST3 (1 << 27) /* Saved EMAC Abort Source */
308
289#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */ 309#define AT91_MC_AASR (AT91_MC + 0x08) /* MC Abort Address Status Register */
310
290#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */ 311#define AT91_MC_MPR (AT91_MC + 0x0c) /* MC Master Priority Register */
312#define AT91_MPR_MSTP0 (7 << 0) /* ARM920T Priority */
313#define AT91_MPR_MSTP1 (7 << 4) /* PDC Priority */
314#define AT91_MPR_MSTP2 (7 << 8) /* UHP Priority */
315#define AT91_MPR_MSTP3 (7 << 12) /* EMAC Priority */
291 316
292/* External Bus Interface (EBI) registers */ 317/* External Bus Interface (EBI) registers */
293#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */ 318#define AT91_EBI_CSA (AT91_MC + 0x60) /* Chip Select Assignment Register */
@@ -309,8 +334,10 @@
309/* Static Memory Controller (SMC) registers */ 334/* Static Memory Controller (SMC) registers */
310#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */ 335#define AT91_SMC_CSR(n) (AT91_MC + 0x70 + ((n) * 4))/* SMC Chip Select Register */
311#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */ 336#define AT91_SMC_NWS (0x7f << 0) /* Number of Wait States */
337#define AT91_SMC_NWS_(x) ((x) << 0)
312#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */ 338#define AT91_SMC_WSEN (1 << 7) /* Wait State Enable */
313#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */ 339#define AT91_SMC_TDF (0xf << 8) /* Data Float Time */
340#define AT91_SMC_TDF_(x) ((x) << 8)
314#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */ 341#define AT91_SMC_BAT (1 << 12) /* Byte Access Type */
315#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */ 342#define AT91_SMC_DBW (3 << 13) /* Data Bus Width */
316#define AT91_SMC_DBW_16 (1 << 13) 343#define AT91_SMC_DBW_16 (1 << 13)
@@ -322,7 +349,78 @@
322#define AT91_SMC_ACSS_2 (2 << 16) 349#define AT91_SMC_ACSS_2 (2 << 16)
323#define AT91_SMC_ACSS_3 (3 << 16) 350#define AT91_SMC_ACSS_3 (3 << 16)
324#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */ 351#define AT91_SMC_RWSETUP (7 << 24) /* Read & Write Signal Time Setup */
352#define AT91_SMC_RWSETUP_(x) ((x) << 24)
325#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */ 353#define AT91_SMC_RWHOLD (7 << 28) /* Read & Write Signal Hold Time */
326 354#define AT91_SMC_RWHOLD_(x) ((x) << 28)
355
356/* SDRAM Controller registers */
357#define AT91_SDRAMC_MR (AT91_MC + 0x90) /* Mode Register */
358#define AT91_SDRAMC_MODE (0xf << 0) /* Command Mode */
359#define AT91_SDRAMC_MODE_NORMAL (0 << 0)
360#define AT91_SDRAMC_MODE_NOP (1 << 0)
361#define AT91_SDRAMC_MODE_PRECHARGE (2 << 0)
362#define AT91_SDRAMC_MODE_LMR (3 << 0)
363#define AT91_SDRAMC_MODE_REFRESH (4 << 0)
364#define AT91_SDRAMC_DBW (1 << 4) /* Data Bus Width */
365#define AT91_SDRAMC_DBW_32 (0 << 4)
366#define AT91_SDRAMC_DBW_16 (1 << 4)
367
368#define AT91_SDRAMC_TR (AT91_MC + 0x94) /* Refresh Timer Register */
369#define AT91_SDRAMC_COUNT (0xfff << 0) /* Refresh Timer Count */
370
371#define AT91_SDRAMC_CR (AT91_MC + 0x98) /* Configuration Register */
372#define AT91_SDRAMC_NC (3 << 0) /* Number of Column Bits */
373#define AT91_SDRAMC_NC_8 (0 << 0)
374#define AT91_SDRAMC_NC_9 (1 << 0)
375#define AT91_SDRAMC_NC_10 (2 << 0)
376#define AT91_SDRAMC_NC_11 (3 << 0)
377#define AT91_SDRAMC_NR (3 << 2) /* Number of Row Bits */
378#define AT91_SDRAMC_NR_11 (0 << 2)
379#define AT91_SDRAMC_NR_12 (1 << 2)
380#define AT91_SDRAMC_NR_13 (2 << 2)
381#define AT91_SDRAMC_NB (1 << 4) /* Number of Banks */
382#define AT91_SDRAMC_NB_2 (0 << 4)
383#define AT91_SDRAMC_NB_4 (1 << 4)
384#define AT91_SDRAMC_CAS (3 << 5) /* CAS Latency */
385#define AT91_SDRAMC_CAS_2 (2 << 5)
386#define AT91_SDRAMC_TWR (0xf << 7) /* Write Recovery Delay */
387#define AT91_SDRAMC_TRC (0xf << 11) /* Row Cycle Delay */
388#define AT91_SDRAMC_TRP (0xf << 15) /* Row Precharge Delay */
389#define AT91_SDRAMC_TRCD (0xf << 19) /* Row to Column Delay */
390#define AT91_SDRAMC_TRAS (0xf << 23) /* Active to Precharge Delay */
391#define AT91_SDRAMC_TXSR (0xf << 27) /* Exit Self Refresh to Active Delay */
392
393#define AT91_SDRAMC_SRR (AT91_MC + 0x9c) /* Self Refresh Register */
394#define AT91_SDRAMC_LPR (AT91_MC + 0xa0) /* Low Power Register */
395#define AT91_SDRAMC_IER (AT91_MC + 0xa4) /* Interrupt Enable Register */
396#define AT91_SDRAMC_IDR (AT91_MC + 0xa8) /* Interrupt Disable Register */
397#define AT91_SDRAMC_IMR (AT91_MC + 0xac) /* Interrupt Mask Register */
398#define AT91_SDRAMC_ISR (AT91_MC + 0xb0) /* Interrupt Status Register */
399
400/* Burst Flash Controller register */
401#define AT91_BFC_MR (AT91_MC + 0xc0) /* Mode Register */
402#define AT91_BFC_BFCOM (3 << 0) /* Burst Flash Controller Operating Mode */
403#define AT91_BFC_BFCOM_DISABLED (0 << 0)
404#define AT91_BFC_BFCOM_ASYNC (1 << 0)
405#define AT91_BFC_BFCOM_BURST (2 << 0)
406#define AT91_BFC_BFCC (3 << 2) /* Burst Flash Controller Clock */
407#define AT91_BFC_BFCC_MCK (1 << 2)
408#define AT91_BFC_BFCC_DIV2 (2 << 2)
409#define AT91_BFC_BFCC_DIV4 (3 << 2)
410#define AT91_BFC_AVL (0xf << 4) /* Address Valid Latency */
411#define AT91_BFC_PAGES (7 << 8) /* Page Size */
412#define AT91_BFC_PAGES_NO_PAGE (0 << 8)
413#define AT91_BFC_PAGES_16 (1 << 8)
414#define AT91_BFC_PAGES_32 (2 << 8)
415#define AT91_BFC_PAGES_64 (3 << 8)
416#define AT91_BFC_PAGES_128 (4 << 8)
417#define AT91_BFC_PAGES_256 (5 << 8)
418#define AT91_BFC_PAGES_512 (6 << 8)
419#define AT91_BFC_PAGES_1024 (7 << 8)
420#define AT91_BFC_OEL (3 << 12) /* Output Enable Latency */
421#define AT91_BFC_BAAEN (1 << 16) /* Burst Address Advance Enable */
422#define AT91_BFC_BFOEH (1 << 17) /* Burst Flash Output Enable Handling */
423#define AT91_BFC_MUXEN (1 << 18) /* Multiplexed Bus Enable */
424#define AT91_BFC_RDYEN (1 << 19) /* Ready Enable Mode */
327 425
328#endif 426#endif
diff --git a/include/asm-arm/assembler.h b/include/asm-arm/assembler.h
index f31ac92b6c7f..d53bafa9bf1c 100644
--- a/include/asm-arm/assembler.h
+++ b/include/asm-arm/assembler.h
@@ -80,16 +80,33 @@
80 instr regs 80 instr regs
81 81
82/* 82/*
83 * Save the current IRQ state and disable IRQs. Note that this macro 83 * Enable and disable interrupts
84 * assumes FIQs are enabled, and that the processor is in SVC mode.
85 */ 84 */
86 .macro save_and_disable_irqs, oldcpsr
87 mrs \oldcpsr, cpsr
88#if __LINUX_ARM_ARCH__ >= 6 85#if __LINUX_ARM_ARCH__ >= 6
86 .macro disable_irq
89 cpsid i 87 cpsid i
88 .endm
89
90 .macro enable_irq
91 cpsie i
92 .endm
90#else 93#else
91 msr cpsr_c, #PSR_I_BIT | MODE_SVC 94 .macro disable_irq
95 msr cpsr_c, #PSR_I_BIT | SVC_MODE
96 .endm
97
98 .macro enable_irq
99 msr cpsr_c, #SVC_MODE
100 .endm
92#endif 101#endif
102
103/*
104 * Save the current IRQ state and disable IRQs. Note that this macro
105 * assumes FIQs are enabled, and that the processor is in SVC mode.
106 */
107 .macro save_and_disable_irqs, oldcpsr
108 mrs \oldcpsr, cpsr
109 disable_irq
93 .endm 110 .endm
94 111
95/* 112/*
diff --git a/include/asm-arm/pgalloc.h b/include/asm-arm/pgalloc.h
index bc18ff405181..c4ac2e67768d 100644
--- a/include/asm-arm/pgalloc.h
+++ b/include/asm-arm/pgalloc.h
@@ -10,10 +10,15 @@
10#ifndef _ASMARM_PGALLOC_H 10#ifndef _ASMARM_PGALLOC_H
11#define _ASMARM_PGALLOC_H 11#define _ASMARM_PGALLOC_H
12 12
13#include <asm/domain.h>
14#include <asm/pgtable-hwdef.h>
13#include <asm/processor.h> 15#include <asm/processor.h>
14#include <asm/cacheflush.h> 16#include <asm/cacheflush.h>
15#include <asm/tlbflush.h> 17#include <asm/tlbflush.h>
16 18
19#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
20#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
21
17/* 22/*
18 * Since we have only two-level page tables, these are trivial 23 * Since we have only two-level page tables, these are trivial
19 */ 24 */
diff --git a/include/asm-arm/pgtable-hwdef.h b/include/asm-arm/pgtable-hwdef.h
new file mode 100644
index 000000000000..1d033495cc75
--- /dev/null
+++ b/include/asm-arm/pgtable-hwdef.h
@@ -0,0 +1,88 @@
1/*
2 * linux/include/asm-arm/pgtable-hwdef.h
3 *
4 * Copyright (C) 1995-2002 Russell King
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef _ASMARM_PGTABLE_HWDEF_H
11#define _ASMARM_PGTABLE_HWDEF_H
12
13/*
14 * Hardware page table definitions.
15 *
16 * + Level 1 descriptor (PMD)
17 * - common
18 */
19#define PMD_TYPE_MASK (3 << 0)
20#define PMD_TYPE_FAULT (0 << 0)
21#define PMD_TYPE_TABLE (1 << 0)
22#define PMD_TYPE_SECT (2 << 0)
23#define PMD_BIT4 (1 << 4)
24#define PMD_DOMAIN(x) ((x) << 5)
25#define PMD_PROTECTION (1 << 9) /* v5 */
26/*
27 * - section
28 */
29#define PMD_SECT_BUFFERABLE (1 << 2)
30#define PMD_SECT_CACHEABLE (1 << 3)
31#define PMD_SECT_AP_WRITE (1 << 10)
32#define PMD_SECT_AP_READ (1 << 11)
33#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
34#define PMD_SECT_APX (1 << 15) /* v6 */
35#define PMD_SECT_S (1 << 16) /* v6 */
36#define PMD_SECT_nG (1 << 17) /* v6 */
37#define PMD_SECT_SUPER (1 << 18) /* v6 */
38
39#define PMD_SECT_UNCACHED (0)
40#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
41#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
42#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
43#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
44#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
45#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
46
47/*
48 * - coarse table (not used)
49 */
50
51/*
52 * + Level 2 descriptor (PTE)
53 * - common
54 */
55#define PTE_TYPE_MASK (3 << 0)
56#define PTE_TYPE_FAULT (0 << 0)
57#define PTE_TYPE_LARGE (1 << 0)
58#define PTE_TYPE_SMALL (2 << 0)
59#define PTE_TYPE_EXT (3 << 0) /* v5 */
60#define PTE_BUFFERABLE (1 << 2)
61#define PTE_CACHEABLE (1 << 3)
62
63/*
64 * - extended small page/tiny page
65 */
66#define PTE_EXT_XN (1 << 0) /* v6 */
67#define PTE_EXT_AP_MASK (3 << 4)
68#define PTE_EXT_AP0 (1 << 4)
69#define PTE_EXT_AP1 (2 << 4)
70#define PTE_EXT_AP_UNO_SRO (0 << 4)
71#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
72#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
73#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
74#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
75#define PTE_EXT_APX (1 << 9) /* v6 */
76#define PTE_EXT_SHARED (1 << 10) /* v6 */
77#define PTE_EXT_NG (1 << 11) /* v6 */
78
79/*
80 * - small page
81 */
82#define PTE_SMALL_AP_MASK (0xff << 4)
83#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
84#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
85#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
86#define PTE_SMALL_AP_URW_SRW (0xff << 4)
87
88#endif
diff --git a/include/asm-arm/pgtable.h b/include/asm-arm/pgtable.h
index 70e00d08345e..e595ae24efe2 100644
--- a/include/asm-arm/pgtable.h
+++ b/include/asm-arm/pgtable.h
@@ -137,81 +137,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
137#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1)) 137#define SUPERSECTION_MASK (~(SUPERSECTION_SIZE-1))
138 138
139/* 139/*
140 * Hardware page table definitions.
141 *
142 * + Level 1 descriptor (PMD)
143 * - common
144 */
145#define PMD_TYPE_MASK (3 << 0)
146#define PMD_TYPE_FAULT (0 << 0)
147#define PMD_TYPE_TABLE (1 << 0)
148#define PMD_TYPE_SECT (2 << 0)
149#define PMD_BIT4 (1 << 4)
150#define PMD_DOMAIN(x) ((x) << 5)
151#define PMD_PROTECTION (1 << 9) /* v5 */
152/*
153 * - section
154 */
155#define PMD_SECT_BUFFERABLE (1 << 2)
156#define PMD_SECT_CACHEABLE (1 << 3)
157#define PMD_SECT_AP_WRITE (1 << 10)
158#define PMD_SECT_AP_READ (1 << 11)
159#define PMD_SECT_TEX(x) ((x) << 12) /* v5 */
160#define PMD_SECT_APX (1 << 15) /* v6 */
161#define PMD_SECT_S (1 << 16) /* v6 */
162#define PMD_SECT_nG (1 << 17) /* v6 */
163#define PMD_SECT_SUPER (1 << 18) /* v6 */
164
165#define PMD_SECT_UNCACHED (0)
166#define PMD_SECT_BUFFERED (PMD_SECT_BUFFERABLE)
167#define PMD_SECT_WT (PMD_SECT_CACHEABLE)
168#define PMD_SECT_WB (PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
169#define PMD_SECT_MINICACHE (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE)
170#define PMD_SECT_WBWA (PMD_SECT_TEX(1) | PMD_SECT_CACHEABLE | PMD_SECT_BUFFERABLE)
171#define PMD_SECT_NONSHARED_DEV (PMD_SECT_TEX(2))
172
173/*
174 * - coarse table (not used)
175 */
176
177/*
178 * + Level 2 descriptor (PTE)
179 * - common
180 */
181#define PTE_TYPE_MASK (3 << 0)
182#define PTE_TYPE_FAULT (0 << 0)
183#define PTE_TYPE_LARGE (1 << 0)
184#define PTE_TYPE_SMALL (2 << 0)
185#define PTE_TYPE_EXT (3 << 0) /* v5 */
186#define PTE_BUFFERABLE (1 << 2)
187#define PTE_CACHEABLE (1 << 3)
188
189/*
190 * - extended small page/tiny page
191 */
192#define PTE_EXT_XN (1 << 0) /* v6 */
193#define PTE_EXT_AP_MASK (3 << 4)
194#define PTE_EXT_AP0 (1 << 4)
195#define PTE_EXT_AP1 (2 << 4)
196#define PTE_EXT_AP_UNO_SRO (0 << 4)
197#define PTE_EXT_AP_UNO_SRW (PTE_EXT_AP0)
198#define PTE_EXT_AP_URO_SRW (PTE_EXT_AP1)
199#define PTE_EXT_AP_URW_SRW (PTE_EXT_AP1|PTE_EXT_AP0)
200#define PTE_EXT_TEX(x) ((x) << 6) /* v5 */
201#define PTE_EXT_APX (1 << 9) /* v6 */
202#define PTE_EXT_SHARED (1 << 10) /* v6 */
203#define PTE_EXT_NG (1 << 11) /* v6 */
204
205/*
206 * - small page
207 */
208#define PTE_SMALL_AP_MASK (0xff << 4)
209#define PTE_SMALL_AP_UNO_SRO (0x00 << 4)
210#define PTE_SMALL_AP_UNO_SRW (0x55 << 4)
211#define PTE_SMALL_AP_URO_SRW (0xaa << 4)
212#define PTE_SMALL_AP_URW_SRW (0xff << 4)
213
214/*
215 * "Linux" PTE definitions. 140 * "Linux" PTE definitions.
216 * 141 *
217 * We keep two sets of PTEs - the hardware and the linux version. 142 * We keep two sets of PTEs - the hardware and the linux version.
@@ -236,11 +161,6 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
236 161
237#ifndef __ASSEMBLY__ 162#ifndef __ASSEMBLY__
238 163
239#include <asm/domain.h>
240
241#define _PAGE_USER_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_USER))
242#define _PAGE_KERNEL_TABLE (PMD_TYPE_TABLE | PMD_BIT4 | PMD_DOMAIN(DOMAIN_KERNEL))
243
244/* 164/*
245 * The following macros handle the cache and bufferable bits... 165 * The following macros handle the cache and bufferable bits...
246 */ 166 */
diff --git a/include/asm-arm/tlb.h b/include/asm-arm/tlb.h
index f49bfb78c221..cb740025d413 100644
--- a/include/asm-arm/tlb.h
+++ b/include/asm-arm/tlb.h
@@ -19,6 +19,14 @@
19 19
20#include <asm/cacheflush.h> 20#include <asm/cacheflush.h>
21#include <asm/tlbflush.h> 21#include <asm/tlbflush.h>
22
23#ifndef CONFIG_MMU
24
25#include <linux/pagemap.h>
26#include <asm-generic/tlb.h>
27
28#else /* !CONFIG_MMU */
29
22#include <asm/pgalloc.h> 30#include <asm/pgalloc.h>
23 31
24/* 32/*
@@ -82,4 +90,5 @@ tlb_end_vma(struct mmu_gather *tlb, struct vm_area_struct *vma)
82 90
83#define tlb_migrate_finish(mm) do { } while (0) 91#define tlb_migrate_finish(mm) do { } while (0)
84 92
93#endif /* CONFIG_MMU */
85#endif 94#endif
diff --git a/include/asm-arm/tlbflush.h b/include/asm-arm/tlbflush.h
index 0c2acc944a0a..728992451dd1 100644
--- a/include/asm-arm/tlbflush.h
+++ b/include/asm-arm/tlbflush.h
@@ -11,6 +11,13 @@
11#define _ASMARM_TLBFLUSH_H 11#define _ASMARM_TLBFLUSH_H
12 12
13#include <linux/config.h> 13#include <linux/config.h>
14
15#ifndef CONFIG_MMU
16
17#define tlb_flush(tlb) ((void) tlb)
18
19#else /* CONFIG_MMU */
20
14#include <asm/glue.h> 21#include <asm/glue.h>
15 22
16#define TLB_V3_PAGE (1 << 0) 23#define TLB_V3_PAGE (1 << 0)
@@ -423,4 +430,6 @@ extern void update_mmu_cache(struct vm_area_struct *vma, unsigned long addr, pte
423 430
424#endif 431#endif
425 432
433#endif /* CONFIG_MMU */
434
426#endif 435#endif
diff --git a/include/linux/clk.h b/include/linux/clk.h
index 12848f81bb37..5ca8c6fddb56 100644
--- a/include/linux/clk.h
+++ b/include/linux/clk.h
@@ -8,8 +8,8 @@
8 * it under the terms of the GNU General Public License version 2 as 8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation. 9 * published by the Free Software Foundation.
10 */ 10 */
11#ifndef ASMARM_CLOCK_H 11#ifndef __LINUX_CLK_H
12#define ASMARM_CLOCK_H 12#define __LINUX_CLK_H
13 13
14struct device; 14struct device;
15 15
generated by cgit v1.2.2 (git 2.25.0) at 2024-12-26 18:48:45 -0500