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-rw-r--r--include/linux/input/tps6507x-ts.h24
-rw-r--r--include/linux/mfd/88pm860x.h4
-rw-r--r--include/linux/mfd/ab4500.h262
-rw-r--r--include/linux/mfd/ab8500.h128
-rw-r--r--include/linux/mfd/abx500.h (renamed from include/linux/mfd/ab3100.h)134
-rw-r--r--include/linux/mfd/janz.h54
-rw-r--r--include/linux/mfd/rdc321x.h26
-rw-r--r--include/linux/mfd/tc35892.h132
-rw-r--r--include/linux/mfd/tps6507x.h169
-rw-r--r--include/linux/mfd/wm831x/core.h5
10 files changed, 657 insertions, 281 deletions
diff --git a/include/linux/input/tps6507x-ts.h b/include/linux/input/tps6507x-ts.h
new file mode 100644
index 000000000000..ab1440313924
--- /dev/null
+++ b/include/linux/input/tps6507x-ts.h
@@ -0,0 +1,24 @@
1/* linux/i2c/tps6507x-ts.h
2 *
3 * Functions to access TPS65070 touch screen chip.
4 *
5 * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
6 *
7 *
8 * For licencing details see kernel-base/COPYING
9 */
10
11#ifndef __LINUX_I2C_TPS6507X_TS_H
12#define __LINUX_I2C_TPS6507X_TS_H
13
14/* Board specific touch screen initial values */
15struct touchscreen_init_data {
16 int poll_period; /* ms */
17 int vref; /* non-zero to leave vref on */
18 __u16 min_pressure; /* min reading to be treated as a touch */
19 __u16 vendor;
20 __u16 product;
21 __u16 version;
22};
23
24#endif /* __LINUX_I2C_TPS6507X_TS_H */
diff --git a/include/linux/mfd/88pm860x.h b/include/linux/mfd/88pm860x.h
index e3c4ff8c3e38..bfd23bef7363 100644
--- a/include/linux/mfd/88pm860x.h
+++ b/include/linux/mfd/88pm860x.h
@@ -370,7 +370,7 @@ extern int pm860x_set_bits(struct i2c_client *, int, unsigned char,
370 unsigned char); 370 unsigned char);
371 371
372extern int pm860x_device_init(struct pm860x_chip *chip, 372extern int pm860x_device_init(struct pm860x_chip *chip,
373 struct pm860x_platform_data *pdata); 373 struct pm860x_platform_data *pdata) __devinit ;
374extern void pm860x_device_exit(struct pm860x_chip *chip); 374extern void pm860x_device_exit(struct pm860x_chip *chip) __devexit ;
375 375
376#endif /* __LINUX_MFD_88PM860X_H */ 376#endif /* __LINUX_MFD_88PM860X_H */
diff --git a/include/linux/mfd/ab4500.h b/include/linux/mfd/ab4500.h
deleted file mode 100644
index a42a7033ae53..000000000000
--- a/include/linux/mfd/ab4500.h
+++ /dev/null
@@ -1,262 +0,0 @@
1/*
2 * Copyright (C) 2009 ST-Ericsson
3 *
4 * Author: Srinidhi KASAGAR <srinidhi.kasagar@stericsson.com>
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2, as
8 * published by the Free Software Foundation.
9 *
10 * AB4500 device core funtions, for client access
11 */
12#ifndef MFD_AB4500_H
13#define MFD_AB4500_H
14
15#include <linux/device.h>
16
17/*
18 * AB4500 bank addresses
19 */
20#define AB4500_SYS_CTRL1_BLOCK 0x1
21#define AB4500_SYS_CTRL2_BLOCK 0x2
22#define AB4500_REGU_CTRL1 0x3
23#define AB4500_REGU_CTRL2 0x4
24#define AB4500_USB 0x5
25#define AB4500_TVOUT 0x6
26#define AB4500_DBI 0x7
27#define AB4500_ECI_AV_ACC 0x8
28#define AB4500_RESERVED 0x9
29#define AB4500_GPADC 0xA
30#define AB4500_CHARGER 0xB
31#define AB4500_GAS_GAUGE 0xC
32#define AB4500_AUDIO 0xD
33#define AB4500_INTERRUPT 0xE
34#define AB4500_RTC 0xF
35#define AB4500_MISC 0x10
36#define AB4500_DEBUG 0x12
37#define AB4500_PROD_TEST 0x13
38#define AB4500_OTP_EMUL 0x15
39
40/*
41 * System control 1 register offsets.
42 * Bank = 0x01
43 */
44#define AB4500_TURNON_STAT_REG 0x0100
45#define AB4500_RESET_STAT_REG 0x0101
46#define AB4500_PONKEY1_PRESS_STAT_REG 0x0102
47
48#define AB4500_FSM_STAT1_REG 0x0140
49#define AB4500_FSM_STAT2_REG 0x0141
50#define AB4500_SYSCLK_REQ_STAT_REG 0x0142
51#define AB4500_USB_STAT1_REG 0x0143
52#define AB4500_USB_STAT2_REG 0x0144
53#define AB4500_STATUS_SPARE1_REG 0x0145
54#define AB4500_STATUS_SPARE2_REG 0x0146
55
56#define AB4500_CTRL1_REG 0x0180
57#define AB4500_CTRL2_REG 0x0181
58
59/*
60 * System control 2 register offsets.
61 * bank = 0x02
62 */
63#define AB4500_CTRL3_REG 0x0200
64#define AB4500_MAIN_WDOG_CTRL_REG 0x0201
65#define AB4500_MAIN_WDOG_TIMER_REG 0x0202
66#define AB4500_LOW_BAT_REG 0x0203
67#define AB4500_BATT_OK_REG 0x0204
68#define AB4500_SYSCLK_TIMER_REG 0x0205
69#define AB4500_SMPSCLK_CTRL_REG 0x0206
70#define AB4500_SMPSCLK_SEL1_REG 0x0207
71#define AB4500_SMPSCLK_SEL2_REG 0x0208
72#define AB4500_SMPSCLK_SEL3_REG 0x0209
73#define AB4500_SYSULPCLK_CONF_REG 0x020A
74#define AB4500_SYSULPCLK_CTRL1_REG 0x020B
75#define AB4500_SYSCLK_CTRL_REG 0x020C
76#define AB4500_SYSCLK_REQ1_VALID_REG 0x020D
77#define AB4500_SYSCLK_REQ_VALID_REG 0x020E
78#define AB4500_SYSCTRL_SPARE_REG 0x020F
79#define AB4500_PAD_CONF_REG 0x0210
80
81/*
82 * Regu control1 register offsets
83 * Bank = 0x03
84 */
85#define AB4500_REGU_SERIAL_CTRL1_REG 0x0300
86#define AB4500_REGU_SERIAL_CTRL2_REG 0x0301
87#define AB4500_REGU_SERIAL_CTRL3_REG 0x0302
88#define AB4500_REGU_REQ_CTRL1_REG 0x0303
89#define AB4500_REGU_REQ_CTRL2_REG 0x0304
90#define AB4500_REGU_REQ_CTRL3_REG 0x0305
91#define AB4500_REGU_REQ_CTRL4_REG 0x0306
92#define AB4500_REGU_MISC1_REG 0x0380
93#define AB4500_REGU_OTGSUPPLY_CTRL_REG 0x0381
94#define AB4500_REGU_VUSB_CTRL_REG 0x0382
95#define AB4500_REGU_VAUDIO_SUPPLY_REG 0x0383
96#define AB4500_REGU_CTRL1_SPARE_REG 0x0384
97
98/*
99 * Regu control2 Vmod register offsets
100 */
101#define AB4500_REGU_VMOD_REGU_REG 0x0440
102#define AB4500_REGU_VMOD_SEL1_REG 0x0441
103#define AB4500_REGU_VMOD_SEL2_REG 0x0442
104#define AB4500_REGU_CTRL_DISCH_REG 0x0443
105#define AB4500_REGU_CTRL_DISCH2_REG 0x0444
106
107/*
108 * USB/ULPI register offsets
109 * Bank : 0x5
110 */
111#define AB4500_USB_LINE_STAT_REG 0x0580
112#define AB4500_USB_LINE_CTRL1_REG 0x0581
113#define AB4500_USB_LINE_CTRL2_REG 0x0582
114#define AB4500_USB_LINE_CTRL3_REG 0x0583
115#define AB4500_USB_LINE_CTRL4_REG 0x0584
116#define AB4500_USB_LINE_CTRL5_REG 0x0585
117#define AB4500_USB_OTG_CTRL_REG 0x0587
118#define AB4500_USB_OTG_STAT_REG 0x0588
119#define AB4500_USB_OTG_STAT_REG 0x0588
120#define AB4500_USB_CTRL_SPARE_REG 0x0589
121#define AB4500_USB_PHY_CTRL_REG 0x058A
122
123/*
124 * TVOUT / CTRL register offsets
125 * Bank : 0x06
126 */
127#define AB4500_TVOUT_CTRL_REG 0x0680
128
129/*
130 * DBI register offsets
131 * Bank : 0x07
132 */
133#define AB4500_DBI_REG1_REG 0x0700
134#define AB4500_DBI_REG2_REG 0x0701
135
136/*
137 * ECI regsiter offsets
138 * Bank : 0x08
139 */
140#define AB4500_ECI_CTRL_REG 0x0800
141#define AB4500_ECI_HOOKLEVEL_REG 0x0801
142#define AB4500_ECI_DATAOUT_REG 0x0802
143#define AB4500_ECI_DATAIN_REG 0x0803
144
145/*
146 * AV Connector register offsets
147 * Bank : 0x08
148 */
149#define AB4500_AV_CONN_REG 0x0840
150
151/*
152 * Accessory detection register offsets
153 * Bank : 0x08
154 */
155#define AB4500_ACC_DET_DB1_REG 0x0880
156#define AB4500_ACC_DET_DB2_REG 0x0881
157
158/*
159 * GPADC register offsets
160 * Bank : 0x0A
161 */
162#define AB4500_GPADC_CTRL1_REG 0x0A00
163#define AB4500_GPADC_CTRL2_REG 0x0A01
164#define AB4500_GPADC_CTRL3_REG 0x0A02
165#define AB4500_GPADC_AUTO_TIMER_REG 0x0A03
166#define AB4500_GPADC_STAT_REG 0x0A04
167#define AB4500_GPADC_MANDATAL_REG 0x0A05
168#define AB4500_GPADC_MANDATAH_REG 0x0A06
169#define AB4500_GPADC_AUTODATAL_REG 0x0A07
170#define AB4500_GPADC_AUTODATAH_REG 0x0A08
171#define AB4500_GPADC_MUX_CTRL_REG 0x0A09
172
173/*
174 * Charger / status register offfsets
175 * Bank : 0x0B
176 */
177#define AB4500_CH_STATUS1_REG 0x0B00
178#define AB4500_CH_STATUS2_REG 0x0B01
179#define AB4500_CH_USBCH_STAT1_REG 0x0B02
180#define AB4500_CH_USBCH_STAT2_REG 0x0B03
181#define AB4500_CH_FSM_STAT_REG 0x0B04
182#define AB4500_CH_STAT_REG 0x0B05
183
184/*
185 * Charger / control register offfsets
186 * Bank : 0x0B
187 */
188#define AB4500_CH_VOLT_LVL_REG 0x0B40
189
190/*
191 * Charger / main control register offfsets
192 * Bank : 0x0B
193 */
194#define AB4500_MCH_CTRL1 0x0B80
195#define AB4500_MCH_CTRL2 0x0B81
196#define AB4500_MCH_IPT_CURLVL_REG 0x0B82
197#define AB4500_CH_WD_REG 0x0B83
198
199/*
200 * Charger / USB control register offsets
201 * Bank : 0x0B
202 */
203#define AB4500_USBCH_CTRL1_REG 0x0BC0
204#define AB4500_USBCH_CTRL2_REG 0x0BC1
205#define AB4500_USBCH_IPT_CRNTLVL_REG 0x0BC2
206
207/*
208 * RTC bank register offsets
209 * Bank : 0xF
210 */
211#define AB4500_RTC_SOFF_STAT_REG 0x0F00
212#define AB4500_RTC_CC_CONF_REG 0x0F01
213#define AB4500_RTC_READ_REQ_REG 0x0F02
214#define AB4500_RTC_WATCH_TSECMID_REG 0x0F03
215#define AB4500_RTC_WATCH_TSECHI_REG 0x0F04
216#define AB4500_RTC_WATCH_TMIN_LOW_REG 0x0F05
217#define AB4500_RTC_WATCH_TMIN_MID_REG 0x0F06
218#define AB4500_RTC_WATCH_TMIN_HI_REG 0x0F07
219#define AB4500_RTC_ALRM_MIN_LOW_REG 0x0F08
220#define AB4500_RTC_ALRM_MIN_MID_REG 0x0F09
221#define AB4500_RTC_ALRM_MIN_HI_REG 0x0F0A
222#define AB4500_RTC_STAT_REG 0x0F0B
223#define AB4500_RTC_BKUP_CHG_REG 0x0F0C
224#define AB4500_RTC_FORCE_BKUP_REG 0x0F0D
225#define AB4500_RTC_CALIB_REG 0x0F0E
226#define AB4500_RTC_SWITCH_STAT_REG 0x0F0F
227
228/*
229 * PWM Out generators
230 * Bank: 0x10
231 */
232#define AB4500_PWM_OUT_CTRL1_REG 0x1060
233#define AB4500_PWM_OUT_CTRL2_REG 0x1061
234#define AB4500_PWM_OUT_CTRL3_REG 0x1062
235#define AB4500_PWM_OUT_CTRL4_REG 0x1063
236#define AB4500_PWM_OUT_CTRL5_REG 0x1064
237#define AB4500_PWM_OUT_CTRL6_REG 0x1065
238#define AB4500_PWM_OUT_CTRL7_REG 0x1066
239
240#define AB4500_I2C_PAD_CTRL_REG 0x1067
241#define AB4500_REV_REG 0x1080
242
243/**
244 * struct ab4500
245 * @spi: spi device structure
246 * @tx_buf: transmit buffer
247 * @rx_buf: receive buffer
248 * @lock: sync primitive
249 */
250struct ab4500 {
251 struct spi_device *spi;
252 unsigned long tx_buf[4];
253 unsigned long rx_buf[4];
254 struct mutex lock;
255};
256
257int ab4500_write(struct ab4500 *ab4500, unsigned char block,
258 unsigned long addr, unsigned char data);
259int ab4500_read(struct ab4500 *ab4500, unsigned char block,
260 unsigned long addr);
261
262#endif /* MFD_AB4500_H */
diff --git a/include/linux/mfd/ab8500.h b/include/linux/mfd/ab8500.h
new file mode 100644
index 000000000000..b63ff3ba3351
--- /dev/null
+++ b/include/linux/mfd/ab8500.h
@@ -0,0 +1,128 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License v2
5 * Author: Srinidhi Kasagar <srinidhi.kasagar@stericsson.com>
6 */
7#ifndef MFD_AB8500_H
8#define MFD_AB8500_H
9
10#include <linux/device.h>
11
12/*
13 * Interrupts
14 */
15
16#define AB8500_INT_MAIN_EXT_CH_NOT_OK 0
17#define AB8500_INT_UN_PLUG_TV_DET 1
18#define AB8500_INT_PLUG_TV_DET 2
19#define AB8500_INT_TEMP_WARM 3
20#define AB8500_INT_PON_KEY2DB_F 4
21#define AB8500_INT_PON_KEY2DB_R 5
22#define AB8500_INT_PON_KEY1DB_F 6
23#define AB8500_INT_PON_KEY1DB_R 7
24#define AB8500_INT_BATT_OVV 8
25#define AB8500_INT_MAIN_CH_UNPLUG_DET 10
26#define AB8500_INT_MAIN_CH_PLUG_DET 11
27#define AB8500_INT_USB_ID_DET_F 12
28#define AB8500_INT_USB_ID_DET_R 13
29#define AB8500_INT_VBUS_DET_F 14
30#define AB8500_INT_VBUS_DET_R 15
31#define AB8500_INT_VBUS_CH_DROP_END 16
32#define AB8500_INT_RTC_60S 17
33#define AB8500_INT_RTC_ALARM 18
34#define AB8500_INT_BAT_CTRL_INDB 20
35#define AB8500_INT_CH_WD_EXP 21
36#define AB8500_INT_VBUS_OVV 22
37#define AB8500_INT_MAIN_CH_DROP_END 23
38#define AB8500_INT_CCN_CONV_ACC 24
39#define AB8500_INT_INT_AUD 25
40#define AB8500_INT_CCEOC 26
41#define AB8500_INT_CC_INT_CALIB 27
42#define AB8500_INT_LOW_BAT_F 28
43#define AB8500_INT_LOW_BAT_R 29
44#define AB8500_INT_BUP_CHG_NOT_OK 30
45#define AB8500_INT_BUP_CHG_OK 31
46#define AB8500_INT_GP_HW_ADC_CONV_END 32
47#define AB8500_INT_ACC_DETECT_1DB_F 33
48#define AB8500_INT_ACC_DETECT_1DB_R 34
49#define AB8500_INT_ACC_DETECT_22DB_F 35
50#define AB8500_INT_ACC_DETECT_22DB_R 36
51#define AB8500_INT_ACC_DETECT_21DB_F 37
52#define AB8500_INT_ACC_DETECT_21DB_R 38
53#define AB8500_INT_GP_SW_ADC_CONV_END 39
54#define AB8500_INT_BTEMP_LOW 72
55#define AB8500_INT_BTEMP_LOW_MEDIUM 73
56#define AB8500_INT_BTEMP_MEDIUM_HIGH 74
57#define AB8500_INT_BTEMP_HIGH 75
58#define AB8500_INT_USB_CHARGER_NOT_OK 81
59#define AB8500_INT_ID_WAKEUP_R 82
60#define AB8500_INT_ID_DET_R1R 84
61#define AB8500_INT_ID_DET_R2R 85
62#define AB8500_INT_ID_DET_R3R 86
63#define AB8500_INT_ID_DET_R4R 87
64#define AB8500_INT_ID_WAKEUP_F 88
65#define AB8500_INT_ID_DET_R1F 90
66#define AB8500_INT_ID_DET_R2F 91
67#define AB8500_INT_ID_DET_R3F 92
68#define AB8500_INT_ID_DET_R4F 93
69#define AB8500_INT_USB_CHG_DET_DONE 94
70#define AB8500_INT_USB_CH_TH_PROT_F 96
71#define AB8500_INT_USB_CH_TH_PROP_R 97
72#define AB8500_INT_MAIN_CH_TH_PROP_F 98
73#define AB8500_INT_MAIN_CH_TH_PROT_R 99
74#define AB8500_INT_USB_CHARGER_NOT_OKF 103
75
76#define AB8500_NR_IRQS 104
77#define AB8500_NUM_IRQ_REGS 13
78
79/**
80 * struct ab8500 - ab8500 internal structure
81 * @dev: parent device
82 * @lock: read/write operations lock
83 * @irq_lock: genirq bus lock
84 * @revision: chip revision
85 * @irq: irq line
86 * @write: register write
87 * @read: register read
88 * @rx_buf: rx buf for SPI
89 * @tx_buf: tx buf for SPI
90 * @mask: cache of IRQ regs for bus lock
91 * @oldmask: cache of previous IRQ regs for bus lock
92 */
93struct ab8500 {
94 struct device *dev;
95 struct mutex lock;
96 struct mutex irq_lock;
97 int revision;
98 int irq_base;
99 int irq;
100
101 int (*write) (struct ab8500 *a8500, u16 addr, u8 data);
102 int (*read) (struct ab8500 *a8500, u16 addr);
103
104 unsigned long tx_buf[4];
105 unsigned long rx_buf[4];
106
107 u8 mask[AB8500_NUM_IRQ_REGS];
108 u8 oldmask[AB8500_NUM_IRQ_REGS];
109};
110
111/**
112 * struct ab8500_platform_data - AB8500 platform data
113 * @irq_base: start of AB8500 IRQs, AB8500_NR_IRQS will be used
114 * @init: board-specific initialization after detection of ab8500
115 */
116struct ab8500_platform_data {
117 int irq_base;
118 void (*init) (struct ab8500 *);
119};
120
121extern int ab8500_write(struct ab8500 *a8500, u16 addr, u8 data);
122extern int ab8500_read(struct ab8500 *a8500, u16 addr);
123extern int ab8500_set_bits(struct ab8500 *a8500, u16 addr, u8 mask, u8 data);
124
125extern int __devinit ab8500_init(struct ab8500 *ab8500);
126extern int __devexit ab8500_exit(struct ab8500 *ab8500);
127
128#endif /* MFD_AB8500_H */
diff --git a/include/linux/mfd/ab3100.h b/include/linux/mfd/abx500.h
index 9a881c305a50..390726fcbcb1 100644
--- a/include/linux/mfd/ab3100.h
+++ b/include/linux/mfd/abx500.h
@@ -3,17 +3,37 @@
3 * License terms: GNU General Public License (GPL) version 2 3 * License terms: GNU General Public License (GPL) version 2
4 * AB3100 core access functions 4 * AB3100 core access functions
5 * Author: Linus Walleij <linus.walleij@stericsson.com> 5 * Author: Linus Walleij <linus.walleij@stericsson.com>
6 *
7 * ABX500 core access functions.
8 * The abx500 interface is used for the Analog Baseband chip
9 * ab3100, ab3550, ab5500 and possibly comming. It is not used for
10 * ab4500 and ab8500 since they are another family of chip.
11 *
12 * Author: Mattias Wallin <mattias.wallin@stericsson.com>
13 * Author: Mattias Nilsson <mattias.i.nilsson@stericsson.com>
14 * Author: Bengt Jonsson <bengt.g.jonsson@stericsson.com>
15 * Author: Rickard Andersson <rickard.andersson@stericsson.com>
6 */ 16 */
7 17
8#include <linux/device.h> 18#include <linux/device.h>
9#include <linux/regulator/machine.h> 19#include <linux/regulator/machine.h>
10 20
11#ifndef MFD_AB3100_H 21#ifndef MFD_ABX500_H
12#define MFD_AB3100_H 22#define MFD_ABX500_H
13 23
14#define ABUNKNOWN 0 24#define AB3100_P1A 0xc0
15#define AB3000 1 25#define AB3100_P1B 0xc1
16#define AB3100 2 26#define AB3100_P1C 0xc2
27#define AB3100_P1D 0xc3
28#define AB3100_P1E 0xc4
29#define AB3100_P1F 0xc5
30#define AB3100_P1G 0xc6
31#define AB3100_R2A 0xc7
32#define AB3100_R2B 0xc8
33#define AB3550_P1A 0x10
34#define AB5500_1_0 0x20
35#define AB5500_2_0 0x21
36#define AB5500_2_1 0x22
17 37
18/* 38/*
19 * AB3100, EVENTA1, A2 and A3 event register flags 39 * AB3100, EVENTA1, A2 and A3 event register flags
@@ -89,7 +109,7 @@ struct ab3100 {
89 char chip_name[32]; 109 char chip_name[32];
90 u8 chip_id; 110 u8 chip_id;
91 struct blocking_notifier_head event_subscribers; 111 struct blocking_notifier_head event_subscribers;
92 u32 startup_events; 112 u8 startup_events[3];
93 bool startup_events_read; 113 bool startup_events_read;
94}; 114};
95 115
@@ -112,18 +132,102 @@ struct ab3100_platform_data {
112 int external_voltage; 132 int external_voltage;
113}; 133};
114 134
115int ab3100_set_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 regval);
116int ab3100_get_register_interruptible(struct ab3100 *ab3100, u8 reg, u8 *regval);
117int ab3100_get_register_page_interruptible(struct ab3100 *ab3100,
118 u8 first_reg, u8 *regvals, u8 numregs);
119int ab3100_mask_and_set_register_interruptible(struct ab3100 *ab3100,
120 u8 reg, u8 andmask, u8 ormask);
121u8 ab3100_get_chip_type(struct ab3100 *ab3100);
122int ab3100_event_register(struct ab3100 *ab3100, 135int ab3100_event_register(struct ab3100 *ab3100,
123 struct notifier_block *nb); 136 struct notifier_block *nb);
124int ab3100_event_unregister(struct ab3100 *ab3100, 137int ab3100_event_unregister(struct ab3100 *ab3100,
125 struct notifier_block *nb); 138 struct notifier_block *nb);
126int ab3100_event_registers_startup_state_get(struct ab3100 *ab3100,
127 u32 *fatevent);
128 139
140/* AB3550, STR register flags */
141#define AB3550_STR_ONSWA (0x01)
142#define AB3550_STR_ONSWB (0x02)
143#define AB3550_STR_ONSWC (0x04)
144#define AB3550_STR_DCIO (0x08)
145#define AB3550_STR_BOOT_MODE (0x10)
146#define AB3550_STR_SIM_OFF (0x20)
147#define AB3550_STR_BATT_REMOVAL (0x40)
148#define AB3550_STR_VBUS (0x80)
149
150/* Interrupt mask registers */
151#define AB3550_IMR1 0x29
152#define AB3550_IMR2 0x2a
153#define AB3550_IMR3 0x2b
154#define AB3550_IMR4 0x2c
155#define AB3550_IMR5 0x2d
156
157enum ab3550_devid {
158 AB3550_DEVID_ADC,
159 AB3550_DEVID_DAC,
160 AB3550_DEVID_LEDS,
161 AB3550_DEVID_POWER,
162 AB3550_DEVID_REGULATORS,
163 AB3550_DEVID_SIM,
164 AB3550_DEVID_UART,
165 AB3550_DEVID_RTC,
166 AB3550_DEVID_CHARGER,
167 AB3550_DEVID_FUELGAUGE,
168 AB3550_DEVID_VIBRATOR,
169 AB3550_DEVID_CODEC,
170 AB3550_NUM_DEVICES,
171};
172
173/**
174 * struct abx500_init_setting
175 * Initial value of the registers for driver to use during setup.
176 */
177struct abx500_init_settings {
178 u8 bank;
179 u8 reg;
180 u8 setting;
181};
182
183/**
184 * struct ab3550_platform_data
185 * Data supplied to initialize board connections to the AB3550
186 */
187struct ab3550_platform_data {
188 struct {unsigned int base; unsigned int count; } irq;
189 void *dev_data[AB3550_NUM_DEVICES];
190 size_t dev_data_sz[AB3550_NUM_DEVICES];
191 struct abx500_init_settings *init_settings;
192 unsigned int init_settings_sz;
193};
194
195int abx500_set_register_interruptible(struct device *dev, u8 bank, u8 reg,
196 u8 value);
197int abx500_get_register_interruptible(struct device *dev, u8 bank, u8 reg,
198 u8 *value);
199int abx500_get_register_page_interruptible(struct device *dev, u8 bank,
200 u8 first_reg, u8 *regvals, u8 numregs);
201int abx500_set_register_page_interruptible(struct device *dev, u8 bank,
202 u8 first_reg, u8 *regvals, u8 numregs);
203/**
204 * abx500_mask_and_set_register_inerruptible() - Modifies selected bits of a
205 * target register
206 *
207 * @dev: The AB sub device.
208 * @bank: The i2c bank number.
209 * @bitmask: The bit mask to use.
210 * @bitvalues: The new bit values.
211 *
212 * Updates the value of an AB register:
213 * value -> ((value & ~bitmask) | (bitvalues & bitmask))
214 */
215int abx500_mask_and_set_register_interruptible(struct device *dev, u8 bank,
216 u8 reg, u8 bitmask, u8 bitvalues);
217int abx500_get_chip_id(struct device *dev);
218int abx500_event_registers_startup_state_get(struct device *dev, u8 *event);
219int abx500_startup_irq_enabled(struct device *dev, unsigned int irq);
220
221struct abx500_ops {
222 int (*get_chip_id) (struct device *);
223 int (*get_register) (struct device *, u8, u8, u8 *);
224 int (*set_register) (struct device *, u8, u8, u8);
225 int (*get_register_page) (struct device *, u8, u8, u8 *, u8);
226 int (*set_register_page) (struct device *, u8, u8, u8 *, u8);
227 int (*mask_and_set_register) (struct device *, u8, u8, u8, u8);
228 int (*event_registers_startup_state_get) (struct device *, u8 *);
229 int (*startup_irq_enabled) (struct device *, unsigned int);
230};
231
232int abx500_register_ops(struct device *core_dev, struct abx500_ops *ops);
129#endif 233#endif
diff --git a/include/linux/mfd/janz.h b/include/linux/mfd/janz.h
new file mode 100644
index 000000000000..e9994c469803
--- /dev/null
+++ b/include/linux/mfd/janz.h
@@ -0,0 +1,54 @@
1/*
2 * Common Definitions for Janz MODULbus devices
3 *
4 * Copyright (c) 2010 Ira W. Snyder <iws@ovro.caltech.edu>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License as published by the
8 * Free Software Foundation; either version 2 of the License, or (at your
9 * option) any later version.
10 */
11
12#ifndef JANZ_H
13#define JANZ_H
14
15struct janz_platform_data {
16 /* MODULbus Module Number */
17 unsigned int modno;
18};
19
20/* PLX bridge chip onboard registers */
21struct janz_cmodio_onboard_regs {
22 u8 unused1;
23
24 /*
25 * Read access: interrupt status
26 * Write access: interrupt disable
27 */
28 u8 int_disable;
29 u8 unused2;
30
31 /*
32 * Read access: MODULbus number (hex switch)
33 * Write access: interrupt enable
34 */
35 u8 int_enable;
36 u8 unused3;
37
38 /* write-only */
39 u8 reset_assert;
40 u8 unused4;
41
42 /* write-only */
43 u8 reset_deassert;
44 u8 unused5;
45
46 /* read-write access to serial EEPROM */
47 u8 eep;
48 u8 unused6;
49
50 /* write-only access to EEPROM chip select */
51 u8 enid;
52};
53
54#endif /* JANZ_H */
diff --git a/include/linux/mfd/rdc321x.h b/include/linux/mfd/rdc321x.h
new file mode 100644
index 000000000000..4bdf19c8eedf
--- /dev/null
+++ b/include/linux/mfd/rdc321x.h
@@ -0,0 +1,26 @@
1#ifndef __RDC321X_MFD_H
2#define __RDC321X_MFD_H
3
4#include <linux/types.h>
5#include <linux/pci.h>
6
7/* Offsets to be accessed in the southbridge PCI
8 * device configuration register */
9#define RDC321X_WDT_CTRL 0x44
10#define RDC321X_GPIO_CTRL_REG1 0x48
11#define RDC321X_GPIO_DATA_REG1 0x4c
12#define RDC321X_GPIO_CTRL_REG2 0x84
13#define RDC321X_GPIO_DATA_REG2 0x88
14
15#define RDC321X_MAX_GPIO 58
16
17struct rdc321x_gpio_pdata {
18 struct pci_dev *sb_pdev;
19 unsigned max_gpios;
20};
21
22struct rdc321x_wdt_pdata {
23 struct pci_dev *sb_pdev;
24};
25
26#endif /* __RDC321X_MFD_H */
diff --git a/include/linux/mfd/tc35892.h b/include/linux/mfd/tc35892.h
new file mode 100644
index 000000000000..e47f770d3068
--- /dev/null
+++ b/include/linux/mfd/tc35892.h
@@ -0,0 +1,132 @@
1/*
2 * Copyright (C) ST-Ericsson SA 2010
3 *
4 * License Terms: GNU General Public License, version 2
5 */
6
7#ifndef __LINUX_MFD_TC35892_H
8#define __LINUX_MFD_TC35892_H
9
10#include <linux/device.h>
11
12#define TC35892_RSTCTRL_IRQRST (1 << 4)
13#define TC35892_RSTCTRL_TIMRST (1 << 3)
14#define TC35892_RSTCTRL_ROTRST (1 << 2)
15#define TC35892_RSTCTRL_KBDRST (1 << 1)
16#define TC35892_RSTCTRL_GPIRST (1 << 0)
17
18#define TC35892_IRQST 0x91
19
20#define TC35892_MANFCODE_MAGIC 0x03
21#define TC35892_MANFCODE 0x80
22#define TC35892_VERSION 0x81
23#define TC35892_IOCFG 0xA7
24
25#define TC35892_CLKMODE 0x88
26#define TC35892_CLKCFG 0x89
27#define TC35892_CLKEN 0x8A
28
29#define TC35892_RSTCTRL 0x82
30#define TC35892_EXTRSTN 0x83
31#define TC35892_RSTINTCLR 0x84
32
33#define TC35892_GPIOIS0 0xC9
34#define TC35892_GPIOIS1 0xCA
35#define TC35892_GPIOIS2 0xCB
36#define TC35892_GPIOIBE0 0xCC
37#define TC35892_GPIOIBE1 0xCD
38#define TC35892_GPIOIBE2 0xCE
39#define TC35892_GPIOIEV0 0xCF
40#define TC35892_GPIOIEV1 0xD0
41#define TC35892_GPIOIEV2 0xD1
42#define TC35892_GPIOIE0 0xD2
43#define TC35892_GPIOIE1 0xD3
44#define TC35892_GPIOIE2 0xD4
45#define TC35892_GPIORIS0 0xD6
46#define TC35892_GPIORIS1 0xD7
47#define TC35892_GPIORIS2 0xD8
48#define TC35892_GPIOMIS0 0xD9
49#define TC35892_GPIOMIS1 0xDA
50#define TC35892_GPIOMIS2 0xDB
51#define TC35892_GPIOIC0 0xDC
52#define TC35892_GPIOIC1 0xDD
53#define TC35892_GPIOIC2 0xDE
54
55#define TC35892_GPIODATA0 0xC0
56#define TC35892_GPIOMASK0 0xc1
57#define TC35892_GPIODATA1 0xC2
58#define TC35892_GPIOMASK1 0xc3
59#define TC35892_GPIODATA2 0xC4
60#define TC35892_GPIOMASK2 0xC5
61
62#define TC35892_GPIODIR0 0xC6
63#define TC35892_GPIODIR1 0xC7
64#define TC35892_GPIODIR2 0xC8
65
66#define TC35892_GPIOSYNC0 0xE6
67#define TC35892_GPIOSYNC1 0xE7
68#define TC35892_GPIOSYNC2 0xE8
69
70#define TC35892_GPIOWAKE0 0xE9
71#define TC35892_GPIOWAKE1 0xEA
72#define TC35892_GPIOWAKE2 0xEB
73
74#define TC35892_GPIOODM0 0xE0
75#define TC35892_GPIOODE0 0xE1
76#define TC35892_GPIOODM1 0xE2
77#define TC35892_GPIOODE1 0xE3
78#define TC35892_GPIOODM2 0xE4
79#define TC35892_GPIOODE2 0xE5
80
81#define TC35892_INT_GPIIRQ 0
82#define TC35892_INT_TI0IRQ 1
83#define TC35892_INT_TI1IRQ 2
84#define TC35892_INT_TI2IRQ 3
85#define TC35892_INT_ROTIRQ 5
86#define TC35892_INT_KBDIRQ 6
87#define TC35892_INT_PORIRQ 7
88
89#define TC35892_NR_INTERNAL_IRQS 8
90#define TC35892_INT_GPIO(x) (TC35892_NR_INTERNAL_IRQS + (x))
91
92struct tc35892 {
93 struct mutex lock;
94 struct device *dev;
95 struct i2c_client *i2c;
96
97 int irq_base;
98 int num_gpio;
99 struct tc35892_platform_data *pdata;
100};
101
102extern int tc35892_reg_write(struct tc35892 *tc35892, u8 reg, u8 data);
103extern int tc35892_reg_read(struct tc35892 *tc35892, u8 reg);
104extern int tc35892_block_read(struct tc35892 *tc35892, u8 reg, u8 length,
105 u8 *values);
106extern int tc35892_block_write(struct tc35892 *tc35892, u8 reg, u8 length,
107 const u8 *values);
108extern int tc35892_set_bits(struct tc35892 *tc35892, u8 reg, u8 mask, u8 val);
109
110/**
111 * struct tc35892_gpio_platform_data - TC35892 GPIO platform data
112 * @gpio_base: first gpio number assigned to TC35892. A maximum of
113 * %TC35892_NR_GPIOS GPIOs will be allocated.
114 */
115struct tc35892_gpio_platform_data {
116 int gpio_base;
117};
118
119/**
120 * struct tc35892_platform_data - TC35892 platform data
121 * @irq_base: base IRQ number. %TC35892_NR_IRQS irqs will be used.
122 * @gpio: GPIO-specific platform data
123 */
124struct tc35892_platform_data {
125 int irq_base;
126 struct tc35892_gpio_platform_data *gpio;
127};
128
129#define TC35892_NR_GPIOS 24
130#define TC35892_NR_IRQS TC35892_INT_GPIO(TC35892_NR_GPIOS)
131
132#endif
diff --git a/include/linux/mfd/tps6507x.h b/include/linux/mfd/tps6507x.h
new file mode 100644
index 000000000000..c923e4864f55
--- /dev/null
+++ b/include/linux/mfd/tps6507x.h
@@ -0,0 +1,169 @@
1/* linux/mfd/tps6507x.h
2 *
3 * Functions to access TPS65070 power management chip.
4 *
5 * Copyright (c) 2009 RidgeRun (todd.fischer@ridgerun.com)
6 *
7 *
8 * For licencing details see kernel-base/COPYING
9 */
10
11#ifndef __LINUX_MFD_TPS6507X_H
12#define __LINUX_MFD_TPS6507X_H
13
14/*
15 * ----------------------------------------------------------------------------
16 * Registers, all 8 bits
17 * ----------------------------------------------------------------------------
18 */
19
20
21/* Register definitions */
22#define TPS6507X_REG_PPATH1 0X01
23#define TPS6507X_CHG_USB BIT(7)
24#define TPS6507X_CHG_AC BIT(6)
25#define TPS6507X_CHG_USB_PW_ENABLE BIT(5)
26#define TPS6507X_CHG_AC_PW_ENABLE BIT(4)
27#define TPS6507X_CHG_AC_CURRENT BIT(2)
28#define TPS6507X_CHG_USB_CURRENT BIT(0)
29
30#define TPS6507X_REG_INT 0X02
31#define TPS6507X_REG_MASK_AC_USB BIT(7)
32#define TPS6507X_REG_MASK_TSC BIT(6)
33#define TPS6507X_REG_MASK_PB_IN BIT(5)
34#define TPS6507X_REG_TSC_INT BIT(3)
35#define TPS6507X_REG_PB_IN_INT BIT(2)
36#define TPS6507X_REG_AC_USB_APPLIED BIT(1)
37#define TPS6507X_REG_AC_USB_REMOVED BIT(0)
38
39#define TPS6507X_REG_CHGCONFIG0 0X03
40
41#define TPS6507X_REG_CHGCONFIG1 0X04
42#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
43#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
44#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
45#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
46#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
47
48#define TPS6507X_REG_CHGCONFIG2 0X05
49
50#define TPS6507X_REG_CHGCONFIG3 0X06
51
52#define TPS6507X_REG_ADCONFIG 0X07
53#define TPS6507X_ADCONFIG_AD_ENABLE BIT(7)
54#define TPS6507X_ADCONFIG_START_CONVERSION BIT(6)
55#define TPS6507X_ADCONFIG_CONVERSION_DONE BIT(5)
56#define TPS6507X_ADCONFIG_VREF_ENABLE BIT(4)
57#define TPS6507X_ADCONFIG_INPUT_AD_IN1 0
58#define TPS6507X_ADCONFIG_INPUT_AD_IN2 1
59#define TPS6507X_ADCONFIG_INPUT_AD_IN3 2
60#define TPS6507X_ADCONFIG_INPUT_AD_IN4 3
61#define TPS6507X_ADCONFIG_INPUT_TS_PIN 4
62#define TPS6507X_ADCONFIG_INPUT_BAT_CURRENT 5
63#define TPS6507X_ADCONFIG_INPUT_AC_VOLTAGE 6
64#define TPS6507X_ADCONFIG_INPUT_SYS_VOLTAGE 7
65#define TPS6507X_ADCONFIG_INPUT_CHARGER_VOLTAGE 8
66#define TPS6507X_ADCONFIG_INPUT_BAT_VOLTAGE 9
67#define TPS6507X_ADCONFIG_INPUT_THRESHOLD_VOLTAGE 10
68#define TPS6507X_ADCONFIG_INPUT_ISET1_VOLTAGE 11
69#define TPS6507X_ADCONFIG_INPUT_ISET2_VOLTAGE 12
70#define TPS6507X_ADCONFIG_INPUT_REAL_TSC 14
71#define TPS6507X_ADCONFIG_INPUT_TSC 15
72
73#define TPS6507X_REG_TSCMODE 0X08
74#define TPS6507X_TSCMODE_X_POSITION 0
75#define TPS6507X_TSCMODE_Y_POSITION 1
76#define TPS6507X_TSCMODE_PRESSURE 2
77#define TPS6507X_TSCMODE_X_PLATE 3
78#define TPS6507X_TSCMODE_Y_PLATE 4
79#define TPS6507X_TSCMODE_STANDBY 5
80#define TPS6507X_TSCMODE_ADC_INPUT 6
81#define TPS6507X_TSCMODE_DISABLE 7
82
83#define TPS6507X_REG_ADRESULT_1 0X09
84
85#define TPS6507X_REG_ADRESULT_2 0X0A
86#define TPS6507X_REG_ADRESULT_2_MASK (BIT(1) | BIT(0))
87
88#define TPS6507X_REG_PGOOD 0X0B
89
90#define TPS6507X_REG_PGOODMASK 0X0C
91
92#define TPS6507X_REG_CON_CTRL1 0X0D
93#define TPS6507X_CON_CTRL1_DCDC1_ENABLE BIT(4)
94#define TPS6507X_CON_CTRL1_DCDC2_ENABLE BIT(3)
95#define TPS6507X_CON_CTRL1_DCDC3_ENABLE BIT(2)
96#define TPS6507X_CON_CTRL1_LDO1_ENABLE BIT(1)
97#define TPS6507X_CON_CTRL1_LDO2_ENABLE BIT(0)
98
99#define TPS6507X_REG_CON_CTRL2 0X0E
100
101#define TPS6507X_REG_CON_CTRL3 0X0F
102
103#define TPS6507X_REG_DEFDCDC1 0X10
104#define TPS6507X_DEFDCDC1_DCDC1_EXT_ADJ_EN BIT(7)
105#define TPS6507X_DEFDCDC1_DCDC1_MASK 0X3F
106
107#define TPS6507X_REG_DEFDCDC2_LOW 0X11
108#define TPS6507X_DEFDCDC2_LOW_DCDC2_MASK 0X3F
109
110#define TPS6507X_REG_DEFDCDC2_HIGH 0X12
111#define TPS6507X_DEFDCDC2_HIGH_DCDC2_MASK 0X3F
112
113#define TPS6507X_REG_DEFDCDC3_LOW 0X13
114#define TPS6507X_DEFDCDC3_LOW_DCDC3_MASK 0X3F
115
116#define TPS6507X_REG_DEFDCDC3_HIGH 0X14
117#define TPS6507X_DEFDCDC3_HIGH_DCDC3_MASK 0X3F
118
119#define TPS6507X_REG_DEFSLEW 0X15
120
121#define TPS6507X_REG_LDO_CTRL1 0X16
122#define TPS6507X_REG_LDO_CTRL1_LDO1_MASK 0X0F
123
124#define TPS6507X_REG_DEFLDO2 0X17
125#define TPS6507X_REG_DEFLDO2_LDO2_MASK 0X3F
126
127#define TPS6507X_REG_WLED_CTRL1 0X18
128
129#define TPS6507X_REG_WLED_CTRL2 0X19
130
131/* VDCDC MASK */
132#define TPS6507X_DEFDCDCX_DCDC_MASK 0X3F
133
134#define TPS6507X_MAX_REGISTER 0X19
135
136/**
137 * struct tps6507x_board - packages regulator and touchscreen init data
138 * @tps6507x_regulator_data: regulator initialization values
139 *
140 * Board data may be used to initialize regulator and touchscreen.
141 */
142
143struct tps6507x_board {
144 struct regulator_init_data *tps6507x_pmic_init_data;
145 struct touchscreen_init_data *tps6507x_ts_init_data;
146};
147
148/**
149 * struct tps6507x_dev - tps6507x sub-driver chip access routines
150 * @read_dev() - I2C register read function
151 * @write_dev() - I2C register write function
152 *
153 * Device data may be used to access the TPS6507x chip
154 */
155
156struct tps6507x_dev {
157 struct device *dev;
158 struct i2c_client *i2c_client;
159 int (*read_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
160 void *dest);
161 int (*write_dev)(struct tps6507x_dev *tps6507x, char reg, int size,
162 void *src);
163
164 /* Client devices */
165 struct tps6507x_pmic *pmic;
166 struct tps6507x_ts *ts;
167};
168
169#endif /* __LINUX_MFD_TPS6507X_H */
diff --git a/include/linux/mfd/wm831x/core.h b/include/linux/mfd/wm831x/core.h
index 5915f6e3d9ab..eb5bd4e0e03c 100644
--- a/include/linux/mfd/wm831x/core.h
+++ b/include/linux/mfd/wm831x/core.h
@@ -256,8 +256,9 @@ struct wm831x {
256 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */ 256 int irq_masks_cache[WM831X_NUM_IRQ_REGS]; /* Cached hardware value */
257 257
258 /* Chip revision based flags */ 258 /* Chip revision based flags */
259 unsigned has_gpio_ena:1; /* Has GPIO enable bit */ 259 unsigned has_gpio_ena:1; /* Has GPIO enable bit */
260 unsigned has_cs_sts:1; /* Has current sink status bit */ 260 unsigned has_cs_sts:1; /* Has current sink status bit */
261 unsigned charger_irq_wake:1; /* Are charger IRQs a wake source? */
261 262
262 int num_gpio; 263 int num_gpio;
263 264
generated by cgit v1.2.2 (git 2.25.0) at 2024-11-26 02:56:59 -0500