diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-sh/irq.h | 32 | ||||
| -rw-r--r-- | include/asm-sh/titan.h | 32 |
2 files changed, 31 insertions, 33 deletions
diff --git a/include/asm-sh/irq.h b/include/asm-sh/irq.h index f10cfc10227e..fd576088e47e 100644 --- a/include/asm-sh/irq.h +++ b/include/asm-sh/irq.h | |||
| @@ -93,6 +93,12 @@ | |||
| 93 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) | 93 | #define NR_IRQS (ONCHIP_NR_IRQS + PINT_NR_IRQS + OFFCHIP_NR_IRQS) |
| 94 | 94 | ||
| 95 | /* | 95 | /* |
| 96 | * Convert back and forth between INTEVT and IRQ values. | ||
| 97 | */ | ||
| 98 | #define evt2irq(evt) (((evt) >> 5) - 16) | ||
| 99 | #define irq2evt(irq) (((irq) + 16) << 5) | ||
| 100 | |||
| 101 | /* | ||
| 96 | * Simple Mask Register Support | 102 | * Simple Mask Register Support |
| 97 | */ | 103 | */ |
| 98 | extern void make_maskreg_irq(unsigned int irq); | 104 | extern void make_maskreg_irq(unsigned int irq); |
| @@ -103,18 +109,36 @@ extern unsigned short *irq_mask_register; | |||
| 103 | */ | 109 | */ |
| 104 | void init_IRQ_pint(void); | 110 | void init_IRQ_pint(void); |
| 105 | 111 | ||
| 112 | /* | ||
| 113 | * The shift value is now the number of bits to shift, not the number of | ||
| 114 | * bits/4. This is to make it easier to read the value directly from the | ||
| 115 | * datasheets. The IPR address, addr, will be set from ipr_idx via the | ||
| 116 | * map_ipridx_to_addr function. | ||
| 117 | */ | ||
| 106 | struct ipr_data { | 118 | struct ipr_data { |
| 107 | unsigned int irq; | 119 | unsigned int irq; |
| 108 | unsigned int addr; /* Address of Interrupt Priority Register */ | 120 | int ipr_idx; /* Index for the IPR registered */ |
| 109 | int shift; /* Shifts of the 16-bit data */ | 121 | int shift; /* Number of bits to shift the data */ |
| 110 | int priority; /* The priority */ | 122 | int priority; /* The priority */ |
| 123 | unsigned int addr; /* Address of Interrupt Priority Register */ | ||
| 111 | }; | 124 | }; |
| 112 | 125 | ||
| 113 | /* | 126 | /* |
| 127 | * Given an IPR IDX, map the value to an IPR register address. | ||
| 128 | */ | ||
| 129 | unsigned int map_ipridx_to_addr(int idx); | ||
| 130 | |||
| 131 | /* | ||
| 132 | * Enable individual interrupt mode for external IPR IRQs. | ||
| 133 | */ | ||
| 134 | void ipr_irq_enable_irlm(void); | ||
| 135 | |||
| 136 | /* | ||
| 114 | * Function for "on chip support modules". | 137 | * Function for "on chip support modules". |
| 115 | */ | 138 | */ |
| 116 | extern void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); | 139 | void make_ipr_irq(struct ipr_data *table, unsigned int nr_irqs); |
| 117 | extern void make_imask_irq(unsigned int irq); | 140 | void make_imask_irq(unsigned int irq); |
| 141 | void init_IRQ_ipr(void); | ||
| 118 | 142 | ||
| 119 | struct intc2_data { | 143 | struct intc2_data { |
| 120 | unsigned short irq; | 144 | unsigned short irq; |
diff --git a/include/asm-sh/titan.h b/include/asm-sh/titan.h index 270a4f4bc8a9..03f3583c8918 100644 --- a/include/asm-sh/titan.h +++ b/include/asm-sh/titan.h | |||
| @@ -1,9 +1,8 @@ | |||
| 1 | /* | 1 | /* |
| 2 | * Platform defintions for Titan | 2 | * Platform defintions for Titan |
| 3 | */ | 3 | */ |
| 4 | 4 | #ifndef _ASM_SH_TITAN_H | |
| 5 | #ifndef _ASM_SH_TITAN_TITAN_H | 5 | #define _ASM_SH_TITAN_H |
| 6 | #define _ASM_SH_TITAN_TITAN_H | ||
| 7 | 6 | ||
| 8 | #define __IO_PREFIX titan | 7 | #define __IO_PREFIX titan |
| 9 | #include <asm/io_generic.h> | 8 | #include <asm/io_generic.h> |
| @@ -15,29 +14,4 @@ | |||
| 15 | #define TITAN_IRQ_MPCIB 11 /* mPCI B */ | 14 | #define TITAN_IRQ_MPCIB 11 /* mPCI B */ |
| 16 | #define TITAN_IRQ_USB 11 /* USB */ | 15 | #define TITAN_IRQ_USB 11 /* USB */ |
| 17 | 16 | ||
| 18 | /* | 17 | #endif /* __ASM_SH_TITAN_H */ |
| 19 | * The external interrupt lines, these take up ints 0 - 15 inclusive | ||
| 20 | * depending on the priority for the interrupt. In fact the priority | ||
| 21 | * is the interrupt :-) | ||
| 22 | */ | ||
| 23 | #define IRL0_IRQ 0 | ||
| 24 | #define IRL0_IPR_ADDR INTC_IPRD | ||
| 25 | #define IRL0_IPR_POS 3 | ||
| 26 | #define IRL0_PRIORITY 8 | ||
| 27 | |||
| 28 | #define IRL1_IRQ 1 | ||
| 29 | #define IRL1_IPR_ADDR INTC_IPRD | ||
| 30 | #define IRL1_IPR_POS 2 | ||
| 31 | #define IRL1_PRIORITY 8 | ||
| 32 | |||
| 33 | #define IRL2_IRQ 2 | ||
| 34 | #define IRL2_IPR_ADDR INTC_IPRD | ||
| 35 | #define IRL2_IPR_POS 1 | ||
| 36 | #define IRL2_PRIORITY 8 | ||
| 37 | |||
| 38 | #define IRL3_IRQ 3 | ||
| 39 | #define IRL3_IPR_ADDR INTC_IPRD | ||
| 40 | #define IRL3_IPR_POS 0 | ||
| 41 | #define IRL3_PRIORITY 8 | ||
| 42 | |||
| 43 | #endif | ||
