diff options
Diffstat (limited to 'include')
-rw-r--r-- | include/asm-blackfin/mach-bf527/anomaly.h | 5 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf533/anomaly.h | 31 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf537/anomaly.h | 10 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf548/anomaly.h | 2 | ||||
-rw-r--r-- | include/asm-blackfin/mach-bf561/anomaly.h | 2 |
5 files changed, 27 insertions, 23 deletions
diff --git a/include/asm-blackfin/mach-bf527/anomaly.h b/include/asm-blackfin/mach-bf527/anomaly.h index 735fa02fafb2..4725268a5ada 100644 --- a/include/asm-blackfin/mach-bf527/anomaly.h +++ b/include/asm-blackfin/mach-bf527/anomaly.h | |||
@@ -15,12 +15,16 @@ | |||
15 | 15 | ||
16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ | 16 | /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */ |
17 | #define ANOMALY_05000074 (1) | 17 | #define ANOMALY_05000074 (1) |
18 | /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */ | ||
19 | #define ANOMALY_05000119 (1) | ||
18 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ | 20 | /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */ |
19 | #define ANOMALY_05000122 (1) | 21 | #define ANOMALY_05000122 (1) |
20 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ | 22 | /* Spurious Hardware Error from an Access in the Shadow of a Conditional Branch */ |
21 | #define ANOMALY_05000245 (1) | 23 | #define ANOMALY_05000245 (1) |
22 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ | 24 | /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */ |
23 | #define ANOMALY_05000265 (1) | 25 | #define ANOMALY_05000265 (1) |
26 | /* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */ | ||
27 | #define ANOMALY_05000312 (1) | ||
24 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ | 28 | /* Incorrect Access of OTP_STATUS During otp_write() Function */ |
25 | #define ANOMALY_05000328 (1) | 29 | #define ANOMALY_05000328 (1) |
26 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ | 30 | /* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */ |
@@ -92,7 +96,6 @@ | |||
92 | #define ANOMALY_05000266 (0) | 96 | #define ANOMALY_05000266 (0) |
93 | #define ANOMALY_05000273 (0) | 97 | #define ANOMALY_05000273 (0) |
94 | #define ANOMALY_05000311 (0) | 98 | #define ANOMALY_05000311 (0) |
95 | #define ANOMALY_05000312 (0) | ||
96 | #define ANOMALY_05000323 (0) | 99 | #define ANOMALY_05000323 (0) |
97 | #define ANOMALY_05000363 (0) | 100 | #define ANOMALY_05000363 (0) |
98 | 101 | ||
diff --git a/include/asm-blackfin/mach-bf533/anomaly.h b/include/asm-blackfin/mach-bf533/anomaly.h index 5a6dcc5fa36c..8f7ea112fd3a 100644 --- a/include/asm-blackfin/mach-bf533/anomaly.h +++ b/include/asm-blackfin/mach-bf533/anomaly.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * File: include/asm-blackfin/mach-bf533/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf533/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
4 | * | 4 | * |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
@@ -176,6 +176,21 @@ | |||
176 | #define ANOMALY_05000315 (1) | 176 | #define ANOMALY_05000315 (1) |
177 | /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ | 177 | /* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */ |
178 | #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) | 178 | #define ANOMALY_05000319 (ANOMALY_BF531 || ANOMALY_BF532) |
179 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | ||
180 | #define ANOMALY_05000357 (1) | ||
181 | /* UART Break Signal Issues */ | ||
182 | #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) | ||
183 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | ||
184 | #define ANOMALY_05000366 (1) | ||
185 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | ||
186 | #define ANOMALY_05000371 (1) | ||
187 | /* PPI Does Not Start Properly In Specific Mode */ | ||
188 | #define ANOMALY_05000400 (__SILICON_REVISION__ >= 5) | ||
189 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | ||
190 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) | ||
191 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | ||
192 | #define ANOMALY_05000403 (1) | ||
193 | |||
179 | 194 | ||
180 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are | 195 | /* These anomalies have been "phased" out of analog.com anomaly sheets and are |
181 | * here to show running on older silicon just isn't feasible. | 196 | * here to show running on older silicon just isn't feasible. |
@@ -249,20 +264,6 @@ | |||
249 | #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) | 264 | #define ANOMALY_05000192 (__SILICON_REVISION__ < 3) |
250 | /* Internal Voltage Regulator may not start up */ | 265 | /* Internal Voltage Regulator may not start up */ |
251 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) | 266 | #define ANOMALY_05000206 (__SILICON_REVISION__ < 3) |
252 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | ||
253 | #define ANOMALY_05000357 (1) | ||
254 | /* UART Break Signal Issues */ | ||
255 | #define ANOMALY_05000363 (__SILICON_REVISION__ < 5) | ||
256 | /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */ | ||
257 | #define ANOMALY_05000366 (1) | ||
258 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | ||
259 | #define ANOMALY_05000371 (1) | ||
260 | /* PPI Does Not Start Properly In Specific Mode */ | ||
261 | #define ANOMALY_05000400 (__SILICON_REVISION__ == 5) | ||
262 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | ||
263 | #define ANOMALY_05000402 (__SILICON_REVISION__ == 5) | ||
264 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | ||
265 | #define ANOMALY_05000403 (1) | ||
266 | 267 | ||
267 | /* Anomalies that don't exist on this proc */ | 268 | /* Anomalies that don't exist on this proc */ |
268 | #define ANOMALY_05000266 (0) | 269 | #define ANOMALY_05000266 (0) |
diff --git a/include/asm-blackfin/mach-bf537/anomaly.h b/include/asm-blackfin/mach-bf537/anomaly.h index a6b08facb242..8460ab9c324f 100644 --- a/include/asm-blackfin/mach-bf537/anomaly.h +++ b/include/asm-blackfin/mach-bf537/anomaly.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * File: include/asm-blackfin/mach-bf537/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf537/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
4 | * | 4 | * |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||
@@ -132,8 +132,8 @@ | |||
132 | #define ANOMALY_05000322 (1) | 132 | #define ANOMALY_05000322 (1) |
133 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ | 133 | /* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */ |
134 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) | 134 | #define ANOMALY_05000341 (__SILICON_REVISION__ >= 3) |
135 | /* New Feature: UART Remains Enabled after UART Boot (Not Available on Older Silicon) */ | 135 | /* New Feature: UART Remains Enabled after UART Boot */ |
136 | #define ANOMALY_05000350 (__SILICON_REVISION__ < 3) | 136 | #define ANOMALY_05000350 (__SILICON_REVISION__ >= 3) |
137 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ | 137 | /* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */ |
138 | #define ANOMALY_05000355 (1) | 138 | #define ANOMALY_05000355 (1) |
139 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ | 139 | /* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */ |
@@ -145,12 +145,10 @@ | |||
145 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | 145 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ |
146 | #define ANOMALY_05000371 (1) | 146 | #define ANOMALY_05000371 (1) |
147 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ | 147 | /* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */ |
148 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 3) | 148 | #define ANOMALY_05000402 (__SILICON_REVISION__ >= 5) |
149 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ | 149 | /* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */ |
150 | #define ANOMALY_05000403 (1) | 150 | #define ANOMALY_05000403 (1) |
151 | 151 | ||
152 | |||
153 | |||
154 | /* Anomalies that don't exist on this proc */ | 152 | /* Anomalies that don't exist on this proc */ |
155 | #define ANOMALY_05000125 (0) | 153 | #define ANOMALY_05000125 (0) |
156 | #define ANOMALY_05000158 (0) | 154 | #define ANOMALY_05000158 (0) |
diff --git a/include/asm-blackfin/mach-bf548/anomaly.h b/include/asm-blackfin/mach-bf548/anomaly.h index 49d3cebc5293..3ad59655881a 100644 --- a/include/asm-blackfin/mach-bf548/anomaly.h +++ b/include/asm-blackfin/mach-bf548/anomaly.h | |||
@@ -75,6 +75,8 @@ | |||
75 | #define ANOMALY_05000365 (1) | 75 | #define ANOMALY_05000365 (1) |
76 | /* Addressing Conflict between Boot ROM and Asynchronous Memory */ | 76 | /* Addressing Conflict between Boot ROM and Asynchronous Memory */ |
77 | #define ANOMALY_05000369 (1) | 77 | #define ANOMALY_05000369 (1) |
78 | /* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */ | ||
79 | #define ANOMALY_05000371 (1) | ||
78 | /* Mobile DDR Operation Not Functional */ | 80 | /* Mobile DDR Operation Not Functional */ |
79 | #define ANOMALY_05000377 (1) | 81 | #define ANOMALY_05000377 (1) |
80 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ | 82 | /* Security/Authentication Speedpath Causes Authentication To Fail To Initiate */ |
diff --git a/include/asm-blackfin/mach-bf561/anomaly.h b/include/asm-blackfin/mach-bf561/anomaly.h index 82157caa96a2..5c5d7d7d695f 100644 --- a/include/asm-blackfin/mach-bf561/anomaly.h +++ b/include/asm-blackfin/mach-bf561/anomaly.h | |||
@@ -2,7 +2,7 @@ | |||
2 | * File: include/asm-blackfin/mach-bf561/anomaly.h | 2 | * File: include/asm-blackfin/mach-bf561/anomaly.h |
3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ | 3 | * Bugs: Enter bugs at http://blackfin.uclinux.org/ |
4 | * | 4 | * |
5 | * Copyright (C) 2004-2007 Analog Devices Inc. | 5 | * Copyright (C) 2004-2008 Analog Devices Inc. |
6 | * Licensed under the GPL-2 or later. | 6 | * Licensed under the GPL-2 or later. |
7 | */ | 7 | */ |
8 | 8 | ||