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-rw-r--r--include/asm-avr32/arch-at32ap/board.h9
-rw-r--r--include/asm-avr32/arch-at32ap/pm.h48
-rw-r--r--include/asm-avr32/arch-at32ap/time.h112
-rw-r--r--include/asm-avr32/asm.h8
-rw-r--r--include/asm-avr32/intc.h128
-rw-r--r--include/asm-avr32/irq.h5
-rw-r--r--include/asm-avr32/page.h8
-rw-r--r--include/asm-avr32/serial.h13
-rw-r--r--include/asm-avr32/xor.h6
-rw-r--r--include/linux/atmel_tc.h252
-rw-r--r--include/linux/usb/atmel_usba_udc.h22
11 files changed, 358 insertions, 253 deletions
diff --git a/include/asm-avr32/arch-at32ap/board.h b/include/asm-avr32/arch-at32ap/board.h
index 7597b0bd2f01..a4e2d28bfb58 100644
--- a/include/asm-avr32/arch-at32ap/board.h
+++ b/include/asm-avr32/arch-at32ap/board.h
@@ -38,9 +38,7 @@ struct platform_device *
38at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data, 38at32_add_device_lcdc(unsigned int id, struct atmel_lcdfb_info *data,
39 unsigned long fbmem_start, unsigned long fbmem_len); 39 unsigned long fbmem_start, unsigned long fbmem_len);
40 40
41struct usba_platform_data { 41struct usba_platform_data;
42 int vbus_pin;
43};
44struct platform_device * 42struct platform_device *
45at32_add_device_usba(unsigned int id, struct usba_platform_data *data); 43at32_add_device_usba(unsigned int id, struct usba_platform_data *data);
46 44
@@ -68,7 +66,10 @@ struct platform_device *at32_add_device_pwm(u32 mask);
68struct platform_device * 66struct platform_device *
69at32_add_device_ssc(unsigned int id, unsigned int flags); 67at32_add_device_ssc(unsigned int id, unsigned int flags);
70 68
71struct platform_device *at32_add_device_twi(unsigned int id); 69struct i2c_board_info;
70struct platform_device *at32_add_device_twi(unsigned int id,
71 struct i2c_board_info *b,
72 unsigned int n);
72struct platform_device *at32_add_device_mci(unsigned int id); 73struct platform_device *at32_add_device_mci(unsigned int id);
73struct platform_device *at32_add_device_ac97c(unsigned int id); 74struct platform_device *at32_add_device_ac97c(unsigned int id);
74struct platform_device *at32_add_device_abdac(unsigned int id); 75struct platform_device *at32_add_device_abdac(unsigned int id);
diff --git a/include/asm-avr32/arch-at32ap/pm.h b/include/asm-avr32/arch-at32ap/pm.h
new file mode 100644
index 000000000000..356e43064903
--- /dev/null
+++ b/include/asm-avr32/arch-at32ap/pm.h
@@ -0,0 +1,48 @@
1/*
2 * AVR32 AP Power Management.
3 *
4 * Copyright (C) 2008 Atmel Corporation
5 *
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
9 */
10#ifndef __ASM_AVR32_ARCH_PM_H
11#define __ASM_AVR32_ARCH_PM_H
12
13/* Possible arguments to the "sleep" instruction */
14#define CPU_SLEEP_IDLE 0
15#define CPU_SLEEP_FROZEN 1
16#define CPU_SLEEP_STANDBY 2
17#define CPU_SLEEP_STOP 3
18#define CPU_SLEEP_STATIC 5
19
20#ifndef __ASSEMBLY__
21extern void cpu_enter_idle(void);
22
23extern bool disable_idle_sleep;
24
25static inline void cpu_disable_idle_sleep(void)
26{
27 disable_idle_sleep = true;
28}
29
30static inline void cpu_enable_idle_sleep(void)
31{
32 disable_idle_sleep = false;
33}
34
35static inline void cpu_idle_sleep(void)
36{
37 /*
38 * If we're using the COUNT and COMPARE registers for
39 * timekeeping, we can't use the IDLE state.
40 */
41 if (disable_idle_sleep)
42 cpu_relax();
43 else
44 cpu_enter_idle();
45}
46#endif
47
48#endif /* __ASM_AVR32_ARCH_PM_H */
diff --git a/include/asm-avr32/arch-at32ap/time.h b/include/asm-avr32/arch-at32ap/time.h
deleted file mode 100644
index cc8a43418a4d..000000000000
--- a/include/asm-avr32/arch-at32ap/time.h
+++ /dev/null
@@ -1,112 +0,0 @@
1/*
2 * Copyright (C) 2007 Atmel Corporation
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License version 2 as
6 * published by the Free Software Foundation.
7 */
8
9#ifndef _ASM_AVR32_ARCH_AT32AP_TIME_H
10#define _ASM_AVR32_ARCH_AT32AP_TIME_H
11
12#include <linux/platform_device.h>
13
14extern struct irqaction timer_irqaction;
15extern struct platform_device at32_systc0_device;
16extern void local_timer_interrupt(int irq, void *dev_id);
17
18#define TIMER_BCR 0x000000c0
19#define TIMER_BCR_SYNC 0
20#define TIMER_BMR 0x000000c4
21#define TIMER_BMR_TC0XC0S 0
22#define TIMER_BMR_TC1XC1S 2
23#define TIMER_BMR_TC2XC2S 4
24#define TIMER_CCR 0x00000000
25#define TIMER_CCR_CLKDIS 1
26#define TIMER_CCR_CLKEN 0
27#define TIMER_CCR_SWTRG 2
28#define TIMER_CMR 0x00000004
29#define TIMER_CMR_ABETRG 10
30#define TIMER_CMR_ACPA 16
31#define TIMER_CMR_ACPC 18
32#define TIMER_CMR_AEEVT 20
33#define TIMER_CMR_ASWTRG 22
34#define TIMER_CMR_BCPB 24
35#define TIMER_CMR_BCPC 26
36#define TIMER_CMR_BEEVT 28
37#define TIMER_CMR_BSWTRG 30
38#define TIMER_CMR_BURST 4
39#define TIMER_CMR_CLKI 3
40#define TIMER_CMR_CPCDIS 7
41#define TIMER_CMR_CPCSTOP 6
42#define TIMER_CMR_CPCTRG 14
43#define TIMER_CMR_EEVT 10
44#define TIMER_CMR_EEVTEDG 8
45#define TIMER_CMR_ENETRG 12
46#define TIMER_CMR_ETRGEDG 8
47#define TIMER_CMR_LDBDIS 7
48#define TIMER_CMR_LDBSTOP 6
49#define TIMER_CMR_LDRA 16
50#define TIMER_CMR_LDRB 18
51#define TIMER_CMR_TCCLKS 0
52#define TIMER_CMR_WAVE 15
53#define TIMER_CMR_WAVSEL 13
54#define TIMER_CV 0x00000010
55#define TIMER_CV_CV 0
56#define TIMER_IDR 0x00000028
57#define TIMER_IDR_COVFS 0
58#define TIMER_IDR_CPAS 2
59#define TIMER_IDR_CPBS 3
60#define TIMER_IDR_CPCS 4
61#define TIMER_IDR_ETRGS 7
62#define TIMER_IDR_LDRAS 5
63#define TIMER_IDR_LDRBS 6
64#define TIMER_IDR_LOVRS 1
65#define TIMER_IER 0x00000024
66#define TIMER_IER_COVFS 0
67#define TIMER_IER_CPAS 2
68#define TIMER_IER_CPBS 3
69#define TIMER_IER_CPCS 4
70#define TIMER_IER_ETRGS 7
71#define TIMER_IER_LDRAS 5
72#define TIMER_IER_LDRBS 6
73#define TIMER_IER_LOVRS 1
74#define TIMER_IMR 0x0000002c
75#define TIMER_IMR_COVFS 0
76#define TIMER_IMR_CPAS 2
77#define TIMER_IMR_CPBS 3
78#define TIMER_IMR_CPCS 4
79#define TIMER_IMR_ETRGS 7
80#define TIMER_IMR_LDRAS 5
81#define TIMER_IMR_LDRBS 6
82#define TIMER_IMR_LOVRS 1
83#define TIMER_RA 0x00000014
84#define TIMER_RA_RA 0
85#define TIMER_RB 0x00000018
86#define TIMER_RB_RB 0
87#define TIMER_RC 0x0000001c
88#define TIMER_RC_RC 0
89#define TIMER_SR 0x00000020
90#define TIMER_SR_CLKSTA 16
91#define TIMER_SR_COVFS 0
92#define TIMER_SR_CPAS 2
93#define TIMER_SR_CPBS 3
94#define TIMER_SR_CPCS 4
95#define TIMER_SR_ETRGS 7
96#define TIMER_SR_LDRAS 5
97#define TIMER_SR_LDRBS 6
98#define TIMER_SR_LOVRS 1
99#define TIMER_SR_MTIOA 17
100#define TIMER_SR_MTIOB 18
101
102/* Bit manipulation macros */
103#define TIMER_BIT(name) (1 << TIMER_##name)
104#define TIMER_BF(name,value) ((value) << TIMER_##name)
105
106/* Register access macros */
107#define timer_read(port,instance,reg) \
108 __raw_readl(port + (0x40 * instance) + TIMER_##reg)
109#define timer_write(port,instance,reg,value) \
110 __raw_writel((value), port + (0x40 * instance) + TIMER_##reg)
111
112#endif /* _ASM_AVR32_ARCH_AT32AP_TIME_H */
diff --git a/include/asm-avr32/asm.h b/include/asm-avr32/asm.h
index 515c7618952b..a2c64f404b98 100644
--- a/include/asm-avr32/asm.h
+++ b/include/asm-avr32/asm.h
@@ -12,10 +12,10 @@
12#include <asm/asm-offsets.h> 12#include <asm/asm-offsets.h>
13#include <asm/thread_info.h> 13#include <asm/thread_info.h>
14 14
15#define mask_interrupts ssrf SR_GM_BIT 15#define mask_interrupts ssrf SYSREG_GM_OFFSET
16#define mask_exceptions ssrf SR_EM_BIT 16#define mask_exceptions ssrf SYSREG_EM_OFFSET
17#define unmask_interrupts csrf SR_GM_BIT 17#define unmask_interrupts csrf SYSREG_GM_OFFSET
18#define unmask_exceptions csrf SR_EM_BIT 18#define unmask_exceptions csrf SYSREG_EM_OFFSET
19 19
20#ifdef CONFIG_FRAME_POINTER 20#ifdef CONFIG_FRAME_POINTER
21 .macro save_fp 21 .macro save_fp
diff --git a/include/asm-avr32/intc.h b/include/asm-avr32/intc.h
deleted file mode 100644
index 1ac9ca75e8fd..000000000000
--- a/include/asm-avr32/intc.h
+++ /dev/null
@@ -1,128 +0,0 @@
1#ifndef __ASM_AVR32_INTC_H
2#define __ASM_AVR32_INTC_H
3
4#include <linux/sysdev.h>
5#include <linux/interrupt.h>
6
7struct irq_controller;
8struct irqaction;
9struct pt_regs;
10
11struct platform_device;
12
13/* Information about the internal interrupt controller */
14struct intc_device {
15 /* ioremapped address of configuration block */
16 void __iomem *regs;
17
18 /* the physical device */
19 struct platform_device *pdev;
20
21 /* Number of interrupt lines per group. */
22 unsigned int irqs_per_group;
23
24 /* The highest group ID + 1 */
25 unsigned int nr_groups;
26
27 /*
28 * Bitfield indicating which groups are actually in use. The
29 * size of the array is
30 * ceil(group_max / (8 * sizeof(unsigned int))).
31 */
32 unsigned int group_mask[];
33};
34
35struct irq_controller_class {
36 /*
37 * A short name identifying this kind of controller.
38 */
39 const char *typename;
40 /*
41 * Handle the IRQ. Must do any necessary acking and masking.
42 */
43 irqreturn_t (*handle)(int irq, void *dev_id, struct pt_regs *regs);
44 /*
45 * Register a new IRQ handler.
46 */
47 int (*setup)(struct irq_controller *ctrl, unsigned int irq,
48 struct irqaction *action);
49 /*
50 * Unregister a IRQ handler.
51 */
52 void (*free)(struct irq_controller *ctrl, unsigned int irq,
53 void *dev_id);
54 /*
55 * Mask the IRQ in the interrupt controller.
56 */
57 void (*mask)(struct irq_controller *ctrl, unsigned int irq);
58 /*
59 * Unmask the IRQ in the interrupt controller.
60 */
61 void (*unmask)(struct irq_controller *ctrl, unsigned int irq);
62 /*
63 * Set the type of the IRQ. See below for possible types.
64 * Return -EINVAL if a given type is not supported
65 */
66 int (*set_type)(struct irq_controller *ctrl, unsigned int irq,
67 unsigned int type);
68 /*
69 * Return the IRQ type currently set
70 */
71 unsigned int (*get_type)(struct irq_controller *ctrl, unsigned int irq);
72};
73
74struct irq_controller {
75 struct irq_controller_class *class;
76 unsigned int irq_group;
77 unsigned int first_irq;
78 unsigned int nr_irqs;
79 struct list_head list;
80};
81
82struct intc_group_desc {
83 struct irq_controller *ctrl;
84 irqreturn_t (*handle)(int, void *, struct pt_regs *);
85 unsigned long flags;
86 void *dev_id;
87 const char *devname;
88};
89
90/*
91 * The internal interrupt controller. Defined in board/part-specific
92 * devices.c.
93 * TODO: Should probably be defined per-cpu.
94 */
95extern struct intc_device intc;
96
97extern int request_internal_irq(unsigned int irq,
98 irqreturn_t (*handler)(int, void *, struct pt_regs *),
99 unsigned long irqflags,
100 const char *devname, void *dev_id);
101extern void free_internal_irq(unsigned int irq);
102
103/* Only used by time_init() */
104extern int setup_internal_irq(unsigned int irq, struct intc_group_desc *desc);
105
106/*
107 * Set interrupt priority for a given group. `group' can be found by
108 * using irq_to_group(irq). Priority can be from 0 (lowest) to 3
109 * (highest). Higher-priority interrupts will preempt lower-priority
110 * interrupts (unless interrupts are masked globally).
111 *
112 * This function does not check for conflicts within a group.
113 */
114extern int intc_set_priority(unsigned int group,
115 unsigned int priority);
116
117/*
118 * Returns a bitmask of pending interrupts in a group.
119 */
120extern unsigned long intc_get_pending(unsigned int group);
121
122/*
123 * Register a new external interrupt controller. Returns the first
124 * external IRQ number that is assigned to the new controller.
125 */
126extern int intc_register_controller(struct irq_controller *ctrl);
127
128#endif /* __ASM_AVR32_INTC_H */
diff --git a/include/asm-avr32/irq.h b/include/asm-avr32/irq.h
index 9315724c0596..c563b7720c1a 100644
--- a/include/asm-avr32/irq.h
+++ b/include/asm-avr32/irq.h
@@ -14,6 +14,11 @@
14#ifndef __ASSEMBLER__ 14#ifndef __ASSEMBLER__
15int nmi_enable(void); 15int nmi_enable(void);
16void nmi_disable(void); 16void nmi_disable(void);
17
18/*
19 * Returns a bitmask of pending interrupts in a group.
20 */
21extern unsigned long intc_get_pending(unsigned int group);
17#endif 22#endif
18 23
19#endif /* __ASM_AVR32_IOCTLS_H */ 24#endif /* __ASM_AVR32_IOCTLS_H */
diff --git a/include/asm-avr32/page.h b/include/asm-avr32/page.h
index 5582968feee8..cbbc5ca9728b 100644
--- a/include/asm-avr32/page.h
+++ b/include/asm-avr32/page.h
@@ -8,13 +8,11 @@
8#ifndef __ASM_AVR32_PAGE_H 8#ifndef __ASM_AVR32_PAGE_H
9#define __ASM_AVR32_PAGE_H 9#define __ASM_AVR32_PAGE_H
10 10
11#include <linux/const.h>
12
11/* PAGE_SHIFT determines the page size */ 13/* PAGE_SHIFT determines the page size */
12#define PAGE_SHIFT 12 14#define PAGE_SHIFT 12
13#ifdef __ASSEMBLY__ 15#define PAGE_SIZE (_AC(1, UL) << PAGE_SHIFT)
14#define PAGE_SIZE (1 << PAGE_SHIFT)
15#else
16#define PAGE_SIZE (1UL << PAGE_SHIFT)
17#endif
18#define PAGE_MASK (~(PAGE_SIZE-1)) 16#define PAGE_MASK (~(PAGE_SIZE-1))
19#define PTE_MASK PAGE_MASK 17#define PTE_MASK PAGE_MASK
20 18
diff --git a/include/asm-avr32/serial.h b/include/asm-avr32/serial.h
new file mode 100644
index 000000000000..5ecaebc22b02
--- /dev/null
+++ b/include/asm-avr32/serial.h
@@ -0,0 +1,13 @@
1#ifndef _ASM_SERIAL_H
2#define _ASM_SERIAL_H
3
4/*
5 * This assumes you have a 1.8432 MHz clock for your UART.
6 *
7 * It'd be nice if someone built a serial card with a 24.576 MHz
8 * clock, since the 16550A is capable of handling a top speed of 1.5
9 * megabits/second; but this requires the faster clock.
10 */
11#define BASE_BAUD (1843200 / 16)
12
13#endif /* _ASM_SERIAL_H */
diff --git a/include/asm-avr32/xor.h b/include/asm-avr32/xor.h
new file mode 100644
index 000000000000..99c87aa0af4f
--- /dev/null
+++ b/include/asm-avr32/xor.h
@@ -0,0 +1,6 @@
1#ifndef _ASM_XOR_H
2#define _ASM_XOR_H
3
4#include <asm-generic/xor.h>
5
6#endif
diff --git a/include/linux/atmel_tc.h b/include/linux/atmel_tc.h
new file mode 100644
index 000000000000..53ba65e30caa
--- /dev/null
+++ b/include/linux/atmel_tc.h
@@ -0,0 +1,252 @@
1/*
2 * Timer/Counter Unit (TC) registers.
3 *
4 * This program is free software; you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation; either version 2 of the License, or
7 * (at your option) any later version.
8 */
9
10#ifndef ATMEL_TC_H
11#define ATMEL_TC_H
12
13#include <linux/compiler.h>
14#include <linux/list.h>
15
16/*
17 * Many 32-bit Atmel SOCs include one or more TC blocks, each of which holds
18 * three general-purpose 16-bit timers. These timers share one register bank.
19 * Depending on the SOC, each timer may have its own clock and IRQ, or those
20 * may be shared by the whole TC block.
21 *
22 * These TC blocks may have up to nine external pins: TCLK0..2 signals for
23 * clocks or clock gates, and per-timer TIOA and TIOB signals used for PWM
24 * or triggering. Those pins need to be set up for use with the TC block,
25 * else they will be used as GPIOs or for a different controller.
26 *
27 * Although we expect each TC block to have a platform_device node, those
28 * nodes are not what drivers bind to. Instead, they ask for a specific
29 * TC block, by number ... which is a common approach on systems with many
30 * timers. Then they use clk_get() and platform_get_irq() to get clock and
31 * IRQ resources.
32 */
33
34struct clk;
35
36/**
37 * struct atmel_tc - information about a Timer/Counter Block
38 * @pdev: physical device
39 * @iomem: resource associated with the I/O register
40 * @regs: mapping through which the I/O registers can be accessed
41 * @irq: irq for each of the three channels
42 * @clk: internal clock source for each of the three channels
43 * @node: list node, for tclib internal use
44 *
45 * On some platforms, each TC channel has its own clocks and IRQs,
46 * while on others, all TC channels share the same clock and IRQ.
47 * Drivers should clk_enable() all the clocks they need even though
48 * all the entries in @clk may point to the same physical clock.
49 * Likewise, drivers should request irqs independently for each
50 * channel, but they must use IRQF_SHARED in case some of the entries
51 * in @irq are actually the same IRQ.
52 */
53struct atmel_tc {
54 struct platform_device *pdev;
55 struct resource *iomem;
56 void __iomem *regs;
57 int irq[3];
58 struct clk *clk[3];
59 struct list_head node;
60};
61
62extern struct atmel_tc *atmel_tc_alloc(unsigned block, const char *name);
63extern void atmel_tc_free(struct atmel_tc *tc);
64
65/* platform-specific ATMEL_TC_TIMER_CLOCKx divisors (0 means 32KiHz) */
66extern const u8 atmel_tc_divisors[5];
67
68
69/*
70 * Two registers have block-wide controls. These are: configuring the three
71 * "external" clocks (or event sources) used by the timer channels; and
72 * synchronizing the timers by resetting them all at once.
73 *
74 * "External" can mean "external to chip" using the TCLK0, TCLK1, or TCLK2
75 * signals. Or, it can mean "external to timer", using the TIOA output from
76 * one of the other two timers that's being run in waveform mode.
77 */
78
79#define ATMEL_TC_BCR 0xc0 /* TC Block Control Register */
80#define ATMEL_TC_SYNC (1 << 0) /* synchronize timers */
81
82#define ATMEL_TC_BMR 0xc4 /* TC Block Mode Register */
83#define ATMEL_TC_TC0XC0S (3 << 0) /* external clock 0 source */
84#define ATMEL_TC_TC0XC0S_TCLK0 (0 << 0)
85#define ATMEL_TC_TC0XC0S_NONE (1 << 0)
86#define ATMEL_TC_TC0XC0S_TIOA1 (2 << 0)
87#define ATMEL_TC_TC0XC0S_TIOA2 (3 << 0)
88#define ATMEL_TC_TC1XC1S (3 << 2) /* external clock 1 source */
89#define ATMEL_TC_TC1XC1S_TCLK1 (0 << 2)
90#define ATMEL_TC_TC1XC1S_NONE (1 << 2)
91#define ATMEL_TC_TC1XC1S_TIOA0 (2 << 2)
92#define ATMEL_TC_TC1XC1S_TIOA2 (3 << 2)
93#define ATMEL_TC_TC2XC2S (3 << 4) /* external clock 2 source */
94#define ATMEL_TC_TC2XC2S_TCLK2 (0 << 4)
95#define ATMEL_TC_TC2XC2S_NONE (1 << 4)
96#define ATMEL_TC_TC2XC2S_TIOA0 (2 << 4)
97#define ATMEL_TC_TC2XC2S_TIOA1 (3 << 4)
98
99
100/*
101 * Each TC block has three "channels", each with one counter and controls.
102 *
103 * Note that the semantics of ATMEL_TC_TIMER_CLOCKx (input clock selection
104 * when it's not "external") is silicon-specific. AT91 platforms use one
105 * set of definitions; AVR32 platforms use a different set. Don't hard-wire
106 * such knowledge into your code, use the global "atmel_tc_divisors" ...
107 * where index N is the divisor for clock N+1, else zero to indicate it uses
108 * the 32 KiHz clock.
109 *
110 * The timers can be chained in various ways, and operated in "waveform"
111 * generation mode (including PWM) or "capture" mode (to time events). In
112 * both modes, behavior can be configured in many ways.
113 *
114 * Each timer has two I/O pins, TIOA and TIOB. Waveform mode uses TIOA as a
115 * PWM output, and TIOB as either another PWM or as a trigger. Capture mode
116 * uses them only as inputs.
117 */
118#define ATMEL_TC_CHAN(idx) ((idx)*0x40)
119#define ATMEL_TC_REG(idx, reg) (ATMEL_TC_CHAN(idx) + ATMEL_TC_ ## reg)
120
121#define ATMEL_TC_CCR 0x00 /* Channel Control Register */
122#define ATMEL_TC_CLKEN (1 << 0) /* clock enable */
123#define ATMEL_TC_CLKDIS (1 << 1) /* clock disable */
124#define ATMEL_TC_SWTRG (1 << 2) /* software trigger */
125
126#define ATMEL_TC_CMR 0x04 /* Channel Mode Register */
127
128/* Both modes share some CMR bits */
129#define ATMEL_TC_TCCLKS (7 << 0) /* clock source */
130#define ATMEL_TC_TIMER_CLOCK1 (0 << 0)
131#define ATMEL_TC_TIMER_CLOCK2 (1 << 0)
132#define ATMEL_TC_TIMER_CLOCK3 (2 << 0)
133#define ATMEL_TC_TIMER_CLOCK4 (3 << 0)
134#define ATMEL_TC_TIMER_CLOCK5 (4 << 0)
135#define ATMEL_TC_XC0 (5 << 0)
136#define ATMEL_TC_XC1 (6 << 0)
137#define ATMEL_TC_XC2 (7 << 0)
138#define ATMEL_TC_CLKI (1 << 3) /* clock invert */
139#define ATMEL_TC_BURST (3 << 4) /* clock gating */
140#define ATMEL_TC_GATE_NONE (0 << 4)
141#define ATMEL_TC_GATE_XC0 (1 << 4)
142#define ATMEL_TC_GATE_XC1 (2 << 4)
143#define ATMEL_TC_GATE_XC2 (3 << 4)
144#define ATMEL_TC_WAVE (1 << 15) /* true = Waveform mode */
145
146/* CAPTURE mode CMR bits */
147#define ATMEL_TC_LDBSTOP (1 << 6) /* counter stops on RB load */
148#define ATMEL_TC_LDBDIS (1 << 7) /* counter disable on RB load */
149#define ATMEL_TC_ETRGEDG (3 << 8) /* external trigger edge */
150#define ATMEL_TC_ETRGEDG_NONE (0 << 8)
151#define ATMEL_TC_ETRGEDG_RISING (1 << 8)
152#define ATMEL_TC_ETRGEDG_FALLING (2 << 8)
153#define ATMEL_TC_ETRGEDG_BOTH (3 << 8)
154#define ATMEL_TC_ABETRG (1 << 10) /* external trigger is TIOA? */
155#define ATMEL_TC_CPCTRG (1 << 14) /* RC compare trigger enable */
156#define ATMEL_TC_LDRA (3 << 16) /* RA loading edge (of TIOA) */
157#define ATMEL_TC_LDRA_NONE (0 << 16)
158#define ATMEL_TC_LDRA_RISING (1 << 16)
159#define ATMEL_TC_LDRA_FALLING (2 << 16)
160#define ATMEL_TC_LDRA_BOTH (3 << 16)
161#define ATMEL_TC_LDRB (3 << 18) /* RB loading edge (of TIOA) */
162#define ATMEL_TC_LDRB_NONE (0 << 18)
163#define ATMEL_TC_LDRB_RISING (1 << 18)
164#define ATMEL_TC_LDRB_FALLING (2 << 18)
165#define ATMEL_TC_LDRB_BOTH (3 << 18)
166
167/* WAVEFORM mode CMR bits */
168#define ATMEL_TC_CPCSTOP (1 << 6) /* RC compare stops counter */
169#define ATMEL_TC_CPCDIS (1 << 7) /* RC compare disables counter */
170#define ATMEL_TC_EEVTEDG (3 << 8) /* external event edge */
171#define ATMEL_TC_EEVTEDG_NONE (0 << 8)
172#define ATMEL_TC_EEVTEDG_RISING (1 << 8)
173#define ATMEL_TC_EEVTEDG_FALLING (2 << 8)
174#define ATMEL_TC_EEVTEDG_BOTH (3 << 8)
175#define ATMEL_TC_EEVT (3 << 10) /* external event source */
176#define ATMEL_TC_EEVT_TIOB (0 << 10)
177#define ATMEL_TC_EEVT_XC0 (1 << 10)
178#define ATMEL_TC_EEVT_XC1 (2 << 10)
179#define ATMEL_TC_EEVT_XC2 (3 << 10)
180#define ATMEL_TC_ENETRG (1 << 12) /* external event is trigger */
181#define ATMEL_TC_WAVESEL (3 << 13) /* waveform type */
182#define ATMEL_TC_WAVESEL_UP (0 << 13)
183#define ATMEL_TC_WAVESEL_UPDOWN (1 << 13)
184#define ATMEL_TC_WAVESEL_UP_AUTO (2 << 13)
185#define ATMEL_TC_WAVESEL_UPDOWN_AUTO (3 << 13)
186#define ATMEL_TC_ACPA (3 << 16) /* RA compare changes TIOA */
187#define ATMEL_TC_ACPA_NONE (0 << 16)
188#define ATMEL_TC_ACPA_SET (1 << 16)
189#define ATMEL_TC_ACPA_CLEAR (2 << 16)
190#define ATMEL_TC_ACPA_TOGGLE (3 << 16)
191#define ATMEL_TC_ACPC (3 << 18) /* RC compare changes TIOA */
192#define ATMEL_TC_ACPC_NONE (0 << 18)
193#define ATMEL_TC_ACPC_SET (1 << 18)
194#define ATMEL_TC_ACPC_CLEAR (2 << 18)
195#define ATMEL_TC_ACPC_TOGGLE (3 << 18)
196#define ATMEL_TC_AEEVT (3 << 20) /* external event changes TIOA */
197#define ATMEL_TC_AEEVT_NONE (0 << 20)
198#define ATMEL_TC_AEEVT_SET (1 << 20)
199#define ATMEL_TC_AEEVT_CLEAR (2 << 20)
200#define ATMEL_TC_AEEVT_TOGGLE (3 << 20)
201#define ATMEL_TC_ASWTRG (3 << 22) /* software trigger changes TIOA */
202#define ATMEL_TC_ASWTRG_NONE (0 << 22)
203#define ATMEL_TC_ASWTRG_SET (1 << 22)
204#define ATMEL_TC_ASWTRG_CLEAR (2 << 22)
205#define ATMEL_TC_ASWTRG_TOGGLE (3 << 22)
206#define ATMEL_TC_BCPB (3 << 24) /* RB compare changes TIOB */
207#define ATMEL_TC_BCPB_NONE (0 << 24)
208#define ATMEL_TC_BCPB_SET (1 << 24)
209#define ATMEL_TC_BCPB_CLEAR (2 << 24)
210#define ATMEL_TC_BCPB_TOGGLE (3 << 24)
211#define ATMEL_TC_BCPC (3 << 26) /* RC compare changes TIOB */
212#define ATMEL_TC_BCPC_NONE (0 << 26)
213#define ATMEL_TC_BCPC_SET (1 << 26)
214#define ATMEL_TC_BCPC_CLEAR (2 << 26)
215#define ATMEL_TC_BCPC_TOGGLE (3 << 26)
216#define ATMEL_TC_BEEVT (3 << 28) /* external event changes TIOB */
217#define ATMEL_TC_BEEVT_NONE (0 << 28)
218#define ATMEL_TC_BEEVT_SET (1 << 28)
219#define ATMEL_TC_BEEVT_CLEAR (2 << 28)
220#define ATMEL_TC_BEEVT_TOGGLE (3 << 28)
221#define ATMEL_TC_BSWTRG (3 << 30) /* software trigger changes TIOB */
222#define ATMEL_TC_BSWTRG_NONE (0 << 30)
223#define ATMEL_TC_BSWTRG_SET (1 << 30)
224#define ATMEL_TC_BSWTRG_CLEAR (2 << 30)
225#define ATMEL_TC_BSWTRG_TOGGLE (3 << 30)
226
227#define ATMEL_TC_CV 0x10 /* counter Value */
228#define ATMEL_TC_RA 0x14 /* register A */
229#define ATMEL_TC_RB 0x18 /* register B */
230#define ATMEL_TC_RC 0x1c /* register C */
231
232#define ATMEL_TC_SR 0x20 /* status (read-only) */
233/* Status-only flags */
234#define ATMEL_TC_CLKSTA (1 << 16) /* clock enabled */
235#define ATMEL_TC_MTIOA (1 << 17) /* TIOA mirror */
236#define ATMEL_TC_MTIOB (1 << 18) /* TIOB mirror */
237
238#define ATMEL_TC_IER 0x24 /* interrupt enable (write-only) */
239#define ATMEL_TC_IDR 0x28 /* interrupt disable (write-only) */
240#define ATMEL_TC_IMR 0x2c /* interrupt mask (read-only) */
241
242/* Status and IRQ flags */
243#define ATMEL_TC_COVFS (1 << 0) /* counter overflow */
244#define ATMEL_TC_LOVRS (1 << 1) /* load overrun */
245#define ATMEL_TC_CPAS (1 << 2) /* RA compare */
246#define ATMEL_TC_CPBS (1 << 3) /* RB compare */
247#define ATMEL_TC_CPCS (1 << 4) /* RC compare */
248#define ATMEL_TC_LDRAS (1 << 5) /* RA loading */
249#define ATMEL_TC_LDRBS (1 << 6) /* RB loading */
250#define ATMEL_TC_ETRGS (1 << 7) /* external trigger */
251
252#endif
diff --git a/include/linux/usb/atmel_usba_udc.h b/include/linux/usb/atmel_usba_udc.h
new file mode 100644
index 000000000000..6311fa2d9f82
--- /dev/null
+++ b/include/linux/usb/atmel_usba_udc.h
@@ -0,0 +1,22 @@
1/*
2 * Platform data definitions for Atmel USBA gadget driver.
3 */
4#ifndef __LINUX_USB_USBA_H
5#define __LINUX_USB_USBA_H
6
7struct usba_ep_data {
8 char *name;
9 int index;
10 int fifo_size;
11 int nr_banks;
12 int can_dma;
13 int can_isoc;
14};
15
16struct usba_platform_data {
17 int vbus_pin;
18 int num_ep;
19 struct usba_ep_data ep[0];
20};
21
22#endif /* __LINUX_USB_USBA_H */
generated by cgit v1.2.2 (git 2.25.0) at 2025-01-07 18:52:19 -0500