diff options
Diffstat (limited to 'include')
| -rw-r--r-- | include/asm-arm/arch-s3c2410/regs-mem.h | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/include/asm-arm/arch-s3c2410/regs-mem.h b/include/asm-arm/arch-s3c2410/regs-mem.h index e4d82341f7ba..312ff93b63c6 100644 --- a/include/asm-arm/arch-s3c2410/regs-mem.h +++ b/include/asm-arm/arch-s3c2410/regs-mem.h | |||
| @@ -98,16 +98,19 @@ | |||
| 98 | #define S3C2410_BANKCON_Tacp3 (0x1 << 2) | 98 | #define S3C2410_BANKCON_Tacp3 (0x1 << 2) |
| 99 | #define S3C2410_BANKCON_Tacp4 (0x2 << 2) | 99 | #define S3C2410_BANKCON_Tacp4 (0x2 << 2) |
| 100 | #define S3C2410_BANKCON_Tacp6 (0x3 << 2) | 100 | #define S3C2410_BANKCON_Tacp6 (0x3 << 2) |
| 101 | #define S3C2410_BANKCON_Tacp_SHIFT (2) | ||
| 101 | 102 | ||
| 102 | #define S3C2410_BANKCON_Tcah0 (0x0 << 4) | 103 | #define S3C2410_BANKCON_Tcah0 (0x0 << 4) |
| 103 | #define S3C2410_BANKCON_Tcah1 (0x1 << 4) | 104 | #define S3C2410_BANKCON_Tcah1 (0x1 << 4) |
| 104 | #define S3C2410_BANKCON_Tcah2 (0x2 << 4) | 105 | #define S3C2410_BANKCON_Tcah2 (0x2 << 4) |
| 105 | #define S3C2410_BANKCON_Tcah4 (0x3 << 4) | 106 | #define S3C2410_BANKCON_Tcah4 (0x3 << 4) |
| 107 | #define S3C2410_BANKCON_Tcah_SHIFT (4) | ||
| 106 | 108 | ||
| 107 | #define S3C2410_BANKCON_Tcoh0 (0x0 << 6) | 109 | #define S3C2410_BANKCON_Tcoh0 (0x0 << 6) |
| 108 | #define S3C2410_BANKCON_Tcoh1 (0x1 << 6) | 110 | #define S3C2410_BANKCON_Tcoh1 (0x1 << 6) |
| 109 | #define S3C2410_BANKCON_Tcoh2 (0x2 << 6) | 111 | #define S3C2410_BANKCON_Tcoh2 (0x2 << 6) |
| 110 | #define S3C2410_BANKCON_Tcoh4 (0x3 << 6) | 112 | #define S3C2410_BANKCON_Tcoh4 (0x3 << 6) |
| 113 | #define S3C2410_BANKCON_Tcoh_SHIFT (6) | ||
| 111 | 114 | ||
| 112 | #define S3C2410_BANKCON_Tacc1 (0x0 << 8) | 115 | #define S3C2410_BANKCON_Tacc1 (0x0 << 8) |
| 113 | #define S3C2410_BANKCON_Tacc2 (0x1 << 8) | 116 | #define S3C2410_BANKCON_Tacc2 (0x1 << 8) |
| @@ -117,16 +120,19 @@ | |||
| 117 | #define S3C2410_BANKCON_Tacc8 (0x5 << 8) | 120 | #define S3C2410_BANKCON_Tacc8 (0x5 << 8) |
| 118 | #define S3C2410_BANKCON_Tacc10 (0x6 << 8) | 121 | #define S3C2410_BANKCON_Tacc10 (0x6 << 8) |
| 119 | #define S3C2410_BANKCON_Tacc14 (0x7 << 8) | 122 | #define S3C2410_BANKCON_Tacc14 (0x7 << 8) |
| 123 | #define S3C2410_BANKCON_Tacc_SHIFT (8) | ||
| 120 | 124 | ||
| 121 | #define S3C2410_BANKCON_Tcos0 (0x0 << 11) | 125 | #define S3C2410_BANKCON_Tcos0 (0x0 << 11) |
| 122 | #define S3C2410_BANKCON_Tcos1 (0x1 << 11) | 126 | #define S3C2410_BANKCON_Tcos1 (0x1 << 11) |
| 123 | #define S3C2410_BANKCON_Tcos2 (0x2 << 11) | 127 | #define S3C2410_BANKCON_Tcos2 (0x2 << 11) |
| 124 | #define S3C2410_BANKCON_Tcos4 (0x3 << 11) | 128 | #define S3C2410_BANKCON_Tcos4 (0x3 << 11) |
| 129 | #define S3C2410_BANKCON_Tcos_SHIFT (11) | ||
| 125 | 130 | ||
| 126 | #define S3C2410_BANKCON_Tacs0 (0x0 << 13) | 131 | #define S3C2410_BANKCON_Tacs0 (0x0 << 13) |
| 127 | #define S3C2410_BANKCON_Tacs1 (0x1 << 13) | 132 | #define S3C2410_BANKCON_Tacs1 (0x1 << 13) |
| 128 | #define S3C2410_BANKCON_Tacs2 (0x2 << 13) | 133 | #define S3C2410_BANKCON_Tacs2 (0x2 << 13) |
| 129 | #define S3C2410_BANKCON_Tacs4 (0x3 << 13) | 134 | #define S3C2410_BANKCON_Tacs4 (0x3 << 13) |
| 135 | #define S3C2410_BANKCON_Tacs_SHIFT (13) | ||
| 130 | 136 | ||
| 131 | #define S3C2410_BANKCON_SRAM (0x0 << 15) | 137 | #define S3C2410_BANKCON_SRAM (0x0 << 15) |
| 132 | #define S3C2400_BANKCON_EDODRAM (0x2 << 15) | 138 | #define S3C2400_BANKCON_EDODRAM (0x2 << 15) |
